1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "double-int.h"
34 #include "fold-const.h"
36 #include "stor-layout.h"
39 #include "hard-reg-set.h"
43 #include "insn-config.h"
44 #include "conditions.h"
46 #include "insn-attr.h"
48 #include "diagnostic-core.h"
53 #include "target-def.h"
56 #include "dominance.h"
62 #include "cfgcleanup.h"
64 #include "basic-block.h"
66 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
67 #include "sched-int.h"
68 #include "insn-codes.h"
75 enum reg_class regno_reg_class
[] =
77 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
78 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
79 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
80 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
81 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
82 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
87 /* The minimum number of integer registers that we want to save with the
88 movem instruction. Using two movel instructions instead of a single
89 moveml is about 15% faster for the 68020 and 68030 at no expense in
91 #define MIN_MOVEM_REGS 3
93 /* The minimum number of floating point registers that we want to save
94 with the fmovem instruction. */
95 #define MIN_FMOVEM_REGS 1
97 /* Structure describing stack frame layout. */
100 /* Stack pointer to frame pointer offset. */
101 HOST_WIDE_INT offset
;
103 /* Offset of FPU registers. */
104 HOST_WIDE_INT foffset
;
106 /* Frame size in bytes (rounded up). */
109 /* Data and address register. */
111 unsigned int reg_mask
;
115 unsigned int fpu_mask
;
117 /* Offsets relative to ARG_POINTER. */
118 HOST_WIDE_INT frame_pointer_offset
;
119 HOST_WIDE_INT stack_pointer_offset
;
121 /* Function which the above information refers to. */
125 /* Current frame information calculated by m68k_compute_frame_layout(). */
126 static struct m68k_frame current_frame
;
128 /* Structure describing an m68k address.
130 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
131 with null fields evaluating to 0. Here:
133 - BASE satisfies m68k_legitimate_base_reg_p
134 - INDEX satisfies m68k_legitimate_index_reg_p
135 - OFFSET satisfies m68k_legitimate_constant_address_p
137 INDEX is either HImode or SImode. The other fields are SImode.
139 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
140 the address is (BASE)+. */
141 struct m68k_address
{
149 static int m68k_sched_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
150 static int m68k_sched_issue_rate (void);
151 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
152 static void m68k_sched_md_init_global (FILE *, int, int);
153 static void m68k_sched_md_finish_global (FILE *, int);
154 static void m68k_sched_md_init (FILE *, int, int);
155 static void m68k_sched_dfa_pre_advance_cycle (void);
156 static void m68k_sched_dfa_post_advance_cycle (void);
157 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
159 static bool m68k_can_eliminate (const int, const int);
160 static void m68k_conditional_register_usage (void);
161 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
162 static void m68k_option_override (void);
163 static void m68k_override_options_after_change (void);
164 static rtx
find_addr_reg (rtx
);
165 static const char *singlemove_string (rtx
*);
166 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
167 HOST_WIDE_INT
, tree
);
168 static rtx
m68k_struct_value_rtx (tree
, int);
169 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
170 tree args
, int flags
,
172 static void m68k_compute_frame_layout (void);
173 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
174 static bool m68k_ok_for_sibcall_p (tree
, tree
);
175 static bool m68k_tls_symbol_p (rtx
);
176 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
177 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
178 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
179 static bool m68k_return_in_memory (const_tree
, const_tree
);
181 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
182 static void m68k_trampoline_init (rtx
, tree
, rtx
);
183 static int m68k_return_pops_args (tree
, tree
, int);
184 static rtx
m68k_delegitimize_address (rtx
);
185 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
187 static rtx
m68k_function_arg (cumulative_args_t
, machine_mode
,
189 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
190 static bool m68k_output_addr_const_extra (FILE *, rtx
);
191 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
193 /* Initialize the GCC target structure. */
195 #if INT_OP_GROUP == INT_OP_DOT_WORD
196 #undef TARGET_ASM_ALIGNED_HI_OP
197 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
200 #if INT_OP_GROUP == INT_OP_NO_DOT
201 #undef TARGET_ASM_BYTE_OP
202 #define TARGET_ASM_BYTE_OP "\tbyte\t"
203 #undef TARGET_ASM_ALIGNED_HI_OP
204 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
205 #undef TARGET_ASM_ALIGNED_SI_OP
206 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
209 #if INT_OP_GROUP == INT_OP_DC
210 #undef TARGET_ASM_BYTE_OP
211 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
212 #undef TARGET_ASM_ALIGNED_HI_OP
213 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
214 #undef TARGET_ASM_ALIGNED_SI_OP
215 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
218 #undef TARGET_ASM_UNALIGNED_HI_OP
219 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
220 #undef TARGET_ASM_UNALIGNED_SI_OP
221 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
223 #undef TARGET_ASM_OUTPUT_MI_THUNK
224 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
225 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
226 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
228 #undef TARGET_ASM_FILE_START_APP_OFF
229 #define TARGET_ASM_FILE_START_APP_OFF true
231 #undef TARGET_LEGITIMIZE_ADDRESS
232 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
234 #undef TARGET_SCHED_ADJUST_COST
235 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
237 #undef TARGET_SCHED_ISSUE_RATE
238 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
240 #undef TARGET_SCHED_VARIABLE_ISSUE
241 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
243 #undef TARGET_SCHED_INIT_GLOBAL
244 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
246 #undef TARGET_SCHED_FINISH_GLOBAL
247 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
249 #undef TARGET_SCHED_INIT
250 #define TARGET_SCHED_INIT m68k_sched_md_init
252 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
253 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
255 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
256 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
258 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
259 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
260 m68k_sched_first_cycle_multipass_dfa_lookahead
262 #undef TARGET_OPTION_OVERRIDE
263 #define TARGET_OPTION_OVERRIDE m68k_option_override
265 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
266 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
268 #undef TARGET_RTX_COSTS
269 #define TARGET_RTX_COSTS m68k_rtx_costs
271 #undef TARGET_ATTRIBUTE_TABLE
272 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
274 #undef TARGET_PROMOTE_PROTOTYPES
275 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
277 #undef TARGET_STRUCT_VALUE_RTX
278 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
280 #undef TARGET_CANNOT_FORCE_CONST_MEM
281 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
283 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
284 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
286 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
287 #undef TARGET_RETURN_IN_MEMORY
288 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
292 #undef TARGET_HAVE_TLS
293 #define TARGET_HAVE_TLS (true)
295 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
296 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
299 #undef TARGET_LEGITIMATE_ADDRESS_P
300 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
302 #undef TARGET_CAN_ELIMINATE
303 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
305 #undef TARGET_CONDITIONAL_REGISTER_USAGE
306 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
308 #undef TARGET_TRAMPOLINE_INIT
309 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
311 #undef TARGET_RETURN_POPS_ARGS
312 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
314 #undef TARGET_DELEGITIMIZE_ADDRESS
315 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
317 #undef TARGET_FUNCTION_ARG
318 #define TARGET_FUNCTION_ARG m68k_function_arg
320 #undef TARGET_FUNCTION_ARG_ADVANCE
321 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
323 #undef TARGET_LEGITIMATE_CONSTANT_P
324 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
326 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
327 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
329 /* The value stored by TAS. */
330 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
331 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
333 static const struct attribute_spec m68k_attribute_table
[] =
335 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
336 affects_type_identity } */
337 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
339 { "interrupt_handler", 0, 0, true, false, false,
340 m68k_handle_fndecl_attribute
, false },
341 { "interrupt_thread", 0, 0, true, false, false,
342 m68k_handle_fndecl_attribute
, false },
343 { NULL
, 0, 0, false, false, false, NULL
, false }
346 struct gcc_target targetm
= TARGET_INITIALIZER
;
348 /* Base flags for 68k ISAs. */
349 #define FL_FOR_isa_00 FL_ISA_68000
350 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
351 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
352 generated 68881 code for 68020 and 68030 targets unless explicitly told
354 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
355 | FL_BITFIELD | FL_68881 | FL_CAS)
356 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
357 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
359 /* Base flags for ColdFire ISAs. */
360 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
361 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
362 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
363 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
364 /* ISA_C is not upwardly compatible with ISA_B. */
365 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
369 /* Traditional 68000 instruction sets. */
375 /* ColdFire instruction set variants. */
383 /* Information about one of the -march, -mcpu or -mtune arguments. */
384 struct m68k_target_selection
386 /* The argument being described. */
389 /* For -mcpu, this is the device selected by the option.
390 For -mtune and -march, it is a representative device
391 for the microarchitecture or ISA respectively. */
392 enum target_device device
;
394 /* The M68K_DEVICE fields associated with DEVICE. See the comment
395 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
397 enum uarch_type microarch
;
402 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
403 static const struct m68k_target_selection all_devices
[] =
405 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
406 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
407 #include "m68k-devices.def"
409 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
412 /* A list of all ISAs, mapping each one to a representative device.
413 Used for -march selection. */
414 static const struct m68k_target_selection all_isas
[] =
416 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
417 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
418 #include "m68k-isas.def"
420 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
423 /* A list of all microarchitectures, mapping each one to a representative
424 device. Used for -mtune selection. */
425 static const struct m68k_target_selection all_microarchs
[] =
427 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
428 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
429 #include "m68k-microarchs.def"
430 #undef M68K_MICROARCH
431 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
434 /* The entries associated with the -mcpu, -march and -mtune settings,
435 or null for options that have not been used. */
436 const struct m68k_target_selection
*m68k_cpu_entry
;
437 const struct m68k_target_selection
*m68k_arch_entry
;
438 const struct m68k_target_selection
*m68k_tune_entry
;
440 /* Which CPU we are generating code for. */
441 enum target_device m68k_cpu
;
443 /* Which microarchitecture to tune for. */
444 enum uarch_type m68k_tune
;
446 /* Which FPU to use. */
447 enum fpu_type m68k_fpu
;
449 /* The set of FL_* flags that apply to the target processor. */
450 unsigned int m68k_cpu_flags
;
452 /* The set of FL_* flags that apply to the processor to be tuned for. */
453 unsigned int m68k_tune_flags
;
455 /* Asm templates for calling or jumping to an arbitrary symbolic address,
456 or NULL if such calls or jumps are not supported. The address is held
458 const char *m68k_symbolic_call
;
459 const char *m68k_symbolic_jump
;
461 /* Enum variable that corresponds to m68k_symbolic_call values. */
462 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
465 /* Implement TARGET_OPTION_OVERRIDE. */
468 m68k_option_override (void)
470 const struct m68k_target_selection
*entry
;
471 unsigned long target_mask
;
473 if (global_options_set
.x_m68k_arch_option
)
474 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
476 if (global_options_set
.x_m68k_cpu_option
)
477 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
479 if (global_options_set
.x_m68k_tune_option
)
480 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
488 -march=ARCH should generate code that runs any processor
489 implementing architecture ARCH. -mcpu=CPU should override -march
490 and should generate code that runs on processor CPU, making free
491 use of any instructions that CPU understands. -mtune=UARCH applies
492 on top of -mcpu or -march and optimizes the code for UARCH. It does
493 not change the target architecture. */
496 /* Complain if the -march setting is for a different microarchitecture,
497 or includes flags that the -mcpu setting doesn't. */
499 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
500 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
501 warning (0, "-mcpu=%s conflicts with -march=%s",
502 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
504 entry
= m68k_cpu_entry
;
507 entry
= m68k_arch_entry
;
510 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
512 m68k_cpu_flags
= entry
->flags
;
514 /* Use the architecture setting to derive default values for
518 /* ColdFire is lenient about alignment. */
519 if (!TARGET_COLDFIRE
)
520 target_mask
|= MASK_STRICT_ALIGNMENT
;
522 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
523 target_mask
|= MASK_BITFIELD
;
524 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
525 target_mask
|= MASK_CF_HWDIV
;
526 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
527 target_mask
|= MASK_HARD_FLOAT
;
528 target_flags
|= target_mask
& ~target_flags_explicit
;
530 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
531 m68k_cpu
= entry
->device
;
534 m68k_tune
= m68k_tune_entry
->microarch
;
535 m68k_tune_flags
= m68k_tune_entry
->flags
;
537 #ifdef M68K_DEFAULT_TUNE
538 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
540 enum target_device dev
;
541 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
542 m68k_tune_flags
= all_devices
[dev
].flags
;
547 m68k_tune
= entry
->microarch
;
548 m68k_tune_flags
= entry
->flags
;
551 /* Set the type of FPU. */
552 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
553 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
556 /* Sanity check to ensure that msep-data and mid-sahred-library are not
557 * both specified together. Doing so simply doesn't make sense.
559 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
560 error ("cannot specify both -msep-data and -mid-shared-library");
562 /* If we're generating code for a separate A5 relative data segment,
563 * we've got to enable -fPIC as well. This might be relaxable to
564 * -fpic but it hasn't been tested properly.
566 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
569 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
570 error if the target does not support them. */
571 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
572 error ("-mpcrel -fPIC is not currently supported on selected cpu");
574 /* ??? A historic way of turning on pic, or is this intended to
575 be an embedded thing that doesn't have the same name binding
576 significance that it does on hosted ELF systems? */
577 if (TARGET_PCREL
&& flag_pic
== 0)
582 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
584 m68k_symbolic_jump
= "jra %a0";
586 else if (TARGET_ID_SHARED_LIBRARY
)
587 /* All addresses must be loaded from the GOT. */
589 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
592 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
594 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
597 /* No unconditional long branch */;
598 else if (TARGET_PCREL
)
599 m68k_symbolic_jump
= "bra%.l %c0";
601 m68k_symbolic_jump
= "bra%.l %p0";
602 /* Turn off function cse if we are doing PIC. We always want
603 function call to be done as `bsr foo@PLTPC'. */
604 /* ??? It's traditional to do this for -mpcrel too, but it isn't
605 clear how intentional that is. */
606 flag_no_function_cse
= 1;
609 switch (m68k_symbolic_call_var
)
611 case M68K_SYMBOLIC_CALL_JSR
:
612 m68k_symbolic_call
= "jsr %a0";
615 case M68K_SYMBOLIC_CALL_BSR_C
:
616 m68k_symbolic_call
= "bsr%.l %c0";
619 case M68K_SYMBOLIC_CALL_BSR_P
:
620 m68k_symbolic_call
= "bsr%.l %p0";
623 case M68K_SYMBOLIC_CALL_NONE
:
624 gcc_assert (m68k_symbolic_call
== NULL
);
631 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
632 if (align_labels
> 2)
634 warning (0, "-falign-labels=%d is not supported", align_labels
);
639 warning (0, "-falign-loops=%d is not supported", align_loops
);
644 if (stack_limit_rtx
!= NULL_RTX
&& !TARGET_68020
)
646 warning (0, "-fstack-limit- options are not supported on this cpu");
647 stack_limit_rtx
= NULL_RTX
;
650 SUBTARGET_OVERRIDE_OPTIONS
;
652 /* Setup scheduling options. */
654 m68k_sched_cpu
= CPU_CFV1
;
656 m68k_sched_cpu
= CPU_CFV2
;
658 m68k_sched_cpu
= CPU_CFV3
;
660 m68k_sched_cpu
= CPU_CFV4
;
663 m68k_sched_cpu
= CPU_UNKNOWN
;
664 flag_schedule_insns
= 0;
665 flag_schedule_insns_after_reload
= 0;
666 flag_modulo_sched
= 0;
667 flag_live_range_shrinkage
= 0;
670 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
672 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
673 m68k_sched_mac
= MAC_CF_EMAC
;
674 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
675 m68k_sched_mac
= MAC_CF_MAC
;
677 m68k_sched_mac
= MAC_NO
;
681 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
684 m68k_override_options_after_change (void)
686 if (m68k_sched_cpu
== CPU_UNKNOWN
)
688 flag_schedule_insns
= 0;
689 flag_schedule_insns_after_reload
= 0;
690 flag_modulo_sched
= 0;
691 flag_live_range_shrinkage
= 0;
695 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
696 given argument and NAME is the argument passed to -mcpu. Return NULL
697 if -mcpu was not passed. */
700 m68k_cpp_cpu_ident (const char *prefix
)
704 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
707 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
708 given argument and NAME is the name of the representative device for
709 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
712 m68k_cpp_cpu_family (const char *prefix
)
716 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
719 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
720 "interrupt_handler" attribute and interrupt_thread if FUNC has an
721 "interrupt_thread" attribute. Otherwise, return
722 m68k_fk_normal_function. */
724 enum m68k_function_kind
725 m68k_get_function_kind (tree func
)
729 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
731 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
733 return m68k_fk_interrupt_handler
;
735 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
737 return m68k_fk_interrupt_handler
;
739 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
741 return m68k_fk_interrupt_thread
;
743 return m68k_fk_normal_function
;
746 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
747 struct attribute_spec.handler. */
749 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
750 tree args ATTRIBUTE_UNUSED
,
751 int flags ATTRIBUTE_UNUSED
,
754 if (TREE_CODE (*node
) != FUNCTION_DECL
)
756 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
758 *no_add_attrs
= true;
761 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
763 error ("multiple interrupt attributes not allowed");
764 *no_add_attrs
= true;
768 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
770 error ("interrupt_thread is available only on fido");
771 *no_add_attrs
= true;
778 m68k_compute_frame_layout (void)
782 enum m68k_function_kind func_kind
=
783 m68k_get_function_kind (current_function_decl
);
784 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
785 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
787 /* Only compute the frame once per function.
788 Don't cache information until reload has been completed. */
789 if (current_frame
.funcdef_no
== current_function_funcdef_no
793 current_frame
.size
= (get_frame_size () + 3) & -4;
797 /* Interrupt thread does not need to save any register. */
798 if (!interrupt_thread
)
799 for (regno
= 0; regno
< 16; regno
++)
800 if (m68k_save_reg (regno
, interrupt_handler
))
802 mask
|= 1 << (regno
- D0_REG
);
805 current_frame
.offset
= saved
* 4;
806 current_frame
.reg_no
= saved
;
807 current_frame
.reg_mask
= mask
;
809 current_frame
.foffset
= 0;
811 if (TARGET_HARD_FLOAT
)
813 /* Interrupt thread does not need to save any register. */
814 if (!interrupt_thread
)
815 for (regno
= 16; regno
< 24; regno
++)
816 if (m68k_save_reg (regno
, interrupt_handler
))
818 mask
|= 1 << (regno
- FP0_REG
);
821 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
822 current_frame
.offset
+= current_frame
.foffset
;
824 current_frame
.fpu_no
= saved
;
825 current_frame
.fpu_mask
= mask
;
827 /* Remember what function this frame refers to. */
828 current_frame
.funcdef_no
= current_function_funcdef_no
;
831 /* Worker function for TARGET_CAN_ELIMINATE. */
834 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
836 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
840 m68k_initial_elimination_offset (int from
, int to
)
843 /* The arg pointer points 8 bytes before the start of the arguments,
844 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
845 frame pointer in most frames. */
846 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
847 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
848 return argptr_offset
;
850 m68k_compute_frame_layout ();
852 gcc_assert (to
== STACK_POINTER_REGNUM
);
855 case ARG_POINTER_REGNUM
:
856 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
857 case FRAME_POINTER_REGNUM
:
858 return current_frame
.offset
+ current_frame
.size
;
864 /* Refer to the array `regs_ever_live' to determine which registers
865 to save; `regs_ever_live[I]' is nonzero if register number I
866 is ever used in the function. This function is responsible for
867 knowing which registers should not be saved even if used.
868 Return true if we need to save REGNO. */
871 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
873 if (flag_pic
&& regno
== PIC_REG
)
875 if (crtl
->saves_all_registers
)
877 if (crtl
->uses_pic_offset_table
)
879 /* Reload may introduce constant pool references into a function
880 that thitherto didn't need a PIC register. Note that the test
881 above will not catch that case because we will only set
882 crtl->uses_pic_offset_table when emitting
883 the address reloads. */
884 if (crtl
->uses_const_pool
)
888 if (crtl
->calls_eh_return
)
893 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
894 if (test
== INVALID_REGNUM
)
901 /* Fixed regs we never touch. */
902 if (fixed_regs
[regno
])
905 /* The frame pointer (if it is such) is handled specially. */
906 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
909 /* Interrupt handlers must also save call_used_regs
910 if they are live or when calling nested functions. */
911 if (interrupt_handler
)
913 if (df_regs_ever_live_p (regno
))
916 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
920 /* Never need to save registers that aren't touched. */
921 if (!df_regs_ever_live_p (regno
))
924 /* Otherwise save everything that isn't call-clobbered. */
925 return !call_used_regs
[regno
];
928 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
929 the lowest memory address. COUNT is the number of registers to be
930 moved, with register REGNO + I being moved if bit I of MASK is set.
931 STORE_P specifies the direction of the move and ADJUST_STACK_P says
932 whether or not this is pre-decrement (if STORE_P) or post-increment
933 (if !STORE_P) operation. */
936 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
937 unsigned int count
, unsigned int regno
,
938 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
941 rtx body
, addr
, src
, operands
[2];
944 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
945 mode
= reg_raw_mode
[regno
];
950 src
= plus_constant (Pmode
, base
,
952 * GET_MODE_SIZE (mode
)
953 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
954 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
957 for (; mask
!= 0; mask
>>= 1, regno
++)
960 addr
= plus_constant (Pmode
, base
, offset
);
961 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
962 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
963 XVECEXP (body
, 0, i
++)
964 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
965 offset
+= GET_MODE_SIZE (mode
);
967 gcc_assert (i
== XVECLEN (body
, 0));
969 return emit_insn (body
);
972 /* Make INSN a frame-related instruction. */
975 m68k_set_frame_related (rtx_insn
*insn
)
980 RTX_FRAME_RELATED_P (insn
) = 1;
981 body
= PATTERN (insn
);
982 if (GET_CODE (body
) == PARALLEL
)
983 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
984 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
987 /* Emit RTL for the "prologue" define_expand. */
990 m68k_expand_prologue (void)
992 HOST_WIDE_INT fsize_with_regs
;
993 rtx limit
, src
, dest
;
995 m68k_compute_frame_layout ();
997 if (flag_stack_usage_info
)
998 current_function_static_stack_size
999 = current_frame
.size
+ current_frame
.offset
;
1001 /* If the stack limit is a symbol, we can check it here,
1002 before actually allocating the space. */
1003 if (crtl
->limit_stack
1004 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1006 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1007 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1009 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1010 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1012 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1013 stack_pointer_rtx
, limit
),
1014 stack_pointer_rtx
, limit
,
1018 fsize_with_regs
= current_frame
.size
;
1019 if (TARGET_COLDFIRE
)
1021 /* ColdFire's move multiple instructions do not allow pre-decrement
1022 addressing. Add the size of movem saves to the initial stack
1023 allocation instead. */
1024 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1025 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1026 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1027 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1030 if (frame_pointer_needed
)
1032 if (fsize_with_regs
== 0 && TUNE_68040
)
1034 /* On the 68040, two separate moves are faster than link.w 0. */
1035 dest
= gen_frame_mem (Pmode
,
1036 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1037 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1038 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1039 stack_pointer_rtx
));
1041 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1042 m68k_set_frame_related
1043 (emit_insn (gen_link (frame_pointer_rtx
,
1044 GEN_INT (-4 - fsize_with_regs
))));
1047 m68k_set_frame_related
1048 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1049 m68k_set_frame_related
1050 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1052 GEN_INT (-fsize_with_regs
))));
1055 /* If the frame pointer is needed, emit a special barrier that
1056 will prevent the scheduler from moving stores to the frame
1057 before the stack adjustment. */
1058 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1060 else if (fsize_with_regs
!= 0)
1061 m68k_set_frame_related
1062 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1064 GEN_INT (-fsize_with_regs
))));
1066 if (current_frame
.fpu_mask
)
1068 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1070 m68k_set_frame_related
1071 (m68k_emit_movem (stack_pointer_rtx
,
1072 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1073 current_frame
.fpu_no
, FP0_REG
,
1074 current_frame
.fpu_mask
, true, true));
1079 /* If we're using moveml to save the integer registers,
1080 the stack pointer will point to the bottom of the moveml
1081 save area. Find the stack offset of the first FP register. */
1082 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1085 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1086 m68k_set_frame_related
1087 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1088 current_frame
.fpu_no
, FP0_REG
,
1089 current_frame
.fpu_mask
, true, false));
1093 /* If the stack limit is not a symbol, check it here.
1094 This has the disadvantage that it may be too late... */
1095 if (crtl
->limit_stack
)
1097 if (REG_P (stack_limit_rtx
))
1098 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1100 stack_pointer_rtx
, stack_limit_rtx
,
1103 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1104 warning (0, "stack limit expression is not supported");
1107 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1109 /* Store each register separately in the same order moveml does. */
1112 for (i
= 16; i
-- > 0; )
1113 if (current_frame
.reg_mask
& (1 << i
))
1115 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1116 dest
= gen_frame_mem (SImode
,
1117 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1118 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1123 if (TARGET_COLDFIRE
)
1124 /* The required register save space has already been allocated.
1125 The first register should be stored at (%sp). */
1126 m68k_set_frame_related
1127 (m68k_emit_movem (stack_pointer_rtx
, 0,
1128 current_frame
.reg_no
, D0_REG
,
1129 current_frame
.reg_mask
, true, false));
1131 m68k_set_frame_related
1132 (m68k_emit_movem (stack_pointer_rtx
,
1133 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1134 current_frame
.reg_no
, D0_REG
,
1135 current_frame
.reg_mask
, true, true));
1138 if (!TARGET_SEP_DATA
1139 && crtl
->uses_pic_offset_table
)
1140 emit_insn (gen_load_got (pic_offset_table_rtx
));
1143 /* Return true if a simple (return) instruction is sufficient for this
1144 instruction (i.e. if no epilogue is needed). */
1147 m68k_use_return_insn (void)
1149 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1152 m68k_compute_frame_layout ();
1153 return current_frame
.offset
== 0;
1156 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1157 SIBCALL_P says which.
1159 The function epilogue should not depend on the current stack pointer!
1160 It should use the frame pointer only, if there is a frame pointer.
1161 This is mandatory because of alloca; we also take advantage of it to
1162 omit stack adjustments before returning. */
1165 m68k_expand_epilogue (bool sibcall_p
)
1167 HOST_WIDE_INT fsize
, fsize_with_regs
;
1168 bool big
, restore_from_sp
;
1170 m68k_compute_frame_layout ();
1172 fsize
= current_frame
.size
;
1174 restore_from_sp
= false;
1176 /* FIXME : crtl->is_leaf below is too strong.
1177 What we really need to know there is if there could be pending
1178 stack adjustment needed at that point. */
1179 restore_from_sp
= (!frame_pointer_needed
1180 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1182 /* fsize_with_regs is the size we need to adjust the sp when
1183 popping the frame. */
1184 fsize_with_regs
= fsize
;
1185 if (TARGET_COLDFIRE
&& restore_from_sp
)
1187 /* ColdFire's move multiple instructions do not allow post-increment
1188 addressing. Add the size of movem loads to the final deallocation
1190 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1191 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1192 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1193 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1196 if (current_frame
.offset
+ fsize
>= 0x8000
1198 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1201 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1202 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1204 /* ColdFire's move multiple instructions do not support the
1205 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1206 stack-based restore. */
1207 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1208 GEN_INT (-(current_frame
.offset
+ fsize
)));
1209 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1210 gen_rtx_REG (Pmode
, A1_REG
),
1211 frame_pointer_rtx
));
1212 restore_from_sp
= true;
1216 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1222 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1224 /* Restore each register separately in the same order moveml does. */
1226 HOST_WIDE_INT offset
;
1228 offset
= current_frame
.offset
+ fsize
;
1229 for (i
= 0; i
< 16; i
++)
1230 if (current_frame
.reg_mask
& (1 << i
))
1236 /* Generate the address -OFFSET(%fp,%a1.l). */
1237 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1238 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1239 addr
= plus_constant (Pmode
, addr
, -offset
);
1241 else if (restore_from_sp
)
1242 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1244 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1245 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1246 gen_frame_mem (SImode
, addr
));
1247 offset
-= GET_MODE_SIZE (SImode
);
1250 else if (current_frame
.reg_mask
)
1253 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1254 gen_rtx_REG (Pmode
, A1_REG
),
1256 -(current_frame
.offset
+ fsize
),
1257 current_frame
.reg_no
, D0_REG
,
1258 current_frame
.reg_mask
, false, false);
1259 else if (restore_from_sp
)
1260 m68k_emit_movem (stack_pointer_rtx
, 0,
1261 current_frame
.reg_no
, D0_REG
,
1262 current_frame
.reg_mask
, false,
1265 m68k_emit_movem (frame_pointer_rtx
,
1266 -(current_frame
.offset
+ fsize
),
1267 current_frame
.reg_no
, D0_REG
,
1268 current_frame
.reg_mask
, false, false);
1271 if (current_frame
.fpu_no
> 0)
1274 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1275 gen_rtx_REG (Pmode
, A1_REG
),
1277 -(current_frame
.foffset
+ fsize
),
1278 current_frame
.fpu_no
, FP0_REG
,
1279 current_frame
.fpu_mask
, false, false);
1280 else if (restore_from_sp
)
1282 if (TARGET_COLDFIRE
)
1286 /* If we used moveml to restore the integer registers, the
1287 stack pointer will still point to the bottom of the moveml
1288 save area. Find the stack offset of the first FP
1290 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1293 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1294 m68k_emit_movem (stack_pointer_rtx
, offset
,
1295 current_frame
.fpu_no
, FP0_REG
,
1296 current_frame
.fpu_mask
, false, false);
1299 m68k_emit_movem (stack_pointer_rtx
, 0,
1300 current_frame
.fpu_no
, FP0_REG
,
1301 current_frame
.fpu_mask
, false, true);
1304 m68k_emit_movem (frame_pointer_rtx
,
1305 -(current_frame
.foffset
+ fsize
),
1306 current_frame
.fpu_no
, FP0_REG
,
1307 current_frame
.fpu_mask
, false, false);
1310 if (frame_pointer_needed
)
1311 emit_insn (gen_unlink (frame_pointer_rtx
));
1312 else if (fsize_with_regs
)
1313 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1315 GEN_INT (fsize_with_regs
)));
1317 if (crtl
->calls_eh_return
)
1318 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1320 EH_RETURN_STACKADJ_RTX
));
1323 emit_jump_insn (ret_rtx
);
1326 /* Return true if X is a valid comparison operator for the dbcc
1329 Note it rejects floating point comparison operators.
1330 (In the future we could use Fdbcc).
1332 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1335 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1337 switch (GET_CODE (x
))
1339 case EQ
: case NE
: case GTU
: case LTU
:
1343 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1345 case GT
: case LT
: case GE
: case LE
:
1346 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1352 /* Return nonzero if flags are currently in the 68881 flag register. */
1354 flags_in_68881 (void)
1356 /* We could add support for these in the future */
1357 return cc_status
.flags
& CC_IN_68881
;
1360 /* Return true if PARALLEL contains register REGNO. */
1362 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1366 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1369 if (GET_CODE (parallel
) != PARALLEL
)
1372 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1376 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1377 if (REG_P (x
) && REGNO (x
) == regno
)
1384 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1387 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1389 enum m68k_function_kind kind
;
1391 /* We cannot use sibcalls for nested functions because we use the
1392 static chain register for indirect calls. */
1393 if (CALL_EXPR_STATIC_CHAIN (exp
))
1396 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1398 /* Check that the return value locations are the same. For
1399 example that we aren't returning a value from the sibling in
1400 a D0 register but then need to transfer it to a A0 register. */
1404 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1406 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1408 /* Check that the values are equal or that the result the callee
1409 function returns is superset of what the current function returns. */
1410 if (!(rtx_equal_p (cfun_value
, call_value
)
1411 || (REG_P (cfun_value
)
1412 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1416 kind
= m68k_get_function_kind (current_function_decl
);
1417 if (kind
== m68k_fk_normal_function
)
1418 /* We can always sibcall from a normal function, because it's
1419 undefined if it is calling an interrupt function. */
1422 /* Otherwise we can only sibcall if the function kind is known to be
1424 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1430 /* On the m68k all args are always pushed. */
1433 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1434 machine_mode mode ATTRIBUTE_UNUSED
,
1435 const_tree type ATTRIBUTE_UNUSED
,
1436 bool named ATTRIBUTE_UNUSED
)
1442 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1443 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1445 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1447 *cum
+= (mode
!= BLKmode
1448 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1449 : (int_size_in_bytes (type
) + 3) & ~3);
1452 /* Convert X to a legitimate function call memory reference and return the
1456 m68k_legitimize_call_address (rtx x
)
1458 gcc_assert (MEM_P (x
));
1459 if (call_operand (XEXP (x
, 0), VOIDmode
))
1461 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1464 /* Likewise for sibling calls. */
1467 m68k_legitimize_sibcall_address (rtx x
)
1469 gcc_assert (MEM_P (x
));
1470 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1473 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1474 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1477 /* Convert X to a legitimate address and return it if successful. Otherwise
1480 For the 68000, we handle X+REG by loading X into a register R and
1481 using R+REG. R will go in an address reg and indexing will be used.
1482 However, if REG is a broken-out memory address or multiplication,
1483 nothing needs to be done because REG can certainly go in an address reg. */
1486 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1488 if (m68k_tls_symbol_p (x
))
1489 return m68k_legitimize_tls_address (x
);
1491 if (GET_CODE (x
) == PLUS
)
1493 int ch
= (x
) != (oldx
);
1496 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1498 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1501 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1503 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1506 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1510 if (GET_CODE (XEXP (x
, 1)) == REG
1511 && GET_CODE (XEXP (x
, 0)) == REG
)
1513 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1516 x
= force_operand (x
, 0);
1520 if (memory_address_p (mode
, x
))
1523 if (GET_CODE (XEXP (x
, 0)) == REG
1524 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1525 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1526 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1528 rtx temp
= gen_reg_rtx (Pmode
);
1529 rtx val
= force_operand (XEXP (x
, 1), 0);
1530 emit_move_insn (temp
, val
);
1533 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1534 && GET_CODE (XEXP (x
, 0)) == REG
)
1535 x
= force_operand (x
, 0);
1537 else if (GET_CODE (XEXP (x
, 1)) == REG
1538 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1539 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1540 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1542 rtx temp
= gen_reg_rtx (Pmode
);
1543 rtx val
= force_operand (XEXP (x
, 0), 0);
1544 emit_move_insn (temp
, val
);
1547 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1548 && GET_CODE (XEXP (x
, 1)) == REG
)
1549 x
= force_operand (x
, 0);
1557 /* Output a dbCC; jCC sequence. Note we do not handle the
1558 floating point version of this sequence (Fdbcc). We also
1559 do not handle alternative conditions when CC_NO_OVERFLOW is
1560 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1561 kick those out before we get here. */
1564 output_dbcc_and_branch (rtx
*operands
)
1566 switch (GET_CODE (operands
[3]))
1569 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1573 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1577 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1581 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1585 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1589 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1593 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1597 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1601 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1605 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1612 /* If the decrement is to be done in SImode, then we have
1613 to compensate for the fact that dbcc decrements in HImode. */
1614 switch (GET_MODE (operands
[0]))
1617 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1629 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1632 enum rtx_code op_code
= GET_CODE (op
);
1634 /* This does not produce a useful cc. */
1637 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1638 below. Swap the operands and change the op if these requirements
1639 are not fulfilled. */
1640 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1644 operand1
= operand2
;
1646 op_code
= swap_condition (op_code
);
1648 loperands
[0] = operand1
;
1649 if (GET_CODE (operand1
) == REG
)
1650 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1652 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1653 if (operand2
!= const0_rtx
)
1655 loperands
[2] = operand2
;
1656 if (GET_CODE (operand2
) == REG
)
1657 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1659 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1661 loperands
[4] = gen_label_rtx ();
1662 if (operand2
!= const0_rtx
)
1663 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1666 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1667 output_asm_insn ("tst%.l %0", loperands
);
1669 output_asm_insn ("cmp%.w #0,%0", loperands
);
1671 output_asm_insn ("jne %l4", loperands
);
1673 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1674 output_asm_insn ("tst%.l %1", loperands
);
1676 output_asm_insn ("cmp%.w #0,%1", loperands
);
1679 loperands
[5] = dest
;
1684 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1685 CODE_LABEL_NUMBER (loperands
[4]));
1686 output_asm_insn ("seq %5", loperands
);
1690 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1691 CODE_LABEL_NUMBER (loperands
[4]));
1692 output_asm_insn ("sne %5", loperands
);
1696 loperands
[6] = gen_label_rtx ();
1697 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1698 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1699 CODE_LABEL_NUMBER (loperands
[4]));
1700 output_asm_insn ("sgt %5", loperands
);
1701 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1702 CODE_LABEL_NUMBER (loperands
[6]));
1706 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1707 CODE_LABEL_NUMBER (loperands
[4]));
1708 output_asm_insn ("shi %5", loperands
);
1712 loperands
[6] = gen_label_rtx ();
1713 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1714 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1715 CODE_LABEL_NUMBER (loperands
[4]));
1716 output_asm_insn ("slt %5", loperands
);
1717 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1718 CODE_LABEL_NUMBER (loperands
[6]));
1722 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1723 CODE_LABEL_NUMBER (loperands
[4]));
1724 output_asm_insn ("scs %5", loperands
);
1728 loperands
[6] = gen_label_rtx ();
1729 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1730 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1731 CODE_LABEL_NUMBER (loperands
[4]));
1732 output_asm_insn ("sge %5", loperands
);
1733 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1734 CODE_LABEL_NUMBER (loperands
[6]));
1738 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1739 CODE_LABEL_NUMBER (loperands
[4]));
1740 output_asm_insn ("scc %5", loperands
);
1744 loperands
[6] = gen_label_rtx ();
1745 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1746 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1747 CODE_LABEL_NUMBER (loperands
[4]));
1748 output_asm_insn ("sle %5", loperands
);
1749 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1750 CODE_LABEL_NUMBER (loperands
[6]));
1754 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1755 CODE_LABEL_NUMBER (loperands
[4]));
1756 output_asm_insn ("sls %5", loperands
);
1766 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1768 operands
[0] = countop
;
1769 operands
[1] = dataop
;
1771 if (GET_CODE (countop
) == CONST_INT
)
1773 register int count
= INTVAL (countop
);
1774 /* If COUNT is bigger than size of storage unit in use,
1775 advance to the containing unit of same size. */
1776 if (count
> signpos
)
1778 int offset
= (count
& ~signpos
) / 8;
1779 count
= count
& signpos
;
1780 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1782 if (count
== signpos
)
1783 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1785 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1787 /* These three statements used to use next_insns_test_no...
1788 but it appears that this should do the same job. */
1790 && next_insn_tests_no_inequality (insn
))
1793 && next_insn_tests_no_inequality (insn
))
1796 && next_insn_tests_no_inequality (insn
))
1798 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1799 On some m68k variants unfortunately that's slower than btst.
1800 On 68000 and higher, that should also work for all HImode operands. */
1801 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1803 if (count
== 3 && DATA_REG_P (operands
[1])
1804 && next_insn_tests_no_inequality (insn
))
1806 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1807 return "move%.w %1,%%ccr";
1809 if (count
== 2 && DATA_REG_P (operands
[1])
1810 && next_insn_tests_no_inequality (insn
))
1812 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1813 return "move%.w %1,%%ccr";
1815 /* count == 1 followed by bvc/bvs and
1816 count == 0 followed by bcc/bcs are also possible, but need
1817 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1820 cc_status
.flags
= CC_NOT_NEGATIVE
;
1822 return "btst %0,%1";
1825 /* Return true if X is a legitimate base register. STRICT_P says
1826 whether we need strict checking. */
1829 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1831 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1832 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1837 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1838 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1841 /* Return true if X is a legitimate index register. STRICT_P says
1842 whether we need strict checking. */
1845 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1847 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1852 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1853 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1856 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1857 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1858 ADDRESS if so. STRICT_P says whether we need strict checking. */
1861 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1865 /* Check for a scale factor. */
1867 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1868 && GET_CODE (x
) == MULT
1869 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1870 && (INTVAL (XEXP (x
, 1)) == 2
1871 || INTVAL (XEXP (x
, 1)) == 4
1872 || (INTVAL (XEXP (x
, 1)) == 8
1873 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1875 scale
= INTVAL (XEXP (x
, 1));
1879 /* Check for a word extension. */
1880 if (!TARGET_COLDFIRE
1881 && GET_CODE (x
) == SIGN_EXTEND
1882 && GET_MODE (XEXP (x
, 0)) == HImode
)
1885 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1887 address
->scale
= scale
;
1895 /* Return true if X is an illegitimate symbolic constant. */
1898 m68k_illegitimate_symbolic_constant_p (rtx x
)
1902 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1904 split_const (x
, &base
, &offset
);
1905 if (GET_CODE (base
) == SYMBOL_REF
1906 && !offset_within_block_p (base
, INTVAL (offset
)))
1909 return m68k_tls_reference_p (x
, false);
1912 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1915 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1917 return m68k_illegitimate_symbolic_constant_p (x
);
1920 /* Return true if X is a legitimate constant address that can reach
1921 bytes in the range [X, X + REACH). STRICT_P says whether we need
1925 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1929 if (!CONSTANT_ADDRESS_P (x
))
1933 && !(strict_p
&& TARGET_PCREL
)
1934 && symbolic_operand (x
, VOIDmode
))
1937 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1939 split_const (x
, &base
, &offset
);
1940 if (GET_CODE (base
) == SYMBOL_REF
1941 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1945 return !m68k_tls_reference_p (x
, false);
1948 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1949 labels will become jump tables. */
1952 m68k_jump_table_ref_p (rtx x
)
1954 if (GET_CODE (x
) != LABEL_REF
)
1957 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1958 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1961 insn
= next_nonnote_insn (insn
);
1962 return insn
&& JUMP_TABLE_DATA_P (insn
);
1965 /* Return true if X is a legitimate address for values of mode MODE.
1966 STRICT_P says whether strict checking is needed. If the address
1967 is valid, describe its components in *ADDRESS. */
1970 m68k_decompose_address (machine_mode mode
, rtx x
,
1971 bool strict_p
, struct m68k_address
*address
)
1975 memset (address
, 0, sizeof (*address
));
1977 if (mode
== BLKmode
)
1980 reach
= GET_MODE_SIZE (mode
);
1982 /* Check for (An) (mode 2). */
1983 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1989 /* Check for -(An) and (An)+ (modes 3 and 4). */
1990 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1991 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1993 address
->code
= GET_CODE (x
);
1994 address
->base
= XEXP (x
, 0);
1998 /* Check for (d16,An) (mode 5). */
1999 if (GET_CODE (x
) == PLUS
2000 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2001 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2002 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2004 address
->base
= XEXP (x
, 0);
2005 address
->offset
= XEXP (x
, 1);
2009 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2010 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2012 if (GET_CODE (x
) == PLUS
2013 && XEXP (x
, 0) == pic_offset_table_rtx
)
2015 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2016 they are invalid in this context. */
2017 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2019 address
->base
= XEXP (x
, 0);
2020 address
->offset
= XEXP (x
, 1);
2025 /* The ColdFire FPU only accepts addressing modes 2-5. */
2026 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2029 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2030 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2031 All these modes are variations of mode 7. */
2032 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2034 address
->offset
= x
;
2038 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2041 ??? do_tablejump creates these addresses before placing the target
2042 label, so we have to assume that unplaced labels are jump table
2043 references. It seems unlikely that we would ever generate indexed
2044 accesses to unplaced labels in other cases. */
2045 if (GET_CODE (x
) == PLUS
2046 && m68k_jump_table_ref_p (XEXP (x
, 1))
2047 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2049 address
->offset
= XEXP (x
, 1);
2053 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2054 (bd,An,Xn.SIZE*SCALE) addresses. */
2058 /* Check for a nonzero base displacement. */
2059 if (GET_CODE (x
) == PLUS
2060 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2062 address
->offset
= XEXP (x
, 1);
2066 /* Check for a suppressed index register. */
2067 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2073 /* Check for a suppressed base register. Do not allow this case
2074 for non-symbolic offsets as it effectively gives gcc freedom
2075 to treat data registers as base registers, which can generate
2078 && symbolic_operand (address
->offset
, VOIDmode
)
2079 && m68k_decompose_index (x
, strict_p
, address
))
2084 /* Check for a nonzero base displacement. */
2085 if (GET_CODE (x
) == PLUS
2086 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2087 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2089 address
->offset
= XEXP (x
, 1);
2094 /* We now expect the sum of a base and an index. */
2095 if (GET_CODE (x
) == PLUS
)
2097 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2098 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2100 address
->base
= XEXP (x
, 0);
2104 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2105 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2107 address
->base
= XEXP (x
, 1);
2114 /* Return true if X is a legitimate address for values of mode MODE.
2115 STRICT_P says whether strict checking is needed. */
2118 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2120 struct m68k_address address
;
2122 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2125 /* Return true if X is a memory, describing its address in ADDRESS if so.
2126 Apply strict checking if called during or after reload. */
2129 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2132 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2133 reload_in_progress
|| reload_completed
,
2137 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2140 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2142 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2145 /* Return true if X matches the 'Q' constraint. It must be a memory
2146 with a base address and no constant offset or index. */
2149 m68k_matches_q_p (rtx x
)
2151 struct m68k_address address
;
2153 return (m68k_legitimate_mem_p (x
, &address
)
2154 && address
.code
== UNKNOWN
2160 /* Return true if X matches the 'U' constraint. It must be a base address
2161 with a constant offset and no index. */
2164 m68k_matches_u_p (rtx x
)
2166 struct m68k_address address
;
2168 return (m68k_legitimate_mem_p (x
, &address
)
2169 && address
.code
== UNKNOWN
2175 /* Return GOT pointer. */
2180 if (pic_offset_table_rtx
== NULL_RTX
)
2181 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2183 crtl
->uses_pic_offset_table
= 1;
2185 return pic_offset_table_rtx
;
2188 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2190 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2191 RELOC_TLSIE
, RELOC_TLSLE
};
2193 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2195 /* Wrap symbol X into unspec representing relocation RELOC.
2196 BASE_REG - register that should be added to the result.
2197 TEMP_REG - if non-null, temporary register. */
2200 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2204 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2206 if (TARGET_COLDFIRE
&& use_x_p
)
2207 /* When compiling with -mx{got, tls} switch the code will look like this:
2209 move.l <X>@<RELOC>,<TEMP_REG>
2210 add.l <BASE_REG>,<TEMP_REG> */
2212 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2213 to put @RELOC after reference. */
2214 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2216 x
= gen_rtx_CONST (Pmode
, x
);
2218 if (temp_reg
== NULL
)
2220 gcc_assert (can_create_pseudo_p ());
2221 temp_reg
= gen_reg_rtx (Pmode
);
2224 emit_move_insn (temp_reg
, x
);
2225 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2230 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2232 x
= gen_rtx_CONST (Pmode
, x
);
2234 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2240 /* Helper for m68k_unwrap_symbol.
2241 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2242 sets *RELOC_PTR to relocation type for the symbol. */
2245 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2246 enum m68k_reloc
*reloc_ptr
)
2248 if (GET_CODE (orig
) == CONST
)
2251 enum m68k_reloc dummy
;
2255 if (reloc_ptr
== NULL
)
2258 /* Handle an addend. */
2259 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2260 && CONST_INT_P (XEXP (x
, 1)))
2263 if (GET_CODE (x
) == UNSPEC
)
2265 switch (XINT (x
, 1))
2267 case UNSPEC_RELOC16
:
2268 orig
= XVECEXP (x
, 0, 0);
2269 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2272 case UNSPEC_RELOC32
:
2273 if (unwrap_reloc32_p
)
2275 orig
= XVECEXP (x
, 0, 0);
2276 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2289 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2290 UNSPEC_RELOC32 wrappers. */
2293 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2295 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2298 /* Prescan insn before outputing assembler for it. */
2301 m68k_final_prescan_insn (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2302 rtx
*operands
, int n_operands
)
2306 /* Combine and, possibly, other optimizations may do good job
2308 (const (unspec [(symbol)]))
2310 (const (plus (unspec [(symbol)])
2312 The problem with this is emitting @TLS or @GOT decorations.
2313 The decoration is emitted when processing (unspec), so the
2314 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2316 It seems that the easiest solution to this is to convert such
2318 (const (unspec [(plus (symbol)
2320 Note, that the top level of operand remains intact, so we don't have
2321 to patch up anything outside of the operand. */
2323 subrtx_var_iterator::array_type array
;
2324 for (i
= 0; i
< n_operands
; ++i
)
2330 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2333 if (m68k_unwrap_symbol (x
, true) != x
)
2337 gcc_assert (GET_CODE (x
) == CONST
);
2340 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2345 unspec
= XEXP (plus
, 0);
2346 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2347 addend
= XEXP (plus
, 1);
2348 gcc_assert (CONST_INT_P (addend
));
2350 /* We now have all the pieces, rearrange them. */
2352 /* Move symbol to plus. */
2353 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2355 /* Move plus inside unspec. */
2356 XVECEXP (unspec
, 0, 0) = plus
;
2358 /* Move unspec to top level of const. */
2359 XEXP (x
, 0) = unspec
;
2361 iter
.skip_subrtxes ();
2367 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2368 If REG is non-null, use it; generate new pseudo otherwise. */
2371 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2375 if (reg
== NULL_RTX
)
2377 gcc_assert (can_create_pseudo_p ());
2378 reg
= gen_reg_rtx (Pmode
);
2381 insn
= emit_move_insn (reg
, x
);
2382 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2384 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2389 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2393 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2395 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2397 x
= gen_rtx_MEM (Pmode
, x
);
2398 MEM_READONLY_P (x
) = 1;
2403 /* Legitimize PIC addresses. If the address is already
2404 position-independent, we return ORIG. Newly generated
2405 position-independent addresses go to REG. If we need more
2406 than one register, we lose.
2408 An address is legitimized by making an indirect reference
2409 through the Global Offset Table with the name of the symbol
2412 The assembler and linker are responsible for placing the
2413 address of the symbol in the GOT. The function prologue
2414 is responsible for initializing a5 to the starting address
2417 The assembler is also responsible for translating a symbol name
2418 into a constant displacement from the start of the GOT.
2420 A quick example may make things a little clearer:
2422 When not generating PIC code to store the value 12345 into _foo
2423 we would generate the following code:
2427 When generating PIC two transformations are made. First, the compiler
2428 loads the address of foo into a register. So the first transformation makes:
2433 The code in movsi will intercept the lea instruction and call this
2434 routine which will transform the instructions into:
2436 movel a5@(_foo:w), a0
2440 That (in a nutshell) is how *all* symbol and label references are
2444 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2449 /* First handle a simple SYMBOL_REF or LABEL_REF */
2450 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2454 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2455 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2457 else if (GET_CODE (orig
) == CONST
)
2461 /* Make sure this has not already been legitimized. */
2462 if (m68k_unwrap_symbol (orig
, true) != orig
)
2467 /* legitimize both operands of the PLUS */
2468 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2470 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2471 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2472 base
== reg
? 0 : reg
);
2474 if (GET_CODE (orig
) == CONST_INT
)
2475 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2477 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2483 /* The __tls_get_addr symbol. */
2484 static GTY(()) rtx m68k_tls_get_addr
;
2486 /* Return SYMBOL_REF for __tls_get_addr. */
2489 m68k_get_tls_get_addr (void)
2491 if (m68k_tls_get_addr
== NULL_RTX
)
2492 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2494 return m68k_tls_get_addr
;
2497 /* Return libcall result in A0 instead of usual D0. */
2498 static bool m68k_libcall_value_in_a0_p
= false;
2500 /* Emit instruction sequence that calls __tls_get_addr. X is
2501 the TLS symbol we are referencing and RELOC is the symbol type to use
2502 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2503 emitted. A pseudo register with result of __tls_get_addr call is
2507 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2513 /* Emit the call sequence. */
2516 /* FIXME: Unfortunately, emit_library_call_value does not
2517 consider (plus (%a5) (const (unspec))) to be a good enough
2518 operand for push, so it forces it into a register. The bad
2519 thing about this is that combiner, due to copy propagation and other
2520 optimizations, sometimes can not later fix this. As a consequence,
2521 additional register may be allocated resulting in a spill.
2522 For reference, see args processing loops in
2523 calls.c:emit_library_call_value_1.
2524 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2525 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2527 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2528 is the simpliest way of generating a call. The difference between
2529 __tls_get_addr() and libcall is that the result is returned in D0
2530 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2531 which temporarily switches returning the result to A0. */
2533 m68k_libcall_value_in_a0_p
= true;
2534 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2535 Pmode
, 1, x
, Pmode
);
2536 m68k_libcall_value_in_a0_p
= false;
2538 insns
= get_insns ();
2541 gcc_assert (can_create_pseudo_p ());
2542 dest
= gen_reg_rtx (Pmode
);
2543 emit_libcall_block (insns
, dest
, a0
, eqv
);
2548 /* The __tls_get_addr symbol. */
2549 static GTY(()) rtx m68k_read_tp
;
2551 /* Return SYMBOL_REF for __m68k_read_tp. */
2554 m68k_get_m68k_read_tp (void)
2556 if (m68k_read_tp
== NULL_RTX
)
2557 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2559 return m68k_read_tp
;
2562 /* Emit instruction sequence that calls __m68k_read_tp.
2563 A pseudo register with result of __m68k_read_tp call is returned. */
2566 m68k_call_m68k_read_tp (void)
2575 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2576 is the simpliest way of generating a call. The difference between
2577 __m68k_read_tp() and libcall is that the result is returned in D0
2578 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2579 which temporarily switches returning the result to A0. */
2581 /* Emit the call sequence. */
2582 m68k_libcall_value_in_a0_p
= true;
2583 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2585 m68k_libcall_value_in_a0_p
= false;
2586 insns
= get_insns ();
2589 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2590 share the m68k_read_tp result with other IE/LE model accesses. */
2591 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2593 gcc_assert (can_create_pseudo_p ());
2594 dest
= gen_reg_rtx (Pmode
);
2595 emit_libcall_block (insns
, dest
, a0
, eqv
);
2600 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2601 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2605 m68k_legitimize_tls_address (rtx orig
)
2607 switch (SYMBOL_REF_TLS_MODEL (orig
))
2609 case TLS_MODEL_GLOBAL_DYNAMIC
:
2610 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2613 case TLS_MODEL_LOCAL_DYNAMIC
:
2619 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2620 share the LDM result with other LD model accesses. */
2621 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2624 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2626 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2628 if (can_create_pseudo_p ())
2629 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2635 case TLS_MODEL_INITIAL_EXEC
:
2640 a0
= m68k_call_m68k_read_tp ();
2642 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2643 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2645 if (can_create_pseudo_p ())
2646 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2652 case TLS_MODEL_LOCAL_EXEC
:
2657 a0
= m68k_call_m68k_read_tp ();
2659 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2661 if (can_create_pseudo_p ())
2662 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2675 /* Return true if X is a TLS symbol. */
2678 m68k_tls_symbol_p (rtx x
)
2680 if (!TARGET_HAVE_TLS
)
2683 if (GET_CODE (x
) != SYMBOL_REF
)
2686 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2689 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2690 though illegitimate one.
2691 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2694 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2696 if (!TARGET_HAVE_TLS
)
2701 subrtx_var_iterator::array_type array
;
2702 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2706 /* Note: this is not the same as m68k_tls_symbol_p. */
2707 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2710 /* Don't recurse into legitimate TLS references. */
2711 if (m68k_tls_reference_p (x
, true))
2712 iter
.skip_subrtxes ();
2718 enum m68k_reloc reloc
= RELOC_GOT
;
2720 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2721 && TLS_RELOC_P (reloc
));
2727 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2729 /* Return the type of move that should be used for integer I. */
2732 m68k_const_method (HOST_WIDE_INT i
)
2739 /* The ColdFire doesn't have byte or word operations. */
2740 /* FIXME: This may not be useful for the m68060 either. */
2741 if (!TARGET_COLDFIRE
)
2743 /* if -256 < N < 256 but N is not in range for a moveq
2744 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2745 if (USE_MOVQ (i
^ 0xff))
2747 /* Likewise, try with not.w */
2748 if (USE_MOVQ (i
^ 0xffff))
2750 /* This is the only value where neg.w is useful */
2755 /* Try also with swap. */
2757 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2762 /* Try using MVZ/MVS with an immediate value to load constants. */
2763 if (i
>= 0 && i
<= 65535)
2765 if (i
>= -32768 && i
<= 32767)
2769 /* Otherwise, use move.l */
2773 /* Return the cost of moving constant I into a data register. */
2776 const_int_cost (HOST_WIDE_INT i
)
2778 switch (m68k_const_method (i
))
2781 /* Constants between -128 and 127 are cheap due to moveq. */
2789 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2799 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2800 int *total
, bool speed ATTRIBUTE_UNUSED
)
2805 /* Constant zero is super cheap due to clr instruction. */
2806 if (x
== const0_rtx
)
2809 *total
= const_int_cost (INTVAL (x
));
2819 /* Make 0.0 cheaper than other floating constants to
2820 encourage creating tstsf and tstdf insns. */
2821 if (outer_code
== COMPARE
2822 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2828 /* These are vaguely right for a 68020. */
2829 /* The costs for long multiply have been adjusted to work properly
2830 in synth_mult on the 68020, relative to an average of the time
2831 for add and the time for shift, taking away a little more because
2832 sometimes move insns are needed. */
2833 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2838 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2839 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2841 : TARGET_COLDFIRE ? 3 : 13)
2846 : TUNE_68000_10 ? 5 \
2847 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2848 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2850 : TARGET_COLDFIRE ? 2 : 8)
2853 (TARGET_CF_HWDIV ? 11 \
2854 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2857 /* An lea costs about three times as much as a simple add. */
2858 if (GET_MODE (x
) == SImode
2859 && GET_CODE (XEXP (x
, 1)) == REG
2860 && GET_CODE (XEXP (x
, 0)) == MULT
2861 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2862 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2863 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2864 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2865 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2867 /* lea an@(dx:l:i),am */
2868 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2878 *total
= COSTS_N_INSNS(1);
2883 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2885 if (INTVAL (XEXP (x
, 1)) < 16)
2886 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2888 /* We're using clrw + swap for these cases. */
2889 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2892 *total
= COSTS_N_INSNS (10); /* Worst case. */
2895 /* A shift by a big integer takes an extra instruction. */
2896 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2897 && (INTVAL (XEXP (x
, 1)) == 16))
2899 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2902 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2903 && !(INTVAL (XEXP (x
, 1)) > 0
2904 && INTVAL (XEXP (x
, 1)) <= 8))
2906 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2912 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2913 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2914 && GET_MODE (x
) == SImode
)
2915 *total
= COSTS_N_INSNS (MULW_COST
);
2916 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2917 *total
= COSTS_N_INSNS (MULW_COST
);
2919 *total
= COSTS_N_INSNS (MULL_COST
);
2926 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2927 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2928 else if (TARGET_CF_HWDIV
)
2929 *total
= COSTS_N_INSNS (18);
2931 *total
= COSTS_N_INSNS (43); /* div.l */
2935 if (outer_code
== COMPARE
)
2944 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2948 output_move_const_into_data_reg (rtx
*operands
)
2952 i
= INTVAL (operands
[1]);
2953 switch (m68k_const_method (i
))
2956 return "mvzw %1,%0";
2958 return "mvsw %1,%0";
2960 return "moveq %1,%0";
2963 operands
[1] = GEN_INT (i
^ 0xff);
2964 return "moveq %1,%0\n\tnot%.b %0";
2967 operands
[1] = GEN_INT (i
^ 0xffff);
2968 return "moveq %1,%0\n\tnot%.w %0";
2971 return "moveq #-128,%0\n\tneg%.w %0";
2976 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2977 return "moveq %1,%0\n\tswap %0";
2980 return "move%.l %1,%0";
2986 /* Return true if I can be handled by ISA B's mov3q instruction. */
2989 valid_mov3q_const (HOST_WIDE_INT i
)
2991 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2994 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2995 I is the value of OPERANDS[1]. */
2998 output_move_simode_const (rtx
*operands
)
3004 src
= INTVAL (operands
[1]);
3006 && (DATA_REG_P (dest
) || MEM_P (dest
))
3007 /* clr insns on 68000 read before writing. */
3008 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3009 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3011 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3012 return "mov3q%.l %1,%0";
3013 else if (src
== 0 && ADDRESS_REG_P (dest
))
3014 return "sub%.l %0,%0";
3015 else if (DATA_REG_P (dest
))
3016 return output_move_const_into_data_reg (operands
);
3017 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3019 if (valid_mov3q_const (src
))
3020 return "mov3q%.l %1,%0";
3021 return "move%.w %1,%0";
3023 else if (MEM_P (dest
)
3024 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3025 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3026 && IN_RANGE (src
, -0x8000, 0x7fff))
3028 if (valid_mov3q_const (src
))
3029 return "mov3q%.l %1,%-";
3032 return "move%.l %1,%0";
3036 output_move_simode (rtx
*operands
)
3038 if (GET_CODE (operands
[1]) == CONST_INT
)
3039 return output_move_simode_const (operands
);
3040 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3041 || GET_CODE (operands
[1]) == CONST
)
3042 && push_operand (operands
[0], SImode
))
3044 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3045 || GET_CODE (operands
[1]) == CONST
)
3046 && ADDRESS_REG_P (operands
[0]))
3047 return "lea %a1,%0";
3048 return "move%.l %1,%0";
3052 output_move_himode (rtx
*operands
)
3054 if (GET_CODE (operands
[1]) == CONST_INT
)
3056 if (operands
[1] == const0_rtx
3057 && (DATA_REG_P (operands
[0])
3058 || GET_CODE (operands
[0]) == MEM
)
3059 /* clr insns on 68000 read before writing. */
3060 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3061 || !(GET_CODE (operands
[0]) == MEM
3062 && MEM_VOLATILE_P (operands
[0]))))
3064 else if (operands
[1] == const0_rtx
3065 && ADDRESS_REG_P (operands
[0]))
3066 return "sub%.l %0,%0";
3067 else if (DATA_REG_P (operands
[0])
3068 && INTVAL (operands
[1]) < 128
3069 && INTVAL (operands
[1]) >= -128)
3070 return "moveq %1,%0";
3071 else if (INTVAL (operands
[1]) < 0x8000
3072 && INTVAL (operands
[1]) >= -0x8000)
3073 return "move%.w %1,%0";
3075 else if (CONSTANT_P (operands
[1]))
3076 return "move%.l %1,%0";
3077 return "move%.w %1,%0";
3081 output_move_qimode (rtx
*operands
)
3083 /* 68k family always modifies the stack pointer by at least 2, even for
3084 byte pushes. The 5200 (ColdFire) does not do this. */
3086 /* This case is generated by pushqi1 pattern now. */
3087 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3088 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3089 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3090 && ! ADDRESS_REG_P (operands
[1])
3091 && ! TARGET_COLDFIRE
));
3093 /* clr and st insns on 68000 read before writing. */
3094 if (!ADDRESS_REG_P (operands
[0])
3095 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3096 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3098 if (operands
[1] == const0_rtx
)
3100 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3101 && GET_CODE (operands
[1]) == CONST_INT
3102 && (INTVAL (operands
[1]) & 255) == 255)
3108 if (GET_CODE (operands
[1]) == CONST_INT
3109 && DATA_REG_P (operands
[0])
3110 && INTVAL (operands
[1]) < 128
3111 && INTVAL (operands
[1]) >= -128)
3112 return "moveq %1,%0";
3113 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3114 return "sub%.l %0,%0";
3115 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3116 return "move%.l %1,%0";
3117 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3118 from address registers. */
3119 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3120 return "move%.w %1,%0";
3121 return "move%.b %1,%0";
3125 output_move_stricthi (rtx
*operands
)
3127 if (operands
[1] == const0_rtx
3128 /* clr insns on 68000 read before writing. */
3129 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3130 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3132 return "move%.w %1,%0";
3136 output_move_strictqi (rtx
*operands
)
3138 if (operands
[1] == const0_rtx
3139 /* clr insns on 68000 read before writing. */
3140 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3141 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3143 return "move%.b %1,%0";
3146 /* Return the best assembler insn template
3147 for moving operands[1] into operands[0] as a fullword. */
3150 singlemove_string (rtx
*operands
)
3152 if (GET_CODE (operands
[1]) == CONST_INT
)
3153 return output_move_simode_const (operands
);
3154 return "move%.l %1,%0";
3158 /* Output assembler or rtl code to perform a doubleword move insn
3159 with operands OPERANDS.
3160 Pointers to 3 helper functions should be specified:
3161 HANDLE_REG_ADJUST to adjust a register by a small value,
3162 HANDLE_COMPADR to compute an address and
3163 HANDLE_MOVSI to move 4 bytes. */
3166 handle_move_double (rtx operands
[2],
3167 void (*handle_reg_adjust
) (rtx
, int),
3168 void (*handle_compadr
) (rtx
[2]),
3169 void (*handle_movsi
) (rtx
[2]))
3173 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3178 rtx addreg0
= 0, addreg1
= 0;
3179 int dest_overlapped_low
= 0;
3180 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3185 /* First classify both operands. */
3187 if (REG_P (operands
[0]))
3189 else if (offsettable_memref_p (operands
[0]))
3191 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3193 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3195 else if (GET_CODE (operands
[0]) == MEM
)
3200 if (REG_P (operands
[1]))
3202 else if (CONSTANT_P (operands
[1]))
3204 else if (offsettable_memref_p (operands
[1]))
3206 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3208 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3210 else if (GET_CODE (operands
[1]) == MEM
)
3215 /* Check for the cases that the operand constraints are not supposed
3216 to allow to happen. Generating code for these cases is
3218 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3220 /* If one operand is decrementing and one is incrementing
3221 decrement the former register explicitly
3222 and change that operand into ordinary indexing. */
3224 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3226 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3228 handle_reg_adjust (operands
[0], -size
);
3230 if (GET_MODE (operands
[1]) == XFmode
)
3231 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3232 else if (GET_MODE (operands
[0]) == DFmode
)
3233 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3235 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3238 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3240 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3242 handle_reg_adjust (operands
[1], -size
);
3244 if (GET_MODE (operands
[1]) == XFmode
)
3245 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3246 else if (GET_MODE (operands
[1]) == DFmode
)
3247 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3249 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3253 /* If an operand is an unoffsettable memory ref, find a register
3254 we can increment temporarily to make it refer to the second word. */
3256 if (optype0
== MEMOP
)
3257 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3259 if (optype1
== MEMOP
)
3260 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3262 /* Ok, we can do one word at a time.
3263 Normally we do the low-numbered word first,
3264 but if either operand is autodecrementing then we
3265 do the high-numbered word first.
3267 In either case, set up in LATEHALF the operands to use
3268 for the high-numbered word and in some cases alter the
3269 operands in OPERANDS to be suitable for the low-numbered word. */
3273 if (optype0
== REGOP
)
3275 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3276 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3278 else if (optype0
== OFFSOP
)
3280 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3281 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3285 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3286 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3289 if (optype1
== REGOP
)
3291 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3292 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3294 else if (optype1
== OFFSOP
)
3296 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3297 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3299 else if (optype1
== CNSTOP
)
3301 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3306 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3307 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3308 operands
[1] = GEN_INT (l
[0]);
3309 middlehalf
[1] = GEN_INT (l
[1]);
3310 latehalf
[1] = GEN_INT (l
[2]);
3314 /* No non-CONST_DOUBLE constant should ever appear
3316 gcc_assert (!CONSTANT_P (operands
[1]));
3321 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3322 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3326 /* size is not 12: */
3328 if (optype0
== REGOP
)
3329 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3330 else if (optype0
== OFFSOP
)
3331 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3333 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3335 if (optype1
== REGOP
)
3336 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3337 else if (optype1
== OFFSOP
)
3338 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3339 else if (optype1
== CNSTOP
)
3340 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3342 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3345 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3346 word first. We should use the adjusted operand 1 (which is N+4(REG))
3347 for the low word as well, to compensate for the first decrement of
3349 if (optype0
== PUSHOP
3350 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3351 operands
[1] = middlehalf
[1] = latehalf
[1];
3353 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3354 if the upper part of reg N does not appear in the MEM, arrange to
3355 emit the move late-half first. Otherwise, compute the MEM address
3356 into the upper part of N and use that as a pointer to the memory
3358 if (optype0
== REGOP
3359 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3361 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3363 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3364 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3366 /* If both halves of dest are used in the src memory address,
3367 compute the address into latehalf of dest.
3368 Note that this can't happen if the dest is two data regs. */
3370 xops
[0] = latehalf
[0];
3371 xops
[1] = XEXP (operands
[1], 0);
3373 handle_compadr (xops
);
3374 if (GET_MODE (operands
[1]) == XFmode
)
3376 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3377 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3378 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3382 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3383 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3387 && reg_overlap_mentioned_p (middlehalf
[0],
3388 XEXP (operands
[1], 0)))
3390 /* Check for two regs used by both source and dest.
3391 Note that this can't happen if the dest is all data regs.
3392 It can happen if the dest is d6, d7, a0.
3393 But in that case, latehalf is an addr reg, so
3394 the code at compadr does ok. */
3396 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3397 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3400 /* JRV says this can't happen: */
3401 gcc_assert (!addreg0
&& !addreg1
);
3403 /* Only the middle reg conflicts; simply put it last. */
3404 handle_movsi (operands
);
3405 handle_movsi (latehalf
);
3406 handle_movsi (middlehalf
);
3410 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3411 /* If the low half of dest is mentioned in the source memory
3412 address, the arrange to emit the move late half first. */
3413 dest_overlapped_low
= 1;
3416 /* If one or both operands autodecrementing,
3417 do the two words, high-numbered first. */
3419 /* Likewise, the first move would clobber the source of the second one,
3420 do them in the other order. This happens only for registers;
3421 such overlap can't happen in memory unless the user explicitly
3422 sets it up, and that is an undefined circumstance. */
3424 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3425 || (optype0
== REGOP
&& optype1
== REGOP
3426 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3427 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3428 || dest_overlapped_low
)
3430 /* Make any unoffsettable addresses point at high-numbered word. */
3432 handle_reg_adjust (addreg0
, size
- 4);
3434 handle_reg_adjust (addreg1
, size
- 4);
3437 handle_movsi (latehalf
);
3439 /* Undo the adds we just did. */
3441 handle_reg_adjust (addreg0
, -4);
3443 handle_reg_adjust (addreg1
, -4);
3447 handle_movsi (middlehalf
);
3450 handle_reg_adjust (addreg0
, -4);
3452 handle_reg_adjust (addreg1
, -4);
3455 /* Do low-numbered word. */
3457 handle_movsi (operands
);
3461 /* Normal case: do the two words, low-numbered first. */
3463 m68k_final_prescan_insn (NULL
, operands
, 2);
3464 handle_movsi (operands
);
3466 /* Do the middle one of the three words for long double */
3470 handle_reg_adjust (addreg0
, 4);
3472 handle_reg_adjust (addreg1
, 4);
3474 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3475 handle_movsi (middlehalf
);
3478 /* Make any unoffsettable addresses point at high-numbered word. */
3480 handle_reg_adjust (addreg0
, 4);
3482 handle_reg_adjust (addreg1
, 4);
3485 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3486 handle_movsi (latehalf
);
3488 /* Undo the adds we just did. */
3490 handle_reg_adjust (addreg0
, -(size
- 4));
3492 handle_reg_adjust (addreg1
, -(size
- 4));
3497 /* Output assembler code to adjust REG by N. */
3499 output_reg_adjust (rtx reg
, int n
)
3503 gcc_assert (GET_MODE (reg
) == SImode
3504 && -12 <= n
&& n
!= 0 && n
<= 12);
3509 s
= "add%.l #12,%0";
3513 s
= "addq%.l #8,%0";
3517 s
= "addq%.l #4,%0";
3521 s
= "sub%.l #12,%0";
3525 s
= "subq%.l #8,%0";
3529 s
= "subq%.l #4,%0";
3537 output_asm_insn (s
, ®
);
3540 /* Emit rtl code to adjust REG by N. */
3542 emit_reg_adjust (rtx reg1
, int n
)
3546 gcc_assert (GET_MODE (reg1
) == SImode
3547 && -12 <= n
&& n
!= 0 && n
<= 12);
3549 reg1
= copy_rtx (reg1
);
3550 reg2
= copy_rtx (reg1
);
3553 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3555 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3560 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3562 output_compadr (rtx operands
[2])
3564 output_asm_insn ("lea %a1,%0", operands
);
3567 /* Output the best assembler insn for moving operands[1] into operands[0]
3570 output_movsi (rtx operands
[2])
3572 output_asm_insn (singlemove_string (operands
), operands
);
3575 /* Copy OP and change its mode to MODE. */
3577 copy_operand (rtx op
, machine_mode mode
)
3579 /* ??? This looks really ugly. There must be a better way
3580 to change a mode on the operand. */
3581 if (GET_MODE (op
) != VOIDmode
)
3584 op
= gen_rtx_REG (mode
, REGNO (op
));
3588 PUT_MODE (op
, mode
);
3595 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3597 emit_movsi (rtx operands
[2])
3599 operands
[0] = copy_operand (operands
[0], SImode
);
3600 operands
[1] = copy_operand (operands
[1], SImode
);
3602 emit_insn (gen_movsi (operands
[0], operands
[1]));
3605 /* Output assembler code to perform a doubleword move insn
3606 with operands OPERANDS. */
3608 output_move_double (rtx
*operands
)
3610 handle_move_double (operands
,
3611 output_reg_adjust
, output_compadr
, output_movsi
);
3616 /* Output rtl code to perform a doubleword move insn
3617 with operands OPERANDS. */
3619 m68k_emit_move_double (rtx operands
[2])
3621 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3624 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3625 new rtx with the correct mode. */
3628 force_mode (machine_mode mode
, rtx orig
)
3630 if (mode
== GET_MODE (orig
))
3633 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3636 return gen_rtx_REG (mode
, REGNO (orig
));
3640 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3642 return reg_renumber
&& FP_REG_P (op
);
3645 /* Emit insns to move operands[1] into operands[0].
3647 Return 1 if we have written out everything that needs to be done to
3648 do the move. Otherwise, return 0 and the caller will emit the move
3651 Note SCRATCH_REG may not be in the proper mode depending on how it
3652 will be used. This routine is responsible for creating a new copy
3653 of SCRATCH_REG in the proper mode. */
3656 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3658 register rtx operand0
= operands
[0];
3659 register rtx operand1
= operands
[1];
3663 && reload_in_progress
&& GET_CODE (operand0
) == REG
3664 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3665 operand0
= reg_equiv_mem (REGNO (operand0
));
3666 else if (scratch_reg
3667 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3668 && GET_CODE (SUBREG_REG (operand0
)) == REG
3669 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3671 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3672 the code which tracks sets/uses for delete_output_reload. */
3673 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3674 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3675 SUBREG_BYTE (operand0
));
3676 operand0
= alter_subreg (&temp
, true);
3680 && reload_in_progress
&& GET_CODE (operand1
) == REG
3681 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3682 operand1
= reg_equiv_mem (REGNO (operand1
));
3683 else if (scratch_reg
3684 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3685 && GET_CODE (SUBREG_REG (operand1
)) == REG
3686 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3688 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3689 the code which tracks sets/uses for delete_output_reload. */
3690 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3691 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3692 SUBREG_BYTE (operand1
));
3693 operand1
= alter_subreg (&temp
, true);
3696 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3697 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3698 != XEXP (operand0
, 0)))
3699 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3700 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3701 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3702 != XEXP (operand1
, 0)))
3703 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3705 /* Handle secondary reloads for loads/stores of FP registers where
3706 the address is symbolic by using the scratch register */
3707 if (fp_reg_operand (operand0
, mode
)
3708 && ((GET_CODE (operand1
) == MEM
3709 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3710 || ((GET_CODE (operand1
) == SUBREG
3711 && GET_CODE (XEXP (operand1
, 0)) == MEM
3712 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3715 if (GET_CODE (operand1
) == SUBREG
)
3716 operand1
= XEXP (operand1
, 0);
3718 /* SCRATCH_REG will hold an address. We want
3719 it in SImode regardless of what mode it was originally given
3721 scratch_reg
= force_mode (SImode
, scratch_reg
);
3723 /* D might not fit in 14 bits either; for such cases load D into
3725 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3727 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3728 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3730 XEXP (XEXP (operand1
, 0), 0),
3734 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3735 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3736 gen_rtx_MEM (mode
, scratch_reg
)));
3739 else if (fp_reg_operand (operand1
, mode
)
3740 && ((GET_CODE (operand0
) == MEM
3741 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3742 || ((GET_CODE (operand0
) == SUBREG
)
3743 && GET_CODE (XEXP (operand0
, 0)) == MEM
3744 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3747 if (GET_CODE (operand0
) == SUBREG
)
3748 operand0
= XEXP (operand0
, 0);
3750 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3751 it in SIMODE regardless of what mode it was originally given
3753 scratch_reg
= force_mode (SImode
, scratch_reg
);
3755 /* D might not fit in 14 bits either; for such cases load D into
3757 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3759 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3760 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3763 XEXP (XEXP (operand0
, 0),
3768 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3769 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3773 /* Handle secondary reloads for loads of FP registers from constant
3774 expressions by forcing the constant into memory.
3776 use scratch_reg to hold the address of the memory location.
3778 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3779 NO_REGS when presented with a const_int and an register class
3780 containing only FP registers. Doing so unfortunately creates
3781 more problems than it solves. Fix this for 2.5. */
3782 else if (fp_reg_operand (operand0
, mode
)
3783 && CONSTANT_P (operand1
)
3788 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3789 it in SIMODE regardless of what mode it was originally given
3791 scratch_reg
= force_mode (SImode
, scratch_reg
);
3793 /* Force the constant into memory and put the address of the
3794 memory location into scratch_reg. */
3795 xoperands
[0] = scratch_reg
;
3796 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3797 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3799 /* Now load the destination register. */
3800 emit_insn (gen_rtx_SET (mode
, operand0
,
3801 gen_rtx_MEM (mode
, scratch_reg
)));
3805 /* Now have insn-emit do whatever it normally does. */
3809 /* Split one or more DImode RTL references into pairs of SImode
3810 references. The RTL can be REG, offsettable MEM, integer constant, or
3811 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3812 split and "num" is its length. lo_half and hi_half are output arrays
3813 that parallel "operands". */
3816 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3820 rtx op
= operands
[num
];
3822 /* simplify_subreg refuses to split volatile memory addresses,
3823 but we still have to handle it. */
3824 if (GET_CODE (op
) == MEM
)
3826 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3827 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3831 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3832 GET_MODE (op
) == VOIDmode
3833 ? DImode
: GET_MODE (op
), 4);
3834 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3835 GET_MODE (op
) == VOIDmode
3836 ? DImode
: GET_MODE (op
), 0);
3841 /* Split X into a base and a constant offset, storing them in *BASE
3842 and *OFFSET respectively. */
3845 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3848 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3850 *offset
+= INTVAL (XEXP (x
, 1));
3856 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3857 instruction. STORE_P says whether the move is a load or store.
3859 If the instruction uses post-increment or pre-decrement addressing,
3860 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3861 adjustment. This adjustment will be made by the first element of
3862 PARALLEL, with the loads or stores starting at element 1. If the
3863 instruction does not use post-increment or pre-decrement addressing,
3864 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3865 start at element 0. */
3868 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3869 HOST_WIDE_INT automod_offset
, bool store_p
)
3871 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3872 HOST_WIDE_INT offset
, mem_offset
;
3874 enum reg_class rclass
;
3876 len
= XVECLEN (pattern
, 0);
3877 first
= (automod_base
!= NULL
);
3881 /* Stores must be pre-decrement and loads must be post-increment. */
3882 if (store_p
!= (automod_offset
< 0))
3885 /* Work out the base and offset for lowest memory location. */
3886 base
= automod_base
;
3887 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3891 /* Allow any valid base and offset in the first access. */
3898 for (i
= first
; i
< len
; i
++)
3900 /* We need a plain SET. */
3901 set
= XVECEXP (pattern
, 0, i
);
3902 if (GET_CODE (set
) != SET
)
3905 /* Check that we have a memory location... */
3906 mem
= XEXP (set
, !store_p
);
3907 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3910 /* ...with the right address. */
3913 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3914 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3915 There are no mode restrictions for 680x0 besides the
3916 automodification rules enforced above. */
3918 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3923 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3924 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3928 /* Check that we have a register of the required mode and class. */
3929 reg
= XEXP (set
, store_p
);
3931 || !HARD_REGISTER_P (reg
)
3932 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3937 /* The register must belong to RCLASS and have a higher number
3938 than the register in the previous SET. */
3939 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3940 || REGNO (last_reg
) >= REGNO (reg
))
3945 /* Work out which register class we need. */
3946 if (INT_REGNO_P (REGNO (reg
)))
3947 rclass
= GENERAL_REGS
;
3948 else if (FP_REGNO_P (REGNO (reg
)))
3955 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3958 /* If we have an automodification, check whether the final offset is OK. */
3959 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3962 /* Reject unprofitable cases. */
3963 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3969 /* Return the assembly code template for a movem or fmovem instruction
3970 whose pattern is given by PATTERN. Store the template's operands
3973 If the instruction uses post-increment or pre-decrement addressing,
3974 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3975 is true if this is a store instruction. */
3978 m68k_output_movem (rtx
*operands
, rtx pattern
,
3979 HOST_WIDE_INT automod_offset
, bool store_p
)
3984 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3986 first
= (automod_offset
!= 0);
3987 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3989 /* When using movem with pre-decrement addressing, register X + D0_REG
3990 is controlled by bit 15 - X. For all other addressing modes,
3991 register X + D0_REG is controlled by bit X. Confusingly, the
3992 register mask for fmovem is in the opposite order to that for
3996 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3997 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3998 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3999 if (automod_offset
< 0)
4001 if (FP_REGNO_P (regno
))
4002 mask
|= 1 << (regno
- FP0_REG
);
4004 mask
|= 1 << (15 - (regno
- D0_REG
));
4008 if (FP_REGNO_P (regno
))
4009 mask
|= 1 << (7 - (regno
- FP0_REG
));
4011 mask
|= 1 << (regno
- D0_REG
);
4016 if (automod_offset
== 0)
4017 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4018 else if (automod_offset
< 0)
4019 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4021 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4022 operands
[1] = GEN_INT (mask
);
4023 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4026 return "fmovem %1,%a0";
4028 return "fmovem %a0,%1";
4033 return "movem%.l %1,%a0";
4035 return "movem%.l %a0,%1";
4039 /* Return a REG that occurs in ADDR with coefficient 1.
4040 ADDR can be effectively incremented by incrementing REG. */
4043 find_addr_reg (rtx addr
)
4045 while (GET_CODE (addr
) == PLUS
)
4047 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4048 addr
= XEXP (addr
, 0);
4049 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4050 addr
= XEXP (addr
, 1);
4051 else if (CONSTANT_P (XEXP (addr
, 0)))
4052 addr
= XEXP (addr
, 1);
4053 else if (CONSTANT_P (XEXP (addr
, 1)))
4054 addr
= XEXP (addr
, 0);
4058 gcc_assert (GET_CODE (addr
) == REG
);
4062 /* Output assembler code to perform a 32-bit 3-operand add. */
4065 output_addsi3 (rtx
*operands
)
4067 if (! operands_match_p (operands
[0], operands
[1]))
4069 if (!ADDRESS_REG_P (operands
[1]))
4071 rtx tmp
= operands
[1];
4073 operands
[1] = operands
[2];
4077 /* These insns can result from reloads to access
4078 stack slots over 64k from the frame pointer. */
4079 if (GET_CODE (operands
[2]) == CONST_INT
4080 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4081 return "move%.l %2,%0\n\tadd%.l %1,%0";
4082 if (GET_CODE (operands
[2]) == REG
)
4083 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4084 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4086 if (GET_CODE (operands
[2]) == CONST_INT
)
4088 if (INTVAL (operands
[2]) > 0
4089 && INTVAL (operands
[2]) <= 8)
4090 return "addq%.l %2,%0";
4091 if (INTVAL (operands
[2]) < 0
4092 && INTVAL (operands
[2]) >= -8)
4094 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4095 return "subq%.l %2,%0";
4097 /* On the CPU32 it is faster to use two addql instructions to
4098 add a small integer (8 < N <= 16) to a register.
4099 Likewise for subql. */
4100 if (TUNE_CPU32
&& REG_P (operands
[0]))
4102 if (INTVAL (operands
[2]) > 8
4103 && INTVAL (operands
[2]) <= 16)
4105 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4106 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4108 if (INTVAL (operands
[2]) < -8
4109 && INTVAL (operands
[2]) >= -16)
4111 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4112 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4115 if (ADDRESS_REG_P (operands
[0])
4116 && INTVAL (operands
[2]) >= -0x8000
4117 && INTVAL (operands
[2]) < 0x8000)
4120 return "add%.w %2,%0";
4122 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4125 return "add%.l %2,%0";
4128 /* Store in cc_status the expressions that the condition codes will
4129 describe after execution of an instruction whose pattern is EXP.
4130 Do not alter them if the instruction would not alter the cc's. */
4132 /* On the 68000, all the insns to store in an address register fail to
4133 set the cc's. However, in some cases these instructions can make it
4134 possibly invalid to use the saved cc's. In those cases we clear out
4135 some or all of the saved cc's so they won't be used. */
4138 notice_update_cc (rtx exp
, rtx insn
)
4140 if (GET_CODE (exp
) == SET
)
4142 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4144 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4146 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4147 cc_status
.value1
= 0;
4148 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4149 cc_status
.value2
= 0;
4151 /* fmoves to memory or data registers do not set the condition
4152 codes. Normal moves _do_ set the condition codes, but not in
4153 a way that is appropriate for comparison with 0, because -0.0
4154 would be treated as a negative nonzero number. Note that it
4155 isn't appropriate to conditionalize this restriction on
4156 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4157 we care about the difference between -0.0 and +0.0. */
4158 else if (!FP_REG_P (SET_DEST (exp
))
4159 && SET_DEST (exp
) != cc0_rtx
4160 && (FP_REG_P (SET_SRC (exp
))
4161 || GET_CODE (SET_SRC (exp
)) == FIX
4162 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4164 /* A pair of move insns doesn't produce a useful overall cc. */
4165 else if (!FP_REG_P (SET_DEST (exp
))
4166 && !FP_REG_P (SET_SRC (exp
))
4167 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4168 && (GET_CODE (SET_SRC (exp
)) == REG
4169 || GET_CODE (SET_SRC (exp
)) == MEM
4170 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4172 else if (SET_DEST (exp
) != pc_rtx
)
4174 cc_status
.flags
= 0;
4175 cc_status
.value1
= SET_DEST (exp
);
4176 cc_status
.value2
= SET_SRC (exp
);
4179 else if (GET_CODE (exp
) == PARALLEL
4180 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4182 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4183 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4185 if (ADDRESS_REG_P (dest
))
4187 else if (dest
!= pc_rtx
)
4189 cc_status
.flags
= 0;
4190 cc_status
.value1
= dest
;
4191 cc_status
.value2
= src
;
4196 if (cc_status
.value2
!= 0
4197 && ADDRESS_REG_P (cc_status
.value2
)
4198 && GET_MODE (cc_status
.value2
) == QImode
)
4200 if (cc_status
.value2
!= 0)
4201 switch (GET_CODE (cc_status
.value2
))
4203 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4204 case ROTATE
: case ROTATERT
:
4205 /* These instructions always clear the overflow bit, and set
4206 the carry to the bit shifted out. */
4207 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4210 case PLUS
: case MINUS
: case MULT
:
4211 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4212 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4213 cc_status
.flags
|= CC_NO_OVERFLOW
;
4216 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4217 ends with a move insn moving r2 in r2's mode.
4218 Thus, the cc's are set for r2.
4219 This can set N bit spuriously. */
4220 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4225 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4227 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4228 cc_status
.value2
= 0;
4229 /* Check for PRE_DEC in dest modifying a register used in src. */
4230 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4231 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4233 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4235 cc_status
.value2
= 0;
4236 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4237 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4238 cc_status
.flags
= CC_IN_68881
;
4239 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4240 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4242 cc_status
.flags
= CC_IN_68881
;
4243 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4244 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4245 cc_status
.flags
|= CC_REVERSED
;
4250 output_move_const_double (rtx
*operands
)
4252 int code
= standard_68881_constant_p (operands
[1]);
4256 static char buf
[40];
4258 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4261 return "fmove%.d %1,%0";
4265 output_move_const_single (rtx
*operands
)
4267 int code
= standard_68881_constant_p (operands
[1]);
4271 static char buf
[40];
4273 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4276 return "fmove%.s %f1,%0";
4279 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4280 from the "fmovecr" instruction.
4281 The value, anded with 0xff, gives the code to use in fmovecr
4282 to get the desired constant. */
4284 /* This code has been fixed for cross-compilation. */
4286 static int inited_68881_table
= 0;
4288 static const char *const strings_68881
[7] = {
4298 static const int codes_68881
[7] = {
4308 REAL_VALUE_TYPE values_68881
[7];
4310 /* Set up values_68881 array by converting the decimal values
4311 strings_68881 to binary. */
4314 init_68881_table (void)
4321 for (i
= 0; i
< 7; i
++)
4325 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4326 values_68881
[i
] = r
;
4328 inited_68881_table
= 1;
4332 standard_68881_constant_p (rtx x
)
4337 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4338 used at all on those chips. */
4342 if (! inited_68881_table
)
4343 init_68881_table ();
4345 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4347 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4349 for (i
= 0; i
< 6; i
++)
4351 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4352 return (codes_68881
[i
]);
4355 if (GET_MODE (x
) == SFmode
)
4358 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4359 return (codes_68881
[6]);
4361 /* larger powers of ten in the constants ram are not used
4362 because they are not equal to a `double' C constant. */
4366 /* If X is a floating-point constant, return the logarithm of X base 2,
4367 or 0 if X is not a power of 2. */
4370 floating_exact_log2 (rtx x
)
4372 REAL_VALUE_TYPE r
, r1
;
4375 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4377 if (REAL_VALUES_LESS (r
, dconst1
))
4380 exp
= real_exponent (&r
);
4381 real_2expN (&r1
, exp
, DFmode
);
4382 if (REAL_VALUES_EQUAL (r1
, r
))
4388 /* A C compound statement to output to stdio stream STREAM the
4389 assembler syntax for an instruction operand X. X is an RTL
4392 CODE is a value that can be used to specify one of several ways
4393 of printing the operand. It is used when identical operands
4394 must be printed differently depending on the context. CODE
4395 comes from the `%' specification that was used to request
4396 printing of the operand. If the specification was just `%DIGIT'
4397 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4398 is the ASCII code for LTR.
4400 If X is a register, this macro should print the register's name.
4401 The names can be found in an array `reg_names' whose type is
4402 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4404 When the machine description has a specification `%PUNCT' (a `%'
4405 followed by a punctuation character), this macro is called with
4406 a null pointer for X and the punctuation character for CODE.
4408 The m68k specific codes are:
4410 '.' for dot needed in Motorola-style opcode names.
4411 '-' for an operand pushing on the stack:
4412 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4413 '+' for an operand pushing on the stack:
4414 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4415 '@' for a reference to the top word on the stack:
4416 sp@, (sp) or (%sp) depending on the style of syntax.
4417 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4418 but & in SGS syntax).
4419 '!' for the cc register (used in an `and to cc' insn).
4420 '$' for the letter `s' in an op code, but only on the 68040.
4421 '&' for the letter `d' in an op code, but only on the 68040.
4422 '/' for register prefix needed by longlong.h.
4423 '?' for m68k_library_id_string
4425 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4426 'd' to force memory addressing to be absolute, not relative.
4427 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4428 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4429 or print pair of registers as rx:ry.
4430 'p' print an address with @PLTPC attached, but only if the operand
4431 is not locally-bound. */
4434 print_operand (FILE *file
, rtx op
, int letter
)
4439 fprintf (file
, ".");
4441 else if (letter
== '#')
4442 asm_fprintf (file
, "%I");
4443 else if (letter
== '-')
4444 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4445 else if (letter
== '+')
4446 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4447 else if (letter
== '@')
4448 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4449 else if (letter
== '!')
4450 asm_fprintf (file
, "%Rfpcr");
4451 else if (letter
== '$')
4454 fprintf (file
, "s");
4456 else if (letter
== '&')
4459 fprintf (file
, "d");
4461 else if (letter
== '/')
4462 asm_fprintf (file
, "%R");
4463 else if (letter
== '?')
4464 asm_fprintf (file
, m68k_library_id_string
);
4465 else if (letter
== 'p')
4467 output_addr_const (file
, op
);
4468 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4469 fprintf (file
, "@PLTPC");
4471 else if (GET_CODE (op
) == REG
)
4474 /* Print out the second register name of a register pair.
4475 I.e., R (6) => 7. */
4476 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4478 fputs (M68K_REGNAME(REGNO (op
)), file
);
4480 else if (GET_CODE (op
) == MEM
)
4482 output_address (XEXP (op
, 0));
4483 if (letter
== 'd' && ! TARGET_68020
4484 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4485 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4486 && INTVAL (XEXP (op
, 0)) < 0x8000
4487 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4488 fprintf (file
, MOTOROLA
? ".l" : ":l");
4490 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4494 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4495 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4496 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4498 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4502 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4503 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4504 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4505 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4507 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4511 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4512 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4513 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4517 /* Use `print_operand_address' instead of `output_addr_const'
4518 to ensure that we print relevant PIC stuff. */
4519 asm_fprintf (file
, "%I");
4521 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4522 print_operand_address (file
, op
);
4524 output_addr_const (file
, op
);
4528 /* Return string for TLS relocation RELOC. */
4531 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4533 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4534 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4541 if (flag_pic
== 1 && TARGET_68020
)
4582 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4585 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4587 if (GET_CODE (x
) == UNSPEC
)
4589 switch (XINT (x
, 1))
4591 case UNSPEC_RELOC16
:
4592 case UNSPEC_RELOC32
:
4593 output_addr_const (file
, XVECEXP (x
, 0, 0));
4594 fputs (m68k_get_reloc_decoration
4595 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4606 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4609 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4611 gcc_assert (size
== 4);
4612 fputs ("\t.long\t", file
);
4613 output_addr_const (file
, x
);
4614 fputs ("@TLSLDO+0x8000", file
);
4617 /* In the name of slightly smaller debug output, and to cater to
4618 general assembler lossage, recognize various UNSPEC sequences
4619 and turn them back into a direct symbol reference. */
4622 m68k_delegitimize_address (rtx orig_x
)
4625 struct m68k_address addr
;
4628 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4633 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4636 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4637 || addr
.offset
== NULL_RTX
4638 || GET_CODE (addr
.offset
) != CONST
)
4641 unspec
= XEXP (addr
.offset
, 0);
4642 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4643 unspec
= XEXP (unspec
, 0);
4644 if (GET_CODE (unspec
) != UNSPEC
4645 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4646 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4648 x
= XVECEXP (unspec
, 0, 0);
4649 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4650 if (unspec
!= XEXP (addr
.offset
, 0))
4651 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4654 rtx idx
= addr
.index
;
4655 if (addr
.scale
!= 1)
4656 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4657 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4660 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4662 x
= replace_equiv_address_nv (orig_x
, x
);
4667 /* A C compound statement to output to stdio stream STREAM the
4668 assembler syntax for an instruction operand that is a memory
4669 reference whose address is ADDR. ADDR is an RTL expression.
4671 Note that this contains a kludge that knows that the only reason
4672 we have an address (plus (label_ref...) (reg...)) when not generating
4673 PIC code is in the insn before a tablejump, and we know that m68k.md
4674 generates a label LInnn: on such an insn.
4676 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4677 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4679 This routine is responsible for distinguishing between -fpic and -fPIC
4680 style relocations in an address. When generating -fpic code the
4681 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4682 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4685 print_operand_address (FILE *file
, rtx addr
)
4687 struct m68k_address address
;
4689 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4692 if (address
.code
== PRE_DEC
)
4693 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4694 M68K_REGNAME (REGNO (address
.base
)));
4695 else if (address
.code
== POST_INC
)
4696 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4697 M68K_REGNAME (REGNO (address
.base
)));
4698 else if (!address
.base
&& !address
.index
)
4700 /* A constant address. */
4701 gcc_assert (address
.offset
== addr
);
4702 if (GET_CODE (addr
) == CONST_INT
)
4704 /* (xxx).w or (xxx).l. */
4705 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4706 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4708 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4710 else if (TARGET_PCREL
)
4712 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4714 output_addr_const (file
, addr
);
4715 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4719 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4720 name ends in `.<letter>', as the last 2 characters can be
4721 mistaken as a size suffix. Put the name in parentheses. */
4722 if (GET_CODE (addr
) == SYMBOL_REF
4723 && strlen (XSTR (addr
, 0)) > 2
4724 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4727 output_addr_const (file
, addr
);
4731 output_addr_const (file
, addr
);
4738 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4739 label being accessed, otherwise it is -1. */
4740 labelno
= (address
.offset
4742 && GET_CODE (address
.offset
) == LABEL_REF
4743 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4747 /* Print the "offset(base" component. */
4749 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4753 output_addr_const (file
, address
.offset
);
4757 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4759 /* Print the ",index" component, if any. */
4764 fprintf (file
, "%s.%c",
4765 M68K_REGNAME (REGNO (address
.index
)),
4766 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4767 if (address
.scale
!= 1)
4768 fprintf (file
, "*%d", address
.scale
);
4772 else /* !MOTOROLA */
4774 if (!address
.offset
&& !address
.index
)
4775 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4778 /* Print the "base@(offset" component. */
4780 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4784 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4785 fprintf (file
, "@(");
4787 output_addr_const (file
, address
.offset
);
4789 /* Print the ",index" component, if any. */
4792 fprintf (file
, ",%s:%c",
4793 M68K_REGNAME (REGNO (address
.index
)),
4794 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4795 if (address
.scale
!= 1)
4796 fprintf (file
, ":%d", address
.scale
);
4804 /* Check for cases where a clr insns can be omitted from code using
4805 strict_low_part sets. For example, the second clrl here is not needed:
4806 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4808 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4809 insn we are checking for redundancy. TARGET is the register set by the
4813 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4816 rtx_insn
*p
= first_insn
;
4818 while ((p
= PREV_INSN (p
)))
4820 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4826 /* If it isn't an insn, then give up. */
4830 if (reg_set_p (target
, p
))
4832 rtx set
= single_set (p
);
4835 /* If it isn't an easy to recognize insn, then give up. */
4839 dest
= SET_DEST (set
);
4841 /* If this sets the entire target register to zero, then our
4842 first_insn is redundant. */
4843 if (rtx_equal_p (dest
, target
)
4844 && SET_SRC (set
) == const0_rtx
)
4846 else if (GET_CODE (dest
) == STRICT_LOW_PART
4847 && GET_CODE (XEXP (dest
, 0)) == REG
4848 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4849 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4850 <= GET_MODE_SIZE (mode
)))
4851 /* This is a strict low part set which modifies less than
4852 we are using, so it is safe. */
4862 /* Operand predicates for implementing asymmetric pc-relative addressing
4863 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4864 when used as a source operand, but not as a destination operand.
4866 We model this by restricting the meaning of the basic predicates
4867 (general_operand, memory_operand, etc) to forbid the use of this
4868 addressing mode, and then define the following predicates that permit
4869 this addressing mode. These predicates can then be used for the
4870 source operands of the appropriate instructions.
4872 n.b. While it is theoretically possible to change all machine patterns
4873 to use this addressing more where permitted by the architecture,
4874 it has only been implemented for "common" cases: SImode, HImode, and
4875 QImode operands, and only for the principle operations that would
4876 require this addressing mode: data movement and simple integer operations.
4878 In parallel with these new predicates, two new constraint letters
4879 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4880 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4881 In the pcrel case 's' is only valid in combination with 'a' registers.
4882 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4883 of how these constraints are used.
4885 The use of these predicates is strictly optional, though patterns that
4886 don't will cause an extra reload register to be allocated where one
4889 lea (abc:w,%pc),%a0 ; need to reload address
4890 moveq &1,%d1 ; since write to pc-relative space
4891 movel %d1,%a0@ ; is not allowed
4893 lea (abc:w,%pc),%a1 ; no need to reload address here
4894 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4896 For more info, consult tiemann@cygnus.com.
4899 All of the ugliness with predicates and constraints is due to the
4900 simple fact that the m68k does not allow a pc-relative addressing
4901 mode as a destination. gcc does not distinguish between source and
4902 destination addresses. Hence, if we claim that pc-relative address
4903 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4904 end up with invalid code. To get around this problem, we left
4905 pc-relative modes as invalid addresses, and then added special
4906 predicates and constraints to accept them.
4908 A cleaner way to handle this is to modify gcc to distinguish
4909 between source and destination addresses. We can then say that
4910 pc-relative is a valid source address but not a valid destination
4911 address, and hopefully avoid a lot of the predicate and constraint
4912 hackery. Unfortunately, this would be a pretty big change. It would
4913 be a useful change for a number of ports, but there aren't any current
4914 plans to undertake this.
4916 ***************************************************************************/
4920 output_andsi3 (rtx
*operands
)
4923 if (GET_CODE (operands
[2]) == CONST_INT
4924 && (INTVAL (operands
[2]) | 0xffff) == -1
4925 && (DATA_REG_P (operands
[0])
4926 || offsettable_memref_p (operands
[0]))
4927 && !TARGET_COLDFIRE
)
4929 if (GET_CODE (operands
[0]) != REG
)
4930 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4931 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4932 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4934 if (operands
[2] == const0_rtx
)
4936 return "and%.w %2,%0";
4938 if (GET_CODE (operands
[2]) == CONST_INT
4939 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4940 && (DATA_REG_P (operands
[0])
4941 || offsettable_memref_p (operands
[0])))
4943 if (DATA_REG_P (operands
[0]))
4944 operands
[1] = GEN_INT (logval
);
4947 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4948 operands
[1] = GEN_INT (logval
% 8);
4950 /* This does not set condition codes in a standard way. */
4952 return "bclr %1,%0";
4954 return "and%.l %2,%0";
4958 output_iorsi3 (rtx
*operands
)
4960 register int logval
;
4961 if (GET_CODE (operands
[2]) == CONST_INT
4962 && INTVAL (operands
[2]) >> 16 == 0
4963 && (DATA_REG_P (operands
[0])
4964 || offsettable_memref_p (operands
[0]))
4965 && !TARGET_COLDFIRE
)
4967 if (GET_CODE (operands
[0]) != REG
)
4968 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4969 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4971 if (INTVAL (operands
[2]) == 0xffff)
4972 return "mov%.w %2,%0";
4973 return "or%.w %2,%0";
4975 if (GET_CODE (operands
[2]) == CONST_INT
4976 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4977 && (DATA_REG_P (operands
[0])
4978 || offsettable_memref_p (operands
[0])))
4980 if (DATA_REG_P (operands
[0]))
4981 operands
[1] = GEN_INT (logval
);
4984 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4985 operands
[1] = GEN_INT (logval
% 8);
4988 return "bset %1,%0";
4990 return "or%.l %2,%0";
4994 output_xorsi3 (rtx
*operands
)
4996 register int logval
;
4997 if (GET_CODE (operands
[2]) == CONST_INT
4998 && INTVAL (operands
[2]) >> 16 == 0
4999 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5000 && !TARGET_COLDFIRE
)
5002 if (! DATA_REG_P (operands
[0]))
5003 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5004 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5006 if (INTVAL (operands
[2]) == 0xffff)
5008 return "eor%.w %2,%0";
5010 if (GET_CODE (operands
[2]) == CONST_INT
5011 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5012 && (DATA_REG_P (operands
[0])
5013 || offsettable_memref_p (operands
[0])))
5015 if (DATA_REG_P (operands
[0]))
5016 operands
[1] = GEN_INT (logval
);
5019 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5020 operands
[1] = GEN_INT (logval
% 8);
5023 return "bchg %1,%0";
5025 return "eor%.l %2,%0";
5028 /* Return the instruction that should be used for a call to address X,
5029 which is known to be in operand 0. */
5034 if (symbolic_operand (x
, VOIDmode
))
5035 return m68k_symbolic_call
;
5040 /* Likewise sibling calls. */
5043 output_sibcall (rtx x
)
5045 if (symbolic_operand (x
, VOIDmode
))
5046 return m68k_symbolic_jump
;
5052 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5053 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5056 rtx this_slot
, offset
, addr
, mem
, tmp
;
5059 /* Avoid clobbering the struct value reg by using the
5060 static chain reg as a temporary. */
5061 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5063 /* Pretend to be a post-reload pass while generating rtl. */
5064 reload_completed
= 1;
5066 /* The "this" pointer is stored at 4(%sp). */
5067 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5068 stack_pointer_rtx
, 4));
5070 /* Add DELTA to THIS. */
5073 /* Make the offset a legitimate operand for memory addition. */
5074 offset
= GEN_INT (delta
);
5075 if ((delta
< -8 || delta
> 8)
5076 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5078 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5079 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5081 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5082 copy_rtx (this_slot
), offset
));
5085 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5086 if (vcall_offset
!= 0)
5088 /* Set the static chain register to *THIS. */
5089 emit_move_insn (tmp
, this_slot
);
5090 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5092 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5093 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5094 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5096 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5100 /* Load the offset into %d0 and add it to THIS. */
5101 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5102 gen_rtx_MEM (Pmode
, addr
));
5103 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5104 copy_rtx (this_slot
),
5105 gen_rtx_REG (Pmode
, D0_REG
)));
5108 /* Jump to the target function. Use a sibcall if direct jumps are
5109 allowed, otherwise load the address into a register first. */
5110 mem
= DECL_RTL (function
);
5111 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5113 gcc_assert (flag_pic
);
5115 if (!TARGET_SEP_DATA
)
5117 /* Use the static chain register as a temporary (call-clobbered)
5118 GOT pointer for this function. We can use the static chain
5119 register because it isn't live on entry to the thunk. */
5120 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5121 emit_insn (gen_load_got (pic_offset_table_rtx
));
5123 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5124 mem
= replace_equiv_address (mem
, tmp
);
5126 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5127 SIBLING_CALL_P (insn
) = 1;
5129 /* Run just enough of rest_of_compilation. */
5130 insn
= get_insns ();
5131 split_all_insns_noflow ();
5132 final_start_function (insn
, file
, 1);
5133 final (insn
, file
, 1);
5134 final_end_function ();
5136 /* Clean up the vars set above. */
5137 reload_completed
= 0;
5139 /* Restore the original PIC register. */
5141 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5144 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5147 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5148 int incoming ATTRIBUTE_UNUSED
)
5150 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5153 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5155 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5156 unsigned int new_reg
)
5159 /* Interrupt functions can only use registers that have already been
5160 saved by the prologue, even if they would normally be
5163 if ((m68k_get_function_kind (current_function_decl
)
5164 == m68k_fk_interrupt_handler
)
5165 && !df_regs_ever_live_p (new_reg
))
5171 /* Value is true if hard register REGNO can hold a value of machine-mode
5172 MODE. On the 68000, we let the cpu registers can hold any mode, but
5173 restrict the 68881 registers to floating-point modes. */
5176 m68k_regno_mode_ok (int regno
, machine_mode mode
)
5178 if (DATA_REGNO_P (regno
))
5180 /* Data Registers, can hold aggregate if fits in. */
5181 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5184 else if (ADDRESS_REGNO_P (regno
))
5186 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5189 else if (FP_REGNO_P (regno
))
5191 /* FPU registers, hold float or complex float of long double or
5193 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5194 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5195 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5201 /* Implement SECONDARY_RELOAD_CLASS. */
5204 m68k_secondary_reload_class (enum reg_class rclass
,
5205 machine_mode mode
, rtx x
)
5209 regno
= true_regnum (x
);
5211 /* If one operand of a movqi is an address register, the other
5212 operand must be a general register or constant. Other types
5213 of operand must be reloaded through a data register. */
5214 if (GET_MODE_SIZE (mode
) == 1
5215 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5216 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5219 /* PC-relative addresses must be loaded into an address register first. */
5221 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5222 && symbolic_operand (x
, VOIDmode
))
5228 /* Implement PREFERRED_RELOAD_CLASS. */
5231 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5233 enum reg_class secondary_class
;
5235 /* If RCLASS might need a secondary reload, try restricting it to
5236 a class that doesn't. */
5237 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5238 if (secondary_class
!= NO_REGS
5239 && reg_class_subset_p (secondary_class
, rclass
))
5240 return secondary_class
;
5242 /* Prefer to use moveq for in-range constants. */
5243 if (GET_CODE (x
) == CONST_INT
5244 && reg_class_subset_p (DATA_REGS
, rclass
)
5245 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5248 /* ??? Do we really need this now? */
5249 if (GET_CODE (x
) == CONST_DOUBLE
5250 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5252 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5261 /* Return floating point values in a 68881 register. This makes 68881 code
5262 a little bit faster. It also makes -msoft-float code incompatible with
5263 hard-float code, so people have to be careful not to mix the two.
5264 For ColdFire it was decided the ABI incompatibility is undesirable.
5265 If there is need for a hard-float ABI it is probably worth doing it
5266 properly and also passing function arguments in FP registers. */
5268 m68k_libcall_value (machine_mode mode
)
5275 return gen_rtx_REG (mode
, FP0_REG
);
5281 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5284 /* Location in which function value is returned.
5285 NOTE: Due to differences in ABIs, don't call this function directly,
5286 use FUNCTION_VALUE instead. */
5288 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5292 mode
= TYPE_MODE (valtype
);
5298 return gen_rtx_REG (mode
, FP0_REG
);
5304 /* If the function returns a pointer, push that into %a0. */
5305 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5306 /* For compatibility with the large body of existing code which
5307 does not always properly declare external functions returning
5308 pointer types, the m68k/SVR4 convention is to copy the value
5309 returned for pointer functions from a0 to d0 in the function
5310 epilogue, so that callers that have neglected to properly
5311 declare the callee can still find the correct return value in
5313 return gen_rtx_PARALLEL
5316 gen_rtx_EXPR_LIST (VOIDmode
,
5317 gen_rtx_REG (mode
, A0_REG
),
5319 gen_rtx_EXPR_LIST (VOIDmode
,
5320 gen_rtx_REG (mode
, D0_REG
),
5322 else if (POINTER_TYPE_P (valtype
))
5323 return gen_rtx_REG (mode
, A0_REG
);
5325 return gen_rtx_REG (mode
, D0_REG
);
5328 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5329 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5331 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5333 machine_mode mode
= TYPE_MODE (type
);
5335 if (mode
== BLKmode
)
5338 /* If TYPE's known alignment is less than the alignment of MODE that
5339 would contain the structure, then return in memory. We need to
5340 do so to maintain the compatibility between code compiled with
5341 -mstrict-align and that compiled with -mno-strict-align. */
5342 if (AGGREGATE_TYPE_P (type
)
5343 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5350 /* CPU to schedule the program for. */
5351 enum attr_cpu m68k_sched_cpu
;
5353 /* MAC to schedule the program for. */
5354 enum attr_mac m68k_sched_mac
;
5362 /* Integer register. */
5368 /* Implicit mem reference (e.g. stack). */
5371 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5374 /* Memory with offset but without indexing. EA mode 5. */
5377 /* Memory with indexing. EA mode 6. */
5380 /* Memory referenced by absolute address. EA mode 7. */
5383 /* Immediate operand that doesn't require extension word. */
5386 /* Immediate 16 bit operand. */
5389 /* Immediate 32 bit operand. */
5393 /* Return type of memory ADDR_RTX refers to. */
5394 static enum attr_op_type
5395 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5397 struct m68k_address address
;
5399 if (symbolic_operand (addr_rtx
, VOIDmode
))
5400 return OP_TYPE_MEM7
;
5402 if (!m68k_decompose_address (mode
, addr_rtx
,
5403 reload_completed
, &address
))
5405 gcc_assert (!reload_completed
);
5406 /* Reload will likely fix the address to be in the register. */
5407 return OP_TYPE_MEM234
;
5410 if (address
.scale
!= 0)
5411 return OP_TYPE_MEM6
;
5413 if (address
.base
!= NULL_RTX
)
5415 if (address
.offset
== NULL_RTX
)
5416 return OP_TYPE_MEM234
;
5418 return OP_TYPE_MEM5
;
5421 gcc_assert (address
.offset
!= NULL_RTX
);
5423 return OP_TYPE_MEM7
;
5426 /* Return X or Y (depending on OPX_P) operand of INSN. */
5428 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5432 if (recog_memoized (insn
) < 0)
5435 extract_constrain_insn_cached (insn
);
5438 i
= get_attr_opx (insn
);
5440 i
= get_attr_opy (insn
);
5442 if (i
>= recog_data
.n_operands
)
5445 return recog_data
.operand
[i
];
5448 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5449 If ADDRESS_P is true, return type of memory location operand refers to. */
5450 static enum attr_op_type
5451 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5455 op
= sched_get_operand (insn
, opx_p
);
5459 gcc_assert (!reload_completed
);
5464 return sched_address_type (QImode
, op
);
5466 if (memory_operand (op
, VOIDmode
))
5467 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5469 if (register_operand (op
, VOIDmode
))
5471 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5472 || (reload_completed
&& FP_REG_P (op
)))
5478 if (GET_CODE (op
) == CONST_INT
)
5484 /* Check for quick constants. */
5485 switch (get_attr_type (insn
))
5488 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5489 return OP_TYPE_IMM_Q
;
5491 gcc_assert (!reload_completed
);
5495 if (USE_MOVQ (ival
))
5496 return OP_TYPE_IMM_Q
;
5498 gcc_assert (!reload_completed
);
5502 if (valid_mov3q_const (ival
))
5503 return OP_TYPE_IMM_Q
;
5505 gcc_assert (!reload_completed
);
5512 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5513 return OP_TYPE_IMM_W
;
5515 return OP_TYPE_IMM_L
;
5518 if (GET_CODE (op
) == CONST_DOUBLE
)
5520 switch (GET_MODE (op
))
5523 return OP_TYPE_IMM_W
;
5527 return OP_TYPE_IMM_L
;
5534 if (GET_CODE (op
) == CONST
5535 || symbolic_operand (op
, VOIDmode
)
5538 switch (GET_MODE (op
))
5541 return OP_TYPE_IMM_Q
;
5544 return OP_TYPE_IMM_W
;
5547 return OP_TYPE_IMM_L
;
5550 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5552 return OP_TYPE_IMM_W
;
5554 return OP_TYPE_IMM_L
;
5558 gcc_assert (!reload_completed
);
5560 if (FLOAT_MODE_P (GET_MODE (op
)))
5566 /* Implement opx_type attribute.
5567 Return type of INSN's operand X.
5568 If ADDRESS_P is true, return type of memory location operand refers to. */
5570 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5572 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5578 return OPX_TYPE_FPN
;
5581 return OPX_TYPE_MEM1
;
5583 case OP_TYPE_MEM234
:
5584 return OPX_TYPE_MEM234
;
5587 return OPX_TYPE_MEM5
;
5590 return OPX_TYPE_MEM6
;
5593 return OPX_TYPE_MEM7
;
5596 return OPX_TYPE_IMM_Q
;
5599 return OPX_TYPE_IMM_W
;
5602 return OPX_TYPE_IMM_L
;
5609 /* Implement opy_type attribute.
5610 Return type of INSN's operand Y.
5611 If ADDRESS_P is true, return type of memory location operand refers to. */
5613 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5615 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5621 return OPY_TYPE_FPN
;
5624 return OPY_TYPE_MEM1
;
5626 case OP_TYPE_MEM234
:
5627 return OPY_TYPE_MEM234
;
5630 return OPY_TYPE_MEM5
;
5633 return OPY_TYPE_MEM6
;
5636 return OPY_TYPE_MEM7
;
5639 return OPY_TYPE_IMM_Q
;
5642 return OPY_TYPE_IMM_W
;
5645 return OPY_TYPE_IMM_L
;
5652 /* Return size of INSN as int. */
5654 sched_get_attr_size_int (rtx_insn
*insn
)
5658 switch (get_attr_type (insn
))
5661 /* There should be no references to m68k_sched_attr_size for 'ignore'
5675 switch (get_attr_opx_type (insn
))
5681 case OPX_TYPE_MEM234
:
5682 case OPY_TYPE_IMM_Q
:
5687 /* Here we assume that most absolute references are short. */
5689 case OPY_TYPE_IMM_W
:
5693 case OPY_TYPE_IMM_L
:
5701 switch (get_attr_opy_type (insn
))
5707 case OPY_TYPE_MEM234
:
5708 case OPY_TYPE_IMM_Q
:
5713 /* Here we assume that most absolute references are short. */
5715 case OPY_TYPE_IMM_W
:
5719 case OPY_TYPE_IMM_L
:
5729 gcc_assert (!reload_completed
);
5737 /* Return size of INSN as attribute enum value. */
5739 m68k_sched_attr_size (rtx_insn
*insn
)
5741 switch (sched_get_attr_size_int (insn
))
5757 /* Return operand X or Y (depending on OPX_P) of INSN,
5758 if it is a MEM, or NULL overwise. */
5759 static enum attr_op_type
5760 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5764 switch (get_attr_opx_type (insn
))
5769 case OPX_TYPE_IMM_Q
:
5770 case OPX_TYPE_IMM_W
:
5771 case OPX_TYPE_IMM_L
:
5775 case OPX_TYPE_MEM234
:
5778 return OP_TYPE_MEM1
;
5781 return OP_TYPE_MEM6
;
5789 switch (get_attr_opy_type (insn
))
5794 case OPY_TYPE_IMM_Q
:
5795 case OPY_TYPE_IMM_W
:
5796 case OPY_TYPE_IMM_L
:
5800 case OPY_TYPE_MEM234
:
5803 return OP_TYPE_MEM1
;
5806 return OP_TYPE_MEM6
;
5814 /* Implement op_mem attribute. */
5816 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5818 enum attr_op_type opx
;
5819 enum attr_op_type opy
;
5821 opx
= sched_get_opxy_mem_type (insn
, true);
5822 opy
= sched_get_opxy_mem_type (insn
, false);
5824 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5827 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5829 switch (get_attr_opx_access (insn
))
5845 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5847 switch (get_attr_opx_access (insn
))
5863 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5866 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5868 switch (get_attr_opx_access (insn
))
5874 gcc_assert (!reload_completed
);
5879 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5881 switch (get_attr_opx_access (insn
))
5887 gcc_assert (!reload_completed
);
5892 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5895 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5897 switch (get_attr_opx_access (insn
))
5903 gcc_assert (!reload_completed
);
5908 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5909 gcc_assert (!reload_completed
);
5913 /* Data for ColdFire V4 index bypass.
5914 Producer modifies register that is used as index in consumer with
5918 /* Producer instruction. */
5921 /* Consumer instruction. */
5924 /* Scale of indexed memory access within consumer.
5925 Or zero if bypass should not be effective at the moment. */
5927 } sched_cfv4_bypass_data
;
5929 /* An empty state that is used in m68k_sched_adjust_cost. */
5930 static state_t sched_adjust_cost_state
;
5932 /* Implement adjust_cost scheduler hook.
5933 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5935 m68k_sched_adjust_cost (rtx_insn
*insn
, rtx link ATTRIBUTE_UNUSED
,
5936 rtx_insn
*def_insn
, int cost
)
5940 if (recog_memoized (def_insn
) < 0
5941 || recog_memoized (insn
) < 0)
5944 if (sched_cfv4_bypass_data
.scale
== 1)
5945 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5947 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5948 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5949 that the data in sched_cfv4_bypass_data is up to date. */
5950 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5951 && sched_cfv4_bypass_data
.con
== insn
);
5956 sched_cfv4_bypass_data
.pro
= NULL
;
5957 sched_cfv4_bypass_data
.con
= NULL
;
5958 sched_cfv4_bypass_data
.scale
= 0;
5961 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5962 && sched_cfv4_bypass_data
.con
== NULL
5963 && sched_cfv4_bypass_data
.scale
== 0);
5965 /* Don't try to issue INSN earlier than DFA permits.
5966 This is especially useful for instructions that write to memory,
5967 as their true dependence (default) latency is better to be set to 0
5968 to workaround alias analysis limitations.
5969 This is, in fact, a machine independent tweak, so, probably,
5970 it should be moved to haifa-sched.c: insn_cost (). */
5971 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5978 /* Return maximal number of insns that can be scheduled on a single cycle. */
5980 m68k_sched_issue_rate (void)
5982 switch (m68k_sched_cpu
)
5998 /* Maximal length of instruction for current CPU.
5999 E.g. it is 3 for any ColdFire core. */
6000 static int max_insn_size
;
6002 /* Data to model instruction buffer of CPU. */
6005 /* True if instruction buffer model is modeled for current CPU. */
6008 /* Size of the instruction buffer in words. */
6011 /* Number of filled words in the instruction buffer. */
6014 /* Additional information about instruction buffer for CPUs that have
6015 a buffer of instruction records, rather then a plain buffer
6016 of instruction words. */
6017 struct _sched_ib_records
6019 /* Size of buffer in records. */
6022 /* Array to hold data on adjustements made to the size of the buffer. */
6025 /* Index of the above array. */
6029 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6033 static struct _sched_ib sched_ib
;
6035 /* ID of memory unit. */
6036 static int sched_mem_unit_code
;
6038 /* Implementation of the targetm.sched.variable_issue () hook.
6039 It is called after INSN was issued. It returns the number of insns
6040 that can possibly get scheduled on the current cycle.
6041 It is used here to determine the effect of INSN on the instruction
6044 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6045 int sched_verbose ATTRIBUTE_UNUSED
,
6046 rtx_insn
*insn
, int can_issue_more
)
6050 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6052 switch (m68k_sched_cpu
)
6056 insn_size
= sched_get_attr_size_int (insn
);
6060 insn_size
= sched_get_attr_size_int (insn
);
6062 /* ColdFire V3 and V4 cores have instruction buffers that can
6063 accumulate up to 8 instructions regardless of instructions'
6064 sizes. So we should take care not to "prefetch" 24 one-word
6065 or 12 two-words instructions.
6066 To model this behavior we temporarily decrease size of the
6067 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6071 adjust
= max_insn_size
- insn_size
;
6072 sched_ib
.size
-= adjust
;
6074 if (sched_ib
.filled
> sched_ib
.size
)
6075 sched_ib
.filled
= sched_ib
.size
;
6077 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6080 ++sched_ib
.records
.adjust_index
;
6081 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6082 sched_ib
.records
.adjust_index
= 0;
6084 /* Undo adjustement we did 7 instructions ago. */
6086 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6091 gcc_assert (!sched_ib
.enabled_p
);
6099 if (insn_size
> sched_ib
.filled
)
6100 /* Scheduling for register pressure does not always take DFA into
6101 account. Workaround instruction buffer not being filled enough. */
6103 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6104 insn_size
= sched_ib
.filled
;
6109 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6110 || asm_noperands (PATTERN (insn
)) >= 0)
6111 insn_size
= sched_ib
.filled
;
6115 sched_ib
.filled
-= insn_size
;
6117 return can_issue_more
;
6120 /* Return how many instructions should scheduler lookahead to choose the
6123 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6125 return m68k_sched_issue_rate () - 1;
6128 /* Implementation of targetm.sched.init_global () hook.
6129 It is invoked once per scheduling pass and is used here
6130 to initialize scheduler constants. */
6132 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6133 int sched_verbose ATTRIBUTE_UNUSED
,
6134 int n_insns ATTRIBUTE_UNUSED
)
6136 #ifdef ENABLE_CHECKING
6137 /* Check that all instructions have DFA reservations and
6138 that all instructions can be issued from a clean state. */
6143 state
= alloca (state_size ());
6145 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6147 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6149 gcc_assert (insn_has_dfa_reservation_p (insn
));
6151 state_reset (state
);
6152 if (state_transition (state
, insn
) >= 0)
6159 /* Setup target cpu. */
6161 /* ColdFire V4 has a set of features to keep its instruction buffer full
6162 (e.g., a separate memory bus for instructions) and, hence, we do not model
6163 buffer for this CPU. */
6164 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6166 switch (m68k_sched_cpu
)
6169 sched_ib
.filled
= 0;
6176 sched_ib
.records
.n_insns
= 0;
6177 sched_ib
.records
.adjust
= NULL
;
6182 sched_ib
.records
.n_insns
= 8;
6183 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6190 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6192 sched_adjust_cost_state
= xmalloc (state_size ());
6193 state_reset (sched_adjust_cost_state
);
6196 emit_insn (gen_ib ());
6197 sched_ib
.insn
= get_insns ();
6201 /* Scheduling pass is now finished. Free/reset static variables. */
6203 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6204 int verbose ATTRIBUTE_UNUSED
)
6206 sched_ib
.insn
= NULL
;
6208 free (sched_adjust_cost_state
);
6209 sched_adjust_cost_state
= NULL
;
6211 sched_mem_unit_code
= 0;
6213 free (sched_ib
.records
.adjust
);
6214 sched_ib
.records
.adjust
= NULL
;
6215 sched_ib
.records
.n_insns
= 0;
6219 /* Implementation of targetm.sched.init () hook.
6220 It is invoked each time scheduler starts on the new block (basic block or
6221 extended basic block). */
6223 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6224 int sched_verbose ATTRIBUTE_UNUSED
,
6225 int n_insns ATTRIBUTE_UNUSED
)
6227 switch (m68k_sched_cpu
)
6235 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6237 memset (sched_ib
.records
.adjust
, 0,
6238 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6239 sched_ib
.records
.adjust_index
= 0;
6243 gcc_assert (!sched_ib
.enabled_p
);
6251 if (sched_ib
.enabled_p
)
6252 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6253 the first cycle. Workaround that. */
6254 sched_ib
.filled
= -2;
6257 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6258 It is invoked just before current cycle finishes and is used here
6259 to track if instruction buffer got its two words this cycle. */
6261 m68k_sched_dfa_pre_advance_cycle (void)
6263 if (!sched_ib
.enabled_p
)
6266 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6268 sched_ib
.filled
+= 2;
6270 if (sched_ib
.filled
> sched_ib
.size
)
6271 sched_ib
.filled
= sched_ib
.size
;
6275 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6276 It is invoked just after new cycle begins and is used here
6277 to setup number of filled words in the instruction buffer so that
6278 instructions which won't have all their words prefetched would be
6279 stalled for a cycle. */
6281 m68k_sched_dfa_post_advance_cycle (void)
6285 if (!sched_ib
.enabled_p
)
6288 /* Setup number of prefetched instruction words in the instruction
6290 i
= max_insn_size
- sched_ib
.filled
;
6294 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6295 /* Pick up scheduler state. */
6300 /* Return X or Y (depending on OPX_P) operand of INSN,
6301 if it is an integer register, or NULL overwise. */
6303 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6309 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6311 op
= sched_get_operand (insn
, true);
6312 gcc_assert (op
!= NULL
);
6314 if (!reload_completed
&& !REG_P (op
))
6320 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6322 op
= sched_get_operand (insn
, false);
6323 gcc_assert (op
!= NULL
);
6325 if (!reload_completed
&& !REG_P (op
))
6333 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6336 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6338 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6349 /* Return X or Y (depending on OPX_P) operand of INSN,
6350 if it is a MEM, or NULL overwise. */
6352 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6372 if (opy_p
&& sched_mem_operand_p (insn
, false))
6373 return sched_get_operand (insn
, false);
6375 if (opx_p
&& sched_mem_operand_p (insn
, true))
6376 return sched_get_operand (insn
, true);
6382 /* Return non-zero if PRO modifies register used as part of
6385 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6390 pro_x
= sched_get_reg_operand (pro
, true);
6394 con_mem_read
= sched_get_mem_operand (con
, true, false);
6395 gcc_assert (con_mem_read
!= NULL
);
6397 if (reg_mentioned_p (pro_x
, con_mem_read
))
6403 /* Helper function for m68k_sched_indexed_address_bypass_p.
6404 if PRO modifies register used as index in CON,
6405 return scale of indexed memory access in CON. Return zero overwise. */
6407 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6411 struct m68k_address address
;
6413 reg
= sched_get_reg_operand (pro
, true);
6417 mem
= sched_get_mem_operand (con
, true, false);
6418 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6420 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6424 if (REGNO (reg
) == REGNO (address
.index
))
6426 gcc_assert (address
.scale
!= 0);
6427 return address
.scale
;
6433 /* Return non-zero if PRO modifies register used
6434 as index with scale 2 or 4 in CON. */
6436 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6438 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6439 && sched_cfv4_bypass_data
.con
== NULL
6440 && sched_cfv4_bypass_data
.scale
== 0);
6442 switch (sched_get_indexed_address_scale (pro
, con
))
6445 /* We can't have a variable latency bypass, so
6446 remember to adjust the insn cost in adjust_cost hook. */
6447 sched_cfv4_bypass_data
.pro
= pro
;
6448 sched_cfv4_bypass_data
.con
= con
;
6449 sched_cfv4_bypass_data
.scale
= 1;
6461 /* We generate a two-instructions program at M_TRAMP :
6462 movea.l &CHAIN_VALUE,%a0
6464 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6467 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6469 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6472 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6474 mem
= adjust_address (m_tramp
, HImode
, 0);
6475 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6476 mem
= adjust_address (m_tramp
, SImode
, 2);
6477 emit_move_insn (mem
, chain_value
);
6479 mem
= adjust_address (m_tramp
, HImode
, 6);
6480 emit_move_insn (mem
, GEN_INT(0x4EF9));
6481 mem
= adjust_address (m_tramp
, SImode
, 8);
6482 emit_move_insn (mem
, fnaddr
);
6484 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6487 /* On the 68000, the RTS insn cannot pop anything.
6488 On the 68010, the RTD insn may be used to pop them if the number
6489 of args is fixed, but if the number is variable then the caller
6490 must pop them all. RTD can't be used for library calls now
6491 because the library is compiled with the Unix compiler.
6492 Use of RTD is a selectable option, since it is incompatible with
6493 standard Unix calling sequences. If the option is not selected,
6494 the caller must always pop the args. */
6497 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6501 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6502 && (!stdarg_p (funtype
)))
6506 /* Make sure everything's fine if we *don't* have a given processor.
6507 This assumes that putting a register in fixed_regs will keep the
6508 compiler's mitts completely off it. We don't bother to zero it out
6509 of register classes. */
6512 m68k_conditional_register_usage (void)
6516 if (!TARGET_HARD_FLOAT
)
6518 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6519 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6520 if (TEST_HARD_REG_BIT (x
, i
))
6521 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6524 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6528 m68k_init_sync_libfuncs (void)
6530 init_sync_libfuncs (UNITS_PER_WORD
);
6533 /* Implements EPILOGUE_USES. All registers are live on exit from an
6534 interrupt routine. */
6536 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6538 return (reload_completed
6539 && (m68k_get_function_kind (current_function_decl
)
6540 == m68k_fk_interrupt_handler
));
6543 #include "gt-m68k.h"