1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
29 #include "fold-const.h"
31 #include "stor-layout.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
39 #include "diagnostic-core.h"
55 #include "cfgcleanup.h"
56 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
57 #include "sched-int.h"
58 #include "insn-codes.h"
64 /* This file should be included last. */
65 #include "target-def.h"
67 enum reg_class regno_reg_class
[] =
69 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
70 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
71 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
72 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
73 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
74 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
79 /* The minimum number of integer registers that we want to save with the
80 movem instruction. Using two movel instructions instead of a single
81 moveml is about 15% faster for the 68020 and 68030 at no expense in
83 #define MIN_MOVEM_REGS 3
85 /* The minimum number of floating point registers that we want to save
86 with the fmovem instruction. */
87 #define MIN_FMOVEM_REGS 1
89 /* Structure describing stack frame layout. */
92 /* Stack pointer to frame pointer offset. */
95 /* Offset of FPU registers. */
96 HOST_WIDE_INT foffset
;
98 /* Frame size in bytes (rounded up). */
101 /* Data and address register. */
103 unsigned int reg_mask
;
107 unsigned int fpu_mask
;
109 /* Offsets relative to ARG_POINTER. */
110 HOST_WIDE_INT frame_pointer_offset
;
111 HOST_WIDE_INT stack_pointer_offset
;
113 /* Function which the above information refers to. */
117 /* Current frame information calculated by m68k_compute_frame_layout(). */
118 static struct m68k_frame current_frame
;
120 /* Structure describing an m68k address.
122 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
123 with null fields evaluating to 0. Here:
125 - BASE satisfies m68k_legitimate_base_reg_p
126 - INDEX satisfies m68k_legitimate_index_reg_p
127 - OFFSET satisfies m68k_legitimate_constant_address_p
129 INDEX is either HImode or SImode. The other fields are SImode.
131 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
132 the address is (BASE)+. */
133 struct m68k_address
{
141 static int m68k_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
143 static int m68k_sched_issue_rate (void);
144 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
145 static void m68k_sched_md_init_global (FILE *, int, int);
146 static void m68k_sched_md_finish_global (FILE *, int);
147 static void m68k_sched_md_init (FILE *, int, int);
148 static void m68k_sched_dfa_pre_advance_cycle (void);
149 static void m68k_sched_dfa_post_advance_cycle (void);
150 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
152 static bool m68k_can_eliminate (const int, const int);
153 static void m68k_conditional_register_usage (void);
154 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
155 static void m68k_option_override (void);
156 static void m68k_override_options_after_change (void);
157 static rtx
find_addr_reg (rtx
);
158 static const char *singlemove_string (rtx
*);
159 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
160 HOST_WIDE_INT
, tree
);
161 static rtx
m68k_struct_value_rtx (tree
, int);
162 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
163 tree args
, int flags
,
165 static void m68k_compute_frame_layout (void);
166 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
167 static bool m68k_ok_for_sibcall_p (tree
, tree
);
168 static bool m68k_tls_symbol_p (rtx
);
169 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
170 static bool m68k_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
171 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
172 static bool m68k_return_in_memory (const_tree
, const_tree
);
174 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
175 static void m68k_trampoline_init (rtx
, tree
, rtx
);
176 static int m68k_return_pops_args (tree
, tree
, int);
177 static rtx
m68k_delegitimize_address (rtx
);
178 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
180 static rtx
m68k_function_arg (cumulative_args_t
, machine_mode
,
182 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
183 static bool m68k_output_addr_const_extra (FILE *, rtx
);
184 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
186 /* Initialize the GCC target structure. */
188 #if INT_OP_GROUP == INT_OP_DOT_WORD
189 #undef TARGET_ASM_ALIGNED_HI_OP
190 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
193 #if INT_OP_GROUP == INT_OP_NO_DOT
194 #undef TARGET_ASM_BYTE_OP
195 #define TARGET_ASM_BYTE_OP "\tbyte\t"
196 #undef TARGET_ASM_ALIGNED_HI_OP
197 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
198 #undef TARGET_ASM_ALIGNED_SI_OP
199 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
202 #if INT_OP_GROUP == INT_OP_DC
203 #undef TARGET_ASM_BYTE_OP
204 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
205 #undef TARGET_ASM_ALIGNED_HI_OP
206 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
207 #undef TARGET_ASM_ALIGNED_SI_OP
208 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
211 #undef TARGET_ASM_UNALIGNED_HI_OP
212 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
213 #undef TARGET_ASM_UNALIGNED_SI_OP
214 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
216 #undef TARGET_ASM_OUTPUT_MI_THUNK
217 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
218 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
219 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
221 #undef TARGET_ASM_FILE_START_APP_OFF
222 #define TARGET_ASM_FILE_START_APP_OFF true
224 #undef TARGET_LEGITIMIZE_ADDRESS
225 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
227 #undef TARGET_SCHED_ADJUST_COST
228 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
230 #undef TARGET_SCHED_ISSUE_RATE
231 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
233 #undef TARGET_SCHED_VARIABLE_ISSUE
234 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
236 #undef TARGET_SCHED_INIT_GLOBAL
237 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
239 #undef TARGET_SCHED_FINISH_GLOBAL
240 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
242 #undef TARGET_SCHED_INIT
243 #define TARGET_SCHED_INIT m68k_sched_md_init
245 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
246 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
248 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
249 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
251 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
252 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
253 m68k_sched_first_cycle_multipass_dfa_lookahead
255 #undef TARGET_OPTION_OVERRIDE
256 #define TARGET_OPTION_OVERRIDE m68k_option_override
258 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
259 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
261 #undef TARGET_RTX_COSTS
262 #define TARGET_RTX_COSTS m68k_rtx_costs
264 #undef TARGET_ATTRIBUTE_TABLE
265 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
267 #undef TARGET_PROMOTE_PROTOTYPES
268 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
270 #undef TARGET_STRUCT_VALUE_RTX
271 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
273 #undef TARGET_CANNOT_FORCE_CONST_MEM
274 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
276 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
277 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
279 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
280 #undef TARGET_RETURN_IN_MEMORY
281 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
285 #undef TARGET_HAVE_TLS
286 #define TARGET_HAVE_TLS (true)
288 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
289 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
293 #define TARGET_LRA_P hook_bool_void_false
295 #undef TARGET_LEGITIMATE_ADDRESS_P
296 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
298 #undef TARGET_CAN_ELIMINATE
299 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
301 #undef TARGET_CONDITIONAL_REGISTER_USAGE
302 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
304 #undef TARGET_TRAMPOLINE_INIT
305 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
307 #undef TARGET_RETURN_POPS_ARGS
308 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
310 #undef TARGET_DELEGITIMIZE_ADDRESS
311 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
313 #undef TARGET_FUNCTION_ARG
314 #define TARGET_FUNCTION_ARG m68k_function_arg
316 #undef TARGET_FUNCTION_ARG_ADVANCE
317 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
319 #undef TARGET_LEGITIMATE_CONSTANT_P
320 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
322 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
323 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
325 /* The value stored by TAS. */
326 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
327 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
329 static const struct attribute_spec m68k_attribute_table
[] =
331 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
332 affects_type_identity } */
333 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
335 { "interrupt_handler", 0, 0, true, false, false,
336 m68k_handle_fndecl_attribute
, false },
337 { "interrupt_thread", 0, 0, true, false, false,
338 m68k_handle_fndecl_attribute
, false },
339 { NULL
, 0, 0, false, false, false, NULL
, false }
342 struct gcc_target targetm
= TARGET_INITIALIZER
;
344 /* Base flags for 68k ISAs. */
345 #define FL_FOR_isa_00 FL_ISA_68000
346 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
347 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
348 generated 68881 code for 68020 and 68030 targets unless explicitly told
350 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
351 | FL_BITFIELD | FL_68881 | FL_CAS)
352 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
353 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
355 /* Base flags for ColdFire ISAs. */
356 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
357 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
358 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
359 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
360 /* ISA_C is not upwardly compatible with ISA_B. */
361 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
365 /* Traditional 68000 instruction sets. */
371 /* ColdFire instruction set variants. */
379 /* Information about one of the -march, -mcpu or -mtune arguments. */
380 struct m68k_target_selection
382 /* The argument being described. */
385 /* For -mcpu, this is the device selected by the option.
386 For -mtune and -march, it is a representative device
387 for the microarchitecture or ISA respectively. */
388 enum target_device device
;
390 /* The M68K_DEVICE fields associated with DEVICE. See the comment
391 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
393 enum uarch_type microarch
;
398 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
399 static const struct m68k_target_selection all_devices
[] =
401 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
402 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
403 #include "m68k-devices.def"
405 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
408 /* A list of all ISAs, mapping each one to a representative device.
409 Used for -march selection. */
410 static const struct m68k_target_selection all_isas
[] =
412 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
413 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
414 #include "m68k-isas.def"
416 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
419 /* A list of all microarchitectures, mapping each one to a representative
420 device. Used for -mtune selection. */
421 static const struct m68k_target_selection all_microarchs
[] =
423 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
424 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
425 #include "m68k-microarchs.def"
426 #undef M68K_MICROARCH
427 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
430 /* The entries associated with the -mcpu, -march and -mtune settings,
431 or null for options that have not been used. */
432 const struct m68k_target_selection
*m68k_cpu_entry
;
433 const struct m68k_target_selection
*m68k_arch_entry
;
434 const struct m68k_target_selection
*m68k_tune_entry
;
436 /* Which CPU we are generating code for. */
437 enum target_device m68k_cpu
;
439 /* Which microarchitecture to tune for. */
440 enum uarch_type m68k_tune
;
442 /* Which FPU to use. */
443 enum fpu_type m68k_fpu
;
445 /* The set of FL_* flags that apply to the target processor. */
446 unsigned int m68k_cpu_flags
;
448 /* The set of FL_* flags that apply to the processor to be tuned for. */
449 unsigned int m68k_tune_flags
;
451 /* Asm templates for calling or jumping to an arbitrary symbolic address,
452 or NULL if such calls or jumps are not supported. The address is held
454 const char *m68k_symbolic_call
;
455 const char *m68k_symbolic_jump
;
457 /* Enum variable that corresponds to m68k_symbolic_call values. */
458 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
461 /* Implement TARGET_OPTION_OVERRIDE. */
464 m68k_option_override (void)
466 const struct m68k_target_selection
*entry
;
467 unsigned long target_mask
;
469 if (global_options_set
.x_m68k_arch_option
)
470 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
472 if (global_options_set
.x_m68k_cpu_option
)
473 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
475 if (global_options_set
.x_m68k_tune_option
)
476 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
484 -march=ARCH should generate code that runs any processor
485 implementing architecture ARCH. -mcpu=CPU should override -march
486 and should generate code that runs on processor CPU, making free
487 use of any instructions that CPU understands. -mtune=UARCH applies
488 on top of -mcpu or -march and optimizes the code for UARCH. It does
489 not change the target architecture. */
492 /* Complain if the -march setting is for a different microarchitecture,
493 or includes flags that the -mcpu setting doesn't. */
495 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
496 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
497 warning (0, "-mcpu=%s conflicts with -march=%s",
498 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
500 entry
= m68k_cpu_entry
;
503 entry
= m68k_arch_entry
;
506 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
508 m68k_cpu_flags
= entry
->flags
;
510 /* Use the architecture setting to derive default values for
514 /* ColdFire is lenient about alignment. */
515 if (!TARGET_COLDFIRE
)
516 target_mask
|= MASK_STRICT_ALIGNMENT
;
518 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
519 target_mask
|= MASK_BITFIELD
;
520 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
521 target_mask
|= MASK_CF_HWDIV
;
522 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
523 target_mask
|= MASK_HARD_FLOAT
;
524 target_flags
|= target_mask
& ~target_flags_explicit
;
526 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
527 m68k_cpu
= entry
->device
;
530 m68k_tune
= m68k_tune_entry
->microarch
;
531 m68k_tune_flags
= m68k_tune_entry
->flags
;
533 #ifdef M68K_DEFAULT_TUNE
534 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
536 enum target_device dev
;
537 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
538 m68k_tune_flags
= all_devices
[dev
].flags
;
543 m68k_tune
= entry
->microarch
;
544 m68k_tune_flags
= entry
->flags
;
547 /* Set the type of FPU. */
548 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
549 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
552 /* Sanity check to ensure that msep-data and mid-sahred-library are not
553 * both specified together. Doing so simply doesn't make sense.
555 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
556 error ("cannot specify both -msep-data and -mid-shared-library");
558 /* If we're generating code for a separate A5 relative data segment,
559 * we've got to enable -fPIC as well. This might be relaxable to
560 * -fpic but it hasn't been tested properly.
562 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
565 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
566 error if the target does not support them. */
567 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
568 error ("-mpcrel -fPIC is not currently supported on selected cpu");
570 /* ??? A historic way of turning on pic, or is this intended to
571 be an embedded thing that doesn't have the same name binding
572 significance that it does on hosted ELF systems? */
573 if (TARGET_PCREL
&& flag_pic
== 0)
578 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
580 m68k_symbolic_jump
= "jra %a0";
582 else if (TARGET_ID_SHARED_LIBRARY
)
583 /* All addresses must be loaded from the GOT. */
585 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
588 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
590 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
593 /* No unconditional long branch */;
594 else if (TARGET_PCREL
)
595 m68k_symbolic_jump
= "bra%.l %c0";
597 m68k_symbolic_jump
= "bra%.l %p0";
598 /* Turn off function cse if we are doing PIC. We always want
599 function call to be done as `bsr foo@PLTPC'. */
600 /* ??? It's traditional to do this for -mpcrel too, but it isn't
601 clear how intentional that is. */
602 flag_no_function_cse
= 1;
605 switch (m68k_symbolic_call_var
)
607 case M68K_SYMBOLIC_CALL_JSR
:
608 m68k_symbolic_call
= "jsr %a0";
611 case M68K_SYMBOLIC_CALL_BSR_C
:
612 m68k_symbolic_call
= "bsr%.l %c0";
615 case M68K_SYMBOLIC_CALL_BSR_P
:
616 m68k_symbolic_call
= "bsr%.l %p0";
619 case M68K_SYMBOLIC_CALL_NONE
:
620 gcc_assert (m68k_symbolic_call
== NULL
);
627 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
628 if (align_labels
> 2)
630 warning (0, "-falign-labels=%d is not supported", align_labels
);
635 warning (0, "-falign-loops=%d is not supported", align_loops
);
640 if (stack_limit_rtx
!= NULL_RTX
&& !TARGET_68020
)
642 warning (0, "-fstack-limit- options are not supported on this cpu");
643 stack_limit_rtx
= NULL_RTX
;
646 SUBTARGET_OVERRIDE_OPTIONS
;
648 /* Setup scheduling options. */
650 m68k_sched_cpu
= CPU_CFV1
;
652 m68k_sched_cpu
= CPU_CFV2
;
654 m68k_sched_cpu
= CPU_CFV3
;
656 m68k_sched_cpu
= CPU_CFV4
;
659 m68k_sched_cpu
= CPU_UNKNOWN
;
660 flag_schedule_insns
= 0;
661 flag_schedule_insns_after_reload
= 0;
662 flag_modulo_sched
= 0;
663 flag_live_range_shrinkage
= 0;
666 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
668 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
669 m68k_sched_mac
= MAC_CF_EMAC
;
670 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
671 m68k_sched_mac
= MAC_CF_MAC
;
673 m68k_sched_mac
= MAC_NO
;
677 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
680 m68k_override_options_after_change (void)
682 if (m68k_sched_cpu
== CPU_UNKNOWN
)
684 flag_schedule_insns
= 0;
685 flag_schedule_insns_after_reload
= 0;
686 flag_modulo_sched
= 0;
687 flag_live_range_shrinkage
= 0;
691 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
692 given argument and NAME is the argument passed to -mcpu. Return NULL
693 if -mcpu was not passed. */
696 m68k_cpp_cpu_ident (const char *prefix
)
700 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
703 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
704 given argument and NAME is the name of the representative device for
705 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
708 m68k_cpp_cpu_family (const char *prefix
)
712 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
715 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
716 "interrupt_handler" attribute and interrupt_thread if FUNC has an
717 "interrupt_thread" attribute. Otherwise, return
718 m68k_fk_normal_function. */
720 enum m68k_function_kind
721 m68k_get_function_kind (tree func
)
725 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
727 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
729 return m68k_fk_interrupt_handler
;
731 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
733 return m68k_fk_interrupt_handler
;
735 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
737 return m68k_fk_interrupt_thread
;
739 return m68k_fk_normal_function
;
742 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
743 struct attribute_spec.handler. */
745 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
746 tree args ATTRIBUTE_UNUSED
,
747 int flags ATTRIBUTE_UNUSED
,
750 if (TREE_CODE (*node
) != FUNCTION_DECL
)
752 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
754 *no_add_attrs
= true;
757 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
759 error ("multiple interrupt attributes not allowed");
760 *no_add_attrs
= true;
764 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
766 error ("interrupt_thread is available only on fido");
767 *no_add_attrs
= true;
774 m68k_compute_frame_layout (void)
778 enum m68k_function_kind func_kind
=
779 m68k_get_function_kind (current_function_decl
);
780 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
781 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
783 /* Only compute the frame once per function.
784 Don't cache information until reload has been completed. */
785 if (current_frame
.funcdef_no
== current_function_funcdef_no
789 current_frame
.size
= (get_frame_size () + 3) & -4;
793 /* Interrupt thread does not need to save any register. */
794 if (!interrupt_thread
)
795 for (regno
= 0; regno
< 16; regno
++)
796 if (m68k_save_reg (regno
, interrupt_handler
))
798 mask
|= 1 << (regno
- D0_REG
);
801 current_frame
.offset
= saved
* 4;
802 current_frame
.reg_no
= saved
;
803 current_frame
.reg_mask
= mask
;
805 current_frame
.foffset
= 0;
807 if (TARGET_HARD_FLOAT
)
809 /* Interrupt thread does not need to save any register. */
810 if (!interrupt_thread
)
811 for (regno
= 16; regno
< 24; regno
++)
812 if (m68k_save_reg (regno
, interrupt_handler
))
814 mask
|= 1 << (regno
- FP0_REG
);
817 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
818 current_frame
.offset
+= current_frame
.foffset
;
820 current_frame
.fpu_no
= saved
;
821 current_frame
.fpu_mask
= mask
;
823 /* Remember what function this frame refers to. */
824 current_frame
.funcdef_no
= current_function_funcdef_no
;
827 /* Worker function for TARGET_CAN_ELIMINATE. */
830 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
832 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
836 m68k_initial_elimination_offset (int from
, int to
)
839 /* The arg pointer points 8 bytes before the start of the arguments,
840 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
841 frame pointer in most frames. */
842 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
843 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
844 return argptr_offset
;
846 m68k_compute_frame_layout ();
848 gcc_assert (to
== STACK_POINTER_REGNUM
);
851 case ARG_POINTER_REGNUM
:
852 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
853 case FRAME_POINTER_REGNUM
:
854 return current_frame
.offset
+ current_frame
.size
;
860 /* Refer to the array `regs_ever_live' to determine which registers
861 to save; `regs_ever_live[I]' is nonzero if register number I
862 is ever used in the function. This function is responsible for
863 knowing which registers should not be saved even if used.
864 Return true if we need to save REGNO. */
867 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
869 if (flag_pic
&& regno
== PIC_REG
)
871 if (crtl
->saves_all_registers
)
873 if (crtl
->uses_pic_offset_table
)
875 /* Reload may introduce constant pool references into a function
876 that thitherto didn't need a PIC register. Note that the test
877 above will not catch that case because we will only set
878 crtl->uses_pic_offset_table when emitting
879 the address reloads. */
880 if (crtl
->uses_const_pool
)
884 if (crtl
->calls_eh_return
)
889 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
890 if (test
== INVALID_REGNUM
)
897 /* Fixed regs we never touch. */
898 if (fixed_regs
[regno
])
901 /* The frame pointer (if it is such) is handled specially. */
902 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
905 /* Interrupt handlers must also save call_used_regs
906 if they are live or when calling nested functions. */
907 if (interrupt_handler
)
909 if (df_regs_ever_live_p (regno
))
912 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
916 /* Never need to save registers that aren't touched. */
917 if (!df_regs_ever_live_p (regno
))
920 /* Otherwise save everything that isn't call-clobbered. */
921 return !call_used_regs
[regno
];
924 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
925 the lowest memory address. COUNT is the number of registers to be
926 moved, with register REGNO + I being moved if bit I of MASK is set.
927 STORE_P specifies the direction of the move and ADJUST_STACK_P says
928 whether or not this is pre-decrement (if STORE_P) or post-increment
929 (if !STORE_P) operation. */
932 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
933 unsigned int count
, unsigned int regno
,
934 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
937 rtx body
, addr
, src
, operands
[2];
940 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
941 mode
= reg_raw_mode
[regno
];
946 src
= plus_constant (Pmode
, base
,
948 * GET_MODE_SIZE (mode
)
949 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
950 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
953 for (; mask
!= 0; mask
>>= 1, regno
++)
956 addr
= plus_constant (Pmode
, base
, offset
);
957 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
958 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
959 XVECEXP (body
, 0, i
++)
960 = gen_rtx_SET (operands
[0], operands
[1]);
961 offset
+= GET_MODE_SIZE (mode
);
963 gcc_assert (i
== XVECLEN (body
, 0));
965 return emit_insn (body
);
968 /* Make INSN a frame-related instruction. */
971 m68k_set_frame_related (rtx_insn
*insn
)
976 RTX_FRAME_RELATED_P (insn
) = 1;
977 body
= PATTERN (insn
);
978 if (GET_CODE (body
) == PARALLEL
)
979 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
980 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
983 /* Emit RTL for the "prologue" define_expand. */
986 m68k_expand_prologue (void)
988 HOST_WIDE_INT fsize_with_regs
;
989 rtx limit
, src
, dest
;
991 m68k_compute_frame_layout ();
993 if (flag_stack_usage_info
)
994 current_function_static_stack_size
995 = current_frame
.size
+ current_frame
.offset
;
997 /* If the stack limit is a symbol, we can check it here,
998 before actually allocating the space. */
999 if (crtl
->limit_stack
1000 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1002 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1003 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1005 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1006 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1008 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1009 stack_pointer_rtx
, limit
),
1010 stack_pointer_rtx
, limit
,
1014 fsize_with_regs
= current_frame
.size
;
1015 if (TARGET_COLDFIRE
)
1017 /* ColdFire's move multiple instructions do not allow pre-decrement
1018 addressing. Add the size of movem saves to the initial stack
1019 allocation instead. */
1020 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1021 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1022 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1023 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1026 if (frame_pointer_needed
)
1028 if (fsize_with_regs
== 0 && TUNE_68040
)
1030 /* On the 68040, two separate moves are faster than link.w 0. */
1031 dest
= gen_frame_mem (Pmode
,
1032 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1033 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1034 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1035 stack_pointer_rtx
));
1037 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1038 m68k_set_frame_related
1039 (emit_insn (gen_link (frame_pointer_rtx
,
1040 GEN_INT (-4 - fsize_with_regs
))));
1043 m68k_set_frame_related
1044 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1045 m68k_set_frame_related
1046 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1048 GEN_INT (-fsize_with_regs
))));
1051 /* If the frame pointer is needed, emit a special barrier that
1052 will prevent the scheduler from moving stores to the frame
1053 before the stack adjustment. */
1054 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1056 else if (fsize_with_regs
!= 0)
1057 m68k_set_frame_related
1058 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1060 GEN_INT (-fsize_with_regs
))));
1062 if (current_frame
.fpu_mask
)
1064 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1066 m68k_set_frame_related
1067 (m68k_emit_movem (stack_pointer_rtx
,
1068 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1069 current_frame
.fpu_no
, FP0_REG
,
1070 current_frame
.fpu_mask
, true, true));
1075 /* If we're using moveml to save the integer registers,
1076 the stack pointer will point to the bottom of the moveml
1077 save area. Find the stack offset of the first FP register. */
1078 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1081 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1082 m68k_set_frame_related
1083 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1084 current_frame
.fpu_no
, FP0_REG
,
1085 current_frame
.fpu_mask
, true, false));
1089 /* If the stack limit is not a symbol, check it here.
1090 This has the disadvantage that it may be too late... */
1091 if (crtl
->limit_stack
)
1093 if (REG_P (stack_limit_rtx
))
1094 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1096 stack_pointer_rtx
, stack_limit_rtx
,
1099 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1100 warning (0, "stack limit expression is not supported");
1103 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1105 /* Store each register separately in the same order moveml does. */
1108 for (i
= 16; i
-- > 0; )
1109 if (current_frame
.reg_mask
& (1 << i
))
1111 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1112 dest
= gen_frame_mem (SImode
,
1113 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1114 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1119 if (TARGET_COLDFIRE
)
1120 /* The required register save space has already been allocated.
1121 The first register should be stored at (%sp). */
1122 m68k_set_frame_related
1123 (m68k_emit_movem (stack_pointer_rtx
, 0,
1124 current_frame
.reg_no
, D0_REG
,
1125 current_frame
.reg_mask
, true, false));
1127 m68k_set_frame_related
1128 (m68k_emit_movem (stack_pointer_rtx
,
1129 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1130 current_frame
.reg_no
, D0_REG
,
1131 current_frame
.reg_mask
, true, true));
1134 if (!TARGET_SEP_DATA
1135 && crtl
->uses_pic_offset_table
)
1136 emit_insn (gen_load_got (pic_offset_table_rtx
));
1139 /* Return true if a simple (return) instruction is sufficient for this
1140 instruction (i.e. if no epilogue is needed). */
1143 m68k_use_return_insn (void)
1145 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1148 m68k_compute_frame_layout ();
1149 return current_frame
.offset
== 0;
1152 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1153 SIBCALL_P says which.
1155 The function epilogue should not depend on the current stack pointer!
1156 It should use the frame pointer only, if there is a frame pointer.
1157 This is mandatory because of alloca; we also take advantage of it to
1158 omit stack adjustments before returning. */
1161 m68k_expand_epilogue (bool sibcall_p
)
1163 HOST_WIDE_INT fsize
, fsize_with_regs
;
1164 bool big
, restore_from_sp
;
1166 m68k_compute_frame_layout ();
1168 fsize
= current_frame
.size
;
1170 restore_from_sp
= false;
1172 /* FIXME : crtl->is_leaf below is too strong.
1173 What we really need to know there is if there could be pending
1174 stack adjustment needed at that point. */
1175 restore_from_sp
= (!frame_pointer_needed
1176 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1178 /* fsize_with_regs is the size we need to adjust the sp when
1179 popping the frame. */
1180 fsize_with_regs
= fsize
;
1181 if (TARGET_COLDFIRE
&& restore_from_sp
)
1183 /* ColdFire's move multiple instructions do not allow post-increment
1184 addressing. Add the size of movem loads to the final deallocation
1186 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1187 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1188 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1189 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1192 if (current_frame
.offset
+ fsize
>= 0x8000
1194 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1197 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1198 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1200 /* ColdFire's move multiple instructions do not support the
1201 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1202 stack-based restore. */
1203 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1204 GEN_INT (-(current_frame
.offset
+ fsize
)));
1205 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1206 gen_rtx_REG (Pmode
, A1_REG
),
1207 frame_pointer_rtx
));
1208 restore_from_sp
= true;
1212 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1218 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1220 /* Restore each register separately in the same order moveml does. */
1222 HOST_WIDE_INT offset
;
1224 offset
= current_frame
.offset
+ fsize
;
1225 for (i
= 0; i
< 16; i
++)
1226 if (current_frame
.reg_mask
& (1 << i
))
1232 /* Generate the address -OFFSET(%fp,%a1.l). */
1233 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1234 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1235 addr
= plus_constant (Pmode
, addr
, -offset
);
1237 else if (restore_from_sp
)
1238 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1240 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1241 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1242 gen_frame_mem (SImode
, addr
));
1243 offset
-= GET_MODE_SIZE (SImode
);
1246 else if (current_frame
.reg_mask
)
1249 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1250 gen_rtx_REG (Pmode
, A1_REG
),
1252 -(current_frame
.offset
+ fsize
),
1253 current_frame
.reg_no
, D0_REG
,
1254 current_frame
.reg_mask
, false, false);
1255 else if (restore_from_sp
)
1256 m68k_emit_movem (stack_pointer_rtx
, 0,
1257 current_frame
.reg_no
, D0_REG
,
1258 current_frame
.reg_mask
, false,
1261 m68k_emit_movem (frame_pointer_rtx
,
1262 -(current_frame
.offset
+ fsize
),
1263 current_frame
.reg_no
, D0_REG
,
1264 current_frame
.reg_mask
, false, false);
1267 if (current_frame
.fpu_no
> 0)
1270 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1271 gen_rtx_REG (Pmode
, A1_REG
),
1273 -(current_frame
.foffset
+ fsize
),
1274 current_frame
.fpu_no
, FP0_REG
,
1275 current_frame
.fpu_mask
, false, false);
1276 else if (restore_from_sp
)
1278 if (TARGET_COLDFIRE
)
1282 /* If we used moveml to restore the integer registers, the
1283 stack pointer will still point to the bottom of the moveml
1284 save area. Find the stack offset of the first FP
1286 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1289 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1290 m68k_emit_movem (stack_pointer_rtx
, offset
,
1291 current_frame
.fpu_no
, FP0_REG
,
1292 current_frame
.fpu_mask
, false, false);
1295 m68k_emit_movem (stack_pointer_rtx
, 0,
1296 current_frame
.fpu_no
, FP0_REG
,
1297 current_frame
.fpu_mask
, false, true);
1300 m68k_emit_movem (frame_pointer_rtx
,
1301 -(current_frame
.foffset
+ fsize
),
1302 current_frame
.fpu_no
, FP0_REG
,
1303 current_frame
.fpu_mask
, false, false);
1306 if (frame_pointer_needed
)
1307 emit_insn (gen_unlink (frame_pointer_rtx
));
1308 else if (fsize_with_regs
)
1309 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1311 GEN_INT (fsize_with_regs
)));
1313 if (crtl
->calls_eh_return
)
1314 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1316 EH_RETURN_STACKADJ_RTX
));
1319 emit_jump_insn (ret_rtx
);
1322 /* Return true if X is a valid comparison operator for the dbcc
1325 Note it rejects floating point comparison operators.
1326 (In the future we could use Fdbcc).
1328 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1331 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1333 switch (GET_CODE (x
))
1335 case EQ
: case NE
: case GTU
: case LTU
:
1339 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1341 case GT
: case LT
: case GE
: case LE
:
1342 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1348 /* Return nonzero if flags are currently in the 68881 flag register. */
1350 flags_in_68881 (void)
1352 /* We could add support for these in the future */
1353 return cc_status
.flags
& CC_IN_68881
;
1356 /* Return true if PARALLEL contains register REGNO. */
1358 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1362 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1365 if (GET_CODE (parallel
) != PARALLEL
)
1368 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1372 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1373 if (REG_P (x
) && REGNO (x
) == regno
)
1380 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1383 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1385 enum m68k_function_kind kind
;
1387 /* We cannot use sibcalls for nested functions because we use the
1388 static chain register for indirect calls. */
1389 if (CALL_EXPR_STATIC_CHAIN (exp
))
1392 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1394 /* Check that the return value locations are the same. For
1395 example that we aren't returning a value from the sibling in
1396 a D0 register but then need to transfer it to a A0 register. */
1400 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1402 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1404 /* Check that the values are equal or that the result the callee
1405 function returns is superset of what the current function returns. */
1406 if (!(rtx_equal_p (cfun_value
, call_value
)
1407 || (REG_P (cfun_value
)
1408 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1412 kind
= m68k_get_function_kind (current_function_decl
);
1413 if (kind
== m68k_fk_normal_function
)
1414 /* We can always sibcall from a normal function, because it's
1415 undefined if it is calling an interrupt function. */
1418 /* Otherwise we can only sibcall if the function kind is known to be
1420 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1426 /* On the m68k all args are always pushed. */
1429 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1430 machine_mode mode ATTRIBUTE_UNUSED
,
1431 const_tree type ATTRIBUTE_UNUSED
,
1432 bool named ATTRIBUTE_UNUSED
)
1438 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1439 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1441 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1443 *cum
+= (mode
!= BLKmode
1444 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1445 : (int_size_in_bytes (type
) + 3) & ~3);
1448 /* Convert X to a legitimate function call memory reference and return the
1452 m68k_legitimize_call_address (rtx x
)
1454 gcc_assert (MEM_P (x
));
1455 if (call_operand (XEXP (x
, 0), VOIDmode
))
1457 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1460 /* Likewise for sibling calls. */
1463 m68k_legitimize_sibcall_address (rtx x
)
1465 gcc_assert (MEM_P (x
));
1466 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1469 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1470 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1473 /* Convert X to a legitimate address and return it if successful. Otherwise
1476 For the 68000, we handle X+REG by loading X into a register R and
1477 using R+REG. R will go in an address reg and indexing will be used.
1478 However, if REG is a broken-out memory address or multiplication,
1479 nothing needs to be done because REG can certainly go in an address reg. */
1482 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1484 if (m68k_tls_symbol_p (x
))
1485 return m68k_legitimize_tls_address (x
);
1487 if (GET_CODE (x
) == PLUS
)
1489 int ch
= (x
) != (oldx
);
1492 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1494 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1497 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1499 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1502 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1506 if (GET_CODE (XEXP (x
, 1)) == REG
1507 && GET_CODE (XEXP (x
, 0)) == REG
)
1509 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1512 x
= force_operand (x
, 0);
1516 if (memory_address_p (mode
, x
))
1519 if (GET_CODE (XEXP (x
, 0)) == REG
1520 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1521 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1522 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1524 rtx temp
= gen_reg_rtx (Pmode
);
1525 rtx val
= force_operand (XEXP (x
, 1), 0);
1526 emit_move_insn (temp
, val
);
1529 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1530 && GET_CODE (XEXP (x
, 0)) == REG
)
1531 x
= force_operand (x
, 0);
1533 else if (GET_CODE (XEXP (x
, 1)) == REG
1534 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1535 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1536 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1538 rtx temp
= gen_reg_rtx (Pmode
);
1539 rtx val
= force_operand (XEXP (x
, 0), 0);
1540 emit_move_insn (temp
, val
);
1543 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1544 && GET_CODE (XEXP (x
, 1)) == REG
)
1545 x
= force_operand (x
, 0);
1553 /* Output a dbCC; jCC sequence. Note we do not handle the
1554 floating point version of this sequence (Fdbcc). We also
1555 do not handle alternative conditions when CC_NO_OVERFLOW is
1556 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1557 kick those out before we get here. */
1560 output_dbcc_and_branch (rtx
*operands
)
1562 switch (GET_CODE (operands
[3]))
1565 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1569 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1573 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1577 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1581 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1585 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1589 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1593 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1597 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1601 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1608 /* If the decrement is to be done in SImode, then we have
1609 to compensate for the fact that dbcc decrements in HImode. */
1610 switch (GET_MODE (operands
[0]))
1613 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1625 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1628 enum rtx_code op_code
= GET_CODE (op
);
1630 /* This does not produce a useful cc. */
1633 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1634 below. Swap the operands and change the op if these requirements
1635 are not fulfilled. */
1636 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1640 operand1
= operand2
;
1642 op_code
= swap_condition (op_code
);
1644 loperands
[0] = operand1
;
1645 if (GET_CODE (operand1
) == REG
)
1646 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1648 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1649 if (operand2
!= const0_rtx
)
1651 loperands
[2] = operand2
;
1652 if (GET_CODE (operand2
) == REG
)
1653 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1655 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1657 loperands
[4] = gen_label_rtx ();
1658 if (operand2
!= const0_rtx
)
1659 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1662 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1663 output_asm_insn ("tst%.l %0", loperands
);
1665 output_asm_insn ("cmp%.w #0,%0", loperands
);
1667 output_asm_insn ("jne %l4", loperands
);
1669 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1670 output_asm_insn ("tst%.l %1", loperands
);
1672 output_asm_insn ("cmp%.w #0,%1", loperands
);
1675 loperands
[5] = dest
;
1680 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1681 CODE_LABEL_NUMBER (loperands
[4]));
1682 output_asm_insn ("seq %5", loperands
);
1686 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1687 CODE_LABEL_NUMBER (loperands
[4]));
1688 output_asm_insn ("sne %5", loperands
);
1692 loperands
[6] = gen_label_rtx ();
1693 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1694 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1695 CODE_LABEL_NUMBER (loperands
[4]));
1696 output_asm_insn ("sgt %5", loperands
);
1697 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1698 CODE_LABEL_NUMBER (loperands
[6]));
1702 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1703 CODE_LABEL_NUMBER (loperands
[4]));
1704 output_asm_insn ("shi %5", loperands
);
1708 loperands
[6] = gen_label_rtx ();
1709 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1710 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1711 CODE_LABEL_NUMBER (loperands
[4]));
1712 output_asm_insn ("slt %5", loperands
);
1713 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1714 CODE_LABEL_NUMBER (loperands
[6]));
1718 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1719 CODE_LABEL_NUMBER (loperands
[4]));
1720 output_asm_insn ("scs %5", loperands
);
1724 loperands
[6] = gen_label_rtx ();
1725 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1726 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1727 CODE_LABEL_NUMBER (loperands
[4]));
1728 output_asm_insn ("sge %5", loperands
);
1729 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1730 CODE_LABEL_NUMBER (loperands
[6]));
1734 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1735 CODE_LABEL_NUMBER (loperands
[4]));
1736 output_asm_insn ("scc %5", loperands
);
1740 loperands
[6] = gen_label_rtx ();
1741 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1742 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1743 CODE_LABEL_NUMBER (loperands
[4]));
1744 output_asm_insn ("sle %5", loperands
);
1745 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1746 CODE_LABEL_NUMBER (loperands
[6]));
1750 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1751 CODE_LABEL_NUMBER (loperands
[4]));
1752 output_asm_insn ("sls %5", loperands
);
1762 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1764 operands
[0] = countop
;
1765 operands
[1] = dataop
;
1767 if (GET_CODE (countop
) == CONST_INT
)
1769 register int count
= INTVAL (countop
);
1770 /* If COUNT is bigger than size of storage unit in use,
1771 advance to the containing unit of same size. */
1772 if (count
> signpos
)
1774 int offset
= (count
& ~signpos
) / 8;
1775 count
= count
& signpos
;
1776 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1778 if (count
== signpos
)
1779 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1781 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1783 /* These three statements used to use next_insns_test_no...
1784 but it appears that this should do the same job. */
1786 && next_insn_tests_no_inequality (insn
))
1789 && next_insn_tests_no_inequality (insn
))
1792 && next_insn_tests_no_inequality (insn
))
1794 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1795 On some m68k variants unfortunately that's slower than btst.
1796 On 68000 and higher, that should also work for all HImode operands. */
1797 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1799 if (count
== 3 && DATA_REG_P (operands
[1])
1800 && next_insn_tests_no_inequality (insn
))
1802 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1803 return "move%.w %1,%%ccr";
1805 if (count
== 2 && DATA_REG_P (operands
[1])
1806 && next_insn_tests_no_inequality (insn
))
1808 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1809 return "move%.w %1,%%ccr";
1811 /* count == 1 followed by bvc/bvs and
1812 count == 0 followed by bcc/bcs are also possible, but need
1813 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1816 cc_status
.flags
= CC_NOT_NEGATIVE
;
1818 return "btst %0,%1";
1821 /* Return true if X is a legitimate base register. STRICT_P says
1822 whether we need strict checking. */
1825 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1827 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1828 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1833 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1834 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1837 /* Return true if X is a legitimate index register. STRICT_P says
1838 whether we need strict checking. */
1841 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1843 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1848 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1849 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1852 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1853 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1854 ADDRESS if so. STRICT_P says whether we need strict checking. */
1857 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1861 /* Check for a scale factor. */
1863 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1864 && GET_CODE (x
) == MULT
1865 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1866 && (INTVAL (XEXP (x
, 1)) == 2
1867 || INTVAL (XEXP (x
, 1)) == 4
1868 || (INTVAL (XEXP (x
, 1)) == 8
1869 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1871 scale
= INTVAL (XEXP (x
, 1));
1875 /* Check for a word extension. */
1876 if (!TARGET_COLDFIRE
1877 && GET_CODE (x
) == SIGN_EXTEND
1878 && GET_MODE (XEXP (x
, 0)) == HImode
)
1881 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1883 address
->scale
= scale
;
1891 /* Return true if X is an illegitimate symbolic constant. */
1894 m68k_illegitimate_symbolic_constant_p (rtx x
)
1898 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1900 split_const (x
, &base
, &offset
);
1901 if (GET_CODE (base
) == SYMBOL_REF
1902 && !offset_within_block_p (base
, INTVAL (offset
)))
1905 return m68k_tls_reference_p (x
, false);
1908 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1911 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1913 return m68k_illegitimate_symbolic_constant_p (x
);
1916 /* Return true if X is a legitimate constant address that can reach
1917 bytes in the range [X, X + REACH). STRICT_P says whether we need
1921 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1925 if (!CONSTANT_ADDRESS_P (x
))
1929 && !(strict_p
&& TARGET_PCREL
)
1930 && symbolic_operand (x
, VOIDmode
))
1933 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1935 split_const (x
, &base
, &offset
);
1936 if (GET_CODE (base
) == SYMBOL_REF
1937 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1941 return !m68k_tls_reference_p (x
, false);
1944 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1945 labels will become jump tables. */
1948 m68k_jump_table_ref_p (rtx x
)
1950 if (GET_CODE (x
) != LABEL_REF
)
1953 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1954 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1957 insn
= next_nonnote_insn (insn
);
1958 return insn
&& JUMP_TABLE_DATA_P (insn
);
1961 /* Return true if X is a legitimate address for values of mode MODE.
1962 STRICT_P says whether strict checking is needed. If the address
1963 is valid, describe its components in *ADDRESS. */
1966 m68k_decompose_address (machine_mode mode
, rtx x
,
1967 bool strict_p
, struct m68k_address
*address
)
1971 memset (address
, 0, sizeof (*address
));
1973 if (mode
== BLKmode
)
1976 reach
= GET_MODE_SIZE (mode
);
1978 /* Check for (An) (mode 2). */
1979 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1985 /* Check for -(An) and (An)+ (modes 3 and 4). */
1986 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1987 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1989 address
->code
= GET_CODE (x
);
1990 address
->base
= XEXP (x
, 0);
1994 /* Check for (d16,An) (mode 5). */
1995 if (GET_CODE (x
) == PLUS
1996 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1997 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1998 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2000 address
->base
= XEXP (x
, 0);
2001 address
->offset
= XEXP (x
, 1);
2005 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2006 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2008 if (GET_CODE (x
) == PLUS
2009 && XEXP (x
, 0) == pic_offset_table_rtx
)
2011 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2012 they are invalid in this context. */
2013 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2015 address
->base
= XEXP (x
, 0);
2016 address
->offset
= XEXP (x
, 1);
2021 /* The ColdFire FPU only accepts addressing modes 2-5. */
2022 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2025 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2026 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2027 All these modes are variations of mode 7. */
2028 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2030 address
->offset
= x
;
2034 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2037 ??? do_tablejump creates these addresses before placing the target
2038 label, so we have to assume that unplaced labels are jump table
2039 references. It seems unlikely that we would ever generate indexed
2040 accesses to unplaced labels in other cases. */
2041 if (GET_CODE (x
) == PLUS
2042 && m68k_jump_table_ref_p (XEXP (x
, 1))
2043 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2045 address
->offset
= XEXP (x
, 1);
2049 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2050 (bd,An,Xn.SIZE*SCALE) addresses. */
2054 /* Check for a nonzero base displacement. */
2055 if (GET_CODE (x
) == PLUS
2056 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2058 address
->offset
= XEXP (x
, 1);
2062 /* Check for a suppressed index register. */
2063 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2069 /* Check for a suppressed base register. Do not allow this case
2070 for non-symbolic offsets as it effectively gives gcc freedom
2071 to treat data registers as base registers, which can generate
2074 && symbolic_operand (address
->offset
, VOIDmode
)
2075 && m68k_decompose_index (x
, strict_p
, address
))
2080 /* Check for a nonzero base displacement. */
2081 if (GET_CODE (x
) == PLUS
2082 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2083 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2085 address
->offset
= XEXP (x
, 1);
2090 /* We now expect the sum of a base and an index. */
2091 if (GET_CODE (x
) == PLUS
)
2093 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2094 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2096 address
->base
= XEXP (x
, 0);
2100 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2101 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2103 address
->base
= XEXP (x
, 1);
2110 /* Return true if X is a legitimate address for values of mode MODE.
2111 STRICT_P says whether strict checking is needed. */
2114 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2116 struct m68k_address address
;
2118 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2121 /* Return true if X is a memory, describing its address in ADDRESS if so.
2122 Apply strict checking if called during or after reload. */
2125 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2128 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2129 reload_in_progress
|| reload_completed
,
2133 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2136 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2138 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2141 /* Return true if X matches the 'Q' constraint. It must be a memory
2142 with a base address and no constant offset or index. */
2145 m68k_matches_q_p (rtx x
)
2147 struct m68k_address address
;
2149 return (m68k_legitimate_mem_p (x
, &address
)
2150 && address
.code
== UNKNOWN
2156 /* Return true if X matches the 'U' constraint. It must be a base address
2157 with a constant offset and no index. */
2160 m68k_matches_u_p (rtx x
)
2162 struct m68k_address address
;
2164 return (m68k_legitimate_mem_p (x
, &address
)
2165 && address
.code
== UNKNOWN
2171 /* Return GOT pointer. */
2176 if (pic_offset_table_rtx
== NULL_RTX
)
2177 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2179 crtl
->uses_pic_offset_table
= 1;
2181 return pic_offset_table_rtx
;
2184 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2186 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2187 RELOC_TLSIE
, RELOC_TLSLE
};
2189 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2191 /* Wrap symbol X into unspec representing relocation RELOC.
2192 BASE_REG - register that should be added to the result.
2193 TEMP_REG - if non-null, temporary register. */
2196 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2200 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2202 if (TARGET_COLDFIRE
&& use_x_p
)
2203 /* When compiling with -mx{got, tls} switch the code will look like this:
2205 move.l <X>@<RELOC>,<TEMP_REG>
2206 add.l <BASE_REG>,<TEMP_REG> */
2208 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2209 to put @RELOC after reference. */
2210 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2212 x
= gen_rtx_CONST (Pmode
, x
);
2214 if (temp_reg
== NULL
)
2216 gcc_assert (can_create_pseudo_p ());
2217 temp_reg
= gen_reg_rtx (Pmode
);
2220 emit_move_insn (temp_reg
, x
);
2221 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2226 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2228 x
= gen_rtx_CONST (Pmode
, x
);
2230 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2236 /* Helper for m68k_unwrap_symbol.
2237 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2238 sets *RELOC_PTR to relocation type for the symbol. */
2241 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2242 enum m68k_reloc
*reloc_ptr
)
2244 if (GET_CODE (orig
) == CONST
)
2247 enum m68k_reloc dummy
;
2251 if (reloc_ptr
== NULL
)
2254 /* Handle an addend. */
2255 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2256 && CONST_INT_P (XEXP (x
, 1)))
2259 if (GET_CODE (x
) == UNSPEC
)
2261 switch (XINT (x
, 1))
2263 case UNSPEC_RELOC16
:
2264 orig
= XVECEXP (x
, 0, 0);
2265 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2268 case UNSPEC_RELOC32
:
2269 if (unwrap_reloc32_p
)
2271 orig
= XVECEXP (x
, 0, 0);
2272 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2285 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2286 UNSPEC_RELOC32 wrappers. */
2289 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2291 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2294 /* Prescan insn before outputing assembler for it. */
2297 m68k_final_prescan_insn (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2298 rtx
*operands
, int n_operands
)
2302 /* Combine and, possibly, other optimizations may do good job
2304 (const (unspec [(symbol)]))
2306 (const (plus (unspec [(symbol)])
2308 The problem with this is emitting @TLS or @GOT decorations.
2309 The decoration is emitted when processing (unspec), so the
2310 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2312 It seems that the easiest solution to this is to convert such
2314 (const (unspec [(plus (symbol)
2316 Note, that the top level of operand remains intact, so we don't have
2317 to patch up anything outside of the operand. */
2319 subrtx_var_iterator::array_type array
;
2320 for (i
= 0; i
< n_operands
; ++i
)
2326 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2329 if (m68k_unwrap_symbol (x
, true) != x
)
2333 gcc_assert (GET_CODE (x
) == CONST
);
2336 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2341 unspec
= XEXP (plus
, 0);
2342 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2343 addend
= XEXP (plus
, 1);
2344 gcc_assert (CONST_INT_P (addend
));
2346 /* We now have all the pieces, rearrange them. */
2348 /* Move symbol to plus. */
2349 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2351 /* Move plus inside unspec. */
2352 XVECEXP (unspec
, 0, 0) = plus
;
2354 /* Move unspec to top level of const. */
2355 XEXP (x
, 0) = unspec
;
2357 iter
.skip_subrtxes ();
2363 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2364 If REG is non-null, use it; generate new pseudo otherwise. */
2367 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2371 if (reg
== NULL_RTX
)
2373 gcc_assert (can_create_pseudo_p ());
2374 reg
= gen_reg_rtx (Pmode
);
2377 insn
= emit_move_insn (reg
, x
);
2378 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2380 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2385 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2389 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2391 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2393 x
= gen_rtx_MEM (Pmode
, x
);
2394 MEM_READONLY_P (x
) = 1;
2399 /* Legitimize PIC addresses. If the address is already
2400 position-independent, we return ORIG. Newly generated
2401 position-independent addresses go to REG. If we need more
2402 than one register, we lose.
2404 An address is legitimized by making an indirect reference
2405 through the Global Offset Table with the name of the symbol
2408 The assembler and linker are responsible for placing the
2409 address of the symbol in the GOT. The function prologue
2410 is responsible for initializing a5 to the starting address
2413 The assembler is also responsible for translating a symbol name
2414 into a constant displacement from the start of the GOT.
2416 A quick example may make things a little clearer:
2418 When not generating PIC code to store the value 12345 into _foo
2419 we would generate the following code:
2423 When generating PIC two transformations are made. First, the compiler
2424 loads the address of foo into a register. So the first transformation makes:
2429 The code in movsi will intercept the lea instruction and call this
2430 routine which will transform the instructions into:
2432 movel a5@(_foo:w), a0
2436 That (in a nutshell) is how *all* symbol and label references are
2440 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2445 /* First handle a simple SYMBOL_REF or LABEL_REF */
2446 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2450 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2451 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2453 else if (GET_CODE (orig
) == CONST
)
2457 /* Make sure this has not already been legitimized. */
2458 if (m68k_unwrap_symbol (orig
, true) != orig
)
2463 /* legitimize both operands of the PLUS */
2464 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2466 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2467 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2468 base
== reg
? 0 : reg
);
2470 if (GET_CODE (orig
) == CONST_INT
)
2471 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2473 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2479 /* The __tls_get_addr symbol. */
2480 static GTY(()) rtx m68k_tls_get_addr
;
2482 /* Return SYMBOL_REF for __tls_get_addr. */
2485 m68k_get_tls_get_addr (void)
2487 if (m68k_tls_get_addr
== NULL_RTX
)
2488 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2490 return m68k_tls_get_addr
;
2493 /* Return libcall result in A0 instead of usual D0. */
2494 static bool m68k_libcall_value_in_a0_p
= false;
2496 /* Emit instruction sequence that calls __tls_get_addr. X is
2497 the TLS symbol we are referencing and RELOC is the symbol type to use
2498 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2499 emitted. A pseudo register with result of __tls_get_addr call is
2503 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2509 /* Emit the call sequence. */
2512 /* FIXME: Unfortunately, emit_library_call_value does not
2513 consider (plus (%a5) (const (unspec))) to be a good enough
2514 operand for push, so it forces it into a register. The bad
2515 thing about this is that combiner, due to copy propagation and other
2516 optimizations, sometimes can not later fix this. As a consequence,
2517 additional register may be allocated resulting in a spill.
2518 For reference, see args processing loops in
2519 calls.c:emit_library_call_value_1.
2520 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2521 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2523 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2524 is the simpliest way of generating a call. The difference between
2525 __tls_get_addr() and libcall is that the result is returned in D0
2526 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2527 which temporarily switches returning the result to A0. */
2529 m68k_libcall_value_in_a0_p
= true;
2530 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2531 Pmode
, 1, x
, Pmode
);
2532 m68k_libcall_value_in_a0_p
= false;
2534 insns
= get_insns ();
2537 gcc_assert (can_create_pseudo_p ());
2538 dest
= gen_reg_rtx (Pmode
);
2539 emit_libcall_block (insns
, dest
, a0
, eqv
);
2544 /* The __tls_get_addr symbol. */
2545 static GTY(()) rtx m68k_read_tp
;
2547 /* Return SYMBOL_REF for __m68k_read_tp. */
2550 m68k_get_m68k_read_tp (void)
2552 if (m68k_read_tp
== NULL_RTX
)
2553 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2555 return m68k_read_tp
;
2558 /* Emit instruction sequence that calls __m68k_read_tp.
2559 A pseudo register with result of __m68k_read_tp call is returned. */
2562 m68k_call_m68k_read_tp (void)
2571 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2572 is the simpliest way of generating a call. The difference between
2573 __m68k_read_tp() and libcall is that the result is returned in D0
2574 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2575 which temporarily switches returning the result to A0. */
2577 /* Emit the call sequence. */
2578 m68k_libcall_value_in_a0_p
= true;
2579 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2581 m68k_libcall_value_in_a0_p
= false;
2582 insns
= get_insns ();
2585 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2586 share the m68k_read_tp result with other IE/LE model accesses. */
2587 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2589 gcc_assert (can_create_pseudo_p ());
2590 dest
= gen_reg_rtx (Pmode
);
2591 emit_libcall_block (insns
, dest
, a0
, eqv
);
2596 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2597 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2601 m68k_legitimize_tls_address (rtx orig
)
2603 switch (SYMBOL_REF_TLS_MODEL (orig
))
2605 case TLS_MODEL_GLOBAL_DYNAMIC
:
2606 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2609 case TLS_MODEL_LOCAL_DYNAMIC
:
2615 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2616 share the LDM result with other LD model accesses. */
2617 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2620 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2622 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2624 if (can_create_pseudo_p ())
2625 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2631 case TLS_MODEL_INITIAL_EXEC
:
2636 a0
= m68k_call_m68k_read_tp ();
2638 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2639 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2641 if (can_create_pseudo_p ())
2642 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2648 case TLS_MODEL_LOCAL_EXEC
:
2653 a0
= m68k_call_m68k_read_tp ();
2655 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2657 if (can_create_pseudo_p ())
2658 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2671 /* Return true if X is a TLS symbol. */
2674 m68k_tls_symbol_p (rtx x
)
2676 if (!TARGET_HAVE_TLS
)
2679 if (GET_CODE (x
) != SYMBOL_REF
)
2682 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2685 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2686 though illegitimate one.
2687 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2690 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2692 if (!TARGET_HAVE_TLS
)
2697 subrtx_var_iterator::array_type array
;
2698 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2702 /* Note: this is not the same as m68k_tls_symbol_p. */
2703 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2706 /* Don't recurse into legitimate TLS references. */
2707 if (m68k_tls_reference_p (x
, true))
2708 iter
.skip_subrtxes ();
2714 enum m68k_reloc reloc
= RELOC_GOT
;
2716 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2717 && TLS_RELOC_P (reloc
));
2723 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2725 /* Return the type of move that should be used for integer I. */
2728 m68k_const_method (HOST_WIDE_INT i
)
2735 /* The ColdFire doesn't have byte or word operations. */
2736 /* FIXME: This may not be useful for the m68060 either. */
2737 if (!TARGET_COLDFIRE
)
2739 /* if -256 < N < 256 but N is not in range for a moveq
2740 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2741 if (USE_MOVQ (i
^ 0xff))
2743 /* Likewise, try with not.w */
2744 if (USE_MOVQ (i
^ 0xffff))
2746 /* This is the only value where neg.w is useful */
2751 /* Try also with swap. */
2753 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2758 /* Try using MVZ/MVS with an immediate value to load constants. */
2759 if (i
>= 0 && i
<= 65535)
2761 if (i
>= -32768 && i
<= 32767)
2765 /* Otherwise, use move.l */
2769 /* Return the cost of moving constant I into a data register. */
2772 const_int_cost (HOST_WIDE_INT i
)
2774 switch (m68k_const_method (i
))
2777 /* Constants between -128 and 127 are cheap due to moveq. */
2785 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2795 m68k_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2796 int opno ATTRIBUTE_UNUSED
,
2797 int *total
, bool speed ATTRIBUTE_UNUSED
)
2799 int code
= GET_CODE (x
);
2804 /* Constant zero is super cheap due to clr instruction. */
2805 if (x
== const0_rtx
)
2808 *total
= const_int_cost (INTVAL (x
));
2818 /* Make 0.0 cheaper than other floating constants to
2819 encourage creating tstsf and tstdf insns. */
2820 if (outer_code
== COMPARE
2821 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2827 /* These are vaguely right for a 68020. */
2828 /* The costs for long multiply have been adjusted to work properly
2829 in synth_mult on the 68020, relative to an average of the time
2830 for add and the time for shift, taking away a little more because
2831 sometimes move insns are needed. */
2832 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2837 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2838 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2840 : TARGET_COLDFIRE ? 3 : 13)
2845 : TUNE_68000_10 ? 5 \
2846 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2847 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2849 : TARGET_COLDFIRE ? 2 : 8)
2852 (TARGET_CF_HWDIV ? 11 \
2853 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2856 /* An lea costs about three times as much as a simple add. */
2858 && GET_CODE (XEXP (x
, 1)) == REG
2859 && GET_CODE (XEXP (x
, 0)) == MULT
2860 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2861 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2862 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2863 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2864 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2866 /* lea an@(dx:l:i),am */
2867 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2877 *total
= COSTS_N_INSNS(1);
2882 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2884 if (INTVAL (XEXP (x
, 1)) < 16)
2885 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2887 /* We're using clrw + swap for these cases. */
2888 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2891 *total
= COSTS_N_INSNS (10); /* Worst case. */
2894 /* A shift by a big integer takes an extra instruction. */
2895 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2896 && (INTVAL (XEXP (x
, 1)) == 16))
2898 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2901 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2902 && !(INTVAL (XEXP (x
, 1)) > 0
2903 && INTVAL (XEXP (x
, 1)) <= 8))
2905 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2911 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2912 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2914 *total
= COSTS_N_INSNS (MULW_COST
);
2915 else if (mode
== QImode
|| mode
== HImode
)
2916 *total
= COSTS_N_INSNS (MULW_COST
);
2918 *total
= COSTS_N_INSNS (MULL_COST
);
2925 if (mode
== QImode
|| mode
== HImode
)
2926 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2927 else if (TARGET_CF_HWDIV
)
2928 *total
= COSTS_N_INSNS (18);
2930 *total
= COSTS_N_INSNS (43); /* div.l */
2934 if (outer_code
== COMPARE
)
2943 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2947 output_move_const_into_data_reg (rtx
*operands
)
2951 i
= INTVAL (operands
[1]);
2952 switch (m68k_const_method (i
))
2955 return "mvzw %1,%0";
2957 return "mvsw %1,%0";
2959 return "moveq %1,%0";
2962 operands
[1] = GEN_INT (i
^ 0xff);
2963 return "moveq %1,%0\n\tnot%.b %0";
2966 operands
[1] = GEN_INT (i
^ 0xffff);
2967 return "moveq %1,%0\n\tnot%.w %0";
2970 return "moveq #-128,%0\n\tneg%.w %0";
2975 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2976 return "moveq %1,%0\n\tswap %0";
2979 return "move%.l %1,%0";
2985 /* Return true if I can be handled by ISA B's mov3q instruction. */
2988 valid_mov3q_const (HOST_WIDE_INT i
)
2990 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2993 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2994 I is the value of OPERANDS[1]. */
2997 output_move_simode_const (rtx
*operands
)
3003 src
= INTVAL (operands
[1]);
3005 && (DATA_REG_P (dest
) || MEM_P (dest
))
3006 /* clr insns on 68000 read before writing. */
3007 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3008 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3010 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3011 return "mov3q%.l %1,%0";
3012 else if (src
== 0 && ADDRESS_REG_P (dest
))
3013 return "sub%.l %0,%0";
3014 else if (DATA_REG_P (dest
))
3015 return output_move_const_into_data_reg (operands
);
3016 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3018 if (valid_mov3q_const (src
))
3019 return "mov3q%.l %1,%0";
3020 return "move%.w %1,%0";
3022 else if (MEM_P (dest
)
3023 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3024 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3025 && IN_RANGE (src
, -0x8000, 0x7fff))
3027 if (valid_mov3q_const (src
))
3028 return "mov3q%.l %1,%-";
3031 return "move%.l %1,%0";
3035 output_move_simode (rtx
*operands
)
3037 if (GET_CODE (operands
[1]) == CONST_INT
)
3038 return output_move_simode_const (operands
);
3039 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3040 || GET_CODE (operands
[1]) == CONST
)
3041 && push_operand (operands
[0], SImode
))
3043 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3044 || GET_CODE (operands
[1]) == CONST
)
3045 && ADDRESS_REG_P (operands
[0]))
3046 return "lea %a1,%0";
3047 return "move%.l %1,%0";
3051 output_move_himode (rtx
*operands
)
3053 if (GET_CODE (operands
[1]) == CONST_INT
)
3055 if (operands
[1] == const0_rtx
3056 && (DATA_REG_P (operands
[0])
3057 || GET_CODE (operands
[0]) == MEM
)
3058 /* clr insns on 68000 read before writing. */
3059 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3060 || !(GET_CODE (operands
[0]) == MEM
3061 && MEM_VOLATILE_P (operands
[0]))))
3063 else if (operands
[1] == const0_rtx
3064 && ADDRESS_REG_P (operands
[0]))
3065 return "sub%.l %0,%0";
3066 else if (DATA_REG_P (operands
[0])
3067 && INTVAL (operands
[1]) < 128
3068 && INTVAL (operands
[1]) >= -128)
3069 return "moveq %1,%0";
3070 else if (INTVAL (operands
[1]) < 0x8000
3071 && INTVAL (operands
[1]) >= -0x8000)
3072 return "move%.w %1,%0";
3074 else if (CONSTANT_P (operands
[1]))
3075 return "move%.l %1,%0";
3076 return "move%.w %1,%0";
3080 output_move_qimode (rtx
*operands
)
3082 /* 68k family always modifies the stack pointer by at least 2, even for
3083 byte pushes. The 5200 (ColdFire) does not do this. */
3085 /* This case is generated by pushqi1 pattern now. */
3086 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3087 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3088 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3089 && ! ADDRESS_REG_P (operands
[1])
3090 && ! TARGET_COLDFIRE
));
3092 /* clr and st insns on 68000 read before writing. */
3093 if (!ADDRESS_REG_P (operands
[0])
3094 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3095 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3097 if (operands
[1] == const0_rtx
)
3099 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3100 && GET_CODE (operands
[1]) == CONST_INT
3101 && (INTVAL (operands
[1]) & 255) == 255)
3107 if (GET_CODE (operands
[1]) == CONST_INT
3108 && DATA_REG_P (operands
[0])
3109 && INTVAL (operands
[1]) < 128
3110 && INTVAL (operands
[1]) >= -128)
3111 return "moveq %1,%0";
3112 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3113 return "sub%.l %0,%0";
3114 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3115 return "move%.l %1,%0";
3116 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3117 from address registers. */
3118 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3119 return "move%.w %1,%0";
3120 return "move%.b %1,%0";
3124 output_move_stricthi (rtx
*operands
)
3126 if (operands
[1] == const0_rtx
3127 /* clr insns on 68000 read before writing. */
3128 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3129 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3131 return "move%.w %1,%0";
3135 output_move_strictqi (rtx
*operands
)
3137 if (operands
[1] == const0_rtx
3138 /* clr insns on 68000 read before writing. */
3139 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3140 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3142 return "move%.b %1,%0";
3145 /* Return the best assembler insn template
3146 for moving operands[1] into operands[0] as a fullword. */
3149 singlemove_string (rtx
*operands
)
3151 if (GET_CODE (operands
[1]) == CONST_INT
)
3152 return output_move_simode_const (operands
);
3153 return "move%.l %1,%0";
3157 /* Output assembler or rtl code to perform a doubleword move insn
3158 with operands OPERANDS.
3159 Pointers to 3 helper functions should be specified:
3160 HANDLE_REG_ADJUST to adjust a register by a small value,
3161 HANDLE_COMPADR to compute an address and
3162 HANDLE_MOVSI to move 4 bytes. */
3165 handle_move_double (rtx operands
[2],
3166 void (*handle_reg_adjust
) (rtx
, int),
3167 void (*handle_compadr
) (rtx
[2]),
3168 void (*handle_movsi
) (rtx
[2]))
3172 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3177 rtx addreg0
= 0, addreg1
= 0;
3178 int dest_overlapped_low
= 0;
3179 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3184 /* First classify both operands. */
3186 if (REG_P (operands
[0]))
3188 else if (offsettable_memref_p (operands
[0]))
3190 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3192 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3194 else if (GET_CODE (operands
[0]) == MEM
)
3199 if (REG_P (operands
[1]))
3201 else if (CONSTANT_P (operands
[1]))
3203 else if (offsettable_memref_p (operands
[1]))
3205 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3207 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3209 else if (GET_CODE (operands
[1]) == MEM
)
3214 /* Check for the cases that the operand constraints are not supposed
3215 to allow to happen. Generating code for these cases is
3217 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3219 /* If one operand is decrementing and one is incrementing
3220 decrement the former register explicitly
3221 and change that operand into ordinary indexing. */
3223 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3225 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3227 handle_reg_adjust (operands
[0], -size
);
3229 if (GET_MODE (operands
[1]) == XFmode
)
3230 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3231 else if (GET_MODE (operands
[0]) == DFmode
)
3232 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3234 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3237 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3239 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3241 handle_reg_adjust (operands
[1], -size
);
3243 if (GET_MODE (operands
[1]) == XFmode
)
3244 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3245 else if (GET_MODE (operands
[1]) == DFmode
)
3246 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3248 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3252 /* If an operand is an unoffsettable memory ref, find a register
3253 we can increment temporarily to make it refer to the second word. */
3255 if (optype0
== MEMOP
)
3256 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3258 if (optype1
== MEMOP
)
3259 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3261 /* Ok, we can do one word at a time.
3262 Normally we do the low-numbered word first,
3263 but if either operand is autodecrementing then we
3264 do the high-numbered word first.
3266 In either case, set up in LATEHALF the operands to use
3267 for the high-numbered word and in some cases alter the
3268 operands in OPERANDS to be suitable for the low-numbered word. */
3272 if (optype0
== REGOP
)
3274 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3275 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3277 else if (optype0
== OFFSOP
)
3279 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3280 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3284 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3285 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3288 if (optype1
== REGOP
)
3290 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3291 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3293 else if (optype1
== OFFSOP
)
3295 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3296 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3298 else if (optype1
== CNSTOP
)
3300 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3304 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3305 (*CONST_DOUBLE_REAL_VALUE (operands
[1]), l
);
3306 operands
[1] = GEN_INT (l
[0]);
3307 middlehalf
[1] = GEN_INT (l
[1]);
3308 latehalf
[1] = GEN_INT (l
[2]);
3312 /* No non-CONST_DOUBLE constant should ever appear
3314 gcc_assert (!CONSTANT_P (operands
[1]));
3319 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3320 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3324 /* size is not 12: */
3326 if (optype0
== REGOP
)
3327 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3328 else if (optype0
== OFFSOP
)
3329 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3331 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3333 if (optype1
== REGOP
)
3334 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3335 else if (optype1
== OFFSOP
)
3336 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3337 else if (optype1
== CNSTOP
)
3338 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3340 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3343 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3344 word first. We should use the adjusted operand 1 (which is N+4(REG))
3345 for the low word as well, to compensate for the first decrement of
3347 if (optype0
== PUSHOP
3348 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3349 operands
[1] = middlehalf
[1] = latehalf
[1];
3351 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3352 if the upper part of reg N does not appear in the MEM, arrange to
3353 emit the move late-half first. Otherwise, compute the MEM address
3354 into the upper part of N and use that as a pointer to the memory
3356 if (optype0
== REGOP
3357 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3359 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3361 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3362 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3364 /* If both halves of dest are used in the src memory address,
3365 compute the address into latehalf of dest.
3366 Note that this can't happen if the dest is two data regs. */
3368 xops
[0] = latehalf
[0];
3369 xops
[1] = XEXP (operands
[1], 0);
3371 handle_compadr (xops
);
3372 if (GET_MODE (operands
[1]) == XFmode
)
3374 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3375 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3376 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3380 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3381 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3385 && reg_overlap_mentioned_p (middlehalf
[0],
3386 XEXP (operands
[1], 0)))
3388 /* Check for two regs used by both source and dest.
3389 Note that this can't happen if the dest is all data regs.
3390 It can happen if the dest is d6, d7, a0.
3391 But in that case, latehalf is an addr reg, so
3392 the code at compadr does ok. */
3394 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3395 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3398 /* JRV says this can't happen: */
3399 gcc_assert (!addreg0
&& !addreg1
);
3401 /* Only the middle reg conflicts; simply put it last. */
3402 handle_movsi (operands
);
3403 handle_movsi (latehalf
);
3404 handle_movsi (middlehalf
);
3408 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3409 /* If the low half of dest is mentioned in the source memory
3410 address, the arrange to emit the move late half first. */
3411 dest_overlapped_low
= 1;
3414 /* If one or both operands autodecrementing,
3415 do the two words, high-numbered first. */
3417 /* Likewise, the first move would clobber the source of the second one,
3418 do them in the other order. This happens only for registers;
3419 such overlap can't happen in memory unless the user explicitly
3420 sets it up, and that is an undefined circumstance. */
3422 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3423 || (optype0
== REGOP
&& optype1
== REGOP
3424 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3425 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3426 || dest_overlapped_low
)
3428 /* Make any unoffsettable addresses point at high-numbered word. */
3430 handle_reg_adjust (addreg0
, size
- 4);
3432 handle_reg_adjust (addreg1
, size
- 4);
3435 handle_movsi (latehalf
);
3437 /* Undo the adds we just did. */
3439 handle_reg_adjust (addreg0
, -4);
3441 handle_reg_adjust (addreg1
, -4);
3445 handle_movsi (middlehalf
);
3448 handle_reg_adjust (addreg0
, -4);
3450 handle_reg_adjust (addreg1
, -4);
3453 /* Do low-numbered word. */
3455 handle_movsi (operands
);
3459 /* Normal case: do the two words, low-numbered first. */
3461 m68k_final_prescan_insn (NULL
, operands
, 2);
3462 handle_movsi (operands
);
3464 /* Do the middle one of the three words for long double */
3468 handle_reg_adjust (addreg0
, 4);
3470 handle_reg_adjust (addreg1
, 4);
3472 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3473 handle_movsi (middlehalf
);
3476 /* Make any unoffsettable addresses point at high-numbered word. */
3478 handle_reg_adjust (addreg0
, 4);
3480 handle_reg_adjust (addreg1
, 4);
3483 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3484 handle_movsi (latehalf
);
3486 /* Undo the adds we just did. */
3488 handle_reg_adjust (addreg0
, -(size
- 4));
3490 handle_reg_adjust (addreg1
, -(size
- 4));
3495 /* Output assembler code to adjust REG by N. */
3497 output_reg_adjust (rtx reg
, int n
)
3501 gcc_assert (GET_MODE (reg
) == SImode
3502 && -12 <= n
&& n
!= 0 && n
<= 12);
3507 s
= "add%.l #12,%0";
3511 s
= "addq%.l #8,%0";
3515 s
= "addq%.l #4,%0";
3519 s
= "sub%.l #12,%0";
3523 s
= "subq%.l #8,%0";
3527 s
= "subq%.l #4,%0";
3535 output_asm_insn (s
, ®
);
3538 /* Emit rtl code to adjust REG by N. */
3540 emit_reg_adjust (rtx reg1
, int n
)
3544 gcc_assert (GET_MODE (reg1
) == SImode
3545 && -12 <= n
&& n
!= 0 && n
<= 12);
3547 reg1
= copy_rtx (reg1
);
3548 reg2
= copy_rtx (reg1
);
3551 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3553 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3558 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3560 output_compadr (rtx operands
[2])
3562 output_asm_insn ("lea %a1,%0", operands
);
3565 /* Output the best assembler insn for moving operands[1] into operands[0]
3568 output_movsi (rtx operands
[2])
3570 output_asm_insn (singlemove_string (operands
), operands
);
3573 /* Copy OP and change its mode to MODE. */
3575 copy_operand (rtx op
, machine_mode mode
)
3577 /* ??? This looks really ugly. There must be a better way
3578 to change a mode on the operand. */
3579 if (GET_MODE (op
) != VOIDmode
)
3582 op
= gen_rtx_REG (mode
, REGNO (op
));
3586 PUT_MODE (op
, mode
);
3593 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3595 emit_movsi (rtx operands
[2])
3597 operands
[0] = copy_operand (operands
[0], SImode
);
3598 operands
[1] = copy_operand (operands
[1], SImode
);
3600 emit_insn (gen_movsi (operands
[0], operands
[1]));
3603 /* Output assembler code to perform a doubleword move insn
3604 with operands OPERANDS. */
3606 output_move_double (rtx
*operands
)
3608 handle_move_double (operands
,
3609 output_reg_adjust
, output_compadr
, output_movsi
);
3614 /* Output rtl code to perform a doubleword move insn
3615 with operands OPERANDS. */
3617 m68k_emit_move_double (rtx operands
[2])
3619 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3622 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3623 new rtx with the correct mode. */
3626 force_mode (machine_mode mode
, rtx orig
)
3628 if (mode
== GET_MODE (orig
))
3631 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3634 return gen_rtx_REG (mode
, REGNO (orig
));
3638 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3640 return reg_renumber
&& FP_REG_P (op
);
3643 /* Emit insns to move operands[1] into operands[0].
3645 Return 1 if we have written out everything that needs to be done to
3646 do the move. Otherwise, return 0 and the caller will emit the move
3649 Note SCRATCH_REG may not be in the proper mode depending on how it
3650 will be used. This routine is responsible for creating a new copy
3651 of SCRATCH_REG in the proper mode. */
3654 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3656 register rtx operand0
= operands
[0];
3657 register rtx operand1
= operands
[1];
3661 && reload_in_progress
&& GET_CODE (operand0
) == REG
3662 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3663 operand0
= reg_equiv_mem (REGNO (operand0
));
3664 else if (scratch_reg
3665 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3666 && GET_CODE (SUBREG_REG (operand0
)) == REG
3667 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3669 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3670 the code which tracks sets/uses for delete_output_reload. */
3671 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3672 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3673 SUBREG_BYTE (operand0
));
3674 operand0
= alter_subreg (&temp
, true);
3678 && reload_in_progress
&& GET_CODE (operand1
) == REG
3679 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3680 operand1
= reg_equiv_mem (REGNO (operand1
));
3681 else if (scratch_reg
3682 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3683 && GET_CODE (SUBREG_REG (operand1
)) == REG
3684 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3686 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3687 the code which tracks sets/uses for delete_output_reload. */
3688 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3689 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3690 SUBREG_BYTE (operand1
));
3691 operand1
= alter_subreg (&temp
, true);
3694 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3695 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3696 != XEXP (operand0
, 0)))
3697 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3698 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3699 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3700 != XEXP (operand1
, 0)))
3701 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3703 /* Handle secondary reloads for loads/stores of FP registers where
3704 the address is symbolic by using the scratch register */
3705 if (fp_reg_operand (operand0
, mode
)
3706 && ((GET_CODE (operand1
) == MEM
3707 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3708 || ((GET_CODE (operand1
) == SUBREG
3709 && GET_CODE (XEXP (operand1
, 0)) == MEM
3710 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3713 if (GET_CODE (operand1
) == SUBREG
)
3714 operand1
= XEXP (operand1
, 0);
3716 /* SCRATCH_REG will hold an address. We want
3717 it in SImode regardless of what mode it was originally given
3719 scratch_reg
= force_mode (SImode
, scratch_reg
);
3721 /* D might not fit in 14 bits either; for such cases load D into
3723 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3725 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3726 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3728 XEXP (XEXP (operand1
, 0), 0),
3732 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3733 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3736 else if (fp_reg_operand (operand1
, mode
)
3737 && ((GET_CODE (operand0
) == MEM
3738 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3739 || ((GET_CODE (operand0
) == SUBREG
)
3740 && GET_CODE (XEXP (operand0
, 0)) == MEM
3741 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3744 if (GET_CODE (operand0
) == SUBREG
)
3745 operand0
= XEXP (operand0
, 0);
3747 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3748 it in SIMODE regardless of what mode it was originally given
3750 scratch_reg
= force_mode (SImode
, scratch_reg
);
3752 /* D might not fit in 14 bits either; for such cases load D into
3754 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3756 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3757 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3760 XEXP (XEXP (operand0
, 0),
3765 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3766 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3769 /* Handle secondary reloads for loads of FP registers from constant
3770 expressions by forcing the constant into memory.
3772 use scratch_reg to hold the address of the memory location.
3774 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3775 NO_REGS when presented with a const_int and an register class
3776 containing only FP registers. Doing so unfortunately creates
3777 more problems than it solves. Fix this for 2.5. */
3778 else if (fp_reg_operand (operand0
, mode
)
3779 && CONSTANT_P (operand1
)
3784 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3785 it in SIMODE regardless of what mode it was originally given
3787 scratch_reg
= force_mode (SImode
, scratch_reg
);
3789 /* Force the constant into memory and put the address of the
3790 memory location into scratch_reg. */
3791 xoperands
[0] = scratch_reg
;
3792 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3793 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3795 /* Now load the destination register. */
3796 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3800 /* Now have insn-emit do whatever it normally does. */
3804 /* Split one or more DImode RTL references into pairs of SImode
3805 references. The RTL can be REG, offsettable MEM, integer constant, or
3806 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3807 split and "num" is its length. lo_half and hi_half are output arrays
3808 that parallel "operands". */
3811 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3815 rtx op
= operands
[num
];
3817 /* simplify_subreg refuses to split volatile memory addresses,
3818 but we still have to handle it. */
3819 if (GET_CODE (op
) == MEM
)
3821 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3822 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3826 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3827 GET_MODE (op
) == VOIDmode
3828 ? DImode
: GET_MODE (op
), 4);
3829 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3830 GET_MODE (op
) == VOIDmode
3831 ? DImode
: GET_MODE (op
), 0);
3836 /* Split X into a base and a constant offset, storing them in *BASE
3837 and *OFFSET respectively. */
3840 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3843 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3845 *offset
+= INTVAL (XEXP (x
, 1));
3851 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3852 instruction. STORE_P says whether the move is a load or store.
3854 If the instruction uses post-increment or pre-decrement addressing,
3855 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3856 adjustment. This adjustment will be made by the first element of
3857 PARALLEL, with the loads or stores starting at element 1. If the
3858 instruction does not use post-increment or pre-decrement addressing,
3859 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3860 start at element 0. */
3863 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3864 HOST_WIDE_INT automod_offset
, bool store_p
)
3866 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3867 HOST_WIDE_INT offset
, mem_offset
;
3869 enum reg_class rclass
;
3871 len
= XVECLEN (pattern
, 0);
3872 first
= (automod_base
!= NULL
);
3876 /* Stores must be pre-decrement and loads must be post-increment. */
3877 if (store_p
!= (automod_offset
< 0))
3880 /* Work out the base and offset for lowest memory location. */
3881 base
= automod_base
;
3882 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3886 /* Allow any valid base and offset in the first access. */
3893 for (i
= first
; i
< len
; i
++)
3895 /* We need a plain SET. */
3896 set
= XVECEXP (pattern
, 0, i
);
3897 if (GET_CODE (set
) != SET
)
3900 /* Check that we have a memory location... */
3901 mem
= XEXP (set
, !store_p
);
3902 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3905 /* ...with the right address. */
3908 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3909 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3910 There are no mode restrictions for 680x0 besides the
3911 automodification rules enforced above. */
3913 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3918 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3919 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3923 /* Check that we have a register of the required mode and class. */
3924 reg
= XEXP (set
, store_p
);
3926 || !HARD_REGISTER_P (reg
)
3927 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3932 /* The register must belong to RCLASS and have a higher number
3933 than the register in the previous SET. */
3934 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3935 || REGNO (last_reg
) >= REGNO (reg
))
3940 /* Work out which register class we need. */
3941 if (INT_REGNO_P (REGNO (reg
)))
3942 rclass
= GENERAL_REGS
;
3943 else if (FP_REGNO_P (REGNO (reg
)))
3950 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3953 /* If we have an automodification, check whether the final offset is OK. */
3954 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3957 /* Reject unprofitable cases. */
3958 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3964 /* Return the assembly code template for a movem or fmovem instruction
3965 whose pattern is given by PATTERN. Store the template's operands
3968 If the instruction uses post-increment or pre-decrement addressing,
3969 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3970 is true if this is a store instruction. */
3973 m68k_output_movem (rtx
*operands
, rtx pattern
,
3974 HOST_WIDE_INT automod_offset
, bool store_p
)
3979 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3981 first
= (automod_offset
!= 0);
3982 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3984 /* When using movem with pre-decrement addressing, register X + D0_REG
3985 is controlled by bit 15 - X. For all other addressing modes,
3986 register X + D0_REG is controlled by bit X. Confusingly, the
3987 register mask for fmovem is in the opposite order to that for
3991 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3992 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3993 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3994 if (automod_offset
< 0)
3996 if (FP_REGNO_P (regno
))
3997 mask
|= 1 << (regno
- FP0_REG
);
3999 mask
|= 1 << (15 - (regno
- D0_REG
));
4003 if (FP_REGNO_P (regno
))
4004 mask
|= 1 << (7 - (regno
- FP0_REG
));
4006 mask
|= 1 << (regno
- D0_REG
);
4011 if (automod_offset
== 0)
4012 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4013 else if (automod_offset
< 0)
4014 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4016 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4017 operands
[1] = GEN_INT (mask
);
4018 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4021 return "fmovem %1,%a0";
4023 return "fmovem %a0,%1";
4028 return "movem%.l %1,%a0";
4030 return "movem%.l %a0,%1";
4034 /* Return a REG that occurs in ADDR with coefficient 1.
4035 ADDR can be effectively incremented by incrementing REG. */
4038 find_addr_reg (rtx addr
)
4040 while (GET_CODE (addr
) == PLUS
)
4042 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4043 addr
= XEXP (addr
, 0);
4044 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4045 addr
= XEXP (addr
, 1);
4046 else if (CONSTANT_P (XEXP (addr
, 0)))
4047 addr
= XEXP (addr
, 1);
4048 else if (CONSTANT_P (XEXP (addr
, 1)))
4049 addr
= XEXP (addr
, 0);
4053 gcc_assert (GET_CODE (addr
) == REG
);
4057 /* Output assembler code to perform a 32-bit 3-operand add. */
4060 output_addsi3 (rtx
*operands
)
4062 if (! operands_match_p (operands
[0], operands
[1]))
4064 if (!ADDRESS_REG_P (operands
[1]))
4066 rtx tmp
= operands
[1];
4068 operands
[1] = operands
[2];
4072 /* These insns can result from reloads to access
4073 stack slots over 64k from the frame pointer. */
4074 if (GET_CODE (operands
[2]) == CONST_INT
4075 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4076 return "move%.l %2,%0\n\tadd%.l %1,%0";
4077 if (GET_CODE (operands
[2]) == REG
)
4078 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4079 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4081 if (GET_CODE (operands
[2]) == CONST_INT
)
4083 if (INTVAL (operands
[2]) > 0
4084 && INTVAL (operands
[2]) <= 8)
4085 return "addq%.l %2,%0";
4086 if (INTVAL (operands
[2]) < 0
4087 && INTVAL (operands
[2]) >= -8)
4089 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4090 return "subq%.l %2,%0";
4092 /* On the CPU32 it is faster to use two addql instructions to
4093 add a small integer (8 < N <= 16) to a register.
4094 Likewise for subql. */
4095 if (TUNE_CPU32
&& REG_P (operands
[0]))
4097 if (INTVAL (operands
[2]) > 8
4098 && INTVAL (operands
[2]) <= 16)
4100 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4101 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4103 if (INTVAL (operands
[2]) < -8
4104 && INTVAL (operands
[2]) >= -16)
4106 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4107 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4110 if (ADDRESS_REG_P (operands
[0])
4111 && INTVAL (operands
[2]) >= -0x8000
4112 && INTVAL (operands
[2]) < 0x8000)
4115 return "add%.w %2,%0";
4117 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4120 return "add%.l %2,%0";
4123 /* Store in cc_status the expressions that the condition codes will
4124 describe after execution of an instruction whose pattern is EXP.
4125 Do not alter them if the instruction would not alter the cc's. */
4127 /* On the 68000, all the insns to store in an address register fail to
4128 set the cc's. However, in some cases these instructions can make it
4129 possibly invalid to use the saved cc's. In those cases we clear out
4130 some or all of the saved cc's so they won't be used. */
4133 notice_update_cc (rtx exp
, rtx insn
)
4135 if (GET_CODE (exp
) == SET
)
4137 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4139 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4141 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4142 cc_status
.value1
= 0;
4143 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4144 cc_status
.value2
= 0;
4146 /* fmoves to memory or data registers do not set the condition
4147 codes. Normal moves _do_ set the condition codes, but not in
4148 a way that is appropriate for comparison with 0, because -0.0
4149 would be treated as a negative nonzero number. Note that it
4150 isn't appropriate to conditionalize this restriction on
4151 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4152 we care about the difference between -0.0 and +0.0. */
4153 else if (!FP_REG_P (SET_DEST (exp
))
4154 && SET_DEST (exp
) != cc0_rtx
4155 && (FP_REG_P (SET_SRC (exp
))
4156 || GET_CODE (SET_SRC (exp
)) == FIX
4157 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4159 /* A pair of move insns doesn't produce a useful overall cc. */
4160 else if (!FP_REG_P (SET_DEST (exp
))
4161 && !FP_REG_P (SET_SRC (exp
))
4162 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4163 && (GET_CODE (SET_SRC (exp
)) == REG
4164 || GET_CODE (SET_SRC (exp
)) == MEM
4165 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4167 else if (SET_DEST (exp
) != pc_rtx
)
4169 cc_status
.flags
= 0;
4170 cc_status
.value1
= SET_DEST (exp
);
4171 cc_status
.value2
= SET_SRC (exp
);
4174 else if (GET_CODE (exp
) == PARALLEL
4175 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4177 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4178 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4180 if (ADDRESS_REG_P (dest
))
4182 else if (dest
!= pc_rtx
)
4184 cc_status
.flags
= 0;
4185 cc_status
.value1
= dest
;
4186 cc_status
.value2
= src
;
4191 if (cc_status
.value2
!= 0
4192 && ADDRESS_REG_P (cc_status
.value2
)
4193 && GET_MODE (cc_status
.value2
) == QImode
)
4195 if (cc_status
.value2
!= 0)
4196 switch (GET_CODE (cc_status
.value2
))
4198 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4199 case ROTATE
: case ROTATERT
:
4200 /* These instructions always clear the overflow bit, and set
4201 the carry to the bit shifted out. */
4202 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4205 case PLUS
: case MINUS
: case MULT
:
4206 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4207 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4208 cc_status
.flags
|= CC_NO_OVERFLOW
;
4211 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4212 ends with a move insn moving r2 in r2's mode.
4213 Thus, the cc's are set for r2.
4214 This can set N bit spuriously. */
4215 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4220 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4222 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4223 cc_status
.value2
= 0;
4224 /* Check for PRE_DEC in dest modifying a register used in src. */
4225 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4226 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4228 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4230 cc_status
.value2
= 0;
4231 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4232 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4233 cc_status
.flags
= CC_IN_68881
;
4234 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4235 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4237 cc_status
.flags
= CC_IN_68881
;
4238 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4239 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4240 cc_status
.flags
|= CC_REVERSED
;
4245 output_move_const_double (rtx
*operands
)
4247 int code
= standard_68881_constant_p (operands
[1]);
4251 static char buf
[40];
4253 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4256 return "fmove%.d %1,%0";
4260 output_move_const_single (rtx
*operands
)
4262 int code
= standard_68881_constant_p (operands
[1]);
4266 static char buf
[40];
4268 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4271 return "fmove%.s %f1,%0";
4274 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4275 from the "fmovecr" instruction.
4276 The value, anded with 0xff, gives the code to use in fmovecr
4277 to get the desired constant. */
4279 /* This code has been fixed for cross-compilation. */
4281 static int inited_68881_table
= 0;
4283 static const char *const strings_68881
[7] = {
4293 static const int codes_68881
[7] = {
4303 REAL_VALUE_TYPE values_68881
[7];
4305 /* Set up values_68881 array by converting the decimal values
4306 strings_68881 to binary. */
4309 init_68881_table (void)
4316 for (i
= 0; i
< 7; i
++)
4320 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4321 values_68881
[i
] = r
;
4323 inited_68881_table
= 1;
4327 standard_68881_constant_p (rtx x
)
4329 const REAL_VALUE_TYPE
*r
;
4332 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4333 used at all on those chips. */
4337 if (! inited_68881_table
)
4338 init_68881_table ();
4340 r
= CONST_DOUBLE_REAL_VALUE (x
);
4342 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4343 for (i
= 0; i
< 6; i
++)
4345 if (real_identical (r
, &values_68881
[i
]))
4346 return (codes_68881
[i
]);
4349 if (GET_MODE (x
) == SFmode
)
4352 if (real_equal (r
, &values_68881
[6]))
4353 return (codes_68881
[6]);
4355 /* larger powers of ten in the constants ram are not used
4356 because they are not equal to a `double' C constant. */
4360 /* If X is a floating-point constant, return the logarithm of X base 2,
4361 or 0 if X is not a power of 2. */
4364 floating_exact_log2 (rtx x
)
4366 const REAL_VALUE_TYPE
*r
;
4370 r
= CONST_DOUBLE_REAL_VALUE (x
);
4372 if (real_less (r
, &dconst1
))
4375 exp
= real_exponent (r
);
4376 real_2expN (&r1
, exp
, DFmode
);
4377 if (real_equal (&r1
, r
))
4383 /* A C compound statement to output to stdio stream STREAM the
4384 assembler syntax for an instruction operand X. X is an RTL
4387 CODE is a value that can be used to specify one of several ways
4388 of printing the operand. It is used when identical operands
4389 must be printed differently depending on the context. CODE
4390 comes from the `%' specification that was used to request
4391 printing of the operand. If the specification was just `%DIGIT'
4392 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4393 is the ASCII code for LTR.
4395 If X is a register, this macro should print the register's name.
4396 The names can be found in an array `reg_names' whose type is
4397 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4399 When the machine description has a specification `%PUNCT' (a `%'
4400 followed by a punctuation character), this macro is called with
4401 a null pointer for X and the punctuation character for CODE.
4403 The m68k specific codes are:
4405 '.' for dot needed in Motorola-style opcode names.
4406 '-' for an operand pushing on the stack:
4407 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4408 '+' for an operand pushing on the stack:
4409 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4410 '@' for a reference to the top word on the stack:
4411 sp@, (sp) or (%sp) depending on the style of syntax.
4412 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4413 but & in SGS syntax).
4414 '!' for the cc register (used in an `and to cc' insn).
4415 '$' for the letter `s' in an op code, but only on the 68040.
4416 '&' for the letter `d' in an op code, but only on the 68040.
4417 '/' for register prefix needed by longlong.h.
4418 '?' for m68k_library_id_string
4420 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4421 'd' to force memory addressing to be absolute, not relative.
4422 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4423 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4424 or print pair of registers as rx:ry.
4425 'p' print an address with @PLTPC attached, but only if the operand
4426 is not locally-bound. */
4429 print_operand (FILE *file
, rtx op
, int letter
)
4434 fprintf (file
, ".");
4436 else if (letter
== '#')
4437 asm_fprintf (file
, "%I");
4438 else if (letter
== '-')
4439 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4440 else if (letter
== '+')
4441 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4442 else if (letter
== '@')
4443 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4444 else if (letter
== '!')
4445 asm_fprintf (file
, "%Rfpcr");
4446 else if (letter
== '$')
4449 fprintf (file
, "s");
4451 else if (letter
== '&')
4454 fprintf (file
, "d");
4456 else if (letter
== '/')
4457 asm_fprintf (file
, "%R");
4458 else if (letter
== '?')
4459 asm_fprintf (file
, m68k_library_id_string
);
4460 else if (letter
== 'p')
4462 output_addr_const (file
, op
);
4463 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4464 fprintf (file
, "@PLTPC");
4466 else if (GET_CODE (op
) == REG
)
4469 /* Print out the second register name of a register pair.
4470 I.e., R (6) => 7. */
4471 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4473 fputs (M68K_REGNAME(REGNO (op
)), file
);
4475 else if (GET_CODE (op
) == MEM
)
4477 output_address (GET_MODE (op
), XEXP (op
, 0));
4478 if (letter
== 'd' && ! TARGET_68020
4479 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4480 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4481 && INTVAL (XEXP (op
, 0)) < 0x8000
4482 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4483 fprintf (file
, MOTOROLA
? ".l" : ":l");
4485 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4488 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4489 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4491 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4494 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4495 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4496 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4498 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4501 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4502 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4506 /* Use `print_operand_address' instead of `output_addr_const'
4507 to ensure that we print relevant PIC stuff. */
4508 asm_fprintf (file
, "%I");
4510 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4511 print_operand_address (file
, op
);
4513 output_addr_const (file
, op
);
4517 /* Return string for TLS relocation RELOC. */
4520 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4522 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4523 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4530 if (flag_pic
== 1 && TARGET_68020
)
4571 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4574 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4576 if (GET_CODE (x
) == UNSPEC
)
4578 switch (XINT (x
, 1))
4580 case UNSPEC_RELOC16
:
4581 case UNSPEC_RELOC32
:
4582 output_addr_const (file
, XVECEXP (x
, 0, 0));
4583 fputs (m68k_get_reloc_decoration
4584 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4595 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4598 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4600 gcc_assert (size
== 4);
4601 fputs ("\t.long\t", file
);
4602 output_addr_const (file
, x
);
4603 fputs ("@TLSLDO+0x8000", file
);
4606 /* In the name of slightly smaller debug output, and to cater to
4607 general assembler lossage, recognize various UNSPEC sequences
4608 and turn them back into a direct symbol reference. */
4611 m68k_delegitimize_address (rtx orig_x
)
4614 struct m68k_address addr
;
4617 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4622 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4625 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4626 || addr
.offset
== NULL_RTX
4627 || GET_CODE (addr
.offset
) != CONST
)
4630 unspec
= XEXP (addr
.offset
, 0);
4631 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4632 unspec
= XEXP (unspec
, 0);
4633 if (GET_CODE (unspec
) != UNSPEC
4634 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4635 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4637 x
= XVECEXP (unspec
, 0, 0);
4638 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4639 if (unspec
!= XEXP (addr
.offset
, 0))
4640 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4643 rtx idx
= addr
.index
;
4644 if (addr
.scale
!= 1)
4645 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4646 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4649 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4651 x
= replace_equiv_address_nv (orig_x
, x
);
4656 /* A C compound statement to output to stdio stream STREAM the
4657 assembler syntax for an instruction operand that is a memory
4658 reference whose address is ADDR. ADDR is an RTL expression.
4660 Note that this contains a kludge that knows that the only reason
4661 we have an address (plus (label_ref...) (reg...)) when not generating
4662 PIC code is in the insn before a tablejump, and we know that m68k.md
4663 generates a label LInnn: on such an insn.
4665 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4666 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4668 This routine is responsible for distinguishing between -fpic and -fPIC
4669 style relocations in an address. When generating -fpic code the
4670 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4671 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4674 print_operand_address (FILE *file
, rtx addr
)
4676 struct m68k_address address
;
4678 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4681 if (address
.code
== PRE_DEC
)
4682 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4683 M68K_REGNAME (REGNO (address
.base
)));
4684 else if (address
.code
== POST_INC
)
4685 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4686 M68K_REGNAME (REGNO (address
.base
)));
4687 else if (!address
.base
&& !address
.index
)
4689 /* A constant address. */
4690 gcc_assert (address
.offset
== addr
);
4691 if (GET_CODE (addr
) == CONST_INT
)
4693 /* (xxx).w or (xxx).l. */
4694 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4695 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4697 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4699 else if (TARGET_PCREL
)
4701 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4703 output_addr_const (file
, addr
);
4704 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4708 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4709 name ends in `.<letter>', as the last 2 characters can be
4710 mistaken as a size suffix. Put the name in parentheses. */
4711 if (GET_CODE (addr
) == SYMBOL_REF
4712 && strlen (XSTR (addr
, 0)) > 2
4713 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4716 output_addr_const (file
, addr
);
4720 output_addr_const (file
, addr
);
4727 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4728 label being accessed, otherwise it is -1. */
4729 labelno
= (address
.offset
4731 && GET_CODE (address
.offset
) == LABEL_REF
4732 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4736 /* Print the "offset(base" component. */
4738 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4742 output_addr_const (file
, address
.offset
);
4746 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4748 /* Print the ",index" component, if any. */
4753 fprintf (file
, "%s.%c",
4754 M68K_REGNAME (REGNO (address
.index
)),
4755 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4756 if (address
.scale
!= 1)
4757 fprintf (file
, "*%d", address
.scale
);
4761 else /* !MOTOROLA */
4763 if (!address
.offset
&& !address
.index
)
4764 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4767 /* Print the "base@(offset" component. */
4769 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4773 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4774 fprintf (file
, "@(");
4776 output_addr_const (file
, address
.offset
);
4778 /* Print the ",index" component, if any. */
4781 fprintf (file
, ",%s:%c",
4782 M68K_REGNAME (REGNO (address
.index
)),
4783 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4784 if (address
.scale
!= 1)
4785 fprintf (file
, ":%d", address
.scale
);
4793 /* Check for cases where a clr insns can be omitted from code using
4794 strict_low_part sets. For example, the second clrl here is not needed:
4795 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4797 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4798 insn we are checking for redundancy. TARGET is the register set by the
4802 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4805 rtx_insn
*p
= first_insn
;
4807 while ((p
= PREV_INSN (p
)))
4809 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4815 /* If it isn't an insn, then give up. */
4819 if (reg_set_p (target
, p
))
4821 rtx set
= single_set (p
);
4824 /* If it isn't an easy to recognize insn, then give up. */
4828 dest
= SET_DEST (set
);
4830 /* If this sets the entire target register to zero, then our
4831 first_insn is redundant. */
4832 if (rtx_equal_p (dest
, target
)
4833 && SET_SRC (set
) == const0_rtx
)
4835 else if (GET_CODE (dest
) == STRICT_LOW_PART
4836 && GET_CODE (XEXP (dest
, 0)) == REG
4837 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4838 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4839 <= GET_MODE_SIZE (mode
)))
4840 /* This is a strict low part set which modifies less than
4841 we are using, so it is safe. */
4851 /* Operand predicates for implementing asymmetric pc-relative addressing
4852 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4853 when used as a source operand, but not as a destination operand.
4855 We model this by restricting the meaning of the basic predicates
4856 (general_operand, memory_operand, etc) to forbid the use of this
4857 addressing mode, and then define the following predicates that permit
4858 this addressing mode. These predicates can then be used for the
4859 source operands of the appropriate instructions.
4861 n.b. While it is theoretically possible to change all machine patterns
4862 to use this addressing more where permitted by the architecture,
4863 it has only been implemented for "common" cases: SImode, HImode, and
4864 QImode operands, and only for the principle operations that would
4865 require this addressing mode: data movement and simple integer operations.
4867 In parallel with these new predicates, two new constraint letters
4868 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4869 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4870 In the pcrel case 's' is only valid in combination with 'a' registers.
4871 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4872 of how these constraints are used.
4874 The use of these predicates is strictly optional, though patterns that
4875 don't will cause an extra reload register to be allocated where one
4878 lea (abc:w,%pc),%a0 ; need to reload address
4879 moveq &1,%d1 ; since write to pc-relative space
4880 movel %d1,%a0@ ; is not allowed
4882 lea (abc:w,%pc),%a1 ; no need to reload address here
4883 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4885 For more info, consult tiemann@cygnus.com.
4888 All of the ugliness with predicates and constraints is due to the
4889 simple fact that the m68k does not allow a pc-relative addressing
4890 mode as a destination. gcc does not distinguish between source and
4891 destination addresses. Hence, if we claim that pc-relative address
4892 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4893 end up with invalid code. To get around this problem, we left
4894 pc-relative modes as invalid addresses, and then added special
4895 predicates and constraints to accept them.
4897 A cleaner way to handle this is to modify gcc to distinguish
4898 between source and destination addresses. We can then say that
4899 pc-relative is a valid source address but not a valid destination
4900 address, and hopefully avoid a lot of the predicate and constraint
4901 hackery. Unfortunately, this would be a pretty big change. It would
4902 be a useful change for a number of ports, but there aren't any current
4903 plans to undertake this.
4905 ***************************************************************************/
4909 output_andsi3 (rtx
*operands
)
4912 if (GET_CODE (operands
[2]) == CONST_INT
4913 && (INTVAL (operands
[2]) | 0xffff) == -1
4914 && (DATA_REG_P (operands
[0])
4915 || offsettable_memref_p (operands
[0]))
4916 && !TARGET_COLDFIRE
)
4918 if (GET_CODE (operands
[0]) != REG
)
4919 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4920 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4921 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4923 if (operands
[2] == const0_rtx
)
4925 return "and%.w %2,%0";
4927 if (GET_CODE (operands
[2]) == CONST_INT
4928 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4929 && (DATA_REG_P (operands
[0])
4930 || offsettable_memref_p (operands
[0])))
4932 if (DATA_REG_P (operands
[0]))
4933 operands
[1] = GEN_INT (logval
);
4936 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4937 operands
[1] = GEN_INT (logval
% 8);
4939 /* This does not set condition codes in a standard way. */
4941 return "bclr %1,%0";
4943 return "and%.l %2,%0";
4947 output_iorsi3 (rtx
*operands
)
4949 register int logval
;
4950 if (GET_CODE (operands
[2]) == CONST_INT
4951 && INTVAL (operands
[2]) >> 16 == 0
4952 && (DATA_REG_P (operands
[0])
4953 || offsettable_memref_p (operands
[0]))
4954 && !TARGET_COLDFIRE
)
4956 if (GET_CODE (operands
[0]) != REG
)
4957 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4958 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4960 if (INTVAL (operands
[2]) == 0xffff)
4961 return "mov%.w %2,%0";
4962 return "or%.w %2,%0";
4964 if (GET_CODE (operands
[2]) == CONST_INT
4965 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4966 && (DATA_REG_P (operands
[0])
4967 || offsettable_memref_p (operands
[0])))
4969 if (DATA_REG_P (operands
[0]))
4970 operands
[1] = GEN_INT (logval
);
4973 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4974 operands
[1] = GEN_INT (logval
% 8);
4977 return "bset %1,%0";
4979 return "or%.l %2,%0";
4983 output_xorsi3 (rtx
*operands
)
4985 register int logval
;
4986 if (GET_CODE (operands
[2]) == CONST_INT
4987 && INTVAL (operands
[2]) >> 16 == 0
4988 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4989 && !TARGET_COLDFIRE
)
4991 if (! DATA_REG_P (operands
[0]))
4992 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4993 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4995 if (INTVAL (operands
[2]) == 0xffff)
4997 return "eor%.w %2,%0";
4999 if (GET_CODE (operands
[2]) == CONST_INT
5000 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5001 && (DATA_REG_P (operands
[0])
5002 || offsettable_memref_p (operands
[0])))
5004 if (DATA_REG_P (operands
[0]))
5005 operands
[1] = GEN_INT (logval
);
5008 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5009 operands
[1] = GEN_INT (logval
% 8);
5012 return "bchg %1,%0";
5014 return "eor%.l %2,%0";
5017 /* Return the instruction that should be used for a call to address X,
5018 which is known to be in operand 0. */
5023 if (symbolic_operand (x
, VOIDmode
))
5024 return m68k_symbolic_call
;
5029 /* Likewise sibling calls. */
5032 output_sibcall (rtx x
)
5034 if (symbolic_operand (x
, VOIDmode
))
5035 return m68k_symbolic_jump
;
5041 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5042 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5045 rtx this_slot
, offset
, addr
, mem
, tmp
;
5048 /* Avoid clobbering the struct value reg by using the
5049 static chain reg as a temporary. */
5050 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5052 /* Pretend to be a post-reload pass while generating rtl. */
5053 reload_completed
= 1;
5055 /* The "this" pointer is stored at 4(%sp). */
5056 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5057 stack_pointer_rtx
, 4));
5059 /* Add DELTA to THIS. */
5062 /* Make the offset a legitimate operand for memory addition. */
5063 offset
= GEN_INT (delta
);
5064 if ((delta
< -8 || delta
> 8)
5065 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5067 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5068 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5070 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5071 copy_rtx (this_slot
), offset
));
5074 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5075 if (vcall_offset
!= 0)
5077 /* Set the static chain register to *THIS. */
5078 emit_move_insn (tmp
, this_slot
);
5079 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5081 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5082 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5083 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5085 emit_insn (gen_rtx_SET (tmp
, addr
));
5089 /* Load the offset into %d0 and add it to THIS. */
5090 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5091 gen_rtx_MEM (Pmode
, addr
));
5092 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5093 copy_rtx (this_slot
),
5094 gen_rtx_REG (Pmode
, D0_REG
)));
5097 /* Jump to the target function. Use a sibcall if direct jumps are
5098 allowed, otherwise load the address into a register first. */
5099 mem
= DECL_RTL (function
);
5100 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5102 gcc_assert (flag_pic
);
5104 if (!TARGET_SEP_DATA
)
5106 /* Use the static chain register as a temporary (call-clobbered)
5107 GOT pointer for this function. We can use the static chain
5108 register because it isn't live on entry to the thunk. */
5109 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5110 emit_insn (gen_load_got (pic_offset_table_rtx
));
5112 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5113 mem
= replace_equiv_address (mem
, tmp
);
5115 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5116 SIBLING_CALL_P (insn
) = 1;
5118 /* Run just enough of rest_of_compilation. */
5119 insn
= get_insns ();
5120 split_all_insns_noflow ();
5121 final_start_function (insn
, file
, 1);
5122 final (insn
, file
, 1);
5123 final_end_function ();
5125 /* Clean up the vars set above. */
5126 reload_completed
= 0;
5128 /* Restore the original PIC register. */
5130 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5133 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5136 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5137 int incoming ATTRIBUTE_UNUSED
)
5139 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5142 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5144 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5145 unsigned int new_reg
)
5148 /* Interrupt functions can only use registers that have already been
5149 saved by the prologue, even if they would normally be
5152 if ((m68k_get_function_kind (current_function_decl
)
5153 == m68k_fk_interrupt_handler
)
5154 && !df_regs_ever_live_p (new_reg
))
5160 /* Value is true if hard register REGNO can hold a value of machine-mode
5161 MODE. On the 68000, we let the cpu registers can hold any mode, but
5162 restrict the 68881 registers to floating-point modes. */
5165 m68k_regno_mode_ok (int regno
, machine_mode mode
)
5167 if (DATA_REGNO_P (regno
))
5169 /* Data Registers, can hold aggregate if fits in. */
5170 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5173 else if (ADDRESS_REGNO_P (regno
))
5175 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5178 else if (FP_REGNO_P (regno
))
5180 /* FPU registers, hold float or complex float of long double or
5182 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5183 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5184 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5190 /* Implement SECONDARY_RELOAD_CLASS. */
5193 m68k_secondary_reload_class (enum reg_class rclass
,
5194 machine_mode mode
, rtx x
)
5198 regno
= true_regnum (x
);
5200 /* If one operand of a movqi is an address register, the other
5201 operand must be a general register or constant. Other types
5202 of operand must be reloaded through a data register. */
5203 if (GET_MODE_SIZE (mode
) == 1
5204 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5205 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5208 /* PC-relative addresses must be loaded into an address register first. */
5210 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5211 && symbolic_operand (x
, VOIDmode
))
5217 /* Implement PREFERRED_RELOAD_CLASS. */
5220 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5222 enum reg_class secondary_class
;
5224 /* If RCLASS might need a secondary reload, try restricting it to
5225 a class that doesn't. */
5226 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5227 if (secondary_class
!= NO_REGS
5228 && reg_class_subset_p (secondary_class
, rclass
))
5229 return secondary_class
;
5231 /* Prefer to use moveq for in-range constants. */
5232 if (GET_CODE (x
) == CONST_INT
5233 && reg_class_subset_p (DATA_REGS
, rclass
)
5234 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5237 /* ??? Do we really need this now? */
5238 if (GET_CODE (x
) == CONST_DOUBLE
5239 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5241 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5250 /* Return floating point values in a 68881 register. This makes 68881 code
5251 a little bit faster. It also makes -msoft-float code incompatible with
5252 hard-float code, so people have to be careful not to mix the two.
5253 For ColdFire it was decided the ABI incompatibility is undesirable.
5254 If there is need for a hard-float ABI it is probably worth doing it
5255 properly and also passing function arguments in FP registers. */
5257 m68k_libcall_value (machine_mode mode
)
5264 return gen_rtx_REG (mode
, FP0_REG
);
5270 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5273 /* Location in which function value is returned.
5274 NOTE: Due to differences in ABIs, don't call this function directly,
5275 use FUNCTION_VALUE instead. */
5277 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5281 mode
= TYPE_MODE (valtype
);
5287 return gen_rtx_REG (mode
, FP0_REG
);
5293 /* If the function returns a pointer, push that into %a0. */
5294 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5295 /* For compatibility with the large body of existing code which
5296 does not always properly declare external functions returning
5297 pointer types, the m68k/SVR4 convention is to copy the value
5298 returned for pointer functions from a0 to d0 in the function
5299 epilogue, so that callers that have neglected to properly
5300 declare the callee can still find the correct return value in
5302 return gen_rtx_PARALLEL
5305 gen_rtx_EXPR_LIST (VOIDmode
,
5306 gen_rtx_REG (mode
, A0_REG
),
5308 gen_rtx_EXPR_LIST (VOIDmode
,
5309 gen_rtx_REG (mode
, D0_REG
),
5311 else if (POINTER_TYPE_P (valtype
))
5312 return gen_rtx_REG (mode
, A0_REG
);
5314 return gen_rtx_REG (mode
, D0_REG
);
5317 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5318 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5320 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5322 machine_mode mode
= TYPE_MODE (type
);
5324 if (mode
== BLKmode
)
5327 /* If TYPE's known alignment is less than the alignment of MODE that
5328 would contain the structure, then return in memory. We need to
5329 do so to maintain the compatibility between code compiled with
5330 -mstrict-align and that compiled with -mno-strict-align. */
5331 if (AGGREGATE_TYPE_P (type
)
5332 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5339 /* CPU to schedule the program for. */
5340 enum attr_cpu m68k_sched_cpu
;
5342 /* MAC to schedule the program for. */
5343 enum attr_mac m68k_sched_mac
;
5351 /* Integer register. */
5357 /* Implicit mem reference (e.g. stack). */
5360 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5363 /* Memory with offset but without indexing. EA mode 5. */
5366 /* Memory with indexing. EA mode 6. */
5369 /* Memory referenced by absolute address. EA mode 7. */
5372 /* Immediate operand that doesn't require extension word. */
5375 /* Immediate 16 bit operand. */
5378 /* Immediate 32 bit operand. */
5382 /* Return type of memory ADDR_RTX refers to. */
5383 static enum attr_op_type
5384 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5386 struct m68k_address address
;
5388 if (symbolic_operand (addr_rtx
, VOIDmode
))
5389 return OP_TYPE_MEM7
;
5391 if (!m68k_decompose_address (mode
, addr_rtx
,
5392 reload_completed
, &address
))
5394 gcc_assert (!reload_completed
);
5395 /* Reload will likely fix the address to be in the register. */
5396 return OP_TYPE_MEM234
;
5399 if (address
.scale
!= 0)
5400 return OP_TYPE_MEM6
;
5402 if (address
.base
!= NULL_RTX
)
5404 if (address
.offset
== NULL_RTX
)
5405 return OP_TYPE_MEM234
;
5407 return OP_TYPE_MEM5
;
5410 gcc_assert (address
.offset
!= NULL_RTX
);
5412 return OP_TYPE_MEM7
;
5415 /* Return X or Y (depending on OPX_P) operand of INSN. */
5417 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5421 if (recog_memoized (insn
) < 0)
5424 extract_constrain_insn_cached (insn
);
5427 i
= get_attr_opx (insn
);
5429 i
= get_attr_opy (insn
);
5431 if (i
>= recog_data
.n_operands
)
5434 return recog_data
.operand
[i
];
5437 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5438 If ADDRESS_P is true, return type of memory location operand refers to. */
5439 static enum attr_op_type
5440 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5444 op
= sched_get_operand (insn
, opx_p
);
5448 gcc_assert (!reload_completed
);
5453 return sched_address_type (QImode
, op
);
5455 if (memory_operand (op
, VOIDmode
))
5456 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5458 if (register_operand (op
, VOIDmode
))
5460 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5461 || (reload_completed
&& FP_REG_P (op
)))
5467 if (GET_CODE (op
) == CONST_INT
)
5473 /* Check for quick constants. */
5474 switch (get_attr_type (insn
))
5477 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5478 return OP_TYPE_IMM_Q
;
5480 gcc_assert (!reload_completed
);
5484 if (USE_MOVQ (ival
))
5485 return OP_TYPE_IMM_Q
;
5487 gcc_assert (!reload_completed
);
5491 if (valid_mov3q_const (ival
))
5492 return OP_TYPE_IMM_Q
;
5494 gcc_assert (!reload_completed
);
5501 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5502 return OP_TYPE_IMM_W
;
5504 return OP_TYPE_IMM_L
;
5507 if (GET_CODE (op
) == CONST_DOUBLE
)
5509 switch (GET_MODE (op
))
5512 return OP_TYPE_IMM_W
;
5516 return OP_TYPE_IMM_L
;
5523 if (GET_CODE (op
) == CONST
5524 || symbolic_operand (op
, VOIDmode
)
5527 switch (GET_MODE (op
))
5530 return OP_TYPE_IMM_Q
;
5533 return OP_TYPE_IMM_W
;
5536 return OP_TYPE_IMM_L
;
5539 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5541 return OP_TYPE_IMM_W
;
5543 return OP_TYPE_IMM_L
;
5547 gcc_assert (!reload_completed
);
5549 if (FLOAT_MODE_P (GET_MODE (op
)))
5555 /* Implement opx_type attribute.
5556 Return type of INSN's operand X.
5557 If ADDRESS_P is true, return type of memory location operand refers to. */
5559 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5561 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5567 return OPX_TYPE_FPN
;
5570 return OPX_TYPE_MEM1
;
5572 case OP_TYPE_MEM234
:
5573 return OPX_TYPE_MEM234
;
5576 return OPX_TYPE_MEM5
;
5579 return OPX_TYPE_MEM6
;
5582 return OPX_TYPE_MEM7
;
5585 return OPX_TYPE_IMM_Q
;
5588 return OPX_TYPE_IMM_W
;
5591 return OPX_TYPE_IMM_L
;
5598 /* Implement opy_type attribute.
5599 Return type of INSN's operand Y.
5600 If ADDRESS_P is true, return type of memory location operand refers to. */
5602 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5604 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5610 return OPY_TYPE_FPN
;
5613 return OPY_TYPE_MEM1
;
5615 case OP_TYPE_MEM234
:
5616 return OPY_TYPE_MEM234
;
5619 return OPY_TYPE_MEM5
;
5622 return OPY_TYPE_MEM6
;
5625 return OPY_TYPE_MEM7
;
5628 return OPY_TYPE_IMM_Q
;
5631 return OPY_TYPE_IMM_W
;
5634 return OPY_TYPE_IMM_L
;
5641 /* Return size of INSN as int. */
5643 sched_get_attr_size_int (rtx_insn
*insn
)
5647 switch (get_attr_type (insn
))
5650 /* There should be no references to m68k_sched_attr_size for 'ignore'
5664 switch (get_attr_opx_type (insn
))
5670 case OPX_TYPE_MEM234
:
5671 case OPY_TYPE_IMM_Q
:
5676 /* Here we assume that most absolute references are short. */
5678 case OPY_TYPE_IMM_W
:
5682 case OPY_TYPE_IMM_L
:
5690 switch (get_attr_opy_type (insn
))
5696 case OPY_TYPE_MEM234
:
5697 case OPY_TYPE_IMM_Q
:
5702 /* Here we assume that most absolute references are short. */
5704 case OPY_TYPE_IMM_W
:
5708 case OPY_TYPE_IMM_L
:
5718 gcc_assert (!reload_completed
);
5726 /* Return size of INSN as attribute enum value. */
5728 m68k_sched_attr_size (rtx_insn
*insn
)
5730 switch (sched_get_attr_size_int (insn
))
5746 /* Return operand X or Y (depending on OPX_P) of INSN,
5747 if it is a MEM, or NULL overwise. */
5748 static enum attr_op_type
5749 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5753 switch (get_attr_opx_type (insn
))
5758 case OPX_TYPE_IMM_Q
:
5759 case OPX_TYPE_IMM_W
:
5760 case OPX_TYPE_IMM_L
:
5764 case OPX_TYPE_MEM234
:
5767 return OP_TYPE_MEM1
;
5770 return OP_TYPE_MEM6
;
5778 switch (get_attr_opy_type (insn
))
5783 case OPY_TYPE_IMM_Q
:
5784 case OPY_TYPE_IMM_W
:
5785 case OPY_TYPE_IMM_L
:
5789 case OPY_TYPE_MEM234
:
5792 return OP_TYPE_MEM1
;
5795 return OP_TYPE_MEM6
;
5803 /* Implement op_mem attribute. */
5805 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5807 enum attr_op_type opx
;
5808 enum attr_op_type opy
;
5810 opx
= sched_get_opxy_mem_type (insn
, true);
5811 opy
= sched_get_opxy_mem_type (insn
, false);
5813 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5816 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5818 switch (get_attr_opx_access (insn
))
5834 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5836 switch (get_attr_opx_access (insn
))
5852 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5855 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5857 switch (get_attr_opx_access (insn
))
5863 gcc_assert (!reload_completed
);
5868 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5870 switch (get_attr_opx_access (insn
))
5876 gcc_assert (!reload_completed
);
5881 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5884 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5886 switch (get_attr_opx_access (insn
))
5892 gcc_assert (!reload_completed
);
5897 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5898 gcc_assert (!reload_completed
);
5902 /* Data for ColdFire V4 index bypass.
5903 Producer modifies register that is used as index in consumer with
5907 /* Producer instruction. */
5910 /* Consumer instruction. */
5913 /* Scale of indexed memory access within consumer.
5914 Or zero if bypass should not be effective at the moment. */
5916 } sched_cfv4_bypass_data
;
5918 /* An empty state that is used in m68k_sched_adjust_cost. */
5919 static state_t sched_adjust_cost_state
;
5921 /* Implement adjust_cost scheduler hook.
5922 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5924 m68k_sched_adjust_cost (rtx_insn
*insn
, int, rtx_insn
*def_insn
, int cost
,
5929 if (recog_memoized (def_insn
) < 0
5930 || recog_memoized (insn
) < 0)
5933 if (sched_cfv4_bypass_data
.scale
== 1)
5934 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5936 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5937 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5938 that the data in sched_cfv4_bypass_data is up to date. */
5939 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5940 && sched_cfv4_bypass_data
.con
== insn
);
5945 sched_cfv4_bypass_data
.pro
= NULL
;
5946 sched_cfv4_bypass_data
.con
= NULL
;
5947 sched_cfv4_bypass_data
.scale
= 0;
5950 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5951 && sched_cfv4_bypass_data
.con
== NULL
5952 && sched_cfv4_bypass_data
.scale
== 0);
5954 /* Don't try to issue INSN earlier than DFA permits.
5955 This is especially useful for instructions that write to memory,
5956 as their true dependence (default) latency is better to be set to 0
5957 to workaround alias analysis limitations.
5958 This is, in fact, a machine independent tweak, so, probably,
5959 it should be moved to haifa-sched.c: insn_cost (). */
5960 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5967 /* Return maximal number of insns that can be scheduled on a single cycle. */
5969 m68k_sched_issue_rate (void)
5971 switch (m68k_sched_cpu
)
5987 /* Maximal length of instruction for current CPU.
5988 E.g. it is 3 for any ColdFire core. */
5989 static int max_insn_size
;
5991 /* Data to model instruction buffer of CPU. */
5994 /* True if instruction buffer model is modeled for current CPU. */
5997 /* Size of the instruction buffer in words. */
6000 /* Number of filled words in the instruction buffer. */
6003 /* Additional information about instruction buffer for CPUs that have
6004 a buffer of instruction records, rather then a plain buffer
6005 of instruction words. */
6006 struct _sched_ib_records
6008 /* Size of buffer in records. */
6011 /* Array to hold data on adjustements made to the size of the buffer. */
6014 /* Index of the above array. */
6018 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6022 static struct _sched_ib sched_ib
;
6024 /* ID of memory unit. */
6025 static int sched_mem_unit_code
;
6027 /* Implementation of the targetm.sched.variable_issue () hook.
6028 It is called after INSN was issued. It returns the number of insns
6029 that can possibly get scheduled on the current cycle.
6030 It is used here to determine the effect of INSN on the instruction
6033 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6034 int sched_verbose ATTRIBUTE_UNUSED
,
6035 rtx_insn
*insn
, int can_issue_more
)
6039 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6041 switch (m68k_sched_cpu
)
6045 insn_size
= sched_get_attr_size_int (insn
);
6049 insn_size
= sched_get_attr_size_int (insn
);
6051 /* ColdFire V3 and V4 cores have instruction buffers that can
6052 accumulate up to 8 instructions regardless of instructions'
6053 sizes. So we should take care not to "prefetch" 24 one-word
6054 or 12 two-words instructions.
6055 To model this behavior we temporarily decrease size of the
6056 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6060 adjust
= max_insn_size
- insn_size
;
6061 sched_ib
.size
-= adjust
;
6063 if (sched_ib
.filled
> sched_ib
.size
)
6064 sched_ib
.filled
= sched_ib
.size
;
6066 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6069 ++sched_ib
.records
.adjust_index
;
6070 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6071 sched_ib
.records
.adjust_index
= 0;
6073 /* Undo adjustement we did 7 instructions ago. */
6075 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6080 gcc_assert (!sched_ib
.enabled_p
);
6088 if (insn_size
> sched_ib
.filled
)
6089 /* Scheduling for register pressure does not always take DFA into
6090 account. Workaround instruction buffer not being filled enough. */
6092 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6093 insn_size
= sched_ib
.filled
;
6098 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6099 || asm_noperands (PATTERN (insn
)) >= 0)
6100 insn_size
= sched_ib
.filled
;
6104 sched_ib
.filled
-= insn_size
;
6106 return can_issue_more
;
6109 /* Return how many instructions should scheduler lookahead to choose the
6112 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6114 return m68k_sched_issue_rate () - 1;
6117 /* Implementation of targetm.sched.init_global () hook.
6118 It is invoked once per scheduling pass and is used here
6119 to initialize scheduler constants. */
6121 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6122 int sched_verbose ATTRIBUTE_UNUSED
,
6123 int n_insns ATTRIBUTE_UNUSED
)
6125 /* Check that all instructions have DFA reservations and
6126 that all instructions can be issued from a clean state. */
6132 state
= alloca (state_size ());
6134 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6136 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6138 gcc_assert (insn_has_dfa_reservation_p (insn
));
6140 state_reset (state
);
6141 if (state_transition (state
, insn
) >= 0)
6147 /* Setup target cpu. */
6149 /* ColdFire V4 has a set of features to keep its instruction buffer full
6150 (e.g., a separate memory bus for instructions) and, hence, we do not model
6151 buffer for this CPU. */
6152 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6154 switch (m68k_sched_cpu
)
6157 sched_ib
.filled
= 0;
6164 sched_ib
.records
.n_insns
= 0;
6165 sched_ib
.records
.adjust
= NULL
;
6170 sched_ib
.records
.n_insns
= 8;
6171 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6178 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6180 sched_adjust_cost_state
= xmalloc (state_size ());
6181 state_reset (sched_adjust_cost_state
);
6184 emit_insn (gen_ib ());
6185 sched_ib
.insn
= get_insns ();
6189 /* Scheduling pass is now finished. Free/reset static variables. */
6191 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6192 int verbose ATTRIBUTE_UNUSED
)
6194 sched_ib
.insn
= NULL
;
6196 free (sched_adjust_cost_state
);
6197 sched_adjust_cost_state
= NULL
;
6199 sched_mem_unit_code
= 0;
6201 free (sched_ib
.records
.adjust
);
6202 sched_ib
.records
.adjust
= NULL
;
6203 sched_ib
.records
.n_insns
= 0;
6207 /* Implementation of targetm.sched.init () hook.
6208 It is invoked each time scheduler starts on the new block (basic block or
6209 extended basic block). */
6211 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6212 int sched_verbose ATTRIBUTE_UNUSED
,
6213 int n_insns ATTRIBUTE_UNUSED
)
6215 switch (m68k_sched_cpu
)
6223 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6225 memset (sched_ib
.records
.adjust
, 0,
6226 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6227 sched_ib
.records
.adjust_index
= 0;
6231 gcc_assert (!sched_ib
.enabled_p
);
6239 if (sched_ib
.enabled_p
)
6240 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6241 the first cycle. Workaround that. */
6242 sched_ib
.filled
= -2;
6245 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6246 It is invoked just before current cycle finishes and is used here
6247 to track if instruction buffer got its two words this cycle. */
6249 m68k_sched_dfa_pre_advance_cycle (void)
6251 if (!sched_ib
.enabled_p
)
6254 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6256 sched_ib
.filled
+= 2;
6258 if (sched_ib
.filled
> sched_ib
.size
)
6259 sched_ib
.filled
= sched_ib
.size
;
6263 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6264 It is invoked just after new cycle begins and is used here
6265 to setup number of filled words in the instruction buffer so that
6266 instructions which won't have all their words prefetched would be
6267 stalled for a cycle. */
6269 m68k_sched_dfa_post_advance_cycle (void)
6273 if (!sched_ib
.enabled_p
)
6276 /* Setup number of prefetched instruction words in the instruction
6278 i
= max_insn_size
- sched_ib
.filled
;
6282 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6283 /* Pick up scheduler state. */
6288 /* Return X or Y (depending on OPX_P) operand of INSN,
6289 if it is an integer register, or NULL overwise. */
6291 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6297 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6299 op
= sched_get_operand (insn
, true);
6300 gcc_assert (op
!= NULL
);
6302 if (!reload_completed
&& !REG_P (op
))
6308 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6310 op
= sched_get_operand (insn
, false);
6311 gcc_assert (op
!= NULL
);
6313 if (!reload_completed
&& !REG_P (op
))
6321 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6324 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6326 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6337 /* Return X or Y (depending on OPX_P) operand of INSN,
6338 if it is a MEM, or NULL overwise. */
6340 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6360 if (opy_p
&& sched_mem_operand_p (insn
, false))
6361 return sched_get_operand (insn
, false);
6363 if (opx_p
&& sched_mem_operand_p (insn
, true))
6364 return sched_get_operand (insn
, true);
6370 /* Return non-zero if PRO modifies register used as part of
6373 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6378 pro_x
= sched_get_reg_operand (pro
, true);
6382 con_mem_read
= sched_get_mem_operand (con
, true, false);
6383 gcc_assert (con_mem_read
!= NULL
);
6385 if (reg_mentioned_p (pro_x
, con_mem_read
))
6391 /* Helper function for m68k_sched_indexed_address_bypass_p.
6392 if PRO modifies register used as index in CON,
6393 return scale of indexed memory access in CON. Return zero overwise. */
6395 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6399 struct m68k_address address
;
6401 reg
= sched_get_reg_operand (pro
, true);
6405 mem
= sched_get_mem_operand (con
, true, false);
6406 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6408 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6412 if (REGNO (reg
) == REGNO (address
.index
))
6414 gcc_assert (address
.scale
!= 0);
6415 return address
.scale
;
6421 /* Return non-zero if PRO modifies register used
6422 as index with scale 2 or 4 in CON. */
6424 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6426 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6427 && sched_cfv4_bypass_data
.con
== NULL
6428 && sched_cfv4_bypass_data
.scale
== 0);
6430 switch (sched_get_indexed_address_scale (pro
, con
))
6433 /* We can't have a variable latency bypass, so
6434 remember to adjust the insn cost in adjust_cost hook. */
6435 sched_cfv4_bypass_data
.pro
= pro
;
6436 sched_cfv4_bypass_data
.con
= con
;
6437 sched_cfv4_bypass_data
.scale
= 1;
6449 /* We generate a two-instructions program at M_TRAMP :
6450 movea.l &CHAIN_VALUE,%a0
6452 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6455 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6457 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6460 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6462 mem
= adjust_address (m_tramp
, HImode
, 0);
6463 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6464 mem
= adjust_address (m_tramp
, SImode
, 2);
6465 emit_move_insn (mem
, chain_value
);
6467 mem
= adjust_address (m_tramp
, HImode
, 6);
6468 emit_move_insn (mem
, GEN_INT(0x4EF9));
6469 mem
= adjust_address (m_tramp
, SImode
, 8);
6470 emit_move_insn (mem
, fnaddr
);
6472 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6475 /* On the 68000, the RTS insn cannot pop anything.
6476 On the 68010, the RTD insn may be used to pop them if the number
6477 of args is fixed, but if the number is variable then the caller
6478 must pop them all. RTD can't be used for library calls now
6479 because the library is compiled with the Unix compiler.
6480 Use of RTD is a selectable option, since it is incompatible with
6481 standard Unix calling sequences. If the option is not selected,
6482 the caller must always pop the args. */
6485 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6489 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6490 && (!stdarg_p (funtype
)))
6494 /* Make sure everything's fine if we *don't* have a given processor.
6495 This assumes that putting a register in fixed_regs will keep the
6496 compiler's mitts completely off it. We don't bother to zero it out
6497 of register classes. */
6500 m68k_conditional_register_usage (void)
6504 if (!TARGET_HARD_FLOAT
)
6506 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6507 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6508 if (TEST_HARD_REG_BIT (x
, i
))
6509 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6512 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6516 m68k_init_sync_libfuncs (void)
6518 init_sync_libfuncs (UNITS_PER_WORD
);
6521 /* Implements EPILOGUE_USES. All registers are live on exit from an
6522 interrupt routine. */
6524 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6526 return (reload_completed
6527 && (m68k_get_function_kind (current_function_decl
)
6528 == m68k_fk_interrupt_handler
));
6531 #include "gt-m68k.h"