1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
46 #include "sched-int.h"
47 #include "insn-codes.h"
52 enum reg_class regno_reg_class
[] =
54 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
55 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
56 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
57 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
58 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
64 /* The minimum number of integer registers that we want to save with the
65 movem instruction. Using two movel instructions instead of a single
66 moveml is about 15% faster for the 68020 and 68030 at no expense in
68 #define MIN_MOVEM_REGS 3
70 /* The minimum number of floating point registers that we want to save
71 with the fmovem instruction. */
72 #define MIN_FMOVEM_REGS 1
74 /* Structure describing stack frame layout. */
77 /* Stack pointer to frame pointer offset. */
80 /* Offset of FPU registers. */
81 HOST_WIDE_INT foffset
;
83 /* Frame size in bytes (rounded up). */
86 /* Data and address register. */
88 unsigned int reg_mask
;
92 unsigned int fpu_mask
;
94 /* Offsets relative to ARG_POINTER. */
95 HOST_WIDE_INT frame_pointer_offset
;
96 HOST_WIDE_INT stack_pointer_offset
;
98 /* Function which the above information refers to. */
102 /* Current frame information calculated by m68k_compute_frame_layout(). */
103 static struct m68k_frame current_frame
;
105 /* Structure describing an m68k address.
107 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
108 with null fields evaluating to 0. Here:
110 - BASE satisfies m68k_legitimate_base_reg_p
111 - INDEX satisfies m68k_legitimate_index_reg_p
112 - OFFSET satisfies m68k_legitimate_constant_address_p
114 INDEX is either HImode or SImode. The other fields are SImode.
116 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
117 the address is (BASE)+. */
118 struct m68k_address
{
126 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
127 static int m68k_sched_issue_rate (void);
128 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
129 static void m68k_sched_md_init_global (FILE *, int, int);
130 static void m68k_sched_md_finish_global (FILE *, int);
131 static void m68k_sched_md_init (FILE *, int, int);
132 static void m68k_sched_dfa_pre_advance_cycle (void);
133 static void m68k_sched_dfa_post_advance_cycle (void);
134 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
136 static bool m68k_can_eliminate (const int, const int);
137 static void m68k_conditional_register_usage (void);
138 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
139 static void m68k_option_override (void);
140 static void m68k_override_options_after_change (void);
141 static rtx
find_addr_reg (rtx
);
142 static const char *singlemove_string (rtx
*);
143 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
144 HOST_WIDE_INT
, tree
);
145 static rtx
m68k_struct_value_rtx (tree
, int);
146 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
147 tree args
, int flags
,
149 static void m68k_compute_frame_layout (void);
150 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
151 static bool m68k_ok_for_sibcall_p (tree
, tree
);
152 static bool m68k_tls_symbol_p (rtx
);
153 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
154 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
155 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
156 static bool m68k_return_in_memory (const_tree
, const_tree
);
158 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
159 static void m68k_trampoline_init (rtx
, tree
, rtx
);
160 static int m68k_return_pops_args (tree
, tree
, int);
161 static rtx
m68k_delegitimize_address (rtx
);
162 static void m68k_function_arg_advance (cumulative_args_t
, enum machine_mode
,
164 static rtx
m68k_function_arg (cumulative_args_t
, enum machine_mode
,
166 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
167 static bool m68k_output_addr_const_extra (FILE *, rtx
);
168 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
170 /* Initialize the GCC target structure. */
172 #if INT_OP_GROUP == INT_OP_DOT_WORD
173 #undef TARGET_ASM_ALIGNED_HI_OP
174 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
177 #if INT_OP_GROUP == INT_OP_NO_DOT
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tbyte\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
186 #if INT_OP_GROUP == INT_OP_DC
187 #undef TARGET_ASM_BYTE_OP
188 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
189 #undef TARGET_ASM_ALIGNED_HI_OP
190 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
191 #undef TARGET_ASM_ALIGNED_SI_OP
192 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
195 #undef TARGET_ASM_UNALIGNED_HI_OP
196 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
197 #undef TARGET_ASM_UNALIGNED_SI_OP
198 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
200 #undef TARGET_ASM_OUTPUT_MI_THUNK
201 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
202 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
203 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
205 #undef TARGET_ASM_FILE_START_APP_OFF
206 #define TARGET_ASM_FILE_START_APP_OFF true
208 #undef TARGET_LEGITIMIZE_ADDRESS
209 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
211 #undef TARGET_SCHED_ADJUST_COST
212 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
214 #undef TARGET_SCHED_ISSUE_RATE
215 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
217 #undef TARGET_SCHED_VARIABLE_ISSUE
218 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
220 #undef TARGET_SCHED_INIT_GLOBAL
221 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
223 #undef TARGET_SCHED_FINISH_GLOBAL
224 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
226 #undef TARGET_SCHED_INIT
227 #define TARGET_SCHED_INIT m68k_sched_md_init
229 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
230 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
232 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
233 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
235 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
236 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
237 m68k_sched_first_cycle_multipass_dfa_lookahead
239 #undef TARGET_OPTION_OVERRIDE
240 #define TARGET_OPTION_OVERRIDE m68k_option_override
242 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
243 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
245 #undef TARGET_RTX_COSTS
246 #define TARGET_RTX_COSTS m68k_rtx_costs
248 #undef TARGET_ATTRIBUTE_TABLE
249 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
251 #undef TARGET_PROMOTE_PROTOTYPES
252 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
254 #undef TARGET_STRUCT_VALUE_RTX
255 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
257 #undef TARGET_CANNOT_FORCE_CONST_MEM
258 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
260 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
261 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
263 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
264 #undef TARGET_RETURN_IN_MEMORY
265 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
269 #undef TARGET_HAVE_TLS
270 #define TARGET_HAVE_TLS (true)
272 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
273 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
276 #undef TARGET_LEGITIMATE_ADDRESS_P
277 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
279 #undef TARGET_CAN_ELIMINATE
280 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
282 #undef TARGET_CONDITIONAL_REGISTER_USAGE
283 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
285 #undef TARGET_TRAMPOLINE_INIT
286 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
288 #undef TARGET_RETURN_POPS_ARGS
289 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
291 #undef TARGET_DELEGITIMIZE_ADDRESS
292 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
294 #undef TARGET_FUNCTION_ARG
295 #define TARGET_FUNCTION_ARG m68k_function_arg
297 #undef TARGET_FUNCTION_ARG_ADVANCE
298 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
300 #undef TARGET_LEGITIMATE_CONSTANT_P
301 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
303 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
304 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
306 /* The value stored by TAS. */
307 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
308 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
310 static const struct attribute_spec m68k_attribute_table
[] =
312 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
313 affects_type_identity } */
314 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
316 { "interrupt_handler", 0, 0, true, false, false,
317 m68k_handle_fndecl_attribute
, false },
318 { "interrupt_thread", 0, 0, true, false, false,
319 m68k_handle_fndecl_attribute
, false },
320 { NULL
, 0, 0, false, false, false, NULL
, false }
323 struct gcc_target targetm
= TARGET_INITIALIZER
;
325 /* Base flags for 68k ISAs. */
326 #define FL_FOR_isa_00 FL_ISA_68000
327 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
328 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
329 generated 68881 code for 68020 and 68030 targets unless explicitly told
331 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
332 | FL_BITFIELD | FL_68881 | FL_CAS)
333 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
334 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
336 /* Base flags for ColdFire ISAs. */
337 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
338 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
339 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
340 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
341 /* ISA_C is not upwardly compatible with ISA_B. */
342 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
346 /* Traditional 68000 instruction sets. */
352 /* ColdFire instruction set variants. */
360 /* Information about one of the -march, -mcpu or -mtune arguments. */
361 struct m68k_target_selection
363 /* The argument being described. */
366 /* For -mcpu, this is the device selected by the option.
367 For -mtune and -march, it is a representative device
368 for the microarchitecture or ISA respectively. */
369 enum target_device device
;
371 /* The M68K_DEVICE fields associated with DEVICE. See the comment
372 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
374 enum uarch_type microarch
;
379 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
380 static const struct m68k_target_selection all_devices
[] =
382 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
383 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
384 #include "m68k-devices.def"
386 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
389 /* A list of all ISAs, mapping each one to a representative device.
390 Used for -march selection. */
391 static const struct m68k_target_selection all_isas
[] =
393 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
394 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
395 #include "m68k-isas.def"
397 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
400 /* A list of all microarchitectures, mapping each one to a representative
401 device. Used for -mtune selection. */
402 static const struct m68k_target_selection all_microarchs
[] =
404 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
405 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
406 #include "m68k-microarchs.def"
407 #undef M68K_MICROARCH
408 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
411 /* The entries associated with the -mcpu, -march and -mtune settings,
412 or null for options that have not been used. */
413 const struct m68k_target_selection
*m68k_cpu_entry
;
414 const struct m68k_target_selection
*m68k_arch_entry
;
415 const struct m68k_target_selection
*m68k_tune_entry
;
417 /* Which CPU we are generating code for. */
418 enum target_device m68k_cpu
;
420 /* Which microarchitecture to tune for. */
421 enum uarch_type m68k_tune
;
423 /* Which FPU to use. */
424 enum fpu_type m68k_fpu
;
426 /* The set of FL_* flags that apply to the target processor. */
427 unsigned int m68k_cpu_flags
;
429 /* The set of FL_* flags that apply to the processor to be tuned for. */
430 unsigned int m68k_tune_flags
;
432 /* Asm templates for calling or jumping to an arbitrary symbolic address,
433 or NULL if such calls or jumps are not supported. The address is held
435 const char *m68k_symbolic_call
;
436 const char *m68k_symbolic_jump
;
438 /* Enum variable that corresponds to m68k_symbolic_call values. */
439 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
442 /* Implement TARGET_OPTION_OVERRIDE. */
445 m68k_option_override (void)
447 const struct m68k_target_selection
*entry
;
448 unsigned long target_mask
;
450 if (global_options_set
.x_m68k_arch_option
)
451 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
453 if (global_options_set
.x_m68k_cpu_option
)
454 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
456 if (global_options_set
.x_m68k_tune_option
)
457 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
465 -march=ARCH should generate code that runs any processor
466 implementing architecture ARCH. -mcpu=CPU should override -march
467 and should generate code that runs on processor CPU, making free
468 use of any instructions that CPU understands. -mtune=UARCH applies
469 on top of -mcpu or -march and optimizes the code for UARCH. It does
470 not change the target architecture. */
473 /* Complain if the -march setting is for a different microarchitecture,
474 or includes flags that the -mcpu setting doesn't. */
476 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
477 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
478 warning (0, "-mcpu=%s conflicts with -march=%s",
479 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
481 entry
= m68k_cpu_entry
;
484 entry
= m68k_arch_entry
;
487 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
489 m68k_cpu_flags
= entry
->flags
;
491 /* Use the architecture setting to derive default values for
495 /* ColdFire is lenient about alignment. */
496 if (!TARGET_COLDFIRE
)
497 target_mask
|= MASK_STRICT_ALIGNMENT
;
499 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
500 target_mask
|= MASK_BITFIELD
;
501 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
502 target_mask
|= MASK_CF_HWDIV
;
503 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
504 target_mask
|= MASK_HARD_FLOAT
;
505 target_flags
|= target_mask
& ~target_flags_explicit
;
507 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
508 m68k_cpu
= entry
->device
;
511 m68k_tune
= m68k_tune_entry
->microarch
;
512 m68k_tune_flags
= m68k_tune_entry
->flags
;
514 #ifdef M68K_DEFAULT_TUNE
515 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
517 enum target_device dev
;
518 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
519 m68k_tune_flags
= all_devices
[dev
]->flags
;
524 m68k_tune
= entry
->microarch
;
525 m68k_tune_flags
= entry
->flags
;
528 /* Set the type of FPU. */
529 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
530 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
533 /* Sanity check to ensure that msep-data and mid-sahred-library are not
534 * both specified together. Doing so simply doesn't make sense.
536 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
537 error ("cannot specify both -msep-data and -mid-shared-library");
539 /* If we're generating code for a separate A5 relative data segment,
540 * we've got to enable -fPIC as well. This might be relaxable to
541 * -fpic but it hasn't been tested properly.
543 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
546 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
547 error if the target does not support them. */
548 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
549 error ("-mpcrel -fPIC is not currently supported on selected cpu");
551 /* ??? A historic way of turning on pic, or is this intended to
552 be an embedded thing that doesn't have the same name binding
553 significance that it does on hosted ELF systems? */
554 if (TARGET_PCREL
&& flag_pic
== 0)
559 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
561 m68k_symbolic_jump
= "jra %a0";
563 else if (TARGET_ID_SHARED_LIBRARY
)
564 /* All addresses must be loaded from the GOT. */
566 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
569 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
571 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
574 /* No unconditional long branch */;
575 else if (TARGET_PCREL
)
576 m68k_symbolic_jump
= "bra%.l %c0";
578 m68k_symbolic_jump
= "bra%.l %p0";
579 /* Turn off function cse if we are doing PIC. We always want
580 function call to be done as `bsr foo@PLTPC'. */
581 /* ??? It's traditional to do this for -mpcrel too, but it isn't
582 clear how intentional that is. */
583 flag_no_function_cse
= 1;
586 switch (m68k_symbolic_call_var
)
588 case M68K_SYMBOLIC_CALL_JSR
:
589 m68k_symbolic_call
= "jsr %a0";
592 case M68K_SYMBOLIC_CALL_BSR_C
:
593 m68k_symbolic_call
= "bsr%.l %c0";
596 case M68K_SYMBOLIC_CALL_BSR_P
:
597 m68k_symbolic_call
= "bsr%.l %p0";
600 case M68K_SYMBOLIC_CALL_NONE
:
601 gcc_assert (m68k_symbolic_call
== NULL
);
608 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
609 if (align_labels
> 2)
611 warning (0, "-falign-labels=%d is not supported", align_labels
);
616 warning (0, "-falign-loops=%d is not supported", align_loops
);
621 SUBTARGET_OVERRIDE_OPTIONS
;
623 /* Setup scheduling options. */
625 m68k_sched_cpu
= CPU_CFV1
;
627 m68k_sched_cpu
= CPU_CFV2
;
629 m68k_sched_cpu
= CPU_CFV3
;
631 m68k_sched_cpu
= CPU_CFV4
;
634 m68k_sched_cpu
= CPU_UNKNOWN
;
635 flag_schedule_insns
= 0;
636 flag_schedule_insns_after_reload
= 0;
637 flag_modulo_sched
= 0;
640 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
642 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
643 m68k_sched_mac
= MAC_CF_EMAC
;
644 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
645 m68k_sched_mac
= MAC_CF_MAC
;
647 m68k_sched_mac
= MAC_NO
;
651 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
654 m68k_override_options_after_change (void)
656 if (m68k_sched_cpu
== CPU_UNKNOWN
)
658 flag_schedule_insns
= 0;
659 flag_schedule_insns_after_reload
= 0;
660 flag_modulo_sched
= 0;
664 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
665 given argument and NAME is the argument passed to -mcpu. Return NULL
666 if -mcpu was not passed. */
669 m68k_cpp_cpu_ident (const char *prefix
)
673 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
676 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
677 given argument and NAME is the name of the representative device for
678 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
681 m68k_cpp_cpu_family (const char *prefix
)
685 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
688 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
689 "interrupt_handler" attribute and interrupt_thread if FUNC has an
690 "interrupt_thread" attribute. Otherwise, return
691 m68k_fk_normal_function. */
693 enum m68k_function_kind
694 m68k_get_function_kind (tree func
)
698 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
700 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
702 return m68k_fk_interrupt_handler
;
704 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
706 return m68k_fk_interrupt_handler
;
708 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
710 return m68k_fk_interrupt_thread
;
712 return m68k_fk_normal_function
;
715 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
716 struct attribute_spec.handler. */
718 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
719 tree args ATTRIBUTE_UNUSED
,
720 int flags ATTRIBUTE_UNUSED
,
723 if (TREE_CODE (*node
) != FUNCTION_DECL
)
725 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
727 *no_add_attrs
= true;
730 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
732 error ("multiple interrupt attributes not allowed");
733 *no_add_attrs
= true;
737 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
739 error ("interrupt_thread is available only on fido");
740 *no_add_attrs
= true;
747 m68k_compute_frame_layout (void)
751 enum m68k_function_kind func_kind
=
752 m68k_get_function_kind (current_function_decl
);
753 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
754 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
756 /* Only compute the frame once per function.
757 Don't cache information until reload has been completed. */
758 if (current_frame
.funcdef_no
== current_function_funcdef_no
762 current_frame
.size
= (get_frame_size () + 3) & -4;
766 /* Interrupt thread does not need to save any register. */
767 if (!interrupt_thread
)
768 for (regno
= 0; regno
< 16; regno
++)
769 if (m68k_save_reg (regno
, interrupt_handler
))
771 mask
|= 1 << (regno
- D0_REG
);
774 current_frame
.offset
= saved
* 4;
775 current_frame
.reg_no
= saved
;
776 current_frame
.reg_mask
= mask
;
778 current_frame
.foffset
= 0;
780 if (TARGET_HARD_FLOAT
)
782 /* Interrupt thread does not need to save any register. */
783 if (!interrupt_thread
)
784 for (regno
= 16; regno
< 24; regno
++)
785 if (m68k_save_reg (regno
, interrupt_handler
))
787 mask
|= 1 << (regno
- FP0_REG
);
790 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
791 current_frame
.offset
+= current_frame
.foffset
;
793 current_frame
.fpu_no
= saved
;
794 current_frame
.fpu_mask
= mask
;
796 /* Remember what function this frame refers to. */
797 current_frame
.funcdef_no
= current_function_funcdef_no
;
800 /* Worker function for TARGET_CAN_ELIMINATE. */
803 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
805 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
809 m68k_initial_elimination_offset (int from
, int to
)
812 /* The arg pointer points 8 bytes before the start of the arguments,
813 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
814 frame pointer in most frames. */
815 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
816 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
817 return argptr_offset
;
819 m68k_compute_frame_layout ();
821 gcc_assert (to
== STACK_POINTER_REGNUM
);
824 case ARG_POINTER_REGNUM
:
825 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
826 case FRAME_POINTER_REGNUM
:
827 return current_frame
.offset
+ current_frame
.size
;
833 /* Refer to the array `regs_ever_live' to determine which registers
834 to save; `regs_ever_live[I]' is nonzero if register number I
835 is ever used in the function. This function is responsible for
836 knowing which registers should not be saved even if used.
837 Return true if we need to save REGNO. */
840 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
842 if (flag_pic
&& regno
== PIC_REG
)
844 if (crtl
->saves_all_registers
)
846 if (crtl
->uses_pic_offset_table
)
848 /* Reload may introduce constant pool references into a function
849 that thitherto didn't need a PIC register. Note that the test
850 above will not catch that case because we will only set
851 crtl->uses_pic_offset_table when emitting
852 the address reloads. */
853 if (crtl
->uses_const_pool
)
857 if (crtl
->calls_eh_return
)
862 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
863 if (test
== INVALID_REGNUM
)
870 /* Fixed regs we never touch. */
871 if (fixed_regs
[regno
])
874 /* The frame pointer (if it is such) is handled specially. */
875 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
878 /* Interrupt handlers must also save call_used_regs
879 if they are live or when calling nested functions. */
880 if (interrupt_handler
)
882 if (df_regs_ever_live_p (regno
))
885 if (!current_function_is_leaf
&& call_used_regs
[regno
])
889 /* Never need to save registers that aren't touched. */
890 if (!df_regs_ever_live_p (regno
))
893 /* Otherwise save everything that isn't call-clobbered. */
894 return !call_used_regs
[regno
];
897 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
898 the lowest memory address. COUNT is the number of registers to be
899 moved, with register REGNO + I being moved if bit I of MASK is set.
900 STORE_P specifies the direction of the move and ADJUST_STACK_P says
901 whether or not this is pre-decrement (if STORE_P) or post-increment
902 (if !STORE_P) operation. */
905 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
906 unsigned int count
, unsigned int regno
,
907 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
910 rtx body
, addr
, src
, operands
[2];
911 enum machine_mode mode
;
913 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
914 mode
= reg_raw_mode
[regno
];
919 src
= plus_constant (Pmode
, base
,
921 * GET_MODE_SIZE (mode
)
922 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
923 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
926 for (; mask
!= 0; mask
>>= 1, regno
++)
929 addr
= plus_constant (Pmode
, base
, offset
);
930 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
931 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
932 XVECEXP (body
, 0, i
++)
933 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
934 offset
+= GET_MODE_SIZE (mode
);
936 gcc_assert (i
== XVECLEN (body
, 0));
938 return emit_insn (body
);
941 /* Make INSN a frame-related instruction. */
944 m68k_set_frame_related (rtx insn
)
949 RTX_FRAME_RELATED_P (insn
) = 1;
950 body
= PATTERN (insn
);
951 if (GET_CODE (body
) == PARALLEL
)
952 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
953 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
956 /* Emit RTL for the "prologue" define_expand. */
959 m68k_expand_prologue (void)
961 HOST_WIDE_INT fsize_with_regs
;
962 rtx limit
, src
, dest
;
964 m68k_compute_frame_layout ();
966 if (flag_stack_usage_info
)
967 current_function_static_stack_size
968 = current_frame
.size
+ current_frame
.offset
;
970 /* If the stack limit is a symbol, we can check it here,
971 before actually allocating the space. */
972 if (crtl
->limit_stack
973 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
975 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
976 if (!m68k_legitimate_constant_p (Pmode
, limit
))
978 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
979 limit
= gen_rtx_REG (Pmode
, D0_REG
);
981 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
982 stack_pointer_rtx
, limit
),
983 stack_pointer_rtx
, limit
,
987 fsize_with_regs
= current_frame
.size
;
990 /* ColdFire's move multiple instructions do not allow pre-decrement
991 addressing. Add the size of movem saves to the initial stack
992 allocation instead. */
993 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
994 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
995 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
996 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
999 if (frame_pointer_needed
)
1001 if (fsize_with_regs
== 0 && TUNE_68040
)
1003 /* On the 68040, two separate moves are faster than link.w 0. */
1004 dest
= gen_frame_mem (Pmode
,
1005 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1006 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1007 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1008 stack_pointer_rtx
));
1010 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1011 m68k_set_frame_related
1012 (emit_insn (gen_link (frame_pointer_rtx
,
1013 GEN_INT (-4 - fsize_with_regs
))));
1016 m68k_set_frame_related
1017 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1018 m68k_set_frame_related
1019 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1021 GEN_INT (-fsize_with_regs
))));
1024 /* If the frame pointer is needed, emit a special barrier that
1025 will prevent the scheduler from moving stores to the frame
1026 before the stack adjustment. */
1027 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1029 else if (fsize_with_regs
!= 0)
1030 m68k_set_frame_related
1031 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1033 GEN_INT (-fsize_with_regs
))));
1035 if (current_frame
.fpu_mask
)
1037 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1039 m68k_set_frame_related
1040 (m68k_emit_movem (stack_pointer_rtx
,
1041 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1042 current_frame
.fpu_no
, FP0_REG
,
1043 current_frame
.fpu_mask
, true, true));
1048 /* If we're using moveml to save the integer registers,
1049 the stack pointer will point to the bottom of the moveml
1050 save area. Find the stack offset of the first FP register. */
1051 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1054 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1055 m68k_set_frame_related
1056 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1057 current_frame
.fpu_no
, FP0_REG
,
1058 current_frame
.fpu_mask
, true, false));
1062 /* If the stack limit is not a symbol, check it here.
1063 This has the disadvantage that it may be too late... */
1064 if (crtl
->limit_stack
)
1066 if (REG_P (stack_limit_rtx
))
1067 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1069 stack_pointer_rtx
, stack_limit_rtx
,
1072 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1073 warning (0, "stack limit expression is not supported");
1076 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1078 /* Store each register separately in the same order moveml does. */
1081 for (i
= 16; i
-- > 0; )
1082 if (current_frame
.reg_mask
& (1 << i
))
1084 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1085 dest
= gen_frame_mem (SImode
,
1086 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1087 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1092 if (TARGET_COLDFIRE
)
1093 /* The required register save space has already been allocated.
1094 The first register should be stored at (%sp). */
1095 m68k_set_frame_related
1096 (m68k_emit_movem (stack_pointer_rtx
, 0,
1097 current_frame
.reg_no
, D0_REG
,
1098 current_frame
.reg_mask
, true, false));
1100 m68k_set_frame_related
1101 (m68k_emit_movem (stack_pointer_rtx
,
1102 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1103 current_frame
.reg_no
, D0_REG
,
1104 current_frame
.reg_mask
, true, true));
1107 if (!TARGET_SEP_DATA
1108 && crtl
->uses_pic_offset_table
)
1109 emit_insn (gen_load_got (pic_offset_table_rtx
));
1112 /* Return true if a simple (return) instruction is sufficient for this
1113 instruction (i.e. if no epilogue is needed). */
1116 m68k_use_return_insn (void)
1118 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1121 m68k_compute_frame_layout ();
1122 return current_frame
.offset
== 0;
1125 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1126 SIBCALL_P says which.
1128 The function epilogue should not depend on the current stack pointer!
1129 It should use the frame pointer only, if there is a frame pointer.
1130 This is mandatory because of alloca; we also take advantage of it to
1131 omit stack adjustments before returning. */
1134 m68k_expand_epilogue (bool sibcall_p
)
1136 HOST_WIDE_INT fsize
, fsize_with_regs
;
1137 bool big
, restore_from_sp
;
1139 m68k_compute_frame_layout ();
1141 fsize
= current_frame
.size
;
1143 restore_from_sp
= false;
1145 /* FIXME : current_function_is_leaf below is too strong.
1146 What we really need to know there is if there could be pending
1147 stack adjustment needed at that point. */
1148 restore_from_sp
= (!frame_pointer_needed
1149 || (!cfun
->calls_alloca
1150 && current_function_is_leaf
));
1152 /* fsize_with_regs is the size we need to adjust the sp when
1153 popping the frame. */
1154 fsize_with_regs
= fsize
;
1155 if (TARGET_COLDFIRE
&& restore_from_sp
)
1157 /* ColdFire's move multiple instructions do not allow post-increment
1158 addressing. Add the size of movem loads to the final deallocation
1160 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1161 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1162 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1163 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1166 if (current_frame
.offset
+ fsize
>= 0x8000
1168 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1171 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1172 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1174 /* ColdFire's move multiple instructions do not support the
1175 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1176 stack-based restore. */
1177 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1178 GEN_INT (-(current_frame
.offset
+ fsize
)));
1179 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1180 gen_rtx_REG (Pmode
, A1_REG
),
1181 frame_pointer_rtx
));
1182 restore_from_sp
= true;
1186 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1192 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1194 /* Restore each register separately in the same order moveml does. */
1196 HOST_WIDE_INT offset
;
1198 offset
= current_frame
.offset
+ fsize
;
1199 for (i
= 0; i
< 16; i
++)
1200 if (current_frame
.reg_mask
& (1 << i
))
1206 /* Generate the address -OFFSET(%fp,%a1.l). */
1207 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1208 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1209 addr
= plus_constant (Pmode
, addr
, -offset
);
1211 else if (restore_from_sp
)
1212 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1214 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1215 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1216 gen_frame_mem (SImode
, addr
));
1217 offset
-= GET_MODE_SIZE (SImode
);
1220 else if (current_frame
.reg_mask
)
1223 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1224 gen_rtx_REG (Pmode
, A1_REG
),
1226 -(current_frame
.offset
+ fsize
),
1227 current_frame
.reg_no
, D0_REG
,
1228 current_frame
.reg_mask
, false, false);
1229 else if (restore_from_sp
)
1230 m68k_emit_movem (stack_pointer_rtx
, 0,
1231 current_frame
.reg_no
, D0_REG
,
1232 current_frame
.reg_mask
, false,
1235 m68k_emit_movem (frame_pointer_rtx
,
1236 -(current_frame
.offset
+ fsize
),
1237 current_frame
.reg_no
, D0_REG
,
1238 current_frame
.reg_mask
, false, false);
1241 if (current_frame
.fpu_no
> 0)
1244 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1245 gen_rtx_REG (Pmode
, A1_REG
),
1247 -(current_frame
.foffset
+ fsize
),
1248 current_frame
.fpu_no
, FP0_REG
,
1249 current_frame
.fpu_mask
, false, false);
1250 else if (restore_from_sp
)
1252 if (TARGET_COLDFIRE
)
1256 /* If we used moveml to restore the integer registers, the
1257 stack pointer will still point to the bottom of the moveml
1258 save area. Find the stack offset of the first FP
1260 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1263 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1264 m68k_emit_movem (stack_pointer_rtx
, offset
,
1265 current_frame
.fpu_no
, FP0_REG
,
1266 current_frame
.fpu_mask
, false, false);
1269 m68k_emit_movem (stack_pointer_rtx
, 0,
1270 current_frame
.fpu_no
, FP0_REG
,
1271 current_frame
.fpu_mask
, false, true);
1274 m68k_emit_movem (frame_pointer_rtx
,
1275 -(current_frame
.foffset
+ fsize
),
1276 current_frame
.fpu_no
, FP0_REG
,
1277 current_frame
.fpu_mask
, false, false);
1280 if (frame_pointer_needed
)
1281 emit_insn (gen_unlink (frame_pointer_rtx
));
1282 else if (fsize_with_regs
)
1283 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1285 GEN_INT (fsize_with_regs
)));
1287 if (crtl
->calls_eh_return
)
1288 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1290 EH_RETURN_STACKADJ_RTX
));
1293 emit_jump_insn (ret_rtx
);
1296 /* Return true if X is a valid comparison operator for the dbcc
1299 Note it rejects floating point comparison operators.
1300 (In the future we could use Fdbcc).
1302 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1305 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1307 switch (GET_CODE (x
))
1309 case EQ
: case NE
: case GTU
: case LTU
:
1313 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1315 case GT
: case LT
: case GE
: case LE
:
1316 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1322 /* Return nonzero if flags are currently in the 68881 flag register. */
1324 flags_in_68881 (void)
1326 /* We could add support for these in the future */
1327 return cc_status
.flags
& CC_IN_68881
;
1330 /* Return true if PARALLEL contains register REGNO. */
1332 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1336 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1339 if (GET_CODE (parallel
) != PARALLEL
)
1342 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1346 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1347 if (REG_P (x
) && REGNO (x
) == regno
)
1354 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1357 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1359 enum m68k_function_kind kind
;
1361 /* We cannot use sibcalls for nested functions because we use the
1362 static chain register for indirect calls. */
1363 if (CALL_EXPR_STATIC_CHAIN (exp
))
1366 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1368 /* Check that the return value locations are the same. For
1369 example that we aren't returning a value from the sibling in
1370 a D0 register but then need to transfer it to a A0 register. */
1374 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1376 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1378 /* Check that the values are equal or that the result the callee
1379 function returns is superset of what the current function returns. */
1380 if (!(rtx_equal_p (cfun_value
, call_value
)
1381 || (REG_P (cfun_value
)
1382 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1386 kind
= m68k_get_function_kind (current_function_decl
);
1387 if (kind
== m68k_fk_normal_function
)
1388 /* We can always sibcall from a normal function, because it's
1389 undefined if it is calling an interrupt function. */
1392 /* Otherwise we can only sibcall if the function kind is known to be
1394 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1400 /* On the m68k all args are always pushed. */
1403 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1404 enum machine_mode mode ATTRIBUTE_UNUSED
,
1405 const_tree type ATTRIBUTE_UNUSED
,
1406 bool named ATTRIBUTE_UNUSED
)
1412 m68k_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1413 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1415 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1417 *cum
+= (mode
!= BLKmode
1418 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1419 : (int_size_in_bytes (type
) + 3) & ~3);
1422 /* Convert X to a legitimate function call memory reference and return the
1426 m68k_legitimize_call_address (rtx x
)
1428 gcc_assert (MEM_P (x
));
1429 if (call_operand (XEXP (x
, 0), VOIDmode
))
1431 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1434 /* Likewise for sibling calls. */
1437 m68k_legitimize_sibcall_address (rtx x
)
1439 gcc_assert (MEM_P (x
));
1440 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1443 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1444 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1447 /* Convert X to a legitimate address and return it if successful. Otherwise
1450 For the 68000, we handle X+REG by loading X into a register R and
1451 using R+REG. R will go in an address reg and indexing will be used.
1452 However, if REG is a broken-out memory address or multiplication,
1453 nothing needs to be done because REG can certainly go in an address reg. */
1456 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1458 if (m68k_tls_symbol_p (x
))
1459 return m68k_legitimize_tls_address (x
);
1461 if (GET_CODE (x
) == PLUS
)
1463 int ch
= (x
) != (oldx
);
1466 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1468 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1471 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1473 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1476 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1480 if (GET_CODE (XEXP (x
, 1)) == REG
1481 && GET_CODE (XEXP (x
, 0)) == REG
)
1483 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1486 x
= force_operand (x
, 0);
1490 if (memory_address_p (mode
, x
))
1493 if (GET_CODE (XEXP (x
, 0)) == REG
1494 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1495 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1496 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1498 rtx temp
= gen_reg_rtx (Pmode
);
1499 rtx val
= force_operand (XEXP (x
, 1), 0);
1500 emit_move_insn (temp
, val
);
1503 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1504 && GET_CODE (XEXP (x
, 0)) == REG
)
1505 x
= force_operand (x
, 0);
1507 else if (GET_CODE (XEXP (x
, 1)) == REG
1508 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1509 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1510 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1512 rtx temp
= gen_reg_rtx (Pmode
);
1513 rtx val
= force_operand (XEXP (x
, 0), 0);
1514 emit_move_insn (temp
, val
);
1517 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1518 && GET_CODE (XEXP (x
, 1)) == REG
)
1519 x
= force_operand (x
, 0);
1527 /* Output a dbCC; jCC sequence. Note we do not handle the
1528 floating point version of this sequence (Fdbcc). We also
1529 do not handle alternative conditions when CC_NO_OVERFLOW is
1530 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1531 kick those out before we get here. */
1534 output_dbcc_and_branch (rtx
*operands
)
1536 switch (GET_CODE (operands
[3]))
1539 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1543 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1547 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1551 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1555 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1559 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1563 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1567 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1571 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1575 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1582 /* If the decrement is to be done in SImode, then we have
1583 to compensate for the fact that dbcc decrements in HImode. */
1584 switch (GET_MODE (operands
[0]))
1587 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1599 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1602 enum rtx_code op_code
= GET_CODE (op
);
1604 /* This does not produce a useful cc. */
1607 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1608 below. Swap the operands and change the op if these requirements
1609 are not fulfilled. */
1610 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1614 operand1
= operand2
;
1616 op_code
= swap_condition (op_code
);
1618 loperands
[0] = operand1
;
1619 if (GET_CODE (operand1
) == REG
)
1620 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1622 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1623 if (operand2
!= const0_rtx
)
1625 loperands
[2] = operand2
;
1626 if (GET_CODE (operand2
) == REG
)
1627 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1629 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1631 loperands
[4] = gen_label_rtx ();
1632 if (operand2
!= const0_rtx
)
1633 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1636 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1637 output_asm_insn ("tst%.l %0", loperands
);
1639 output_asm_insn ("cmp%.w #0,%0", loperands
);
1641 output_asm_insn ("jne %l4", loperands
);
1643 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1644 output_asm_insn ("tst%.l %1", loperands
);
1646 output_asm_insn ("cmp%.w #0,%1", loperands
);
1649 loperands
[5] = dest
;
1654 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1655 CODE_LABEL_NUMBER (loperands
[4]));
1656 output_asm_insn ("seq %5", loperands
);
1660 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1661 CODE_LABEL_NUMBER (loperands
[4]));
1662 output_asm_insn ("sne %5", loperands
);
1666 loperands
[6] = gen_label_rtx ();
1667 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1668 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1669 CODE_LABEL_NUMBER (loperands
[4]));
1670 output_asm_insn ("sgt %5", loperands
);
1671 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1672 CODE_LABEL_NUMBER (loperands
[6]));
1676 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1677 CODE_LABEL_NUMBER (loperands
[4]));
1678 output_asm_insn ("shi %5", loperands
);
1682 loperands
[6] = gen_label_rtx ();
1683 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1684 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1685 CODE_LABEL_NUMBER (loperands
[4]));
1686 output_asm_insn ("slt %5", loperands
);
1687 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1688 CODE_LABEL_NUMBER (loperands
[6]));
1692 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1693 CODE_LABEL_NUMBER (loperands
[4]));
1694 output_asm_insn ("scs %5", loperands
);
1698 loperands
[6] = gen_label_rtx ();
1699 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1700 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1701 CODE_LABEL_NUMBER (loperands
[4]));
1702 output_asm_insn ("sge %5", loperands
);
1703 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1704 CODE_LABEL_NUMBER (loperands
[6]));
1708 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1709 CODE_LABEL_NUMBER (loperands
[4]));
1710 output_asm_insn ("scc %5", loperands
);
1714 loperands
[6] = gen_label_rtx ();
1715 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1716 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1717 CODE_LABEL_NUMBER (loperands
[4]));
1718 output_asm_insn ("sle %5", loperands
);
1719 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1720 CODE_LABEL_NUMBER (loperands
[6]));
1724 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1725 CODE_LABEL_NUMBER (loperands
[4]));
1726 output_asm_insn ("sls %5", loperands
);
1736 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1738 operands
[0] = countop
;
1739 operands
[1] = dataop
;
1741 if (GET_CODE (countop
) == CONST_INT
)
1743 register int count
= INTVAL (countop
);
1744 /* If COUNT is bigger than size of storage unit in use,
1745 advance to the containing unit of same size. */
1746 if (count
> signpos
)
1748 int offset
= (count
& ~signpos
) / 8;
1749 count
= count
& signpos
;
1750 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1752 if (count
== signpos
)
1753 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1755 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1757 /* These three statements used to use next_insns_test_no...
1758 but it appears that this should do the same job. */
1760 && next_insn_tests_no_inequality (insn
))
1763 && next_insn_tests_no_inequality (insn
))
1766 && next_insn_tests_no_inequality (insn
))
1768 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1769 On some m68k variants unfortunately that's slower than btst.
1770 On 68000 and higher, that should also work for all HImode operands. */
1771 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1773 if (count
== 3 && DATA_REG_P (operands
[1])
1774 && next_insn_tests_no_inequality (insn
))
1776 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1777 return "move%.w %1,%%ccr";
1779 if (count
== 2 && DATA_REG_P (operands
[1])
1780 && next_insn_tests_no_inequality (insn
))
1782 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1783 return "move%.w %1,%%ccr";
1785 /* count == 1 followed by bvc/bvs and
1786 count == 0 followed by bcc/bcs are also possible, but need
1787 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1790 cc_status
.flags
= CC_NOT_NEGATIVE
;
1792 return "btst %0,%1";
1795 /* Return true if X is a legitimate base register. STRICT_P says
1796 whether we need strict checking. */
1799 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1801 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1802 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1807 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1808 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1811 /* Return true if X is a legitimate index register. STRICT_P says
1812 whether we need strict checking. */
1815 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1817 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1822 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1823 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1826 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1827 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1828 ADDRESS if so. STRICT_P says whether we need strict checking. */
1831 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1835 /* Check for a scale factor. */
1837 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1838 && GET_CODE (x
) == MULT
1839 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1840 && (INTVAL (XEXP (x
, 1)) == 2
1841 || INTVAL (XEXP (x
, 1)) == 4
1842 || (INTVAL (XEXP (x
, 1)) == 8
1843 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1845 scale
= INTVAL (XEXP (x
, 1));
1849 /* Check for a word extension. */
1850 if (!TARGET_COLDFIRE
1851 && GET_CODE (x
) == SIGN_EXTEND
1852 && GET_MODE (XEXP (x
, 0)) == HImode
)
1855 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1857 address
->scale
= scale
;
1865 /* Return true if X is an illegitimate symbolic constant. */
1868 m68k_illegitimate_symbolic_constant_p (rtx x
)
1872 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1874 split_const (x
, &base
, &offset
);
1875 if (GET_CODE (base
) == SYMBOL_REF
1876 && !offset_within_block_p (base
, INTVAL (offset
)))
1879 return m68k_tls_reference_p (x
, false);
1882 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1885 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1887 return m68k_illegitimate_symbolic_constant_p (x
);
1890 /* Return true if X is a legitimate constant address that can reach
1891 bytes in the range [X, X + REACH). STRICT_P says whether we need
1895 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1899 if (!CONSTANT_ADDRESS_P (x
))
1903 && !(strict_p
&& TARGET_PCREL
)
1904 && symbolic_operand (x
, VOIDmode
))
1907 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1909 split_const (x
, &base
, &offset
);
1910 if (GET_CODE (base
) == SYMBOL_REF
1911 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1915 return !m68k_tls_reference_p (x
, false);
1918 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1919 labels will become jump tables. */
1922 m68k_jump_table_ref_p (rtx x
)
1924 if (GET_CODE (x
) != LABEL_REF
)
1928 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1931 x
= next_nonnote_insn (x
);
1932 return x
&& JUMP_TABLE_DATA_P (x
);
1935 /* Return true if X is a legitimate address for values of mode MODE.
1936 STRICT_P says whether strict checking is needed. If the address
1937 is valid, describe its components in *ADDRESS. */
1940 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1941 bool strict_p
, struct m68k_address
*address
)
1945 memset (address
, 0, sizeof (*address
));
1947 if (mode
== BLKmode
)
1950 reach
= GET_MODE_SIZE (mode
);
1952 /* Check for (An) (mode 2). */
1953 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1959 /* Check for -(An) and (An)+ (modes 3 and 4). */
1960 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1961 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1963 address
->code
= GET_CODE (x
);
1964 address
->base
= XEXP (x
, 0);
1968 /* Check for (d16,An) (mode 5). */
1969 if (GET_CODE (x
) == PLUS
1970 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1971 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1972 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1974 address
->base
= XEXP (x
, 0);
1975 address
->offset
= XEXP (x
, 1);
1979 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1980 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1982 if (GET_CODE (x
) == PLUS
1983 && XEXP (x
, 0) == pic_offset_table_rtx
)
1985 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
1986 they are invalid in this context. */
1987 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
1989 address
->base
= XEXP (x
, 0);
1990 address
->offset
= XEXP (x
, 1);
1995 /* The ColdFire FPU only accepts addressing modes 2-5. */
1996 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1999 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2000 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2001 All these modes are variations of mode 7. */
2002 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2004 address
->offset
= x
;
2008 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2011 ??? do_tablejump creates these addresses before placing the target
2012 label, so we have to assume that unplaced labels are jump table
2013 references. It seems unlikely that we would ever generate indexed
2014 accesses to unplaced labels in other cases. */
2015 if (GET_CODE (x
) == PLUS
2016 && m68k_jump_table_ref_p (XEXP (x
, 1))
2017 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2019 address
->offset
= XEXP (x
, 1);
2023 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2024 (bd,An,Xn.SIZE*SCALE) addresses. */
2028 /* Check for a nonzero base displacement. */
2029 if (GET_CODE (x
) == PLUS
2030 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2032 address
->offset
= XEXP (x
, 1);
2036 /* Check for a suppressed index register. */
2037 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2043 /* Check for a suppressed base register. Do not allow this case
2044 for non-symbolic offsets as it effectively gives gcc freedom
2045 to treat data registers as base registers, which can generate
2048 && symbolic_operand (address
->offset
, VOIDmode
)
2049 && m68k_decompose_index (x
, strict_p
, address
))
2054 /* Check for a nonzero base displacement. */
2055 if (GET_CODE (x
) == PLUS
2056 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2057 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2059 address
->offset
= XEXP (x
, 1);
2064 /* We now expect the sum of a base and an index. */
2065 if (GET_CODE (x
) == PLUS
)
2067 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2068 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2070 address
->base
= XEXP (x
, 0);
2074 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2075 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2077 address
->base
= XEXP (x
, 1);
2084 /* Return true if X is a legitimate address for values of mode MODE.
2085 STRICT_P says whether strict checking is needed. */
2088 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2090 struct m68k_address address
;
2092 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2095 /* Return true if X is a memory, describing its address in ADDRESS if so.
2096 Apply strict checking if called during or after reload. */
2099 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2102 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2103 reload_in_progress
|| reload_completed
,
2107 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2110 m68k_legitimate_constant_p (enum machine_mode mode
, rtx x
)
2112 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2115 /* Return true if X matches the 'Q' constraint. It must be a memory
2116 with a base address and no constant offset or index. */
2119 m68k_matches_q_p (rtx x
)
2121 struct m68k_address address
;
2123 return (m68k_legitimate_mem_p (x
, &address
)
2124 && address
.code
== UNKNOWN
2130 /* Return true if X matches the 'U' constraint. It must be a base address
2131 with a constant offset and no index. */
2134 m68k_matches_u_p (rtx x
)
2136 struct m68k_address address
;
2138 return (m68k_legitimate_mem_p (x
, &address
)
2139 && address
.code
== UNKNOWN
2145 /* Return GOT pointer. */
2150 if (pic_offset_table_rtx
== NULL_RTX
)
2151 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2153 crtl
->uses_pic_offset_table
= 1;
2155 return pic_offset_table_rtx
;
2158 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2160 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2161 RELOC_TLSIE
, RELOC_TLSLE
};
2163 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2165 /* Wrap symbol X into unspec representing relocation RELOC.
2166 BASE_REG - register that should be added to the result.
2167 TEMP_REG - if non-null, temporary register. */
2170 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2174 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2176 if (TARGET_COLDFIRE
&& use_x_p
)
2177 /* When compiling with -mx{got, tls} switch the code will look like this:
2179 move.l <X>@<RELOC>,<TEMP_REG>
2180 add.l <BASE_REG>,<TEMP_REG> */
2182 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2183 to put @RELOC after reference. */
2184 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2186 x
= gen_rtx_CONST (Pmode
, x
);
2188 if (temp_reg
== NULL
)
2190 gcc_assert (can_create_pseudo_p ());
2191 temp_reg
= gen_reg_rtx (Pmode
);
2194 emit_move_insn (temp_reg
, x
);
2195 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2200 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2202 x
= gen_rtx_CONST (Pmode
, x
);
2204 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2210 /* Helper for m68k_unwrap_symbol.
2211 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2212 sets *RELOC_PTR to relocation type for the symbol. */
2215 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2216 enum m68k_reloc
*reloc_ptr
)
2218 if (GET_CODE (orig
) == CONST
)
2221 enum m68k_reloc dummy
;
2225 if (reloc_ptr
== NULL
)
2228 /* Handle an addend. */
2229 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2230 && CONST_INT_P (XEXP (x
, 1)))
2233 if (GET_CODE (x
) == UNSPEC
)
2235 switch (XINT (x
, 1))
2237 case UNSPEC_RELOC16
:
2238 orig
= XVECEXP (x
, 0, 0);
2239 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2242 case UNSPEC_RELOC32
:
2243 if (unwrap_reloc32_p
)
2245 orig
= XVECEXP (x
, 0, 0);
2246 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2259 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2260 UNSPEC_RELOC32 wrappers. */
2263 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2265 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2268 /* Helper for m68k_final_prescan_insn. */
2271 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2275 if (m68k_unwrap_symbol (x
, true) != x
)
2276 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2280 gcc_assert (GET_CODE (x
) == CONST
);
2283 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2288 unspec
= XEXP (plus
, 0);
2289 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2290 addend
= XEXP (plus
, 1);
2291 gcc_assert (CONST_INT_P (addend
));
2293 /* We now have all the pieces, rearrange them. */
2295 /* Move symbol to plus. */
2296 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2298 /* Move plus inside unspec. */
2299 XVECEXP (unspec
, 0, 0) = plus
;
2301 /* Move unspec to top level of const. */
2302 XEXP (x
, 0) = unspec
;
2311 /* Prescan insn before outputing assembler for it. */
2314 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2315 rtx
*operands
, int n_operands
)
2319 /* Combine and, possibly, other optimizations may do good job
2321 (const (unspec [(symbol)]))
2323 (const (plus (unspec [(symbol)])
2325 The problem with this is emitting @TLS or @GOT decorations.
2326 The decoration is emitted when processing (unspec), so the
2327 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2329 It seems that the easiest solution to this is to convert such
2331 (const (unspec [(plus (symbol)
2333 Note, that the top level of operand remains intact, so we don't have
2334 to patch up anything outside of the operand. */
2336 for (i
= 0; i
< n_operands
; ++i
)
2342 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2346 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2347 If REG is non-null, use it; generate new pseudo otherwise. */
2350 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2354 if (reg
== NULL_RTX
)
2356 gcc_assert (can_create_pseudo_p ());
2357 reg
= gen_reg_rtx (Pmode
);
2360 insn
= emit_move_insn (reg
, x
);
2361 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2363 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2368 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2372 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2374 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2376 x
= gen_rtx_MEM (Pmode
, x
);
2377 MEM_READONLY_P (x
) = 1;
2382 /* Legitimize PIC addresses. If the address is already
2383 position-independent, we return ORIG. Newly generated
2384 position-independent addresses go to REG. If we need more
2385 than one register, we lose.
2387 An address is legitimized by making an indirect reference
2388 through the Global Offset Table with the name of the symbol
2391 The assembler and linker are responsible for placing the
2392 address of the symbol in the GOT. The function prologue
2393 is responsible for initializing a5 to the starting address
2396 The assembler is also responsible for translating a symbol name
2397 into a constant displacement from the start of the GOT.
2399 A quick example may make things a little clearer:
2401 When not generating PIC code to store the value 12345 into _foo
2402 we would generate the following code:
2406 When generating PIC two transformations are made. First, the compiler
2407 loads the address of foo into a register. So the first transformation makes:
2412 The code in movsi will intercept the lea instruction and call this
2413 routine which will transform the instructions into:
2415 movel a5@(_foo:w), a0
2419 That (in a nutshell) is how *all* symbol and label references are
2423 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2428 /* First handle a simple SYMBOL_REF or LABEL_REF */
2429 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2433 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2434 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2436 else if (GET_CODE (orig
) == CONST
)
2440 /* Make sure this has not already been legitimized. */
2441 if (m68k_unwrap_symbol (orig
, true) != orig
)
2446 /* legitimize both operands of the PLUS */
2447 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2449 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2450 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2451 base
== reg
? 0 : reg
);
2453 if (GET_CODE (orig
) == CONST_INT
)
2454 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2456 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2462 /* The __tls_get_addr symbol. */
2463 static GTY(()) rtx m68k_tls_get_addr
;
2465 /* Return SYMBOL_REF for __tls_get_addr. */
2468 m68k_get_tls_get_addr (void)
2470 if (m68k_tls_get_addr
== NULL_RTX
)
2471 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2473 return m68k_tls_get_addr
;
2476 /* Return libcall result in A0 instead of usual D0. */
2477 static bool m68k_libcall_value_in_a0_p
= false;
2479 /* Emit instruction sequence that calls __tls_get_addr. X is
2480 the TLS symbol we are referencing and RELOC is the symbol type to use
2481 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2482 emitted. A pseudo register with result of __tls_get_addr call is
2486 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2492 /* Emit the call sequence. */
2495 /* FIXME: Unfortunately, emit_library_call_value does not
2496 consider (plus (%a5) (const (unspec))) to be a good enough
2497 operand for push, so it forces it into a register. The bad
2498 thing about this is that combiner, due to copy propagation and other
2499 optimizations, sometimes can not later fix this. As a consequence,
2500 additional register may be allocated resulting in a spill.
2501 For reference, see args processing loops in
2502 calls.c:emit_library_call_value_1.
2503 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2504 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2506 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2507 is the simpliest way of generating a call. The difference between
2508 __tls_get_addr() and libcall is that the result is returned in D0
2509 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2510 which temporarily switches returning the result to A0. */
2512 m68k_libcall_value_in_a0_p
= true;
2513 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2514 Pmode
, 1, x
, Pmode
);
2515 m68k_libcall_value_in_a0_p
= false;
2517 insns
= get_insns ();
2520 gcc_assert (can_create_pseudo_p ());
2521 dest
= gen_reg_rtx (Pmode
);
2522 emit_libcall_block (insns
, dest
, a0
, eqv
);
2527 /* The __tls_get_addr symbol. */
2528 static GTY(()) rtx m68k_read_tp
;
2530 /* Return SYMBOL_REF for __m68k_read_tp. */
2533 m68k_get_m68k_read_tp (void)
2535 if (m68k_read_tp
== NULL_RTX
)
2536 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2538 return m68k_read_tp
;
2541 /* Emit instruction sequence that calls __m68k_read_tp.
2542 A pseudo register with result of __m68k_read_tp call is returned. */
2545 m68k_call_m68k_read_tp (void)
2554 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2555 is the simpliest way of generating a call. The difference between
2556 __m68k_read_tp() and libcall is that the result is returned in D0
2557 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2558 which temporarily switches returning the result to A0. */
2560 /* Emit the call sequence. */
2561 m68k_libcall_value_in_a0_p
= true;
2562 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2564 m68k_libcall_value_in_a0_p
= false;
2565 insns
= get_insns ();
2568 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2569 share the m68k_read_tp result with other IE/LE model accesses. */
2570 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2572 gcc_assert (can_create_pseudo_p ());
2573 dest
= gen_reg_rtx (Pmode
);
2574 emit_libcall_block (insns
, dest
, a0
, eqv
);
2579 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2580 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2584 m68k_legitimize_tls_address (rtx orig
)
2586 switch (SYMBOL_REF_TLS_MODEL (orig
))
2588 case TLS_MODEL_GLOBAL_DYNAMIC
:
2589 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2592 case TLS_MODEL_LOCAL_DYNAMIC
:
2598 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2599 share the LDM result with other LD model accesses. */
2600 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2603 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2605 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2607 if (can_create_pseudo_p ())
2608 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2614 case TLS_MODEL_INITIAL_EXEC
:
2619 a0
= m68k_call_m68k_read_tp ();
2621 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2622 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2624 if (can_create_pseudo_p ())
2625 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2631 case TLS_MODEL_LOCAL_EXEC
:
2636 a0
= m68k_call_m68k_read_tp ();
2638 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2640 if (can_create_pseudo_p ())
2641 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2654 /* Return true if X is a TLS symbol. */
2657 m68k_tls_symbol_p (rtx x
)
2659 if (!TARGET_HAVE_TLS
)
2662 if (GET_CODE (x
) != SYMBOL_REF
)
2665 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2668 /* Helper for m68k_tls_referenced_p. */
2671 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2673 /* Note: this is not the same as m68k_tls_symbol_p. */
2674 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2675 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2677 /* Don't recurse into legitimate TLS references. */
2678 if (m68k_tls_reference_p (*x_ptr
, true))
2684 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2685 though illegitimate one.
2686 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2689 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2691 if (!TARGET_HAVE_TLS
)
2695 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2698 enum m68k_reloc reloc
= RELOC_GOT
;
2700 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2701 && TLS_RELOC_P (reloc
));
2707 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2709 /* Return the type of move that should be used for integer I. */
2712 m68k_const_method (HOST_WIDE_INT i
)
2719 /* The ColdFire doesn't have byte or word operations. */
2720 /* FIXME: This may not be useful for the m68060 either. */
2721 if (!TARGET_COLDFIRE
)
2723 /* if -256 < N < 256 but N is not in range for a moveq
2724 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2725 if (USE_MOVQ (i
^ 0xff))
2727 /* Likewise, try with not.w */
2728 if (USE_MOVQ (i
^ 0xffff))
2730 /* This is the only value where neg.w is useful */
2735 /* Try also with swap. */
2737 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2742 /* Try using MVZ/MVS with an immediate value to load constants. */
2743 if (i
>= 0 && i
<= 65535)
2745 if (i
>= -32768 && i
<= 32767)
2749 /* Otherwise, use move.l */
2753 /* Return the cost of moving constant I into a data register. */
2756 const_int_cost (HOST_WIDE_INT i
)
2758 switch (m68k_const_method (i
))
2761 /* Constants between -128 and 127 are cheap due to moveq. */
2769 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2779 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2780 int *total
, bool speed ATTRIBUTE_UNUSED
)
2785 /* Constant zero is super cheap due to clr instruction. */
2786 if (x
== const0_rtx
)
2789 *total
= const_int_cost (INTVAL (x
));
2799 /* Make 0.0 cheaper than other floating constants to
2800 encourage creating tstsf and tstdf insns. */
2801 if (outer_code
== COMPARE
2802 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2808 /* These are vaguely right for a 68020. */
2809 /* The costs for long multiply have been adjusted to work properly
2810 in synth_mult on the 68020, relative to an average of the time
2811 for add and the time for shift, taking away a little more because
2812 sometimes move insns are needed. */
2813 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2818 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2819 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2821 : TARGET_COLDFIRE ? 3 : 13)
2826 : TUNE_68000_10 ? 5 \
2827 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2828 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2830 : TARGET_COLDFIRE ? 2 : 8)
2833 (TARGET_CF_HWDIV ? 11 \
2834 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2837 /* An lea costs about three times as much as a simple add. */
2838 if (GET_MODE (x
) == SImode
2839 && GET_CODE (XEXP (x
, 1)) == REG
2840 && GET_CODE (XEXP (x
, 0)) == MULT
2841 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2842 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2843 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2844 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2845 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2847 /* lea an@(dx:l:i),am */
2848 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2858 *total
= COSTS_N_INSNS(1);
2863 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2865 if (INTVAL (XEXP (x
, 1)) < 16)
2866 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2868 /* We're using clrw + swap for these cases. */
2869 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2872 *total
= COSTS_N_INSNS (10); /* Worst case. */
2875 /* A shift by a big integer takes an extra instruction. */
2876 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2877 && (INTVAL (XEXP (x
, 1)) == 16))
2879 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2882 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2883 && !(INTVAL (XEXP (x
, 1)) > 0
2884 && INTVAL (XEXP (x
, 1)) <= 8))
2886 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2892 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2893 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2894 && GET_MODE (x
) == SImode
)
2895 *total
= COSTS_N_INSNS (MULW_COST
);
2896 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2897 *total
= COSTS_N_INSNS (MULW_COST
);
2899 *total
= COSTS_N_INSNS (MULL_COST
);
2906 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2907 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2908 else if (TARGET_CF_HWDIV
)
2909 *total
= COSTS_N_INSNS (18);
2911 *total
= COSTS_N_INSNS (43); /* div.l */
2915 if (outer_code
== COMPARE
)
2924 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2928 output_move_const_into_data_reg (rtx
*operands
)
2932 i
= INTVAL (operands
[1]);
2933 switch (m68k_const_method (i
))
2936 return "mvzw %1,%0";
2938 return "mvsw %1,%0";
2940 return "moveq %1,%0";
2943 operands
[1] = GEN_INT (i
^ 0xff);
2944 return "moveq %1,%0\n\tnot%.b %0";
2947 operands
[1] = GEN_INT (i
^ 0xffff);
2948 return "moveq %1,%0\n\tnot%.w %0";
2951 return "moveq #-128,%0\n\tneg%.w %0";
2956 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2957 return "moveq %1,%0\n\tswap %0";
2960 return "move%.l %1,%0";
2966 /* Return true if I can be handled by ISA B's mov3q instruction. */
2969 valid_mov3q_const (HOST_WIDE_INT i
)
2971 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2974 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2975 I is the value of OPERANDS[1]. */
2978 output_move_simode_const (rtx
*operands
)
2984 src
= INTVAL (operands
[1]);
2986 && (DATA_REG_P (dest
) || MEM_P (dest
))
2987 /* clr insns on 68000 read before writing. */
2988 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2989 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2991 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2992 return "mov3q%.l %1,%0";
2993 else if (src
== 0 && ADDRESS_REG_P (dest
))
2994 return "sub%.l %0,%0";
2995 else if (DATA_REG_P (dest
))
2996 return output_move_const_into_data_reg (operands
);
2997 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2999 if (valid_mov3q_const (src
))
3000 return "mov3q%.l %1,%0";
3001 return "move%.w %1,%0";
3003 else if (MEM_P (dest
)
3004 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3005 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3006 && IN_RANGE (src
, -0x8000, 0x7fff))
3008 if (valid_mov3q_const (src
))
3009 return "mov3q%.l %1,%-";
3012 return "move%.l %1,%0";
3016 output_move_simode (rtx
*operands
)
3018 if (GET_CODE (operands
[1]) == CONST_INT
)
3019 return output_move_simode_const (operands
);
3020 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3021 || GET_CODE (operands
[1]) == CONST
)
3022 && push_operand (operands
[0], SImode
))
3024 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3025 || GET_CODE (operands
[1]) == CONST
)
3026 && ADDRESS_REG_P (operands
[0]))
3027 return "lea %a1,%0";
3028 return "move%.l %1,%0";
3032 output_move_himode (rtx
*operands
)
3034 if (GET_CODE (operands
[1]) == CONST_INT
)
3036 if (operands
[1] == const0_rtx
3037 && (DATA_REG_P (operands
[0])
3038 || GET_CODE (operands
[0]) == MEM
)
3039 /* clr insns on 68000 read before writing. */
3040 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3041 || !(GET_CODE (operands
[0]) == MEM
3042 && MEM_VOLATILE_P (operands
[0]))))
3044 else if (operands
[1] == const0_rtx
3045 && ADDRESS_REG_P (operands
[0]))
3046 return "sub%.l %0,%0";
3047 else if (DATA_REG_P (operands
[0])
3048 && INTVAL (operands
[1]) < 128
3049 && INTVAL (operands
[1]) >= -128)
3050 return "moveq %1,%0";
3051 else if (INTVAL (operands
[1]) < 0x8000
3052 && INTVAL (operands
[1]) >= -0x8000)
3053 return "move%.w %1,%0";
3055 else if (CONSTANT_P (operands
[1]))
3056 return "move%.l %1,%0";
3057 return "move%.w %1,%0";
3061 output_move_qimode (rtx
*operands
)
3063 /* 68k family always modifies the stack pointer by at least 2, even for
3064 byte pushes. The 5200 (ColdFire) does not do this. */
3066 /* This case is generated by pushqi1 pattern now. */
3067 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3068 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3069 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3070 && ! ADDRESS_REG_P (operands
[1])
3071 && ! TARGET_COLDFIRE
));
3073 /* clr and st insns on 68000 read before writing. */
3074 if (!ADDRESS_REG_P (operands
[0])
3075 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3076 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3078 if (operands
[1] == const0_rtx
)
3080 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3081 && GET_CODE (operands
[1]) == CONST_INT
3082 && (INTVAL (operands
[1]) & 255) == 255)
3088 if (GET_CODE (operands
[1]) == CONST_INT
3089 && DATA_REG_P (operands
[0])
3090 && INTVAL (operands
[1]) < 128
3091 && INTVAL (operands
[1]) >= -128)
3092 return "moveq %1,%0";
3093 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3094 return "sub%.l %0,%0";
3095 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3096 return "move%.l %1,%0";
3097 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3098 from address registers. */
3099 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3100 return "move%.w %1,%0";
3101 return "move%.b %1,%0";
3105 output_move_stricthi (rtx
*operands
)
3107 if (operands
[1] == const0_rtx
3108 /* clr insns on 68000 read before writing. */
3109 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3110 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3112 return "move%.w %1,%0";
3116 output_move_strictqi (rtx
*operands
)
3118 if (operands
[1] == const0_rtx
3119 /* clr insns on 68000 read before writing. */
3120 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3121 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3123 return "move%.b %1,%0";
3126 /* Return the best assembler insn template
3127 for moving operands[1] into operands[0] as a fullword. */
3130 singlemove_string (rtx
*operands
)
3132 if (GET_CODE (operands
[1]) == CONST_INT
)
3133 return output_move_simode_const (operands
);
3134 return "move%.l %1,%0";
3138 /* Output assembler or rtl code to perform a doubleword move insn
3139 with operands OPERANDS.
3140 Pointers to 3 helper functions should be specified:
3141 HANDLE_REG_ADJUST to adjust a register by a small value,
3142 HANDLE_COMPADR to compute an address and
3143 HANDLE_MOVSI to move 4 bytes. */
3146 handle_move_double (rtx operands
[2],
3147 void (*handle_reg_adjust
) (rtx
, int),
3148 void (*handle_compadr
) (rtx
[2]),
3149 void (*handle_movsi
) (rtx
[2]))
3153 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3158 rtx addreg0
= 0, addreg1
= 0;
3159 int dest_overlapped_low
= 0;
3160 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3165 /* First classify both operands. */
3167 if (REG_P (operands
[0]))
3169 else if (offsettable_memref_p (operands
[0]))
3171 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3173 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3175 else if (GET_CODE (operands
[0]) == MEM
)
3180 if (REG_P (operands
[1]))
3182 else if (CONSTANT_P (operands
[1]))
3184 else if (offsettable_memref_p (operands
[1]))
3186 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3188 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3190 else if (GET_CODE (operands
[1]) == MEM
)
3195 /* Check for the cases that the operand constraints are not supposed
3196 to allow to happen. Generating code for these cases is
3198 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3200 /* If one operand is decrementing and one is incrementing
3201 decrement the former register explicitly
3202 and change that operand into ordinary indexing. */
3204 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3206 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3208 handle_reg_adjust (operands
[0], -size
);
3210 if (GET_MODE (operands
[1]) == XFmode
)
3211 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3212 else if (GET_MODE (operands
[0]) == DFmode
)
3213 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3215 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3218 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3220 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3222 handle_reg_adjust (operands
[1], -size
);
3224 if (GET_MODE (operands
[1]) == XFmode
)
3225 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3226 else if (GET_MODE (operands
[1]) == DFmode
)
3227 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3229 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3233 /* If an operand is an unoffsettable memory ref, find a register
3234 we can increment temporarily to make it refer to the second word. */
3236 if (optype0
== MEMOP
)
3237 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3239 if (optype1
== MEMOP
)
3240 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3242 /* Ok, we can do one word at a time.
3243 Normally we do the low-numbered word first,
3244 but if either operand is autodecrementing then we
3245 do the high-numbered word first.
3247 In either case, set up in LATEHALF the operands to use
3248 for the high-numbered word and in some cases alter the
3249 operands in OPERANDS to be suitable for the low-numbered word. */
3253 if (optype0
== REGOP
)
3255 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3256 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3258 else if (optype0
== OFFSOP
)
3260 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3261 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3265 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3266 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3269 if (optype1
== REGOP
)
3271 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3272 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3274 else if (optype1
== OFFSOP
)
3276 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3277 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3279 else if (optype1
== CNSTOP
)
3281 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3286 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3287 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3288 operands
[1] = GEN_INT (l
[0]);
3289 middlehalf
[1] = GEN_INT (l
[1]);
3290 latehalf
[1] = GEN_INT (l
[2]);
3294 /* No non-CONST_DOUBLE constant should ever appear
3296 gcc_assert (!CONSTANT_P (operands
[1]));
3301 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3302 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3306 /* size is not 12: */
3308 if (optype0
== REGOP
)
3309 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3310 else if (optype0
== OFFSOP
)
3311 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3313 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3315 if (optype1
== REGOP
)
3316 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3317 else if (optype1
== OFFSOP
)
3318 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3319 else if (optype1
== CNSTOP
)
3320 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3322 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3325 /* If insn is effectively movd N(sp),-(sp) then we will do the
3326 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3327 for the low word as well, to compensate for the first decrement of sp. */
3328 if (optype0
== PUSHOP
3329 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3330 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3331 operands
[1] = middlehalf
[1] = latehalf
[1];
3333 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3334 if the upper part of reg N does not appear in the MEM, arrange to
3335 emit the move late-half first. Otherwise, compute the MEM address
3336 into the upper part of N and use that as a pointer to the memory
3338 if (optype0
== REGOP
3339 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3341 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3343 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3344 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3346 /* If both halves of dest are used in the src memory address,
3347 compute the address into latehalf of dest.
3348 Note that this can't happen if the dest is two data regs. */
3350 xops
[0] = latehalf
[0];
3351 xops
[1] = XEXP (operands
[1], 0);
3353 handle_compadr (xops
);
3354 if (GET_MODE (operands
[1]) == XFmode
)
3356 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3357 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3358 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3362 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3363 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3367 && reg_overlap_mentioned_p (middlehalf
[0],
3368 XEXP (operands
[1], 0)))
3370 /* Check for two regs used by both source and dest.
3371 Note that this can't happen if the dest is all data regs.
3372 It can happen if the dest is d6, d7, a0.
3373 But in that case, latehalf is an addr reg, so
3374 the code at compadr does ok. */
3376 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3377 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3380 /* JRV says this can't happen: */
3381 gcc_assert (!addreg0
&& !addreg1
);
3383 /* Only the middle reg conflicts; simply put it last. */
3384 handle_movsi (operands
);
3385 handle_movsi (latehalf
);
3386 handle_movsi (middlehalf
);
3390 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3391 /* If the low half of dest is mentioned in the source memory
3392 address, the arrange to emit the move late half first. */
3393 dest_overlapped_low
= 1;
3396 /* If one or both operands autodecrementing,
3397 do the two words, high-numbered first. */
3399 /* Likewise, the first move would clobber the source of the second one,
3400 do them in the other order. This happens only for registers;
3401 such overlap can't happen in memory unless the user explicitly
3402 sets it up, and that is an undefined circumstance. */
3404 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3405 || (optype0
== REGOP
&& optype1
== REGOP
3406 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3407 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3408 || dest_overlapped_low
)
3410 /* Make any unoffsettable addresses point at high-numbered word. */
3412 handle_reg_adjust (addreg0
, size
- 4);
3414 handle_reg_adjust (addreg1
, size
- 4);
3417 handle_movsi (latehalf
);
3419 /* Undo the adds we just did. */
3421 handle_reg_adjust (addreg0
, -4);
3423 handle_reg_adjust (addreg1
, -4);
3427 handle_movsi (middlehalf
);
3430 handle_reg_adjust (addreg0
, -4);
3432 handle_reg_adjust (addreg1
, -4);
3435 /* Do low-numbered word. */
3437 handle_movsi (operands
);
3441 /* Normal case: do the two words, low-numbered first. */
3443 m68k_final_prescan_insn (NULL
, operands
, 2);
3444 handle_movsi (operands
);
3446 /* Do the middle one of the three words for long double */
3450 handle_reg_adjust (addreg0
, 4);
3452 handle_reg_adjust (addreg1
, 4);
3454 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3455 handle_movsi (middlehalf
);
3458 /* Make any unoffsettable addresses point at high-numbered word. */
3460 handle_reg_adjust (addreg0
, 4);
3462 handle_reg_adjust (addreg1
, 4);
3465 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3466 handle_movsi (latehalf
);
3468 /* Undo the adds we just did. */
3470 handle_reg_adjust (addreg0
, -(size
- 4));
3472 handle_reg_adjust (addreg1
, -(size
- 4));
3477 /* Output assembler code to adjust REG by N. */
3479 output_reg_adjust (rtx reg
, int n
)
3483 gcc_assert (GET_MODE (reg
) == SImode
3484 && -12 <= n
&& n
!= 0 && n
<= 12);
3489 s
= "add%.l #12,%0";
3493 s
= "addq%.l #8,%0";
3497 s
= "addq%.l #4,%0";
3501 s
= "sub%.l #12,%0";
3505 s
= "subq%.l #8,%0";
3509 s
= "subq%.l #4,%0";
3517 output_asm_insn (s
, ®
);
3520 /* Emit rtl code to adjust REG by N. */
3522 emit_reg_adjust (rtx reg1
, int n
)
3526 gcc_assert (GET_MODE (reg1
) == SImode
3527 && -12 <= n
&& n
!= 0 && n
<= 12);
3529 reg1
= copy_rtx (reg1
);
3530 reg2
= copy_rtx (reg1
);
3533 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3535 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3540 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3542 output_compadr (rtx operands
[2])
3544 output_asm_insn ("lea %a1,%0", operands
);
3547 /* Output the best assembler insn for moving operands[1] into operands[0]
3550 output_movsi (rtx operands
[2])
3552 output_asm_insn (singlemove_string (operands
), operands
);
3555 /* Copy OP and change its mode to MODE. */
3557 copy_operand (rtx op
, enum machine_mode mode
)
3559 /* ??? This looks really ugly. There must be a better way
3560 to change a mode on the operand. */
3561 if (GET_MODE (op
) != VOIDmode
)
3564 op
= gen_rtx_REG (mode
, REGNO (op
));
3568 PUT_MODE (op
, mode
);
3575 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3577 emit_movsi (rtx operands
[2])
3579 operands
[0] = copy_operand (operands
[0], SImode
);
3580 operands
[1] = copy_operand (operands
[1], SImode
);
3582 emit_insn (gen_movsi (operands
[0], operands
[1]));
3585 /* Output assembler code to perform a doubleword move insn
3586 with operands OPERANDS. */
3588 output_move_double (rtx
*operands
)
3590 handle_move_double (operands
,
3591 output_reg_adjust
, output_compadr
, output_movsi
);
3596 /* Output rtl code to perform a doubleword move insn
3597 with operands OPERANDS. */
3599 m68k_emit_move_double (rtx operands
[2])
3601 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3604 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3605 new rtx with the correct mode. */
3608 force_mode (enum machine_mode mode
, rtx orig
)
3610 if (mode
== GET_MODE (orig
))
3613 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3616 return gen_rtx_REG (mode
, REGNO (orig
));
3620 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3622 return reg_renumber
&& FP_REG_P (op
);
3625 /* Emit insns to move operands[1] into operands[0].
3627 Return 1 if we have written out everything that needs to be done to
3628 do the move. Otherwise, return 0 and the caller will emit the move
3631 Note SCRATCH_REG may not be in the proper mode depending on how it
3632 will be used. This routine is responsible for creating a new copy
3633 of SCRATCH_REG in the proper mode. */
3636 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3638 register rtx operand0
= operands
[0];
3639 register rtx operand1
= operands
[1];
3643 && reload_in_progress
&& GET_CODE (operand0
) == REG
3644 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3645 operand0
= reg_equiv_mem (REGNO (operand0
));
3646 else if (scratch_reg
3647 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3648 && GET_CODE (SUBREG_REG (operand0
)) == REG
3649 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3651 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3652 the code which tracks sets/uses for delete_output_reload. */
3653 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3654 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3655 SUBREG_BYTE (operand0
));
3656 operand0
= alter_subreg (&temp
);
3660 && reload_in_progress
&& GET_CODE (operand1
) == REG
3661 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3662 operand1
= reg_equiv_mem (REGNO (operand1
));
3663 else if (scratch_reg
3664 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3665 && GET_CODE (SUBREG_REG (operand1
)) == REG
3666 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3668 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3669 the code which tracks sets/uses for delete_output_reload. */
3670 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3671 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3672 SUBREG_BYTE (operand1
));
3673 operand1
= alter_subreg (&temp
);
3676 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3677 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3678 != XEXP (operand0
, 0)))
3679 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3680 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3681 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3682 != XEXP (operand1
, 0)))
3683 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3685 /* Handle secondary reloads for loads/stores of FP registers where
3686 the address is symbolic by using the scratch register */
3687 if (fp_reg_operand (operand0
, mode
)
3688 && ((GET_CODE (operand1
) == MEM
3689 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3690 || ((GET_CODE (operand1
) == SUBREG
3691 && GET_CODE (XEXP (operand1
, 0)) == MEM
3692 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3695 if (GET_CODE (operand1
) == SUBREG
)
3696 operand1
= XEXP (operand1
, 0);
3698 /* SCRATCH_REG will hold an address. We want
3699 it in SImode regardless of what mode it was originally given
3701 scratch_reg
= force_mode (SImode
, scratch_reg
);
3703 /* D might not fit in 14 bits either; for such cases load D into
3705 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3707 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3708 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3710 XEXP (XEXP (operand1
, 0), 0),
3714 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3715 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3716 gen_rtx_MEM (mode
, scratch_reg
)));
3719 else if (fp_reg_operand (operand1
, mode
)
3720 && ((GET_CODE (operand0
) == MEM
3721 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3722 || ((GET_CODE (operand0
) == SUBREG
)
3723 && GET_CODE (XEXP (operand0
, 0)) == MEM
3724 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3727 if (GET_CODE (operand0
) == SUBREG
)
3728 operand0
= XEXP (operand0
, 0);
3730 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3731 it in SIMODE regardless of what mode it was originally given
3733 scratch_reg
= force_mode (SImode
, scratch_reg
);
3735 /* D might not fit in 14 bits either; for such cases load D into
3737 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3739 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3740 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3743 XEXP (XEXP (operand0
, 0),
3748 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3749 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3753 /* Handle secondary reloads for loads of FP registers from constant
3754 expressions by forcing the constant into memory.
3756 use scratch_reg to hold the address of the memory location.
3758 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3759 NO_REGS when presented with a const_int and an register class
3760 containing only FP registers. Doing so unfortunately creates
3761 more problems than it solves. Fix this for 2.5. */
3762 else if (fp_reg_operand (operand0
, mode
)
3763 && CONSTANT_P (operand1
)
3768 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3769 it in SIMODE regardless of what mode it was originally given
3771 scratch_reg
= force_mode (SImode
, scratch_reg
);
3773 /* Force the constant into memory and put the address of the
3774 memory location into scratch_reg. */
3775 xoperands
[0] = scratch_reg
;
3776 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3777 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3779 /* Now load the destination register. */
3780 emit_insn (gen_rtx_SET (mode
, operand0
,
3781 gen_rtx_MEM (mode
, scratch_reg
)));
3785 /* Now have insn-emit do whatever it normally does. */
3789 /* Split one or more DImode RTL references into pairs of SImode
3790 references. The RTL can be REG, offsettable MEM, integer constant, or
3791 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3792 split and "num" is its length. lo_half and hi_half are output arrays
3793 that parallel "operands". */
3796 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3800 rtx op
= operands
[num
];
3802 /* simplify_subreg refuses to split volatile memory addresses,
3803 but we still have to handle it. */
3804 if (GET_CODE (op
) == MEM
)
3806 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3807 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3811 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3812 GET_MODE (op
) == VOIDmode
3813 ? DImode
: GET_MODE (op
), 4);
3814 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3815 GET_MODE (op
) == VOIDmode
3816 ? DImode
: GET_MODE (op
), 0);
3821 /* Split X into a base and a constant offset, storing them in *BASE
3822 and *OFFSET respectively. */
3825 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3828 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3830 *offset
+= INTVAL (XEXP (x
, 1));
3836 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3837 instruction. STORE_P says whether the move is a load or store.
3839 If the instruction uses post-increment or pre-decrement addressing,
3840 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3841 adjustment. This adjustment will be made by the first element of
3842 PARALLEL, with the loads or stores starting at element 1. If the
3843 instruction does not use post-increment or pre-decrement addressing,
3844 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3845 start at element 0. */
3848 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3849 HOST_WIDE_INT automod_offset
, bool store_p
)
3851 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3852 HOST_WIDE_INT offset
, mem_offset
;
3854 enum reg_class rclass
;
3856 len
= XVECLEN (pattern
, 0);
3857 first
= (automod_base
!= NULL
);
3861 /* Stores must be pre-decrement and loads must be post-increment. */
3862 if (store_p
!= (automod_offset
< 0))
3865 /* Work out the base and offset for lowest memory location. */
3866 base
= automod_base
;
3867 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3871 /* Allow any valid base and offset in the first access. */
3878 for (i
= first
; i
< len
; i
++)
3880 /* We need a plain SET. */
3881 set
= XVECEXP (pattern
, 0, i
);
3882 if (GET_CODE (set
) != SET
)
3885 /* Check that we have a memory location... */
3886 mem
= XEXP (set
, !store_p
);
3887 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3890 /* ...with the right address. */
3893 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3894 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3895 There are no mode restrictions for 680x0 besides the
3896 automodification rules enforced above. */
3898 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3903 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3904 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3908 /* Check that we have a register of the required mode and class. */
3909 reg
= XEXP (set
, store_p
);
3911 || !HARD_REGISTER_P (reg
)
3912 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3917 /* The register must belong to RCLASS and have a higher number
3918 than the register in the previous SET. */
3919 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3920 || REGNO (last_reg
) >= REGNO (reg
))
3925 /* Work out which register class we need. */
3926 if (INT_REGNO_P (REGNO (reg
)))
3927 rclass
= GENERAL_REGS
;
3928 else if (FP_REGNO_P (REGNO (reg
)))
3935 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3938 /* If we have an automodification, check whether the final offset is OK. */
3939 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3942 /* Reject unprofitable cases. */
3943 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3949 /* Return the assembly code template for a movem or fmovem instruction
3950 whose pattern is given by PATTERN. Store the template's operands
3953 If the instruction uses post-increment or pre-decrement addressing,
3954 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3955 is true if this is a store instruction. */
3958 m68k_output_movem (rtx
*operands
, rtx pattern
,
3959 HOST_WIDE_INT automod_offset
, bool store_p
)
3964 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3966 first
= (automod_offset
!= 0);
3967 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3969 /* When using movem with pre-decrement addressing, register X + D0_REG
3970 is controlled by bit 15 - X. For all other addressing modes,
3971 register X + D0_REG is controlled by bit X. Confusingly, the
3972 register mask for fmovem is in the opposite order to that for
3976 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3977 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3978 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3979 if (automod_offset
< 0)
3981 if (FP_REGNO_P (regno
))
3982 mask
|= 1 << (regno
- FP0_REG
);
3984 mask
|= 1 << (15 - (regno
- D0_REG
));
3988 if (FP_REGNO_P (regno
))
3989 mask
|= 1 << (7 - (regno
- FP0_REG
));
3991 mask
|= 1 << (regno
- D0_REG
);
3996 if (automod_offset
== 0)
3997 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3998 else if (automod_offset
< 0)
3999 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4001 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4002 operands
[1] = GEN_INT (mask
);
4003 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4006 return "fmovem %1,%a0";
4008 return "fmovem %a0,%1";
4013 return "movem%.l %1,%a0";
4015 return "movem%.l %a0,%1";
4019 /* Return a REG that occurs in ADDR with coefficient 1.
4020 ADDR can be effectively incremented by incrementing REG. */
4023 find_addr_reg (rtx addr
)
4025 while (GET_CODE (addr
) == PLUS
)
4027 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4028 addr
= XEXP (addr
, 0);
4029 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4030 addr
= XEXP (addr
, 1);
4031 else if (CONSTANT_P (XEXP (addr
, 0)))
4032 addr
= XEXP (addr
, 1);
4033 else if (CONSTANT_P (XEXP (addr
, 1)))
4034 addr
= XEXP (addr
, 0);
4038 gcc_assert (GET_CODE (addr
) == REG
);
4042 /* Output assembler code to perform a 32-bit 3-operand add. */
4045 output_addsi3 (rtx
*operands
)
4047 if (! operands_match_p (operands
[0], operands
[1]))
4049 if (!ADDRESS_REG_P (operands
[1]))
4051 rtx tmp
= operands
[1];
4053 operands
[1] = operands
[2];
4057 /* These insns can result from reloads to access
4058 stack slots over 64k from the frame pointer. */
4059 if (GET_CODE (operands
[2]) == CONST_INT
4060 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4061 return "move%.l %2,%0\n\tadd%.l %1,%0";
4062 if (GET_CODE (operands
[2]) == REG
)
4063 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4064 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4066 if (GET_CODE (operands
[2]) == CONST_INT
)
4068 if (INTVAL (operands
[2]) > 0
4069 && INTVAL (operands
[2]) <= 8)
4070 return "addq%.l %2,%0";
4071 if (INTVAL (operands
[2]) < 0
4072 && INTVAL (operands
[2]) >= -8)
4074 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4075 return "subq%.l %2,%0";
4077 /* On the CPU32 it is faster to use two addql instructions to
4078 add a small integer (8 < N <= 16) to a register.
4079 Likewise for subql. */
4080 if (TUNE_CPU32
&& REG_P (operands
[0]))
4082 if (INTVAL (operands
[2]) > 8
4083 && INTVAL (operands
[2]) <= 16)
4085 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4086 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4088 if (INTVAL (operands
[2]) < -8
4089 && INTVAL (operands
[2]) >= -16)
4091 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4092 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4095 if (ADDRESS_REG_P (operands
[0])
4096 && INTVAL (operands
[2]) >= -0x8000
4097 && INTVAL (operands
[2]) < 0x8000)
4100 return "add%.w %2,%0";
4102 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4105 return "add%.l %2,%0";
4108 /* Store in cc_status the expressions that the condition codes will
4109 describe after execution of an instruction whose pattern is EXP.
4110 Do not alter them if the instruction would not alter the cc's. */
4112 /* On the 68000, all the insns to store in an address register fail to
4113 set the cc's. However, in some cases these instructions can make it
4114 possibly invalid to use the saved cc's. In those cases we clear out
4115 some or all of the saved cc's so they won't be used. */
4118 notice_update_cc (rtx exp
, rtx insn
)
4120 if (GET_CODE (exp
) == SET
)
4122 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4124 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4126 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4127 cc_status
.value1
= 0;
4128 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4129 cc_status
.value2
= 0;
4131 /* fmoves to memory or data registers do not set the condition
4132 codes. Normal moves _do_ set the condition codes, but not in
4133 a way that is appropriate for comparison with 0, because -0.0
4134 would be treated as a negative nonzero number. Note that it
4135 isn't appropriate to conditionalize this restriction on
4136 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4137 we care about the difference between -0.0 and +0.0. */
4138 else if (!FP_REG_P (SET_DEST (exp
))
4139 && SET_DEST (exp
) != cc0_rtx
4140 && (FP_REG_P (SET_SRC (exp
))
4141 || GET_CODE (SET_SRC (exp
)) == FIX
4142 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4144 /* A pair of move insns doesn't produce a useful overall cc. */
4145 else if (!FP_REG_P (SET_DEST (exp
))
4146 && !FP_REG_P (SET_SRC (exp
))
4147 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4148 && (GET_CODE (SET_SRC (exp
)) == REG
4149 || GET_CODE (SET_SRC (exp
)) == MEM
4150 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4152 else if (SET_DEST (exp
) != pc_rtx
)
4154 cc_status
.flags
= 0;
4155 cc_status
.value1
= SET_DEST (exp
);
4156 cc_status
.value2
= SET_SRC (exp
);
4159 else if (GET_CODE (exp
) == PARALLEL
4160 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4162 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4163 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4165 if (ADDRESS_REG_P (dest
))
4167 else if (dest
!= pc_rtx
)
4169 cc_status
.flags
= 0;
4170 cc_status
.value1
= dest
;
4171 cc_status
.value2
= src
;
4176 if (cc_status
.value2
!= 0
4177 && ADDRESS_REG_P (cc_status
.value2
)
4178 && GET_MODE (cc_status
.value2
) == QImode
)
4180 if (cc_status
.value2
!= 0)
4181 switch (GET_CODE (cc_status
.value2
))
4183 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4184 case ROTATE
: case ROTATERT
:
4185 /* These instructions always clear the overflow bit, and set
4186 the carry to the bit shifted out. */
4187 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4190 case PLUS
: case MINUS
: case MULT
:
4191 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4192 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4193 cc_status
.flags
|= CC_NO_OVERFLOW
;
4196 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4197 ends with a move insn moving r2 in r2's mode.
4198 Thus, the cc's are set for r2.
4199 This can set N bit spuriously. */
4200 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4205 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4207 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4208 cc_status
.value2
= 0;
4209 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4210 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4211 cc_status
.flags
= CC_IN_68881
;
4212 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4213 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4215 cc_status
.flags
= CC_IN_68881
;
4216 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4217 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4218 cc_status
.flags
|= CC_REVERSED
;
4223 output_move_const_double (rtx
*operands
)
4225 int code
= standard_68881_constant_p (operands
[1]);
4229 static char buf
[40];
4231 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4234 return "fmove%.d %1,%0";
4238 output_move_const_single (rtx
*operands
)
4240 int code
= standard_68881_constant_p (operands
[1]);
4244 static char buf
[40];
4246 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4249 return "fmove%.s %f1,%0";
4252 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4253 from the "fmovecr" instruction.
4254 The value, anded with 0xff, gives the code to use in fmovecr
4255 to get the desired constant. */
4257 /* This code has been fixed for cross-compilation. */
4259 static int inited_68881_table
= 0;
4261 static const char *const strings_68881
[7] = {
4271 static const int codes_68881
[7] = {
4281 REAL_VALUE_TYPE values_68881
[7];
4283 /* Set up values_68881 array by converting the decimal values
4284 strings_68881 to binary. */
4287 init_68881_table (void)
4291 enum machine_mode mode
;
4294 for (i
= 0; i
< 7; i
++)
4298 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4299 values_68881
[i
] = r
;
4301 inited_68881_table
= 1;
4305 standard_68881_constant_p (rtx x
)
4310 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4311 used at all on those chips. */
4315 if (! inited_68881_table
)
4316 init_68881_table ();
4318 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4320 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4322 for (i
= 0; i
< 6; i
++)
4324 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4325 return (codes_68881
[i
]);
4328 if (GET_MODE (x
) == SFmode
)
4331 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4332 return (codes_68881
[6]);
4334 /* larger powers of ten in the constants ram are not used
4335 because they are not equal to a `double' C constant. */
4339 /* If X is a floating-point constant, return the logarithm of X base 2,
4340 or 0 if X is not a power of 2. */
4343 floating_exact_log2 (rtx x
)
4345 REAL_VALUE_TYPE r
, r1
;
4348 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4350 if (REAL_VALUES_LESS (r
, dconst1
))
4353 exp
= real_exponent (&r
);
4354 real_2expN (&r1
, exp
, DFmode
);
4355 if (REAL_VALUES_EQUAL (r1
, r
))
4361 /* A C compound statement to output to stdio stream STREAM the
4362 assembler syntax for an instruction operand X. X is an RTL
4365 CODE is a value that can be used to specify one of several ways
4366 of printing the operand. It is used when identical operands
4367 must be printed differently depending on the context. CODE
4368 comes from the `%' specification that was used to request
4369 printing of the operand. If the specification was just `%DIGIT'
4370 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4371 is the ASCII code for LTR.
4373 If X is a register, this macro should print the register's name.
4374 The names can be found in an array `reg_names' whose type is
4375 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4377 When the machine description has a specification `%PUNCT' (a `%'
4378 followed by a punctuation character), this macro is called with
4379 a null pointer for X and the punctuation character for CODE.
4381 The m68k specific codes are:
4383 '.' for dot needed in Motorola-style opcode names.
4384 '-' for an operand pushing on the stack:
4385 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4386 '+' for an operand pushing on the stack:
4387 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4388 '@' for a reference to the top word on the stack:
4389 sp@, (sp) or (%sp) depending on the style of syntax.
4390 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4391 but & in SGS syntax).
4392 '!' for the cc register (used in an `and to cc' insn).
4393 '$' for the letter `s' in an op code, but only on the 68040.
4394 '&' for the letter `d' in an op code, but only on the 68040.
4395 '/' for register prefix needed by longlong.h.
4396 '?' for m68k_library_id_string
4398 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4399 'd' to force memory addressing to be absolute, not relative.
4400 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4401 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4402 or print pair of registers as rx:ry.
4403 'p' print an address with @PLTPC attached, but only if the operand
4404 is not locally-bound. */
4407 print_operand (FILE *file
, rtx op
, int letter
)
4412 fprintf (file
, ".");
4414 else if (letter
== '#')
4415 asm_fprintf (file
, "%I");
4416 else if (letter
== '-')
4417 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4418 else if (letter
== '+')
4419 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4420 else if (letter
== '@')
4421 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4422 else if (letter
== '!')
4423 asm_fprintf (file
, "%Rfpcr");
4424 else if (letter
== '$')
4427 fprintf (file
, "s");
4429 else if (letter
== '&')
4432 fprintf (file
, "d");
4434 else if (letter
== '/')
4435 asm_fprintf (file
, "%R");
4436 else if (letter
== '?')
4437 asm_fprintf (file
, m68k_library_id_string
);
4438 else if (letter
== 'p')
4440 output_addr_const (file
, op
);
4441 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4442 fprintf (file
, "@PLTPC");
4444 else if (GET_CODE (op
) == REG
)
4447 /* Print out the second register name of a register pair.
4448 I.e., R (6) => 7. */
4449 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4451 fputs (M68K_REGNAME(REGNO (op
)), file
);
4453 else if (GET_CODE (op
) == MEM
)
4455 output_address (XEXP (op
, 0));
4456 if (letter
== 'd' && ! TARGET_68020
4457 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4458 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4459 && INTVAL (XEXP (op
, 0)) < 0x8000
4460 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4461 fprintf (file
, MOTOROLA
? ".l" : ":l");
4463 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4467 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4468 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4469 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4471 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4475 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4476 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4477 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4478 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4480 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4484 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4485 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4486 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4490 /* Use `print_operand_address' instead of `output_addr_const'
4491 to ensure that we print relevant PIC stuff. */
4492 asm_fprintf (file
, "%I");
4494 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4495 print_operand_address (file
, op
);
4497 output_addr_const (file
, op
);
4501 /* Return string for TLS relocation RELOC. */
4504 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4506 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4507 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4514 if (flag_pic
== 1 && TARGET_68020
)
4555 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4558 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4560 if (GET_CODE (x
) == UNSPEC
)
4562 switch (XINT (x
, 1))
4564 case UNSPEC_RELOC16
:
4565 case UNSPEC_RELOC32
:
4566 output_addr_const (file
, XVECEXP (x
, 0, 0));
4567 fputs (m68k_get_reloc_decoration
4568 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4579 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4582 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4584 gcc_assert (size
== 4);
4585 fputs ("\t.long\t", file
);
4586 output_addr_const (file
, x
);
4587 fputs ("@TLSLDO+0x8000", file
);
4590 /* In the name of slightly smaller debug output, and to cater to
4591 general assembler lossage, recognize various UNSPEC sequences
4592 and turn them back into a direct symbol reference. */
4595 m68k_delegitimize_address (rtx orig_x
)
4598 struct m68k_address addr
;
4601 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4606 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4609 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4610 || addr
.offset
== NULL_RTX
4611 || GET_CODE (addr
.offset
) != CONST
)
4614 unspec
= XEXP (addr
.offset
, 0);
4615 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4616 unspec
= XEXP (unspec
, 0);
4617 if (GET_CODE (unspec
) != UNSPEC
4618 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4619 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4621 x
= XVECEXP (unspec
, 0, 0);
4622 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4623 if (unspec
!= XEXP (addr
.offset
, 0))
4624 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4627 rtx idx
= addr
.index
;
4628 if (addr
.scale
!= 1)
4629 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4630 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4633 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4635 x
= replace_equiv_address_nv (orig_x
, x
);
4640 /* A C compound statement to output to stdio stream STREAM the
4641 assembler syntax for an instruction operand that is a memory
4642 reference whose address is ADDR. ADDR is an RTL expression.
4644 Note that this contains a kludge that knows that the only reason
4645 we have an address (plus (label_ref...) (reg...)) when not generating
4646 PIC code is in the insn before a tablejump, and we know that m68k.md
4647 generates a label LInnn: on such an insn.
4649 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4650 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4652 This routine is responsible for distinguishing between -fpic and -fPIC
4653 style relocations in an address. When generating -fpic code the
4654 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4655 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4658 print_operand_address (FILE *file
, rtx addr
)
4660 struct m68k_address address
;
4662 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4665 if (address
.code
== PRE_DEC
)
4666 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4667 M68K_REGNAME (REGNO (address
.base
)));
4668 else if (address
.code
== POST_INC
)
4669 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4670 M68K_REGNAME (REGNO (address
.base
)));
4671 else if (!address
.base
&& !address
.index
)
4673 /* A constant address. */
4674 gcc_assert (address
.offset
== addr
);
4675 if (GET_CODE (addr
) == CONST_INT
)
4677 /* (xxx).w or (xxx).l. */
4678 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4679 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4681 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4683 else if (TARGET_PCREL
)
4685 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4687 output_addr_const (file
, addr
);
4688 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4692 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4693 name ends in `.<letter>', as the last 2 characters can be
4694 mistaken as a size suffix. Put the name in parentheses. */
4695 if (GET_CODE (addr
) == SYMBOL_REF
4696 && strlen (XSTR (addr
, 0)) > 2
4697 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4700 output_addr_const (file
, addr
);
4704 output_addr_const (file
, addr
);
4711 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4712 label being accessed, otherwise it is -1. */
4713 labelno
= (address
.offset
4715 && GET_CODE (address
.offset
) == LABEL_REF
4716 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4720 /* Print the "offset(base" component. */
4722 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4726 output_addr_const (file
, address
.offset
);
4730 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4732 /* Print the ",index" component, if any. */
4737 fprintf (file
, "%s.%c",
4738 M68K_REGNAME (REGNO (address
.index
)),
4739 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4740 if (address
.scale
!= 1)
4741 fprintf (file
, "*%d", address
.scale
);
4745 else /* !MOTOROLA */
4747 if (!address
.offset
&& !address
.index
)
4748 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4751 /* Print the "base@(offset" component. */
4753 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4757 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4758 fprintf (file
, "@(");
4760 output_addr_const (file
, address
.offset
);
4762 /* Print the ",index" component, if any. */
4765 fprintf (file
, ",%s:%c",
4766 M68K_REGNAME (REGNO (address
.index
)),
4767 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4768 if (address
.scale
!= 1)
4769 fprintf (file
, ":%d", address
.scale
);
4777 /* Check for cases where a clr insns can be omitted from code using
4778 strict_low_part sets. For example, the second clrl here is not needed:
4779 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4781 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4782 insn we are checking for redundancy. TARGET is the register set by the
4786 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4791 while ((p
= PREV_INSN (p
)))
4793 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4799 /* If it isn't an insn, then give up. */
4803 if (reg_set_p (target
, p
))
4805 rtx set
= single_set (p
);
4808 /* If it isn't an easy to recognize insn, then give up. */
4812 dest
= SET_DEST (set
);
4814 /* If this sets the entire target register to zero, then our
4815 first_insn is redundant. */
4816 if (rtx_equal_p (dest
, target
)
4817 && SET_SRC (set
) == const0_rtx
)
4819 else if (GET_CODE (dest
) == STRICT_LOW_PART
4820 && GET_CODE (XEXP (dest
, 0)) == REG
4821 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4822 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4823 <= GET_MODE_SIZE (mode
)))
4824 /* This is a strict low part set which modifies less than
4825 we are using, so it is safe. */
4835 /* Operand predicates for implementing asymmetric pc-relative addressing
4836 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4837 when used as a source operand, but not as a destination operand.
4839 We model this by restricting the meaning of the basic predicates
4840 (general_operand, memory_operand, etc) to forbid the use of this
4841 addressing mode, and then define the following predicates that permit
4842 this addressing mode. These predicates can then be used for the
4843 source operands of the appropriate instructions.
4845 n.b. While it is theoretically possible to change all machine patterns
4846 to use this addressing more where permitted by the architecture,
4847 it has only been implemented for "common" cases: SImode, HImode, and
4848 QImode operands, and only for the principle operations that would
4849 require this addressing mode: data movement and simple integer operations.
4851 In parallel with these new predicates, two new constraint letters
4852 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4853 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4854 In the pcrel case 's' is only valid in combination with 'a' registers.
4855 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4856 of how these constraints are used.
4858 The use of these predicates is strictly optional, though patterns that
4859 don't will cause an extra reload register to be allocated where one
4862 lea (abc:w,%pc),%a0 ; need to reload address
4863 moveq &1,%d1 ; since write to pc-relative space
4864 movel %d1,%a0@ ; is not allowed
4866 lea (abc:w,%pc),%a1 ; no need to reload address here
4867 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4869 For more info, consult tiemann@cygnus.com.
4872 All of the ugliness with predicates and constraints is due to the
4873 simple fact that the m68k does not allow a pc-relative addressing
4874 mode as a destination. gcc does not distinguish between source and
4875 destination addresses. Hence, if we claim that pc-relative address
4876 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4877 end up with invalid code. To get around this problem, we left
4878 pc-relative modes as invalid addresses, and then added special
4879 predicates and constraints to accept them.
4881 A cleaner way to handle this is to modify gcc to distinguish
4882 between source and destination addresses. We can then say that
4883 pc-relative is a valid source address but not a valid destination
4884 address, and hopefully avoid a lot of the predicate and constraint
4885 hackery. Unfortunately, this would be a pretty big change. It would
4886 be a useful change for a number of ports, but there aren't any current
4887 plans to undertake this.
4889 ***************************************************************************/
4893 output_andsi3 (rtx
*operands
)
4896 if (GET_CODE (operands
[2]) == CONST_INT
4897 && (INTVAL (operands
[2]) | 0xffff) == -1
4898 && (DATA_REG_P (operands
[0])
4899 || offsettable_memref_p (operands
[0]))
4900 && !TARGET_COLDFIRE
)
4902 if (GET_CODE (operands
[0]) != REG
)
4903 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4904 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4905 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4907 if (operands
[2] == const0_rtx
)
4909 return "and%.w %2,%0";
4911 if (GET_CODE (operands
[2]) == CONST_INT
4912 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4913 && (DATA_REG_P (operands
[0])
4914 || offsettable_memref_p (operands
[0])))
4916 if (DATA_REG_P (operands
[0]))
4917 operands
[1] = GEN_INT (logval
);
4920 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4921 operands
[1] = GEN_INT (logval
% 8);
4923 /* This does not set condition codes in a standard way. */
4925 return "bclr %1,%0";
4927 return "and%.l %2,%0";
4931 output_iorsi3 (rtx
*operands
)
4933 register int logval
;
4934 if (GET_CODE (operands
[2]) == CONST_INT
4935 && INTVAL (operands
[2]) >> 16 == 0
4936 && (DATA_REG_P (operands
[0])
4937 || offsettable_memref_p (operands
[0]))
4938 && !TARGET_COLDFIRE
)
4940 if (GET_CODE (operands
[0]) != REG
)
4941 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4942 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4944 if (INTVAL (operands
[2]) == 0xffff)
4945 return "mov%.w %2,%0";
4946 return "or%.w %2,%0";
4948 if (GET_CODE (operands
[2]) == CONST_INT
4949 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4950 && (DATA_REG_P (operands
[0])
4951 || offsettable_memref_p (operands
[0])))
4953 if (DATA_REG_P (operands
[0]))
4954 operands
[1] = GEN_INT (logval
);
4957 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4958 operands
[1] = GEN_INT (logval
% 8);
4961 return "bset %1,%0";
4963 return "or%.l %2,%0";
4967 output_xorsi3 (rtx
*operands
)
4969 register int logval
;
4970 if (GET_CODE (operands
[2]) == CONST_INT
4971 && INTVAL (operands
[2]) >> 16 == 0
4972 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4973 && !TARGET_COLDFIRE
)
4975 if (! DATA_REG_P (operands
[0]))
4976 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4977 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4979 if (INTVAL (operands
[2]) == 0xffff)
4981 return "eor%.w %2,%0";
4983 if (GET_CODE (operands
[2]) == CONST_INT
4984 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4985 && (DATA_REG_P (operands
[0])
4986 || offsettable_memref_p (operands
[0])))
4988 if (DATA_REG_P (operands
[0]))
4989 operands
[1] = GEN_INT (logval
);
4992 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4993 operands
[1] = GEN_INT (logval
% 8);
4996 return "bchg %1,%0";
4998 return "eor%.l %2,%0";
5001 /* Return the instruction that should be used for a call to address X,
5002 which is known to be in operand 0. */
5007 if (symbolic_operand (x
, VOIDmode
))
5008 return m68k_symbolic_call
;
5013 /* Likewise sibling calls. */
5016 output_sibcall (rtx x
)
5018 if (symbolic_operand (x
, VOIDmode
))
5019 return m68k_symbolic_jump
;
5025 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5026 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5029 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5031 /* Avoid clobbering the struct value reg by using the
5032 static chain reg as a temporary. */
5033 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5035 /* Pretend to be a post-reload pass while generating rtl. */
5036 reload_completed
= 1;
5038 /* The "this" pointer is stored at 4(%sp). */
5039 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5040 stack_pointer_rtx
, 4));
5042 /* Add DELTA to THIS. */
5045 /* Make the offset a legitimate operand for memory addition. */
5046 offset
= GEN_INT (delta
);
5047 if ((delta
< -8 || delta
> 8)
5048 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5050 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5051 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5053 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5054 copy_rtx (this_slot
), offset
));
5057 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5058 if (vcall_offset
!= 0)
5060 /* Set the static chain register to *THIS. */
5061 emit_move_insn (tmp
, this_slot
);
5062 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5064 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5065 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5066 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5068 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5072 /* Load the offset into %d0 and add it to THIS. */
5073 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5074 gen_rtx_MEM (Pmode
, addr
));
5075 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5076 copy_rtx (this_slot
),
5077 gen_rtx_REG (Pmode
, D0_REG
)));
5080 /* Jump to the target function. Use a sibcall if direct jumps are
5081 allowed, otherwise load the address into a register first. */
5082 mem
= DECL_RTL (function
);
5083 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5085 gcc_assert (flag_pic
);
5087 if (!TARGET_SEP_DATA
)
5089 /* Use the static chain register as a temporary (call-clobbered)
5090 GOT pointer for this function. We can use the static chain
5091 register because it isn't live on entry to the thunk. */
5092 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5093 emit_insn (gen_load_got (pic_offset_table_rtx
));
5095 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5096 mem
= replace_equiv_address (mem
, tmp
);
5098 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5099 SIBLING_CALL_P (insn
) = 1;
5101 /* Run just enough of rest_of_compilation. */
5102 insn
= get_insns ();
5103 split_all_insns_noflow ();
5104 final_start_function (insn
, file
, 1);
5105 final (insn
, file
, 1);
5106 final_end_function ();
5108 /* Clean up the vars set above. */
5109 reload_completed
= 0;
5111 /* Restore the original PIC register. */
5113 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5116 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5119 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5120 int incoming ATTRIBUTE_UNUSED
)
5122 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5125 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5127 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5128 unsigned int new_reg
)
5131 /* Interrupt functions can only use registers that have already been
5132 saved by the prologue, even if they would normally be
5135 if ((m68k_get_function_kind (current_function_decl
)
5136 == m68k_fk_interrupt_handler
)
5137 && !df_regs_ever_live_p (new_reg
))
5143 /* Value is true if hard register REGNO can hold a value of machine-mode
5144 MODE. On the 68000, we let the cpu registers can hold any mode, but
5145 restrict the 68881 registers to floating-point modes. */
5148 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5150 if (DATA_REGNO_P (regno
))
5152 /* Data Registers, can hold aggregate if fits in. */
5153 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5156 else if (ADDRESS_REGNO_P (regno
))
5158 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5161 else if (FP_REGNO_P (regno
))
5163 /* FPU registers, hold float or complex float of long double or
5165 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5166 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5167 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5173 /* Implement SECONDARY_RELOAD_CLASS. */
5176 m68k_secondary_reload_class (enum reg_class rclass
,
5177 enum machine_mode mode
, rtx x
)
5181 regno
= true_regnum (x
);
5183 /* If one operand of a movqi is an address register, the other
5184 operand must be a general register or constant. Other types
5185 of operand must be reloaded through a data register. */
5186 if (GET_MODE_SIZE (mode
) == 1
5187 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5188 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5191 /* PC-relative addresses must be loaded into an address register first. */
5193 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5194 && symbolic_operand (x
, VOIDmode
))
5200 /* Implement PREFERRED_RELOAD_CLASS. */
5203 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5205 enum reg_class secondary_class
;
5207 /* If RCLASS might need a secondary reload, try restricting it to
5208 a class that doesn't. */
5209 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5210 if (secondary_class
!= NO_REGS
5211 && reg_class_subset_p (secondary_class
, rclass
))
5212 return secondary_class
;
5214 /* Prefer to use moveq for in-range constants. */
5215 if (GET_CODE (x
) == CONST_INT
5216 && reg_class_subset_p (DATA_REGS
, rclass
)
5217 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5220 /* ??? Do we really need this now? */
5221 if (GET_CODE (x
) == CONST_DOUBLE
5222 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5224 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5233 /* Return floating point values in a 68881 register. This makes 68881 code
5234 a little bit faster. It also makes -msoft-float code incompatible with
5235 hard-float code, so people have to be careful not to mix the two.
5236 For ColdFire it was decided the ABI incompatibility is undesirable.
5237 If there is need for a hard-float ABI it is probably worth doing it
5238 properly and also passing function arguments in FP registers. */
5240 m68k_libcall_value (enum machine_mode mode
)
5247 return gen_rtx_REG (mode
, FP0_REG
);
5253 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5256 /* Location in which function value is returned.
5257 NOTE: Due to differences in ABIs, don't call this function directly,
5258 use FUNCTION_VALUE instead. */
5260 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5262 enum machine_mode mode
;
5264 mode
= TYPE_MODE (valtype
);
5270 return gen_rtx_REG (mode
, FP0_REG
);
5276 /* If the function returns a pointer, push that into %a0. */
5277 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5278 /* For compatibility with the large body of existing code which
5279 does not always properly declare external functions returning
5280 pointer types, the m68k/SVR4 convention is to copy the value
5281 returned for pointer functions from a0 to d0 in the function
5282 epilogue, so that callers that have neglected to properly
5283 declare the callee can still find the correct return value in
5285 return gen_rtx_PARALLEL
5288 gen_rtx_EXPR_LIST (VOIDmode
,
5289 gen_rtx_REG (mode
, A0_REG
),
5291 gen_rtx_EXPR_LIST (VOIDmode
,
5292 gen_rtx_REG (mode
, D0_REG
),
5294 else if (POINTER_TYPE_P (valtype
))
5295 return gen_rtx_REG (mode
, A0_REG
);
5297 return gen_rtx_REG (mode
, D0_REG
);
5300 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5301 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5303 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5305 enum machine_mode mode
= TYPE_MODE (type
);
5307 if (mode
== BLKmode
)
5310 /* If TYPE's known alignment is less than the alignment of MODE that
5311 would contain the structure, then return in memory. We need to
5312 do so to maintain the compatibility between code compiled with
5313 -mstrict-align and that compiled with -mno-strict-align. */
5314 if (AGGREGATE_TYPE_P (type
)
5315 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5322 /* CPU to schedule the program for. */
5323 enum attr_cpu m68k_sched_cpu
;
5325 /* MAC to schedule the program for. */
5326 enum attr_mac m68k_sched_mac
;
5334 /* Integer register. */
5340 /* Implicit mem reference (e.g. stack). */
5343 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5346 /* Memory with offset but without indexing. EA mode 5. */
5349 /* Memory with indexing. EA mode 6. */
5352 /* Memory referenced by absolute address. EA mode 7. */
5355 /* Immediate operand that doesn't require extension word. */
5358 /* Immediate 16 bit operand. */
5361 /* Immediate 32 bit operand. */
5365 /* Return type of memory ADDR_RTX refers to. */
5366 static enum attr_op_type
5367 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5369 struct m68k_address address
;
5371 if (symbolic_operand (addr_rtx
, VOIDmode
))
5372 return OP_TYPE_MEM7
;
5374 if (!m68k_decompose_address (mode
, addr_rtx
,
5375 reload_completed
, &address
))
5377 gcc_assert (!reload_completed
);
5378 /* Reload will likely fix the address to be in the register. */
5379 return OP_TYPE_MEM234
;
5382 if (address
.scale
!= 0)
5383 return OP_TYPE_MEM6
;
5385 if (address
.base
!= NULL_RTX
)
5387 if (address
.offset
== NULL_RTX
)
5388 return OP_TYPE_MEM234
;
5390 return OP_TYPE_MEM5
;
5393 gcc_assert (address
.offset
!= NULL_RTX
);
5395 return OP_TYPE_MEM7
;
5398 /* Return X or Y (depending on OPX_P) operand of INSN. */
5400 sched_get_operand (rtx insn
, bool opx_p
)
5404 if (recog_memoized (insn
) < 0)
5407 extract_constrain_insn_cached (insn
);
5410 i
= get_attr_opx (insn
);
5412 i
= get_attr_opy (insn
);
5414 if (i
>= recog_data
.n_operands
)
5417 return recog_data
.operand
[i
];
5420 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5421 If ADDRESS_P is true, return type of memory location operand refers to. */
5422 static enum attr_op_type
5423 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5427 op
= sched_get_operand (insn
, opx_p
);
5431 gcc_assert (!reload_completed
);
5436 return sched_address_type (QImode
, op
);
5438 if (memory_operand (op
, VOIDmode
))
5439 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5441 if (register_operand (op
, VOIDmode
))
5443 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5444 || (reload_completed
&& FP_REG_P (op
)))
5450 if (GET_CODE (op
) == CONST_INT
)
5456 /* Check for quick constants. */
5457 switch (get_attr_type (insn
))
5460 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5461 return OP_TYPE_IMM_Q
;
5463 gcc_assert (!reload_completed
);
5467 if (USE_MOVQ (ival
))
5468 return OP_TYPE_IMM_Q
;
5470 gcc_assert (!reload_completed
);
5474 if (valid_mov3q_const (ival
))
5475 return OP_TYPE_IMM_Q
;
5477 gcc_assert (!reload_completed
);
5484 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5485 return OP_TYPE_IMM_W
;
5487 return OP_TYPE_IMM_L
;
5490 if (GET_CODE (op
) == CONST_DOUBLE
)
5492 switch (GET_MODE (op
))
5495 return OP_TYPE_IMM_W
;
5499 return OP_TYPE_IMM_L
;
5506 if (GET_CODE (op
) == CONST
5507 || symbolic_operand (op
, VOIDmode
)
5510 switch (GET_MODE (op
))
5513 return OP_TYPE_IMM_Q
;
5516 return OP_TYPE_IMM_W
;
5519 return OP_TYPE_IMM_L
;
5522 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5524 return OP_TYPE_IMM_W
;
5526 return OP_TYPE_IMM_L
;
5530 gcc_assert (!reload_completed
);
5532 if (FLOAT_MODE_P (GET_MODE (op
)))
5538 /* Implement opx_type attribute.
5539 Return type of INSN's operand X.
5540 If ADDRESS_P is true, return type of memory location operand refers to. */
5542 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5544 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5550 return OPX_TYPE_FPN
;
5553 return OPX_TYPE_MEM1
;
5555 case OP_TYPE_MEM234
:
5556 return OPX_TYPE_MEM234
;
5559 return OPX_TYPE_MEM5
;
5562 return OPX_TYPE_MEM6
;
5565 return OPX_TYPE_MEM7
;
5568 return OPX_TYPE_IMM_Q
;
5571 return OPX_TYPE_IMM_W
;
5574 return OPX_TYPE_IMM_L
;
5581 /* Implement opy_type attribute.
5582 Return type of INSN's operand Y.
5583 If ADDRESS_P is true, return type of memory location operand refers to. */
5585 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5587 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5593 return OPY_TYPE_FPN
;
5596 return OPY_TYPE_MEM1
;
5598 case OP_TYPE_MEM234
:
5599 return OPY_TYPE_MEM234
;
5602 return OPY_TYPE_MEM5
;
5605 return OPY_TYPE_MEM6
;
5608 return OPY_TYPE_MEM7
;
5611 return OPY_TYPE_IMM_Q
;
5614 return OPY_TYPE_IMM_W
;
5617 return OPY_TYPE_IMM_L
;
5624 /* Return size of INSN as int. */
5626 sched_get_attr_size_int (rtx insn
)
5630 switch (get_attr_type (insn
))
5633 /* There should be no references to m68k_sched_attr_size for 'ignore'
5647 switch (get_attr_opx_type (insn
))
5653 case OPX_TYPE_MEM234
:
5654 case OPY_TYPE_IMM_Q
:
5659 /* Here we assume that most absolute references are short. */
5661 case OPY_TYPE_IMM_W
:
5665 case OPY_TYPE_IMM_L
:
5673 switch (get_attr_opy_type (insn
))
5679 case OPY_TYPE_MEM234
:
5680 case OPY_TYPE_IMM_Q
:
5685 /* Here we assume that most absolute references are short. */
5687 case OPY_TYPE_IMM_W
:
5691 case OPY_TYPE_IMM_L
:
5701 gcc_assert (!reload_completed
);
5709 /* Return size of INSN as attribute enum value. */
5711 m68k_sched_attr_size (rtx insn
)
5713 switch (sched_get_attr_size_int (insn
))
5729 /* Return operand X or Y (depending on OPX_P) of INSN,
5730 if it is a MEM, or NULL overwise. */
5731 static enum attr_op_type
5732 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5736 switch (get_attr_opx_type (insn
))
5741 case OPX_TYPE_IMM_Q
:
5742 case OPX_TYPE_IMM_W
:
5743 case OPX_TYPE_IMM_L
:
5747 case OPX_TYPE_MEM234
:
5750 return OP_TYPE_MEM1
;
5753 return OP_TYPE_MEM6
;
5761 switch (get_attr_opy_type (insn
))
5766 case OPY_TYPE_IMM_Q
:
5767 case OPY_TYPE_IMM_W
:
5768 case OPY_TYPE_IMM_L
:
5772 case OPY_TYPE_MEM234
:
5775 return OP_TYPE_MEM1
;
5778 return OP_TYPE_MEM6
;
5786 /* Implement op_mem attribute. */
5788 m68k_sched_attr_op_mem (rtx insn
)
5790 enum attr_op_type opx
;
5791 enum attr_op_type opy
;
5793 opx
= sched_get_opxy_mem_type (insn
, true);
5794 opy
= sched_get_opxy_mem_type (insn
, false);
5796 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5799 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5801 switch (get_attr_opx_access (insn
))
5817 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5819 switch (get_attr_opx_access (insn
))
5835 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5838 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5840 switch (get_attr_opx_access (insn
))
5846 gcc_assert (!reload_completed
);
5851 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5853 switch (get_attr_opx_access (insn
))
5859 gcc_assert (!reload_completed
);
5864 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5867 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5869 switch (get_attr_opx_access (insn
))
5875 gcc_assert (!reload_completed
);
5880 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5881 gcc_assert (!reload_completed
);
5885 /* Data for ColdFire V4 index bypass.
5886 Producer modifies register that is used as index in consumer with
5890 /* Producer instruction. */
5893 /* Consumer instruction. */
5896 /* Scale of indexed memory access within consumer.
5897 Or zero if bypass should not be effective at the moment. */
5899 } sched_cfv4_bypass_data
;
5901 /* An empty state that is used in m68k_sched_adjust_cost. */
5902 static state_t sched_adjust_cost_state
;
5904 /* Implement adjust_cost scheduler hook.
5905 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5907 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5912 if (recog_memoized (def_insn
) < 0
5913 || recog_memoized (insn
) < 0)
5916 if (sched_cfv4_bypass_data
.scale
== 1)
5917 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5919 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5920 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5921 that the data in sched_cfv4_bypass_data is up to date. */
5922 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5923 && sched_cfv4_bypass_data
.con
== insn
);
5928 sched_cfv4_bypass_data
.pro
= NULL
;
5929 sched_cfv4_bypass_data
.con
= NULL
;
5930 sched_cfv4_bypass_data
.scale
= 0;
5933 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5934 && sched_cfv4_bypass_data
.con
== NULL
5935 && sched_cfv4_bypass_data
.scale
== 0);
5937 /* Don't try to issue INSN earlier than DFA permits.
5938 This is especially useful for instructions that write to memory,
5939 as their true dependence (default) latency is better to be set to 0
5940 to workaround alias analysis limitations.
5941 This is, in fact, a machine independent tweak, so, probably,
5942 it should be moved to haifa-sched.c: insn_cost (). */
5943 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5950 /* Return maximal number of insns that can be scheduled on a single cycle. */
5952 m68k_sched_issue_rate (void)
5954 switch (m68k_sched_cpu
)
5970 /* Maximal length of instruction for current CPU.
5971 E.g. it is 3 for any ColdFire core. */
5972 static int max_insn_size
;
5974 /* Data to model instruction buffer of CPU. */
5977 /* True if instruction buffer model is modeled for current CPU. */
5980 /* Size of the instruction buffer in words. */
5983 /* Number of filled words in the instruction buffer. */
5986 /* Additional information about instruction buffer for CPUs that have
5987 a buffer of instruction records, rather then a plain buffer
5988 of instruction words. */
5989 struct _sched_ib_records
5991 /* Size of buffer in records. */
5994 /* Array to hold data on adjustements made to the size of the buffer. */
5997 /* Index of the above array. */
6001 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6005 static struct _sched_ib sched_ib
;
6007 /* ID of memory unit. */
6008 static int sched_mem_unit_code
;
6010 /* Implementation of the targetm.sched.variable_issue () hook.
6011 It is called after INSN was issued. It returns the number of insns
6012 that can possibly get scheduled on the current cycle.
6013 It is used here to determine the effect of INSN on the instruction
6016 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6017 int sched_verbose ATTRIBUTE_UNUSED
,
6018 rtx insn
, int can_issue_more
)
6022 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6024 switch (m68k_sched_cpu
)
6028 insn_size
= sched_get_attr_size_int (insn
);
6032 insn_size
= sched_get_attr_size_int (insn
);
6034 /* ColdFire V3 and V4 cores have instruction buffers that can
6035 accumulate up to 8 instructions regardless of instructions'
6036 sizes. So we should take care not to "prefetch" 24 one-word
6037 or 12 two-words instructions.
6038 To model this behavior we temporarily decrease size of the
6039 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6043 adjust
= max_insn_size
- insn_size
;
6044 sched_ib
.size
-= adjust
;
6046 if (sched_ib
.filled
> sched_ib
.size
)
6047 sched_ib
.filled
= sched_ib
.size
;
6049 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6052 ++sched_ib
.records
.adjust_index
;
6053 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6054 sched_ib
.records
.adjust_index
= 0;
6056 /* Undo adjustement we did 7 instructions ago. */
6058 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6063 gcc_assert (!sched_ib
.enabled_p
);
6071 if (insn_size
> sched_ib
.filled
)
6072 /* Scheduling for register pressure does not always take DFA into
6073 account. Workaround instruction buffer not being filled enough. */
6075 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6076 insn_size
= sched_ib
.filled
;
6081 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6082 || asm_noperands (PATTERN (insn
)) >= 0)
6083 insn_size
= sched_ib
.filled
;
6087 sched_ib
.filled
-= insn_size
;
6089 return can_issue_more
;
6092 /* Return how many instructions should scheduler lookahead to choose the
6095 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6097 return m68k_sched_issue_rate () - 1;
6100 /* Implementation of targetm.sched.init_global () hook.
6101 It is invoked once per scheduling pass and is used here
6102 to initialize scheduler constants. */
6104 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6105 int sched_verbose ATTRIBUTE_UNUSED
,
6106 int n_insns ATTRIBUTE_UNUSED
)
6108 #ifdef ENABLE_CHECKING
6109 /* Check that all instructions have DFA reservations and
6110 that all instructions can be issued from a clean state. */
6115 state
= alloca (state_size ());
6117 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6119 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6121 gcc_assert (insn_has_dfa_reservation_p (insn
));
6123 state_reset (state
);
6124 if (state_transition (state
, insn
) >= 0)
6131 /* Setup target cpu. */
6133 /* ColdFire V4 has a set of features to keep its instruction buffer full
6134 (e.g., a separate memory bus for instructions) and, hence, we do not model
6135 buffer for this CPU. */
6136 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6138 switch (m68k_sched_cpu
)
6141 sched_ib
.filled
= 0;
6148 sched_ib
.records
.n_insns
= 0;
6149 sched_ib
.records
.adjust
= NULL
;
6154 sched_ib
.records
.n_insns
= 8;
6155 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6162 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6164 sched_adjust_cost_state
= xmalloc (state_size ());
6165 state_reset (sched_adjust_cost_state
);
6168 emit_insn (gen_ib ());
6169 sched_ib
.insn
= get_insns ();
6173 /* Scheduling pass is now finished. Free/reset static variables. */
6175 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6176 int verbose ATTRIBUTE_UNUSED
)
6178 sched_ib
.insn
= NULL
;
6180 free (sched_adjust_cost_state
);
6181 sched_adjust_cost_state
= NULL
;
6183 sched_mem_unit_code
= 0;
6185 free (sched_ib
.records
.adjust
);
6186 sched_ib
.records
.adjust
= NULL
;
6187 sched_ib
.records
.n_insns
= 0;
6191 /* Implementation of targetm.sched.init () hook.
6192 It is invoked each time scheduler starts on the new block (basic block or
6193 extended basic block). */
6195 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6196 int sched_verbose ATTRIBUTE_UNUSED
,
6197 int n_insns ATTRIBUTE_UNUSED
)
6199 switch (m68k_sched_cpu
)
6207 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6209 memset (sched_ib
.records
.adjust
, 0,
6210 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6211 sched_ib
.records
.adjust_index
= 0;
6215 gcc_assert (!sched_ib
.enabled_p
);
6223 if (sched_ib
.enabled_p
)
6224 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6225 the first cycle. Workaround that. */
6226 sched_ib
.filled
= -2;
6229 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6230 It is invoked just before current cycle finishes and is used here
6231 to track if instruction buffer got its two words this cycle. */
6233 m68k_sched_dfa_pre_advance_cycle (void)
6235 if (!sched_ib
.enabled_p
)
6238 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6240 sched_ib
.filled
+= 2;
6242 if (sched_ib
.filled
> sched_ib
.size
)
6243 sched_ib
.filled
= sched_ib
.size
;
6247 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6248 It is invoked just after new cycle begins and is used here
6249 to setup number of filled words in the instruction buffer so that
6250 instructions which won't have all their words prefetched would be
6251 stalled for a cycle. */
6253 m68k_sched_dfa_post_advance_cycle (void)
6257 if (!sched_ib
.enabled_p
)
6260 /* Setup number of prefetched instruction words in the instruction
6262 i
= max_insn_size
- sched_ib
.filled
;
6266 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6271 /* Return X or Y (depending on OPX_P) operand of INSN,
6272 if it is an integer register, or NULL overwise. */
6274 sched_get_reg_operand (rtx insn
, bool opx_p
)
6280 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6282 op
= sched_get_operand (insn
, true);
6283 gcc_assert (op
!= NULL
);
6285 if (!reload_completed
&& !REG_P (op
))
6291 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6293 op
= sched_get_operand (insn
, false);
6294 gcc_assert (op
!= NULL
);
6296 if (!reload_completed
&& !REG_P (op
))
6304 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6307 sched_mem_operand_p (rtx insn
, bool opx_p
)
6309 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6320 /* Return X or Y (depending on OPX_P) operand of INSN,
6321 if it is a MEM, or NULL overwise. */
6323 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6343 if (opy_p
&& sched_mem_operand_p (insn
, false))
6344 return sched_get_operand (insn
, false);
6346 if (opx_p
&& sched_mem_operand_p (insn
, true))
6347 return sched_get_operand (insn
, true);
6353 /* Return non-zero if PRO modifies register used as part of
6356 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6361 pro_x
= sched_get_reg_operand (pro
, true);
6365 con_mem_read
= sched_get_mem_operand (con
, true, false);
6366 gcc_assert (con_mem_read
!= NULL
);
6368 if (reg_mentioned_p (pro_x
, con_mem_read
))
6374 /* Helper function for m68k_sched_indexed_address_bypass_p.
6375 if PRO modifies register used as index in CON,
6376 return scale of indexed memory access in CON. Return zero overwise. */
6378 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6382 struct m68k_address address
;
6384 reg
= sched_get_reg_operand (pro
, true);
6388 mem
= sched_get_mem_operand (con
, true, false);
6389 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6391 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6395 if (REGNO (reg
) == REGNO (address
.index
))
6397 gcc_assert (address
.scale
!= 0);
6398 return address
.scale
;
6404 /* Return non-zero if PRO modifies register used
6405 as index with scale 2 or 4 in CON. */
6407 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6409 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6410 && sched_cfv4_bypass_data
.con
== NULL
6411 && sched_cfv4_bypass_data
.scale
== 0);
6413 switch (sched_get_indexed_address_scale (pro
, con
))
6416 /* We can't have a variable latency bypass, so
6417 remember to adjust the insn cost in adjust_cost hook. */
6418 sched_cfv4_bypass_data
.pro
= pro
;
6419 sched_cfv4_bypass_data
.con
= con
;
6420 sched_cfv4_bypass_data
.scale
= 1;
6432 /* We generate a two-instructions program at M_TRAMP :
6433 movea.l &CHAIN_VALUE,%a0
6435 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6438 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6440 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6443 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6445 mem
= adjust_address (m_tramp
, HImode
, 0);
6446 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6447 mem
= adjust_address (m_tramp
, SImode
, 2);
6448 emit_move_insn (mem
, chain_value
);
6450 mem
= adjust_address (m_tramp
, HImode
, 6);
6451 emit_move_insn (mem
, GEN_INT(0x4EF9));
6452 mem
= adjust_address (m_tramp
, SImode
, 8);
6453 emit_move_insn (mem
, fnaddr
);
6455 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6458 /* On the 68000, the RTS insn cannot pop anything.
6459 On the 68010, the RTD insn may be used to pop them if the number
6460 of args is fixed, but if the number is variable then the caller
6461 must pop them all. RTD can't be used for library calls now
6462 because the library is compiled with the Unix compiler.
6463 Use of RTD is a selectable option, since it is incompatible with
6464 standard Unix calling sequences. If the option is not selected,
6465 the caller must always pop the args. */
6468 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6472 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6473 && (!stdarg_p (funtype
)))
6477 /* Make sure everything's fine if we *don't* have a given processor.
6478 This assumes that putting a register in fixed_regs will keep the
6479 compiler's mitts completely off it. We don't bother to zero it out
6480 of register classes. */
6483 m68k_conditional_register_usage (void)
6487 if (!TARGET_HARD_FLOAT
)
6489 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6490 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6491 if (TEST_HARD_REG_BIT (x
, i
))
6492 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6495 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6499 m68k_init_sync_libfuncs (void)
6501 init_sync_libfuncs (UNITS_PER_WORD
);
6504 #include "gt-m68k.h"