1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #define IN_TARGET_CODE 1
24 #include "coretypes.h"
28 #include "stringpool.h"
33 #include "fold-const.h"
35 #include "stor-layout.h"
38 #include "insn-config.h"
39 #include "conditions.h"
41 #include "insn-attr.h"
43 #include "diagnostic-core.h"
60 #include "cfgcleanup.h"
61 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
62 #include "sched-int.h"
63 #include "insn-codes.h"
70 /* This file should be included last. */
71 #include "target-def.h"
73 enum reg_class regno_reg_class
[] =
75 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
76 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
77 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
78 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
79 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
80 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
85 /* The minimum number of integer registers that we want to save with the
86 movem instruction. Using two movel instructions instead of a single
87 moveml is about 15% faster for the 68020 and 68030 at no expense in
89 #define MIN_MOVEM_REGS 3
91 /* The minimum number of floating point registers that we want to save
92 with the fmovem instruction. */
93 #define MIN_FMOVEM_REGS 1
95 /* Structure describing stack frame layout. */
98 /* Stack pointer to frame pointer offset. */
101 /* Offset of FPU registers. */
102 HOST_WIDE_INT foffset
;
104 /* Frame size in bytes (rounded up). */
107 /* Data and address register. */
109 unsigned int reg_mask
;
113 unsigned int fpu_mask
;
115 /* Offsets relative to ARG_POINTER. */
116 HOST_WIDE_INT frame_pointer_offset
;
117 HOST_WIDE_INT stack_pointer_offset
;
119 /* Function which the above information refers to. */
123 /* Current frame information calculated by m68k_compute_frame_layout(). */
124 static struct m68k_frame current_frame
;
126 /* Structure describing an m68k address.
128 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
129 with null fields evaluating to 0. Here:
131 - BASE satisfies m68k_legitimate_base_reg_p
132 - INDEX satisfies m68k_legitimate_index_reg_p
133 - OFFSET satisfies m68k_legitimate_constant_address_p
135 INDEX is either HImode or SImode. The other fields are SImode.
137 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
138 the address is (BASE)+. */
139 struct m68k_address
{
147 static int m68k_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
149 static int m68k_sched_issue_rate (void);
150 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
151 static void m68k_sched_md_init_global (FILE *, int, int);
152 static void m68k_sched_md_finish_global (FILE *, int);
153 static void m68k_sched_md_init (FILE *, int, int);
154 static void m68k_sched_dfa_pre_advance_cycle (void);
155 static void m68k_sched_dfa_post_advance_cycle (void);
156 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
158 static bool m68k_can_eliminate (const int, const int);
159 static void m68k_conditional_register_usage (void);
160 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
161 static void m68k_option_override (void);
162 static void m68k_override_options_after_change (void);
163 static rtx
find_addr_reg (rtx
);
164 static const char *singlemove_string (rtx
*);
165 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
166 HOST_WIDE_INT
, tree
);
167 static rtx
m68k_struct_value_rtx (tree
, int);
168 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
169 tree args
, int flags
,
171 static void m68k_compute_frame_layout (void);
172 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
173 static bool m68k_ok_for_sibcall_p (tree
, tree
);
174 static bool m68k_tls_symbol_p (rtx
);
175 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
176 static bool m68k_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
177 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
178 static bool m68k_return_in_memory (const_tree
, const_tree
);
180 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
181 static void m68k_trampoline_init (rtx
, tree
, rtx
);
182 static poly_int64
m68k_return_pops_args (tree
, tree
, poly_int64
);
183 static rtx
m68k_delegitimize_address (rtx
);
184 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
186 static rtx
m68k_function_arg (cumulative_args_t
, const function_arg_info
&);
187 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
188 static bool m68k_output_addr_const_extra (FILE *, rtx
);
189 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
190 static enum flt_eval_method
191 m68k_excess_precision (enum excess_precision_type
);
192 static unsigned int m68k_hard_regno_nregs (unsigned int, machine_mode
);
193 static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode
);
194 static bool m68k_modes_tieable_p (machine_mode
, machine_mode
);
195 static machine_mode
m68k_promote_function_mode (const_tree
, machine_mode
,
196 int *, const_tree
, int);
198 /* Initialize the GCC target structure. */
200 #if INT_OP_GROUP == INT_OP_DOT_WORD
201 #undef TARGET_ASM_ALIGNED_HI_OP
202 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
205 #if INT_OP_GROUP == INT_OP_NO_DOT
206 #undef TARGET_ASM_BYTE_OP
207 #define TARGET_ASM_BYTE_OP "\tbyte\t"
208 #undef TARGET_ASM_ALIGNED_HI_OP
209 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
210 #undef TARGET_ASM_ALIGNED_SI_OP
211 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
214 #if INT_OP_GROUP == INT_OP_DC
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
219 #undef TARGET_ASM_ALIGNED_SI_OP
220 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
223 #undef TARGET_ASM_UNALIGNED_HI_OP
224 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
225 #undef TARGET_ASM_UNALIGNED_SI_OP
226 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
228 #undef TARGET_ASM_OUTPUT_MI_THUNK
229 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
230 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
231 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
233 #undef TARGET_ASM_FILE_START_APP_OFF
234 #define TARGET_ASM_FILE_START_APP_OFF true
236 #undef TARGET_LEGITIMIZE_ADDRESS
237 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
239 #undef TARGET_SCHED_ADJUST_COST
240 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
242 #undef TARGET_SCHED_ISSUE_RATE
243 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
245 #undef TARGET_SCHED_VARIABLE_ISSUE
246 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
248 #undef TARGET_SCHED_INIT_GLOBAL
249 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
251 #undef TARGET_SCHED_FINISH_GLOBAL
252 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
254 #undef TARGET_SCHED_INIT
255 #define TARGET_SCHED_INIT m68k_sched_md_init
257 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
258 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
260 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
261 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
263 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
264 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
265 m68k_sched_first_cycle_multipass_dfa_lookahead
267 #undef TARGET_OPTION_OVERRIDE
268 #define TARGET_OPTION_OVERRIDE m68k_option_override
270 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
271 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
273 #undef TARGET_RTX_COSTS
274 #define TARGET_RTX_COSTS m68k_rtx_costs
276 #undef TARGET_ATTRIBUTE_TABLE
277 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
279 #undef TARGET_PROMOTE_PROTOTYPES
280 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
282 #undef TARGET_STRUCT_VALUE_RTX
283 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
285 #undef TARGET_CANNOT_FORCE_CONST_MEM
286 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
288 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
289 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
291 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
292 #undef TARGET_RETURN_IN_MEMORY
293 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
297 #undef TARGET_HAVE_TLS
298 #define TARGET_HAVE_TLS (true)
300 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
301 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
305 #define TARGET_LRA_P hook_bool_void_false
307 #undef TARGET_LEGITIMATE_ADDRESS_P
308 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
310 #undef TARGET_CAN_ELIMINATE
311 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
313 #undef TARGET_CONDITIONAL_REGISTER_USAGE
314 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
316 #undef TARGET_TRAMPOLINE_INIT
317 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
319 #undef TARGET_RETURN_POPS_ARGS
320 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
322 #undef TARGET_DELEGITIMIZE_ADDRESS
323 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
325 #undef TARGET_FUNCTION_ARG
326 #define TARGET_FUNCTION_ARG m68k_function_arg
328 #undef TARGET_FUNCTION_ARG_ADVANCE
329 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
331 #undef TARGET_LEGITIMATE_CONSTANT_P
332 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
334 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
335 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
337 #undef TARGET_C_EXCESS_PRECISION
338 #define TARGET_C_EXCESS_PRECISION m68k_excess_precision
340 /* The value stored by TAS. */
341 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
342 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
344 #undef TARGET_HARD_REGNO_NREGS
345 #define TARGET_HARD_REGNO_NREGS m68k_hard_regno_nregs
346 #undef TARGET_HARD_REGNO_MODE_OK
347 #define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
349 #undef TARGET_MODES_TIEABLE_P
350 #define TARGET_MODES_TIEABLE_P m68k_modes_tieable_p
352 #undef TARGET_PROMOTE_FUNCTION_MODE
353 #define TARGET_PROMOTE_FUNCTION_MODE m68k_promote_function_mode
355 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE
356 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
358 static const struct attribute_spec m68k_attribute_table
[] =
360 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
361 affects_type_identity, handler, exclude } */
362 { "interrupt", 0, 0, true, false, false, false,
363 m68k_handle_fndecl_attribute
, NULL
},
364 { "interrupt_handler", 0, 0, true, false, false, false,
365 m68k_handle_fndecl_attribute
, NULL
},
366 { "interrupt_thread", 0, 0, true, false, false, false,
367 m68k_handle_fndecl_attribute
, NULL
},
368 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
371 struct gcc_target targetm
= TARGET_INITIALIZER
;
373 /* Base flags for 68k ISAs. */
374 #define FL_FOR_isa_00 FL_ISA_68000
375 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
376 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
377 generated 68881 code for 68020 and 68030 targets unless explicitly told
379 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
380 | FL_BITFIELD | FL_68881 | FL_CAS)
381 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
382 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
384 /* Base flags for ColdFire ISAs. */
385 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
386 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
387 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
388 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
389 /* ISA_C is not upwardly compatible with ISA_B. */
390 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
394 /* Traditional 68000 instruction sets. */
400 /* ColdFire instruction set variants. */
408 /* Information about one of the -march, -mcpu or -mtune arguments. */
409 struct m68k_target_selection
411 /* The argument being described. */
414 /* For -mcpu, this is the device selected by the option.
415 For -mtune and -march, it is a representative device
416 for the microarchitecture or ISA respectively. */
417 enum target_device device
;
419 /* The M68K_DEVICE fields associated with DEVICE. See the comment
420 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
422 enum uarch_type microarch
;
427 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
428 static const struct m68k_target_selection all_devices
[] =
430 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
431 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
432 #include "m68k-devices.def"
434 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
437 /* A list of all ISAs, mapping each one to a representative device.
438 Used for -march selection. */
439 static const struct m68k_target_selection all_isas
[] =
441 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
442 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
443 #include "m68k-isas.def"
445 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
448 /* A list of all microarchitectures, mapping each one to a representative
449 device. Used for -mtune selection. */
450 static const struct m68k_target_selection all_microarchs
[] =
452 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
453 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
454 #include "m68k-microarchs.def"
455 #undef M68K_MICROARCH
456 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
459 /* The entries associated with the -mcpu, -march and -mtune settings,
460 or null for options that have not been used. */
461 const struct m68k_target_selection
*m68k_cpu_entry
;
462 const struct m68k_target_selection
*m68k_arch_entry
;
463 const struct m68k_target_selection
*m68k_tune_entry
;
465 /* Which CPU we are generating code for. */
466 enum target_device m68k_cpu
;
468 /* Which microarchitecture to tune for. */
469 enum uarch_type m68k_tune
;
471 /* Which FPU to use. */
472 enum fpu_type m68k_fpu
;
474 /* The set of FL_* flags that apply to the target processor. */
475 unsigned int m68k_cpu_flags
;
477 /* The set of FL_* flags that apply to the processor to be tuned for. */
478 unsigned int m68k_tune_flags
;
480 /* Asm templates for calling or jumping to an arbitrary symbolic address,
481 or NULL if such calls or jumps are not supported. The address is held
483 const char *m68k_symbolic_call
;
484 const char *m68k_symbolic_jump
;
486 /* Enum variable that corresponds to m68k_symbolic_call values. */
487 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
490 /* Implement TARGET_OPTION_OVERRIDE. */
493 m68k_option_override (void)
495 const struct m68k_target_selection
*entry
;
496 unsigned long target_mask
;
498 if (global_options_set
.x_m68k_arch_option
)
499 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
501 if (global_options_set
.x_m68k_cpu_option
)
502 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
504 if (global_options_set
.x_m68k_tune_option
)
505 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
513 -march=ARCH should generate code that runs any processor
514 implementing architecture ARCH. -mcpu=CPU should override -march
515 and should generate code that runs on processor CPU, making free
516 use of any instructions that CPU understands. -mtune=UARCH applies
517 on top of -mcpu or -march and optimizes the code for UARCH. It does
518 not change the target architecture. */
521 /* Complain if the -march setting is for a different microarchitecture,
522 or includes flags that the -mcpu setting doesn't. */
524 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
525 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
526 warning (0, "%<-mcpu=%s%> conflicts with %<-march=%s%>",
527 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
529 entry
= m68k_cpu_entry
;
532 entry
= m68k_arch_entry
;
535 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
537 m68k_cpu_flags
= entry
->flags
;
539 /* Use the architecture setting to derive default values for
543 /* ColdFire is lenient about alignment. */
544 if (!TARGET_COLDFIRE
)
545 target_mask
|= MASK_STRICT_ALIGNMENT
;
547 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
548 target_mask
|= MASK_BITFIELD
;
549 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
550 target_mask
|= MASK_CF_HWDIV
;
551 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
552 target_mask
|= MASK_HARD_FLOAT
;
553 target_flags
|= target_mask
& ~target_flags_explicit
;
555 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
556 m68k_cpu
= entry
->device
;
559 m68k_tune
= m68k_tune_entry
->microarch
;
560 m68k_tune_flags
= m68k_tune_entry
->flags
;
562 #ifdef M68K_DEFAULT_TUNE
563 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
565 enum target_device dev
;
566 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
567 m68k_tune_flags
= all_devices
[dev
].flags
;
572 m68k_tune
= entry
->microarch
;
573 m68k_tune_flags
= entry
->flags
;
576 /* Set the type of FPU. */
577 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
578 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
581 /* Sanity check to ensure that msep-data and mid-sahred-library are not
582 * both specified together. Doing so simply doesn't make sense.
584 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
585 error ("cannot specify both %<-msep-data%> and %<-mid-shared-library%>");
587 /* If we're generating code for a separate A5 relative data segment,
588 * we've got to enable -fPIC as well. This might be relaxable to
589 * -fpic but it hasn't been tested properly.
591 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
594 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
595 error if the target does not support them. */
596 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
597 error ("%<-mpcrel%> %<-fPIC%> is not currently supported on selected cpu");
599 /* ??? A historic way of turning on pic, or is this intended to
600 be an embedded thing that doesn't have the same name binding
601 significance that it does on hosted ELF systems? */
602 if (TARGET_PCREL
&& flag_pic
== 0)
607 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
609 m68k_symbolic_jump
= "jra %a0";
611 else if (TARGET_ID_SHARED_LIBRARY
)
612 /* All addresses must be loaded from the GOT. */
614 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
617 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
619 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
622 /* No unconditional long branch */;
623 else if (TARGET_PCREL
)
624 m68k_symbolic_jump
= "bra%.l %c0";
626 m68k_symbolic_jump
= "bra%.l %p0";
627 /* Turn off function cse if we are doing PIC. We always want
628 function call to be done as `bsr foo@PLTPC'. */
629 /* ??? It's traditional to do this for -mpcrel too, but it isn't
630 clear how intentional that is. */
631 flag_no_function_cse
= 1;
634 switch (m68k_symbolic_call_var
)
636 case M68K_SYMBOLIC_CALL_JSR
:
637 m68k_symbolic_call
= "jsr %a0";
640 case M68K_SYMBOLIC_CALL_BSR_C
:
641 m68k_symbolic_call
= "bsr%.l %c0";
644 case M68K_SYMBOLIC_CALL_BSR_P
:
645 m68k_symbolic_call
= "bsr%.l %p0";
648 case M68K_SYMBOLIC_CALL_NONE
:
649 gcc_assert (m68k_symbolic_call
== NULL
);
656 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
657 parse_alignment_opts ();
658 int label_alignment
= align_labels
.levels
[0].get_value ();
659 if (label_alignment
> 2)
661 warning (0, "%<-falign-labels=%d%> is not supported", label_alignment
);
662 str_align_labels
= "1";
665 int loop_alignment
= align_loops
.levels
[0].get_value ();
666 if (loop_alignment
> 2)
668 warning (0, "%<-falign-loops=%d%> is not supported", loop_alignment
);
669 str_align_loops
= "1";
673 if ((opt_fstack_limit_symbol_arg
!= NULL
|| opt_fstack_limit_register_no
>= 0)
676 warning (0, "%<-fstack-limit-%> options are not supported on this cpu");
677 opt_fstack_limit_symbol_arg
= NULL
;
678 opt_fstack_limit_register_no
= -1;
681 SUBTARGET_OVERRIDE_OPTIONS
;
683 /* Setup scheduling options. */
685 m68k_sched_cpu
= CPU_CFV1
;
687 m68k_sched_cpu
= CPU_CFV2
;
689 m68k_sched_cpu
= CPU_CFV3
;
691 m68k_sched_cpu
= CPU_CFV4
;
694 m68k_sched_cpu
= CPU_UNKNOWN
;
695 flag_schedule_insns
= 0;
696 flag_schedule_insns_after_reload
= 0;
697 flag_modulo_sched
= 0;
698 flag_live_range_shrinkage
= 0;
701 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
703 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
704 m68k_sched_mac
= MAC_CF_EMAC
;
705 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
706 m68k_sched_mac
= MAC_CF_MAC
;
708 m68k_sched_mac
= MAC_NO
;
712 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
715 m68k_override_options_after_change (void)
717 if (m68k_sched_cpu
== CPU_UNKNOWN
)
719 flag_schedule_insns
= 0;
720 flag_schedule_insns_after_reload
= 0;
721 flag_modulo_sched
= 0;
722 flag_live_range_shrinkage
= 0;
726 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
727 given argument and NAME is the argument passed to -mcpu. Return NULL
728 if -mcpu was not passed. */
731 m68k_cpp_cpu_ident (const char *prefix
)
735 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
738 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
739 given argument and NAME is the name of the representative device for
740 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
743 m68k_cpp_cpu_family (const char *prefix
)
747 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
750 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
751 "interrupt_handler" attribute and interrupt_thread if FUNC has an
752 "interrupt_thread" attribute. Otherwise, return
753 m68k_fk_normal_function. */
755 enum m68k_function_kind
756 m68k_get_function_kind (tree func
)
760 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
762 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
764 return m68k_fk_interrupt_handler
;
766 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
768 return m68k_fk_interrupt_handler
;
770 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
772 return m68k_fk_interrupt_thread
;
774 return m68k_fk_normal_function
;
777 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
778 struct attribute_spec.handler. */
780 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
781 tree args ATTRIBUTE_UNUSED
,
782 int flags ATTRIBUTE_UNUSED
,
785 if (TREE_CODE (*node
) != FUNCTION_DECL
)
787 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
789 *no_add_attrs
= true;
792 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
794 error ("multiple interrupt attributes not allowed");
795 *no_add_attrs
= true;
799 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
801 error ("interrupt_thread is available only on fido");
802 *no_add_attrs
= true;
809 m68k_compute_frame_layout (void)
813 enum m68k_function_kind func_kind
=
814 m68k_get_function_kind (current_function_decl
);
815 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
816 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
818 /* Only compute the frame once per function.
819 Don't cache information until reload has been completed. */
820 if (current_frame
.funcdef_no
== current_function_funcdef_no
824 current_frame
.size
= (get_frame_size () + 3) & -4;
828 /* Interrupt thread does not need to save any register. */
829 if (!interrupt_thread
)
830 for (regno
= 0; regno
< 16; regno
++)
831 if (m68k_save_reg (regno
, interrupt_handler
))
833 mask
|= 1 << (regno
- D0_REG
);
836 current_frame
.offset
= saved
* 4;
837 current_frame
.reg_no
= saved
;
838 current_frame
.reg_mask
= mask
;
840 current_frame
.foffset
= 0;
842 if (TARGET_HARD_FLOAT
)
844 /* Interrupt thread does not need to save any register. */
845 if (!interrupt_thread
)
846 for (regno
= 16; regno
< 24; regno
++)
847 if (m68k_save_reg (regno
, interrupt_handler
))
849 mask
|= 1 << (regno
- FP0_REG
);
852 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
853 current_frame
.offset
+= current_frame
.foffset
;
855 current_frame
.fpu_no
= saved
;
856 current_frame
.fpu_mask
= mask
;
858 /* Remember what function this frame refers to. */
859 current_frame
.funcdef_no
= current_function_funcdef_no
;
862 /* Worker function for TARGET_CAN_ELIMINATE. */
865 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
867 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
871 m68k_initial_elimination_offset (int from
, int to
)
874 /* The arg pointer points 8 bytes before the start of the arguments,
875 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
876 frame pointer in most frames. */
877 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
878 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
879 return argptr_offset
;
881 m68k_compute_frame_layout ();
883 gcc_assert (to
== STACK_POINTER_REGNUM
);
886 case ARG_POINTER_REGNUM
:
887 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
888 case FRAME_POINTER_REGNUM
:
889 return current_frame
.offset
+ current_frame
.size
;
895 /* Refer to the array `regs_ever_live' to determine which registers
896 to save; `regs_ever_live[I]' is nonzero if register number I
897 is ever used in the function. This function is responsible for
898 knowing which registers should not be saved even if used.
899 Return true if we need to save REGNO. */
902 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
904 if (flag_pic
&& regno
== PIC_REG
)
906 if (crtl
->saves_all_registers
)
908 if (crtl
->uses_pic_offset_table
)
910 /* Reload may introduce constant pool references into a function
911 that thitherto didn't need a PIC register. Note that the test
912 above will not catch that case because we will only set
913 crtl->uses_pic_offset_table when emitting
914 the address reloads. */
915 if (crtl
->uses_const_pool
)
919 if (crtl
->calls_eh_return
)
924 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
925 if (test
== INVALID_REGNUM
)
932 /* Fixed regs we never touch. */
933 if (fixed_regs
[regno
])
936 /* The frame pointer (if it is such) is handled specially. */
937 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
940 /* Interrupt handlers must also save call_used_regs
941 if they are live or when calling nested functions. */
942 if (interrupt_handler
)
944 if (df_regs_ever_live_p (regno
))
947 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
951 /* Never need to save registers that aren't touched. */
952 if (!df_regs_ever_live_p (regno
))
955 /* Otherwise save everything that isn't call-clobbered. */
956 return !call_used_regs
[regno
];
959 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
960 the lowest memory address. COUNT is the number of registers to be
961 moved, with register REGNO + I being moved if bit I of MASK is set.
962 STORE_P specifies the direction of the move and ADJUST_STACK_P says
963 whether or not this is pre-decrement (if STORE_P) or post-increment
964 (if !STORE_P) operation. */
967 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
968 unsigned int count
, unsigned int regno
,
969 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
972 rtx body
, addr
, src
, operands
[2];
975 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
976 mode
= reg_raw_mode
[regno
];
981 src
= plus_constant (Pmode
, base
,
983 * GET_MODE_SIZE (mode
)
984 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
985 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
988 for (; mask
!= 0; mask
>>= 1, regno
++)
991 addr
= plus_constant (Pmode
, base
, offset
);
992 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
993 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
994 XVECEXP (body
, 0, i
++)
995 = gen_rtx_SET (operands
[0], operands
[1]);
996 offset
+= GET_MODE_SIZE (mode
);
998 gcc_assert (i
== XVECLEN (body
, 0));
1000 return emit_insn (body
);
1003 /* Make INSN a frame-related instruction. */
1006 m68k_set_frame_related (rtx_insn
*insn
)
1011 RTX_FRAME_RELATED_P (insn
) = 1;
1012 body
= PATTERN (insn
);
1013 if (GET_CODE (body
) == PARALLEL
)
1014 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
1015 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
1018 /* Emit RTL for the "prologue" define_expand. */
1021 m68k_expand_prologue (void)
1023 HOST_WIDE_INT fsize_with_regs
;
1024 rtx limit
, src
, dest
;
1026 m68k_compute_frame_layout ();
1028 if (flag_stack_usage_info
)
1029 current_function_static_stack_size
1030 = current_frame
.size
+ current_frame
.offset
;
1032 /* If the stack limit is a symbol, we can check it here,
1033 before actually allocating the space. */
1034 if (crtl
->limit_stack
1035 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1037 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1038 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1040 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1041 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1043 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1044 stack_pointer_rtx
, limit
),
1045 stack_pointer_rtx
, limit
,
1049 fsize_with_regs
= current_frame
.size
;
1050 if (TARGET_COLDFIRE
)
1052 /* ColdFire's move multiple instructions do not allow pre-decrement
1053 addressing. Add the size of movem saves to the initial stack
1054 allocation instead. */
1055 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1056 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1057 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1058 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1061 if (frame_pointer_needed
)
1063 if (fsize_with_regs
== 0 && TUNE_68040
)
1065 /* On the 68040, two separate moves are faster than link.w 0. */
1066 dest
= gen_frame_mem (Pmode
,
1067 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1068 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1069 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1070 stack_pointer_rtx
));
1072 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1073 m68k_set_frame_related
1074 (emit_insn (gen_link (frame_pointer_rtx
,
1075 GEN_INT (-4 - fsize_with_regs
))));
1078 m68k_set_frame_related
1079 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1080 m68k_set_frame_related
1081 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1083 GEN_INT (-fsize_with_regs
))));
1086 /* If the frame pointer is needed, emit a special barrier that
1087 will prevent the scheduler from moving stores to the frame
1088 before the stack adjustment. */
1089 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1091 else if (fsize_with_regs
!= 0)
1092 m68k_set_frame_related
1093 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1095 GEN_INT (-fsize_with_regs
))));
1097 if (current_frame
.fpu_mask
)
1099 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1101 m68k_set_frame_related
1102 (m68k_emit_movem (stack_pointer_rtx
,
1103 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1104 current_frame
.fpu_no
, FP0_REG
,
1105 current_frame
.fpu_mask
, true, true));
1110 /* If we're using moveml to save the integer registers,
1111 the stack pointer will point to the bottom of the moveml
1112 save area. Find the stack offset of the first FP register. */
1113 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1116 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1117 m68k_set_frame_related
1118 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1119 current_frame
.fpu_no
, FP0_REG
,
1120 current_frame
.fpu_mask
, true, false));
1124 /* If the stack limit is not a symbol, check it here.
1125 This has the disadvantage that it may be too late... */
1126 if (crtl
->limit_stack
)
1128 if (REG_P (stack_limit_rtx
))
1129 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1131 stack_pointer_rtx
, stack_limit_rtx
,
1134 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1135 warning (0, "stack limit expression is not supported");
1138 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1140 /* Store each register separately in the same order moveml does. */
1143 for (i
= 16; i
-- > 0; )
1144 if (current_frame
.reg_mask
& (1 << i
))
1146 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1147 dest
= gen_frame_mem (SImode
,
1148 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1149 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1154 if (TARGET_COLDFIRE
)
1155 /* The required register save space has already been allocated.
1156 The first register should be stored at (%sp). */
1157 m68k_set_frame_related
1158 (m68k_emit_movem (stack_pointer_rtx
, 0,
1159 current_frame
.reg_no
, D0_REG
,
1160 current_frame
.reg_mask
, true, false));
1162 m68k_set_frame_related
1163 (m68k_emit_movem (stack_pointer_rtx
,
1164 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1165 current_frame
.reg_no
, D0_REG
,
1166 current_frame
.reg_mask
, true, true));
1169 if (!TARGET_SEP_DATA
1170 && crtl
->uses_pic_offset_table
)
1171 emit_insn (gen_load_got (pic_offset_table_rtx
));
1174 /* Return true if a simple (return) instruction is sufficient for this
1175 instruction (i.e. if no epilogue is needed). */
1178 m68k_use_return_insn (void)
1180 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1183 m68k_compute_frame_layout ();
1184 return current_frame
.offset
== 0;
1187 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1188 SIBCALL_P says which.
1190 The function epilogue should not depend on the current stack pointer!
1191 It should use the frame pointer only, if there is a frame pointer.
1192 This is mandatory because of alloca; we also take advantage of it to
1193 omit stack adjustments before returning. */
1196 m68k_expand_epilogue (bool sibcall_p
)
1198 HOST_WIDE_INT fsize
, fsize_with_regs
;
1199 bool big
, restore_from_sp
;
1201 m68k_compute_frame_layout ();
1203 fsize
= current_frame
.size
;
1205 restore_from_sp
= false;
1207 /* FIXME : crtl->is_leaf below is too strong.
1208 What we really need to know there is if there could be pending
1209 stack adjustment needed at that point. */
1210 restore_from_sp
= (!frame_pointer_needed
1211 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1213 /* fsize_with_regs is the size we need to adjust the sp when
1214 popping the frame. */
1215 fsize_with_regs
= fsize
;
1216 if (TARGET_COLDFIRE
&& restore_from_sp
)
1218 /* ColdFire's move multiple instructions do not allow post-increment
1219 addressing. Add the size of movem loads to the final deallocation
1221 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1222 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1223 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1224 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1227 if (current_frame
.offset
+ fsize
>= 0x8000
1229 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1232 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1233 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1235 /* ColdFire's move multiple instructions do not support the
1236 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1237 stack-based restore. */
1238 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1239 GEN_INT (-(current_frame
.offset
+ fsize
)));
1240 emit_insn (gen_blockage ());
1241 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1242 gen_rtx_REG (Pmode
, A1_REG
),
1243 frame_pointer_rtx
));
1244 restore_from_sp
= true;
1248 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1254 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1256 /* Restore each register separately in the same order moveml does. */
1258 HOST_WIDE_INT offset
;
1260 offset
= current_frame
.offset
+ fsize
;
1261 for (i
= 0; i
< 16; i
++)
1262 if (current_frame
.reg_mask
& (1 << i
))
1268 /* Generate the address -OFFSET(%fp,%a1.l). */
1269 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1270 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1271 addr
= plus_constant (Pmode
, addr
, -offset
);
1273 else if (restore_from_sp
)
1274 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1276 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1277 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1278 gen_frame_mem (SImode
, addr
));
1279 offset
-= GET_MODE_SIZE (SImode
);
1282 else if (current_frame
.reg_mask
)
1285 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1286 gen_rtx_REG (Pmode
, A1_REG
),
1288 -(current_frame
.offset
+ fsize
),
1289 current_frame
.reg_no
, D0_REG
,
1290 current_frame
.reg_mask
, false, false);
1291 else if (restore_from_sp
)
1292 m68k_emit_movem (stack_pointer_rtx
, 0,
1293 current_frame
.reg_no
, D0_REG
,
1294 current_frame
.reg_mask
, false,
1297 m68k_emit_movem (frame_pointer_rtx
,
1298 -(current_frame
.offset
+ fsize
),
1299 current_frame
.reg_no
, D0_REG
,
1300 current_frame
.reg_mask
, false, false);
1303 if (current_frame
.fpu_no
> 0)
1306 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1307 gen_rtx_REG (Pmode
, A1_REG
),
1309 -(current_frame
.foffset
+ fsize
),
1310 current_frame
.fpu_no
, FP0_REG
,
1311 current_frame
.fpu_mask
, false, false);
1312 else if (restore_from_sp
)
1314 if (TARGET_COLDFIRE
)
1318 /* If we used moveml to restore the integer registers, the
1319 stack pointer will still point to the bottom of the moveml
1320 save area. Find the stack offset of the first FP
1322 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1325 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1326 m68k_emit_movem (stack_pointer_rtx
, offset
,
1327 current_frame
.fpu_no
, FP0_REG
,
1328 current_frame
.fpu_mask
, false, false);
1331 m68k_emit_movem (stack_pointer_rtx
, 0,
1332 current_frame
.fpu_no
, FP0_REG
,
1333 current_frame
.fpu_mask
, false, true);
1336 m68k_emit_movem (frame_pointer_rtx
,
1337 -(current_frame
.foffset
+ fsize
),
1338 current_frame
.fpu_no
, FP0_REG
,
1339 current_frame
.fpu_mask
, false, false);
1342 emit_insn (gen_blockage ());
1343 if (frame_pointer_needed
)
1344 emit_insn (gen_unlink (frame_pointer_rtx
));
1345 else if (fsize_with_regs
)
1346 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1348 GEN_INT (fsize_with_regs
)));
1350 if (crtl
->calls_eh_return
)
1351 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1353 EH_RETURN_STACKADJ_RTX
));
1356 emit_jump_insn (ret_rtx
);
1359 /* Return true if X is a valid comparison operator for the dbcc
1362 Note it rejects floating point comparison operators.
1363 (In the future we could use Fdbcc).
1365 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1368 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1370 switch (GET_CODE (x
))
1372 case EQ
: case NE
: case GTU
: case LTU
:
1376 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1378 case GT
: case LT
: case GE
: case LE
:
1379 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1385 /* Return nonzero if flags are currently in the 68881 flag register. */
1387 flags_in_68881 (void)
1389 /* We could add support for these in the future */
1390 return cc_status
.flags
& CC_IN_68881
;
1393 /* Return true if PARALLEL contains register REGNO. */
1395 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1399 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1402 if (GET_CODE (parallel
) != PARALLEL
)
1405 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1409 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1410 if (REG_P (x
) && REGNO (x
) == regno
)
1417 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1420 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1422 enum m68k_function_kind kind
;
1424 /* We cannot use sibcalls for nested functions because we use the
1425 static chain register for indirect calls. */
1426 if (CALL_EXPR_STATIC_CHAIN (exp
))
1429 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1431 /* Check that the return value locations are the same. For
1432 example that we aren't returning a value from the sibling in
1433 a D0 register but then need to transfer it to a A0 register. */
1437 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1439 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1441 /* Check that the values are equal or that the result the callee
1442 function returns is superset of what the current function returns. */
1443 if (!(rtx_equal_p (cfun_value
, call_value
)
1444 || (REG_P (cfun_value
)
1445 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1449 kind
= m68k_get_function_kind (current_function_decl
);
1450 if (kind
== m68k_fk_normal_function
)
1451 /* We can always sibcall from a normal function, because it's
1452 undefined if it is calling an interrupt function. */
1455 /* Otherwise we can only sibcall if the function kind is known to be
1457 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1463 /* On the m68k all args are always pushed. */
1466 m68k_function_arg (cumulative_args_t
, const function_arg_info
&)
1472 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1473 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1475 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1477 *cum
+= (mode
!= BLKmode
1478 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1479 : (int_size_in_bytes (type
) + 3) & ~3);
1482 /* Convert X to a legitimate function call memory reference and return the
1486 m68k_legitimize_call_address (rtx x
)
1488 gcc_assert (MEM_P (x
));
1489 if (call_operand (XEXP (x
, 0), VOIDmode
))
1491 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1494 /* Likewise for sibling calls. */
1497 m68k_legitimize_sibcall_address (rtx x
)
1499 gcc_assert (MEM_P (x
));
1500 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1503 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1504 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1507 /* Convert X to a legitimate address and return it if successful. Otherwise
1510 For the 68000, we handle X+REG by loading X into a register R and
1511 using R+REG. R will go in an address reg and indexing will be used.
1512 However, if REG is a broken-out memory address or multiplication,
1513 nothing needs to be done because REG can certainly go in an address reg. */
1516 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1518 if (m68k_tls_symbol_p (x
))
1519 return m68k_legitimize_tls_address (x
);
1521 if (GET_CODE (x
) == PLUS
)
1523 int ch
= (x
) != (oldx
);
1526 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1528 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1531 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1533 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1536 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1540 if (GET_CODE (XEXP (x
, 1)) == REG
1541 && GET_CODE (XEXP (x
, 0)) == REG
)
1543 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1546 x
= force_operand (x
, 0);
1550 if (memory_address_p (mode
, x
))
1553 if (GET_CODE (XEXP (x
, 0)) == REG
1554 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1555 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1556 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1558 rtx temp
= gen_reg_rtx (Pmode
);
1559 rtx val
= force_operand (XEXP (x
, 1), 0);
1560 emit_move_insn (temp
, val
);
1563 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1564 && GET_CODE (XEXP (x
, 0)) == REG
)
1565 x
= force_operand (x
, 0);
1567 else if (GET_CODE (XEXP (x
, 1)) == REG
1568 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1569 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1570 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1572 rtx temp
= gen_reg_rtx (Pmode
);
1573 rtx val
= force_operand (XEXP (x
, 0), 0);
1574 emit_move_insn (temp
, val
);
1577 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1578 && GET_CODE (XEXP (x
, 1)) == REG
)
1579 x
= force_operand (x
, 0);
1587 /* Output a dbCC; jCC sequence. Note we do not handle the
1588 floating point version of this sequence (Fdbcc). We also
1589 do not handle alternative conditions when CC_NO_OVERFLOW is
1590 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1591 kick those out before we get here. */
1594 output_dbcc_and_branch (rtx
*operands
)
1596 switch (GET_CODE (operands
[3]))
1599 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1603 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1607 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1611 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1615 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1619 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1623 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1627 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1631 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1635 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1642 /* If the decrement is to be done in SImode, then we have
1643 to compensate for the fact that dbcc decrements in HImode. */
1644 switch (GET_MODE (operands
[0]))
1647 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1659 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1662 enum rtx_code op_code
= GET_CODE (op
);
1664 /* This does not produce a useful cc. */
1667 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1668 below. Swap the operands and change the op if these requirements
1669 are not fulfilled. */
1670 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1674 operand1
= operand2
;
1676 op_code
= swap_condition (op_code
);
1678 loperands
[0] = operand1
;
1679 if (GET_CODE (operand1
) == REG
)
1680 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1682 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1683 if (operand2
!= const0_rtx
)
1685 loperands
[2] = operand2
;
1686 if (GET_CODE (operand2
) == REG
)
1687 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1689 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1691 loperands
[4] = gen_label_rtx ();
1692 if (operand2
!= const0_rtx
)
1693 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1696 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1697 output_asm_insn ("tst%.l %0", loperands
);
1699 output_asm_insn ("cmp%.w #0,%0", loperands
);
1701 output_asm_insn ("jne %l4", loperands
);
1703 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1704 output_asm_insn ("tst%.l %1", loperands
);
1706 output_asm_insn ("cmp%.w #0,%1", loperands
);
1709 loperands
[5] = dest
;
1714 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1715 CODE_LABEL_NUMBER (loperands
[4]));
1716 output_asm_insn ("seq %5", loperands
);
1720 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1721 CODE_LABEL_NUMBER (loperands
[4]));
1722 output_asm_insn ("sne %5", loperands
);
1726 loperands
[6] = gen_label_rtx ();
1727 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1728 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1729 CODE_LABEL_NUMBER (loperands
[4]));
1730 output_asm_insn ("sgt %5", loperands
);
1731 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1732 CODE_LABEL_NUMBER (loperands
[6]));
1736 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1737 CODE_LABEL_NUMBER (loperands
[4]));
1738 output_asm_insn ("shi %5", loperands
);
1742 loperands
[6] = gen_label_rtx ();
1743 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1744 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1745 CODE_LABEL_NUMBER (loperands
[4]));
1746 output_asm_insn ("slt %5", loperands
);
1747 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1748 CODE_LABEL_NUMBER (loperands
[6]));
1752 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1753 CODE_LABEL_NUMBER (loperands
[4]));
1754 output_asm_insn ("scs %5", loperands
);
1758 loperands
[6] = gen_label_rtx ();
1759 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1760 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1761 CODE_LABEL_NUMBER (loperands
[4]));
1762 output_asm_insn ("sge %5", loperands
);
1763 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1764 CODE_LABEL_NUMBER (loperands
[6]));
1768 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1769 CODE_LABEL_NUMBER (loperands
[4]));
1770 output_asm_insn ("scc %5", loperands
);
1774 loperands
[6] = gen_label_rtx ();
1775 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1776 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1777 CODE_LABEL_NUMBER (loperands
[4]));
1778 output_asm_insn ("sle %5", loperands
);
1779 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1780 CODE_LABEL_NUMBER (loperands
[6]));
1784 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1785 CODE_LABEL_NUMBER (loperands
[4]));
1786 output_asm_insn ("sls %5", loperands
);
1796 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1798 operands
[0] = countop
;
1799 operands
[1] = dataop
;
1801 if (GET_CODE (countop
) == CONST_INT
)
1803 register int count
= INTVAL (countop
);
1804 /* If COUNT is bigger than size of storage unit in use,
1805 advance to the containing unit of same size. */
1806 if (count
> signpos
)
1808 int offset
= (count
& ~signpos
) / 8;
1809 count
= count
& signpos
;
1810 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1812 if (count
== signpos
)
1813 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1815 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1817 /* These three statements used to use next_insns_test_no...
1818 but it appears that this should do the same job. */
1820 && next_insn_tests_no_inequality (insn
))
1823 && next_insn_tests_no_inequality (insn
))
1826 && next_insn_tests_no_inequality (insn
))
1828 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1829 On some m68k variants unfortunately that's slower than btst.
1830 On 68000 and higher, that should also work for all HImode operands. */
1831 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1833 if (count
== 3 && DATA_REG_P (operands
[1])
1834 && next_insn_tests_no_inequality (insn
))
1836 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1837 return "move%.w %1,%%ccr";
1839 if (count
== 2 && DATA_REG_P (operands
[1])
1840 && next_insn_tests_no_inequality (insn
))
1842 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1843 return "move%.w %1,%%ccr";
1845 /* count == 1 followed by bvc/bvs and
1846 count == 0 followed by bcc/bcs are also possible, but need
1847 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1850 cc_status
.flags
= CC_NOT_NEGATIVE
;
1852 return "btst %0,%1";
1855 /* Return true if X is a legitimate base register. STRICT_P says
1856 whether we need strict checking. */
1859 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1861 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1862 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1867 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1868 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1871 /* Return true if X is a legitimate index register. STRICT_P says
1872 whether we need strict checking. */
1875 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1877 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1882 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1883 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1886 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1887 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1888 ADDRESS if so. STRICT_P says whether we need strict checking. */
1891 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1895 /* Check for a scale factor. */
1897 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1898 && GET_CODE (x
) == MULT
1899 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1900 && (INTVAL (XEXP (x
, 1)) == 2
1901 || INTVAL (XEXP (x
, 1)) == 4
1902 || (INTVAL (XEXP (x
, 1)) == 8
1903 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1905 scale
= INTVAL (XEXP (x
, 1));
1909 /* Check for a word extension. */
1910 if (!TARGET_COLDFIRE
1911 && GET_CODE (x
) == SIGN_EXTEND
1912 && GET_MODE (XEXP (x
, 0)) == HImode
)
1915 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1917 address
->scale
= scale
;
1925 /* Return true if X is an illegitimate symbolic constant. */
1928 m68k_illegitimate_symbolic_constant_p (rtx x
)
1932 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1934 split_const (x
, &base
, &offset
);
1935 if (GET_CODE (base
) == SYMBOL_REF
1936 && !offset_within_block_p (base
, INTVAL (offset
)))
1939 return m68k_tls_reference_p (x
, false);
1942 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1945 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1947 return m68k_illegitimate_symbolic_constant_p (x
);
1950 /* Return true if X is a legitimate constant address that can reach
1951 bytes in the range [X, X + REACH). STRICT_P says whether we need
1955 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1959 if (!CONSTANT_ADDRESS_P (x
))
1963 && !(strict_p
&& TARGET_PCREL
)
1964 && symbolic_operand (x
, VOIDmode
))
1967 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1969 split_const (x
, &base
, &offset
);
1970 if (GET_CODE (base
) == SYMBOL_REF
1971 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1975 return !m68k_tls_reference_p (x
, false);
1978 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1979 labels will become jump tables. */
1982 m68k_jump_table_ref_p (rtx x
)
1984 if (GET_CODE (x
) != LABEL_REF
)
1987 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1988 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1991 insn
= next_nonnote_insn (insn
);
1992 return insn
&& JUMP_TABLE_DATA_P (insn
);
1995 /* Return true if X is a legitimate address for values of mode MODE.
1996 STRICT_P says whether strict checking is needed. If the address
1997 is valid, describe its components in *ADDRESS. */
2000 m68k_decompose_address (machine_mode mode
, rtx x
,
2001 bool strict_p
, struct m68k_address
*address
)
2005 memset (address
, 0, sizeof (*address
));
2007 if (mode
== BLKmode
)
2010 reach
= GET_MODE_SIZE (mode
);
2012 /* Check for (An) (mode 2). */
2013 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2019 /* Check for -(An) and (An)+ (modes 3 and 4). */
2020 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
2021 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2023 address
->code
= GET_CODE (x
);
2024 address
->base
= XEXP (x
, 0);
2028 /* Check for (d16,An) (mode 5). */
2029 if (GET_CODE (x
) == PLUS
2030 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2031 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2032 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2034 address
->base
= XEXP (x
, 0);
2035 address
->offset
= XEXP (x
, 1);
2039 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2040 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2042 if (GET_CODE (x
) == PLUS
2043 && XEXP (x
, 0) == pic_offset_table_rtx
)
2045 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2046 they are invalid in this context. */
2047 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2049 address
->base
= XEXP (x
, 0);
2050 address
->offset
= XEXP (x
, 1);
2055 /* The ColdFire FPU only accepts addressing modes 2-5. */
2056 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2059 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2060 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2061 All these modes are variations of mode 7. */
2062 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2064 address
->offset
= x
;
2068 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2071 ??? do_tablejump creates these addresses before placing the target
2072 label, so we have to assume that unplaced labels are jump table
2073 references. It seems unlikely that we would ever generate indexed
2074 accesses to unplaced labels in other cases. */
2075 if (GET_CODE (x
) == PLUS
2076 && m68k_jump_table_ref_p (XEXP (x
, 1))
2077 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2079 address
->offset
= XEXP (x
, 1);
2083 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2084 (bd,An,Xn.SIZE*SCALE) addresses. */
2088 /* Check for a nonzero base displacement. */
2089 if (GET_CODE (x
) == PLUS
2090 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2092 address
->offset
= XEXP (x
, 1);
2096 /* Check for a suppressed index register. */
2097 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2103 /* Check for a suppressed base register. Do not allow this case
2104 for non-symbolic offsets as it effectively gives gcc freedom
2105 to treat data registers as base registers, which can generate
2108 && symbolic_operand (address
->offset
, VOIDmode
)
2109 && m68k_decompose_index (x
, strict_p
, address
))
2114 /* Check for a nonzero base displacement. */
2115 if (GET_CODE (x
) == PLUS
2116 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2117 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2119 address
->offset
= XEXP (x
, 1);
2124 /* We now expect the sum of a base and an index. */
2125 if (GET_CODE (x
) == PLUS
)
2127 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2128 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2130 address
->base
= XEXP (x
, 0);
2134 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2135 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2137 address
->base
= XEXP (x
, 1);
2144 /* Return true if X is a legitimate address for values of mode MODE.
2145 STRICT_P says whether strict checking is needed. */
2148 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2150 struct m68k_address address
;
2152 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2155 /* Return true if X is a memory, describing its address in ADDRESS if so.
2156 Apply strict checking if called during or after reload. */
2159 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2162 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2163 reload_in_progress
|| reload_completed
,
2167 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2170 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2172 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2175 /* Return true if X matches the 'Q' constraint. It must be a memory
2176 with a base address and no constant offset or index. */
2179 m68k_matches_q_p (rtx x
)
2181 struct m68k_address address
;
2183 return (m68k_legitimate_mem_p (x
, &address
)
2184 && address
.code
== UNKNOWN
2190 /* Return true if X matches the 'U' constraint. It must be a base address
2191 with a constant offset and no index. */
2194 m68k_matches_u_p (rtx x
)
2196 struct m68k_address address
;
2198 return (m68k_legitimate_mem_p (x
, &address
)
2199 && address
.code
== UNKNOWN
2205 /* Return GOT pointer. */
2210 if (pic_offset_table_rtx
== NULL_RTX
)
2211 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2213 crtl
->uses_pic_offset_table
= 1;
2215 return pic_offset_table_rtx
;
2218 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2220 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2221 RELOC_TLSIE
, RELOC_TLSLE
};
2223 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2225 /* Wrap symbol X into unspec representing relocation RELOC.
2226 BASE_REG - register that should be added to the result.
2227 TEMP_REG - if non-null, temporary register. */
2230 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2234 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2236 if (TARGET_COLDFIRE
&& use_x_p
)
2237 /* When compiling with -mx{got, tls} switch the code will look like this:
2239 move.l <X>@<RELOC>,<TEMP_REG>
2240 add.l <BASE_REG>,<TEMP_REG> */
2242 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2243 to put @RELOC after reference. */
2244 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2246 x
= gen_rtx_CONST (Pmode
, x
);
2248 if (temp_reg
== NULL
)
2250 gcc_assert (can_create_pseudo_p ());
2251 temp_reg
= gen_reg_rtx (Pmode
);
2254 emit_move_insn (temp_reg
, x
);
2255 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2260 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2262 x
= gen_rtx_CONST (Pmode
, x
);
2264 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2270 /* Helper for m68k_unwrap_symbol.
2271 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2272 sets *RELOC_PTR to relocation type for the symbol. */
2275 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2276 enum m68k_reloc
*reloc_ptr
)
2278 if (GET_CODE (orig
) == CONST
)
2281 enum m68k_reloc dummy
;
2285 if (reloc_ptr
== NULL
)
2288 /* Handle an addend. */
2289 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2290 && CONST_INT_P (XEXP (x
, 1)))
2293 if (GET_CODE (x
) == UNSPEC
)
2295 switch (XINT (x
, 1))
2297 case UNSPEC_RELOC16
:
2298 orig
= XVECEXP (x
, 0, 0);
2299 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2302 case UNSPEC_RELOC32
:
2303 if (unwrap_reloc32_p
)
2305 orig
= XVECEXP (x
, 0, 0);
2306 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2319 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2320 UNSPEC_RELOC32 wrappers. */
2323 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2325 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2328 /* Adjust decorated address operand before outputing assembler for it. */
2331 m68k_adjust_decorated_operand (rtx op
)
2333 /* Combine and, possibly, other optimizations may do good job
2335 (const (unspec [(symbol)]))
2337 (const (plus (unspec [(symbol)])
2339 The problem with this is emitting @TLS or @GOT decorations.
2340 The decoration is emitted when processing (unspec), so the
2341 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2343 It seems that the easiest solution to this is to convert such
2345 (const (unspec [(plus (symbol)
2347 Note, that the top level of operand remains intact, so we don't have
2348 to patch up anything outside of the operand. */
2350 subrtx_var_iterator::array_type array
;
2351 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2354 if (m68k_unwrap_symbol (x
, true) != x
)
2358 gcc_assert (GET_CODE (x
) == CONST
);
2361 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2366 unspec
= XEXP (plus
, 0);
2367 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2368 addend
= XEXP (plus
, 1);
2369 gcc_assert (CONST_INT_P (addend
));
2371 /* We now have all the pieces, rearrange them. */
2373 /* Move symbol to plus. */
2374 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2376 /* Move plus inside unspec. */
2377 XVECEXP (unspec
, 0, 0) = plus
;
2379 /* Move unspec to top level of const. */
2380 XEXP (x
, 0) = unspec
;
2382 iter
.skip_subrtxes ();
2387 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2388 If REG is non-null, use it; generate new pseudo otherwise. */
2391 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2395 if (reg
== NULL_RTX
)
2397 gcc_assert (can_create_pseudo_p ());
2398 reg
= gen_reg_rtx (Pmode
);
2401 insn
= emit_move_insn (reg
, x
);
2402 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2404 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2409 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2413 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2415 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2417 x
= gen_rtx_MEM (Pmode
, x
);
2418 MEM_READONLY_P (x
) = 1;
2423 /* Legitimize PIC addresses. If the address is already
2424 position-independent, we return ORIG. Newly generated
2425 position-independent addresses go to REG. If we need more
2426 than one register, we lose.
2428 An address is legitimized by making an indirect reference
2429 through the Global Offset Table with the name of the symbol
2432 The assembler and linker are responsible for placing the
2433 address of the symbol in the GOT. The function prologue
2434 is responsible for initializing a5 to the starting address
2437 The assembler is also responsible for translating a symbol name
2438 into a constant displacement from the start of the GOT.
2440 A quick example may make things a little clearer:
2442 When not generating PIC code to store the value 12345 into _foo
2443 we would generate the following code:
2447 When generating PIC two transformations are made. First, the compiler
2448 loads the address of foo into a register. So the first transformation makes:
2453 The code in movsi will intercept the lea instruction and call this
2454 routine which will transform the instructions into:
2456 movel a5@(_foo:w), a0
2460 That (in a nutshell) is how *all* symbol and label references are
2464 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2469 /* First handle a simple SYMBOL_REF or LABEL_REF */
2470 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2474 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2475 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2477 else if (GET_CODE (orig
) == CONST
)
2481 /* Make sure this has not already been legitimized. */
2482 if (m68k_unwrap_symbol (orig
, true) != orig
)
2487 /* legitimize both operands of the PLUS */
2488 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2490 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2491 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2492 base
== reg
? 0 : reg
);
2494 if (GET_CODE (orig
) == CONST_INT
)
2495 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2497 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2503 /* The __tls_get_addr symbol. */
2504 static GTY(()) rtx m68k_tls_get_addr
;
2506 /* Return SYMBOL_REF for __tls_get_addr. */
2509 m68k_get_tls_get_addr (void)
2511 if (m68k_tls_get_addr
== NULL_RTX
)
2512 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2514 return m68k_tls_get_addr
;
2517 /* Return libcall result in A0 instead of usual D0. */
2518 static bool m68k_libcall_value_in_a0_p
= false;
2520 /* Emit instruction sequence that calls __tls_get_addr. X is
2521 the TLS symbol we are referencing and RELOC is the symbol type to use
2522 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2523 emitted. A pseudo register with result of __tls_get_addr call is
2527 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2533 /* Emit the call sequence. */
2536 /* FIXME: Unfortunately, emit_library_call_value does not
2537 consider (plus (%a5) (const (unspec))) to be a good enough
2538 operand for push, so it forces it into a register. The bad
2539 thing about this is that combiner, due to copy propagation and other
2540 optimizations, sometimes cannot later fix this. As a consequence,
2541 additional register may be allocated resulting in a spill.
2542 For reference, see args processing loops in
2543 calls.c:emit_library_call_value_1.
2544 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2545 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2547 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2548 is the simpliest way of generating a call. The difference between
2549 __tls_get_addr() and libcall is that the result is returned in D0
2550 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2551 which temporarily switches returning the result to A0. */
2553 m68k_libcall_value_in_a0_p
= true;
2554 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2556 m68k_libcall_value_in_a0_p
= false;
2558 insns
= get_insns ();
2561 gcc_assert (can_create_pseudo_p ());
2562 dest
= gen_reg_rtx (Pmode
);
2563 emit_libcall_block (insns
, dest
, a0
, eqv
);
2568 /* The __tls_get_addr symbol. */
2569 static GTY(()) rtx m68k_read_tp
;
2571 /* Return SYMBOL_REF for __m68k_read_tp. */
2574 m68k_get_m68k_read_tp (void)
2576 if (m68k_read_tp
== NULL_RTX
)
2577 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2579 return m68k_read_tp
;
2582 /* Emit instruction sequence that calls __m68k_read_tp.
2583 A pseudo register with result of __m68k_read_tp call is returned. */
2586 m68k_call_m68k_read_tp (void)
2595 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2596 is the simpliest way of generating a call. The difference between
2597 __m68k_read_tp() and libcall is that the result is returned in D0
2598 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2599 which temporarily switches returning the result to A0. */
2601 /* Emit the call sequence. */
2602 m68k_libcall_value_in_a0_p
= true;
2603 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2605 m68k_libcall_value_in_a0_p
= false;
2606 insns
= get_insns ();
2609 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2610 share the m68k_read_tp result with other IE/LE model accesses. */
2611 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2613 gcc_assert (can_create_pseudo_p ());
2614 dest
= gen_reg_rtx (Pmode
);
2615 emit_libcall_block (insns
, dest
, a0
, eqv
);
2620 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2621 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2625 m68k_legitimize_tls_address (rtx orig
)
2627 switch (SYMBOL_REF_TLS_MODEL (orig
))
2629 case TLS_MODEL_GLOBAL_DYNAMIC
:
2630 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2633 case TLS_MODEL_LOCAL_DYNAMIC
:
2639 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2640 share the LDM result with other LD model accesses. */
2641 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2644 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2646 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2648 if (can_create_pseudo_p ())
2649 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2655 case TLS_MODEL_INITIAL_EXEC
:
2660 a0
= m68k_call_m68k_read_tp ();
2662 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2663 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2665 if (can_create_pseudo_p ())
2666 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2672 case TLS_MODEL_LOCAL_EXEC
:
2677 a0
= m68k_call_m68k_read_tp ();
2679 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2681 if (can_create_pseudo_p ())
2682 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2695 /* Return true if X is a TLS symbol. */
2698 m68k_tls_symbol_p (rtx x
)
2700 if (!TARGET_HAVE_TLS
)
2703 if (GET_CODE (x
) != SYMBOL_REF
)
2706 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2709 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2710 though illegitimate one.
2711 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2714 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2716 if (!TARGET_HAVE_TLS
)
2721 subrtx_var_iterator::array_type array
;
2722 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2726 /* Note: this is not the same as m68k_tls_symbol_p. */
2727 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2730 /* Don't recurse into legitimate TLS references. */
2731 if (m68k_tls_reference_p (x
, true))
2732 iter
.skip_subrtxes ();
2738 enum m68k_reloc reloc
= RELOC_GOT
;
2740 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2741 && TLS_RELOC_P (reloc
));
2747 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2749 /* Return the type of move that should be used for integer I. */
2752 m68k_const_method (HOST_WIDE_INT i
)
2759 /* The ColdFire doesn't have byte or word operations. */
2760 /* FIXME: This may not be useful for the m68060 either. */
2761 if (!TARGET_COLDFIRE
)
2763 /* if -256 < N < 256 but N is not in range for a moveq
2764 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2765 if (USE_MOVQ (i
^ 0xff))
2767 /* Likewise, try with not.w */
2768 if (USE_MOVQ (i
^ 0xffff))
2770 /* This is the only value where neg.w is useful */
2775 /* Try also with swap. */
2777 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2782 /* Try using MVZ/MVS with an immediate value to load constants. */
2783 if (i
>= 0 && i
<= 65535)
2785 if (i
>= -32768 && i
<= 32767)
2789 /* Otherwise, use move.l */
2793 /* Return the cost of moving constant I into a data register. */
2796 const_int_cost (HOST_WIDE_INT i
)
2798 switch (m68k_const_method (i
))
2801 /* Constants between -128 and 127 are cheap due to moveq. */
2809 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2819 m68k_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2820 int opno ATTRIBUTE_UNUSED
,
2821 int *total
, bool speed ATTRIBUTE_UNUSED
)
2823 int code
= GET_CODE (x
);
2828 /* Constant zero is super cheap due to clr instruction. */
2829 if (x
== const0_rtx
)
2832 *total
= const_int_cost (INTVAL (x
));
2842 /* Make 0.0 cheaper than other floating constants to
2843 encourage creating tstsf and tstdf insns. */
2844 if (outer_code
== COMPARE
2845 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2851 /* These are vaguely right for a 68020. */
2852 /* The costs for long multiply have been adjusted to work properly
2853 in synth_mult on the 68020, relative to an average of the time
2854 for add and the time for shift, taking away a little more because
2855 sometimes move insns are needed. */
2856 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2861 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2862 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2864 : TARGET_COLDFIRE ? 3 : 13)
2869 : TUNE_68000_10 ? 5 \
2870 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2871 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2873 : TARGET_COLDFIRE ? 2 : 8)
2876 (TARGET_CF_HWDIV ? 11 \
2877 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2880 /* An lea costs about three times as much as a simple add. */
2882 && GET_CODE (XEXP (x
, 1)) == REG
2883 && GET_CODE (XEXP (x
, 0)) == MULT
2884 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2885 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2886 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2887 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2888 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2890 /* lea an@(dx:l:i),am */
2891 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2901 *total
= COSTS_N_INSNS(1);
2906 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2908 if (INTVAL (XEXP (x
, 1)) < 16)
2909 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2911 /* We're using clrw + swap for these cases. */
2912 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2915 *total
= COSTS_N_INSNS (10); /* Worst case. */
2918 /* A shift by a big integer takes an extra instruction. */
2919 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2920 && (INTVAL (XEXP (x
, 1)) == 16))
2922 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2925 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2926 && !(INTVAL (XEXP (x
, 1)) > 0
2927 && INTVAL (XEXP (x
, 1)) <= 8))
2929 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2935 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2936 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2938 *total
= COSTS_N_INSNS (MULW_COST
);
2939 else if (mode
== QImode
|| mode
== HImode
)
2940 *total
= COSTS_N_INSNS (MULW_COST
);
2942 *total
= COSTS_N_INSNS (MULL_COST
);
2949 if (mode
== QImode
|| mode
== HImode
)
2950 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2951 else if (TARGET_CF_HWDIV
)
2952 *total
= COSTS_N_INSNS (18);
2954 *total
= COSTS_N_INSNS (43); /* div.l */
2958 if (outer_code
== COMPARE
)
2967 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2971 output_move_const_into_data_reg (rtx
*operands
)
2975 i
= INTVAL (operands
[1]);
2976 switch (m68k_const_method (i
))
2979 return "mvzw %1,%0";
2981 return "mvsw %1,%0";
2983 return "moveq %1,%0";
2986 operands
[1] = GEN_INT (i
^ 0xff);
2987 return "moveq %1,%0\n\tnot%.b %0";
2990 operands
[1] = GEN_INT (i
^ 0xffff);
2991 return "moveq %1,%0\n\tnot%.w %0";
2994 return "moveq #-128,%0\n\tneg%.w %0";
2999 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
3000 return "moveq %1,%0\n\tswap %0";
3003 return "move%.l %1,%0";
3009 /* Return true if I can be handled by ISA B's mov3q instruction. */
3012 valid_mov3q_const (HOST_WIDE_INT i
)
3014 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3017 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3018 I is the value of OPERANDS[1]. */
3021 output_move_simode_const (rtx
*operands
)
3027 src
= INTVAL (operands
[1]);
3029 && (DATA_REG_P (dest
) || MEM_P (dest
))
3030 /* clr insns on 68000 read before writing. */
3031 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3032 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3034 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3035 return "mov3q%.l %1,%0";
3036 else if (src
== 0 && ADDRESS_REG_P (dest
))
3037 return "sub%.l %0,%0";
3038 else if (DATA_REG_P (dest
))
3039 return output_move_const_into_data_reg (operands
);
3040 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3042 if (valid_mov3q_const (src
))
3043 return "mov3q%.l %1,%0";
3044 return "move%.w %1,%0";
3046 else if (MEM_P (dest
)
3047 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3048 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3049 && IN_RANGE (src
, -0x8000, 0x7fff))
3051 if (valid_mov3q_const (src
))
3052 return "mov3q%.l %1,%-";
3055 return "move%.l %1,%0";
3059 output_move_simode (rtx
*operands
)
3061 if (GET_CODE (operands
[1]) == CONST_INT
)
3062 return output_move_simode_const (operands
);
3063 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3064 || GET_CODE (operands
[1]) == CONST
)
3065 && push_operand (operands
[0], SImode
))
3067 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3068 || GET_CODE (operands
[1]) == CONST
)
3069 && ADDRESS_REG_P (operands
[0]))
3070 return "lea %a1,%0";
3071 return "move%.l %1,%0";
3075 output_move_himode (rtx
*operands
)
3077 if (GET_CODE (operands
[1]) == CONST_INT
)
3079 if (operands
[1] == const0_rtx
3080 && (DATA_REG_P (operands
[0])
3081 || GET_CODE (operands
[0]) == MEM
)
3082 /* clr insns on 68000 read before writing. */
3083 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3084 || !(GET_CODE (operands
[0]) == MEM
3085 && MEM_VOLATILE_P (operands
[0]))))
3087 else if (operands
[1] == const0_rtx
3088 && ADDRESS_REG_P (operands
[0]))
3089 return "sub%.l %0,%0";
3090 else if (DATA_REG_P (operands
[0])
3091 && INTVAL (operands
[1]) < 128
3092 && INTVAL (operands
[1]) >= -128)
3093 return "moveq %1,%0";
3094 else if (INTVAL (operands
[1]) < 0x8000
3095 && INTVAL (operands
[1]) >= -0x8000)
3096 return "move%.w %1,%0";
3098 else if (CONSTANT_P (operands
[1]))
3099 return "move%.l %1,%0";
3100 return "move%.w %1,%0";
3104 output_move_qimode (rtx
*operands
)
3106 /* 68k family always modifies the stack pointer by at least 2, even for
3107 byte pushes. The 5200 (ColdFire) does not do this. */
3109 /* This case is generated by pushqi1 pattern now. */
3110 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3111 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3112 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3113 && ! ADDRESS_REG_P (operands
[1])
3114 && ! TARGET_COLDFIRE
));
3116 /* clr and st insns on 68000 read before writing. */
3117 if (!ADDRESS_REG_P (operands
[0])
3118 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3119 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3121 if (operands
[1] == const0_rtx
)
3123 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3124 && GET_CODE (operands
[1]) == CONST_INT
3125 && (INTVAL (operands
[1]) & 255) == 255)
3131 if (GET_CODE (operands
[1]) == CONST_INT
3132 && DATA_REG_P (operands
[0])
3133 && INTVAL (operands
[1]) < 128
3134 && INTVAL (operands
[1]) >= -128)
3135 return "moveq %1,%0";
3136 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3137 return "sub%.l %0,%0";
3138 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3139 return "move%.l %1,%0";
3140 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3141 from address registers. */
3142 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3143 return "move%.w %1,%0";
3144 return "move%.b %1,%0";
3148 output_move_stricthi (rtx
*operands
)
3150 if (operands
[1] == const0_rtx
3151 /* clr insns on 68000 read before writing. */
3152 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3153 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3155 return "move%.w %1,%0";
3159 output_move_strictqi (rtx
*operands
)
3161 if (operands
[1] == const0_rtx
3162 /* clr insns on 68000 read before writing. */
3163 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3164 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3166 return "move%.b %1,%0";
3169 /* Return the best assembler insn template
3170 for moving operands[1] into operands[0] as a fullword. */
3173 singlemove_string (rtx
*operands
)
3175 if (GET_CODE (operands
[1]) == CONST_INT
)
3176 return output_move_simode_const (operands
);
3177 return "move%.l %1,%0";
3181 /* Output assembler or rtl code to perform a doubleword move insn
3182 with operands OPERANDS.
3183 Pointers to 3 helper functions should be specified:
3184 HANDLE_REG_ADJUST to adjust a register by a small value,
3185 HANDLE_COMPADR to compute an address and
3186 HANDLE_MOVSI to move 4 bytes. */
3189 handle_move_double (rtx operands
[2],
3190 void (*handle_reg_adjust
) (rtx
, int),
3191 void (*handle_compadr
) (rtx
[2]),
3192 void (*handle_movsi
) (rtx
[2]))
3196 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3201 rtx addreg0
= 0, addreg1
= 0;
3202 int dest_overlapped_low
= 0;
3203 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3208 /* First classify both operands. */
3210 if (REG_P (operands
[0]))
3212 else if (offsettable_memref_p (operands
[0]))
3214 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3216 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3218 else if (GET_CODE (operands
[0]) == MEM
)
3223 if (REG_P (operands
[1]))
3225 else if (CONSTANT_P (operands
[1]))
3227 else if (offsettable_memref_p (operands
[1]))
3229 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3231 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3233 else if (GET_CODE (operands
[1]) == MEM
)
3238 /* Check for the cases that the operand constraints are not supposed
3239 to allow to happen. Generating code for these cases is
3241 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3243 /* If one operand is decrementing and one is incrementing
3244 decrement the former register explicitly
3245 and change that operand into ordinary indexing. */
3247 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3249 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3251 handle_reg_adjust (operands
[0], -size
);
3253 if (GET_MODE (operands
[1]) == XFmode
)
3254 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3255 else if (GET_MODE (operands
[0]) == DFmode
)
3256 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3258 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3261 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3263 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3265 handle_reg_adjust (operands
[1], -size
);
3267 if (GET_MODE (operands
[1]) == XFmode
)
3268 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3269 else if (GET_MODE (operands
[1]) == DFmode
)
3270 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3272 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3276 /* If an operand is an unoffsettable memory ref, find a register
3277 we can increment temporarily to make it refer to the second word. */
3279 if (optype0
== MEMOP
)
3280 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3282 if (optype1
== MEMOP
)
3283 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3285 /* Ok, we can do one word at a time.
3286 Normally we do the low-numbered word first,
3287 but if either operand is autodecrementing then we
3288 do the high-numbered word first.
3290 In either case, set up in LATEHALF the operands to use
3291 for the high-numbered word and in some cases alter the
3292 operands in OPERANDS to be suitable for the low-numbered word. */
3296 if (optype0
== REGOP
)
3298 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3299 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3301 else if (optype0
== OFFSOP
)
3303 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3304 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3308 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3309 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3312 if (optype1
== REGOP
)
3314 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3315 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3317 else if (optype1
== OFFSOP
)
3319 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3320 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3322 else if (optype1
== CNSTOP
)
3324 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3328 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3329 (*CONST_DOUBLE_REAL_VALUE (operands
[1]), l
);
3330 operands
[1] = GEN_INT (l
[0]);
3331 middlehalf
[1] = GEN_INT (l
[1]);
3332 latehalf
[1] = GEN_INT (l
[2]);
3336 /* No non-CONST_DOUBLE constant should ever appear
3338 gcc_assert (!CONSTANT_P (operands
[1]));
3343 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3344 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3348 /* size is not 12: */
3350 if (optype0
== REGOP
)
3351 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3352 else if (optype0
== OFFSOP
)
3353 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3355 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3357 if (optype1
== REGOP
)
3358 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3359 else if (optype1
== OFFSOP
)
3360 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3361 else if (optype1
== CNSTOP
)
3362 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3364 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3367 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3368 word first. We should use the adjusted operand 1 (which is N+4(REG))
3369 for the low word as well, to compensate for the first decrement of
3371 if (optype0
== PUSHOP
3372 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3373 operands
[1] = middlehalf
[1] = latehalf
[1];
3375 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3376 if the upper part of reg N does not appear in the MEM, arrange to
3377 emit the move late-half first. Otherwise, compute the MEM address
3378 into the upper part of N and use that as a pointer to the memory
3380 if (optype0
== REGOP
3381 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3383 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3385 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3386 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3388 /* If both halves of dest are used in the src memory address,
3389 compute the address into latehalf of dest.
3390 Note that this can't happen if the dest is two data regs. */
3392 xops
[0] = latehalf
[0];
3393 xops
[1] = XEXP (operands
[1], 0);
3395 handle_compadr (xops
);
3396 if (GET_MODE (operands
[1]) == XFmode
)
3398 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3399 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3400 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3404 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3405 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3409 && reg_overlap_mentioned_p (middlehalf
[0],
3410 XEXP (operands
[1], 0)))
3412 /* Check for two regs used by both source and dest.
3413 Note that this can't happen if the dest is all data regs.
3414 It can happen if the dest is d6, d7, a0.
3415 But in that case, latehalf is an addr reg, so
3416 the code at compadr does ok. */
3418 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3419 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3422 /* JRV says this can't happen: */
3423 gcc_assert (!addreg0
&& !addreg1
);
3425 /* Only the middle reg conflicts; simply put it last. */
3426 handle_movsi (operands
);
3427 handle_movsi (latehalf
);
3428 handle_movsi (middlehalf
);
3432 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3433 /* If the low half of dest is mentioned in the source memory
3434 address, the arrange to emit the move late half first. */
3435 dest_overlapped_low
= 1;
3438 /* If one or both operands autodecrementing,
3439 do the two words, high-numbered first. */
3441 /* Likewise, the first move would clobber the source of the second one,
3442 do them in the other order. This happens only for registers;
3443 such overlap can't happen in memory unless the user explicitly
3444 sets it up, and that is an undefined circumstance. */
3446 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3447 || (optype0
== REGOP
&& optype1
== REGOP
3448 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3449 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3450 || dest_overlapped_low
)
3452 /* Make any unoffsettable addresses point at high-numbered word. */
3454 handle_reg_adjust (addreg0
, size
- 4);
3456 handle_reg_adjust (addreg1
, size
- 4);
3459 handle_movsi (latehalf
);
3461 /* Undo the adds we just did. */
3463 handle_reg_adjust (addreg0
, -4);
3465 handle_reg_adjust (addreg1
, -4);
3469 handle_movsi (middlehalf
);
3472 handle_reg_adjust (addreg0
, -4);
3474 handle_reg_adjust (addreg1
, -4);
3477 /* Do low-numbered word. */
3479 handle_movsi (operands
);
3483 /* Normal case: do the two words, low-numbered first. */
3485 handle_movsi (operands
);
3487 /* Do the middle one of the three words for long double */
3491 handle_reg_adjust (addreg0
, 4);
3493 handle_reg_adjust (addreg1
, 4);
3495 handle_movsi (middlehalf
);
3498 /* Make any unoffsettable addresses point at high-numbered word. */
3500 handle_reg_adjust (addreg0
, 4);
3502 handle_reg_adjust (addreg1
, 4);
3505 handle_movsi (latehalf
);
3507 /* Undo the adds we just did. */
3509 handle_reg_adjust (addreg0
, -(size
- 4));
3511 handle_reg_adjust (addreg1
, -(size
- 4));
3516 /* Output assembler code to adjust REG by N. */
3518 output_reg_adjust (rtx reg
, int n
)
3522 gcc_assert (GET_MODE (reg
) == SImode
&& n
>= -12 && n
!= 0 && n
<= 12);
3527 s
= "add%.l #12,%0";
3531 s
= "addq%.l #8,%0";
3535 s
= "addq%.l #4,%0";
3539 s
= "sub%.l #12,%0";
3543 s
= "subq%.l #8,%0";
3547 s
= "subq%.l #4,%0";
3555 output_asm_insn (s
, ®
);
3558 /* Emit rtl code to adjust REG by N. */
3560 emit_reg_adjust (rtx reg1
, int n
)
3564 gcc_assert (GET_MODE (reg1
) == SImode
&& n
>= -12 && n
!= 0 && n
<= 12);
3566 reg1
= copy_rtx (reg1
);
3567 reg2
= copy_rtx (reg1
);
3570 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3572 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3577 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3579 output_compadr (rtx operands
[2])
3581 output_asm_insn ("lea %a1,%0", operands
);
3584 /* Output the best assembler insn for moving operands[1] into operands[0]
3587 output_movsi (rtx operands
[2])
3589 output_asm_insn (singlemove_string (operands
), operands
);
3592 /* Copy OP and change its mode to MODE. */
3594 copy_operand (rtx op
, machine_mode mode
)
3596 /* ??? This looks really ugly. There must be a better way
3597 to change a mode on the operand. */
3598 if (GET_MODE (op
) != VOIDmode
)
3601 op
= gen_rtx_REG (mode
, REGNO (op
));
3605 PUT_MODE (op
, mode
);
3612 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3614 emit_movsi (rtx operands
[2])
3616 operands
[0] = copy_operand (operands
[0], SImode
);
3617 operands
[1] = copy_operand (operands
[1], SImode
);
3619 emit_insn (gen_movsi (operands
[0], operands
[1]));
3622 /* Output assembler code to perform a doubleword move insn
3623 with operands OPERANDS. */
3625 output_move_double (rtx
*operands
)
3627 handle_move_double (operands
,
3628 output_reg_adjust
, output_compadr
, output_movsi
);
3633 /* Output rtl code to perform a doubleword move insn
3634 with operands OPERANDS. */
3636 m68k_emit_move_double (rtx operands
[2])
3638 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3641 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3642 new rtx with the correct mode. */
3645 force_mode (machine_mode mode
, rtx orig
)
3647 if (mode
== GET_MODE (orig
))
3650 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3653 return gen_rtx_REG (mode
, REGNO (orig
));
3657 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3659 return reg_renumber
&& FP_REG_P (op
);
3662 /* Emit insns to move operands[1] into operands[0].
3664 Return 1 if we have written out everything that needs to be done to
3665 do the move. Otherwise, return 0 and the caller will emit the move
3668 Note SCRATCH_REG may not be in the proper mode depending on how it
3669 will be used. This routine is responsible for creating a new copy
3670 of SCRATCH_REG in the proper mode. */
3673 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3675 register rtx operand0
= operands
[0];
3676 register rtx operand1
= operands
[1];
3680 && reload_in_progress
&& GET_CODE (operand0
) == REG
3681 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3682 operand0
= reg_equiv_mem (REGNO (operand0
));
3683 else if (scratch_reg
3684 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3685 && GET_CODE (SUBREG_REG (operand0
)) == REG
3686 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3688 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3689 the code which tracks sets/uses for delete_output_reload. */
3690 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3691 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3692 SUBREG_BYTE (operand0
));
3693 operand0
= alter_subreg (&temp
, true);
3697 && reload_in_progress
&& GET_CODE (operand1
) == REG
3698 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3699 operand1
= reg_equiv_mem (REGNO (operand1
));
3700 else if (scratch_reg
3701 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3702 && GET_CODE (SUBREG_REG (operand1
)) == REG
3703 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3705 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3706 the code which tracks sets/uses for delete_output_reload. */
3707 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3708 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3709 SUBREG_BYTE (operand1
));
3710 operand1
= alter_subreg (&temp
, true);
3713 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3714 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3715 != XEXP (operand0
, 0)))
3716 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3717 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3718 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3719 != XEXP (operand1
, 0)))
3720 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3722 /* Handle secondary reloads for loads/stores of FP registers where
3723 the address is symbolic by using the scratch register */
3724 if (fp_reg_operand (operand0
, mode
)
3725 && ((GET_CODE (operand1
) == MEM
3726 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3727 || ((GET_CODE (operand1
) == SUBREG
3728 && GET_CODE (XEXP (operand1
, 0)) == MEM
3729 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3732 if (GET_CODE (operand1
) == SUBREG
)
3733 operand1
= XEXP (operand1
, 0);
3735 /* SCRATCH_REG will hold an address. We want
3736 it in SImode regardless of what mode it was originally given
3738 scratch_reg
= force_mode (SImode
, scratch_reg
);
3740 /* D might not fit in 14 bits either; for such cases load D into
3742 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3744 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3745 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3747 XEXP (XEXP (operand1
, 0), 0),
3751 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3752 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3755 else if (fp_reg_operand (operand1
, mode
)
3756 && ((GET_CODE (operand0
) == MEM
3757 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3758 || ((GET_CODE (operand0
) == SUBREG
)
3759 && GET_CODE (XEXP (operand0
, 0)) == MEM
3760 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3763 if (GET_CODE (operand0
) == SUBREG
)
3764 operand0
= XEXP (operand0
, 0);
3766 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3767 it in SIMODE regardless of what mode it was originally given
3769 scratch_reg
= force_mode (SImode
, scratch_reg
);
3771 /* D might not fit in 14 bits either; for such cases load D into
3773 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3775 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3776 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3779 XEXP (XEXP (operand0
, 0),
3784 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3785 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3788 /* Handle secondary reloads for loads of FP registers from constant
3789 expressions by forcing the constant into memory.
3791 use scratch_reg to hold the address of the memory location.
3793 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3794 NO_REGS when presented with a const_int and an register class
3795 containing only FP registers. Doing so unfortunately creates
3796 more problems than it solves. Fix this for 2.5. */
3797 else if (fp_reg_operand (operand0
, mode
)
3798 && CONSTANT_P (operand1
)
3803 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3804 it in SIMODE regardless of what mode it was originally given
3806 scratch_reg
= force_mode (SImode
, scratch_reg
);
3808 /* Force the constant into memory and put the address of the
3809 memory location into scratch_reg. */
3810 xoperands
[0] = scratch_reg
;
3811 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3812 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3814 /* Now load the destination register. */
3815 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3819 /* Now have insn-emit do whatever it normally does. */
3823 /* Split one or more DImode RTL references into pairs of SImode
3824 references. The RTL can be REG, offsettable MEM, integer constant, or
3825 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3826 split and "num" is its length. lo_half and hi_half are output arrays
3827 that parallel "operands". */
3830 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3834 rtx op
= operands
[num
];
3836 /* simplify_subreg refuses to split volatile memory addresses,
3837 but we still have to handle it. */
3838 if (GET_CODE (op
) == MEM
)
3840 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3841 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3845 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3846 GET_MODE (op
) == VOIDmode
3847 ? DImode
: GET_MODE (op
), 4);
3848 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3849 GET_MODE (op
) == VOIDmode
3850 ? DImode
: GET_MODE (op
), 0);
3855 /* Split X into a base and a constant offset, storing them in *BASE
3856 and *OFFSET respectively. */
3859 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3862 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3864 *offset
+= INTVAL (XEXP (x
, 1));
3870 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3871 instruction. STORE_P says whether the move is a load or store.
3873 If the instruction uses post-increment or pre-decrement addressing,
3874 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3875 adjustment. This adjustment will be made by the first element of
3876 PARALLEL, with the loads or stores starting at element 1. If the
3877 instruction does not use post-increment or pre-decrement addressing,
3878 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3879 start at element 0. */
3882 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3883 HOST_WIDE_INT automod_offset
, bool store_p
)
3885 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3886 HOST_WIDE_INT offset
, mem_offset
;
3888 enum reg_class rclass
;
3890 len
= XVECLEN (pattern
, 0);
3891 first
= (automod_base
!= NULL
);
3895 /* Stores must be pre-decrement and loads must be post-increment. */
3896 if (store_p
!= (automod_offset
< 0))
3899 /* Work out the base and offset for lowest memory location. */
3900 base
= automod_base
;
3901 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3905 /* Allow any valid base and offset in the first access. */
3912 for (i
= first
; i
< len
; i
++)
3914 /* We need a plain SET. */
3915 set
= XVECEXP (pattern
, 0, i
);
3916 if (GET_CODE (set
) != SET
)
3919 /* Check that we have a memory location... */
3920 mem
= XEXP (set
, !store_p
);
3921 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3924 /* ...with the right address. */
3927 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3928 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3929 There are no mode restrictions for 680x0 besides the
3930 automodification rules enforced above. */
3932 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3937 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3938 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3942 /* Check that we have a register of the required mode and class. */
3943 reg
= XEXP (set
, store_p
);
3945 || !HARD_REGISTER_P (reg
)
3946 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3951 /* The register must belong to RCLASS and have a higher number
3952 than the register in the previous SET. */
3953 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3954 || REGNO (last_reg
) >= REGNO (reg
))
3959 /* Work out which register class we need. */
3960 if (INT_REGNO_P (REGNO (reg
)))
3961 rclass
= GENERAL_REGS
;
3962 else if (FP_REGNO_P (REGNO (reg
)))
3969 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3972 /* If we have an automodification, check whether the final offset is OK. */
3973 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3976 /* Reject unprofitable cases. */
3977 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3983 /* Return the assembly code template for a movem or fmovem instruction
3984 whose pattern is given by PATTERN. Store the template's operands
3987 If the instruction uses post-increment or pre-decrement addressing,
3988 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3989 is true if this is a store instruction. */
3992 m68k_output_movem (rtx
*operands
, rtx pattern
,
3993 HOST_WIDE_INT automod_offset
, bool store_p
)
3998 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
4000 first
= (automod_offset
!= 0);
4001 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
4003 /* When using movem with pre-decrement addressing, register X + D0_REG
4004 is controlled by bit 15 - X. For all other addressing modes,
4005 register X + D0_REG is controlled by bit X. Confusingly, the
4006 register mask for fmovem is in the opposite order to that for
4010 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4011 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4012 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4013 if (automod_offset
< 0)
4015 if (FP_REGNO_P (regno
))
4016 mask
|= 1 << (regno
- FP0_REG
);
4018 mask
|= 1 << (15 - (regno
- D0_REG
));
4022 if (FP_REGNO_P (regno
))
4023 mask
|= 1 << (7 - (regno
- FP0_REG
));
4025 mask
|= 1 << (regno
- D0_REG
);
4030 if (automod_offset
== 0)
4031 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4032 else if (automod_offset
< 0)
4033 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4035 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4036 operands
[1] = GEN_INT (mask
);
4037 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4040 return "fmovem %1,%a0";
4042 return "fmovem %a0,%1";
4047 return "movem%.l %1,%a0";
4049 return "movem%.l %a0,%1";
4053 /* Return a REG that occurs in ADDR with coefficient 1.
4054 ADDR can be effectively incremented by incrementing REG. */
4057 find_addr_reg (rtx addr
)
4059 while (GET_CODE (addr
) == PLUS
)
4061 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4062 addr
= XEXP (addr
, 0);
4063 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4064 addr
= XEXP (addr
, 1);
4065 else if (CONSTANT_P (XEXP (addr
, 0)))
4066 addr
= XEXP (addr
, 1);
4067 else if (CONSTANT_P (XEXP (addr
, 1)))
4068 addr
= XEXP (addr
, 0);
4072 gcc_assert (GET_CODE (addr
) == REG
);
4076 /* Output assembler code to perform a 32-bit 3-operand add. */
4079 output_addsi3 (rtx
*operands
)
4081 if (! operands_match_p (operands
[0], operands
[1]))
4083 if (!ADDRESS_REG_P (operands
[1]))
4085 rtx tmp
= operands
[1];
4087 operands
[1] = operands
[2];
4091 /* These insns can result from reloads to access
4092 stack slots over 64k from the frame pointer. */
4093 if (GET_CODE (operands
[2]) == CONST_INT
4094 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4095 return "move%.l %2,%0\n\tadd%.l %1,%0";
4096 if (GET_CODE (operands
[2]) == REG
)
4097 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4098 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4100 if (GET_CODE (operands
[2]) == CONST_INT
)
4102 if (INTVAL (operands
[2]) > 0
4103 && INTVAL (operands
[2]) <= 8)
4104 return "addq%.l %2,%0";
4105 if (INTVAL (operands
[2]) < 0
4106 && INTVAL (operands
[2]) >= -8)
4108 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4109 return "subq%.l %2,%0";
4111 /* On the CPU32 it is faster to use two addql instructions to
4112 add a small integer (8 < N <= 16) to a register.
4113 Likewise for subql. */
4114 if (TUNE_CPU32
&& REG_P (operands
[0]))
4116 if (INTVAL (operands
[2]) > 8
4117 && INTVAL (operands
[2]) <= 16)
4119 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4120 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4122 if (INTVAL (operands
[2]) < -8
4123 && INTVAL (operands
[2]) >= -16)
4125 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4126 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4129 if (ADDRESS_REG_P (operands
[0])
4130 && INTVAL (operands
[2]) >= -0x8000
4131 && INTVAL (operands
[2]) < 0x8000)
4134 return "add%.w %2,%0";
4136 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4139 return "add%.l %2,%0";
4142 /* Store in cc_status the expressions that the condition codes will
4143 describe after execution of an instruction whose pattern is EXP.
4144 Do not alter them if the instruction would not alter the cc's. */
4146 /* On the 68000, all the insns to store in an address register fail to
4147 set the cc's. However, in some cases these instructions can make it
4148 possibly invalid to use the saved cc's. In those cases we clear out
4149 some or all of the saved cc's so they won't be used. */
4152 notice_update_cc (rtx exp
, rtx insn
)
4154 if (GET_CODE (exp
) == SET
)
4156 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4158 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4160 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4161 cc_status
.value1
= 0;
4162 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4163 cc_status
.value2
= 0;
4165 /* fmoves to memory or data registers do not set the condition
4166 codes. Normal moves _do_ set the condition codes, but not in
4167 a way that is appropriate for comparison with 0, because -0.0
4168 would be treated as a negative nonzero number. Note that it
4169 isn't appropriate to conditionalize this restriction on
4170 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4171 we care about the difference between -0.0 and +0.0. */
4172 else if (!FP_REG_P (SET_DEST (exp
))
4173 && SET_DEST (exp
) != cc0_rtx
4174 && (FP_REG_P (SET_SRC (exp
))
4175 || GET_CODE (SET_SRC (exp
)) == FIX
4176 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4178 /* A pair of move insns doesn't produce a useful overall cc. */
4179 else if (!FP_REG_P (SET_DEST (exp
))
4180 && !FP_REG_P (SET_SRC (exp
))
4181 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4182 && (GET_CODE (SET_SRC (exp
)) == REG
4183 || GET_CODE (SET_SRC (exp
)) == MEM
4184 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4186 else if (SET_DEST (exp
) != pc_rtx
)
4188 cc_status
.flags
= 0;
4189 cc_status
.value1
= SET_DEST (exp
);
4190 cc_status
.value2
= SET_SRC (exp
);
4193 else if (GET_CODE (exp
) == PARALLEL
4194 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4196 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4197 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4199 if (ADDRESS_REG_P (dest
))
4201 else if (dest
!= pc_rtx
)
4203 cc_status
.flags
= 0;
4204 cc_status
.value1
= dest
;
4205 cc_status
.value2
= src
;
4210 if (cc_status
.value2
!= 0
4211 && ADDRESS_REG_P (cc_status
.value2
)
4212 && GET_MODE (cc_status
.value2
) == QImode
)
4214 if (cc_status
.value2
!= 0)
4215 switch (GET_CODE (cc_status
.value2
))
4217 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4218 case ROTATE
: case ROTATERT
:
4219 /* These instructions always clear the overflow bit, and set
4220 the carry to the bit shifted out. */
4221 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4224 case PLUS
: case MINUS
: case MULT
:
4225 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4226 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4227 cc_status
.flags
|= CC_NO_OVERFLOW
;
4230 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4231 ends with a move insn moving r2 in r2's mode.
4232 Thus, the cc's are set for r2.
4233 This can set N bit spuriously. */
4234 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4239 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4241 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4242 cc_status
.value2
= 0;
4243 /* Check for PRE_DEC in dest modifying a register used in src. */
4244 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4245 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4247 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4249 cc_status
.value2
= 0;
4250 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4251 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4252 cc_status
.flags
= CC_IN_68881
;
4253 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4254 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4256 cc_status
.flags
= CC_IN_68881
;
4257 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4258 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4259 cc_status
.flags
|= CC_REVERSED
;
4264 output_move_const_double (rtx
*operands
)
4266 int code
= standard_68881_constant_p (operands
[1]);
4270 static char buf
[40];
4272 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4275 return "fmove%.d %1,%0";
4279 output_move_const_single (rtx
*operands
)
4281 int code
= standard_68881_constant_p (operands
[1]);
4285 static char buf
[40];
4287 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4290 return "fmove%.s %f1,%0";
4293 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4294 from the "fmovecr" instruction.
4295 The value, anded with 0xff, gives the code to use in fmovecr
4296 to get the desired constant. */
4298 /* This code has been fixed for cross-compilation. */
4300 static int inited_68881_table
= 0;
4302 static const char *const strings_68881
[7] = {
4312 static const int codes_68881
[7] = {
4322 REAL_VALUE_TYPE values_68881
[7];
4324 /* Set up values_68881 array by converting the decimal values
4325 strings_68881 to binary. */
4328 init_68881_table (void)
4335 for (i
= 0; i
< 7; i
++)
4339 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4340 values_68881
[i
] = r
;
4342 inited_68881_table
= 1;
4346 standard_68881_constant_p (rtx x
)
4348 const REAL_VALUE_TYPE
*r
;
4351 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4352 used at all on those chips. */
4356 if (! inited_68881_table
)
4357 init_68881_table ();
4359 r
= CONST_DOUBLE_REAL_VALUE (x
);
4361 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4362 for (i
= 0; i
< 6; i
++)
4364 if (real_identical (r
, &values_68881
[i
]))
4365 return (codes_68881
[i
]);
4368 if (GET_MODE (x
) == SFmode
)
4371 if (real_equal (r
, &values_68881
[6]))
4372 return (codes_68881
[6]);
4374 /* larger powers of ten in the constants ram are not used
4375 because they are not equal to a `double' C constant. */
4379 /* If X is a floating-point constant, return the logarithm of X base 2,
4380 or 0 if X is not a power of 2. */
4383 floating_exact_log2 (rtx x
)
4385 const REAL_VALUE_TYPE
*r
;
4389 r
= CONST_DOUBLE_REAL_VALUE (x
);
4391 if (real_less (r
, &dconst1
))
4394 exp
= real_exponent (r
);
4395 real_2expN (&r1
, exp
, DFmode
);
4396 if (real_equal (&r1
, r
))
4402 /* A C compound statement to output to stdio stream STREAM the
4403 assembler syntax for an instruction operand X. X is an RTL
4406 CODE is a value that can be used to specify one of several ways
4407 of printing the operand. It is used when identical operands
4408 must be printed differently depending on the context. CODE
4409 comes from the `%' specification that was used to request
4410 printing of the operand. If the specification was just `%DIGIT'
4411 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4412 is the ASCII code for LTR.
4414 If X is a register, this macro should print the register's name.
4415 The names can be found in an array `reg_names' whose type is
4416 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4418 When the machine description has a specification `%PUNCT' (a `%'
4419 followed by a punctuation character), this macro is called with
4420 a null pointer for X and the punctuation character for CODE.
4422 The m68k specific codes are:
4424 '.' for dot needed in Motorola-style opcode names.
4425 '-' for an operand pushing on the stack:
4426 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4427 '+' for an operand pushing on the stack:
4428 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4429 '@' for a reference to the top word on the stack:
4430 sp@, (sp) or (%sp) depending on the style of syntax.
4431 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4432 but & in SGS syntax).
4433 '!' for the cc register (used in an `and to cc' insn).
4434 '$' for the letter `s' in an op code, but only on the 68040.
4435 '&' for the letter `d' in an op code, but only on the 68040.
4436 '/' for register prefix needed by longlong.h.
4437 '?' for m68k_library_id_string
4439 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4440 'd' to force memory addressing to be absolute, not relative.
4441 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4442 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4443 or print pair of registers as rx:ry.
4444 'p' print an address with @PLTPC attached, but only if the operand
4445 is not locally-bound. */
4448 print_operand (FILE *file
, rtx op
, int letter
)
4451 m68k_adjust_decorated_operand (op
);
4456 fprintf (file
, ".");
4458 else if (letter
== '#')
4459 asm_fprintf (file
, "%I");
4460 else if (letter
== '-')
4461 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4462 else if (letter
== '+')
4463 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4464 else if (letter
== '@')
4465 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4466 else if (letter
== '!')
4467 asm_fprintf (file
, "%Rfpcr");
4468 else if (letter
== '$')
4471 fprintf (file
, "s");
4473 else if (letter
== '&')
4476 fprintf (file
, "d");
4478 else if (letter
== '/')
4479 asm_fprintf (file
, "%R");
4480 else if (letter
== '?')
4481 asm_fprintf (file
, m68k_library_id_string
);
4482 else if (letter
== 'p')
4484 output_addr_const (file
, op
);
4485 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4486 fprintf (file
, "@PLTPC");
4488 else if (GET_CODE (op
) == REG
)
4491 /* Print out the second register name of a register pair.
4492 I.e., R (6) => 7. */
4493 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4495 fputs (M68K_REGNAME(REGNO (op
)), file
);
4497 else if (GET_CODE (op
) == MEM
)
4499 output_address (GET_MODE (op
), XEXP (op
, 0));
4500 if (letter
== 'd' && ! TARGET_68020
4501 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4502 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4503 && INTVAL (XEXP (op
, 0)) < 0x8000
4504 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4505 fprintf (file
, MOTOROLA
? ".l" : ":l");
4507 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4510 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4511 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4513 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4516 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4517 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4518 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4520 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4523 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4524 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4528 /* Use `print_operand_address' instead of `output_addr_const'
4529 to ensure that we print relevant PIC stuff. */
4530 asm_fprintf (file
, "%I");
4532 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4533 print_operand_address (file
, op
);
4535 output_addr_const (file
, op
);
4539 /* Return string for TLS relocation RELOC. */
4542 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4544 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4545 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4552 if (flag_pic
== 1 && TARGET_68020
)
4594 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4597 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4599 if (GET_CODE (x
) == UNSPEC
)
4601 switch (XINT (x
, 1))
4603 case UNSPEC_RELOC16
:
4604 case UNSPEC_RELOC32
:
4605 output_addr_const (file
, XVECEXP (x
, 0, 0));
4606 fputs (m68k_get_reloc_decoration
4607 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4618 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4621 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4623 gcc_assert (size
== 4);
4624 fputs ("\t.long\t", file
);
4625 output_addr_const (file
, x
);
4626 fputs ("@TLSLDO+0x8000", file
);
4629 /* In the name of slightly smaller debug output, and to cater to
4630 general assembler lossage, recognize various UNSPEC sequences
4631 and turn them back into a direct symbol reference. */
4634 m68k_delegitimize_address (rtx orig_x
)
4637 struct m68k_address addr
;
4640 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4645 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4648 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4649 || addr
.offset
== NULL_RTX
4650 || GET_CODE (addr
.offset
) != CONST
)
4653 unspec
= XEXP (addr
.offset
, 0);
4654 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4655 unspec
= XEXP (unspec
, 0);
4656 if (GET_CODE (unspec
) != UNSPEC
4657 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4658 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4660 x
= XVECEXP (unspec
, 0, 0);
4661 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4662 if (unspec
!= XEXP (addr
.offset
, 0))
4663 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4666 rtx idx
= addr
.index
;
4667 if (addr
.scale
!= 1)
4668 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4669 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4672 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4674 x
= replace_equiv_address_nv (orig_x
, x
);
4679 /* A C compound statement to output to stdio stream STREAM the
4680 assembler syntax for an instruction operand that is a memory
4681 reference whose address is ADDR. ADDR is an RTL expression.
4683 Note that this contains a kludge that knows that the only reason
4684 we have an address (plus (label_ref...) (reg...)) when not generating
4685 PIC code is in the insn before a tablejump, and we know that m68k.md
4686 generates a label LInnn: on such an insn.
4688 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4689 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4691 This routine is responsible for distinguishing between -fpic and -fPIC
4692 style relocations in an address. When generating -fpic code the
4693 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4694 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4697 print_operand_address (FILE *file
, rtx addr
)
4699 struct m68k_address address
;
4701 m68k_adjust_decorated_operand (addr
);
4703 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4706 if (address
.code
== PRE_DEC
)
4707 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4708 M68K_REGNAME (REGNO (address
.base
)));
4709 else if (address
.code
== POST_INC
)
4710 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4711 M68K_REGNAME (REGNO (address
.base
)));
4712 else if (!address
.base
&& !address
.index
)
4714 /* A constant address. */
4715 gcc_assert (address
.offset
== addr
);
4716 if (GET_CODE (addr
) == CONST_INT
)
4718 /* (xxx).w or (xxx).l. */
4719 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4720 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4722 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4724 else if (TARGET_PCREL
)
4726 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4728 output_addr_const (file
, addr
);
4729 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4733 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4734 name ends in `.<letter>', as the last 2 characters can be
4735 mistaken as a size suffix. Put the name in parentheses. */
4736 if (GET_CODE (addr
) == SYMBOL_REF
4737 && strlen (XSTR (addr
, 0)) > 2
4738 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4741 output_addr_const (file
, addr
);
4745 output_addr_const (file
, addr
);
4752 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4753 label being accessed, otherwise it is -1. */
4754 labelno
= (address
.offset
4756 && GET_CODE (address
.offset
) == LABEL_REF
4757 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4761 /* Print the "offset(base" component. */
4763 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4767 output_addr_const (file
, address
.offset
);
4771 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4773 /* Print the ",index" component, if any. */
4778 fprintf (file
, "%s.%c",
4779 M68K_REGNAME (REGNO (address
.index
)),
4780 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4781 if (address
.scale
!= 1)
4782 fprintf (file
, "*%d", address
.scale
);
4786 else /* !MOTOROLA */
4788 if (!address
.offset
&& !address
.index
)
4789 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4792 /* Print the "base@(offset" component. */
4794 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4798 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4799 fprintf (file
, "@(");
4801 output_addr_const (file
, address
.offset
);
4803 /* Print the ",index" component, if any. */
4806 fprintf (file
, ",%s:%c",
4807 M68K_REGNAME (REGNO (address
.index
)),
4808 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4809 if (address
.scale
!= 1)
4810 fprintf (file
, ":%d", address
.scale
);
4818 /* Check for cases where a clr insns can be omitted from code using
4819 strict_low_part sets. For example, the second clrl here is not needed:
4820 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4822 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4823 insn we are checking for redundancy. TARGET is the register set by the
4827 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4830 rtx_insn
*p
= first_insn
;
4832 while ((p
= PREV_INSN (p
)))
4834 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4840 /* If it isn't an insn, then give up. */
4844 if (reg_set_p (target
, p
))
4846 rtx set
= single_set (p
);
4849 /* If it isn't an easy to recognize insn, then give up. */
4853 dest
= SET_DEST (set
);
4855 /* If this sets the entire target register to zero, then our
4856 first_insn is redundant. */
4857 if (rtx_equal_p (dest
, target
)
4858 && SET_SRC (set
) == const0_rtx
)
4860 else if (GET_CODE (dest
) == STRICT_LOW_PART
4861 && GET_CODE (XEXP (dest
, 0)) == REG
4862 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4863 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4864 <= GET_MODE_SIZE (mode
)))
4865 /* This is a strict low part set which modifies less than
4866 we are using, so it is safe. */
4876 /* Operand predicates for implementing asymmetric pc-relative addressing
4877 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4878 when used as a source operand, but not as a destination operand.
4880 We model this by restricting the meaning of the basic predicates
4881 (general_operand, memory_operand, etc) to forbid the use of this
4882 addressing mode, and then define the following predicates that permit
4883 this addressing mode. These predicates can then be used for the
4884 source operands of the appropriate instructions.
4886 n.b. While it is theoretically possible to change all machine patterns
4887 to use this addressing more where permitted by the architecture,
4888 it has only been implemented for "common" cases: SImode, HImode, and
4889 QImode operands, and only for the principle operations that would
4890 require this addressing mode: data movement and simple integer operations.
4892 In parallel with these new predicates, two new constraint letters
4893 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4894 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4895 In the pcrel case 's' is only valid in combination with 'a' registers.
4896 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4897 of how these constraints are used.
4899 The use of these predicates is strictly optional, though patterns that
4900 don't will cause an extra reload register to be allocated where one
4903 lea (abc:w,%pc),%a0 ; need to reload address
4904 moveq &1,%d1 ; since write to pc-relative space
4905 movel %d1,%a0@ ; is not allowed
4907 lea (abc:w,%pc),%a1 ; no need to reload address here
4908 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4910 For more info, consult tiemann@cygnus.com.
4913 All of the ugliness with predicates and constraints is due to the
4914 simple fact that the m68k does not allow a pc-relative addressing
4915 mode as a destination. gcc does not distinguish between source and
4916 destination addresses. Hence, if we claim that pc-relative address
4917 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4918 end up with invalid code. To get around this problem, we left
4919 pc-relative modes as invalid addresses, and then added special
4920 predicates and constraints to accept them.
4922 A cleaner way to handle this is to modify gcc to distinguish
4923 between source and destination addresses. We can then say that
4924 pc-relative is a valid source address but not a valid destination
4925 address, and hopefully avoid a lot of the predicate and constraint
4926 hackery. Unfortunately, this would be a pretty big change. It would
4927 be a useful change for a number of ports, but there aren't any current
4928 plans to undertake this.
4930 ***************************************************************************/
4934 output_andsi3 (rtx
*operands
)
4937 if (GET_CODE (operands
[2]) == CONST_INT
4938 && (INTVAL (operands
[2]) | 0xffff) == -1
4939 && (DATA_REG_P (operands
[0])
4940 || offsettable_memref_p (operands
[0]))
4941 && !TARGET_COLDFIRE
)
4943 if (GET_CODE (operands
[0]) != REG
)
4944 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4945 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4946 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4948 if (operands
[2] == const0_rtx
)
4950 return "and%.w %2,%0";
4952 if (GET_CODE (operands
[2]) == CONST_INT
4953 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4954 && (DATA_REG_P (operands
[0])
4955 || offsettable_memref_p (operands
[0])))
4957 if (DATA_REG_P (operands
[0]))
4958 operands
[1] = GEN_INT (logval
);
4961 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4962 operands
[1] = GEN_INT (logval
% 8);
4964 /* This does not set condition codes in a standard way. */
4966 return "bclr %1,%0";
4968 return "and%.l %2,%0";
4972 output_iorsi3 (rtx
*operands
)
4974 register int logval
;
4975 if (GET_CODE (operands
[2]) == CONST_INT
4976 && INTVAL (operands
[2]) >> 16 == 0
4977 && (DATA_REG_P (operands
[0])
4978 || offsettable_memref_p (operands
[0]))
4979 && !TARGET_COLDFIRE
)
4981 if (GET_CODE (operands
[0]) != REG
)
4982 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4983 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4985 if (INTVAL (operands
[2]) == 0xffff)
4986 return "mov%.w %2,%0";
4987 return "or%.w %2,%0";
4989 if (GET_CODE (operands
[2]) == CONST_INT
4990 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4991 && (DATA_REG_P (operands
[0])
4992 || offsettable_memref_p (operands
[0])))
4994 if (DATA_REG_P (operands
[0]))
4995 operands
[1] = GEN_INT (logval
);
4998 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4999 operands
[1] = GEN_INT (logval
% 8);
5002 return "bset %1,%0";
5004 return "or%.l %2,%0";
5008 output_xorsi3 (rtx
*operands
)
5010 register int logval
;
5011 if (GET_CODE (operands
[2]) == CONST_INT
5012 && INTVAL (operands
[2]) >> 16 == 0
5013 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5014 && !TARGET_COLDFIRE
)
5016 if (! DATA_REG_P (operands
[0]))
5017 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5018 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5020 if (INTVAL (operands
[2]) == 0xffff)
5022 return "eor%.w %2,%0";
5024 if (GET_CODE (operands
[2]) == CONST_INT
5025 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5026 && (DATA_REG_P (operands
[0])
5027 || offsettable_memref_p (operands
[0])))
5029 if (DATA_REG_P (operands
[0]))
5030 operands
[1] = GEN_INT (logval
);
5033 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5034 operands
[1] = GEN_INT (logval
% 8);
5037 return "bchg %1,%0";
5039 return "eor%.l %2,%0";
5042 /* Return the instruction that should be used for a call to address X,
5043 which is known to be in operand 0. */
5048 if (symbolic_operand (x
, VOIDmode
))
5049 return m68k_symbolic_call
;
5054 /* Likewise sibling calls. */
5057 output_sibcall (rtx x
)
5059 if (symbolic_operand (x
, VOIDmode
))
5060 return m68k_symbolic_jump
;
5066 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5067 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5070 const char *fnname
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk
));
5071 rtx this_slot
, offset
, addr
, mem
, tmp
;
5074 /* Avoid clobbering the struct value reg by using the
5075 static chain reg as a temporary. */
5076 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5078 /* Pretend to be a post-reload pass while generating rtl. */
5079 reload_completed
= 1;
5081 /* The "this" pointer is stored at 4(%sp). */
5082 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5083 stack_pointer_rtx
, 4));
5085 /* Add DELTA to THIS. */
5088 /* Make the offset a legitimate operand for memory addition. */
5089 offset
= GEN_INT (delta
);
5090 if ((delta
< -8 || delta
> 8)
5091 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5093 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5094 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5096 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5097 copy_rtx (this_slot
), offset
));
5100 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5101 if (vcall_offset
!= 0)
5103 /* Set the static chain register to *THIS. */
5104 emit_move_insn (tmp
, this_slot
);
5105 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5107 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5108 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5109 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5111 emit_insn (gen_rtx_SET (tmp
, addr
));
5115 /* Load the offset into %d0 and add it to THIS. */
5116 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5117 gen_rtx_MEM (Pmode
, addr
));
5118 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5119 copy_rtx (this_slot
),
5120 gen_rtx_REG (Pmode
, D0_REG
)));
5123 /* Jump to the target function. Use a sibcall if direct jumps are
5124 allowed, otherwise load the address into a register first. */
5125 mem
= DECL_RTL (function
);
5126 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5128 gcc_assert (flag_pic
);
5130 if (!TARGET_SEP_DATA
)
5132 /* Use the static chain register as a temporary (call-clobbered)
5133 GOT pointer for this function. We can use the static chain
5134 register because it isn't live on entry to the thunk. */
5135 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5136 emit_insn (gen_load_got (pic_offset_table_rtx
));
5138 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5139 mem
= replace_equiv_address (mem
, tmp
);
5141 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5142 SIBLING_CALL_P (insn
) = 1;
5144 /* Run just enough of rest_of_compilation. */
5145 insn
= get_insns ();
5146 split_all_insns_noflow ();
5147 assemble_start_function (thunk
, fnname
);
5148 final_start_function (insn
, file
, 1);
5149 final (insn
, file
, 1);
5150 final_end_function ();
5151 assemble_end_function (thunk
, fnname
);
5153 /* Clean up the vars set above. */
5154 reload_completed
= 0;
5156 /* Restore the original PIC register. */
5158 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5161 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5164 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5165 int incoming ATTRIBUTE_UNUSED
)
5167 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5170 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5172 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5173 unsigned int new_reg
)
5176 /* Interrupt functions can only use registers that have already been
5177 saved by the prologue, even if they would normally be
5180 if ((m68k_get_function_kind (current_function_decl
)
5181 == m68k_fk_interrupt_handler
)
5182 && !df_regs_ever_live_p (new_reg
))
5188 /* Implement TARGET_HARD_REGNO_NREGS.
5190 On the m68k, ordinary registers hold 32 bits worth;
5191 for the 68881 registers, a single register is always enough for
5192 anything that can be stored in them at all. */
5195 m68k_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
5198 return GET_MODE_NUNITS (mode
);
5199 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
5202 /* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
5203 registers can hold any mode, but restrict the 68881 registers to
5204 floating-point modes. */
5207 m68k_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
5209 if (DATA_REGNO_P (regno
))
5211 /* Data Registers, can hold aggregate if fits in. */
5212 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5215 else if (ADDRESS_REGNO_P (regno
))
5217 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5220 else if (FP_REGNO_P (regno
))
5222 /* FPU registers, hold float or complex float of long double or
5224 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5225 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5226 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5232 /* Implement TARGET_MODES_TIEABLE_P. */
5235 m68k_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
5237 return (!TARGET_HARD_FLOAT
5238 || ((GET_MODE_CLASS (mode1
) == MODE_FLOAT
5239 || GET_MODE_CLASS (mode1
) == MODE_COMPLEX_FLOAT
)
5240 == (GET_MODE_CLASS (mode2
) == MODE_FLOAT
5241 || GET_MODE_CLASS (mode2
) == MODE_COMPLEX_FLOAT
)));
5244 /* Implement SECONDARY_RELOAD_CLASS. */
5247 m68k_secondary_reload_class (enum reg_class rclass
,
5248 machine_mode mode
, rtx x
)
5252 regno
= true_regnum (x
);
5254 /* If one operand of a movqi is an address register, the other
5255 operand must be a general register or constant. Other types
5256 of operand must be reloaded through a data register. */
5257 if (GET_MODE_SIZE (mode
) == 1
5258 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5259 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5262 /* PC-relative addresses must be loaded into an address register first. */
5264 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5265 && symbolic_operand (x
, VOIDmode
))
5271 /* Implement PREFERRED_RELOAD_CLASS. */
5274 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5276 enum reg_class secondary_class
;
5278 /* If RCLASS might need a secondary reload, try restricting it to
5279 a class that doesn't. */
5280 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5281 if (secondary_class
!= NO_REGS
5282 && reg_class_subset_p (secondary_class
, rclass
))
5283 return secondary_class
;
5285 /* Prefer to use moveq for in-range constants. */
5286 if (GET_CODE (x
) == CONST_INT
5287 && reg_class_subset_p (DATA_REGS
, rclass
)
5288 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5291 /* ??? Do we really need this now? */
5292 if (GET_CODE (x
) == CONST_DOUBLE
5293 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5295 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5304 /* Return floating point values in a 68881 register. This makes 68881 code
5305 a little bit faster. It also makes -msoft-float code incompatible with
5306 hard-float code, so people have to be careful not to mix the two.
5307 For ColdFire it was decided the ABI incompatibility is undesirable.
5308 If there is need for a hard-float ABI it is probably worth doing it
5309 properly and also passing function arguments in FP registers. */
5311 m68k_libcall_value (machine_mode mode
)
5318 return gen_rtx_REG (mode
, FP0_REG
);
5324 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5327 /* Location in which function value is returned.
5328 NOTE: Due to differences in ABIs, don't call this function directly,
5329 use FUNCTION_VALUE instead. */
5331 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5335 mode
= TYPE_MODE (valtype
);
5341 return gen_rtx_REG (mode
, FP0_REG
);
5347 /* If the function returns a pointer, push that into %a0. */
5348 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5349 /* For compatibility with the large body of existing code which
5350 does not always properly declare external functions returning
5351 pointer types, the m68k/SVR4 convention is to copy the value
5352 returned for pointer functions from a0 to d0 in the function
5353 epilogue, so that callers that have neglected to properly
5354 declare the callee can still find the correct return value in
5356 return gen_rtx_PARALLEL
5359 gen_rtx_EXPR_LIST (VOIDmode
,
5360 gen_rtx_REG (mode
, A0_REG
),
5362 gen_rtx_EXPR_LIST (VOIDmode
,
5363 gen_rtx_REG (mode
, D0_REG
),
5365 else if (POINTER_TYPE_P (valtype
))
5366 return gen_rtx_REG (mode
, A0_REG
);
5368 return gen_rtx_REG (mode
, D0_REG
);
5371 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5372 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5374 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5376 machine_mode mode
= TYPE_MODE (type
);
5378 if (mode
== BLKmode
)
5381 /* If TYPE's known alignment is less than the alignment of MODE that
5382 would contain the structure, then return in memory. We need to
5383 do so to maintain the compatibility between code compiled with
5384 -mstrict-align and that compiled with -mno-strict-align. */
5385 if (AGGREGATE_TYPE_P (type
)
5386 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5393 /* CPU to schedule the program for. */
5394 enum attr_cpu m68k_sched_cpu
;
5396 /* MAC to schedule the program for. */
5397 enum attr_mac m68k_sched_mac
;
5405 /* Integer register. */
5411 /* Implicit mem reference (e.g. stack). */
5414 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5417 /* Memory with offset but without indexing. EA mode 5. */
5420 /* Memory with indexing. EA mode 6. */
5423 /* Memory referenced by absolute address. EA mode 7. */
5426 /* Immediate operand that doesn't require extension word. */
5429 /* Immediate 16 bit operand. */
5432 /* Immediate 32 bit operand. */
5436 /* Return type of memory ADDR_RTX refers to. */
5437 static enum attr_op_type
5438 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5440 struct m68k_address address
;
5442 if (symbolic_operand (addr_rtx
, VOIDmode
))
5443 return OP_TYPE_MEM7
;
5445 if (!m68k_decompose_address (mode
, addr_rtx
,
5446 reload_completed
, &address
))
5448 gcc_assert (!reload_completed
);
5449 /* Reload will likely fix the address to be in the register. */
5450 return OP_TYPE_MEM234
;
5453 if (address
.scale
!= 0)
5454 return OP_TYPE_MEM6
;
5456 if (address
.base
!= NULL_RTX
)
5458 if (address
.offset
== NULL_RTX
)
5459 return OP_TYPE_MEM234
;
5461 return OP_TYPE_MEM5
;
5464 gcc_assert (address
.offset
!= NULL_RTX
);
5466 return OP_TYPE_MEM7
;
5469 /* Return X or Y (depending on OPX_P) operand of INSN. */
5471 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5475 if (recog_memoized (insn
) < 0)
5478 extract_constrain_insn_cached (insn
);
5481 i
= get_attr_opx (insn
);
5483 i
= get_attr_opy (insn
);
5485 if (i
>= recog_data
.n_operands
)
5488 return recog_data
.operand
[i
];
5491 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5492 If ADDRESS_P is true, return type of memory location operand refers to. */
5493 static enum attr_op_type
5494 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5498 op
= sched_get_operand (insn
, opx_p
);
5502 gcc_assert (!reload_completed
);
5507 return sched_address_type (QImode
, op
);
5509 if (memory_operand (op
, VOIDmode
))
5510 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5512 if (register_operand (op
, VOIDmode
))
5514 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5515 || (reload_completed
&& FP_REG_P (op
)))
5521 if (GET_CODE (op
) == CONST_INT
)
5527 /* Check for quick constants. */
5528 switch (get_attr_type (insn
))
5531 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5532 return OP_TYPE_IMM_Q
;
5534 gcc_assert (!reload_completed
);
5538 if (USE_MOVQ (ival
))
5539 return OP_TYPE_IMM_Q
;
5541 gcc_assert (!reload_completed
);
5545 if (valid_mov3q_const (ival
))
5546 return OP_TYPE_IMM_Q
;
5548 gcc_assert (!reload_completed
);
5555 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5556 return OP_TYPE_IMM_W
;
5558 return OP_TYPE_IMM_L
;
5561 if (GET_CODE (op
) == CONST_DOUBLE
)
5563 switch (GET_MODE (op
))
5566 return OP_TYPE_IMM_W
;
5570 return OP_TYPE_IMM_L
;
5577 if (GET_CODE (op
) == CONST
5578 || symbolic_operand (op
, VOIDmode
)
5581 switch (GET_MODE (op
))
5584 return OP_TYPE_IMM_Q
;
5587 return OP_TYPE_IMM_W
;
5590 return OP_TYPE_IMM_L
;
5593 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5595 return OP_TYPE_IMM_W
;
5597 return OP_TYPE_IMM_L
;
5601 gcc_assert (!reload_completed
);
5603 if (FLOAT_MODE_P (GET_MODE (op
)))
5609 /* Implement opx_type attribute.
5610 Return type of INSN's operand X.
5611 If ADDRESS_P is true, return type of memory location operand refers to. */
5613 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5615 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5621 return OPX_TYPE_FPN
;
5624 return OPX_TYPE_MEM1
;
5626 case OP_TYPE_MEM234
:
5627 return OPX_TYPE_MEM234
;
5630 return OPX_TYPE_MEM5
;
5633 return OPX_TYPE_MEM6
;
5636 return OPX_TYPE_MEM7
;
5639 return OPX_TYPE_IMM_Q
;
5642 return OPX_TYPE_IMM_W
;
5645 return OPX_TYPE_IMM_L
;
5652 /* Implement opy_type attribute.
5653 Return type of INSN's operand Y.
5654 If ADDRESS_P is true, return type of memory location operand refers to. */
5656 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5658 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5664 return OPY_TYPE_FPN
;
5667 return OPY_TYPE_MEM1
;
5669 case OP_TYPE_MEM234
:
5670 return OPY_TYPE_MEM234
;
5673 return OPY_TYPE_MEM5
;
5676 return OPY_TYPE_MEM6
;
5679 return OPY_TYPE_MEM7
;
5682 return OPY_TYPE_IMM_Q
;
5685 return OPY_TYPE_IMM_W
;
5688 return OPY_TYPE_IMM_L
;
5695 /* Return size of INSN as int. */
5697 sched_get_attr_size_int (rtx_insn
*insn
)
5701 switch (get_attr_type (insn
))
5704 /* There should be no references to m68k_sched_attr_size for 'ignore'
5718 switch (get_attr_opx_type (insn
))
5724 case OPX_TYPE_MEM234
:
5725 case OPY_TYPE_IMM_Q
:
5730 /* Here we assume that most absolute references are short. */
5732 case OPY_TYPE_IMM_W
:
5736 case OPY_TYPE_IMM_L
:
5744 switch (get_attr_opy_type (insn
))
5750 case OPY_TYPE_MEM234
:
5751 case OPY_TYPE_IMM_Q
:
5756 /* Here we assume that most absolute references are short. */
5758 case OPY_TYPE_IMM_W
:
5762 case OPY_TYPE_IMM_L
:
5772 gcc_assert (!reload_completed
);
5780 /* Return size of INSN as attribute enum value. */
5782 m68k_sched_attr_size (rtx_insn
*insn
)
5784 switch (sched_get_attr_size_int (insn
))
5800 /* Return operand X or Y (depending on OPX_P) of INSN,
5801 if it is a MEM, or NULL overwise. */
5802 static enum attr_op_type
5803 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5807 switch (get_attr_opx_type (insn
))
5812 case OPX_TYPE_IMM_Q
:
5813 case OPX_TYPE_IMM_W
:
5814 case OPX_TYPE_IMM_L
:
5818 case OPX_TYPE_MEM234
:
5821 return OP_TYPE_MEM1
;
5824 return OP_TYPE_MEM6
;
5832 switch (get_attr_opy_type (insn
))
5837 case OPY_TYPE_IMM_Q
:
5838 case OPY_TYPE_IMM_W
:
5839 case OPY_TYPE_IMM_L
:
5843 case OPY_TYPE_MEM234
:
5846 return OP_TYPE_MEM1
;
5849 return OP_TYPE_MEM6
;
5857 /* Implement op_mem attribute. */
5859 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5861 enum attr_op_type opx
;
5862 enum attr_op_type opy
;
5864 opx
= sched_get_opxy_mem_type (insn
, true);
5865 opy
= sched_get_opxy_mem_type (insn
, false);
5867 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5870 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5872 switch (get_attr_opx_access (insn
))
5888 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5890 switch (get_attr_opx_access (insn
))
5906 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5909 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5911 switch (get_attr_opx_access (insn
))
5917 gcc_assert (!reload_completed
);
5922 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5924 switch (get_attr_opx_access (insn
))
5930 gcc_assert (!reload_completed
);
5935 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5938 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5940 switch (get_attr_opx_access (insn
))
5946 gcc_assert (!reload_completed
);
5951 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5952 gcc_assert (!reload_completed
);
5956 /* Data for ColdFire V4 index bypass.
5957 Producer modifies register that is used as index in consumer with
5961 /* Producer instruction. */
5964 /* Consumer instruction. */
5967 /* Scale of indexed memory access within consumer.
5968 Or zero if bypass should not be effective at the moment. */
5970 } sched_cfv4_bypass_data
;
5972 /* An empty state that is used in m68k_sched_adjust_cost. */
5973 static state_t sched_adjust_cost_state
;
5975 /* Implement adjust_cost scheduler hook.
5976 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5978 m68k_sched_adjust_cost (rtx_insn
*insn
, int, rtx_insn
*def_insn
, int cost
,
5983 if (recog_memoized (def_insn
) < 0
5984 || recog_memoized (insn
) < 0)
5987 if (sched_cfv4_bypass_data
.scale
== 1)
5988 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5990 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5991 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5992 that the data in sched_cfv4_bypass_data is up to date. */
5993 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5994 && sched_cfv4_bypass_data
.con
== insn
);
5999 sched_cfv4_bypass_data
.pro
= NULL
;
6000 sched_cfv4_bypass_data
.con
= NULL
;
6001 sched_cfv4_bypass_data
.scale
= 0;
6004 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6005 && sched_cfv4_bypass_data
.con
== NULL
6006 && sched_cfv4_bypass_data
.scale
== 0);
6008 /* Don't try to issue INSN earlier than DFA permits.
6009 This is especially useful for instructions that write to memory,
6010 as their true dependence (default) latency is better to be set to 0
6011 to workaround alias analysis limitations.
6012 This is, in fact, a machine independent tweak, so, probably,
6013 it should be moved to haifa-sched.c: insn_cost (). */
6014 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
6021 /* Return maximal number of insns that can be scheduled on a single cycle. */
6023 m68k_sched_issue_rate (void)
6025 switch (m68k_sched_cpu
)
6041 /* Maximal length of instruction for current CPU.
6042 E.g. it is 3 for any ColdFire core. */
6043 static int max_insn_size
;
6045 /* Data to model instruction buffer of CPU. */
6048 /* True if instruction buffer model is modeled for current CPU. */
6051 /* Size of the instruction buffer in words. */
6054 /* Number of filled words in the instruction buffer. */
6057 /* Additional information about instruction buffer for CPUs that have
6058 a buffer of instruction records, rather then a plain buffer
6059 of instruction words. */
6060 struct _sched_ib_records
6062 /* Size of buffer in records. */
6065 /* Array to hold data on adjustments made to the size of the buffer. */
6068 /* Index of the above array. */
6072 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6076 static struct _sched_ib sched_ib
;
6078 /* ID of memory unit. */
6079 static int sched_mem_unit_code
;
6081 /* Implementation of the targetm.sched.variable_issue () hook.
6082 It is called after INSN was issued. It returns the number of insns
6083 that can possibly get scheduled on the current cycle.
6084 It is used here to determine the effect of INSN on the instruction
6087 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6088 int sched_verbose ATTRIBUTE_UNUSED
,
6089 rtx_insn
*insn
, int can_issue_more
)
6093 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6095 switch (m68k_sched_cpu
)
6099 insn_size
= sched_get_attr_size_int (insn
);
6103 insn_size
= sched_get_attr_size_int (insn
);
6105 /* ColdFire V3 and V4 cores have instruction buffers that can
6106 accumulate up to 8 instructions regardless of instructions'
6107 sizes. So we should take care not to "prefetch" 24 one-word
6108 or 12 two-words instructions.
6109 To model this behavior we temporarily decrease size of the
6110 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6114 adjust
= max_insn_size
- insn_size
;
6115 sched_ib
.size
-= adjust
;
6117 if (sched_ib
.filled
> sched_ib
.size
)
6118 sched_ib
.filled
= sched_ib
.size
;
6120 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6123 ++sched_ib
.records
.adjust_index
;
6124 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6125 sched_ib
.records
.adjust_index
= 0;
6127 /* Undo adjustment we did 7 instructions ago. */
6129 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6134 gcc_assert (!sched_ib
.enabled_p
);
6142 if (insn_size
> sched_ib
.filled
)
6143 /* Scheduling for register pressure does not always take DFA into
6144 account. Workaround instruction buffer not being filled enough. */
6146 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6147 insn_size
= sched_ib
.filled
;
6152 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6153 || asm_noperands (PATTERN (insn
)) >= 0)
6154 insn_size
= sched_ib
.filled
;
6158 sched_ib
.filled
-= insn_size
;
6160 return can_issue_more
;
6163 /* Return how many instructions should scheduler lookahead to choose the
6166 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6168 return m68k_sched_issue_rate () - 1;
6171 /* Implementation of targetm.sched.init_global () hook.
6172 It is invoked once per scheduling pass and is used here
6173 to initialize scheduler constants. */
6175 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6176 int sched_verbose ATTRIBUTE_UNUSED
,
6177 int n_insns ATTRIBUTE_UNUSED
)
6179 /* Check that all instructions have DFA reservations and
6180 that all instructions can be issued from a clean state. */
6186 state
= alloca (state_size ());
6188 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6190 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6192 gcc_assert (insn_has_dfa_reservation_p (insn
));
6194 state_reset (state
);
6195 if (state_transition (state
, insn
) >= 0)
6201 /* Setup target cpu. */
6203 /* ColdFire V4 has a set of features to keep its instruction buffer full
6204 (e.g., a separate memory bus for instructions) and, hence, we do not model
6205 buffer for this CPU. */
6206 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6208 switch (m68k_sched_cpu
)
6211 sched_ib
.filled
= 0;
6218 sched_ib
.records
.n_insns
= 0;
6219 sched_ib
.records
.adjust
= NULL
;
6224 sched_ib
.records
.n_insns
= 8;
6225 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6232 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6234 sched_adjust_cost_state
= xmalloc (state_size ());
6235 state_reset (sched_adjust_cost_state
);
6238 emit_insn (gen_ib ());
6239 sched_ib
.insn
= get_insns ();
6243 /* Scheduling pass is now finished. Free/reset static variables. */
6245 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6246 int verbose ATTRIBUTE_UNUSED
)
6248 sched_ib
.insn
= NULL
;
6250 free (sched_adjust_cost_state
);
6251 sched_adjust_cost_state
= NULL
;
6253 sched_mem_unit_code
= 0;
6255 free (sched_ib
.records
.adjust
);
6256 sched_ib
.records
.adjust
= NULL
;
6257 sched_ib
.records
.n_insns
= 0;
6261 /* Implementation of targetm.sched.init () hook.
6262 It is invoked each time scheduler starts on the new block (basic block or
6263 extended basic block). */
6265 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6266 int sched_verbose ATTRIBUTE_UNUSED
,
6267 int n_insns ATTRIBUTE_UNUSED
)
6269 switch (m68k_sched_cpu
)
6277 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6279 memset (sched_ib
.records
.adjust
, 0,
6280 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6281 sched_ib
.records
.adjust_index
= 0;
6285 gcc_assert (!sched_ib
.enabled_p
);
6293 if (sched_ib
.enabled_p
)
6294 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6295 the first cycle. Workaround that. */
6296 sched_ib
.filled
= -2;
6299 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6300 It is invoked just before current cycle finishes and is used here
6301 to track if instruction buffer got its two words this cycle. */
6303 m68k_sched_dfa_pre_advance_cycle (void)
6305 if (!sched_ib
.enabled_p
)
6308 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6310 sched_ib
.filled
+= 2;
6312 if (sched_ib
.filled
> sched_ib
.size
)
6313 sched_ib
.filled
= sched_ib
.size
;
6317 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6318 It is invoked just after new cycle begins and is used here
6319 to setup number of filled words in the instruction buffer so that
6320 instructions which won't have all their words prefetched would be
6321 stalled for a cycle. */
6323 m68k_sched_dfa_post_advance_cycle (void)
6327 if (!sched_ib
.enabled_p
)
6330 /* Setup number of prefetched instruction words in the instruction
6332 i
= max_insn_size
- sched_ib
.filled
;
6336 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6337 /* Pick up scheduler state. */
6342 /* Return X or Y (depending on OPX_P) operand of INSN,
6343 if it is an integer register, or NULL overwise. */
6345 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6351 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6353 op
= sched_get_operand (insn
, true);
6354 gcc_assert (op
!= NULL
);
6356 if (!reload_completed
&& !REG_P (op
))
6362 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6364 op
= sched_get_operand (insn
, false);
6365 gcc_assert (op
!= NULL
);
6367 if (!reload_completed
&& !REG_P (op
))
6375 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6378 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6380 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6391 /* Return X or Y (depending on OPX_P) operand of INSN,
6392 if it is a MEM, or NULL overwise. */
6394 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6414 if (opy_p
&& sched_mem_operand_p (insn
, false))
6415 return sched_get_operand (insn
, false);
6417 if (opx_p
&& sched_mem_operand_p (insn
, true))
6418 return sched_get_operand (insn
, true);
6424 /* Return non-zero if PRO modifies register used as part of
6427 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6432 pro_x
= sched_get_reg_operand (pro
, true);
6436 con_mem_read
= sched_get_mem_operand (con
, true, false);
6437 gcc_assert (con_mem_read
!= NULL
);
6439 if (reg_mentioned_p (pro_x
, con_mem_read
))
6445 /* Helper function for m68k_sched_indexed_address_bypass_p.
6446 if PRO modifies register used as index in CON,
6447 return scale of indexed memory access in CON. Return zero overwise. */
6449 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6453 struct m68k_address address
;
6455 reg
= sched_get_reg_operand (pro
, true);
6459 mem
= sched_get_mem_operand (con
, true, false);
6460 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6462 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6466 if (REGNO (reg
) == REGNO (address
.index
))
6468 gcc_assert (address
.scale
!= 0);
6469 return address
.scale
;
6475 /* Return non-zero if PRO modifies register used
6476 as index with scale 2 or 4 in CON. */
6478 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6480 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6481 && sched_cfv4_bypass_data
.con
== NULL
6482 && sched_cfv4_bypass_data
.scale
== 0);
6484 switch (sched_get_indexed_address_scale (pro
, con
))
6487 /* We can't have a variable latency bypass, so
6488 remember to adjust the insn cost in adjust_cost hook. */
6489 sched_cfv4_bypass_data
.pro
= pro
;
6490 sched_cfv4_bypass_data
.con
= con
;
6491 sched_cfv4_bypass_data
.scale
= 1;
6503 /* We generate a two-instructions program at M_TRAMP :
6504 movea.l &CHAIN_VALUE,%a0
6506 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6509 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6511 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6514 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6516 mem
= adjust_address (m_tramp
, HImode
, 0);
6517 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6518 mem
= adjust_address (m_tramp
, SImode
, 2);
6519 emit_move_insn (mem
, chain_value
);
6521 mem
= adjust_address (m_tramp
, HImode
, 6);
6522 emit_move_insn (mem
, GEN_INT(0x4EF9));
6523 mem
= adjust_address (m_tramp
, SImode
, 8);
6524 emit_move_insn (mem
, fnaddr
);
6526 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6529 /* On the 68000, the RTS insn cannot pop anything.
6530 On the 68010, the RTD insn may be used to pop them if the number
6531 of args is fixed, but if the number is variable then the caller
6532 must pop them all. RTD can't be used for library calls now
6533 because the library is compiled with the Unix compiler.
6534 Use of RTD is a selectable option, since it is incompatible with
6535 standard Unix calling sequences. If the option is not selected,
6536 the caller must always pop the args. */
6539 m68k_return_pops_args (tree fundecl
, tree funtype
, poly_int64 size
)
6543 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6544 && (!stdarg_p (funtype
)))
6545 ? (HOST_WIDE_INT
) size
: 0);
6548 /* Make sure everything's fine if we *don't* have a given processor.
6549 This assumes that putting a register in fixed_regs will keep the
6550 compiler's mitts completely off it. We don't bother to zero it out
6551 of register classes. */
6554 m68k_conditional_register_usage (void)
6558 if (!TARGET_HARD_FLOAT
)
6560 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6561 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6562 if (TEST_HARD_REG_BIT (x
, i
))
6563 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6566 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6570 m68k_init_sync_libfuncs (void)
6572 init_sync_libfuncs (UNITS_PER_WORD
);
6575 /* Implements EPILOGUE_USES. All registers are live on exit from an
6576 interrupt routine. */
6578 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6580 return (reload_completed
6581 && (m68k_get_function_kind (current_function_decl
)
6582 == m68k_fk_interrupt_handler
));
6586 /* Implement TARGET_C_EXCESS_PRECISION.
6588 Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
6589 instructions, we get proper intermediate rounding, otherwise we
6590 get extended precision results. */
6592 static enum flt_eval_method
6593 m68k_excess_precision (enum excess_precision_type type
)
6597 case EXCESS_PRECISION_TYPE_FAST
:
6598 /* The fastest type to promote to will always be the native type,
6599 whether that occurs with implicit excess precision or
6601 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6602 case EXCESS_PRECISION_TYPE_STANDARD
:
6603 case EXCESS_PRECISION_TYPE_IMPLICIT
:
6604 /* Otherwise, the excess precision we want when we are
6605 in a standards compliant mode, and the implicit precision we
6606 provide can be identical. */
6607 if (TARGET_68040
|| ! TARGET_68881
)
6608 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6610 return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE
;
6614 return FLT_EVAL_METHOD_UNPREDICTABLE
;
6617 /* Implement PUSH_ROUNDING. On the 680x0, sp@- in a byte insn really pushes
6618 a word. On the ColdFire, sp@- in a byte insn pushes just a byte. */
6621 m68k_push_rounding (poly_int64 bytes
)
6623 if (TARGET_COLDFIRE
)
6625 return (bytes
+ 1) & ~1;
6628 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
6631 m68k_promote_function_mode (const_tree type
, machine_mode mode
,
6632 int *punsignedp ATTRIBUTE_UNUSED
,
6633 const_tree fntype ATTRIBUTE_UNUSED
,
6636 /* Promote libcall arguments narrower than int to match the normal C
6637 ABI (for which promotions are handled via
6638 TARGET_PROMOTE_PROTOTYPES). */
6639 if (type
== NULL_TREE
&& !for_return
&& (mode
== QImode
|| mode
== HImode
))
6644 #include "gt-m68k.h"