1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "stor-layout.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
37 #include "diagnostic-core.h"
42 #include "target-def.h"
46 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
47 #include "sched-int.h"
48 #include "insn-codes.h"
53 enum reg_class regno_reg_class
[] =
55 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
56 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
57 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
58 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
59 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
60 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
65 /* The minimum number of integer registers that we want to save with the
66 movem instruction. Using two movel instructions instead of a single
67 moveml is about 15% faster for the 68020 and 68030 at no expense in
69 #define MIN_MOVEM_REGS 3
71 /* The minimum number of floating point registers that we want to save
72 with the fmovem instruction. */
73 #define MIN_FMOVEM_REGS 1
75 /* Structure describing stack frame layout. */
78 /* Stack pointer to frame pointer offset. */
81 /* Offset of FPU registers. */
82 HOST_WIDE_INT foffset
;
84 /* Frame size in bytes (rounded up). */
87 /* Data and address register. */
89 unsigned int reg_mask
;
93 unsigned int fpu_mask
;
95 /* Offsets relative to ARG_POINTER. */
96 HOST_WIDE_INT frame_pointer_offset
;
97 HOST_WIDE_INT stack_pointer_offset
;
99 /* Function which the above information refers to. */
103 /* Current frame information calculated by m68k_compute_frame_layout(). */
104 static struct m68k_frame current_frame
;
106 /* Structure describing an m68k address.
108 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
109 with null fields evaluating to 0. Here:
111 - BASE satisfies m68k_legitimate_base_reg_p
112 - INDEX satisfies m68k_legitimate_index_reg_p
113 - OFFSET satisfies m68k_legitimate_constant_address_p
115 INDEX is either HImode or SImode. The other fields are SImode.
117 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
118 the address is (BASE)+. */
119 struct m68k_address
{
127 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
128 static int m68k_sched_issue_rate (void);
129 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
130 static void m68k_sched_md_init_global (FILE *, int, int);
131 static void m68k_sched_md_finish_global (FILE *, int);
132 static void m68k_sched_md_init (FILE *, int, int);
133 static void m68k_sched_dfa_pre_advance_cycle (void);
134 static void m68k_sched_dfa_post_advance_cycle (void);
135 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
137 static bool m68k_can_eliminate (const int, const int);
138 static void m68k_conditional_register_usage (void);
139 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
140 static void m68k_option_override (void);
141 static void m68k_override_options_after_change (void);
142 static rtx
find_addr_reg (rtx
);
143 static const char *singlemove_string (rtx
*);
144 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
145 HOST_WIDE_INT
, tree
);
146 static rtx
m68k_struct_value_rtx (tree
, int);
147 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
148 tree args
, int flags
,
150 static void m68k_compute_frame_layout (void);
151 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
152 static bool m68k_ok_for_sibcall_p (tree
, tree
);
153 static bool m68k_tls_symbol_p (rtx
);
154 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
155 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
156 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
157 static bool m68k_return_in_memory (const_tree
, const_tree
);
159 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
160 static void m68k_trampoline_init (rtx
, tree
, rtx
);
161 static int m68k_return_pops_args (tree
, tree
, int);
162 static rtx
m68k_delegitimize_address (rtx
);
163 static void m68k_function_arg_advance (cumulative_args_t
, enum machine_mode
,
165 static rtx
m68k_function_arg (cumulative_args_t
, enum machine_mode
,
167 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
168 static bool m68k_output_addr_const_extra (FILE *, rtx
);
169 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
171 /* Initialize the GCC target structure. */
173 #if INT_OP_GROUP == INT_OP_DOT_WORD
174 #undef TARGET_ASM_ALIGNED_HI_OP
175 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
178 #if INT_OP_GROUP == INT_OP_NO_DOT
179 #undef TARGET_ASM_BYTE_OP
180 #define TARGET_ASM_BYTE_OP "\tbyte\t"
181 #undef TARGET_ASM_ALIGNED_HI_OP
182 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
183 #undef TARGET_ASM_ALIGNED_SI_OP
184 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
187 #if INT_OP_GROUP == INT_OP_DC
188 #undef TARGET_ASM_BYTE_OP
189 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
190 #undef TARGET_ASM_ALIGNED_HI_OP
191 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
192 #undef TARGET_ASM_ALIGNED_SI_OP
193 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
196 #undef TARGET_ASM_UNALIGNED_HI_OP
197 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
198 #undef TARGET_ASM_UNALIGNED_SI_OP
199 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
201 #undef TARGET_ASM_OUTPUT_MI_THUNK
202 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
203 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
204 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
206 #undef TARGET_ASM_FILE_START_APP_OFF
207 #define TARGET_ASM_FILE_START_APP_OFF true
209 #undef TARGET_LEGITIMIZE_ADDRESS
210 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
212 #undef TARGET_SCHED_ADJUST_COST
213 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
215 #undef TARGET_SCHED_ISSUE_RATE
216 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
218 #undef TARGET_SCHED_VARIABLE_ISSUE
219 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
221 #undef TARGET_SCHED_INIT_GLOBAL
222 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
224 #undef TARGET_SCHED_FINISH_GLOBAL
225 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
227 #undef TARGET_SCHED_INIT
228 #define TARGET_SCHED_INIT m68k_sched_md_init
230 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
231 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
233 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
234 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
236 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
237 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
238 m68k_sched_first_cycle_multipass_dfa_lookahead
240 #undef TARGET_OPTION_OVERRIDE
241 #define TARGET_OPTION_OVERRIDE m68k_option_override
243 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
244 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
246 #undef TARGET_RTX_COSTS
247 #define TARGET_RTX_COSTS m68k_rtx_costs
249 #undef TARGET_ATTRIBUTE_TABLE
250 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
252 #undef TARGET_PROMOTE_PROTOTYPES
253 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
255 #undef TARGET_STRUCT_VALUE_RTX
256 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
258 #undef TARGET_CANNOT_FORCE_CONST_MEM
259 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
261 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
262 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
264 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
265 #undef TARGET_RETURN_IN_MEMORY
266 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
270 #undef TARGET_HAVE_TLS
271 #define TARGET_HAVE_TLS (true)
273 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
274 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
277 #undef TARGET_LEGITIMATE_ADDRESS_P
278 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
280 #undef TARGET_CAN_ELIMINATE
281 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
283 #undef TARGET_CONDITIONAL_REGISTER_USAGE
284 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
286 #undef TARGET_TRAMPOLINE_INIT
287 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
289 #undef TARGET_RETURN_POPS_ARGS
290 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
292 #undef TARGET_DELEGITIMIZE_ADDRESS
293 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
295 #undef TARGET_FUNCTION_ARG
296 #define TARGET_FUNCTION_ARG m68k_function_arg
298 #undef TARGET_FUNCTION_ARG_ADVANCE
299 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
301 #undef TARGET_LEGITIMATE_CONSTANT_P
302 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
304 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
305 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
307 /* The value stored by TAS. */
308 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
309 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
311 static const struct attribute_spec m68k_attribute_table
[] =
313 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
314 affects_type_identity } */
315 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
317 { "interrupt_handler", 0, 0, true, false, false,
318 m68k_handle_fndecl_attribute
, false },
319 { "interrupt_thread", 0, 0, true, false, false,
320 m68k_handle_fndecl_attribute
, false },
321 { NULL
, 0, 0, false, false, false, NULL
, false }
324 struct gcc_target targetm
= TARGET_INITIALIZER
;
326 /* Base flags for 68k ISAs. */
327 #define FL_FOR_isa_00 FL_ISA_68000
328 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
329 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
330 generated 68881 code for 68020 and 68030 targets unless explicitly told
332 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
333 | FL_BITFIELD | FL_68881 | FL_CAS)
334 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
335 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
337 /* Base flags for ColdFire ISAs. */
338 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
339 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
340 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
341 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
342 /* ISA_C is not upwardly compatible with ISA_B. */
343 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
347 /* Traditional 68000 instruction sets. */
353 /* ColdFire instruction set variants. */
361 /* Information about one of the -march, -mcpu or -mtune arguments. */
362 struct m68k_target_selection
364 /* The argument being described. */
367 /* For -mcpu, this is the device selected by the option.
368 For -mtune and -march, it is a representative device
369 for the microarchitecture or ISA respectively. */
370 enum target_device device
;
372 /* The M68K_DEVICE fields associated with DEVICE. See the comment
373 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
375 enum uarch_type microarch
;
380 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
381 static const struct m68k_target_selection all_devices
[] =
383 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
384 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
385 #include "m68k-devices.def"
387 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
390 /* A list of all ISAs, mapping each one to a representative device.
391 Used for -march selection. */
392 static const struct m68k_target_selection all_isas
[] =
394 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
395 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
396 #include "m68k-isas.def"
398 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
401 /* A list of all microarchitectures, mapping each one to a representative
402 device. Used for -mtune selection. */
403 static const struct m68k_target_selection all_microarchs
[] =
405 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
406 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
407 #include "m68k-microarchs.def"
408 #undef M68K_MICROARCH
409 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
412 /* The entries associated with the -mcpu, -march and -mtune settings,
413 or null for options that have not been used. */
414 const struct m68k_target_selection
*m68k_cpu_entry
;
415 const struct m68k_target_selection
*m68k_arch_entry
;
416 const struct m68k_target_selection
*m68k_tune_entry
;
418 /* Which CPU we are generating code for. */
419 enum target_device m68k_cpu
;
421 /* Which microarchitecture to tune for. */
422 enum uarch_type m68k_tune
;
424 /* Which FPU to use. */
425 enum fpu_type m68k_fpu
;
427 /* The set of FL_* flags that apply to the target processor. */
428 unsigned int m68k_cpu_flags
;
430 /* The set of FL_* flags that apply to the processor to be tuned for. */
431 unsigned int m68k_tune_flags
;
433 /* Asm templates for calling or jumping to an arbitrary symbolic address,
434 or NULL if such calls or jumps are not supported. The address is held
436 const char *m68k_symbolic_call
;
437 const char *m68k_symbolic_jump
;
439 /* Enum variable that corresponds to m68k_symbolic_call values. */
440 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
443 /* Implement TARGET_OPTION_OVERRIDE. */
446 m68k_option_override (void)
448 const struct m68k_target_selection
*entry
;
449 unsigned long target_mask
;
451 if (global_options_set
.x_m68k_arch_option
)
452 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
454 if (global_options_set
.x_m68k_cpu_option
)
455 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
457 if (global_options_set
.x_m68k_tune_option
)
458 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
466 -march=ARCH should generate code that runs any processor
467 implementing architecture ARCH. -mcpu=CPU should override -march
468 and should generate code that runs on processor CPU, making free
469 use of any instructions that CPU understands. -mtune=UARCH applies
470 on top of -mcpu or -march and optimizes the code for UARCH. It does
471 not change the target architecture. */
474 /* Complain if the -march setting is for a different microarchitecture,
475 or includes flags that the -mcpu setting doesn't. */
477 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
478 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
479 warning (0, "-mcpu=%s conflicts with -march=%s",
480 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
482 entry
= m68k_cpu_entry
;
485 entry
= m68k_arch_entry
;
488 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
490 m68k_cpu_flags
= entry
->flags
;
492 /* Use the architecture setting to derive default values for
496 /* ColdFire is lenient about alignment. */
497 if (!TARGET_COLDFIRE
)
498 target_mask
|= MASK_STRICT_ALIGNMENT
;
500 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
501 target_mask
|= MASK_BITFIELD
;
502 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
503 target_mask
|= MASK_CF_HWDIV
;
504 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
505 target_mask
|= MASK_HARD_FLOAT
;
506 target_flags
|= target_mask
& ~target_flags_explicit
;
508 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
509 m68k_cpu
= entry
->device
;
512 m68k_tune
= m68k_tune_entry
->microarch
;
513 m68k_tune_flags
= m68k_tune_entry
->flags
;
515 #ifdef M68K_DEFAULT_TUNE
516 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
518 enum target_device dev
;
519 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
520 m68k_tune_flags
= all_devices
[dev
]->flags
;
525 m68k_tune
= entry
->microarch
;
526 m68k_tune_flags
= entry
->flags
;
529 /* Set the type of FPU. */
530 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
531 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
534 /* Sanity check to ensure that msep-data and mid-sahred-library are not
535 * both specified together. Doing so simply doesn't make sense.
537 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
538 error ("cannot specify both -msep-data and -mid-shared-library");
540 /* If we're generating code for a separate A5 relative data segment,
541 * we've got to enable -fPIC as well. This might be relaxable to
542 * -fpic but it hasn't been tested properly.
544 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
547 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
548 error if the target does not support them. */
549 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
550 error ("-mpcrel -fPIC is not currently supported on selected cpu");
552 /* ??? A historic way of turning on pic, or is this intended to
553 be an embedded thing that doesn't have the same name binding
554 significance that it does on hosted ELF systems? */
555 if (TARGET_PCREL
&& flag_pic
== 0)
560 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
562 m68k_symbolic_jump
= "jra %a0";
564 else if (TARGET_ID_SHARED_LIBRARY
)
565 /* All addresses must be loaded from the GOT. */
567 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
570 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
572 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
575 /* No unconditional long branch */;
576 else if (TARGET_PCREL
)
577 m68k_symbolic_jump
= "bra%.l %c0";
579 m68k_symbolic_jump
= "bra%.l %p0";
580 /* Turn off function cse if we are doing PIC. We always want
581 function call to be done as `bsr foo@PLTPC'. */
582 /* ??? It's traditional to do this for -mpcrel too, but it isn't
583 clear how intentional that is. */
584 flag_no_function_cse
= 1;
587 switch (m68k_symbolic_call_var
)
589 case M68K_SYMBOLIC_CALL_JSR
:
590 m68k_symbolic_call
= "jsr %a0";
593 case M68K_SYMBOLIC_CALL_BSR_C
:
594 m68k_symbolic_call
= "bsr%.l %c0";
597 case M68K_SYMBOLIC_CALL_BSR_P
:
598 m68k_symbolic_call
= "bsr%.l %p0";
601 case M68K_SYMBOLIC_CALL_NONE
:
602 gcc_assert (m68k_symbolic_call
== NULL
);
609 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
610 if (align_labels
> 2)
612 warning (0, "-falign-labels=%d is not supported", align_labels
);
617 warning (0, "-falign-loops=%d is not supported", align_loops
);
622 if (stack_limit_rtx
!= NULL_RTX
&& !TARGET_68020
)
624 warning (0, "-fstack-limit- options are not supported on this cpu");
625 stack_limit_rtx
= NULL_RTX
;
628 SUBTARGET_OVERRIDE_OPTIONS
;
630 /* Setup scheduling options. */
632 m68k_sched_cpu
= CPU_CFV1
;
634 m68k_sched_cpu
= CPU_CFV2
;
636 m68k_sched_cpu
= CPU_CFV3
;
638 m68k_sched_cpu
= CPU_CFV4
;
641 m68k_sched_cpu
= CPU_UNKNOWN
;
642 flag_schedule_insns
= 0;
643 flag_schedule_insns_after_reload
= 0;
644 flag_modulo_sched
= 0;
647 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
649 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
650 m68k_sched_mac
= MAC_CF_EMAC
;
651 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
652 m68k_sched_mac
= MAC_CF_MAC
;
654 m68k_sched_mac
= MAC_NO
;
658 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
661 m68k_override_options_after_change (void)
663 if (m68k_sched_cpu
== CPU_UNKNOWN
)
665 flag_schedule_insns
= 0;
666 flag_schedule_insns_after_reload
= 0;
667 flag_modulo_sched
= 0;
671 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
672 given argument and NAME is the argument passed to -mcpu. Return NULL
673 if -mcpu was not passed. */
676 m68k_cpp_cpu_ident (const char *prefix
)
680 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
683 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
684 given argument and NAME is the name of the representative device for
685 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
688 m68k_cpp_cpu_family (const char *prefix
)
692 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
695 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
696 "interrupt_handler" attribute and interrupt_thread if FUNC has an
697 "interrupt_thread" attribute. Otherwise, return
698 m68k_fk_normal_function. */
700 enum m68k_function_kind
701 m68k_get_function_kind (tree func
)
705 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
707 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
709 return m68k_fk_interrupt_handler
;
711 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
713 return m68k_fk_interrupt_handler
;
715 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
717 return m68k_fk_interrupt_thread
;
719 return m68k_fk_normal_function
;
722 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
723 struct attribute_spec.handler. */
725 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
726 tree args ATTRIBUTE_UNUSED
,
727 int flags ATTRIBUTE_UNUSED
,
730 if (TREE_CODE (*node
) != FUNCTION_DECL
)
732 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
734 *no_add_attrs
= true;
737 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
739 error ("multiple interrupt attributes not allowed");
740 *no_add_attrs
= true;
744 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
746 error ("interrupt_thread is available only on fido");
747 *no_add_attrs
= true;
754 m68k_compute_frame_layout (void)
758 enum m68k_function_kind func_kind
=
759 m68k_get_function_kind (current_function_decl
);
760 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
761 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
763 /* Only compute the frame once per function.
764 Don't cache information until reload has been completed. */
765 if (current_frame
.funcdef_no
== current_function_funcdef_no
769 current_frame
.size
= (get_frame_size () + 3) & -4;
773 /* Interrupt thread does not need to save any register. */
774 if (!interrupt_thread
)
775 for (regno
= 0; regno
< 16; regno
++)
776 if (m68k_save_reg (regno
, interrupt_handler
))
778 mask
|= 1 << (regno
- D0_REG
);
781 current_frame
.offset
= saved
* 4;
782 current_frame
.reg_no
= saved
;
783 current_frame
.reg_mask
= mask
;
785 current_frame
.foffset
= 0;
787 if (TARGET_HARD_FLOAT
)
789 /* Interrupt thread does not need to save any register. */
790 if (!interrupt_thread
)
791 for (regno
= 16; regno
< 24; regno
++)
792 if (m68k_save_reg (regno
, interrupt_handler
))
794 mask
|= 1 << (regno
- FP0_REG
);
797 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
798 current_frame
.offset
+= current_frame
.foffset
;
800 current_frame
.fpu_no
= saved
;
801 current_frame
.fpu_mask
= mask
;
803 /* Remember what function this frame refers to. */
804 current_frame
.funcdef_no
= current_function_funcdef_no
;
807 /* Worker function for TARGET_CAN_ELIMINATE. */
810 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
812 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
816 m68k_initial_elimination_offset (int from
, int to
)
819 /* The arg pointer points 8 bytes before the start of the arguments,
820 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
821 frame pointer in most frames. */
822 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
823 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
824 return argptr_offset
;
826 m68k_compute_frame_layout ();
828 gcc_assert (to
== STACK_POINTER_REGNUM
);
831 case ARG_POINTER_REGNUM
:
832 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
833 case FRAME_POINTER_REGNUM
:
834 return current_frame
.offset
+ current_frame
.size
;
840 /* Refer to the array `regs_ever_live' to determine which registers
841 to save; `regs_ever_live[I]' is nonzero if register number I
842 is ever used in the function. This function is responsible for
843 knowing which registers should not be saved even if used.
844 Return true if we need to save REGNO. */
847 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
849 if (flag_pic
&& regno
== PIC_REG
)
851 if (crtl
->saves_all_registers
)
853 if (crtl
->uses_pic_offset_table
)
855 /* Reload may introduce constant pool references into a function
856 that thitherto didn't need a PIC register. Note that the test
857 above will not catch that case because we will only set
858 crtl->uses_pic_offset_table when emitting
859 the address reloads. */
860 if (crtl
->uses_const_pool
)
864 if (crtl
->calls_eh_return
)
869 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
870 if (test
== INVALID_REGNUM
)
877 /* Fixed regs we never touch. */
878 if (fixed_regs
[regno
])
881 /* The frame pointer (if it is such) is handled specially. */
882 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
885 /* Interrupt handlers must also save call_used_regs
886 if they are live or when calling nested functions. */
887 if (interrupt_handler
)
889 if (df_regs_ever_live_p (regno
))
892 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
896 /* Never need to save registers that aren't touched. */
897 if (!df_regs_ever_live_p (regno
))
900 /* Otherwise save everything that isn't call-clobbered. */
901 return !call_used_regs
[regno
];
904 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
905 the lowest memory address. COUNT is the number of registers to be
906 moved, with register REGNO + I being moved if bit I of MASK is set.
907 STORE_P specifies the direction of the move and ADJUST_STACK_P says
908 whether or not this is pre-decrement (if STORE_P) or post-increment
909 (if !STORE_P) operation. */
912 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
913 unsigned int count
, unsigned int regno
,
914 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
917 rtx body
, addr
, src
, operands
[2];
918 enum machine_mode mode
;
920 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
921 mode
= reg_raw_mode
[regno
];
926 src
= plus_constant (Pmode
, base
,
928 * GET_MODE_SIZE (mode
)
929 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
930 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
933 for (; mask
!= 0; mask
>>= 1, regno
++)
936 addr
= plus_constant (Pmode
, base
, offset
);
937 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
938 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
939 XVECEXP (body
, 0, i
++)
940 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
941 offset
+= GET_MODE_SIZE (mode
);
943 gcc_assert (i
== XVECLEN (body
, 0));
945 return emit_insn (body
);
948 /* Make INSN a frame-related instruction. */
951 m68k_set_frame_related (rtx insn
)
956 RTX_FRAME_RELATED_P (insn
) = 1;
957 body
= PATTERN (insn
);
958 if (GET_CODE (body
) == PARALLEL
)
959 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
960 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
963 /* Emit RTL for the "prologue" define_expand. */
966 m68k_expand_prologue (void)
968 HOST_WIDE_INT fsize_with_regs
;
969 rtx limit
, src
, dest
;
971 m68k_compute_frame_layout ();
973 if (flag_stack_usage_info
)
974 current_function_static_stack_size
975 = current_frame
.size
+ current_frame
.offset
;
977 /* If the stack limit is a symbol, we can check it here,
978 before actually allocating the space. */
979 if (crtl
->limit_stack
980 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
982 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
983 if (!m68k_legitimate_constant_p (Pmode
, limit
))
985 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
986 limit
= gen_rtx_REG (Pmode
, D0_REG
);
988 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
989 stack_pointer_rtx
, limit
),
990 stack_pointer_rtx
, limit
,
994 fsize_with_regs
= current_frame
.size
;
997 /* ColdFire's move multiple instructions do not allow pre-decrement
998 addressing. Add the size of movem saves to the initial stack
999 allocation instead. */
1000 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1001 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1002 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1003 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1006 if (frame_pointer_needed
)
1008 if (fsize_with_regs
== 0 && TUNE_68040
)
1010 /* On the 68040, two separate moves are faster than link.w 0. */
1011 dest
= gen_frame_mem (Pmode
,
1012 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1013 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1014 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1015 stack_pointer_rtx
));
1017 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1018 m68k_set_frame_related
1019 (emit_insn (gen_link (frame_pointer_rtx
,
1020 GEN_INT (-4 - fsize_with_regs
))));
1023 m68k_set_frame_related
1024 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1025 m68k_set_frame_related
1026 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1028 GEN_INT (-fsize_with_regs
))));
1031 /* If the frame pointer is needed, emit a special barrier that
1032 will prevent the scheduler from moving stores to the frame
1033 before the stack adjustment. */
1034 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1036 else if (fsize_with_regs
!= 0)
1037 m68k_set_frame_related
1038 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1040 GEN_INT (-fsize_with_regs
))));
1042 if (current_frame
.fpu_mask
)
1044 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1046 m68k_set_frame_related
1047 (m68k_emit_movem (stack_pointer_rtx
,
1048 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1049 current_frame
.fpu_no
, FP0_REG
,
1050 current_frame
.fpu_mask
, true, true));
1055 /* If we're using moveml to save the integer registers,
1056 the stack pointer will point to the bottom of the moveml
1057 save area. Find the stack offset of the first FP register. */
1058 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1061 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1062 m68k_set_frame_related
1063 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1064 current_frame
.fpu_no
, FP0_REG
,
1065 current_frame
.fpu_mask
, true, false));
1069 /* If the stack limit is not a symbol, check it here.
1070 This has the disadvantage that it may be too late... */
1071 if (crtl
->limit_stack
)
1073 if (REG_P (stack_limit_rtx
))
1074 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1076 stack_pointer_rtx
, stack_limit_rtx
,
1079 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1080 warning (0, "stack limit expression is not supported");
1083 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1085 /* Store each register separately in the same order moveml does. */
1088 for (i
= 16; i
-- > 0; )
1089 if (current_frame
.reg_mask
& (1 << i
))
1091 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1092 dest
= gen_frame_mem (SImode
,
1093 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1094 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1099 if (TARGET_COLDFIRE
)
1100 /* The required register save space has already been allocated.
1101 The first register should be stored at (%sp). */
1102 m68k_set_frame_related
1103 (m68k_emit_movem (stack_pointer_rtx
, 0,
1104 current_frame
.reg_no
, D0_REG
,
1105 current_frame
.reg_mask
, true, false));
1107 m68k_set_frame_related
1108 (m68k_emit_movem (stack_pointer_rtx
,
1109 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1110 current_frame
.reg_no
, D0_REG
,
1111 current_frame
.reg_mask
, true, true));
1114 if (!TARGET_SEP_DATA
1115 && crtl
->uses_pic_offset_table
)
1116 emit_insn (gen_load_got (pic_offset_table_rtx
));
1119 /* Return true if a simple (return) instruction is sufficient for this
1120 instruction (i.e. if no epilogue is needed). */
1123 m68k_use_return_insn (void)
1125 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1128 m68k_compute_frame_layout ();
1129 return current_frame
.offset
== 0;
1132 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1133 SIBCALL_P says which.
1135 The function epilogue should not depend on the current stack pointer!
1136 It should use the frame pointer only, if there is a frame pointer.
1137 This is mandatory because of alloca; we also take advantage of it to
1138 omit stack adjustments before returning. */
1141 m68k_expand_epilogue (bool sibcall_p
)
1143 HOST_WIDE_INT fsize
, fsize_with_regs
;
1144 bool big
, restore_from_sp
;
1146 m68k_compute_frame_layout ();
1148 fsize
= current_frame
.size
;
1150 restore_from_sp
= false;
1152 /* FIXME : crtl->is_leaf below is too strong.
1153 What we really need to know there is if there could be pending
1154 stack adjustment needed at that point. */
1155 restore_from_sp
= (!frame_pointer_needed
1156 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1158 /* fsize_with_regs is the size we need to adjust the sp when
1159 popping the frame. */
1160 fsize_with_regs
= fsize
;
1161 if (TARGET_COLDFIRE
&& restore_from_sp
)
1163 /* ColdFire's move multiple instructions do not allow post-increment
1164 addressing. Add the size of movem loads to the final deallocation
1166 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1167 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1168 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1169 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1172 if (current_frame
.offset
+ fsize
>= 0x8000
1174 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1177 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1178 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1180 /* ColdFire's move multiple instructions do not support the
1181 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1182 stack-based restore. */
1183 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1184 GEN_INT (-(current_frame
.offset
+ fsize
)));
1185 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1186 gen_rtx_REG (Pmode
, A1_REG
),
1187 frame_pointer_rtx
));
1188 restore_from_sp
= true;
1192 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1198 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1200 /* Restore each register separately in the same order moveml does. */
1202 HOST_WIDE_INT offset
;
1204 offset
= current_frame
.offset
+ fsize
;
1205 for (i
= 0; i
< 16; i
++)
1206 if (current_frame
.reg_mask
& (1 << i
))
1212 /* Generate the address -OFFSET(%fp,%a1.l). */
1213 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1214 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1215 addr
= plus_constant (Pmode
, addr
, -offset
);
1217 else if (restore_from_sp
)
1218 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1220 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1221 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1222 gen_frame_mem (SImode
, addr
));
1223 offset
-= GET_MODE_SIZE (SImode
);
1226 else if (current_frame
.reg_mask
)
1229 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1230 gen_rtx_REG (Pmode
, A1_REG
),
1232 -(current_frame
.offset
+ fsize
),
1233 current_frame
.reg_no
, D0_REG
,
1234 current_frame
.reg_mask
, false, false);
1235 else if (restore_from_sp
)
1236 m68k_emit_movem (stack_pointer_rtx
, 0,
1237 current_frame
.reg_no
, D0_REG
,
1238 current_frame
.reg_mask
, false,
1241 m68k_emit_movem (frame_pointer_rtx
,
1242 -(current_frame
.offset
+ fsize
),
1243 current_frame
.reg_no
, D0_REG
,
1244 current_frame
.reg_mask
, false, false);
1247 if (current_frame
.fpu_no
> 0)
1250 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1251 gen_rtx_REG (Pmode
, A1_REG
),
1253 -(current_frame
.foffset
+ fsize
),
1254 current_frame
.fpu_no
, FP0_REG
,
1255 current_frame
.fpu_mask
, false, false);
1256 else if (restore_from_sp
)
1258 if (TARGET_COLDFIRE
)
1262 /* If we used moveml to restore the integer registers, the
1263 stack pointer will still point to the bottom of the moveml
1264 save area. Find the stack offset of the first FP
1266 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1269 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1270 m68k_emit_movem (stack_pointer_rtx
, offset
,
1271 current_frame
.fpu_no
, FP0_REG
,
1272 current_frame
.fpu_mask
, false, false);
1275 m68k_emit_movem (stack_pointer_rtx
, 0,
1276 current_frame
.fpu_no
, FP0_REG
,
1277 current_frame
.fpu_mask
, false, true);
1280 m68k_emit_movem (frame_pointer_rtx
,
1281 -(current_frame
.foffset
+ fsize
),
1282 current_frame
.fpu_no
, FP0_REG
,
1283 current_frame
.fpu_mask
, false, false);
1286 if (frame_pointer_needed
)
1287 emit_insn (gen_unlink (frame_pointer_rtx
));
1288 else if (fsize_with_regs
)
1289 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1291 GEN_INT (fsize_with_regs
)));
1293 if (crtl
->calls_eh_return
)
1294 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1296 EH_RETURN_STACKADJ_RTX
));
1299 emit_jump_insn (ret_rtx
);
1302 /* Return true if X is a valid comparison operator for the dbcc
1305 Note it rejects floating point comparison operators.
1306 (In the future we could use Fdbcc).
1308 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1311 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1313 switch (GET_CODE (x
))
1315 case EQ
: case NE
: case GTU
: case LTU
:
1319 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1321 case GT
: case LT
: case GE
: case LE
:
1322 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1328 /* Return nonzero if flags are currently in the 68881 flag register. */
1330 flags_in_68881 (void)
1332 /* We could add support for these in the future */
1333 return cc_status
.flags
& CC_IN_68881
;
1336 /* Return true if PARALLEL contains register REGNO. */
1338 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1342 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1345 if (GET_CODE (parallel
) != PARALLEL
)
1348 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1352 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1353 if (REG_P (x
) && REGNO (x
) == regno
)
1360 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1363 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1365 enum m68k_function_kind kind
;
1367 /* We cannot use sibcalls for nested functions because we use the
1368 static chain register for indirect calls. */
1369 if (CALL_EXPR_STATIC_CHAIN (exp
))
1372 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1374 /* Check that the return value locations are the same. For
1375 example that we aren't returning a value from the sibling in
1376 a D0 register but then need to transfer it to a A0 register. */
1380 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1382 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1384 /* Check that the values are equal or that the result the callee
1385 function returns is superset of what the current function returns. */
1386 if (!(rtx_equal_p (cfun_value
, call_value
)
1387 || (REG_P (cfun_value
)
1388 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1392 kind
= m68k_get_function_kind (current_function_decl
);
1393 if (kind
== m68k_fk_normal_function
)
1394 /* We can always sibcall from a normal function, because it's
1395 undefined if it is calling an interrupt function. */
1398 /* Otherwise we can only sibcall if the function kind is known to be
1400 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1406 /* On the m68k all args are always pushed. */
1409 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1410 enum machine_mode mode ATTRIBUTE_UNUSED
,
1411 const_tree type ATTRIBUTE_UNUSED
,
1412 bool named ATTRIBUTE_UNUSED
)
1418 m68k_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1419 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1421 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1423 *cum
+= (mode
!= BLKmode
1424 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1425 : (int_size_in_bytes (type
) + 3) & ~3);
1428 /* Convert X to a legitimate function call memory reference and return the
1432 m68k_legitimize_call_address (rtx x
)
1434 gcc_assert (MEM_P (x
));
1435 if (call_operand (XEXP (x
, 0), VOIDmode
))
1437 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1440 /* Likewise for sibling calls. */
1443 m68k_legitimize_sibcall_address (rtx x
)
1445 gcc_assert (MEM_P (x
));
1446 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1449 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1450 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1453 /* Convert X to a legitimate address and return it if successful. Otherwise
1456 For the 68000, we handle X+REG by loading X into a register R and
1457 using R+REG. R will go in an address reg and indexing will be used.
1458 However, if REG is a broken-out memory address or multiplication,
1459 nothing needs to be done because REG can certainly go in an address reg. */
1462 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1464 if (m68k_tls_symbol_p (x
))
1465 return m68k_legitimize_tls_address (x
);
1467 if (GET_CODE (x
) == PLUS
)
1469 int ch
= (x
) != (oldx
);
1472 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1474 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1477 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1479 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1482 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1486 if (GET_CODE (XEXP (x
, 1)) == REG
1487 && GET_CODE (XEXP (x
, 0)) == REG
)
1489 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1492 x
= force_operand (x
, 0);
1496 if (memory_address_p (mode
, x
))
1499 if (GET_CODE (XEXP (x
, 0)) == REG
1500 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1501 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1502 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1504 rtx temp
= gen_reg_rtx (Pmode
);
1505 rtx val
= force_operand (XEXP (x
, 1), 0);
1506 emit_move_insn (temp
, val
);
1509 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1510 && GET_CODE (XEXP (x
, 0)) == REG
)
1511 x
= force_operand (x
, 0);
1513 else if (GET_CODE (XEXP (x
, 1)) == REG
1514 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1515 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1516 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1518 rtx temp
= gen_reg_rtx (Pmode
);
1519 rtx val
= force_operand (XEXP (x
, 0), 0);
1520 emit_move_insn (temp
, val
);
1523 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1524 && GET_CODE (XEXP (x
, 1)) == REG
)
1525 x
= force_operand (x
, 0);
1533 /* Output a dbCC; jCC sequence. Note we do not handle the
1534 floating point version of this sequence (Fdbcc). We also
1535 do not handle alternative conditions when CC_NO_OVERFLOW is
1536 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1537 kick those out before we get here. */
1540 output_dbcc_and_branch (rtx
*operands
)
1542 switch (GET_CODE (operands
[3]))
1545 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1549 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1553 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1557 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1561 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1565 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1569 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1573 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1577 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1581 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1588 /* If the decrement is to be done in SImode, then we have
1589 to compensate for the fact that dbcc decrements in HImode. */
1590 switch (GET_MODE (operands
[0]))
1593 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1605 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1608 enum rtx_code op_code
= GET_CODE (op
);
1610 /* This does not produce a useful cc. */
1613 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1614 below. Swap the operands and change the op if these requirements
1615 are not fulfilled. */
1616 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1620 operand1
= operand2
;
1622 op_code
= swap_condition (op_code
);
1624 loperands
[0] = operand1
;
1625 if (GET_CODE (operand1
) == REG
)
1626 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1628 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1629 if (operand2
!= const0_rtx
)
1631 loperands
[2] = operand2
;
1632 if (GET_CODE (operand2
) == REG
)
1633 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1635 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1637 loperands
[4] = gen_label_rtx ();
1638 if (operand2
!= const0_rtx
)
1639 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1642 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1643 output_asm_insn ("tst%.l %0", loperands
);
1645 output_asm_insn ("cmp%.w #0,%0", loperands
);
1647 output_asm_insn ("jne %l4", loperands
);
1649 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1650 output_asm_insn ("tst%.l %1", loperands
);
1652 output_asm_insn ("cmp%.w #0,%1", loperands
);
1655 loperands
[5] = dest
;
1660 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1661 CODE_LABEL_NUMBER (loperands
[4]));
1662 output_asm_insn ("seq %5", loperands
);
1666 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1667 CODE_LABEL_NUMBER (loperands
[4]));
1668 output_asm_insn ("sne %5", loperands
);
1672 loperands
[6] = gen_label_rtx ();
1673 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1674 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1675 CODE_LABEL_NUMBER (loperands
[4]));
1676 output_asm_insn ("sgt %5", loperands
);
1677 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1678 CODE_LABEL_NUMBER (loperands
[6]));
1682 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1683 CODE_LABEL_NUMBER (loperands
[4]));
1684 output_asm_insn ("shi %5", loperands
);
1688 loperands
[6] = gen_label_rtx ();
1689 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1690 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1691 CODE_LABEL_NUMBER (loperands
[4]));
1692 output_asm_insn ("slt %5", loperands
);
1693 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1694 CODE_LABEL_NUMBER (loperands
[6]));
1698 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1699 CODE_LABEL_NUMBER (loperands
[4]));
1700 output_asm_insn ("scs %5", loperands
);
1704 loperands
[6] = gen_label_rtx ();
1705 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1706 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1707 CODE_LABEL_NUMBER (loperands
[4]));
1708 output_asm_insn ("sge %5", loperands
);
1709 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1710 CODE_LABEL_NUMBER (loperands
[6]));
1714 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1715 CODE_LABEL_NUMBER (loperands
[4]));
1716 output_asm_insn ("scc %5", loperands
);
1720 loperands
[6] = gen_label_rtx ();
1721 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1722 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1723 CODE_LABEL_NUMBER (loperands
[4]));
1724 output_asm_insn ("sle %5", loperands
);
1725 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1726 CODE_LABEL_NUMBER (loperands
[6]));
1730 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1731 CODE_LABEL_NUMBER (loperands
[4]));
1732 output_asm_insn ("sls %5", loperands
);
1742 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1744 operands
[0] = countop
;
1745 operands
[1] = dataop
;
1747 if (GET_CODE (countop
) == CONST_INT
)
1749 register int count
= INTVAL (countop
);
1750 /* If COUNT is bigger than size of storage unit in use,
1751 advance to the containing unit of same size. */
1752 if (count
> signpos
)
1754 int offset
= (count
& ~signpos
) / 8;
1755 count
= count
& signpos
;
1756 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1758 if (count
== signpos
)
1759 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1761 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1763 /* These three statements used to use next_insns_test_no...
1764 but it appears that this should do the same job. */
1766 && next_insn_tests_no_inequality (insn
))
1769 && next_insn_tests_no_inequality (insn
))
1772 && next_insn_tests_no_inequality (insn
))
1774 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1775 On some m68k variants unfortunately that's slower than btst.
1776 On 68000 and higher, that should also work for all HImode operands. */
1777 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1779 if (count
== 3 && DATA_REG_P (operands
[1])
1780 && next_insn_tests_no_inequality (insn
))
1782 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1783 return "move%.w %1,%%ccr";
1785 if (count
== 2 && DATA_REG_P (operands
[1])
1786 && next_insn_tests_no_inequality (insn
))
1788 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1789 return "move%.w %1,%%ccr";
1791 /* count == 1 followed by bvc/bvs and
1792 count == 0 followed by bcc/bcs are also possible, but need
1793 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1796 cc_status
.flags
= CC_NOT_NEGATIVE
;
1798 return "btst %0,%1";
1801 /* Return true if X is a legitimate base register. STRICT_P says
1802 whether we need strict checking. */
1805 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1807 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1808 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1813 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1814 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1817 /* Return true if X is a legitimate index register. STRICT_P says
1818 whether we need strict checking. */
1821 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1823 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1828 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1829 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1832 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1833 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1834 ADDRESS if so. STRICT_P says whether we need strict checking. */
1837 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1841 /* Check for a scale factor. */
1843 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1844 && GET_CODE (x
) == MULT
1845 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1846 && (INTVAL (XEXP (x
, 1)) == 2
1847 || INTVAL (XEXP (x
, 1)) == 4
1848 || (INTVAL (XEXP (x
, 1)) == 8
1849 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1851 scale
= INTVAL (XEXP (x
, 1));
1855 /* Check for a word extension. */
1856 if (!TARGET_COLDFIRE
1857 && GET_CODE (x
) == SIGN_EXTEND
1858 && GET_MODE (XEXP (x
, 0)) == HImode
)
1861 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1863 address
->scale
= scale
;
1871 /* Return true if X is an illegitimate symbolic constant. */
1874 m68k_illegitimate_symbolic_constant_p (rtx x
)
1878 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1880 split_const (x
, &base
, &offset
);
1881 if (GET_CODE (base
) == SYMBOL_REF
1882 && !offset_within_block_p (base
, INTVAL (offset
)))
1885 return m68k_tls_reference_p (x
, false);
1888 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1891 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1893 return m68k_illegitimate_symbolic_constant_p (x
);
1896 /* Return true if X is a legitimate constant address that can reach
1897 bytes in the range [X, X + REACH). STRICT_P says whether we need
1901 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1905 if (!CONSTANT_ADDRESS_P (x
))
1909 && !(strict_p
&& TARGET_PCREL
)
1910 && symbolic_operand (x
, VOIDmode
))
1913 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1915 split_const (x
, &base
, &offset
);
1916 if (GET_CODE (base
) == SYMBOL_REF
1917 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1921 return !m68k_tls_reference_p (x
, false);
1924 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1925 labels will become jump tables. */
1928 m68k_jump_table_ref_p (rtx x
)
1930 if (GET_CODE (x
) != LABEL_REF
)
1934 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1937 x
= next_nonnote_insn (x
);
1938 return x
&& JUMP_TABLE_DATA_P (x
);
1941 /* Return true if X is a legitimate address for values of mode MODE.
1942 STRICT_P says whether strict checking is needed. If the address
1943 is valid, describe its components in *ADDRESS. */
1946 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1947 bool strict_p
, struct m68k_address
*address
)
1951 memset (address
, 0, sizeof (*address
));
1953 if (mode
== BLKmode
)
1956 reach
= GET_MODE_SIZE (mode
);
1958 /* Check for (An) (mode 2). */
1959 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1965 /* Check for -(An) and (An)+ (modes 3 and 4). */
1966 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1967 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1969 address
->code
= GET_CODE (x
);
1970 address
->base
= XEXP (x
, 0);
1974 /* Check for (d16,An) (mode 5). */
1975 if (GET_CODE (x
) == PLUS
1976 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1977 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1978 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1980 address
->base
= XEXP (x
, 0);
1981 address
->offset
= XEXP (x
, 1);
1985 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1986 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1988 if (GET_CODE (x
) == PLUS
1989 && XEXP (x
, 0) == pic_offset_table_rtx
)
1991 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
1992 they are invalid in this context. */
1993 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
1995 address
->base
= XEXP (x
, 0);
1996 address
->offset
= XEXP (x
, 1);
2001 /* The ColdFire FPU only accepts addressing modes 2-5. */
2002 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2005 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2006 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2007 All these modes are variations of mode 7. */
2008 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2010 address
->offset
= x
;
2014 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2017 ??? do_tablejump creates these addresses before placing the target
2018 label, so we have to assume that unplaced labels are jump table
2019 references. It seems unlikely that we would ever generate indexed
2020 accesses to unplaced labels in other cases. */
2021 if (GET_CODE (x
) == PLUS
2022 && m68k_jump_table_ref_p (XEXP (x
, 1))
2023 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2025 address
->offset
= XEXP (x
, 1);
2029 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2030 (bd,An,Xn.SIZE*SCALE) addresses. */
2034 /* Check for a nonzero base displacement. */
2035 if (GET_CODE (x
) == PLUS
2036 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2038 address
->offset
= XEXP (x
, 1);
2042 /* Check for a suppressed index register. */
2043 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2049 /* Check for a suppressed base register. Do not allow this case
2050 for non-symbolic offsets as it effectively gives gcc freedom
2051 to treat data registers as base registers, which can generate
2054 && symbolic_operand (address
->offset
, VOIDmode
)
2055 && m68k_decompose_index (x
, strict_p
, address
))
2060 /* Check for a nonzero base displacement. */
2061 if (GET_CODE (x
) == PLUS
2062 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2063 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2065 address
->offset
= XEXP (x
, 1);
2070 /* We now expect the sum of a base and an index. */
2071 if (GET_CODE (x
) == PLUS
)
2073 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2074 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2076 address
->base
= XEXP (x
, 0);
2080 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2081 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2083 address
->base
= XEXP (x
, 1);
2090 /* Return true if X is a legitimate address for values of mode MODE.
2091 STRICT_P says whether strict checking is needed. */
2094 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2096 struct m68k_address address
;
2098 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2101 /* Return true if X is a memory, describing its address in ADDRESS if so.
2102 Apply strict checking if called during or after reload. */
2105 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2108 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2109 reload_in_progress
|| reload_completed
,
2113 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2116 m68k_legitimate_constant_p (enum machine_mode mode
, rtx x
)
2118 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2121 /* Return true if X matches the 'Q' constraint. It must be a memory
2122 with a base address and no constant offset or index. */
2125 m68k_matches_q_p (rtx x
)
2127 struct m68k_address address
;
2129 return (m68k_legitimate_mem_p (x
, &address
)
2130 && address
.code
== UNKNOWN
2136 /* Return true if X matches the 'U' constraint. It must be a base address
2137 with a constant offset and no index. */
2140 m68k_matches_u_p (rtx x
)
2142 struct m68k_address address
;
2144 return (m68k_legitimate_mem_p (x
, &address
)
2145 && address
.code
== UNKNOWN
2151 /* Return GOT pointer. */
2156 if (pic_offset_table_rtx
== NULL_RTX
)
2157 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2159 crtl
->uses_pic_offset_table
= 1;
2161 return pic_offset_table_rtx
;
2164 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2166 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2167 RELOC_TLSIE
, RELOC_TLSLE
};
2169 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2171 /* Wrap symbol X into unspec representing relocation RELOC.
2172 BASE_REG - register that should be added to the result.
2173 TEMP_REG - if non-null, temporary register. */
2176 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2180 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2182 if (TARGET_COLDFIRE
&& use_x_p
)
2183 /* When compiling with -mx{got, tls} switch the code will look like this:
2185 move.l <X>@<RELOC>,<TEMP_REG>
2186 add.l <BASE_REG>,<TEMP_REG> */
2188 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2189 to put @RELOC after reference. */
2190 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2192 x
= gen_rtx_CONST (Pmode
, x
);
2194 if (temp_reg
== NULL
)
2196 gcc_assert (can_create_pseudo_p ());
2197 temp_reg
= gen_reg_rtx (Pmode
);
2200 emit_move_insn (temp_reg
, x
);
2201 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2206 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2208 x
= gen_rtx_CONST (Pmode
, x
);
2210 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2216 /* Helper for m68k_unwrap_symbol.
2217 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2218 sets *RELOC_PTR to relocation type for the symbol. */
2221 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2222 enum m68k_reloc
*reloc_ptr
)
2224 if (GET_CODE (orig
) == CONST
)
2227 enum m68k_reloc dummy
;
2231 if (reloc_ptr
== NULL
)
2234 /* Handle an addend. */
2235 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2236 && CONST_INT_P (XEXP (x
, 1)))
2239 if (GET_CODE (x
) == UNSPEC
)
2241 switch (XINT (x
, 1))
2243 case UNSPEC_RELOC16
:
2244 orig
= XVECEXP (x
, 0, 0);
2245 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2248 case UNSPEC_RELOC32
:
2249 if (unwrap_reloc32_p
)
2251 orig
= XVECEXP (x
, 0, 0);
2252 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2265 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2266 UNSPEC_RELOC32 wrappers. */
2269 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2271 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2274 /* Helper for m68k_final_prescan_insn. */
2277 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2281 if (m68k_unwrap_symbol (x
, true) != x
)
2282 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2286 gcc_assert (GET_CODE (x
) == CONST
);
2289 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2294 unspec
= XEXP (plus
, 0);
2295 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2296 addend
= XEXP (plus
, 1);
2297 gcc_assert (CONST_INT_P (addend
));
2299 /* We now have all the pieces, rearrange them. */
2301 /* Move symbol to plus. */
2302 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2304 /* Move plus inside unspec. */
2305 XVECEXP (unspec
, 0, 0) = plus
;
2307 /* Move unspec to top level of const. */
2308 XEXP (x
, 0) = unspec
;
2317 /* Prescan insn before outputing assembler for it. */
2320 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2321 rtx
*operands
, int n_operands
)
2325 /* Combine and, possibly, other optimizations may do good job
2327 (const (unspec [(symbol)]))
2329 (const (plus (unspec [(symbol)])
2331 The problem with this is emitting @TLS or @GOT decorations.
2332 The decoration is emitted when processing (unspec), so the
2333 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2335 It seems that the easiest solution to this is to convert such
2337 (const (unspec [(plus (symbol)
2339 Note, that the top level of operand remains intact, so we don't have
2340 to patch up anything outside of the operand. */
2342 for (i
= 0; i
< n_operands
; ++i
)
2348 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2352 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2353 If REG is non-null, use it; generate new pseudo otherwise. */
2356 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2360 if (reg
== NULL_RTX
)
2362 gcc_assert (can_create_pseudo_p ());
2363 reg
= gen_reg_rtx (Pmode
);
2366 insn
= emit_move_insn (reg
, x
);
2367 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2369 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2374 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2378 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2380 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2382 x
= gen_rtx_MEM (Pmode
, x
);
2383 MEM_READONLY_P (x
) = 1;
2388 /* Legitimize PIC addresses. If the address is already
2389 position-independent, we return ORIG. Newly generated
2390 position-independent addresses go to REG. If we need more
2391 than one register, we lose.
2393 An address is legitimized by making an indirect reference
2394 through the Global Offset Table with the name of the symbol
2397 The assembler and linker are responsible for placing the
2398 address of the symbol in the GOT. The function prologue
2399 is responsible for initializing a5 to the starting address
2402 The assembler is also responsible for translating a symbol name
2403 into a constant displacement from the start of the GOT.
2405 A quick example may make things a little clearer:
2407 When not generating PIC code to store the value 12345 into _foo
2408 we would generate the following code:
2412 When generating PIC two transformations are made. First, the compiler
2413 loads the address of foo into a register. So the first transformation makes:
2418 The code in movsi will intercept the lea instruction and call this
2419 routine which will transform the instructions into:
2421 movel a5@(_foo:w), a0
2425 That (in a nutshell) is how *all* symbol and label references are
2429 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2434 /* First handle a simple SYMBOL_REF or LABEL_REF */
2435 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2439 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2440 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2442 else if (GET_CODE (orig
) == CONST
)
2446 /* Make sure this has not already been legitimized. */
2447 if (m68k_unwrap_symbol (orig
, true) != orig
)
2452 /* legitimize both operands of the PLUS */
2453 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2455 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2456 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2457 base
== reg
? 0 : reg
);
2459 if (GET_CODE (orig
) == CONST_INT
)
2460 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2462 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2468 /* The __tls_get_addr symbol. */
2469 static GTY(()) rtx m68k_tls_get_addr
;
2471 /* Return SYMBOL_REF for __tls_get_addr. */
2474 m68k_get_tls_get_addr (void)
2476 if (m68k_tls_get_addr
== NULL_RTX
)
2477 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2479 return m68k_tls_get_addr
;
2482 /* Return libcall result in A0 instead of usual D0. */
2483 static bool m68k_libcall_value_in_a0_p
= false;
2485 /* Emit instruction sequence that calls __tls_get_addr. X is
2486 the TLS symbol we are referencing and RELOC is the symbol type to use
2487 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2488 emitted. A pseudo register with result of __tls_get_addr call is
2492 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2498 /* Emit the call sequence. */
2501 /* FIXME: Unfortunately, emit_library_call_value does not
2502 consider (plus (%a5) (const (unspec))) to be a good enough
2503 operand for push, so it forces it into a register. The bad
2504 thing about this is that combiner, due to copy propagation and other
2505 optimizations, sometimes can not later fix this. As a consequence,
2506 additional register may be allocated resulting in a spill.
2507 For reference, see args processing loops in
2508 calls.c:emit_library_call_value_1.
2509 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2510 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2512 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2513 is the simpliest way of generating a call. The difference between
2514 __tls_get_addr() and libcall is that the result is returned in D0
2515 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2516 which temporarily switches returning the result to A0. */
2518 m68k_libcall_value_in_a0_p
= true;
2519 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2520 Pmode
, 1, x
, Pmode
);
2521 m68k_libcall_value_in_a0_p
= false;
2523 insns
= get_insns ();
2526 gcc_assert (can_create_pseudo_p ());
2527 dest
= gen_reg_rtx (Pmode
);
2528 emit_libcall_block (insns
, dest
, a0
, eqv
);
2533 /* The __tls_get_addr symbol. */
2534 static GTY(()) rtx m68k_read_tp
;
2536 /* Return SYMBOL_REF for __m68k_read_tp. */
2539 m68k_get_m68k_read_tp (void)
2541 if (m68k_read_tp
== NULL_RTX
)
2542 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2544 return m68k_read_tp
;
2547 /* Emit instruction sequence that calls __m68k_read_tp.
2548 A pseudo register with result of __m68k_read_tp call is returned. */
2551 m68k_call_m68k_read_tp (void)
2560 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2561 is the simpliest way of generating a call. The difference between
2562 __m68k_read_tp() and libcall is that the result is returned in D0
2563 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2564 which temporarily switches returning the result to A0. */
2566 /* Emit the call sequence. */
2567 m68k_libcall_value_in_a0_p
= true;
2568 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2570 m68k_libcall_value_in_a0_p
= false;
2571 insns
= get_insns ();
2574 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2575 share the m68k_read_tp result with other IE/LE model accesses. */
2576 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2578 gcc_assert (can_create_pseudo_p ());
2579 dest
= gen_reg_rtx (Pmode
);
2580 emit_libcall_block (insns
, dest
, a0
, eqv
);
2585 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2586 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2590 m68k_legitimize_tls_address (rtx orig
)
2592 switch (SYMBOL_REF_TLS_MODEL (orig
))
2594 case TLS_MODEL_GLOBAL_DYNAMIC
:
2595 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2598 case TLS_MODEL_LOCAL_DYNAMIC
:
2604 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2605 share the LDM result with other LD model accesses. */
2606 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2609 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2611 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2613 if (can_create_pseudo_p ())
2614 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2620 case TLS_MODEL_INITIAL_EXEC
:
2625 a0
= m68k_call_m68k_read_tp ();
2627 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2628 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2630 if (can_create_pseudo_p ())
2631 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2637 case TLS_MODEL_LOCAL_EXEC
:
2642 a0
= m68k_call_m68k_read_tp ();
2644 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2646 if (can_create_pseudo_p ())
2647 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2660 /* Return true if X is a TLS symbol. */
2663 m68k_tls_symbol_p (rtx x
)
2665 if (!TARGET_HAVE_TLS
)
2668 if (GET_CODE (x
) != SYMBOL_REF
)
2671 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2674 /* Helper for m68k_tls_referenced_p. */
2677 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2679 /* Note: this is not the same as m68k_tls_symbol_p. */
2680 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2681 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2683 /* Don't recurse into legitimate TLS references. */
2684 if (m68k_tls_reference_p (*x_ptr
, true))
2690 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2691 though illegitimate one.
2692 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2695 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2697 if (!TARGET_HAVE_TLS
)
2701 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2704 enum m68k_reloc reloc
= RELOC_GOT
;
2706 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2707 && TLS_RELOC_P (reloc
));
2713 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2715 /* Return the type of move that should be used for integer I. */
2718 m68k_const_method (HOST_WIDE_INT i
)
2725 /* The ColdFire doesn't have byte or word operations. */
2726 /* FIXME: This may not be useful for the m68060 either. */
2727 if (!TARGET_COLDFIRE
)
2729 /* if -256 < N < 256 but N is not in range for a moveq
2730 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2731 if (USE_MOVQ (i
^ 0xff))
2733 /* Likewise, try with not.w */
2734 if (USE_MOVQ (i
^ 0xffff))
2736 /* This is the only value where neg.w is useful */
2741 /* Try also with swap. */
2743 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2748 /* Try using MVZ/MVS with an immediate value to load constants. */
2749 if (i
>= 0 && i
<= 65535)
2751 if (i
>= -32768 && i
<= 32767)
2755 /* Otherwise, use move.l */
2759 /* Return the cost of moving constant I into a data register. */
2762 const_int_cost (HOST_WIDE_INT i
)
2764 switch (m68k_const_method (i
))
2767 /* Constants between -128 and 127 are cheap due to moveq. */
2775 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2785 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2786 int *total
, bool speed ATTRIBUTE_UNUSED
)
2791 /* Constant zero is super cheap due to clr instruction. */
2792 if (x
== const0_rtx
)
2795 *total
= const_int_cost (INTVAL (x
));
2805 /* Make 0.0 cheaper than other floating constants to
2806 encourage creating tstsf and tstdf insns. */
2807 if (outer_code
== COMPARE
2808 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2814 /* These are vaguely right for a 68020. */
2815 /* The costs for long multiply have been adjusted to work properly
2816 in synth_mult on the 68020, relative to an average of the time
2817 for add and the time for shift, taking away a little more because
2818 sometimes move insns are needed. */
2819 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2824 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2825 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2827 : TARGET_COLDFIRE ? 3 : 13)
2832 : TUNE_68000_10 ? 5 \
2833 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2834 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2836 : TARGET_COLDFIRE ? 2 : 8)
2839 (TARGET_CF_HWDIV ? 11 \
2840 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2843 /* An lea costs about three times as much as a simple add. */
2844 if (GET_MODE (x
) == SImode
2845 && GET_CODE (XEXP (x
, 1)) == REG
2846 && GET_CODE (XEXP (x
, 0)) == MULT
2847 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2848 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2849 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2850 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2851 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2853 /* lea an@(dx:l:i),am */
2854 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2864 *total
= COSTS_N_INSNS(1);
2869 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2871 if (INTVAL (XEXP (x
, 1)) < 16)
2872 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2874 /* We're using clrw + swap for these cases. */
2875 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2878 *total
= COSTS_N_INSNS (10); /* Worst case. */
2881 /* A shift by a big integer takes an extra instruction. */
2882 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2883 && (INTVAL (XEXP (x
, 1)) == 16))
2885 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2888 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2889 && !(INTVAL (XEXP (x
, 1)) > 0
2890 && INTVAL (XEXP (x
, 1)) <= 8))
2892 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2898 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2899 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2900 && GET_MODE (x
) == SImode
)
2901 *total
= COSTS_N_INSNS (MULW_COST
);
2902 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2903 *total
= COSTS_N_INSNS (MULW_COST
);
2905 *total
= COSTS_N_INSNS (MULL_COST
);
2912 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2913 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2914 else if (TARGET_CF_HWDIV
)
2915 *total
= COSTS_N_INSNS (18);
2917 *total
= COSTS_N_INSNS (43); /* div.l */
2921 if (outer_code
== COMPARE
)
2930 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2934 output_move_const_into_data_reg (rtx
*operands
)
2938 i
= INTVAL (operands
[1]);
2939 switch (m68k_const_method (i
))
2942 return "mvzw %1,%0";
2944 return "mvsw %1,%0";
2946 return "moveq %1,%0";
2949 operands
[1] = GEN_INT (i
^ 0xff);
2950 return "moveq %1,%0\n\tnot%.b %0";
2953 operands
[1] = GEN_INT (i
^ 0xffff);
2954 return "moveq %1,%0\n\tnot%.w %0";
2957 return "moveq #-128,%0\n\tneg%.w %0";
2962 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2963 return "moveq %1,%0\n\tswap %0";
2966 return "move%.l %1,%0";
2972 /* Return true if I can be handled by ISA B's mov3q instruction. */
2975 valid_mov3q_const (HOST_WIDE_INT i
)
2977 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2980 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2981 I is the value of OPERANDS[1]. */
2984 output_move_simode_const (rtx
*operands
)
2990 src
= INTVAL (operands
[1]);
2992 && (DATA_REG_P (dest
) || MEM_P (dest
))
2993 /* clr insns on 68000 read before writing. */
2994 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2995 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2997 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2998 return "mov3q%.l %1,%0";
2999 else if (src
== 0 && ADDRESS_REG_P (dest
))
3000 return "sub%.l %0,%0";
3001 else if (DATA_REG_P (dest
))
3002 return output_move_const_into_data_reg (operands
);
3003 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3005 if (valid_mov3q_const (src
))
3006 return "mov3q%.l %1,%0";
3007 return "move%.w %1,%0";
3009 else if (MEM_P (dest
)
3010 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3011 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3012 && IN_RANGE (src
, -0x8000, 0x7fff))
3014 if (valid_mov3q_const (src
))
3015 return "mov3q%.l %1,%-";
3018 return "move%.l %1,%0";
3022 output_move_simode (rtx
*operands
)
3024 if (GET_CODE (operands
[1]) == CONST_INT
)
3025 return output_move_simode_const (operands
);
3026 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3027 || GET_CODE (operands
[1]) == CONST
)
3028 && push_operand (operands
[0], SImode
))
3030 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3031 || GET_CODE (operands
[1]) == CONST
)
3032 && ADDRESS_REG_P (operands
[0]))
3033 return "lea %a1,%0";
3034 return "move%.l %1,%0";
3038 output_move_himode (rtx
*operands
)
3040 if (GET_CODE (operands
[1]) == CONST_INT
)
3042 if (operands
[1] == const0_rtx
3043 && (DATA_REG_P (operands
[0])
3044 || GET_CODE (operands
[0]) == MEM
)
3045 /* clr insns on 68000 read before writing. */
3046 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3047 || !(GET_CODE (operands
[0]) == MEM
3048 && MEM_VOLATILE_P (operands
[0]))))
3050 else if (operands
[1] == const0_rtx
3051 && ADDRESS_REG_P (operands
[0]))
3052 return "sub%.l %0,%0";
3053 else if (DATA_REG_P (operands
[0])
3054 && INTVAL (operands
[1]) < 128
3055 && INTVAL (operands
[1]) >= -128)
3056 return "moveq %1,%0";
3057 else if (INTVAL (operands
[1]) < 0x8000
3058 && INTVAL (operands
[1]) >= -0x8000)
3059 return "move%.w %1,%0";
3061 else if (CONSTANT_P (operands
[1]))
3062 return "move%.l %1,%0";
3063 return "move%.w %1,%0";
3067 output_move_qimode (rtx
*operands
)
3069 /* 68k family always modifies the stack pointer by at least 2, even for
3070 byte pushes. The 5200 (ColdFire) does not do this. */
3072 /* This case is generated by pushqi1 pattern now. */
3073 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3074 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3075 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3076 && ! ADDRESS_REG_P (operands
[1])
3077 && ! TARGET_COLDFIRE
));
3079 /* clr and st insns on 68000 read before writing. */
3080 if (!ADDRESS_REG_P (operands
[0])
3081 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3082 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3084 if (operands
[1] == const0_rtx
)
3086 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3087 && GET_CODE (operands
[1]) == CONST_INT
3088 && (INTVAL (operands
[1]) & 255) == 255)
3094 if (GET_CODE (operands
[1]) == CONST_INT
3095 && DATA_REG_P (operands
[0])
3096 && INTVAL (operands
[1]) < 128
3097 && INTVAL (operands
[1]) >= -128)
3098 return "moveq %1,%0";
3099 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3100 return "sub%.l %0,%0";
3101 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3102 return "move%.l %1,%0";
3103 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3104 from address registers. */
3105 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3106 return "move%.w %1,%0";
3107 return "move%.b %1,%0";
3111 output_move_stricthi (rtx
*operands
)
3113 if (operands
[1] == const0_rtx
3114 /* clr insns on 68000 read before writing. */
3115 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3116 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3118 return "move%.w %1,%0";
3122 output_move_strictqi (rtx
*operands
)
3124 if (operands
[1] == const0_rtx
3125 /* clr insns on 68000 read before writing. */
3126 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3127 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3129 return "move%.b %1,%0";
3132 /* Return the best assembler insn template
3133 for moving operands[1] into operands[0] as a fullword. */
3136 singlemove_string (rtx
*operands
)
3138 if (GET_CODE (operands
[1]) == CONST_INT
)
3139 return output_move_simode_const (operands
);
3140 return "move%.l %1,%0";
3144 /* Output assembler or rtl code to perform a doubleword move insn
3145 with operands OPERANDS.
3146 Pointers to 3 helper functions should be specified:
3147 HANDLE_REG_ADJUST to adjust a register by a small value,
3148 HANDLE_COMPADR to compute an address and
3149 HANDLE_MOVSI to move 4 bytes. */
3152 handle_move_double (rtx operands
[2],
3153 void (*handle_reg_adjust
) (rtx
, int),
3154 void (*handle_compadr
) (rtx
[2]),
3155 void (*handle_movsi
) (rtx
[2]))
3159 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3164 rtx addreg0
= 0, addreg1
= 0;
3165 int dest_overlapped_low
= 0;
3166 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3171 /* First classify both operands. */
3173 if (REG_P (operands
[0]))
3175 else if (offsettable_memref_p (operands
[0]))
3177 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3179 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3181 else if (GET_CODE (operands
[0]) == MEM
)
3186 if (REG_P (operands
[1]))
3188 else if (CONSTANT_P (operands
[1]))
3190 else if (offsettable_memref_p (operands
[1]))
3192 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3194 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3196 else if (GET_CODE (operands
[1]) == MEM
)
3201 /* Check for the cases that the operand constraints are not supposed
3202 to allow to happen. Generating code for these cases is
3204 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3206 /* If one operand is decrementing and one is incrementing
3207 decrement the former register explicitly
3208 and change that operand into ordinary indexing. */
3210 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3212 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3214 handle_reg_adjust (operands
[0], -size
);
3216 if (GET_MODE (operands
[1]) == XFmode
)
3217 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3218 else if (GET_MODE (operands
[0]) == DFmode
)
3219 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3221 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3224 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3226 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3228 handle_reg_adjust (operands
[1], -size
);
3230 if (GET_MODE (operands
[1]) == XFmode
)
3231 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3232 else if (GET_MODE (operands
[1]) == DFmode
)
3233 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3235 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3239 /* If an operand is an unoffsettable memory ref, find a register
3240 we can increment temporarily to make it refer to the second word. */
3242 if (optype0
== MEMOP
)
3243 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3245 if (optype1
== MEMOP
)
3246 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3248 /* Ok, we can do one word at a time.
3249 Normally we do the low-numbered word first,
3250 but if either operand is autodecrementing then we
3251 do the high-numbered word first.
3253 In either case, set up in LATEHALF the operands to use
3254 for the high-numbered word and in some cases alter the
3255 operands in OPERANDS to be suitable for the low-numbered word. */
3259 if (optype0
== REGOP
)
3261 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3262 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3264 else if (optype0
== OFFSOP
)
3266 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3267 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3271 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3272 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3275 if (optype1
== REGOP
)
3277 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3278 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3280 else if (optype1
== OFFSOP
)
3282 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3283 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3285 else if (optype1
== CNSTOP
)
3287 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3292 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3293 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3294 operands
[1] = GEN_INT (l
[0]);
3295 middlehalf
[1] = GEN_INT (l
[1]);
3296 latehalf
[1] = GEN_INT (l
[2]);
3300 /* No non-CONST_DOUBLE constant should ever appear
3302 gcc_assert (!CONSTANT_P (operands
[1]));
3307 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3308 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3312 /* size is not 12: */
3314 if (optype0
== REGOP
)
3315 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3316 else if (optype0
== OFFSOP
)
3317 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3319 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3321 if (optype1
== REGOP
)
3322 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3323 else if (optype1
== OFFSOP
)
3324 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3325 else if (optype1
== CNSTOP
)
3326 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3328 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3331 /* If insn is effectively movd N(sp),-(sp) then we will do the
3332 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3333 for the low word as well, to compensate for the first decrement of sp. */
3334 if (optype0
== PUSHOP
3335 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3336 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3337 operands
[1] = middlehalf
[1] = latehalf
[1];
3339 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3340 if the upper part of reg N does not appear in the MEM, arrange to
3341 emit the move late-half first. Otherwise, compute the MEM address
3342 into the upper part of N and use that as a pointer to the memory
3344 if (optype0
== REGOP
3345 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3347 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3349 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3350 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3352 /* If both halves of dest are used in the src memory address,
3353 compute the address into latehalf of dest.
3354 Note that this can't happen if the dest is two data regs. */
3356 xops
[0] = latehalf
[0];
3357 xops
[1] = XEXP (operands
[1], 0);
3359 handle_compadr (xops
);
3360 if (GET_MODE (operands
[1]) == XFmode
)
3362 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3363 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3364 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3368 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3369 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3373 && reg_overlap_mentioned_p (middlehalf
[0],
3374 XEXP (operands
[1], 0)))
3376 /* Check for two regs used by both source and dest.
3377 Note that this can't happen if the dest is all data regs.
3378 It can happen if the dest is d6, d7, a0.
3379 But in that case, latehalf is an addr reg, so
3380 the code at compadr does ok. */
3382 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3383 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3386 /* JRV says this can't happen: */
3387 gcc_assert (!addreg0
&& !addreg1
);
3389 /* Only the middle reg conflicts; simply put it last. */
3390 handle_movsi (operands
);
3391 handle_movsi (latehalf
);
3392 handle_movsi (middlehalf
);
3396 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3397 /* If the low half of dest is mentioned in the source memory
3398 address, the arrange to emit the move late half first. */
3399 dest_overlapped_low
= 1;
3402 /* If one or both operands autodecrementing,
3403 do the two words, high-numbered first. */
3405 /* Likewise, the first move would clobber the source of the second one,
3406 do them in the other order. This happens only for registers;
3407 such overlap can't happen in memory unless the user explicitly
3408 sets it up, and that is an undefined circumstance. */
3410 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3411 || (optype0
== REGOP
&& optype1
== REGOP
3412 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3413 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3414 || dest_overlapped_low
)
3416 /* Make any unoffsettable addresses point at high-numbered word. */
3418 handle_reg_adjust (addreg0
, size
- 4);
3420 handle_reg_adjust (addreg1
, size
- 4);
3423 handle_movsi (latehalf
);
3425 /* Undo the adds we just did. */
3427 handle_reg_adjust (addreg0
, -4);
3429 handle_reg_adjust (addreg1
, -4);
3433 handle_movsi (middlehalf
);
3436 handle_reg_adjust (addreg0
, -4);
3438 handle_reg_adjust (addreg1
, -4);
3441 /* Do low-numbered word. */
3443 handle_movsi (operands
);
3447 /* Normal case: do the two words, low-numbered first. */
3449 m68k_final_prescan_insn (NULL
, operands
, 2);
3450 handle_movsi (operands
);
3452 /* Do the middle one of the three words for long double */
3456 handle_reg_adjust (addreg0
, 4);
3458 handle_reg_adjust (addreg1
, 4);
3460 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3461 handle_movsi (middlehalf
);
3464 /* Make any unoffsettable addresses point at high-numbered word. */
3466 handle_reg_adjust (addreg0
, 4);
3468 handle_reg_adjust (addreg1
, 4);
3471 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3472 handle_movsi (latehalf
);
3474 /* Undo the adds we just did. */
3476 handle_reg_adjust (addreg0
, -(size
- 4));
3478 handle_reg_adjust (addreg1
, -(size
- 4));
3483 /* Output assembler code to adjust REG by N. */
3485 output_reg_adjust (rtx reg
, int n
)
3489 gcc_assert (GET_MODE (reg
) == SImode
3490 && -12 <= n
&& n
!= 0 && n
<= 12);
3495 s
= "add%.l #12,%0";
3499 s
= "addq%.l #8,%0";
3503 s
= "addq%.l #4,%0";
3507 s
= "sub%.l #12,%0";
3511 s
= "subq%.l #8,%0";
3515 s
= "subq%.l #4,%0";
3523 output_asm_insn (s
, ®
);
3526 /* Emit rtl code to adjust REG by N. */
3528 emit_reg_adjust (rtx reg1
, int n
)
3532 gcc_assert (GET_MODE (reg1
) == SImode
3533 && -12 <= n
&& n
!= 0 && n
<= 12);
3535 reg1
= copy_rtx (reg1
);
3536 reg2
= copy_rtx (reg1
);
3539 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3541 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3546 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3548 output_compadr (rtx operands
[2])
3550 output_asm_insn ("lea %a1,%0", operands
);
3553 /* Output the best assembler insn for moving operands[1] into operands[0]
3556 output_movsi (rtx operands
[2])
3558 output_asm_insn (singlemove_string (operands
), operands
);
3561 /* Copy OP and change its mode to MODE. */
3563 copy_operand (rtx op
, enum machine_mode mode
)
3565 /* ??? This looks really ugly. There must be a better way
3566 to change a mode on the operand. */
3567 if (GET_MODE (op
) != VOIDmode
)
3570 op
= gen_rtx_REG (mode
, REGNO (op
));
3574 PUT_MODE (op
, mode
);
3581 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3583 emit_movsi (rtx operands
[2])
3585 operands
[0] = copy_operand (operands
[0], SImode
);
3586 operands
[1] = copy_operand (operands
[1], SImode
);
3588 emit_insn (gen_movsi (operands
[0], operands
[1]));
3591 /* Output assembler code to perform a doubleword move insn
3592 with operands OPERANDS. */
3594 output_move_double (rtx
*operands
)
3596 handle_move_double (operands
,
3597 output_reg_adjust
, output_compadr
, output_movsi
);
3602 /* Output rtl code to perform a doubleword move insn
3603 with operands OPERANDS. */
3605 m68k_emit_move_double (rtx operands
[2])
3607 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3610 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3611 new rtx with the correct mode. */
3614 force_mode (enum machine_mode mode
, rtx orig
)
3616 if (mode
== GET_MODE (orig
))
3619 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3622 return gen_rtx_REG (mode
, REGNO (orig
));
3626 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3628 return reg_renumber
&& FP_REG_P (op
);
3631 /* Emit insns to move operands[1] into operands[0].
3633 Return 1 if we have written out everything that needs to be done to
3634 do the move. Otherwise, return 0 and the caller will emit the move
3637 Note SCRATCH_REG may not be in the proper mode depending on how it
3638 will be used. This routine is responsible for creating a new copy
3639 of SCRATCH_REG in the proper mode. */
3642 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3644 register rtx operand0
= operands
[0];
3645 register rtx operand1
= operands
[1];
3649 && reload_in_progress
&& GET_CODE (operand0
) == REG
3650 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3651 operand0
= reg_equiv_mem (REGNO (operand0
));
3652 else if (scratch_reg
3653 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3654 && GET_CODE (SUBREG_REG (operand0
)) == REG
3655 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3657 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3658 the code which tracks sets/uses for delete_output_reload. */
3659 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3660 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3661 SUBREG_BYTE (operand0
));
3662 operand0
= alter_subreg (&temp
, true);
3666 && reload_in_progress
&& GET_CODE (operand1
) == REG
3667 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3668 operand1
= reg_equiv_mem (REGNO (operand1
));
3669 else if (scratch_reg
3670 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3671 && GET_CODE (SUBREG_REG (operand1
)) == REG
3672 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3674 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3675 the code which tracks sets/uses for delete_output_reload. */
3676 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3677 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3678 SUBREG_BYTE (operand1
));
3679 operand1
= alter_subreg (&temp
, true);
3682 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3683 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3684 != XEXP (operand0
, 0)))
3685 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3686 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3687 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3688 != XEXP (operand1
, 0)))
3689 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3691 /* Handle secondary reloads for loads/stores of FP registers where
3692 the address is symbolic by using the scratch register */
3693 if (fp_reg_operand (operand0
, mode
)
3694 && ((GET_CODE (operand1
) == MEM
3695 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3696 || ((GET_CODE (operand1
) == SUBREG
3697 && GET_CODE (XEXP (operand1
, 0)) == MEM
3698 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3701 if (GET_CODE (operand1
) == SUBREG
)
3702 operand1
= XEXP (operand1
, 0);
3704 /* SCRATCH_REG will hold an address. We want
3705 it in SImode regardless of what mode it was originally given
3707 scratch_reg
= force_mode (SImode
, scratch_reg
);
3709 /* D might not fit in 14 bits either; for such cases load D into
3711 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3713 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3714 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3716 XEXP (XEXP (operand1
, 0), 0),
3720 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3721 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3722 gen_rtx_MEM (mode
, scratch_reg
)));
3725 else if (fp_reg_operand (operand1
, mode
)
3726 && ((GET_CODE (operand0
) == MEM
3727 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3728 || ((GET_CODE (operand0
) == SUBREG
)
3729 && GET_CODE (XEXP (operand0
, 0)) == MEM
3730 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3733 if (GET_CODE (operand0
) == SUBREG
)
3734 operand0
= XEXP (operand0
, 0);
3736 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3737 it in SIMODE regardless of what mode it was originally given
3739 scratch_reg
= force_mode (SImode
, scratch_reg
);
3741 /* D might not fit in 14 bits either; for such cases load D into
3743 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3745 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3746 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3749 XEXP (XEXP (operand0
, 0),
3754 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3755 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3759 /* Handle secondary reloads for loads of FP registers from constant
3760 expressions by forcing the constant into memory.
3762 use scratch_reg to hold the address of the memory location.
3764 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3765 NO_REGS when presented with a const_int and an register class
3766 containing only FP registers. Doing so unfortunately creates
3767 more problems than it solves. Fix this for 2.5. */
3768 else if (fp_reg_operand (operand0
, mode
)
3769 && CONSTANT_P (operand1
)
3774 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3775 it in SIMODE regardless of what mode it was originally given
3777 scratch_reg
= force_mode (SImode
, scratch_reg
);
3779 /* Force the constant into memory and put the address of the
3780 memory location into scratch_reg. */
3781 xoperands
[0] = scratch_reg
;
3782 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3783 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3785 /* Now load the destination register. */
3786 emit_insn (gen_rtx_SET (mode
, operand0
,
3787 gen_rtx_MEM (mode
, scratch_reg
)));
3791 /* Now have insn-emit do whatever it normally does. */
3795 /* Split one or more DImode RTL references into pairs of SImode
3796 references. The RTL can be REG, offsettable MEM, integer constant, or
3797 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3798 split and "num" is its length. lo_half and hi_half are output arrays
3799 that parallel "operands". */
3802 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3806 rtx op
= operands
[num
];
3808 /* simplify_subreg refuses to split volatile memory addresses,
3809 but we still have to handle it. */
3810 if (GET_CODE (op
) == MEM
)
3812 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3813 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3817 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3818 GET_MODE (op
) == VOIDmode
3819 ? DImode
: GET_MODE (op
), 4);
3820 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3821 GET_MODE (op
) == VOIDmode
3822 ? DImode
: GET_MODE (op
), 0);
3827 /* Split X into a base and a constant offset, storing them in *BASE
3828 and *OFFSET respectively. */
3831 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3834 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3836 *offset
+= INTVAL (XEXP (x
, 1));
3842 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3843 instruction. STORE_P says whether the move is a load or store.
3845 If the instruction uses post-increment or pre-decrement addressing,
3846 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3847 adjustment. This adjustment will be made by the first element of
3848 PARALLEL, with the loads or stores starting at element 1. If the
3849 instruction does not use post-increment or pre-decrement addressing,
3850 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3851 start at element 0. */
3854 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3855 HOST_WIDE_INT automod_offset
, bool store_p
)
3857 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3858 HOST_WIDE_INT offset
, mem_offset
;
3860 enum reg_class rclass
;
3862 len
= XVECLEN (pattern
, 0);
3863 first
= (automod_base
!= NULL
);
3867 /* Stores must be pre-decrement and loads must be post-increment. */
3868 if (store_p
!= (automod_offset
< 0))
3871 /* Work out the base and offset for lowest memory location. */
3872 base
= automod_base
;
3873 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3877 /* Allow any valid base and offset in the first access. */
3884 for (i
= first
; i
< len
; i
++)
3886 /* We need a plain SET. */
3887 set
= XVECEXP (pattern
, 0, i
);
3888 if (GET_CODE (set
) != SET
)
3891 /* Check that we have a memory location... */
3892 mem
= XEXP (set
, !store_p
);
3893 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3896 /* ...with the right address. */
3899 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3900 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3901 There are no mode restrictions for 680x0 besides the
3902 automodification rules enforced above. */
3904 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3909 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3910 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3914 /* Check that we have a register of the required mode and class. */
3915 reg
= XEXP (set
, store_p
);
3917 || !HARD_REGISTER_P (reg
)
3918 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3923 /* The register must belong to RCLASS and have a higher number
3924 than the register in the previous SET. */
3925 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3926 || REGNO (last_reg
) >= REGNO (reg
))
3931 /* Work out which register class we need. */
3932 if (INT_REGNO_P (REGNO (reg
)))
3933 rclass
= GENERAL_REGS
;
3934 else if (FP_REGNO_P (REGNO (reg
)))
3941 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3944 /* If we have an automodification, check whether the final offset is OK. */
3945 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3948 /* Reject unprofitable cases. */
3949 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3955 /* Return the assembly code template for a movem or fmovem instruction
3956 whose pattern is given by PATTERN. Store the template's operands
3959 If the instruction uses post-increment or pre-decrement addressing,
3960 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3961 is true if this is a store instruction. */
3964 m68k_output_movem (rtx
*operands
, rtx pattern
,
3965 HOST_WIDE_INT automod_offset
, bool store_p
)
3970 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3972 first
= (automod_offset
!= 0);
3973 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3975 /* When using movem with pre-decrement addressing, register X + D0_REG
3976 is controlled by bit 15 - X. For all other addressing modes,
3977 register X + D0_REG is controlled by bit X. Confusingly, the
3978 register mask for fmovem is in the opposite order to that for
3982 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3983 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3984 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3985 if (automod_offset
< 0)
3987 if (FP_REGNO_P (regno
))
3988 mask
|= 1 << (regno
- FP0_REG
);
3990 mask
|= 1 << (15 - (regno
- D0_REG
));
3994 if (FP_REGNO_P (regno
))
3995 mask
|= 1 << (7 - (regno
- FP0_REG
));
3997 mask
|= 1 << (regno
- D0_REG
);
4002 if (automod_offset
== 0)
4003 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4004 else if (automod_offset
< 0)
4005 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4007 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4008 operands
[1] = GEN_INT (mask
);
4009 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4012 return "fmovem %1,%a0";
4014 return "fmovem %a0,%1";
4019 return "movem%.l %1,%a0";
4021 return "movem%.l %a0,%1";
4025 /* Return a REG that occurs in ADDR with coefficient 1.
4026 ADDR can be effectively incremented by incrementing REG. */
4029 find_addr_reg (rtx addr
)
4031 while (GET_CODE (addr
) == PLUS
)
4033 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4034 addr
= XEXP (addr
, 0);
4035 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4036 addr
= XEXP (addr
, 1);
4037 else if (CONSTANT_P (XEXP (addr
, 0)))
4038 addr
= XEXP (addr
, 1);
4039 else if (CONSTANT_P (XEXP (addr
, 1)))
4040 addr
= XEXP (addr
, 0);
4044 gcc_assert (GET_CODE (addr
) == REG
);
4048 /* Output assembler code to perform a 32-bit 3-operand add. */
4051 output_addsi3 (rtx
*operands
)
4053 if (! operands_match_p (operands
[0], operands
[1]))
4055 if (!ADDRESS_REG_P (operands
[1]))
4057 rtx tmp
= operands
[1];
4059 operands
[1] = operands
[2];
4063 /* These insns can result from reloads to access
4064 stack slots over 64k from the frame pointer. */
4065 if (GET_CODE (operands
[2]) == CONST_INT
4066 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4067 return "move%.l %2,%0\n\tadd%.l %1,%0";
4068 if (GET_CODE (operands
[2]) == REG
)
4069 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4070 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4072 if (GET_CODE (operands
[2]) == CONST_INT
)
4074 if (INTVAL (operands
[2]) > 0
4075 && INTVAL (operands
[2]) <= 8)
4076 return "addq%.l %2,%0";
4077 if (INTVAL (operands
[2]) < 0
4078 && INTVAL (operands
[2]) >= -8)
4080 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4081 return "subq%.l %2,%0";
4083 /* On the CPU32 it is faster to use two addql instructions to
4084 add a small integer (8 < N <= 16) to a register.
4085 Likewise for subql. */
4086 if (TUNE_CPU32
&& REG_P (operands
[0]))
4088 if (INTVAL (operands
[2]) > 8
4089 && INTVAL (operands
[2]) <= 16)
4091 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4092 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4094 if (INTVAL (operands
[2]) < -8
4095 && INTVAL (operands
[2]) >= -16)
4097 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4098 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4101 if (ADDRESS_REG_P (operands
[0])
4102 && INTVAL (operands
[2]) >= -0x8000
4103 && INTVAL (operands
[2]) < 0x8000)
4106 return "add%.w %2,%0";
4108 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4111 return "add%.l %2,%0";
4114 /* Store in cc_status the expressions that the condition codes will
4115 describe after execution of an instruction whose pattern is EXP.
4116 Do not alter them if the instruction would not alter the cc's. */
4118 /* On the 68000, all the insns to store in an address register fail to
4119 set the cc's. However, in some cases these instructions can make it
4120 possibly invalid to use the saved cc's. In those cases we clear out
4121 some or all of the saved cc's so they won't be used. */
4124 notice_update_cc (rtx exp
, rtx insn
)
4126 if (GET_CODE (exp
) == SET
)
4128 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4130 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4132 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4133 cc_status
.value1
= 0;
4134 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4135 cc_status
.value2
= 0;
4137 /* fmoves to memory or data registers do not set the condition
4138 codes. Normal moves _do_ set the condition codes, but not in
4139 a way that is appropriate for comparison with 0, because -0.0
4140 would be treated as a negative nonzero number. Note that it
4141 isn't appropriate to conditionalize this restriction on
4142 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4143 we care about the difference between -0.0 and +0.0. */
4144 else if (!FP_REG_P (SET_DEST (exp
))
4145 && SET_DEST (exp
) != cc0_rtx
4146 && (FP_REG_P (SET_SRC (exp
))
4147 || GET_CODE (SET_SRC (exp
)) == FIX
4148 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4150 /* A pair of move insns doesn't produce a useful overall cc. */
4151 else if (!FP_REG_P (SET_DEST (exp
))
4152 && !FP_REG_P (SET_SRC (exp
))
4153 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4154 && (GET_CODE (SET_SRC (exp
)) == REG
4155 || GET_CODE (SET_SRC (exp
)) == MEM
4156 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4158 else if (SET_DEST (exp
) != pc_rtx
)
4160 cc_status
.flags
= 0;
4161 cc_status
.value1
= SET_DEST (exp
);
4162 cc_status
.value2
= SET_SRC (exp
);
4165 else if (GET_CODE (exp
) == PARALLEL
4166 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4168 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4169 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4171 if (ADDRESS_REG_P (dest
))
4173 else if (dest
!= pc_rtx
)
4175 cc_status
.flags
= 0;
4176 cc_status
.value1
= dest
;
4177 cc_status
.value2
= src
;
4182 if (cc_status
.value2
!= 0
4183 && ADDRESS_REG_P (cc_status
.value2
)
4184 && GET_MODE (cc_status
.value2
) == QImode
)
4186 if (cc_status
.value2
!= 0)
4187 switch (GET_CODE (cc_status
.value2
))
4189 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4190 case ROTATE
: case ROTATERT
:
4191 /* These instructions always clear the overflow bit, and set
4192 the carry to the bit shifted out. */
4193 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4196 case PLUS
: case MINUS
: case MULT
:
4197 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4198 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4199 cc_status
.flags
|= CC_NO_OVERFLOW
;
4202 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4203 ends with a move insn moving r2 in r2's mode.
4204 Thus, the cc's are set for r2.
4205 This can set N bit spuriously. */
4206 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4211 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4213 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4214 cc_status
.value2
= 0;
4215 /* Check for PRE_DEC in dest modifying a register used in src. */
4216 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4217 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4219 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4221 cc_status
.value2
= 0;
4222 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4223 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4224 cc_status
.flags
= CC_IN_68881
;
4225 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4226 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4228 cc_status
.flags
= CC_IN_68881
;
4229 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4230 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4231 cc_status
.flags
|= CC_REVERSED
;
4236 output_move_const_double (rtx
*operands
)
4238 int code
= standard_68881_constant_p (operands
[1]);
4242 static char buf
[40];
4244 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4247 return "fmove%.d %1,%0";
4251 output_move_const_single (rtx
*operands
)
4253 int code
= standard_68881_constant_p (operands
[1]);
4257 static char buf
[40];
4259 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4262 return "fmove%.s %f1,%0";
4265 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4266 from the "fmovecr" instruction.
4267 The value, anded with 0xff, gives the code to use in fmovecr
4268 to get the desired constant. */
4270 /* This code has been fixed for cross-compilation. */
4272 static int inited_68881_table
= 0;
4274 static const char *const strings_68881
[7] = {
4284 static const int codes_68881
[7] = {
4294 REAL_VALUE_TYPE values_68881
[7];
4296 /* Set up values_68881 array by converting the decimal values
4297 strings_68881 to binary. */
4300 init_68881_table (void)
4304 enum machine_mode mode
;
4307 for (i
= 0; i
< 7; i
++)
4311 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4312 values_68881
[i
] = r
;
4314 inited_68881_table
= 1;
4318 standard_68881_constant_p (rtx x
)
4323 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4324 used at all on those chips. */
4328 if (! inited_68881_table
)
4329 init_68881_table ();
4331 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4333 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4335 for (i
= 0; i
< 6; i
++)
4337 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4338 return (codes_68881
[i
]);
4341 if (GET_MODE (x
) == SFmode
)
4344 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4345 return (codes_68881
[6]);
4347 /* larger powers of ten in the constants ram are not used
4348 because they are not equal to a `double' C constant. */
4352 /* If X is a floating-point constant, return the logarithm of X base 2,
4353 or 0 if X is not a power of 2. */
4356 floating_exact_log2 (rtx x
)
4358 REAL_VALUE_TYPE r
, r1
;
4361 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4363 if (REAL_VALUES_LESS (r
, dconst1
))
4366 exp
= real_exponent (&r
);
4367 real_2expN (&r1
, exp
, DFmode
);
4368 if (REAL_VALUES_EQUAL (r1
, r
))
4374 /* A C compound statement to output to stdio stream STREAM the
4375 assembler syntax for an instruction operand X. X is an RTL
4378 CODE is a value that can be used to specify one of several ways
4379 of printing the operand. It is used when identical operands
4380 must be printed differently depending on the context. CODE
4381 comes from the `%' specification that was used to request
4382 printing of the operand. If the specification was just `%DIGIT'
4383 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4384 is the ASCII code for LTR.
4386 If X is a register, this macro should print the register's name.
4387 The names can be found in an array `reg_names' whose type is
4388 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4390 When the machine description has a specification `%PUNCT' (a `%'
4391 followed by a punctuation character), this macro is called with
4392 a null pointer for X and the punctuation character for CODE.
4394 The m68k specific codes are:
4396 '.' for dot needed in Motorola-style opcode names.
4397 '-' for an operand pushing on the stack:
4398 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4399 '+' for an operand pushing on the stack:
4400 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4401 '@' for a reference to the top word on the stack:
4402 sp@, (sp) or (%sp) depending on the style of syntax.
4403 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4404 but & in SGS syntax).
4405 '!' for the cc register (used in an `and to cc' insn).
4406 '$' for the letter `s' in an op code, but only on the 68040.
4407 '&' for the letter `d' in an op code, but only on the 68040.
4408 '/' for register prefix needed by longlong.h.
4409 '?' for m68k_library_id_string
4411 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4412 'd' to force memory addressing to be absolute, not relative.
4413 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4414 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4415 or print pair of registers as rx:ry.
4416 'p' print an address with @PLTPC attached, but only if the operand
4417 is not locally-bound. */
4420 print_operand (FILE *file
, rtx op
, int letter
)
4425 fprintf (file
, ".");
4427 else if (letter
== '#')
4428 asm_fprintf (file
, "%I");
4429 else if (letter
== '-')
4430 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4431 else if (letter
== '+')
4432 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4433 else if (letter
== '@')
4434 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4435 else if (letter
== '!')
4436 asm_fprintf (file
, "%Rfpcr");
4437 else if (letter
== '$')
4440 fprintf (file
, "s");
4442 else if (letter
== '&')
4445 fprintf (file
, "d");
4447 else if (letter
== '/')
4448 asm_fprintf (file
, "%R");
4449 else if (letter
== '?')
4450 asm_fprintf (file
, m68k_library_id_string
);
4451 else if (letter
== 'p')
4453 output_addr_const (file
, op
);
4454 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4455 fprintf (file
, "@PLTPC");
4457 else if (GET_CODE (op
) == REG
)
4460 /* Print out the second register name of a register pair.
4461 I.e., R (6) => 7. */
4462 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4464 fputs (M68K_REGNAME(REGNO (op
)), file
);
4466 else if (GET_CODE (op
) == MEM
)
4468 output_address (XEXP (op
, 0));
4469 if (letter
== 'd' && ! TARGET_68020
4470 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4471 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4472 && INTVAL (XEXP (op
, 0)) < 0x8000
4473 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4474 fprintf (file
, MOTOROLA
? ".l" : ":l");
4476 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4480 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4481 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4482 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4484 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4488 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4489 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4490 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4491 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4493 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4497 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4498 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4499 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4503 /* Use `print_operand_address' instead of `output_addr_const'
4504 to ensure that we print relevant PIC stuff. */
4505 asm_fprintf (file
, "%I");
4507 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4508 print_operand_address (file
, op
);
4510 output_addr_const (file
, op
);
4514 /* Return string for TLS relocation RELOC. */
4517 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4519 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4520 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4527 if (flag_pic
== 1 && TARGET_68020
)
4568 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4571 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4573 if (GET_CODE (x
) == UNSPEC
)
4575 switch (XINT (x
, 1))
4577 case UNSPEC_RELOC16
:
4578 case UNSPEC_RELOC32
:
4579 output_addr_const (file
, XVECEXP (x
, 0, 0));
4580 fputs (m68k_get_reloc_decoration
4581 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4592 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4595 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4597 gcc_assert (size
== 4);
4598 fputs ("\t.long\t", file
);
4599 output_addr_const (file
, x
);
4600 fputs ("@TLSLDO+0x8000", file
);
4603 /* In the name of slightly smaller debug output, and to cater to
4604 general assembler lossage, recognize various UNSPEC sequences
4605 and turn them back into a direct symbol reference. */
4608 m68k_delegitimize_address (rtx orig_x
)
4611 struct m68k_address addr
;
4614 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4619 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4622 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4623 || addr
.offset
== NULL_RTX
4624 || GET_CODE (addr
.offset
) != CONST
)
4627 unspec
= XEXP (addr
.offset
, 0);
4628 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4629 unspec
= XEXP (unspec
, 0);
4630 if (GET_CODE (unspec
) != UNSPEC
4631 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4632 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4634 x
= XVECEXP (unspec
, 0, 0);
4635 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4636 if (unspec
!= XEXP (addr
.offset
, 0))
4637 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4640 rtx idx
= addr
.index
;
4641 if (addr
.scale
!= 1)
4642 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4643 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4646 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4648 x
= replace_equiv_address_nv (orig_x
, x
);
4653 /* A C compound statement to output to stdio stream STREAM the
4654 assembler syntax for an instruction operand that is a memory
4655 reference whose address is ADDR. ADDR is an RTL expression.
4657 Note that this contains a kludge that knows that the only reason
4658 we have an address (plus (label_ref...) (reg...)) when not generating
4659 PIC code is in the insn before a tablejump, and we know that m68k.md
4660 generates a label LInnn: on such an insn.
4662 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4663 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4665 This routine is responsible for distinguishing between -fpic and -fPIC
4666 style relocations in an address. When generating -fpic code the
4667 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4668 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4671 print_operand_address (FILE *file
, rtx addr
)
4673 struct m68k_address address
;
4675 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4678 if (address
.code
== PRE_DEC
)
4679 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4680 M68K_REGNAME (REGNO (address
.base
)));
4681 else if (address
.code
== POST_INC
)
4682 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4683 M68K_REGNAME (REGNO (address
.base
)));
4684 else if (!address
.base
&& !address
.index
)
4686 /* A constant address. */
4687 gcc_assert (address
.offset
== addr
);
4688 if (GET_CODE (addr
) == CONST_INT
)
4690 /* (xxx).w or (xxx).l. */
4691 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4692 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4694 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4696 else if (TARGET_PCREL
)
4698 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4700 output_addr_const (file
, addr
);
4701 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4705 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4706 name ends in `.<letter>', as the last 2 characters can be
4707 mistaken as a size suffix. Put the name in parentheses. */
4708 if (GET_CODE (addr
) == SYMBOL_REF
4709 && strlen (XSTR (addr
, 0)) > 2
4710 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4713 output_addr_const (file
, addr
);
4717 output_addr_const (file
, addr
);
4724 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4725 label being accessed, otherwise it is -1. */
4726 labelno
= (address
.offset
4728 && GET_CODE (address
.offset
) == LABEL_REF
4729 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4733 /* Print the "offset(base" component. */
4735 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4739 output_addr_const (file
, address
.offset
);
4743 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4745 /* Print the ",index" component, if any. */
4750 fprintf (file
, "%s.%c",
4751 M68K_REGNAME (REGNO (address
.index
)),
4752 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4753 if (address
.scale
!= 1)
4754 fprintf (file
, "*%d", address
.scale
);
4758 else /* !MOTOROLA */
4760 if (!address
.offset
&& !address
.index
)
4761 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4764 /* Print the "base@(offset" component. */
4766 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4770 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4771 fprintf (file
, "@(");
4773 output_addr_const (file
, address
.offset
);
4775 /* Print the ",index" component, if any. */
4778 fprintf (file
, ",%s:%c",
4779 M68K_REGNAME (REGNO (address
.index
)),
4780 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4781 if (address
.scale
!= 1)
4782 fprintf (file
, ":%d", address
.scale
);
4790 /* Check for cases where a clr insns can be omitted from code using
4791 strict_low_part sets. For example, the second clrl here is not needed:
4792 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4794 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4795 insn we are checking for redundancy. TARGET is the register set by the
4799 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4804 while ((p
= PREV_INSN (p
)))
4806 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4812 /* If it isn't an insn, then give up. */
4816 if (reg_set_p (target
, p
))
4818 rtx set
= single_set (p
);
4821 /* If it isn't an easy to recognize insn, then give up. */
4825 dest
= SET_DEST (set
);
4827 /* If this sets the entire target register to zero, then our
4828 first_insn is redundant. */
4829 if (rtx_equal_p (dest
, target
)
4830 && SET_SRC (set
) == const0_rtx
)
4832 else if (GET_CODE (dest
) == STRICT_LOW_PART
4833 && GET_CODE (XEXP (dest
, 0)) == REG
4834 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4835 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4836 <= GET_MODE_SIZE (mode
)))
4837 /* This is a strict low part set which modifies less than
4838 we are using, so it is safe. */
4848 /* Operand predicates for implementing asymmetric pc-relative addressing
4849 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4850 when used as a source operand, but not as a destination operand.
4852 We model this by restricting the meaning of the basic predicates
4853 (general_operand, memory_operand, etc) to forbid the use of this
4854 addressing mode, and then define the following predicates that permit
4855 this addressing mode. These predicates can then be used for the
4856 source operands of the appropriate instructions.
4858 n.b. While it is theoretically possible to change all machine patterns
4859 to use this addressing more where permitted by the architecture,
4860 it has only been implemented for "common" cases: SImode, HImode, and
4861 QImode operands, and only for the principle operations that would
4862 require this addressing mode: data movement and simple integer operations.
4864 In parallel with these new predicates, two new constraint letters
4865 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4866 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4867 In the pcrel case 's' is only valid in combination with 'a' registers.
4868 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4869 of how these constraints are used.
4871 The use of these predicates is strictly optional, though patterns that
4872 don't will cause an extra reload register to be allocated where one
4875 lea (abc:w,%pc),%a0 ; need to reload address
4876 moveq &1,%d1 ; since write to pc-relative space
4877 movel %d1,%a0@ ; is not allowed
4879 lea (abc:w,%pc),%a1 ; no need to reload address here
4880 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4882 For more info, consult tiemann@cygnus.com.
4885 All of the ugliness with predicates and constraints is due to the
4886 simple fact that the m68k does not allow a pc-relative addressing
4887 mode as a destination. gcc does not distinguish between source and
4888 destination addresses. Hence, if we claim that pc-relative address
4889 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4890 end up with invalid code. To get around this problem, we left
4891 pc-relative modes as invalid addresses, and then added special
4892 predicates and constraints to accept them.
4894 A cleaner way to handle this is to modify gcc to distinguish
4895 between source and destination addresses. We can then say that
4896 pc-relative is a valid source address but not a valid destination
4897 address, and hopefully avoid a lot of the predicate and constraint
4898 hackery. Unfortunately, this would be a pretty big change. It would
4899 be a useful change for a number of ports, but there aren't any current
4900 plans to undertake this.
4902 ***************************************************************************/
4906 output_andsi3 (rtx
*operands
)
4909 if (GET_CODE (operands
[2]) == CONST_INT
4910 && (INTVAL (operands
[2]) | 0xffff) == -1
4911 && (DATA_REG_P (operands
[0])
4912 || offsettable_memref_p (operands
[0]))
4913 && !TARGET_COLDFIRE
)
4915 if (GET_CODE (operands
[0]) != REG
)
4916 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4917 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4918 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4920 if (operands
[2] == const0_rtx
)
4922 return "and%.w %2,%0";
4924 if (GET_CODE (operands
[2]) == CONST_INT
4925 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4926 && (DATA_REG_P (operands
[0])
4927 || offsettable_memref_p (operands
[0])))
4929 if (DATA_REG_P (operands
[0]))
4930 operands
[1] = GEN_INT (logval
);
4933 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4934 operands
[1] = GEN_INT (logval
% 8);
4936 /* This does not set condition codes in a standard way. */
4938 return "bclr %1,%0";
4940 return "and%.l %2,%0";
4944 output_iorsi3 (rtx
*operands
)
4946 register int logval
;
4947 if (GET_CODE (operands
[2]) == CONST_INT
4948 && INTVAL (operands
[2]) >> 16 == 0
4949 && (DATA_REG_P (operands
[0])
4950 || offsettable_memref_p (operands
[0]))
4951 && !TARGET_COLDFIRE
)
4953 if (GET_CODE (operands
[0]) != REG
)
4954 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4955 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4957 if (INTVAL (operands
[2]) == 0xffff)
4958 return "mov%.w %2,%0";
4959 return "or%.w %2,%0";
4961 if (GET_CODE (operands
[2]) == CONST_INT
4962 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4963 && (DATA_REG_P (operands
[0])
4964 || offsettable_memref_p (operands
[0])))
4966 if (DATA_REG_P (operands
[0]))
4967 operands
[1] = GEN_INT (logval
);
4970 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4971 operands
[1] = GEN_INT (logval
% 8);
4974 return "bset %1,%0";
4976 return "or%.l %2,%0";
4980 output_xorsi3 (rtx
*operands
)
4982 register int logval
;
4983 if (GET_CODE (operands
[2]) == CONST_INT
4984 && INTVAL (operands
[2]) >> 16 == 0
4985 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4986 && !TARGET_COLDFIRE
)
4988 if (! DATA_REG_P (operands
[0]))
4989 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4990 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4992 if (INTVAL (operands
[2]) == 0xffff)
4994 return "eor%.w %2,%0";
4996 if (GET_CODE (operands
[2]) == CONST_INT
4997 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4998 && (DATA_REG_P (operands
[0])
4999 || offsettable_memref_p (operands
[0])))
5001 if (DATA_REG_P (operands
[0]))
5002 operands
[1] = GEN_INT (logval
);
5005 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5006 operands
[1] = GEN_INT (logval
% 8);
5009 return "bchg %1,%0";
5011 return "eor%.l %2,%0";
5014 /* Return the instruction that should be used for a call to address X,
5015 which is known to be in operand 0. */
5020 if (symbolic_operand (x
, VOIDmode
))
5021 return m68k_symbolic_call
;
5026 /* Likewise sibling calls. */
5029 output_sibcall (rtx x
)
5031 if (symbolic_operand (x
, VOIDmode
))
5032 return m68k_symbolic_jump
;
5038 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5039 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5042 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5044 /* Avoid clobbering the struct value reg by using the
5045 static chain reg as a temporary. */
5046 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5048 /* Pretend to be a post-reload pass while generating rtl. */
5049 reload_completed
= 1;
5051 /* The "this" pointer is stored at 4(%sp). */
5052 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5053 stack_pointer_rtx
, 4));
5055 /* Add DELTA to THIS. */
5058 /* Make the offset a legitimate operand for memory addition. */
5059 offset
= GEN_INT (delta
);
5060 if ((delta
< -8 || delta
> 8)
5061 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5063 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5064 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5066 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5067 copy_rtx (this_slot
), offset
));
5070 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5071 if (vcall_offset
!= 0)
5073 /* Set the static chain register to *THIS. */
5074 emit_move_insn (tmp
, this_slot
);
5075 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5077 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5078 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5079 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5081 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5085 /* Load the offset into %d0 and add it to THIS. */
5086 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5087 gen_rtx_MEM (Pmode
, addr
));
5088 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5089 copy_rtx (this_slot
),
5090 gen_rtx_REG (Pmode
, D0_REG
)));
5093 /* Jump to the target function. Use a sibcall if direct jumps are
5094 allowed, otherwise load the address into a register first. */
5095 mem
= DECL_RTL (function
);
5096 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5098 gcc_assert (flag_pic
);
5100 if (!TARGET_SEP_DATA
)
5102 /* Use the static chain register as a temporary (call-clobbered)
5103 GOT pointer for this function. We can use the static chain
5104 register because it isn't live on entry to the thunk. */
5105 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5106 emit_insn (gen_load_got (pic_offset_table_rtx
));
5108 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5109 mem
= replace_equiv_address (mem
, tmp
);
5111 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5112 SIBLING_CALL_P (insn
) = 1;
5114 /* Run just enough of rest_of_compilation. */
5115 insn
= get_insns ();
5116 split_all_insns_noflow ();
5117 final_start_function (insn
, file
, 1);
5118 final (insn
, file
, 1);
5119 final_end_function ();
5121 /* Clean up the vars set above. */
5122 reload_completed
= 0;
5124 /* Restore the original PIC register. */
5126 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5129 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5132 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5133 int incoming ATTRIBUTE_UNUSED
)
5135 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5138 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5140 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5141 unsigned int new_reg
)
5144 /* Interrupt functions can only use registers that have already been
5145 saved by the prologue, even if they would normally be
5148 if ((m68k_get_function_kind (current_function_decl
)
5149 == m68k_fk_interrupt_handler
)
5150 && !df_regs_ever_live_p (new_reg
))
5156 /* Value is true if hard register REGNO can hold a value of machine-mode
5157 MODE. On the 68000, we let the cpu registers can hold any mode, but
5158 restrict the 68881 registers to floating-point modes. */
5161 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5163 if (DATA_REGNO_P (regno
))
5165 /* Data Registers, can hold aggregate if fits in. */
5166 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5169 else if (ADDRESS_REGNO_P (regno
))
5171 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5174 else if (FP_REGNO_P (regno
))
5176 /* FPU registers, hold float or complex float of long double or
5178 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5179 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5180 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5186 /* Implement SECONDARY_RELOAD_CLASS. */
5189 m68k_secondary_reload_class (enum reg_class rclass
,
5190 enum machine_mode mode
, rtx x
)
5194 regno
= true_regnum (x
);
5196 /* If one operand of a movqi is an address register, the other
5197 operand must be a general register or constant. Other types
5198 of operand must be reloaded through a data register. */
5199 if (GET_MODE_SIZE (mode
) == 1
5200 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5201 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5204 /* PC-relative addresses must be loaded into an address register first. */
5206 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5207 && symbolic_operand (x
, VOIDmode
))
5213 /* Implement PREFERRED_RELOAD_CLASS. */
5216 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5218 enum reg_class secondary_class
;
5220 /* If RCLASS might need a secondary reload, try restricting it to
5221 a class that doesn't. */
5222 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5223 if (secondary_class
!= NO_REGS
5224 && reg_class_subset_p (secondary_class
, rclass
))
5225 return secondary_class
;
5227 /* Prefer to use moveq for in-range constants. */
5228 if (GET_CODE (x
) == CONST_INT
5229 && reg_class_subset_p (DATA_REGS
, rclass
)
5230 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5233 /* ??? Do we really need this now? */
5234 if (GET_CODE (x
) == CONST_DOUBLE
5235 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5237 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5246 /* Return floating point values in a 68881 register. This makes 68881 code
5247 a little bit faster. It also makes -msoft-float code incompatible with
5248 hard-float code, so people have to be careful not to mix the two.
5249 For ColdFire it was decided the ABI incompatibility is undesirable.
5250 If there is need for a hard-float ABI it is probably worth doing it
5251 properly and also passing function arguments in FP registers. */
5253 m68k_libcall_value (enum machine_mode mode
)
5260 return gen_rtx_REG (mode
, FP0_REG
);
5266 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5269 /* Location in which function value is returned.
5270 NOTE: Due to differences in ABIs, don't call this function directly,
5271 use FUNCTION_VALUE instead. */
5273 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5275 enum machine_mode mode
;
5277 mode
= TYPE_MODE (valtype
);
5283 return gen_rtx_REG (mode
, FP0_REG
);
5289 /* If the function returns a pointer, push that into %a0. */
5290 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5291 /* For compatibility with the large body of existing code which
5292 does not always properly declare external functions returning
5293 pointer types, the m68k/SVR4 convention is to copy the value
5294 returned for pointer functions from a0 to d0 in the function
5295 epilogue, so that callers that have neglected to properly
5296 declare the callee can still find the correct return value in
5298 return gen_rtx_PARALLEL
5301 gen_rtx_EXPR_LIST (VOIDmode
,
5302 gen_rtx_REG (mode
, A0_REG
),
5304 gen_rtx_EXPR_LIST (VOIDmode
,
5305 gen_rtx_REG (mode
, D0_REG
),
5307 else if (POINTER_TYPE_P (valtype
))
5308 return gen_rtx_REG (mode
, A0_REG
);
5310 return gen_rtx_REG (mode
, D0_REG
);
5313 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5314 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5316 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5318 enum machine_mode mode
= TYPE_MODE (type
);
5320 if (mode
== BLKmode
)
5323 /* If TYPE's known alignment is less than the alignment of MODE that
5324 would contain the structure, then return in memory. We need to
5325 do so to maintain the compatibility between code compiled with
5326 -mstrict-align and that compiled with -mno-strict-align. */
5327 if (AGGREGATE_TYPE_P (type
)
5328 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5335 /* CPU to schedule the program for. */
5336 enum attr_cpu m68k_sched_cpu
;
5338 /* MAC to schedule the program for. */
5339 enum attr_mac m68k_sched_mac
;
5347 /* Integer register. */
5353 /* Implicit mem reference (e.g. stack). */
5356 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5359 /* Memory with offset but without indexing. EA mode 5. */
5362 /* Memory with indexing. EA mode 6. */
5365 /* Memory referenced by absolute address. EA mode 7. */
5368 /* Immediate operand that doesn't require extension word. */
5371 /* Immediate 16 bit operand. */
5374 /* Immediate 32 bit operand. */
5378 /* Return type of memory ADDR_RTX refers to. */
5379 static enum attr_op_type
5380 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5382 struct m68k_address address
;
5384 if (symbolic_operand (addr_rtx
, VOIDmode
))
5385 return OP_TYPE_MEM7
;
5387 if (!m68k_decompose_address (mode
, addr_rtx
,
5388 reload_completed
, &address
))
5390 gcc_assert (!reload_completed
);
5391 /* Reload will likely fix the address to be in the register. */
5392 return OP_TYPE_MEM234
;
5395 if (address
.scale
!= 0)
5396 return OP_TYPE_MEM6
;
5398 if (address
.base
!= NULL_RTX
)
5400 if (address
.offset
== NULL_RTX
)
5401 return OP_TYPE_MEM234
;
5403 return OP_TYPE_MEM5
;
5406 gcc_assert (address
.offset
!= NULL_RTX
);
5408 return OP_TYPE_MEM7
;
5411 /* Return X or Y (depending on OPX_P) operand of INSN. */
5413 sched_get_operand (rtx insn
, bool opx_p
)
5417 if (recog_memoized (insn
) < 0)
5420 extract_constrain_insn_cached (insn
);
5423 i
= get_attr_opx (insn
);
5425 i
= get_attr_opy (insn
);
5427 if (i
>= recog_data
.n_operands
)
5430 return recog_data
.operand
[i
];
5433 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5434 If ADDRESS_P is true, return type of memory location operand refers to. */
5435 static enum attr_op_type
5436 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5440 op
= sched_get_operand (insn
, opx_p
);
5444 gcc_assert (!reload_completed
);
5449 return sched_address_type (QImode
, op
);
5451 if (memory_operand (op
, VOIDmode
))
5452 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5454 if (register_operand (op
, VOIDmode
))
5456 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5457 || (reload_completed
&& FP_REG_P (op
)))
5463 if (GET_CODE (op
) == CONST_INT
)
5469 /* Check for quick constants. */
5470 switch (get_attr_type (insn
))
5473 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5474 return OP_TYPE_IMM_Q
;
5476 gcc_assert (!reload_completed
);
5480 if (USE_MOVQ (ival
))
5481 return OP_TYPE_IMM_Q
;
5483 gcc_assert (!reload_completed
);
5487 if (valid_mov3q_const (ival
))
5488 return OP_TYPE_IMM_Q
;
5490 gcc_assert (!reload_completed
);
5497 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5498 return OP_TYPE_IMM_W
;
5500 return OP_TYPE_IMM_L
;
5503 if (GET_CODE (op
) == CONST_DOUBLE
)
5505 switch (GET_MODE (op
))
5508 return OP_TYPE_IMM_W
;
5512 return OP_TYPE_IMM_L
;
5519 if (GET_CODE (op
) == CONST
5520 || symbolic_operand (op
, VOIDmode
)
5523 switch (GET_MODE (op
))
5526 return OP_TYPE_IMM_Q
;
5529 return OP_TYPE_IMM_W
;
5532 return OP_TYPE_IMM_L
;
5535 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5537 return OP_TYPE_IMM_W
;
5539 return OP_TYPE_IMM_L
;
5543 gcc_assert (!reload_completed
);
5545 if (FLOAT_MODE_P (GET_MODE (op
)))
5551 /* Implement opx_type attribute.
5552 Return type of INSN's operand X.
5553 If ADDRESS_P is true, return type of memory location operand refers to. */
5555 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5557 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5563 return OPX_TYPE_FPN
;
5566 return OPX_TYPE_MEM1
;
5568 case OP_TYPE_MEM234
:
5569 return OPX_TYPE_MEM234
;
5572 return OPX_TYPE_MEM5
;
5575 return OPX_TYPE_MEM6
;
5578 return OPX_TYPE_MEM7
;
5581 return OPX_TYPE_IMM_Q
;
5584 return OPX_TYPE_IMM_W
;
5587 return OPX_TYPE_IMM_L
;
5594 /* Implement opy_type attribute.
5595 Return type of INSN's operand Y.
5596 If ADDRESS_P is true, return type of memory location operand refers to. */
5598 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5600 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5606 return OPY_TYPE_FPN
;
5609 return OPY_TYPE_MEM1
;
5611 case OP_TYPE_MEM234
:
5612 return OPY_TYPE_MEM234
;
5615 return OPY_TYPE_MEM5
;
5618 return OPY_TYPE_MEM6
;
5621 return OPY_TYPE_MEM7
;
5624 return OPY_TYPE_IMM_Q
;
5627 return OPY_TYPE_IMM_W
;
5630 return OPY_TYPE_IMM_L
;
5637 /* Return size of INSN as int. */
5639 sched_get_attr_size_int (rtx insn
)
5643 switch (get_attr_type (insn
))
5646 /* There should be no references to m68k_sched_attr_size for 'ignore'
5660 switch (get_attr_opx_type (insn
))
5666 case OPX_TYPE_MEM234
:
5667 case OPY_TYPE_IMM_Q
:
5672 /* Here we assume that most absolute references are short. */
5674 case OPY_TYPE_IMM_W
:
5678 case OPY_TYPE_IMM_L
:
5686 switch (get_attr_opy_type (insn
))
5692 case OPY_TYPE_MEM234
:
5693 case OPY_TYPE_IMM_Q
:
5698 /* Here we assume that most absolute references are short. */
5700 case OPY_TYPE_IMM_W
:
5704 case OPY_TYPE_IMM_L
:
5714 gcc_assert (!reload_completed
);
5722 /* Return size of INSN as attribute enum value. */
5724 m68k_sched_attr_size (rtx insn
)
5726 switch (sched_get_attr_size_int (insn
))
5742 /* Return operand X or Y (depending on OPX_P) of INSN,
5743 if it is a MEM, or NULL overwise. */
5744 static enum attr_op_type
5745 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5749 switch (get_attr_opx_type (insn
))
5754 case OPX_TYPE_IMM_Q
:
5755 case OPX_TYPE_IMM_W
:
5756 case OPX_TYPE_IMM_L
:
5760 case OPX_TYPE_MEM234
:
5763 return OP_TYPE_MEM1
;
5766 return OP_TYPE_MEM6
;
5774 switch (get_attr_opy_type (insn
))
5779 case OPY_TYPE_IMM_Q
:
5780 case OPY_TYPE_IMM_W
:
5781 case OPY_TYPE_IMM_L
:
5785 case OPY_TYPE_MEM234
:
5788 return OP_TYPE_MEM1
;
5791 return OP_TYPE_MEM6
;
5799 /* Implement op_mem attribute. */
5801 m68k_sched_attr_op_mem (rtx insn
)
5803 enum attr_op_type opx
;
5804 enum attr_op_type opy
;
5806 opx
= sched_get_opxy_mem_type (insn
, true);
5807 opy
= sched_get_opxy_mem_type (insn
, false);
5809 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5812 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5814 switch (get_attr_opx_access (insn
))
5830 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5832 switch (get_attr_opx_access (insn
))
5848 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5851 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5853 switch (get_attr_opx_access (insn
))
5859 gcc_assert (!reload_completed
);
5864 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5866 switch (get_attr_opx_access (insn
))
5872 gcc_assert (!reload_completed
);
5877 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5880 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5882 switch (get_attr_opx_access (insn
))
5888 gcc_assert (!reload_completed
);
5893 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5894 gcc_assert (!reload_completed
);
5898 /* Data for ColdFire V4 index bypass.
5899 Producer modifies register that is used as index in consumer with
5903 /* Producer instruction. */
5906 /* Consumer instruction. */
5909 /* Scale of indexed memory access within consumer.
5910 Or zero if bypass should not be effective at the moment. */
5912 } sched_cfv4_bypass_data
;
5914 /* An empty state that is used in m68k_sched_adjust_cost. */
5915 static state_t sched_adjust_cost_state
;
5917 /* Implement adjust_cost scheduler hook.
5918 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5920 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5925 if (recog_memoized (def_insn
) < 0
5926 || recog_memoized (insn
) < 0)
5929 if (sched_cfv4_bypass_data
.scale
== 1)
5930 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5932 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5933 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5934 that the data in sched_cfv4_bypass_data is up to date. */
5935 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5936 && sched_cfv4_bypass_data
.con
== insn
);
5941 sched_cfv4_bypass_data
.pro
= NULL
;
5942 sched_cfv4_bypass_data
.con
= NULL
;
5943 sched_cfv4_bypass_data
.scale
= 0;
5946 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5947 && sched_cfv4_bypass_data
.con
== NULL
5948 && sched_cfv4_bypass_data
.scale
== 0);
5950 /* Don't try to issue INSN earlier than DFA permits.
5951 This is especially useful for instructions that write to memory,
5952 as their true dependence (default) latency is better to be set to 0
5953 to workaround alias analysis limitations.
5954 This is, in fact, a machine independent tweak, so, probably,
5955 it should be moved to haifa-sched.c: insn_cost (). */
5956 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5963 /* Return maximal number of insns that can be scheduled on a single cycle. */
5965 m68k_sched_issue_rate (void)
5967 switch (m68k_sched_cpu
)
5983 /* Maximal length of instruction for current CPU.
5984 E.g. it is 3 for any ColdFire core. */
5985 static int max_insn_size
;
5987 /* Data to model instruction buffer of CPU. */
5990 /* True if instruction buffer model is modeled for current CPU. */
5993 /* Size of the instruction buffer in words. */
5996 /* Number of filled words in the instruction buffer. */
5999 /* Additional information about instruction buffer for CPUs that have
6000 a buffer of instruction records, rather then a plain buffer
6001 of instruction words. */
6002 struct _sched_ib_records
6004 /* Size of buffer in records. */
6007 /* Array to hold data on adjustements made to the size of the buffer. */
6010 /* Index of the above array. */
6014 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6018 static struct _sched_ib sched_ib
;
6020 /* ID of memory unit. */
6021 static int sched_mem_unit_code
;
6023 /* Implementation of the targetm.sched.variable_issue () hook.
6024 It is called after INSN was issued. It returns the number of insns
6025 that can possibly get scheduled on the current cycle.
6026 It is used here to determine the effect of INSN on the instruction
6029 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6030 int sched_verbose ATTRIBUTE_UNUSED
,
6031 rtx insn
, int can_issue_more
)
6035 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6037 switch (m68k_sched_cpu
)
6041 insn_size
= sched_get_attr_size_int (insn
);
6045 insn_size
= sched_get_attr_size_int (insn
);
6047 /* ColdFire V3 and V4 cores have instruction buffers that can
6048 accumulate up to 8 instructions regardless of instructions'
6049 sizes. So we should take care not to "prefetch" 24 one-word
6050 or 12 two-words instructions.
6051 To model this behavior we temporarily decrease size of the
6052 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6056 adjust
= max_insn_size
- insn_size
;
6057 sched_ib
.size
-= adjust
;
6059 if (sched_ib
.filled
> sched_ib
.size
)
6060 sched_ib
.filled
= sched_ib
.size
;
6062 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6065 ++sched_ib
.records
.adjust_index
;
6066 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6067 sched_ib
.records
.adjust_index
= 0;
6069 /* Undo adjustement we did 7 instructions ago. */
6071 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6076 gcc_assert (!sched_ib
.enabled_p
);
6084 if (insn_size
> sched_ib
.filled
)
6085 /* Scheduling for register pressure does not always take DFA into
6086 account. Workaround instruction buffer not being filled enough. */
6088 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6089 insn_size
= sched_ib
.filled
;
6094 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6095 || asm_noperands (PATTERN (insn
)) >= 0)
6096 insn_size
= sched_ib
.filled
;
6100 sched_ib
.filled
-= insn_size
;
6102 return can_issue_more
;
6105 /* Return how many instructions should scheduler lookahead to choose the
6108 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6110 return m68k_sched_issue_rate () - 1;
6113 /* Implementation of targetm.sched.init_global () hook.
6114 It is invoked once per scheduling pass and is used here
6115 to initialize scheduler constants. */
6117 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6118 int sched_verbose ATTRIBUTE_UNUSED
,
6119 int n_insns ATTRIBUTE_UNUSED
)
6121 #ifdef ENABLE_CHECKING
6122 /* Check that all instructions have DFA reservations and
6123 that all instructions can be issued from a clean state. */
6128 state
= alloca (state_size ());
6130 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6132 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6134 gcc_assert (insn_has_dfa_reservation_p (insn
));
6136 state_reset (state
);
6137 if (state_transition (state
, insn
) >= 0)
6144 /* Setup target cpu. */
6146 /* ColdFire V4 has a set of features to keep its instruction buffer full
6147 (e.g., a separate memory bus for instructions) and, hence, we do not model
6148 buffer for this CPU. */
6149 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6151 switch (m68k_sched_cpu
)
6154 sched_ib
.filled
= 0;
6161 sched_ib
.records
.n_insns
= 0;
6162 sched_ib
.records
.adjust
= NULL
;
6167 sched_ib
.records
.n_insns
= 8;
6168 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6175 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6177 sched_adjust_cost_state
= xmalloc (state_size ());
6178 state_reset (sched_adjust_cost_state
);
6181 emit_insn (gen_ib ());
6182 sched_ib
.insn
= get_insns ();
6186 /* Scheduling pass is now finished. Free/reset static variables. */
6188 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6189 int verbose ATTRIBUTE_UNUSED
)
6191 sched_ib
.insn
= NULL
;
6193 free (sched_adjust_cost_state
);
6194 sched_adjust_cost_state
= NULL
;
6196 sched_mem_unit_code
= 0;
6198 free (sched_ib
.records
.adjust
);
6199 sched_ib
.records
.adjust
= NULL
;
6200 sched_ib
.records
.n_insns
= 0;
6204 /* Implementation of targetm.sched.init () hook.
6205 It is invoked each time scheduler starts on the new block (basic block or
6206 extended basic block). */
6208 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6209 int sched_verbose ATTRIBUTE_UNUSED
,
6210 int n_insns ATTRIBUTE_UNUSED
)
6212 switch (m68k_sched_cpu
)
6220 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6222 memset (sched_ib
.records
.adjust
, 0,
6223 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6224 sched_ib
.records
.adjust_index
= 0;
6228 gcc_assert (!sched_ib
.enabled_p
);
6236 if (sched_ib
.enabled_p
)
6237 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6238 the first cycle. Workaround that. */
6239 sched_ib
.filled
= -2;
6242 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6243 It is invoked just before current cycle finishes and is used here
6244 to track if instruction buffer got its two words this cycle. */
6246 m68k_sched_dfa_pre_advance_cycle (void)
6248 if (!sched_ib
.enabled_p
)
6251 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6253 sched_ib
.filled
+= 2;
6255 if (sched_ib
.filled
> sched_ib
.size
)
6256 sched_ib
.filled
= sched_ib
.size
;
6260 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6261 It is invoked just after new cycle begins and is used here
6262 to setup number of filled words in the instruction buffer so that
6263 instructions which won't have all their words prefetched would be
6264 stalled for a cycle. */
6266 m68k_sched_dfa_post_advance_cycle (void)
6270 if (!sched_ib
.enabled_p
)
6273 /* Setup number of prefetched instruction words in the instruction
6275 i
= max_insn_size
- sched_ib
.filled
;
6279 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6280 /* Pick up scheduler state. */
6285 /* Return X or Y (depending on OPX_P) operand of INSN,
6286 if it is an integer register, or NULL overwise. */
6288 sched_get_reg_operand (rtx insn
, bool opx_p
)
6294 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6296 op
= sched_get_operand (insn
, true);
6297 gcc_assert (op
!= NULL
);
6299 if (!reload_completed
&& !REG_P (op
))
6305 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6307 op
= sched_get_operand (insn
, false);
6308 gcc_assert (op
!= NULL
);
6310 if (!reload_completed
&& !REG_P (op
))
6318 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6321 sched_mem_operand_p (rtx insn
, bool opx_p
)
6323 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6334 /* Return X or Y (depending on OPX_P) operand of INSN,
6335 if it is a MEM, or NULL overwise. */
6337 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6357 if (opy_p
&& sched_mem_operand_p (insn
, false))
6358 return sched_get_operand (insn
, false);
6360 if (opx_p
&& sched_mem_operand_p (insn
, true))
6361 return sched_get_operand (insn
, true);
6367 /* Return non-zero if PRO modifies register used as part of
6370 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6375 pro_x
= sched_get_reg_operand (pro
, true);
6379 con_mem_read
= sched_get_mem_operand (con
, true, false);
6380 gcc_assert (con_mem_read
!= NULL
);
6382 if (reg_mentioned_p (pro_x
, con_mem_read
))
6388 /* Helper function for m68k_sched_indexed_address_bypass_p.
6389 if PRO modifies register used as index in CON,
6390 return scale of indexed memory access in CON. Return zero overwise. */
6392 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6396 struct m68k_address address
;
6398 reg
= sched_get_reg_operand (pro
, true);
6402 mem
= sched_get_mem_operand (con
, true, false);
6403 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6405 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6409 if (REGNO (reg
) == REGNO (address
.index
))
6411 gcc_assert (address
.scale
!= 0);
6412 return address
.scale
;
6418 /* Return non-zero if PRO modifies register used
6419 as index with scale 2 or 4 in CON. */
6421 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6423 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6424 && sched_cfv4_bypass_data
.con
== NULL
6425 && sched_cfv4_bypass_data
.scale
== 0);
6427 switch (sched_get_indexed_address_scale (pro
, con
))
6430 /* We can't have a variable latency bypass, so
6431 remember to adjust the insn cost in adjust_cost hook. */
6432 sched_cfv4_bypass_data
.pro
= pro
;
6433 sched_cfv4_bypass_data
.con
= con
;
6434 sched_cfv4_bypass_data
.scale
= 1;
6446 /* We generate a two-instructions program at M_TRAMP :
6447 movea.l &CHAIN_VALUE,%a0
6449 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6452 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6454 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6457 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6459 mem
= adjust_address (m_tramp
, HImode
, 0);
6460 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6461 mem
= adjust_address (m_tramp
, SImode
, 2);
6462 emit_move_insn (mem
, chain_value
);
6464 mem
= adjust_address (m_tramp
, HImode
, 6);
6465 emit_move_insn (mem
, GEN_INT(0x4EF9));
6466 mem
= adjust_address (m_tramp
, SImode
, 8);
6467 emit_move_insn (mem
, fnaddr
);
6469 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6472 /* On the 68000, the RTS insn cannot pop anything.
6473 On the 68010, the RTD insn may be used to pop them if the number
6474 of args is fixed, but if the number is variable then the caller
6475 must pop them all. RTD can't be used for library calls now
6476 because the library is compiled with the Unix compiler.
6477 Use of RTD is a selectable option, since it is incompatible with
6478 standard Unix calling sequences. If the option is not selected,
6479 the caller must always pop the args. */
6482 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6486 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6487 && (!stdarg_p (funtype
)))
6491 /* Make sure everything's fine if we *don't* have a given processor.
6492 This assumes that putting a register in fixed_regs will keep the
6493 compiler's mitts completely off it. We don't bother to zero it out
6494 of register classes. */
6497 m68k_conditional_register_usage (void)
6501 if (!TARGET_HARD_FLOAT
)
6503 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6504 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6505 if (TEST_HARD_REG_BIT (x
, i
))
6506 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6509 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6513 m68k_init_sync_libfuncs (void)
6515 init_sync_libfuncs (UNITS_PER_WORD
);
6518 /* Implements EPILOGUE_USES. All registers are live on exit from an
6519 interrupt routine. */
6521 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6523 return (reload_completed
6524 && (m68k_get_function_kind (current_function_decl
)
6525 == m68k_fk_interrupt_handler
));
6528 #include "gt-m68k.h"