1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "stringpool.h"
31 #include "fold-const.h"
33 #include "stor-layout.h"
36 #include "insn-config.h"
37 #include "conditions.h"
39 #include "insn-attr.h"
41 #include "diagnostic-core.h"
58 #include "cfgcleanup.h"
59 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
60 #include "sched-int.h"
61 #include "insn-codes.h"
67 /* This file should be included last. */
68 #include "target-def.h"
70 enum reg_class regno_reg_class
[] =
72 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
73 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
74 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
75 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
76 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
77 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
82 /* The minimum number of integer registers that we want to save with the
83 movem instruction. Using two movel instructions instead of a single
84 moveml is about 15% faster for the 68020 and 68030 at no expense in
86 #define MIN_MOVEM_REGS 3
88 /* The minimum number of floating point registers that we want to save
89 with the fmovem instruction. */
90 #define MIN_FMOVEM_REGS 1
92 /* Structure describing stack frame layout. */
95 /* Stack pointer to frame pointer offset. */
98 /* Offset of FPU registers. */
99 HOST_WIDE_INT foffset
;
101 /* Frame size in bytes (rounded up). */
104 /* Data and address register. */
106 unsigned int reg_mask
;
110 unsigned int fpu_mask
;
112 /* Offsets relative to ARG_POINTER. */
113 HOST_WIDE_INT frame_pointer_offset
;
114 HOST_WIDE_INT stack_pointer_offset
;
116 /* Function which the above information refers to. */
120 /* Current frame information calculated by m68k_compute_frame_layout(). */
121 static struct m68k_frame current_frame
;
123 /* Structure describing an m68k address.
125 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
126 with null fields evaluating to 0. Here:
128 - BASE satisfies m68k_legitimate_base_reg_p
129 - INDEX satisfies m68k_legitimate_index_reg_p
130 - OFFSET satisfies m68k_legitimate_constant_address_p
132 INDEX is either HImode or SImode. The other fields are SImode.
134 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
135 the address is (BASE)+. */
136 struct m68k_address
{
144 static int m68k_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
146 static int m68k_sched_issue_rate (void);
147 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
148 static void m68k_sched_md_init_global (FILE *, int, int);
149 static void m68k_sched_md_finish_global (FILE *, int);
150 static void m68k_sched_md_init (FILE *, int, int);
151 static void m68k_sched_dfa_pre_advance_cycle (void);
152 static void m68k_sched_dfa_post_advance_cycle (void);
153 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
155 static bool m68k_can_eliminate (const int, const int);
156 static void m68k_conditional_register_usage (void);
157 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
158 static void m68k_option_override (void);
159 static void m68k_override_options_after_change (void);
160 static rtx
find_addr_reg (rtx
);
161 static const char *singlemove_string (rtx
*);
162 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
163 HOST_WIDE_INT
, tree
);
164 static rtx
m68k_struct_value_rtx (tree
, int);
165 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
166 tree args
, int flags
,
168 static void m68k_compute_frame_layout (void);
169 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
170 static bool m68k_ok_for_sibcall_p (tree
, tree
);
171 static bool m68k_tls_symbol_p (rtx
);
172 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
173 static bool m68k_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
174 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
175 static bool m68k_return_in_memory (const_tree
, const_tree
);
177 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
178 static void m68k_trampoline_init (rtx
, tree
, rtx
);
179 static int m68k_return_pops_args (tree
, tree
, int);
180 static rtx
m68k_delegitimize_address (rtx
);
181 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
183 static rtx
m68k_function_arg (cumulative_args_t
, machine_mode
,
185 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
186 static bool m68k_output_addr_const_extra (FILE *, rtx
);
187 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
188 static enum flt_eval_method
189 m68k_excess_precision (enum excess_precision_type
);
190 static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode
);
192 /* Initialize the GCC target structure. */
194 #if INT_OP_GROUP == INT_OP_DOT_WORD
195 #undef TARGET_ASM_ALIGNED_HI_OP
196 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
199 #if INT_OP_GROUP == INT_OP_NO_DOT
200 #undef TARGET_ASM_BYTE_OP
201 #define TARGET_ASM_BYTE_OP "\tbyte\t"
202 #undef TARGET_ASM_ALIGNED_HI_OP
203 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
204 #undef TARGET_ASM_ALIGNED_SI_OP
205 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
208 #if INT_OP_GROUP == INT_OP_DC
209 #undef TARGET_ASM_BYTE_OP
210 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
211 #undef TARGET_ASM_ALIGNED_HI_OP
212 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
213 #undef TARGET_ASM_ALIGNED_SI_OP
214 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
217 #undef TARGET_ASM_UNALIGNED_HI_OP
218 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
219 #undef TARGET_ASM_UNALIGNED_SI_OP
220 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
222 #undef TARGET_ASM_OUTPUT_MI_THUNK
223 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
224 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
225 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
227 #undef TARGET_ASM_FILE_START_APP_OFF
228 #define TARGET_ASM_FILE_START_APP_OFF true
230 #undef TARGET_LEGITIMIZE_ADDRESS
231 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
233 #undef TARGET_SCHED_ADJUST_COST
234 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
236 #undef TARGET_SCHED_ISSUE_RATE
237 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
239 #undef TARGET_SCHED_VARIABLE_ISSUE
240 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
242 #undef TARGET_SCHED_INIT_GLOBAL
243 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
245 #undef TARGET_SCHED_FINISH_GLOBAL
246 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
248 #undef TARGET_SCHED_INIT
249 #define TARGET_SCHED_INIT m68k_sched_md_init
251 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
252 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
254 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
255 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
257 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
258 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
259 m68k_sched_first_cycle_multipass_dfa_lookahead
261 #undef TARGET_OPTION_OVERRIDE
262 #define TARGET_OPTION_OVERRIDE m68k_option_override
264 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
265 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
267 #undef TARGET_RTX_COSTS
268 #define TARGET_RTX_COSTS m68k_rtx_costs
270 #undef TARGET_ATTRIBUTE_TABLE
271 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
273 #undef TARGET_PROMOTE_PROTOTYPES
274 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
276 #undef TARGET_STRUCT_VALUE_RTX
277 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
279 #undef TARGET_CANNOT_FORCE_CONST_MEM
280 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
282 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
283 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
285 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
286 #undef TARGET_RETURN_IN_MEMORY
287 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
291 #undef TARGET_HAVE_TLS
292 #define TARGET_HAVE_TLS (true)
294 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
295 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
299 #define TARGET_LRA_P hook_bool_void_false
301 #undef TARGET_LEGITIMATE_ADDRESS_P
302 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
304 #undef TARGET_CAN_ELIMINATE
305 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
307 #undef TARGET_CONDITIONAL_REGISTER_USAGE
308 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
310 #undef TARGET_TRAMPOLINE_INIT
311 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
313 #undef TARGET_RETURN_POPS_ARGS
314 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
316 #undef TARGET_DELEGITIMIZE_ADDRESS
317 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
319 #undef TARGET_FUNCTION_ARG
320 #define TARGET_FUNCTION_ARG m68k_function_arg
322 #undef TARGET_FUNCTION_ARG_ADVANCE
323 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
325 #undef TARGET_LEGITIMATE_CONSTANT_P
326 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
328 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
329 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
331 #undef TARGET_C_EXCESS_PRECISION
332 #define TARGET_C_EXCESS_PRECISION m68k_excess_precision
334 /* The value stored by TAS. */
335 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
336 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
338 #undef TARGET_HARD_REGNO_MODE_OK
339 #define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
341 static const struct attribute_spec m68k_attribute_table
[] =
343 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
344 affects_type_identity } */
345 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
347 { "interrupt_handler", 0, 0, true, false, false,
348 m68k_handle_fndecl_attribute
, false },
349 { "interrupt_thread", 0, 0, true, false, false,
350 m68k_handle_fndecl_attribute
, false },
351 { NULL
, 0, 0, false, false, false, NULL
, false }
354 struct gcc_target targetm
= TARGET_INITIALIZER
;
356 /* Base flags for 68k ISAs. */
357 #define FL_FOR_isa_00 FL_ISA_68000
358 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
359 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
360 generated 68881 code for 68020 and 68030 targets unless explicitly told
362 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
363 | FL_BITFIELD | FL_68881 | FL_CAS)
364 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
365 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
367 /* Base flags for ColdFire ISAs. */
368 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
369 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
370 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
371 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
372 /* ISA_C is not upwardly compatible with ISA_B. */
373 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
377 /* Traditional 68000 instruction sets. */
383 /* ColdFire instruction set variants. */
391 /* Information about one of the -march, -mcpu or -mtune arguments. */
392 struct m68k_target_selection
394 /* The argument being described. */
397 /* For -mcpu, this is the device selected by the option.
398 For -mtune and -march, it is a representative device
399 for the microarchitecture or ISA respectively. */
400 enum target_device device
;
402 /* The M68K_DEVICE fields associated with DEVICE. See the comment
403 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
405 enum uarch_type microarch
;
410 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
411 static const struct m68k_target_selection all_devices
[] =
413 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
414 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
415 #include "m68k-devices.def"
417 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
420 /* A list of all ISAs, mapping each one to a representative device.
421 Used for -march selection. */
422 static const struct m68k_target_selection all_isas
[] =
424 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
425 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
426 #include "m68k-isas.def"
428 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
431 /* A list of all microarchitectures, mapping each one to a representative
432 device. Used for -mtune selection. */
433 static const struct m68k_target_selection all_microarchs
[] =
435 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
436 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
437 #include "m68k-microarchs.def"
438 #undef M68K_MICROARCH
439 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
442 /* The entries associated with the -mcpu, -march and -mtune settings,
443 or null for options that have not been used. */
444 const struct m68k_target_selection
*m68k_cpu_entry
;
445 const struct m68k_target_selection
*m68k_arch_entry
;
446 const struct m68k_target_selection
*m68k_tune_entry
;
448 /* Which CPU we are generating code for. */
449 enum target_device m68k_cpu
;
451 /* Which microarchitecture to tune for. */
452 enum uarch_type m68k_tune
;
454 /* Which FPU to use. */
455 enum fpu_type m68k_fpu
;
457 /* The set of FL_* flags that apply to the target processor. */
458 unsigned int m68k_cpu_flags
;
460 /* The set of FL_* flags that apply to the processor to be tuned for. */
461 unsigned int m68k_tune_flags
;
463 /* Asm templates for calling or jumping to an arbitrary symbolic address,
464 or NULL if such calls or jumps are not supported. The address is held
466 const char *m68k_symbolic_call
;
467 const char *m68k_symbolic_jump
;
469 /* Enum variable that corresponds to m68k_symbolic_call values. */
470 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
473 /* Implement TARGET_OPTION_OVERRIDE. */
476 m68k_option_override (void)
478 const struct m68k_target_selection
*entry
;
479 unsigned long target_mask
;
481 if (global_options_set
.x_m68k_arch_option
)
482 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
484 if (global_options_set
.x_m68k_cpu_option
)
485 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
487 if (global_options_set
.x_m68k_tune_option
)
488 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
496 -march=ARCH should generate code that runs any processor
497 implementing architecture ARCH. -mcpu=CPU should override -march
498 and should generate code that runs on processor CPU, making free
499 use of any instructions that CPU understands. -mtune=UARCH applies
500 on top of -mcpu or -march and optimizes the code for UARCH. It does
501 not change the target architecture. */
504 /* Complain if the -march setting is for a different microarchitecture,
505 or includes flags that the -mcpu setting doesn't. */
507 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
508 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
509 warning (0, "-mcpu=%s conflicts with -march=%s",
510 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
512 entry
= m68k_cpu_entry
;
515 entry
= m68k_arch_entry
;
518 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
520 m68k_cpu_flags
= entry
->flags
;
522 /* Use the architecture setting to derive default values for
526 /* ColdFire is lenient about alignment. */
527 if (!TARGET_COLDFIRE
)
528 target_mask
|= MASK_STRICT_ALIGNMENT
;
530 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
531 target_mask
|= MASK_BITFIELD
;
532 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
533 target_mask
|= MASK_CF_HWDIV
;
534 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
535 target_mask
|= MASK_HARD_FLOAT
;
536 target_flags
|= target_mask
& ~target_flags_explicit
;
538 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
539 m68k_cpu
= entry
->device
;
542 m68k_tune
= m68k_tune_entry
->microarch
;
543 m68k_tune_flags
= m68k_tune_entry
->flags
;
545 #ifdef M68K_DEFAULT_TUNE
546 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
548 enum target_device dev
;
549 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
550 m68k_tune_flags
= all_devices
[dev
].flags
;
555 m68k_tune
= entry
->microarch
;
556 m68k_tune_flags
= entry
->flags
;
559 /* Set the type of FPU. */
560 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
561 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
564 /* Sanity check to ensure that msep-data and mid-sahred-library are not
565 * both specified together. Doing so simply doesn't make sense.
567 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
568 error ("cannot specify both -msep-data and -mid-shared-library");
570 /* If we're generating code for a separate A5 relative data segment,
571 * we've got to enable -fPIC as well. This might be relaxable to
572 * -fpic but it hasn't been tested properly.
574 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
577 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
578 error if the target does not support them. */
579 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
580 error ("-mpcrel -fPIC is not currently supported on selected cpu");
582 /* ??? A historic way of turning on pic, or is this intended to
583 be an embedded thing that doesn't have the same name binding
584 significance that it does on hosted ELF systems? */
585 if (TARGET_PCREL
&& flag_pic
== 0)
590 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
592 m68k_symbolic_jump
= "jra %a0";
594 else if (TARGET_ID_SHARED_LIBRARY
)
595 /* All addresses must be loaded from the GOT. */
597 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
600 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
602 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
605 /* No unconditional long branch */;
606 else if (TARGET_PCREL
)
607 m68k_symbolic_jump
= "bra%.l %c0";
609 m68k_symbolic_jump
= "bra%.l %p0";
610 /* Turn off function cse if we are doing PIC. We always want
611 function call to be done as `bsr foo@PLTPC'. */
612 /* ??? It's traditional to do this for -mpcrel too, but it isn't
613 clear how intentional that is. */
614 flag_no_function_cse
= 1;
617 switch (m68k_symbolic_call_var
)
619 case M68K_SYMBOLIC_CALL_JSR
:
620 m68k_symbolic_call
= "jsr %a0";
623 case M68K_SYMBOLIC_CALL_BSR_C
:
624 m68k_symbolic_call
= "bsr%.l %c0";
627 case M68K_SYMBOLIC_CALL_BSR_P
:
628 m68k_symbolic_call
= "bsr%.l %p0";
631 case M68K_SYMBOLIC_CALL_NONE
:
632 gcc_assert (m68k_symbolic_call
== NULL
);
639 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
640 if (align_labels
> 2)
642 warning (0, "-falign-labels=%d is not supported", align_labels
);
647 warning (0, "-falign-loops=%d is not supported", align_loops
);
652 if ((opt_fstack_limit_symbol_arg
!= NULL
|| opt_fstack_limit_register_no
>= 0)
655 warning (0, "-fstack-limit- options are not supported on this cpu");
656 opt_fstack_limit_symbol_arg
= NULL
;
657 opt_fstack_limit_register_no
= -1;
660 SUBTARGET_OVERRIDE_OPTIONS
;
662 /* Setup scheduling options. */
664 m68k_sched_cpu
= CPU_CFV1
;
666 m68k_sched_cpu
= CPU_CFV2
;
668 m68k_sched_cpu
= CPU_CFV3
;
670 m68k_sched_cpu
= CPU_CFV4
;
673 m68k_sched_cpu
= CPU_UNKNOWN
;
674 flag_schedule_insns
= 0;
675 flag_schedule_insns_after_reload
= 0;
676 flag_modulo_sched
= 0;
677 flag_live_range_shrinkage
= 0;
680 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
682 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
683 m68k_sched_mac
= MAC_CF_EMAC
;
684 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
685 m68k_sched_mac
= MAC_CF_MAC
;
687 m68k_sched_mac
= MAC_NO
;
691 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
694 m68k_override_options_after_change (void)
696 if (m68k_sched_cpu
== CPU_UNKNOWN
)
698 flag_schedule_insns
= 0;
699 flag_schedule_insns_after_reload
= 0;
700 flag_modulo_sched
= 0;
701 flag_live_range_shrinkage
= 0;
705 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
706 given argument and NAME is the argument passed to -mcpu. Return NULL
707 if -mcpu was not passed. */
710 m68k_cpp_cpu_ident (const char *prefix
)
714 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
717 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
718 given argument and NAME is the name of the representative device for
719 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
722 m68k_cpp_cpu_family (const char *prefix
)
726 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
729 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
730 "interrupt_handler" attribute and interrupt_thread if FUNC has an
731 "interrupt_thread" attribute. Otherwise, return
732 m68k_fk_normal_function. */
734 enum m68k_function_kind
735 m68k_get_function_kind (tree func
)
739 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
741 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
743 return m68k_fk_interrupt_handler
;
745 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
747 return m68k_fk_interrupt_handler
;
749 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
751 return m68k_fk_interrupt_thread
;
753 return m68k_fk_normal_function
;
756 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
757 struct attribute_spec.handler. */
759 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
760 tree args ATTRIBUTE_UNUSED
,
761 int flags ATTRIBUTE_UNUSED
,
764 if (TREE_CODE (*node
) != FUNCTION_DECL
)
766 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
768 *no_add_attrs
= true;
771 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
773 error ("multiple interrupt attributes not allowed");
774 *no_add_attrs
= true;
778 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
780 error ("interrupt_thread is available only on fido");
781 *no_add_attrs
= true;
788 m68k_compute_frame_layout (void)
792 enum m68k_function_kind func_kind
=
793 m68k_get_function_kind (current_function_decl
);
794 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
795 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
797 /* Only compute the frame once per function.
798 Don't cache information until reload has been completed. */
799 if (current_frame
.funcdef_no
== current_function_funcdef_no
803 current_frame
.size
= (get_frame_size () + 3) & -4;
807 /* Interrupt thread does not need to save any register. */
808 if (!interrupt_thread
)
809 for (regno
= 0; regno
< 16; regno
++)
810 if (m68k_save_reg (regno
, interrupt_handler
))
812 mask
|= 1 << (regno
- D0_REG
);
815 current_frame
.offset
= saved
* 4;
816 current_frame
.reg_no
= saved
;
817 current_frame
.reg_mask
= mask
;
819 current_frame
.foffset
= 0;
821 if (TARGET_HARD_FLOAT
)
823 /* Interrupt thread does not need to save any register. */
824 if (!interrupt_thread
)
825 for (regno
= 16; regno
< 24; regno
++)
826 if (m68k_save_reg (regno
, interrupt_handler
))
828 mask
|= 1 << (regno
- FP0_REG
);
831 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
832 current_frame
.offset
+= current_frame
.foffset
;
834 current_frame
.fpu_no
= saved
;
835 current_frame
.fpu_mask
= mask
;
837 /* Remember what function this frame refers to. */
838 current_frame
.funcdef_no
= current_function_funcdef_no
;
841 /* Worker function for TARGET_CAN_ELIMINATE. */
844 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
846 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
850 m68k_initial_elimination_offset (int from
, int to
)
853 /* The arg pointer points 8 bytes before the start of the arguments,
854 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
855 frame pointer in most frames. */
856 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
857 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
858 return argptr_offset
;
860 m68k_compute_frame_layout ();
862 gcc_assert (to
== STACK_POINTER_REGNUM
);
865 case ARG_POINTER_REGNUM
:
866 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
867 case FRAME_POINTER_REGNUM
:
868 return current_frame
.offset
+ current_frame
.size
;
874 /* Refer to the array `regs_ever_live' to determine which registers
875 to save; `regs_ever_live[I]' is nonzero if register number I
876 is ever used in the function. This function is responsible for
877 knowing which registers should not be saved even if used.
878 Return true if we need to save REGNO. */
881 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
883 if (flag_pic
&& regno
== PIC_REG
)
885 if (crtl
->saves_all_registers
)
887 if (crtl
->uses_pic_offset_table
)
889 /* Reload may introduce constant pool references into a function
890 that thitherto didn't need a PIC register. Note that the test
891 above will not catch that case because we will only set
892 crtl->uses_pic_offset_table when emitting
893 the address reloads. */
894 if (crtl
->uses_const_pool
)
898 if (crtl
->calls_eh_return
)
903 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
904 if (test
== INVALID_REGNUM
)
911 /* Fixed regs we never touch. */
912 if (fixed_regs
[regno
])
915 /* The frame pointer (if it is such) is handled specially. */
916 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
919 /* Interrupt handlers must also save call_used_regs
920 if they are live or when calling nested functions. */
921 if (interrupt_handler
)
923 if (df_regs_ever_live_p (regno
))
926 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
930 /* Never need to save registers that aren't touched. */
931 if (!df_regs_ever_live_p (regno
))
934 /* Otherwise save everything that isn't call-clobbered. */
935 return !call_used_regs
[regno
];
938 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
939 the lowest memory address. COUNT is the number of registers to be
940 moved, with register REGNO + I being moved if bit I of MASK is set.
941 STORE_P specifies the direction of the move and ADJUST_STACK_P says
942 whether or not this is pre-decrement (if STORE_P) or post-increment
943 (if !STORE_P) operation. */
946 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
947 unsigned int count
, unsigned int regno
,
948 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
951 rtx body
, addr
, src
, operands
[2];
954 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
955 mode
= reg_raw_mode
[regno
];
960 src
= plus_constant (Pmode
, base
,
962 * GET_MODE_SIZE (mode
)
963 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
964 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
967 for (; mask
!= 0; mask
>>= 1, regno
++)
970 addr
= plus_constant (Pmode
, base
, offset
);
971 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
972 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
973 XVECEXP (body
, 0, i
++)
974 = gen_rtx_SET (operands
[0], operands
[1]);
975 offset
+= GET_MODE_SIZE (mode
);
977 gcc_assert (i
== XVECLEN (body
, 0));
979 return emit_insn (body
);
982 /* Make INSN a frame-related instruction. */
985 m68k_set_frame_related (rtx_insn
*insn
)
990 RTX_FRAME_RELATED_P (insn
) = 1;
991 body
= PATTERN (insn
);
992 if (GET_CODE (body
) == PARALLEL
)
993 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
994 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
997 /* Emit RTL for the "prologue" define_expand. */
1000 m68k_expand_prologue (void)
1002 HOST_WIDE_INT fsize_with_regs
;
1003 rtx limit
, src
, dest
;
1005 m68k_compute_frame_layout ();
1007 if (flag_stack_usage_info
)
1008 current_function_static_stack_size
1009 = current_frame
.size
+ current_frame
.offset
;
1011 /* If the stack limit is a symbol, we can check it here,
1012 before actually allocating the space. */
1013 if (crtl
->limit_stack
1014 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1016 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1017 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1019 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1020 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1022 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1023 stack_pointer_rtx
, limit
),
1024 stack_pointer_rtx
, limit
,
1028 fsize_with_regs
= current_frame
.size
;
1029 if (TARGET_COLDFIRE
)
1031 /* ColdFire's move multiple instructions do not allow pre-decrement
1032 addressing. Add the size of movem saves to the initial stack
1033 allocation instead. */
1034 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1035 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1036 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1037 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1040 if (frame_pointer_needed
)
1042 if (fsize_with_regs
== 0 && TUNE_68040
)
1044 /* On the 68040, two separate moves are faster than link.w 0. */
1045 dest
= gen_frame_mem (Pmode
,
1046 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1047 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1048 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1049 stack_pointer_rtx
));
1051 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1052 m68k_set_frame_related
1053 (emit_insn (gen_link (frame_pointer_rtx
,
1054 GEN_INT (-4 - fsize_with_regs
))));
1057 m68k_set_frame_related
1058 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1059 m68k_set_frame_related
1060 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1062 GEN_INT (-fsize_with_regs
))));
1065 /* If the frame pointer is needed, emit a special barrier that
1066 will prevent the scheduler from moving stores to the frame
1067 before the stack adjustment. */
1068 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1070 else if (fsize_with_regs
!= 0)
1071 m68k_set_frame_related
1072 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1074 GEN_INT (-fsize_with_regs
))));
1076 if (current_frame
.fpu_mask
)
1078 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1080 m68k_set_frame_related
1081 (m68k_emit_movem (stack_pointer_rtx
,
1082 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1083 current_frame
.fpu_no
, FP0_REG
,
1084 current_frame
.fpu_mask
, true, true));
1089 /* If we're using moveml to save the integer registers,
1090 the stack pointer will point to the bottom of the moveml
1091 save area. Find the stack offset of the first FP register. */
1092 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1095 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1096 m68k_set_frame_related
1097 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1098 current_frame
.fpu_no
, FP0_REG
,
1099 current_frame
.fpu_mask
, true, false));
1103 /* If the stack limit is not a symbol, check it here.
1104 This has the disadvantage that it may be too late... */
1105 if (crtl
->limit_stack
)
1107 if (REG_P (stack_limit_rtx
))
1108 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1110 stack_pointer_rtx
, stack_limit_rtx
,
1113 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1114 warning (0, "stack limit expression is not supported");
1117 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1119 /* Store each register separately in the same order moveml does. */
1122 for (i
= 16; i
-- > 0; )
1123 if (current_frame
.reg_mask
& (1 << i
))
1125 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1126 dest
= gen_frame_mem (SImode
,
1127 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1128 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1133 if (TARGET_COLDFIRE
)
1134 /* The required register save space has already been allocated.
1135 The first register should be stored at (%sp). */
1136 m68k_set_frame_related
1137 (m68k_emit_movem (stack_pointer_rtx
, 0,
1138 current_frame
.reg_no
, D0_REG
,
1139 current_frame
.reg_mask
, true, false));
1141 m68k_set_frame_related
1142 (m68k_emit_movem (stack_pointer_rtx
,
1143 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1144 current_frame
.reg_no
, D0_REG
,
1145 current_frame
.reg_mask
, true, true));
1148 if (!TARGET_SEP_DATA
1149 && crtl
->uses_pic_offset_table
)
1150 emit_insn (gen_load_got (pic_offset_table_rtx
));
1153 /* Return true if a simple (return) instruction is sufficient for this
1154 instruction (i.e. if no epilogue is needed). */
1157 m68k_use_return_insn (void)
1159 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1162 m68k_compute_frame_layout ();
1163 return current_frame
.offset
== 0;
1166 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1167 SIBCALL_P says which.
1169 The function epilogue should not depend on the current stack pointer!
1170 It should use the frame pointer only, if there is a frame pointer.
1171 This is mandatory because of alloca; we also take advantage of it to
1172 omit stack adjustments before returning. */
1175 m68k_expand_epilogue (bool sibcall_p
)
1177 HOST_WIDE_INT fsize
, fsize_with_regs
;
1178 bool big
, restore_from_sp
;
1180 m68k_compute_frame_layout ();
1182 fsize
= current_frame
.size
;
1184 restore_from_sp
= false;
1186 /* FIXME : crtl->is_leaf below is too strong.
1187 What we really need to know there is if there could be pending
1188 stack adjustment needed at that point. */
1189 restore_from_sp
= (!frame_pointer_needed
1190 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1192 /* fsize_with_regs is the size we need to adjust the sp when
1193 popping the frame. */
1194 fsize_with_regs
= fsize
;
1195 if (TARGET_COLDFIRE
&& restore_from_sp
)
1197 /* ColdFire's move multiple instructions do not allow post-increment
1198 addressing. Add the size of movem loads to the final deallocation
1200 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1201 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1202 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1203 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1206 if (current_frame
.offset
+ fsize
>= 0x8000
1208 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1211 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1212 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1214 /* ColdFire's move multiple instructions do not support the
1215 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1216 stack-based restore. */
1217 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1218 GEN_INT (-(current_frame
.offset
+ fsize
)));
1219 emit_insn (gen_blockage ());
1220 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1221 gen_rtx_REG (Pmode
, A1_REG
),
1222 frame_pointer_rtx
));
1223 restore_from_sp
= true;
1227 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1233 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1235 /* Restore each register separately in the same order moveml does. */
1237 HOST_WIDE_INT offset
;
1239 offset
= current_frame
.offset
+ fsize
;
1240 for (i
= 0; i
< 16; i
++)
1241 if (current_frame
.reg_mask
& (1 << i
))
1247 /* Generate the address -OFFSET(%fp,%a1.l). */
1248 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1249 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1250 addr
= plus_constant (Pmode
, addr
, -offset
);
1252 else if (restore_from_sp
)
1253 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1255 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1256 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1257 gen_frame_mem (SImode
, addr
));
1258 offset
-= GET_MODE_SIZE (SImode
);
1261 else if (current_frame
.reg_mask
)
1264 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1265 gen_rtx_REG (Pmode
, A1_REG
),
1267 -(current_frame
.offset
+ fsize
),
1268 current_frame
.reg_no
, D0_REG
,
1269 current_frame
.reg_mask
, false, false);
1270 else if (restore_from_sp
)
1271 m68k_emit_movem (stack_pointer_rtx
, 0,
1272 current_frame
.reg_no
, D0_REG
,
1273 current_frame
.reg_mask
, false,
1276 m68k_emit_movem (frame_pointer_rtx
,
1277 -(current_frame
.offset
+ fsize
),
1278 current_frame
.reg_no
, D0_REG
,
1279 current_frame
.reg_mask
, false, false);
1282 if (current_frame
.fpu_no
> 0)
1285 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1286 gen_rtx_REG (Pmode
, A1_REG
),
1288 -(current_frame
.foffset
+ fsize
),
1289 current_frame
.fpu_no
, FP0_REG
,
1290 current_frame
.fpu_mask
, false, false);
1291 else if (restore_from_sp
)
1293 if (TARGET_COLDFIRE
)
1297 /* If we used moveml to restore the integer registers, the
1298 stack pointer will still point to the bottom of the moveml
1299 save area. Find the stack offset of the first FP
1301 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1304 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1305 m68k_emit_movem (stack_pointer_rtx
, offset
,
1306 current_frame
.fpu_no
, FP0_REG
,
1307 current_frame
.fpu_mask
, false, false);
1310 m68k_emit_movem (stack_pointer_rtx
, 0,
1311 current_frame
.fpu_no
, FP0_REG
,
1312 current_frame
.fpu_mask
, false, true);
1315 m68k_emit_movem (frame_pointer_rtx
,
1316 -(current_frame
.foffset
+ fsize
),
1317 current_frame
.fpu_no
, FP0_REG
,
1318 current_frame
.fpu_mask
, false, false);
1321 emit_insn (gen_blockage ());
1322 if (frame_pointer_needed
)
1323 emit_insn (gen_unlink (frame_pointer_rtx
));
1324 else if (fsize_with_regs
)
1325 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1327 GEN_INT (fsize_with_regs
)));
1329 if (crtl
->calls_eh_return
)
1330 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1332 EH_RETURN_STACKADJ_RTX
));
1335 emit_jump_insn (ret_rtx
);
1338 /* Return true if X is a valid comparison operator for the dbcc
1341 Note it rejects floating point comparison operators.
1342 (In the future we could use Fdbcc).
1344 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1347 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1349 switch (GET_CODE (x
))
1351 case EQ
: case NE
: case GTU
: case LTU
:
1355 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1357 case GT
: case LT
: case GE
: case LE
:
1358 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1364 /* Return nonzero if flags are currently in the 68881 flag register. */
1366 flags_in_68881 (void)
1368 /* We could add support for these in the future */
1369 return cc_status
.flags
& CC_IN_68881
;
1372 /* Return true if PARALLEL contains register REGNO. */
1374 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1378 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1381 if (GET_CODE (parallel
) != PARALLEL
)
1384 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1388 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1389 if (REG_P (x
) && REGNO (x
) == regno
)
1396 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1399 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1401 enum m68k_function_kind kind
;
1403 /* We cannot use sibcalls for nested functions because we use the
1404 static chain register for indirect calls. */
1405 if (CALL_EXPR_STATIC_CHAIN (exp
))
1408 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1410 /* Check that the return value locations are the same. For
1411 example that we aren't returning a value from the sibling in
1412 a D0 register but then need to transfer it to a A0 register. */
1416 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1418 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1420 /* Check that the values are equal or that the result the callee
1421 function returns is superset of what the current function returns. */
1422 if (!(rtx_equal_p (cfun_value
, call_value
)
1423 || (REG_P (cfun_value
)
1424 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1428 kind
= m68k_get_function_kind (current_function_decl
);
1429 if (kind
== m68k_fk_normal_function
)
1430 /* We can always sibcall from a normal function, because it's
1431 undefined if it is calling an interrupt function. */
1434 /* Otherwise we can only sibcall if the function kind is known to be
1436 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1442 /* On the m68k all args are always pushed. */
1445 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1446 machine_mode mode ATTRIBUTE_UNUSED
,
1447 const_tree type ATTRIBUTE_UNUSED
,
1448 bool named ATTRIBUTE_UNUSED
)
1454 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1455 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1457 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1459 *cum
+= (mode
!= BLKmode
1460 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1461 : (int_size_in_bytes (type
) + 3) & ~3);
1464 /* Convert X to a legitimate function call memory reference and return the
1468 m68k_legitimize_call_address (rtx x
)
1470 gcc_assert (MEM_P (x
));
1471 if (call_operand (XEXP (x
, 0), VOIDmode
))
1473 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1476 /* Likewise for sibling calls. */
1479 m68k_legitimize_sibcall_address (rtx x
)
1481 gcc_assert (MEM_P (x
));
1482 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1485 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1486 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1489 /* Convert X to a legitimate address and return it if successful. Otherwise
1492 For the 68000, we handle X+REG by loading X into a register R and
1493 using R+REG. R will go in an address reg and indexing will be used.
1494 However, if REG is a broken-out memory address or multiplication,
1495 nothing needs to be done because REG can certainly go in an address reg. */
1498 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1500 if (m68k_tls_symbol_p (x
))
1501 return m68k_legitimize_tls_address (x
);
1503 if (GET_CODE (x
) == PLUS
)
1505 int ch
= (x
) != (oldx
);
1508 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1510 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1513 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1515 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1518 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1522 if (GET_CODE (XEXP (x
, 1)) == REG
1523 && GET_CODE (XEXP (x
, 0)) == REG
)
1525 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1528 x
= force_operand (x
, 0);
1532 if (memory_address_p (mode
, x
))
1535 if (GET_CODE (XEXP (x
, 0)) == REG
1536 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1537 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1538 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1540 rtx temp
= gen_reg_rtx (Pmode
);
1541 rtx val
= force_operand (XEXP (x
, 1), 0);
1542 emit_move_insn (temp
, val
);
1545 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1546 && GET_CODE (XEXP (x
, 0)) == REG
)
1547 x
= force_operand (x
, 0);
1549 else if (GET_CODE (XEXP (x
, 1)) == REG
1550 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1551 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1552 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1554 rtx temp
= gen_reg_rtx (Pmode
);
1555 rtx val
= force_operand (XEXP (x
, 0), 0);
1556 emit_move_insn (temp
, val
);
1559 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1560 && GET_CODE (XEXP (x
, 1)) == REG
)
1561 x
= force_operand (x
, 0);
1569 /* Output a dbCC; jCC sequence. Note we do not handle the
1570 floating point version of this sequence (Fdbcc). We also
1571 do not handle alternative conditions when CC_NO_OVERFLOW is
1572 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1573 kick those out before we get here. */
1576 output_dbcc_and_branch (rtx
*operands
)
1578 switch (GET_CODE (operands
[3]))
1581 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1585 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1589 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1593 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1597 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1601 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1605 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1609 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1613 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1617 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1624 /* If the decrement is to be done in SImode, then we have
1625 to compensate for the fact that dbcc decrements in HImode. */
1626 switch (GET_MODE (operands
[0]))
1629 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1641 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1644 enum rtx_code op_code
= GET_CODE (op
);
1646 /* This does not produce a useful cc. */
1649 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1650 below. Swap the operands and change the op if these requirements
1651 are not fulfilled. */
1652 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1656 operand1
= operand2
;
1658 op_code
= swap_condition (op_code
);
1660 loperands
[0] = operand1
;
1661 if (GET_CODE (operand1
) == REG
)
1662 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1664 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1665 if (operand2
!= const0_rtx
)
1667 loperands
[2] = operand2
;
1668 if (GET_CODE (operand2
) == REG
)
1669 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1671 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1673 loperands
[4] = gen_label_rtx ();
1674 if (operand2
!= const0_rtx
)
1675 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1678 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1679 output_asm_insn ("tst%.l %0", loperands
);
1681 output_asm_insn ("cmp%.w #0,%0", loperands
);
1683 output_asm_insn ("jne %l4", loperands
);
1685 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1686 output_asm_insn ("tst%.l %1", loperands
);
1688 output_asm_insn ("cmp%.w #0,%1", loperands
);
1691 loperands
[5] = dest
;
1696 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1697 CODE_LABEL_NUMBER (loperands
[4]));
1698 output_asm_insn ("seq %5", loperands
);
1702 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1703 CODE_LABEL_NUMBER (loperands
[4]));
1704 output_asm_insn ("sne %5", loperands
);
1708 loperands
[6] = gen_label_rtx ();
1709 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1710 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1711 CODE_LABEL_NUMBER (loperands
[4]));
1712 output_asm_insn ("sgt %5", loperands
);
1713 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1714 CODE_LABEL_NUMBER (loperands
[6]));
1718 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1719 CODE_LABEL_NUMBER (loperands
[4]));
1720 output_asm_insn ("shi %5", loperands
);
1724 loperands
[6] = gen_label_rtx ();
1725 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1726 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1727 CODE_LABEL_NUMBER (loperands
[4]));
1728 output_asm_insn ("slt %5", loperands
);
1729 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1730 CODE_LABEL_NUMBER (loperands
[6]));
1734 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1735 CODE_LABEL_NUMBER (loperands
[4]));
1736 output_asm_insn ("scs %5", loperands
);
1740 loperands
[6] = gen_label_rtx ();
1741 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1742 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1743 CODE_LABEL_NUMBER (loperands
[4]));
1744 output_asm_insn ("sge %5", loperands
);
1745 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1746 CODE_LABEL_NUMBER (loperands
[6]));
1750 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1751 CODE_LABEL_NUMBER (loperands
[4]));
1752 output_asm_insn ("scc %5", loperands
);
1756 loperands
[6] = gen_label_rtx ();
1757 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1758 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1759 CODE_LABEL_NUMBER (loperands
[4]));
1760 output_asm_insn ("sle %5", loperands
);
1761 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1762 CODE_LABEL_NUMBER (loperands
[6]));
1766 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1767 CODE_LABEL_NUMBER (loperands
[4]));
1768 output_asm_insn ("sls %5", loperands
);
1778 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1780 operands
[0] = countop
;
1781 operands
[1] = dataop
;
1783 if (GET_CODE (countop
) == CONST_INT
)
1785 register int count
= INTVAL (countop
);
1786 /* If COUNT is bigger than size of storage unit in use,
1787 advance to the containing unit of same size. */
1788 if (count
> signpos
)
1790 int offset
= (count
& ~signpos
) / 8;
1791 count
= count
& signpos
;
1792 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1794 if (count
== signpos
)
1795 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1797 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1799 /* These three statements used to use next_insns_test_no...
1800 but it appears that this should do the same job. */
1802 && next_insn_tests_no_inequality (insn
))
1805 && next_insn_tests_no_inequality (insn
))
1808 && next_insn_tests_no_inequality (insn
))
1810 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1811 On some m68k variants unfortunately that's slower than btst.
1812 On 68000 and higher, that should also work for all HImode operands. */
1813 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1815 if (count
== 3 && DATA_REG_P (operands
[1])
1816 && next_insn_tests_no_inequality (insn
))
1818 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1819 return "move%.w %1,%%ccr";
1821 if (count
== 2 && DATA_REG_P (operands
[1])
1822 && next_insn_tests_no_inequality (insn
))
1824 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1825 return "move%.w %1,%%ccr";
1827 /* count == 1 followed by bvc/bvs and
1828 count == 0 followed by bcc/bcs are also possible, but need
1829 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1832 cc_status
.flags
= CC_NOT_NEGATIVE
;
1834 return "btst %0,%1";
1837 /* Return true if X is a legitimate base register. STRICT_P says
1838 whether we need strict checking. */
1841 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1843 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1844 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1849 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1850 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1853 /* Return true if X is a legitimate index register. STRICT_P says
1854 whether we need strict checking. */
1857 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1859 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1864 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1865 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1868 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1869 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1870 ADDRESS if so. STRICT_P says whether we need strict checking. */
1873 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1877 /* Check for a scale factor. */
1879 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1880 && GET_CODE (x
) == MULT
1881 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1882 && (INTVAL (XEXP (x
, 1)) == 2
1883 || INTVAL (XEXP (x
, 1)) == 4
1884 || (INTVAL (XEXP (x
, 1)) == 8
1885 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1887 scale
= INTVAL (XEXP (x
, 1));
1891 /* Check for a word extension. */
1892 if (!TARGET_COLDFIRE
1893 && GET_CODE (x
) == SIGN_EXTEND
1894 && GET_MODE (XEXP (x
, 0)) == HImode
)
1897 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1899 address
->scale
= scale
;
1907 /* Return true if X is an illegitimate symbolic constant. */
1910 m68k_illegitimate_symbolic_constant_p (rtx x
)
1914 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1916 split_const (x
, &base
, &offset
);
1917 if (GET_CODE (base
) == SYMBOL_REF
1918 && !offset_within_block_p (base
, INTVAL (offset
)))
1921 return m68k_tls_reference_p (x
, false);
1924 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1927 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1929 return m68k_illegitimate_symbolic_constant_p (x
);
1932 /* Return true if X is a legitimate constant address that can reach
1933 bytes in the range [X, X + REACH). STRICT_P says whether we need
1937 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1941 if (!CONSTANT_ADDRESS_P (x
))
1945 && !(strict_p
&& TARGET_PCREL
)
1946 && symbolic_operand (x
, VOIDmode
))
1949 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1951 split_const (x
, &base
, &offset
);
1952 if (GET_CODE (base
) == SYMBOL_REF
1953 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1957 return !m68k_tls_reference_p (x
, false);
1960 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1961 labels will become jump tables. */
1964 m68k_jump_table_ref_p (rtx x
)
1966 if (GET_CODE (x
) != LABEL_REF
)
1969 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1970 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1973 insn
= next_nonnote_insn (insn
);
1974 return insn
&& JUMP_TABLE_DATA_P (insn
);
1977 /* Return true if X is a legitimate address for values of mode MODE.
1978 STRICT_P says whether strict checking is needed. If the address
1979 is valid, describe its components in *ADDRESS. */
1982 m68k_decompose_address (machine_mode mode
, rtx x
,
1983 bool strict_p
, struct m68k_address
*address
)
1987 memset (address
, 0, sizeof (*address
));
1989 if (mode
== BLKmode
)
1992 reach
= GET_MODE_SIZE (mode
);
1994 /* Check for (An) (mode 2). */
1995 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2001 /* Check for -(An) and (An)+ (modes 3 and 4). */
2002 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
2003 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2005 address
->code
= GET_CODE (x
);
2006 address
->base
= XEXP (x
, 0);
2010 /* Check for (d16,An) (mode 5). */
2011 if (GET_CODE (x
) == PLUS
2012 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2013 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2014 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2016 address
->base
= XEXP (x
, 0);
2017 address
->offset
= XEXP (x
, 1);
2021 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2022 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2024 if (GET_CODE (x
) == PLUS
2025 && XEXP (x
, 0) == pic_offset_table_rtx
)
2027 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2028 they are invalid in this context. */
2029 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2031 address
->base
= XEXP (x
, 0);
2032 address
->offset
= XEXP (x
, 1);
2037 /* The ColdFire FPU only accepts addressing modes 2-5. */
2038 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2041 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2042 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2043 All these modes are variations of mode 7. */
2044 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2046 address
->offset
= x
;
2050 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2053 ??? do_tablejump creates these addresses before placing the target
2054 label, so we have to assume that unplaced labels are jump table
2055 references. It seems unlikely that we would ever generate indexed
2056 accesses to unplaced labels in other cases. */
2057 if (GET_CODE (x
) == PLUS
2058 && m68k_jump_table_ref_p (XEXP (x
, 1))
2059 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2061 address
->offset
= XEXP (x
, 1);
2065 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2066 (bd,An,Xn.SIZE*SCALE) addresses. */
2070 /* Check for a nonzero base displacement. */
2071 if (GET_CODE (x
) == PLUS
2072 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2074 address
->offset
= XEXP (x
, 1);
2078 /* Check for a suppressed index register. */
2079 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2085 /* Check for a suppressed base register. Do not allow this case
2086 for non-symbolic offsets as it effectively gives gcc freedom
2087 to treat data registers as base registers, which can generate
2090 && symbolic_operand (address
->offset
, VOIDmode
)
2091 && m68k_decompose_index (x
, strict_p
, address
))
2096 /* Check for a nonzero base displacement. */
2097 if (GET_CODE (x
) == PLUS
2098 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2099 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2101 address
->offset
= XEXP (x
, 1);
2106 /* We now expect the sum of a base and an index. */
2107 if (GET_CODE (x
) == PLUS
)
2109 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2110 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2112 address
->base
= XEXP (x
, 0);
2116 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2117 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2119 address
->base
= XEXP (x
, 1);
2126 /* Return true if X is a legitimate address for values of mode MODE.
2127 STRICT_P says whether strict checking is needed. */
2130 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2132 struct m68k_address address
;
2134 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2137 /* Return true if X is a memory, describing its address in ADDRESS if so.
2138 Apply strict checking if called during or after reload. */
2141 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2144 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2145 reload_in_progress
|| reload_completed
,
2149 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2152 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2154 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2157 /* Return true if X matches the 'Q' constraint. It must be a memory
2158 with a base address and no constant offset or index. */
2161 m68k_matches_q_p (rtx x
)
2163 struct m68k_address address
;
2165 return (m68k_legitimate_mem_p (x
, &address
)
2166 && address
.code
== UNKNOWN
2172 /* Return true if X matches the 'U' constraint. It must be a base address
2173 with a constant offset and no index. */
2176 m68k_matches_u_p (rtx x
)
2178 struct m68k_address address
;
2180 return (m68k_legitimate_mem_p (x
, &address
)
2181 && address
.code
== UNKNOWN
2187 /* Return GOT pointer. */
2192 if (pic_offset_table_rtx
== NULL_RTX
)
2193 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2195 crtl
->uses_pic_offset_table
= 1;
2197 return pic_offset_table_rtx
;
2200 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2202 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2203 RELOC_TLSIE
, RELOC_TLSLE
};
2205 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2207 /* Wrap symbol X into unspec representing relocation RELOC.
2208 BASE_REG - register that should be added to the result.
2209 TEMP_REG - if non-null, temporary register. */
2212 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2216 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2218 if (TARGET_COLDFIRE
&& use_x_p
)
2219 /* When compiling with -mx{got, tls} switch the code will look like this:
2221 move.l <X>@<RELOC>,<TEMP_REG>
2222 add.l <BASE_REG>,<TEMP_REG> */
2224 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2225 to put @RELOC after reference. */
2226 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2228 x
= gen_rtx_CONST (Pmode
, x
);
2230 if (temp_reg
== NULL
)
2232 gcc_assert (can_create_pseudo_p ());
2233 temp_reg
= gen_reg_rtx (Pmode
);
2236 emit_move_insn (temp_reg
, x
);
2237 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2242 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2244 x
= gen_rtx_CONST (Pmode
, x
);
2246 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2252 /* Helper for m68k_unwrap_symbol.
2253 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2254 sets *RELOC_PTR to relocation type for the symbol. */
2257 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2258 enum m68k_reloc
*reloc_ptr
)
2260 if (GET_CODE (orig
) == CONST
)
2263 enum m68k_reloc dummy
;
2267 if (reloc_ptr
== NULL
)
2270 /* Handle an addend. */
2271 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2272 && CONST_INT_P (XEXP (x
, 1)))
2275 if (GET_CODE (x
) == UNSPEC
)
2277 switch (XINT (x
, 1))
2279 case UNSPEC_RELOC16
:
2280 orig
= XVECEXP (x
, 0, 0);
2281 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2284 case UNSPEC_RELOC32
:
2285 if (unwrap_reloc32_p
)
2287 orig
= XVECEXP (x
, 0, 0);
2288 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2301 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2302 UNSPEC_RELOC32 wrappers. */
2305 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2307 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2310 /* Prescan insn before outputing assembler for it. */
2313 m68k_final_prescan_insn (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2314 rtx
*operands
, int n_operands
)
2318 /* Combine and, possibly, other optimizations may do good job
2320 (const (unspec [(symbol)]))
2322 (const (plus (unspec [(symbol)])
2324 The problem with this is emitting @TLS or @GOT decorations.
2325 The decoration is emitted when processing (unspec), so the
2326 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2328 It seems that the easiest solution to this is to convert such
2330 (const (unspec [(plus (symbol)
2332 Note, that the top level of operand remains intact, so we don't have
2333 to patch up anything outside of the operand. */
2335 subrtx_var_iterator::array_type array
;
2336 for (i
= 0; i
< n_operands
; ++i
)
2342 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2345 if (m68k_unwrap_symbol (x
, true) != x
)
2349 gcc_assert (GET_CODE (x
) == CONST
);
2352 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2357 unspec
= XEXP (plus
, 0);
2358 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2359 addend
= XEXP (plus
, 1);
2360 gcc_assert (CONST_INT_P (addend
));
2362 /* We now have all the pieces, rearrange them. */
2364 /* Move symbol to plus. */
2365 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2367 /* Move plus inside unspec. */
2368 XVECEXP (unspec
, 0, 0) = plus
;
2370 /* Move unspec to top level of const. */
2371 XEXP (x
, 0) = unspec
;
2373 iter
.skip_subrtxes ();
2379 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2380 If REG is non-null, use it; generate new pseudo otherwise. */
2383 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2387 if (reg
== NULL_RTX
)
2389 gcc_assert (can_create_pseudo_p ());
2390 reg
= gen_reg_rtx (Pmode
);
2393 insn
= emit_move_insn (reg
, x
);
2394 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2396 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2401 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2405 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2407 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2409 x
= gen_rtx_MEM (Pmode
, x
);
2410 MEM_READONLY_P (x
) = 1;
2415 /* Legitimize PIC addresses. If the address is already
2416 position-independent, we return ORIG. Newly generated
2417 position-independent addresses go to REG. If we need more
2418 than one register, we lose.
2420 An address is legitimized by making an indirect reference
2421 through the Global Offset Table with the name of the symbol
2424 The assembler and linker are responsible for placing the
2425 address of the symbol in the GOT. The function prologue
2426 is responsible for initializing a5 to the starting address
2429 The assembler is also responsible for translating a symbol name
2430 into a constant displacement from the start of the GOT.
2432 A quick example may make things a little clearer:
2434 When not generating PIC code to store the value 12345 into _foo
2435 we would generate the following code:
2439 When generating PIC two transformations are made. First, the compiler
2440 loads the address of foo into a register. So the first transformation makes:
2445 The code in movsi will intercept the lea instruction and call this
2446 routine which will transform the instructions into:
2448 movel a5@(_foo:w), a0
2452 That (in a nutshell) is how *all* symbol and label references are
2456 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2461 /* First handle a simple SYMBOL_REF or LABEL_REF */
2462 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2466 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2467 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2469 else if (GET_CODE (orig
) == CONST
)
2473 /* Make sure this has not already been legitimized. */
2474 if (m68k_unwrap_symbol (orig
, true) != orig
)
2479 /* legitimize both operands of the PLUS */
2480 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2482 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2483 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2484 base
== reg
? 0 : reg
);
2486 if (GET_CODE (orig
) == CONST_INT
)
2487 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2489 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2495 /* The __tls_get_addr symbol. */
2496 static GTY(()) rtx m68k_tls_get_addr
;
2498 /* Return SYMBOL_REF for __tls_get_addr. */
2501 m68k_get_tls_get_addr (void)
2503 if (m68k_tls_get_addr
== NULL_RTX
)
2504 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2506 return m68k_tls_get_addr
;
2509 /* Return libcall result in A0 instead of usual D0. */
2510 static bool m68k_libcall_value_in_a0_p
= false;
2512 /* Emit instruction sequence that calls __tls_get_addr. X is
2513 the TLS symbol we are referencing and RELOC is the symbol type to use
2514 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2515 emitted. A pseudo register with result of __tls_get_addr call is
2519 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2525 /* Emit the call sequence. */
2528 /* FIXME: Unfortunately, emit_library_call_value does not
2529 consider (plus (%a5) (const (unspec))) to be a good enough
2530 operand for push, so it forces it into a register. The bad
2531 thing about this is that combiner, due to copy propagation and other
2532 optimizations, sometimes can not later fix this. As a consequence,
2533 additional register may be allocated resulting in a spill.
2534 For reference, see args processing loops in
2535 calls.c:emit_library_call_value_1.
2536 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2537 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2539 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2540 is the simpliest way of generating a call. The difference between
2541 __tls_get_addr() and libcall is that the result is returned in D0
2542 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2543 which temporarily switches returning the result to A0. */
2545 m68k_libcall_value_in_a0_p
= true;
2546 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2548 m68k_libcall_value_in_a0_p
= false;
2550 insns
= get_insns ();
2553 gcc_assert (can_create_pseudo_p ());
2554 dest
= gen_reg_rtx (Pmode
);
2555 emit_libcall_block (insns
, dest
, a0
, eqv
);
2560 /* The __tls_get_addr symbol. */
2561 static GTY(()) rtx m68k_read_tp
;
2563 /* Return SYMBOL_REF for __m68k_read_tp. */
2566 m68k_get_m68k_read_tp (void)
2568 if (m68k_read_tp
== NULL_RTX
)
2569 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2571 return m68k_read_tp
;
2574 /* Emit instruction sequence that calls __m68k_read_tp.
2575 A pseudo register with result of __m68k_read_tp call is returned. */
2578 m68k_call_m68k_read_tp (void)
2587 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2588 is the simpliest way of generating a call. The difference between
2589 __m68k_read_tp() and libcall is that the result is returned in D0
2590 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2591 which temporarily switches returning the result to A0. */
2593 /* Emit the call sequence. */
2594 m68k_libcall_value_in_a0_p
= true;
2595 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2597 m68k_libcall_value_in_a0_p
= false;
2598 insns
= get_insns ();
2601 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2602 share the m68k_read_tp result with other IE/LE model accesses. */
2603 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2605 gcc_assert (can_create_pseudo_p ());
2606 dest
= gen_reg_rtx (Pmode
);
2607 emit_libcall_block (insns
, dest
, a0
, eqv
);
2612 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2613 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2617 m68k_legitimize_tls_address (rtx orig
)
2619 switch (SYMBOL_REF_TLS_MODEL (orig
))
2621 case TLS_MODEL_GLOBAL_DYNAMIC
:
2622 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2625 case TLS_MODEL_LOCAL_DYNAMIC
:
2631 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2632 share the LDM result with other LD model accesses. */
2633 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2636 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2638 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2640 if (can_create_pseudo_p ())
2641 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2647 case TLS_MODEL_INITIAL_EXEC
:
2652 a0
= m68k_call_m68k_read_tp ();
2654 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2655 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2657 if (can_create_pseudo_p ())
2658 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2664 case TLS_MODEL_LOCAL_EXEC
:
2669 a0
= m68k_call_m68k_read_tp ();
2671 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2673 if (can_create_pseudo_p ())
2674 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2687 /* Return true if X is a TLS symbol. */
2690 m68k_tls_symbol_p (rtx x
)
2692 if (!TARGET_HAVE_TLS
)
2695 if (GET_CODE (x
) != SYMBOL_REF
)
2698 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2701 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2702 though illegitimate one.
2703 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2706 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2708 if (!TARGET_HAVE_TLS
)
2713 subrtx_var_iterator::array_type array
;
2714 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2718 /* Note: this is not the same as m68k_tls_symbol_p. */
2719 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2722 /* Don't recurse into legitimate TLS references. */
2723 if (m68k_tls_reference_p (x
, true))
2724 iter
.skip_subrtxes ();
2730 enum m68k_reloc reloc
= RELOC_GOT
;
2732 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2733 && TLS_RELOC_P (reloc
));
2739 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2741 /* Return the type of move that should be used for integer I. */
2744 m68k_const_method (HOST_WIDE_INT i
)
2751 /* The ColdFire doesn't have byte or word operations. */
2752 /* FIXME: This may not be useful for the m68060 either. */
2753 if (!TARGET_COLDFIRE
)
2755 /* if -256 < N < 256 but N is not in range for a moveq
2756 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2757 if (USE_MOVQ (i
^ 0xff))
2759 /* Likewise, try with not.w */
2760 if (USE_MOVQ (i
^ 0xffff))
2762 /* This is the only value where neg.w is useful */
2767 /* Try also with swap. */
2769 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2774 /* Try using MVZ/MVS with an immediate value to load constants. */
2775 if (i
>= 0 && i
<= 65535)
2777 if (i
>= -32768 && i
<= 32767)
2781 /* Otherwise, use move.l */
2785 /* Return the cost of moving constant I into a data register. */
2788 const_int_cost (HOST_WIDE_INT i
)
2790 switch (m68k_const_method (i
))
2793 /* Constants between -128 and 127 are cheap due to moveq. */
2801 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2811 m68k_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2812 int opno ATTRIBUTE_UNUSED
,
2813 int *total
, bool speed ATTRIBUTE_UNUSED
)
2815 int code
= GET_CODE (x
);
2820 /* Constant zero is super cheap due to clr instruction. */
2821 if (x
== const0_rtx
)
2824 *total
= const_int_cost (INTVAL (x
));
2834 /* Make 0.0 cheaper than other floating constants to
2835 encourage creating tstsf and tstdf insns. */
2836 if (outer_code
== COMPARE
2837 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2843 /* These are vaguely right for a 68020. */
2844 /* The costs for long multiply have been adjusted to work properly
2845 in synth_mult on the 68020, relative to an average of the time
2846 for add and the time for shift, taking away a little more because
2847 sometimes move insns are needed. */
2848 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2853 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2854 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2856 : TARGET_COLDFIRE ? 3 : 13)
2861 : TUNE_68000_10 ? 5 \
2862 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2863 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2865 : TARGET_COLDFIRE ? 2 : 8)
2868 (TARGET_CF_HWDIV ? 11 \
2869 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2872 /* An lea costs about three times as much as a simple add. */
2874 && GET_CODE (XEXP (x
, 1)) == REG
2875 && GET_CODE (XEXP (x
, 0)) == MULT
2876 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2877 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2878 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2879 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2880 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2882 /* lea an@(dx:l:i),am */
2883 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2893 *total
= COSTS_N_INSNS(1);
2898 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2900 if (INTVAL (XEXP (x
, 1)) < 16)
2901 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2903 /* We're using clrw + swap for these cases. */
2904 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2907 *total
= COSTS_N_INSNS (10); /* Worst case. */
2910 /* A shift by a big integer takes an extra instruction. */
2911 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2912 && (INTVAL (XEXP (x
, 1)) == 16))
2914 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2917 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2918 && !(INTVAL (XEXP (x
, 1)) > 0
2919 && INTVAL (XEXP (x
, 1)) <= 8))
2921 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2927 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2928 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2930 *total
= COSTS_N_INSNS (MULW_COST
);
2931 else if (mode
== QImode
|| mode
== HImode
)
2932 *total
= COSTS_N_INSNS (MULW_COST
);
2934 *total
= COSTS_N_INSNS (MULL_COST
);
2941 if (mode
== QImode
|| mode
== HImode
)
2942 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2943 else if (TARGET_CF_HWDIV
)
2944 *total
= COSTS_N_INSNS (18);
2946 *total
= COSTS_N_INSNS (43); /* div.l */
2950 if (outer_code
== COMPARE
)
2959 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2963 output_move_const_into_data_reg (rtx
*operands
)
2967 i
= INTVAL (operands
[1]);
2968 switch (m68k_const_method (i
))
2971 return "mvzw %1,%0";
2973 return "mvsw %1,%0";
2975 return "moveq %1,%0";
2978 operands
[1] = GEN_INT (i
^ 0xff);
2979 return "moveq %1,%0\n\tnot%.b %0";
2982 operands
[1] = GEN_INT (i
^ 0xffff);
2983 return "moveq %1,%0\n\tnot%.w %0";
2986 return "moveq #-128,%0\n\tneg%.w %0";
2991 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2992 return "moveq %1,%0\n\tswap %0";
2995 return "move%.l %1,%0";
3001 /* Return true if I can be handled by ISA B's mov3q instruction. */
3004 valid_mov3q_const (HOST_WIDE_INT i
)
3006 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3009 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3010 I is the value of OPERANDS[1]. */
3013 output_move_simode_const (rtx
*operands
)
3019 src
= INTVAL (operands
[1]);
3021 && (DATA_REG_P (dest
) || MEM_P (dest
))
3022 /* clr insns on 68000 read before writing. */
3023 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3024 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3026 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3027 return "mov3q%.l %1,%0";
3028 else if (src
== 0 && ADDRESS_REG_P (dest
))
3029 return "sub%.l %0,%0";
3030 else if (DATA_REG_P (dest
))
3031 return output_move_const_into_data_reg (operands
);
3032 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3034 if (valid_mov3q_const (src
))
3035 return "mov3q%.l %1,%0";
3036 return "move%.w %1,%0";
3038 else if (MEM_P (dest
)
3039 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3040 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3041 && IN_RANGE (src
, -0x8000, 0x7fff))
3043 if (valid_mov3q_const (src
))
3044 return "mov3q%.l %1,%-";
3047 return "move%.l %1,%0";
3051 output_move_simode (rtx
*operands
)
3053 if (GET_CODE (operands
[1]) == CONST_INT
)
3054 return output_move_simode_const (operands
);
3055 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3056 || GET_CODE (operands
[1]) == CONST
)
3057 && push_operand (operands
[0], SImode
))
3059 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3060 || GET_CODE (operands
[1]) == CONST
)
3061 && ADDRESS_REG_P (operands
[0]))
3062 return "lea %a1,%0";
3063 return "move%.l %1,%0";
3067 output_move_himode (rtx
*operands
)
3069 if (GET_CODE (operands
[1]) == CONST_INT
)
3071 if (operands
[1] == const0_rtx
3072 && (DATA_REG_P (operands
[0])
3073 || GET_CODE (operands
[0]) == MEM
)
3074 /* clr insns on 68000 read before writing. */
3075 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3076 || !(GET_CODE (operands
[0]) == MEM
3077 && MEM_VOLATILE_P (operands
[0]))))
3079 else if (operands
[1] == const0_rtx
3080 && ADDRESS_REG_P (operands
[0]))
3081 return "sub%.l %0,%0";
3082 else if (DATA_REG_P (operands
[0])
3083 && INTVAL (operands
[1]) < 128
3084 && INTVAL (operands
[1]) >= -128)
3085 return "moveq %1,%0";
3086 else if (INTVAL (operands
[1]) < 0x8000
3087 && INTVAL (operands
[1]) >= -0x8000)
3088 return "move%.w %1,%0";
3090 else if (CONSTANT_P (operands
[1]))
3091 return "move%.l %1,%0";
3092 return "move%.w %1,%0";
3096 output_move_qimode (rtx
*operands
)
3098 /* 68k family always modifies the stack pointer by at least 2, even for
3099 byte pushes. The 5200 (ColdFire) does not do this. */
3101 /* This case is generated by pushqi1 pattern now. */
3102 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3103 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3104 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3105 && ! ADDRESS_REG_P (operands
[1])
3106 && ! TARGET_COLDFIRE
));
3108 /* clr and st insns on 68000 read before writing. */
3109 if (!ADDRESS_REG_P (operands
[0])
3110 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3111 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3113 if (operands
[1] == const0_rtx
)
3115 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3116 && GET_CODE (operands
[1]) == CONST_INT
3117 && (INTVAL (operands
[1]) & 255) == 255)
3123 if (GET_CODE (operands
[1]) == CONST_INT
3124 && DATA_REG_P (operands
[0])
3125 && INTVAL (operands
[1]) < 128
3126 && INTVAL (operands
[1]) >= -128)
3127 return "moveq %1,%0";
3128 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3129 return "sub%.l %0,%0";
3130 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3131 return "move%.l %1,%0";
3132 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3133 from address registers. */
3134 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3135 return "move%.w %1,%0";
3136 return "move%.b %1,%0";
3140 output_move_stricthi (rtx
*operands
)
3142 if (operands
[1] == const0_rtx
3143 /* clr insns on 68000 read before writing. */
3144 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3145 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3147 return "move%.w %1,%0";
3151 output_move_strictqi (rtx
*operands
)
3153 if (operands
[1] == const0_rtx
3154 /* clr insns on 68000 read before writing. */
3155 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3156 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3158 return "move%.b %1,%0";
3161 /* Return the best assembler insn template
3162 for moving operands[1] into operands[0] as a fullword. */
3165 singlemove_string (rtx
*operands
)
3167 if (GET_CODE (operands
[1]) == CONST_INT
)
3168 return output_move_simode_const (operands
);
3169 return "move%.l %1,%0";
3173 /* Output assembler or rtl code to perform a doubleword move insn
3174 with operands OPERANDS.
3175 Pointers to 3 helper functions should be specified:
3176 HANDLE_REG_ADJUST to adjust a register by a small value,
3177 HANDLE_COMPADR to compute an address and
3178 HANDLE_MOVSI to move 4 bytes. */
3181 handle_move_double (rtx operands
[2],
3182 void (*handle_reg_adjust
) (rtx
, int),
3183 void (*handle_compadr
) (rtx
[2]),
3184 void (*handle_movsi
) (rtx
[2]))
3188 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3193 rtx addreg0
= 0, addreg1
= 0;
3194 int dest_overlapped_low
= 0;
3195 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3200 /* First classify both operands. */
3202 if (REG_P (operands
[0]))
3204 else if (offsettable_memref_p (operands
[0]))
3206 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3208 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3210 else if (GET_CODE (operands
[0]) == MEM
)
3215 if (REG_P (operands
[1]))
3217 else if (CONSTANT_P (operands
[1]))
3219 else if (offsettable_memref_p (operands
[1]))
3221 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3223 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3225 else if (GET_CODE (operands
[1]) == MEM
)
3230 /* Check for the cases that the operand constraints are not supposed
3231 to allow to happen. Generating code for these cases is
3233 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3235 /* If one operand is decrementing and one is incrementing
3236 decrement the former register explicitly
3237 and change that operand into ordinary indexing. */
3239 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3241 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3243 handle_reg_adjust (operands
[0], -size
);
3245 if (GET_MODE (operands
[1]) == XFmode
)
3246 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3247 else if (GET_MODE (operands
[0]) == DFmode
)
3248 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3250 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3253 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3255 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3257 handle_reg_adjust (operands
[1], -size
);
3259 if (GET_MODE (operands
[1]) == XFmode
)
3260 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3261 else if (GET_MODE (operands
[1]) == DFmode
)
3262 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3264 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3268 /* If an operand is an unoffsettable memory ref, find a register
3269 we can increment temporarily to make it refer to the second word. */
3271 if (optype0
== MEMOP
)
3272 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3274 if (optype1
== MEMOP
)
3275 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3277 /* Ok, we can do one word at a time.
3278 Normally we do the low-numbered word first,
3279 but if either operand is autodecrementing then we
3280 do the high-numbered word first.
3282 In either case, set up in LATEHALF the operands to use
3283 for the high-numbered word and in some cases alter the
3284 operands in OPERANDS to be suitable for the low-numbered word. */
3288 if (optype0
== REGOP
)
3290 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3291 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3293 else if (optype0
== OFFSOP
)
3295 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3296 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3300 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3301 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3304 if (optype1
== REGOP
)
3306 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3307 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3309 else if (optype1
== OFFSOP
)
3311 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3312 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3314 else if (optype1
== CNSTOP
)
3316 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3320 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3321 (*CONST_DOUBLE_REAL_VALUE (operands
[1]), l
);
3322 operands
[1] = GEN_INT (l
[0]);
3323 middlehalf
[1] = GEN_INT (l
[1]);
3324 latehalf
[1] = GEN_INT (l
[2]);
3328 /* No non-CONST_DOUBLE constant should ever appear
3330 gcc_assert (!CONSTANT_P (operands
[1]));
3335 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3336 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3340 /* size is not 12: */
3342 if (optype0
== REGOP
)
3343 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3344 else if (optype0
== OFFSOP
)
3345 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3347 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3349 if (optype1
== REGOP
)
3350 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3351 else if (optype1
== OFFSOP
)
3352 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3353 else if (optype1
== CNSTOP
)
3354 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3356 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3359 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3360 word first. We should use the adjusted operand 1 (which is N+4(REG))
3361 for the low word as well, to compensate for the first decrement of
3363 if (optype0
== PUSHOP
3364 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3365 operands
[1] = middlehalf
[1] = latehalf
[1];
3367 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3368 if the upper part of reg N does not appear in the MEM, arrange to
3369 emit the move late-half first. Otherwise, compute the MEM address
3370 into the upper part of N and use that as a pointer to the memory
3372 if (optype0
== REGOP
3373 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3375 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3377 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3378 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3380 /* If both halves of dest are used in the src memory address,
3381 compute the address into latehalf of dest.
3382 Note that this can't happen if the dest is two data regs. */
3384 xops
[0] = latehalf
[0];
3385 xops
[1] = XEXP (operands
[1], 0);
3387 handle_compadr (xops
);
3388 if (GET_MODE (operands
[1]) == XFmode
)
3390 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3391 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3392 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3396 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3397 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3401 && reg_overlap_mentioned_p (middlehalf
[0],
3402 XEXP (operands
[1], 0)))
3404 /* Check for two regs used by both source and dest.
3405 Note that this can't happen if the dest is all data regs.
3406 It can happen if the dest is d6, d7, a0.
3407 But in that case, latehalf is an addr reg, so
3408 the code at compadr does ok. */
3410 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3411 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3414 /* JRV says this can't happen: */
3415 gcc_assert (!addreg0
&& !addreg1
);
3417 /* Only the middle reg conflicts; simply put it last. */
3418 handle_movsi (operands
);
3419 handle_movsi (latehalf
);
3420 handle_movsi (middlehalf
);
3424 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3425 /* If the low half of dest is mentioned in the source memory
3426 address, the arrange to emit the move late half first. */
3427 dest_overlapped_low
= 1;
3430 /* If one or both operands autodecrementing,
3431 do the two words, high-numbered first. */
3433 /* Likewise, the first move would clobber the source of the second one,
3434 do them in the other order. This happens only for registers;
3435 such overlap can't happen in memory unless the user explicitly
3436 sets it up, and that is an undefined circumstance. */
3438 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3439 || (optype0
== REGOP
&& optype1
== REGOP
3440 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3441 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3442 || dest_overlapped_low
)
3444 /* Make any unoffsettable addresses point at high-numbered word. */
3446 handle_reg_adjust (addreg0
, size
- 4);
3448 handle_reg_adjust (addreg1
, size
- 4);
3451 handle_movsi (latehalf
);
3453 /* Undo the adds we just did. */
3455 handle_reg_adjust (addreg0
, -4);
3457 handle_reg_adjust (addreg1
, -4);
3461 handle_movsi (middlehalf
);
3464 handle_reg_adjust (addreg0
, -4);
3466 handle_reg_adjust (addreg1
, -4);
3469 /* Do low-numbered word. */
3471 handle_movsi (operands
);
3475 /* Normal case: do the two words, low-numbered first. */
3477 m68k_final_prescan_insn (NULL
, operands
, 2);
3478 handle_movsi (operands
);
3480 /* Do the middle one of the three words for long double */
3484 handle_reg_adjust (addreg0
, 4);
3486 handle_reg_adjust (addreg1
, 4);
3488 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3489 handle_movsi (middlehalf
);
3492 /* Make any unoffsettable addresses point at high-numbered word. */
3494 handle_reg_adjust (addreg0
, 4);
3496 handle_reg_adjust (addreg1
, 4);
3499 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3500 handle_movsi (latehalf
);
3502 /* Undo the adds we just did. */
3504 handle_reg_adjust (addreg0
, -(size
- 4));
3506 handle_reg_adjust (addreg1
, -(size
- 4));
3511 /* Output assembler code to adjust REG by N. */
3513 output_reg_adjust (rtx reg
, int n
)
3517 gcc_assert (GET_MODE (reg
) == SImode
3518 && -12 <= n
&& n
!= 0 && n
<= 12);
3523 s
= "add%.l #12,%0";
3527 s
= "addq%.l #8,%0";
3531 s
= "addq%.l #4,%0";
3535 s
= "sub%.l #12,%0";
3539 s
= "subq%.l #8,%0";
3543 s
= "subq%.l #4,%0";
3551 output_asm_insn (s
, ®
);
3554 /* Emit rtl code to adjust REG by N. */
3556 emit_reg_adjust (rtx reg1
, int n
)
3560 gcc_assert (GET_MODE (reg1
) == SImode
3561 && -12 <= n
&& n
!= 0 && n
<= 12);
3563 reg1
= copy_rtx (reg1
);
3564 reg2
= copy_rtx (reg1
);
3567 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3569 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3574 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3576 output_compadr (rtx operands
[2])
3578 output_asm_insn ("lea %a1,%0", operands
);
3581 /* Output the best assembler insn for moving operands[1] into operands[0]
3584 output_movsi (rtx operands
[2])
3586 output_asm_insn (singlemove_string (operands
), operands
);
3589 /* Copy OP and change its mode to MODE. */
3591 copy_operand (rtx op
, machine_mode mode
)
3593 /* ??? This looks really ugly. There must be a better way
3594 to change a mode on the operand. */
3595 if (GET_MODE (op
) != VOIDmode
)
3598 op
= gen_rtx_REG (mode
, REGNO (op
));
3602 PUT_MODE (op
, mode
);
3609 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3611 emit_movsi (rtx operands
[2])
3613 operands
[0] = copy_operand (operands
[0], SImode
);
3614 operands
[1] = copy_operand (operands
[1], SImode
);
3616 emit_insn (gen_movsi (operands
[0], operands
[1]));
3619 /* Output assembler code to perform a doubleword move insn
3620 with operands OPERANDS. */
3622 output_move_double (rtx
*operands
)
3624 handle_move_double (operands
,
3625 output_reg_adjust
, output_compadr
, output_movsi
);
3630 /* Output rtl code to perform a doubleword move insn
3631 with operands OPERANDS. */
3633 m68k_emit_move_double (rtx operands
[2])
3635 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3638 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3639 new rtx with the correct mode. */
3642 force_mode (machine_mode mode
, rtx orig
)
3644 if (mode
== GET_MODE (orig
))
3647 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3650 return gen_rtx_REG (mode
, REGNO (orig
));
3654 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3656 return reg_renumber
&& FP_REG_P (op
);
3659 /* Emit insns to move operands[1] into operands[0].
3661 Return 1 if we have written out everything that needs to be done to
3662 do the move. Otherwise, return 0 and the caller will emit the move
3665 Note SCRATCH_REG may not be in the proper mode depending on how it
3666 will be used. This routine is responsible for creating a new copy
3667 of SCRATCH_REG in the proper mode. */
3670 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3672 register rtx operand0
= operands
[0];
3673 register rtx operand1
= operands
[1];
3677 && reload_in_progress
&& GET_CODE (operand0
) == REG
3678 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3679 operand0
= reg_equiv_mem (REGNO (operand0
));
3680 else if (scratch_reg
3681 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3682 && GET_CODE (SUBREG_REG (operand0
)) == REG
3683 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3685 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3686 the code which tracks sets/uses for delete_output_reload. */
3687 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3688 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3689 SUBREG_BYTE (operand0
));
3690 operand0
= alter_subreg (&temp
, true);
3694 && reload_in_progress
&& GET_CODE (operand1
) == REG
3695 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3696 operand1
= reg_equiv_mem (REGNO (operand1
));
3697 else if (scratch_reg
3698 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3699 && GET_CODE (SUBREG_REG (operand1
)) == REG
3700 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3702 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3703 the code which tracks sets/uses for delete_output_reload. */
3704 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3705 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3706 SUBREG_BYTE (operand1
));
3707 operand1
= alter_subreg (&temp
, true);
3710 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3711 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3712 != XEXP (operand0
, 0)))
3713 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3714 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3715 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3716 != XEXP (operand1
, 0)))
3717 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3719 /* Handle secondary reloads for loads/stores of FP registers where
3720 the address is symbolic by using the scratch register */
3721 if (fp_reg_operand (operand0
, mode
)
3722 && ((GET_CODE (operand1
) == MEM
3723 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3724 || ((GET_CODE (operand1
) == SUBREG
3725 && GET_CODE (XEXP (operand1
, 0)) == MEM
3726 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3729 if (GET_CODE (operand1
) == SUBREG
)
3730 operand1
= XEXP (operand1
, 0);
3732 /* SCRATCH_REG will hold an address. We want
3733 it in SImode regardless of what mode it was originally given
3735 scratch_reg
= force_mode (SImode
, scratch_reg
);
3737 /* D might not fit in 14 bits either; for such cases load D into
3739 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3741 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3742 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3744 XEXP (XEXP (operand1
, 0), 0),
3748 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3749 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3752 else if (fp_reg_operand (operand1
, mode
)
3753 && ((GET_CODE (operand0
) == MEM
3754 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3755 || ((GET_CODE (operand0
) == SUBREG
)
3756 && GET_CODE (XEXP (operand0
, 0)) == MEM
3757 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3760 if (GET_CODE (operand0
) == SUBREG
)
3761 operand0
= XEXP (operand0
, 0);
3763 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3764 it in SIMODE regardless of what mode it was originally given
3766 scratch_reg
= force_mode (SImode
, scratch_reg
);
3768 /* D might not fit in 14 bits either; for such cases load D into
3770 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3772 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3773 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3776 XEXP (XEXP (operand0
, 0),
3781 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3782 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3785 /* Handle secondary reloads for loads of FP registers from constant
3786 expressions by forcing the constant into memory.
3788 use scratch_reg to hold the address of the memory location.
3790 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3791 NO_REGS when presented with a const_int and an register class
3792 containing only FP registers. Doing so unfortunately creates
3793 more problems than it solves. Fix this for 2.5. */
3794 else if (fp_reg_operand (operand0
, mode
)
3795 && CONSTANT_P (operand1
)
3800 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3801 it in SIMODE regardless of what mode it was originally given
3803 scratch_reg
= force_mode (SImode
, scratch_reg
);
3805 /* Force the constant into memory and put the address of the
3806 memory location into scratch_reg. */
3807 xoperands
[0] = scratch_reg
;
3808 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3809 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3811 /* Now load the destination register. */
3812 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3816 /* Now have insn-emit do whatever it normally does. */
3820 /* Split one or more DImode RTL references into pairs of SImode
3821 references. The RTL can be REG, offsettable MEM, integer constant, or
3822 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3823 split and "num" is its length. lo_half and hi_half are output arrays
3824 that parallel "operands". */
3827 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3831 rtx op
= operands
[num
];
3833 /* simplify_subreg refuses to split volatile memory addresses,
3834 but we still have to handle it. */
3835 if (GET_CODE (op
) == MEM
)
3837 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3838 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3842 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3843 GET_MODE (op
) == VOIDmode
3844 ? DImode
: GET_MODE (op
), 4);
3845 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3846 GET_MODE (op
) == VOIDmode
3847 ? DImode
: GET_MODE (op
), 0);
3852 /* Split X into a base and a constant offset, storing them in *BASE
3853 and *OFFSET respectively. */
3856 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3859 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3861 *offset
+= INTVAL (XEXP (x
, 1));
3867 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3868 instruction. STORE_P says whether the move is a load or store.
3870 If the instruction uses post-increment or pre-decrement addressing,
3871 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3872 adjustment. This adjustment will be made by the first element of
3873 PARALLEL, with the loads or stores starting at element 1. If the
3874 instruction does not use post-increment or pre-decrement addressing,
3875 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3876 start at element 0. */
3879 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3880 HOST_WIDE_INT automod_offset
, bool store_p
)
3882 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3883 HOST_WIDE_INT offset
, mem_offset
;
3885 enum reg_class rclass
;
3887 len
= XVECLEN (pattern
, 0);
3888 first
= (automod_base
!= NULL
);
3892 /* Stores must be pre-decrement and loads must be post-increment. */
3893 if (store_p
!= (automod_offset
< 0))
3896 /* Work out the base and offset for lowest memory location. */
3897 base
= automod_base
;
3898 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3902 /* Allow any valid base and offset in the first access. */
3909 for (i
= first
; i
< len
; i
++)
3911 /* We need a plain SET. */
3912 set
= XVECEXP (pattern
, 0, i
);
3913 if (GET_CODE (set
) != SET
)
3916 /* Check that we have a memory location... */
3917 mem
= XEXP (set
, !store_p
);
3918 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3921 /* ...with the right address. */
3924 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3925 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3926 There are no mode restrictions for 680x0 besides the
3927 automodification rules enforced above. */
3929 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3934 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3935 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3939 /* Check that we have a register of the required mode and class. */
3940 reg
= XEXP (set
, store_p
);
3942 || !HARD_REGISTER_P (reg
)
3943 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3948 /* The register must belong to RCLASS and have a higher number
3949 than the register in the previous SET. */
3950 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3951 || REGNO (last_reg
) >= REGNO (reg
))
3956 /* Work out which register class we need. */
3957 if (INT_REGNO_P (REGNO (reg
)))
3958 rclass
= GENERAL_REGS
;
3959 else if (FP_REGNO_P (REGNO (reg
)))
3966 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3969 /* If we have an automodification, check whether the final offset is OK. */
3970 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3973 /* Reject unprofitable cases. */
3974 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3980 /* Return the assembly code template for a movem or fmovem instruction
3981 whose pattern is given by PATTERN. Store the template's operands
3984 If the instruction uses post-increment or pre-decrement addressing,
3985 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3986 is true if this is a store instruction. */
3989 m68k_output_movem (rtx
*operands
, rtx pattern
,
3990 HOST_WIDE_INT automod_offset
, bool store_p
)
3995 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3997 first
= (automod_offset
!= 0);
3998 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
4000 /* When using movem with pre-decrement addressing, register X + D0_REG
4001 is controlled by bit 15 - X. For all other addressing modes,
4002 register X + D0_REG is controlled by bit X. Confusingly, the
4003 register mask for fmovem is in the opposite order to that for
4007 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4008 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4009 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4010 if (automod_offset
< 0)
4012 if (FP_REGNO_P (regno
))
4013 mask
|= 1 << (regno
- FP0_REG
);
4015 mask
|= 1 << (15 - (regno
- D0_REG
));
4019 if (FP_REGNO_P (regno
))
4020 mask
|= 1 << (7 - (regno
- FP0_REG
));
4022 mask
|= 1 << (regno
- D0_REG
);
4027 if (automod_offset
== 0)
4028 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4029 else if (automod_offset
< 0)
4030 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4032 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4033 operands
[1] = GEN_INT (mask
);
4034 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4037 return "fmovem %1,%a0";
4039 return "fmovem %a0,%1";
4044 return "movem%.l %1,%a0";
4046 return "movem%.l %a0,%1";
4050 /* Return a REG that occurs in ADDR with coefficient 1.
4051 ADDR can be effectively incremented by incrementing REG. */
4054 find_addr_reg (rtx addr
)
4056 while (GET_CODE (addr
) == PLUS
)
4058 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4059 addr
= XEXP (addr
, 0);
4060 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4061 addr
= XEXP (addr
, 1);
4062 else if (CONSTANT_P (XEXP (addr
, 0)))
4063 addr
= XEXP (addr
, 1);
4064 else if (CONSTANT_P (XEXP (addr
, 1)))
4065 addr
= XEXP (addr
, 0);
4069 gcc_assert (GET_CODE (addr
) == REG
);
4073 /* Output assembler code to perform a 32-bit 3-operand add. */
4076 output_addsi3 (rtx
*operands
)
4078 if (! operands_match_p (operands
[0], operands
[1]))
4080 if (!ADDRESS_REG_P (operands
[1]))
4082 rtx tmp
= operands
[1];
4084 operands
[1] = operands
[2];
4088 /* These insns can result from reloads to access
4089 stack slots over 64k from the frame pointer. */
4090 if (GET_CODE (operands
[2]) == CONST_INT
4091 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4092 return "move%.l %2,%0\n\tadd%.l %1,%0";
4093 if (GET_CODE (operands
[2]) == REG
)
4094 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4095 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4097 if (GET_CODE (operands
[2]) == CONST_INT
)
4099 if (INTVAL (operands
[2]) > 0
4100 && INTVAL (operands
[2]) <= 8)
4101 return "addq%.l %2,%0";
4102 if (INTVAL (operands
[2]) < 0
4103 && INTVAL (operands
[2]) >= -8)
4105 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4106 return "subq%.l %2,%0";
4108 /* On the CPU32 it is faster to use two addql instructions to
4109 add a small integer (8 < N <= 16) to a register.
4110 Likewise for subql. */
4111 if (TUNE_CPU32
&& REG_P (operands
[0]))
4113 if (INTVAL (operands
[2]) > 8
4114 && INTVAL (operands
[2]) <= 16)
4116 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4117 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4119 if (INTVAL (operands
[2]) < -8
4120 && INTVAL (operands
[2]) >= -16)
4122 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4123 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4126 if (ADDRESS_REG_P (operands
[0])
4127 && INTVAL (operands
[2]) >= -0x8000
4128 && INTVAL (operands
[2]) < 0x8000)
4131 return "add%.w %2,%0";
4133 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4136 return "add%.l %2,%0";
4139 /* Store in cc_status the expressions that the condition codes will
4140 describe after execution of an instruction whose pattern is EXP.
4141 Do not alter them if the instruction would not alter the cc's. */
4143 /* On the 68000, all the insns to store in an address register fail to
4144 set the cc's. However, in some cases these instructions can make it
4145 possibly invalid to use the saved cc's. In those cases we clear out
4146 some or all of the saved cc's so they won't be used. */
4149 notice_update_cc (rtx exp
, rtx insn
)
4151 if (GET_CODE (exp
) == SET
)
4153 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4155 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4157 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4158 cc_status
.value1
= 0;
4159 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4160 cc_status
.value2
= 0;
4162 /* fmoves to memory or data registers do not set the condition
4163 codes. Normal moves _do_ set the condition codes, but not in
4164 a way that is appropriate for comparison with 0, because -0.0
4165 would be treated as a negative nonzero number. Note that it
4166 isn't appropriate to conditionalize this restriction on
4167 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4168 we care about the difference between -0.0 and +0.0. */
4169 else if (!FP_REG_P (SET_DEST (exp
))
4170 && SET_DEST (exp
) != cc0_rtx
4171 && (FP_REG_P (SET_SRC (exp
))
4172 || GET_CODE (SET_SRC (exp
)) == FIX
4173 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4175 /* A pair of move insns doesn't produce a useful overall cc. */
4176 else if (!FP_REG_P (SET_DEST (exp
))
4177 && !FP_REG_P (SET_SRC (exp
))
4178 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4179 && (GET_CODE (SET_SRC (exp
)) == REG
4180 || GET_CODE (SET_SRC (exp
)) == MEM
4181 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4183 else if (SET_DEST (exp
) != pc_rtx
)
4185 cc_status
.flags
= 0;
4186 cc_status
.value1
= SET_DEST (exp
);
4187 cc_status
.value2
= SET_SRC (exp
);
4190 else if (GET_CODE (exp
) == PARALLEL
4191 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4193 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4194 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4196 if (ADDRESS_REG_P (dest
))
4198 else if (dest
!= pc_rtx
)
4200 cc_status
.flags
= 0;
4201 cc_status
.value1
= dest
;
4202 cc_status
.value2
= src
;
4207 if (cc_status
.value2
!= 0
4208 && ADDRESS_REG_P (cc_status
.value2
)
4209 && GET_MODE (cc_status
.value2
) == QImode
)
4211 if (cc_status
.value2
!= 0)
4212 switch (GET_CODE (cc_status
.value2
))
4214 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4215 case ROTATE
: case ROTATERT
:
4216 /* These instructions always clear the overflow bit, and set
4217 the carry to the bit shifted out. */
4218 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4221 case PLUS
: case MINUS
: case MULT
:
4222 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4223 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4224 cc_status
.flags
|= CC_NO_OVERFLOW
;
4227 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4228 ends with a move insn moving r2 in r2's mode.
4229 Thus, the cc's are set for r2.
4230 This can set N bit spuriously. */
4231 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4236 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4238 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4239 cc_status
.value2
= 0;
4240 /* Check for PRE_DEC in dest modifying a register used in src. */
4241 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4242 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4244 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4246 cc_status
.value2
= 0;
4247 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4248 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4249 cc_status
.flags
= CC_IN_68881
;
4250 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4251 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4253 cc_status
.flags
= CC_IN_68881
;
4254 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4255 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4256 cc_status
.flags
|= CC_REVERSED
;
4261 output_move_const_double (rtx
*operands
)
4263 int code
= standard_68881_constant_p (operands
[1]);
4267 static char buf
[40];
4269 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4272 return "fmove%.d %1,%0";
4276 output_move_const_single (rtx
*operands
)
4278 int code
= standard_68881_constant_p (operands
[1]);
4282 static char buf
[40];
4284 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4287 return "fmove%.s %f1,%0";
4290 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4291 from the "fmovecr" instruction.
4292 The value, anded with 0xff, gives the code to use in fmovecr
4293 to get the desired constant. */
4295 /* This code has been fixed for cross-compilation. */
4297 static int inited_68881_table
= 0;
4299 static const char *const strings_68881
[7] = {
4309 static const int codes_68881
[7] = {
4319 REAL_VALUE_TYPE values_68881
[7];
4321 /* Set up values_68881 array by converting the decimal values
4322 strings_68881 to binary. */
4325 init_68881_table (void)
4332 for (i
= 0; i
< 7; i
++)
4336 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4337 values_68881
[i
] = r
;
4339 inited_68881_table
= 1;
4343 standard_68881_constant_p (rtx x
)
4345 const REAL_VALUE_TYPE
*r
;
4348 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4349 used at all on those chips. */
4353 if (! inited_68881_table
)
4354 init_68881_table ();
4356 r
= CONST_DOUBLE_REAL_VALUE (x
);
4358 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4359 for (i
= 0; i
< 6; i
++)
4361 if (real_identical (r
, &values_68881
[i
]))
4362 return (codes_68881
[i
]);
4365 if (GET_MODE (x
) == SFmode
)
4368 if (real_equal (r
, &values_68881
[6]))
4369 return (codes_68881
[6]);
4371 /* larger powers of ten in the constants ram are not used
4372 because they are not equal to a `double' C constant. */
4376 /* If X is a floating-point constant, return the logarithm of X base 2,
4377 or 0 if X is not a power of 2. */
4380 floating_exact_log2 (rtx x
)
4382 const REAL_VALUE_TYPE
*r
;
4386 r
= CONST_DOUBLE_REAL_VALUE (x
);
4388 if (real_less (r
, &dconst1
))
4391 exp
= real_exponent (r
);
4392 real_2expN (&r1
, exp
, DFmode
);
4393 if (real_equal (&r1
, r
))
4399 /* A C compound statement to output to stdio stream STREAM the
4400 assembler syntax for an instruction operand X. X is an RTL
4403 CODE is a value that can be used to specify one of several ways
4404 of printing the operand. It is used when identical operands
4405 must be printed differently depending on the context. CODE
4406 comes from the `%' specification that was used to request
4407 printing of the operand. If the specification was just `%DIGIT'
4408 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4409 is the ASCII code for LTR.
4411 If X is a register, this macro should print the register's name.
4412 The names can be found in an array `reg_names' whose type is
4413 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4415 When the machine description has a specification `%PUNCT' (a `%'
4416 followed by a punctuation character), this macro is called with
4417 a null pointer for X and the punctuation character for CODE.
4419 The m68k specific codes are:
4421 '.' for dot needed in Motorola-style opcode names.
4422 '-' for an operand pushing on the stack:
4423 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4424 '+' for an operand pushing on the stack:
4425 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4426 '@' for a reference to the top word on the stack:
4427 sp@, (sp) or (%sp) depending on the style of syntax.
4428 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4429 but & in SGS syntax).
4430 '!' for the cc register (used in an `and to cc' insn).
4431 '$' for the letter `s' in an op code, but only on the 68040.
4432 '&' for the letter `d' in an op code, but only on the 68040.
4433 '/' for register prefix needed by longlong.h.
4434 '?' for m68k_library_id_string
4436 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4437 'd' to force memory addressing to be absolute, not relative.
4438 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4439 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4440 or print pair of registers as rx:ry.
4441 'p' print an address with @PLTPC attached, but only if the operand
4442 is not locally-bound. */
4445 print_operand (FILE *file
, rtx op
, int letter
)
4450 fprintf (file
, ".");
4452 else if (letter
== '#')
4453 asm_fprintf (file
, "%I");
4454 else if (letter
== '-')
4455 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4456 else if (letter
== '+')
4457 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4458 else if (letter
== '@')
4459 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4460 else if (letter
== '!')
4461 asm_fprintf (file
, "%Rfpcr");
4462 else if (letter
== '$')
4465 fprintf (file
, "s");
4467 else if (letter
== '&')
4470 fprintf (file
, "d");
4472 else if (letter
== '/')
4473 asm_fprintf (file
, "%R");
4474 else if (letter
== '?')
4475 asm_fprintf (file
, m68k_library_id_string
);
4476 else if (letter
== 'p')
4478 output_addr_const (file
, op
);
4479 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4480 fprintf (file
, "@PLTPC");
4482 else if (GET_CODE (op
) == REG
)
4485 /* Print out the second register name of a register pair.
4486 I.e., R (6) => 7. */
4487 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4489 fputs (M68K_REGNAME(REGNO (op
)), file
);
4491 else if (GET_CODE (op
) == MEM
)
4493 output_address (GET_MODE (op
), XEXP (op
, 0));
4494 if (letter
== 'd' && ! TARGET_68020
4495 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4496 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4497 && INTVAL (XEXP (op
, 0)) < 0x8000
4498 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4499 fprintf (file
, MOTOROLA
? ".l" : ":l");
4501 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4504 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4505 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4507 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4510 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4511 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4512 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4514 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4517 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4518 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4522 /* Use `print_operand_address' instead of `output_addr_const'
4523 to ensure that we print relevant PIC stuff. */
4524 asm_fprintf (file
, "%I");
4526 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4527 print_operand_address (file
, op
);
4529 output_addr_const (file
, op
);
4533 /* Return string for TLS relocation RELOC. */
4536 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4538 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4539 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4546 if (flag_pic
== 1 && TARGET_68020
)
4588 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4591 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4593 if (GET_CODE (x
) == UNSPEC
)
4595 switch (XINT (x
, 1))
4597 case UNSPEC_RELOC16
:
4598 case UNSPEC_RELOC32
:
4599 output_addr_const (file
, XVECEXP (x
, 0, 0));
4600 fputs (m68k_get_reloc_decoration
4601 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4612 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4615 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4617 gcc_assert (size
== 4);
4618 fputs ("\t.long\t", file
);
4619 output_addr_const (file
, x
);
4620 fputs ("@TLSLDO+0x8000", file
);
4623 /* In the name of slightly smaller debug output, and to cater to
4624 general assembler lossage, recognize various UNSPEC sequences
4625 and turn them back into a direct symbol reference. */
4628 m68k_delegitimize_address (rtx orig_x
)
4631 struct m68k_address addr
;
4634 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4639 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4642 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4643 || addr
.offset
== NULL_RTX
4644 || GET_CODE (addr
.offset
) != CONST
)
4647 unspec
= XEXP (addr
.offset
, 0);
4648 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4649 unspec
= XEXP (unspec
, 0);
4650 if (GET_CODE (unspec
) != UNSPEC
4651 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4652 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4654 x
= XVECEXP (unspec
, 0, 0);
4655 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4656 if (unspec
!= XEXP (addr
.offset
, 0))
4657 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4660 rtx idx
= addr
.index
;
4661 if (addr
.scale
!= 1)
4662 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4663 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4666 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4668 x
= replace_equiv_address_nv (orig_x
, x
);
4673 /* A C compound statement to output to stdio stream STREAM the
4674 assembler syntax for an instruction operand that is a memory
4675 reference whose address is ADDR. ADDR is an RTL expression.
4677 Note that this contains a kludge that knows that the only reason
4678 we have an address (plus (label_ref...) (reg...)) when not generating
4679 PIC code is in the insn before a tablejump, and we know that m68k.md
4680 generates a label LInnn: on such an insn.
4682 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4683 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4685 This routine is responsible for distinguishing between -fpic and -fPIC
4686 style relocations in an address. When generating -fpic code the
4687 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4688 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4691 print_operand_address (FILE *file
, rtx addr
)
4693 struct m68k_address address
;
4695 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4698 if (address
.code
== PRE_DEC
)
4699 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4700 M68K_REGNAME (REGNO (address
.base
)));
4701 else if (address
.code
== POST_INC
)
4702 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4703 M68K_REGNAME (REGNO (address
.base
)));
4704 else if (!address
.base
&& !address
.index
)
4706 /* A constant address. */
4707 gcc_assert (address
.offset
== addr
);
4708 if (GET_CODE (addr
) == CONST_INT
)
4710 /* (xxx).w or (xxx).l. */
4711 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4712 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4714 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4716 else if (TARGET_PCREL
)
4718 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4720 output_addr_const (file
, addr
);
4721 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4725 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4726 name ends in `.<letter>', as the last 2 characters can be
4727 mistaken as a size suffix. Put the name in parentheses. */
4728 if (GET_CODE (addr
) == SYMBOL_REF
4729 && strlen (XSTR (addr
, 0)) > 2
4730 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4733 output_addr_const (file
, addr
);
4737 output_addr_const (file
, addr
);
4744 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4745 label being accessed, otherwise it is -1. */
4746 labelno
= (address
.offset
4748 && GET_CODE (address
.offset
) == LABEL_REF
4749 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4753 /* Print the "offset(base" component. */
4755 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4759 output_addr_const (file
, address
.offset
);
4763 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4765 /* Print the ",index" component, if any. */
4770 fprintf (file
, "%s.%c",
4771 M68K_REGNAME (REGNO (address
.index
)),
4772 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4773 if (address
.scale
!= 1)
4774 fprintf (file
, "*%d", address
.scale
);
4778 else /* !MOTOROLA */
4780 if (!address
.offset
&& !address
.index
)
4781 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4784 /* Print the "base@(offset" component. */
4786 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4790 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4791 fprintf (file
, "@(");
4793 output_addr_const (file
, address
.offset
);
4795 /* Print the ",index" component, if any. */
4798 fprintf (file
, ",%s:%c",
4799 M68K_REGNAME (REGNO (address
.index
)),
4800 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4801 if (address
.scale
!= 1)
4802 fprintf (file
, ":%d", address
.scale
);
4810 /* Check for cases where a clr insns can be omitted from code using
4811 strict_low_part sets. For example, the second clrl here is not needed:
4812 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4814 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4815 insn we are checking for redundancy. TARGET is the register set by the
4819 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4822 rtx_insn
*p
= first_insn
;
4824 while ((p
= PREV_INSN (p
)))
4826 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4832 /* If it isn't an insn, then give up. */
4836 if (reg_set_p (target
, p
))
4838 rtx set
= single_set (p
);
4841 /* If it isn't an easy to recognize insn, then give up. */
4845 dest
= SET_DEST (set
);
4847 /* If this sets the entire target register to zero, then our
4848 first_insn is redundant. */
4849 if (rtx_equal_p (dest
, target
)
4850 && SET_SRC (set
) == const0_rtx
)
4852 else if (GET_CODE (dest
) == STRICT_LOW_PART
4853 && GET_CODE (XEXP (dest
, 0)) == REG
4854 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4855 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4856 <= GET_MODE_SIZE (mode
)))
4857 /* This is a strict low part set which modifies less than
4858 we are using, so it is safe. */
4868 /* Operand predicates for implementing asymmetric pc-relative addressing
4869 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4870 when used as a source operand, but not as a destination operand.
4872 We model this by restricting the meaning of the basic predicates
4873 (general_operand, memory_operand, etc) to forbid the use of this
4874 addressing mode, and then define the following predicates that permit
4875 this addressing mode. These predicates can then be used for the
4876 source operands of the appropriate instructions.
4878 n.b. While it is theoretically possible to change all machine patterns
4879 to use this addressing more where permitted by the architecture,
4880 it has only been implemented for "common" cases: SImode, HImode, and
4881 QImode operands, and only for the principle operations that would
4882 require this addressing mode: data movement and simple integer operations.
4884 In parallel with these new predicates, two new constraint letters
4885 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4886 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4887 In the pcrel case 's' is only valid in combination with 'a' registers.
4888 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4889 of how these constraints are used.
4891 The use of these predicates is strictly optional, though patterns that
4892 don't will cause an extra reload register to be allocated where one
4895 lea (abc:w,%pc),%a0 ; need to reload address
4896 moveq &1,%d1 ; since write to pc-relative space
4897 movel %d1,%a0@ ; is not allowed
4899 lea (abc:w,%pc),%a1 ; no need to reload address here
4900 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4902 For more info, consult tiemann@cygnus.com.
4905 All of the ugliness with predicates and constraints is due to the
4906 simple fact that the m68k does not allow a pc-relative addressing
4907 mode as a destination. gcc does not distinguish between source and
4908 destination addresses. Hence, if we claim that pc-relative address
4909 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4910 end up with invalid code. To get around this problem, we left
4911 pc-relative modes as invalid addresses, and then added special
4912 predicates and constraints to accept them.
4914 A cleaner way to handle this is to modify gcc to distinguish
4915 between source and destination addresses. We can then say that
4916 pc-relative is a valid source address but not a valid destination
4917 address, and hopefully avoid a lot of the predicate and constraint
4918 hackery. Unfortunately, this would be a pretty big change. It would
4919 be a useful change for a number of ports, but there aren't any current
4920 plans to undertake this.
4922 ***************************************************************************/
4926 output_andsi3 (rtx
*operands
)
4929 if (GET_CODE (operands
[2]) == CONST_INT
4930 && (INTVAL (operands
[2]) | 0xffff) == -1
4931 && (DATA_REG_P (operands
[0])
4932 || offsettable_memref_p (operands
[0]))
4933 && !TARGET_COLDFIRE
)
4935 if (GET_CODE (operands
[0]) != REG
)
4936 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4937 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4938 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4940 if (operands
[2] == const0_rtx
)
4942 return "and%.w %2,%0";
4944 if (GET_CODE (operands
[2]) == CONST_INT
4945 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4946 && (DATA_REG_P (operands
[0])
4947 || offsettable_memref_p (operands
[0])))
4949 if (DATA_REG_P (operands
[0]))
4950 operands
[1] = GEN_INT (logval
);
4953 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4954 operands
[1] = GEN_INT (logval
% 8);
4956 /* This does not set condition codes in a standard way. */
4958 return "bclr %1,%0";
4960 return "and%.l %2,%0";
4964 output_iorsi3 (rtx
*operands
)
4966 register int logval
;
4967 if (GET_CODE (operands
[2]) == CONST_INT
4968 && INTVAL (operands
[2]) >> 16 == 0
4969 && (DATA_REG_P (operands
[0])
4970 || offsettable_memref_p (operands
[0]))
4971 && !TARGET_COLDFIRE
)
4973 if (GET_CODE (operands
[0]) != REG
)
4974 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4975 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4977 if (INTVAL (operands
[2]) == 0xffff)
4978 return "mov%.w %2,%0";
4979 return "or%.w %2,%0";
4981 if (GET_CODE (operands
[2]) == CONST_INT
4982 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4983 && (DATA_REG_P (operands
[0])
4984 || offsettable_memref_p (operands
[0])))
4986 if (DATA_REG_P (operands
[0]))
4987 operands
[1] = GEN_INT (logval
);
4990 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4991 operands
[1] = GEN_INT (logval
% 8);
4994 return "bset %1,%0";
4996 return "or%.l %2,%0";
5000 output_xorsi3 (rtx
*operands
)
5002 register int logval
;
5003 if (GET_CODE (operands
[2]) == CONST_INT
5004 && INTVAL (operands
[2]) >> 16 == 0
5005 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5006 && !TARGET_COLDFIRE
)
5008 if (! DATA_REG_P (operands
[0]))
5009 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5010 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5012 if (INTVAL (operands
[2]) == 0xffff)
5014 return "eor%.w %2,%0";
5016 if (GET_CODE (operands
[2]) == CONST_INT
5017 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5018 && (DATA_REG_P (operands
[0])
5019 || offsettable_memref_p (operands
[0])))
5021 if (DATA_REG_P (operands
[0]))
5022 operands
[1] = GEN_INT (logval
);
5025 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5026 operands
[1] = GEN_INT (logval
% 8);
5029 return "bchg %1,%0";
5031 return "eor%.l %2,%0";
5034 /* Return the instruction that should be used for a call to address X,
5035 which is known to be in operand 0. */
5040 if (symbolic_operand (x
, VOIDmode
))
5041 return m68k_symbolic_call
;
5046 /* Likewise sibling calls. */
5049 output_sibcall (rtx x
)
5051 if (symbolic_operand (x
, VOIDmode
))
5052 return m68k_symbolic_jump
;
5058 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5059 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5062 rtx this_slot
, offset
, addr
, mem
, tmp
;
5065 /* Avoid clobbering the struct value reg by using the
5066 static chain reg as a temporary. */
5067 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5069 /* Pretend to be a post-reload pass while generating rtl. */
5070 reload_completed
= 1;
5072 /* The "this" pointer is stored at 4(%sp). */
5073 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5074 stack_pointer_rtx
, 4));
5076 /* Add DELTA to THIS. */
5079 /* Make the offset a legitimate operand for memory addition. */
5080 offset
= GEN_INT (delta
);
5081 if ((delta
< -8 || delta
> 8)
5082 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5084 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5085 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5087 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5088 copy_rtx (this_slot
), offset
));
5091 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5092 if (vcall_offset
!= 0)
5094 /* Set the static chain register to *THIS. */
5095 emit_move_insn (tmp
, this_slot
);
5096 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5098 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5099 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5100 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5102 emit_insn (gen_rtx_SET (tmp
, addr
));
5106 /* Load the offset into %d0 and add it to THIS. */
5107 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5108 gen_rtx_MEM (Pmode
, addr
));
5109 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5110 copy_rtx (this_slot
),
5111 gen_rtx_REG (Pmode
, D0_REG
)));
5114 /* Jump to the target function. Use a sibcall if direct jumps are
5115 allowed, otherwise load the address into a register first. */
5116 mem
= DECL_RTL (function
);
5117 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5119 gcc_assert (flag_pic
);
5121 if (!TARGET_SEP_DATA
)
5123 /* Use the static chain register as a temporary (call-clobbered)
5124 GOT pointer for this function. We can use the static chain
5125 register because it isn't live on entry to the thunk. */
5126 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5127 emit_insn (gen_load_got (pic_offset_table_rtx
));
5129 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5130 mem
= replace_equiv_address (mem
, tmp
);
5132 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5133 SIBLING_CALL_P (insn
) = 1;
5135 /* Run just enough of rest_of_compilation. */
5136 insn
= get_insns ();
5137 split_all_insns_noflow ();
5138 final_start_function (insn
, file
, 1);
5139 final (insn
, file
, 1);
5140 final_end_function ();
5142 /* Clean up the vars set above. */
5143 reload_completed
= 0;
5145 /* Restore the original PIC register. */
5147 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5150 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5153 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5154 int incoming ATTRIBUTE_UNUSED
)
5156 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5159 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5161 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5162 unsigned int new_reg
)
5165 /* Interrupt functions can only use registers that have already been
5166 saved by the prologue, even if they would normally be
5169 if ((m68k_get_function_kind (current_function_decl
)
5170 == m68k_fk_interrupt_handler
)
5171 && !df_regs_ever_live_p (new_reg
))
5177 /* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
5178 registers can hold any mode, but restrict the 68881 registers to
5179 floating-point modes. */
5182 m68k_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
5184 if (DATA_REGNO_P (regno
))
5186 /* Data Registers, can hold aggregate if fits in. */
5187 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5190 else if (ADDRESS_REGNO_P (regno
))
5192 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5195 else if (FP_REGNO_P (regno
))
5197 /* FPU registers, hold float or complex float of long double or
5199 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5200 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5201 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5207 /* Implement SECONDARY_RELOAD_CLASS. */
5210 m68k_secondary_reload_class (enum reg_class rclass
,
5211 machine_mode mode
, rtx x
)
5215 regno
= true_regnum (x
);
5217 /* If one operand of a movqi is an address register, the other
5218 operand must be a general register or constant. Other types
5219 of operand must be reloaded through a data register. */
5220 if (GET_MODE_SIZE (mode
) == 1
5221 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5222 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5225 /* PC-relative addresses must be loaded into an address register first. */
5227 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5228 && symbolic_operand (x
, VOIDmode
))
5234 /* Implement PREFERRED_RELOAD_CLASS. */
5237 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5239 enum reg_class secondary_class
;
5241 /* If RCLASS might need a secondary reload, try restricting it to
5242 a class that doesn't. */
5243 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5244 if (secondary_class
!= NO_REGS
5245 && reg_class_subset_p (secondary_class
, rclass
))
5246 return secondary_class
;
5248 /* Prefer to use moveq for in-range constants. */
5249 if (GET_CODE (x
) == CONST_INT
5250 && reg_class_subset_p (DATA_REGS
, rclass
)
5251 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5254 /* ??? Do we really need this now? */
5255 if (GET_CODE (x
) == CONST_DOUBLE
5256 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5258 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5267 /* Return floating point values in a 68881 register. This makes 68881 code
5268 a little bit faster. It also makes -msoft-float code incompatible with
5269 hard-float code, so people have to be careful not to mix the two.
5270 For ColdFire it was decided the ABI incompatibility is undesirable.
5271 If there is need for a hard-float ABI it is probably worth doing it
5272 properly and also passing function arguments in FP registers. */
5274 m68k_libcall_value (machine_mode mode
)
5281 return gen_rtx_REG (mode
, FP0_REG
);
5287 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5290 /* Location in which function value is returned.
5291 NOTE: Due to differences in ABIs, don't call this function directly,
5292 use FUNCTION_VALUE instead. */
5294 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5298 mode
= TYPE_MODE (valtype
);
5304 return gen_rtx_REG (mode
, FP0_REG
);
5310 /* If the function returns a pointer, push that into %a0. */
5311 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5312 /* For compatibility with the large body of existing code which
5313 does not always properly declare external functions returning
5314 pointer types, the m68k/SVR4 convention is to copy the value
5315 returned for pointer functions from a0 to d0 in the function
5316 epilogue, so that callers that have neglected to properly
5317 declare the callee can still find the correct return value in
5319 return gen_rtx_PARALLEL
5322 gen_rtx_EXPR_LIST (VOIDmode
,
5323 gen_rtx_REG (mode
, A0_REG
),
5325 gen_rtx_EXPR_LIST (VOIDmode
,
5326 gen_rtx_REG (mode
, D0_REG
),
5328 else if (POINTER_TYPE_P (valtype
))
5329 return gen_rtx_REG (mode
, A0_REG
);
5331 return gen_rtx_REG (mode
, D0_REG
);
5334 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5335 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5337 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5339 machine_mode mode
= TYPE_MODE (type
);
5341 if (mode
== BLKmode
)
5344 /* If TYPE's known alignment is less than the alignment of MODE that
5345 would contain the structure, then return in memory. We need to
5346 do so to maintain the compatibility between code compiled with
5347 -mstrict-align and that compiled with -mno-strict-align. */
5348 if (AGGREGATE_TYPE_P (type
)
5349 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5356 /* CPU to schedule the program for. */
5357 enum attr_cpu m68k_sched_cpu
;
5359 /* MAC to schedule the program for. */
5360 enum attr_mac m68k_sched_mac
;
5368 /* Integer register. */
5374 /* Implicit mem reference (e.g. stack). */
5377 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5380 /* Memory with offset but without indexing. EA mode 5. */
5383 /* Memory with indexing. EA mode 6. */
5386 /* Memory referenced by absolute address. EA mode 7. */
5389 /* Immediate operand that doesn't require extension word. */
5392 /* Immediate 16 bit operand. */
5395 /* Immediate 32 bit operand. */
5399 /* Return type of memory ADDR_RTX refers to. */
5400 static enum attr_op_type
5401 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5403 struct m68k_address address
;
5405 if (symbolic_operand (addr_rtx
, VOIDmode
))
5406 return OP_TYPE_MEM7
;
5408 if (!m68k_decompose_address (mode
, addr_rtx
,
5409 reload_completed
, &address
))
5411 gcc_assert (!reload_completed
);
5412 /* Reload will likely fix the address to be in the register. */
5413 return OP_TYPE_MEM234
;
5416 if (address
.scale
!= 0)
5417 return OP_TYPE_MEM6
;
5419 if (address
.base
!= NULL_RTX
)
5421 if (address
.offset
== NULL_RTX
)
5422 return OP_TYPE_MEM234
;
5424 return OP_TYPE_MEM5
;
5427 gcc_assert (address
.offset
!= NULL_RTX
);
5429 return OP_TYPE_MEM7
;
5432 /* Return X or Y (depending on OPX_P) operand of INSN. */
5434 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5438 if (recog_memoized (insn
) < 0)
5441 extract_constrain_insn_cached (insn
);
5444 i
= get_attr_opx (insn
);
5446 i
= get_attr_opy (insn
);
5448 if (i
>= recog_data
.n_operands
)
5451 return recog_data
.operand
[i
];
5454 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5455 If ADDRESS_P is true, return type of memory location operand refers to. */
5456 static enum attr_op_type
5457 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5461 op
= sched_get_operand (insn
, opx_p
);
5465 gcc_assert (!reload_completed
);
5470 return sched_address_type (QImode
, op
);
5472 if (memory_operand (op
, VOIDmode
))
5473 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5475 if (register_operand (op
, VOIDmode
))
5477 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5478 || (reload_completed
&& FP_REG_P (op
)))
5484 if (GET_CODE (op
) == CONST_INT
)
5490 /* Check for quick constants. */
5491 switch (get_attr_type (insn
))
5494 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5495 return OP_TYPE_IMM_Q
;
5497 gcc_assert (!reload_completed
);
5501 if (USE_MOVQ (ival
))
5502 return OP_TYPE_IMM_Q
;
5504 gcc_assert (!reload_completed
);
5508 if (valid_mov3q_const (ival
))
5509 return OP_TYPE_IMM_Q
;
5511 gcc_assert (!reload_completed
);
5518 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5519 return OP_TYPE_IMM_W
;
5521 return OP_TYPE_IMM_L
;
5524 if (GET_CODE (op
) == CONST_DOUBLE
)
5526 switch (GET_MODE (op
))
5529 return OP_TYPE_IMM_W
;
5533 return OP_TYPE_IMM_L
;
5540 if (GET_CODE (op
) == CONST
5541 || symbolic_operand (op
, VOIDmode
)
5544 switch (GET_MODE (op
))
5547 return OP_TYPE_IMM_Q
;
5550 return OP_TYPE_IMM_W
;
5553 return OP_TYPE_IMM_L
;
5556 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5558 return OP_TYPE_IMM_W
;
5560 return OP_TYPE_IMM_L
;
5564 gcc_assert (!reload_completed
);
5566 if (FLOAT_MODE_P (GET_MODE (op
)))
5572 /* Implement opx_type attribute.
5573 Return type of INSN's operand X.
5574 If ADDRESS_P is true, return type of memory location operand refers to. */
5576 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5578 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5584 return OPX_TYPE_FPN
;
5587 return OPX_TYPE_MEM1
;
5589 case OP_TYPE_MEM234
:
5590 return OPX_TYPE_MEM234
;
5593 return OPX_TYPE_MEM5
;
5596 return OPX_TYPE_MEM6
;
5599 return OPX_TYPE_MEM7
;
5602 return OPX_TYPE_IMM_Q
;
5605 return OPX_TYPE_IMM_W
;
5608 return OPX_TYPE_IMM_L
;
5615 /* Implement opy_type attribute.
5616 Return type of INSN's operand Y.
5617 If ADDRESS_P is true, return type of memory location operand refers to. */
5619 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5621 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5627 return OPY_TYPE_FPN
;
5630 return OPY_TYPE_MEM1
;
5632 case OP_TYPE_MEM234
:
5633 return OPY_TYPE_MEM234
;
5636 return OPY_TYPE_MEM5
;
5639 return OPY_TYPE_MEM6
;
5642 return OPY_TYPE_MEM7
;
5645 return OPY_TYPE_IMM_Q
;
5648 return OPY_TYPE_IMM_W
;
5651 return OPY_TYPE_IMM_L
;
5658 /* Return size of INSN as int. */
5660 sched_get_attr_size_int (rtx_insn
*insn
)
5664 switch (get_attr_type (insn
))
5667 /* There should be no references to m68k_sched_attr_size for 'ignore'
5681 switch (get_attr_opx_type (insn
))
5687 case OPX_TYPE_MEM234
:
5688 case OPY_TYPE_IMM_Q
:
5693 /* Here we assume that most absolute references are short. */
5695 case OPY_TYPE_IMM_W
:
5699 case OPY_TYPE_IMM_L
:
5707 switch (get_attr_opy_type (insn
))
5713 case OPY_TYPE_MEM234
:
5714 case OPY_TYPE_IMM_Q
:
5719 /* Here we assume that most absolute references are short. */
5721 case OPY_TYPE_IMM_W
:
5725 case OPY_TYPE_IMM_L
:
5735 gcc_assert (!reload_completed
);
5743 /* Return size of INSN as attribute enum value. */
5745 m68k_sched_attr_size (rtx_insn
*insn
)
5747 switch (sched_get_attr_size_int (insn
))
5763 /* Return operand X or Y (depending on OPX_P) of INSN,
5764 if it is a MEM, or NULL overwise. */
5765 static enum attr_op_type
5766 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5770 switch (get_attr_opx_type (insn
))
5775 case OPX_TYPE_IMM_Q
:
5776 case OPX_TYPE_IMM_W
:
5777 case OPX_TYPE_IMM_L
:
5781 case OPX_TYPE_MEM234
:
5784 return OP_TYPE_MEM1
;
5787 return OP_TYPE_MEM6
;
5795 switch (get_attr_opy_type (insn
))
5800 case OPY_TYPE_IMM_Q
:
5801 case OPY_TYPE_IMM_W
:
5802 case OPY_TYPE_IMM_L
:
5806 case OPY_TYPE_MEM234
:
5809 return OP_TYPE_MEM1
;
5812 return OP_TYPE_MEM6
;
5820 /* Implement op_mem attribute. */
5822 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5824 enum attr_op_type opx
;
5825 enum attr_op_type opy
;
5827 opx
= sched_get_opxy_mem_type (insn
, true);
5828 opy
= sched_get_opxy_mem_type (insn
, false);
5830 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5833 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5835 switch (get_attr_opx_access (insn
))
5851 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5853 switch (get_attr_opx_access (insn
))
5869 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5872 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5874 switch (get_attr_opx_access (insn
))
5880 gcc_assert (!reload_completed
);
5885 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5887 switch (get_attr_opx_access (insn
))
5893 gcc_assert (!reload_completed
);
5898 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5901 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5903 switch (get_attr_opx_access (insn
))
5909 gcc_assert (!reload_completed
);
5914 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5915 gcc_assert (!reload_completed
);
5919 /* Data for ColdFire V4 index bypass.
5920 Producer modifies register that is used as index in consumer with
5924 /* Producer instruction. */
5927 /* Consumer instruction. */
5930 /* Scale of indexed memory access within consumer.
5931 Or zero if bypass should not be effective at the moment. */
5933 } sched_cfv4_bypass_data
;
5935 /* An empty state that is used in m68k_sched_adjust_cost. */
5936 static state_t sched_adjust_cost_state
;
5938 /* Implement adjust_cost scheduler hook.
5939 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5941 m68k_sched_adjust_cost (rtx_insn
*insn
, int, rtx_insn
*def_insn
, int cost
,
5946 if (recog_memoized (def_insn
) < 0
5947 || recog_memoized (insn
) < 0)
5950 if (sched_cfv4_bypass_data
.scale
== 1)
5951 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5953 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5954 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5955 that the data in sched_cfv4_bypass_data is up to date. */
5956 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5957 && sched_cfv4_bypass_data
.con
== insn
);
5962 sched_cfv4_bypass_data
.pro
= NULL
;
5963 sched_cfv4_bypass_data
.con
= NULL
;
5964 sched_cfv4_bypass_data
.scale
= 0;
5967 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5968 && sched_cfv4_bypass_data
.con
== NULL
5969 && sched_cfv4_bypass_data
.scale
== 0);
5971 /* Don't try to issue INSN earlier than DFA permits.
5972 This is especially useful for instructions that write to memory,
5973 as their true dependence (default) latency is better to be set to 0
5974 to workaround alias analysis limitations.
5975 This is, in fact, a machine independent tweak, so, probably,
5976 it should be moved to haifa-sched.c: insn_cost (). */
5977 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5984 /* Return maximal number of insns that can be scheduled on a single cycle. */
5986 m68k_sched_issue_rate (void)
5988 switch (m68k_sched_cpu
)
6004 /* Maximal length of instruction for current CPU.
6005 E.g. it is 3 for any ColdFire core. */
6006 static int max_insn_size
;
6008 /* Data to model instruction buffer of CPU. */
6011 /* True if instruction buffer model is modeled for current CPU. */
6014 /* Size of the instruction buffer in words. */
6017 /* Number of filled words in the instruction buffer. */
6020 /* Additional information about instruction buffer for CPUs that have
6021 a buffer of instruction records, rather then a plain buffer
6022 of instruction words. */
6023 struct _sched_ib_records
6025 /* Size of buffer in records. */
6028 /* Array to hold data on adjustments made to the size of the buffer. */
6031 /* Index of the above array. */
6035 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6039 static struct _sched_ib sched_ib
;
6041 /* ID of memory unit. */
6042 static int sched_mem_unit_code
;
6044 /* Implementation of the targetm.sched.variable_issue () hook.
6045 It is called after INSN was issued. It returns the number of insns
6046 that can possibly get scheduled on the current cycle.
6047 It is used here to determine the effect of INSN on the instruction
6050 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6051 int sched_verbose ATTRIBUTE_UNUSED
,
6052 rtx_insn
*insn
, int can_issue_more
)
6056 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6058 switch (m68k_sched_cpu
)
6062 insn_size
= sched_get_attr_size_int (insn
);
6066 insn_size
= sched_get_attr_size_int (insn
);
6068 /* ColdFire V3 and V4 cores have instruction buffers that can
6069 accumulate up to 8 instructions regardless of instructions'
6070 sizes. So we should take care not to "prefetch" 24 one-word
6071 or 12 two-words instructions.
6072 To model this behavior we temporarily decrease size of the
6073 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6077 adjust
= max_insn_size
- insn_size
;
6078 sched_ib
.size
-= adjust
;
6080 if (sched_ib
.filled
> sched_ib
.size
)
6081 sched_ib
.filled
= sched_ib
.size
;
6083 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6086 ++sched_ib
.records
.adjust_index
;
6087 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6088 sched_ib
.records
.adjust_index
= 0;
6090 /* Undo adjustment we did 7 instructions ago. */
6092 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6097 gcc_assert (!sched_ib
.enabled_p
);
6105 if (insn_size
> sched_ib
.filled
)
6106 /* Scheduling for register pressure does not always take DFA into
6107 account. Workaround instruction buffer not being filled enough. */
6109 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6110 insn_size
= sched_ib
.filled
;
6115 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6116 || asm_noperands (PATTERN (insn
)) >= 0)
6117 insn_size
= sched_ib
.filled
;
6121 sched_ib
.filled
-= insn_size
;
6123 return can_issue_more
;
6126 /* Return how many instructions should scheduler lookahead to choose the
6129 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6131 return m68k_sched_issue_rate () - 1;
6134 /* Implementation of targetm.sched.init_global () hook.
6135 It is invoked once per scheduling pass and is used here
6136 to initialize scheduler constants. */
6138 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6139 int sched_verbose ATTRIBUTE_UNUSED
,
6140 int n_insns ATTRIBUTE_UNUSED
)
6142 /* Check that all instructions have DFA reservations and
6143 that all instructions can be issued from a clean state. */
6149 state
= alloca (state_size ());
6151 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6153 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6155 gcc_assert (insn_has_dfa_reservation_p (insn
));
6157 state_reset (state
);
6158 if (state_transition (state
, insn
) >= 0)
6164 /* Setup target cpu. */
6166 /* ColdFire V4 has a set of features to keep its instruction buffer full
6167 (e.g., a separate memory bus for instructions) and, hence, we do not model
6168 buffer for this CPU. */
6169 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6171 switch (m68k_sched_cpu
)
6174 sched_ib
.filled
= 0;
6181 sched_ib
.records
.n_insns
= 0;
6182 sched_ib
.records
.adjust
= NULL
;
6187 sched_ib
.records
.n_insns
= 8;
6188 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6195 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6197 sched_adjust_cost_state
= xmalloc (state_size ());
6198 state_reset (sched_adjust_cost_state
);
6201 emit_insn (gen_ib ());
6202 sched_ib
.insn
= get_insns ();
6206 /* Scheduling pass is now finished. Free/reset static variables. */
6208 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6209 int verbose ATTRIBUTE_UNUSED
)
6211 sched_ib
.insn
= NULL
;
6213 free (sched_adjust_cost_state
);
6214 sched_adjust_cost_state
= NULL
;
6216 sched_mem_unit_code
= 0;
6218 free (sched_ib
.records
.adjust
);
6219 sched_ib
.records
.adjust
= NULL
;
6220 sched_ib
.records
.n_insns
= 0;
6224 /* Implementation of targetm.sched.init () hook.
6225 It is invoked each time scheduler starts on the new block (basic block or
6226 extended basic block). */
6228 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6229 int sched_verbose ATTRIBUTE_UNUSED
,
6230 int n_insns ATTRIBUTE_UNUSED
)
6232 switch (m68k_sched_cpu
)
6240 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6242 memset (sched_ib
.records
.adjust
, 0,
6243 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6244 sched_ib
.records
.adjust_index
= 0;
6248 gcc_assert (!sched_ib
.enabled_p
);
6256 if (sched_ib
.enabled_p
)
6257 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6258 the first cycle. Workaround that. */
6259 sched_ib
.filled
= -2;
6262 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6263 It is invoked just before current cycle finishes and is used here
6264 to track if instruction buffer got its two words this cycle. */
6266 m68k_sched_dfa_pre_advance_cycle (void)
6268 if (!sched_ib
.enabled_p
)
6271 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6273 sched_ib
.filled
+= 2;
6275 if (sched_ib
.filled
> sched_ib
.size
)
6276 sched_ib
.filled
= sched_ib
.size
;
6280 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6281 It is invoked just after new cycle begins and is used here
6282 to setup number of filled words in the instruction buffer so that
6283 instructions which won't have all their words prefetched would be
6284 stalled for a cycle. */
6286 m68k_sched_dfa_post_advance_cycle (void)
6290 if (!sched_ib
.enabled_p
)
6293 /* Setup number of prefetched instruction words in the instruction
6295 i
= max_insn_size
- sched_ib
.filled
;
6299 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6300 /* Pick up scheduler state. */
6305 /* Return X or Y (depending on OPX_P) operand of INSN,
6306 if it is an integer register, or NULL overwise. */
6308 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6314 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6316 op
= sched_get_operand (insn
, true);
6317 gcc_assert (op
!= NULL
);
6319 if (!reload_completed
&& !REG_P (op
))
6325 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6327 op
= sched_get_operand (insn
, false);
6328 gcc_assert (op
!= NULL
);
6330 if (!reload_completed
&& !REG_P (op
))
6338 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6341 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6343 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6354 /* Return X or Y (depending on OPX_P) operand of INSN,
6355 if it is a MEM, or NULL overwise. */
6357 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6377 if (opy_p
&& sched_mem_operand_p (insn
, false))
6378 return sched_get_operand (insn
, false);
6380 if (opx_p
&& sched_mem_operand_p (insn
, true))
6381 return sched_get_operand (insn
, true);
6387 /* Return non-zero if PRO modifies register used as part of
6390 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6395 pro_x
= sched_get_reg_operand (pro
, true);
6399 con_mem_read
= sched_get_mem_operand (con
, true, false);
6400 gcc_assert (con_mem_read
!= NULL
);
6402 if (reg_mentioned_p (pro_x
, con_mem_read
))
6408 /* Helper function for m68k_sched_indexed_address_bypass_p.
6409 if PRO modifies register used as index in CON,
6410 return scale of indexed memory access in CON. Return zero overwise. */
6412 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6416 struct m68k_address address
;
6418 reg
= sched_get_reg_operand (pro
, true);
6422 mem
= sched_get_mem_operand (con
, true, false);
6423 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6425 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6429 if (REGNO (reg
) == REGNO (address
.index
))
6431 gcc_assert (address
.scale
!= 0);
6432 return address
.scale
;
6438 /* Return non-zero if PRO modifies register used
6439 as index with scale 2 or 4 in CON. */
6441 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6443 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6444 && sched_cfv4_bypass_data
.con
== NULL
6445 && sched_cfv4_bypass_data
.scale
== 0);
6447 switch (sched_get_indexed_address_scale (pro
, con
))
6450 /* We can't have a variable latency bypass, so
6451 remember to adjust the insn cost in adjust_cost hook. */
6452 sched_cfv4_bypass_data
.pro
= pro
;
6453 sched_cfv4_bypass_data
.con
= con
;
6454 sched_cfv4_bypass_data
.scale
= 1;
6466 /* We generate a two-instructions program at M_TRAMP :
6467 movea.l &CHAIN_VALUE,%a0
6469 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6472 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6474 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6477 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6479 mem
= adjust_address (m_tramp
, HImode
, 0);
6480 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6481 mem
= adjust_address (m_tramp
, SImode
, 2);
6482 emit_move_insn (mem
, chain_value
);
6484 mem
= adjust_address (m_tramp
, HImode
, 6);
6485 emit_move_insn (mem
, GEN_INT(0x4EF9));
6486 mem
= adjust_address (m_tramp
, SImode
, 8);
6487 emit_move_insn (mem
, fnaddr
);
6489 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6492 /* On the 68000, the RTS insn cannot pop anything.
6493 On the 68010, the RTD insn may be used to pop them if the number
6494 of args is fixed, but if the number is variable then the caller
6495 must pop them all. RTD can't be used for library calls now
6496 because the library is compiled with the Unix compiler.
6497 Use of RTD is a selectable option, since it is incompatible with
6498 standard Unix calling sequences. If the option is not selected,
6499 the caller must always pop the args. */
6502 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6506 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6507 && (!stdarg_p (funtype
)))
6511 /* Make sure everything's fine if we *don't* have a given processor.
6512 This assumes that putting a register in fixed_regs will keep the
6513 compiler's mitts completely off it. We don't bother to zero it out
6514 of register classes. */
6517 m68k_conditional_register_usage (void)
6521 if (!TARGET_HARD_FLOAT
)
6523 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6524 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6525 if (TEST_HARD_REG_BIT (x
, i
))
6526 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6529 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6533 m68k_init_sync_libfuncs (void)
6535 init_sync_libfuncs (UNITS_PER_WORD
);
6538 /* Implements EPILOGUE_USES. All registers are live on exit from an
6539 interrupt routine. */
6541 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6543 return (reload_completed
6544 && (m68k_get_function_kind (current_function_decl
)
6545 == m68k_fk_interrupt_handler
));
6549 /* Implement TARGET_C_EXCESS_PRECISION.
6551 Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
6552 instructions, we get proper intermediate rounding, otherwise we
6553 get extended precision results. */
6555 static enum flt_eval_method
6556 m68k_excess_precision (enum excess_precision_type type
)
6560 case EXCESS_PRECISION_TYPE_FAST
:
6561 /* The fastest type to promote to will always be the native type,
6562 whether that occurs with implicit excess precision or
6564 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6565 case EXCESS_PRECISION_TYPE_STANDARD
:
6566 case EXCESS_PRECISION_TYPE_IMPLICIT
:
6567 /* Otherwise, the excess precision we want when we are
6568 in a standards compliant mode, and the implicit precision we
6569 provide can be identical. */
6570 if (TARGET_68040
|| ! TARGET_68881
)
6571 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6573 return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE
;
6577 return FLT_EVAL_METHOD_UNPREDICTABLE
;
6580 #include "gt-m68k.h"