1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
46 #include "sched-int.h"
47 #include "insn-codes.h"
51 enum reg_class regno_reg_class
[] =
53 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
54 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
55 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
56 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
57 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
58 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
63 /* The minimum number of integer registers that we want to save with the
64 movem instruction. Using two movel instructions instead of a single
65 moveml is about 15% faster for the 68020 and 68030 at no expense in
67 #define MIN_MOVEM_REGS 3
69 /* The minimum number of floating point registers that we want to save
70 with the fmovem instruction. */
71 #define MIN_FMOVEM_REGS 1
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
91 unsigned int fpu_mask
;
93 /* Offsets relative to ARG_POINTER. */
94 HOST_WIDE_INT frame_pointer_offset
;
95 HOST_WIDE_INT stack_pointer_offset
;
97 /* Function which the above information refers to. */
101 /* Current frame information calculated by m68k_compute_frame_layout(). */
102 static struct m68k_frame current_frame
;
104 /* Structure describing an m68k address.
106 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
107 with null fields evaluating to 0. Here:
109 - BASE satisfies m68k_legitimate_base_reg_p
110 - INDEX satisfies m68k_legitimate_index_reg_p
111 - OFFSET satisfies m68k_legitimate_constant_address_p
113 INDEX is either HImode or SImode. The other fields are SImode.
115 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
116 the address is (BASE)+. */
117 struct m68k_address
{
125 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
126 static int m68k_sched_issue_rate (void);
127 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
128 static void m68k_sched_md_init_global (FILE *, int, int);
129 static void m68k_sched_md_finish_global (FILE *, int);
130 static void m68k_sched_md_init (FILE *, int, int);
131 static void m68k_sched_dfa_pre_advance_cycle (void);
132 static void m68k_sched_dfa_post_advance_cycle (void);
133 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
135 static bool m68k_can_eliminate (const int, const int);
136 static void m68k_conditional_register_usage (void);
137 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
138 static bool m68k_handle_option (struct gcc_options
*, struct gcc_options
*,
139 const struct cl_decoded_option
*, location_t
);
140 static void m68k_option_override (void);
141 static rtx
find_addr_reg (rtx
);
142 static const char *singlemove_string (rtx
*);
143 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
144 HOST_WIDE_INT
, tree
);
145 static rtx
m68k_struct_value_rtx (tree
, int);
146 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
147 tree args
, int flags
,
149 static void m68k_compute_frame_layout (void);
150 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
151 static bool m68k_ok_for_sibcall_p (tree
, tree
);
152 static bool m68k_tls_symbol_p (rtx
);
153 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
154 static bool m68k_rtx_costs (rtx
, int, int, int *, bool);
155 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
156 static bool m68k_return_in_memory (const_tree
, const_tree
);
158 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
159 static void m68k_trampoline_init (rtx
, tree
, rtx
);
160 static int m68k_return_pops_args (tree
, tree
, int);
161 static rtx
m68k_delegitimize_address (rtx
);
162 static void m68k_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
164 static rtx
m68k_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
166 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
168 /* Initialize the GCC target structure. */
170 #if INT_OP_GROUP == INT_OP_DOT_WORD
171 #undef TARGET_ASM_ALIGNED_HI_OP
172 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
175 #if INT_OP_GROUP == INT_OP_NO_DOT
176 #undef TARGET_ASM_BYTE_OP
177 #define TARGET_ASM_BYTE_OP "\tbyte\t"
178 #undef TARGET_ASM_ALIGNED_HI_OP
179 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
180 #undef TARGET_ASM_ALIGNED_SI_OP
181 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
184 #if INT_OP_GROUP == INT_OP_DC
185 #undef TARGET_ASM_BYTE_OP
186 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
187 #undef TARGET_ASM_ALIGNED_HI_OP
188 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
189 #undef TARGET_ASM_ALIGNED_SI_OP
190 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
193 #undef TARGET_ASM_UNALIGNED_HI_OP
194 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
195 #undef TARGET_ASM_UNALIGNED_SI_OP
196 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
198 #undef TARGET_ASM_OUTPUT_MI_THUNK
199 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
200 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
201 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
203 #undef TARGET_ASM_FILE_START_APP_OFF
204 #define TARGET_ASM_FILE_START_APP_OFF true
206 #undef TARGET_LEGITIMIZE_ADDRESS
207 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
209 #undef TARGET_SCHED_ADJUST_COST
210 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
212 #undef TARGET_SCHED_ISSUE_RATE
213 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
215 #undef TARGET_SCHED_VARIABLE_ISSUE
216 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
218 #undef TARGET_SCHED_INIT_GLOBAL
219 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
221 #undef TARGET_SCHED_FINISH_GLOBAL
222 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
224 #undef TARGET_SCHED_INIT
225 #define TARGET_SCHED_INIT m68k_sched_md_init
227 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
228 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
230 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
231 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
233 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
234 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
235 m68k_sched_first_cycle_multipass_dfa_lookahead
237 #undef TARGET_HANDLE_OPTION
238 #define TARGET_HANDLE_OPTION m68k_handle_option
240 #undef TARGET_OPTION_OVERRIDE
241 #define TARGET_OPTION_OVERRIDE m68k_option_override
243 #undef TARGET_RTX_COSTS
244 #define TARGET_RTX_COSTS m68k_rtx_costs
246 #undef TARGET_ATTRIBUTE_TABLE
247 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
249 #undef TARGET_PROMOTE_PROTOTYPES
250 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
252 #undef TARGET_STRUCT_VALUE_RTX
253 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
255 #undef TARGET_CANNOT_FORCE_CONST_MEM
256 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
258 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
259 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
261 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
262 #undef TARGET_RETURN_IN_MEMORY
263 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
267 #undef TARGET_HAVE_TLS
268 #define TARGET_HAVE_TLS (true)
270 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
271 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
274 #undef TARGET_LEGITIMATE_ADDRESS_P
275 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
277 #undef TARGET_CAN_ELIMINATE
278 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
280 #undef TARGET_CONDITIONAL_REGISTER_USAGE
281 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
283 #undef TARGET_TRAMPOLINE_INIT
284 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
286 #undef TARGET_RETURN_POPS_ARGS
287 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
289 #undef TARGET_DELEGITIMIZE_ADDRESS
290 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
292 #undef TARGET_FUNCTION_ARG
293 #define TARGET_FUNCTION_ARG m68k_function_arg
295 #undef TARGET_FUNCTION_ARG_ADVANCE
296 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
298 #undef TARGET_LEGITIMATE_CONSTANT_P
299 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
301 static const struct attribute_spec m68k_attribute_table
[] =
303 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
304 affects_type_identity } */
305 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
307 { "interrupt_handler", 0, 0, true, false, false,
308 m68k_handle_fndecl_attribute
, false },
309 { "interrupt_thread", 0, 0, true, false, false,
310 m68k_handle_fndecl_attribute
, false },
311 { NULL
, 0, 0, false, false, false, NULL
, false }
314 struct gcc_target targetm
= TARGET_INITIALIZER
;
316 /* Base flags for 68k ISAs. */
317 #define FL_FOR_isa_00 FL_ISA_68000
318 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
319 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
320 generated 68881 code for 68020 and 68030 targets unless explicitly told
322 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
323 | FL_BITFIELD | FL_68881)
324 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
325 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
327 /* Base flags for ColdFire ISAs. */
328 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
329 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
330 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
331 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
332 /* ISA_C is not upwardly compatible with ISA_B. */
333 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
337 /* Traditional 68000 instruction sets. */
343 /* ColdFire instruction set variants. */
351 /* Information about one of the -march, -mcpu or -mtune arguments. */
352 struct m68k_target_selection
354 /* The argument being described. */
357 /* For -mcpu, this is the device selected by the option.
358 For -mtune and -march, it is a representative device
359 for the microarchitecture or ISA respectively. */
360 enum target_device device
;
362 /* The M68K_DEVICE fields associated with DEVICE. See the comment
363 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
365 enum uarch_type microarch
;
370 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
371 static const struct m68k_target_selection all_devices
[] =
373 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
374 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
375 #include "m68k-devices.def"
377 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
380 /* A list of all ISAs, mapping each one to a representative device.
381 Used for -march selection. */
382 static const struct m68k_target_selection all_isas
[] =
384 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
385 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
386 #include "m68k-isas.def"
388 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
391 /* A list of all microarchitectures, mapping each one to a representative
392 device. Used for -mtune selection. */
393 static const struct m68k_target_selection all_microarchs
[] =
395 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
396 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
397 #include "m68k-microarchs.def"
398 #undef M68K_MICROARCH
399 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
402 /* The entries associated with the -mcpu, -march and -mtune settings,
403 or null for options that have not been used. */
404 const struct m68k_target_selection
*m68k_cpu_entry
;
405 const struct m68k_target_selection
*m68k_arch_entry
;
406 const struct m68k_target_selection
*m68k_tune_entry
;
408 /* Which CPU we are generating code for. */
409 enum target_device m68k_cpu
;
411 /* Which microarchitecture to tune for. */
412 enum uarch_type m68k_tune
;
414 /* Which FPU to use. */
415 enum fpu_type m68k_fpu
;
417 /* The set of FL_* flags that apply to the target processor. */
418 unsigned int m68k_cpu_flags
;
420 /* The set of FL_* flags that apply to the processor to be tuned for. */
421 unsigned int m68k_tune_flags
;
423 /* Asm templates for calling or jumping to an arbitrary symbolic address,
424 or NULL if such calls or jumps are not supported. The address is held
426 const char *m68k_symbolic_call
;
427 const char *m68k_symbolic_jump
;
429 /* Enum variable that corresponds to m68k_symbolic_call values. */
430 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
433 /* Implement TARGET_HANDLE_OPTION. */
436 m68k_handle_option (struct gcc_options
*opts
,
437 struct gcc_options
*opts_set ATTRIBUTE_UNUSED
,
438 const struct cl_decoded_option
*decoded
,
441 size_t code
= decoded
->opt_index
;
442 const char *arg
= decoded
->arg
;
443 int value
= decoded
->value
;
448 opts
->x_m68k_tune_option
= u68020_40
;
449 opts
->x_m68k_cpu_option
= m68020
;
453 opts
->x_m68k_tune_option
= u68020_60
;
454 opts
->x_m68k_cpu_option
= m68020
;
457 case OPT_mshared_library_id_
:
458 if (value
> MAX_LIBRARY_ID
)
459 error_at (loc
, "-mshared-library-id=%s is not between 0 and %d",
460 arg
, MAX_LIBRARY_ID
);
464 asprintf (&tmp
, "%d", (value
* -4) - 4);
465 opts
->x_m68k_library_id_string
= tmp
;
474 /* Implement TARGET_OPTION_OVERRIDE. */
477 m68k_option_override (void)
479 const struct m68k_target_selection
*entry
;
480 unsigned long target_mask
;
482 if (global_options_set
.x_m68k_arch_option
)
483 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
485 if (global_options_set
.x_m68k_cpu_option
)
486 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
488 if (global_options_set
.x_m68k_tune_option
)
489 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
497 -march=ARCH should generate code that runs any processor
498 implementing architecture ARCH. -mcpu=CPU should override -march
499 and should generate code that runs on processor CPU, making free
500 use of any instructions that CPU understands. -mtune=UARCH applies
501 on top of -mcpu or -march and optimizes the code for UARCH. It does
502 not change the target architecture. */
505 /* Complain if the -march setting is for a different microarchitecture,
506 or includes flags that the -mcpu setting doesn't. */
508 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
509 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
510 warning (0, "-mcpu=%s conflicts with -march=%s",
511 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
513 entry
= m68k_cpu_entry
;
516 entry
= m68k_arch_entry
;
519 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
521 m68k_cpu_flags
= entry
->flags
;
523 /* Use the architecture setting to derive default values for
527 /* ColdFire is lenient about alignment. */
528 if (!TARGET_COLDFIRE
)
529 target_mask
|= MASK_STRICT_ALIGNMENT
;
531 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
532 target_mask
|= MASK_BITFIELD
;
533 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
534 target_mask
|= MASK_CF_HWDIV
;
535 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
536 target_mask
|= MASK_HARD_FLOAT
;
537 target_flags
|= target_mask
& ~target_flags_explicit
;
539 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
540 m68k_cpu
= entry
->device
;
543 m68k_tune
= m68k_tune_entry
->microarch
;
544 m68k_tune_flags
= m68k_tune_entry
->flags
;
546 #ifdef M68K_DEFAULT_TUNE
547 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
549 enum target_device dev
;
550 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
551 m68k_tune_flags
= all_devices
[dev
]->flags
;
556 m68k_tune
= entry
->microarch
;
557 m68k_tune_flags
= entry
->flags
;
560 /* Set the type of FPU. */
561 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
562 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
565 /* Sanity check to ensure that msep-data and mid-sahred-library are not
566 * both specified together. Doing so simply doesn't make sense.
568 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
569 error ("cannot specify both -msep-data and -mid-shared-library");
571 /* If we're generating code for a separate A5 relative data segment,
572 * we've got to enable -fPIC as well. This might be relaxable to
573 * -fpic but it hasn't been tested properly.
575 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
578 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
579 error if the target does not support them. */
580 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
581 error ("-mpcrel -fPIC is not currently supported on selected cpu");
583 /* ??? A historic way of turning on pic, or is this intended to
584 be an embedded thing that doesn't have the same name binding
585 significance that it does on hosted ELF systems? */
586 if (TARGET_PCREL
&& flag_pic
== 0)
591 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
593 m68k_symbolic_jump
= "jra %a0";
595 else if (TARGET_ID_SHARED_LIBRARY
)
596 /* All addresses must be loaded from the GOT. */
598 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
601 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
603 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
606 /* No unconditional long branch */;
607 else if (TARGET_PCREL
)
608 m68k_symbolic_jump
= "bra%.l %c0";
610 m68k_symbolic_jump
= "bra%.l %p0";
611 /* Turn off function cse if we are doing PIC. We always want
612 function call to be done as `bsr foo@PLTPC'. */
613 /* ??? It's traditional to do this for -mpcrel too, but it isn't
614 clear how intentional that is. */
615 flag_no_function_cse
= 1;
618 switch (m68k_symbolic_call_var
)
620 case M68K_SYMBOLIC_CALL_JSR
:
621 m68k_symbolic_call
= "jsr %a0";
624 case M68K_SYMBOLIC_CALL_BSR_C
:
625 m68k_symbolic_call
= "bsr%.l %c0";
628 case M68K_SYMBOLIC_CALL_BSR_P
:
629 m68k_symbolic_call
= "bsr%.l %p0";
632 case M68K_SYMBOLIC_CALL_NONE
:
633 gcc_assert (m68k_symbolic_call
== NULL
);
640 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
641 if (align_labels
> 2)
643 warning (0, "-falign-labels=%d is not supported", align_labels
);
648 warning (0, "-falign-loops=%d is not supported", align_loops
);
653 SUBTARGET_OVERRIDE_OPTIONS
;
655 /* Setup scheduling options. */
657 m68k_sched_cpu
= CPU_CFV1
;
659 m68k_sched_cpu
= CPU_CFV2
;
661 m68k_sched_cpu
= CPU_CFV3
;
663 m68k_sched_cpu
= CPU_CFV4
;
666 m68k_sched_cpu
= CPU_UNKNOWN
;
667 flag_schedule_insns
= 0;
668 flag_schedule_insns_after_reload
= 0;
669 flag_modulo_sched
= 0;
672 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
674 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
675 m68k_sched_mac
= MAC_CF_EMAC
;
676 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
677 m68k_sched_mac
= MAC_CF_MAC
;
679 m68k_sched_mac
= MAC_NO
;
683 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
684 given argument and NAME is the argument passed to -mcpu. Return NULL
685 if -mcpu was not passed. */
688 m68k_cpp_cpu_ident (const char *prefix
)
692 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
695 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
696 given argument and NAME is the name of the representative device for
697 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
700 m68k_cpp_cpu_family (const char *prefix
)
704 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
707 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
708 "interrupt_handler" attribute and interrupt_thread if FUNC has an
709 "interrupt_thread" attribute. Otherwise, return
710 m68k_fk_normal_function. */
712 enum m68k_function_kind
713 m68k_get_function_kind (tree func
)
717 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
719 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
721 return m68k_fk_interrupt_handler
;
723 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
725 return m68k_fk_interrupt_handler
;
727 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
729 return m68k_fk_interrupt_thread
;
731 return m68k_fk_normal_function
;
734 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
735 struct attribute_spec.handler. */
737 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
738 tree args ATTRIBUTE_UNUSED
,
739 int flags ATTRIBUTE_UNUSED
,
742 if (TREE_CODE (*node
) != FUNCTION_DECL
)
744 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
746 *no_add_attrs
= true;
749 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
751 error ("multiple interrupt attributes not allowed");
752 *no_add_attrs
= true;
756 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
758 error ("interrupt_thread is available only on fido");
759 *no_add_attrs
= true;
766 m68k_compute_frame_layout (void)
770 enum m68k_function_kind func_kind
=
771 m68k_get_function_kind (current_function_decl
);
772 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
773 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
775 /* Only compute the frame once per function.
776 Don't cache information until reload has been completed. */
777 if (current_frame
.funcdef_no
== current_function_funcdef_no
781 current_frame
.size
= (get_frame_size () + 3) & -4;
785 /* Interrupt thread does not need to save any register. */
786 if (!interrupt_thread
)
787 for (regno
= 0; regno
< 16; regno
++)
788 if (m68k_save_reg (regno
, interrupt_handler
))
790 mask
|= 1 << (regno
- D0_REG
);
793 current_frame
.offset
= saved
* 4;
794 current_frame
.reg_no
= saved
;
795 current_frame
.reg_mask
= mask
;
797 current_frame
.foffset
= 0;
799 if (TARGET_HARD_FLOAT
)
801 /* Interrupt thread does not need to save any register. */
802 if (!interrupt_thread
)
803 for (regno
= 16; regno
< 24; regno
++)
804 if (m68k_save_reg (regno
, interrupt_handler
))
806 mask
|= 1 << (regno
- FP0_REG
);
809 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
810 current_frame
.offset
+= current_frame
.foffset
;
812 current_frame
.fpu_no
= saved
;
813 current_frame
.fpu_mask
= mask
;
815 /* Remember what function this frame refers to. */
816 current_frame
.funcdef_no
= current_function_funcdef_no
;
819 /* Worker function for TARGET_CAN_ELIMINATE. */
822 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
824 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
828 m68k_initial_elimination_offset (int from
, int to
)
831 /* The arg pointer points 8 bytes before the start of the arguments,
832 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
833 frame pointer in most frames. */
834 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
835 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
836 return argptr_offset
;
838 m68k_compute_frame_layout ();
840 gcc_assert (to
== STACK_POINTER_REGNUM
);
843 case ARG_POINTER_REGNUM
:
844 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
845 case FRAME_POINTER_REGNUM
:
846 return current_frame
.offset
+ current_frame
.size
;
852 /* Refer to the array `regs_ever_live' to determine which registers
853 to save; `regs_ever_live[I]' is nonzero if register number I
854 is ever used in the function. This function is responsible for
855 knowing which registers should not be saved even if used.
856 Return true if we need to save REGNO. */
859 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
861 if (flag_pic
&& regno
== PIC_REG
)
863 if (crtl
->saves_all_registers
)
865 if (crtl
->uses_pic_offset_table
)
867 /* Reload may introduce constant pool references into a function
868 that thitherto didn't need a PIC register. Note that the test
869 above will not catch that case because we will only set
870 crtl->uses_pic_offset_table when emitting
871 the address reloads. */
872 if (crtl
->uses_const_pool
)
876 if (crtl
->calls_eh_return
)
881 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
882 if (test
== INVALID_REGNUM
)
889 /* Fixed regs we never touch. */
890 if (fixed_regs
[regno
])
893 /* The frame pointer (if it is such) is handled specially. */
894 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
897 /* Interrupt handlers must also save call_used_regs
898 if they are live or when calling nested functions. */
899 if (interrupt_handler
)
901 if (df_regs_ever_live_p (regno
))
904 if (!current_function_is_leaf
&& call_used_regs
[regno
])
908 /* Never need to save registers that aren't touched. */
909 if (!df_regs_ever_live_p (regno
))
912 /* Otherwise save everything that isn't call-clobbered. */
913 return !call_used_regs
[regno
];
916 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
917 the lowest memory address. COUNT is the number of registers to be
918 moved, with register REGNO + I being moved if bit I of MASK is set.
919 STORE_P specifies the direction of the move and ADJUST_STACK_P says
920 whether or not this is pre-decrement (if STORE_P) or post-increment
921 (if !STORE_P) operation. */
924 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
925 unsigned int count
, unsigned int regno
,
926 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
929 rtx body
, addr
, src
, operands
[2];
930 enum machine_mode mode
;
932 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
933 mode
= reg_raw_mode
[regno
];
938 src
= plus_constant (base
, (count
939 * GET_MODE_SIZE (mode
)
940 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
941 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
944 for (; mask
!= 0; mask
>>= 1, regno
++)
947 addr
= plus_constant (base
, offset
);
948 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
949 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
950 XVECEXP (body
, 0, i
++)
951 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
952 offset
+= GET_MODE_SIZE (mode
);
954 gcc_assert (i
== XVECLEN (body
, 0));
956 return emit_insn (body
);
959 /* Make INSN a frame-related instruction. */
962 m68k_set_frame_related (rtx insn
)
967 RTX_FRAME_RELATED_P (insn
) = 1;
968 body
= PATTERN (insn
);
969 if (GET_CODE (body
) == PARALLEL
)
970 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
971 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
974 /* Emit RTL for the "prologue" define_expand. */
977 m68k_expand_prologue (void)
979 HOST_WIDE_INT fsize_with_regs
;
980 rtx limit
, src
, dest
;
982 m68k_compute_frame_layout ();
984 if (flag_stack_usage
)
985 current_function_static_stack_size
986 = current_frame
.size
+ current_frame
.offset
;
988 /* If the stack limit is a symbol, we can check it here,
989 before actually allocating the space. */
990 if (crtl
->limit_stack
991 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
993 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
994 if (!m68k_legitimate_constant_p (Pmode
, limit
))
996 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
997 limit
= gen_rtx_REG (Pmode
, D0_REG
);
999 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1000 stack_pointer_rtx
, limit
),
1001 stack_pointer_rtx
, limit
,
1005 fsize_with_regs
= current_frame
.size
;
1006 if (TARGET_COLDFIRE
)
1008 /* ColdFire's move multiple instructions do not allow pre-decrement
1009 addressing. Add the size of movem saves to the initial stack
1010 allocation instead. */
1011 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1012 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1013 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1014 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1017 if (frame_pointer_needed
)
1019 if (fsize_with_regs
== 0 && TUNE_68040
)
1021 /* On the 68040, two separate moves are faster than link.w 0. */
1022 dest
= gen_frame_mem (Pmode
,
1023 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1024 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1025 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1026 stack_pointer_rtx
));
1028 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1029 m68k_set_frame_related
1030 (emit_insn (gen_link (frame_pointer_rtx
,
1031 GEN_INT (-4 - fsize_with_regs
))));
1034 m68k_set_frame_related
1035 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1036 m68k_set_frame_related
1037 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1039 GEN_INT (-fsize_with_regs
))));
1042 /* If the frame pointer is needed, emit a special barrier that
1043 will prevent the scheduler from moving stores to the frame
1044 before the stack adjustment. */
1045 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1047 else if (fsize_with_regs
!= 0)
1048 m68k_set_frame_related
1049 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1051 GEN_INT (-fsize_with_regs
))));
1053 if (current_frame
.fpu_mask
)
1055 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1057 m68k_set_frame_related
1058 (m68k_emit_movem (stack_pointer_rtx
,
1059 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1060 current_frame
.fpu_no
, FP0_REG
,
1061 current_frame
.fpu_mask
, true, true));
1066 /* If we're using moveml to save the integer registers,
1067 the stack pointer will point to the bottom of the moveml
1068 save area. Find the stack offset of the first FP register. */
1069 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1072 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1073 m68k_set_frame_related
1074 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1075 current_frame
.fpu_no
, FP0_REG
,
1076 current_frame
.fpu_mask
, true, false));
1080 /* If the stack limit is not a symbol, check it here.
1081 This has the disadvantage that it may be too late... */
1082 if (crtl
->limit_stack
)
1084 if (REG_P (stack_limit_rtx
))
1085 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1087 stack_pointer_rtx
, stack_limit_rtx
,
1090 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1091 warning (0, "stack limit expression is not supported");
1094 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1096 /* Store each register separately in the same order moveml does. */
1099 for (i
= 16; i
-- > 0; )
1100 if (current_frame
.reg_mask
& (1 << i
))
1102 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1103 dest
= gen_frame_mem (SImode
,
1104 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1105 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1110 if (TARGET_COLDFIRE
)
1111 /* The required register save space has already been allocated.
1112 The first register should be stored at (%sp). */
1113 m68k_set_frame_related
1114 (m68k_emit_movem (stack_pointer_rtx
, 0,
1115 current_frame
.reg_no
, D0_REG
,
1116 current_frame
.reg_mask
, true, false));
1118 m68k_set_frame_related
1119 (m68k_emit_movem (stack_pointer_rtx
,
1120 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1121 current_frame
.reg_no
, D0_REG
,
1122 current_frame
.reg_mask
, true, true));
1125 if (!TARGET_SEP_DATA
1126 && crtl
->uses_pic_offset_table
)
1127 emit_insn (gen_load_got (pic_offset_table_rtx
));
1130 /* Return true if a simple (return) instruction is sufficient for this
1131 instruction (i.e. if no epilogue is needed). */
1134 m68k_use_return_insn (void)
1136 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1139 m68k_compute_frame_layout ();
1140 return current_frame
.offset
== 0;
1143 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1144 SIBCALL_P says which.
1146 The function epilogue should not depend on the current stack pointer!
1147 It should use the frame pointer only, if there is a frame pointer.
1148 This is mandatory because of alloca; we also take advantage of it to
1149 omit stack adjustments before returning. */
1152 m68k_expand_epilogue (bool sibcall_p
)
1154 HOST_WIDE_INT fsize
, fsize_with_regs
;
1155 bool big
, restore_from_sp
;
1157 m68k_compute_frame_layout ();
1159 fsize
= current_frame
.size
;
1161 restore_from_sp
= false;
1163 /* FIXME : current_function_is_leaf below is too strong.
1164 What we really need to know there is if there could be pending
1165 stack adjustment needed at that point. */
1166 restore_from_sp
= (!frame_pointer_needed
1167 || (!cfun
->calls_alloca
1168 && current_function_is_leaf
));
1170 /* fsize_with_regs is the size we need to adjust the sp when
1171 popping the frame. */
1172 fsize_with_regs
= fsize
;
1173 if (TARGET_COLDFIRE
&& restore_from_sp
)
1175 /* ColdFire's move multiple instructions do not allow post-increment
1176 addressing. Add the size of movem loads to the final deallocation
1178 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1179 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1180 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1181 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1184 if (current_frame
.offset
+ fsize
>= 0x8000
1186 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1189 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1190 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1192 /* ColdFire's move multiple instructions do not support the
1193 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1194 stack-based restore. */
1195 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1196 GEN_INT (-(current_frame
.offset
+ fsize
)));
1197 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1198 gen_rtx_REG (Pmode
, A1_REG
),
1199 frame_pointer_rtx
));
1200 restore_from_sp
= true;
1204 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1210 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1212 /* Restore each register separately in the same order moveml does. */
1214 HOST_WIDE_INT offset
;
1216 offset
= current_frame
.offset
+ fsize
;
1217 for (i
= 0; i
< 16; i
++)
1218 if (current_frame
.reg_mask
& (1 << i
))
1224 /* Generate the address -OFFSET(%fp,%a1.l). */
1225 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1226 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1227 addr
= plus_constant (addr
, -offset
);
1229 else if (restore_from_sp
)
1230 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1232 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1233 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1234 gen_frame_mem (SImode
, addr
));
1235 offset
-= GET_MODE_SIZE (SImode
);
1238 else if (current_frame
.reg_mask
)
1241 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1242 gen_rtx_REG (Pmode
, A1_REG
),
1244 -(current_frame
.offset
+ fsize
),
1245 current_frame
.reg_no
, D0_REG
,
1246 current_frame
.reg_mask
, false, false);
1247 else if (restore_from_sp
)
1248 m68k_emit_movem (stack_pointer_rtx
, 0,
1249 current_frame
.reg_no
, D0_REG
,
1250 current_frame
.reg_mask
, false,
1253 m68k_emit_movem (frame_pointer_rtx
,
1254 -(current_frame
.offset
+ fsize
),
1255 current_frame
.reg_no
, D0_REG
,
1256 current_frame
.reg_mask
, false, false);
1259 if (current_frame
.fpu_no
> 0)
1262 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1263 gen_rtx_REG (Pmode
, A1_REG
),
1265 -(current_frame
.foffset
+ fsize
),
1266 current_frame
.fpu_no
, FP0_REG
,
1267 current_frame
.fpu_mask
, false, false);
1268 else if (restore_from_sp
)
1270 if (TARGET_COLDFIRE
)
1274 /* If we used moveml to restore the integer registers, the
1275 stack pointer will still point to the bottom of the moveml
1276 save area. Find the stack offset of the first FP
1278 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1281 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1282 m68k_emit_movem (stack_pointer_rtx
, offset
,
1283 current_frame
.fpu_no
, FP0_REG
,
1284 current_frame
.fpu_mask
, false, false);
1287 m68k_emit_movem (stack_pointer_rtx
, 0,
1288 current_frame
.fpu_no
, FP0_REG
,
1289 current_frame
.fpu_mask
, false, true);
1292 m68k_emit_movem (frame_pointer_rtx
,
1293 -(current_frame
.foffset
+ fsize
),
1294 current_frame
.fpu_no
, FP0_REG
,
1295 current_frame
.fpu_mask
, false, false);
1298 if (frame_pointer_needed
)
1299 emit_insn (gen_unlink (frame_pointer_rtx
));
1300 else if (fsize_with_regs
)
1301 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1303 GEN_INT (fsize_with_regs
)));
1305 if (crtl
->calls_eh_return
)
1306 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1308 EH_RETURN_STACKADJ_RTX
));
1311 emit_jump_insn (ret_rtx
);
1314 /* Return true if X is a valid comparison operator for the dbcc
1317 Note it rejects floating point comparison operators.
1318 (In the future we could use Fdbcc).
1320 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1323 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1325 switch (GET_CODE (x
))
1327 case EQ
: case NE
: case GTU
: case LTU
:
1331 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1333 case GT
: case LT
: case GE
: case LE
:
1334 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1340 /* Return nonzero if flags are currently in the 68881 flag register. */
1342 flags_in_68881 (void)
1344 /* We could add support for these in the future */
1345 return cc_status
.flags
& CC_IN_68881
;
1348 /* Return true if PARALLEL contains register REGNO. */
1350 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1354 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1357 if (GET_CODE (parallel
) != PARALLEL
)
1360 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1364 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1365 if (REG_P (x
) && REGNO (x
) == regno
)
1372 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1375 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1377 enum m68k_function_kind kind
;
1379 /* We cannot use sibcalls for nested functions because we use the
1380 static chain register for indirect calls. */
1381 if (CALL_EXPR_STATIC_CHAIN (exp
))
1384 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1386 /* Check that the return value locations are the same. For
1387 example that we aren't returning a value from the sibling in
1388 a D0 register but then need to transfer it to a A0 register. */
1392 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1394 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1396 /* Check that the values are equal or that the result the callee
1397 function returns is superset of what the current function returns. */
1398 if (!(rtx_equal_p (cfun_value
, call_value
)
1399 || (REG_P (cfun_value
)
1400 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1404 kind
= m68k_get_function_kind (current_function_decl
);
1405 if (kind
== m68k_fk_normal_function
)
1406 /* We can always sibcall from a normal function, because it's
1407 undefined if it is calling an interrupt function. */
1410 /* Otherwise we can only sibcall if the function kind is known to be
1412 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1418 /* On the m68k all args are always pushed. */
1421 m68k_function_arg (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
1422 enum machine_mode mode ATTRIBUTE_UNUSED
,
1423 const_tree type ATTRIBUTE_UNUSED
,
1424 bool named ATTRIBUTE_UNUSED
)
1430 m68k_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1431 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1433 *cum
+= (mode
!= BLKmode
1434 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1435 : (int_size_in_bytes (type
) + 3) & ~3);
1438 /* Convert X to a legitimate function call memory reference and return the
1442 m68k_legitimize_call_address (rtx x
)
1444 gcc_assert (MEM_P (x
));
1445 if (call_operand (XEXP (x
, 0), VOIDmode
))
1447 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1450 /* Likewise for sibling calls. */
1453 m68k_legitimize_sibcall_address (rtx x
)
1455 gcc_assert (MEM_P (x
));
1456 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1459 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1460 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1463 /* Convert X to a legitimate address and return it if successful. Otherwise
1466 For the 68000, we handle X+REG by loading X into a register R and
1467 using R+REG. R will go in an address reg and indexing will be used.
1468 However, if REG is a broken-out memory address or multiplication,
1469 nothing needs to be done because REG can certainly go in an address reg. */
1472 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1474 if (m68k_tls_symbol_p (x
))
1475 return m68k_legitimize_tls_address (x
);
1477 if (GET_CODE (x
) == PLUS
)
1479 int ch
= (x
) != (oldx
);
1482 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1484 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1487 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1489 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1492 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1496 if (GET_CODE (XEXP (x
, 1)) == REG
1497 && GET_CODE (XEXP (x
, 0)) == REG
)
1499 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1502 x
= force_operand (x
, 0);
1506 if (memory_address_p (mode
, x
))
1509 if (GET_CODE (XEXP (x
, 0)) == REG
1510 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1511 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1512 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1514 rtx temp
= gen_reg_rtx (Pmode
);
1515 rtx val
= force_operand (XEXP (x
, 1), 0);
1516 emit_move_insn (temp
, val
);
1519 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1520 && GET_CODE (XEXP (x
, 0)) == REG
)
1521 x
= force_operand (x
, 0);
1523 else if (GET_CODE (XEXP (x
, 1)) == REG
1524 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1525 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1526 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1528 rtx temp
= gen_reg_rtx (Pmode
);
1529 rtx val
= force_operand (XEXP (x
, 0), 0);
1530 emit_move_insn (temp
, val
);
1533 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1534 && GET_CODE (XEXP (x
, 1)) == REG
)
1535 x
= force_operand (x
, 0);
1543 /* Output a dbCC; jCC sequence. Note we do not handle the
1544 floating point version of this sequence (Fdbcc). We also
1545 do not handle alternative conditions when CC_NO_OVERFLOW is
1546 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1547 kick those out before we get here. */
1550 output_dbcc_and_branch (rtx
*operands
)
1552 switch (GET_CODE (operands
[3]))
1555 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1559 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1563 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1567 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1571 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1575 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1579 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1583 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1587 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1591 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1598 /* If the decrement is to be done in SImode, then we have
1599 to compensate for the fact that dbcc decrements in HImode. */
1600 switch (GET_MODE (operands
[0]))
1603 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1615 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1618 enum rtx_code op_code
= GET_CODE (op
);
1620 /* This does not produce a useful cc. */
1623 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1624 below. Swap the operands and change the op if these requirements
1625 are not fulfilled. */
1626 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1630 operand1
= operand2
;
1632 op_code
= swap_condition (op_code
);
1634 loperands
[0] = operand1
;
1635 if (GET_CODE (operand1
) == REG
)
1636 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1638 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1639 if (operand2
!= const0_rtx
)
1641 loperands
[2] = operand2
;
1642 if (GET_CODE (operand2
) == REG
)
1643 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1645 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1647 loperands
[4] = gen_label_rtx ();
1648 if (operand2
!= const0_rtx
)
1649 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1652 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1653 output_asm_insn ("tst%.l %0", loperands
);
1655 output_asm_insn ("cmp%.w #0,%0", loperands
);
1657 output_asm_insn ("jne %l4", loperands
);
1659 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1660 output_asm_insn ("tst%.l %1", loperands
);
1662 output_asm_insn ("cmp%.w #0,%1", loperands
);
1665 loperands
[5] = dest
;
1670 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1671 CODE_LABEL_NUMBER (loperands
[4]));
1672 output_asm_insn ("seq %5", loperands
);
1676 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1677 CODE_LABEL_NUMBER (loperands
[4]));
1678 output_asm_insn ("sne %5", loperands
);
1682 loperands
[6] = gen_label_rtx ();
1683 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1684 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1685 CODE_LABEL_NUMBER (loperands
[4]));
1686 output_asm_insn ("sgt %5", loperands
);
1687 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1688 CODE_LABEL_NUMBER (loperands
[6]));
1692 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1693 CODE_LABEL_NUMBER (loperands
[4]));
1694 output_asm_insn ("shi %5", loperands
);
1698 loperands
[6] = gen_label_rtx ();
1699 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1700 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1701 CODE_LABEL_NUMBER (loperands
[4]));
1702 output_asm_insn ("slt %5", loperands
);
1703 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1704 CODE_LABEL_NUMBER (loperands
[6]));
1708 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1709 CODE_LABEL_NUMBER (loperands
[4]));
1710 output_asm_insn ("scs %5", loperands
);
1714 loperands
[6] = gen_label_rtx ();
1715 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1716 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1717 CODE_LABEL_NUMBER (loperands
[4]));
1718 output_asm_insn ("sge %5", loperands
);
1719 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1720 CODE_LABEL_NUMBER (loperands
[6]));
1724 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1725 CODE_LABEL_NUMBER (loperands
[4]));
1726 output_asm_insn ("scc %5", loperands
);
1730 loperands
[6] = gen_label_rtx ();
1731 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1732 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1733 CODE_LABEL_NUMBER (loperands
[4]));
1734 output_asm_insn ("sle %5", loperands
);
1735 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1736 CODE_LABEL_NUMBER (loperands
[6]));
1740 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1741 CODE_LABEL_NUMBER (loperands
[4]));
1742 output_asm_insn ("sls %5", loperands
);
1752 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1754 operands
[0] = countop
;
1755 operands
[1] = dataop
;
1757 if (GET_CODE (countop
) == CONST_INT
)
1759 register int count
= INTVAL (countop
);
1760 /* If COUNT is bigger than size of storage unit in use,
1761 advance to the containing unit of same size. */
1762 if (count
> signpos
)
1764 int offset
= (count
& ~signpos
) / 8;
1765 count
= count
& signpos
;
1766 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1768 if (count
== signpos
)
1769 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1771 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1773 /* These three statements used to use next_insns_test_no...
1774 but it appears that this should do the same job. */
1776 && next_insn_tests_no_inequality (insn
))
1779 && next_insn_tests_no_inequality (insn
))
1782 && next_insn_tests_no_inequality (insn
))
1784 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1785 On some m68k variants unfortunately that's slower than btst.
1786 On 68000 and higher, that should also work for all HImode operands. */
1787 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1789 if (count
== 3 && DATA_REG_P (operands
[1])
1790 && next_insn_tests_no_inequality (insn
))
1792 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1793 return "move%.w %1,%%ccr";
1795 if (count
== 2 && DATA_REG_P (operands
[1])
1796 && next_insn_tests_no_inequality (insn
))
1798 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1799 return "move%.w %1,%%ccr";
1801 /* count == 1 followed by bvc/bvs and
1802 count == 0 followed by bcc/bcs are also possible, but need
1803 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1806 cc_status
.flags
= CC_NOT_NEGATIVE
;
1808 return "btst %0,%1";
1811 /* Return true if X is a legitimate base register. STRICT_P says
1812 whether we need strict checking. */
1815 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1817 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1818 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1823 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1824 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1827 /* Return true if X is a legitimate index register. STRICT_P says
1828 whether we need strict checking. */
1831 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1833 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1838 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1839 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1842 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1843 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1844 ADDRESS if so. STRICT_P says whether we need strict checking. */
1847 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1851 /* Check for a scale factor. */
1853 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1854 && GET_CODE (x
) == MULT
1855 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1856 && (INTVAL (XEXP (x
, 1)) == 2
1857 || INTVAL (XEXP (x
, 1)) == 4
1858 || (INTVAL (XEXP (x
, 1)) == 8
1859 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1861 scale
= INTVAL (XEXP (x
, 1));
1865 /* Check for a word extension. */
1866 if (!TARGET_COLDFIRE
1867 && GET_CODE (x
) == SIGN_EXTEND
1868 && GET_MODE (XEXP (x
, 0)) == HImode
)
1871 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1873 address
->scale
= scale
;
1881 /* Return true if X is an illegitimate symbolic constant. */
1884 m68k_illegitimate_symbolic_constant_p (rtx x
)
1888 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1890 split_const (x
, &base
, &offset
);
1891 if (GET_CODE (base
) == SYMBOL_REF
1892 && !offset_within_block_p (base
, INTVAL (offset
)))
1895 return m68k_tls_reference_p (x
, false);
1898 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1901 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1903 return m68k_illegitimate_symbolic_constant_p (x
);
1906 /* Return true if X is a legitimate constant address that can reach
1907 bytes in the range [X, X + REACH). STRICT_P says whether we need
1911 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1915 if (!CONSTANT_ADDRESS_P (x
))
1919 && !(strict_p
&& TARGET_PCREL
)
1920 && symbolic_operand (x
, VOIDmode
))
1923 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1925 split_const (x
, &base
, &offset
);
1926 if (GET_CODE (base
) == SYMBOL_REF
1927 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1931 return !m68k_tls_reference_p (x
, false);
1934 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1935 labels will become jump tables. */
1938 m68k_jump_table_ref_p (rtx x
)
1940 if (GET_CODE (x
) != LABEL_REF
)
1944 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1947 x
= next_nonnote_insn (x
);
1948 return x
&& JUMP_TABLE_DATA_P (x
);
1951 /* Return true if X is a legitimate address for values of mode MODE.
1952 STRICT_P says whether strict checking is needed. If the address
1953 is valid, describe its components in *ADDRESS. */
1956 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1957 bool strict_p
, struct m68k_address
*address
)
1961 memset (address
, 0, sizeof (*address
));
1963 if (mode
== BLKmode
)
1966 reach
= GET_MODE_SIZE (mode
);
1968 /* Check for (An) (mode 2). */
1969 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1975 /* Check for -(An) and (An)+ (modes 3 and 4). */
1976 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1977 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1979 address
->code
= GET_CODE (x
);
1980 address
->base
= XEXP (x
, 0);
1984 /* Check for (d16,An) (mode 5). */
1985 if (GET_CODE (x
) == PLUS
1986 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1987 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1988 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1990 address
->base
= XEXP (x
, 0);
1991 address
->offset
= XEXP (x
, 1);
1995 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1996 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1998 if (GET_CODE (x
) == PLUS
1999 && XEXP (x
, 0) == pic_offset_table_rtx
)
2001 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2002 they are invalid in this context. */
2003 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2005 address
->base
= XEXP (x
, 0);
2006 address
->offset
= XEXP (x
, 1);
2011 /* The ColdFire FPU only accepts addressing modes 2-5. */
2012 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2015 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2016 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2017 All these modes are variations of mode 7. */
2018 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2020 address
->offset
= x
;
2024 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2027 ??? do_tablejump creates these addresses before placing the target
2028 label, so we have to assume that unplaced labels are jump table
2029 references. It seems unlikely that we would ever generate indexed
2030 accesses to unplaced labels in other cases. */
2031 if (GET_CODE (x
) == PLUS
2032 && m68k_jump_table_ref_p (XEXP (x
, 1))
2033 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2035 address
->offset
= XEXP (x
, 1);
2039 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2040 (bd,An,Xn.SIZE*SCALE) addresses. */
2044 /* Check for a nonzero base displacement. */
2045 if (GET_CODE (x
) == PLUS
2046 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2048 address
->offset
= XEXP (x
, 1);
2052 /* Check for a suppressed index register. */
2053 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2059 /* Check for a suppressed base register. Do not allow this case
2060 for non-symbolic offsets as it effectively gives gcc freedom
2061 to treat data registers as base registers, which can generate
2064 && symbolic_operand (address
->offset
, VOIDmode
)
2065 && m68k_decompose_index (x
, strict_p
, address
))
2070 /* Check for a nonzero base displacement. */
2071 if (GET_CODE (x
) == PLUS
2072 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2073 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2075 address
->offset
= XEXP (x
, 1);
2080 /* We now expect the sum of a base and an index. */
2081 if (GET_CODE (x
) == PLUS
)
2083 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2084 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2086 address
->base
= XEXP (x
, 0);
2090 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2091 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2093 address
->base
= XEXP (x
, 1);
2100 /* Return true if X is a legitimate address for values of mode MODE.
2101 STRICT_P says whether strict checking is needed. */
2104 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2106 struct m68k_address address
;
2108 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2111 /* Return true if X is a memory, describing its address in ADDRESS if so.
2112 Apply strict checking if called during or after reload. */
2115 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2118 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2119 reload_in_progress
|| reload_completed
,
2123 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2126 m68k_legitimate_constant_p (enum machine_mode mode
, rtx x
)
2128 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2131 /* Return true if X matches the 'Q' constraint. It must be a memory
2132 with a base address and no constant offset or index. */
2135 m68k_matches_q_p (rtx x
)
2137 struct m68k_address address
;
2139 return (m68k_legitimate_mem_p (x
, &address
)
2140 && address
.code
== UNKNOWN
2146 /* Return true if X matches the 'U' constraint. It must be a base address
2147 with a constant offset and no index. */
2150 m68k_matches_u_p (rtx x
)
2152 struct m68k_address address
;
2154 return (m68k_legitimate_mem_p (x
, &address
)
2155 && address
.code
== UNKNOWN
2161 /* Return GOT pointer. */
2166 if (pic_offset_table_rtx
== NULL_RTX
)
2167 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2169 crtl
->uses_pic_offset_table
= 1;
2171 return pic_offset_table_rtx
;
2174 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2176 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2177 RELOC_TLSIE
, RELOC_TLSLE
};
2179 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2181 /* Wrap symbol X into unspec representing relocation RELOC.
2182 BASE_REG - register that should be added to the result.
2183 TEMP_REG - if non-null, temporary register. */
2186 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2190 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2192 if (TARGET_COLDFIRE
&& use_x_p
)
2193 /* When compiling with -mx{got, tls} switch the code will look like this:
2195 move.l <X>@<RELOC>,<TEMP_REG>
2196 add.l <BASE_REG>,<TEMP_REG> */
2198 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2199 to put @RELOC after reference. */
2200 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2202 x
= gen_rtx_CONST (Pmode
, x
);
2204 if (temp_reg
== NULL
)
2206 gcc_assert (can_create_pseudo_p ());
2207 temp_reg
= gen_reg_rtx (Pmode
);
2210 emit_move_insn (temp_reg
, x
);
2211 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2216 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2218 x
= gen_rtx_CONST (Pmode
, x
);
2220 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2226 /* Helper for m68k_unwrap_symbol.
2227 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2228 sets *RELOC_PTR to relocation type for the symbol. */
2231 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2232 enum m68k_reloc
*reloc_ptr
)
2234 if (GET_CODE (orig
) == CONST
)
2237 enum m68k_reloc dummy
;
2241 if (reloc_ptr
== NULL
)
2244 /* Handle an addend. */
2245 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2246 && CONST_INT_P (XEXP (x
, 1)))
2249 if (GET_CODE (x
) == UNSPEC
)
2251 switch (XINT (x
, 1))
2253 case UNSPEC_RELOC16
:
2254 orig
= XVECEXP (x
, 0, 0);
2255 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2258 case UNSPEC_RELOC32
:
2259 if (unwrap_reloc32_p
)
2261 orig
= XVECEXP (x
, 0, 0);
2262 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2275 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2276 UNSPEC_RELOC32 wrappers. */
2279 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2281 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2284 /* Helper for m68k_final_prescan_insn. */
2287 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2291 if (m68k_unwrap_symbol (x
, true) != x
)
2292 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2296 gcc_assert (GET_CODE (x
) == CONST
);
2299 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2304 unspec
= XEXP (plus
, 0);
2305 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2306 addend
= XEXP (plus
, 1);
2307 gcc_assert (CONST_INT_P (addend
));
2309 /* We now have all the pieces, rearrange them. */
2311 /* Move symbol to plus. */
2312 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2314 /* Move plus inside unspec. */
2315 XVECEXP (unspec
, 0, 0) = plus
;
2317 /* Move unspec to top level of const. */
2318 XEXP (x
, 0) = unspec
;
2327 /* Prescan insn before outputing assembler for it. */
2330 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2331 rtx
*operands
, int n_operands
)
2335 /* Combine and, possibly, other optimizations may do good job
2337 (const (unspec [(symbol)]))
2339 (const (plus (unspec [(symbol)])
2341 The problem with this is emitting @TLS or @GOT decorations.
2342 The decoration is emitted when processing (unspec), so the
2343 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2345 It seems that the easiest solution to this is to convert such
2347 (const (unspec [(plus (symbol)
2349 Note, that the top level of operand remains intact, so we don't have
2350 to patch up anything outside of the operand. */
2352 for (i
= 0; i
< n_operands
; ++i
)
2358 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2362 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2363 If REG is non-null, use it; generate new pseudo otherwise. */
2366 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2370 if (reg
== NULL_RTX
)
2372 gcc_assert (can_create_pseudo_p ());
2373 reg
= gen_reg_rtx (Pmode
);
2376 insn
= emit_move_insn (reg
, x
);
2377 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2379 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2384 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2388 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2390 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2392 x
= gen_rtx_MEM (Pmode
, x
);
2393 MEM_READONLY_P (x
) = 1;
2398 /* Legitimize PIC addresses. If the address is already
2399 position-independent, we return ORIG. Newly generated
2400 position-independent addresses go to REG. If we need more
2401 than one register, we lose.
2403 An address is legitimized by making an indirect reference
2404 through the Global Offset Table with the name of the symbol
2407 The assembler and linker are responsible for placing the
2408 address of the symbol in the GOT. The function prologue
2409 is responsible for initializing a5 to the starting address
2412 The assembler is also responsible for translating a symbol name
2413 into a constant displacement from the start of the GOT.
2415 A quick example may make things a little clearer:
2417 When not generating PIC code to store the value 12345 into _foo
2418 we would generate the following code:
2422 When generating PIC two transformations are made. First, the compiler
2423 loads the address of foo into a register. So the first transformation makes:
2428 The code in movsi will intercept the lea instruction and call this
2429 routine which will transform the instructions into:
2431 movel a5@(_foo:w), a0
2435 That (in a nutshell) is how *all* symbol and label references are
2439 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2444 /* First handle a simple SYMBOL_REF or LABEL_REF */
2445 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2449 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2450 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2452 else if (GET_CODE (orig
) == CONST
)
2456 /* Make sure this has not already been legitimized. */
2457 if (m68k_unwrap_symbol (orig
, true) != orig
)
2462 /* legitimize both operands of the PLUS */
2463 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2465 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2466 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2467 base
== reg
? 0 : reg
);
2469 if (GET_CODE (orig
) == CONST_INT
)
2470 pic_ref
= plus_constant (base
, INTVAL (orig
));
2472 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2478 /* The __tls_get_addr symbol. */
2479 static GTY(()) rtx m68k_tls_get_addr
;
2481 /* Return SYMBOL_REF for __tls_get_addr. */
2484 m68k_get_tls_get_addr (void)
2486 if (m68k_tls_get_addr
== NULL_RTX
)
2487 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2489 return m68k_tls_get_addr
;
2492 /* Return libcall result in A0 instead of usual D0. */
2493 static bool m68k_libcall_value_in_a0_p
= false;
2495 /* Emit instruction sequence that calls __tls_get_addr. X is
2496 the TLS symbol we are referencing and RELOC is the symbol type to use
2497 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2498 emitted. A pseudo register with result of __tls_get_addr call is
2502 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2508 /* Emit the call sequence. */
2511 /* FIXME: Unfortunately, emit_library_call_value does not
2512 consider (plus (%a5) (const (unspec))) to be a good enough
2513 operand for push, so it forces it into a register. The bad
2514 thing about this is that combiner, due to copy propagation and other
2515 optimizations, sometimes can not later fix this. As a consequence,
2516 additional register may be allocated resulting in a spill.
2517 For reference, see args processing loops in
2518 calls.c:emit_library_call_value_1.
2519 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2520 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2522 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2523 is the simpliest way of generating a call. The difference between
2524 __tls_get_addr() and libcall is that the result is returned in D0
2525 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2526 which temporarily switches returning the result to A0. */
2528 m68k_libcall_value_in_a0_p
= true;
2529 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2530 Pmode
, 1, x
, Pmode
);
2531 m68k_libcall_value_in_a0_p
= false;
2533 insns
= get_insns ();
2536 gcc_assert (can_create_pseudo_p ());
2537 dest
= gen_reg_rtx (Pmode
);
2538 emit_libcall_block (insns
, dest
, a0
, eqv
);
2543 /* The __tls_get_addr symbol. */
2544 static GTY(()) rtx m68k_read_tp
;
2546 /* Return SYMBOL_REF for __m68k_read_tp. */
2549 m68k_get_m68k_read_tp (void)
2551 if (m68k_read_tp
== NULL_RTX
)
2552 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2554 return m68k_read_tp
;
2557 /* Emit instruction sequence that calls __m68k_read_tp.
2558 A pseudo register with result of __m68k_read_tp call is returned. */
2561 m68k_call_m68k_read_tp (void)
2570 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2571 is the simpliest way of generating a call. The difference between
2572 __m68k_read_tp() and libcall is that the result is returned in D0
2573 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2574 which temporarily switches returning the result to A0. */
2576 /* Emit the call sequence. */
2577 m68k_libcall_value_in_a0_p
= true;
2578 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2580 m68k_libcall_value_in_a0_p
= false;
2581 insns
= get_insns ();
2584 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2585 share the m68k_read_tp result with other IE/LE model accesses. */
2586 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2588 gcc_assert (can_create_pseudo_p ());
2589 dest
= gen_reg_rtx (Pmode
);
2590 emit_libcall_block (insns
, dest
, a0
, eqv
);
2595 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2596 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2600 m68k_legitimize_tls_address (rtx orig
)
2602 switch (SYMBOL_REF_TLS_MODEL (orig
))
2604 case TLS_MODEL_GLOBAL_DYNAMIC
:
2605 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2608 case TLS_MODEL_LOCAL_DYNAMIC
:
2614 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2615 share the LDM result with other LD model accesses. */
2616 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2619 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2621 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2623 if (can_create_pseudo_p ())
2624 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2630 case TLS_MODEL_INITIAL_EXEC
:
2635 a0
= m68k_call_m68k_read_tp ();
2637 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2638 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2640 if (can_create_pseudo_p ())
2641 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2647 case TLS_MODEL_LOCAL_EXEC
:
2652 a0
= m68k_call_m68k_read_tp ();
2654 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2656 if (can_create_pseudo_p ())
2657 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2670 /* Return true if X is a TLS symbol. */
2673 m68k_tls_symbol_p (rtx x
)
2675 if (!TARGET_HAVE_TLS
)
2678 if (GET_CODE (x
) != SYMBOL_REF
)
2681 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2684 /* Helper for m68k_tls_referenced_p. */
2687 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2689 /* Note: this is not the same as m68k_tls_symbol_p. */
2690 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2691 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2693 /* Don't recurse into legitimate TLS references. */
2694 if (m68k_tls_reference_p (*x_ptr
, true))
2700 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2701 though illegitimate one.
2702 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2705 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2707 if (!TARGET_HAVE_TLS
)
2711 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2714 enum m68k_reloc reloc
= RELOC_GOT
;
2716 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2717 && TLS_RELOC_P (reloc
));
2723 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2725 /* Return the type of move that should be used for integer I. */
2728 m68k_const_method (HOST_WIDE_INT i
)
2735 /* The ColdFire doesn't have byte or word operations. */
2736 /* FIXME: This may not be useful for the m68060 either. */
2737 if (!TARGET_COLDFIRE
)
2739 /* if -256 < N < 256 but N is not in range for a moveq
2740 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2741 if (USE_MOVQ (i
^ 0xff))
2743 /* Likewise, try with not.w */
2744 if (USE_MOVQ (i
^ 0xffff))
2746 /* This is the only value where neg.w is useful */
2751 /* Try also with swap. */
2753 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2758 /* Try using MVZ/MVS with an immediate value to load constants. */
2759 if (i
>= 0 && i
<= 65535)
2761 if (i
>= -32768 && i
<= 32767)
2765 /* Otherwise, use move.l */
2769 /* Return the cost of moving constant I into a data register. */
2772 const_int_cost (HOST_WIDE_INT i
)
2774 switch (m68k_const_method (i
))
2777 /* Constants between -128 and 127 are cheap due to moveq. */
2785 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2795 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2796 bool speed ATTRIBUTE_UNUSED
)
2801 /* Constant zero is super cheap due to clr instruction. */
2802 if (x
== const0_rtx
)
2805 *total
= const_int_cost (INTVAL (x
));
2815 /* Make 0.0 cheaper than other floating constants to
2816 encourage creating tstsf and tstdf insns. */
2817 if (outer_code
== COMPARE
2818 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2824 /* These are vaguely right for a 68020. */
2825 /* The costs for long multiply have been adjusted to work properly
2826 in synth_mult on the 68020, relative to an average of the time
2827 for add and the time for shift, taking away a little more because
2828 sometimes move insns are needed. */
2829 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2834 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2835 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2837 : TARGET_COLDFIRE ? 3 : 13)
2842 : TUNE_68000_10 ? 5 \
2843 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2844 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2846 : TARGET_COLDFIRE ? 2 : 8)
2849 (TARGET_CF_HWDIV ? 11 \
2850 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2853 /* An lea costs about three times as much as a simple add. */
2854 if (GET_MODE (x
) == SImode
2855 && GET_CODE (XEXP (x
, 1)) == REG
2856 && GET_CODE (XEXP (x
, 0)) == MULT
2857 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2858 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2859 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2860 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2861 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2863 /* lea an@(dx:l:i),am */
2864 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2874 *total
= COSTS_N_INSNS(1);
2879 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2881 if (INTVAL (XEXP (x
, 1)) < 16)
2882 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2884 /* We're using clrw + swap for these cases. */
2885 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2888 *total
= COSTS_N_INSNS (10); /* Worst case. */
2891 /* A shift by a big integer takes an extra instruction. */
2892 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2893 && (INTVAL (XEXP (x
, 1)) == 16))
2895 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2898 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2899 && !(INTVAL (XEXP (x
, 1)) > 0
2900 && INTVAL (XEXP (x
, 1)) <= 8))
2902 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2908 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2909 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2910 && GET_MODE (x
) == SImode
)
2911 *total
= COSTS_N_INSNS (MULW_COST
);
2912 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2913 *total
= COSTS_N_INSNS (MULW_COST
);
2915 *total
= COSTS_N_INSNS (MULL_COST
);
2922 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2923 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2924 else if (TARGET_CF_HWDIV
)
2925 *total
= COSTS_N_INSNS (18);
2927 *total
= COSTS_N_INSNS (43); /* div.l */
2931 if (outer_code
== COMPARE
)
2940 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2944 output_move_const_into_data_reg (rtx
*operands
)
2948 i
= INTVAL (operands
[1]);
2949 switch (m68k_const_method (i
))
2952 return "mvzw %1,%0";
2954 return "mvsw %1,%0";
2956 return "moveq %1,%0";
2959 operands
[1] = GEN_INT (i
^ 0xff);
2960 return "moveq %1,%0\n\tnot%.b %0";
2963 operands
[1] = GEN_INT (i
^ 0xffff);
2964 return "moveq %1,%0\n\tnot%.w %0";
2967 return "moveq #-128,%0\n\tneg%.w %0";
2972 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2973 return "moveq %1,%0\n\tswap %0";
2976 return "move%.l %1,%0";
2982 /* Return true if I can be handled by ISA B's mov3q instruction. */
2985 valid_mov3q_const (HOST_WIDE_INT i
)
2987 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2990 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2991 I is the value of OPERANDS[1]. */
2994 output_move_simode_const (rtx
*operands
)
3000 src
= INTVAL (operands
[1]);
3002 && (DATA_REG_P (dest
) || MEM_P (dest
))
3003 /* clr insns on 68000 read before writing. */
3004 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3005 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3007 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3008 return "mov3q%.l %1,%0";
3009 else if (src
== 0 && ADDRESS_REG_P (dest
))
3010 return "sub%.l %0,%0";
3011 else if (DATA_REG_P (dest
))
3012 return output_move_const_into_data_reg (operands
);
3013 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3015 if (valid_mov3q_const (src
))
3016 return "mov3q%.l %1,%0";
3017 return "move%.w %1,%0";
3019 else if (MEM_P (dest
)
3020 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3021 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3022 && IN_RANGE (src
, -0x8000, 0x7fff))
3024 if (valid_mov3q_const (src
))
3025 return "mov3q%.l %1,%-";
3028 return "move%.l %1,%0";
3032 output_move_simode (rtx
*operands
)
3034 if (GET_CODE (operands
[1]) == CONST_INT
)
3035 return output_move_simode_const (operands
);
3036 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3037 || GET_CODE (operands
[1]) == CONST
)
3038 && push_operand (operands
[0], SImode
))
3040 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3041 || GET_CODE (operands
[1]) == CONST
)
3042 && ADDRESS_REG_P (operands
[0]))
3043 return "lea %a1,%0";
3044 return "move%.l %1,%0";
3048 output_move_himode (rtx
*operands
)
3050 if (GET_CODE (operands
[1]) == CONST_INT
)
3052 if (operands
[1] == const0_rtx
3053 && (DATA_REG_P (operands
[0])
3054 || GET_CODE (operands
[0]) == MEM
)
3055 /* clr insns on 68000 read before writing. */
3056 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3057 || !(GET_CODE (operands
[0]) == MEM
3058 && MEM_VOLATILE_P (operands
[0]))))
3060 else if (operands
[1] == const0_rtx
3061 && ADDRESS_REG_P (operands
[0]))
3062 return "sub%.l %0,%0";
3063 else if (DATA_REG_P (operands
[0])
3064 && INTVAL (operands
[1]) < 128
3065 && INTVAL (operands
[1]) >= -128)
3066 return "moveq %1,%0";
3067 else if (INTVAL (operands
[1]) < 0x8000
3068 && INTVAL (operands
[1]) >= -0x8000)
3069 return "move%.w %1,%0";
3071 else if (CONSTANT_P (operands
[1]))
3072 return "move%.l %1,%0";
3073 return "move%.w %1,%0";
3077 output_move_qimode (rtx
*operands
)
3079 /* 68k family always modifies the stack pointer by at least 2, even for
3080 byte pushes. The 5200 (ColdFire) does not do this. */
3082 /* This case is generated by pushqi1 pattern now. */
3083 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3084 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3085 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3086 && ! ADDRESS_REG_P (operands
[1])
3087 && ! TARGET_COLDFIRE
));
3089 /* clr and st insns on 68000 read before writing. */
3090 if (!ADDRESS_REG_P (operands
[0])
3091 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3092 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3094 if (operands
[1] == const0_rtx
)
3096 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3097 && GET_CODE (operands
[1]) == CONST_INT
3098 && (INTVAL (operands
[1]) & 255) == 255)
3104 if (GET_CODE (operands
[1]) == CONST_INT
3105 && DATA_REG_P (operands
[0])
3106 && INTVAL (operands
[1]) < 128
3107 && INTVAL (operands
[1]) >= -128)
3108 return "moveq %1,%0";
3109 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3110 return "sub%.l %0,%0";
3111 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3112 return "move%.l %1,%0";
3113 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3114 from address registers. */
3115 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3116 return "move%.w %1,%0";
3117 return "move%.b %1,%0";
3121 output_move_stricthi (rtx
*operands
)
3123 if (operands
[1] == const0_rtx
3124 /* clr insns on 68000 read before writing. */
3125 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3126 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3128 return "move%.w %1,%0";
3132 output_move_strictqi (rtx
*operands
)
3134 if (operands
[1] == const0_rtx
3135 /* clr insns on 68000 read before writing. */
3136 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3137 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3139 return "move%.b %1,%0";
3142 /* Return the best assembler insn template
3143 for moving operands[1] into operands[0] as a fullword. */
3146 singlemove_string (rtx
*operands
)
3148 if (GET_CODE (operands
[1]) == CONST_INT
)
3149 return output_move_simode_const (operands
);
3150 return "move%.l %1,%0";
3154 /* Output assembler or rtl code to perform a doubleword move insn
3155 with operands OPERANDS.
3156 Pointers to 3 helper functions should be specified:
3157 HANDLE_REG_ADJUST to adjust a register by a small value,
3158 HANDLE_COMPADR to compute an address and
3159 HANDLE_MOVSI to move 4 bytes. */
3162 handle_move_double (rtx operands
[2],
3163 void (*handle_reg_adjust
) (rtx
, int),
3164 void (*handle_compadr
) (rtx
[2]),
3165 void (*handle_movsi
) (rtx
[2]))
3169 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3174 rtx addreg0
= 0, addreg1
= 0;
3175 int dest_overlapped_low
= 0;
3176 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3181 /* First classify both operands. */
3183 if (REG_P (operands
[0]))
3185 else if (offsettable_memref_p (operands
[0]))
3187 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3189 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3191 else if (GET_CODE (operands
[0]) == MEM
)
3196 if (REG_P (operands
[1]))
3198 else if (CONSTANT_P (operands
[1]))
3200 else if (offsettable_memref_p (operands
[1]))
3202 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3204 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3206 else if (GET_CODE (operands
[1]) == MEM
)
3211 /* Check for the cases that the operand constraints are not supposed
3212 to allow to happen. Generating code for these cases is
3214 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3216 /* If one operand is decrementing and one is incrementing
3217 decrement the former register explicitly
3218 and change that operand into ordinary indexing. */
3220 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3222 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3224 handle_reg_adjust (operands
[0], -size
);
3226 if (GET_MODE (operands
[1]) == XFmode
)
3227 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3228 else if (GET_MODE (operands
[0]) == DFmode
)
3229 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3231 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3234 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3236 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3238 handle_reg_adjust (operands
[1], -size
);
3240 if (GET_MODE (operands
[1]) == XFmode
)
3241 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3242 else if (GET_MODE (operands
[1]) == DFmode
)
3243 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3245 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3249 /* If an operand is an unoffsettable memory ref, find a register
3250 we can increment temporarily to make it refer to the second word. */
3252 if (optype0
== MEMOP
)
3253 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3255 if (optype1
== MEMOP
)
3256 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3258 /* Ok, we can do one word at a time.
3259 Normally we do the low-numbered word first,
3260 but if either operand is autodecrementing then we
3261 do the high-numbered word first.
3263 In either case, set up in LATEHALF the operands to use
3264 for the high-numbered word and in some cases alter the
3265 operands in OPERANDS to be suitable for the low-numbered word. */
3269 if (optype0
== REGOP
)
3271 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3272 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3274 else if (optype0
== OFFSOP
)
3276 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3277 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3281 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3282 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3285 if (optype1
== REGOP
)
3287 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3288 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3290 else if (optype1
== OFFSOP
)
3292 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3293 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3295 else if (optype1
== CNSTOP
)
3297 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3302 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3303 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3304 operands
[1] = GEN_INT (l
[0]);
3305 middlehalf
[1] = GEN_INT (l
[1]);
3306 latehalf
[1] = GEN_INT (l
[2]);
3310 /* No non-CONST_DOUBLE constant should ever appear
3312 gcc_assert (!CONSTANT_P (operands
[1]));
3317 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3318 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3322 /* size is not 12: */
3324 if (optype0
== REGOP
)
3325 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3326 else if (optype0
== OFFSOP
)
3327 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3329 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3331 if (optype1
== REGOP
)
3332 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3333 else if (optype1
== OFFSOP
)
3334 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3335 else if (optype1
== CNSTOP
)
3336 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3338 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3341 /* If insn is effectively movd N(sp),-(sp) then we will do the
3342 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3343 for the low word as well, to compensate for the first decrement of sp. */
3344 if (optype0
== PUSHOP
3345 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3346 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3347 operands
[1] = middlehalf
[1] = latehalf
[1];
3349 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3350 if the upper part of reg N does not appear in the MEM, arrange to
3351 emit the move late-half first. Otherwise, compute the MEM address
3352 into the upper part of N and use that as a pointer to the memory
3354 if (optype0
== REGOP
3355 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3357 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3359 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3360 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3362 /* If both halves of dest are used in the src memory address,
3363 compute the address into latehalf of dest.
3364 Note that this can't happen if the dest is two data regs. */
3366 xops
[0] = latehalf
[0];
3367 xops
[1] = XEXP (operands
[1], 0);
3369 handle_compadr (xops
);
3370 if (GET_MODE (operands
[1]) == XFmode
)
3372 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3373 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3374 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3378 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3379 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3383 && reg_overlap_mentioned_p (middlehalf
[0],
3384 XEXP (operands
[1], 0)))
3386 /* Check for two regs used by both source and dest.
3387 Note that this can't happen if the dest is all data regs.
3388 It can happen if the dest is d6, d7, a0.
3389 But in that case, latehalf is an addr reg, so
3390 the code at compadr does ok. */
3392 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3393 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3396 /* JRV says this can't happen: */
3397 gcc_assert (!addreg0
&& !addreg1
);
3399 /* Only the middle reg conflicts; simply put it last. */
3400 handle_movsi (operands
);
3401 handle_movsi (latehalf
);
3402 handle_movsi (middlehalf
);
3406 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3407 /* If the low half of dest is mentioned in the source memory
3408 address, the arrange to emit the move late half first. */
3409 dest_overlapped_low
= 1;
3412 /* If one or both operands autodecrementing,
3413 do the two words, high-numbered first. */
3415 /* Likewise, the first move would clobber the source of the second one,
3416 do them in the other order. This happens only for registers;
3417 such overlap can't happen in memory unless the user explicitly
3418 sets it up, and that is an undefined circumstance. */
3420 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3421 || (optype0
== REGOP
&& optype1
== REGOP
3422 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3423 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3424 || dest_overlapped_low
)
3426 /* Make any unoffsettable addresses point at high-numbered word. */
3428 handle_reg_adjust (addreg0
, size
- 4);
3430 handle_reg_adjust (addreg1
, size
- 4);
3433 handle_movsi (latehalf
);
3435 /* Undo the adds we just did. */
3437 handle_reg_adjust (addreg0
, -4);
3439 handle_reg_adjust (addreg1
, -4);
3443 handle_movsi (middlehalf
);
3446 handle_reg_adjust (addreg0
, -4);
3448 handle_reg_adjust (addreg1
, -4);
3451 /* Do low-numbered word. */
3453 handle_movsi (operands
);
3457 /* Normal case: do the two words, low-numbered first. */
3459 m68k_final_prescan_insn (NULL
, operands
, 2);
3460 handle_movsi (operands
);
3462 /* Do the middle one of the three words for long double */
3466 handle_reg_adjust (addreg0
, 4);
3468 handle_reg_adjust (addreg1
, 4);
3470 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3471 handle_movsi (middlehalf
);
3474 /* Make any unoffsettable addresses point at high-numbered word. */
3476 handle_reg_adjust (addreg0
, 4);
3478 handle_reg_adjust (addreg1
, 4);
3481 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3482 handle_movsi (latehalf
);
3484 /* Undo the adds we just did. */
3486 handle_reg_adjust (addreg0
, -(size
- 4));
3488 handle_reg_adjust (addreg1
, -(size
- 4));
3493 /* Output assembler code to adjust REG by N. */
3495 output_reg_adjust (rtx reg
, int n
)
3499 gcc_assert (GET_MODE (reg
) == SImode
3500 && -12 <= n
&& n
!= 0 && n
<= 12);
3505 s
= "add%.l #12,%0";
3509 s
= "addq%.l #8,%0";
3513 s
= "addq%.l #4,%0";
3517 s
= "sub%.l #12,%0";
3521 s
= "subq%.l #8,%0";
3525 s
= "subq%.l #4,%0";
3533 output_asm_insn (s
, ®
);
3536 /* Emit rtl code to adjust REG by N. */
3538 emit_reg_adjust (rtx reg1
, int n
)
3542 gcc_assert (GET_MODE (reg1
) == SImode
3543 && -12 <= n
&& n
!= 0 && n
<= 12);
3545 reg1
= copy_rtx (reg1
);
3546 reg2
= copy_rtx (reg1
);
3549 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3551 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3556 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3558 output_compadr (rtx operands
[2])
3560 output_asm_insn ("lea %a1,%0", operands
);
3563 /* Output the best assembler insn for moving operands[1] into operands[0]
3566 output_movsi (rtx operands
[2])
3568 output_asm_insn (singlemove_string (operands
), operands
);
3571 /* Copy OP and change its mode to MODE. */
3573 copy_operand (rtx op
, enum machine_mode mode
)
3575 /* ??? This looks really ugly. There must be a better way
3576 to change a mode on the operand. */
3577 if (GET_MODE (op
) != VOIDmode
)
3580 op
= gen_rtx_REG (mode
, REGNO (op
));
3584 PUT_MODE (op
, mode
);
3591 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3593 emit_movsi (rtx operands
[2])
3595 operands
[0] = copy_operand (operands
[0], SImode
);
3596 operands
[1] = copy_operand (operands
[1], SImode
);
3598 emit_insn (gen_movsi (operands
[0], operands
[1]));
3601 /* Output assembler code to perform a doubleword move insn
3602 with operands OPERANDS. */
3604 output_move_double (rtx
*operands
)
3606 handle_move_double (operands
,
3607 output_reg_adjust
, output_compadr
, output_movsi
);
3612 /* Output rtl code to perform a doubleword move insn
3613 with operands OPERANDS. */
3615 m68k_emit_move_double (rtx operands
[2])
3617 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3620 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3621 new rtx with the correct mode. */
3624 force_mode (enum machine_mode mode
, rtx orig
)
3626 if (mode
== GET_MODE (orig
))
3629 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3632 return gen_rtx_REG (mode
, REGNO (orig
));
3636 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3638 return reg_renumber
&& FP_REG_P (op
);
3641 /* Emit insns to move operands[1] into operands[0].
3643 Return 1 if we have written out everything that needs to be done to
3644 do the move. Otherwise, return 0 and the caller will emit the move
3647 Note SCRATCH_REG may not be in the proper mode depending on how it
3648 will be used. This routine is responsible for creating a new copy
3649 of SCRATCH_REG in the proper mode. */
3652 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3654 register rtx operand0
= operands
[0];
3655 register rtx operand1
= operands
[1];
3659 && reload_in_progress
&& GET_CODE (operand0
) == REG
3660 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3661 operand0
= reg_equiv_mem (REGNO (operand0
));
3662 else if (scratch_reg
3663 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3664 && GET_CODE (SUBREG_REG (operand0
)) == REG
3665 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3667 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3668 the code which tracks sets/uses for delete_output_reload. */
3669 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3670 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3671 SUBREG_BYTE (operand0
));
3672 operand0
= alter_subreg (&temp
);
3676 && reload_in_progress
&& GET_CODE (operand1
) == REG
3677 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3678 operand1
= reg_equiv_mem (REGNO (operand1
));
3679 else if (scratch_reg
3680 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3681 && GET_CODE (SUBREG_REG (operand1
)) == REG
3682 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3684 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3685 the code which tracks sets/uses for delete_output_reload. */
3686 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3687 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3688 SUBREG_BYTE (operand1
));
3689 operand1
= alter_subreg (&temp
);
3692 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3693 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3694 != XEXP (operand0
, 0)))
3695 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3696 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3697 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3698 != XEXP (operand1
, 0)))
3699 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3701 /* Handle secondary reloads for loads/stores of FP registers where
3702 the address is symbolic by using the scratch register */
3703 if (fp_reg_operand (operand0
, mode
)
3704 && ((GET_CODE (operand1
) == MEM
3705 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3706 || ((GET_CODE (operand1
) == SUBREG
3707 && GET_CODE (XEXP (operand1
, 0)) == MEM
3708 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3711 if (GET_CODE (operand1
) == SUBREG
)
3712 operand1
= XEXP (operand1
, 0);
3714 /* SCRATCH_REG will hold an address. We want
3715 it in SImode regardless of what mode it was originally given
3717 scratch_reg
= force_mode (SImode
, scratch_reg
);
3719 /* D might not fit in 14 bits either; for such cases load D into
3721 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3723 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3724 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3726 XEXP (XEXP (operand1
, 0), 0),
3730 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3731 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3732 gen_rtx_MEM (mode
, scratch_reg
)));
3735 else if (fp_reg_operand (operand1
, mode
)
3736 && ((GET_CODE (operand0
) == MEM
3737 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3738 || ((GET_CODE (operand0
) == SUBREG
)
3739 && GET_CODE (XEXP (operand0
, 0)) == MEM
3740 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3743 if (GET_CODE (operand0
) == SUBREG
)
3744 operand0
= XEXP (operand0
, 0);
3746 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3747 it in SIMODE regardless of what mode it was originally given
3749 scratch_reg
= force_mode (SImode
, scratch_reg
);
3751 /* D might not fit in 14 bits either; for such cases load D into
3753 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3755 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3756 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3759 XEXP (XEXP (operand0
, 0),
3764 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3765 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3769 /* Handle secondary reloads for loads of FP registers from constant
3770 expressions by forcing the constant into memory.
3772 use scratch_reg to hold the address of the memory location.
3774 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3775 NO_REGS when presented with a const_int and an register class
3776 containing only FP registers. Doing so unfortunately creates
3777 more problems than it solves. Fix this for 2.5. */
3778 else if (fp_reg_operand (operand0
, mode
)
3779 && CONSTANT_P (operand1
)
3784 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3785 it in SIMODE regardless of what mode it was originally given
3787 scratch_reg
= force_mode (SImode
, scratch_reg
);
3789 /* Force the constant into memory and put the address of the
3790 memory location into scratch_reg. */
3791 xoperands
[0] = scratch_reg
;
3792 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3793 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3795 /* Now load the destination register. */
3796 emit_insn (gen_rtx_SET (mode
, operand0
,
3797 gen_rtx_MEM (mode
, scratch_reg
)));
3801 /* Now have insn-emit do whatever it normally does. */
3805 /* Split one or more DImode RTL references into pairs of SImode
3806 references. The RTL can be REG, offsettable MEM, integer constant, or
3807 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3808 split and "num" is its length. lo_half and hi_half are output arrays
3809 that parallel "operands". */
3812 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3816 rtx op
= operands
[num
];
3818 /* simplify_subreg refuses to split volatile memory addresses,
3819 but we still have to handle it. */
3820 if (GET_CODE (op
) == MEM
)
3822 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3823 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3827 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3828 GET_MODE (op
) == VOIDmode
3829 ? DImode
: GET_MODE (op
), 4);
3830 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3831 GET_MODE (op
) == VOIDmode
3832 ? DImode
: GET_MODE (op
), 0);
3837 /* Split X into a base and a constant offset, storing them in *BASE
3838 and *OFFSET respectively. */
3841 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3844 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3846 *offset
+= INTVAL (XEXP (x
, 1));
3852 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3853 instruction. STORE_P says whether the move is a load or store.
3855 If the instruction uses post-increment or pre-decrement addressing,
3856 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3857 adjustment. This adjustment will be made by the first element of
3858 PARALLEL, with the loads or stores starting at element 1. If the
3859 instruction does not use post-increment or pre-decrement addressing,
3860 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3861 start at element 0. */
3864 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3865 HOST_WIDE_INT automod_offset
, bool store_p
)
3867 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3868 HOST_WIDE_INT offset
, mem_offset
;
3870 enum reg_class rclass
;
3872 len
= XVECLEN (pattern
, 0);
3873 first
= (automod_base
!= NULL
);
3877 /* Stores must be pre-decrement and loads must be post-increment. */
3878 if (store_p
!= (automod_offset
< 0))
3881 /* Work out the base and offset for lowest memory location. */
3882 base
= automod_base
;
3883 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3887 /* Allow any valid base and offset in the first access. */
3894 for (i
= first
; i
< len
; i
++)
3896 /* We need a plain SET. */
3897 set
= XVECEXP (pattern
, 0, i
);
3898 if (GET_CODE (set
) != SET
)
3901 /* Check that we have a memory location... */
3902 mem
= XEXP (set
, !store_p
);
3903 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3906 /* ...with the right address. */
3909 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3910 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3911 There are no mode restrictions for 680x0 besides the
3912 automodification rules enforced above. */
3914 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3919 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3920 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3924 /* Check that we have a register of the required mode and class. */
3925 reg
= XEXP (set
, store_p
);
3927 || !HARD_REGISTER_P (reg
)
3928 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3933 /* The register must belong to RCLASS and have a higher number
3934 than the register in the previous SET. */
3935 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3936 || REGNO (last_reg
) >= REGNO (reg
))
3941 /* Work out which register class we need. */
3942 if (INT_REGNO_P (REGNO (reg
)))
3943 rclass
= GENERAL_REGS
;
3944 else if (FP_REGNO_P (REGNO (reg
)))
3951 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3954 /* If we have an automodification, check whether the final offset is OK. */
3955 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3958 /* Reject unprofitable cases. */
3959 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3965 /* Return the assembly code template for a movem or fmovem instruction
3966 whose pattern is given by PATTERN. Store the template's operands
3969 If the instruction uses post-increment or pre-decrement addressing,
3970 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3971 is true if this is a store instruction. */
3974 m68k_output_movem (rtx
*operands
, rtx pattern
,
3975 HOST_WIDE_INT automod_offset
, bool store_p
)
3980 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3982 first
= (automod_offset
!= 0);
3983 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3985 /* When using movem with pre-decrement addressing, register X + D0_REG
3986 is controlled by bit 15 - X. For all other addressing modes,
3987 register X + D0_REG is controlled by bit X. Confusingly, the
3988 register mask for fmovem is in the opposite order to that for
3992 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3993 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3994 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3995 if (automod_offset
< 0)
3997 if (FP_REGNO_P (regno
))
3998 mask
|= 1 << (regno
- FP0_REG
);
4000 mask
|= 1 << (15 - (regno
- D0_REG
));
4004 if (FP_REGNO_P (regno
))
4005 mask
|= 1 << (7 - (regno
- FP0_REG
));
4007 mask
|= 1 << (regno
- D0_REG
);
4012 if (automod_offset
== 0)
4013 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4014 else if (automod_offset
< 0)
4015 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4017 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4018 operands
[1] = GEN_INT (mask
);
4019 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4022 return "fmovem %1,%a0";
4024 return "fmovem %a0,%1";
4029 return "movem%.l %1,%a0";
4031 return "movem%.l %a0,%1";
4035 /* Return a REG that occurs in ADDR with coefficient 1.
4036 ADDR can be effectively incremented by incrementing REG. */
4039 find_addr_reg (rtx addr
)
4041 while (GET_CODE (addr
) == PLUS
)
4043 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4044 addr
= XEXP (addr
, 0);
4045 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4046 addr
= XEXP (addr
, 1);
4047 else if (CONSTANT_P (XEXP (addr
, 0)))
4048 addr
= XEXP (addr
, 1);
4049 else if (CONSTANT_P (XEXP (addr
, 1)))
4050 addr
= XEXP (addr
, 0);
4054 gcc_assert (GET_CODE (addr
) == REG
);
4058 /* Output assembler code to perform a 32-bit 3-operand add. */
4061 output_addsi3 (rtx
*operands
)
4063 if (! operands_match_p (operands
[0], operands
[1]))
4065 if (!ADDRESS_REG_P (operands
[1]))
4067 rtx tmp
= operands
[1];
4069 operands
[1] = operands
[2];
4073 /* These insns can result from reloads to access
4074 stack slots over 64k from the frame pointer. */
4075 if (GET_CODE (operands
[2]) == CONST_INT
4076 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4077 return "move%.l %2,%0\n\tadd%.l %1,%0";
4078 if (GET_CODE (operands
[2]) == REG
)
4079 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4080 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4082 if (GET_CODE (operands
[2]) == CONST_INT
)
4084 if (INTVAL (operands
[2]) > 0
4085 && INTVAL (operands
[2]) <= 8)
4086 return "addq%.l %2,%0";
4087 if (INTVAL (operands
[2]) < 0
4088 && INTVAL (operands
[2]) >= -8)
4090 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4091 return "subq%.l %2,%0";
4093 /* On the CPU32 it is faster to use two addql instructions to
4094 add a small integer (8 < N <= 16) to a register.
4095 Likewise for subql. */
4096 if (TUNE_CPU32
&& REG_P (operands
[0]))
4098 if (INTVAL (operands
[2]) > 8
4099 && INTVAL (operands
[2]) <= 16)
4101 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4102 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4104 if (INTVAL (operands
[2]) < -8
4105 && INTVAL (operands
[2]) >= -16)
4107 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4108 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4111 if (ADDRESS_REG_P (operands
[0])
4112 && INTVAL (operands
[2]) >= -0x8000
4113 && INTVAL (operands
[2]) < 0x8000)
4116 return "add%.w %2,%0";
4118 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4121 return "add%.l %2,%0";
4124 /* Store in cc_status the expressions that the condition codes will
4125 describe after execution of an instruction whose pattern is EXP.
4126 Do not alter them if the instruction would not alter the cc's. */
4128 /* On the 68000, all the insns to store in an address register fail to
4129 set the cc's. However, in some cases these instructions can make it
4130 possibly invalid to use the saved cc's. In those cases we clear out
4131 some or all of the saved cc's so they won't be used. */
4134 notice_update_cc (rtx exp
, rtx insn
)
4136 if (GET_CODE (exp
) == SET
)
4138 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4140 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4142 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4143 cc_status
.value1
= 0;
4144 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4145 cc_status
.value2
= 0;
4147 /* fmoves to memory or data registers do not set the condition
4148 codes. Normal moves _do_ set the condition codes, but not in
4149 a way that is appropriate for comparison with 0, because -0.0
4150 would be treated as a negative nonzero number. Note that it
4151 isn't appropriate to conditionalize this restriction on
4152 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4153 we care about the difference between -0.0 and +0.0. */
4154 else if (!FP_REG_P (SET_DEST (exp
))
4155 && SET_DEST (exp
) != cc0_rtx
4156 && (FP_REG_P (SET_SRC (exp
))
4157 || GET_CODE (SET_SRC (exp
)) == FIX
4158 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4160 /* A pair of move insns doesn't produce a useful overall cc. */
4161 else if (!FP_REG_P (SET_DEST (exp
))
4162 && !FP_REG_P (SET_SRC (exp
))
4163 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4164 && (GET_CODE (SET_SRC (exp
)) == REG
4165 || GET_CODE (SET_SRC (exp
)) == MEM
4166 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4168 else if (SET_DEST (exp
) != pc_rtx
)
4170 cc_status
.flags
= 0;
4171 cc_status
.value1
= SET_DEST (exp
);
4172 cc_status
.value2
= SET_SRC (exp
);
4175 else if (GET_CODE (exp
) == PARALLEL
4176 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4178 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4179 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4181 if (ADDRESS_REG_P (dest
))
4183 else if (dest
!= pc_rtx
)
4185 cc_status
.flags
= 0;
4186 cc_status
.value1
= dest
;
4187 cc_status
.value2
= src
;
4192 if (cc_status
.value2
!= 0
4193 && ADDRESS_REG_P (cc_status
.value2
)
4194 && GET_MODE (cc_status
.value2
) == QImode
)
4196 if (cc_status
.value2
!= 0)
4197 switch (GET_CODE (cc_status
.value2
))
4199 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4200 case ROTATE
: case ROTATERT
:
4201 /* These instructions always clear the overflow bit, and set
4202 the carry to the bit shifted out. */
4203 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4206 case PLUS
: case MINUS
: case MULT
:
4207 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4208 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4209 cc_status
.flags
|= CC_NO_OVERFLOW
;
4212 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4213 ends with a move insn moving r2 in r2's mode.
4214 Thus, the cc's are set for r2.
4215 This can set N bit spuriously. */
4216 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4221 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4223 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4224 cc_status
.value2
= 0;
4225 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4226 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4227 cc_status
.flags
= CC_IN_68881
;
4228 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4229 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4231 cc_status
.flags
= CC_IN_68881
;
4232 if (!FP_REG_P (XEXP (cc_status
.value2
, 0)))
4233 cc_status
.flags
|= CC_REVERSED
;
4238 output_move_const_double (rtx
*operands
)
4240 int code
= standard_68881_constant_p (operands
[1]);
4244 static char buf
[40];
4246 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4249 return "fmove%.d %1,%0";
4253 output_move_const_single (rtx
*operands
)
4255 int code
= standard_68881_constant_p (operands
[1]);
4259 static char buf
[40];
4261 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4264 return "fmove%.s %f1,%0";
4267 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4268 from the "fmovecr" instruction.
4269 The value, anded with 0xff, gives the code to use in fmovecr
4270 to get the desired constant. */
4272 /* This code has been fixed for cross-compilation. */
4274 static int inited_68881_table
= 0;
4276 static const char *const strings_68881
[7] = {
4286 static const int codes_68881
[7] = {
4296 REAL_VALUE_TYPE values_68881
[7];
4298 /* Set up values_68881 array by converting the decimal values
4299 strings_68881 to binary. */
4302 init_68881_table (void)
4306 enum machine_mode mode
;
4309 for (i
= 0; i
< 7; i
++)
4313 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4314 values_68881
[i
] = r
;
4316 inited_68881_table
= 1;
4320 standard_68881_constant_p (rtx x
)
4325 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4326 used at all on those chips. */
4330 if (! inited_68881_table
)
4331 init_68881_table ();
4333 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4335 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4337 for (i
= 0; i
< 6; i
++)
4339 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4340 return (codes_68881
[i
]);
4343 if (GET_MODE (x
) == SFmode
)
4346 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4347 return (codes_68881
[6]);
4349 /* larger powers of ten in the constants ram are not used
4350 because they are not equal to a `double' C constant. */
4354 /* If X is a floating-point constant, return the logarithm of X base 2,
4355 or 0 if X is not a power of 2. */
4358 floating_exact_log2 (rtx x
)
4360 REAL_VALUE_TYPE r
, r1
;
4363 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4365 if (REAL_VALUES_LESS (r
, dconst1
))
4368 exp
= real_exponent (&r
);
4369 real_2expN (&r1
, exp
, DFmode
);
4370 if (REAL_VALUES_EQUAL (r1
, r
))
4376 /* A C compound statement to output to stdio stream STREAM the
4377 assembler syntax for an instruction operand X. X is an RTL
4380 CODE is a value that can be used to specify one of several ways
4381 of printing the operand. It is used when identical operands
4382 must be printed differently depending on the context. CODE
4383 comes from the `%' specification that was used to request
4384 printing of the operand. If the specification was just `%DIGIT'
4385 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4386 is the ASCII code for LTR.
4388 If X is a register, this macro should print the register's name.
4389 The names can be found in an array `reg_names' whose type is
4390 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4392 When the machine description has a specification `%PUNCT' (a `%'
4393 followed by a punctuation character), this macro is called with
4394 a null pointer for X and the punctuation character for CODE.
4396 The m68k specific codes are:
4398 '.' for dot needed in Motorola-style opcode names.
4399 '-' for an operand pushing on the stack:
4400 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4401 '+' for an operand pushing on the stack:
4402 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4403 '@' for a reference to the top word on the stack:
4404 sp@, (sp) or (%sp) depending on the style of syntax.
4405 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4406 but & in SGS syntax).
4407 '!' for the cc register (used in an `and to cc' insn).
4408 '$' for the letter `s' in an op code, but only on the 68040.
4409 '&' for the letter `d' in an op code, but only on the 68040.
4410 '/' for register prefix needed by longlong.h.
4411 '?' for m68k_library_id_string
4413 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4414 'd' to force memory addressing to be absolute, not relative.
4415 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4416 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4417 or print pair of registers as rx:ry.
4418 'p' print an address with @PLTPC attached, but only if the operand
4419 is not locally-bound. */
4422 print_operand (FILE *file
, rtx op
, int letter
)
4427 fprintf (file
, ".");
4429 else if (letter
== '#')
4430 asm_fprintf (file
, "%I");
4431 else if (letter
== '-')
4432 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4433 else if (letter
== '+')
4434 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4435 else if (letter
== '@')
4436 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4437 else if (letter
== '!')
4438 asm_fprintf (file
, "%Rfpcr");
4439 else if (letter
== '$')
4442 fprintf (file
, "s");
4444 else if (letter
== '&')
4447 fprintf (file
, "d");
4449 else if (letter
== '/')
4450 asm_fprintf (file
, "%R");
4451 else if (letter
== '?')
4452 asm_fprintf (file
, m68k_library_id_string
);
4453 else if (letter
== 'p')
4455 output_addr_const (file
, op
);
4456 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4457 fprintf (file
, "@PLTPC");
4459 else if (GET_CODE (op
) == REG
)
4462 /* Print out the second register name of a register pair.
4463 I.e., R (6) => 7. */
4464 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4466 fputs (M68K_REGNAME(REGNO (op
)), file
);
4468 else if (GET_CODE (op
) == MEM
)
4470 output_address (XEXP (op
, 0));
4471 if (letter
== 'd' && ! TARGET_68020
4472 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4473 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4474 && INTVAL (XEXP (op
, 0)) < 0x8000
4475 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4476 fprintf (file
, MOTOROLA
? ".l" : ":l");
4478 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4482 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4483 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4484 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4486 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4490 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4491 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4492 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4493 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4495 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4499 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4500 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4501 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4505 /* Use `print_operand_address' instead of `output_addr_const'
4506 to ensure that we print relevant PIC stuff. */
4507 asm_fprintf (file
, "%I");
4509 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4510 print_operand_address (file
, op
);
4512 output_addr_const (file
, op
);
4516 /* Return string for TLS relocation RELOC. */
4519 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4521 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4522 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4529 if (flag_pic
== 1 && TARGET_68020
)
4570 /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */
4573 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4575 if (GET_CODE (x
) == UNSPEC
)
4577 switch (XINT (x
, 1))
4579 case UNSPEC_RELOC16
:
4580 case UNSPEC_RELOC32
:
4581 output_addr_const (file
, XVECEXP (x
, 0, 0));
4582 fputs (m68k_get_reloc_decoration
4583 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4594 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4597 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4599 gcc_assert (size
== 4);
4600 fputs ("\t.long\t", file
);
4601 output_addr_const (file
, x
);
4602 fputs ("@TLSLDO+0x8000", file
);
4605 /* In the name of slightly smaller debug output, and to cater to
4606 general assembler lossage, recognize various UNSPEC sequences
4607 and turn them back into a direct symbol reference. */
4610 m68k_delegitimize_address (rtx orig_x
)
4613 struct m68k_address addr
;
4616 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4621 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4624 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4625 || addr
.offset
== NULL_RTX
4626 || GET_CODE (addr
.offset
) != CONST
)
4629 unspec
= XEXP (addr
.offset
, 0);
4630 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4631 unspec
= XEXP (unspec
, 0);
4632 if (GET_CODE (unspec
) != UNSPEC
4633 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4634 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4636 x
= XVECEXP (unspec
, 0, 0);
4637 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4638 if (unspec
!= XEXP (addr
.offset
, 0))
4639 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4642 rtx idx
= addr
.index
;
4643 if (addr
.scale
!= 1)
4644 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4645 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4648 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4650 x
= replace_equiv_address_nv (orig_x
, x
);
4655 /* A C compound statement to output to stdio stream STREAM the
4656 assembler syntax for an instruction operand that is a memory
4657 reference whose address is ADDR. ADDR is an RTL expression.
4659 Note that this contains a kludge that knows that the only reason
4660 we have an address (plus (label_ref...) (reg...)) when not generating
4661 PIC code is in the insn before a tablejump, and we know that m68k.md
4662 generates a label LInnn: on such an insn.
4664 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4665 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4667 This routine is responsible for distinguishing between -fpic and -fPIC
4668 style relocations in an address. When generating -fpic code the
4669 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4670 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4673 print_operand_address (FILE *file
, rtx addr
)
4675 struct m68k_address address
;
4677 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4680 if (address
.code
== PRE_DEC
)
4681 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4682 M68K_REGNAME (REGNO (address
.base
)));
4683 else if (address
.code
== POST_INC
)
4684 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4685 M68K_REGNAME (REGNO (address
.base
)));
4686 else if (!address
.base
&& !address
.index
)
4688 /* A constant address. */
4689 gcc_assert (address
.offset
== addr
);
4690 if (GET_CODE (addr
) == CONST_INT
)
4692 /* (xxx).w or (xxx).l. */
4693 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4694 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4696 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4698 else if (TARGET_PCREL
)
4700 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4702 output_addr_const (file
, addr
);
4703 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4707 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4708 name ends in `.<letter>', as the last 2 characters can be
4709 mistaken as a size suffix. Put the name in parentheses. */
4710 if (GET_CODE (addr
) == SYMBOL_REF
4711 && strlen (XSTR (addr
, 0)) > 2
4712 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4715 output_addr_const (file
, addr
);
4719 output_addr_const (file
, addr
);
4726 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4727 label being accessed, otherwise it is -1. */
4728 labelno
= (address
.offset
4730 && GET_CODE (address
.offset
) == LABEL_REF
4731 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4735 /* Print the "offset(base" component. */
4737 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4741 output_addr_const (file
, address
.offset
);
4745 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4747 /* Print the ",index" component, if any. */
4752 fprintf (file
, "%s.%c",
4753 M68K_REGNAME (REGNO (address
.index
)),
4754 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4755 if (address
.scale
!= 1)
4756 fprintf (file
, "*%d", address
.scale
);
4760 else /* !MOTOROLA */
4762 if (!address
.offset
&& !address
.index
)
4763 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4766 /* Print the "base@(offset" component. */
4768 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4772 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4773 fprintf (file
, "@(");
4775 output_addr_const (file
, address
.offset
);
4777 /* Print the ",index" component, if any. */
4780 fprintf (file
, ",%s:%c",
4781 M68K_REGNAME (REGNO (address
.index
)),
4782 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4783 if (address
.scale
!= 1)
4784 fprintf (file
, ":%d", address
.scale
);
4792 /* Check for cases where a clr insns can be omitted from code using
4793 strict_low_part sets. For example, the second clrl here is not needed:
4794 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4796 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4797 insn we are checking for redundancy. TARGET is the register set by the
4801 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4806 while ((p
= PREV_INSN (p
)))
4808 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4814 /* If it isn't an insn, then give up. */
4818 if (reg_set_p (target
, p
))
4820 rtx set
= single_set (p
);
4823 /* If it isn't an easy to recognize insn, then give up. */
4827 dest
= SET_DEST (set
);
4829 /* If this sets the entire target register to zero, then our
4830 first_insn is redundant. */
4831 if (rtx_equal_p (dest
, target
)
4832 && SET_SRC (set
) == const0_rtx
)
4834 else if (GET_CODE (dest
) == STRICT_LOW_PART
4835 && GET_CODE (XEXP (dest
, 0)) == REG
4836 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4837 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4838 <= GET_MODE_SIZE (mode
)))
4839 /* This is a strict low part set which modifies less than
4840 we are using, so it is safe. */
4850 /* Operand predicates for implementing asymmetric pc-relative addressing
4851 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4852 when used as a source operand, but not as a destination operand.
4854 We model this by restricting the meaning of the basic predicates
4855 (general_operand, memory_operand, etc) to forbid the use of this
4856 addressing mode, and then define the following predicates that permit
4857 this addressing mode. These predicates can then be used for the
4858 source operands of the appropriate instructions.
4860 n.b. While it is theoretically possible to change all machine patterns
4861 to use this addressing more where permitted by the architecture,
4862 it has only been implemented for "common" cases: SImode, HImode, and
4863 QImode operands, and only for the principle operations that would
4864 require this addressing mode: data movement and simple integer operations.
4866 In parallel with these new predicates, two new constraint letters
4867 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4868 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4869 In the pcrel case 's' is only valid in combination with 'a' registers.
4870 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4871 of how these constraints are used.
4873 The use of these predicates is strictly optional, though patterns that
4874 don't will cause an extra reload register to be allocated where one
4877 lea (abc:w,%pc),%a0 ; need to reload address
4878 moveq &1,%d1 ; since write to pc-relative space
4879 movel %d1,%a0@ ; is not allowed
4881 lea (abc:w,%pc),%a1 ; no need to reload address here
4882 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4884 For more info, consult tiemann@cygnus.com.
4887 All of the ugliness with predicates and constraints is due to the
4888 simple fact that the m68k does not allow a pc-relative addressing
4889 mode as a destination. gcc does not distinguish between source and
4890 destination addresses. Hence, if we claim that pc-relative address
4891 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4892 end up with invalid code. To get around this problem, we left
4893 pc-relative modes as invalid addresses, and then added special
4894 predicates and constraints to accept them.
4896 A cleaner way to handle this is to modify gcc to distinguish
4897 between source and destination addresses. We can then say that
4898 pc-relative is a valid source address but not a valid destination
4899 address, and hopefully avoid a lot of the predicate and constraint
4900 hackery. Unfortunately, this would be a pretty big change. It would
4901 be a useful change for a number of ports, but there aren't any current
4902 plans to undertake this.
4904 ***************************************************************************/
4908 output_andsi3 (rtx
*operands
)
4911 if (GET_CODE (operands
[2]) == CONST_INT
4912 && (INTVAL (operands
[2]) | 0xffff) == -1
4913 && (DATA_REG_P (operands
[0])
4914 || offsettable_memref_p (operands
[0]))
4915 && !TARGET_COLDFIRE
)
4917 if (GET_CODE (operands
[0]) != REG
)
4918 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4919 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4920 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4922 if (operands
[2] == const0_rtx
)
4924 return "and%.w %2,%0";
4926 if (GET_CODE (operands
[2]) == CONST_INT
4927 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4928 && (DATA_REG_P (operands
[0])
4929 || offsettable_memref_p (operands
[0])))
4931 if (DATA_REG_P (operands
[0]))
4932 operands
[1] = GEN_INT (logval
);
4935 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4936 operands
[1] = GEN_INT (logval
% 8);
4938 /* This does not set condition codes in a standard way. */
4940 return "bclr %1,%0";
4942 return "and%.l %2,%0";
4946 output_iorsi3 (rtx
*operands
)
4948 register int logval
;
4949 if (GET_CODE (operands
[2]) == CONST_INT
4950 && INTVAL (operands
[2]) >> 16 == 0
4951 && (DATA_REG_P (operands
[0])
4952 || offsettable_memref_p (operands
[0]))
4953 && !TARGET_COLDFIRE
)
4955 if (GET_CODE (operands
[0]) != REG
)
4956 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4957 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4959 if (INTVAL (operands
[2]) == 0xffff)
4960 return "mov%.w %2,%0";
4961 return "or%.w %2,%0";
4963 if (GET_CODE (operands
[2]) == CONST_INT
4964 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4965 && (DATA_REG_P (operands
[0])
4966 || offsettable_memref_p (operands
[0])))
4968 if (DATA_REG_P (operands
[0]))
4969 operands
[1] = GEN_INT (logval
);
4972 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4973 operands
[1] = GEN_INT (logval
% 8);
4976 return "bset %1,%0";
4978 return "or%.l %2,%0";
4982 output_xorsi3 (rtx
*operands
)
4984 register int logval
;
4985 if (GET_CODE (operands
[2]) == CONST_INT
4986 && INTVAL (operands
[2]) >> 16 == 0
4987 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4988 && !TARGET_COLDFIRE
)
4990 if (! DATA_REG_P (operands
[0]))
4991 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4992 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4994 if (INTVAL (operands
[2]) == 0xffff)
4996 return "eor%.w %2,%0";
4998 if (GET_CODE (operands
[2]) == CONST_INT
4999 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5000 && (DATA_REG_P (operands
[0])
5001 || offsettable_memref_p (operands
[0])))
5003 if (DATA_REG_P (operands
[0]))
5004 operands
[1] = GEN_INT (logval
);
5007 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5008 operands
[1] = GEN_INT (logval
% 8);
5011 return "bchg %1,%0";
5013 return "eor%.l %2,%0";
5016 /* Return the instruction that should be used for a call to address X,
5017 which is known to be in operand 0. */
5022 if (symbolic_operand (x
, VOIDmode
))
5023 return m68k_symbolic_call
;
5028 /* Likewise sibling calls. */
5031 output_sibcall (rtx x
)
5033 if (symbolic_operand (x
, VOIDmode
))
5034 return m68k_symbolic_jump
;
5040 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5041 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5044 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5046 /* Avoid clobbering the struct value reg by using the
5047 static chain reg as a temporary. */
5048 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5050 /* Pretend to be a post-reload pass while generating rtl. */
5051 reload_completed
= 1;
5053 /* The "this" pointer is stored at 4(%sp). */
5054 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
5056 /* Add DELTA to THIS. */
5059 /* Make the offset a legitimate operand for memory addition. */
5060 offset
= GEN_INT (delta
);
5061 if ((delta
< -8 || delta
> 8)
5062 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5064 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5065 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5067 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5068 copy_rtx (this_slot
), offset
));
5071 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5072 if (vcall_offset
!= 0)
5074 /* Set the static chain register to *THIS. */
5075 emit_move_insn (tmp
, this_slot
);
5076 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5078 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5079 addr
= plus_constant (tmp
, vcall_offset
);
5080 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5082 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5086 /* Load the offset into %d0 and add it to THIS. */
5087 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5088 gen_rtx_MEM (Pmode
, addr
));
5089 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5090 copy_rtx (this_slot
),
5091 gen_rtx_REG (Pmode
, D0_REG
)));
5094 /* Jump to the target function. Use a sibcall if direct jumps are
5095 allowed, otherwise load the address into a register first. */
5096 mem
= DECL_RTL (function
);
5097 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5099 gcc_assert (flag_pic
);
5101 if (!TARGET_SEP_DATA
)
5103 /* Use the static chain register as a temporary (call-clobbered)
5104 GOT pointer for this function. We can use the static chain
5105 register because it isn't live on entry to the thunk. */
5106 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5107 emit_insn (gen_load_got (pic_offset_table_rtx
));
5109 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5110 mem
= replace_equiv_address (mem
, tmp
);
5112 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5113 SIBLING_CALL_P (insn
) = 1;
5115 /* Run just enough of rest_of_compilation. */
5116 insn
= get_insns ();
5117 split_all_insns_noflow ();
5118 final_start_function (insn
, file
, 1);
5119 final (insn
, file
, 1);
5120 final_end_function ();
5122 /* Clean up the vars set above. */
5123 reload_completed
= 0;
5125 /* Restore the original PIC register. */
5127 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5130 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5133 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5134 int incoming ATTRIBUTE_UNUSED
)
5136 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5139 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5141 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5142 unsigned int new_reg
)
5145 /* Interrupt functions can only use registers that have already been
5146 saved by the prologue, even if they would normally be
5149 if ((m68k_get_function_kind (current_function_decl
)
5150 == m68k_fk_interrupt_handler
)
5151 && !df_regs_ever_live_p (new_reg
))
5157 /* Value is true if hard register REGNO can hold a value of machine-mode
5158 MODE. On the 68000, we let the cpu registers can hold any mode, but
5159 restrict the 68881 registers to floating-point modes. */
5162 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5164 if (DATA_REGNO_P (regno
))
5166 /* Data Registers, can hold aggregate if fits in. */
5167 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5170 else if (ADDRESS_REGNO_P (regno
))
5172 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5175 else if (FP_REGNO_P (regno
))
5177 /* FPU registers, hold float or complex float of long double or
5179 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5180 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5181 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5187 /* Implement SECONDARY_RELOAD_CLASS. */
5190 m68k_secondary_reload_class (enum reg_class rclass
,
5191 enum machine_mode mode
, rtx x
)
5195 regno
= true_regnum (x
);
5197 /* If one operand of a movqi is an address register, the other
5198 operand must be a general register or constant. Other types
5199 of operand must be reloaded through a data register. */
5200 if (GET_MODE_SIZE (mode
) == 1
5201 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5202 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5205 /* PC-relative addresses must be loaded into an address register first. */
5207 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5208 && symbolic_operand (x
, VOIDmode
))
5214 /* Implement PREFERRED_RELOAD_CLASS. */
5217 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5219 enum reg_class secondary_class
;
5221 /* If RCLASS might need a secondary reload, try restricting it to
5222 a class that doesn't. */
5223 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5224 if (secondary_class
!= NO_REGS
5225 && reg_class_subset_p (secondary_class
, rclass
))
5226 return secondary_class
;
5228 /* Prefer to use moveq for in-range constants. */
5229 if (GET_CODE (x
) == CONST_INT
5230 && reg_class_subset_p (DATA_REGS
, rclass
)
5231 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5234 /* ??? Do we really need this now? */
5235 if (GET_CODE (x
) == CONST_DOUBLE
5236 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5238 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5247 /* Return floating point values in a 68881 register. This makes 68881 code
5248 a little bit faster. It also makes -msoft-float code incompatible with
5249 hard-float code, so people have to be careful not to mix the two.
5250 For ColdFire it was decided the ABI incompatibility is undesirable.
5251 If there is need for a hard-float ABI it is probably worth doing it
5252 properly and also passing function arguments in FP registers. */
5254 m68k_libcall_value (enum machine_mode mode
)
5261 return gen_rtx_REG (mode
, FP0_REG
);
5267 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5270 /* Location in which function value is returned.
5271 NOTE: Due to differences in ABIs, don't call this function directly,
5272 use FUNCTION_VALUE instead. */
5274 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5276 enum machine_mode mode
;
5278 mode
= TYPE_MODE (valtype
);
5284 return gen_rtx_REG (mode
, FP0_REG
);
5290 /* If the function returns a pointer, push that into %a0. */
5291 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5292 /* For compatibility with the large body of existing code which
5293 does not always properly declare external functions returning
5294 pointer types, the m68k/SVR4 convention is to copy the value
5295 returned for pointer functions from a0 to d0 in the function
5296 epilogue, so that callers that have neglected to properly
5297 declare the callee can still find the correct return value in
5299 return gen_rtx_PARALLEL
5302 gen_rtx_EXPR_LIST (VOIDmode
,
5303 gen_rtx_REG (mode
, A0_REG
),
5305 gen_rtx_EXPR_LIST (VOIDmode
,
5306 gen_rtx_REG (mode
, D0_REG
),
5308 else if (POINTER_TYPE_P (valtype
))
5309 return gen_rtx_REG (mode
, A0_REG
);
5311 return gen_rtx_REG (mode
, D0_REG
);
5314 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5315 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5317 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5319 enum machine_mode mode
= TYPE_MODE (type
);
5321 if (mode
== BLKmode
)
5324 /* If TYPE's known alignment is less than the alignment of MODE that
5325 would contain the structure, then return in memory. We need to
5326 do so to maintain the compatibility between code compiled with
5327 -mstrict-align and that compiled with -mno-strict-align. */
5328 if (AGGREGATE_TYPE_P (type
)
5329 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5336 /* CPU to schedule the program for. */
5337 enum attr_cpu m68k_sched_cpu
;
5339 /* MAC to schedule the program for. */
5340 enum attr_mac m68k_sched_mac
;
5348 /* Integer register. */
5354 /* Implicit mem reference (e.g. stack). */
5357 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5360 /* Memory with offset but without indexing. EA mode 5. */
5363 /* Memory with indexing. EA mode 6. */
5366 /* Memory referenced by absolute address. EA mode 7. */
5369 /* Immediate operand that doesn't require extension word. */
5372 /* Immediate 16 bit operand. */
5375 /* Immediate 32 bit operand. */
5379 /* Return type of memory ADDR_RTX refers to. */
5380 static enum attr_op_type
5381 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5383 struct m68k_address address
;
5385 if (symbolic_operand (addr_rtx
, VOIDmode
))
5386 return OP_TYPE_MEM7
;
5388 if (!m68k_decompose_address (mode
, addr_rtx
,
5389 reload_completed
, &address
))
5391 gcc_assert (!reload_completed
);
5392 /* Reload will likely fix the address to be in the register. */
5393 return OP_TYPE_MEM234
;
5396 if (address
.scale
!= 0)
5397 return OP_TYPE_MEM6
;
5399 if (address
.base
!= NULL_RTX
)
5401 if (address
.offset
== NULL_RTX
)
5402 return OP_TYPE_MEM234
;
5404 return OP_TYPE_MEM5
;
5407 gcc_assert (address
.offset
!= NULL_RTX
);
5409 return OP_TYPE_MEM7
;
5412 /* Return X or Y (depending on OPX_P) operand of INSN. */
5414 sched_get_operand (rtx insn
, bool opx_p
)
5418 if (recog_memoized (insn
) < 0)
5421 extract_constrain_insn_cached (insn
);
5424 i
= get_attr_opx (insn
);
5426 i
= get_attr_opy (insn
);
5428 if (i
>= recog_data
.n_operands
)
5431 return recog_data
.operand
[i
];
5434 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5435 If ADDRESS_P is true, return type of memory location operand refers to. */
5436 static enum attr_op_type
5437 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5441 op
= sched_get_operand (insn
, opx_p
);
5445 gcc_assert (!reload_completed
);
5450 return sched_address_type (QImode
, op
);
5452 if (memory_operand (op
, VOIDmode
))
5453 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5455 if (register_operand (op
, VOIDmode
))
5457 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5458 || (reload_completed
&& FP_REG_P (op
)))
5464 if (GET_CODE (op
) == CONST_INT
)
5470 /* Check for quick constants. */
5471 switch (get_attr_type (insn
))
5474 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5475 return OP_TYPE_IMM_Q
;
5477 gcc_assert (!reload_completed
);
5481 if (USE_MOVQ (ival
))
5482 return OP_TYPE_IMM_Q
;
5484 gcc_assert (!reload_completed
);
5488 if (valid_mov3q_const (ival
))
5489 return OP_TYPE_IMM_Q
;
5491 gcc_assert (!reload_completed
);
5498 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5499 return OP_TYPE_IMM_W
;
5501 return OP_TYPE_IMM_L
;
5504 if (GET_CODE (op
) == CONST_DOUBLE
)
5506 switch (GET_MODE (op
))
5509 return OP_TYPE_IMM_W
;
5513 return OP_TYPE_IMM_L
;
5520 if (GET_CODE (op
) == CONST
5521 || symbolic_operand (op
, VOIDmode
)
5524 switch (GET_MODE (op
))
5527 return OP_TYPE_IMM_Q
;
5530 return OP_TYPE_IMM_W
;
5533 return OP_TYPE_IMM_L
;
5536 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5538 return OP_TYPE_IMM_W
;
5540 return OP_TYPE_IMM_L
;
5544 gcc_assert (!reload_completed
);
5546 if (FLOAT_MODE_P (GET_MODE (op
)))
5552 /* Implement opx_type attribute.
5553 Return type of INSN's operand X.
5554 If ADDRESS_P is true, return type of memory location operand refers to. */
5556 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5558 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5564 return OPX_TYPE_FPN
;
5567 return OPX_TYPE_MEM1
;
5569 case OP_TYPE_MEM234
:
5570 return OPX_TYPE_MEM234
;
5573 return OPX_TYPE_MEM5
;
5576 return OPX_TYPE_MEM6
;
5579 return OPX_TYPE_MEM7
;
5582 return OPX_TYPE_IMM_Q
;
5585 return OPX_TYPE_IMM_W
;
5588 return OPX_TYPE_IMM_L
;
5595 /* Implement opy_type attribute.
5596 Return type of INSN's operand Y.
5597 If ADDRESS_P is true, return type of memory location operand refers to. */
5599 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5601 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5607 return OPY_TYPE_FPN
;
5610 return OPY_TYPE_MEM1
;
5612 case OP_TYPE_MEM234
:
5613 return OPY_TYPE_MEM234
;
5616 return OPY_TYPE_MEM5
;
5619 return OPY_TYPE_MEM6
;
5622 return OPY_TYPE_MEM7
;
5625 return OPY_TYPE_IMM_Q
;
5628 return OPY_TYPE_IMM_W
;
5631 return OPY_TYPE_IMM_L
;
5638 /* Return size of INSN as int. */
5640 sched_get_attr_size_int (rtx insn
)
5644 switch (get_attr_type (insn
))
5647 /* There should be no references to m68k_sched_attr_size for 'ignore'
5661 switch (get_attr_opx_type (insn
))
5667 case OPX_TYPE_MEM234
:
5668 case OPY_TYPE_IMM_Q
:
5673 /* Here we assume that most absolute references are short. */
5675 case OPY_TYPE_IMM_W
:
5679 case OPY_TYPE_IMM_L
:
5687 switch (get_attr_opy_type (insn
))
5693 case OPY_TYPE_MEM234
:
5694 case OPY_TYPE_IMM_Q
:
5699 /* Here we assume that most absolute references are short. */
5701 case OPY_TYPE_IMM_W
:
5705 case OPY_TYPE_IMM_L
:
5715 gcc_assert (!reload_completed
);
5723 /* Return size of INSN as attribute enum value. */
5725 m68k_sched_attr_size (rtx insn
)
5727 switch (sched_get_attr_size_int (insn
))
5743 /* Return operand X or Y (depending on OPX_P) of INSN,
5744 if it is a MEM, or NULL overwise. */
5745 static enum attr_op_type
5746 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5750 switch (get_attr_opx_type (insn
))
5755 case OPX_TYPE_IMM_Q
:
5756 case OPX_TYPE_IMM_W
:
5757 case OPX_TYPE_IMM_L
:
5761 case OPX_TYPE_MEM234
:
5764 return OP_TYPE_MEM1
;
5767 return OP_TYPE_MEM6
;
5775 switch (get_attr_opy_type (insn
))
5780 case OPY_TYPE_IMM_Q
:
5781 case OPY_TYPE_IMM_W
:
5782 case OPY_TYPE_IMM_L
:
5786 case OPY_TYPE_MEM234
:
5789 return OP_TYPE_MEM1
;
5792 return OP_TYPE_MEM6
;
5800 /* Implement op_mem attribute. */
5802 m68k_sched_attr_op_mem (rtx insn
)
5804 enum attr_op_type opx
;
5805 enum attr_op_type opy
;
5807 opx
= sched_get_opxy_mem_type (insn
, true);
5808 opy
= sched_get_opxy_mem_type (insn
, false);
5810 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5813 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5815 switch (get_attr_opx_access (insn
))
5831 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5833 switch (get_attr_opx_access (insn
))
5849 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5852 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5854 switch (get_attr_opx_access (insn
))
5860 gcc_assert (!reload_completed
);
5865 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5867 switch (get_attr_opx_access (insn
))
5873 gcc_assert (!reload_completed
);
5878 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5881 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5883 switch (get_attr_opx_access (insn
))
5889 gcc_assert (!reload_completed
);
5894 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5895 gcc_assert (!reload_completed
);
5899 /* Jump instructions types. Indexed by INSN_UID.
5900 The same rtl insn can be expanded into different asm instructions
5901 depending on the cc0_status. To properly determine type of jump
5902 instructions we scan instruction stream and map jumps types to this
5904 static enum attr_type
*sched_branch_type
;
5906 /* Return the type of the jump insn. */
5908 m68k_sched_branch_type (rtx insn
)
5910 enum attr_type type
;
5912 type
= sched_branch_type
[INSN_UID (insn
)];
5914 gcc_assert (type
!= 0);
5919 /* Data for ColdFire V4 index bypass.
5920 Producer modifies register that is used as index in consumer with
5924 /* Producer instruction. */
5927 /* Consumer instruction. */
5930 /* Scale of indexed memory access within consumer.
5931 Or zero if bypass should not be effective at the moment. */
5933 } sched_cfv4_bypass_data
;
5935 /* An empty state that is used in m68k_sched_adjust_cost. */
5936 static state_t sched_adjust_cost_state
;
5938 /* Implement adjust_cost scheduler hook.
5939 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5941 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5946 if (recog_memoized (def_insn
) < 0
5947 || recog_memoized (insn
) < 0)
5950 if (sched_cfv4_bypass_data
.scale
== 1)
5951 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5953 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5954 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5955 that the data in sched_cfv4_bypass_data is up to date. */
5956 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5957 && sched_cfv4_bypass_data
.con
== insn
);
5962 sched_cfv4_bypass_data
.pro
= NULL
;
5963 sched_cfv4_bypass_data
.con
= NULL
;
5964 sched_cfv4_bypass_data
.scale
= 0;
5967 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5968 && sched_cfv4_bypass_data
.con
== NULL
5969 && sched_cfv4_bypass_data
.scale
== 0);
5971 /* Don't try to issue INSN earlier than DFA permits.
5972 This is especially useful for instructions that write to memory,
5973 as their true dependence (default) latency is better to be set to 0
5974 to workaround alias analysis limitations.
5975 This is, in fact, a machine independent tweak, so, probably,
5976 it should be moved to haifa-sched.c: insn_cost (). */
5977 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5984 /* Return maximal number of insns that can be scheduled on a single cycle. */
5986 m68k_sched_issue_rate (void)
5988 switch (m68k_sched_cpu
)
6004 /* Maximal length of instruction for current CPU.
6005 E.g. it is 3 for any ColdFire core. */
6006 static int max_insn_size
;
6008 /* Data to model instruction buffer of CPU. */
6011 /* True if instruction buffer model is modeled for current CPU. */
6014 /* Size of the instruction buffer in words. */
6017 /* Number of filled words in the instruction buffer. */
6020 /* Additional information about instruction buffer for CPUs that have
6021 a buffer of instruction records, rather then a plain buffer
6022 of instruction words. */
6023 struct _sched_ib_records
6025 /* Size of buffer in records. */
6028 /* Array to hold data on adjustements made to the size of the buffer. */
6031 /* Index of the above array. */
6035 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6039 static struct _sched_ib sched_ib
;
6041 /* ID of memory unit. */
6042 static int sched_mem_unit_code
;
6044 /* Implementation of the targetm.sched.variable_issue () hook.
6045 It is called after INSN was issued. It returns the number of insns
6046 that can possibly get scheduled on the current cycle.
6047 It is used here to determine the effect of INSN on the instruction
6050 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6051 int sched_verbose ATTRIBUTE_UNUSED
,
6052 rtx insn
, int can_issue_more
)
6056 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6058 switch (m68k_sched_cpu
)
6062 insn_size
= sched_get_attr_size_int (insn
);
6066 insn_size
= sched_get_attr_size_int (insn
);
6068 /* ColdFire V3 and V4 cores have instruction buffers that can
6069 accumulate up to 8 instructions regardless of instructions'
6070 sizes. So we should take care not to "prefetch" 24 one-word
6071 or 12 two-words instructions.
6072 To model this behavior we temporarily decrease size of the
6073 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6077 adjust
= max_insn_size
- insn_size
;
6078 sched_ib
.size
-= adjust
;
6080 if (sched_ib
.filled
> sched_ib
.size
)
6081 sched_ib
.filled
= sched_ib
.size
;
6083 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6086 ++sched_ib
.records
.adjust_index
;
6087 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6088 sched_ib
.records
.adjust_index
= 0;
6090 /* Undo adjustement we did 7 instructions ago. */
6092 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6097 gcc_assert (!sched_ib
.enabled_p
);
6105 if (insn_size
> sched_ib
.filled
)
6106 /* Scheduling for register pressure does not always take DFA into
6107 account. Workaround instruction buffer not being filled enough. */
6109 gcc_assert (sched_pressure_p
);
6110 insn_size
= sched_ib
.filled
;
6115 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6116 || asm_noperands (PATTERN (insn
)) >= 0)
6117 insn_size
= sched_ib
.filled
;
6121 sched_ib
.filled
-= insn_size
;
6123 return can_issue_more
;
6126 /* Return how many instructions should scheduler lookahead to choose the
6129 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6131 return m68k_sched_issue_rate () - 1;
6134 /* Implementation of targetm.sched.init_global () hook.
6135 It is invoked once per scheduling pass and is used here
6136 to initialize scheduler constants. */
6138 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6139 int sched_verbose ATTRIBUTE_UNUSED
,
6140 int n_insns ATTRIBUTE_UNUSED
)
6142 /* Init branch types. */
6146 sched_branch_type
= XCNEWVEC (enum attr_type
, get_max_uid () + 1);
6148 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6151 /* !!! FIXME: Implement real scan here. */
6152 sched_branch_type
[INSN_UID (insn
)] = TYPE_BCC
;
6156 #ifdef ENABLE_CHECKING
6157 /* Check that all instructions have DFA reservations and
6158 that all instructions can be issued from a clean state. */
6163 state
= alloca (state_size ());
6165 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6167 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6169 gcc_assert (insn_has_dfa_reservation_p (insn
));
6171 state_reset (state
);
6172 if (state_transition (state
, insn
) >= 0)
6179 /* Setup target cpu. */
6181 /* ColdFire V4 has a set of features to keep its instruction buffer full
6182 (e.g., a separate memory bus for instructions) and, hence, we do not model
6183 buffer for this CPU. */
6184 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6186 switch (m68k_sched_cpu
)
6189 sched_ib
.filled
= 0;
6196 sched_ib
.records
.n_insns
= 0;
6197 sched_ib
.records
.adjust
= NULL
;
6202 sched_ib
.records
.n_insns
= 8;
6203 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6210 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6212 sched_adjust_cost_state
= xmalloc (state_size ());
6213 state_reset (sched_adjust_cost_state
);
6216 emit_insn (gen_ib ());
6217 sched_ib
.insn
= get_insns ();
6221 /* Scheduling pass is now finished. Free/reset static variables. */
6223 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6224 int verbose ATTRIBUTE_UNUSED
)
6226 sched_ib
.insn
= NULL
;
6228 free (sched_adjust_cost_state
);
6229 sched_adjust_cost_state
= NULL
;
6231 sched_mem_unit_code
= 0;
6233 free (sched_ib
.records
.adjust
);
6234 sched_ib
.records
.adjust
= NULL
;
6235 sched_ib
.records
.n_insns
= 0;
6238 free (sched_branch_type
);
6239 sched_branch_type
= NULL
;
6242 /* Implementation of targetm.sched.init () hook.
6243 It is invoked each time scheduler starts on the new block (basic block or
6244 extended basic block). */
6246 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6247 int sched_verbose ATTRIBUTE_UNUSED
,
6248 int n_insns ATTRIBUTE_UNUSED
)
6250 switch (m68k_sched_cpu
)
6258 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6260 memset (sched_ib
.records
.adjust
, 0,
6261 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6262 sched_ib
.records
.adjust_index
= 0;
6266 gcc_assert (!sched_ib
.enabled_p
);
6274 if (sched_ib
.enabled_p
)
6275 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6276 the first cycle. Workaround that. */
6277 sched_ib
.filled
= -2;
6280 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6281 It is invoked just before current cycle finishes and is used here
6282 to track if instruction buffer got its two words this cycle. */
6284 m68k_sched_dfa_pre_advance_cycle (void)
6286 if (!sched_ib
.enabled_p
)
6289 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6291 sched_ib
.filled
+= 2;
6293 if (sched_ib
.filled
> sched_ib
.size
)
6294 sched_ib
.filled
= sched_ib
.size
;
6298 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6299 It is invoked just after new cycle begins and is used here
6300 to setup number of filled words in the instruction buffer so that
6301 instructions which won't have all their words prefetched would be
6302 stalled for a cycle. */
6304 m68k_sched_dfa_post_advance_cycle (void)
6308 if (!sched_ib
.enabled_p
)
6311 /* Setup number of prefetched instruction words in the instruction
6313 i
= max_insn_size
- sched_ib
.filled
;
6317 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6322 /* Return X or Y (depending on OPX_P) operand of INSN,
6323 if it is an integer register, or NULL overwise. */
6325 sched_get_reg_operand (rtx insn
, bool opx_p
)
6331 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6333 op
= sched_get_operand (insn
, true);
6334 gcc_assert (op
!= NULL
);
6336 if (!reload_completed
&& !REG_P (op
))
6342 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6344 op
= sched_get_operand (insn
, false);
6345 gcc_assert (op
!= NULL
);
6347 if (!reload_completed
&& !REG_P (op
))
6355 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6358 sched_mem_operand_p (rtx insn
, bool opx_p
)
6360 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6371 /* Return X or Y (depending on OPX_P) operand of INSN,
6372 if it is a MEM, or NULL overwise. */
6374 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6394 if (opy_p
&& sched_mem_operand_p (insn
, false))
6395 return sched_get_operand (insn
, false);
6397 if (opx_p
&& sched_mem_operand_p (insn
, true))
6398 return sched_get_operand (insn
, true);
6404 /* Return non-zero if PRO modifies register used as part of
6407 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6412 pro_x
= sched_get_reg_operand (pro
, true);
6416 con_mem_read
= sched_get_mem_operand (con
, true, false);
6417 gcc_assert (con_mem_read
!= NULL
);
6419 if (reg_mentioned_p (pro_x
, con_mem_read
))
6425 /* Helper function for m68k_sched_indexed_address_bypass_p.
6426 if PRO modifies register used as index in CON,
6427 return scale of indexed memory access in CON. Return zero overwise. */
6429 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6433 struct m68k_address address
;
6435 reg
= sched_get_reg_operand (pro
, true);
6439 mem
= sched_get_mem_operand (con
, true, false);
6440 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6442 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6446 if (REGNO (reg
) == REGNO (address
.index
))
6448 gcc_assert (address
.scale
!= 0);
6449 return address
.scale
;
6455 /* Return non-zero if PRO modifies register used
6456 as index with scale 2 or 4 in CON. */
6458 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6460 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6461 && sched_cfv4_bypass_data
.con
== NULL
6462 && sched_cfv4_bypass_data
.scale
== 0);
6464 switch (sched_get_indexed_address_scale (pro
, con
))
6467 /* We can't have a variable latency bypass, so
6468 remember to adjust the insn cost in adjust_cost hook. */
6469 sched_cfv4_bypass_data
.pro
= pro
;
6470 sched_cfv4_bypass_data
.con
= con
;
6471 sched_cfv4_bypass_data
.scale
= 1;
6483 /* We generate a two-instructions program at M_TRAMP :
6484 movea.l &CHAIN_VALUE,%a0
6486 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6489 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6491 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6494 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6496 mem
= adjust_address (m_tramp
, HImode
, 0);
6497 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6498 mem
= adjust_address (m_tramp
, SImode
, 2);
6499 emit_move_insn (mem
, chain_value
);
6501 mem
= adjust_address (m_tramp
, HImode
, 6);
6502 emit_move_insn (mem
, GEN_INT(0x4EF9));
6503 mem
= adjust_address (m_tramp
, SImode
, 8);
6504 emit_move_insn (mem
, fnaddr
);
6506 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6509 /* On the 68000, the RTS insn cannot pop anything.
6510 On the 68010, the RTD insn may be used to pop them if the number
6511 of args is fixed, but if the number is variable then the caller
6512 must pop them all. RTD can't be used for library calls now
6513 because the library is compiled with the Unix compiler.
6514 Use of RTD is a selectable option, since it is incompatible with
6515 standard Unix calling sequences. If the option is not selected,
6516 the caller must always pop the args. */
6519 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6523 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6524 && (!stdarg_p (funtype
)))
6528 /* Make sure everything's fine if we *don't* have a given processor.
6529 This assumes that putting a register in fixed_regs will keep the
6530 compiler's mitts completely off it. We don't bother to zero it out
6531 of register classes. */
6534 m68k_conditional_register_usage (void)
6538 if (!TARGET_HARD_FLOAT
)
6540 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6541 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6542 if (TEST_HARD_REG_BIT (x
, i
))
6543 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6546 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6549 #include "gt-m68k.h"