1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
29 #include "fold-const.h"
31 #include "stor-layout.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
39 #include "diagnostic-core.h"
55 #include "cfgcleanup.h"
56 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
57 #include "sched-int.h"
58 #include "insn-codes.h"
64 /* This file should be included last. */
65 #include "target-def.h"
67 enum reg_class regno_reg_class
[] =
69 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
70 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
71 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
72 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
73 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
74 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
79 /* The minimum number of integer registers that we want to save with the
80 movem instruction. Using two movel instructions instead of a single
81 moveml is about 15% faster for the 68020 and 68030 at no expense in
83 #define MIN_MOVEM_REGS 3
85 /* The minimum number of floating point registers that we want to save
86 with the fmovem instruction. */
87 #define MIN_FMOVEM_REGS 1
89 /* Structure describing stack frame layout. */
92 /* Stack pointer to frame pointer offset. */
95 /* Offset of FPU registers. */
96 HOST_WIDE_INT foffset
;
98 /* Frame size in bytes (rounded up). */
101 /* Data and address register. */
103 unsigned int reg_mask
;
107 unsigned int fpu_mask
;
109 /* Offsets relative to ARG_POINTER. */
110 HOST_WIDE_INT frame_pointer_offset
;
111 HOST_WIDE_INT stack_pointer_offset
;
113 /* Function which the above information refers to. */
117 /* Current frame information calculated by m68k_compute_frame_layout(). */
118 static struct m68k_frame current_frame
;
120 /* Structure describing an m68k address.
122 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
123 with null fields evaluating to 0. Here:
125 - BASE satisfies m68k_legitimate_base_reg_p
126 - INDEX satisfies m68k_legitimate_index_reg_p
127 - OFFSET satisfies m68k_legitimate_constant_address_p
129 INDEX is either HImode or SImode. The other fields are SImode.
131 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
132 the address is (BASE)+. */
133 struct m68k_address
{
141 static int m68k_sched_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
142 static int m68k_sched_issue_rate (void);
143 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
144 static void m68k_sched_md_init_global (FILE *, int, int);
145 static void m68k_sched_md_finish_global (FILE *, int);
146 static void m68k_sched_md_init (FILE *, int, int);
147 static void m68k_sched_dfa_pre_advance_cycle (void);
148 static void m68k_sched_dfa_post_advance_cycle (void);
149 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
151 static bool m68k_can_eliminate (const int, const int);
152 static void m68k_conditional_register_usage (void);
153 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
154 static void m68k_option_override (void);
155 static void m68k_override_options_after_change (void);
156 static rtx
find_addr_reg (rtx
);
157 static const char *singlemove_string (rtx
*);
158 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
159 HOST_WIDE_INT
, tree
);
160 static rtx
m68k_struct_value_rtx (tree
, int);
161 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
162 tree args
, int flags
,
164 static void m68k_compute_frame_layout (void);
165 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
166 static bool m68k_ok_for_sibcall_p (tree
, tree
);
167 static bool m68k_tls_symbol_p (rtx
);
168 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
169 static bool m68k_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
170 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
171 static bool m68k_return_in_memory (const_tree
, const_tree
);
173 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
174 static void m68k_trampoline_init (rtx
, tree
, rtx
);
175 static int m68k_return_pops_args (tree
, tree
, int);
176 static rtx
m68k_delegitimize_address (rtx
);
177 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
179 static rtx
m68k_function_arg (cumulative_args_t
, machine_mode
,
181 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
182 static bool m68k_output_addr_const_extra (FILE *, rtx
);
183 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
185 /* Initialize the GCC target structure. */
187 #if INT_OP_GROUP == INT_OP_DOT_WORD
188 #undef TARGET_ASM_ALIGNED_HI_OP
189 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
192 #if INT_OP_GROUP == INT_OP_NO_DOT
193 #undef TARGET_ASM_BYTE_OP
194 #define TARGET_ASM_BYTE_OP "\tbyte\t"
195 #undef TARGET_ASM_ALIGNED_HI_OP
196 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
197 #undef TARGET_ASM_ALIGNED_SI_OP
198 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
201 #if INT_OP_GROUP == INT_OP_DC
202 #undef TARGET_ASM_BYTE_OP
203 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
204 #undef TARGET_ASM_ALIGNED_HI_OP
205 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
206 #undef TARGET_ASM_ALIGNED_SI_OP
207 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
210 #undef TARGET_ASM_UNALIGNED_HI_OP
211 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
212 #undef TARGET_ASM_UNALIGNED_SI_OP
213 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
215 #undef TARGET_ASM_OUTPUT_MI_THUNK
216 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
217 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
218 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
220 #undef TARGET_ASM_FILE_START_APP_OFF
221 #define TARGET_ASM_FILE_START_APP_OFF true
223 #undef TARGET_LEGITIMIZE_ADDRESS
224 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
226 #undef TARGET_SCHED_ADJUST_COST
227 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
229 #undef TARGET_SCHED_ISSUE_RATE
230 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
232 #undef TARGET_SCHED_VARIABLE_ISSUE
233 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
235 #undef TARGET_SCHED_INIT_GLOBAL
236 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
238 #undef TARGET_SCHED_FINISH_GLOBAL
239 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
241 #undef TARGET_SCHED_INIT
242 #define TARGET_SCHED_INIT m68k_sched_md_init
244 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
245 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
247 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
248 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
250 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
251 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
252 m68k_sched_first_cycle_multipass_dfa_lookahead
254 #undef TARGET_OPTION_OVERRIDE
255 #define TARGET_OPTION_OVERRIDE m68k_option_override
257 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
258 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
260 #undef TARGET_RTX_COSTS
261 #define TARGET_RTX_COSTS m68k_rtx_costs
263 #undef TARGET_ATTRIBUTE_TABLE
264 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
266 #undef TARGET_PROMOTE_PROTOTYPES
267 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
269 #undef TARGET_STRUCT_VALUE_RTX
270 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
272 #undef TARGET_CANNOT_FORCE_CONST_MEM
273 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
275 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
276 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
278 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
279 #undef TARGET_RETURN_IN_MEMORY
280 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
284 #undef TARGET_HAVE_TLS
285 #define TARGET_HAVE_TLS (true)
287 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
288 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
291 #undef TARGET_LEGITIMATE_ADDRESS_P
292 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
294 #undef TARGET_CAN_ELIMINATE
295 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
297 #undef TARGET_CONDITIONAL_REGISTER_USAGE
298 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
300 #undef TARGET_TRAMPOLINE_INIT
301 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
303 #undef TARGET_RETURN_POPS_ARGS
304 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
306 #undef TARGET_DELEGITIMIZE_ADDRESS
307 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
309 #undef TARGET_FUNCTION_ARG
310 #define TARGET_FUNCTION_ARG m68k_function_arg
312 #undef TARGET_FUNCTION_ARG_ADVANCE
313 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
315 #undef TARGET_LEGITIMATE_CONSTANT_P
316 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
318 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
319 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
321 /* The value stored by TAS. */
322 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
323 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
325 static const struct attribute_spec m68k_attribute_table
[] =
327 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
328 affects_type_identity } */
329 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
331 { "interrupt_handler", 0, 0, true, false, false,
332 m68k_handle_fndecl_attribute
, false },
333 { "interrupt_thread", 0, 0, true, false, false,
334 m68k_handle_fndecl_attribute
, false },
335 { NULL
, 0, 0, false, false, false, NULL
, false }
338 struct gcc_target targetm
= TARGET_INITIALIZER
;
340 /* Base flags for 68k ISAs. */
341 #define FL_FOR_isa_00 FL_ISA_68000
342 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
343 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
344 generated 68881 code for 68020 and 68030 targets unless explicitly told
346 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
347 | FL_BITFIELD | FL_68881 | FL_CAS)
348 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
349 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
351 /* Base flags for ColdFire ISAs. */
352 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
353 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
354 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
355 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
356 /* ISA_C is not upwardly compatible with ISA_B. */
357 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
361 /* Traditional 68000 instruction sets. */
367 /* ColdFire instruction set variants. */
375 /* Information about one of the -march, -mcpu or -mtune arguments. */
376 struct m68k_target_selection
378 /* The argument being described. */
381 /* For -mcpu, this is the device selected by the option.
382 For -mtune and -march, it is a representative device
383 for the microarchitecture or ISA respectively. */
384 enum target_device device
;
386 /* The M68K_DEVICE fields associated with DEVICE. See the comment
387 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
389 enum uarch_type microarch
;
394 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
395 static const struct m68k_target_selection all_devices
[] =
397 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
398 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
399 #include "m68k-devices.def"
401 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
404 /* A list of all ISAs, mapping each one to a representative device.
405 Used for -march selection. */
406 static const struct m68k_target_selection all_isas
[] =
408 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
409 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
410 #include "m68k-isas.def"
412 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
415 /* A list of all microarchitectures, mapping each one to a representative
416 device. Used for -mtune selection. */
417 static const struct m68k_target_selection all_microarchs
[] =
419 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
420 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
421 #include "m68k-microarchs.def"
422 #undef M68K_MICROARCH
423 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
426 /* The entries associated with the -mcpu, -march and -mtune settings,
427 or null for options that have not been used. */
428 const struct m68k_target_selection
*m68k_cpu_entry
;
429 const struct m68k_target_selection
*m68k_arch_entry
;
430 const struct m68k_target_selection
*m68k_tune_entry
;
432 /* Which CPU we are generating code for. */
433 enum target_device m68k_cpu
;
435 /* Which microarchitecture to tune for. */
436 enum uarch_type m68k_tune
;
438 /* Which FPU to use. */
439 enum fpu_type m68k_fpu
;
441 /* The set of FL_* flags that apply to the target processor. */
442 unsigned int m68k_cpu_flags
;
444 /* The set of FL_* flags that apply to the processor to be tuned for. */
445 unsigned int m68k_tune_flags
;
447 /* Asm templates for calling or jumping to an arbitrary symbolic address,
448 or NULL if such calls or jumps are not supported. The address is held
450 const char *m68k_symbolic_call
;
451 const char *m68k_symbolic_jump
;
453 /* Enum variable that corresponds to m68k_symbolic_call values. */
454 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
457 /* Implement TARGET_OPTION_OVERRIDE. */
460 m68k_option_override (void)
462 const struct m68k_target_selection
*entry
;
463 unsigned long target_mask
;
465 if (global_options_set
.x_m68k_arch_option
)
466 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
468 if (global_options_set
.x_m68k_cpu_option
)
469 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
471 if (global_options_set
.x_m68k_tune_option
)
472 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
480 -march=ARCH should generate code that runs any processor
481 implementing architecture ARCH. -mcpu=CPU should override -march
482 and should generate code that runs on processor CPU, making free
483 use of any instructions that CPU understands. -mtune=UARCH applies
484 on top of -mcpu or -march and optimizes the code for UARCH. It does
485 not change the target architecture. */
488 /* Complain if the -march setting is for a different microarchitecture,
489 or includes flags that the -mcpu setting doesn't. */
491 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
492 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
493 warning (0, "-mcpu=%s conflicts with -march=%s",
494 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
496 entry
= m68k_cpu_entry
;
499 entry
= m68k_arch_entry
;
502 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
504 m68k_cpu_flags
= entry
->flags
;
506 /* Use the architecture setting to derive default values for
510 /* ColdFire is lenient about alignment. */
511 if (!TARGET_COLDFIRE
)
512 target_mask
|= MASK_STRICT_ALIGNMENT
;
514 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
515 target_mask
|= MASK_BITFIELD
;
516 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
517 target_mask
|= MASK_CF_HWDIV
;
518 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
519 target_mask
|= MASK_HARD_FLOAT
;
520 target_flags
|= target_mask
& ~target_flags_explicit
;
522 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
523 m68k_cpu
= entry
->device
;
526 m68k_tune
= m68k_tune_entry
->microarch
;
527 m68k_tune_flags
= m68k_tune_entry
->flags
;
529 #ifdef M68K_DEFAULT_TUNE
530 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
532 enum target_device dev
;
533 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
534 m68k_tune_flags
= all_devices
[dev
].flags
;
539 m68k_tune
= entry
->microarch
;
540 m68k_tune_flags
= entry
->flags
;
543 /* Set the type of FPU. */
544 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
545 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
548 /* Sanity check to ensure that msep-data and mid-sahred-library are not
549 * both specified together. Doing so simply doesn't make sense.
551 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
552 error ("cannot specify both -msep-data and -mid-shared-library");
554 /* If we're generating code for a separate A5 relative data segment,
555 * we've got to enable -fPIC as well. This might be relaxable to
556 * -fpic but it hasn't been tested properly.
558 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
561 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
562 error if the target does not support them. */
563 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
564 error ("-mpcrel -fPIC is not currently supported on selected cpu");
566 /* ??? A historic way of turning on pic, or is this intended to
567 be an embedded thing that doesn't have the same name binding
568 significance that it does on hosted ELF systems? */
569 if (TARGET_PCREL
&& flag_pic
== 0)
574 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
576 m68k_symbolic_jump
= "jra %a0";
578 else if (TARGET_ID_SHARED_LIBRARY
)
579 /* All addresses must be loaded from the GOT. */
581 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
584 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
586 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
589 /* No unconditional long branch */;
590 else if (TARGET_PCREL
)
591 m68k_symbolic_jump
= "bra%.l %c0";
593 m68k_symbolic_jump
= "bra%.l %p0";
594 /* Turn off function cse if we are doing PIC. We always want
595 function call to be done as `bsr foo@PLTPC'. */
596 /* ??? It's traditional to do this for -mpcrel too, but it isn't
597 clear how intentional that is. */
598 flag_no_function_cse
= 1;
601 switch (m68k_symbolic_call_var
)
603 case M68K_SYMBOLIC_CALL_JSR
:
604 m68k_symbolic_call
= "jsr %a0";
607 case M68K_SYMBOLIC_CALL_BSR_C
:
608 m68k_symbolic_call
= "bsr%.l %c0";
611 case M68K_SYMBOLIC_CALL_BSR_P
:
612 m68k_symbolic_call
= "bsr%.l %p0";
615 case M68K_SYMBOLIC_CALL_NONE
:
616 gcc_assert (m68k_symbolic_call
== NULL
);
623 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
624 if (align_labels
> 2)
626 warning (0, "-falign-labels=%d is not supported", align_labels
);
631 warning (0, "-falign-loops=%d is not supported", align_loops
);
636 if (stack_limit_rtx
!= NULL_RTX
&& !TARGET_68020
)
638 warning (0, "-fstack-limit- options are not supported on this cpu");
639 stack_limit_rtx
= NULL_RTX
;
642 SUBTARGET_OVERRIDE_OPTIONS
;
644 /* Setup scheduling options. */
646 m68k_sched_cpu
= CPU_CFV1
;
648 m68k_sched_cpu
= CPU_CFV2
;
650 m68k_sched_cpu
= CPU_CFV3
;
652 m68k_sched_cpu
= CPU_CFV4
;
655 m68k_sched_cpu
= CPU_UNKNOWN
;
656 flag_schedule_insns
= 0;
657 flag_schedule_insns_after_reload
= 0;
658 flag_modulo_sched
= 0;
659 flag_live_range_shrinkage
= 0;
662 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
664 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
665 m68k_sched_mac
= MAC_CF_EMAC
;
666 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
667 m68k_sched_mac
= MAC_CF_MAC
;
669 m68k_sched_mac
= MAC_NO
;
673 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
676 m68k_override_options_after_change (void)
678 if (m68k_sched_cpu
== CPU_UNKNOWN
)
680 flag_schedule_insns
= 0;
681 flag_schedule_insns_after_reload
= 0;
682 flag_modulo_sched
= 0;
683 flag_live_range_shrinkage
= 0;
687 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
688 given argument and NAME is the argument passed to -mcpu. Return NULL
689 if -mcpu was not passed. */
692 m68k_cpp_cpu_ident (const char *prefix
)
696 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
699 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
700 given argument and NAME is the name of the representative device for
701 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
704 m68k_cpp_cpu_family (const char *prefix
)
708 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
711 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
712 "interrupt_handler" attribute and interrupt_thread if FUNC has an
713 "interrupt_thread" attribute. Otherwise, return
714 m68k_fk_normal_function. */
716 enum m68k_function_kind
717 m68k_get_function_kind (tree func
)
721 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
723 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
725 return m68k_fk_interrupt_handler
;
727 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
729 return m68k_fk_interrupt_handler
;
731 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
733 return m68k_fk_interrupt_thread
;
735 return m68k_fk_normal_function
;
738 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
739 struct attribute_spec.handler. */
741 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
742 tree args ATTRIBUTE_UNUSED
,
743 int flags ATTRIBUTE_UNUSED
,
746 if (TREE_CODE (*node
) != FUNCTION_DECL
)
748 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
750 *no_add_attrs
= true;
753 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
755 error ("multiple interrupt attributes not allowed");
756 *no_add_attrs
= true;
760 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
762 error ("interrupt_thread is available only on fido");
763 *no_add_attrs
= true;
770 m68k_compute_frame_layout (void)
774 enum m68k_function_kind func_kind
=
775 m68k_get_function_kind (current_function_decl
);
776 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
777 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
779 /* Only compute the frame once per function.
780 Don't cache information until reload has been completed. */
781 if (current_frame
.funcdef_no
== current_function_funcdef_no
785 current_frame
.size
= (get_frame_size () + 3) & -4;
789 /* Interrupt thread does not need to save any register. */
790 if (!interrupt_thread
)
791 for (regno
= 0; regno
< 16; regno
++)
792 if (m68k_save_reg (regno
, interrupt_handler
))
794 mask
|= 1 << (regno
- D0_REG
);
797 current_frame
.offset
= saved
* 4;
798 current_frame
.reg_no
= saved
;
799 current_frame
.reg_mask
= mask
;
801 current_frame
.foffset
= 0;
803 if (TARGET_HARD_FLOAT
)
805 /* Interrupt thread does not need to save any register. */
806 if (!interrupt_thread
)
807 for (regno
= 16; regno
< 24; regno
++)
808 if (m68k_save_reg (regno
, interrupt_handler
))
810 mask
|= 1 << (regno
- FP0_REG
);
813 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
814 current_frame
.offset
+= current_frame
.foffset
;
816 current_frame
.fpu_no
= saved
;
817 current_frame
.fpu_mask
= mask
;
819 /* Remember what function this frame refers to. */
820 current_frame
.funcdef_no
= current_function_funcdef_no
;
823 /* Worker function for TARGET_CAN_ELIMINATE. */
826 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
828 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
832 m68k_initial_elimination_offset (int from
, int to
)
835 /* The arg pointer points 8 bytes before the start of the arguments,
836 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
837 frame pointer in most frames. */
838 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
839 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
840 return argptr_offset
;
842 m68k_compute_frame_layout ();
844 gcc_assert (to
== STACK_POINTER_REGNUM
);
847 case ARG_POINTER_REGNUM
:
848 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
849 case FRAME_POINTER_REGNUM
:
850 return current_frame
.offset
+ current_frame
.size
;
856 /* Refer to the array `regs_ever_live' to determine which registers
857 to save; `regs_ever_live[I]' is nonzero if register number I
858 is ever used in the function. This function is responsible for
859 knowing which registers should not be saved even if used.
860 Return true if we need to save REGNO. */
863 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
865 if (flag_pic
&& regno
== PIC_REG
)
867 if (crtl
->saves_all_registers
)
869 if (crtl
->uses_pic_offset_table
)
871 /* Reload may introduce constant pool references into a function
872 that thitherto didn't need a PIC register. Note that the test
873 above will not catch that case because we will only set
874 crtl->uses_pic_offset_table when emitting
875 the address reloads. */
876 if (crtl
->uses_const_pool
)
880 if (crtl
->calls_eh_return
)
885 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
886 if (test
== INVALID_REGNUM
)
893 /* Fixed regs we never touch. */
894 if (fixed_regs
[regno
])
897 /* The frame pointer (if it is such) is handled specially. */
898 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
901 /* Interrupt handlers must also save call_used_regs
902 if they are live or when calling nested functions. */
903 if (interrupt_handler
)
905 if (df_regs_ever_live_p (regno
))
908 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
912 /* Never need to save registers that aren't touched. */
913 if (!df_regs_ever_live_p (regno
))
916 /* Otherwise save everything that isn't call-clobbered. */
917 return !call_used_regs
[regno
];
920 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
921 the lowest memory address. COUNT is the number of registers to be
922 moved, with register REGNO + I being moved if bit I of MASK is set.
923 STORE_P specifies the direction of the move and ADJUST_STACK_P says
924 whether or not this is pre-decrement (if STORE_P) or post-increment
925 (if !STORE_P) operation. */
928 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
929 unsigned int count
, unsigned int regno
,
930 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
933 rtx body
, addr
, src
, operands
[2];
936 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
937 mode
= reg_raw_mode
[regno
];
942 src
= plus_constant (Pmode
, base
,
944 * GET_MODE_SIZE (mode
)
945 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
946 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
949 for (; mask
!= 0; mask
>>= 1, regno
++)
952 addr
= plus_constant (Pmode
, base
, offset
);
953 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
954 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
955 XVECEXP (body
, 0, i
++)
956 = gen_rtx_SET (operands
[0], operands
[1]);
957 offset
+= GET_MODE_SIZE (mode
);
959 gcc_assert (i
== XVECLEN (body
, 0));
961 return emit_insn (body
);
964 /* Make INSN a frame-related instruction. */
967 m68k_set_frame_related (rtx_insn
*insn
)
972 RTX_FRAME_RELATED_P (insn
) = 1;
973 body
= PATTERN (insn
);
974 if (GET_CODE (body
) == PARALLEL
)
975 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
976 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
979 /* Emit RTL for the "prologue" define_expand. */
982 m68k_expand_prologue (void)
984 HOST_WIDE_INT fsize_with_regs
;
985 rtx limit
, src
, dest
;
987 m68k_compute_frame_layout ();
989 if (flag_stack_usage_info
)
990 current_function_static_stack_size
991 = current_frame
.size
+ current_frame
.offset
;
993 /* If the stack limit is a symbol, we can check it here,
994 before actually allocating the space. */
995 if (crtl
->limit_stack
996 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
998 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
999 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1001 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1002 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1004 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1005 stack_pointer_rtx
, limit
),
1006 stack_pointer_rtx
, limit
,
1010 fsize_with_regs
= current_frame
.size
;
1011 if (TARGET_COLDFIRE
)
1013 /* ColdFire's move multiple instructions do not allow pre-decrement
1014 addressing. Add the size of movem saves to the initial stack
1015 allocation instead. */
1016 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1017 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1018 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1019 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1022 if (frame_pointer_needed
)
1024 if (fsize_with_regs
== 0 && TUNE_68040
)
1026 /* On the 68040, two separate moves are faster than link.w 0. */
1027 dest
= gen_frame_mem (Pmode
,
1028 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1029 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1030 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1031 stack_pointer_rtx
));
1033 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1034 m68k_set_frame_related
1035 (emit_insn (gen_link (frame_pointer_rtx
,
1036 GEN_INT (-4 - fsize_with_regs
))));
1039 m68k_set_frame_related
1040 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1041 m68k_set_frame_related
1042 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1044 GEN_INT (-fsize_with_regs
))));
1047 /* If the frame pointer is needed, emit a special barrier that
1048 will prevent the scheduler from moving stores to the frame
1049 before the stack adjustment. */
1050 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1052 else if (fsize_with_regs
!= 0)
1053 m68k_set_frame_related
1054 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1056 GEN_INT (-fsize_with_regs
))));
1058 if (current_frame
.fpu_mask
)
1060 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1062 m68k_set_frame_related
1063 (m68k_emit_movem (stack_pointer_rtx
,
1064 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1065 current_frame
.fpu_no
, FP0_REG
,
1066 current_frame
.fpu_mask
, true, true));
1071 /* If we're using moveml to save the integer registers,
1072 the stack pointer will point to the bottom of the moveml
1073 save area. Find the stack offset of the first FP register. */
1074 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1077 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1078 m68k_set_frame_related
1079 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1080 current_frame
.fpu_no
, FP0_REG
,
1081 current_frame
.fpu_mask
, true, false));
1085 /* If the stack limit is not a symbol, check it here.
1086 This has the disadvantage that it may be too late... */
1087 if (crtl
->limit_stack
)
1089 if (REG_P (stack_limit_rtx
))
1090 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1092 stack_pointer_rtx
, stack_limit_rtx
,
1095 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1096 warning (0, "stack limit expression is not supported");
1099 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1101 /* Store each register separately in the same order moveml does. */
1104 for (i
= 16; i
-- > 0; )
1105 if (current_frame
.reg_mask
& (1 << i
))
1107 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1108 dest
= gen_frame_mem (SImode
,
1109 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1110 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1115 if (TARGET_COLDFIRE
)
1116 /* The required register save space has already been allocated.
1117 The first register should be stored at (%sp). */
1118 m68k_set_frame_related
1119 (m68k_emit_movem (stack_pointer_rtx
, 0,
1120 current_frame
.reg_no
, D0_REG
,
1121 current_frame
.reg_mask
, true, false));
1123 m68k_set_frame_related
1124 (m68k_emit_movem (stack_pointer_rtx
,
1125 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1126 current_frame
.reg_no
, D0_REG
,
1127 current_frame
.reg_mask
, true, true));
1130 if (!TARGET_SEP_DATA
1131 && crtl
->uses_pic_offset_table
)
1132 emit_insn (gen_load_got (pic_offset_table_rtx
));
1135 /* Return true if a simple (return) instruction is sufficient for this
1136 instruction (i.e. if no epilogue is needed). */
1139 m68k_use_return_insn (void)
1141 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1144 m68k_compute_frame_layout ();
1145 return current_frame
.offset
== 0;
1148 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1149 SIBCALL_P says which.
1151 The function epilogue should not depend on the current stack pointer!
1152 It should use the frame pointer only, if there is a frame pointer.
1153 This is mandatory because of alloca; we also take advantage of it to
1154 omit stack adjustments before returning. */
1157 m68k_expand_epilogue (bool sibcall_p
)
1159 HOST_WIDE_INT fsize
, fsize_with_regs
;
1160 bool big
, restore_from_sp
;
1162 m68k_compute_frame_layout ();
1164 fsize
= current_frame
.size
;
1166 restore_from_sp
= false;
1168 /* FIXME : crtl->is_leaf below is too strong.
1169 What we really need to know there is if there could be pending
1170 stack adjustment needed at that point. */
1171 restore_from_sp
= (!frame_pointer_needed
1172 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1174 /* fsize_with_regs is the size we need to adjust the sp when
1175 popping the frame. */
1176 fsize_with_regs
= fsize
;
1177 if (TARGET_COLDFIRE
&& restore_from_sp
)
1179 /* ColdFire's move multiple instructions do not allow post-increment
1180 addressing. Add the size of movem loads to the final deallocation
1182 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1183 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1184 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1185 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1188 if (current_frame
.offset
+ fsize
>= 0x8000
1190 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1193 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1194 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1196 /* ColdFire's move multiple instructions do not support the
1197 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1198 stack-based restore. */
1199 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1200 GEN_INT (-(current_frame
.offset
+ fsize
)));
1201 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1202 gen_rtx_REG (Pmode
, A1_REG
),
1203 frame_pointer_rtx
));
1204 restore_from_sp
= true;
1208 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1214 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1216 /* Restore each register separately in the same order moveml does. */
1218 HOST_WIDE_INT offset
;
1220 offset
= current_frame
.offset
+ fsize
;
1221 for (i
= 0; i
< 16; i
++)
1222 if (current_frame
.reg_mask
& (1 << i
))
1228 /* Generate the address -OFFSET(%fp,%a1.l). */
1229 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1230 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1231 addr
= plus_constant (Pmode
, addr
, -offset
);
1233 else if (restore_from_sp
)
1234 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1236 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1237 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1238 gen_frame_mem (SImode
, addr
));
1239 offset
-= GET_MODE_SIZE (SImode
);
1242 else if (current_frame
.reg_mask
)
1245 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1246 gen_rtx_REG (Pmode
, A1_REG
),
1248 -(current_frame
.offset
+ fsize
),
1249 current_frame
.reg_no
, D0_REG
,
1250 current_frame
.reg_mask
, false, false);
1251 else if (restore_from_sp
)
1252 m68k_emit_movem (stack_pointer_rtx
, 0,
1253 current_frame
.reg_no
, D0_REG
,
1254 current_frame
.reg_mask
, false,
1257 m68k_emit_movem (frame_pointer_rtx
,
1258 -(current_frame
.offset
+ fsize
),
1259 current_frame
.reg_no
, D0_REG
,
1260 current_frame
.reg_mask
, false, false);
1263 if (current_frame
.fpu_no
> 0)
1266 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1267 gen_rtx_REG (Pmode
, A1_REG
),
1269 -(current_frame
.foffset
+ fsize
),
1270 current_frame
.fpu_no
, FP0_REG
,
1271 current_frame
.fpu_mask
, false, false);
1272 else if (restore_from_sp
)
1274 if (TARGET_COLDFIRE
)
1278 /* If we used moveml to restore the integer registers, the
1279 stack pointer will still point to the bottom of the moveml
1280 save area. Find the stack offset of the first FP
1282 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1285 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1286 m68k_emit_movem (stack_pointer_rtx
, offset
,
1287 current_frame
.fpu_no
, FP0_REG
,
1288 current_frame
.fpu_mask
, false, false);
1291 m68k_emit_movem (stack_pointer_rtx
, 0,
1292 current_frame
.fpu_no
, FP0_REG
,
1293 current_frame
.fpu_mask
, false, true);
1296 m68k_emit_movem (frame_pointer_rtx
,
1297 -(current_frame
.foffset
+ fsize
),
1298 current_frame
.fpu_no
, FP0_REG
,
1299 current_frame
.fpu_mask
, false, false);
1302 if (frame_pointer_needed
)
1303 emit_insn (gen_unlink (frame_pointer_rtx
));
1304 else if (fsize_with_regs
)
1305 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1307 GEN_INT (fsize_with_regs
)));
1309 if (crtl
->calls_eh_return
)
1310 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1312 EH_RETURN_STACKADJ_RTX
));
1315 emit_jump_insn (ret_rtx
);
1318 /* Return true if X is a valid comparison operator for the dbcc
1321 Note it rejects floating point comparison operators.
1322 (In the future we could use Fdbcc).
1324 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1327 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1329 switch (GET_CODE (x
))
1331 case EQ
: case NE
: case GTU
: case LTU
:
1335 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1337 case GT
: case LT
: case GE
: case LE
:
1338 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1344 /* Return nonzero if flags are currently in the 68881 flag register. */
1346 flags_in_68881 (void)
1348 /* We could add support for these in the future */
1349 return cc_status
.flags
& CC_IN_68881
;
1352 /* Return true if PARALLEL contains register REGNO. */
1354 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1358 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1361 if (GET_CODE (parallel
) != PARALLEL
)
1364 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1368 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1369 if (REG_P (x
) && REGNO (x
) == regno
)
1376 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1379 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1381 enum m68k_function_kind kind
;
1383 /* We cannot use sibcalls for nested functions because we use the
1384 static chain register for indirect calls. */
1385 if (CALL_EXPR_STATIC_CHAIN (exp
))
1388 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1390 /* Check that the return value locations are the same. For
1391 example that we aren't returning a value from the sibling in
1392 a D0 register but then need to transfer it to a A0 register. */
1396 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1398 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1400 /* Check that the values are equal or that the result the callee
1401 function returns is superset of what the current function returns. */
1402 if (!(rtx_equal_p (cfun_value
, call_value
)
1403 || (REG_P (cfun_value
)
1404 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1408 kind
= m68k_get_function_kind (current_function_decl
);
1409 if (kind
== m68k_fk_normal_function
)
1410 /* We can always sibcall from a normal function, because it's
1411 undefined if it is calling an interrupt function. */
1414 /* Otherwise we can only sibcall if the function kind is known to be
1416 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1422 /* On the m68k all args are always pushed. */
1425 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1426 machine_mode mode ATTRIBUTE_UNUSED
,
1427 const_tree type ATTRIBUTE_UNUSED
,
1428 bool named ATTRIBUTE_UNUSED
)
1434 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1435 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1437 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1439 *cum
+= (mode
!= BLKmode
1440 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1441 : (int_size_in_bytes (type
) + 3) & ~3);
1444 /* Convert X to a legitimate function call memory reference and return the
1448 m68k_legitimize_call_address (rtx x
)
1450 gcc_assert (MEM_P (x
));
1451 if (call_operand (XEXP (x
, 0), VOIDmode
))
1453 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1456 /* Likewise for sibling calls. */
1459 m68k_legitimize_sibcall_address (rtx x
)
1461 gcc_assert (MEM_P (x
));
1462 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1465 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1466 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1469 /* Convert X to a legitimate address and return it if successful. Otherwise
1472 For the 68000, we handle X+REG by loading X into a register R and
1473 using R+REG. R will go in an address reg and indexing will be used.
1474 However, if REG is a broken-out memory address or multiplication,
1475 nothing needs to be done because REG can certainly go in an address reg. */
1478 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1480 if (m68k_tls_symbol_p (x
))
1481 return m68k_legitimize_tls_address (x
);
1483 if (GET_CODE (x
) == PLUS
)
1485 int ch
= (x
) != (oldx
);
1488 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1490 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1493 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1495 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1498 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1502 if (GET_CODE (XEXP (x
, 1)) == REG
1503 && GET_CODE (XEXP (x
, 0)) == REG
)
1505 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1508 x
= force_operand (x
, 0);
1512 if (memory_address_p (mode
, x
))
1515 if (GET_CODE (XEXP (x
, 0)) == REG
1516 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1517 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1518 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1520 rtx temp
= gen_reg_rtx (Pmode
);
1521 rtx val
= force_operand (XEXP (x
, 1), 0);
1522 emit_move_insn (temp
, val
);
1525 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1526 && GET_CODE (XEXP (x
, 0)) == REG
)
1527 x
= force_operand (x
, 0);
1529 else if (GET_CODE (XEXP (x
, 1)) == REG
1530 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1531 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1532 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1534 rtx temp
= gen_reg_rtx (Pmode
);
1535 rtx val
= force_operand (XEXP (x
, 0), 0);
1536 emit_move_insn (temp
, val
);
1539 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1540 && GET_CODE (XEXP (x
, 1)) == REG
)
1541 x
= force_operand (x
, 0);
1549 /* Output a dbCC; jCC sequence. Note we do not handle the
1550 floating point version of this sequence (Fdbcc). We also
1551 do not handle alternative conditions when CC_NO_OVERFLOW is
1552 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1553 kick those out before we get here. */
1556 output_dbcc_and_branch (rtx
*operands
)
1558 switch (GET_CODE (operands
[3]))
1561 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1565 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1569 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1573 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1577 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1581 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1585 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1589 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1593 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1597 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1604 /* If the decrement is to be done in SImode, then we have
1605 to compensate for the fact that dbcc decrements in HImode. */
1606 switch (GET_MODE (operands
[0]))
1609 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1621 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1624 enum rtx_code op_code
= GET_CODE (op
);
1626 /* This does not produce a useful cc. */
1629 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1630 below. Swap the operands and change the op if these requirements
1631 are not fulfilled. */
1632 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1636 operand1
= operand2
;
1638 op_code
= swap_condition (op_code
);
1640 loperands
[0] = operand1
;
1641 if (GET_CODE (operand1
) == REG
)
1642 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1644 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1645 if (operand2
!= const0_rtx
)
1647 loperands
[2] = operand2
;
1648 if (GET_CODE (operand2
) == REG
)
1649 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1651 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1653 loperands
[4] = gen_label_rtx ();
1654 if (operand2
!= const0_rtx
)
1655 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1658 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1659 output_asm_insn ("tst%.l %0", loperands
);
1661 output_asm_insn ("cmp%.w #0,%0", loperands
);
1663 output_asm_insn ("jne %l4", loperands
);
1665 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1666 output_asm_insn ("tst%.l %1", loperands
);
1668 output_asm_insn ("cmp%.w #0,%1", loperands
);
1671 loperands
[5] = dest
;
1676 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1677 CODE_LABEL_NUMBER (loperands
[4]));
1678 output_asm_insn ("seq %5", loperands
);
1682 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1683 CODE_LABEL_NUMBER (loperands
[4]));
1684 output_asm_insn ("sne %5", loperands
);
1688 loperands
[6] = gen_label_rtx ();
1689 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1690 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1691 CODE_LABEL_NUMBER (loperands
[4]));
1692 output_asm_insn ("sgt %5", loperands
);
1693 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1694 CODE_LABEL_NUMBER (loperands
[6]));
1698 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1699 CODE_LABEL_NUMBER (loperands
[4]));
1700 output_asm_insn ("shi %5", loperands
);
1704 loperands
[6] = gen_label_rtx ();
1705 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1706 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1707 CODE_LABEL_NUMBER (loperands
[4]));
1708 output_asm_insn ("slt %5", loperands
);
1709 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1710 CODE_LABEL_NUMBER (loperands
[6]));
1714 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1715 CODE_LABEL_NUMBER (loperands
[4]));
1716 output_asm_insn ("scs %5", loperands
);
1720 loperands
[6] = gen_label_rtx ();
1721 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1722 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1723 CODE_LABEL_NUMBER (loperands
[4]));
1724 output_asm_insn ("sge %5", loperands
);
1725 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1726 CODE_LABEL_NUMBER (loperands
[6]));
1730 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1731 CODE_LABEL_NUMBER (loperands
[4]));
1732 output_asm_insn ("scc %5", loperands
);
1736 loperands
[6] = gen_label_rtx ();
1737 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1738 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1739 CODE_LABEL_NUMBER (loperands
[4]));
1740 output_asm_insn ("sle %5", loperands
);
1741 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1742 CODE_LABEL_NUMBER (loperands
[6]));
1746 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1747 CODE_LABEL_NUMBER (loperands
[4]));
1748 output_asm_insn ("sls %5", loperands
);
1758 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1760 operands
[0] = countop
;
1761 operands
[1] = dataop
;
1763 if (GET_CODE (countop
) == CONST_INT
)
1765 register int count
= INTVAL (countop
);
1766 /* If COUNT is bigger than size of storage unit in use,
1767 advance to the containing unit of same size. */
1768 if (count
> signpos
)
1770 int offset
= (count
& ~signpos
) / 8;
1771 count
= count
& signpos
;
1772 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1774 if (count
== signpos
)
1775 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1777 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1779 /* These three statements used to use next_insns_test_no...
1780 but it appears that this should do the same job. */
1782 && next_insn_tests_no_inequality (insn
))
1785 && next_insn_tests_no_inequality (insn
))
1788 && next_insn_tests_no_inequality (insn
))
1790 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1791 On some m68k variants unfortunately that's slower than btst.
1792 On 68000 and higher, that should also work for all HImode operands. */
1793 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1795 if (count
== 3 && DATA_REG_P (operands
[1])
1796 && next_insn_tests_no_inequality (insn
))
1798 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1799 return "move%.w %1,%%ccr";
1801 if (count
== 2 && DATA_REG_P (operands
[1])
1802 && next_insn_tests_no_inequality (insn
))
1804 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1805 return "move%.w %1,%%ccr";
1807 /* count == 1 followed by bvc/bvs and
1808 count == 0 followed by bcc/bcs are also possible, but need
1809 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1812 cc_status
.flags
= CC_NOT_NEGATIVE
;
1814 return "btst %0,%1";
1817 /* Return true if X is a legitimate base register. STRICT_P says
1818 whether we need strict checking. */
1821 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1823 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1824 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1829 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1830 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1833 /* Return true if X is a legitimate index register. STRICT_P says
1834 whether we need strict checking. */
1837 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1839 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1844 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1845 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1848 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1849 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1850 ADDRESS if so. STRICT_P says whether we need strict checking. */
1853 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1857 /* Check for a scale factor. */
1859 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1860 && GET_CODE (x
) == MULT
1861 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1862 && (INTVAL (XEXP (x
, 1)) == 2
1863 || INTVAL (XEXP (x
, 1)) == 4
1864 || (INTVAL (XEXP (x
, 1)) == 8
1865 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1867 scale
= INTVAL (XEXP (x
, 1));
1871 /* Check for a word extension. */
1872 if (!TARGET_COLDFIRE
1873 && GET_CODE (x
) == SIGN_EXTEND
1874 && GET_MODE (XEXP (x
, 0)) == HImode
)
1877 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1879 address
->scale
= scale
;
1887 /* Return true if X is an illegitimate symbolic constant. */
1890 m68k_illegitimate_symbolic_constant_p (rtx x
)
1894 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1896 split_const (x
, &base
, &offset
);
1897 if (GET_CODE (base
) == SYMBOL_REF
1898 && !offset_within_block_p (base
, INTVAL (offset
)))
1901 return m68k_tls_reference_p (x
, false);
1904 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1907 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1909 return m68k_illegitimate_symbolic_constant_p (x
);
1912 /* Return true if X is a legitimate constant address that can reach
1913 bytes in the range [X, X + REACH). STRICT_P says whether we need
1917 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1921 if (!CONSTANT_ADDRESS_P (x
))
1925 && !(strict_p
&& TARGET_PCREL
)
1926 && symbolic_operand (x
, VOIDmode
))
1929 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1931 split_const (x
, &base
, &offset
);
1932 if (GET_CODE (base
) == SYMBOL_REF
1933 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1937 return !m68k_tls_reference_p (x
, false);
1940 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1941 labels will become jump tables. */
1944 m68k_jump_table_ref_p (rtx x
)
1946 if (GET_CODE (x
) != LABEL_REF
)
1949 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1950 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1953 insn
= next_nonnote_insn (insn
);
1954 return insn
&& JUMP_TABLE_DATA_P (insn
);
1957 /* Return true if X is a legitimate address for values of mode MODE.
1958 STRICT_P says whether strict checking is needed. If the address
1959 is valid, describe its components in *ADDRESS. */
1962 m68k_decompose_address (machine_mode mode
, rtx x
,
1963 bool strict_p
, struct m68k_address
*address
)
1967 memset (address
, 0, sizeof (*address
));
1969 if (mode
== BLKmode
)
1972 reach
= GET_MODE_SIZE (mode
);
1974 /* Check for (An) (mode 2). */
1975 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1981 /* Check for -(An) and (An)+ (modes 3 and 4). */
1982 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1983 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1985 address
->code
= GET_CODE (x
);
1986 address
->base
= XEXP (x
, 0);
1990 /* Check for (d16,An) (mode 5). */
1991 if (GET_CODE (x
) == PLUS
1992 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1993 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1994 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1996 address
->base
= XEXP (x
, 0);
1997 address
->offset
= XEXP (x
, 1);
2001 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2002 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2004 if (GET_CODE (x
) == PLUS
2005 && XEXP (x
, 0) == pic_offset_table_rtx
)
2007 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2008 they are invalid in this context. */
2009 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2011 address
->base
= XEXP (x
, 0);
2012 address
->offset
= XEXP (x
, 1);
2017 /* The ColdFire FPU only accepts addressing modes 2-5. */
2018 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2021 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2022 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2023 All these modes are variations of mode 7. */
2024 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2026 address
->offset
= x
;
2030 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2033 ??? do_tablejump creates these addresses before placing the target
2034 label, so we have to assume that unplaced labels are jump table
2035 references. It seems unlikely that we would ever generate indexed
2036 accesses to unplaced labels in other cases. */
2037 if (GET_CODE (x
) == PLUS
2038 && m68k_jump_table_ref_p (XEXP (x
, 1))
2039 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2041 address
->offset
= XEXP (x
, 1);
2045 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2046 (bd,An,Xn.SIZE*SCALE) addresses. */
2050 /* Check for a nonzero base displacement. */
2051 if (GET_CODE (x
) == PLUS
2052 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2054 address
->offset
= XEXP (x
, 1);
2058 /* Check for a suppressed index register. */
2059 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2065 /* Check for a suppressed base register. Do not allow this case
2066 for non-symbolic offsets as it effectively gives gcc freedom
2067 to treat data registers as base registers, which can generate
2070 && symbolic_operand (address
->offset
, VOIDmode
)
2071 && m68k_decompose_index (x
, strict_p
, address
))
2076 /* Check for a nonzero base displacement. */
2077 if (GET_CODE (x
) == PLUS
2078 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2079 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2081 address
->offset
= XEXP (x
, 1);
2086 /* We now expect the sum of a base and an index. */
2087 if (GET_CODE (x
) == PLUS
)
2089 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2090 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2092 address
->base
= XEXP (x
, 0);
2096 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2097 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2099 address
->base
= XEXP (x
, 1);
2106 /* Return true if X is a legitimate address for values of mode MODE.
2107 STRICT_P says whether strict checking is needed. */
2110 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2112 struct m68k_address address
;
2114 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2117 /* Return true if X is a memory, describing its address in ADDRESS if so.
2118 Apply strict checking if called during or after reload. */
2121 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2124 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2125 reload_in_progress
|| reload_completed
,
2129 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2132 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2134 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2137 /* Return true if X matches the 'Q' constraint. It must be a memory
2138 with a base address and no constant offset or index. */
2141 m68k_matches_q_p (rtx x
)
2143 struct m68k_address address
;
2145 return (m68k_legitimate_mem_p (x
, &address
)
2146 && address
.code
== UNKNOWN
2152 /* Return true if X matches the 'U' constraint. It must be a base address
2153 with a constant offset and no index. */
2156 m68k_matches_u_p (rtx x
)
2158 struct m68k_address address
;
2160 return (m68k_legitimate_mem_p (x
, &address
)
2161 && address
.code
== UNKNOWN
2167 /* Return GOT pointer. */
2172 if (pic_offset_table_rtx
== NULL_RTX
)
2173 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2175 crtl
->uses_pic_offset_table
= 1;
2177 return pic_offset_table_rtx
;
2180 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2182 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2183 RELOC_TLSIE
, RELOC_TLSLE
};
2185 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2187 /* Wrap symbol X into unspec representing relocation RELOC.
2188 BASE_REG - register that should be added to the result.
2189 TEMP_REG - if non-null, temporary register. */
2192 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2196 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2198 if (TARGET_COLDFIRE
&& use_x_p
)
2199 /* When compiling with -mx{got, tls} switch the code will look like this:
2201 move.l <X>@<RELOC>,<TEMP_REG>
2202 add.l <BASE_REG>,<TEMP_REG> */
2204 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2205 to put @RELOC after reference. */
2206 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2208 x
= gen_rtx_CONST (Pmode
, x
);
2210 if (temp_reg
== NULL
)
2212 gcc_assert (can_create_pseudo_p ());
2213 temp_reg
= gen_reg_rtx (Pmode
);
2216 emit_move_insn (temp_reg
, x
);
2217 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2222 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2224 x
= gen_rtx_CONST (Pmode
, x
);
2226 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2232 /* Helper for m68k_unwrap_symbol.
2233 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2234 sets *RELOC_PTR to relocation type for the symbol. */
2237 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2238 enum m68k_reloc
*reloc_ptr
)
2240 if (GET_CODE (orig
) == CONST
)
2243 enum m68k_reloc dummy
;
2247 if (reloc_ptr
== NULL
)
2250 /* Handle an addend. */
2251 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2252 && CONST_INT_P (XEXP (x
, 1)))
2255 if (GET_CODE (x
) == UNSPEC
)
2257 switch (XINT (x
, 1))
2259 case UNSPEC_RELOC16
:
2260 orig
= XVECEXP (x
, 0, 0);
2261 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2264 case UNSPEC_RELOC32
:
2265 if (unwrap_reloc32_p
)
2267 orig
= XVECEXP (x
, 0, 0);
2268 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2281 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2282 UNSPEC_RELOC32 wrappers. */
2285 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2287 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2290 /* Prescan insn before outputing assembler for it. */
2293 m68k_final_prescan_insn (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2294 rtx
*operands
, int n_operands
)
2298 /* Combine and, possibly, other optimizations may do good job
2300 (const (unspec [(symbol)]))
2302 (const (plus (unspec [(symbol)])
2304 The problem with this is emitting @TLS or @GOT decorations.
2305 The decoration is emitted when processing (unspec), so the
2306 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2308 It seems that the easiest solution to this is to convert such
2310 (const (unspec [(plus (symbol)
2312 Note, that the top level of operand remains intact, so we don't have
2313 to patch up anything outside of the operand. */
2315 subrtx_var_iterator::array_type array
;
2316 for (i
= 0; i
< n_operands
; ++i
)
2322 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2325 if (m68k_unwrap_symbol (x
, true) != x
)
2329 gcc_assert (GET_CODE (x
) == CONST
);
2332 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2337 unspec
= XEXP (plus
, 0);
2338 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2339 addend
= XEXP (plus
, 1);
2340 gcc_assert (CONST_INT_P (addend
));
2342 /* We now have all the pieces, rearrange them. */
2344 /* Move symbol to plus. */
2345 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2347 /* Move plus inside unspec. */
2348 XVECEXP (unspec
, 0, 0) = plus
;
2350 /* Move unspec to top level of const. */
2351 XEXP (x
, 0) = unspec
;
2353 iter
.skip_subrtxes ();
2359 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2360 If REG is non-null, use it; generate new pseudo otherwise. */
2363 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2367 if (reg
== NULL_RTX
)
2369 gcc_assert (can_create_pseudo_p ());
2370 reg
= gen_reg_rtx (Pmode
);
2373 insn
= emit_move_insn (reg
, x
);
2374 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2376 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2381 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2385 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2387 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2389 x
= gen_rtx_MEM (Pmode
, x
);
2390 MEM_READONLY_P (x
) = 1;
2395 /* Legitimize PIC addresses. If the address is already
2396 position-independent, we return ORIG. Newly generated
2397 position-independent addresses go to REG. If we need more
2398 than one register, we lose.
2400 An address is legitimized by making an indirect reference
2401 through the Global Offset Table with the name of the symbol
2404 The assembler and linker are responsible for placing the
2405 address of the symbol in the GOT. The function prologue
2406 is responsible for initializing a5 to the starting address
2409 The assembler is also responsible for translating a symbol name
2410 into a constant displacement from the start of the GOT.
2412 A quick example may make things a little clearer:
2414 When not generating PIC code to store the value 12345 into _foo
2415 we would generate the following code:
2419 When generating PIC two transformations are made. First, the compiler
2420 loads the address of foo into a register. So the first transformation makes:
2425 The code in movsi will intercept the lea instruction and call this
2426 routine which will transform the instructions into:
2428 movel a5@(_foo:w), a0
2432 That (in a nutshell) is how *all* symbol and label references are
2436 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2441 /* First handle a simple SYMBOL_REF or LABEL_REF */
2442 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2446 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2447 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2449 else if (GET_CODE (orig
) == CONST
)
2453 /* Make sure this has not already been legitimized. */
2454 if (m68k_unwrap_symbol (orig
, true) != orig
)
2459 /* legitimize both operands of the PLUS */
2460 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2462 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2463 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2464 base
== reg
? 0 : reg
);
2466 if (GET_CODE (orig
) == CONST_INT
)
2467 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2469 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2475 /* The __tls_get_addr symbol. */
2476 static GTY(()) rtx m68k_tls_get_addr
;
2478 /* Return SYMBOL_REF for __tls_get_addr. */
2481 m68k_get_tls_get_addr (void)
2483 if (m68k_tls_get_addr
== NULL_RTX
)
2484 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2486 return m68k_tls_get_addr
;
2489 /* Return libcall result in A0 instead of usual D0. */
2490 static bool m68k_libcall_value_in_a0_p
= false;
2492 /* Emit instruction sequence that calls __tls_get_addr. X is
2493 the TLS symbol we are referencing and RELOC is the symbol type to use
2494 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2495 emitted. A pseudo register with result of __tls_get_addr call is
2499 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2505 /* Emit the call sequence. */
2508 /* FIXME: Unfortunately, emit_library_call_value does not
2509 consider (plus (%a5) (const (unspec))) to be a good enough
2510 operand for push, so it forces it into a register. The bad
2511 thing about this is that combiner, due to copy propagation and other
2512 optimizations, sometimes can not later fix this. As a consequence,
2513 additional register may be allocated resulting in a spill.
2514 For reference, see args processing loops in
2515 calls.c:emit_library_call_value_1.
2516 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2517 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2519 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2520 is the simpliest way of generating a call. The difference between
2521 __tls_get_addr() and libcall is that the result is returned in D0
2522 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2523 which temporarily switches returning the result to A0. */
2525 m68k_libcall_value_in_a0_p
= true;
2526 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2527 Pmode
, 1, x
, Pmode
);
2528 m68k_libcall_value_in_a0_p
= false;
2530 insns
= get_insns ();
2533 gcc_assert (can_create_pseudo_p ());
2534 dest
= gen_reg_rtx (Pmode
);
2535 emit_libcall_block (insns
, dest
, a0
, eqv
);
2540 /* The __tls_get_addr symbol. */
2541 static GTY(()) rtx m68k_read_tp
;
2543 /* Return SYMBOL_REF for __m68k_read_tp. */
2546 m68k_get_m68k_read_tp (void)
2548 if (m68k_read_tp
== NULL_RTX
)
2549 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2551 return m68k_read_tp
;
2554 /* Emit instruction sequence that calls __m68k_read_tp.
2555 A pseudo register with result of __m68k_read_tp call is returned. */
2558 m68k_call_m68k_read_tp (void)
2567 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2568 is the simpliest way of generating a call. The difference between
2569 __m68k_read_tp() and libcall is that the result is returned in D0
2570 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2571 which temporarily switches returning the result to A0. */
2573 /* Emit the call sequence. */
2574 m68k_libcall_value_in_a0_p
= true;
2575 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2577 m68k_libcall_value_in_a0_p
= false;
2578 insns
= get_insns ();
2581 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2582 share the m68k_read_tp result with other IE/LE model accesses. */
2583 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2585 gcc_assert (can_create_pseudo_p ());
2586 dest
= gen_reg_rtx (Pmode
);
2587 emit_libcall_block (insns
, dest
, a0
, eqv
);
2592 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2593 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2597 m68k_legitimize_tls_address (rtx orig
)
2599 switch (SYMBOL_REF_TLS_MODEL (orig
))
2601 case TLS_MODEL_GLOBAL_DYNAMIC
:
2602 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2605 case TLS_MODEL_LOCAL_DYNAMIC
:
2611 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2612 share the LDM result with other LD model accesses. */
2613 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2616 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2618 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2620 if (can_create_pseudo_p ())
2621 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2627 case TLS_MODEL_INITIAL_EXEC
:
2632 a0
= m68k_call_m68k_read_tp ();
2634 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2635 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2637 if (can_create_pseudo_p ())
2638 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2644 case TLS_MODEL_LOCAL_EXEC
:
2649 a0
= m68k_call_m68k_read_tp ();
2651 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2653 if (can_create_pseudo_p ())
2654 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2667 /* Return true if X is a TLS symbol. */
2670 m68k_tls_symbol_p (rtx x
)
2672 if (!TARGET_HAVE_TLS
)
2675 if (GET_CODE (x
) != SYMBOL_REF
)
2678 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2681 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2682 though illegitimate one.
2683 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2686 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2688 if (!TARGET_HAVE_TLS
)
2693 subrtx_var_iterator::array_type array
;
2694 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2698 /* Note: this is not the same as m68k_tls_symbol_p. */
2699 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2702 /* Don't recurse into legitimate TLS references. */
2703 if (m68k_tls_reference_p (x
, true))
2704 iter
.skip_subrtxes ();
2710 enum m68k_reloc reloc
= RELOC_GOT
;
2712 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2713 && TLS_RELOC_P (reloc
));
2719 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2721 /* Return the type of move that should be used for integer I. */
2724 m68k_const_method (HOST_WIDE_INT i
)
2731 /* The ColdFire doesn't have byte or word operations. */
2732 /* FIXME: This may not be useful for the m68060 either. */
2733 if (!TARGET_COLDFIRE
)
2735 /* if -256 < N < 256 but N is not in range for a moveq
2736 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2737 if (USE_MOVQ (i
^ 0xff))
2739 /* Likewise, try with not.w */
2740 if (USE_MOVQ (i
^ 0xffff))
2742 /* This is the only value where neg.w is useful */
2747 /* Try also with swap. */
2749 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2754 /* Try using MVZ/MVS with an immediate value to load constants. */
2755 if (i
>= 0 && i
<= 65535)
2757 if (i
>= -32768 && i
<= 32767)
2761 /* Otherwise, use move.l */
2765 /* Return the cost of moving constant I into a data register. */
2768 const_int_cost (HOST_WIDE_INT i
)
2770 switch (m68k_const_method (i
))
2773 /* Constants between -128 and 127 are cheap due to moveq. */
2781 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2791 m68k_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2792 int opno ATTRIBUTE_UNUSED
,
2793 int *total
, bool speed ATTRIBUTE_UNUSED
)
2795 int code
= GET_CODE (x
);
2800 /* Constant zero is super cheap due to clr instruction. */
2801 if (x
== const0_rtx
)
2804 *total
= const_int_cost (INTVAL (x
));
2814 /* Make 0.0 cheaper than other floating constants to
2815 encourage creating tstsf and tstdf insns. */
2816 if (outer_code
== COMPARE
2817 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2823 /* These are vaguely right for a 68020. */
2824 /* The costs for long multiply have been adjusted to work properly
2825 in synth_mult on the 68020, relative to an average of the time
2826 for add and the time for shift, taking away a little more because
2827 sometimes move insns are needed. */
2828 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2833 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2834 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2836 : TARGET_COLDFIRE ? 3 : 13)
2841 : TUNE_68000_10 ? 5 \
2842 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2843 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2845 : TARGET_COLDFIRE ? 2 : 8)
2848 (TARGET_CF_HWDIV ? 11 \
2849 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2852 /* An lea costs about three times as much as a simple add. */
2854 && GET_CODE (XEXP (x
, 1)) == REG
2855 && GET_CODE (XEXP (x
, 0)) == MULT
2856 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2857 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2858 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2859 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2860 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2862 /* lea an@(dx:l:i),am */
2863 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2873 *total
= COSTS_N_INSNS(1);
2878 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2880 if (INTVAL (XEXP (x
, 1)) < 16)
2881 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2883 /* We're using clrw + swap for these cases. */
2884 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2887 *total
= COSTS_N_INSNS (10); /* Worst case. */
2890 /* A shift by a big integer takes an extra instruction. */
2891 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2892 && (INTVAL (XEXP (x
, 1)) == 16))
2894 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2897 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2898 && !(INTVAL (XEXP (x
, 1)) > 0
2899 && INTVAL (XEXP (x
, 1)) <= 8))
2901 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2907 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2908 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2910 *total
= COSTS_N_INSNS (MULW_COST
);
2911 else if (mode
== QImode
|| mode
== HImode
)
2912 *total
= COSTS_N_INSNS (MULW_COST
);
2914 *total
= COSTS_N_INSNS (MULL_COST
);
2921 if (mode
== QImode
|| mode
== HImode
)
2922 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2923 else if (TARGET_CF_HWDIV
)
2924 *total
= COSTS_N_INSNS (18);
2926 *total
= COSTS_N_INSNS (43); /* div.l */
2930 if (outer_code
== COMPARE
)
2939 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2943 output_move_const_into_data_reg (rtx
*operands
)
2947 i
= INTVAL (operands
[1]);
2948 switch (m68k_const_method (i
))
2951 return "mvzw %1,%0";
2953 return "mvsw %1,%0";
2955 return "moveq %1,%0";
2958 operands
[1] = GEN_INT (i
^ 0xff);
2959 return "moveq %1,%0\n\tnot%.b %0";
2962 operands
[1] = GEN_INT (i
^ 0xffff);
2963 return "moveq %1,%0\n\tnot%.w %0";
2966 return "moveq #-128,%0\n\tneg%.w %0";
2971 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2972 return "moveq %1,%0\n\tswap %0";
2975 return "move%.l %1,%0";
2981 /* Return true if I can be handled by ISA B's mov3q instruction. */
2984 valid_mov3q_const (HOST_WIDE_INT i
)
2986 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2989 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2990 I is the value of OPERANDS[1]. */
2993 output_move_simode_const (rtx
*operands
)
2999 src
= INTVAL (operands
[1]);
3001 && (DATA_REG_P (dest
) || MEM_P (dest
))
3002 /* clr insns on 68000 read before writing. */
3003 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3004 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3006 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3007 return "mov3q%.l %1,%0";
3008 else if (src
== 0 && ADDRESS_REG_P (dest
))
3009 return "sub%.l %0,%0";
3010 else if (DATA_REG_P (dest
))
3011 return output_move_const_into_data_reg (operands
);
3012 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3014 if (valid_mov3q_const (src
))
3015 return "mov3q%.l %1,%0";
3016 return "move%.w %1,%0";
3018 else if (MEM_P (dest
)
3019 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3020 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3021 && IN_RANGE (src
, -0x8000, 0x7fff))
3023 if (valid_mov3q_const (src
))
3024 return "mov3q%.l %1,%-";
3027 return "move%.l %1,%0";
3031 output_move_simode (rtx
*operands
)
3033 if (GET_CODE (operands
[1]) == CONST_INT
)
3034 return output_move_simode_const (operands
);
3035 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3036 || GET_CODE (operands
[1]) == CONST
)
3037 && push_operand (operands
[0], SImode
))
3039 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3040 || GET_CODE (operands
[1]) == CONST
)
3041 && ADDRESS_REG_P (operands
[0]))
3042 return "lea %a1,%0";
3043 return "move%.l %1,%0";
3047 output_move_himode (rtx
*operands
)
3049 if (GET_CODE (operands
[1]) == CONST_INT
)
3051 if (operands
[1] == const0_rtx
3052 && (DATA_REG_P (operands
[0])
3053 || GET_CODE (operands
[0]) == MEM
)
3054 /* clr insns on 68000 read before writing. */
3055 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3056 || !(GET_CODE (operands
[0]) == MEM
3057 && MEM_VOLATILE_P (operands
[0]))))
3059 else if (operands
[1] == const0_rtx
3060 && ADDRESS_REG_P (operands
[0]))
3061 return "sub%.l %0,%0";
3062 else if (DATA_REG_P (operands
[0])
3063 && INTVAL (operands
[1]) < 128
3064 && INTVAL (operands
[1]) >= -128)
3065 return "moveq %1,%0";
3066 else if (INTVAL (operands
[1]) < 0x8000
3067 && INTVAL (operands
[1]) >= -0x8000)
3068 return "move%.w %1,%0";
3070 else if (CONSTANT_P (operands
[1]))
3071 return "move%.l %1,%0";
3072 return "move%.w %1,%0";
3076 output_move_qimode (rtx
*operands
)
3078 /* 68k family always modifies the stack pointer by at least 2, even for
3079 byte pushes. The 5200 (ColdFire) does not do this. */
3081 /* This case is generated by pushqi1 pattern now. */
3082 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3083 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3084 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3085 && ! ADDRESS_REG_P (operands
[1])
3086 && ! TARGET_COLDFIRE
));
3088 /* clr and st insns on 68000 read before writing. */
3089 if (!ADDRESS_REG_P (operands
[0])
3090 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3091 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3093 if (operands
[1] == const0_rtx
)
3095 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3096 && GET_CODE (operands
[1]) == CONST_INT
3097 && (INTVAL (operands
[1]) & 255) == 255)
3103 if (GET_CODE (operands
[1]) == CONST_INT
3104 && DATA_REG_P (operands
[0])
3105 && INTVAL (operands
[1]) < 128
3106 && INTVAL (operands
[1]) >= -128)
3107 return "moveq %1,%0";
3108 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3109 return "sub%.l %0,%0";
3110 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3111 return "move%.l %1,%0";
3112 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3113 from address registers. */
3114 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3115 return "move%.w %1,%0";
3116 return "move%.b %1,%0";
3120 output_move_stricthi (rtx
*operands
)
3122 if (operands
[1] == const0_rtx
3123 /* clr insns on 68000 read before writing. */
3124 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3125 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3127 return "move%.w %1,%0";
3131 output_move_strictqi (rtx
*operands
)
3133 if (operands
[1] == const0_rtx
3134 /* clr insns on 68000 read before writing. */
3135 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3136 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3138 return "move%.b %1,%0";
3141 /* Return the best assembler insn template
3142 for moving operands[1] into operands[0] as a fullword. */
3145 singlemove_string (rtx
*operands
)
3147 if (GET_CODE (operands
[1]) == CONST_INT
)
3148 return output_move_simode_const (operands
);
3149 return "move%.l %1,%0";
3153 /* Output assembler or rtl code to perform a doubleword move insn
3154 with operands OPERANDS.
3155 Pointers to 3 helper functions should be specified:
3156 HANDLE_REG_ADJUST to adjust a register by a small value,
3157 HANDLE_COMPADR to compute an address and
3158 HANDLE_MOVSI to move 4 bytes. */
3161 handle_move_double (rtx operands
[2],
3162 void (*handle_reg_adjust
) (rtx
, int),
3163 void (*handle_compadr
) (rtx
[2]),
3164 void (*handle_movsi
) (rtx
[2]))
3168 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3173 rtx addreg0
= 0, addreg1
= 0;
3174 int dest_overlapped_low
= 0;
3175 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3180 /* First classify both operands. */
3182 if (REG_P (operands
[0]))
3184 else if (offsettable_memref_p (operands
[0]))
3186 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3188 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3190 else if (GET_CODE (operands
[0]) == MEM
)
3195 if (REG_P (operands
[1]))
3197 else if (CONSTANT_P (operands
[1]))
3199 else if (offsettable_memref_p (operands
[1]))
3201 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3203 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3205 else if (GET_CODE (operands
[1]) == MEM
)
3210 /* Check for the cases that the operand constraints are not supposed
3211 to allow to happen. Generating code for these cases is
3213 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3215 /* If one operand is decrementing and one is incrementing
3216 decrement the former register explicitly
3217 and change that operand into ordinary indexing. */
3219 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3221 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3223 handle_reg_adjust (operands
[0], -size
);
3225 if (GET_MODE (operands
[1]) == XFmode
)
3226 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3227 else if (GET_MODE (operands
[0]) == DFmode
)
3228 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3230 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3233 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3235 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3237 handle_reg_adjust (operands
[1], -size
);
3239 if (GET_MODE (operands
[1]) == XFmode
)
3240 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3241 else if (GET_MODE (operands
[1]) == DFmode
)
3242 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3244 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3248 /* If an operand is an unoffsettable memory ref, find a register
3249 we can increment temporarily to make it refer to the second word. */
3251 if (optype0
== MEMOP
)
3252 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3254 if (optype1
== MEMOP
)
3255 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3257 /* Ok, we can do one word at a time.
3258 Normally we do the low-numbered word first,
3259 but if either operand is autodecrementing then we
3260 do the high-numbered word first.
3262 In either case, set up in LATEHALF the operands to use
3263 for the high-numbered word and in some cases alter the
3264 operands in OPERANDS to be suitable for the low-numbered word. */
3268 if (optype0
== REGOP
)
3270 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3271 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3273 else if (optype0
== OFFSOP
)
3275 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3276 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3280 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3281 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3284 if (optype1
== REGOP
)
3286 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3287 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3289 else if (optype1
== OFFSOP
)
3291 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3292 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3294 else if (optype1
== CNSTOP
)
3296 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3301 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3302 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3303 operands
[1] = GEN_INT (l
[0]);
3304 middlehalf
[1] = GEN_INT (l
[1]);
3305 latehalf
[1] = GEN_INT (l
[2]);
3309 /* No non-CONST_DOUBLE constant should ever appear
3311 gcc_assert (!CONSTANT_P (operands
[1]));
3316 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3317 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3321 /* size is not 12: */
3323 if (optype0
== REGOP
)
3324 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3325 else if (optype0
== OFFSOP
)
3326 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3328 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3330 if (optype1
== REGOP
)
3331 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3332 else if (optype1
== OFFSOP
)
3333 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3334 else if (optype1
== CNSTOP
)
3335 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3337 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3340 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3341 word first. We should use the adjusted operand 1 (which is N+4(REG))
3342 for the low word as well, to compensate for the first decrement of
3344 if (optype0
== PUSHOP
3345 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3346 operands
[1] = middlehalf
[1] = latehalf
[1];
3348 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3349 if the upper part of reg N does not appear in the MEM, arrange to
3350 emit the move late-half first. Otherwise, compute the MEM address
3351 into the upper part of N and use that as a pointer to the memory
3353 if (optype0
== REGOP
3354 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3356 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3358 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3359 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3361 /* If both halves of dest are used in the src memory address,
3362 compute the address into latehalf of dest.
3363 Note that this can't happen if the dest is two data regs. */
3365 xops
[0] = latehalf
[0];
3366 xops
[1] = XEXP (operands
[1], 0);
3368 handle_compadr (xops
);
3369 if (GET_MODE (operands
[1]) == XFmode
)
3371 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3372 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3373 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3377 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3378 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3382 && reg_overlap_mentioned_p (middlehalf
[0],
3383 XEXP (operands
[1], 0)))
3385 /* Check for two regs used by both source and dest.
3386 Note that this can't happen if the dest is all data regs.
3387 It can happen if the dest is d6, d7, a0.
3388 But in that case, latehalf is an addr reg, so
3389 the code at compadr does ok. */
3391 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3392 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3395 /* JRV says this can't happen: */
3396 gcc_assert (!addreg0
&& !addreg1
);
3398 /* Only the middle reg conflicts; simply put it last. */
3399 handle_movsi (operands
);
3400 handle_movsi (latehalf
);
3401 handle_movsi (middlehalf
);
3405 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3406 /* If the low half of dest is mentioned in the source memory
3407 address, the arrange to emit the move late half first. */
3408 dest_overlapped_low
= 1;
3411 /* If one or both operands autodecrementing,
3412 do the two words, high-numbered first. */
3414 /* Likewise, the first move would clobber the source of the second one,
3415 do them in the other order. This happens only for registers;
3416 such overlap can't happen in memory unless the user explicitly
3417 sets it up, and that is an undefined circumstance. */
3419 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3420 || (optype0
== REGOP
&& optype1
== REGOP
3421 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3422 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3423 || dest_overlapped_low
)
3425 /* Make any unoffsettable addresses point at high-numbered word. */
3427 handle_reg_adjust (addreg0
, size
- 4);
3429 handle_reg_adjust (addreg1
, size
- 4);
3432 handle_movsi (latehalf
);
3434 /* Undo the adds we just did. */
3436 handle_reg_adjust (addreg0
, -4);
3438 handle_reg_adjust (addreg1
, -4);
3442 handle_movsi (middlehalf
);
3445 handle_reg_adjust (addreg0
, -4);
3447 handle_reg_adjust (addreg1
, -4);
3450 /* Do low-numbered word. */
3452 handle_movsi (operands
);
3456 /* Normal case: do the two words, low-numbered first. */
3458 m68k_final_prescan_insn (NULL
, operands
, 2);
3459 handle_movsi (operands
);
3461 /* Do the middle one of the three words for long double */
3465 handle_reg_adjust (addreg0
, 4);
3467 handle_reg_adjust (addreg1
, 4);
3469 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3470 handle_movsi (middlehalf
);
3473 /* Make any unoffsettable addresses point at high-numbered word. */
3475 handle_reg_adjust (addreg0
, 4);
3477 handle_reg_adjust (addreg1
, 4);
3480 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3481 handle_movsi (latehalf
);
3483 /* Undo the adds we just did. */
3485 handle_reg_adjust (addreg0
, -(size
- 4));
3487 handle_reg_adjust (addreg1
, -(size
- 4));
3492 /* Output assembler code to adjust REG by N. */
3494 output_reg_adjust (rtx reg
, int n
)
3498 gcc_assert (GET_MODE (reg
) == SImode
3499 && -12 <= n
&& n
!= 0 && n
<= 12);
3504 s
= "add%.l #12,%0";
3508 s
= "addq%.l #8,%0";
3512 s
= "addq%.l #4,%0";
3516 s
= "sub%.l #12,%0";
3520 s
= "subq%.l #8,%0";
3524 s
= "subq%.l #4,%0";
3532 output_asm_insn (s
, ®
);
3535 /* Emit rtl code to adjust REG by N. */
3537 emit_reg_adjust (rtx reg1
, int n
)
3541 gcc_assert (GET_MODE (reg1
) == SImode
3542 && -12 <= n
&& n
!= 0 && n
<= 12);
3544 reg1
= copy_rtx (reg1
);
3545 reg2
= copy_rtx (reg1
);
3548 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3550 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3555 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3557 output_compadr (rtx operands
[2])
3559 output_asm_insn ("lea %a1,%0", operands
);
3562 /* Output the best assembler insn for moving operands[1] into operands[0]
3565 output_movsi (rtx operands
[2])
3567 output_asm_insn (singlemove_string (operands
), operands
);
3570 /* Copy OP and change its mode to MODE. */
3572 copy_operand (rtx op
, machine_mode mode
)
3574 /* ??? This looks really ugly. There must be a better way
3575 to change a mode on the operand. */
3576 if (GET_MODE (op
) != VOIDmode
)
3579 op
= gen_rtx_REG (mode
, REGNO (op
));
3583 PUT_MODE (op
, mode
);
3590 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3592 emit_movsi (rtx operands
[2])
3594 operands
[0] = copy_operand (operands
[0], SImode
);
3595 operands
[1] = copy_operand (operands
[1], SImode
);
3597 emit_insn (gen_movsi (operands
[0], operands
[1]));
3600 /* Output assembler code to perform a doubleword move insn
3601 with operands OPERANDS. */
3603 output_move_double (rtx
*operands
)
3605 handle_move_double (operands
,
3606 output_reg_adjust
, output_compadr
, output_movsi
);
3611 /* Output rtl code to perform a doubleword move insn
3612 with operands OPERANDS. */
3614 m68k_emit_move_double (rtx operands
[2])
3616 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3619 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3620 new rtx with the correct mode. */
3623 force_mode (machine_mode mode
, rtx orig
)
3625 if (mode
== GET_MODE (orig
))
3628 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3631 return gen_rtx_REG (mode
, REGNO (orig
));
3635 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3637 return reg_renumber
&& FP_REG_P (op
);
3640 /* Emit insns to move operands[1] into operands[0].
3642 Return 1 if we have written out everything that needs to be done to
3643 do the move. Otherwise, return 0 and the caller will emit the move
3646 Note SCRATCH_REG may not be in the proper mode depending on how it
3647 will be used. This routine is responsible for creating a new copy
3648 of SCRATCH_REG in the proper mode. */
3651 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3653 register rtx operand0
= operands
[0];
3654 register rtx operand1
= operands
[1];
3658 && reload_in_progress
&& GET_CODE (operand0
) == REG
3659 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3660 operand0
= reg_equiv_mem (REGNO (operand0
));
3661 else if (scratch_reg
3662 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3663 && GET_CODE (SUBREG_REG (operand0
)) == REG
3664 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3666 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3667 the code which tracks sets/uses for delete_output_reload. */
3668 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3669 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3670 SUBREG_BYTE (operand0
));
3671 operand0
= alter_subreg (&temp
, true);
3675 && reload_in_progress
&& GET_CODE (operand1
) == REG
3676 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3677 operand1
= reg_equiv_mem (REGNO (operand1
));
3678 else if (scratch_reg
3679 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3680 && GET_CODE (SUBREG_REG (operand1
)) == REG
3681 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3683 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3684 the code which tracks sets/uses for delete_output_reload. */
3685 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3686 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3687 SUBREG_BYTE (operand1
));
3688 operand1
= alter_subreg (&temp
, true);
3691 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3692 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3693 != XEXP (operand0
, 0)))
3694 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3695 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3696 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3697 != XEXP (operand1
, 0)))
3698 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3700 /* Handle secondary reloads for loads/stores of FP registers where
3701 the address is symbolic by using the scratch register */
3702 if (fp_reg_operand (operand0
, mode
)
3703 && ((GET_CODE (operand1
) == MEM
3704 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3705 || ((GET_CODE (operand1
) == SUBREG
3706 && GET_CODE (XEXP (operand1
, 0)) == MEM
3707 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3710 if (GET_CODE (operand1
) == SUBREG
)
3711 operand1
= XEXP (operand1
, 0);
3713 /* SCRATCH_REG will hold an address. We want
3714 it in SImode regardless of what mode it was originally given
3716 scratch_reg
= force_mode (SImode
, scratch_reg
);
3718 /* D might not fit in 14 bits either; for such cases load D into
3720 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3722 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3723 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3725 XEXP (XEXP (operand1
, 0), 0),
3729 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3730 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3733 else if (fp_reg_operand (operand1
, mode
)
3734 && ((GET_CODE (operand0
) == MEM
3735 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3736 || ((GET_CODE (operand0
) == SUBREG
)
3737 && GET_CODE (XEXP (operand0
, 0)) == MEM
3738 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3741 if (GET_CODE (operand0
) == SUBREG
)
3742 operand0
= XEXP (operand0
, 0);
3744 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3745 it in SIMODE regardless of what mode it was originally given
3747 scratch_reg
= force_mode (SImode
, scratch_reg
);
3749 /* D might not fit in 14 bits either; for such cases load D into
3751 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3753 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3754 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3757 XEXP (XEXP (operand0
, 0),
3762 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3763 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3766 /* Handle secondary reloads for loads of FP registers from constant
3767 expressions by forcing the constant into memory.
3769 use scratch_reg to hold the address of the memory location.
3771 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3772 NO_REGS when presented with a const_int and an register class
3773 containing only FP registers. Doing so unfortunately creates
3774 more problems than it solves. Fix this for 2.5. */
3775 else if (fp_reg_operand (operand0
, mode
)
3776 && CONSTANT_P (operand1
)
3781 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3782 it in SIMODE regardless of what mode it was originally given
3784 scratch_reg
= force_mode (SImode
, scratch_reg
);
3786 /* Force the constant into memory and put the address of the
3787 memory location into scratch_reg. */
3788 xoperands
[0] = scratch_reg
;
3789 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3790 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3792 /* Now load the destination register. */
3793 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3797 /* Now have insn-emit do whatever it normally does. */
3801 /* Split one or more DImode RTL references into pairs of SImode
3802 references. The RTL can be REG, offsettable MEM, integer constant, or
3803 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3804 split and "num" is its length. lo_half and hi_half are output arrays
3805 that parallel "operands". */
3808 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3812 rtx op
= operands
[num
];
3814 /* simplify_subreg refuses to split volatile memory addresses,
3815 but we still have to handle it. */
3816 if (GET_CODE (op
) == MEM
)
3818 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3819 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3823 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3824 GET_MODE (op
) == VOIDmode
3825 ? DImode
: GET_MODE (op
), 4);
3826 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3827 GET_MODE (op
) == VOIDmode
3828 ? DImode
: GET_MODE (op
), 0);
3833 /* Split X into a base and a constant offset, storing them in *BASE
3834 and *OFFSET respectively. */
3837 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3840 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3842 *offset
+= INTVAL (XEXP (x
, 1));
3848 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3849 instruction. STORE_P says whether the move is a load or store.
3851 If the instruction uses post-increment or pre-decrement addressing,
3852 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3853 adjustment. This adjustment will be made by the first element of
3854 PARALLEL, with the loads or stores starting at element 1. If the
3855 instruction does not use post-increment or pre-decrement addressing,
3856 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3857 start at element 0. */
3860 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3861 HOST_WIDE_INT automod_offset
, bool store_p
)
3863 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3864 HOST_WIDE_INT offset
, mem_offset
;
3866 enum reg_class rclass
;
3868 len
= XVECLEN (pattern
, 0);
3869 first
= (automod_base
!= NULL
);
3873 /* Stores must be pre-decrement and loads must be post-increment. */
3874 if (store_p
!= (automod_offset
< 0))
3877 /* Work out the base and offset for lowest memory location. */
3878 base
= automod_base
;
3879 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3883 /* Allow any valid base and offset in the first access. */
3890 for (i
= first
; i
< len
; i
++)
3892 /* We need a plain SET. */
3893 set
= XVECEXP (pattern
, 0, i
);
3894 if (GET_CODE (set
) != SET
)
3897 /* Check that we have a memory location... */
3898 mem
= XEXP (set
, !store_p
);
3899 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3902 /* ...with the right address. */
3905 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3906 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3907 There are no mode restrictions for 680x0 besides the
3908 automodification rules enforced above. */
3910 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3915 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3916 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3920 /* Check that we have a register of the required mode and class. */
3921 reg
= XEXP (set
, store_p
);
3923 || !HARD_REGISTER_P (reg
)
3924 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3929 /* The register must belong to RCLASS and have a higher number
3930 than the register in the previous SET. */
3931 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3932 || REGNO (last_reg
) >= REGNO (reg
))
3937 /* Work out which register class we need. */
3938 if (INT_REGNO_P (REGNO (reg
)))
3939 rclass
= GENERAL_REGS
;
3940 else if (FP_REGNO_P (REGNO (reg
)))
3947 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3950 /* If we have an automodification, check whether the final offset is OK. */
3951 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3954 /* Reject unprofitable cases. */
3955 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3961 /* Return the assembly code template for a movem or fmovem instruction
3962 whose pattern is given by PATTERN. Store the template's operands
3965 If the instruction uses post-increment or pre-decrement addressing,
3966 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3967 is true if this is a store instruction. */
3970 m68k_output_movem (rtx
*operands
, rtx pattern
,
3971 HOST_WIDE_INT automod_offset
, bool store_p
)
3976 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3978 first
= (automod_offset
!= 0);
3979 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3981 /* When using movem with pre-decrement addressing, register X + D0_REG
3982 is controlled by bit 15 - X. For all other addressing modes,
3983 register X + D0_REG is controlled by bit X. Confusingly, the
3984 register mask for fmovem is in the opposite order to that for
3988 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3989 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3990 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3991 if (automod_offset
< 0)
3993 if (FP_REGNO_P (regno
))
3994 mask
|= 1 << (regno
- FP0_REG
);
3996 mask
|= 1 << (15 - (regno
- D0_REG
));
4000 if (FP_REGNO_P (regno
))
4001 mask
|= 1 << (7 - (regno
- FP0_REG
));
4003 mask
|= 1 << (regno
- D0_REG
);
4008 if (automod_offset
== 0)
4009 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4010 else if (automod_offset
< 0)
4011 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4013 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4014 operands
[1] = GEN_INT (mask
);
4015 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4018 return "fmovem %1,%a0";
4020 return "fmovem %a0,%1";
4025 return "movem%.l %1,%a0";
4027 return "movem%.l %a0,%1";
4031 /* Return a REG that occurs in ADDR with coefficient 1.
4032 ADDR can be effectively incremented by incrementing REG. */
4035 find_addr_reg (rtx addr
)
4037 while (GET_CODE (addr
) == PLUS
)
4039 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4040 addr
= XEXP (addr
, 0);
4041 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4042 addr
= XEXP (addr
, 1);
4043 else if (CONSTANT_P (XEXP (addr
, 0)))
4044 addr
= XEXP (addr
, 1);
4045 else if (CONSTANT_P (XEXP (addr
, 1)))
4046 addr
= XEXP (addr
, 0);
4050 gcc_assert (GET_CODE (addr
) == REG
);
4054 /* Output assembler code to perform a 32-bit 3-operand add. */
4057 output_addsi3 (rtx
*operands
)
4059 if (! operands_match_p (operands
[0], operands
[1]))
4061 if (!ADDRESS_REG_P (operands
[1]))
4063 rtx tmp
= operands
[1];
4065 operands
[1] = operands
[2];
4069 /* These insns can result from reloads to access
4070 stack slots over 64k from the frame pointer. */
4071 if (GET_CODE (operands
[2]) == CONST_INT
4072 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4073 return "move%.l %2,%0\n\tadd%.l %1,%0";
4074 if (GET_CODE (operands
[2]) == REG
)
4075 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4076 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4078 if (GET_CODE (operands
[2]) == CONST_INT
)
4080 if (INTVAL (operands
[2]) > 0
4081 && INTVAL (operands
[2]) <= 8)
4082 return "addq%.l %2,%0";
4083 if (INTVAL (operands
[2]) < 0
4084 && INTVAL (operands
[2]) >= -8)
4086 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4087 return "subq%.l %2,%0";
4089 /* On the CPU32 it is faster to use two addql instructions to
4090 add a small integer (8 < N <= 16) to a register.
4091 Likewise for subql. */
4092 if (TUNE_CPU32
&& REG_P (operands
[0]))
4094 if (INTVAL (operands
[2]) > 8
4095 && INTVAL (operands
[2]) <= 16)
4097 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4098 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4100 if (INTVAL (operands
[2]) < -8
4101 && INTVAL (operands
[2]) >= -16)
4103 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4104 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4107 if (ADDRESS_REG_P (operands
[0])
4108 && INTVAL (operands
[2]) >= -0x8000
4109 && INTVAL (operands
[2]) < 0x8000)
4112 return "add%.w %2,%0";
4114 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4117 return "add%.l %2,%0";
4120 /* Store in cc_status the expressions that the condition codes will
4121 describe after execution of an instruction whose pattern is EXP.
4122 Do not alter them if the instruction would not alter the cc's. */
4124 /* On the 68000, all the insns to store in an address register fail to
4125 set the cc's. However, in some cases these instructions can make it
4126 possibly invalid to use the saved cc's. In those cases we clear out
4127 some or all of the saved cc's so they won't be used. */
4130 notice_update_cc (rtx exp
, rtx insn
)
4132 if (GET_CODE (exp
) == SET
)
4134 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4136 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4138 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4139 cc_status
.value1
= 0;
4140 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4141 cc_status
.value2
= 0;
4143 /* fmoves to memory or data registers do not set the condition
4144 codes. Normal moves _do_ set the condition codes, but not in
4145 a way that is appropriate for comparison with 0, because -0.0
4146 would be treated as a negative nonzero number. Note that it
4147 isn't appropriate to conditionalize this restriction on
4148 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4149 we care about the difference between -0.0 and +0.0. */
4150 else if (!FP_REG_P (SET_DEST (exp
))
4151 && SET_DEST (exp
) != cc0_rtx
4152 && (FP_REG_P (SET_SRC (exp
))
4153 || GET_CODE (SET_SRC (exp
)) == FIX
4154 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4156 /* A pair of move insns doesn't produce a useful overall cc. */
4157 else if (!FP_REG_P (SET_DEST (exp
))
4158 && !FP_REG_P (SET_SRC (exp
))
4159 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4160 && (GET_CODE (SET_SRC (exp
)) == REG
4161 || GET_CODE (SET_SRC (exp
)) == MEM
4162 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4164 else if (SET_DEST (exp
) != pc_rtx
)
4166 cc_status
.flags
= 0;
4167 cc_status
.value1
= SET_DEST (exp
);
4168 cc_status
.value2
= SET_SRC (exp
);
4171 else if (GET_CODE (exp
) == PARALLEL
4172 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4174 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4175 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4177 if (ADDRESS_REG_P (dest
))
4179 else if (dest
!= pc_rtx
)
4181 cc_status
.flags
= 0;
4182 cc_status
.value1
= dest
;
4183 cc_status
.value2
= src
;
4188 if (cc_status
.value2
!= 0
4189 && ADDRESS_REG_P (cc_status
.value2
)
4190 && GET_MODE (cc_status
.value2
) == QImode
)
4192 if (cc_status
.value2
!= 0)
4193 switch (GET_CODE (cc_status
.value2
))
4195 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4196 case ROTATE
: case ROTATERT
:
4197 /* These instructions always clear the overflow bit, and set
4198 the carry to the bit shifted out. */
4199 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4202 case PLUS
: case MINUS
: case MULT
:
4203 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4204 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4205 cc_status
.flags
|= CC_NO_OVERFLOW
;
4208 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4209 ends with a move insn moving r2 in r2's mode.
4210 Thus, the cc's are set for r2.
4211 This can set N bit spuriously. */
4212 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4217 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4219 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4220 cc_status
.value2
= 0;
4221 /* Check for PRE_DEC in dest modifying a register used in src. */
4222 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4223 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4225 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4227 cc_status
.value2
= 0;
4228 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4229 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4230 cc_status
.flags
= CC_IN_68881
;
4231 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4232 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4234 cc_status
.flags
= CC_IN_68881
;
4235 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4236 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4237 cc_status
.flags
|= CC_REVERSED
;
4242 output_move_const_double (rtx
*operands
)
4244 int code
= standard_68881_constant_p (operands
[1]);
4248 static char buf
[40];
4250 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4253 return "fmove%.d %1,%0";
4257 output_move_const_single (rtx
*operands
)
4259 int code
= standard_68881_constant_p (operands
[1]);
4263 static char buf
[40];
4265 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4268 return "fmove%.s %f1,%0";
4271 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4272 from the "fmovecr" instruction.
4273 The value, anded with 0xff, gives the code to use in fmovecr
4274 to get the desired constant. */
4276 /* This code has been fixed for cross-compilation. */
4278 static int inited_68881_table
= 0;
4280 static const char *const strings_68881
[7] = {
4290 static const int codes_68881
[7] = {
4300 REAL_VALUE_TYPE values_68881
[7];
4302 /* Set up values_68881 array by converting the decimal values
4303 strings_68881 to binary. */
4306 init_68881_table (void)
4313 for (i
= 0; i
< 7; i
++)
4317 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4318 values_68881
[i
] = r
;
4320 inited_68881_table
= 1;
4324 standard_68881_constant_p (rtx x
)
4329 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4330 used at all on those chips. */
4334 if (! inited_68881_table
)
4335 init_68881_table ();
4337 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4339 /* Use REAL_VALUES_IDENTICAL instead of real_equal so that -0.0
4341 for (i
= 0; i
< 6; i
++)
4343 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4344 return (codes_68881
[i
]);
4347 if (GET_MODE (x
) == SFmode
)
4350 if (real_equal (&r
, &values_68881
[6]))
4351 return (codes_68881
[6]);
4353 /* larger powers of ten in the constants ram are not used
4354 because they are not equal to a `double' C constant. */
4358 /* If X is a floating-point constant, return the logarithm of X base 2,
4359 or 0 if X is not a power of 2. */
4362 floating_exact_log2 (rtx x
)
4364 REAL_VALUE_TYPE r
, r1
;
4367 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4369 if (REAL_VALUES_LESS (r
, dconst1
))
4372 exp
= real_exponent (&r
);
4373 real_2expN (&r1
, exp
, DFmode
);
4374 if (real_equal (&r1
, &r
))
4380 /* A C compound statement to output to stdio stream STREAM the
4381 assembler syntax for an instruction operand X. X is an RTL
4384 CODE is a value that can be used to specify one of several ways
4385 of printing the operand. It is used when identical operands
4386 must be printed differently depending on the context. CODE
4387 comes from the `%' specification that was used to request
4388 printing of the operand. If the specification was just `%DIGIT'
4389 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4390 is the ASCII code for LTR.
4392 If X is a register, this macro should print the register's name.
4393 The names can be found in an array `reg_names' whose type is
4394 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4396 When the machine description has a specification `%PUNCT' (a `%'
4397 followed by a punctuation character), this macro is called with
4398 a null pointer for X and the punctuation character for CODE.
4400 The m68k specific codes are:
4402 '.' for dot needed in Motorola-style opcode names.
4403 '-' for an operand pushing on the stack:
4404 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4405 '+' for an operand pushing on the stack:
4406 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4407 '@' for a reference to the top word on the stack:
4408 sp@, (sp) or (%sp) depending on the style of syntax.
4409 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4410 but & in SGS syntax).
4411 '!' for the cc register (used in an `and to cc' insn).
4412 '$' for the letter `s' in an op code, but only on the 68040.
4413 '&' for the letter `d' in an op code, but only on the 68040.
4414 '/' for register prefix needed by longlong.h.
4415 '?' for m68k_library_id_string
4417 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4418 'd' to force memory addressing to be absolute, not relative.
4419 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4420 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4421 or print pair of registers as rx:ry.
4422 'p' print an address with @PLTPC attached, but only if the operand
4423 is not locally-bound. */
4426 print_operand (FILE *file
, rtx op
, int letter
)
4431 fprintf (file
, ".");
4433 else if (letter
== '#')
4434 asm_fprintf (file
, "%I");
4435 else if (letter
== '-')
4436 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4437 else if (letter
== '+')
4438 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4439 else if (letter
== '@')
4440 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4441 else if (letter
== '!')
4442 asm_fprintf (file
, "%Rfpcr");
4443 else if (letter
== '$')
4446 fprintf (file
, "s");
4448 else if (letter
== '&')
4451 fprintf (file
, "d");
4453 else if (letter
== '/')
4454 asm_fprintf (file
, "%R");
4455 else if (letter
== '?')
4456 asm_fprintf (file
, m68k_library_id_string
);
4457 else if (letter
== 'p')
4459 output_addr_const (file
, op
);
4460 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4461 fprintf (file
, "@PLTPC");
4463 else if (GET_CODE (op
) == REG
)
4466 /* Print out the second register name of a register pair.
4467 I.e., R (6) => 7. */
4468 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4470 fputs (M68K_REGNAME(REGNO (op
)), file
);
4472 else if (GET_CODE (op
) == MEM
)
4474 output_address (XEXP (op
, 0));
4475 if (letter
== 'd' && ! TARGET_68020
4476 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4477 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4478 && INTVAL (XEXP (op
, 0)) < 0x8000
4479 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4480 fprintf (file
, MOTOROLA
? ".l" : ":l");
4482 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4486 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4487 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4488 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4490 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4494 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4495 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4496 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4497 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4499 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4503 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4504 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4505 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4509 /* Use `print_operand_address' instead of `output_addr_const'
4510 to ensure that we print relevant PIC stuff. */
4511 asm_fprintf (file
, "%I");
4513 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4514 print_operand_address (file
, op
);
4516 output_addr_const (file
, op
);
4520 /* Return string for TLS relocation RELOC. */
4523 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4525 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4526 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4533 if (flag_pic
== 1 && TARGET_68020
)
4574 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4577 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4579 if (GET_CODE (x
) == UNSPEC
)
4581 switch (XINT (x
, 1))
4583 case UNSPEC_RELOC16
:
4584 case UNSPEC_RELOC32
:
4585 output_addr_const (file
, XVECEXP (x
, 0, 0));
4586 fputs (m68k_get_reloc_decoration
4587 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4598 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4601 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4603 gcc_assert (size
== 4);
4604 fputs ("\t.long\t", file
);
4605 output_addr_const (file
, x
);
4606 fputs ("@TLSLDO+0x8000", file
);
4609 /* In the name of slightly smaller debug output, and to cater to
4610 general assembler lossage, recognize various UNSPEC sequences
4611 and turn them back into a direct symbol reference. */
4614 m68k_delegitimize_address (rtx orig_x
)
4617 struct m68k_address addr
;
4620 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4625 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4628 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4629 || addr
.offset
== NULL_RTX
4630 || GET_CODE (addr
.offset
) != CONST
)
4633 unspec
= XEXP (addr
.offset
, 0);
4634 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4635 unspec
= XEXP (unspec
, 0);
4636 if (GET_CODE (unspec
) != UNSPEC
4637 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4638 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4640 x
= XVECEXP (unspec
, 0, 0);
4641 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4642 if (unspec
!= XEXP (addr
.offset
, 0))
4643 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4646 rtx idx
= addr
.index
;
4647 if (addr
.scale
!= 1)
4648 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4649 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4652 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4654 x
= replace_equiv_address_nv (orig_x
, x
);
4659 /* A C compound statement to output to stdio stream STREAM the
4660 assembler syntax for an instruction operand that is a memory
4661 reference whose address is ADDR. ADDR is an RTL expression.
4663 Note that this contains a kludge that knows that the only reason
4664 we have an address (plus (label_ref...) (reg...)) when not generating
4665 PIC code is in the insn before a tablejump, and we know that m68k.md
4666 generates a label LInnn: on such an insn.
4668 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4669 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4671 This routine is responsible for distinguishing between -fpic and -fPIC
4672 style relocations in an address. When generating -fpic code the
4673 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4674 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4677 print_operand_address (FILE *file
, rtx addr
)
4679 struct m68k_address address
;
4681 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4684 if (address
.code
== PRE_DEC
)
4685 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4686 M68K_REGNAME (REGNO (address
.base
)));
4687 else if (address
.code
== POST_INC
)
4688 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4689 M68K_REGNAME (REGNO (address
.base
)));
4690 else if (!address
.base
&& !address
.index
)
4692 /* A constant address. */
4693 gcc_assert (address
.offset
== addr
);
4694 if (GET_CODE (addr
) == CONST_INT
)
4696 /* (xxx).w or (xxx).l. */
4697 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4698 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4700 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4702 else if (TARGET_PCREL
)
4704 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4706 output_addr_const (file
, addr
);
4707 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4711 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4712 name ends in `.<letter>', as the last 2 characters can be
4713 mistaken as a size suffix. Put the name in parentheses. */
4714 if (GET_CODE (addr
) == SYMBOL_REF
4715 && strlen (XSTR (addr
, 0)) > 2
4716 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4719 output_addr_const (file
, addr
);
4723 output_addr_const (file
, addr
);
4730 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4731 label being accessed, otherwise it is -1. */
4732 labelno
= (address
.offset
4734 && GET_CODE (address
.offset
) == LABEL_REF
4735 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4739 /* Print the "offset(base" component. */
4741 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4745 output_addr_const (file
, address
.offset
);
4749 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4751 /* Print the ",index" component, if any. */
4756 fprintf (file
, "%s.%c",
4757 M68K_REGNAME (REGNO (address
.index
)),
4758 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4759 if (address
.scale
!= 1)
4760 fprintf (file
, "*%d", address
.scale
);
4764 else /* !MOTOROLA */
4766 if (!address
.offset
&& !address
.index
)
4767 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4770 /* Print the "base@(offset" component. */
4772 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4776 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4777 fprintf (file
, "@(");
4779 output_addr_const (file
, address
.offset
);
4781 /* Print the ",index" component, if any. */
4784 fprintf (file
, ",%s:%c",
4785 M68K_REGNAME (REGNO (address
.index
)),
4786 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4787 if (address
.scale
!= 1)
4788 fprintf (file
, ":%d", address
.scale
);
4796 /* Check for cases where a clr insns can be omitted from code using
4797 strict_low_part sets. For example, the second clrl here is not needed:
4798 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4800 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4801 insn we are checking for redundancy. TARGET is the register set by the
4805 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4808 rtx_insn
*p
= first_insn
;
4810 while ((p
= PREV_INSN (p
)))
4812 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4818 /* If it isn't an insn, then give up. */
4822 if (reg_set_p (target
, p
))
4824 rtx set
= single_set (p
);
4827 /* If it isn't an easy to recognize insn, then give up. */
4831 dest
= SET_DEST (set
);
4833 /* If this sets the entire target register to zero, then our
4834 first_insn is redundant. */
4835 if (rtx_equal_p (dest
, target
)
4836 && SET_SRC (set
) == const0_rtx
)
4838 else if (GET_CODE (dest
) == STRICT_LOW_PART
4839 && GET_CODE (XEXP (dest
, 0)) == REG
4840 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4841 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4842 <= GET_MODE_SIZE (mode
)))
4843 /* This is a strict low part set which modifies less than
4844 we are using, so it is safe. */
4854 /* Operand predicates for implementing asymmetric pc-relative addressing
4855 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4856 when used as a source operand, but not as a destination operand.
4858 We model this by restricting the meaning of the basic predicates
4859 (general_operand, memory_operand, etc) to forbid the use of this
4860 addressing mode, and then define the following predicates that permit
4861 this addressing mode. These predicates can then be used for the
4862 source operands of the appropriate instructions.
4864 n.b. While it is theoretically possible to change all machine patterns
4865 to use this addressing more where permitted by the architecture,
4866 it has only been implemented for "common" cases: SImode, HImode, and
4867 QImode operands, and only for the principle operations that would
4868 require this addressing mode: data movement and simple integer operations.
4870 In parallel with these new predicates, two new constraint letters
4871 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4872 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4873 In the pcrel case 's' is only valid in combination with 'a' registers.
4874 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4875 of how these constraints are used.
4877 The use of these predicates is strictly optional, though patterns that
4878 don't will cause an extra reload register to be allocated where one
4881 lea (abc:w,%pc),%a0 ; need to reload address
4882 moveq &1,%d1 ; since write to pc-relative space
4883 movel %d1,%a0@ ; is not allowed
4885 lea (abc:w,%pc),%a1 ; no need to reload address here
4886 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4888 For more info, consult tiemann@cygnus.com.
4891 All of the ugliness with predicates and constraints is due to the
4892 simple fact that the m68k does not allow a pc-relative addressing
4893 mode as a destination. gcc does not distinguish between source and
4894 destination addresses. Hence, if we claim that pc-relative address
4895 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4896 end up with invalid code. To get around this problem, we left
4897 pc-relative modes as invalid addresses, and then added special
4898 predicates and constraints to accept them.
4900 A cleaner way to handle this is to modify gcc to distinguish
4901 between source and destination addresses. We can then say that
4902 pc-relative is a valid source address but not a valid destination
4903 address, and hopefully avoid a lot of the predicate and constraint
4904 hackery. Unfortunately, this would be a pretty big change. It would
4905 be a useful change for a number of ports, but there aren't any current
4906 plans to undertake this.
4908 ***************************************************************************/
4912 output_andsi3 (rtx
*operands
)
4915 if (GET_CODE (operands
[2]) == CONST_INT
4916 && (INTVAL (operands
[2]) | 0xffff) == -1
4917 && (DATA_REG_P (operands
[0])
4918 || offsettable_memref_p (operands
[0]))
4919 && !TARGET_COLDFIRE
)
4921 if (GET_CODE (operands
[0]) != REG
)
4922 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4923 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4924 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4926 if (operands
[2] == const0_rtx
)
4928 return "and%.w %2,%0";
4930 if (GET_CODE (operands
[2]) == CONST_INT
4931 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4932 && (DATA_REG_P (operands
[0])
4933 || offsettable_memref_p (operands
[0])))
4935 if (DATA_REG_P (operands
[0]))
4936 operands
[1] = GEN_INT (logval
);
4939 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4940 operands
[1] = GEN_INT (logval
% 8);
4942 /* This does not set condition codes in a standard way. */
4944 return "bclr %1,%0";
4946 return "and%.l %2,%0";
4950 output_iorsi3 (rtx
*operands
)
4952 register int logval
;
4953 if (GET_CODE (operands
[2]) == CONST_INT
4954 && INTVAL (operands
[2]) >> 16 == 0
4955 && (DATA_REG_P (operands
[0])
4956 || offsettable_memref_p (operands
[0]))
4957 && !TARGET_COLDFIRE
)
4959 if (GET_CODE (operands
[0]) != REG
)
4960 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4961 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4963 if (INTVAL (operands
[2]) == 0xffff)
4964 return "mov%.w %2,%0";
4965 return "or%.w %2,%0";
4967 if (GET_CODE (operands
[2]) == CONST_INT
4968 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4969 && (DATA_REG_P (operands
[0])
4970 || offsettable_memref_p (operands
[0])))
4972 if (DATA_REG_P (operands
[0]))
4973 operands
[1] = GEN_INT (logval
);
4976 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4977 operands
[1] = GEN_INT (logval
% 8);
4980 return "bset %1,%0";
4982 return "or%.l %2,%0";
4986 output_xorsi3 (rtx
*operands
)
4988 register int logval
;
4989 if (GET_CODE (operands
[2]) == CONST_INT
4990 && INTVAL (operands
[2]) >> 16 == 0
4991 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4992 && !TARGET_COLDFIRE
)
4994 if (! DATA_REG_P (operands
[0]))
4995 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4996 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4998 if (INTVAL (operands
[2]) == 0xffff)
5000 return "eor%.w %2,%0";
5002 if (GET_CODE (operands
[2]) == CONST_INT
5003 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5004 && (DATA_REG_P (operands
[0])
5005 || offsettable_memref_p (operands
[0])))
5007 if (DATA_REG_P (operands
[0]))
5008 operands
[1] = GEN_INT (logval
);
5011 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5012 operands
[1] = GEN_INT (logval
% 8);
5015 return "bchg %1,%0";
5017 return "eor%.l %2,%0";
5020 /* Return the instruction that should be used for a call to address X,
5021 which is known to be in operand 0. */
5026 if (symbolic_operand (x
, VOIDmode
))
5027 return m68k_symbolic_call
;
5032 /* Likewise sibling calls. */
5035 output_sibcall (rtx x
)
5037 if (symbolic_operand (x
, VOIDmode
))
5038 return m68k_symbolic_jump
;
5044 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5045 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5048 rtx this_slot
, offset
, addr
, mem
, tmp
;
5051 /* Avoid clobbering the struct value reg by using the
5052 static chain reg as a temporary. */
5053 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5055 /* Pretend to be a post-reload pass while generating rtl. */
5056 reload_completed
= 1;
5058 /* The "this" pointer is stored at 4(%sp). */
5059 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5060 stack_pointer_rtx
, 4));
5062 /* Add DELTA to THIS. */
5065 /* Make the offset a legitimate operand for memory addition. */
5066 offset
= GEN_INT (delta
);
5067 if ((delta
< -8 || delta
> 8)
5068 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5070 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5071 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5073 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5074 copy_rtx (this_slot
), offset
));
5077 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5078 if (vcall_offset
!= 0)
5080 /* Set the static chain register to *THIS. */
5081 emit_move_insn (tmp
, this_slot
);
5082 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5084 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5085 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5086 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5088 emit_insn (gen_rtx_SET (tmp
, addr
));
5092 /* Load the offset into %d0 and add it to THIS. */
5093 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5094 gen_rtx_MEM (Pmode
, addr
));
5095 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5096 copy_rtx (this_slot
),
5097 gen_rtx_REG (Pmode
, D0_REG
)));
5100 /* Jump to the target function. Use a sibcall if direct jumps are
5101 allowed, otherwise load the address into a register first. */
5102 mem
= DECL_RTL (function
);
5103 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5105 gcc_assert (flag_pic
);
5107 if (!TARGET_SEP_DATA
)
5109 /* Use the static chain register as a temporary (call-clobbered)
5110 GOT pointer for this function. We can use the static chain
5111 register because it isn't live on entry to the thunk. */
5112 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5113 emit_insn (gen_load_got (pic_offset_table_rtx
));
5115 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5116 mem
= replace_equiv_address (mem
, tmp
);
5118 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5119 SIBLING_CALL_P (insn
) = 1;
5121 /* Run just enough of rest_of_compilation. */
5122 insn
= get_insns ();
5123 split_all_insns_noflow ();
5124 final_start_function (insn
, file
, 1);
5125 final (insn
, file
, 1);
5126 final_end_function ();
5128 /* Clean up the vars set above. */
5129 reload_completed
= 0;
5131 /* Restore the original PIC register. */
5133 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5136 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5139 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5140 int incoming ATTRIBUTE_UNUSED
)
5142 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5145 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5147 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5148 unsigned int new_reg
)
5151 /* Interrupt functions can only use registers that have already been
5152 saved by the prologue, even if they would normally be
5155 if ((m68k_get_function_kind (current_function_decl
)
5156 == m68k_fk_interrupt_handler
)
5157 && !df_regs_ever_live_p (new_reg
))
5163 /* Value is true if hard register REGNO can hold a value of machine-mode
5164 MODE. On the 68000, we let the cpu registers can hold any mode, but
5165 restrict the 68881 registers to floating-point modes. */
5168 m68k_regno_mode_ok (int regno
, machine_mode mode
)
5170 if (DATA_REGNO_P (regno
))
5172 /* Data Registers, can hold aggregate if fits in. */
5173 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5176 else if (ADDRESS_REGNO_P (regno
))
5178 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5181 else if (FP_REGNO_P (regno
))
5183 /* FPU registers, hold float or complex float of long double or
5185 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5186 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5187 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5193 /* Implement SECONDARY_RELOAD_CLASS. */
5196 m68k_secondary_reload_class (enum reg_class rclass
,
5197 machine_mode mode
, rtx x
)
5201 regno
= true_regnum (x
);
5203 /* If one operand of a movqi is an address register, the other
5204 operand must be a general register or constant. Other types
5205 of operand must be reloaded through a data register. */
5206 if (GET_MODE_SIZE (mode
) == 1
5207 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5208 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5211 /* PC-relative addresses must be loaded into an address register first. */
5213 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5214 && symbolic_operand (x
, VOIDmode
))
5220 /* Implement PREFERRED_RELOAD_CLASS. */
5223 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5225 enum reg_class secondary_class
;
5227 /* If RCLASS might need a secondary reload, try restricting it to
5228 a class that doesn't. */
5229 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5230 if (secondary_class
!= NO_REGS
5231 && reg_class_subset_p (secondary_class
, rclass
))
5232 return secondary_class
;
5234 /* Prefer to use moveq for in-range constants. */
5235 if (GET_CODE (x
) == CONST_INT
5236 && reg_class_subset_p (DATA_REGS
, rclass
)
5237 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5240 /* ??? Do we really need this now? */
5241 if (GET_CODE (x
) == CONST_DOUBLE
5242 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5244 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5253 /* Return floating point values in a 68881 register. This makes 68881 code
5254 a little bit faster. It also makes -msoft-float code incompatible with
5255 hard-float code, so people have to be careful not to mix the two.
5256 For ColdFire it was decided the ABI incompatibility is undesirable.
5257 If there is need for a hard-float ABI it is probably worth doing it
5258 properly and also passing function arguments in FP registers. */
5260 m68k_libcall_value (machine_mode mode
)
5267 return gen_rtx_REG (mode
, FP0_REG
);
5273 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5276 /* Location in which function value is returned.
5277 NOTE: Due to differences in ABIs, don't call this function directly,
5278 use FUNCTION_VALUE instead. */
5280 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5284 mode
= TYPE_MODE (valtype
);
5290 return gen_rtx_REG (mode
, FP0_REG
);
5296 /* If the function returns a pointer, push that into %a0. */
5297 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5298 /* For compatibility with the large body of existing code which
5299 does not always properly declare external functions returning
5300 pointer types, the m68k/SVR4 convention is to copy the value
5301 returned for pointer functions from a0 to d0 in the function
5302 epilogue, so that callers that have neglected to properly
5303 declare the callee can still find the correct return value in
5305 return gen_rtx_PARALLEL
5308 gen_rtx_EXPR_LIST (VOIDmode
,
5309 gen_rtx_REG (mode
, A0_REG
),
5311 gen_rtx_EXPR_LIST (VOIDmode
,
5312 gen_rtx_REG (mode
, D0_REG
),
5314 else if (POINTER_TYPE_P (valtype
))
5315 return gen_rtx_REG (mode
, A0_REG
);
5317 return gen_rtx_REG (mode
, D0_REG
);
5320 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5321 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5323 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5325 machine_mode mode
= TYPE_MODE (type
);
5327 if (mode
== BLKmode
)
5330 /* If TYPE's known alignment is less than the alignment of MODE that
5331 would contain the structure, then return in memory. We need to
5332 do so to maintain the compatibility between code compiled with
5333 -mstrict-align and that compiled with -mno-strict-align. */
5334 if (AGGREGATE_TYPE_P (type
)
5335 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5342 /* CPU to schedule the program for. */
5343 enum attr_cpu m68k_sched_cpu
;
5345 /* MAC to schedule the program for. */
5346 enum attr_mac m68k_sched_mac
;
5354 /* Integer register. */
5360 /* Implicit mem reference (e.g. stack). */
5363 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5366 /* Memory with offset but without indexing. EA mode 5. */
5369 /* Memory with indexing. EA mode 6. */
5372 /* Memory referenced by absolute address. EA mode 7. */
5375 /* Immediate operand that doesn't require extension word. */
5378 /* Immediate 16 bit operand. */
5381 /* Immediate 32 bit operand. */
5385 /* Return type of memory ADDR_RTX refers to. */
5386 static enum attr_op_type
5387 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5389 struct m68k_address address
;
5391 if (symbolic_operand (addr_rtx
, VOIDmode
))
5392 return OP_TYPE_MEM7
;
5394 if (!m68k_decompose_address (mode
, addr_rtx
,
5395 reload_completed
, &address
))
5397 gcc_assert (!reload_completed
);
5398 /* Reload will likely fix the address to be in the register. */
5399 return OP_TYPE_MEM234
;
5402 if (address
.scale
!= 0)
5403 return OP_TYPE_MEM6
;
5405 if (address
.base
!= NULL_RTX
)
5407 if (address
.offset
== NULL_RTX
)
5408 return OP_TYPE_MEM234
;
5410 return OP_TYPE_MEM5
;
5413 gcc_assert (address
.offset
!= NULL_RTX
);
5415 return OP_TYPE_MEM7
;
5418 /* Return X or Y (depending on OPX_P) operand of INSN. */
5420 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5424 if (recog_memoized (insn
) < 0)
5427 extract_constrain_insn_cached (insn
);
5430 i
= get_attr_opx (insn
);
5432 i
= get_attr_opy (insn
);
5434 if (i
>= recog_data
.n_operands
)
5437 return recog_data
.operand
[i
];
5440 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5441 If ADDRESS_P is true, return type of memory location operand refers to. */
5442 static enum attr_op_type
5443 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5447 op
= sched_get_operand (insn
, opx_p
);
5451 gcc_assert (!reload_completed
);
5456 return sched_address_type (QImode
, op
);
5458 if (memory_operand (op
, VOIDmode
))
5459 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5461 if (register_operand (op
, VOIDmode
))
5463 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5464 || (reload_completed
&& FP_REG_P (op
)))
5470 if (GET_CODE (op
) == CONST_INT
)
5476 /* Check for quick constants. */
5477 switch (get_attr_type (insn
))
5480 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5481 return OP_TYPE_IMM_Q
;
5483 gcc_assert (!reload_completed
);
5487 if (USE_MOVQ (ival
))
5488 return OP_TYPE_IMM_Q
;
5490 gcc_assert (!reload_completed
);
5494 if (valid_mov3q_const (ival
))
5495 return OP_TYPE_IMM_Q
;
5497 gcc_assert (!reload_completed
);
5504 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5505 return OP_TYPE_IMM_W
;
5507 return OP_TYPE_IMM_L
;
5510 if (GET_CODE (op
) == CONST_DOUBLE
)
5512 switch (GET_MODE (op
))
5515 return OP_TYPE_IMM_W
;
5519 return OP_TYPE_IMM_L
;
5526 if (GET_CODE (op
) == CONST
5527 || symbolic_operand (op
, VOIDmode
)
5530 switch (GET_MODE (op
))
5533 return OP_TYPE_IMM_Q
;
5536 return OP_TYPE_IMM_W
;
5539 return OP_TYPE_IMM_L
;
5542 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5544 return OP_TYPE_IMM_W
;
5546 return OP_TYPE_IMM_L
;
5550 gcc_assert (!reload_completed
);
5552 if (FLOAT_MODE_P (GET_MODE (op
)))
5558 /* Implement opx_type attribute.
5559 Return type of INSN's operand X.
5560 If ADDRESS_P is true, return type of memory location operand refers to. */
5562 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5564 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5570 return OPX_TYPE_FPN
;
5573 return OPX_TYPE_MEM1
;
5575 case OP_TYPE_MEM234
:
5576 return OPX_TYPE_MEM234
;
5579 return OPX_TYPE_MEM5
;
5582 return OPX_TYPE_MEM6
;
5585 return OPX_TYPE_MEM7
;
5588 return OPX_TYPE_IMM_Q
;
5591 return OPX_TYPE_IMM_W
;
5594 return OPX_TYPE_IMM_L
;
5601 /* Implement opy_type attribute.
5602 Return type of INSN's operand Y.
5603 If ADDRESS_P is true, return type of memory location operand refers to. */
5605 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5607 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5613 return OPY_TYPE_FPN
;
5616 return OPY_TYPE_MEM1
;
5618 case OP_TYPE_MEM234
:
5619 return OPY_TYPE_MEM234
;
5622 return OPY_TYPE_MEM5
;
5625 return OPY_TYPE_MEM6
;
5628 return OPY_TYPE_MEM7
;
5631 return OPY_TYPE_IMM_Q
;
5634 return OPY_TYPE_IMM_W
;
5637 return OPY_TYPE_IMM_L
;
5644 /* Return size of INSN as int. */
5646 sched_get_attr_size_int (rtx_insn
*insn
)
5650 switch (get_attr_type (insn
))
5653 /* There should be no references to m68k_sched_attr_size for 'ignore'
5667 switch (get_attr_opx_type (insn
))
5673 case OPX_TYPE_MEM234
:
5674 case OPY_TYPE_IMM_Q
:
5679 /* Here we assume that most absolute references are short. */
5681 case OPY_TYPE_IMM_W
:
5685 case OPY_TYPE_IMM_L
:
5693 switch (get_attr_opy_type (insn
))
5699 case OPY_TYPE_MEM234
:
5700 case OPY_TYPE_IMM_Q
:
5705 /* Here we assume that most absolute references are short. */
5707 case OPY_TYPE_IMM_W
:
5711 case OPY_TYPE_IMM_L
:
5721 gcc_assert (!reload_completed
);
5729 /* Return size of INSN as attribute enum value. */
5731 m68k_sched_attr_size (rtx_insn
*insn
)
5733 switch (sched_get_attr_size_int (insn
))
5749 /* Return operand X or Y (depending on OPX_P) of INSN,
5750 if it is a MEM, or NULL overwise. */
5751 static enum attr_op_type
5752 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5756 switch (get_attr_opx_type (insn
))
5761 case OPX_TYPE_IMM_Q
:
5762 case OPX_TYPE_IMM_W
:
5763 case OPX_TYPE_IMM_L
:
5767 case OPX_TYPE_MEM234
:
5770 return OP_TYPE_MEM1
;
5773 return OP_TYPE_MEM6
;
5781 switch (get_attr_opy_type (insn
))
5786 case OPY_TYPE_IMM_Q
:
5787 case OPY_TYPE_IMM_W
:
5788 case OPY_TYPE_IMM_L
:
5792 case OPY_TYPE_MEM234
:
5795 return OP_TYPE_MEM1
;
5798 return OP_TYPE_MEM6
;
5806 /* Implement op_mem attribute. */
5808 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5810 enum attr_op_type opx
;
5811 enum attr_op_type opy
;
5813 opx
= sched_get_opxy_mem_type (insn
, true);
5814 opy
= sched_get_opxy_mem_type (insn
, false);
5816 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5819 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5821 switch (get_attr_opx_access (insn
))
5837 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5839 switch (get_attr_opx_access (insn
))
5855 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5858 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5860 switch (get_attr_opx_access (insn
))
5866 gcc_assert (!reload_completed
);
5871 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5873 switch (get_attr_opx_access (insn
))
5879 gcc_assert (!reload_completed
);
5884 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5887 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5889 switch (get_attr_opx_access (insn
))
5895 gcc_assert (!reload_completed
);
5900 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5901 gcc_assert (!reload_completed
);
5905 /* Data for ColdFire V4 index bypass.
5906 Producer modifies register that is used as index in consumer with
5910 /* Producer instruction. */
5913 /* Consumer instruction. */
5916 /* Scale of indexed memory access within consumer.
5917 Or zero if bypass should not be effective at the moment. */
5919 } sched_cfv4_bypass_data
;
5921 /* An empty state that is used in m68k_sched_adjust_cost. */
5922 static state_t sched_adjust_cost_state
;
5924 /* Implement adjust_cost scheduler hook.
5925 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5927 m68k_sched_adjust_cost (rtx_insn
*insn
, rtx link ATTRIBUTE_UNUSED
,
5928 rtx_insn
*def_insn
, int cost
)
5932 if (recog_memoized (def_insn
) < 0
5933 || recog_memoized (insn
) < 0)
5936 if (sched_cfv4_bypass_data
.scale
== 1)
5937 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5939 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5940 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5941 that the data in sched_cfv4_bypass_data is up to date. */
5942 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5943 && sched_cfv4_bypass_data
.con
== insn
);
5948 sched_cfv4_bypass_data
.pro
= NULL
;
5949 sched_cfv4_bypass_data
.con
= NULL
;
5950 sched_cfv4_bypass_data
.scale
= 0;
5953 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5954 && sched_cfv4_bypass_data
.con
== NULL
5955 && sched_cfv4_bypass_data
.scale
== 0);
5957 /* Don't try to issue INSN earlier than DFA permits.
5958 This is especially useful for instructions that write to memory,
5959 as their true dependence (default) latency is better to be set to 0
5960 to workaround alias analysis limitations.
5961 This is, in fact, a machine independent tweak, so, probably,
5962 it should be moved to haifa-sched.c: insn_cost (). */
5963 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5970 /* Return maximal number of insns that can be scheduled on a single cycle. */
5972 m68k_sched_issue_rate (void)
5974 switch (m68k_sched_cpu
)
5990 /* Maximal length of instruction for current CPU.
5991 E.g. it is 3 for any ColdFire core. */
5992 static int max_insn_size
;
5994 /* Data to model instruction buffer of CPU. */
5997 /* True if instruction buffer model is modeled for current CPU. */
6000 /* Size of the instruction buffer in words. */
6003 /* Number of filled words in the instruction buffer. */
6006 /* Additional information about instruction buffer for CPUs that have
6007 a buffer of instruction records, rather then a plain buffer
6008 of instruction words. */
6009 struct _sched_ib_records
6011 /* Size of buffer in records. */
6014 /* Array to hold data on adjustements made to the size of the buffer. */
6017 /* Index of the above array. */
6021 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6025 static struct _sched_ib sched_ib
;
6027 /* ID of memory unit. */
6028 static int sched_mem_unit_code
;
6030 /* Implementation of the targetm.sched.variable_issue () hook.
6031 It is called after INSN was issued. It returns the number of insns
6032 that can possibly get scheduled on the current cycle.
6033 It is used here to determine the effect of INSN on the instruction
6036 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6037 int sched_verbose ATTRIBUTE_UNUSED
,
6038 rtx_insn
*insn
, int can_issue_more
)
6042 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6044 switch (m68k_sched_cpu
)
6048 insn_size
= sched_get_attr_size_int (insn
);
6052 insn_size
= sched_get_attr_size_int (insn
);
6054 /* ColdFire V3 and V4 cores have instruction buffers that can
6055 accumulate up to 8 instructions regardless of instructions'
6056 sizes. So we should take care not to "prefetch" 24 one-word
6057 or 12 two-words instructions.
6058 To model this behavior we temporarily decrease size of the
6059 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6063 adjust
= max_insn_size
- insn_size
;
6064 sched_ib
.size
-= adjust
;
6066 if (sched_ib
.filled
> sched_ib
.size
)
6067 sched_ib
.filled
= sched_ib
.size
;
6069 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6072 ++sched_ib
.records
.adjust_index
;
6073 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6074 sched_ib
.records
.adjust_index
= 0;
6076 /* Undo adjustement we did 7 instructions ago. */
6078 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6083 gcc_assert (!sched_ib
.enabled_p
);
6091 if (insn_size
> sched_ib
.filled
)
6092 /* Scheduling for register pressure does not always take DFA into
6093 account. Workaround instruction buffer not being filled enough. */
6095 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6096 insn_size
= sched_ib
.filled
;
6101 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6102 || asm_noperands (PATTERN (insn
)) >= 0)
6103 insn_size
= sched_ib
.filled
;
6107 sched_ib
.filled
-= insn_size
;
6109 return can_issue_more
;
6112 /* Return how many instructions should scheduler lookahead to choose the
6115 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6117 return m68k_sched_issue_rate () - 1;
6120 /* Implementation of targetm.sched.init_global () hook.
6121 It is invoked once per scheduling pass and is used here
6122 to initialize scheduler constants. */
6124 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6125 int sched_verbose ATTRIBUTE_UNUSED
,
6126 int n_insns ATTRIBUTE_UNUSED
)
6128 #ifdef ENABLE_CHECKING
6129 /* Check that all instructions have DFA reservations and
6130 that all instructions can be issued from a clean state. */
6135 state
= alloca (state_size ());
6137 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6139 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6141 gcc_assert (insn_has_dfa_reservation_p (insn
));
6143 state_reset (state
);
6144 if (state_transition (state
, insn
) >= 0)
6151 /* Setup target cpu. */
6153 /* ColdFire V4 has a set of features to keep its instruction buffer full
6154 (e.g., a separate memory bus for instructions) and, hence, we do not model
6155 buffer for this CPU. */
6156 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6158 switch (m68k_sched_cpu
)
6161 sched_ib
.filled
= 0;
6168 sched_ib
.records
.n_insns
= 0;
6169 sched_ib
.records
.adjust
= NULL
;
6174 sched_ib
.records
.n_insns
= 8;
6175 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6182 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6184 sched_adjust_cost_state
= xmalloc (state_size ());
6185 state_reset (sched_adjust_cost_state
);
6188 emit_insn (gen_ib ());
6189 sched_ib
.insn
= get_insns ();
6193 /* Scheduling pass is now finished. Free/reset static variables. */
6195 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6196 int verbose ATTRIBUTE_UNUSED
)
6198 sched_ib
.insn
= NULL
;
6200 free (sched_adjust_cost_state
);
6201 sched_adjust_cost_state
= NULL
;
6203 sched_mem_unit_code
= 0;
6205 free (sched_ib
.records
.adjust
);
6206 sched_ib
.records
.adjust
= NULL
;
6207 sched_ib
.records
.n_insns
= 0;
6211 /* Implementation of targetm.sched.init () hook.
6212 It is invoked each time scheduler starts on the new block (basic block or
6213 extended basic block). */
6215 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6216 int sched_verbose ATTRIBUTE_UNUSED
,
6217 int n_insns ATTRIBUTE_UNUSED
)
6219 switch (m68k_sched_cpu
)
6227 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6229 memset (sched_ib
.records
.adjust
, 0,
6230 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6231 sched_ib
.records
.adjust_index
= 0;
6235 gcc_assert (!sched_ib
.enabled_p
);
6243 if (sched_ib
.enabled_p
)
6244 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6245 the first cycle. Workaround that. */
6246 sched_ib
.filled
= -2;
6249 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6250 It is invoked just before current cycle finishes and is used here
6251 to track if instruction buffer got its two words this cycle. */
6253 m68k_sched_dfa_pre_advance_cycle (void)
6255 if (!sched_ib
.enabled_p
)
6258 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6260 sched_ib
.filled
+= 2;
6262 if (sched_ib
.filled
> sched_ib
.size
)
6263 sched_ib
.filled
= sched_ib
.size
;
6267 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6268 It is invoked just after new cycle begins and is used here
6269 to setup number of filled words in the instruction buffer so that
6270 instructions which won't have all their words prefetched would be
6271 stalled for a cycle. */
6273 m68k_sched_dfa_post_advance_cycle (void)
6277 if (!sched_ib
.enabled_p
)
6280 /* Setup number of prefetched instruction words in the instruction
6282 i
= max_insn_size
- sched_ib
.filled
;
6286 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6287 /* Pick up scheduler state. */
6292 /* Return X or Y (depending on OPX_P) operand of INSN,
6293 if it is an integer register, or NULL overwise. */
6295 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6301 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6303 op
= sched_get_operand (insn
, true);
6304 gcc_assert (op
!= NULL
);
6306 if (!reload_completed
&& !REG_P (op
))
6312 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6314 op
= sched_get_operand (insn
, false);
6315 gcc_assert (op
!= NULL
);
6317 if (!reload_completed
&& !REG_P (op
))
6325 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6328 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6330 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6341 /* Return X or Y (depending on OPX_P) operand of INSN,
6342 if it is a MEM, or NULL overwise. */
6344 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6364 if (opy_p
&& sched_mem_operand_p (insn
, false))
6365 return sched_get_operand (insn
, false);
6367 if (opx_p
&& sched_mem_operand_p (insn
, true))
6368 return sched_get_operand (insn
, true);
6374 /* Return non-zero if PRO modifies register used as part of
6377 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6382 pro_x
= sched_get_reg_operand (pro
, true);
6386 con_mem_read
= sched_get_mem_operand (con
, true, false);
6387 gcc_assert (con_mem_read
!= NULL
);
6389 if (reg_mentioned_p (pro_x
, con_mem_read
))
6395 /* Helper function for m68k_sched_indexed_address_bypass_p.
6396 if PRO modifies register used as index in CON,
6397 return scale of indexed memory access in CON. Return zero overwise. */
6399 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6403 struct m68k_address address
;
6405 reg
= sched_get_reg_operand (pro
, true);
6409 mem
= sched_get_mem_operand (con
, true, false);
6410 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6412 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6416 if (REGNO (reg
) == REGNO (address
.index
))
6418 gcc_assert (address
.scale
!= 0);
6419 return address
.scale
;
6425 /* Return non-zero if PRO modifies register used
6426 as index with scale 2 or 4 in CON. */
6428 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6430 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6431 && sched_cfv4_bypass_data
.con
== NULL
6432 && sched_cfv4_bypass_data
.scale
== 0);
6434 switch (sched_get_indexed_address_scale (pro
, con
))
6437 /* We can't have a variable latency bypass, so
6438 remember to adjust the insn cost in adjust_cost hook. */
6439 sched_cfv4_bypass_data
.pro
= pro
;
6440 sched_cfv4_bypass_data
.con
= con
;
6441 sched_cfv4_bypass_data
.scale
= 1;
6453 /* We generate a two-instructions program at M_TRAMP :
6454 movea.l &CHAIN_VALUE,%a0
6456 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6459 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6461 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6464 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6466 mem
= adjust_address (m_tramp
, HImode
, 0);
6467 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6468 mem
= adjust_address (m_tramp
, SImode
, 2);
6469 emit_move_insn (mem
, chain_value
);
6471 mem
= adjust_address (m_tramp
, HImode
, 6);
6472 emit_move_insn (mem
, GEN_INT(0x4EF9));
6473 mem
= adjust_address (m_tramp
, SImode
, 8);
6474 emit_move_insn (mem
, fnaddr
);
6476 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6479 /* On the 68000, the RTS insn cannot pop anything.
6480 On the 68010, the RTD insn may be used to pop them if the number
6481 of args is fixed, but if the number is variable then the caller
6482 must pop them all. RTD can't be used for library calls now
6483 because the library is compiled with the Unix compiler.
6484 Use of RTD is a selectable option, since it is incompatible with
6485 standard Unix calling sequences. If the option is not selected,
6486 the caller must always pop the args. */
6489 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6493 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6494 && (!stdarg_p (funtype
)))
6498 /* Make sure everything's fine if we *don't* have a given processor.
6499 This assumes that putting a register in fixed_regs will keep the
6500 compiler's mitts completely off it. We don't bother to zero it out
6501 of register classes. */
6504 m68k_conditional_register_usage (void)
6508 if (!TARGET_HARD_FLOAT
)
6510 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6511 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6512 if (TEST_HARD_REG_BIT (x
, i
))
6513 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6516 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6520 m68k_init_sync_libfuncs (void)
6522 init_sync_libfuncs (UNITS_PER_WORD
);
6525 /* Implements EPILOGUE_USES. All registers are live on exit from an
6526 interrupt routine. */
6528 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6530 return (reload_completed
6531 && (m68k_get_function_kind (current_function_decl
)
6532 == m68k_fk_interrupt_handler
));
6535 #include "gt-m68k.h"