1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
46 #include "sched-int.h"
47 #include "insn-codes.h"
51 enum reg_class regno_reg_class
[] =
53 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
54 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
55 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
56 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
57 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
58 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
63 /* The minimum number of integer registers that we want to save with the
64 movem instruction. Using two movel instructions instead of a single
65 moveml is about 15% faster for the 68020 and 68030 at no expense in
67 #define MIN_MOVEM_REGS 3
69 /* The minimum number of floating point registers that we want to save
70 with the fmovem instruction. */
71 #define MIN_FMOVEM_REGS 1
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
91 unsigned int fpu_mask
;
93 /* Offsets relative to ARG_POINTER. */
94 HOST_WIDE_INT frame_pointer_offset
;
95 HOST_WIDE_INT stack_pointer_offset
;
97 /* Function which the above information refers to. */
101 /* Current frame information calculated by m68k_compute_frame_layout(). */
102 static struct m68k_frame current_frame
;
104 /* Structure describing an m68k address.
106 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
107 with null fields evaluating to 0. Here:
109 - BASE satisfies m68k_legitimate_base_reg_p
110 - INDEX satisfies m68k_legitimate_index_reg_p
111 - OFFSET satisfies m68k_legitimate_constant_address_p
113 INDEX is either HImode or SImode. The other fields are SImode.
115 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
116 the address is (BASE)+. */
117 struct m68k_address
{
125 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
126 static int m68k_sched_issue_rate (void);
127 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
128 static void m68k_sched_md_init_global (FILE *, int, int);
129 static void m68k_sched_md_finish_global (FILE *, int);
130 static void m68k_sched_md_init (FILE *, int, int);
131 static void m68k_sched_dfa_pre_advance_cycle (void);
132 static void m68k_sched_dfa_post_advance_cycle (void);
133 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
135 static bool m68k_can_eliminate (const int, const int);
136 static void m68k_conditional_register_usage (void);
137 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
138 static void m68k_option_override (void);
139 static rtx
find_addr_reg (rtx
);
140 static const char *singlemove_string (rtx
*);
141 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
142 HOST_WIDE_INT
, tree
);
143 static rtx
m68k_struct_value_rtx (tree
, int);
144 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
145 tree args
, int flags
,
147 static void m68k_compute_frame_layout (void);
148 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
149 static bool m68k_ok_for_sibcall_p (tree
, tree
);
150 static bool m68k_tls_symbol_p (rtx
);
151 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
152 static bool m68k_rtx_costs (rtx
, int, int, int *, bool);
153 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
154 static bool m68k_return_in_memory (const_tree
, const_tree
);
156 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
157 static void m68k_trampoline_init (rtx
, tree
, rtx
);
158 static int m68k_return_pops_args (tree
, tree
, int);
159 static rtx
m68k_delegitimize_address (rtx
);
160 static void m68k_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
162 static rtx
m68k_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
164 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
166 /* Initialize the GCC target structure. */
168 #if INT_OP_GROUP == INT_OP_DOT_WORD
169 #undef TARGET_ASM_ALIGNED_HI_OP
170 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
173 #if INT_OP_GROUP == INT_OP_NO_DOT
174 #undef TARGET_ASM_BYTE_OP
175 #define TARGET_ASM_BYTE_OP "\tbyte\t"
176 #undef TARGET_ASM_ALIGNED_HI_OP
177 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
178 #undef TARGET_ASM_ALIGNED_SI_OP
179 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
182 #if INT_OP_GROUP == INT_OP_DC
183 #undef TARGET_ASM_BYTE_OP
184 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
185 #undef TARGET_ASM_ALIGNED_HI_OP
186 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
187 #undef TARGET_ASM_ALIGNED_SI_OP
188 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
191 #undef TARGET_ASM_UNALIGNED_HI_OP
192 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
193 #undef TARGET_ASM_UNALIGNED_SI_OP
194 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
196 #undef TARGET_ASM_OUTPUT_MI_THUNK
197 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
198 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
199 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
201 #undef TARGET_ASM_FILE_START_APP_OFF
202 #define TARGET_ASM_FILE_START_APP_OFF true
204 #undef TARGET_LEGITIMIZE_ADDRESS
205 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
207 #undef TARGET_SCHED_ADJUST_COST
208 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
210 #undef TARGET_SCHED_ISSUE_RATE
211 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
213 #undef TARGET_SCHED_VARIABLE_ISSUE
214 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
216 #undef TARGET_SCHED_INIT_GLOBAL
217 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
219 #undef TARGET_SCHED_FINISH_GLOBAL
220 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
222 #undef TARGET_SCHED_INIT
223 #define TARGET_SCHED_INIT m68k_sched_md_init
225 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
226 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
228 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
229 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
231 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
232 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
233 m68k_sched_first_cycle_multipass_dfa_lookahead
235 #undef TARGET_OPTION_OVERRIDE
236 #define TARGET_OPTION_OVERRIDE m68k_option_override
238 #undef TARGET_RTX_COSTS
239 #define TARGET_RTX_COSTS m68k_rtx_costs
241 #undef TARGET_ATTRIBUTE_TABLE
242 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
244 #undef TARGET_PROMOTE_PROTOTYPES
245 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
247 #undef TARGET_STRUCT_VALUE_RTX
248 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
250 #undef TARGET_CANNOT_FORCE_CONST_MEM
251 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
253 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
254 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
256 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
257 #undef TARGET_RETURN_IN_MEMORY
258 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
262 #undef TARGET_HAVE_TLS
263 #define TARGET_HAVE_TLS (true)
265 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
266 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
269 #undef TARGET_LEGITIMATE_ADDRESS_P
270 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
272 #undef TARGET_CAN_ELIMINATE
273 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
275 #undef TARGET_CONDITIONAL_REGISTER_USAGE
276 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
278 #undef TARGET_TRAMPOLINE_INIT
279 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
281 #undef TARGET_RETURN_POPS_ARGS
282 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
284 #undef TARGET_DELEGITIMIZE_ADDRESS
285 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
287 #undef TARGET_FUNCTION_ARG
288 #define TARGET_FUNCTION_ARG m68k_function_arg
290 #undef TARGET_FUNCTION_ARG_ADVANCE
291 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
293 #undef TARGET_LEGITIMATE_CONSTANT_P
294 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
296 static const struct attribute_spec m68k_attribute_table
[] =
298 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
299 affects_type_identity } */
300 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
302 { "interrupt_handler", 0, 0, true, false, false,
303 m68k_handle_fndecl_attribute
, false },
304 { "interrupt_thread", 0, 0, true, false, false,
305 m68k_handle_fndecl_attribute
, false },
306 { NULL
, 0, 0, false, false, false, NULL
, false }
309 struct gcc_target targetm
= TARGET_INITIALIZER
;
311 /* Base flags for 68k ISAs. */
312 #define FL_FOR_isa_00 FL_ISA_68000
313 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
314 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
315 generated 68881 code for 68020 and 68030 targets unless explicitly told
317 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
318 | FL_BITFIELD | FL_68881)
319 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
320 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
322 /* Base flags for ColdFire ISAs. */
323 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
324 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
325 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
326 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
327 /* ISA_C is not upwardly compatible with ISA_B. */
328 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
332 /* Traditional 68000 instruction sets. */
338 /* ColdFire instruction set variants. */
346 /* Information about one of the -march, -mcpu or -mtune arguments. */
347 struct m68k_target_selection
349 /* The argument being described. */
352 /* For -mcpu, this is the device selected by the option.
353 For -mtune and -march, it is a representative device
354 for the microarchitecture or ISA respectively. */
355 enum target_device device
;
357 /* The M68K_DEVICE fields associated with DEVICE. See the comment
358 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
360 enum uarch_type microarch
;
365 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
366 static const struct m68k_target_selection all_devices
[] =
368 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
369 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
370 #include "m68k-devices.def"
372 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
375 /* A list of all ISAs, mapping each one to a representative device.
376 Used for -march selection. */
377 static const struct m68k_target_selection all_isas
[] =
379 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
380 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
381 #include "m68k-isas.def"
383 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
386 /* A list of all microarchitectures, mapping each one to a representative
387 device. Used for -mtune selection. */
388 static const struct m68k_target_selection all_microarchs
[] =
390 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
391 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
392 #include "m68k-microarchs.def"
393 #undef M68K_MICROARCH
394 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
397 /* The entries associated with the -mcpu, -march and -mtune settings,
398 or null for options that have not been used. */
399 const struct m68k_target_selection
*m68k_cpu_entry
;
400 const struct m68k_target_selection
*m68k_arch_entry
;
401 const struct m68k_target_selection
*m68k_tune_entry
;
403 /* Which CPU we are generating code for. */
404 enum target_device m68k_cpu
;
406 /* Which microarchitecture to tune for. */
407 enum uarch_type m68k_tune
;
409 /* Which FPU to use. */
410 enum fpu_type m68k_fpu
;
412 /* The set of FL_* flags that apply to the target processor. */
413 unsigned int m68k_cpu_flags
;
415 /* The set of FL_* flags that apply to the processor to be tuned for. */
416 unsigned int m68k_tune_flags
;
418 /* Asm templates for calling or jumping to an arbitrary symbolic address,
419 or NULL if such calls or jumps are not supported. The address is held
421 const char *m68k_symbolic_call
;
422 const char *m68k_symbolic_jump
;
424 /* Enum variable that corresponds to m68k_symbolic_call values. */
425 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
428 /* Implement TARGET_OPTION_OVERRIDE. */
431 m68k_option_override (void)
433 const struct m68k_target_selection
*entry
;
434 unsigned long target_mask
;
436 if (global_options_set
.x_m68k_arch_option
)
437 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
439 if (global_options_set
.x_m68k_cpu_option
)
440 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
442 if (global_options_set
.x_m68k_tune_option
)
443 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
451 -march=ARCH should generate code that runs any processor
452 implementing architecture ARCH. -mcpu=CPU should override -march
453 and should generate code that runs on processor CPU, making free
454 use of any instructions that CPU understands. -mtune=UARCH applies
455 on top of -mcpu or -march and optimizes the code for UARCH. It does
456 not change the target architecture. */
459 /* Complain if the -march setting is for a different microarchitecture,
460 or includes flags that the -mcpu setting doesn't. */
462 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
463 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
464 warning (0, "-mcpu=%s conflicts with -march=%s",
465 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
467 entry
= m68k_cpu_entry
;
470 entry
= m68k_arch_entry
;
473 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
475 m68k_cpu_flags
= entry
->flags
;
477 /* Use the architecture setting to derive default values for
481 /* ColdFire is lenient about alignment. */
482 if (!TARGET_COLDFIRE
)
483 target_mask
|= MASK_STRICT_ALIGNMENT
;
485 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
486 target_mask
|= MASK_BITFIELD
;
487 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
488 target_mask
|= MASK_CF_HWDIV
;
489 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
490 target_mask
|= MASK_HARD_FLOAT
;
491 target_flags
|= target_mask
& ~target_flags_explicit
;
493 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
494 m68k_cpu
= entry
->device
;
497 m68k_tune
= m68k_tune_entry
->microarch
;
498 m68k_tune_flags
= m68k_tune_entry
->flags
;
500 #ifdef M68K_DEFAULT_TUNE
501 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
503 enum target_device dev
;
504 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
505 m68k_tune_flags
= all_devices
[dev
]->flags
;
510 m68k_tune
= entry
->microarch
;
511 m68k_tune_flags
= entry
->flags
;
514 /* Set the type of FPU. */
515 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
516 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
519 /* Sanity check to ensure that msep-data and mid-sahred-library are not
520 * both specified together. Doing so simply doesn't make sense.
522 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
523 error ("cannot specify both -msep-data and -mid-shared-library");
525 /* If we're generating code for a separate A5 relative data segment,
526 * we've got to enable -fPIC as well. This might be relaxable to
527 * -fpic but it hasn't been tested properly.
529 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
532 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
533 error if the target does not support them. */
534 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
535 error ("-mpcrel -fPIC is not currently supported on selected cpu");
537 /* ??? A historic way of turning on pic, or is this intended to
538 be an embedded thing that doesn't have the same name binding
539 significance that it does on hosted ELF systems? */
540 if (TARGET_PCREL
&& flag_pic
== 0)
545 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
547 m68k_symbolic_jump
= "jra %a0";
549 else if (TARGET_ID_SHARED_LIBRARY
)
550 /* All addresses must be loaded from the GOT. */
552 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
555 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
557 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
560 /* No unconditional long branch */;
561 else if (TARGET_PCREL
)
562 m68k_symbolic_jump
= "bra%.l %c0";
564 m68k_symbolic_jump
= "bra%.l %p0";
565 /* Turn off function cse if we are doing PIC. We always want
566 function call to be done as `bsr foo@PLTPC'. */
567 /* ??? It's traditional to do this for -mpcrel too, but it isn't
568 clear how intentional that is. */
569 flag_no_function_cse
= 1;
572 switch (m68k_symbolic_call_var
)
574 case M68K_SYMBOLIC_CALL_JSR
:
575 m68k_symbolic_call
= "jsr %a0";
578 case M68K_SYMBOLIC_CALL_BSR_C
:
579 m68k_symbolic_call
= "bsr%.l %c0";
582 case M68K_SYMBOLIC_CALL_BSR_P
:
583 m68k_symbolic_call
= "bsr%.l %p0";
586 case M68K_SYMBOLIC_CALL_NONE
:
587 gcc_assert (m68k_symbolic_call
== NULL
);
594 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
595 if (align_labels
> 2)
597 warning (0, "-falign-labels=%d is not supported", align_labels
);
602 warning (0, "-falign-loops=%d is not supported", align_loops
);
607 SUBTARGET_OVERRIDE_OPTIONS
;
609 /* Setup scheduling options. */
611 m68k_sched_cpu
= CPU_CFV1
;
613 m68k_sched_cpu
= CPU_CFV2
;
615 m68k_sched_cpu
= CPU_CFV3
;
617 m68k_sched_cpu
= CPU_CFV4
;
620 m68k_sched_cpu
= CPU_UNKNOWN
;
621 flag_schedule_insns
= 0;
622 flag_schedule_insns_after_reload
= 0;
623 flag_modulo_sched
= 0;
626 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
628 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
629 m68k_sched_mac
= MAC_CF_EMAC
;
630 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
631 m68k_sched_mac
= MAC_CF_MAC
;
633 m68k_sched_mac
= MAC_NO
;
637 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
638 given argument and NAME is the argument passed to -mcpu. Return NULL
639 if -mcpu was not passed. */
642 m68k_cpp_cpu_ident (const char *prefix
)
646 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
649 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
650 given argument and NAME is the name of the representative device for
651 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
654 m68k_cpp_cpu_family (const char *prefix
)
658 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
661 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
662 "interrupt_handler" attribute and interrupt_thread if FUNC has an
663 "interrupt_thread" attribute. Otherwise, return
664 m68k_fk_normal_function. */
666 enum m68k_function_kind
667 m68k_get_function_kind (tree func
)
671 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
673 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
675 return m68k_fk_interrupt_handler
;
677 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
679 return m68k_fk_interrupt_handler
;
681 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
683 return m68k_fk_interrupt_thread
;
685 return m68k_fk_normal_function
;
688 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
689 struct attribute_spec.handler. */
691 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
692 tree args ATTRIBUTE_UNUSED
,
693 int flags ATTRIBUTE_UNUSED
,
696 if (TREE_CODE (*node
) != FUNCTION_DECL
)
698 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
700 *no_add_attrs
= true;
703 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
705 error ("multiple interrupt attributes not allowed");
706 *no_add_attrs
= true;
710 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
712 error ("interrupt_thread is available only on fido");
713 *no_add_attrs
= true;
720 m68k_compute_frame_layout (void)
724 enum m68k_function_kind func_kind
=
725 m68k_get_function_kind (current_function_decl
);
726 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
727 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
729 /* Only compute the frame once per function.
730 Don't cache information until reload has been completed. */
731 if (current_frame
.funcdef_no
== current_function_funcdef_no
735 current_frame
.size
= (get_frame_size () + 3) & -4;
739 /* Interrupt thread does not need to save any register. */
740 if (!interrupt_thread
)
741 for (regno
= 0; regno
< 16; regno
++)
742 if (m68k_save_reg (regno
, interrupt_handler
))
744 mask
|= 1 << (regno
- D0_REG
);
747 current_frame
.offset
= saved
* 4;
748 current_frame
.reg_no
= saved
;
749 current_frame
.reg_mask
= mask
;
751 current_frame
.foffset
= 0;
753 if (TARGET_HARD_FLOAT
)
755 /* Interrupt thread does not need to save any register. */
756 if (!interrupt_thread
)
757 for (regno
= 16; regno
< 24; regno
++)
758 if (m68k_save_reg (regno
, interrupt_handler
))
760 mask
|= 1 << (regno
- FP0_REG
);
763 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
764 current_frame
.offset
+= current_frame
.foffset
;
766 current_frame
.fpu_no
= saved
;
767 current_frame
.fpu_mask
= mask
;
769 /* Remember what function this frame refers to. */
770 current_frame
.funcdef_no
= current_function_funcdef_no
;
773 /* Worker function for TARGET_CAN_ELIMINATE. */
776 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
778 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
782 m68k_initial_elimination_offset (int from
, int to
)
785 /* The arg pointer points 8 bytes before the start of the arguments,
786 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
787 frame pointer in most frames. */
788 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
789 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
790 return argptr_offset
;
792 m68k_compute_frame_layout ();
794 gcc_assert (to
== STACK_POINTER_REGNUM
);
797 case ARG_POINTER_REGNUM
:
798 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
799 case FRAME_POINTER_REGNUM
:
800 return current_frame
.offset
+ current_frame
.size
;
806 /* Refer to the array `regs_ever_live' to determine which registers
807 to save; `regs_ever_live[I]' is nonzero if register number I
808 is ever used in the function. This function is responsible for
809 knowing which registers should not be saved even if used.
810 Return true if we need to save REGNO. */
813 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
815 if (flag_pic
&& regno
== PIC_REG
)
817 if (crtl
->saves_all_registers
)
819 if (crtl
->uses_pic_offset_table
)
821 /* Reload may introduce constant pool references into a function
822 that thitherto didn't need a PIC register. Note that the test
823 above will not catch that case because we will only set
824 crtl->uses_pic_offset_table when emitting
825 the address reloads. */
826 if (crtl
->uses_const_pool
)
830 if (crtl
->calls_eh_return
)
835 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
836 if (test
== INVALID_REGNUM
)
843 /* Fixed regs we never touch. */
844 if (fixed_regs
[regno
])
847 /* The frame pointer (if it is such) is handled specially. */
848 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
851 /* Interrupt handlers must also save call_used_regs
852 if they are live or when calling nested functions. */
853 if (interrupt_handler
)
855 if (df_regs_ever_live_p (regno
))
858 if (!current_function_is_leaf
&& call_used_regs
[regno
])
862 /* Never need to save registers that aren't touched. */
863 if (!df_regs_ever_live_p (regno
))
866 /* Otherwise save everything that isn't call-clobbered. */
867 return !call_used_regs
[regno
];
870 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
871 the lowest memory address. COUNT is the number of registers to be
872 moved, with register REGNO + I being moved if bit I of MASK is set.
873 STORE_P specifies the direction of the move and ADJUST_STACK_P says
874 whether or not this is pre-decrement (if STORE_P) or post-increment
875 (if !STORE_P) operation. */
878 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
879 unsigned int count
, unsigned int regno
,
880 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
883 rtx body
, addr
, src
, operands
[2];
884 enum machine_mode mode
;
886 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
887 mode
= reg_raw_mode
[regno
];
892 src
= plus_constant (base
, (count
893 * GET_MODE_SIZE (mode
)
894 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
895 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
898 for (; mask
!= 0; mask
>>= 1, regno
++)
901 addr
= plus_constant (base
, offset
);
902 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
903 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
904 XVECEXP (body
, 0, i
++)
905 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
906 offset
+= GET_MODE_SIZE (mode
);
908 gcc_assert (i
== XVECLEN (body
, 0));
910 return emit_insn (body
);
913 /* Make INSN a frame-related instruction. */
916 m68k_set_frame_related (rtx insn
)
921 RTX_FRAME_RELATED_P (insn
) = 1;
922 body
= PATTERN (insn
);
923 if (GET_CODE (body
) == PARALLEL
)
924 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
925 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
928 /* Emit RTL for the "prologue" define_expand. */
931 m68k_expand_prologue (void)
933 HOST_WIDE_INT fsize_with_regs
;
934 rtx limit
, src
, dest
;
936 m68k_compute_frame_layout ();
938 if (flag_stack_usage_info
)
939 current_function_static_stack_size
940 = current_frame
.size
+ current_frame
.offset
;
942 /* If the stack limit is a symbol, we can check it here,
943 before actually allocating the space. */
944 if (crtl
->limit_stack
945 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
947 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
948 if (!m68k_legitimate_constant_p (Pmode
, limit
))
950 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
951 limit
= gen_rtx_REG (Pmode
, D0_REG
);
953 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
954 stack_pointer_rtx
, limit
),
955 stack_pointer_rtx
, limit
,
959 fsize_with_regs
= current_frame
.size
;
962 /* ColdFire's move multiple instructions do not allow pre-decrement
963 addressing. Add the size of movem saves to the initial stack
964 allocation instead. */
965 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
966 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
967 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
968 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
971 if (frame_pointer_needed
)
973 if (fsize_with_regs
== 0 && TUNE_68040
)
975 /* On the 68040, two separate moves are faster than link.w 0. */
976 dest
= gen_frame_mem (Pmode
,
977 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
978 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
979 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
982 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
983 m68k_set_frame_related
984 (emit_insn (gen_link (frame_pointer_rtx
,
985 GEN_INT (-4 - fsize_with_regs
))));
988 m68k_set_frame_related
989 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
990 m68k_set_frame_related
991 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
993 GEN_INT (-fsize_with_regs
))));
996 /* If the frame pointer is needed, emit a special barrier that
997 will prevent the scheduler from moving stores to the frame
998 before the stack adjustment. */
999 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1001 else if (fsize_with_regs
!= 0)
1002 m68k_set_frame_related
1003 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1005 GEN_INT (-fsize_with_regs
))));
1007 if (current_frame
.fpu_mask
)
1009 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1011 m68k_set_frame_related
1012 (m68k_emit_movem (stack_pointer_rtx
,
1013 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1014 current_frame
.fpu_no
, FP0_REG
,
1015 current_frame
.fpu_mask
, true, true));
1020 /* If we're using moveml to save the integer registers,
1021 the stack pointer will point to the bottom of the moveml
1022 save area. Find the stack offset of the first FP register. */
1023 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1026 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1027 m68k_set_frame_related
1028 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1029 current_frame
.fpu_no
, FP0_REG
,
1030 current_frame
.fpu_mask
, true, false));
1034 /* If the stack limit is not a symbol, check it here.
1035 This has the disadvantage that it may be too late... */
1036 if (crtl
->limit_stack
)
1038 if (REG_P (stack_limit_rtx
))
1039 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1041 stack_pointer_rtx
, stack_limit_rtx
,
1044 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1045 warning (0, "stack limit expression is not supported");
1048 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1050 /* Store each register separately in the same order moveml does. */
1053 for (i
= 16; i
-- > 0; )
1054 if (current_frame
.reg_mask
& (1 << i
))
1056 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1057 dest
= gen_frame_mem (SImode
,
1058 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1059 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1064 if (TARGET_COLDFIRE
)
1065 /* The required register save space has already been allocated.
1066 The first register should be stored at (%sp). */
1067 m68k_set_frame_related
1068 (m68k_emit_movem (stack_pointer_rtx
, 0,
1069 current_frame
.reg_no
, D0_REG
,
1070 current_frame
.reg_mask
, true, false));
1072 m68k_set_frame_related
1073 (m68k_emit_movem (stack_pointer_rtx
,
1074 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1075 current_frame
.reg_no
, D0_REG
,
1076 current_frame
.reg_mask
, true, true));
1079 if (!TARGET_SEP_DATA
1080 && crtl
->uses_pic_offset_table
)
1081 emit_insn (gen_load_got (pic_offset_table_rtx
));
1084 /* Return true if a simple (return) instruction is sufficient for this
1085 instruction (i.e. if no epilogue is needed). */
1088 m68k_use_return_insn (void)
1090 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1093 m68k_compute_frame_layout ();
1094 return current_frame
.offset
== 0;
1097 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1098 SIBCALL_P says which.
1100 The function epilogue should not depend on the current stack pointer!
1101 It should use the frame pointer only, if there is a frame pointer.
1102 This is mandatory because of alloca; we also take advantage of it to
1103 omit stack adjustments before returning. */
1106 m68k_expand_epilogue (bool sibcall_p
)
1108 HOST_WIDE_INT fsize
, fsize_with_regs
;
1109 bool big
, restore_from_sp
;
1111 m68k_compute_frame_layout ();
1113 fsize
= current_frame
.size
;
1115 restore_from_sp
= false;
1117 /* FIXME : current_function_is_leaf below is too strong.
1118 What we really need to know there is if there could be pending
1119 stack adjustment needed at that point. */
1120 restore_from_sp
= (!frame_pointer_needed
1121 || (!cfun
->calls_alloca
1122 && current_function_is_leaf
));
1124 /* fsize_with_regs is the size we need to adjust the sp when
1125 popping the frame. */
1126 fsize_with_regs
= fsize
;
1127 if (TARGET_COLDFIRE
&& restore_from_sp
)
1129 /* ColdFire's move multiple instructions do not allow post-increment
1130 addressing. Add the size of movem loads to the final deallocation
1132 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1133 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1134 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1135 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1138 if (current_frame
.offset
+ fsize
>= 0x8000
1140 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1143 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1144 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1146 /* ColdFire's move multiple instructions do not support the
1147 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1148 stack-based restore. */
1149 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1150 GEN_INT (-(current_frame
.offset
+ fsize
)));
1151 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1152 gen_rtx_REG (Pmode
, A1_REG
),
1153 frame_pointer_rtx
));
1154 restore_from_sp
= true;
1158 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1164 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1166 /* Restore each register separately in the same order moveml does. */
1168 HOST_WIDE_INT offset
;
1170 offset
= current_frame
.offset
+ fsize
;
1171 for (i
= 0; i
< 16; i
++)
1172 if (current_frame
.reg_mask
& (1 << i
))
1178 /* Generate the address -OFFSET(%fp,%a1.l). */
1179 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1180 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1181 addr
= plus_constant (addr
, -offset
);
1183 else if (restore_from_sp
)
1184 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1186 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1187 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1188 gen_frame_mem (SImode
, addr
));
1189 offset
-= GET_MODE_SIZE (SImode
);
1192 else if (current_frame
.reg_mask
)
1195 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1196 gen_rtx_REG (Pmode
, A1_REG
),
1198 -(current_frame
.offset
+ fsize
),
1199 current_frame
.reg_no
, D0_REG
,
1200 current_frame
.reg_mask
, false, false);
1201 else if (restore_from_sp
)
1202 m68k_emit_movem (stack_pointer_rtx
, 0,
1203 current_frame
.reg_no
, D0_REG
,
1204 current_frame
.reg_mask
, false,
1207 m68k_emit_movem (frame_pointer_rtx
,
1208 -(current_frame
.offset
+ fsize
),
1209 current_frame
.reg_no
, D0_REG
,
1210 current_frame
.reg_mask
, false, false);
1213 if (current_frame
.fpu_no
> 0)
1216 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1217 gen_rtx_REG (Pmode
, A1_REG
),
1219 -(current_frame
.foffset
+ fsize
),
1220 current_frame
.fpu_no
, FP0_REG
,
1221 current_frame
.fpu_mask
, false, false);
1222 else if (restore_from_sp
)
1224 if (TARGET_COLDFIRE
)
1228 /* If we used moveml to restore the integer registers, the
1229 stack pointer will still point to the bottom of the moveml
1230 save area. Find the stack offset of the first FP
1232 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1235 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1236 m68k_emit_movem (stack_pointer_rtx
, offset
,
1237 current_frame
.fpu_no
, FP0_REG
,
1238 current_frame
.fpu_mask
, false, false);
1241 m68k_emit_movem (stack_pointer_rtx
, 0,
1242 current_frame
.fpu_no
, FP0_REG
,
1243 current_frame
.fpu_mask
, false, true);
1246 m68k_emit_movem (frame_pointer_rtx
,
1247 -(current_frame
.foffset
+ fsize
),
1248 current_frame
.fpu_no
, FP0_REG
,
1249 current_frame
.fpu_mask
, false, false);
1252 if (frame_pointer_needed
)
1253 emit_insn (gen_unlink (frame_pointer_rtx
));
1254 else if (fsize_with_regs
)
1255 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1257 GEN_INT (fsize_with_regs
)));
1259 if (crtl
->calls_eh_return
)
1260 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1262 EH_RETURN_STACKADJ_RTX
));
1265 emit_jump_insn (ret_rtx
);
1268 /* Return true if X is a valid comparison operator for the dbcc
1271 Note it rejects floating point comparison operators.
1272 (In the future we could use Fdbcc).
1274 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1277 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1279 switch (GET_CODE (x
))
1281 case EQ
: case NE
: case GTU
: case LTU
:
1285 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1287 case GT
: case LT
: case GE
: case LE
:
1288 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1294 /* Return nonzero if flags are currently in the 68881 flag register. */
1296 flags_in_68881 (void)
1298 /* We could add support for these in the future */
1299 return cc_status
.flags
& CC_IN_68881
;
1302 /* Return true if PARALLEL contains register REGNO. */
1304 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1308 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1311 if (GET_CODE (parallel
) != PARALLEL
)
1314 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1318 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1319 if (REG_P (x
) && REGNO (x
) == regno
)
1326 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1329 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1331 enum m68k_function_kind kind
;
1333 /* We cannot use sibcalls for nested functions because we use the
1334 static chain register for indirect calls. */
1335 if (CALL_EXPR_STATIC_CHAIN (exp
))
1338 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1340 /* Check that the return value locations are the same. For
1341 example that we aren't returning a value from the sibling in
1342 a D0 register but then need to transfer it to a A0 register. */
1346 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1348 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1350 /* Check that the values are equal or that the result the callee
1351 function returns is superset of what the current function returns. */
1352 if (!(rtx_equal_p (cfun_value
, call_value
)
1353 || (REG_P (cfun_value
)
1354 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1358 kind
= m68k_get_function_kind (current_function_decl
);
1359 if (kind
== m68k_fk_normal_function
)
1360 /* We can always sibcall from a normal function, because it's
1361 undefined if it is calling an interrupt function. */
1364 /* Otherwise we can only sibcall if the function kind is known to be
1366 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1372 /* On the m68k all args are always pushed. */
1375 m68k_function_arg (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
1376 enum machine_mode mode ATTRIBUTE_UNUSED
,
1377 const_tree type ATTRIBUTE_UNUSED
,
1378 bool named ATTRIBUTE_UNUSED
)
1384 m68k_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1385 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1387 *cum
+= (mode
!= BLKmode
1388 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1389 : (int_size_in_bytes (type
) + 3) & ~3);
1392 /* Convert X to a legitimate function call memory reference and return the
1396 m68k_legitimize_call_address (rtx x
)
1398 gcc_assert (MEM_P (x
));
1399 if (call_operand (XEXP (x
, 0), VOIDmode
))
1401 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1404 /* Likewise for sibling calls. */
1407 m68k_legitimize_sibcall_address (rtx x
)
1409 gcc_assert (MEM_P (x
));
1410 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1413 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1414 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1417 /* Convert X to a legitimate address and return it if successful. Otherwise
1420 For the 68000, we handle X+REG by loading X into a register R and
1421 using R+REG. R will go in an address reg and indexing will be used.
1422 However, if REG is a broken-out memory address or multiplication,
1423 nothing needs to be done because REG can certainly go in an address reg. */
1426 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1428 if (m68k_tls_symbol_p (x
))
1429 return m68k_legitimize_tls_address (x
);
1431 if (GET_CODE (x
) == PLUS
)
1433 int ch
= (x
) != (oldx
);
1436 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1438 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1441 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1443 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1446 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1450 if (GET_CODE (XEXP (x
, 1)) == REG
1451 && GET_CODE (XEXP (x
, 0)) == REG
)
1453 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1456 x
= force_operand (x
, 0);
1460 if (memory_address_p (mode
, x
))
1463 if (GET_CODE (XEXP (x
, 0)) == REG
1464 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1465 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1466 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1468 rtx temp
= gen_reg_rtx (Pmode
);
1469 rtx val
= force_operand (XEXP (x
, 1), 0);
1470 emit_move_insn (temp
, val
);
1473 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1474 && GET_CODE (XEXP (x
, 0)) == REG
)
1475 x
= force_operand (x
, 0);
1477 else if (GET_CODE (XEXP (x
, 1)) == REG
1478 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1479 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1480 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1482 rtx temp
= gen_reg_rtx (Pmode
);
1483 rtx val
= force_operand (XEXP (x
, 0), 0);
1484 emit_move_insn (temp
, val
);
1487 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1488 && GET_CODE (XEXP (x
, 1)) == REG
)
1489 x
= force_operand (x
, 0);
1497 /* Output a dbCC; jCC sequence. Note we do not handle the
1498 floating point version of this sequence (Fdbcc). We also
1499 do not handle alternative conditions when CC_NO_OVERFLOW is
1500 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1501 kick those out before we get here. */
1504 output_dbcc_and_branch (rtx
*operands
)
1506 switch (GET_CODE (operands
[3]))
1509 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1513 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1517 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1521 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1525 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1529 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1533 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1537 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1541 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1545 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1552 /* If the decrement is to be done in SImode, then we have
1553 to compensate for the fact that dbcc decrements in HImode. */
1554 switch (GET_MODE (operands
[0]))
1557 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1569 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1572 enum rtx_code op_code
= GET_CODE (op
);
1574 /* This does not produce a useful cc. */
1577 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1578 below. Swap the operands and change the op if these requirements
1579 are not fulfilled. */
1580 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1584 operand1
= operand2
;
1586 op_code
= swap_condition (op_code
);
1588 loperands
[0] = operand1
;
1589 if (GET_CODE (operand1
) == REG
)
1590 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1592 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1593 if (operand2
!= const0_rtx
)
1595 loperands
[2] = operand2
;
1596 if (GET_CODE (operand2
) == REG
)
1597 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1599 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1601 loperands
[4] = gen_label_rtx ();
1602 if (operand2
!= const0_rtx
)
1603 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1606 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1607 output_asm_insn ("tst%.l %0", loperands
);
1609 output_asm_insn ("cmp%.w #0,%0", loperands
);
1611 output_asm_insn ("jne %l4", loperands
);
1613 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1614 output_asm_insn ("tst%.l %1", loperands
);
1616 output_asm_insn ("cmp%.w #0,%1", loperands
);
1619 loperands
[5] = dest
;
1624 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1625 CODE_LABEL_NUMBER (loperands
[4]));
1626 output_asm_insn ("seq %5", loperands
);
1630 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1631 CODE_LABEL_NUMBER (loperands
[4]));
1632 output_asm_insn ("sne %5", loperands
);
1636 loperands
[6] = gen_label_rtx ();
1637 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1638 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1639 CODE_LABEL_NUMBER (loperands
[4]));
1640 output_asm_insn ("sgt %5", loperands
);
1641 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1642 CODE_LABEL_NUMBER (loperands
[6]));
1646 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1647 CODE_LABEL_NUMBER (loperands
[4]));
1648 output_asm_insn ("shi %5", loperands
);
1652 loperands
[6] = gen_label_rtx ();
1653 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1654 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1655 CODE_LABEL_NUMBER (loperands
[4]));
1656 output_asm_insn ("slt %5", loperands
);
1657 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1658 CODE_LABEL_NUMBER (loperands
[6]));
1662 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1663 CODE_LABEL_NUMBER (loperands
[4]));
1664 output_asm_insn ("scs %5", loperands
);
1668 loperands
[6] = gen_label_rtx ();
1669 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1670 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1671 CODE_LABEL_NUMBER (loperands
[4]));
1672 output_asm_insn ("sge %5", loperands
);
1673 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1674 CODE_LABEL_NUMBER (loperands
[6]));
1678 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1679 CODE_LABEL_NUMBER (loperands
[4]));
1680 output_asm_insn ("scc %5", loperands
);
1684 loperands
[6] = gen_label_rtx ();
1685 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1686 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1687 CODE_LABEL_NUMBER (loperands
[4]));
1688 output_asm_insn ("sle %5", loperands
);
1689 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1690 CODE_LABEL_NUMBER (loperands
[6]));
1694 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1695 CODE_LABEL_NUMBER (loperands
[4]));
1696 output_asm_insn ("sls %5", loperands
);
1706 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1708 operands
[0] = countop
;
1709 operands
[1] = dataop
;
1711 if (GET_CODE (countop
) == CONST_INT
)
1713 register int count
= INTVAL (countop
);
1714 /* If COUNT is bigger than size of storage unit in use,
1715 advance to the containing unit of same size. */
1716 if (count
> signpos
)
1718 int offset
= (count
& ~signpos
) / 8;
1719 count
= count
& signpos
;
1720 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1722 if (count
== signpos
)
1723 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1725 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1727 /* These three statements used to use next_insns_test_no...
1728 but it appears that this should do the same job. */
1730 && next_insn_tests_no_inequality (insn
))
1733 && next_insn_tests_no_inequality (insn
))
1736 && next_insn_tests_no_inequality (insn
))
1738 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1739 On some m68k variants unfortunately that's slower than btst.
1740 On 68000 and higher, that should also work for all HImode operands. */
1741 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1743 if (count
== 3 && DATA_REG_P (operands
[1])
1744 && next_insn_tests_no_inequality (insn
))
1746 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1747 return "move%.w %1,%%ccr";
1749 if (count
== 2 && DATA_REG_P (operands
[1])
1750 && next_insn_tests_no_inequality (insn
))
1752 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1753 return "move%.w %1,%%ccr";
1755 /* count == 1 followed by bvc/bvs and
1756 count == 0 followed by bcc/bcs are also possible, but need
1757 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1760 cc_status
.flags
= CC_NOT_NEGATIVE
;
1762 return "btst %0,%1";
1765 /* Return true if X is a legitimate base register. STRICT_P says
1766 whether we need strict checking. */
1769 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1771 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1772 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1777 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1778 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1781 /* Return true if X is a legitimate index register. STRICT_P says
1782 whether we need strict checking. */
1785 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1787 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1792 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1793 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1796 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1797 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1798 ADDRESS if so. STRICT_P says whether we need strict checking. */
1801 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1805 /* Check for a scale factor. */
1807 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1808 && GET_CODE (x
) == MULT
1809 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1810 && (INTVAL (XEXP (x
, 1)) == 2
1811 || INTVAL (XEXP (x
, 1)) == 4
1812 || (INTVAL (XEXP (x
, 1)) == 8
1813 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1815 scale
= INTVAL (XEXP (x
, 1));
1819 /* Check for a word extension. */
1820 if (!TARGET_COLDFIRE
1821 && GET_CODE (x
) == SIGN_EXTEND
1822 && GET_MODE (XEXP (x
, 0)) == HImode
)
1825 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1827 address
->scale
= scale
;
1835 /* Return true if X is an illegitimate symbolic constant. */
1838 m68k_illegitimate_symbolic_constant_p (rtx x
)
1842 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1844 split_const (x
, &base
, &offset
);
1845 if (GET_CODE (base
) == SYMBOL_REF
1846 && !offset_within_block_p (base
, INTVAL (offset
)))
1849 return m68k_tls_reference_p (x
, false);
1852 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1855 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1857 return m68k_illegitimate_symbolic_constant_p (x
);
1860 /* Return true if X is a legitimate constant address that can reach
1861 bytes in the range [X, X + REACH). STRICT_P says whether we need
1865 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1869 if (!CONSTANT_ADDRESS_P (x
))
1873 && !(strict_p
&& TARGET_PCREL
)
1874 && symbolic_operand (x
, VOIDmode
))
1877 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1879 split_const (x
, &base
, &offset
);
1880 if (GET_CODE (base
) == SYMBOL_REF
1881 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1885 return !m68k_tls_reference_p (x
, false);
1888 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1889 labels will become jump tables. */
1892 m68k_jump_table_ref_p (rtx x
)
1894 if (GET_CODE (x
) != LABEL_REF
)
1898 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1901 x
= next_nonnote_insn (x
);
1902 return x
&& JUMP_TABLE_DATA_P (x
);
1905 /* Return true if X is a legitimate address for values of mode MODE.
1906 STRICT_P says whether strict checking is needed. If the address
1907 is valid, describe its components in *ADDRESS. */
1910 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1911 bool strict_p
, struct m68k_address
*address
)
1915 memset (address
, 0, sizeof (*address
));
1917 if (mode
== BLKmode
)
1920 reach
= GET_MODE_SIZE (mode
);
1922 /* Check for (An) (mode 2). */
1923 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1929 /* Check for -(An) and (An)+ (modes 3 and 4). */
1930 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1931 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1933 address
->code
= GET_CODE (x
);
1934 address
->base
= XEXP (x
, 0);
1938 /* Check for (d16,An) (mode 5). */
1939 if (GET_CODE (x
) == PLUS
1940 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1941 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1942 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1944 address
->base
= XEXP (x
, 0);
1945 address
->offset
= XEXP (x
, 1);
1949 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1950 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1952 if (GET_CODE (x
) == PLUS
1953 && XEXP (x
, 0) == pic_offset_table_rtx
)
1955 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
1956 they are invalid in this context. */
1957 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
1959 address
->base
= XEXP (x
, 0);
1960 address
->offset
= XEXP (x
, 1);
1965 /* The ColdFire FPU only accepts addressing modes 2-5. */
1966 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1969 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
1970 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
1971 All these modes are variations of mode 7. */
1972 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
1974 address
->offset
= x
;
1978 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
1981 ??? do_tablejump creates these addresses before placing the target
1982 label, so we have to assume that unplaced labels are jump table
1983 references. It seems unlikely that we would ever generate indexed
1984 accesses to unplaced labels in other cases. */
1985 if (GET_CODE (x
) == PLUS
1986 && m68k_jump_table_ref_p (XEXP (x
, 1))
1987 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
1989 address
->offset
= XEXP (x
, 1);
1993 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
1994 (bd,An,Xn.SIZE*SCALE) addresses. */
1998 /* Check for a nonzero base displacement. */
1999 if (GET_CODE (x
) == PLUS
2000 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2002 address
->offset
= XEXP (x
, 1);
2006 /* Check for a suppressed index register. */
2007 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2013 /* Check for a suppressed base register. Do not allow this case
2014 for non-symbolic offsets as it effectively gives gcc freedom
2015 to treat data registers as base registers, which can generate
2018 && symbolic_operand (address
->offset
, VOIDmode
)
2019 && m68k_decompose_index (x
, strict_p
, address
))
2024 /* Check for a nonzero base displacement. */
2025 if (GET_CODE (x
) == PLUS
2026 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2027 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2029 address
->offset
= XEXP (x
, 1);
2034 /* We now expect the sum of a base and an index. */
2035 if (GET_CODE (x
) == PLUS
)
2037 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2038 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2040 address
->base
= XEXP (x
, 0);
2044 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2045 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2047 address
->base
= XEXP (x
, 1);
2054 /* Return true if X is a legitimate address for values of mode MODE.
2055 STRICT_P says whether strict checking is needed. */
2058 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2060 struct m68k_address address
;
2062 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2065 /* Return true if X is a memory, describing its address in ADDRESS if so.
2066 Apply strict checking if called during or after reload. */
2069 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2072 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2073 reload_in_progress
|| reload_completed
,
2077 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2080 m68k_legitimate_constant_p (enum machine_mode mode
, rtx x
)
2082 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2085 /* Return true if X matches the 'Q' constraint. It must be a memory
2086 with a base address and no constant offset or index. */
2089 m68k_matches_q_p (rtx x
)
2091 struct m68k_address address
;
2093 return (m68k_legitimate_mem_p (x
, &address
)
2094 && address
.code
== UNKNOWN
2100 /* Return true if X matches the 'U' constraint. It must be a base address
2101 with a constant offset and no index. */
2104 m68k_matches_u_p (rtx x
)
2106 struct m68k_address address
;
2108 return (m68k_legitimate_mem_p (x
, &address
)
2109 && address
.code
== UNKNOWN
2115 /* Return GOT pointer. */
2120 if (pic_offset_table_rtx
== NULL_RTX
)
2121 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2123 crtl
->uses_pic_offset_table
= 1;
2125 return pic_offset_table_rtx
;
2128 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2130 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2131 RELOC_TLSIE
, RELOC_TLSLE
};
2133 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2135 /* Wrap symbol X into unspec representing relocation RELOC.
2136 BASE_REG - register that should be added to the result.
2137 TEMP_REG - if non-null, temporary register. */
2140 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2144 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2146 if (TARGET_COLDFIRE
&& use_x_p
)
2147 /* When compiling with -mx{got, tls} switch the code will look like this:
2149 move.l <X>@<RELOC>,<TEMP_REG>
2150 add.l <BASE_REG>,<TEMP_REG> */
2152 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2153 to put @RELOC after reference. */
2154 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2156 x
= gen_rtx_CONST (Pmode
, x
);
2158 if (temp_reg
== NULL
)
2160 gcc_assert (can_create_pseudo_p ());
2161 temp_reg
= gen_reg_rtx (Pmode
);
2164 emit_move_insn (temp_reg
, x
);
2165 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2170 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2172 x
= gen_rtx_CONST (Pmode
, x
);
2174 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2180 /* Helper for m68k_unwrap_symbol.
2181 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2182 sets *RELOC_PTR to relocation type for the symbol. */
2185 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2186 enum m68k_reloc
*reloc_ptr
)
2188 if (GET_CODE (orig
) == CONST
)
2191 enum m68k_reloc dummy
;
2195 if (reloc_ptr
== NULL
)
2198 /* Handle an addend. */
2199 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2200 && CONST_INT_P (XEXP (x
, 1)))
2203 if (GET_CODE (x
) == UNSPEC
)
2205 switch (XINT (x
, 1))
2207 case UNSPEC_RELOC16
:
2208 orig
= XVECEXP (x
, 0, 0);
2209 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2212 case UNSPEC_RELOC32
:
2213 if (unwrap_reloc32_p
)
2215 orig
= XVECEXP (x
, 0, 0);
2216 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2229 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2230 UNSPEC_RELOC32 wrappers. */
2233 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2235 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2238 /* Helper for m68k_final_prescan_insn. */
2241 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2245 if (m68k_unwrap_symbol (x
, true) != x
)
2246 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2250 gcc_assert (GET_CODE (x
) == CONST
);
2253 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2258 unspec
= XEXP (plus
, 0);
2259 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2260 addend
= XEXP (plus
, 1);
2261 gcc_assert (CONST_INT_P (addend
));
2263 /* We now have all the pieces, rearrange them. */
2265 /* Move symbol to plus. */
2266 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2268 /* Move plus inside unspec. */
2269 XVECEXP (unspec
, 0, 0) = plus
;
2271 /* Move unspec to top level of const. */
2272 XEXP (x
, 0) = unspec
;
2281 /* Prescan insn before outputing assembler for it. */
2284 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2285 rtx
*operands
, int n_operands
)
2289 /* Combine and, possibly, other optimizations may do good job
2291 (const (unspec [(symbol)]))
2293 (const (plus (unspec [(symbol)])
2295 The problem with this is emitting @TLS or @GOT decorations.
2296 The decoration is emitted when processing (unspec), so the
2297 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2299 It seems that the easiest solution to this is to convert such
2301 (const (unspec [(plus (symbol)
2303 Note, that the top level of operand remains intact, so we don't have
2304 to patch up anything outside of the operand. */
2306 for (i
= 0; i
< n_operands
; ++i
)
2312 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2316 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2317 If REG is non-null, use it; generate new pseudo otherwise. */
2320 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2324 if (reg
== NULL_RTX
)
2326 gcc_assert (can_create_pseudo_p ());
2327 reg
= gen_reg_rtx (Pmode
);
2330 insn
= emit_move_insn (reg
, x
);
2331 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2333 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2338 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2342 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2344 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2346 x
= gen_rtx_MEM (Pmode
, x
);
2347 MEM_READONLY_P (x
) = 1;
2352 /* Legitimize PIC addresses. If the address is already
2353 position-independent, we return ORIG. Newly generated
2354 position-independent addresses go to REG. If we need more
2355 than one register, we lose.
2357 An address is legitimized by making an indirect reference
2358 through the Global Offset Table with the name of the symbol
2361 The assembler and linker are responsible for placing the
2362 address of the symbol in the GOT. The function prologue
2363 is responsible for initializing a5 to the starting address
2366 The assembler is also responsible for translating a symbol name
2367 into a constant displacement from the start of the GOT.
2369 A quick example may make things a little clearer:
2371 When not generating PIC code to store the value 12345 into _foo
2372 we would generate the following code:
2376 When generating PIC two transformations are made. First, the compiler
2377 loads the address of foo into a register. So the first transformation makes:
2382 The code in movsi will intercept the lea instruction and call this
2383 routine which will transform the instructions into:
2385 movel a5@(_foo:w), a0
2389 That (in a nutshell) is how *all* symbol and label references are
2393 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2398 /* First handle a simple SYMBOL_REF or LABEL_REF */
2399 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2403 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2404 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2406 else if (GET_CODE (orig
) == CONST
)
2410 /* Make sure this has not already been legitimized. */
2411 if (m68k_unwrap_symbol (orig
, true) != orig
)
2416 /* legitimize both operands of the PLUS */
2417 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2419 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2420 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2421 base
== reg
? 0 : reg
);
2423 if (GET_CODE (orig
) == CONST_INT
)
2424 pic_ref
= plus_constant (base
, INTVAL (orig
));
2426 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2432 /* The __tls_get_addr symbol. */
2433 static GTY(()) rtx m68k_tls_get_addr
;
2435 /* Return SYMBOL_REF for __tls_get_addr. */
2438 m68k_get_tls_get_addr (void)
2440 if (m68k_tls_get_addr
== NULL_RTX
)
2441 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2443 return m68k_tls_get_addr
;
2446 /* Return libcall result in A0 instead of usual D0. */
2447 static bool m68k_libcall_value_in_a0_p
= false;
2449 /* Emit instruction sequence that calls __tls_get_addr. X is
2450 the TLS symbol we are referencing and RELOC is the symbol type to use
2451 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2452 emitted. A pseudo register with result of __tls_get_addr call is
2456 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2462 /* Emit the call sequence. */
2465 /* FIXME: Unfortunately, emit_library_call_value does not
2466 consider (plus (%a5) (const (unspec))) to be a good enough
2467 operand for push, so it forces it into a register. The bad
2468 thing about this is that combiner, due to copy propagation and other
2469 optimizations, sometimes can not later fix this. As a consequence,
2470 additional register may be allocated resulting in a spill.
2471 For reference, see args processing loops in
2472 calls.c:emit_library_call_value_1.
2473 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2474 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2476 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2477 is the simpliest way of generating a call. The difference between
2478 __tls_get_addr() and libcall is that the result is returned in D0
2479 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2480 which temporarily switches returning the result to A0. */
2482 m68k_libcall_value_in_a0_p
= true;
2483 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2484 Pmode
, 1, x
, Pmode
);
2485 m68k_libcall_value_in_a0_p
= false;
2487 insns
= get_insns ();
2490 gcc_assert (can_create_pseudo_p ());
2491 dest
= gen_reg_rtx (Pmode
);
2492 emit_libcall_block (insns
, dest
, a0
, eqv
);
2497 /* The __tls_get_addr symbol. */
2498 static GTY(()) rtx m68k_read_tp
;
2500 /* Return SYMBOL_REF for __m68k_read_tp. */
2503 m68k_get_m68k_read_tp (void)
2505 if (m68k_read_tp
== NULL_RTX
)
2506 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2508 return m68k_read_tp
;
2511 /* Emit instruction sequence that calls __m68k_read_tp.
2512 A pseudo register with result of __m68k_read_tp call is returned. */
2515 m68k_call_m68k_read_tp (void)
2524 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2525 is the simpliest way of generating a call. The difference between
2526 __m68k_read_tp() and libcall is that the result is returned in D0
2527 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2528 which temporarily switches returning the result to A0. */
2530 /* Emit the call sequence. */
2531 m68k_libcall_value_in_a0_p
= true;
2532 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2534 m68k_libcall_value_in_a0_p
= false;
2535 insns
= get_insns ();
2538 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2539 share the m68k_read_tp result with other IE/LE model accesses. */
2540 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2542 gcc_assert (can_create_pseudo_p ());
2543 dest
= gen_reg_rtx (Pmode
);
2544 emit_libcall_block (insns
, dest
, a0
, eqv
);
2549 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2550 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2554 m68k_legitimize_tls_address (rtx orig
)
2556 switch (SYMBOL_REF_TLS_MODEL (orig
))
2558 case TLS_MODEL_GLOBAL_DYNAMIC
:
2559 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2562 case TLS_MODEL_LOCAL_DYNAMIC
:
2568 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2569 share the LDM result with other LD model accesses. */
2570 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2573 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2575 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2577 if (can_create_pseudo_p ())
2578 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2584 case TLS_MODEL_INITIAL_EXEC
:
2589 a0
= m68k_call_m68k_read_tp ();
2591 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2592 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2594 if (can_create_pseudo_p ())
2595 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2601 case TLS_MODEL_LOCAL_EXEC
:
2606 a0
= m68k_call_m68k_read_tp ();
2608 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2610 if (can_create_pseudo_p ())
2611 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2624 /* Return true if X is a TLS symbol. */
2627 m68k_tls_symbol_p (rtx x
)
2629 if (!TARGET_HAVE_TLS
)
2632 if (GET_CODE (x
) != SYMBOL_REF
)
2635 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2638 /* Helper for m68k_tls_referenced_p. */
2641 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2643 /* Note: this is not the same as m68k_tls_symbol_p. */
2644 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2645 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2647 /* Don't recurse into legitimate TLS references. */
2648 if (m68k_tls_reference_p (*x_ptr
, true))
2654 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2655 though illegitimate one.
2656 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2659 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2661 if (!TARGET_HAVE_TLS
)
2665 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2668 enum m68k_reloc reloc
= RELOC_GOT
;
2670 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2671 && TLS_RELOC_P (reloc
));
2677 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2679 /* Return the type of move that should be used for integer I. */
2682 m68k_const_method (HOST_WIDE_INT i
)
2689 /* The ColdFire doesn't have byte or word operations. */
2690 /* FIXME: This may not be useful for the m68060 either. */
2691 if (!TARGET_COLDFIRE
)
2693 /* if -256 < N < 256 but N is not in range for a moveq
2694 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2695 if (USE_MOVQ (i
^ 0xff))
2697 /* Likewise, try with not.w */
2698 if (USE_MOVQ (i
^ 0xffff))
2700 /* This is the only value where neg.w is useful */
2705 /* Try also with swap. */
2707 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2712 /* Try using MVZ/MVS with an immediate value to load constants. */
2713 if (i
>= 0 && i
<= 65535)
2715 if (i
>= -32768 && i
<= 32767)
2719 /* Otherwise, use move.l */
2723 /* Return the cost of moving constant I into a data register. */
2726 const_int_cost (HOST_WIDE_INT i
)
2728 switch (m68k_const_method (i
))
2731 /* Constants between -128 and 127 are cheap due to moveq. */
2739 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2749 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2750 bool speed ATTRIBUTE_UNUSED
)
2755 /* Constant zero is super cheap due to clr instruction. */
2756 if (x
== const0_rtx
)
2759 *total
= const_int_cost (INTVAL (x
));
2769 /* Make 0.0 cheaper than other floating constants to
2770 encourage creating tstsf and tstdf insns. */
2771 if (outer_code
== COMPARE
2772 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2778 /* These are vaguely right for a 68020. */
2779 /* The costs for long multiply have been adjusted to work properly
2780 in synth_mult on the 68020, relative to an average of the time
2781 for add and the time for shift, taking away a little more because
2782 sometimes move insns are needed. */
2783 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2788 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2789 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2791 : TARGET_COLDFIRE ? 3 : 13)
2796 : TUNE_68000_10 ? 5 \
2797 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2798 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2800 : TARGET_COLDFIRE ? 2 : 8)
2803 (TARGET_CF_HWDIV ? 11 \
2804 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2807 /* An lea costs about three times as much as a simple add. */
2808 if (GET_MODE (x
) == SImode
2809 && GET_CODE (XEXP (x
, 1)) == REG
2810 && GET_CODE (XEXP (x
, 0)) == MULT
2811 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2812 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2813 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2814 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2815 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2817 /* lea an@(dx:l:i),am */
2818 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2828 *total
= COSTS_N_INSNS(1);
2833 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2835 if (INTVAL (XEXP (x
, 1)) < 16)
2836 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2838 /* We're using clrw + swap for these cases. */
2839 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2842 *total
= COSTS_N_INSNS (10); /* Worst case. */
2845 /* A shift by a big integer takes an extra instruction. */
2846 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2847 && (INTVAL (XEXP (x
, 1)) == 16))
2849 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2852 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2853 && !(INTVAL (XEXP (x
, 1)) > 0
2854 && INTVAL (XEXP (x
, 1)) <= 8))
2856 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2862 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2863 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2864 && GET_MODE (x
) == SImode
)
2865 *total
= COSTS_N_INSNS (MULW_COST
);
2866 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2867 *total
= COSTS_N_INSNS (MULW_COST
);
2869 *total
= COSTS_N_INSNS (MULL_COST
);
2876 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2877 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2878 else if (TARGET_CF_HWDIV
)
2879 *total
= COSTS_N_INSNS (18);
2881 *total
= COSTS_N_INSNS (43); /* div.l */
2885 if (outer_code
== COMPARE
)
2894 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2898 output_move_const_into_data_reg (rtx
*operands
)
2902 i
= INTVAL (operands
[1]);
2903 switch (m68k_const_method (i
))
2906 return "mvzw %1,%0";
2908 return "mvsw %1,%0";
2910 return "moveq %1,%0";
2913 operands
[1] = GEN_INT (i
^ 0xff);
2914 return "moveq %1,%0\n\tnot%.b %0";
2917 operands
[1] = GEN_INT (i
^ 0xffff);
2918 return "moveq %1,%0\n\tnot%.w %0";
2921 return "moveq #-128,%0\n\tneg%.w %0";
2926 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2927 return "moveq %1,%0\n\tswap %0";
2930 return "move%.l %1,%0";
2936 /* Return true if I can be handled by ISA B's mov3q instruction. */
2939 valid_mov3q_const (HOST_WIDE_INT i
)
2941 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2944 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2945 I is the value of OPERANDS[1]. */
2948 output_move_simode_const (rtx
*operands
)
2954 src
= INTVAL (operands
[1]);
2956 && (DATA_REG_P (dest
) || MEM_P (dest
))
2957 /* clr insns on 68000 read before writing. */
2958 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2959 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2961 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2962 return "mov3q%.l %1,%0";
2963 else if (src
== 0 && ADDRESS_REG_P (dest
))
2964 return "sub%.l %0,%0";
2965 else if (DATA_REG_P (dest
))
2966 return output_move_const_into_data_reg (operands
);
2967 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
2969 if (valid_mov3q_const (src
))
2970 return "mov3q%.l %1,%0";
2971 return "move%.w %1,%0";
2973 else if (MEM_P (dest
)
2974 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
2975 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
2976 && IN_RANGE (src
, -0x8000, 0x7fff))
2978 if (valid_mov3q_const (src
))
2979 return "mov3q%.l %1,%-";
2982 return "move%.l %1,%0";
2986 output_move_simode (rtx
*operands
)
2988 if (GET_CODE (operands
[1]) == CONST_INT
)
2989 return output_move_simode_const (operands
);
2990 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2991 || GET_CODE (operands
[1]) == CONST
)
2992 && push_operand (operands
[0], SImode
))
2994 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
2995 || GET_CODE (operands
[1]) == CONST
)
2996 && ADDRESS_REG_P (operands
[0]))
2997 return "lea %a1,%0";
2998 return "move%.l %1,%0";
3002 output_move_himode (rtx
*operands
)
3004 if (GET_CODE (operands
[1]) == CONST_INT
)
3006 if (operands
[1] == const0_rtx
3007 && (DATA_REG_P (operands
[0])
3008 || GET_CODE (operands
[0]) == MEM
)
3009 /* clr insns on 68000 read before writing. */
3010 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3011 || !(GET_CODE (operands
[0]) == MEM
3012 && MEM_VOLATILE_P (operands
[0]))))
3014 else if (operands
[1] == const0_rtx
3015 && ADDRESS_REG_P (operands
[0]))
3016 return "sub%.l %0,%0";
3017 else if (DATA_REG_P (operands
[0])
3018 && INTVAL (operands
[1]) < 128
3019 && INTVAL (operands
[1]) >= -128)
3020 return "moveq %1,%0";
3021 else if (INTVAL (operands
[1]) < 0x8000
3022 && INTVAL (operands
[1]) >= -0x8000)
3023 return "move%.w %1,%0";
3025 else if (CONSTANT_P (operands
[1]))
3026 return "move%.l %1,%0";
3027 return "move%.w %1,%0";
3031 output_move_qimode (rtx
*operands
)
3033 /* 68k family always modifies the stack pointer by at least 2, even for
3034 byte pushes. The 5200 (ColdFire) does not do this. */
3036 /* This case is generated by pushqi1 pattern now. */
3037 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3038 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3039 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3040 && ! ADDRESS_REG_P (operands
[1])
3041 && ! TARGET_COLDFIRE
));
3043 /* clr and st insns on 68000 read before writing. */
3044 if (!ADDRESS_REG_P (operands
[0])
3045 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3046 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3048 if (operands
[1] == const0_rtx
)
3050 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3051 && GET_CODE (operands
[1]) == CONST_INT
3052 && (INTVAL (operands
[1]) & 255) == 255)
3058 if (GET_CODE (operands
[1]) == CONST_INT
3059 && DATA_REG_P (operands
[0])
3060 && INTVAL (operands
[1]) < 128
3061 && INTVAL (operands
[1]) >= -128)
3062 return "moveq %1,%0";
3063 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3064 return "sub%.l %0,%0";
3065 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3066 return "move%.l %1,%0";
3067 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3068 from address registers. */
3069 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3070 return "move%.w %1,%0";
3071 return "move%.b %1,%0";
3075 output_move_stricthi (rtx
*operands
)
3077 if (operands
[1] == const0_rtx
3078 /* clr insns on 68000 read before writing. */
3079 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3080 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3082 return "move%.w %1,%0";
3086 output_move_strictqi (rtx
*operands
)
3088 if (operands
[1] == const0_rtx
3089 /* clr insns on 68000 read before writing. */
3090 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3091 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3093 return "move%.b %1,%0";
3096 /* Return the best assembler insn template
3097 for moving operands[1] into operands[0] as a fullword. */
3100 singlemove_string (rtx
*operands
)
3102 if (GET_CODE (operands
[1]) == CONST_INT
)
3103 return output_move_simode_const (operands
);
3104 return "move%.l %1,%0";
3108 /* Output assembler or rtl code to perform a doubleword move insn
3109 with operands OPERANDS.
3110 Pointers to 3 helper functions should be specified:
3111 HANDLE_REG_ADJUST to adjust a register by a small value,
3112 HANDLE_COMPADR to compute an address and
3113 HANDLE_MOVSI to move 4 bytes. */
3116 handle_move_double (rtx operands
[2],
3117 void (*handle_reg_adjust
) (rtx
, int),
3118 void (*handle_compadr
) (rtx
[2]),
3119 void (*handle_movsi
) (rtx
[2]))
3123 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3128 rtx addreg0
= 0, addreg1
= 0;
3129 int dest_overlapped_low
= 0;
3130 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3135 /* First classify both operands. */
3137 if (REG_P (operands
[0]))
3139 else if (offsettable_memref_p (operands
[0]))
3141 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3143 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3145 else if (GET_CODE (operands
[0]) == MEM
)
3150 if (REG_P (operands
[1]))
3152 else if (CONSTANT_P (operands
[1]))
3154 else if (offsettable_memref_p (operands
[1]))
3156 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3158 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3160 else if (GET_CODE (operands
[1]) == MEM
)
3165 /* Check for the cases that the operand constraints are not supposed
3166 to allow to happen. Generating code for these cases is
3168 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3170 /* If one operand is decrementing and one is incrementing
3171 decrement the former register explicitly
3172 and change that operand into ordinary indexing. */
3174 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3176 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3178 handle_reg_adjust (operands
[0], -size
);
3180 if (GET_MODE (operands
[1]) == XFmode
)
3181 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3182 else if (GET_MODE (operands
[0]) == DFmode
)
3183 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3185 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3188 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3190 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3192 handle_reg_adjust (operands
[1], -size
);
3194 if (GET_MODE (operands
[1]) == XFmode
)
3195 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3196 else if (GET_MODE (operands
[1]) == DFmode
)
3197 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3199 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3203 /* If an operand is an unoffsettable memory ref, find a register
3204 we can increment temporarily to make it refer to the second word. */
3206 if (optype0
== MEMOP
)
3207 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3209 if (optype1
== MEMOP
)
3210 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3212 /* Ok, we can do one word at a time.
3213 Normally we do the low-numbered word first,
3214 but if either operand is autodecrementing then we
3215 do the high-numbered word first.
3217 In either case, set up in LATEHALF the operands to use
3218 for the high-numbered word and in some cases alter the
3219 operands in OPERANDS to be suitable for the low-numbered word. */
3223 if (optype0
== REGOP
)
3225 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3226 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3228 else if (optype0
== OFFSOP
)
3230 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3231 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3235 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3236 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3239 if (optype1
== REGOP
)
3241 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3242 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3244 else if (optype1
== OFFSOP
)
3246 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3247 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3249 else if (optype1
== CNSTOP
)
3251 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3256 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3257 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3258 operands
[1] = GEN_INT (l
[0]);
3259 middlehalf
[1] = GEN_INT (l
[1]);
3260 latehalf
[1] = GEN_INT (l
[2]);
3264 /* No non-CONST_DOUBLE constant should ever appear
3266 gcc_assert (!CONSTANT_P (operands
[1]));
3271 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3272 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3276 /* size is not 12: */
3278 if (optype0
== REGOP
)
3279 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3280 else if (optype0
== OFFSOP
)
3281 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3283 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3285 if (optype1
== REGOP
)
3286 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3287 else if (optype1
== OFFSOP
)
3288 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3289 else if (optype1
== CNSTOP
)
3290 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3292 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3295 /* If insn is effectively movd N(sp),-(sp) then we will do the
3296 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3297 for the low word as well, to compensate for the first decrement of sp. */
3298 if (optype0
== PUSHOP
3299 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3300 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3301 operands
[1] = middlehalf
[1] = latehalf
[1];
3303 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3304 if the upper part of reg N does not appear in the MEM, arrange to
3305 emit the move late-half first. Otherwise, compute the MEM address
3306 into the upper part of N and use that as a pointer to the memory
3308 if (optype0
== REGOP
3309 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3311 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3313 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3314 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3316 /* If both halves of dest are used in the src memory address,
3317 compute the address into latehalf of dest.
3318 Note that this can't happen if the dest is two data regs. */
3320 xops
[0] = latehalf
[0];
3321 xops
[1] = XEXP (operands
[1], 0);
3323 handle_compadr (xops
);
3324 if (GET_MODE (operands
[1]) == XFmode
)
3326 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3327 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3328 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3332 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3333 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3337 && reg_overlap_mentioned_p (middlehalf
[0],
3338 XEXP (operands
[1], 0)))
3340 /* Check for two regs used by both source and dest.
3341 Note that this can't happen if the dest is all data regs.
3342 It can happen if the dest is d6, d7, a0.
3343 But in that case, latehalf is an addr reg, so
3344 the code at compadr does ok. */
3346 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3347 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3350 /* JRV says this can't happen: */
3351 gcc_assert (!addreg0
&& !addreg1
);
3353 /* Only the middle reg conflicts; simply put it last. */
3354 handle_movsi (operands
);
3355 handle_movsi (latehalf
);
3356 handle_movsi (middlehalf
);
3360 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3361 /* If the low half of dest is mentioned in the source memory
3362 address, the arrange to emit the move late half first. */
3363 dest_overlapped_low
= 1;
3366 /* If one or both operands autodecrementing,
3367 do the two words, high-numbered first. */
3369 /* Likewise, the first move would clobber the source of the second one,
3370 do them in the other order. This happens only for registers;
3371 such overlap can't happen in memory unless the user explicitly
3372 sets it up, and that is an undefined circumstance. */
3374 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3375 || (optype0
== REGOP
&& optype1
== REGOP
3376 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3377 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3378 || dest_overlapped_low
)
3380 /* Make any unoffsettable addresses point at high-numbered word. */
3382 handle_reg_adjust (addreg0
, size
- 4);
3384 handle_reg_adjust (addreg1
, size
- 4);
3387 handle_movsi (latehalf
);
3389 /* Undo the adds we just did. */
3391 handle_reg_adjust (addreg0
, -4);
3393 handle_reg_adjust (addreg1
, -4);
3397 handle_movsi (middlehalf
);
3400 handle_reg_adjust (addreg0
, -4);
3402 handle_reg_adjust (addreg1
, -4);
3405 /* Do low-numbered word. */
3407 handle_movsi (operands
);
3411 /* Normal case: do the two words, low-numbered first. */
3413 m68k_final_prescan_insn (NULL
, operands
, 2);
3414 handle_movsi (operands
);
3416 /* Do the middle one of the three words for long double */
3420 handle_reg_adjust (addreg0
, 4);
3422 handle_reg_adjust (addreg1
, 4);
3424 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3425 handle_movsi (middlehalf
);
3428 /* Make any unoffsettable addresses point at high-numbered word. */
3430 handle_reg_adjust (addreg0
, 4);
3432 handle_reg_adjust (addreg1
, 4);
3435 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3436 handle_movsi (latehalf
);
3438 /* Undo the adds we just did. */
3440 handle_reg_adjust (addreg0
, -(size
- 4));
3442 handle_reg_adjust (addreg1
, -(size
- 4));
3447 /* Output assembler code to adjust REG by N. */
3449 output_reg_adjust (rtx reg
, int n
)
3453 gcc_assert (GET_MODE (reg
) == SImode
3454 && -12 <= n
&& n
!= 0 && n
<= 12);
3459 s
= "add%.l #12,%0";
3463 s
= "addq%.l #8,%0";
3467 s
= "addq%.l #4,%0";
3471 s
= "sub%.l #12,%0";
3475 s
= "subq%.l #8,%0";
3479 s
= "subq%.l #4,%0";
3487 output_asm_insn (s
, ®
);
3490 /* Emit rtl code to adjust REG by N. */
3492 emit_reg_adjust (rtx reg1
, int n
)
3496 gcc_assert (GET_MODE (reg1
) == SImode
3497 && -12 <= n
&& n
!= 0 && n
<= 12);
3499 reg1
= copy_rtx (reg1
);
3500 reg2
= copy_rtx (reg1
);
3503 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3505 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3510 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3512 output_compadr (rtx operands
[2])
3514 output_asm_insn ("lea %a1,%0", operands
);
3517 /* Output the best assembler insn for moving operands[1] into operands[0]
3520 output_movsi (rtx operands
[2])
3522 output_asm_insn (singlemove_string (operands
), operands
);
3525 /* Copy OP and change its mode to MODE. */
3527 copy_operand (rtx op
, enum machine_mode mode
)
3529 /* ??? This looks really ugly. There must be a better way
3530 to change a mode on the operand. */
3531 if (GET_MODE (op
) != VOIDmode
)
3534 op
= gen_rtx_REG (mode
, REGNO (op
));
3538 PUT_MODE (op
, mode
);
3545 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3547 emit_movsi (rtx operands
[2])
3549 operands
[0] = copy_operand (operands
[0], SImode
);
3550 operands
[1] = copy_operand (operands
[1], SImode
);
3552 emit_insn (gen_movsi (operands
[0], operands
[1]));
3555 /* Output assembler code to perform a doubleword move insn
3556 with operands OPERANDS. */
3558 output_move_double (rtx
*operands
)
3560 handle_move_double (operands
,
3561 output_reg_adjust
, output_compadr
, output_movsi
);
3566 /* Output rtl code to perform a doubleword move insn
3567 with operands OPERANDS. */
3569 m68k_emit_move_double (rtx operands
[2])
3571 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3574 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3575 new rtx with the correct mode. */
3578 force_mode (enum machine_mode mode
, rtx orig
)
3580 if (mode
== GET_MODE (orig
))
3583 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3586 return gen_rtx_REG (mode
, REGNO (orig
));
3590 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3592 return reg_renumber
&& FP_REG_P (op
);
3595 /* Emit insns to move operands[1] into operands[0].
3597 Return 1 if we have written out everything that needs to be done to
3598 do the move. Otherwise, return 0 and the caller will emit the move
3601 Note SCRATCH_REG may not be in the proper mode depending on how it
3602 will be used. This routine is responsible for creating a new copy
3603 of SCRATCH_REG in the proper mode. */
3606 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3608 register rtx operand0
= operands
[0];
3609 register rtx operand1
= operands
[1];
3613 && reload_in_progress
&& GET_CODE (operand0
) == REG
3614 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3615 operand0
= reg_equiv_mem (REGNO (operand0
));
3616 else if (scratch_reg
3617 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3618 && GET_CODE (SUBREG_REG (operand0
)) == REG
3619 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3621 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3622 the code which tracks sets/uses for delete_output_reload. */
3623 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3624 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3625 SUBREG_BYTE (operand0
));
3626 operand0
= alter_subreg (&temp
);
3630 && reload_in_progress
&& GET_CODE (operand1
) == REG
3631 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3632 operand1
= reg_equiv_mem (REGNO (operand1
));
3633 else if (scratch_reg
3634 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3635 && GET_CODE (SUBREG_REG (operand1
)) == REG
3636 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3638 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3639 the code which tracks sets/uses for delete_output_reload. */
3640 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3641 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3642 SUBREG_BYTE (operand1
));
3643 operand1
= alter_subreg (&temp
);
3646 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3647 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3648 != XEXP (operand0
, 0)))
3649 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3650 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3651 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3652 != XEXP (operand1
, 0)))
3653 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3655 /* Handle secondary reloads for loads/stores of FP registers where
3656 the address is symbolic by using the scratch register */
3657 if (fp_reg_operand (operand0
, mode
)
3658 && ((GET_CODE (operand1
) == MEM
3659 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3660 || ((GET_CODE (operand1
) == SUBREG
3661 && GET_CODE (XEXP (operand1
, 0)) == MEM
3662 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3665 if (GET_CODE (operand1
) == SUBREG
)
3666 operand1
= XEXP (operand1
, 0);
3668 /* SCRATCH_REG will hold an address. We want
3669 it in SImode regardless of what mode it was originally given
3671 scratch_reg
= force_mode (SImode
, scratch_reg
);
3673 /* D might not fit in 14 bits either; for such cases load D into
3675 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3677 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3678 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3680 XEXP (XEXP (operand1
, 0), 0),
3684 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3685 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3686 gen_rtx_MEM (mode
, scratch_reg
)));
3689 else if (fp_reg_operand (operand1
, mode
)
3690 && ((GET_CODE (operand0
) == MEM
3691 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3692 || ((GET_CODE (operand0
) == SUBREG
)
3693 && GET_CODE (XEXP (operand0
, 0)) == MEM
3694 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3697 if (GET_CODE (operand0
) == SUBREG
)
3698 operand0
= XEXP (operand0
, 0);
3700 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3701 it in SIMODE regardless of what mode it was originally given
3703 scratch_reg
= force_mode (SImode
, scratch_reg
);
3705 /* D might not fit in 14 bits either; for such cases load D into
3707 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3709 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3710 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3713 XEXP (XEXP (operand0
, 0),
3718 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3719 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3723 /* Handle secondary reloads for loads of FP registers from constant
3724 expressions by forcing the constant into memory.
3726 use scratch_reg to hold the address of the memory location.
3728 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3729 NO_REGS when presented with a const_int and an register class
3730 containing only FP registers. Doing so unfortunately creates
3731 more problems than it solves. Fix this for 2.5. */
3732 else if (fp_reg_operand (operand0
, mode
)
3733 && CONSTANT_P (operand1
)
3738 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3739 it in SIMODE regardless of what mode it was originally given
3741 scratch_reg
= force_mode (SImode
, scratch_reg
);
3743 /* Force the constant into memory and put the address of the
3744 memory location into scratch_reg. */
3745 xoperands
[0] = scratch_reg
;
3746 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3747 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3749 /* Now load the destination register. */
3750 emit_insn (gen_rtx_SET (mode
, operand0
,
3751 gen_rtx_MEM (mode
, scratch_reg
)));
3755 /* Now have insn-emit do whatever it normally does. */
3759 /* Split one or more DImode RTL references into pairs of SImode
3760 references. The RTL can be REG, offsettable MEM, integer constant, or
3761 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3762 split and "num" is its length. lo_half and hi_half are output arrays
3763 that parallel "operands". */
3766 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3770 rtx op
= operands
[num
];
3772 /* simplify_subreg refuses to split volatile memory addresses,
3773 but we still have to handle it. */
3774 if (GET_CODE (op
) == MEM
)
3776 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3777 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3781 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3782 GET_MODE (op
) == VOIDmode
3783 ? DImode
: GET_MODE (op
), 4);
3784 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3785 GET_MODE (op
) == VOIDmode
3786 ? DImode
: GET_MODE (op
), 0);
3791 /* Split X into a base and a constant offset, storing them in *BASE
3792 and *OFFSET respectively. */
3795 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3798 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3800 *offset
+= INTVAL (XEXP (x
, 1));
3806 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3807 instruction. STORE_P says whether the move is a load or store.
3809 If the instruction uses post-increment or pre-decrement addressing,
3810 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3811 adjustment. This adjustment will be made by the first element of
3812 PARALLEL, with the loads or stores starting at element 1. If the
3813 instruction does not use post-increment or pre-decrement addressing,
3814 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3815 start at element 0. */
3818 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3819 HOST_WIDE_INT automod_offset
, bool store_p
)
3821 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3822 HOST_WIDE_INT offset
, mem_offset
;
3824 enum reg_class rclass
;
3826 len
= XVECLEN (pattern
, 0);
3827 first
= (automod_base
!= NULL
);
3831 /* Stores must be pre-decrement and loads must be post-increment. */
3832 if (store_p
!= (automod_offset
< 0))
3835 /* Work out the base and offset for lowest memory location. */
3836 base
= automod_base
;
3837 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3841 /* Allow any valid base and offset in the first access. */
3848 for (i
= first
; i
< len
; i
++)
3850 /* We need a plain SET. */
3851 set
= XVECEXP (pattern
, 0, i
);
3852 if (GET_CODE (set
) != SET
)
3855 /* Check that we have a memory location... */
3856 mem
= XEXP (set
, !store_p
);
3857 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3860 /* ...with the right address. */
3863 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3864 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3865 There are no mode restrictions for 680x0 besides the
3866 automodification rules enforced above. */
3868 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3873 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3874 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3878 /* Check that we have a register of the required mode and class. */
3879 reg
= XEXP (set
, store_p
);
3881 || !HARD_REGISTER_P (reg
)
3882 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3887 /* The register must belong to RCLASS and have a higher number
3888 than the register in the previous SET. */
3889 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3890 || REGNO (last_reg
) >= REGNO (reg
))
3895 /* Work out which register class we need. */
3896 if (INT_REGNO_P (REGNO (reg
)))
3897 rclass
= GENERAL_REGS
;
3898 else if (FP_REGNO_P (REGNO (reg
)))
3905 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3908 /* If we have an automodification, check whether the final offset is OK. */
3909 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3912 /* Reject unprofitable cases. */
3913 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3919 /* Return the assembly code template for a movem or fmovem instruction
3920 whose pattern is given by PATTERN. Store the template's operands
3923 If the instruction uses post-increment or pre-decrement addressing,
3924 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3925 is true if this is a store instruction. */
3928 m68k_output_movem (rtx
*operands
, rtx pattern
,
3929 HOST_WIDE_INT automod_offset
, bool store_p
)
3934 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3936 first
= (automod_offset
!= 0);
3937 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3939 /* When using movem with pre-decrement addressing, register X + D0_REG
3940 is controlled by bit 15 - X. For all other addressing modes,
3941 register X + D0_REG is controlled by bit X. Confusingly, the
3942 register mask for fmovem is in the opposite order to that for
3946 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3947 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3948 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3949 if (automod_offset
< 0)
3951 if (FP_REGNO_P (regno
))
3952 mask
|= 1 << (regno
- FP0_REG
);
3954 mask
|= 1 << (15 - (regno
- D0_REG
));
3958 if (FP_REGNO_P (regno
))
3959 mask
|= 1 << (7 - (regno
- FP0_REG
));
3961 mask
|= 1 << (regno
- D0_REG
);
3966 if (automod_offset
== 0)
3967 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
3968 else if (automod_offset
< 0)
3969 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3971 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
3972 operands
[1] = GEN_INT (mask
);
3973 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
3976 return "fmovem %1,%a0";
3978 return "fmovem %a0,%1";
3983 return "movem%.l %1,%a0";
3985 return "movem%.l %a0,%1";
3989 /* Return a REG that occurs in ADDR with coefficient 1.
3990 ADDR can be effectively incremented by incrementing REG. */
3993 find_addr_reg (rtx addr
)
3995 while (GET_CODE (addr
) == PLUS
)
3997 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3998 addr
= XEXP (addr
, 0);
3999 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4000 addr
= XEXP (addr
, 1);
4001 else if (CONSTANT_P (XEXP (addr
, 0)))
4002 addr
= XEXP (addr
, 1);
4003 else if (CONSTANT_P (XEXP (addr
, 1)))
4004 addr
= XEXP (addr
, 0);
4008 gcc_assert (GET_CODE (addr
) == REG
);
4012 /* Output assembler code to perform a 32-bit 3-operand add. */
4015 output_addsi3 (rtx
*operands
)
4017 if (! operands_match_p (operands
[0], operands
[1]))
4019 if (!ADDRESS_REG_P (operands
[1]))
4021 rtx tmp
= operands
[1];
4023 operands
[1] = operands
[2];
4027 /* These insns can result from reloads to access
4028 stack slots over 64k from the frame pointer. */
4029 if (GET_CODE (operands
[2]) == CONST_INT
4030 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4031 return "move%.l %2,%0\n\tadd%.l %1,%0";
4032 if (GET_CODE (operands
[2]) == REG
)
4033 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4034 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4036 if (GET_CODE (operands
[2]) == CONST_INT
)
4038 if (INTVAL (operands
[2]) > 0
4039 && INTVAL (operands
[2]) <= 8)
4040 return "addq%.l %2,%0";
4041 if (INTVAL (operands
[2]) < 0
4042 && INTVAL (operands
[2]) >= -8)
4044 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4045 return "subq%.l %2,%0";
4047 /* On the CPU32 it is faster to use two addql instructions to
4048 add a small integer (8 < N <= 16) to a register.
4049 Likewise for subql. */
4050 if (TUNE_CPU32
&& REG_P (operands
[0]))
4052 if (INTVAL (operands
[2]) > 8
4053 && INTVAL (operands
[2]) <= 16)
4055 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4056 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4058 if (INTVAL (operands
[2]) < -8
4059 && INTVAL (operands
[2]) >= -16)
4061 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4062 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4065 if (ADDRESS_REG_P (operands
[0])
4066 && INTVAL (operands
[2]) >= -0x8000
4067 && INTVAL (operands
[2]) < 0x8000)
4070 return "add%.w %2,%0";
4072 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4075 return "add%.l %2,%0";
4078 /* Store in cc_status the expressions that the condition codes will
4079 describe after execution of an instruction whose pattern is EXP.
4080 Do not alter them if the instruction would not alter the cc's. */
4082 /* On the 68000, all the insns to store in an address register fail to
4083 set the cc's. However, in some cases these instructions can make it
4084 possibly invalid to use the saved cc's. In those cases we clear out
4085 some or all of the saved cc's so they won't be used. */
4088 notice_update_cc (rtx exp
, rtx insn
)
4090 if (GET_CODE (exp
) == SET
)
4092 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4094 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4096 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4097 cc_status
.value1
= 0;
4098 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4099 cc_status
.value2
= 0;
4101 /* fmoves to memory or data registers do not set the condition
4102 codes. Normal moves _do_ set the condition codes, but not in
4103 a way that is appropriate for comparison with 0, because -0.0
4104 would be treated as a negative nonzero number. Note that it
4105 isn't appropriate to conditionalize this restriction on
4106 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4107 we care about the difference between -0.0 and +0.0. */
4108 else if (!FP_REG_P (SET_DEST (exp
))
4109 && SET_DEST (exp
) != cc0_rtx
4110 && (FP_REG_P (SET_SRC (exp
))
4111 || GET_CODE (SET_SRC (exp
)) == FIX
4112 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4114 /* A pair of move insns doesn't produce a useful overall cc. */
4115 else if (!FP_REG_P (SET_DEST (exp
))
4116 && !FP_REG_P (SET_SRC (exp
))
4117 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4118 && (GET_CODE (SET_SRC (exp
)) == REG
4119 || GET_CODE (SET_SRC (exp
)) == MEM
4120 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4122 else if (SET_DEST (exp
) != pc_rtx
)
4124 cc_status
.flags
= 0;
4125 cc_status
.value1
= SET_DEST (exp
);
4126 cc_status
.value2
= SET_SRC (exp
);
4129 else if (GET_CODE (exp
) == PARALLEL
4130 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4132 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4133 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4135 if (ADDRESS_REG_P (dest
))
4137 else if (dest
!= pc_rtx
)
4139 cc_status
.flags
= 0;
4140 cc_status
.value1
= dest
;
4141 cc_status
.value2
= src
;
4146 if (cc_status
.value2
!= 0
4147 && ADDRESS_REG_P (cc_status
.value2
)
4148 && GET_MODE (cc_status
.value2
) == QImode
)
4150 if (cc_status
.value2
!= 0)
4151 switch (GET_CODE (cc_status
.value2
))
4153 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4154 case ROTATE
: case ROTATERT
:
4155 /* These instructions always clear the overflow bit, and set
4156 the carry to the bit shifted out. */
4157 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4160 case PLUS
: case MINUS
: case MULT
:
4161 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4162 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4163 cc_status
.flags
|= CC_NO_OVERFLOW
;
4166 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4167 ends with a move insn moving r2 in r2's mode.
4168 Thus, the cc's are set for r2.
4169 This can set N bit spuriously. */
4170 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4175 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4177 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4178 cc_status
.value2
= 0;
4179 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4180 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4181 cc_status
.flags
= CC_IN_68881
;
4182 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4183 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4185 cc_status
.flags
= CC_IN_68881
;
4186 if (!FP_REG_P (XEXP (cc_status
.value2
, 0)))
4187 cc_status
.flags
|= CC_REVERSED
;
4192 output_move_const_double (rtx
*operands
)
4194 int code
= standard_68881_constant_p (operands
[1]);
4198 static char buf
[40];
4200 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4203 return "fmove%.d %1,%0";
4207 output_move_const_single (rtx
*operands
)
4209 int code
= standard_68881_constant_p (operands
[1]);
4213 static char buf
[40];
4215 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4218 return "fmove%.s %f1,%0";
4221 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4222 from the "fmovecr" instruction.
4223 The value, anded with 0xff, gives the code to use in fmovecr
4224 to get the desired constant. */
4226 /* This code has been fixed for cross-compilation. */
4228 static int inited_68881_table
= 0;
4230 static const char *const strings_68881
[7] = {
4240 static const int codes_68881
[7] = {
4250 REAL_VALUE_TYPE values_68881
[7];
4252 /* Set up values_68881 array by converting the decimal values
4253 strings_68881 to binary. */
4256 init_68881_table (void)
4260 enum machine_mode mode
;
4263 for (i
= 0; i
< 7; i
++)
4267 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4268 values_68881
[i
] = r
;
4270 inited_68881_table
= 1;
4274 standard_68881_constant_p (rtx x
)
4279 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4280 used at all on those chips. */
4284 if (! inited_68881_table
)
4285 init_68881_table ();
4287 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4289 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4291 for (i
= 0; i
< 6; i
++)
4293 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4294 return (codes_68881
[i
]);
4297 if (GET_MODE (x
) == SFmode
)
4300 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4301 return (codes_68881
[6]);
4303 /* larger powers of ten in the constants ram are not used
4304 because they are not equal to a `double' C constant. */
4308 /* If X is a floating-point constant, return the logarithm of X base 2,
4309 or 0 if X is not a power of 2. */
4312 floating_exact_log2 (rtx x
)
4314 REAL_VALUE_TYPE r
, r1
;
4317 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4319 if (REAL_VALUES_LESS (r
, dconst1
))
4322 exp
= real_exponent (&r
);
4323 real_2expN (&r1
, exp
, DFmode
);
4324 if (REAL_VALUES_EQUAL (r1
, r
))
4330 /* A C compound statement to output to stdio stream STREAM the
4331 assembler syntax for an instruction operand X. X is an RTL
4334 CODE is a value that can be used to specify one of several ways
4335 of printing the operand. It is used when identical operands
4336 must be printed differently depending on the context. CODE
4337 comes from the `%' specification that was used to request
4338 printing of the operand. If the specification was just `%DIGIT'
4339 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4340 is the ASCII code for LTR.
4342 If X is a register, this macro should print the register's name.
4343 The names can be found in an array `reg_names' whose type is
4344 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4346 When the machine description has a specification `%PUNCT' (a `%'
4347 followed by a punctuation character), this macro is called with
4348 a null pointer for X and the punctuation character for CODE.
4350 The m68k specific codes are:
4352 '.' for dot needed in Motorola-style opcode names.
4353 '-' for an operand pushing on the stack:
4354 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4355 '+' for an operand pushing on the stack:
4356 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4357 '@' for a reference to the top word on the stack:
4358 sp@, (sp) or (%sp) depending on the style of syntax.
4359 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4360 but & in SGS syntax).
4361 '!' for the cc register (used in an `and to cc' insn).
4362 '$' for the letter `s' in an op code, but only on the 68040.
4363 '&' for the letter `d' in an op code, but only on the 68040.
4364 '/' for register prefix needed by longlong.h.
4365 '?' for m68k_library_id_string
4367 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4368 'd' to force memory addressing to be absolute, not relative.
4369 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4370 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4371 or print pair of registers as rx:ry.
4372 'p' print an address with @PLTPC attached, but only if the operand
4373 is not locally-bound. */
4376 print_operand (FILE *file
, rtx op
, int letter
)
4381 fprintf (file
, ".");
4383 else if (letter
== '#')
4384 asm_fprintf (file
, "%I");
4385 else if (letter
== '-')
4386 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4387 else if (letter
== '+')
4388 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4389 else if (letter
== '@')
4390 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4391 else if (letter
== '!')
4392 asm_fprintf (file
, "%Rfpcr");
4393 else if (letter
== '$')
4396 fprintf (file
, "s");
4398 else if (letter
== '&')
4401 fprintf (file
, "d");
4403 else if (letter
== '/')
4404 asm_fprintf (file
, "%R");
4405 else if (letter
== '?')
4406 asm_fprintf (file
, m68k_library_id_string
);
4407 else if (letter
== 'p')
4409 output_addr_const (file
, op
);
4410 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4411 fprintf (file
, "@PLTPC");
4413 else if (GET_CODE (op
) == REG
)
4416 /* Print out the second register name of a register pair.
4417 I.e., R (6) => 7. */
4418 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4420 fputs (M68K_REGNAME(REGNO (op
)), file
);
4422 else if (GET_CODE (op
) == MEM
)
4424 output_address (XEXP (op
, 0));
4425 if (letter
== 'd' && ! TARGET_68020
4426 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4427 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4428 && INTVAL (XEXP (op
, 0)) < 0x8000
4429 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4430 fprintf (file
, MOTOROLA
? ".l" : ":l");
4432 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4436 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4437 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4438 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4440 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4444 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4445 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4446 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4447 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4449 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4453 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4454 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4455 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4459 /* Use `print_operand_address' instead of `output_addr_const'
4460 to ensure that we print relevant PIC stuff. */
4461 asm_fprintf (file
, "%I");
4463 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4464 print_operand_address (file
, op
);
4466 output_addr_const (file
, op
);
4470 /* Return string for TLS relocation RELOC. */
4473 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4475 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4476 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4483 if (flag_pic
== 1 && TARGET_68020
)
4524 /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */
4527 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4529 if (GET_CODE (x
) == UNSPEC
)
4531 switch (XINT (x
, 1))
4533 case UNSPEC_RELOC16
:
4534 case UNSPEC_RELOC32
:
4535 output_addr_const (file
, XVECEXP (x
, 0, 0));
4536 fputs (m68k_get_reloc_decoration
4537 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4548 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4551 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4553 gcc_assert (size
== 4);
4554 fputs ("\t.long\t", file
);
4555 output_addr_const (file
, x
);
4556 fputs ("@TLSLDO+0x8000", file
);
4559 /* In the name of slightly smaller debug output, and to cater to
4560 general assembler lossage, recognize various UNSPEC sequences
4561 and turn them back into a direct symbol reference. */
4564 m68k_delegitimize_address (rtx orig_x
)
4567 struct m68k_address addr
;
4570 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4575 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4578 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4579 || addr
.offset
== NULL_RTX
4580 || GET_CODE (addr
.offset
) != CONST
)
4583 unspec
= XEXP (addr
.offset
, 0);
4584 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4585 unspec
= XEXP (unspec
, 0);
4586 if (GET_CODE (unspec
) != UNSPEC
4587 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4588 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4590 x
= XVECEXP (unspec
, 0, 0);
4591 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4592 if (unspec
!= XEXP (addr
.offset
, 0))
4593 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4596 rtx idx
= addr
.index
;
4597 if (addr
.scale
!= 1)
4598 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4599 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4602 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4604 x
= replace_equiv_address_nv (orig_x
, x
);
4609 /* A C compound statement to output to stdio stream STREAM the
4610 assembler syntax for an instruction operand that is a memory
4611 reference whose address is ADDR. ADDR is an RTL expression.
4613 Note that this contains a kludge that knows that the only reason
4614 we have an address (plus (label_ref...) (reg...)) when not generating
4615 PIC code is in the insn before a tablejump, and we know that m68k.md
4616 generates a label LInnn: on such an insn.
4618 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4619 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4621 This routine is responsible for distinguishing between -fpic and -fPIC
4622 style relocations in an address. When generating -fpic code the
4623 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4624 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4627 print_operand_address (FILE *file
, rtx addr
)
4629 struct m68k_address address
;
4631 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4634 if (address
.code
== PRE_DEC
)
4635 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4636 M68K_REGNAME (REGNO (address
.base
)));
4637 else if (address
.code
== POST_INC
)
4638 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4639 M68K_REGNAME (REGNO (address
.base
)));
4640 else if (!address
.base
&& !address
.index
)
4642 /* A constant address. */
4643 gcc_assert (address
.offset
== addr
);
4644 if (GET_CODE (addr
) == CONST_INT
)
4646 /* (xxx).w or (xxx).l. */
4647 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4648 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4650 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4652 else if (TARGET_PCREL
)
4654 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4656 output_addr_const (file
, addr
);
4657 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4661 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4662 name ends in `.<letter>', as the last 2 characters can be
4663 mistaken as a size suffix. Put the name in parentheses. */
4664 if (GET_CODE (addr
) == SYMBOL_REF
4665 && strlen (XSTR (addr
, 0)) > 2
4666 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4669 output_addr_const (file
, addr
);
4673 output_addr_const (file
, addr
);
4680 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4681 label being accessed, otherwise it is -1. */
4682 labelno
= (address
.offset
4684 && GET_CODE (address
.offset
) == LABEL_REF
4685 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4689 /* Print the "offset(base" component. */
4691 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4695 output_addr_const (file
, address
.offset
);
4699 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4701 /* Print the ",index" component, if any. */
4706 fprintf (file
, "%s.%c",
4707 M68K_REGNAME (REGNO (address
.index
)),
4708 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4709 if (address
.scale
!= 1)
4710 fprintf (file
, "*%d", address
.scale
);
4714 else /* !MOTOROLA */
4716 if (!address
.offset
&& !address
.index
)
4717 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4720 /* Print the "base@(offset" component. */
4722 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4726 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4727 fprintf (file
, "@(");
4729 output_addr_const (file
, address
.offset
);
4731 /* Print the ",index" component, if any. */
4734 fprintf (file
, ",%s:%c",
4735 M68K_REGNAME (REGNO (address
.index
)),
4736 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4737 if (address
.scale
!= 1)
4738 fprintf (file
, ":%d", address
.scale
);
4746 /* Check for cases where a clr insns can be omitted from code using
4747 strict_low_part sets. For example, the second clrl here is not needed:
4748 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4750 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4751 insn we are checking for redundancy. TARGET is the register set by the
4755 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4760 while ((p
= PREV_INSN (p
)))
4762 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4768 /* If it isn't an insn, then give up. */
4772 if (reg_set_p (target
, p
))
4774 rtx set
= single_set (p
);
4777 /* If it isn't an easy to recognize insn, then give up. */
4781 dest
= SET_DEST (set
);
4783 /* If this sets the entire target register to zero, then our
4784 first_insn is redundant. */
4785 if (rtx_equal_p (dest
, target
)
4786 && SET_SRC (set
) == const0_rtx
)
4788 else if (GET_CODE (dest
) == STRICT_LOW_PART
4789 && GET_CODE (XEXP (dest
, 0)) == REG
4790 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4791 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4792 <= GET_MODE_SIZE (mode
)))
4793 /* This is a strict low part set which modifies less than
4794 we are using, so it is safe. */
4804 /* Operand predicates for implementing asymmetric pc-relative addressing
4805 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4806 when used as a source operand, but not as a destination operand.
4808 We model this by restricting the meaning of the basic predicates
4809 (general_operand, memory_operand, etc) to forbid the use of this
4810 addressing mode, and then define the following predicates that permit
4811 this addressing mode. These predicates can then be used for the
4812 source operands of the appropriate instructions.
4814 n.b. While it is theoretically possible to change all machine patterns
4815 to use this addressing more where permitted by the architecture,
4816 it has only been implemented for "common" cases: SImode, HImode, and
4817 QImode operands, and only for the principle operations that would
4818 require this addressing mode: data movement and simple integer operations.
4820 In parallel with these new predicates, two new constraint letters
4821 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4822 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4823 In the pcrel case 's' is only valid in combination with 'a' registers.
4824 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4825 of how these constraints are used.
4827 The use of these predicates is strictly optional, though patterns that
4828 don't will cause an extra reload register to be allocated where one
4831 lea (abc:w,%pc),%a0 ; need to reload address
4832 moveq &1,%d1 ; since write to pc-relative space
4833 movel %d1,%a0@ ; is not allowed
4835 lea (abc:w,%pc),%a1 ; no need to reload address here
4836 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4838 For more info, consult tiemann@cygnus.com.
4841 All of the ugliness with predicates and constraints is due to the
4842 simple fact that the m68k does not allow a pc-relative addressing
4843 mode as a destination. gcc does not distinguish between source and
4844 destination addresses. Hence, if we claim that pc-relative address
4845 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4846 end up with invalid code. To get around this problem, we left
4847 pc-relative modes as invalid addresses, and then added special
4848 predicates and constraints to accept them.
4850 A cleaner way to handle this is to modify gcc to distinguish
4851 between source and destination addresses. We can then say that
4852 pc-relative is a valid source address but not a valid destination
4853 address, and hopefully avoid a lot of the predicate and constraint
4854 hackery. Unfortunately, this would be a pretty big change. It would
4855 be a useful change for a number of ports, but there aren't any current
4856 plans to undertake this.
4858 ***************************************************************************/
4862 output_andsi3 (rtx
*operands
)
4865 if (GET_CODE (operands
[2]) == CONST_INT
4866 && (INTVAL (operands
[2]) | 0xffff) == -1
4867 && (DATA_REG_P (operands
[0])
4868 || offsettable_memref_p (operands
[0]))
4869 && !TARGET_COLDFIRE
)
4871 if (GET_CODE (operands
[0]) != REG
)
4872 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4873 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4874 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4876 if (operands
[2] == const0_rtx
)
4878 return "and%.w %2,%0";
4880 if (GET_CODE (operands
[2]) == CONST_INT
4881 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4882 && (DATA_REG_P (operands
[0])
4883 || offsettable_memref_p (operands
[0])))
4885 if (DATA_REG_P (operands
[0]))
4886 operands
[1] = GEN_INT (logval
);
4889 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4890 operands
[1] = GEN_INT (logval
% 8);
4892 /* This does not set condition codes in a standard way. */
4894 return "bclr %1,%0";
4896 return "and%.l %2,%0";
4900 output_iorsi3 (rtx
*operands
)
4902 register int logval
;
4903 if (GET_CODE (operands
[2]) == CONST_INT
4904 && INTVAL (operands
[2]) >> 16 == 0
4905 && (DATA_REG_P (operands
[0])
4906 || offsettable_memref_p (operands
[0]))
4907 && !TARGET_COLDFIRE
)
4909 if (GET_CODE (operands
[0]) != REG
)
4910 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4911 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4913 if (INTVAL (operands
[2]) == 0xffff)
4914 return "mov%.w %2,%0";
4915 return "or%.w %2,%0";
4917 if (GET_CODE (operands
[2]) == CONST_INT
4918 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4919 && (DATA_REG_P (operands
[0])
4920 || offsettable_memref_p (operands
[0])))
4922 if (DATA_REG_P (operands
[0]))
4923 operands
[1] = GEN_INT (logval
);
4926 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4927 operands
[1] = GEN_INT (logval
% 8);
4930 return "bset %1,%0";
4932 return "or%.l %2,%0";
4936 output_xorsi3 (rtx
*operands
)
4938 register int logval
;
4939 if (GET_CODE (operands
[2]) == CONST_INT
4940 && INTVAL (operands
[2]) >> 16 == 0
4941 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4942 && !TARGET_COLDFIRE
)
4944 if (! DATA_REG_P (operands
[0]))
4945 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4946 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4948 if (INTVAL (operands
[2]) == 0xffff)
4950 return "eor%.w %2,%0";
4952 if (GET_CODE (operands
[2]) == CONST_INT
4953 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4954 && (DATA_REG_P (operands
[0])
4955 || offsettable_memref_p (operands
[0])))
4957 if (DATA_REG_P (operands
[0]))
4958 operands
[1] = GEN_INT (logval
);
4961 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4962 operands
[1] = GEN_INT (logval
% 8);
4965 return "bchg %1,%0";
4967 return "eor%.l %2,%0";
4970 /* Return the instruction that should be used for a call to address X,
4971 which is known to be in operand 0. */
4976 if (symbolic_operand (x
, VOIDmode
))
4977 return m68k_symbolic_call
;
4982 /* Likewise sibling calls. */
4985 output_sibcall (rtx x
)
4987 if (symbolic_operand (x
, VOIDmode
))
4988 return m68k_symbolic_jump
;
4994 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
4995 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
4998 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5000 /* Avoid clobbering the struct value reg by using the
5001 static chain reg as a temporary. */
5002 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5004 /* Pretend to be a post-reload pass while generating rtl. */
5005 reload_completed
= 1;
5007 /* The "this" pointer is stored at 4(%sp). */
5008 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
5010 /* Add DELTA to THIS. */
5013 /* Make the offset a legitimate operand for memory addition. */
5014 offset
= GEN_INT (delta
);
5015 if ((delta
< -8 || delta
> 8)
5016 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5018 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5019 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5021 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5022 copy_rtx (this_slot
), offset
));
5025 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5026 if (vcall_offset
!= 0)
5028 /* Set the static chain register to *THIS. */
5029 emit_move_insn (tmp
, this_slot
);
5030 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5032 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5033 addr
= plus_constant (tmp
, vcall_offset
);
5034 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5036 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5040 /* Load the offset into %d0 and add it to THIS. */
5041 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5042 gen_rtx_MEM (Pmode
, addr
));
5043 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5044 copy_rtx (this_slot
),
5045 gen_rtx_REG (Pmode
, D0_REG
)));
5048 /* Jump to the target function. Use a sibcall if direct jumps are
5049 allowed, otherwise load the address into a register first. */
5050 mem
= DECL_RTL (function
);
5051 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5053 gcc_assert (flag_pic
);
5055 if (!TARGET_SEP_DATA
)
5057 /* Use the static chain register as a temporary (call-clobbered)
5058 GOT pointer for this function. We can use the static chain
5059 register because it isn't live on entry to the thunk. */
5060 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5061 emit_insn (gen_load_got (pic_offset_table_rtx
));
5063 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5064 mem
= replace_equiv_address (mem
, tmp
);
5066 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5067 SIBLING_CALL_P (insn
) = 1;
5069 /* Run just enough of rest_of_compilation. */
5070 insn
= get_insns ();
5071 split_all_insns_noflow ();
5072 final_start_function (insn
, file
, 1);
5073 final (insn
, file
, 1);
5074 final_end_function ();
5076 /* Clean up the vars set above. */
5077 reload_completed
= 0;
5079 /* Restore the original PIC register. */
5081 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5084 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5087 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5088 int incoming ATTRIBUTE_UNUSED
)
5090 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5093 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5095 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5096 unsigned int new_reg
)
5099 /* Interrupt functions can only use registers that have already been
5100 saved by the prologue, even if they would normally be
5103 if ((m68k_get_function_kind (current_function_decl
)
5104 == m68k_fk_interrupt_handler
)
5105 && !df_regs_ever_live_p (new_reg
))
5111 /* Value is true if hard register REGNO can hold a value of machine-mode
5112 MODE. On the 68000, we let the cpu registers can hold any mode, but
5113 restrict the 68881 registers to floating-point modes. */
5116 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5118 if (DATA_REGNO_P (regno
))
5120 /* Data Registers, can hold aggregate if fits in. */
5121 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5124 else if (ADDRESS_REGNO_P (regno
))
5126 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5129 else if (FP_REGNO_P (regno
))
5131 /* FPU registers, hold float or complex float of long double or
5133 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5134 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5135 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5141 /* Implement SECONDARY_RELOAD_CLASS. */
5144 m68k_secondary_reload_class (enum reg_class rclass
,
5145 enum machine_mode mode
, rtx x
)
5149 regno
= true_regnum (x
);
5151 /* If one operand of a movqi is an address register, the other
5152 operand must be a general register or constant. Other types
5153 of operand must be reloaded through a data register. */
5154 if (GET_MODE_SIZE (mode
) == 1
5155 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5156 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5159 /* PC-relative addresses must be loaded into an address register first. */
5161 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5162 && symbolic_operand (x
, VOIDmode
))
5168 /* Implement PREFERRED_RELOAD_CLASS. */
5171 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5173 enum reg_class secondary_class
;
5175 /* If RCLASS might need a secondary reload, try restricting it to
5176 a class that doesn't. */
5177 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5178 if (secondary_class
!= NO_REGS
5179 && reg_class_subset_p (secondary_class
, rclass
))
5180 return secondary_class
;
5182 /* Prefer to use moveq for in-range constants. */
5183 if (GET_CODE (x
) == CONST_INT
5184 && reg_class_subset_p (DATA_REGS
, rclass
)
5185 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5188 /* ??? Do we really need this now? */
5189 if (GET_CODE (x
) == CONST_DOUBLE
5190 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5192 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5201 /* Return floating point values in a 68881 register. This makes 68881 code
5202 a little bit faster. It also makes -msoft-float code incompatible with
5203 hard-float code, so people have to be careful not to mix the two.
5204 For ColdFire it was decided the ABI incompatibility is undesirable.
5205 If there is need for a hard-float ABI it is probably worth doing it
5206 properly and also passing function arguments in FP registers. */
5208 m68k_libcall_value (enum machine_mode mode
)
5215 return gen_rtx_REG (mode
, FP0_REG
);
5221 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5224 /* Location in which function value is returned.
5225 NOTE: Due to differences in ABIs, don't call this function directly,
5226 use FUNCTION_VALUE instead. */
5228 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5230 enum machine_mode mode
;
5232 mode
= TYPE_MODE (valtype
);
5238 return gen_rtx_REG (mode
, FP0_REG
);
5244 /* If the function returns a pointer, push that into %a0. */
5245 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5246 /* For compatibility with the large body of existing code which
5247 does not always properly declare external functions returning
5248 pointer types, the m68k/SVR4 convention is to copy the value
5249 returned for pointer functions from a0 to d0 in the function
5250 epilogue, so that callers that have neglected to properly
5251 declare the callee can still find the correct return value in
5253 return gen_rtx_PARALLEL
5256 gen_rtx_EXPR_LIST (VOIDmode
,
5257 gen_rtx_REG (mode
, A0_REG
),
5259 gen_rtx_EXPR_LIST (VOIDmode
,
5260 gen_rtx_REG (mode
, D0_REG
),
5262 else if (POINTER_TYPE_P (valtype
))
5263 return gen_rtx_REG (mode
, A0_REG
);
5265 return gen_rtx_REG (mode
, D0_REG
);
5268 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5269 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5271 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5273 enum machine_mode mode
= TYPE_MODE (type
);
5275 if (mode
== BLKmode
)
5278 /* If TYPE's known alignment is less than the alignment of MODE that
5279 would contain the structure, then return in memory. We need to
5280 do so to maintain the compatibility between code compiled with
5281 -mstrict-align and that compiled with -mno-strict-align. */
5282 if (AGGREGATE_TYPE_P (type
)
5283 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5290 /* CPU to schedule the program for. */
5291 enum attr_cpu m68k_sched_cpu
;
5293 /* MAC to schedule the program for. */
5294 enum attr_mac m68k_sched_mac
;
5302 /* Integer register. */
5308 /* Implicit mem reference (e.g. stack). */
5311 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5314 /* Memory with offset but without indexing. EA mode 5. */
5317 /* Memory with indexing. EA mode 6. */
5320 /* Memory referenced by absolute address. EA mode 7. */
5323 /* Immediate operand that doesn't require extension word. */
5326 /* Immediate 16 bit operand. */
5329 /* Immediate 32 bit operand. */
5333 /* Return type of memory ADDR_RTX refers to. */
5334 static enum attr_op_type
5335 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5337 struct m68k_address address
;
5339 if (symbolic_operand (addr_rtx
, VOIDmode
))
5340 return OP_TYPE_MEM7
;
5342 if (!m68k_decompose_address (mode
, addr_rtx
,
5343 reload_completed
, &address
))
5345 gcc_assert (!reload_completed
);
5346 /* Reload will likely fix the address to be in the register. */
5347 return OP_TYPE_MEM234
;
5350 if (address
.scale
!= 0)
5351 return OP_TYPE_MEM6
;
5353 if (address
.base
!= NULL_RTX
)
5355 if (address
.offset
== NULL_RTX
)
5356 return OP_TYPE_MEM234
;
5358 return OP_TYPE_MEM5
;
5361 gcc_assert (address
.offset
!= NULL_RTX
);
5363 return OP_TYPE_MEM7
;
5366 /* Return X or Y (depending on OPX_P) operand of INSN. */
5368 sched_get_operand (rtx insn
, bool opx_p
)
5372 if (recog_memoized (insn
) < 0)
5375 extract_constrain_insn_cached (insn
);
5378 i
= get_attr_opx (insn
);
5380 i
= get_attr_opy (insn
);
5382 if (i
>= recog_data
.n_operands
)
5385 return recog_data
.operand
[i
];
5388 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5389 If ADDRESS_P is true, return type of memory location operand refers to. */
5390 static enum attr_op_type
5391 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5395 op
= sched_get_operand (insn
, opx_p
);
5399 gcc_assert (!reload_completed
);
5404 return sched_address_type (QImode
, op
);
5406 if (memory_operand (op
, VOIDmode
))
5407 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5409 if (register_operand (op
, VOIDmode
))
5411 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5412 || (reload_completed
&& FP_REG_P (op
)))
5418 if (GET_CODE (op
) == CONST_INT
)
5424 /* Check for quick constants. */
5425 switch (get_attr_type (insn
))
5428 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5429 return OP_TYPE_IMM_Q
;
5431 gcc_assert (!reload_completed
);
5435 if (USE_MOVQ (ival
))
5436 return OP_TYPE_IMM_Q
;
5438 gcc_assert (!reload_completed
);
5442 if (valid_mov3q_const (ival
))
5443 return OP_TYPE_IMM_Q
;
5445 gcc_assert (!reload_completed
);
5452 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5453 return OP_TYPE_IMM_W
;
5455 return OP_TYPE_IMM_L
;
5458 if (GET_CODE (op
) == CONST_DOUBLE
)
5460 switch (GET_MODE (op
))
5463 return OP_TYPE_IMM_W
;
5467 return OP_TYPE_IMM_L
;
5474 if (GET_CODE (op
) == CONST
5475 || symbolic_operand (op
, VOIDmode
)
5478 switch (GET_MODE (op
))
5481 return OP_TYPE_IMM_Q
;
5484 return OP_TYPE_IMM_W
;
5487 return OP_TYPE_IMM_L
;
5490 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5492 return OP_TYPE_IMM_W
;
5494 return OP_TYPE_IMM_L
;
5498 gcc_assert (!reload_completed
);
5500 if (FLOAT_MODE_P (GET_MODE (op
)))
5506 /* Implement opx_type attribute.
5507 Return type of INSN's operand X.
5508 If ADDRESS_P is true, return type of memory location operand refers to. */
5510 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5512 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5518 return OPX_TYPE_FPN
;
5521 return OPX_TYPE_MEM1
;
5523 case OP_TYPE_MEM234
:
5524 return OPX_TYPE_MEM234
;
5527 return OPX_TYPE_MEM5
;
5530 return OPX_TYPE_MEM6
;
5533 return OPX_TYPE_MEM7
;
5536 return OPX_TYPE_IMM_Q
;
5539 return OPX_TYPE_IMM_W
;
5542 return OPX_TYPE_IMM_L
;
5549 /* Implement opy_type attribute.
5550 Return type of INSN's operand Y.
5551 If ADDRESS_P is true, return type of memory location operand refers to. */
5553 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5555 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5561 return OPY_TYPE_FPN
;
5564 return OPY_TYPE_MEM1
;
5566 case OP_TYPE_MEM234
:
5567 return OPY_TYPE_MEM234
;
5570 return OPY_TYPE_MEM5
;
5573 return OPY_TYPE_MEM6
;
5576 return OPY_TYPE_MEM7
;
5579 return OPY_TYPE_IMM_Q
;
5582 return OPY_TYPE_IMM_W
;
5585 return OPY_TYPE_IMM_L
;
5592 /* Return size of INSN as int. */
5594 sched_get_attr_size_int (rtx insn
)
5598 switch (get_attr_type (insn
))
5601 /* There should be no references to m68k_sched_attr_size for 'ignore'
5615 switch (get_attr_opx_type (insn
))
5621 case OPX_TYPE_MEM234
:
5622 case OPY_TYPE_IMM_Q
:
5627 /* Here we assume that most absolute references are short. */
5629 case OPY_TYPE_IMM_W
:
5633 case OPY_TYPE_IMM_L
:
5641 switch (get_attr_opy_type (insn
))
5647 case OPY_TYPE_MEM234
:
5648 case OPY_TYPE_IMM_Q
:
5653 /* Here we assume that most absolute references are short. */
5655 case OPY_TYPE_IMM_W
:
5659 case OPY_TYPE_IMM_L
:
5669 gcc_assert (!reload_completed
);
5677 /* Return size of INSN as attribute enum value. */
5679 m68k_sched_attr_size (rtx insn
)
5681 switch (sched_get_attr_size_int (insn
))
5697 /* Return operand X or Y (depending on OPX_P) of INSN,
5698 if it is a MEM, or NULL overwise. */
5699 static enum attr_op_type
5700 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5704 switch (get_attr_opx_type (insn
))
5709 case OPX_TYPE_IMM_Q
:
5710 case OPX_TYPE_IMM_W
:
5711 case OPX_TYPE_IMM_L
:
5715 case OPX_TYPE_MEM234
:
5718 return OP_TYPE_MEM1
;
5721 return OP_TYPE_MEM6
;
5729 switch (get_attr_opy_type (insn
))
5734 case OPY_TYPE_IMM_Q
:
5735 case OPY_TYPE_IMM_W
:
5736 case OPY_TYPE_IMM_L
:
5740 case OPY_TYPE_MEM234
:
5743 return OP_TYPE_MEM1
;
5746 return OP_TYPE_MEM6
;
5754 /* Implement op_mem attribute. */
5756 m68k_sched_attr_op_mem (rtx insn
)
5758 enum attr_op_type opx
;
5759 enum attr_op_type opy
;
5761 opx
= sched_get_opxy_mem_type (insn
, true);
5762 opy
= sched_get_opxy_mem_type (insn
, false);
5764 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5767 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5769 switch (get_attr_opx_access (insn
))
5785 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5787 switch (get_attr_opx_access (insn
))
5803 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5806 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5808 switch (get_attr_opx_access (insn
))
5814 gcc_assert (!reload_completed
);
5819 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5821 switch (get_attr_opx_access (insn
))
5827 gcc_assert (!reload_completed
);
5832 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5835 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5837 switch (get_attr_opx_access (insn
))
5843 gcc_assert (!reload_completed
);
5848 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5849 gcc_assert (!reload_completed
);
5853 /* Jump instructions types. Indexed by INSN_UID.
5854 The same rtl insn can be expanded into different asm instructions
5855 depending on the cc0_status. To properly determine type of jump
5856 instructions we scan instruction stream and map jumps types to this
5858 static enum attr_type
*sched_branch_type
;
5860 /* Return the type of the jump insn. */
5862 m68k_sched_branch_type (rtx insn
)
5864 enum attr_type type
;
5866 type
= sched_branch_type
[INSN_UID (insn
)];
5868 gcc_assert (type
!= 0);
5873 /* Data for ColdFire V4 index bypass.
5874 Producer modifies register that is used as index in consumer with
5878 /* Producer instruction. */
5881 /* Consumer instruction. */
5884 /* Scale of indexed memory access within consumer.
5885 Or zero if bypass should not be effective at the moment. */
5887 } sched_cfv4_bypass_data
;
5889 /* An empty state that is used in m68k_sched_adjust_cost. */
5890 static state_t sched_adjust_cost_state
;
5892 /* Implement adjust_cost scheduler hook.
5893 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5895 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5900 if (recog_memoized (def_insn
) < 0
5901 || recog_memoized (insn
) < 0)
5904 if (sched_cfv4_bypass_data
.scale
== 1)
5905 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5907 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5908 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5909 that the data in sched_cfv4_bypass_data is up to date. */
5910 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5911 && sched_cfv4_bypass_data
.con
== insn
);
5916 sched_cfv4_bypass_data
.pro
= NULL
;
5917 sched_cfv4_bypass_data
.con
= NULL
;
5918 sched_cfv4_bypass_data
.scale
= 0;
5921 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5922 && sched_cfv4_bypass_data
.con
== NULL
5923 && sched_cfv4_bypass_data
.scale
== 0);
5925 /* Don't try to issue INSN earlier than DFA permits.
5926 This is especially useful for instructions that write to memory,
5927 as their true dependence (default) latency is better to be set to 0
5928 to workaround alias analysis limitations.
5929 This is, in fact, a machine independent tweak, so, probably,
5930 it should be moved to haifa-sched.c: insn_cost (). */
5931 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5938 /* Return maximal number of insns that can be scheduled on a single cycle. */
5940 m68k_sched_issue_rate (void)
5942 switch (m68k_sched_cpu
)
5958 /* Maximal length of instruction for current CPU.
5959 E.g. it is 3 for any ColdFire core. */
5960 static int max_insn_size
;
5962 /* Data to model instruction buffer of CPU. */
5965 /* True if instruction buffer model is modeled for current CPU. */
5968 /* Size of the instruction buffer in words. */
5971 /* Number of filled words in the instruction buffer. */
5974 /* Additional information about instruction buffer for CPUs that have
5975 a buffer of instruction records, rather then a plain buffer
5976 of instruction words. */
5977 struct _sched_ib_records
5979 /* Size of buffer in records. */
5982 /* Array to hold data on adjustements made to the size of the buffer. */
5985 /* Index of the above array. */
5989 /* An insn that reserves (marks empty) one word in the instruction buffer. */
5993 static struct _sched_ib sched_ib
;
5995 /* ID of memory unit. */
5996 static int sched_mem_unit_code
;
5998 /* Implementation of the targetm.sched.variable_issue () hook.
5999 It is called after INSN was issued. It returns the number of insns
6000 that can possibly get scheduled on the current cycle.
6001 It is used here to determine the effect of INSN on the instruction
6004 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6005 int sched_verbose ATTRIBUTE_UNUSED
,
6006 rtx insn
, int can_issue_more
)
6010 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6012 switch (m68k_sched_cpu
)
6016 insn_size
= sched_get_attr_size_int (insn
);
6020 insn_size
= sched_get_attr_size_int (insn
);
6022 /* ColdFire V3 and V4 cores have instruction buffers that can
6023 accumulate up to 8 instructions regardless of instructions'
6024 sizes. So we should take care not to "prefetch" 24 one-word
6025 or 12 two-words instructions.
6026 To model this behavior we temporarily decrease size of the
6027 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6031 adjust
= max_insn_size
- insn_size
;
6032 sched_ib
.size
-= adjust
;
6034 if (sched_ib
.filled
> sched_ib
.size
)
6035 sched_ib
.filled
= sched_ib
.size
;
6037 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6040 ++sched_ib
.records
.adjust_index
;
6041 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6042 sched_ib
.records
.adjust_index
= 0;
6044 /* Undo adjustement we did 7 instructions ago. */
6046 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6051 gcc_assert (!sched_ib
.enabled_p
);
6059 if (insn_size
> sched_ib
.filled
)
6060 /* Scheduling for register pressure does not always take DFA into
6061 account. Workaround instruction buffer not being filled enough. */
6063 gcc_assert (sched_pressure_p
);
6064 insn_size
= sched_ib
.filled
;
6069 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6070 || asm_noperands (PATTERN (insn
)) >= 0)
6071 insn_size
= sched_ib
.filled
;
6075 sched_ib
.filled
-= insn_size
;
6077 return can_issue_more
;
6080 /* Return how many instructions should scheduler lookahead to choose the
6083 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6085 return m68k_sched_issue_rate () - 1;
6088 /* Implementation of targetm.sched.init_global () hook.
6089 It is invoked once per scheduling pass and is used here
6090 to initialize scheduler constants. */
6092 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6093 int sched_verbose ATTRIBUTE_UNUSED
,
6094 int n_insns ATTRIBUTE_UNUSED
)
6096 /* Init branch types. */
6100 sched_branch_type
= XCNEWVEC (enum attr_type
, get_max_uid () + 1);
6102 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6105 /* !!! FIXME: Implement real scan here. */
6106 sched_branch_type
[INSN_UID (insn
)] = TYPE_BCC
;
6110 #ifdef ENABLE_CHECKING
6111 /* Check that all instructions have DFA reservations and
6112 that all instructions can be issued from a clean state. */
6117 state
= alloca (state_size ());
6119 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6121 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6123 gcc_assert (insn_has_dfa_reservation_p (insn
));
6125 state_reset (state
);
6126 if (state_transition (state
, insn
) >= 0)
6133 /* Setup target cpu. */
6135 /* ColdFire V4 has a set of features to keep its instruction buffer full
6136 (e.g., a separate memory bus for instructions) and, hence, we do not model
6137 buffer for this CPU. */
6138 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6140 switch (m68k_sched_cpu
)
6143 sched_ib
.filled
= 0;
6150 sched_ib
.records
.n_insns
= 0;
6151 sched_ib
.records
.adjust
= NULL
;
6156 sched_ib
.records
.n_insns
= 8;
6157 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6164 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6166 sched_adjust_cost_state
= xmalloc (state_size ());
6167 state_reset (sched_adjust_cost_state
);
6170 emit_insn (gen_ib ());
6171 sched_ib
.insn
= get_insns ();
6175 /* Scheduling pass is now finished. Free/reset static variables. */
6177 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6178 int verbose ATTRIBUTE_UNUSED
)
6180 sched_ib
.insn
= NULL
;
6182 free (sched_adjust_cost_state
);
6183 sched_adjust_cost_state
= NULL
;
6185 sched_mem_unit_code
= 0;
6187 free (sched_ib
.records
.adjust
);
6188 sched_ib
.records
.adjust
= NULL
;
6189 sched_ib
.records
.n_insns
= 0;
6192 free (sched_branch_type
);
6193 sched_branch_type
= NULL
;
6196 /* Implementation of targetm.sched.init () hook.
6197 It is invoked each time scheduler starts on the new block (basic block or
6198 extended basic block). */
6200 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6201 int sched_verbose ATTRIBUTE_UNUSED
,
6202 int n_insns ATTRIBUTE_UNUSED
)
6204 switch (m68k_sched_cpu
)
6212 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6214 memset (sched_ib
.records
.adjust
, 0,
6215 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6216 sched_ib
.records
.adjust_index
= 0;
6220 gcc_assert (!sched_ib
.enabled_p
);
6228 if (sched_ib
.enabled_p
)
6229 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6230 the first cycle. Workaround that. */
6231 sched_ib
.filled
= -2;
6234 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6235 It is invoked just before current cycle finishes and is used here
6236 to track if instruction buffer got its two words this cycle. */
6238 m68k_sched_dfa_pre_advance_cycle (void)
6240 if (!sched_ib
.enabled_p
)
6243 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6245 sched_ib
.filled
+= 2;
6247 if (sched_ib
.filled
> sched_ib
.size
)
6248 sched_ib
.filled
= sched_ib
.size
;
6252 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6253 It is invoked just after new cycle begins and is used here
6254 to setup number of filled words in the instruction buffer so that
6255 instructions which won't have all their words prefetched would be
6256 stalled for a cycle. */
6258 m68k_sched_dfa_post_advance_cycle (void)
6262 if (!sched_ib
.enabled_p
)
6265 /* Setup number of prefetched instruction words in the instruction
6267 i
= max_insn_size
- sched_ib
.filled
;
6271 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6276 /* Return X or Y (depending on OPX_P) operand of INSN,
6277 if it is an integer register, or NULL overwise. */
6279 sched_get_reg_operand (rtx insn
, bool opx_p
)
6285 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6287 op
= sched_get_operand (insn
, true);
6288 gcc_assert (op
!= NULL
);
6290 if (!reload_completed
&& !REG_P (op
))
6296 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6298 op
= sched_get_operand (insn
, false);
6299 gcc_assert (op
!= NULL
);
6301 if (!reload_completed
&& !REG_P (op
))
6309 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6312 sched_mem_operand_p (rtx insn
, bool opx_p
)
6314 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6325 /* Return X or Y (depending on OPX_P) operand of INSN,
6326 if it is a MEM, or NULL overwise. */
6328 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6348 if (opy_p
&& sched_mem_operand_p (insn
, false))
6349 return sched_get_operand (insn
, false);
6351 if (opx_p
&& sched_mem_operand_p (insn
, true))
6352 return sched_get_operand (insn
, true);
6358 /* Return non-zero if PRO modifies register used as part of
6361 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6366 pro_x
= sched_get_reg_operand (pro
, true);
6370 con_mem_read
= sched_get_mem_operand (con
, true, false);
6371 gcc_assert (con_mem_read
!= NULL
);
6373 if (reg_mentioned_p (pro_x
, con_mem_read
))
6379 /* Helper function for m68k_sched_indexed_address_bypass_p.
6380 if PRO modifies register used as index in CON,
6381 return scale of indexed memory access in CON. Return zero overwise. */
6383 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6387 struct m68k_address address
;
6389 reg
= sched_get_reg_operand (pro
, true);
6393 mem
= sched_get_mem_operand (con
, true, false);
6394 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6396 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6400 if (REGNO (reg
) == REGNO (address
.index
))
6402 gcc_assert (address
.scale
!= 0);
6403 return address
.scale
;
6409 /* Return non-zero if PRO modifies register used
6410 as index with scale 2 or 4 in CON. */
6412 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6414 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6415 && sched_cfv4_bypass_data
.con
== NULL
6416 && sched_cfv4_bypass_data
.scale
== 0);
6418 switch (sched_get_indexed_address_scale (pro
, con
))
6421 /* We can't have a variable latency bypass, so
6422 remember to adjust the insn cost in adjust_cost hook. */
6423 sched_cfv4_bypass_data
.pro
= pro
;
6424 sched_cfv4_bypass_data
.con
= con
;
6425 sched_cfv4_bypass_data
.scale
= 1;
6437 /* We generate a two-instructions program at M_TRAMP :
6438 movea.l &CHAIN_VALUE,%a0
6440 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6443 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6445 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6448 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6450 mem
= adjust_address (m_tramp
, HImode
, 0);
6451 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6452 mem
= adjust_address (m_tramp
, SImode
, 2);
6453 emit_move_insn (mem
, chain_value
);
6455 mem
= adjust_address (m_tramp
, HImode
, 6);
6456 emit_move_insn (mem
, GEN_INT(0x4EF9));
6457 mem
= adjust_address (m_tramp
, SImode
, 8);
6458 emit_move_insn (mem
, fnaddr
);
6460 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6463 /* On the 68000, the RTS insn cannot pop anything.
6464 On the 68010, the RTD insn may be used to pop them if the number
6465 of args is fixed, but if the number is variable then the caller
6466 must pop them all. RTD can't be used for library calls now
6467 because the library is compiled with the Unix compiler.
6468 Use of RTD is a selectable option, since it is incompatible with
6469 standard Unix calling sequences. If the option is not selected,
6470 the caller must always pop the args. */
6473 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6477 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6478 && (!stdarg_p (funtype
)))
6482 /* Make sure everything's fine if we *don't* have a given processor.
6483 This assumes that putting a register in fixed_regs will keep the
6484 compiler's mitts completely off it. We don't bother to zero it out
6485 of register classes. */
6488 m68k_conditional_register_usage (void)
6492 if (!TARGET_HARD_FLOAT
)
6494 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6495 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6496 if (TEST_HARD_REG_BIT (x
, i
))
6497 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6500 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6503 #include "gt-m68k.h"