1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
46 #include "sched-int.h"
47 #include "insn-codes.h"
52 enum reg_class regno_reg_class
[] =
54 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
55 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
56 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
57 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
58 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
59 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
64 /* The minimum number of integer registers that we want to save with the
65 movem instruction. Using two movel instructions instead of a single
66 moveml is about 15% faster for the 68020 and 68030 at no expense in
68 #define MIN_MOVEM_REGS 3
70 /* The minimum number of floating point registers that we want to save
71 with the fmovem instruction. */
72 #define MIN_FMOVEM_REGS 1
74 /* Structure describing stack frame layout. */
77 /* Stack pointer to frame pointer offset. */
80 /* Offset of FPU registers. */
81 HOST_WIDE_INT foffset
;
83 /* Frame size in bytes (rounded up). */
86 /* Data and address register. */
88 unsigned int reg_mask
;
92 unsigned int fpu_mask
;
94 /* Offsets relative to ARG_POINTER. */
95 HOST_WIDE_INT frame_pointer_offset
;
96 HOST_WIDE_INT stack_pointer_offset
;
98 /* Function which the above information refers to. */
102 /* Current frame information calculated by m68k_compute_frame_layout(). */
103 static struct m68k_frame current_frame
;
105 /* Structure describing an m68k address.
107 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
108 with null fields evaluating to 0. Here:
110 - BASE satisfies m68k_legitimate_base_reg_p
111 - INDEX satisfies m68k_legitimate_index_reg_p
112 - OFFSET satisfies m68k_legitimate_constant_address_p
114 INDEX is either HImode or SImode. The other fields are SImode.
116 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
117 the address is (BASE)+. */
118 struct m68k_address
{
126 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
127 static int m68k_sched_issue_rate (void);
128 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
129 static void m68k_sched_md_init_global (FILE *, int, int);
130 static void m68k_sched_md_finish_global (FILE *, int);
131 static void m68k_sched_md_init (FILE *, int, int);
132 static void m68k_sched_dfa_pre_advance_cycle (void);
133 static void m68k_sched_dfa_post_advance_cycle (void);
134 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
136 static bool m68k_can_eliminate (const int, const int);
137 static void m68k_conditional_register_usage (void);
138 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
139 static void m68k_option_override (void);
140 static void m68k_override_options_after_change (void);
141 static rtx
find_addr_reg (rtx
);
142 static const char *singlemove_string (rtx
*);
143 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
144 HOST_WIDE_INT
, tree
);
145 static rtx
m68k_struct_value_rtx (tree
, int);
146 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
147 tree args
, int flags
,
149 static void m68k_compute_frame_layout (void);
150 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
151 static bool m68k_ok_for_sibcall_p (tree
, tree
);
152 static bool m68k_tls_symbol_p (rtx
);
153 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
154 static bool m68k_rtx_costs (rtx
, int, int, int, int *, bool);
155 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
156 static bool m68k_return_in_memory (const_tree
, const_tree
);
158 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
159 static void m68k_trampoline_init (rtx
, tree
, rtx
);
160 static int m68k_return_pops_args (tree
, tree
, int);
161 static rtx
m68k_delegitimize_address (rtx
);
162 static void m68k_function_arg_advance (cumulative_args_t
, enum machine_mode
,
164 static rtx
m68k_function_arg (cumulative_args_t
, enum machine_mode
,
166 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
167 static bool m68k_output_addr_const_extra (FILE *, rtx
);
168 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
170 /* Initialize the GCC target structure. */
172 #if INT_OP_GROUP == INT_OP_DOT_WORD
173 #undef TARGET_ASM_ALIGNED_HI_OP
174 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
177 #if INT_OP_GROUP == INT_OP_NO_DOT
178 #undef TARGET_ASM_BYTE_OP
179 #define TARGET_ASM_BYTE_OP "\tbyte\t"
180 #undef TARGET_ASM_ALIGNED_HI_OP
181 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
182 #undef TARGET_ASM_ALIGNED_SI_OP
183 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
186 #if INT_OP_GROUP == INT_OP_DC
187 #undef TARGET_ASM_BYTE_OP
188 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
189 #undef TARGET_ASM_ALIGNED_HI_OP
190 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
191 #undef TARGET_ASM_ALIGNED_SI_OP
192 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
195 #undef TARGET_ASM_UNALIGNED_HI_OP
196 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
197 #undef TARGET_ASM_UNALIGNED_SI_OP
198 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
200 #undef TARGET_ASM_OUTPUT_MI_THUNK
201 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
202 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
203 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
205 #undef TARGET_ASM_FILE_START_APP_OFF
206 #define TARGET_ASM_FILE_START_APP_OFF true
208 #undef TARGET_LEGITIMIZE_ADDRESS
209 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
211 #undef TARGET_SCHED_ADJUST_COST
212 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
214 #undef TARGET_SCHED_ISSUE_RATE
215 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
217 #undef TARGET_SCHED_VARIABLE_ISSUE
218 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
220 #undef TARGET_SCHED_INIT_GLOBAL
221 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
223 #undef TARGET_SCHED_FINISH_GLOBAL
224 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
226 #undef TARGET_SCHED_INIT
227 #define TARGET_SCHED_INIT m68k_sched_md_init
229 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
230 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
232 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
233 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
235 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
236 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
237 m68k_sched_first_cycle_multipass_dfa_lookahead
239 #undef TARGET_OPTION_OVERRIDE
240 #define TARGET_OPTION_OVERRIDE m68k_option_override
242 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
243 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
245 #undef TARGET_RTX_COSTS
246 #define TARGET_RTX_COSTS m68k_rtx_costs
248 #undef TARGET_ATTRIBUTE_TABLE
249 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
251 #undef TARGET_PROMOTE_PROTOTYPES
252 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
254 #undef TARGET_STRUCT_VALUE_RTX
255 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
257 #undef TARGET_CANNOT_FORCE_CONST_MEM
258 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
260 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
261 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
263 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
264 #undef TARGET_RETURN_IN_MEMORY
265 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
269 #undef TARGET_HAVE_TLS
270 #define TARGET_HAVE_TLS (true)
272 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
273 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
276 #undef TARGET_LEGITIMATE_ADDRESS_P
277 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
279 #undef TARGET_CAN_ELIMINATE
280 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
282 #undef TARGET_CONDITIONAL_REGISTER_USAGE
283 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
285 #undef TARGET_TRAMPOLINE_INIT
286 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
288 #undef TARGET_RETURN_POPS_ARGS
289 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
291 #undef TARGET_DELEGITIMIZE_ADDRESS
292 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
294 #undef TARGET_FUNCTION_ARG
295 #define TARGET_FUNCTION_ARG m68k_function_arg
297 #undef TARGET_FUNCTION_ARG_ADVANCE
298 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
300 #undef TARGET_LEGITIMATE_CONSTANT_P
301 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
303 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
304 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
306 /* The value stored by TAS. */
307 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
308 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
310 static const struct attribute_spec m68k_attribute_table
[] =
312 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
313 affects_type_identity } */
314 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
316 { "interrupt_handler", 0, 0, true, false, false,
317 m68k_handle_fndecl_attribute
, false },
318 { "interrupt_thread", 0, 0, true, false, false,
319 m68k_handle_fndecl_attribute
, false },
320 { NULL
, 0, 0, false, false, false, NULL
, false }
323 struct gcc_target targetm
= TARGET_INITIALIZER
;
325 /* Base flags for 68k ISAs. */
326 #define FL_FOR_isa_00 FL_ISA_68000
327 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
328 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
329 generated 68881 code for 68020 and 68030 targets unless explicitly told
331 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
332 | FL_BITFIELD | FL_68881 | FL_CAS)
333 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
334 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
336 /* Base flags for ColdFire ISAs. */
337 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
338 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
339 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
340 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
341 /* ISA_C is not upwardly compatible with ISA_B. */
342 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
346 /* Traditional 68000 instruction sets. */
352 /* ColdFire instruction set variants. */
360 /* Information about one of the -march, -mcpu or -mtune arguments. */
361 struct m68k_target_selection
363 /* The argument being described. */
366 /* For -mcpu, this is the device selected by the option.
367 For -mtune and -march, it is a representative device
368 for the microarchitecture or ISA respectively. */
369 enum target_device device
;
371 /* The M68K_DEVICE fields associated with DEVICE. See the comment
372 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
374 enum uarch_type microarch
;
379 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
380 static const struct m68k_target_selection all_devices
[] =
382 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
383 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
384 #include "m68k-devices.def"
386 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
389 /* A list of all ISAs, mapping each one to a representative device.
390 Used for -march selection. */
391 static const struct m68k_target_selection all_isas
[] =
393 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
394 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
395 #include "m68k-isas.def"
397 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
400 /* A list of all microarchitectures, mapping each one to a representative
401 device. Used for -mtune selection. */
402 static const struct m68k_target_selection all_microarchs
[] =
404 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
405 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
406 #include "m68k-microarchs.def"
407 #undef M68K_MICROARCH
408 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
411 /* The entries associated with the -mcpu, -march and -mtune settings,
412 or null for options that have not been used. */
413 const struct m68k_target_selection
*m68k_cpu_entry
;
414 const struct m68k_target_selection
*m68k_arch_entry
;
415 const struct m68k_target_selection
*m68k_tune_entry
;
417 /* Which CPU we are generating code for. */
418 enum target_device m68k_cpu
;
420 /* Which microarchitecture to tune for. */
421 enum uarch_type m68k_tune
;
423 /* Which FPU to use. */
424 enum fpu_type m68k_fpu
;
426 /* The set of FL_* flags that apply to the target processor. */
427 unsigned int m68k_cpu_flags
;
429 /* The set of FL_* flags that apply to the processor to be tuned for. */
430 unsigned int m68k_tune_flags
;
432 /* Asm templates for calling or jumping to an arbitrary symbolic address,
433 or NULL if such calls or jumps are not supported. The address is held
435 const char *m68k_symbolic_call
;
436 const char *m68k_symbolic_jump
;
438 /* Enum variable that corresponds to m68k_symbolic_call values. */
439 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
442 /* Implement TARGET_OPTION_OVERRIDE. */
445 m68k_option_override (void)
447 const struct m68k_target_selection
*entry
;
448 unsigned long target_mask
;
450 if (global_options_set
.x_m68k_arch_option
)
451 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
453 if (global_options_set
.x_m68k_cpu_option
)
454 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
456 if (global_options_set
.x_m68k_tune_option
)
457 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
465 -march=ARCH should generate code that runs any processor
466 implementing architecture ARCH. -mcpu=CPU should override -march
467 and should generate code that runs on processor CPU, making free
468 use of any instructions that CPU understands. -mtune=UARCH applies
469 on top of -mcpu or -march and optimizes the code for UARCH. It does
470 not change the target architecture. */
473 /* Complain if the -march setting is for a different microarchitecture,
474 or includes flags that the -mcpu setting doesn't. */
476 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
477 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
478 warning (0, "-mcpu=%s conflicts with -march=%s",
479 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
481 entry
= m68k_cpu_entry
;
484 entry
= m68k_arch_entry
;
487 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
489 m68k_cpu_flags
= entry
->flags
;
491 /* Use the architecture setting to derive default values for
495 /* ColdFire is lenient about alignment. */
496 if (!TARGET_COLDFIRE
)
497 target_mask
|= MASK_STRICT_ALIGNMENT
;
499 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
500 target_mask
|= MASK_BITFIELD
;
501 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
502 target_mask
|= MASK_CF_HWDIV
;
503 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
504 target_mask
|= MASK_HARD_FLOAT
;
505 target_flags
|= target_mask
& ~target_flags_explicit
;
507 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
508 m68k_cpu
= entry
->device
;
511 m68k_tune
= m68k_tune_entry
->microarch
;
512 m68k_tune_flags
= m68k_tune_entry
->flags
;
514 #ifdef M68K_DEFAULT_TUNE
515 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
517 enum target_device dev
;
518 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
519 m68k_tune_flags
= all_devices
[dev
]->flags
;
524 m68k_tune
= entry
->microarch
;
525 m68k_tune_flags
= entry
->flags
;
528 /* Set the type of FPU. */
529 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
530 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
533 /* Sanity check to ensure that msep-data and mid-sahred-library are not
534 * both specified together. Doing so simply doesn't make sense.
536 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
537 error ("cannot specify both -msep-data and -mid-shared-library");
539 /* If we're generating code for a separate A5 relative data segment,
540 * we've got to enable -fPIC as well. This might be relaxable to
541 * -fpic but it hasn't been tested properly.
543 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
546 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
547 error if the target does not support them. */
548 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
549 error ("-mpcrel -fPIC is not currently supported on selected cpu");
551 /* ??? A historic way of turning on pic, or is this intended to
552 be an embedded thing that doesn't have the same name binding
553 significance that it does on hosted ELF systems? */
554 if (TARGET_PCREL
&& flag_pic
== 0)
559 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
561 m68k_symbolic_jump
= "jra %a0";
563 else if (TARGET_ID_SHARED_LIBRARY
)
564 /* All addresses must be loaded from the GOT. */
566 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
569 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
571 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
574 /* No unconditional long branch */;
575 else if (TARGET_PCREL
)
576 m68k_symbolic_jump
= "bra%.l %c0";
578 m68k_symbolic_jump
= "bra%.l %p0";
579 /* Turn off function cse if we are doing PIC. We always want
580 function call to be done as `bsr foo@PLTPC'. */
581 /* ??? It's traditional to do this for -mpcrel too, but it isn't
582 clear how intentional that is. */
583 flag_no_function_cse
= 1;
586 switch (m68k_symbolic_call_var
)
588 case M68K_SYMBOLIC_CALL_JSR
:
589 m68k_symbolic_call
= "jsr %a0";
592 case M68K_SYMBOLIC_CALL_BSR_C
:
593 m68k_symbolic_call
= "bsr%.l %c0";
596 case M68K_SYMBOLIC_CALL_BSR_P
:
597 m68k_symbolic_call
= "bsr%.l %p0";
600 case M68K_SYMBOLIC_CALL_NONE
:
601 gcc_assert (m68k_symbolic_call
== NULL
);
608 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
609 if (align_labels
> 2)
611 warning (0, "-falign-labels=%d is not supported", align_labels
);
616 warning (0, "-falign-loops=%d is not supported", align_loops
);
621 if (stack_limit_rtx
!= NULL_RTX
&& !TARGET_68020
)
623 warning (0, "-fstack-limit- options are not supported on this cpu");
624 stack_limit_rtx
= NULL_RTX
;
627 SUBTARGET_OVERRIDE_OPTIONS
;
629 /* Setup scheduling options. */
631 m68k_sched_cpu
= CPU_CFV1
;
633 m68k_sched_cpu
= CPU_CFV2
;
635 m68k_sched_cpu
= CPU_CFV3
;
637 m68k_sched_cpu
= CPU_CFV4
;
640 m68k_sched_cpu
= CPU_UNKNOWN
;
641 flag_schedule_insns
= 0;
642 flag_schedule_insns_after_reload
= 0;
643 flag_modulo_sched
= 0;
646 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
648 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
649 m68k_sched_mac
= MAC_CF_EMAC
;
650 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
651 m68k_sched_mac
= MAC_CF_MAC
;
653 m68k_sched_mac
= MAC_NO
;
657 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
660 m68k_override_options_after_change (void)
662 if (m68k_sched_cpu
== CPU_UNKNOWN
)
664 flag_schedule_insns
= 0;
665 flag_schedule_insns_after_reload
= 0;
666 flag_modulo_sched
= 0;
670 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
671 given argument and NAME is the argument passed to -mcpu. Return NULL
672 if -mcpu was not passed. */
675 m68k_cpp_cpu_ident (const char *prefix
)
679 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
682 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
683 given argument and NAME is the name of the representative device for
684 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
687 m68k_cpp_cpu_family (const char *prefix
)
691 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
694 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
695 "interrupt_handler" attribute and interrupt_thread if FUNC has an
696 "interrupt_thread" attribute. Otherwise, return
697 m68k_fk_normal_function. */
699 enum m68k_function_kind
700 m68k_get_function_kind (tree func
)
704 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
706 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
708 return m68k_fk_interrupt_handler
;
710 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
712 return m68k_fk_interrupt_handler
;
714 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
716 return m68k_fk_interrupt_thread
;
718 return m68k_fk_normal_function
;
721 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
722 struct attribute_spec.handler. */
724 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
725 tree args ATTRIBUTE_UNUSED
,
726 int flags ATTRIBUTE_UNUSED
,
729 if (TREE_CODE (*node
) != FUNCTION_DECL
)
731 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
733 *no_add_attrs
= true;
736 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
738 error ("multiple interrupt attributes not allowed");
739 *no_add_attrs
= true;
743 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
745 error ("interrupt_thread is available only on fido");
746 *no_add_attrs
= true;
753 m68k_compute_frame_layout (void)
757 enum m68k_function_kind func_kind
=
758 m68k_get_function_kind (current_function_decl
);
759 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
760 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
762 /* Only compute the frame once per function.
763 Don't cache information until reload has been completed. */
764 if (current_frame
.funcdef_no
== current_function_funcdef_no
768 current_frame
.size
= (get_frame_size () + 3) & -4;
772 /* Interrupt thread does not need to save any register. */
773 if (!interrupt_thread
)
774 for (regno
= 0; regno
< 16; regno
++)
775 if (m68k_save_reg (regno
, interrupt_handler
))
777 mask
|= 1 << (regno
- D0_REG
);
780 current_frame
.offset
= saved
* 4;
781 current_frame
.reg_no
= saved
;
782 current_frame
.reg_mask
= mask
;
784 current_frame
.foffset
= 0;
786 if (TARGET_HARD_FLOAT
)
788 /* Interrupt thread does not need to save any register. */
789 if (!interrupt_thread
)
790 for (regno
= 16; regno
< 24; regno
++)
791 if (m68k_save_reg (regno
, interrupt_handler
))
793 mask
|= 1 << (regno
- FP0_REG
);
796 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
797 current_frame
.offset
+= current_frame
.foffset
;
799 current_frame
.fpu_no
= saved
;
800 current_frame
.fpu_mask
= mask
;
802 /* Remember what function this frame refers to. */
803 current_frame
.funcdef_no
= current_function_funcdef_no
;
806 /* Worker function for TARGET_CAN_ELIMINATE. */
809 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
811 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
815 m68k_initial_elimination_offset (int from
, int to
)
818 /* The arg pointer points 8 bytes before the start of the arguments,
819 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
820 frame pointer in most frames. */
821 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
822 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
823 return argptr_offset
;
825 m68k_compute_frame_layout ();
827 gcc_assert (to
== STACK_POINTER_REGNUM
);
830 case ARG_POINTER_REGNUM
:
831 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
832 case FRAME_POINTER_REGNUM
:
833 return current_frame
.offset
+ current_frame
.size
;
839 /* Refer to the array `regs_ever_live' to determine which registers
840 to save; `regs_ever_live[I]' is nonzero if register number I
841 is ever used in the function. This function is responsible for
842 knowing which registers should not be saved even if used.
843 Return true if we need to save REGNO. */
846 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
848 if (flag_pic
&& regno
== PIC_REG
)
850 if (crtl
->saves_all_registers
)
852 if (crtl
->uses_pic_offset_table
)
854 /* Reload may introduce constant pool references into a function
855 that thitherto didn't need a PIC register. Note that the test
856 above will not catch that case because we will only set
857 crtl->uses_pic_offset_table when emitting
858 the address reloads. */
859 if (crtl
->uses_const_pool
)
863 if (crtl
->calls_eh_return
)
868 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
869 if (test
== INVALID_REGNUM
)
876 /* Fixed regs we never touch. */
877 if (fixed_regs
[regno
])
880 /* The frame pointer (if it is such) is handled specially. */
881 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
884 /* Interrupt handlers must also save call_used_regs
885 if they are live or when calling nested functions. */
886 if (interrupt_handler
)
888 if (df_regs_ever_live_p (regno
))
891 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
895 /* Never need to save registers that aren't touched. */
896 if (!df_regs_ever_live_p (regno
))
899 /* Otherwise save everything that isn't call-clobbered. */
900 return !call_used_regs
[regno
];
903 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
904 the lowest memory address. COUNT is the number of registers to be
905 moved, with register REGNO + I being moved if bit I of MASK is set.
906 STORE_P specifies the direction of the move and ADJUST_STACK_P says
907 whether or not this is pre-decrement (if STORE_P) or post-increment
908 (if !STORE_P) operation. */
911 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
912 unsigned int count
, unsigned int regno
,
913 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
916 rtx body
, addr
, src
, operands
[2];
917 enum machine_mode mode
;
919 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
920 mode
= reg_raw_mode
[regno
];
925 src
= plus_constant (Pmode
, base
,
927 * GET_MODE_SIZE (mode
)
928 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
929 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
932 for (; mask
!= 0; mask
>>= 1, regno
++)
935 addr
= plus_constant (Pmode
, base
, offset
);
936 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
937 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
938 XVECEXP (body
, 0, i
++)
939 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
940 offset
+= GET_MODE_SIZE (mode
);
942 gcc_assert (i
== XVECLEN (body
, 0));
944 return emit_insn (body
);
947 /* Make INSN a frame-related instruction. */
950 m68k_set_frame_related (rtx insn
)
955 RTX_FRAME_RELATED_P (insn
) = 1;
956 body
= PATTERN (insn
);
957 if (GET_CODE (body
) == PARALLEL
)
958 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
959 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
962 /* Emit RTL for the "prologue" define_expand. */
965 m68k_expand_prologue (void)
967 HOST_WIDE_INT fsize_with_regs
;
968 rtx limit
, src
, dest
;
970 m68k_compute_frame_layout ();
972 if (flag_stack_usage_info
)
973 current_function_static_stack_size
974 = current_frame
.size
+ current_frame
.offset
;
976 /* If the stack limit is a symbol, we can check it here,
977 before actually allocating the space. */
978 if (crtl
->limit_stack
979 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
981 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
982 if (!m68k_legitimate_constant_p (Pmode
, limit
))
984 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
985 limit
= gen_rtx_REG (Pmode
, D0_REG
);
987 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
988 stack_pointer_rtx
, limit
),
989 stack_pointer_rtx
, limit
,
993 fsize_with_regs
= current_frame
.size
;
996 /* ColdFire's move multiple instructions do not allow pre-decrement
997 addressing. Add the size of movem saves to the initial stack
998 allocation instead. */
999 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1000 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1001 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1002 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1005 if (frame_pointer_needed
)
1007 if (fsize_with_regs
== 0 && TUNE_68040
)
1009 /* On the 68040, two separate moves are faster than link.w 0. */
1010 dest
= gen_frame_mem (Pmode
,
1011 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1012 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1013 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1014 stack_pointer_rtx
));
1016 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1017 m68k_set_frame_related
1018 (emit_insn (gen_link (frame_pointer_rtx
,
1019 GEN_INT (-4 - fsize_with_regs
))));
1022 m68k_set_frame_related
1023 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1024 m68k_set_frame_related
1025 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1027 GEN_INT (-fsize_with_regs
))));
1030 /* If the frame pointer is needed, emit a special barrier that
1031 will prevent the scheduler from moving stores to the frame
1032 before the stack adjustment. */
1033 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1035 else if (fsize_with_regs
!= 0)
1036 m68k_set_frame_related
1037 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1039 GEN_INT (-fsize_with_regs
))));
1041 if (current_frame
.fpu_mask
)
1043 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1045 m68k_set_frame_related
1046 (m68k_emit_movem (stack_pointer_rtx
,
1047 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1048 current_frame
.fpu_no
, FP0_REG
,
1049 current_frame
.fpu_mask
, true, true));
1054 /* If we're using moveml to save the integer registers,
1055 the stack pointer will point to the bottom of the moveml
1056 save area. Find the stack offset of the first FP register. */
1057 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1060 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1061 m68k_set_frame_related
1062 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1063 current_frame
.fpu_no
, FP0_REG
,
1064 current_frame
.fpu_mask
, true, false));
1068 /* If the stack limit is not a symbol, check it here.
1069 This has the disadvantage that it may be too late... */
1070 if (crtl
->limit_stack
)
1072 if (REG_P (stack_limit_rtx
))
1073 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1075 stack_pointer_rtx
, stack_limit_rtx
,
1078 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1079 warning (0, "stack limit expression is not supported");
1082 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1084 /* Store each register separately in the same order moveml does. */
1087 for (i
= 16; i
-- > 0; )
1088 if (current_frame
.reg_mask
& (1 << i
))
1090 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1091 dest
= gen_frame_mem (SImode
,
1092 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1093 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1098 if (TARGET_COLDFIRE
)
1099 /* The required register save space has already been allocated.
1100 The first register should be stored at (%sp). */
1101 m68k_set_frame_related
1102 (m68k_emit_movem (stack_pointer_rtx
, 0,
1103 current_frame
.reg_no
, D0_REG
,
1104 current_frame
.reg_mask
, true, false));
1106 m68k_set_frame_related
1107 (m68k_emit_movem (stack_pointer_rtx
,
1108 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1109 current_frame
.reg_no
, D0_REG
,
1110 current_frame
.reg_mask
, true, true));
1113 if (!TARGET_SEP_DATA
1114 && crtl
->uses_pic_offset_table
)
1115 emit_insn (gen_load_got (pic_offset_table_rtx
));
1118 /* Return true if a simple (return) instruction is sufficient for this
1119 instruction (i.e. if no epilogue is needed). */
1122 m68k_use_return_insn (void)
1124 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1127 m68k_compute_frame_layout ();
1128 return current_frame
.offset
== 0;
1131 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1132 SIBCALL_P says which.
1134 The function epilogue should not depend on the current stack pointer!
1135 It should use the frame pointer only, if there is a frame pointer.
1136 This is mandatory because of alloca; we also take advantage of it to
1137 omit stack adjustments before returning. */
1140 m68k_expand_epilogue (bool sibcall_p
)
1142 HOST_WIDE_INT fsize
, fsize_with_regs
;
1143 bool big
, restore_from_sp
;
1145 m68k_compute_frame_layout ();
1147 fsize
= current_frame
.size
;
1149 restore_from_sp
= false;
1151 /* FIXME : crtl->is_leaf below is too strong.
1152 What we really need to know there is if there could be pending
1153 stack adjustment needed at that point. */
1154 restore_from_sp
= (!frame_pointer_needed
1155 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1157 /* fsize_with_regs is the size we need to adjust the sp when
1158 popping the frame. */
1159 fsize_with_regs
= fsize
;
1160 if (TARGET_COLDFIRE
&& restore_from_sp
)
1162 /* ColdFire's move multiple instructions do not allow post-increment
1163 addressing. Add the size of movem loads to the final deallocation
1165 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1166 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1167 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1168 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1171 if (current_frame
.offset
+ fsize
>= 0x8000
1173 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1176 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1177 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1179 /* ColdFire's move multiple instructions do not support the
1180 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1181 stack-based restore. */
1182 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1183 GEN_INT (-(current_frame
.offset
+ fsize
)));
1184 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1185 gen_rtx_REG (Pmode
, A1_REG
),
1186 frame_pointer_rtx
));
1187 restore_from_sp
= true;
1191 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1197 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1199 /* Restore each register separately in the same order moveml does. */
1201 HOST_WIDE_INT offset
;
1203 offset
= current_frame
.offset
+ fsize
;
1204 for (i
= 0; i
< 16; i
++)
1205 if (current_frame
.reg_mask
& (1 << i
))
1211 /* Generate the address -OFFSET(%fp,%a1.l). */
1212 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1213 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1214 addr
= plus_constant (Pmode
, addr
, -offset
);
1216 else if (restore_from_sp
)
1217 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1219 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1220 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1221 gen_frame_mem (SImode
, addr
));
1222 offset
-= GET_MODE_SIZE (SImode
);
1225 else if (current_frame
.reg_mask
)
1228 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1229 gen_rtx_REG (Pmode
, A1_REG
),
1231 -(current_frame
.offset
+ fsize
),
1232 current_frame
.reg_no
, D0_REG
,
1233 current_frame
.reg_mask
, false, false);
1234 else if (restore_from_sp
)
1235 m68k_emit_movem (stack_pointer_rtx
, 0,
1236 current_frame
.reg_no
, D0_REG
,
1237 current_frame
.reg_mask
, false,
1240 m68k_emit_movem (frame_pointer_rtx
,
1241 -(current_frame
.offset
+ fsize
),
1242 current_frame
.reg_no
, D0_REG
,
1243 current_frame
.reg_mask
, false, false);
1246 if (current_frame
.fpu_no
> 0)
1249 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1250 gen_rtx_REG (Pmode
, A1_REG
),
1252 -(current_frame
.foffset
+ fsize
),
1253 current_frame
.fpu_no
, FP0_REG
,
1254 current_frame
.fpu_mask
, false, false);
1255 else if (restore_from_sp
)
1257 if (TARGET_COLDFIRE
)
1261 /* If we used moveml to restore the integer registers, the
1262 stack pointer will still point to the bottom of the moveml
1263 save area. Find the stack offset of the first FP
1265 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1268 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1269 m68k_emit_movem (stack_pointer_rtx
, offset
,
1270 current_frame
.fpu_no
, FP0_REG
,
1271 current_frame
.fpu_mask
, false, false);
1274 m68k_emit_movem (stack_pointer_rtx
, 0,
1275 current_frame
.fpu_no
, FP0_REG
,
1276 current_frame
.fpu_mask
, false, true);
1279 m68k_emit_movem (frame_pointer_rtx
,
1280 -(current_frame
.foffset
+ fsize
),
1281 current_frame
.fpu_no
, FP0_REG
,
1282 current_frame
.fpu_mask
, false, false);
1285 if (frame_pointer_needed
)
1286 emit_insn (gen_unlink (frame_pointer_rtx
));
1287 else if (fsize_with_regs
)
1288 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1290 GEN_INT (fsize_with_regs
)));
1292 if (crtl
->calls_eh_return
)
1293 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1295 EH_RETURN_STACKADJ_RTX
));
1298 emit_jump_insn (ret_rtx
);
1301 /* Return true if X is a valid comparison operator for the dbcc
1304 Note it rejects floating point comparison operators.
1305 (In the future we could use Fdbcc).
1307 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1310 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1312 switch (GET_CODE (x
))
1314 case EQ
: case NE
: case GTU
: case LTU
:
1318 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1320 case GT
: case LT
: case GE
: case LE
:
1321 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1327 /* Return nonzero if flags are currently in the 68881 flag register. */
1329 flags_in_68881 (void)
1331 /* We could add support for these in the future */
1332 return cc_status
.flags
& CC_IN_68881
;
1335 /* Return true if PARALLEL contains register REGNO. */
1337 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1341 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1344 if (GET_CODE (parallel
) != PARALLEL
)
1347 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1351 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1352 if (REG_P (x
) && REGNO (x
) == regno
)
1359 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1362 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1364 enum m68k_function_kind kind
;
1366 /* We cannot use sibcalls for nested functions because we use the
1367 static chain register for indirect calls. */
1368 if (CALL_EXPR_STATIC_CHAIN (exp
))
1371 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1373 /* Check that the return value locations are the same. For
1374 example that we aren't returning a value from the sibling in
1375 a D0 register but then need to transfer it to a A0 register. */
1379 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1381 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1383 /* Check that the values are equal or that the result the callee
1384 function returns is superset of what the current function returns. */
1385 if (!(rtx_equal_p (cfun_value
, call_value
)
1386 || (REG_P (cfun_value
)
1387 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1391 kind
= m68k_get_function_kind (current_function_decl
);
1392 if (kind
== m68k_fk_normal_function
)
1393 /* We can always sibcall from a normal function, because it's
1394 undefined if it is calling an interrupt function. */
1397 /* Otherwise we can only sibcall if the function kind is known to be
1399 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1405 /* On the m68k all args are always pushed. */
1408 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1409 enum machine_mode mode ATTRIBUTE_UNUSED
,
1410 const_tree type ATTRIBUTE_UNUSED
,
1411 bool named ATTRIBUTE_UNUSED
)
1417 m68k_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1418 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1420 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1422 *cum
+= (mode
!= BLKmode
1423 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1424 : (int_size_in_bytes (type
) + 3) & ~3);
1427 /* Convert X to a legitimate function call memory reference and return the
1431 m68k_legitimize_call_address (rtx x
)
1433 gcc_assert (MEM_P (x
));
1434 if (call_operand (XEXP (x
, 0), VOIDmode
))
1436 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1439 /* Likewise for sibling calls. */
1442 m68k_legitimize_sibcall_address (rtx x
)
1444 gcc_assert (MEM_P (x
));
1445 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1448 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1449 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1452 /* Convert X to a legitimate address and return it if successful. Otherwise
1455 For the 68000, we handle X+REG by loading X into a register R and
1456 using R+REG. R will go in an address reg and indexing will be used.
1457 However, if REG is a broken-out memory address or multiplication,
1458 nothing needs to be done because REG can certainly go in an address reg. */
1461 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1463 if (m68k_tls_symbol_p (x
))
1464 return m68k_legitimize_tls_address (x
);
1466 if (GET_CODE (x
) == PLUS
)
1468 int ch
= (x
) != (oldx
);
1471 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1473 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1476 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1478 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1481 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1485 if (GET_CODE (XEXP (x
, 1)) == REG
1486 && GET_CODE (XEXP (x
, 0)) == REG
)
1488 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1491 x
= force_operand (x
, 0);
1495 if (memory_address_p (mode
, x
))
1498 if (GET_CODE (XEXP (x
, 0)) == REG
1499 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1500 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1501 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1503 rtx temp
= gen_reg_rtx (Pmode
);
1504 rtx val
= force_operand (XEXP (x
, 1), 0);
1505 emit_move_insn (temp
, val
);
1508 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1509 && GET_CODE (XEXP (x
, 0)) == REG
)
1510 x
= force_operand (x
, 0);
1512 else if (GET_CODE (XEXP (x
, 1)) == REG
1513 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1514 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1515 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1517 rtx temp
= gen_reg_rtx (Pmode
);
1518 rtx val
= force_operand (XEXP (x
, 0), 0);
1519 emit_move_insn (temp
, val
);
1522 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1523 && GET_CODE (XEXP (x
, 1)) == REG
)
1524 x
= force_operand (x
, 0);
1532 /* Output a dbCC; jCC sequence. Note we do not handle the
1533 floating point version of this sequence (Fdbcc). We also
1534 do not handle alternative conditions when CC_NO_OVERFLOW is
1535 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1536 kick those out before we get here. */
1539 output_dbcc_and_branch (rtx
*operands
)
1541 switch (GET_CODE (operands
[3]))
1544 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1548 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1552 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1556 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1560 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1564 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1568 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1572 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1576 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1580 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1587 /* If the decrement is to be done in SImode, then we have
1588 to compensate for the fact that dbcc decrements in HImode. */
1589 switch (GET_MODE (operands
[0]))
1592 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1604 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1607 enum rtx_code op_code
= GET_CODE (op
);
1609 /* This does not produce a useful cc. */
1612 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1613 below. Swap the operands and change the op if these requirements
1614 are not fulfilled. */
1615 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1619 operand1
= operand2
;
1621 op_code
= swap_condition (op_code
);
1623 loperands
[0] = operand1
;
1624 if (GET_CODE (operand1
) == REG
)
1625 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1627 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1628 if (operand2
!= const0_rtx
)
1630 loperands
[2] = operand2
;
1631 if (GET_CODE (operand2
) == REG
)
1632 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1634 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1636 loperands
[4] = gen_label_rtx ();
1637 if (operand2
!= const0_rtx
)
1638 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1641 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1642 output_asm_insn ("tst%.l %0", loperands
);
1644 output_asm_insn ("cmp%.w #0,%0", loperands
);
1646 output_asm_insn ("jne %l4", loperands
);
1648 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1649 output_asm_insn ("tst%.l %1", loperands
);
1651 output_asm_insn ("cmp%.w #0,%1", loperands
);
1654 loperands
[5] = dest
;
1659 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1660 CODE_LABEL_NUMBER (loperands
[4]));
1661 output_asm_insn ("seq %5", loperands
);
1665 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1666 CODE_LABEL_NUMBER (loperands
[4]));
1667 output_asm_insn ("sne %5", loperands
);
1671 loperands
[6] = gen_label_rtx ();
1672 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1673 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1674 CODE_LABEL_NUMBER (loperands
[4]));
1675 output_asm_insn ("sgt %5", loperands
);
1676 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1677 CODE_LABEL_NUMBER (loperands
[6]));
1681 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1682 CODE_LABEL_NUMBER (loperands
[4]));
1683 output_asm_insn ("shi %5", loperands
);
1687 loperands
[6] = gen_label_rtx ();
1688 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1689 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1690 CODE_LABEL_NUMBER (loperands
[4]));
1691 output_asm_insn ("slt %5", loperands
);
1692 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1693 CODE_LABEL_NUMBER (loperands
[6]));
1697 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1698 CODE_LABEL_NUMBER (loperands
[4]));
1699 output_asm_insn ("scs %5", loperands
);
1703 loperands
[6] = gen_label_rtx ();
1704 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1705 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1706 CODE_LABEL_NUMBER (loperands
[4]));
1707 output_asm_insn ("sge %5", loperands
);
1708 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1709 CODE_LABEL_NUMBER (loperands
[6]));
1713 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1714 CODE_LABEL_NUMBER (loperands
[4]));
1715 output_asm_insn ("scc %5", loperands
);
1719 loperands
[6] = gen_label_rtx ();
1720 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1721 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1722 CODE_LABEL_NUMBER (loperands
[4]));
1723 output_asm_insn ("sle %5", loperands
);
1724 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1725 CODE_LABEL_NUMBER (loperands
[6]));
1729 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1730 CODE_LABEL_NUMBER (loperands
[4]));
1731 output_asm_insn ("sls %5", loperands
);
1741 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1743 operands
[0] = countop
;
1744 operands
[1] = dataop
;
1746 if (GET_CODE (countop
) == CONST_INT
)
1748 register int count
= INTVAL (countop
);
1749 /* If COUNT is bigger than size of storage unit in use,
1750 advance to the containing unit of same size. */
1751 if (count
> signpos
)
1753 int offset
= (count
& ~signpos
) / 8;
1754 count
= count
& signpos
;
1755 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1757 if (count
== signpos
)
1758 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1760 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1762 /* These three statements used to use next_insns_test_no...
1763 but it appears that this should do the same job. */
1765 && next_insn_tests_no_inequality (insn
))
1768 && next_insn_tests_no_inequality (insn
))
1771 && next_insn_tests_no_inequality (insn
))
1773 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1774 On some m68k variants unfortunately that's slower than btst.
1775 On 68000 and higher, that should also work for all HImode operands. */
1776 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1778 if (count
== 3 && DATA_REG_P (operands
[1])
1779 && next_insn_tests_no_inequality (insn
))
1781 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1782 return "move%.w %1,%%ccr";
1784 if (count
== 2 && DATA_REG_P (operands
[1])
1785 && next_insn_tests_no_inequality (insn
))
1787 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1788 return "move%.w %1,%%ccr";
1790 /* count == 1 followed by bvc/bvs and
1791 count == 0 followed by bcc/bcs are also possible, but need
1792 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1795 cc_status
.flags
= CC_NOT_NEGATIVE
;
1797 return "btst %0,%1";
1800 /* Return true if X is a legitimate base register. STRICT_P says
1801 whether we need strict checking. */
1804 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1806 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1807 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1812 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1813 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1816 /* Return true if X is a legitimate index register. STRICT_P says
1817 whether we need strict checking. */
1820 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1822 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1827 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1828 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1831 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1832 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1833 ADDRESS if so. STRICT_P says whether we need strict checking. */
1836 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1840 /* Check for a scale factor. */
1842 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1843 && GET_CODE (x
) == MULT
1844 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1845 && (INTVAL (XEXP (x
, 1)) == 2
1846 || INTVAL (XEXP (x
, 1)) == 4
1847 || (INTVAL (XEXP (x
, 1)) == 8
1848 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1850 scale
= INTVAL (XEXP (x
, 1));
1854 /* Check for a word extension. */
1855 if (!TARGET_COLDFIRE
1856 && GET_CODE (x
) == SIGN_EXTEND
1857 && GET_MODE (XEXP (x
, 0)) == HImode
)
1860 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1862 address
->scale
= scale
;
1870 /* Return true if X is an illegitimate symbolic constant. */
1873 m68k_illegitimate_symbolic_constant_p (rtx x
)
1877 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1879 split_const (x
, &base
, &offset
);
1880 if (GET_CODE (base
) == SYMBOL_REF
1881 && !offset_within_block_p (base
, INTVAL (offset
)))
1884 return m68k_tls_reference_p (x
, false);
1887 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1890 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1892 return m68k_illegitimate_symbolic_constant_p (x
);
1895 /* Return true if X is a legitimate constant address that can reach
1896 bytes in the range [X, X + REACH). STRICT_P says whether we need
1900 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1904 if (!CONSTANT_ADDRESS_P (x
))
1908 && !(strict_p
&& TARGET_PCREL
)
1909 && symbolic_operand (x
, VOIDmode
))
1912 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1914 split_const (x
, &base
, &offset
);
1915 if (GET_CODE (base
) == SYMBOL_REF
1916 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1920 return !m68k_tls_reference_p (x
, false);
1923 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1924 labels will become jump tables. */
1927 m68k_jump_table_ref_p (rtx x
)
1929 if (GET_CODE (x
) != LABEL_REF
)
1933 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1936 x
= next_nonnote_insn (x
);
1937 return x
&& JUMP_TABLE_DATA_P (x
);
1940 /* Return true if X is a legitimate address for values of mode MODE.
1941 STRICT_P says whether strict checking is needed. If the address
1942 is valid, describe its components in *ADDRESS. */
1945 m68k_decompose_address (enum machine_mode mode
, rtx x
,
1946 bool strict_p
, struct m68k_address
*address
)
1950 memset (address
, 0, sizeof (*address
));
1952 if (mode
== BLKmode
)
1955 reach
= GET_MODE_SIZE (mode
);
1957 /* Check for (An) (mode 2). */
1958 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1964 /* Check for -(An) and (An)+ (modes 3 and 4). */
1965 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1966 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1968 address
->code
= GET_CODE (x
);
1969 address
->base
= XEXP (x
, 0);
1973 /* Check for (d16,An) (mode 5). */
1974 if (GET_CODE (x
) == PLUS
1975 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1976 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
1977 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1979 address
->base
= XEXP (x
, 0);
1980 address
->offset
= XEXP (x
, 1);
1984 /* Check for GOT loads. These are (bd,An,Xn) addresses if
1985 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
1987 if (GET_CODE (x
) == PLUS
1988 && XEXP (x
, 0) == pic_offset_table_rtx
)
1990 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
1991 they are invalid in this context. */
1992 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
1994 address
->base
= XEXP (x
, 0);
1995 address
->offset
= XEXP (x
, 1);
2000 /* The ColdFire FPU only accepts addressing modes 2-5. */
2001 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2004 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2005 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2006 All these modes are variations of mode 7. */
2007 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2009 address
->offset
= x
;
2013 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2016 ??? do_tablejump creates these addresses before placing the target
2017 label, so we have to assume that unplaced labels are jump table
2018 references. It seems unlikely that we would ever generate indexed
2019 accesses to unplaced labels in other cases. */
2020 if (GET_CODE (x
) == PLUS
2021 && m68k_jump_table_ref_p (XEXP (x
, 1))
2022 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2024 address
->offset
= XEXP (x
, 1);
2028 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2029 (bd,An,Xn.SIZE*SCALE) addresses. */
2033 /* Check for a nonzero base displacement. */
2034 if (GET_CODE (x
) == PLUS
2035 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2037 address
->offset
= XEXP (x
, 1);
2041 /* Check for a suppressed index register. */
2042 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2048 /* Check for a suppressed base register. Do not allow this case
2049 for non-symbolic offsets as it effectively gives gcc freedom
2050 to treat data registers as base registers, which can generate
2053 && symbolic_operand (address
->offset
, VOIDmode
)
2054 && m68k_decompose_index (x
, strict_p
, address
))
2059 /* Check for a nonzero base displacement. */
2060 if (GET_CODE (x
) == PLUS
2061 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2062 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2064 address
->offset
= XEXP (x
, 1);
2069 /* We now expect the sum of a base and an index. */
2070 if (GET_CODE (x
) == PLUS
)
2072 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2073 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2075 address
->base
= XEXP (x
, 0);
2079 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2080 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2082 address
->base
= XEXP (x
, 1);
2089 /* Return true if X is a legitimate address for values of mode MODE.
2090 STRICT_P says whether strict checking is needed. */
2093 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2095 struct m68k_address address
;
2097 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2100 /* Return true if X is a memory, describing its address in ADDRESS if so.
2101 Apply strict checking if called during or after reload. */
2104 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2107 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2108 reload_in_progress
|| reload_completed
,
2112 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2115 m68k_legitimate_constant_p (enum machine_mode mode
, rtx x
)
2117 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2120 /* Return true if X matches the 'Q' constraint. It must be a memory
2121 with a base address and no constant offset or index. */
2124 m68k_matches_q_p (rtx x
)
2126 struct m68k_address address
;
2128 return (m68k_legitimate_mem_p (x
, &address
)
2129 && address
.code
== UNKNOWN
2135 /* Return true if X matches the 'U' constraint. It must be a base address
2136 with a constant offset and no index. */
2139 m68k_matches_u_p (rtx x
)
2141 struct m68k_address address
;
2143 return (m68k_legitimate_mem_p (x
, &address
)
2144 && address
.code
== UNKNOWN
2150 /* Return GOT pointer. */
2155 if (pic_offset_table_rtx
== NULL_RTX
)
2156 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2158 crtl
->uses_pic_offset_table
= 1;
2160 return pic_offset_table_rtx
;
2163 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2165 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2166 RELOC_TLSIE
, RELOC_TLSLE
};
2168 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2170 /* Wrap symbol X into unspec representing relocation RELOC.
2171 BASE_REG - register that should be added to the result.
2172 TEMP_REG - if non-null, temporary register. */
2175 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2179 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2181 if (TARGET_COLDFIRE
&& use_x_p
)
2182 /* When compiling with -mx{got, tls} switch the code will look like this:
2184 move.l <X>@<RELOC>,<TEMP_REG>
2185 add.l <BASE_REG>,<TEMP_REG> */
2187 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2188 to put @RELOC after reference. */
2189 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2191 x
= gen_rtx_CONST (Pmode
, x
);
2193 if (temp_reg
== NULL
)
2195 gcc_assert (can_create_pseudo_p ());
2196 temp_reg
= gen_reg_rtx (Pmode
);
2199 emit_move_insn (temp_reg
, x
);
2200 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2205 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2207 x
= gen_rtx_CONST (Pmode
, x
);
2209 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2215 /* Helper for m68k_unwrap_symbol.
2216 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2217 sets *RELOC_PTR to relocation type for the symbol. */
2220 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2221 enum m68k_reloc
*reloc_ptr
)
2223 if (GET_CODE (orig
) == CONST
)
2226 enum m68k_reloc dummy
;
2230 if (reloc_ptr
== NULL
)
2233 /* Handle an addend. */
2234 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2235 && CONST_INT_P (XEXP (x
, 1)))
2238 if (GET_CODE (x
) == UNSPEC
)
2240 switch (XINT (x
, 1))
2242 case UNSPEC_RELOC16
:
2243 orig
= XVECEXP (x
, 0, 0);
2244 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2247 case UNSPEC_RELOC32
:
2248 if (unwrap_reloc32_p
)
2250 orig
= XVECEXP (x
, 0, 0);
2251 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2264 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2265 UNSPEC_RELOC32 wrappers. */
2268 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2270 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2273 /* Helper for m68k_final_prescan_insn. */
2276 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2280 if (m68k_unwrap_symbol (x
, true) != x
)
2281 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2285 gcc_assert (GET_CODE (x
) == CONST
);
2288 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2293 unspec
= XEXP (plus
, 0);
2294 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2295 addend
= XEXP (plus
, 1);
2296 gcc_assert (CONST_INT_P (addend
));
2298 /* We now have all the pieces, rearrange them. */
2300 /* Move symbol to plus. */
2301 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2303 /* Move plus inside unspec. */
2304 XVECEXP (unspec
, 0, 0) = plus
;
2306 /* Move unspec to top level of const. */
2307 XEXP (x
, 0) = unspec
;
2316 /* Prescan insn before outputing assembler for it. */
2319 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2320 rtx
*operands
, int n_operands
)
2324 /* Combine and, possibly, other optimizations may do good job
2326 (const (unspec [(symbol)]))
2328 (const (plus (unspec [(symbol)])
2330 The problem with this is emitting @TLS or @GOT decorations.
2331 The decoration is emitted when processing (unspec), so the
2332 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2334 It seems that the easiest solution to this is to convert such
2336 (const (unspec [(plus (symbol)
2338 Note, that the top level of operand remains intact, so we don't have
2339 to patch up anything outside of the operand. */
2341 for (i
= 0; i
< n_operands
; ++i
)
2347 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2351 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2352 If REG is non-null, use it; generate new pseudo otherwise. */
2355 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2359 if (reg
== NULL_RTX
)
2361 gcc_assert (can_create_pseudo_p ());
2362 reg
= gen_reg_rtx (Pmode
);
2365 insn
= emit_move_insn (reg
, x
);
2366 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2368 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2373 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2377 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2379 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2381 x
= gen_rtx_MEM (Pmode
, x
);
2382 MEM_READONLY_P (x
) = 1;
2387 /* Legitimize PIC addresses. If the address is already
2388 position-independent, we return ORIG. Newly generated
2389 position-independent addresses go to REG. If we need more
2390 than one register, we lose.
2392 An address is legitimized by making an indirect reference
2393 through the Global Offset Table with the name of the symbol
2396 The assembler and linker are responsible for placing the
2397 address of the symbol in the GOT. The function prologue
2398 is responsible for initializing a5 to the starting address
2401 The assembler is also responsible for translating a symbol name
2402 into a constant displacement from the start of the GOT.
2404 A quick example may make things a little clearer:
2406 When not generating PIC code to store the value 12345 into _foo
2407 we would generate the following code:
2411 When generating PIC two transformations are made. First, the compiler
2412 loads the address of foo into a register. So the first transformation makes:
2417 The code in movsi will intercept the lea instruction and call this
2418 routine which will transform the instructions into:
2420 movel a5@(_foo:w), a0
2424 That (in a nutshell) is how *all* symbol and label references are
2428 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2433 /* First handle a simple SYMBOL_REF or LABEL_REF */
2434 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2438 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2439 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2441 else if (GET_CODE (orig
) == CONST
)
2445 /* Make sure this has not already been legitimized. */
2446 if (m68k_unwrap_symbol (orig
, true) != orig
)
2451 /* legitimize both operands of the PLUS */
2452 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2454 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2455 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2456 base
== reg
? 0 : reg
);
2458 if (GET_CODE (orig
) == CONST_INT
)
2459 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2461 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2467 /* The __tls_get_addr symbol. */
2468 static GTY(()) rtx m68k_tls_get_addr
;
2470 /* Return SYMBOL_REF for __tls_get_addr. */
2473 m68k_get_tls_get_addr (void)
2475 if (m68k_tls_get_addr
== NULL_RTX
)
2476 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2478 return m68k_tls_get_addr
;
2481 /* Return libcall result in A0 instead of usual D0. */
2482 static bool m68k_libcall_value_in_a0_p
= false;
2484 /* Emit instruction sequence that calls __tls_get_addr. X is
2485 the TLS symbol we are referencing and RELOC is the symbol type to use
2486 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2487 emitted. A pseudo register with result of __tls_get_addr call is
2491 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2497 /* Emit the call sequence. */
2500 /* FIXME: Unfortunately, emit_library_call_value does not
2501 consider (plus (%a5) (const (unspec))) to be a good enough
2502 operand for push, so it forces it into a register. The bad
2503 thing about this is that combiner, due to copy propagation and other
2504 optimizations, sometimes can not later fix this. As a consequence,
2505 additional register may be allocated resulting in a spill.
2506 For reference, see args processing loops in
2507 calls.c:emit_library_call_value_1.
2508 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2509 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2511 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2512 is the simpliest way of generating a call. The difference between
2513 __tls_get_addr() and libcall is that the result is returned in D0
2514 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2515 which temporarily switches returning the result to A0. */
2517 m68k_libcall_value_in_a0_p
= true;
2518 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2519 Pmode
, 1, x
, Pmode
);
2520 m68k_libcall_value_in_a0_p
= false;
2522 insns
= get_insns ();
2525 gcc_assert (can_create_pseudo_p ());
2526 dest
= gen_reg_rtx (Pmode
);
2527 emit_libcall_block (insns
, dest
, a0
, eqv
);
2532 /* The __tls_get_addr symbol. */
2533 static GTY(()) rtx m68k_read_tp
;
2535 /* Return SYMBOL_REF for __m68k_read_tp. */
2538 m68k_get_m68k_read_tp (void)
2540 if (m68k_read_tp
== NULL_RTX
)
2541 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2543 return m68k_read_tp
;
2546 /* Emit instruction sequence that calls __m68k_read_tp.
2547 A pseudo register with result of __m68k_read_tp call is returned. */
2550 m68k_call_m68k_read_tp (void)
2559 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2560 is the simpliest way of generating a call. The difference between
2561 __m68k_read_tp() and libcall is that the result is returned in D0
2562 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2563 which temporarily switches returning the result to A0. */
2565 /* Emit the call sequence. */
2566 m68k_libcall_value_in_a0_p
= true;
2567 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2569 m68k_libcall_value_in_a0_p
= false;
2570 insns
= get_insns ();
2573 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2574 share the m68k_read_tp result with other IE/LE model accesses. */
2575 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2577 gcc_assert (can_create_pseudo_p ());
2578 dest
= gen_reg_rtx (Pmode
);
2579 emit_libcall_block (insns
, dest
, a0
, eqv
);
2584 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2585 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2589 m68k_legitimize_tls_address (rtx orig
)
2591 switch (SYMBOL_REF_TLS_MODEL (orig
))
2593 case TLS_MODEL_GLOBAL_DYNAMIC
:
2594 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2597 case TLS_MODEL_LOCAL_DYNAMIC
:
2603 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2604 share the LDM result with other LD model accesses. */
2605 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2608 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2610 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2612 if (can_create_pseudo_p ())
2613 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2619 case TLS_MODEL_INITIAL_EXEC
:
2624 a0
= m68k_call_m68k_read_tp ();
2626 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2627 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2629 if (can_create_pseudo_p ())
2630 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2636 case TLS_MODEL_LOCAL_EXEC
:
2641 a0
= m68k_call_m68k_read_tp ();
2643 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2645 if (can_create_pseudo_p ())
2646 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2659 /* Return true if X is a TLS symbol. */
2662 m68k_tls_symbol_p (rtx x
)
2664 if (!TARGET_HAVE_TLS
)
2667 if (GET_CODE (x
) != SYMBOL_REF
)
2670 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2673 /* Helper for m68k_tls_referenced_p. */
2676 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2678 /* Note: this is not the same as m68k_tls_symbol_p. */
2679 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2680 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2682 /* Don't recurse into legitimate TLS references. */
2683 if (m68k_tls_reference_p (*x_ptr
, true))
2689 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2690 though illegitimate one.
2691 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2694 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2696 if (!TARGET_HAVE_TLS
)
2700 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2703 enum m68k_reloc reloc
= RELOC_GOT
;
2705 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2706 && TLS_RELOC_P (reloc
));
2712 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2714 /* Return the type of move that should be used for integer I. */
2717 m68k_const_method (HOST_WIDE_INT i
)
2724 /* The ColdFire doesn't have byte or word operations. */
2725 /* FIXME: This may not be useful for the m68060 either. */
2726 if (!TARGET_COLDFIRE
)
2728 /* if -256 < N < 256 but N is not in range for a moveq
2729 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2730 if (USE_MOVQ (i
^ 0xff))
2732 /* Likewise, try with not.w */
2733 if (USE_MOVQ (i
^ 0xffff))
2735 /* This is the only value where neg.w is useful */
2740 /* Try also with swap. */
2742 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2747 /* Try using MVZ/MVS with an immediate value to load constants. */
2748 if (i
>= 0 && i
<= 65535)
2750 if (i
>= -32768 && i
<= 32767)
2754 /* Otherwise, use move.l */
2758 /* Return the cost of moving constant I into a data register. */
2761 const_int_cost (HOST_WIDE_INT i
)
2763 switch (m68k_const_method (i
))
2766 /* Constants between -128 and 127 are cheap due to moveq. */
2774 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2784 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2785 int *total
, bool speed ATTRIBUTE_UNUSED
)
2790 /* Constant zero is super cheap due to clr instruction. */
2791 if (x
== const0_rtx
)
2794 *total
= const_int_cost (INTVAL (x
));
2804 /* Make 0.0 cheaper than other floating constants to
2805 encourage creating tstsf and tstdf insns. */
2806 if (outer_code
== COMPARE
2807 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2813 /* These are vaguely right for a 68020. */
2814 /* The costs for long multiply have been adjusted to work properly
2815 in synth_mult on the 68020, relative to an average of the time
2816 for add and the time for shift, taking away a little more because
2817 sometimes move insns are needed. */
2818 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2823 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2824 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2826 : TARGET_COLDFIRE ? 3 : 13)
2831 : TUNE_68000_10 ? 5 \
2832 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2833 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2835 : TARGET_COLDFIRE ? 2 : 8)
2838 (TARGET_CF_HWDIV ? 11 \
2839 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2842 /* An lea costs about three times as much as a simple add. */
2843 if (GET_MODE (x
) == SImode
2844 && GET_CODE (XEXP (x
, 1)) == REG
2845 && GET_CODE (XEXP (x
, 0)) == MULT
2846 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2847 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2848 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2849 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2850 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2852 /* lea an@(dx:l:i),am */
2853 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2863 *total
= COSTS_N_INSNS(1);
2868 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2870 if (INTVAL (XEXP (x
, 1)) < 16)
2871 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2873 /* We're using clrw + swap for these cases. */
2874 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2877 *total
= COSTS_N_INSNS (10); /* Worst case. */
2880 /* A shift by a big integer takes an extra instruction. */
2881 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2882 && (INTVAL (XEXP (x
, 1)) == 16))
2884 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2887 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2888 && !(INTVAL (XEXP (x
, 1)) > 0
2889 && INTVAL (XEXP (x
, 1)) <= 8))
2891 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2897 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2898 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2899 && GET_MODE (x
) == SImode
)
2900 *total
= COSTS_N_INSNS (MULW_COST
);
2901 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2902 *total
= COSTS_N_INSNS (MULW_COST
);
2904 *total
= COSTS_N_INSNS (MULL_COST
);
2911 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2912 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2913 else if (TARGET_CF_HWDIV
)
2914 *total
= COSTS_N_INSNS (18);
2916 *total
= COSTS_N_INSNS (43); /* div.l */
2920 if (outer_code
== COMPARE
)
2929 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2933 output_move_const_into_data_reg (rtx
*operands
)
2937 i
= INTVAL (operands
[1]);
2938 switch (m68k_const_method (i
))
2941 return "mvzw %1,%0";
2943 return "mvsw %1,%0";
2945 return "moveq %1,%0";
2948 operands
[1] = GEN_INT (i
^ 0xff);
2949 return "moveq %1,%0\n\tnot%.b %0";
2952 operands
[1] = GEN_INT (i
^ 0xffff);
2953 return "moveq %1,%0\n\tnot%.w %0";
2956 return "moveq #-128,%0\n\tneg%.w %0";
2961 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2962 return "moveq %1,%0\n\tswap %0";
2965 return "move%.l %1,%0";
2971 /* Return true if I can be handled by ISA B's mov3q instruction. */
2974 valid_mov3q_const (HOST_WIDE_INT i
)
2976 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
2979 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
2980 I is the value of OPERANDS[1]. */
2983 output_move_simode_const (rtx
*operands
)
2989 src
= INTVAL (operands
[1]);
2991 && (DATA_REG_P (dest
) || MEM_P (dest
))
2992 /* clr insns on 68000 read before writing. */
2993 && ((TARGET_68010
|| TARGET_COLDFIRE
)
2994 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
2996 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
2997 return "mov3q%.l %1,%0";
2998 else if (src
== 0 && ADDRESS_REG_P (dest
))
2999 return "sub%.l %0,%0";
3000 else if (DATA_REG_P (dest
))
3001 return output_move_const_into_data_reg (operands
);
3002 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3004 if (valid_mov3q_const (src
))
3005 return "mov3q%.l %1,%0";
3006 return "move%.w %1,%0";
3008 else if (MEM_P (dest
)
3009 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3010 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3011 && IN_RANGE (src
, -0x8000, 0x7fff))
3013 if (valid_mov3q_const (src
))
3014 return "mov3q%.l %1,%-";
3017 return "move%.l %1,%0";
3021 output_move_simode (rtx
*operands
)
3023 if (GET_CODE (operands
[1]) == CONST_INT
)
3024 return output_move_simode_const (operands
);
3025 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3026 || GET_CODE (operands
[1]) == CONST
)
3027 && push_operand (operands
[0], SImode
))
3029 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3030 || GET_CODE (operands
[1]) == CONST
)
3031 && ADDRESS_REG_P (operands
[0]))
3032 return "lea %a1,%0";
3033 return "move%.l %1,%0";
3037 output_move_himode (rtx
*operands
)
3039 if (GET_CODE (operands
[1]) == CONST_INT
)
3041 if (operands
[1] == const0_rtx
3042 && (DATA_REG_P (operands
[0])
3043 || GET_CODE (operands
[0]) == MEM
)
3044 /* clr insns on 68000 read before writing. */
3045 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3046 || !(GET_CODE (operands
[0]) == MEM
3047 && MEM_VOLATILE_P (operands
[0]))))
3049 else if (operands
[1] == const0_rtx
3050 && ADDRESS_REG_P (operands
[0]))
3051 return "sub%.l %0,%0";
3052 else if (DATA_REG_P (operands
[0])
3053 && INTVAL (operands
[1]) < 128
3054 && INTVAL (operands
[1]) >= -128)
3055 return "moveq %1,%0";
3056 else if (INTVAL (operands
[1]) < 0x8000
3057 && INTVAL (operands
[1]) >= -0x8000)
3058 return "move%.w %1,%0";
3060 else if (CONSTANT_P (operands
[1]))
3061 return "move%.l %1,%0";
3062 return "move%.w %1,%0";
3066 output_move_qimode (rtx
*operands
)
3068 /* 68k family always modifies the stack pointer by at least 2, even for
3069 byte pushes. The 5200 (ColdFire) does not do this. */
3071 /* This case is generated by pushqi1 pattern now. */
3072 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3073 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3074 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3075 && ! ADDRESS_REG_P (operands
[1])
3076 && ! TARGET_COLDFIRE
));
3078 /* clr and st insns on 68000 read before writing. */
3079 if (!ADDRESS_REG_P (operands
[0])
3080 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3081 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3083 if (operands
[1] == const0_rtx
)
3085 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3086 && GET_CODE (operands
[1]) == CONST_INT
3087 && (INTVAL (operands
[1]) & 255) == 255)
3093 if (GET_CODE (operands
[1]) == CONST_INT
3094 && DATA_REG_P (operands
[0])
3095 && INTVAL (operands
[1]) < 128
3096 && INTVAL (operands
[1]) >= -128)
3097 return "moveq %1,%0";
3098 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3099 return "sub%.l %0,%0";
3100 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3101 return "move%.l %1,%0";
3102 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3103 from address registers. */
3104 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3105 return "move%.w %1,%0";
3106 return "move%.b %1,%0";
3110 output_move_stricthi (rtx
*operands
)
3112 if (operands
[1] == const0_rtx
3113 /* clr insns on 68000 read before writing. */
3114 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3115 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3117 return "move%.w %1,%0";
3121 output_move_strictqi (rtx
*operands
)
3123 if (operands
[1] == const0_rtx
3124 /* clr insns on 68000 read before writing. */
3125 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3126 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3128 return "move%.b %1,%0";
3131 /* Return the best assembler insn template
3132 for moving operands[1] into operands[0] as a fullword. */
3135 singlemove_string (rtx
*operands
)
3137 if (GET_CODE (operands
[1]) == CONST_INT
)
3138 return output_move_simode_const (operands
);
3139 return "move%.l %1,%0";
3143 /* Output assembler or rtl code to perform a doubleword move insn
3144 with operands OPERANDS.
3145 Pointers to 3 helper functions should be specified:
3146 HANDLE_REG_ADJUST to adjust a register by a small value,
3147 HANDLE_COMPADR to compute an address and
3148 HANDLE_MOVSI to move 4 bytes. */
3151 handle_move_double (rtx operands
[2],
3152 void (*handle_reg_adjust
) (rtx
, int),
3153 void (*handle_compadr
) (rtx
[2]),
3154 void (*handle_movsi
) (rtx
[2]))
3158 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3163 rtx addreg0
= 0, addreg1
= 0;
3164 int dest_overlapped_low
= 0;
3165 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3170 /* First classify both operands. */
3172 if (REG_P (operands
[0]))
3174 else if (offsettable_memref_p (operands
[0]))
3176 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3178 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3180 else if (GET_CODE (operands
[0]) == MEM
)
3185 if (REG_P (operands
[1]))
3187 else if (CONSTANT_P (operands
[1]))
3189 else if (offsettable_memref_p (operands
[1]))
3191 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3193 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3195 else if (GET_CODE (operands
[1]) == MEM
)
3200 /* Check for the cases that the operand constraints are not supposed
3201 to allow to happen. Generating code for these cases is
3203 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3205 /* If one operand is decrementing and one is incrementing
3206 decrement the former register explicitly
3207 and change that operand into ordinary indexing. */
3209 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3211 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3213 handle_reg_adjust (operands
[0], -size
);
3215 if (GET_MODE (operands
[1]) == XFmode
)
3216 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3217 else if (GET_MODE (operands
[0]) == DFmode
)
3218 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3220 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3223 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3225 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3227 handle_reg_adjust (operands
[1], -size
);
3229 if (GET_MODE (operands
[1]) == XFmode
)
3230 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3231 else if (GET_MODE (operands
[1]) == DFmode
)
3232 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3234 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3238 /* If an operand is an unoffsettable memory ref, find a register
3239 we can increment temporarily to make it refer to the second word. */
3241 if (optype0
== MEMOP
)
3242 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3244 if (optype1
== MEMOP
)
3245 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3247 /* Ok, we can do one word at a time.
3248 Normally we do the low-numbered word first,
3249 but if either operand is autodecrementing then we
3250 do the high-numbered word first.
3252 In either case, set up in LATEHALF the operands to use
3253 for the high-numbered word and in some cases alter the
3254 operands in OPERANDS to be suitable for the low-numbered word. */
3258 if (optype0
== REGOP
)
3260 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3261 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3263 else if (optype0
== OFFSOP
)
3265 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3266 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3270 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3271 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3274 if (optype1
== REGOP
)
3276 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3277 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3279 else if (optype1
== OFFSOP
)
3281 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3282 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3284 else if (optype1
== CNSTOP
)
3286 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3291 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3292 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3293 operands
[1] = GEN_INT (l
[0]);
3294 middlehalf
[1] = GEN_INT (l
[1]);
3295 latehalf
[1] = GEN_INT (l
[2]);
3299 /* No non-CONST_DOUBLE constant should ever appear
3301 gcc_assert (!CONSTANT_P (operands
[1]));
3306 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3307 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3311 /* size is not 12: */
3313 if (optype0
== REGOP
)
3314 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3315 else if (optype0
== OFFSOP
)
3316 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3318 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3320 if (optype1
== REGOP
)
3321 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3322 else if (optype1
== OFFSOP
)
3323 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3324 else if (optype1
== CNSTOP
)
3325 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3327 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3330 /* If insn is effectively movd N(sp),-(sp) then we will do the
3331 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3332 for the low word as well, to compensate for the first decrement of sp. */
3333 if (optype0
== PUSHOP
3334 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3335 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3336 operands
[1] = middlehalf
[1] = latehalf
[1];
3338 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3339 if the upper part of reg N does not appear in the MEM, arrange to
3340 emit the move late-half first. Otherwise, compute the MEM address
3341 into the upper part of N and use that as a pointer to the memory
3343 if (optype0
== REGOP
3344 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3346 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3348 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3349 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3351 /* If both halves of dest are used in the src memory address,
3352 compute the address into latehalf of dest.
3353 Note that this can't happen if the dest is two data regs. */
3355 xops
[0] = latehalf
[0];
3356 xops
[1] = XEXP (operands
[1], 0);
3358 handle_compadr (xops
);
3359 if (GET_MODE (operands
[1]) == XFmode
)
3361 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3362 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3363 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3367 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3368 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3372 && reg_overlap_mentioned_p (middlehalf
[0],
3373 XEXP (operands
[1], 0)))
3375 /* Check for two regs used by both source and dest.
3376 Note that this can't happen if the dest is all data regs.
3377 It can happen if the dest is d6, d7, a0.
3378 But in that case, latehalf is an addr reg, so
3379 the code at compadr does ok. */
3381 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3382 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3385 /* JRV says this can't happen: */
3386 gcc_assert (!addreg0
&& !addreg1
);
3388 /* Only the middle reg conflicts; simply put it last. */
3389 handle_movsi (operands
);
3390 handle_movsi (latehalf
);
3391 handle_movsi (middlehalf
);
3395 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3396 /* If the low half of dest is mentioned in the source memory
3397 address, the arrange to emit the move late half first. */
3398 dest_overlapped_low
= 1;
3401 /* If one or both operands autodecrementing,
3402 do the two words, high-numbered first. */
3404 /* Likewise, the first move would clobber the source of the second one,
3405 do them in the other order. This happens only for registers;
3406 such overlap can't happen in memory unless the user explicitly
3407 sets it up, and that is an undefined circumstance. */
3409 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3410 || (optype0
== REGOP
&& optype1
== REGOP
3411 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3412 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3413 || dest_overlapped_low
)
3415 /* Make any unoffsettable addresses point at high-numbered word. */
3417 handle_reg_adjust (addreg0
, size
- 4);
3419 handle_reg_adjust (addreg1
, size
- 4);
3422 handle_movsi (latehalf
);
3424 /* Undo the adds we just did. */
3426 handle_reg_adjust (addreg0
, -4);
3428 handle_reg_adjust (addreg1
, -4);
3432 handle_movsi (middlehalf
);
3435 handle_reg_adjust (addreg0
, -4);
3437 handle_reg_adjust (addreg1
, -4);
3440 /* Do low-numbered word. */
3442 handle_movsi (operands
);
3446 /* Normal case: do the two words, low-numbered first. */
3448 m68k_final_prescan_insn (NULL
, operands
, 2);
3449 handle_movsi (operands
);
3451 /* Do the middle one of the three words for long double */
3455 handle_reg_adjust (addreg0
, 4);
3457 handle_reg_adjust (addreg1
, 4);
3459 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3460 handle_movsi (middlehalf
);
3463 /* Make any unoffsettable addresses point at high-numbered word. */
3465 handle_reg_adjust (addreg0
, 4);
3467 handle_reg_adjust (addreg1
, 4);
3470 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3471 handle_movsi (latehalf
);
3473 /* Undo the adds we just did. */
3475 handle_reg_adjust (addreg0
, -(size
- 4));
3477 handle_reg_adjust (addreg1
, -(size
- 4));
3482 /* Output assembler code to adjust REG by N. */
3484 output_reg_adjust (rtx reg
, int n
)
3488 gcc_assert (GET_MODE (reg
) == SImode
3489 && -12 <= n
&& n
!= 0 && n
<= 12);
3494 s
= "add%.l #12,%0";
3498 s
= "addq%.l #8,%0";
3502 s
= "addq%.l #4,%0";
3506 s
= "sub%.l #12,%0";
3510 s
= "subq%.l #8,%0";
3514 s
= "subq%.l #4,%0";
3522 output_asm_insn (s
, ®
);
3525 /* Emit rtl code to adjust REG by N. */
3527 emit_reg_adjust (rtx reg1
, int n
)
3531 gcc_assert (GET_MODE (reg1
) == SImode
3532 && -12 <= n
&& n
!= 0 && n
<= 12);
3534 reg1
= copy_rtx (reg1
);
3535 reg2
= copy_rtx (reg1
);
3538 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3540 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3545 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3547 output_compadr (rtx operands
[2])
3549 output_asm_insn ("lea %a1,%0", operands
);
3552 /* Output the best assembler insn for moving operands[1] into operands[0]
3555 output_movsi (rtx operands
[2])
3557 output_asm_insn (singlemove_string (operands
), operands
);
3560 /* Copy OP and change its mode to MODE. */
3562 copy_operand (rtx op
, enum machine_mode mode
)
3564 /* ??? This looks really ugly. There must be a better way
3565 to change a mode on the operand. */
3566 if (GET_MODE (op
) != VOIDmode
)
3569 op
= gen_rtx_REG (mode
, REGNO (op
));
3573 PUT_MODE (op
, mode
);
3580 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3582 emit_movsi (rtx operands
[2])
3584 operands
[0] = copy_operand (operands
[0], SImode
);
3585 operands
[1] = copy_operand (operands
[1], SImode
);
3587 emit_insn (gen_movsi (operands
[0], operands
[1]));
3590 /* Output assembler code to perform a doubleword move insn
3591 with operands OPERANDS. */
3593 output_move_double (rtx
*operands
)
3595 handle_move_double (operands
,
3596 output_reg_adjust
, output_compadr
, output_movsi
);
3601 /* Output rtl code to perform a doubleword move insn
3602 with operands OPERANDS. */
3604 m68k_emit_move_double (rtx operands
[2])
3606 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3609 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3610 new rtx with the correct mode. */
3613 force_mode (enum machine_mode mode
, rtx orig
)
3615 if (mode
== GET_MODE (orig
))
3618 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3621 return gen_rtx_REG (mode
, REGNO (orig
));
3625 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3627 return reg_renumber
&& FP_REG_P (op
);
3630 /* Emit insns to move operands[1] into operands[0].
3632 Return 1 if we have written out everything that needs to be done to
3633 do the move. Otherwise, return 0 and the caller will emit the move
3636 Note SCRATCH_REG may not be in the proper mode depending on how it
3637 will be used. This routine is responsible for creating a new copy
3638 of SCRATCH_REG in the proper mode. */
3641 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3643 register rtx operand0
= operands
[0];
3644 register rtx operand1
= operands
[1];
3648 && reload_in_progress
&& GET_CODE (operand0
) == REG
3649 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3650 operand0
= reg_equiv_mem (REGNO (operand0
));
3651 else if (scratch_reg
3652 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3653 && GET_CODE (SUBREG_REG (operand0
)) == REG
3654 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3656 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3657 the code which tracks sets/uses for delete_output_reload. */
3658 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3659 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3660 SUBREG_BYTE (operand0
));
3661 operand0
= alter_subreg (&temp
);
3665 && reload_in_progress
&& GET_CODE (operand1
) == REG
3666 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3667 operand1
= reg_equiv_mem (REGNO (operand1
));
3668 else if (scratch_reg
3669 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3670 && GET_CODE (SUBREG_REG (operand1
)) == REG
3671 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3673 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3674 the code which tracks sets/uses for delete_output_reload. */
3675 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3676 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3677 SUBREG_BYTE (operand1
));
3678 operand1
= alter_subreg (&temp
);
3681 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3682 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3683 != XEXP (operand0
, 0)))
3684 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3685 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3686 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3687 != XEXP (operand1
, 0)))
3688 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3690 /* Handle secondary reloads for loads/stores of FP registers where
3691 the address is symbolic by using the scratch register */
3692 if (fp_reg_operand (operand0
, mode
)
3693 && ((GET_CODE (operand1
) == MEM
3694 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3695 || ((GET_CODE (operand1
) == SUBREG
3696 && GET_CODE (XEXP (operand1
, 0)) == MEM
3697 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3700 if (GET_CODE (operand1
) == SUBREG
)
3701 operand1
= XEXP (operand1
, 0);
3703 /* SCRATCH_REG will hold an address. We want
3704 it in SImode regardless of what mode it was originally given
3706 scratch_reg
= force_mode (SImode
, scratch_reg
);
3708 /* D might not fit in 14 bits either; for such cases load D into
3710 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3712 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3713 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3715 XEXP (XEXP (operand1
, 0), 0),
3719 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3720 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3721 gen_rtx_MEM (mode
, scratch_reg
)));
3724 else if (fp_reg_operand (operand1
, mode
)
3725 && ((GET_CODE (operand0
) == MEM
3726 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3727 || ((GET_CODE (operand0
) == SUBREG
)
3728 && GET_CODE (XEXP (operand0
, 0)) == MEM
3729 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3732 if (GET_CODE (operand0
) == SUBREG
)
3733 operand0
= XEXP (operand0
, 0);
3735 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3736 it in SIMODE regardless of what mode it was originally given
3738 scratch_reg
= force_mode (SImode
, scratch_reg
);
3740 /* D might not fit in 14 bits either; for such cases load D into
3742 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3744 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3745 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3748 XEXP (XEXP (operand0
, 0),
3753 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3754 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3758 /* Handle secondary reloads for loads of FP registers from constant
3759 expressions by forcing the constant into memory.
3761 use scratch_reg to hold the address of the memory location.
3763 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3764 NO_REGS when presented with a const_int and an register class
3765 containing only FP registers. Doing so unfortunately creates
3766 more problems than it solves. Fix this for 2.5. */
3767 else if (fp_reg_operand (operand0
, mode
)
3768 && CONSTANT_P (operand1
)
3773 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3774 it in SIMODE regardless of what mode it was originally given
3776 scratch_reg
= force_mode (SImode
, scratch_reg
);
3778 /* Force the constant into memory and put the address of the
3779 memory location into scratch_reg. */
3780 xoperands
[0] = scratch_reg
;
3781 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3782 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3784 /* Now load the destination register. */
3785 emit_insn (gen_rtx_SET (mode
, operand0
,
3786 gen_rtx_MEM (mode
, scratch_reg
)));
3790 /* Now have insn-emit do whatever it normally does. */
3794 /* Split one or more DImode RTL references into pairs of SImode
3795 references. The RTL can be REG, offsettable MEM, integer constant, or
3796 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3797 split and "num" is its length. lo_half and hi_half are output arrays
3798 that parallel "operands". */
3801 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3805 rtx op
= operands
[num
];
3807 /* simplify_subreg refuses to split volatile memory addresses,
3808 but we still have to handle it. */
3809 if (GET_CODE (op
) == MEM
)
3811 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3812 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3816 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3817 GET_MODE (op
) == VOIDmode
3818 ? DImode
: GET_MODE (op
), 4);
3819 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3820 GET_MODE (op
) == VOIDmode
3821 ? DImode
: GET_MODE (op
), 0);
3826 /* Split X into a base and a constant offset, storing them in *BASE
3827 and *OFFSET respectively. */
3830 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3833 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3835 *offset
+= INTVAL (XEXP (x
, 1));
3841 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3842 instruction. STORE_P says whether the move is a load or store.
3844 If the instruction uses post-increment or pre-decrement addressing,
3845 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3846 adjustment. This adjustment will be made by the first element of
3847 PARALLEL, with the loads or stores starting at element 1. If the
3848 instruction does not use post-increment or pre-decrement addressing,
3849 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3850 start at element 0. */
3853 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3854 HOST_WIDE_INT automod_offset
, bool store_p
)
3856 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3857 HOST_WIDE_INT offset
, mem_offset
;
3859 enum reg_class rclass
;
3861 len
= XVECLEN (pattern
, 0);
3862 first
= (automod_base
!= NULL
);
3866 /* Stores must be pre-decrement and loads must be post-increment. */
3867 if (store_p
!= (automod_offset
< 0))
3870 /* Work out the base and offset for lowest memory location. */
3871 base
= automod_base
;
3872 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3876 /* Allow any valid base and offset in the first access. */
3883 for (i
= first
; i
< len
; i
++)
3885 /* We need a plain SET. */
3886 set
= XVECEXP (pattern
, 0, i
);
3887 if (GET_CODE (set
) != SET
)
3890 /* Check that we have a memory location... */
3891 mem
= XEXP (set
, !store_p
);
3892 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3895 /* ...with the right address. */
3898 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3899 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3900 There are no mode restrictions for 680x0 besides the
3901 automodification rules enforced above. */
3903 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3908 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3909 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3913 /* Check that we have a register of the required mode and class. */
3914 reg
= XEXP (set
, store_p
);
3916 || !HARD_REGISTER_P (reg
)
3917 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3922 /* The register must belong to RCLASS and have a higher number
3923 than the register in the previous SET. */
3924 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3925 || REGNO (last_reg
) >= REGNO (reg
))
3930 /* Work out which register class we need. */
3931 if (INT_REGNO_P (REGNO (reg
)))
3932 rclass
= GENERAL_REGS
;
3933 else if (FP_REGNO_P (REGNO (reg
)))
3940 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3943 /* If we have an automodification, check whether the final offset is OK. */
3944 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3947 /* Reject unprofitable cases. */
3948 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3954 /* Return the assembly code template for a movem or fmovem instruction
3955 whose pattern is given by PATTERN. Store the template's operands
3958 If the instruction uses post-increment or pre-decrement addressing,
3959 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3960 is true if this is a store instruction. */
3963 m68k_output_movem (rtx
*operands
, rtx pattern
,
3964 HOST_WIDE_INT automod_offset
, bool store_p
)
3969 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3971 first
= (automod_offset
!= 0);
3972 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3974 /* When using movem with pre-decrement addressing, register X + D0_REG
3975 is controlled by bit 15 - X. For all other addressing modes,
3976 register X + D0_REG is controlled by bit X. Confusingly, the
3977 register mask for fmovem is in the opposite order to that for
3981 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
3982 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
3983 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
3984 if (automod_offset
< 0)
3986 if (FP_REGNO_P (regno
))
3987 mask
|= 1 << (regno
- FP0_REG
);
3989 mask
|= 1 << (15 - (regno
- D0_REG
));
3993 if (FP_REGNO_P (regno
))
3994 mask
|= 1 << (7 - (regno
- FP0_REG
));
3996 mask
|= 1 << (regno
- D0_REG
);
4001 if (automod_offset
== 0)
4002 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4003 else if (automod_offset
< 0)
4004 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4006 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4007 operands
[1] = GEN_INT (mask
);
4008 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4011 return "fmovem %1,%a0";
4013 return "fmovem %a0,%1";
4018 return "movem%.l %1,%a0";
4020 return "movem%.l %a0,%1";
4024 /* Return a REG that occurs in ADDR with coefficient 1.
4025 ADDR can be effectively incremented by incrementing REG. */
4028 find_addr_reg (rtx addr
)
4030 while (GET_CODE (addr
) == PLUS
)
4032 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4033 addr
= XEXP (addr
, 0);
4034 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4035 addr
= XEXP (addr
, 1);
4036 else if (CONSTANT_P (XEXP (addr
, 0)))
4037 addr
= XEXP (addr
, 1);
4038 else if (CONSTANT_P (XEXP (addr
, 1)))
4039 addr
= XEXP (addr
, 0);
4043 gcc_assert (GET_CODE (addr
) == REG
);
4047 /* Output assembler code to perform a 32-bit 3-operand add. */
4050 output_addsi3 (rtx
*operands
)
4052 if (! operands_match_p (operands
[0], operands
[1]))
4054 if (!ADDRESS_REG_P (operands
[1]))
4056 rtx tmp
= operands
[1];
4058 operands
[1] = operands
[2];
4062 /* These insns can result from reloads to access
4063 stack slots over 64k from the frame pointer. */
4064 if (GET_CODE (operands
[2]) == CONST_INT
4065 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4066 return "move%.l %2,%0\n\tadd%.l %1,%0";
4067 if (GET_CODE (operands
[2]) == REG
)
4068 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4069 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4071 if (GET_CODE (operands
[2]) == CONST_INT
)
4073 if (INTVAL (operands
[2]) > 0
4074 && INTVAL (operands
[2]) <= 8)
4075 return "addq%.l %2,%0";
4076 if (INTVAL (operands
[2]) < 0
4077 && INTVAL (operands
[2]) >= -8)
4079 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4080 return "subq%.l %2,%0";
4082 /* On the CPU32 it is faster to use two addql instructions to
4083 add a small integer (8 < N <= 16) to a register.
4084 Likewise for subql. */
4085 if (TUNE_CPU32
&& REG_P (operands
[0]))
4087 if (INTVAL (operands
[2]) > 8
4088 && INTVAL (operands
[2]) <= 16)
4090 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4091 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4093 if (INTVAL (operands
[2]) < -8
4094 && INTVAL (operands
[2]) >= -16)
4096 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4097 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4100 if (ADDRESS_REG_P (operands
[0])
4101 && INTVAL (operands
[2]) >= -0x8000
4102 && INTVAL (operands
[2]) < 0x8000)
4105 return "add%.w %2,%0";
4107 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4110 return "add%.l %2,%0";
4113 /* Store in cc_status the expressions that the condition codes will
4114 describe after execution of an instruction whose pattern is EXP.
4115 Do not alter them if the instruction would not alter the cc's. */
4117 /* On the 68000, all the insns to store in an address register fail to
4118 set the cc's. However, in some cases these instructions can make it
4119 possibly invalid to use the saved cc's. In those cases we clear out
4120 some or all of the saved cc's so they won't be used. */
4123 notice_update_cc (rtx exp
, rtx insn
)
4125 if (GET_CODE (exp
) == SET
)
4127 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4129 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4131 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4132 cc_status
.value1
= 0;
4133 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4134 cc_status
.value2
= 0;
4136 /* fmoves to memory or data registers do not set the condition
4137 codes. Normal moves _do_ set the condition codes, but not in
4138 a way that is appropriate for comparison with 0, because -0.0
4139 would be treated as a negative nonzero number. Note that it
4140 isn't appropriate to conditionalize this restriction on
4141 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4142 we care about the difference between -0.0 and +0.0. */
4143 else if (!FP_REG_P (SET_DEST (exp
))
4144 && SET_DEST (exp
) != cc0_rtx
4145 && (FP_REG_P (SET_SRC (exp
))
4146 || GET_CODE (SET_SRC (exp
)) == FIX
4147 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4149 /* A pair of move insns doesn't produce a useful overall cc. */
4150 else if (!FP_REG_P (SET_DEST (exp
))
4151 && !FP_REG_P (SET_SRC (exp
))
4152 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4153 && (GET_CODE (SET_SRC (exp
)) == REG
4154 || GET_CODE (SET_SRC (exp
)) == MEM
4155 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4157 else if (SET_DEST (exp
) != pc_rtx
)
4159 cc_status
.flags
= 0;
4160 cc_status
.value1
= SET_DEST (exp
);
4161 cc_status
.value2
= SET_SRC (exp
);
4164 else if (GET_CODE (exp
) == PARALLEL
4165 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4167 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4168 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4170 if (ADDRESS_REG_P (dest
))
4172 else if (dest
!= pc_rtx
)
4174 cc_status
.flags
= 0;
4175 cc_status
.value1
= dest
;
4176 cc_status
.value2
= src
;
4181 if (cc_status
.value2
!= 0
4182 && ADDRESS_REG_P (cc_status
.value2
)
4183 && GET_MODE (cc_status
.value2
) == QImode
)
4185 if (cc_status
.value2
!= 0)
4186 switch (GET_CODE (cc_status
.value2
))
4188 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4189 case ROTATE
: case ROTATERT
:
4190 /* These instructions always clear the overflow bit, and set
4191 the carry to the bit shifted out. */
4192 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4195 case PLUS
: case MINUS
: case MULT
:
4196 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4197 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4198 cc_status
.flags
|= CC_NO_OVERFLOW
;
4201 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4202 ends with a move insn moving r2 in r2's mode.
4203 Thus, the cc's are set for r2.
4204 This can set N bit spuriously. */
4205 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4210 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4212 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4213 cc_status
.value2
= 0;
4214 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4215 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4216 cc_status
.flags
= CC_IN_68881
;
4217 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4218 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4220 cc_status
.flags
= CC_IN_68881
;
4221 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4222 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4223 cc_status
.flags
|= CC_REVERSED
;
4228 output_move_const_double (rtx
*operands
)
4230 int code
= standard_68881_constant_p (operands
[1]);
4234 static char buf
[40];
4236 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4239 return "fmove%.d %1,%0";
4243 output_move_const_single (rtx
*operands
)
4245 int code
= standard_68881_constant_p (operands
[1]);
4249 static char buf
[40];
4251 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4254 return "fmove%.s %f1,%0";
4257 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4258 from the "fmovecr" instruction.
4259 The value, anded with 0xff, gives the code to use in fmovecr
4260 to get the desired constant. */
4262 /* This code has been fixed for cross-compilation. */
4264 static int inited_68881_table
= 0;
4266 static const char *const strings_68881
[7] = {
4276 static const int codes_68881
[7] = {
4286 REAL_VALUE_TYPE values_68881
[7];
4288 /* Set up values_68881 array by converting the decimal values
4289 strings_68881 to binary. */
4292 init_68881_table (void)
4296 enum machine_mode mode
;
4299 for (i
= 0; i
< 7; i
++)
4303 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4304 values_68881
[i
] = r
;
4306 inited_68881_table
= 1;
4310 standard_68881_constant_p (rtx x
)
4315 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4316 used at all on those chips. */
4320 if (! inited_68881_table
)
4321 init_68881_table ();
4323 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4325 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4327 for (i
= 0; i
< 6; i
++)
4329 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4330 return (codes_68881
[i
]);
4333 if (GET_MODE (x
) == SFmode
)
4336 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4337 return (codes_68881
[6]);
4339 /* larger powers of ten in the constants ram are not used
4340 because they are not equal to a `double' C constant. */
4344 /* If X is a floating-point constant, return the logarithm of X base 2,
4345 or 0 if X is not a power of 2. */
4348 floating_exact_log2 (rtx x
)
4350 REAL_VALUE_TYPE r
, r1
;
4353 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4355 if (REAL_VALUES_LESS (r
, dconst1
))
4358 exp
= real_exponent (&r
);
4359 real_2expN (&r1
, exp
, DFmode
);
4360 if (REAL_VALUES_EQUAL (r1
, r
))
4366 /* A C compound statement to output to stdio stream STREAM the
4367 assembler syntax for an instruction operand X. X is an RTL
4370 CODE is a value that can be used to specify one of several ways
4371 of printing the operand. It is used when identical operands
4372 must be printed differently depending on the context. CODE
4373 comes from the `%' specification that was used to request
4374 printing of the operand. If the specification was just `%DIGIT'
4375 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4376 is the ASCII code for LTR.
4378 If X is a register, this macro should print the register's name.
4379 The names can be found in an array `reg_names' whose type is
4380 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4382 When the machine description has a specification `%PUNCT' (a `%'
4383 followed by a punctuation character), this macro is called with
4384 a null pointer for X and the punctuation character for CODE.
4386 The m68k specific codes are:
4388 '.' for dot needed in Motorola-style opcode names.
4389 '-' for an operand pushing on the stack:
4390 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4391 '+' for an operand pushing on the stack:
4392 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4393 '@' for a reference to the top word on the stack:
4394 sp@, (sp) or (%sp) depending on the style of syntax.
4395 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4396 but & in SGS syntax).
4397 '!' for the cc register (used in an `and to cc' insn).
4398 '$' for the letter `s' in an op code, but only on the 68040.
4399 '&' for the letter `d' in an op code, but only on the 68040.
4400 '/' for register prefix needed by longlong.h.
4401 '?' for m68k_library_id_string
4403 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4404 'd' to force memory addressing to be absolute, not relative.
4405 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4406 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4407 or print pair of registers as rx:ry.
4408 'p' print an address with @PLTPC attached, but only if the operand
4409 is not locally-bound. */
4412 print_operand (FILE *file
, rtx op
, int letter
)
4417 fprintf (file
, ".");
4419 else if (letter
== '#')
4420 asm_fprintf (file
, "%I");
4421 else if (letter
== '-')
4422 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4423 else if (letter
== '+')
4424 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4425 else if (letter
== '@')
4426 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4427 else if (letter
== '!')
4428 asm_fprintf (file
, "%Rfpcr");
4429 else if (letter
== '$')
4432 fprintf (file
, "s");
4434 else if (letter
== '&')
4437 fprintf (file
, "d");
4439 else if (letter
== '/')
4440 asm_fprintf (file
, "%R");
4441 else if (letter
== '?')
4442 asm_fprintf (file
, m68k_library_id_string
);
4443 else if (letter
== 'p')
4445 output_addr_const (file
, op
);
4446 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4447 fprintf (file
, "@PLTPC");
4449 else if (GET_CODE (op
) == REG
)
4452 /* Print out the second register name of a register pair.
4453 I.e., R (6) => 7. */
4454 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4456 fputs (M68K_REGNAME(REGNO (op
)), file
);
4458 else if (GET_CODE (op
) == MEM
)
4460 output_address (XEXP (op
, 0));
4461 if (letter
== 'd' && ! TARGET_68020
4462 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4463 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4464 && INTVAL (XEXP (op
, 0)) < 0x8000
4465 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4466 fprintf (file
, MOTOROLA
? ".l" : ":l");
4468 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4472 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4473 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4474 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4476 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4480 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4481 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4482 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4483 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4485 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4489 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4490 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4491 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4495 /* Use `print_operand_address' instead of `output_addr_const'
4496 to ensure that we print relevant PIC stuff. */
4497 asm_fprintf (file
, "%I");
4499 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4500 print_operand_address (file
, op
);
4502 output_addr_const (file
, op
);
4506 /* Return string for TLS relocation RELOC. */
4509 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4511 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4512 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4519 if (flag_pic
== 1 && TARGET_68020
)
4560 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4563 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4565 if (GET_CODE (x
) == UNSPEC
)
4567 switch (XINT (x
, 1))
4569 case UNSPEC_RELOC16
:
4570 case UNSPEC_RELOC32
:
4571 output_addr_const (file
, XVECEXP (x
, 0, 0));
4572 fputs (m68k_get_reloc_decoration
4573 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4584 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4587 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4589 gcc_assert (size
== 4);
4590 fputs ("\t.long\t", file
);
4591 output_addr_const (file
, x
);
4592 fputs ("@TLSLDO+0x8000", file
);
4595 /* In the name of slightly smaller debug output, and to cater to
4596 general assembler lossage, recognize various UNSPEC sequences
4597 and turn them back into a direct symbol reference. */
4600 m68k_delegitimize_address (rtx orig_x
)
4603 struct m68k_address addr
;
4606 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4611 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4614 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4615 || addr
.offset
== NULL_RTX
4616 || GET_CODE (addr
.offset
) != CONST
)
4619 unspec
= XEXP (addr
.offset
, 0);
4620 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4621 unspec
= XEXP (unspec
, 0);
4622 if (GET_CODE (unspec
) != UNSPEC
4623 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4624 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4626 x
= XVECEXP (unspec
, 0, 0);
4627 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4628 if (unspec
!= XEXP (addr
.offset
, 0))
4629 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4632 rtx idx
= addr
.index
;
4633 if (addr
.scale
!= 1)
4634 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4635 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4638 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4640 x
= replace_equiv_address_nv (orig_x
, x
);
4645 /* A C compound statement to output to stdio stream STREAM the
4646 assembler syntax for an instruction operand that is a memory
4647 reference whose address is ADDR. ADDR is an RTL expression.
4649 Note that this contains a kludge that knows that the only reason
4650 we have an address (plus (label_ref...) (reg...)) when not generating
4651 PIC code is in the insn before a tablejump, and we know that m68k.md
4652 generates a label LInnn: on such an insn.
4654 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4655 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4657 This routine is responsible for distinguishing between -fpic and -fPIC
4658 style relocations in an address. When generating -fpic code the
4659 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4660 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4663 print_operand_address (FILE *file
, rtx addr
)
4665 struct m68k_address address
;
4667 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4670 if (address
.code
== PRE_DEC
)
4671 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4672 M68K_REGNAME (REGNO (address
.base
)));
4673 else if (address
.code
== POST_INC
)
4674 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4675 M68K_REGNAME (REGNO (address
.base
)));
4676 else if (!address
.base
&& !address
.index
)
4678 /* A constant address. */
4679 gcc_assert (address
.offset
== addr
);
4680 if (GET_CODE (addr
) == CONST_INT
)
4682 /* (xxx).w or (xxx).l. */
4683 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4684 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4686 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4688 else if (TARGET_PCREL
)
4690 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4692 output_addr_const (file
, addr
);
4693 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4697 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4698 name ends in `.<letter>', as the last 2 characters can be
4699 mistaken as a size suffix. Put the name in parentheses. */
4700 if (GET_CODE (addr
) == SYMBOL_REF
4701 && strlen (XSTR (addr
, 0)) > 2
4702 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4705 output_addr_const (file
, addr
);
4709 output_addr_const (file
, addr
);
4716 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4717 label being accessed, otherwise it is -1. */
4718 labelno
= (address
.offset
4720 && GET_CODE (address
.offset
) == LABEL_REF
4721 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4725 /* Print the "offset(base" component. */
4727 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4731 output_addr_const (file
, address
.offset
);
4735 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4737 /* Print the ",index" component, if any. */
4742 fprintf (file
, "%s.%c",
4743 M68K_REGNAME (REGNO (address
.index
)),
4744 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4745 if (address
.scale
!= 1)
4746 fprintf (file
, "*%d", address
.scale
);
4750 else /* !MOTOROLA */
4752 if (!address
.offset
&& !address
.index
)
4753 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4756 /* Print the "base@(offset" component. */
4758 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4762 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4763 fprintf (file
, "@(");
4765 output_addr_const (file
, address
.offset
);
4767 /* Print the ",index" component, if any. */
4770 fprintf (file
, ",%s:%c",
4771 M68K_REGNAME (REGNO (address
.index
)),
4772 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4773 if (address
.scale
!= 1)
4774 fprintf (file
, ":%d", address
.scale
);
4782 /* Check for cases where a clr insns can be omitted from code using
4783 strict_low_part sets. For example, the second clrl here is not needed:
4784 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4786 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4787 insn we are checking for redundancy. TARGET is the register set by the
4791 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4796 while ((p
= PREV_INSN (p
)))
4798 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4804 /* If it isn't an insn, then give up. */
4808 if (reg_set_p (target
, p
))
4810 rtx set
= single_set (p
);
4813 /* If it isn't an easy to recognize insn, then give up. */
4817 dest
= SET_DEST (set
);
4819 /* If this sets the entire target register to zero, then our
4820 first_insn is redundant. */
4821 if (rtx_equal_p (dest
, target
)
4822 && SET_SRC (set
) == const0_rtx
)
4824 else if (GET_CODE (dest
) == STRICT_LOW_PART
4825 && GET_CODE (XEXP (dest
, 0)) == REG
4826 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4827 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4828 <= GET_MODE_SIZE (mode
)))
4829 /* This is a strict low part set which modifies less than
4830 we are using, so it is safe. */
4840 /* Operand predicates for implementing asymmetric pc-relative addressing
4841 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4842 when used as a source operand, but not as a destination operand.
4844 We model this by restricting the meaning of the basic predicates
4845 (general_operand, memory_operand, etc) to forbid the use of this
4846 addressing mode, and then define the following predicates that permit
4847 this addressing mode. These predicates can then be used for the
4848 source operands of the appropriate instructions.
4850 n.b. While it is theoretically possible to change all machine patterns
4851 to use this addressing more where permitted by the architecture,
4852 it has only been implemented for "common" cases: SImode, HImode, and
4853 QImode operands, and only for the principle operations that would
4854 require this addressing mode: data movement and simple integer operations.
4856 In parallel with these new predicates, two new constraint letters
4857 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4858 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4859 In the pcrel case 's' is only valid in combination with 'a' registers.
4860 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4861 of how these constraints are used.
4863 The use of these predicates is strictly optional, though patterns that
4864 don't will cause an extra reload register to be allocated where one
4867 lea (abc:w,%pc),%a0 ; need to reload address
4868 moveq &1,%d1 ; since write to pc-relative space
4869 movel %d1,%a0@ ; is not allowed
4871 lea (abc:w,%pc),%a1 ; no need to reload address here
4872 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4874 For more info, consult tiemann@cygnus.com.
4877 All of the ugliness with predicates and constraints is due to the
4878 simple fact that the m68k does not allow a pc-relative addressing
4879 mode as a destination. gcc does not distinguish between source and
4880 destination addresses. Hence, if we claim that pc-relative address
4881 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4882 end up with invalid code. To get around this problem, we left
4883 pc-relative modes as invalid addresses, and then added special
4884 predicates and constraints to accept them.
4886 A cleaner way to handle this is to modify gcc to distinguish
4887 between source and destination addresses. We can then say that
4888 pc-relative is a valid source address but not a valid destination
4889 address, and hopefully avoid a lot of the predicate and constraint
4890 hackery. Unfortunately, this would be a pretty big change. It would
4891 be a useful change for a number of ports, but there aren't any current
4892 plans to undertake this.
4894 ***************************************************************************/
4898 output_andsi3 (rtx
*operands
)
4901 if (GET_CODE (operands
[2]) == CONST_INT
4902 && (INTVAL (operands
[2]) | 0xffff) == -1
4903 && (DATA_REG_P (operands
[0])
4904 || offsettable_memref_p (operands
[0]))
4905 && !TARGET_COLDFIRE
)
4907 if (GET_CODE (operands
[0]) != REG
)
4908 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4909 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4910 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4912 if (operands
[2] == const0_rtx
)
4914 return "and%.w %2,%0";
4916 if (GET_CODE (operands
[2]) == CONST_INT
4917 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4918 && (DATA_REG_P (operands
[0])
4919 || offsettable_memref_p (operands
[0])))
4921 if (DATA_REG_P (operands
[0]))
4922 operands
[1] = GEN_INT (logval
);
4925 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4926 operands
[1] = GEN_INT (logval
% 8);
4928 /* This does not set condition codes in a standard way. */
4930 return "bclr %1,%0";
4932 return "and%.l %2,%0";
4936 output_iorsi3 (rtx
*operands
)
4938 register int logval
;
4939 if (GET_CODE (operands
[2]) == CONST_INT
4940 && INTVAL (operands
[2]) >> 16 == 0
4941 && (DATA_REG_P (operands
[0])
4942 || offsettable_memref_p (operands
[0]))
4943 && !TARGET_COLDFIRE
)
4945 if (GET_CODE (operands
[0]) != REG
)
4946 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4947 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4949 if (INTVAL (operands
[2]) == 0xffff)
4950 return "mov%.w %2,%0";
4951 return "or%.w %2,%0";
4953 if (GET_CODE (operands
[2]) == CONST_INT
4954 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4955 && (DATA_REG_P (operands
[0])
4956 || offsettable_memref_p (operands
[0])))
4958 if (DATA_REG_P (operands
[0]))
4959 operands
[1] = GEN_INT (logval
);
4962 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4963 operands
[1] = GEN_INT (logval
% 8);
4966 return "bset %1,%0";
4968 return "or%.l %2,%0";
4972 output_xorsi3 (rtx
*operands
)
4974 register int logval
;
4975 if (GET_CODE (operands
[2]) == CONST_INT
4976 && INTVAL (operands
[2]) >> 16 == 0
4977 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
4978 && !TARGET_COLDFIRE
)
4980 if (! DATA_REG_P (operands
[0]))
4981 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4982 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4984 if (INTVAL (operands
[2]) == 0xffff)
4986 return "eor%.w %2,%0";
4988 if (GET_CODE (operands
[2]) == CONST_INT
4989 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4990 && (DATA_REG_P (operands
[0])
4991 || offsettable_memref_p (operands
[0])))
4993 if (DATA_REG_P (operands
[0]))
4994 operands
[1] = GEN_INT (logval
);
4997 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4998 operands
[1] = GEN_INT (logval
% 8);
5001 return "bchg %1,%0";
5003 return "eor%.l %2,%0";
5006 /* Return the instruction that should be used for a call to address X,
5007 which is known to be in operand 0. */
5012 if (symbolic_operand (x
, VOIDmode
))
5013 return m68k_symbolic_call
;
5018 /* Likewise sibling calls. */
5021 output_sibcall (rtx x
)
5023 if (symbolic_operand (x
, VOIDmode
))
5024 return m68k_symbolic_jump
;
5030 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5031 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5034 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5036 /* Avoid clobbering the struct value reg by using the
5037 static chain reg as a temporary. */
5038 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5040 /* Pretend to be a post-reload pass while generating rtl. */
5041 reload_completed
= 1;
5043 /* The "this" pointer is stored at 4(%sp). */
5044 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5045 stack_pointer_rtx
, 4));
5047 /* Add DELTA to THIS. */
5050 /* Make the offset a legitimate operand for memory addition. */
5051 offset
= GEN_INT (delta
);
5052 if ((delta
< -8 || delta
> 8)
5053 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5055 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5056 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5058 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5059 copy_rtx (this_slot
), offset
));
5062 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5063 if (vcall_offset
!= 0)
5065 /* Set the static chain register to *THIS. */
5066 emit_move_insn (tmp
, this_slot
);
5067 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5069 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5070 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5071 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5073 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5077 /* Load the offset into %d0 and add it to THIS. */
5078 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5079 gen_rtx_MEM (Pmode
, addr
));
5080 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5081 copy_rtx (this_slot
),
5082 gen_rtx_REG (Pmode
, D0_REG
)));
5085 /* Jump to the target function. Use a sibcall if direct jumps are
5086 allowed, otherwise load the address into a register first. */
5087 mem
= DECL_RTL (function
);
5088 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5090 gcc_assert (flag_pic
);
5092 if (!TARGET_SEP_DATA
)
5094 /* Use the static chain register as a temporary (call-clobbered)
5095 GOT pointer for this function. We can use the static chain
5096 register because it isn't live on entry to the thunk. */
5097 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5098 emit_insn (gen_load_got (pic_offset_table_rtx
));
5100 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5101 mem
= replace_equiv_address (mem
, tmp
);
5103 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5104 SIBLING_CALL_P (insn
) = 1;
5106 /* Run just enough of rest_of_compilation. */
5107 insn
= get_insns ();
5108 split_all_insns_noflow ();
5109 final_start_function (insn
, file
, 1);
5110 final (insn
, file
, 1);
5111 final_end_function ();
5113 /* Clean up the vars set above. */
5114 reload_completed
= 0;
5116 /* Restore the original PIC register. */
5118 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5121 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5124 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5125 int incoming ATTRIBUTE_UNUSED
)
5127 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5130 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5132 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5133 unsigned int new_reg
)
5136 /* Interrupt functions can only use registers that have already been
5137 saved by the prologue, even if they would normally be
5140 if ((m68k_get_function_kind (current_function_decl
)
5141 == m68k_fk_interrupt_handler
)
5142 && !df_regs_ever_live_p (new_reg
))
5148 /* Value is true if hard register REGNO can hold a value of machine-mode
5149 MODE. On the 68000, we let the cpu registers can hold any mode, but
5150 restrict the 68881 registers to floating-point modes. */
5153 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5155 if (DATA_REGNO_P (regno
))
5157 /* Data Registers, can hold aggregate if fits in. */
5158 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5161 else if (ADDRESS_REGNO_P (regno
))
5163 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5166 else if (FP_REGNO_P (regno
))
5168 /* FPU registers, hold float or complex float of long double or
5170 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5171 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5172 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5178 /* Implement SECONDARY_RELOAD_CLASS. */
5181 m68k_secondary_reload_class (enum reg_class rclass
,
5182 enum machine_mode mode
, rtx x
)
5186 regno
= true_regnum (x
);
5188 /* If one operand of a movqi is an address register, the other
5189 operand must be a general register or constant. Other types
5190 of operand must be reloaded through a data register. */
5191 if (GET_MODE_SIZE (mode
) == 1
5192 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5193 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5196 /* PC-relative addresses must be loaded into an address register first. */
5198 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5199 && symbolic_operand (x
, VOIDmode
))
5205 /* Implement PREFERRED_RELOAD_CLASS. */
5208 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5210 enum reg_class secondary_class
;
5212 /* If RCLASS might need a secondary reload, try restricting it to
5213 a class that doesn't. */
5214 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5215 if (secondary_class
!= NO_REGS
5216 && reg_class_subset_p (secondary_class
, rclass
))
5217 return secondary_class
;
5219 /* Prefer to use moveq for in-range constants. */
5220 if (GET_CODE (x
) == CONST_INT
5221 && reg_class_subset_p (DATA_REGS
, rclass
)
5222 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5225 /* ??? Do we really need this now? */
5226 if (GET_CODE (x
) == CONST_DOUBLE
5227 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5229 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5238 /* Return floating point values in a 68881 register. This makes 68881 code
5239 a little bit faster. It also makes -msoft-float code incompatible with
5240 hard-float code, so people have to be careful not to mix the two.
5241 For ColdFire it was decided the ABI incompatibility is undesirable.
5242 If there is need for a hard-float ABI it is probably worth doing it
5243 properly and also passing function arguments in FP registers. */
5245 m68k_libcall_value (enum machine_mode mode
)
5252 return gen_rtx_REG (mode
, FP0_REG
);
5258 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5261 /* Location in which function value is returned.
5262 NOTE: Due to differences in ABIs, don't call this function directly,
5263 use FUNCTION_VALUE instead. */
5265 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5267 enum machine_mode mode
;
5269 mode
= TYPE_MODE (valtype
);
5275 return gen_rtx_REG (mode
, FP0_REG
);
5281 /* If the function returns a pointer, push that into %a0. */
5282 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5283 /* For compatibility with the large body of existing code which
5284 does not always properly declare external functions returning
5285 pointer types, the m68k/SVR4 convention is to copy the value
5286 returned for pointer functions from a0 to d0 in the function
5287 epilogue, so that callers that have neglected to properly
5288 declare the callee can still find the correct return value in
5290 return gen_rtx_PARALLEL
5293 gen_rtx_EXPR_LIST (VOIDmode
,
5294 gen_rtx_REG (mode
, A0_REG
),
5296 gen_rtx_EXPR_LIST (VOIDmode
,
5297 gen_rtx_REG (mode
, D0_REG
),
5299 else if (POINTER_TYPE_P (valtype
))
5300 return gen_rtx_REG (mode
, A0_REG
);
5302 return gen_rtx_REG (mode
, D0_REG
);
5305 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5306 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5308 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5310 enum machine_mode mode
= TYPE_MODE (type
);
5312 if (mode
== BLKmode
)
5315 /* If TYPE's known alignment is less than the alignment of MODE that
5316 would contain the structure, then return in memory. We need to
5317 do so to maintain the compatibility between code compiled with
5318 -mstrict-align and that compiled with -mno-strict-align. */
5319 if (AGGREGATE_TYPE_P (type
)
5320 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5327 /* CPU to schedule the program for. */
5328 enum attr_cpu m68k_sched_cpu
;
5330 /* MAC to schedule the program for. */
5331 enum attr_mac m68k_sched_mac
;
5339 /* Integer register. */
5345 /* Implicit mem reference (e.g. stack). */
5348 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5351 /* Memory with offset but without indexing. EA mode 5. */
5354 /* Memory with indexing. EA mode 6. */
5357 /* Memory referenced by absolute address. EA mode 7. */
5360 /* Immediate operand that doesn't require extension word. */
5363 /* Immediate 16 bit operand. */
5366 /* Immediate 32 bit operand. */
5370 /* Return type of memory ADDR_RTX refers to. */
5371 static enum attr_op_type
5372 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5374 struct m68k_address address
;
5376 if (symbolic_operand (addr_rtx
, VOIDmode
))
5377 return OP_TYPE_MEM7
;
5379 if (!m68k_decompose_address (mode
, addr_rtx
,
5380 reload_completed
, &address
))
5382 gcc_assert (!reload_completed
);
5383 /* Reload will likely fix the address to be in the register. */
5384 return OP_TYPE_MEM234
;
5387 if (address
.scale
!= 0)
5388 return OP_TYPE_MEM6
;
5390 if (address
.base
!= NULL_RTX
)
5392 if (address
.offset
== NULL_RTX
)
5393 return OP_TYPE_MEM234
;
5395 return OP_TYPE_MEM5
;
5398 gcc_assert (address
.offset
!= NULL_RTX
);
5400 return OP_TYPE_MEM7
;
5403 /* Return X or Y (depending on OPX_P) operand of INSN. */
5405 sched_get_operand (rtx insn
, bool opx_p
)
5409 if (recog_memoized (insn
) < 0)
5412 extract_constrain_insn_cached (insn
);
5415 i
= get_attr_opx (insn
);
5417 i
= get_attr_opy (insn
);
5419 if (i
>= recog_data
.n_operands
)
5422 return recog_data
.operand
[i
];
5425 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5426 If ADDRESS_P is true, return type of memory location operand refers to. */
5427 static enum attr_op_type
5428 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5432 op
= sched_get_operand (insn
, opx_p
);
5436 gcc_assert (!reload_completed
);
5441 return sched_address_type (QImode
, op
);
5443 if (memory_operand (op
, VOIDmode
))
5444 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5446 if (register_operand (op
, VOIDmode
))
5448 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5449 || (reload_completed
&& FP_REG_P (op
)))
5455 if (GET_CODE (op
) == CONST_INT
)
5461 /* Check for quick constants. */
5462 switch (get_attr_type (insn
))
5465 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5466 return OP_TYPE_IMM_Q
;
5468 gcc_assert (!reload_completed
);
5472 if (USE_MOVQ (ival
))
5473 return OP_TYPE_IMM_Q
;
5475 gcc_assert (!reload_completed
);
5479 if (valid_mov3q_const (ival
))
5480 return OP_TYPE_IMM_Q
;
5482 gcc_assert (!reload_completed
);
5489 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5490 return OP_TYPE_IMM_W
;
5492 return OP_TYPE_IMM_L
;
5495 if (GET_CODE (op
) == CONST_DOUBLE
)
5497 switch (GET_MODE (op
))
5500 return OP_TYPE_IMM_W
;
5504 return OP_TYPE_IMM_L
;
5511 if (GET_CODE (op
) == CONST
5512 || symbolic_operand (op
, VOIDmode
)
5515 switch (GET_MODE (op
))
5518 return OP_TYPE_IMM_Q
;
5521 return OP_TYPE_IMM_W
;
5524 return OP_TYPE_IMM_L
;
5527 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5529 return OP_TYPE_IMM_W
;
5531 return OP_TYPE_IMM_L
;
5535 gcc_assert (!reload_completed
);
5537 if (FLOAT_MODE_P (GET_MODE (op
)))
5543 /* Implement opx_type attribute.
5544 Return type of INSN's operand X.
5545 If ADDRESS_P is true, return type of memory location operand refers to. */
5547 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5549 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5555 return OPX_TYPE_FPN
;
5558 return OPX_TYPE_MEM1
;
5560 case OP_TYPE_MEM234
:
5561 return OPX_TYPE_MEM234
;
5564 return OPX_TYPE_MEM5
;
5567 return OPX_TYPE_MEM6
;
5570 return OPX_TYPE_MEM7
;
5573 return OPX_TYPE_IMM_Q
;
5576 return OPX_TYPE_IMM_W
;
5579 return OPX_TYPE_IMM_L
;
5586 /* Implement opy_type attribute.
5587 Return type of INSN's operand Y.
5588 If ADDRESS_P is true, return type of memory location operand refers to. */
5590 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5592 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5598 return OPY_TYPE_FPN
;
5601 return OPY_TYPE_MEM1
;
5603 case OP_TYPE_MEM234
:
5604 return OPY_TYPE_MEM234
;
5607 return OPY_TYPE_MEM5
;
5610 return OPY_TYPE_MEM6
;
5613 return OPY_TYPE_MEM7
;
5616 return OPY_TYPE_IMM_Q
;
5619 return OPY_TYPE_IMM_W
;
5622 return OPY_TYPE_IMM_L
;
5629 /* Return size of INSN as int. */
5631 sched_get_attr_size_int (rtx insn
)
5635 switch (get_attr_type (insn
))
5638 /* There should be no references to m68k_sched_attr_size for 'ignore'
5652 switch (get_attr_opx_type (insn
))
5658 case OPX_TYPE_MEM234
:
5659 case OPY_TYPE_IMM_Q
:
5664 /* Here we assume that most absolute references are short. */
5666 case OPY_TYPE_IMM_W
:
5670 case OPY_TYPE_IMM_L
:
5678 switch (get_attr_opy_type (insn
))
5684 case OPY_TYPE_MEM234
:
5685 case OPY_TYPE_IMM_Q
:
5690 /* Here we assume that most absolute references are short. */
5692 case OPY_TYPE_IMM_W
:
5696 case OPY_TYPE_IMM_L
:
5706 gcc_assert (!reload_completed
);
5714 /* Return size of INSN as attribute enum value. */
5716 m68k_sched_attr_size (rtx insn
)
5718 switch (sched_get_attr_size_int (insn
))
5734 /* Return operand X or Y (depending on OPX_P) of INSN,
5735 if it is a MEM, or NULL overwise. */
5736 static enum attr_op_type
5737 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5741 switch (get_attr_opx_type (insn
))
5746 case OPX_TYPE_IMM_Q
:
5747 case OPX_TYPE_IMM_W
:
5748 case OPX_TYPE_IMM_L
:
5752 case OPX_TYPE_MEM234
:
5755 return OP_TYPE_MEM1
;
5758 return OP_TYPE_MEM6
;
5766 switch (get_attr_opy_type (insn
))
5771 case OPY_TYPE_IMM_Q
:
5772 case OPY_TYPE_IMM_W
:
5773 case OPY_TYPE_IMM_L
:
5777 case OPY_TYPE_MEM234
:
5780 return OP_TYPE_MEM1
;
5783 return OP_TYPE_MEM6
;
5791 /* Implement op_mem attribute. */
5793 m68k_sched_attr_op_mem (rtx insn
)
5795 enum attr_op_type opx
;
5796 enum attr_op_type opy
;
5798 opx
= sched_get_opxy_mem_type (insn
, true);
5799 opy
= sched_get_opxy_mem_type (insn
, false);
5801 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5804 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5806 switch (get_attr_opx_access (insn
))
5822 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5824 switch (get_attr_opx_access (insn
))
5840 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5843 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5845 switch (get_attr_opx_access (insn
))
5851 gcc_assert (!reload_completed
);
5856 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5858 switch (get_attr_opx_access (insn
))
5864 gcc_assert (!reload_completed
);
5869 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5872 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5874 switch (get_attr_opx_access (insn
))
5880 gcc_assert (!reload_completed
);
5885 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5886 gcc_assert (!reload_completed
);
5890 /* Data for ColdFire V4 index bypass.
5891 Producer modifies register that is used as index in consumer with
5895 /* Producer instruction. */
5898 /* Consumer instruction. */
5901 /* Scale of indexed memory access within consumer.
5902 Or zero if bypass should not be effective at the moment. */
5904 } sched_cfv4_bypass_data
;
5906 /* An empty state that is used in m68k_sched_adjust_cost. */
5907 static state_t sched_adjust_cost_state
;
5909 /* Implement adjust_cost scheduler hook.
5910 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5912 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5917 if (recog_memoized (def_insn
) < 0
5918 || recog_memoized (insn
) < 0)
5921 if (sched_cfv4_bypass_data
.scale
== 1)
5922 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5924 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5925 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5926 that the data in sched_cfv4_bypass_data is up to date. */
5927 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5928 && sched_cfv4_bypass_data
.con
== insn
);
5933 sched_cfv4_bypass_data
.pro
= NULL
;
5934 sched_cfv4_bypass_data
.con
= NULL
;
5935 sched_cfv4_bypass_data
.scale
= 0;
5938 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5939 && sched_cfv4_bypass_data
.con
== NULL
5940 && sched_cfv4_bypass_data
.scale
== 0);
5942 /* Don't try to issue INSN earlier than DFA permits.
5943 This is especially useful for instructions that write to memory,
5944 as their true dependence (default) latency is better to be set to 0
5945 to workaround alias analysis limitations.
5946 This is, in fact, a machine independent tweak, so, probably,
5947 it should be moved to haifa-sched.c: insn_cost (). */
5948 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5955 /* Return maximal number of insns that can be scheduled on a single cycle. */
5957 m68k_sched_issue_rate (void)
5959 switch (m68k_sched_cpu
)
5975 /* Maximal length of instruction for current CPU.
5976 E.g. it is 3 for any ColdFire core. */
5977 static int max_insn_size
;
5979 /* Data to model instruction buffer of CPU. */
5982 /* True if instruction buffer model is modeled for current CPU. */
5985 /* Size of the instruction buffer in words. */
5988 /* Number of filled words in the instruction buffer. */
5991 /* Additional information about instruction buffer for CPUs that have
5992 a buffer of instruction records, rather then a plain buffer
5993 of instruction words. */
5994 struct _sched_ib_records
5996 /* Size of buffer in records. */
5999 /* Array to hold data on adjustements made to the size of the buffer. */
6002 /* Index of the above array. */
6006 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6010 static struct _sched_ib sched_ib
;
6012 /* ID of memory unit. */
6013 static int sched_mem_unit_code
;
6015 /* Implementation of the targetm.sched.variable_issue () hook.
6016 It is called after INSN was issued. It returns the number of insns
6017 that can possibly get scheduled on the current cycle.
6018 It is used here to determine the effect of INSN on the instruction
6021 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6022 int sched_verbose ATTRIBUTE_UNUSED
,
6023 rtx insn
, int can_issue_more
)
6027 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6029 switch (m68k_sched_cpu
)
6033 insn_size
= sched_get_attr_size_int (insn
);
6037 insn_size
= sched_get_attr_size_int (insn
);
6039 /* ColdFire V3 and V4 cores have instruction buffers that can
6040 accumulate up to 8 instructions regardless of instructions'
6041 sizes. So we should take care not to "prefetch" 24 one-word
6042 or 12 two-words instructions.
6043 To model this behavior we temporarily decrease size of the
6044 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6048 adjust
= max_insn_size
- insn_size
;
6049 sched_ib
.size
-= adjust
;
6051 if (sched_ib
.filled
> sched_ib
.size
)
6052 sched_ib
.filled
= sched_ib
.size
;
6054 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6057 ++sched_ib
.records
.adjust_index
;
6058 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6059 sched_ib
.records
.adjust_index
= 0;
6061 /* Undo adjustement we did 7 instructions ago. */
6063 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6068 gcc_assert (!sched_ib
.enabled_p
);
6076 if (insn_size
> sched_ib
.filled
)
6077 /* Scheduling for register pressure does not always take DFA into
6078 account. Workaround instruction buffer not being filled enough. */
6080 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6081 insn_size
= sched_ib
.filled
;
6086 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6087 || asm_noperands (PATTERN (insn
)) >= 0)
6088 insn_size
= sched_ib
.filled
;
6092 sched_ib
.filled
-= insn_size
;
6094 return can_issue_more
;
6097 /* Return how many instructions should scheduler lookahead to choose the
6100 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6102 return m68k_sched_issue_rate () - 1;
6105 /* Implementation of targetm.sched.init_global () hook.
6106 It is invoked once per scheduling pass and is used here
6107 to initialize scheduler constants. */
6109 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6110 int sched_verbose ATTRIBUTE_UNUSED
,
6111 int n_insns ATTRIBUTE_UNUSED
)
6113 #ifdef ENABLE_CHECKING
6114 /* Check that all instructions have DFA reservations and
6115 that all instructions can be issued from a clean state. */
6120 state
= alloca (state_size ());
6122 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6124 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6126 gcc_assert (insn_has_dfa_reservation_p (insn
));
6128 state_reset (state
);
6129 if (state_transition (state
, insn
) >= 0)
6136 /* Setup target cpu. */
6138 /* ColdFire V4 has a set of features to keep its instruction buffer full
6139 (e.g., a separate memory bus for instructions) and, hence, we do not model
6140 buffer for this CPU. */
6141 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6143 switch (m68k_sched_cpu
)
6146 sched_ib
.filled
= 0;
6153 sched_ib
.records
.n_insns
= 0;
6154 sched_ib
.records
.adjust
= NULL
;
6159 sched_ib
.records
.n_insns
= 8;
6160 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6167 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6169 sched_adjust_cost_state
= xmalloc (state_size ());
6170 state_reset (sched_adjust_cost_state
);
6173 emit_insn (gen_ib ());
6174 sched_ib
.insn
= get_insns ();
6178 /* Scheduling pass is now finished. Free/reset static variables. */
6180 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6181 int verbose ATTRIBUTE_UNUSED
)
6183 sched_ib
.insn
= NULL
;
6185 free (sched_adjust_cost_state
);
6186 sched_adjust_cost_state
= NULL
;
6188 sched_mem_unit_code
= 0;
6190 free (sched_ib
.records
.adjust
);
6191 sched_ib
.records
.adjust
= NULL
;
6192 sched_ib
.records
.n_insns
= 0;
6196 /* Implementation of targetm.sched.init () hook.
6197 It is invoked each time scheduler starts on the new block (basic block or
6198 extended basic block). */
6200 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6201 int sched_verbose ATTRIBUTE_UNUSED
,
6202 int n_insns ATTRIBUTE_UNUSED
)
6204 switch (m68k_sched_cpu
)
6212 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6214 memset (sched_ib
.records
.adjust
, 0,
6215 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6216 sched_ib
.records
.adjust_index
= 0;
6220 gcc_assert (!sched_ib
.enabled_p
);
6228 if (sched_ib
.enabled_p
)
6229 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6230 the first cycle. Workaround that. */
6231 sched_ib
.filled
= -2;
6234 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6235 It is invoked just before current cycle finishes and is used here
6236 to track if instruction buffer got its two words this cycle. */
6238 m68k_sched_dfa_pre_advance_cycle (void)
6240 if (!sched_ib
.enabled_p
)
6243 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6245 sched_ib
.filled
+= 2;
6247 if (sched_ib
.filled
> sched_ib
.size
)
6248 sched_ib
.filled
= sched_ib
.size
;
6252 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6253 It is invoked just after new cycle begins and is used here
6254 to setup number of filled words in the instruction buffer so that
6255 instructions which won't have all their words prefetched would be
6256 stalled for a cycle. */
6258 m68k_sched_dfa_post_advance_cycle (void)
6262 if (!sched_ib
.enabled_p
)
6265 /* Setup number of prefetched instruction words in the instruction
6267 i
= max_insn_size
- sched_ib
.filled
;
6271 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6276 /* Return X or Y (depending on OPX_P) operand of INSN,
6277 if it is an integer register, or NULL overwise. */
6279 sched_get_reg_operand (rtx insn
, bool opx_p
)
6285 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6287 op
= sched_get_operand (insn
, true);
6288 gcc_assert (op
!= NULL
);
6290 if (!reload_completed
&& !REG_P (op
))
6296 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6298 op
= sched_get_operand (insn
, false);
6299 gcc_assert (op
!= NULL
);
6301 if (!reload_completed
&& !REG_P (op
))
6309 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6312 sched_mem_operand_p (rtx insn
, bool opx_p
)
6314 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6325 /* Return X or Y (depending on OPX_P) operand of INSN,
6326 if it is a MEM, or NULL overwise. */
6328 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6348 if (opy_p
&& sched_mem_operand_p (insn
, false))
6349 return sched_get_operand (insn
, false);
6351 if (opx_p
&& sched_mem_operand_p (insn
, true))
6352 return sched_get_operand (insn
, true);
6358 /* Return non-zero if PRO modifies register used as part of
6361 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6366 pro_x
= sched_get_reg_operand (pro
, true);
6370 con_mem_read
= sched_get_mem_operand (con
, true, false);
6371 gcc_assert (con_mem_read
!= NULL
);
6373 if (reg_mentioned_p (pro_x
, con_mem_read
))
6379 /* Helper function for m68k_sched_indexed_address_bypass_p.
6380 if PRO modifies register used as index in CON,
6381 return scale of indexed memory access in CON. Return zero overwise. */
6383 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6387 struct m68k_address address
;
6389 reg
= sched_get_reg_operand (pro
, true);
6393 mem
= sched_get_mem_operand (con
, true, false);
6394 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6396 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6400 if (REGNO (reg
) == REGNO (address
.index
))
6402 gcc_assert (address
.scale
!= 0);
6403 return address
.scale
;
6409 /* Return non-zero if PRO modifies register used
6410 as index with scale 2 or 4 in CON. */
6412 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6414 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6415 && sched_cfv4_bypass_data
.con
== NULL
6416 && sched_cfv4_bypass_data
.scale
== 0);
6418 switch (sched_get_indexed_address_scale (pro
, con
))
6421 /* We can't have a variable latency bypass, so
6422 remember to adjust the insn cost in adjust_cost hook. */
6423 sched_cfv4_bypass_data
.pro
= pro
;
6424 sched_cfv4_bypass_data
.con
= con
;
6425 sched_cfv4_bypass_data
.scale
= 1;
6437 /* We generate a two-instructions program at M_TRAMP :
6438 movea.l &CHAIN_VALUE,%a0
6440 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6443 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6445 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6448 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6450 mem
= adjust_address (m_tramp
, HImode
, 0);
6451 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6452 mem
= adjust_address (m_tramp
, SImode
, 2);
6453 emit_move_insn (mem
, chain_value
);
6455 mem
= adjust_address (m_tramp
, HImode
, 6);
6456 emit_move_insn (mem
, GEN_INT(0x4EF9));
6457 mem
= adjust_address (m_tramp
, SImode
, 8);
6458 emit_move_insn (mem
, fnaddr
);
6460 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6463 /* On the 68000, the RTS insn cannot pop anything.
6464 On the 68010, the RTD insn may be used to pop them if the number
6465 of args is fixed, but if the number is variable then the caller
6466 must pop them all. RTD can't be used for library calls now
6467 because the library is compiled with the Unix compiler.
6468 Use of RTD is a selectable option, since it is incompatible with
6469 standard Unix calling sequences. If the option is not selected,
6470 the caller must always pop the args. */
6473 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6477 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6478 && (!stdarg_p (funtype
)))
6482 /* Make sure everything's fine if we *don't* have a given processor.
6483 This assumes that putting a register in fixed_regs will keep the
6484 compiler's mitts completely off it. We don't bother to zero it out
6485 of register classes. */
6488 m68k_conditional_register_usage (void)
6492 if (!TARGET_HARD_FLOAT
)
6494 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6495 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6496 if (TEST_HARD_REG_BIT (x
, i
))
6497 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6500 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6504 m68k_init_sync_libfuncs (void)
6506 init_sync_libfuncs (UNITS_PER_WORD
);
6509 #include "gt-m68k.h"