1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
29 #include "fold-const.h"
31 #include "stor-layout.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
39 #include "diagnostic-core.h"
56 #include "cfgcleanup.h"
57 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
58 #include "sched-int.h"
59 #include "insn-codes.h"
65 /* This file should be included last. */
66 #include "target-def.h"
68 enum reg_class regno_reg_class
[] =
70 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
71 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
72 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
73 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
74 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
75 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
80 /* The minimum number of integer registers that we want to save with the
81 movem instruction. Using two movel instructions instead of a single
82 moveml is about 15% faster for the 68020 and 68030 at no expense in
84 #define MIN_MOVEM_REGS 3
86 /* The minimum number of floating point registers that we want to save
87 with the fmovem instruction. */
88 #define MIN_FMOVEM_REGS 1
90 /* Structure describing stack frame layout. */
93 /* Stack pointer to frame pointer offset. */
96 /* Offset of FPU registers. */
97 HOST_WIDE_INT foffset
;
99 /* Frame size in bytes (rounded up). */
102 /* Data and address register. */
104 unsigned int reg_mask
;
108 unsigned int fpu_mask
;
110 /* Offsets relative to ARG_POINTER. */
111 HOST_WIDE_INT frame_pointer_offset
;
112 HOST_WIDE_INT stack_pointer_offset
;
114 /* Function which the above information refers to. */
118 /* Current frame information calculated by m68k_compute_frame_layout(). */
119 static struct m68k_frame current_frame
;
121 /* Structure describing an m68k address.
123 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
124 with null fields evaluating to 0. Here:
126 - BASE satisfies m68k_legitimate_base_reg_p
127 - INDEX satisfies m68k_legitimate_index_reg_p
128 - OFFSET satisfies m68k_legitimate_constant_address_p
130 INDEX is either HImode or SImode. The other fields are SImode.
132 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
133 the address is (BASE)+. */
134 struct m68k_address
{
142 static int m68k_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
144 static int m68k_sched_issue_rate (void);
145 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
146 static void m68k_sched_md_init_global (FILE *, int, int);
147 static void m68k_sched_md_finish_global (FILE *, int);
148 static void m68k_sched_md_init (FILE *, int, int);
149 static void m68k_sched_dfa_pre_advance_cycle (void);
150 static void m68k_sched_dfa_post_advance_cycle (void);
151 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
153 static bool m68k_can_eliminate (const int, const int);
154 static void m68k_conditional_register_usage (void);
155 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
156 static void m68k_option_override (void);
157 static void m68k_override_options_after_change (void);
158 static rtx
find_addr_reg (rtx
);
159 static const char *singlemove_string (rtx
*);
160 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
161 HOST_WIDE_INT
, tree
);
162 static rtx
m68k_struct_value_rtx (tree
, int);
163 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
164 tree args
, int flags
,
166 static void m68k_compute_frame_layout (void);
167 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
168 static bool m68k_ok_for_sibcall_p (tree
, tree
);
169 static bool m68k_tls_symbol_p (rtx
);
170 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
171 static bool m68k_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
172 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
173 static bool m68k_return_in_memory (const_tree
, const_tree
);
175 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
176 static void m68k_trampoline_init (rtx
, tree
, rtx
);
177 static int m68k_return_pops_args (tree
, tree
, int);
178 static rtx
m68k_delegitimize_address (rtx
);
179 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
181 static rtx
m68k_function_arg (cumulative_args_t
, machine_mode
,
183 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
184 static bool m68k_output_addr_const_extra (FILE *, rtx
);
185 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
186 static enum flt_eval_method
187 m68k_excess_precision (enum excess_precision_type
);
189 /* Initialize the GCC target structure. */
191 #if INT_OP_GROUP == INT_OP_DOT_WORD
192 #undef TARGET_ASM_ALIGNED_HI_OP
193 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
196 #if INT_OP_GROUP == INT_OP_NO_DOT
197 #undef TARGET_ASM_BYTE_OP
198 #define TARGET_ASM_BYTE_OP "\tbyte\t"
199 #undef TARGET_ASM_ALIGNED_HI_OP
200 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
201 #undef TARGET_ASM_ALIGNED_SI_OP
202 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
205 #if INT_OP_GROUP == INT_OP_DC
206 #undef TARGET_ASM_BYTE_OP
207 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
208 #undef TARGET_ASM_ALIGNED_HI_OP
209 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
210 #undef TARGET_ASM_ALIGNED_SI_OP
211 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
214 #undef TARGET_ASM_UNALIGNED_HI_OP
215 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
216 #undef TARGET_ASM_UNALIGNED_SI_OP
217 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
219 #undef TARGET_ASM_OUTPUT_MI_THUNK
220 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
221 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
222 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
224 #undef TARGET_ASM_FILE_START_APP_OFF
225 #define TARGET_ASM_FILE_START_APP_OFF true
227 #undef TARGET_LEGITIMIZE_ADDRESS
228 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
230 #undef TARGET_SCHED_ADJUST_COST
231 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
233 #undef TARGET_SCHED_ISSUE_RATE
234 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
236 #undef TARGET_SCHED_VARIABLE_ISSUE
237 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
239 #undef TARGET_SCHED_INIT_GLOBAL
240 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
242 #undef TARGET_SCHED_FINISH_GLOBAL
243 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
245 #undef TARGET_SCHED_INIT
246 #define TARGET_SCHED_INIT m68k_sched_md_init
248 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
249 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
251 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
252 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
254 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
255 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
256 m68k_sched_first_cycle_multipass_dfa_lookahead
258 #undef TARGET_OPTION_OVERRIDE
259 #define TARGET_OPTION_OVERRIDE m68k_option_override
261 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
262 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
264 #undef TARGET_RTX_COSTS
265 #define TARGET_RTX_COSTS m68k_rtx_costs
267 #undef TARGET_ATTRIBUTE_TABLE
268 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
270 #undef TARGET_PROMOTE_PROTOTYPES
271 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
273 #undef TARGET_STRUCT_VALUE_RTX
274 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
276 #undef TARGET_CANNOT_FORCE_CONST_MEM
277 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
279 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
280 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
282 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
283 #undef TARGET_RETURN_IN_MEMORY
284 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
288 #undef TARGET_HAVE_TLS
289 #define TARGET_HAVE_TLS (true)
291 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
292 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
296 #define TARGET_LRA_P hook_bool_void_false
298 #undef TARGET_LEGITIMATE_ADDRESS_P
299 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
301 #undef TARGET_CAN_ELIMINATE
302 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
304 #undef TARGET_CONDITIONAL_REGISTER_USAGE
305 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
307 #undef TARGET_TRAMPOLINE_INIT
308 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
310 #undef TARGET_RETURN_POPS_ARGS
311 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
313 #undef TARGET_DELEGITIMIZE_ADDRESS
314 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
316 #undef TARGET_FUNCTION_ARG
317 #define TARGET_FUNCTION_ARG m68k_function_arg
319 #undef TARGET_FUNCTION_ARG_ADVANCE
320 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
322 #undef TARGET_LEGITIMATE_CONSTANT_P
323 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
325 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
326 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
328 #undef TARGET_C_EXCESS_PRECISION
329 #define TARGET_C_EXCESS_PRECISION m68k_excess_precision
331 /* The value stored by TAS. */
332 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
333 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
335 static const struct attribute_spec m68k_attribute_table
[] =
337 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
338 affects_type_identity } */
339 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
341 { "interrupt_handler", 0, 0, true, false, false,
342 m68k_handle_fndecl_attribute
, false },
343 { "interrupt_thread", 0, 0, true, false, false,
344 m68k_handle_fndecl_attribute
, false },
345 { NULL
, 0, 0, false, false, false, NULL
, false }
348 struct gcc_target targetm
= TARGET_INITIALIZER
;
350 /* Base flags for 68k ISAs. */
351 #define FL_FOR_isa_00 FL_ISA_68000
352 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
353 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
354 generated 68881 code for 68020 and 68030 targets unless explicitly told
356 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
357 | FL_BITFIELD | FL_68881 | FL_CAS)
358 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
359 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
361 /* Base flags for ColdFire ISAs. */
362 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
363 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
364 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
365 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
366 /* ISA_C is not upwardly compatible with ISA_B. */
367 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
371 /* Traditional 68000 instruction sets. */
377 /* ColdFire instruction set variants. */
385 /* Information about one of the -march, -mcpu or -mtune arguments. */
386 struct m68k_target_selection
388 /* The argument being described. */
391 /* For -mcpu, this is the device selected by the option.
392 For -mtune and -march, it is a representative device
393 for the microarchitecture or ISA respectively. */
394 enum target_device device
;
396 /* The M68K_DEVICE fields associated with DEVICE. See the comment
397 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
399 enum uarch_type microarch
;
404 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
405 static const struct m68k_target_selection all_devices
[] =
407 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
408 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
409 #include "m68k-devices.def"
411 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
414 /* A list of all ISAs, mapping each one to a representative device.
415 Used for -march selection. */
416 static const struct m68k_target_selection all_isas
[] =
418 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
419 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
420 #include "m68k-isas.def"
422 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
425 /* A list of all microarchitectures, mapping each one to a representative
426 device. Used for -mtune selection. */
427 static const struct m68k_target_selection all_microarchs
[] =
429 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
430 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
431 #include "m68k-microarchs.def"
432 #undef M68K_MICROARCH
433 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
436 /* The entries associated with the -mcpu, -march and -mtune settings,
437 or null for options that have not been used. */
438 const struct m68k_target_selection
*m68k_cpu_entry
;
439 const struct m68k_target_selection
*m68k_arch_entry
;
440 const struct m68k_target_selection
*m68k_tune_entry
;
442 /* Which CPU we are generating code for. */
443 enum target_device m68k_cpu
;
445 /* Which microarchitecture to tune for. */
446 enum uarch_type m68k_tune
;
448 /* Which FPU to use. */
449 enum fpu_type m68k_fpu
;
451 /* The set of FL_* flags that apply to the target processor. */
452 unsigned int m68k_cpu_flags
;
454 /* The set of FL_* flags that apply to the processor to be tuned for. */
455 unsigned int m68k_tune_flags
;
457 /* Asm templates for calling or jumping to an arbitrary symbolic address,
458 or NULL if such calls or jumps are not supported. The address is held
460 const char *m68k_symbolic_call
;
461 const char *m68k_symbolic_jump
;
463 /* Enum variable that corresponds to m68k_symbolic_call values. */
464 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
467 /* Implement TARGET_OPTION_OVERRIDE. */
470 m68k_option_override (void)
472 const struct m68k_target_selection
*entry
;
473 unsigned long target_mask
;
475 if (global_options_set
.x_m68k_arch_option
)
476 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
478 if (global_options_set
.x_m68k_cpu_option
)
479 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
481 if (global_options_set
.x_m68k_tune_option
)
482 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
490 -march=ARCH should generate code that runs any processor
491 implementing architecture ARCH. -mcpu=CPU should override -march
492 and should generate code that runs on processor CPU, making free
493 use of any instructions that CPU understands. -mtune=UARCH applies
494 on top of -mcpu or -march and optimizes the code for UARCH. It does
495 not change the target architecture. */
498 /* Complain if the -march setting is for a different microarchitecture,
499 or includes flags that the -mcpu setting doesn't. */
501 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
502 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
503 warning (0, "-mcpu=%s conflicts with -march=%s",
504 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
506 entry
= m68k_cpu_entry
;
509 entry
= m68k_arch_entry
;
512 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
514 m68k_cpu_flags
= entry
->flags
;
516 /* Use the architecture setting to derive default values for
520 /* ColdFire is lenient about alignment. */
521 if (!TARGET_COLDFIRE
)
522 target_mask
|= MASK_STRICT_ALIGNMENT
;
524 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
525 target_mask
|= MASK_BITFIELD
;
526 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
527 target_mask
|= MASK_CF_HWDIV
;
528 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
529 target_mask
|= MASK_HARD_FLOAT
;
530 target_flags
|= target_mask
& ~target_flags_explicit
;
532 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
533 m68k_cpu
= entry
->device
;
536 m68k_tune
= m68k_tune_entry
->microarch
;
537 m68k_tune_flags
= m68k_tune_entry
->flags
;
539 #ifdef M68K_DEFAULT_TUNE
540 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
542 enum target_device dev
;
543 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
544 m68k_tune_flags
= all_devices
[dev
].flags
;
549 m68k_tune
= entry
->microarch
;
550 m68k_tune_flags
= entry
->flags
;
553 /* Set the type of FPU. */
554 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
555 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
558 /* Sanity check to ensure that msep-data and mid-sahred-library are not
559 * both specified together. Doing so simply doesn't make sense.
561 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
562 error ("cannot specify both -msep-data and -mid-shared-library");
564 /* If we're generating code for a separate A5 relative data segment,
565 * we've got to enable -fPIC as well. This might be relaxable to
566 * -fpic but it hasn't been tested properly.
568 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
571 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
572 error if the target does not support them. */
573 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
574 error ("-mpcrel -fPIC is not currently supported on selected cpu");
576 /* ??? A historic way of turning on pic, or is this intended to
577 be an embedded thing that doesn't have the same name binding
578 significance that it does on hosted ELF systems? */
579 if (TARGET_PCREL
&& flag_pic
== 0)
584 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
586 m68k_symbolic_jump
= "jra %a0";
588 else if (TARGET_ID_SHARED_LIBRARY
)
589 /* All addresses must be loaded from the GOT. */
591 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
594 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
596 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
599 /* No unconditional long branch */;
600 else if (TARGET_PCREL
)
601 m68k_symbolic_jump
= "bra%.l %c0";
603 m68k_symbolic_jump
= "bra%.l %p0";
604 /* Turn off function cse if we are doing PIC. We always want
605 function call to be done as `bsr foo@PLTPC'. */
606 /* ??? It's traditional to do this for -mpcrel too, but it isn't
607 clear how intentional that is. */
608 flag_no_function_cse
= 1;
611 switch (m68k_symbolic_call_var
)
613 case M68K_SYMBOLIC_CALL_JSR
:
614 m68k_symbolic_call
= "jsr %a0";
617 case M68K_SYMBOLIC_CALL_BSR_C
:
618 m68k_symbolic_call
= "bsr%.l %c0";
621 case M68K_SYMBOLIC_CALL_BSR_P
:
622 m68k_symbolic_call
= "bsr%.l %p0";
625 case M68K_SYMBOLIC_CALL_NONE
:
626 gcc_assert (m68k_symbolic_call
== NULL
);
633 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
634 if (align_labels
> 2)
636 warning (0, "-falign-labels=%d is not supported", align_labels
);
641 warning (0, "-falign-loops=%d is not supported", align_loops
);
646 if ((opt_fstack_limit_symbol_arg
!= NULL
|| opt_fstack_limit_register_no
>= 0)
649 warning (0, "-fstack-limit- options are not supported on this cpu");
650 opt_fstack_limit_symbol_arg
= NULL
;
651 opt_fstack_limit_register_no
= -1;
654 SUBTARGET_OVERRIDE_OPTIONS
;
656 /* Setup scheduling options. */
658 m68k_sched_cpu
= CPU_CFV1
;
660 m68k_sched_cpu
= CPU_CFV2
;
662 m68k_sched_cpu
= CPU_CFV3
;
664 m68k_sched_cpu
= CPU_CFV4
;
667 m68k_sched_cpu
= CPU_UNKNOWN
;
668 flag_schedule_insns
= 0;
669 flag_schedule_insns_after_reload
= 0;
670 flag_modulo_sched
= 0;
671 flag_live_range_shrinkage
= 0;
674 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
676 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
677 m68k_sched_mac
= MAC_CF_EMAC
;
678 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
679 m68k_sched_mac
= MAC_CF_MAC
;
681 m68k_sched_mac
= MAC_NO
;
685 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
688 m68k_override_options_after_change (void)
690 if (m68k_sched_cpu
== CPU_UNKNOWN
)
692 flag_schedule_insns
= 0;
693 flag_schedule_insns_after_reload
= 0;
694 flag_modulo_sched
= 0;
695 flag_live_range_shrinkage
= 0;
699 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
700 given argument and NAME is the argument passed to -mcpu. Return NULL
701 if -mcpu was not passed. */
704 m68k_cpp_cpu_ident (const char *prefix
)
708 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
711 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
712 given argument and NAME is the name of the representative device for
713 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
716 m68k_cpp_cpu_family (const char *prefix
)
720 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
723 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
724 "interrupt_handler" attribute and interrupt_thread if FUNC has an
725 "interrupt_thread" attribute. Otherwise, return
726 m68k_fk_normal_function. */
728 enum m68k_function_kind
729 m68k_get_function_kind (tree func
)
733 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
735 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
737 return m68k_fk_interrupt_handler
;
739 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
741 return m68k_fk_interrupt_handler
;
743 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
745 return m68k_fk_interrupt_thread
;
747 return m68k_fk_normal_function
;
750 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
751 struct attribute_spec.handler. */
753 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
754 tree args ATTRIBUTE_UNUSED
,
755 int flags ATTRIBUTE_UNUSED
,
758 if (TREE_CODE (*node
) != FUNCTION_DECL
)
760 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
762 *no_add_attrs
= true;
765 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
767 error ("multiple interrupt attributes not allowed");
768 *no_add_attrs
= true;
772 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
774 error ("interrupt_thread is available only on fido");
775 *no_add_attrs
= true;
782 m68k_compute_frame_layout (void)
786 enum m68k_function_kind func_kind
=
787 m68k_get_function_kind (current_function_decl
);
788 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
789 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
791 /* Only compute the frame once per function.
792 Don't cache information until reload has been completed. */
793 if (current_frame
.funcdef_no
== current_function_funcdef_no
797 current_frame
.size
= (get_frame_size () + 3) & -4;
801 /* Interrupt thread does not need to save any register. */
802 if (!interrupt_thread
)
803 for (regno
= 0; regno
< 16; regno
++)
804 if (m68k_save_reg (regno
, interrupt_handler
))
806 mask
|= 1 << (regno
- D0_REG
);
809 current_frame
.offset
= saved
* 4;
810 current_frame
.reg_no
= saved
;
811 current_frame
.reg_mask
= mask
;
813 current_frame
.foffset
= 0;
815 if (TARGET_HARD_FLOAT
)
817 /* Interrupt thread does not need to save any register. */
818 if (!interrupt_thread
)
819 for (regno
= 16; regno
< 24; regno
++)
820 if (m68k_save_reg (regno
, interrupt_handler
))
822 mask
|= 1 << (regno
- FP0_REG
);
825 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
826 current_frame
.offset
+= current_frame
.foffset
;
828 current_frame
.fpu_no
= saved
;
829 current_frame
.fpu_mask
= mask
;
831 /* Remember what function this frame refers to. */
832 current_frame
.funcdef_no
= current_function_funcdef_no
;
835 /* Worker function for TARGET_CAN_ELIMINATE. */
838 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
840 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
844 m68k_initial_elimination_offset (int from
, int to
)
847 /* The arg pointer points 8 bytes before the start of the arguments,
848 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
849 frame pointer in most frames. */
850 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
851 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
852 return argptr_offset
;
854 m68k_compute_frame_layout ();
856 gcc_assert (to
== STACK_POINTER_REGNUM
);
859 case ARG_POINTER_REGNUM
:
860 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
861 case FRAME_POINTER_REGNUM
:
862 return current_frame
.offset
+ current_frame
.size
;
868 /* Refer to the array `regs_ever_live' to determine which registers
869 to save; `regs_ever_live[I]' is nonzero if register number I
870 is ever used in the function. This function is responsible for
871 knowing which registers should not be saved even if used.
872 Return true if we need to save REGNO. */
875 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
877 if (flag_pic
&& regno
== PIC_REG
)
879 if (crtl
->saves_all_registers
)
881 if (crtl
->uses_pic_offset_table
)
883 /* Reload may introduce constant pool references into a function
884 that thitherto didn't need a PIC register. Note that the test
885 above will not catch that case because we will only set
886 crtl->uses_pic_offset_table when emitting
887 the address reloads. */
888 if (crtl
->uses_const_pool
)
892 if (crtl
->calls_eh_return
)
897 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
898 if (test
== INVALID_REGNUM
)
905 /* Fixed regs we never touch. */
906 if (fixed_regs
[regno
])
909 /* The frame pointer (if it is such) is handled specially. */
910 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
913 /* Interrupt handlers must also save call_used_regs
914 if they are live or when calling nested functions. */
915 if (interrupt_handler
)
917 if (df_regs_ever_live_p (regno
))
920 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
924 /* Never need to save registers that aren't touched. */
925 if (!df_regs_ever_live_p (regno
))
928 /* Otherwise save everything that isn't call-clobbered. */
929 return !call_used_regs
[regno
];
932 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
933 the lowest memory address. COUNT is the number of registers to be
934 moved, with register REGNO + I being moved if bit I of MASK is set.
935 STORE_P specifies the direction of the move and ADJUST_STACK_P says
936 whether or not this is pre-decrement (if STORE_P) or post-increment
937 (if !STORE_P) operation. */
940 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
941 unsigned int count
, unsigned int regno
,
942 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
945 rtx body
, addr
, src
, operands
[2];
948 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
949 mode
= reg_raw_mode
[regno
];
954 src
= plus_constant (Pmode
, base
,
956 * GET_MODE_SIZE (mode
)
957 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
958 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
961 for (; mask
!= 0; mask
>>= 1, regno
++)
964 addr
= plus_constant (Pmode
, base
, offset
);
965 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
966 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
967 XVECEXP (body
, 0, i
++)
968 = gen_rtx_SET (operands
[0], operands
[1]);
969 offset
+= GET_MODE_SIZE (mode
);
971 gcc_assert (i
== XVECLEN (body
, 0));
973 return emit_insn (body
);
976 /* Make INSN a frame-related instruction. */
979 m68k_set_frame_related (rtx_insn
*insn
)
984 RTX_FRAME_RELATED_P (insn
) = 1;
985 body
= PATTERN (insn
);
986 if (GET_CODE (body
) == PARALLEL
)
987 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
988 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
991 /* Emit RTL for the "prologue" define_expand. */
994 m68k_expand_prologue (void)
996 HOST_WIDE_INT fsize_with_regs
;
997 rtx limit
, src
, dest
;
999 m68k_compute_frame_layout ();
1001 if (flag_stack_usage_info
)
1002 current_function_static_stack_size
1003 = current_frame
.size
+ current_frame
.offset
;
1005 /* If the stack limit is a symbol, we can check it here,
1006 before actually allocating the space. */
1007 if (crtl
->limit_stack
1008 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1010 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1011 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1013 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1014 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1016 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1017 stack_pointer_rtx
, limit
),
1018 stack_pointer_rtx
, limit
,
1022 fsize_with_regs
= current_frame
.size
;
1023 if (TARGET_COLDFIRE
)
1025 /* ColdFire's move multiple instructions do not allow pre-decrement
1026 addressing. Add the size of movem saves to the initial stack
1027 allocation instead. */
1028 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1029 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1030 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1031 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1034 if (frame_pointer_needed
)
1036 if (fsize_with_regs
== 0 && TUNE_68040
)
1038 /* On the 68040, two separate moves are faster than link.w 0. */
1039 dest
= gen_frame_mem (Pmode
,
1040 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1041 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1042 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1043 stack_pointer_rtx
));
1045 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1046 m68k_set_frame_related
1047 (emit_insn (gen_link (frame_pointer_rtx
,
1048 GEN_INT (-4 - fsize_with_regs
))));
1051 m68k_set_frame_related
1052 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1053 m68k_set_frame_related
1054 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1056 GEN_INT (-fsize_with_regs
))));
1059 /* If the frame pointer is needed, emit a special barrier that
1060 will prevent the scheduler from moving stores to the frame
1061 before the stack adjustment. */
1062 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1064 else if (fsize_with_regs
!= 0)
1065 m68k_set_frame_related
1066 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1068 GEN_INT (-fsize_with_regs
))));
1070 if (current_frame
.fpu_mask
)
1072 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1074 m68k_set_frame_related
1075 (m68k_emit_movem (stack_pointer_rtx
,
1076 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1077 current_frame
.fpu_no
, FP0_REG
,
1078 current_frame
.fpu_mask
, true, true));
1083 /* If we're using moveml to save the integer registers,
1084 the stack pointer will point to the bottom of the moveml
1085 save area. Find the stack offset of the first FP register. */
1086 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1089 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1090 m68k_set_frame_related
1091 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1092 current_frame
.fpu_no
, FP0_REG
,
1093 current_frame
.fpu_mask
, true, false));
1097 /* If the stack limit is not a symbol, check it here.
1098 This has the disadvantage that it may be too late... */
1099 if (crtl
->limit_stack
)
1101 if (REG_P (stack_limit_rtx
))
1102 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1104 stack_pointer_rtx
, stack_limit_rtx
,
1107 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1108 warning (0, "stack limit expression is not supported");
1111 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1113 /* Store each register separately in the same order moveml does. */
1116 for (i
= 16; i
-- > 0; )
1117 if (current_frame
.reg_mask
& (1 << i
))
1119 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1120 dest
= gen_frame_mem (SImode
,
1121 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1122 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1127 if (TARGET_COLDFIRE
)
1128 /* The required register save space has already been allocated.
1129 The first register should be stored at (%sp). */
1130 m68k_set_frame_related
1131 (m68k_emit_movem (stack_pointer_rtx
, 0,
1132 current_frame
.reg_no
, D0_REG
,
1133 current_frame
.reg_mask
, true, false));
1135 m68k_set_frame_related
1136 (m68k_emit_movem (stack_pointer_rtx
,
1137 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1138 current_frame
.reg_no
, D0_REG
,
1139 current_frame
.reg_mask
, true, true));
1142 if (!TARGET_SEP_DATA
1143 && crtl
->uses_pic_offset_table
)
1144 emit_insn (gen_load_got (pic_offset_table_rtx
));
1147 /* Return true if a simple (return) instruction is sufficient for this
1148 instruction (i.e. if no epilogue is needed). */
1151 m68k_use_return_insn (void)
1153 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1156 m68k_compute_frame_layout ();
1157 return current_frame
.offset
== 0;
1160 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1161 SIBCALL_P says which.
1163 The function epilogue should not depend on the current stack pointer!
1164 It should use the frame pointer only, if there is a frame pointer.
1165 This is mandatory because of alloca; we also take advantage of it to
1166 omit stack adjustments before returning. */
1169 m68k_expand_epilogue (bool sibcall_p
)
1171 HOST_WIDE_INT fsize
, fsize_with_regs
;
1172 bool big
, restore_from_sp
;
1174 m68k_compute_frame_layout ();
1176 fsize
= current_frame
.size
;
1178 restore_from_sp
= false;
1180 /* FIXME : crtl->is_leaf below is too strong.
1181 What we really need to know there is if there could be pending
1182 stack adjustment needed at that point. */
1183 restore_from_sp
= (!frame_pointer_needed
1184 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1186 /* fsize_with_regs is the size we need to adjust the sp when
1187 popping the frame. */
1188 fsize_with_regs
= fsize
;
1189 if (TARGET_COLDFIRE
&& restore_from_sp
)
1191 /* ColdFire's move multiple instructions do not allow post-increment
1192 addressing. Add the size of movem loads to the final deallocation
1194 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1195 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1196 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1197 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1200 if (current_frame
.offset
+ fsize
>= 0x8000
1202 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1205 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1206 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1208 /* ColdFire's move multiple instructions do not support the
1209 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1210 stack-based restore. */
1211 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1212 GEN_INT (-(current_frame
.offset
+ fsize
)));
1213 emit_insn (gen_blockage ());
1214 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1215 gen_rtx_REG (Pmode
, A1_REG
),
1216 frame_pointer_rtx
));
1217 restore_from_sp
= true;
1221 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1227 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1229 /* Restore each register separately in the same order moveml does. */
1231 HOST_WIDE_INT offset
;
1233 offset
= current_frame
.offset
+ fsize
;
1234 for (i
= 0; i
< 16; i
++)
1235 if (current_frame
.reg_mask
& (1 << i
))
1241 /* Generate the address -OFFSET(%fp,%a1.l). */
1242 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1243 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1244 addr
= plus_constant (Pmode
, addr
, -offset
);
1246 else if (restore_from_sp
)
1247 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1249 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1250 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1251 gen_frame_mem (SImode
, addr
));
1252 offset
-= GET_MODE_SIZE (SImode
);
1255 else if (current_frame
.reg_mask
)
1258 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1259 gen_rtx_REG (Pmode
, A1_REG
),
1261 -(current_frame
.offset
+ fsize
),
1262 current_frame
.reg_no
, D0_REG
,
1263 current_frame
.reg_mask
, false, false);
1264 else if (restore_from_sp
)
1265 m68k_emit_movem (stack_pointer_rtx
, 0,
1266 current_frame
.reg_no
, D0_REG
,
1267 current_frame
.reg_mask
, false,
1270 m68k_emit_movem (frame_pointer_rtx
,
1271 -(current_frame
.offset
+ fsize
),
1272 current_frame
.reg_no
, D0_REG
,
1273 current_frame
.reg_mask
, false, false);
1276 if (current_frame
.fpu_no
> 0)
1279 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1280 gen_rtx_REG (Pmode
, A1_REG
),
1282 -(current_frame
.foffset
+ fsize
),
1283 current_frame
.fpu_no
, FP0_REG
,
1284 current_frame
.fpu_mask
, false, false);
1285 else if (restore_from_sp
)
1287 if (TARGET_COLDFIRE
)
1291 /* If we used moveml to restore the integer registers, the
1292 stack pointer will still point to the bottom of the moveml
1293 save area. Find the stack offset of the first FP
1295 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1298 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1299 m68k_emit_movem (stack_pointer_rtx
, offset
,
1300 current_frame
.fpu_no
, FP0_REG
,
1301 current_frame
.fpu_mask
, false, false);
1304 m68k_emit_movem (stack_pointer_rtx
, 0,
1305 current_frame
.fpu_no
, FP0_REG
,
1306 current_frame
.fpu_mask
, false, true);
1309 m68k_emit_movem (frame_pointer_rtx
,
1310 -(current_frame
.foffset
+ fsize
),
1311 current_frame
.fpu_no
, FP0_REG
,
1312 current_frame
.fpu_mask
, false, false);
1315 emit_insn (gen_blockage ());
1316 if (frame_pointer_needed
)
1317 emit_insn (gen_unlink (frame_pointer_rtx
));
1318 else if (fsize_with_regs
)
1319 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1321 GEN_INT (fsize_with_regs
)));
1323 if (crtl
->calls_eh_return
)
1324 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1326 EH_RETURN_STACKADJ_RTX
));
1329 emit_jump_insn (ret_rtx
);
1332 /* Return true if X is a valid comparison operator for the dbcc
1335 Note it rejects floating point comparison operators.
1336 (In the future we could use Fdbcc).
1338 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1341 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1343 switch (GET_CODE (x
))
1345 case EQ
: case NE
: case GTU
: case LTU
:
1349 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1351 case GT
: case LT
: case GE
: case LE
:
1352 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1358 /* Return nonzero if flags are currently in the 68881 flag register. */
1360 flags_in_68881 (void)
1362 /* We could add support for these in the future */
1363 return cc_status
.flags
& CC_IN_68881
;
1366 /* Return true if PARALLEL contains register REGNO. */
1368 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1372 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1375 if (GET_CODE (parallel
) != PARALLEL
)
1378 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1382 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1383 if (REG_P (x
) && REGNO (x
) == regno
)
1390 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1393 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1395 enum m68k_function_kind kind
;
1397 /* We cannot use sibcalls for nested functions because we use the
1398 static chain register for indirect calls. */
1399 if (CALL_EXPR_STATIC_CHAIN (exp
))
1402 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1404 /* Check that the return value locations are the same. For
1405 example that we aren't returning a value from the sibling in
1406 a D0 register but then need to transfer it to a A0 register. */
1410 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1412 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1414 /* Check that the values are equal or that the result the callee
1415 function returns is superset of what the current function returns. */
1416 if (!(rtx_equal_p (cfun_value
, call_value
)
1417 || (REG_P (cfun_value
)
1418 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1422 kind
= m68k_get_function_kind (current_function_decl
);
1423 if (kind
== m68k_fk_normal_function
)
1424 /* We can always sibcall from a normal function, because it's
1425 undefined if it is calling an interrupt function. */
1428 /* Otherwise we can only sibcall if the function kind is known to be
1430 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1436 /* On the m68k all args are always pushed. */
1439 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1440 machine_mode mode ATTRIBUTE_UNUSED
,
1441 const_tree type ATTRIBUTE_UNUSED
,
1442 bool named ATTRIBUTE_UNUSED
)
1448 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1449 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1451 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1453 *cum
+= (mode
!= BLKmode
1454 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1455 : (int_size_in_bytes (type
) + 3) & ~3);
1458 /* Convert X to a legitimate function call memory reference and return the
1462 m68k_legitimize_call_address (rtx x
)
1464 gcc_assert (MEM_P (x
));
1465 if (call_operand (XEXP (x
, 0), VOIDmode
))
1467 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1470 /* Likewise for sibling calls. */
1473 m68k_legitimize_sibcall_address (rtx x
)
1475 gcc_assert (MEM_P (x
));
1476 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1479 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1480 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1483 /* Convert X to a legitimate address and return it if successful. Otherwise
1486 For the 68000, we handle X+REG by loading X into a register R and
1487 using R+REG. R will go in an address reg and indexing will be used.
1488 However, if REG is a broken-out memory address or multiplication,
1489 nothing needs to be done because REG can certainly go in an address reg. */
1492 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1494 if (m68k_tls_symbol_p (x
))
1495 return m68k_legitimize_tls_address (x
);
1497 if (GET_CODE (x
) == PLUS
)
1499 int ch
= (x
) != (oldx
);
1502 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1504 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1507 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1509 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1512 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1516 if (GET_CODE (XEXP (x
, 1)) == REG
1517 && GET_CODE (XEXP (x
, 0)) == REG
)
1519 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1522 x
= force_operand (x
, 0);
1526 if (memory_address_p (mode
, x
))
1529 if (GET_CODE (XEXP (x
, 0)) == REG
1530 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1531 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1532 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1534 rtx temp
= gen_reg_rtx (Pmode
);
1535 rtx val
= force_operand (XEXP (x
, 1), 0);
1536 emit_move_insn (temp
, val
);
1539 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1540 && GET_CODE (XEXP (x
, 0)) == REG
)
1541 x
= force_operand (x
, 0);
1543 else if (GET_CODE (XEXP (x
, 1)) == REG
1544 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1545 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1546 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1548 rtx temp
= gen_reg_rtx (Pmode
);
1549 rtx val
= force_operand (XEXP (x
, 0), 0);
1550 emit_move_insn (temp
, val
);
1553 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1554 && GET_CODE (XEXP (x
, 1)) == REG
)
1555 x
= force_operand (x
, 0);
1563 /* Output a dbCC; jCC sequence. Note we do not handle the
1564 floating point version of this sequence (Fdbcc). We also
1565 do not handle alternative conditions when CC_NO_OVERFLOW is
1566 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1567 kick those out before we get here. */
1570 output_dbcc_and_branch (rtx
*operands
)
1572 switch (GET_CODE (operands
[3]))
1575 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1579 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1583 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1587 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1591 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1595 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1599 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1603 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1607 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1611 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1618 /* If the decrement is to be done in SImode, then we have
1619 to compensate for the fact that dbcc decrements in HImode. */
1620 switch (GET_MODE (operands
[0]))
1623 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1635 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1638 enum rtx_code op_code
= GET_CODE (op
);
1640 /* This does not produce a useful cc. */
1643 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1644 below. Swap the operands and change the op if these requirements
1645 are not fulfilled. */
1646 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1650 operand1
= operand2
;
1652 op_code
= swap_condition (op_code
);
1654 loperands
[0] = operand1
;
1655 if (GET_CODE (operand1
) == REG
)
1656 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1658 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1659 if (operand2
!= const0_rtx
)
1661 loperands
[2] = operand2
;
1662 if (GET_CODE (operand2
) == REG
)
1663 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1665 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1667 loperands
[4] = gen_label_rtx ();
1668 if (operand2
!= const0_rtx
)
1669 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1672 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1673 output_asm_insn ("tst%.l %0", loperands
);
1675 output_asm_insn ("cmp%.w #0,%0", loperands
);
1677 output_asm_insn ("jne %l4", loperands
);
1679 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1680 output_asm_insn ("tst%.l %1", loperands
);
1682 output_asm_insn ("cmp%.w #0,%1", loperands
);
1685 loperands
[5] = dest
;
1690 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1691 CODE_LABEL_NUMBER (loperands
[4]));
1692 output_asm_insn ("seq %5", loperands
);
1696 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1697 CODE_LABEL_NUMBER (loperands
[4]));
1698 output_asm_insn ("sne %5", loperands
);
1702 loperands
[6] = gen_label_rtx ();
1703 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1704 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1705 CODE_LABEL_NUMBER (loperands
[4]));
1706 output_asm_insn ("sgt %5", loperands
);
1707 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1708 CODE_LABEL_NUMBER (loperands
[6]));
1712 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1713 CODE_LABEL_NUMBER (loperands
[4]));
1714 output_asm_insn ("shi %5", loperands
);
1718 loperands
[6] = gen_label_rtx ();
1719 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1720 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1721 CODE_LABEL_NUMBER (loperands
[4]));
1722 output_asm_insn ("slt %5", loperands
);
1723 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1724 CODE_LABEL_NUMBER (loperands
[6]));
1728 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1729 CODE_LABEL_NUMBER (loperands
[4]));
1730 output_asm_insn ("scs %5", loperands
);
1734 loperands
[6] = gen_label_rtx ();
1735 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1736 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1737 CODE_LABEL_NUMBER (loperands
[4]));
1738 output_asm_insn ("sge %5", loperands
);
1739 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1740 CODE_LABEL_NUMBER (loperands
[6]));
1744 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1745 CODE_LABEL_NUMBER (loperands
[4]));
1746 output_asm_insn ("scc %5", loperands
);
1750 loperands
[6] = gen_label_rtx ();
1751 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1752 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1753 CODE_LABEL_NUMBER (loperands
[4]));
1754 output_asm_insn ("sle %5", loperands
);
1755 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1756 CODE_LABEL_NUMBER (loperands
[6]));
1760 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1761 CODE_LABEL_NUMBER (loperands
[4]));
1762 output_asm_insn ("sls %5", loperands
);
1772 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1774 operands
[0] = countop
;
1775 operands
[1] = dataop
;
1777 if (GET_CODE (countop
) == CONST_INT
)
1779 register int count
= INTVAL (countop
);
1780 /* If COUNT is bigger than size of storage unit in use,
1781 advance to the containing unit of same size. */
1782 if (count
> signpos
)
1784 int offset
= (count
& ~signpos
) / 8;
1785 count
= count
& signpos
;
1786 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1788 if (count
== signpos
)
1789 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1791 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1793 /* These three statements used to use next_insns_test_no...
1794 but it appears that this should do the same job. */
1796 && next_insn_tests_no_inequality (insn
))
1799 && next_insn_tests_no_inequality (insn
))
1802 && next_insn_tests_no_inequality (insn
))
1804 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1805 On some m68k variants unfortunately that's slower than btst.
1806 On 68000 and higher, that should also work for all HImode operands. */
1807 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1809 if (count
== 3 && DATA_REG_P (operands
[1])
1810 && next_insn_tests_no_inequality (insn
))
1812 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1813 return "move%.w %1,%%ccr";
1815 if (count
== 2 && DATA_REG_P (operands
[1])
1816 && next_insn_tests_no_inequality (insn
))
1818 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1819 return "move%.w %1,%%ccr";
1821 /* count == 1 followed by bvc/bvs and
1822 count == 0 followed by bcc/bcs are also possible, but need
1823 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1826 cc_status
.flags
= CC_NOT_NEGATIVE
;
1828 return "btst %0,%1";
1831 /* Return true if X is a legitimate base register. STRICT_P says
1832 whether we need strict checking. */
1835 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1837 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1838 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1843 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1844 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1847 /* Return true if X is a legitimate index register. STRICT_P says
1848 whether we need strict checking. */
1851 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1853 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1858 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1859 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1862 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1863 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1864 ADDRESS if so. STRICT_P says whether we need strict checking. */
1867 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1871 /* Check for a scale factor. */
1873 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1874 && GET_CODE (x
) == MULT
1875 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1876 && (INTVAL (XEXP (x
, 1)) == 2
1877 || INTVAL (XEXP (x
, 1)) == 4
1878 || (INTVAL (XEXP (x
, 1)) == 8
1879 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1881 scale
= INTVAL (XEXP (x
, 1));
1885 /* Check for a word extension. */
1886 if (!TARGET_COLDFIRE
1887 && GET_CODE (x
) == SIGN_EXTEND
1888 && GET_MODE (XEXP (x
, 0)) == HImode
)
1891 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1893 address
->scale
= scale
;
1901 /* Return true if X is an illegitimate symbolic constant. */
1904 m68k_illegitimate_symbolic_constant_p (rtx x
)
1908 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1910 split_const (x
, &base
, &offset
);
1911 if (GET_CODE (base
) == SYMBOL_REF
1912 && !offset_within_block_p (base
, INTVAL (offset
)))
1915 return m68k_tls_reference_p (x
, false);
1918 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1921 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1923 return m68k_illegitimate_symbolic_constant_p (x
);
1926 /* Return true if X is a legitimate constant address that can reach
1927 bytes in the range [X, X + REACH). STRICT_P says whether we need
1931 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1935 if (!CONSTANT_ADDRESS_P (x
))
1939 && !(strict_p
&& TARGET_PCREL
)
1940 && symbolic_operand (x
, VOIDmode
))
1943 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1945 split_const (x
, &base
, &offset
);
1946 if (GET_CODE (base
) == SYMBOL_REF
1947 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1951 return !m68k_tls_reference_p (x
, false);
1954 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1955 labels will become jump tables. */
1958 m68k_jump_table_ref_p (rtx x
)
1960 if (GET_CODE (x
) != LABEL_REF
)
1963 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1964 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1967 insn
= next_nonnote_insn (insn
);
1968 return insn
&& JUMP_TABLE_DATA_P (insn
);
1971 /* Return true if X is a legitimate address for values of mode MODE.
1972 STRICT_P says whether strict checking is needed. If the address
1973 is valid, describe its components in *ADDRESS. */
1976 m68k_decompose_address (machine_mode mode
, rtx x
,
1977 bool strict_p
, struct m68k_address
*address
)
1981 memset (address
, 0, sizeof (*address
));
1983 if (mode
== BLKmode
)
1986 reach
= GET_MODE_SIZE (mode
);
1988 /* Check for (An) (mode 2). */
1989 if (m68k_legitimate_base_reg_p (x
, strict_p
))
1995 /* Check for -(An) and (An)+ (modes 3 and 4). */
1996 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1997 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
1999 address
->code
= GET_CODE (x
);
2000 address
->base
= XEXP (x
, 0);
2004 /* Check for (d16,An) (mode 5). */
2005 if (GET_CODE (x
) == PLUS
2006 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2007 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2008 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2010 address
->base
= XEXP (x
, 0);
2011 address
->offset
= XEXP (x
, 1);
2015 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2016 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2018 if (GET_CODE (x
) == PLUS
2019 && XEXP (x
, 0) == pic_offset_table_rtx
)
2021 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2022 they are invalid in this context. */
2023 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2025 address
->base
= XEXP (x
, 0);
2026 address
->offset
= XEXP (x
, 1);
2031 /* The ColdFire FPU only accepts addressing modes 2-5. */
2032 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2035 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2036 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2037 All these modes are variations of mode 7. */
2038 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2040 address
->offset
= x
;
2044 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2047 ??? do_tablejump creates these addresses before placing the target
2048 label, so we have to assume that unplaced labels are jump table
2049 references. It seems unlikely that we would ever generate indexed
2050 accesses to unplaced labels in other cases. */
2051 if (GET_CODE (x
) == PLUS
2052 && m68k_jump_table_ref_p (XEXP (x
, 1))
2053 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2055 address
->offset
= XEXP (x
, 1);
2059 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2060 (bd,An,Xn.SIZE*SCALE) addresses. */
2064 /* Check for a nonzero base displacement. */
2065 if (GET_CODE (x
) == PLUS
2066 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2068 address
->offset
= XEXP (x
, 1);
2072 /* Check for a suppressed index register. */
2073 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2079 /* Check for a suppressed base register. Do not allow this case
2080 for non-symbolic offsets as it effectively gives gcc freedom
2081 to treat data registers as base registers, which can generate
2084 && symbolic_operand (address
->offset
, VOIDmode
)
2085 && m68k_decompose_index (x
, strict_p
, address
))
2090 /* Check for a nonzero base displacement. */
2091 if (GET_CODE (x
) == PLUS
2092 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2093 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2095 address
->offset
= XEXP (x
, 1);
2100 /* We now expect the sum of a base and an index. */
2101 if (GET_CODE (x
) == PLUS
)
2103 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2104 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2106 address
->base
= XEXP (x
, 0);
2110 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2111 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2113 address
->base
= XEXP (x
, 1);
2120 /* Return true if X is a legitimate address for values of mode MODE.
2121 STRICT_P says whether strict checking is needed. */
2124 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2126 struct m68k_address address
;
2128 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2131 /* Return true if X is a memory, describing its address in ADDRESS if so.
2132 Apply strict checking if called during or after reload. */
2135 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2138 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2139 reload_in_progress
|| reload_completed
,
2143 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2146 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2148 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2151 /* Return true if X matches the 'Q' constraint. It must be a memory
2152 with a base address and no constant offset or index. */
2155 m68k_matches_q_p (rtx x
)
2157 struct m68k_address address
;
2159 return (m68k_legitimate_mem_p (x
, &address
)
2160 && address
.code
== UNKNOWN
2166 /* Return true if X matches the 'U' constraint. It must be a base address
2167 with a constant offset and no index. */
2170 m68k_matches_u_p (rtx x
)
2172 struct m68k_address address
;
2174 return (m68k_legitimate_mem_p (x
, &address
)
2175 && address
.code
== UNKNOWN
2181 /* Return GOT pointer. */
2186 if (pic_offset_table_rtx
== NULL_RTX
)
2187 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2189 crtl
->uses_pic_offset_table
= 1;
2191 return pic_offset_table_rtx
;
2194 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2196 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2197 RELOC_TLSIE
, RELOC_TLSLE
};
2199 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2201 /* Wrap symbol X into unspec representing relocation RELOC.
2202 BASE_REG - register that should be added to the result.
2203 TEMP_REG - if non-null, temporary register. */
2206 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2210 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2212 if (TARGET_COLDFIRE
&& use_x_p
)
2213 /* When compiling with -mx{got, tls} switch the code will look like this:
2215 move.l <X>@<RELOC>,<TEMP_REG>
2216 add.l <BASE_REG>,<TEMP_REG> */
2218 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2219 to put @RELOC after reference. */
2220 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2222 x
= gen_rtx_CONST (Pmode
, x
);
2224 if (temp_reg
== NULL
)
2226 gcc_assert (can_create_pseudo_p ());
2227 temp_reg
= gen_reg_rtx (Pmode
);
2230 emit_move_insn (temp_reg
, x
);
2231 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2236 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2238 x
= gen_rtx_CONST (Pmode
, x
);
2240 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2246 /* Helper for m68k_unwrap_symbol.
2247 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2248 sets *RELOC_PTR to relocation type for the symbol. */
2251 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2252 enum m68k_reloc
*reloc_ptr
)
2254 if (GET_CODE (orig
) == CONST
)
2257 enum m68k_reloc dummy
;
2261 if (reloc_ptr
== NULL
)
2264 /* Handle an addend. */
2265 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2266 && CONST_INT_P (XEXP (x
, 1)))
2269 if (GET_CODE (x
) == UNSPEC
)
2271 switch (XINT (x
, 1))
2273 case UNSPEC_RELOC16
:
2274 orig
= XVECEXP (x
, 0, 0);
2275 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2278 case UNSPEC_RELOC32
:
2279 if (unwrap_reloc32_p
)
2281 orig
= XVECEXP (x
, 0, 0);
2282 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2295 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2296 UNSPEC_RELOC32 wrappers. */
2299 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2301 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2304 /* Prescan insn before outputing assembler for it. */
2307 m68k_final_prescan_insn (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2308 rtx
*operands
, int n_operands
)
2312 /* Combine and, possibly, other optimizations may do good job
2314 (const (unspec [(symbol)]))
2316 (const (plus (unspec [(symbol)])
2318 The problem with this is emitting @TLS or @GOT decorations.
2319 The decoration is emitted when processing (unspec), so the
2320 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2322 It seems that the easiest solution to this is to convert such
2324 (const (unspec [(plus (symbol)
2326 Note, that the top level of operand remains intact, so we don't have
2327 to patch up anything outside of the operand. */
2329 subrtx_var_iterator::array_type array
;
2330 for (i
= 0; i
< n_operands
; ++i
)
2336 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2339 if (m68k_unwrap_symbol (x
, true) != x
)
2343 gcc_assert (GET_CODE (x
) == CONST
);
2346 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2351 unspec
= XEXP (plus
, 0);
2352 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2353 addend
= XEXP (plus
, 1);
2354 gcc_assert (CONST_INT_P (addend
));
2356 /* We now have all the pieces, rearrange them. */
2358 /* Move symbol to plus. */
2359 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2361 /* Move plus inside unspec. */
2362 XVECEXP (unspec
, 0, 0) = plus
;
2364 /* Move unspec to top level of const. */
2365 XEXP (x
, 0) = unspec
;
2367 iter
.skip_subrtxes ();
2373 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2374 If REG is non-null, use it; generate new pseudo otherwise. */
2377 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2381 if (reg
== NULL_RTX
)
2383 gcc_assert (can_create_pseudo_p ());
2384 reg
= gen_reg_rtx (Pmode
);
2387 insn
= emit_move_insn (reg
, x
);
2388 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2390 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2395 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2399 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2401 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2403 x
= gen_rtx_MEM (Pmode
, x
);
2404 MEM_READONLY_P (x
) = 1;
2409 /* Legitimize PIC addresses. If the address is already
2410 position-independent, we return ORIG. Newly generated
2411 position-independent addresses go to REG. If we need more
2412 than one register, we lose.
2414 An address is legitimized by making an indirect reference
2415 through the Global Offset Table with the name of the symbol
2418 The assembler and linker are responsible for placing the
2419 address of the symbol in the GOT. The function prologue
2420 is responsible for initializing a5 to the starting address
2423 The assembler is also responsible for translating a symbol name
2424 into a constant displacement from the start of the GOT.
2426 A quick example may make things a little clearer:
2428 When not generating PIC code to store the value 12345 into _foo
2429 we would generate the following code:
2433 When generating PIC two transformations are made. First, the compiler
2434 loads the address of foo into a register. So the first transformation makes:
2439 The code in movsi will intercept the lea instruction and call this
2440 routine which will transform the instructions into:
2442 movel a5@(_foo:w), a0
2446 That (in a nutshell) is how *all* symbol and label references are
2450 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2455 /* First handle a simple SYMBOL_REF or LABEL_REF */
2456 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2460 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2461 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2463 else if (GET_CODE (orig
) == CONST
)
2467 /* Make sure this has not already been legitimized. */
2468 if (m68k_unwrap_symbol (orig
, true) != orig
)
2473 /* legitimize both operands of the PLUS */
2474 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2476 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2477 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2478 base
== reg
? 0 : reg
);
2480 if (GET_CODE (orig
) == CONST_INT
)
2481 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2483 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2489 /* The __tls_get_addr symbol. */
2490 static GTY(()) rtx m68k_tls_get_addr
;
2492 /* Return SYMBOL_REF for __tls_get_addr. */
2495 m68k_get_tls_get_addr (void)
2497 if (m68k_tls_get_addr
== NULL_RTX
)
2498 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2500 return m68k_tls_get_addr
;
2503 /* Return libcall result in A0 instead of usual D0. */
2504 static bool m68k_libcall_value_in_a0_p
= false;
2506 /* Emit instruction sequence that calls __tls_get_addr. X is
2507 the TLS symbol we are referencing and RELOC is the symbol type to use
2508 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2509 emitted. A pseudo register with result of __tls_get_addr call is
2513 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2519 /* Emit the call sequence. */
2522 /* FIXME: Unfortunately, emit_library_call_value does not
2523 consider (plus (%a5) (const (unspec))) to be a good enough
2524 operand for push, so it forces it into a register. The bad
2525 thing about this is that combiner, due to copy propagation and other
2526 optimizations, sometimes can not later fix this. As a consequence,
2527 additional register may be allocated resulting in a spill.
2528 For reference, see args processing loops in
2529 calls.c:emit_library_call_value_1.
2530 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2531 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2533 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2534 is the simpliest way of generating a call. The difference between
2535 __tls_get_addr() and libcall is that the result is returned in D0
2536 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2537 which temporarily switches returning the result to A0. */
2539 m68k_libcall_value_in_a0_p
= true;
2540 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2541 Pmode
, 1, x
, Pmode
);
2542 m68k_libcall_value_in_a0_p
= false;
2544 insns
= get_insns ();
2547 gcc_assert (can_create_pseudo_p ());
2548 dest
= gen_reg_rtx (Pmode
);
2549 emit_libcall_block (insns
, dest
, a0
, eqv
);
2554 /* The __tls_get_addr symbol. */
2555 static GTY(()) rtx m68k_read_tp
;
2557 /* Return SYMBOL_REF for __m68k_read_tp. */
2560 m68k_get_m68k_read_tp (void)
2562 if (m68k_read_tp
== NULL_RTX
)
2563 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2565 return m68k_read_tp
;
2568 /* Emit instruction sequence that calls __m68k_read_tp.
2569 A pseudo register with result of __m68k_read_tp call is returned. */
2572 m68k_call_m68k_read_tp (void)
2581 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2582 is the simpliest way of generating a call. The difference between
2583 __m68k_read_tp() and libcall is that the result is returned in D0
2584 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2585 which temporarily switches returning the result to A0. */
2587 /* Emit the call sequence. */
2588 m68k_libcall_value_in_a0_p
= true;
2589 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2591 m68k_libcall_value_in_a0_p
= false;
2592 insns
= get_insns ();
2595 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2596 share the m68k_read_tp result with other IE/LE model accesses. */
2597 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2599 gcc_assert (can_create_pseudo_p ());
2600 dest
= gen_reg_rtx (Pmode
);
2601 emit_libcall_block (insns
, dest
, a0
, eqv
);
2606 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2607 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2611 m68k_legitimize_tls_address (rtx orig
)
2613 switch (SYMBOL_REF_TLS_MODEL (orig
))
2615 case TLS_MODEL_GLOBAL_DYNAMIC
:
2616 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2619 case TLS_MODEL_LOCAL_DYNAMIC
:
2625 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2626 share the LDM result with other LD model accesses. */
2627 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2630 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2632 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2634 if (can_create_pseudo_p ())
2635 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2641 case TLS_MODEL_INITIAL_EXEC
:
2646 a0
= m68k_call_m68k_read_tp ();
2648 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2649 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2651 if (can_create_pseudo_p ())
2652 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2658 case TLS_MODEL_LOCAL_EXEC
:
2663 a0
= m68k_call_m68k_read_tp ();
2665 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2667 if (can_create_pseudo_p ())
2668 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2681 /* Return true if X is a TLS symbol. */
2684 m68k_tls_symbol_p (rtx x
)
2686 if (!TARGET_HAVE_TLS
)
2689 if (GET_CODE (x
) != SYMBOL_REF
)
2692 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2695 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2696 though illegitimate one.
2697 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2700 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2702 if (!TARGET_HAVE_TLS
)
2707 subrtx_var_iterator::array_type array
;
2708 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2712 /* Note: this is not the same as m68k_tls_symbol_p. */
2713 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2716 /* Don't recurse into legitimate TLS references. */
2717 if (m68k_tls_reference_p (x
, true))
2718 iter
.skip_subrtxes ();
2724 enum m68k_reloc reloc
= RELOC_GOT
;
2726 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2727 && TLS_RELOC_P (reloc
));
2733 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2735 /* Return the type of move that should be used for integer I. */
2738 m68k_const_method (HOST_WIDE_INT i
)
2745 /* The ColdFire doesn't have byte or word operations. */
2746 /* FIXME: This may not be useful for the m68060 either. */
2747 if (!TARGET_COLDFIRE
)
2749 /* if -256 < N < 256 but N is not in range for a moveq
2750 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2751 if (USE_MOVQ (i
^ 0xff))
2753 /* Likewise, try with not.w */
2754 if (USE_MOVQ (i
^ 0xffff))
2756 /* This is the only value where neg.w is useful */
2761 /* Try also with swap. */
2763 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2768 /* Try using MVZ/MVS with an immediate value to load constants. */
2769 if (i
>= 0 && i
<= 65535)
2771 if (i
>= -32768 && i
<= 32767)
2775 /* Otherwise, use move.l */
2779 /* Return the cost of moving constant I into a data register. */
2782 const_int_cost (HOST_WIDE_INT i
)
2784 switch (m68k_const_method (i
))
2787 /* Constants between -128 and 127 are cheap due to moveq. */
2795 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2805 m68k_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2806 int opno ATTRIBUTE_UNUSED
,
2807 int *total
, bool speed ATTRIBUTE_UNUSED
)
2809 int code
= GET_CODE (x
);
2814 /* Constant zero is super cheap due to clr instruction. */
2815 if (x
== const0_rtx
)
2818 *total
= const_int_cost (INTVAL (x
));
2828 /* Make 0.0 cheaper than other floating constants to
2829 encourage creating tstsf and tstdf insns. */
2830 if (outer_code
== COMPARE
2831 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2837 /* These are vaguely right for a 68020. */
2838 /* The costs for long multiply have been adjusted to work properly
2839 in synth_mult on the 68020, relative to an average of the time
2840 for add and the time for shift, taking away a little more because
2841 sometimes move insns are needed. */
2842 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2847 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2848 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2850 : TARGET_COLDFIRE ? 3 : 13)
2855 : TUNE_68000_10 ? 5 \
2856 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2857 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2859 : TARGET_COLDFIRE ? 2 : 8)
2862 (TARGET_CF_HWDIV ? 11 \
2863 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2866 /* An lea costs about three times as much as a simple add. */
2868 && GET_CODE (XEXP (x
, 1)) == REG
2869 && GET_CODE (XEXP (x
, 0)) == MULT
2870 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2871 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2872 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2873 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2874 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2876 /* lea an@(dx:l:i),am */
2877 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2887 *total
= COSTS_N_INSNS(1);
2892 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2894 if (INTVAL (XEXP (x
, 1)) < 16)
2895 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2897 /* We're using clrw + swap for these cases. */
2898 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2901 *total
= COSTS_N_INSNS (10); /* Worst case. */
2904 /* A shift by a big integer takes an extra instruction. */
2905 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2906 && (INTVAL (XEXP (x
, 1)) == 16))
2908 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2911 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2912 && !(INTVAL (XEXP (x
, 1)) > 0
2913 && INTVAL (XEXP (x
, 1)) <= 8))
2915 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2921 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2922 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2924 *total
= COSTS_N_INSNS (MULW_COST
);
2925 else if (mode
== QImode
|| mode
== HImode
)
2926 *total
= COSTS_N_INSNS (MULW_COST
);
2928 *total
= COSTS_N_INSNS (MULL_COST
);
2935 if (mode
== QImode
|| mode
== HImode
)
2936 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2937 else if (TARGET_CF_HWDIV
)
2938 *total
= COSTS_N_INSNS (18);
2940 *total
= COSTS_N_INSNS (43); /* div.l */
2944 if (outer_code
== COMPARE
)
2953 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2957 output_move_const_into_data_reg (rtx
*operands
)
2961 i
= INTVAL (operands
[1]);
2962 switch (m68k_const_method (i
))
2965 return "mvzw %1,%0";
2967 return "mvsw %1,%0";
2969 return "moveq %1,%0";
2972 operands
[1] = GEN_INT (i
^ 0xff);
2973 return "moveq %1,%0\n\tnot%.b %0";
2976 operands
[1] = GEN_INT (i
^ 0xffff);
2977 return "moveq %1,%0\n\tnot%.w %0";
2980 return "moveq #-128,%0\n\tneg%.w %0";
2985 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
2986 return "moveq %1,%0\n\tswap %0";
2989 return "move%.l %1,%0";
2995 /* Return true if I can be handled by ISA B's mov3q instruction. */
2998 valid_mov3q_const (HOST_WIDE_INT i
)
3000 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3003 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3004 I is the value of OPERANDS[1]. */
3007 output_move_simode_const (rtx
*operands
)
3013 src
= INTVAL (operands
[1]);
3015 && (DATA_REG_P (dest
) || MEM_P (dest
))
3016 /* clr insns on 68000 read before writing. */
3017 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3018 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3020 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3021 return "mov3q%.l %1,%0";
3022 else if (src
== 0 && ADDRESS_REG_P (dest
))
3023 return "sub%.l %0,%0";
3024 else if (DATA_REG_P (dest
))
3025 return output_move_const_into_data_reg (operands
);
3026 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3028 if (valid_mov3q_const (src
))
3029 return "mov3q%.l %1,%0";
3030 return "move%.w %1,%0";
3032 else if (MEM_P (dest
)
3033 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3034 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3035 && IN_RANGE (src
, -0x8000, 0x7fff))
3037 if (valid_mov3q_const (src
))
3038 return "mov3q%.l %1,%-";
3041 return "move%.l %1,%0";
3045 output_move_simode (rtx
*operands
)
3047 if (GET_CODE (operands
[1]) == CONST_INT
)
3048 return output_move_simode_const (operands
);
3049 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3050 || GET_CODE (operands
[1]) == CONST
)
3051 && push_operand (operands
[0], SImode
))
3053 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3054 || GET_CODE (operands
[1]) == CONST
)
3055 && ADDRESS_REG_P (operands
[0]))
3056 return "lea %a1,%0";
3057 return "move%.l %1,%0";
3061 output_move_himode (rtx
*operands
)
3063 if (GET_CODE (operands
[1]) == CONST_INT
)
3065 if (operands
[1] == const0_rtx
3066 && (DATA_REG_P (operands
[0])
3067 || GET_CODE (operands
[0]) == MEM
)
3068 /* clr insns on 68000 read before writing. */
3069 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3070 || !(GET_CODE (operands
[0]) == MEM
3071 && MEM_VOLATILE_P (operands
[0]))))
3073 else if (operands
[1] == const0_rtx
3074 && ADDRESS_REG_P (operands
[0]))
3075 return "sub%.l %0,%0";
3076 else if (DATA_REG_P (operands
[0])
3077 && INTVAL (operands
[1]) < 128
3078 && INTVAL (operands
[1]) >= -128)
3079 return "moveq %1,%0";
3080 else if (INTVAL (operands
[1]) < 0x8000
3081 && INTVAL (operands
[1]) >= -0x8000)
3082 return "move%.w %1,%0";
3084 else if (CONSTANT_P (operands
[1]))
3085 return "move%.l %1,%0";
3086 return "move%.w %1,%0";
3090 output_move_qimode (rtx
*operands
)
3092 /* 68k family always modifies the stack pointer by at least 2, even for
3093 byte pushes. The 5200 (ColdFire) does not do this. */
3095 /* This case is generated by pushqi1 pattern now. */
3096 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3097 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3098 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3099 && ! ADDRESS_REG_P (operands
[1])
3100 && ! TARGET_COLDFIRE
));
3102 /* clr and st insns on 68000 read before writing. */
3103 if (!ADDRESS_REG_P (operands
[0])
3104 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3105 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3107 if (operands
[1] == const0_rtx
)
3109 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3110 && GET_CODE (operands
[1]) == CONST_INT
3111 && (INTVAL (operands
[1]) & 255) == 255)
3117 if (GET_CODE (operands
[1]) == CONST_INT
3118 && DATA_REG_P (operands
[0])
3119 && INTVAL (operands
[1]) < 128
3120 && INTVAL (operands
[1]) >= -128)
3121 return "moveq %1,%0";
3122 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3123 return "sub%.l %0,%0";
3124 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3125 return "move%.l %1,%0";
3126 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3127 from address registers. */
3128 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3129 return "move%.w %1,%0";
3130 return "move%.b %1,%0";
3134 output_move_stricthi (rtx
*operands
)
3136 if (operands
[1] == const0_rtx
3137 /* clr insns on 68000 read before writing. */
3138 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3139 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3141 return "move%.w %1,%0";
3145 output_move_strictqi (rtx
*operands
)
3147 if (operands
[1] == const0_rtx
3148 /* clr insns on 68000 read before writing. */
3149 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3150 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3152 return "move%.b %1,%0";
3155 /* Return the best assembler insn template
3156 for moving operands[1] into operands[0] as a fullword. */
3159 singlemove_string (rtx
*operands
)
3161 if (GET_CODE (operands
[1]) == CONST_INT
)
3162 return output_move_simode_const (operands
);
3163 return "move%.l %1,%0";
3167 /* Output assembler or rtl code to perform a doubleword move insn
3168 with operands OPERANDS.
3169 Pointers to 3 helper functions should be specified:
3170 HANDLE_REG_ADJUST to adjust a register by a small value,
3171 HANDLE_COMPADR to compute an address and
3172 HANDLE_MOVSI to move 4 bytes. */
3175 handle_move_double (rtx operands
[2],
3176 void (*handle_reg_adjust
) (rtx
, int),
3177 void (*handle_compadr
) (rtx
[2]),
3178 void (*handle_movsi
) (rtx
[2]))
3182 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3187 rtx addreg0
= 0, addreg1
= 0;
3188 int dest_overlapped_low
= 0;
3189 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3194 /* First classify both operands. */
3196 if (REG_P (operands
[0]))
3198 else if (offsettable_memref_p (operands
[0]))
3200 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3202 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3204 else if (GET_CODE (operands
[0]) == MEM
)
3209 if (REG_P (operands
[1]))
3211 else if (CONSTANT_P (operands
[1]))
3213 else if (offsettable_memref_p (operands
[1]))
3215 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3217 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3219 else if (GET_CODE (operands
[1]) == MEM
)
3224 /* Check for the cases that the operand constraints are not supposed
3225 to allow to happen. Generating code for these cases is
3227 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3229 /* If one operand is decrementing and one is incrementing
3230 decrement the former register explicitly
3231 and change that operand into ordinary indexing. */
3233 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3235 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3237 handle_reg_adjust (operands
[0], -size
);
3239 if (GET_MODE (operands
[1]) == XFmode
)
3240 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3241 else if (GET_MODE (operands
[0]) == DFmode
)
3242 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3244 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3247 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3249 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3251 handle_reg_adjust (operands
[1], -size
);
3253 if (GET_MODE (operands
[1]) == XFmode
)
3254 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3255 else if (GET_MODE (operands
[1]) == DFmode
)
3256 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3258 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3262 /* If an operand is an unoffsettable memory ref, find a register
3263 we can increment temporarily to make it refer to the second word. */
3265 if (optype0
== MEMOP
)
3266 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3268 if (optype1
== MEMOP
)
3269 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3271 /* Ok, we can do one word at a time.
3272 Normally we do the low-numbered word first,
3273 but if either operand is autodecrementing then we
3274 do the high-numbered word first.
3276 In either case, set up in LATEHALF the operands to use
3277 for the high-numbered word and in some cases alter the
3278 operands in OPERANDS to be suitable for the low-numbered word. */
3282 if (optype0
== REGOP
)
3284 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3285 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3287 else if (optype0
== OFFSOP
)
3289 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3290 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3294 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3295 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3298 if (optype1
== REGOP
)
3300 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3301 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3303 else if (optype1
== OFFSOP
)
3305 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3306 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3308 else if (optype1
== CNSTOP
)
3310 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3314 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3315 (*CONST_DOUBLE_REAL_VALUE (operands
[1]), l
);
3316 operands
[1] = GEN_INT (l
[0]);
3317 middlehalf
[1] = GEN_INT (l
[1]);
3318 latehalf
[1] = GEN_INT (l
[2]);
3322 /* No non-CONST_DOUBLE constant should ever appear
3324 gcc_assert (!CONSTANT_P (operands
[1]));
3329 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3330 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3334 /* size is not 12: */
3336 if (optype0
== REGOP
)
3337 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3338 else if (optype0
== OFFSOP
)
3339 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3341 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3343 if (optype1
== REGOP
)
3344 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3345 else if (optype1
== OFFSOP
)
3346 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3347 else if (optype1
== CNSTOP
)
3348 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3350 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3353 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3354 word first. We should use the adjusted operand 1 (which is N+4(REG))
3355 for the low word as well, to compensate for the first decrement of
3357 if (optype0
== PUSHOP
3358 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3359 operands
[1] = middlehalf
[1] = latehalf
[1];
3361 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3362 if the upper part of reg N does not appear in the MEM, arrange to
3363 emit the move late-half first. Otherwise, compute the MEM address
3364 into the upper part of N and use that as a pointer to the memory
3366 if (optype0
== REGOP
3367 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3369 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3371 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3372 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3374 /* If both halves of dest are used in the src memory address,
3375 compute the address into latehalf of dest.
3376 Note that this can't happen if the dest is two data regs. */
3378 xops
[0] = latehalf
[0];
3379 xops
[1] = XEXP (operands
[1], 0);
3381 handle_compadr (xops
);
3382 if (GET_MODE (operands
[1]) == XFmode
)
3384 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3385 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3386 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3390 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3391 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3395 && reg_overlap_mentioned_p (middlehalf
[0],
3396 XEXP (operands
[1], 0)))
3398 /* Check for two regs used by both source and dest.
3399 Note that this can't happen if the dest is all data regs.
3400 It can happen if the dest is d6, d7, a0.
3401 But in that case, latehalf is an addr reg, so
3402 the code at compadr does ok. */
3404 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3405 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3408 /* JRV says this can't happen: */
3409 gcc_assert (!addreg0
&& !addreg1
);
3411 /* Only the middle reg conflicts; simply put it last. */
3412 handle_movsi (operands
);
3413 handle_movsi (latehalf
);
3414 handle_movsi (middlehalf
);
3418 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3419 /* If the low half of dest is mentioned in the source memory
3420 address, the arrange to emit the move late half first. */
3421 dest_overlapped_low
= 1;
3424 /* If one or both operands autodecrementing,
3425 do the two words, high-numbered first. */
3427 /* Likewise, the first move would clobber the source of the second one,
3428 do them in the other order. This happens only for registers;
3429 such overlap can't happen in memory unless the user explicitly
3430 sets it up, and that is an undefined circumstance. */
3432 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3433 || (optype0
== REGOP
&& optype1
== REGOP
3434 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3435 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3436 || dest_overlapped_low
)
3438 /* Make any unoffsettable addresses point at high-numbered word. */
3440 handle_reg_adjust (addreg0
, size
- 4);
3442 handle_reg_adjust (addreg1
, size
- 4);
3445 handle_movsi (latehalf
);
3447 /* Undo the adds we just did. */
3449 handle_reg_adjust (addreg0
, -4);
3451 handle_reg_adjust (addreg1
, -4);
3455 handle_movsi (middlehalf
);
3458 handle_reg_adjust (addreg0
, -4);
3460 handle_reg_adjust (addreg1
, -4);
3463 /* Do low-numbered word. */
3465 handle_movsi (operands
);
3469 /* Normal case: do the two words, low-numbered first. */
3471 m68k_final_prescan_insn (NULL
, operands
, 2);
3472 handle_movsi (operands
);
3474 /* Do the middle one of the three words for long double */
3478 handle_reg_adjust (addreg0
, 4);
3480 handle_reg_adjust (addreg1
, 4);
3482 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3483 handle_movsi (middlehalf
);
3486 /* Make any unoffsettable addresses point at high-numbered word. */
3488 handle_reg_adjust (addreg0
, 4);
3490 handle_reg_adjust (addreg1
, 4);
3493 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3494 handle_movsi (latehalf
);
3496 /* Undo the adds we just did. */
3498 handle_reg_adjust (addreg0
, -(size
- 4));
3500 handle_reg_adjust (addreg1
, -(size
- 4));
3505 /* Output assembler code to adjust REG by N. */
3507 output_reg_adjust (rtx reg
, int n
)
3511 gcc_assert (GET_MODE (reg
) == SImode
3512 && -12 <= n
&& n
!= 0 && n
<= 12);
3517 s
= "add%.l #12,%0";
3521 s
= "addq%.l #8,%0";
3525 s
= "addq%.l #4,%0";
3529 s
= "sub%.l #12,%0";
3533 s
= "subq%.l #8,%0";
3537 s
= "subq%.l #4,%0";
3545 output_asm_insn (s
, ®
);
3548 /* Emit rtl code to adjust REG by N. */
3550 emit_reg_adjust (rtx reg1
, int n
)
3554 gcc_assert (GET_MODE (reg1
) == SImode
3555 && -12 <= n
&& n
!= 0 && n
<= 12);
3557 reg1
= copy_rtx (reg1
);
3558 reg2
= copy_rtx (reg1
);
3561 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3563 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3568 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3570 output_compadr (rtx operands
[2])
3572 output_asm_insn ("lea %a1,%0", operands
);
3575 /* Output the best assembler insn for moving operands[1] into operands[0]
3578 output_movsi (rtx operands
[2])
3580 output_asm_insn (singlemove_string (operands
), operands
);
3583 /* Copy OP and change its mode to MODE. */
3585 copy_operand (rtx op
, machine_mode mode
)
3587 /* ??? This looks really ugly. There must be a better way
3588 to change a mode on the operand. */
3589 if (GET_MODE (op
) != VOIDmode
)
3592 op
= gen_rtx_REG (mode
, REGNO (op
));
3596 PUT_MODE (op
, mode
);
3603 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3605 emit_movsi (rtx operands
[2])
3607 operands
[0] = copy_operand (operands
[0], SImode
);
3608 operands
[1] = copy_operand (operands
[1], SImode
);
3610 emit_insn (gen_movsi (operands
[0], operands
[1]));
3613 /* Output assembler code to perform a doubleword move insn
3614 with operands OPERANDS. */
3616 output_move_double (rtx
*operands
)
3618 handle_move_double (operands
,
3619 output_reg_adjust
, output_compadr
, output_movsi
);
3624 /* Output rtl code to perform a doubleword move insn
3625 with operands OPERANDS. */
3627 m68k_emit_move_double (rtx operands
[2])
3629 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3632 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3633 new rtx with the correct mode. */
3636 force_mode (machine_mode mode
, rtx orig
)
3638 if (mode
== GET_MODE (orig
))
3641 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3644 return gen_rtx_REG (mode
, REGNO (orig
));
3648 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3650 return reg_renumber
&& FP_REG_P (op
);
3653 /* Emit insns to move operands[1] into operands[0].
3655 Return 1 if we have written out everything that needs to be done to
3656 do the move. Otherwise, return 0 and the caller will emit the move
3659 Note SCRATCH_REG may not be in the proper mode depending on how it
3660 will be used. This routine is responsible for creating a new copy
3661 of SCRATCH_REG in the proper mode. */
3664 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3666 register rtx operand0
= operands
[0];
3667 register rtx operand1
= operands
[1];
3671 && reload_in_progress
&& GET_CODE (operand0
) == REG
3672 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3673 operand0
= reg_equiv_mem (REGNO (operand0
));
3674 else if (scratch_reg
3675 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3676 && GET_CODE (SUBREG_REG (operand0
)) == REG
3677 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3679 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3680 the code which tracks sets/uses for delete_output_reload. */
3681 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3682 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3683 SUBREG_BYTE (operand0
));
3684 operand0
= alter_subreg (&temp
, true);
3688 && reload_in_progress
&& GET_CODE (operand1
) == REG
3689 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3690 operand1
= reg_equiv_mem (REGNO (operand1
));
3691 else if (scratch_reg
3692 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3693 && GET_CODE (SUBREG_REG (operand1
)) == REG
3694 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3696 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3697 the code which tracks sets/uses for delete_output_reload. */
3698 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3699 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3700 SUBREG_BYTE (operand1
));
3701 operand1
= alter_subreg (&temp
, true);
3704 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3705 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3706 != XEXP (operand0
, 0)))
3707 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3708 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3709 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3710 != XEXP (operand1
, 0)))
3711 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3713 /* Handle secondary reloads for loads/stores of FP registers where
3714 the address is symbolic by using the scratch register */
3715 if (fp_reg_operand (operand0
, mode
)
3716 && ((GET_CODE (operand1
) == MEM
3717 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3718 || ((GET_CODE (operand1
) == SUBREG
3719 && GET_CODE (XEXP (operand1
, 0)) == MEM
3720 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3723 if (GET_CODE (operand1
) == SUBREG
)
3724 operand1
= XEXP (operand1
, 0);
3726 /* SCRATCH_REG will hold an address. We want
3727 it in SImode regardless of what mode it was originally given
3729 scratch_reg
= force_mode (SImode
, scratch_reg
);
3731 /* D might not fit in 14 bits either; for such cases load D into
3733 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3735 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3736 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3738 XEXP (XEXP (operand1
, 0), 0),
3742 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3743 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3746 else if (fp_reg_operand (operand1
, mode
)
3747 && ((GET_CODE (operand0
) == MEM
3748 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3749 || ((GET_CODE (operand0
) == SUBREG
)
3750 && GET_CODE (XEXP (operand0
, 0)) == MEM
3751 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3754 if (GET_CODE (operand0
) == SUBREG
)
3755 operand0
= XEXP (operand0
, 0);
3757 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3758 it in SIMODE regardless of what mode it was originally given
3760 scratch_reg
= force_mode (SImode
, scratch_reg
);
3762 /* D might not fit in 14 bits either; for such cases load D into
3764 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3766 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3767 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3770 XEXP (XEXP (operand0
, 0),
3775 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3776 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3779 /* Handle secondary reloads for loads of FP registers from constant
3780 expressions by forcing the constant into memory.
3782 use scratch_reg to hold the address of the memory location.
3784 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3785 NO_REGS when presented with a const_int and an register class
3786 containing only FP registers. Doing so unfortunately creates
3787 more problems than it solves. Fix this for 2.5. */
3788 else if (fp_reg_operand (operand0
, mode
)
3789 && CONSTANT_P (operand1
)
3794 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3795 it in SIMODE regardless of what mode it was originally given
3797 scratch_reg
= force_mode (SImode
, scratch_reg
);
3799 /* Force the constant into memory and put the address of the
3800 memory location into scratch_reg. */
3801 xoperands
[0] = scratch_reg
;
3802 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3803 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3805 /* Now load the destination register. */
3806 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3810 /* Now have insn-emit do whatever it normally does. */
3814 /* Split one or more DImode RTL references into pairs of SImode
3815 references. The RTL can be REG, offsettable MEM, integer constant, or
3816 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3817 split and "num" is its length. lo_half and hi_half are output arrays
3818 that parallel "operands". */
3821 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3825 rtx op
= operands
[num
];
3827 /* simplify_subreg refuses to split volatile memory addresses,
3828 but we still have to handle it. */
3829 if (GET_CODE (op
) == MEM
)
3831 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3832 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3836 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3837 GET_MODE (op
) == VOIDmode
3838 ? DImode
: GET_MODE (op
), 4);
3839 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3840 GET_MODE (op
) == VOIDmode
3841 ? DImode
: GET_MODE (op
), 0);
3846 /* Split X into a base and a constant offset, storing them in *BASE
3847 and *OFFSET respectively. */
3850 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3853 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3855 *offset
+= INTVAL (XEXP (x
, 1));
3861 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3862 instruction. STORE_P says whether the move is a load or store.
3864 If the instruction uses post-increment or pre-decrement addressing,
3865 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3866 adjustment. This adjustment will be made by the first element of
3867 PARALLEL, with the loads or stores starting at element 1. If the
3868 instruction does not use post-increment or pre-decrement addressing,
3869 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3870 start at element 0. */
3873 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3874 HOST_WIDE_INT automod_offset
, bool store_p
)
3876 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3877 HOST_WIDE_INT offset
, mem_offset
;
3879 enum reg_class rclass
;
3881 len
= XVECLEN (pattern
, 0);
3882 first
= (automod_base
!= NULL
);
3886 /* Stores must be pre-decrement and loads must be post-increment. */
3887 if (store_p
!= (automod_offset
< 0))
3890 /* Work out the base and offset for lowest memory location. */
3891 base
= automod_base
;
3892 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3896 /* Allow any valid base and offset in the first access. */
3903 for (i
= first
; i
< len
; i
++)
3905 /* We need a plain SET. */
3906 set
= XVECEXP (pattern
, 0, i
);
3907 if (GET_CODE (set
) != SET
)
3910 /* Check that we have a memory location... */
3911 mem
= XEXP (set
, !store_p
);
3912 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3915 /* ...with the right address. */
3918 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3919 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3920 There are no mode restrictions for 680x0 besides the
3921 automodification rules enforced above. */
3923 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3928 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3929 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3933 /* Check that we have a register of the required mode and class. */
3934 reg
= XEXP (set
, store_p
);
3936 || !HARD_REGISTER_P (reg
)
3937 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3942 /* The register must belong to RCLASS and have a higher number
3943 than the register in the previous SET. */
3944 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3945 || REGNO (last_reg
) >= REGNO (reg
))
3950 /* Work out which register class we need. */
3951 if (INT_REGNO_P (REGNO (reg
)))
3952 rclass
= GENERAL_REGS
;
3953 else if (FP_REGNO_P (REGNO (reg
)))
3960 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3963 /* If we have an automodification, check whether the final offset is OK. */
3964 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3967 /* Reject unprofitable cases. */
3968 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3974 /* Return the assembly code template for a movem or fmovem instruction
3975 whose pattern is given by PATTERN. Store the template's operands
3978 If the instruction uses post-increment or pre-decrement addressing,
3979 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3980 is true if this is a store instruction. */
3983 m68k_output_movem (rtx
*operands
, rtx pattern
,
3984 HOST_WIDE_INT automod_offset
, bool store_p
)
3989 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
3991 first
= (automod_offset
!= 0);
3992 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
3994 /* When using movem with pre-decrement addressing, register X + D0_REG
3995 is controlled by bit 15 - X. For all other addressing modes,
3996 register X + D0_REG is controlled by bit X. Confusingly, the
3997 register mask for fmovem is in the opposite order to that for
4001 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4002 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4003 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4004 if (automod_offset
< 0)
4006 if (FP_REGNO_P (regno
))
4007 mask
|= 1 << (regno
- FP0_REG
);
4009 mask
|= 1 << (15 - (regno
- D0_REG
));
4013 if (FP_REGNO_P (regno
))
4014 mask
|= 1 << (7 - (regno
- FP0_REG
));
4016 mask
|= 1 << (regno
- D0_REG
);
4021 if (automod_offset
== 0)
4022 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4023 else if (automod_offset
< 0)
4024 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4026 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4027 operands
[1] = GEN_INT (mask
);
4028 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4031 return "fmovem %1,%a0";
4033 return "fmovem %a0,%1";
4038 return "movem%.l %1,%a0";
4040 return "movem%.l %a0,%1";
4044 /* Return a REG that occurs in ADDR with coefficient 1.
4045 ADDR can be effectively incremented by incrementing REG. */
4048 find_addr_reg (rtx addr
)
4050 while (GET_CODE (addr
) == PLUS
)
4052 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4053 addr
= XEXP (addr
, 0);
4054 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4055 addr
= XEXP (addr
, 1);
4056 else if (CONSTANT_P (XEXP (addr
, 0)))
4057 addr
= XEXP (addr
, 1);
4058 else if (CONSTANT_P (XEXP (addr
, 1)))
4059 addr
= XEXP (addr
, 0);
4063 gcc_assert (GET_CODE (addr
) == REG
);
4067 /* Output assembler code to perform a 32-bit 3-operand add. */
4070 output_addsi3 (rtx
*operands
)
4072 if (! operands_match_p (operands
[0], operands
[1]))
4074 if (!ADDRESS_REG_P (operands
[1]))
4076 rtx tmp
= operands
[1];
4078 operands
[1] = operands
[2];
4082 /* These insns can result from reloads to access
4083 stack slots over 64k from the frame pointer. */
4084 if (GET_CODE (operands
[2]) == CONST_INT
4085 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4086 return "move%.l %2,%0\n\tadd%.l %1,%0";
4087 if (GET_CODE (operands
[2]) == REG
)
4088 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4089 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4091 if (GET_CODE (operands
[2]) == CONST_INT
)
4093 if (INTVAL (operands
[2]) > 0
4094 && INTVAL (operands
[2]) <= 8)
4095 return "addq%.l %2,%0";
4096 if (INTVAL (operands
[2]) < 0
4097 && INTVAL (operands
[2]) >= -8)
4099 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4100 return "subq%.l %2,%0";
4102 /* On the CPU32 it is faster to use two addql instructions to
4103 add a small integer (8 < N <= 16) to a register.
4104 Likewise for subql. */
4105 if (TUNE_CPU32
&& REG_P (operands
[0]))
4107 if (INTVAL (operands
[2]) > 8
4108 && INTVAL (operands
[2]) <= 16)
4110 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4111 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4113 if (INTVAL (operands
[2]) < -8
4114 && INTVAL (operands
[2]) >= -16)
4116 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4117 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4120 if (ADDRESS_REG_P (operands
[0])
4121 && INTVAL (operands
[2]) >= -0x8000
4122 && INTVAL (operands
[2]) < 0x8000)
4125 return "add%.w %2,%0";
4127 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4130 return "add%.l %2,%0";
4133 /* Store in cc_status the expressions that the condition codes will
4134 describe after execution of an instruction whose pattern is EXP.
4135 Do not alter them if the instruction would not alter the cc's. */
4137 /* On the 68000, all the insns to store in an address register fail to
4138 set the cc's. However, in some cases these instructions can make it
4139 possibly invalid to use the saved cc's. In those cases we clear out
4140 some or all of the saved cc's so they won't be used. */
4143 notice_update_cc (rtx exp
, rtx insn
)
4145 if (GET_CODE (exp
) == SET
)
4147 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4149 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4151 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4152 cc_status
.value1
= 0;
4153 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4154 cc_status
.value2
= 0;
4156 /* fmoves to memory or data registers do not set the condition
4157 codes. Normal moves _do_ set the condition codes, but not in
4158 a way that is appropriate for comparison with 0, because -0.0
4159 would be treated as a negative nonzero number. Note that it
4160 isn't appropriate to conditionalize this restriction on
4161 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4162 we care about the difference between -0.0 and +0.0. */
4163 else if (!FP_REG_P (SET_DEST (exp
))
4164 && SET_DEST (exp
) != cc0_rtx
4165 && (FP_REG_P (SET_SRC (exp
))
4166 || GET_CODE (SET_SRC (exp
)) == FIX
4167 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4169 /* A pair of move insns doesn't produce a useful overall cc. */
4170 else if (!FP_REG_P (SET_DEST (exp
))
4171 && !FP_REG_P (SET_SRC (exp
))
4172 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4173 && (GET_CODE (SET_SRC (exp
)) == REG
4174 || GET_CODE (SET_SRC (exp
)) == MEM
4175 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4177 else if (SET_DEST (exp
) != pc_rtx
)
4179 cc_status
.flags
= 0;
4180 cc_status
.value1
= SET_DEST (exp
);
4181 cc_status
.value2
= SET_SRC (exp
);
4184 else if (GET_CODE (exp
) == PARALLEL
4185 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4187 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4188 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4190 if (ADDRESS_REG_P (dest
))
4192 else if (dest
!= pc_rtx
)
4194 cc_status
.flags
= 0;
4195 cc_status
.value1
= dest
;
4196 cc_status
.value2
= src
;
4201 if (cc_status
.value2
!= 0
4202 && ADDRESS_REG_P (cc_status
.value2
)
4203 && GET_MODE (cc_status
.value2
) == QImode
)
4205 if (cc_status
.value2
!= 0)
4206 switch (GET_CODE (cc_status
.value2
))
4208 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4209 case ROTATE
: case ROTATERT
:
4210 /* These instructions always clear the overflow bit, and set
4211 the carry to the bit shifted out. */
4212 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4215 case PLUS
: case MINUS
: case MULT
:
4216 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4217 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4218 cc_status
.flags
|= CC_NO_OVERFLOW
;
4221 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4222 ends with a move insn moving r2 in r2's mode.
4223 Thus, the cc's are set for r2.
4224 This can set N bit spuriously. */
4225 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4230 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4232 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4233 cc_status
.value2
= 0;
4234 /* Check for PRE_DEC in dest modifying a register used in src. */
4235 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4236 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4238 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4240 cc_status
.value2
= 0;
4241 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4242 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4243 cc_status
.flags
= CC_IN_68881
;
4244 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4245 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4247 cc_status
.flags
= CC_IN_68881
;
4248 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4249 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4250 cc_status
.flags
|= CC_REVERSED
;
4255 output_move_const_double (rtx
*operands
)
4257 int code
= standard_68881_constant_p (operands
[1]);
4261 static char buf
[40];
4263 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4266 return "fmove%.d %1,%0";
4270 output_move_const_single (rtx
*operands
)
4272 int code
= standard_68881_constant_p (operands
[1]);
4276 static char buf
[40];
4278 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4281 return "fmove%.s %f1,%0";
4284 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4285 from the "fmovecr" instruction.
4286 The value, anded with 0xff, gives the code to use in fmovecr
4287 to get the desired constant. */
4289 /* This code has been fixed for cross-compilation. */
4291 static int inited_68881_table
= 0;
4293 static const char *const strings_68881
[7] = {
4303 static const int codes_68881
[7] = {
4313 REAL_VALUE_TYPE values_68881
[7];
4315 /* Set up values_68881 array by converting the decimal values
4316 strings_68881 to binary. */
4319 init_68881_table (void)
4326 for (i
= 0; i
< 7; i
++)
4330 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4331 values_68881
[i
] = r
;
4333 inited_68881_table
= 1;
4337 standard_68881_constant_p (rtx x
)
4339 const REAL_VALUE_TYPE
*r
;
4342 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4343 used at all on those chips. */
4347 if (! inited_68881_table
)
4348 init_68881_table ();
4350 r
= CONST_DOUBLE_REAL_VALUE (x
);
4352 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4353 for (i
= 0; i
< 6; i
++)
4355 if (real_identical (r
, &values_68881
[i
]))
4356 return (codes_68881
[i
]);
4359 if (GET_MODE (x
) == SFmode
)
4362 if (real_equal (r
, &values_68881
[6]))
4363 return (codes_68881
[6]);
4365 /* larger powers of ten in the constants ram are not used
4366 because they are not equal to a `double' C constant. */
4370 /* If X is a floating-point constant, return the logarithm of X base 2,
4371 or 0 if X is not a power of 2. */
4374 floating_exact_log2 (rtx x
)
4376 const REAL_VALUE_TYPE
*r
;
4380 r
= CONST_DOUBLE_REAL_VALUE (x
);
4382 if (real_less (r
, &dconst1
))
4385 exp
= real_exponent (r
);
4386 real_2expN (&r1
, exp
, DFmode
);
4387 if (real_equal (&r1
, r
))
4393 /* A C compound statement to output to stdio stream STREAM the
4394 assembler syntax for an instruction operand X. X is an RTL
4397 CODE is a value that can be used to specify one of several ways
4398 of printing the operand. It is used when identical operands
4399 must be printed differently depending on the context. CODE
4400 comes from the `%' specification that was used to request
4401 printing of the operand. If the specification was just `%DIGIT'
4402 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4403 is the ASCII code for LTR.
4405 If X is a register, this macro should print the register's name.
4406 The names can be found in an array `reg_names' whose type is
4407 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4409 When the machine description has a specification `%PUNCT' (a `%'
4410 followed by a punctuation character), this macro is called with
4411 a null pointer for X and the punctuation character for CODE.
4413 The m68k specific codes are:
4415 '.' for dot needed in Motorola-style opcode names.
4416 '-' for an operand pushing on the stack:
4417 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4418 '+' for an operand pushing on the stack:
4419 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4420 '@' for a reference to the top word on the stack:
4421 sp@, (sp) or (%sp) depending on the style of syntax.
4422 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4423 but & in SGS syntax).
4424 '!' for the cc register (used in an `and to cc' insn).
4425 '$' for the letter `s' in an op code, but only on the 68040.
4426 '&' for the letter `d' in an op code, but only on the 68040.
4427 '/' for register prefix needed by longlong.h.
4428 '?' for m68k_library_id_string
4430 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4431 'd' to force memory addressing to be absolute, not relative.
4432 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4433 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4434 or print pair of registers as rx:ry.
4435 'p' print an address with @PLTPC attached, but only if the operand
4436 is not locally-bound. */
4439 print_operand (FILE *file
, rtx op
, int letter
)
4444 fprintf (file
, ".");
4446 else if (letter
== '#')
4447 asm_fprintf (file
, "%I");
4448 else if (letter
== '-')
4449 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4450 else if (letter
== '+')
4451 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4452 else if (letter
== '@')
4453 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4454 else if (letter
== '!')
4455 asm_fprintf (file
, "%Rfpcr");
4456 else if (letter
== '$')
4459 fprintf (file
, "s");
4461 else if (letter
== '&')
4464 fprintf (file
, "d");
4466 else if (letter
== '/')
4467 asm_fprintf (file
, "%R");
4468 else if (letter
== '?')
4469 asm_fprintf (file
, m68k_library_id_string
);
4470 else if (letter
== 'p')
4472 output_addr_const (file
, op
);
4473 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4474 fprintf (file
, "@PLTPC");
4476 else if (GET_CODE (op
) == REG
)
4479 /* Print out the second register name of a register pair.
4480 I.e., R (6) => 7. */
4481 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4483 fputs (M68K_REGNAME(REGNO (op
)), file
);
4485 else if (GET_CODE (op
) == MEM
)
4487 output_address (GET_MODE (op
), XEXP (op
, 0));
4488 if (letter
== 'd' && ! TARGET_68020
4489 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4490 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4491 && INTVAL (XEXP (op
, 0)) < 0x8000
4492 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4493 fprintf (file
, MOTOROLA
? ".l" : ":l");
4495 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4498 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4499 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4501 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4504 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4505 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4506 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4508 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4511 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4512 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4516 /* Use `print_operand_address' instead of `output_addr_const'
4517 to ensure that we print relevant PIC stuff. */
4518 asm_fprintf (file
, "%I");
4520 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4521 print_operand_address (file
, op
);
4523 output_addr_const (file
, op
);
4527 /* Return string for TLS relocation RELOC. */
4530 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4532 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4533 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4540 if (flag_pic
== 1 && TARGET_68020
)
4582 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4585 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4587 if (GET_CODE (x
) == UNSPEC
)
4589 switch (XINT (x
, 1))
4591 case UNSPEC_RELOC16
:
4592 case UNSPEC_RELOC32
:
4593 output_addr_const (file
, XVECEXP (x
, 0, 0));
4594 fputs (m68k_get_reloc_decoration
4595 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4606 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4609 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4611 gcc_assert (size
== 4);
4612 fputs ("\t.long\t", file
);
4613 output_addr_const (file
, x
);
4614 fputs ("@TLSLDO+0x8000", file
);
4617 /* In the name of slightly smaller debug output, and to cater to
4618 general assembler lossage, recognize various UNSPEC sequences
4619 and turn them back into a direct symbol reference. */
4622 m68k_delegitimize_address (rtx orig_x
)
4625 struct m68k_address addr
;
4628 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4633 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4636 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4637 || addr
.offset
== NULL_RTX
4638 || GET_CODE (addr
.offset
) != CONST
)
4641 unspec
= XEXP (addr
.offset
, 0);
4642 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4643 unspec
= XEXP (unspec
, 0);
4644 if (GET_CODE (unspec
) != UNSPEC
4645 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4646 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4648 x
= XVECEXP (unspec
, 0, 0);
4649 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4650 if (unspec
!= XEXP (addr
.offset
, 0))
4651 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4654 rtx idx
= addr
.index
;
4655 if (addr
.scale
!= 1)
4656 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4657 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4660 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4662 x
= replace_equiv_address_nv (orig_x
, x
);
4667 /* A C compound statement to output to stdio stream STREAM the
4668 assembler syntax for an instruction operand that is a memory
4669 reference whose address is ADDR. ADDR is an RTL expression.
4671 Note that this contains a kludge that knows that the only reason
4672 we have an address (plus (label_ref...) (reg...)) when not generating
4673 PIC code is in the insn before a tablejump, and we know that m68k.md
4674 generates a label LInnn: on such an insn.
4676 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4677 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4679 This routine is responsible for distinguishing between -fpic and -fPIC
4680 style relocations in an address. When generating -fpic code the
4681 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4682 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4685 print_operand_address (FILE *file
, rtx addr
)
4687 struct m68k_address address
;
4689 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4692 if (address
.code
== PRE_DEC
)
4693 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4694 M68K_REGNAME (REGNO (address
.base
)));
4695 else if (address
.code
== POST_INC
)
4696 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4697 M68K_REGNAME (REGNO (address
.base
)));
4698 else if (!address
.base
&& !address
.index
)
4700 /* A constant address. */
4701 gcc_assert (address
.offset
== addr
);
4702 if (GET_CODE (addr
) == CONST_INT
)
4704 /* (xxx).w or (xxx).l. */
4705 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4706 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4708 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4710 else if (TARGET_PCREL
)
4712 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4714 output_addr_const (file
, addr
);
4715 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4719 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4720 name ends in `.<letter>', as the last 2 characters can be
4721 mistaken as a size suffix. Put the name in parentheses. */
4722 if (GET_CODE (addr
) == SYMBOL_REF
4723 && strlen (XSTR (addr
, 0)) > 2
4724 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4727 output_addr_const (file
, addr
);
4731 output_addr_const (file
, addr
);
4738 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4739 label being accessed, otherwise it is -1. */
4740 labelno
= (address
.offset
4742 && GET_CODE (address
.offset
) == LABEL_REF
4743 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4747 /* Print the "offset(base" component. */
4749 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4753 output_addr_const (file
, address
.offset
);
4757 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4759 /* Print the ",index" component, if any. */
4764 fprintf (file
, "%s.%c",
4765 M68K_REGNAME (REGNO (address
.index
)),
4766 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4767 if (address
.scale
!= 1)
4768 fprintf (file
, "*%d", address
.scale
);
4772 else /* !MOTOROLA */
4774 if (!address
.offset
&& !address
.index
)
4775 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4778 /* Print the "base@(offset" component. */
4780 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4784 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4785 fprintf (file
, "@(");
4787 output_addr_const (file
, address
.offset
);
4789 /* Print the ",index" component, if any. */
4792 fprintf (file
, ",%s:%c",
4793 M68K_REGNAME (REGNO (address
.index
)),
4794 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4795 if (address
.scale
!= 1)
4796 fprintf (file
, ":%d", address
.scale
);
4804 /* Check for cases where a clr insns can be omitted from code using
4805 strict_low_part sets. For example, the second clrl here is not needed:
4806 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4808 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4809 insn we are checking for redundancy. TARGET is the register set by the
4813 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4816 rtx_insn
*p
= first_insn
;
4818 while ((p
= PREV_INSN (p
)))
4820 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4826 /* If it isn't an insn, then give up. */
4830 if (reg_set_p (target
, p
))
4832 rtx set
= single_set (p
);
4835 /* If it isn't an easy to recognize insn, then give up. */
4839 dest
= SET_DEST (set
);
4841 /* If this sets the entire target register to zero, then our
4842 first_insn is redundant. */
4843 if (rtx_equal_p (dest
, target
)
4844 && SET_SRC (set
) == const0_rtx
)
4846 else if (GET_CODE (dest
) == STRICT_LOW_PART
4847 && GET_CODE (XEXP (dest
, 0)) == REG
4848 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4849 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4850 <= GET_MODE_SIZE (mode
)))
4851 /* This is a strict low part set which modifies less than
4852 we are using, so it is safe. */
4862 /* Operand predicates for implementing asymmetric pc-relative addressing
4863 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4864 when used as a source operand, but not as a destination operand.
4866 We model this by restricting the meaning of the basic predicates
4867 (general_operand, memory_operand, etc) to forbid the use of this
4868 addressing mode, and then define the following predicates that permit
4869 this addressing mode. These predicates can then be used for the
4870 source operands of the appropriate instructions.
4872 n.b. While it is theoretically possible to change all machine patterns
4873 to use this addressing more where permitted by the architecture,
4874 it has only been implemented for "common" cases: SImode, HImode, and
4875 QImode operands, and only for the principle operations that would
4876 require this addressing mode: data movement and simple integer operations.
4878 In parallel with these new predicates, two new constraint letters
4879 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4880 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4881 In the pcrel case 's' is only valid in combination with 'a' registers.
4882 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4883 of how these constraints are used.
4885 The use of these predicates is strictly optional, though patterns that
4886 don't will cause an extra reload register to be allocated where one
4889 lea (abc:w,%pc),%a0 ; need to reload address
4890 moveq &1,%d1 ; since write to pc-relative space
4891 movel %d1,%a0@ ; is not allowed
4893 lea (abc:w,%pc),%a1 ; no need to reload address here
4894 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4896 For more info, consult tiemann@cygnus.com.
4899 All of the ugliness with predicates and constraints is due to the
4900 simple fact that the m68k does not allow a pc-relative addressing
4901 mode as a destination. gcc does not distinguish between source and
4902 destination addresses. Hence, if we claim that pc-relative address
4903 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4904 end up with invalid code. To get around this problem, we left
4905 pc-relative modes as invalid addresses, and then added special
4906 predicates and constraints to accept them.
4908 A cleaner way to handle this is to modify gcc to distinguish
4909 between source and destination addresses. We can then say that
4910 pc-relative is a valid source address but not a valid destination
4911 address, and hopefully avoid a lot of the predicate and constraint
4912 hackery. Unfortunately, this would be a pretty big change. It would
4913 be a useful change for a number of ports, but there aren't any current
4914 plans to undertake this.
4916 ***************************************************************************/
4920 output_andsi3 (rtx
*operands
)
4923 if (GET_CODE (operands
[2]) == CONST_INT
4924 && (INTVAL (operands
[2]) | 0xffff) == -1
4925 && (DATA_REG_P (operands
[0])
4926 || offsettable_memref_p (operands
[0]))
4927 && !TARGET_COLDFIRE
)
4929 if (GET_CODE (operands
[0]) != REG
)
4930 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4931 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4932 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4934 if (operands
[2] == const0_rtx
)
4936 return "and%.w %2,%0";
4938 if (GET_CODE (operands
[2]) == CONST_INT
4939 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4940 && (DATA_REG_P (operands
[0])
4941 || offsettable_memref_p (operands
[0])))
4943 if (DATA_REG_P (operands
[0]))
4944 operands
[1] = GEN_INT (logval
);
4947 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4948 operands
[1] = GEN_INT (logval
% 8);
4950 /* This does not set condition codes in a standard way. */
4952 return "bclr %1,%0";
4954 return "and%.l %2,%0";
4958 output_iorsi3 (rtx
*operands
)
4960 register int logval
;
4961 if (GET_CODE (operands
[2]) == CONST_INT
4962 && INTVAL (operands
[2]) >> 16 == 0
4963 && (DATA_REG_P (operands
[0])
4964 || offsettable_memref_p (operands
[0]))
4965 && !TARGET_COLDFIRE
)
4967 if (GET_CODE (operands
[0]) != REG
)
4968 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4969 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4971 if (INTVAL (operands
[2]) == 0xffff)
4972 return "mov%.w %2,%0";
4973 return "or%.w %2,%0";
4975 if (GET_CODE (operands
[2]) == CONST_INT
4976 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4977 && (DATA_REG_P (operands
[0])
4978 || offsettable_memref_p (operands
[0])))
4980 if (DATA_REG_P (operands
[0]))
4981 operands
[1] = GEN_INT (logval
);
4984 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4985 operands
[1] = GEN_INT (logval
% 8);
4988 return "bset %1,%0";
4990 return "or%.l %2,%0";
4994 output_xorsi3 (rtx
*operands
)
4996 register int logval
;
4997 if (GET_CODE (operands
[2]) == CONST_INT
4998 && INTVAL (operands
[2]) >> 16 == 0
4999 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5000 && !TARGET_COLDFIRE
)
5002 if (! DATA_REG_P (operands
[0]))
5003 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5004 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5006 if (INTVAL (operands
[2]) == 0xffff)
5008 return "eor%.w %2,%0";
5010 if (GET_CODE (operands
[2]) == CONST_INT
5011 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5012 && (DATA_REG_P (operands
[0])
5013 || offsettable_memref_p (operands
[0])))
5015 if (DATA_REG_P (operands
[0]))
5016 operands
[1] = GEN_INT (logval
);
5019 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5020 operands
[1] = GEN_INT (logval
% 8);
5023 return "bchg %1,%0";
5025 return "eor%.l %2,%0";
5028 /* Return the instruction that should be used for a call to address X,
5029 which is known to be in operand 0. */
5034 if (symbolic_operand (x
, VOIDmode
))
5035 return m68k_symbolic_call
;
5040 /* Likewise sibling calls. */
5043 output_sibcall (rtx x
)
5045 if (symbolic_operand (x
, VOIDmode
))
5046 return m68k_symbolic_jump
;
5052 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5053 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5056 rtx this_slot
, offset
, addr
, mem
, tmp
;
5059 /* Avoid clobbering the struct value reg by using the
5060 static chain reg as a temporary. */
5061 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5063 /* Pretend to be a post-reload pass while generating rtl. */
5064 reload_completed
= 1;
5066 /* The "this" pointer is stored at 4(%sp). */
5067 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5068 stack_pointer_rtx
, 4));
5070 /* Add DELTA to THIS. */
5073 /* Make the offset a legitimate operand for memory addition. */
5074 offset
= GEN_INT (delta
);
5075 if ((delta
< -8 || delta
> 8)
5076 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5078 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5079 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5081 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5082 copy_rtx (this_slot
), offset
));
5085 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5086 if (vcall_offset
!= 0)
5088 /* Set the static chain register to *THIS. */
5089 emit_move_insn (tmp
, this_slot
);
5090 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5092 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5093 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5094 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5096 emit_insn (gen_rtx_SET (tmp
, addr
));
5100 /* Load the offset into %d0 and add it to THIS. */
5101 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5102 gen_rtx_MEM (Pmode
, addr
));
5103 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5104 copy_rtx (this_slot
),
5105 gen_rtx_REG (Pmode
, D0_REG
)));
5108 /* Jump to the target function. Use a sibcall if direct jumps are
5109 allowed, otherwise load the address into a register first. */
5110 mem
= DECL_RTL (function
);
5111 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5113 gcc_assert (flag_pic
);
5115 if (!TARGET_SEP_DATA
)
5117 /* Use the static chain register as a temporary (call-clobbered)
5118 GOT pointer for this function. We can use the static chain
5119 register because it isn't live on entry to the thunk. */
5120 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5121 emit_insn (gen_load_got (pic_offset_table_rtx
));
5123 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5124 mem
= replace_equiv_address (mem
, tmp
);
5126 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5127 SIBLING_CALL_P (insn
) = 1;
5129 /* Run just enough of rest_of_compilation. */
5130 insn
= get_insns ();
5131 split_all_insns_noflow ();
5132 final_start_function (insn
, file
, 1);
5133 final (insn
, file
, 1);
5134 final_end_function ();
5136 /* Clean up the vars set above. */
5137 reload_completed
= 0;
5139 /* Restore the original PIC register. */
5141 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5144 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5147 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5148 int incoming ATTRIBUTE_UNUSED
)
5150 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5153 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5155 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5156 unsigned int new_reg
)
5159 /* Interrupt functions can only use registers that have already been
5160 saved by the prologue, even if they would normally be
5163 if ((m68k_get_function_kind (current_function_decl
)
5164 == m68k_fk_interrupt_handler
)
5165 && !df_regs_ever_live_p (new_reg
))
5171 /* Value is true if hard register REGNO can hold a value of machine-mode
5172 MODE. On the 68000, we let the cpu registers can hold any mode, but
5173 restrict the 68881 registers to floating-point modes. */
5176 m68k_regno_mode_ok (int regno
, machine_mode mode
)
5178 if (DATA_REGNO_P (regno
))
5180 /* Data Registers, can hold aggregate if fits in. */
5181 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5184 else if (ADDRESS_REGNO_P (regno
))
5186 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5189 else if (FP_REGNO_P (regno
))
5191 /* FPU registers, hold float or complex float of long double or
5193 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5194 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5195 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5201 /* Implement SECONDARY_RELOAD_CLASS. */
5204 m68k_secondary_reload_class (enum reg_class rclass
,
5205 machine_mode mode
, rtx x
)
5209 regno
= true_regnum (x
);
5211 /* If one operand of a movqi is an address register, the other
5212 operand must be a general register or constant. Other types
5213 of operand must be reloaded through a data register. */
5214 if (GET_MODE_SIZE (mode
) == 1
5215 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5216 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5219 /* PC-relative addresses must be loaded into an address register first. */
5221 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5222 && symbolic_operand (x
, VOIDmode
))
5228 /* Implement PREFERRED_RELOAD_CLASS. */
5231 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5233 enum reg_class secondary_class
;
5235 /* If RCLASS might need a secondary reload, try restricting it to
5236 a class that doesn't. */
5237 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5238 if (secondary_class
!= NO_REGS
5239 && reg_class_subset_p (secondary_class
, rclass
))
5240 return secondary_class
;
5242 /* Prefer to use moveq for in-range constants. */
5243 if (GET_CODE (x
) == CONST_INT
5244 && reg_class_subset_p (DATA_REGS
, rclass
)
5245 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5248 /* ??? Do we really need this now? */
5249 if (GET_CODE (x
) == CONST_DOUBLE
5250 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5252 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5261 /* Return floating point values in a 68881 register. This makes 68881 code
5262 a little bit faster. It also makes -msoft-float code incompatible with
5263 hard-float code, so people have to be careful not to mix the two.
5264 For ColdFire it was decided the ABI incompatibility is undesirable.
5265 If there is need for a hard-float ABI it is probably worth doing it
5266 properly and also passing function arguments in FP registers. */
5268 m68k_libcall_value (machine_mode mode
)
5275 return gen_rtx_REG (mode
, FP0_REG
);
5281 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5284 /* Location in which function value is returned.
5285 NOTE: Due to differences in ABIs, don't call this function directly,
5286 use FUNCTION_VALUE instead. */
5288 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5292 mode
= TYPE_MODE (valtype
);
5298 return gen_rtx_REG (mode
, FP0_REG
);
5304 /* If the function returns a pointer, push that into %a0. */
5305 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5306 /* For compatibility with the large body of existing code which
5307 does not always properly declare external functions returning
5308 pointer types, the m68k/SVR4 convention is to copy the value
5309 returned for pointer functions from a0 to d0 in the function
5310 epilogue, so that callers that have neglected to properly
5311 declare the callee can still find the correct return value in
5313 return gen_rtx_PARALLEL
5316 gen_rtx_EXPR_LIST (VOIDmode
,
5317 gen_rtx_REG (mode
, A0_REG
),
5319 gen_rtx_EXPR_LIST (VOIDmode
,
5320 gen_rtx_REG (mode
, D0_REG
),
5322 else if (POINTER_TYPE_P (valtype
))
5323 return gen_rtx_REG (mode
, A0_REG
);
5325 return gen_rtx_REG (mode
, D0_REG
);
5328 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5329 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5331 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5333 machine_mode mode
= TYPE_MODE (type
);
5335 if (mode
== BLKmode
)
5338 /* If TYPE's known alignment is less than the alignment of MODE that
5339 would contain the structure, then return in memory. We need to
5340 do so to maintain the compatibility between code compiled with
5341 -mstrict-align and that compiled with -mno-strict-align. */
5342 if (AGGREGATE_TYPE_P (type
)
5343 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5350 /* CPU to schedule the program for. */
5351 enum attr_cpu m68k_sched_cpu
;
5353 /* MAC to schedule the program for. */
5354 enum attr_mac m68k_sched_mac
;
5362 /* Integer register. */
5368 /* Implicit mem reference (e.g. stack). */
5371 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5374 /* Memory with offset but without indexing. EA mode 5. */
5377 /* Memory with indexing. EA mode 6. */
5380 /* Memory referenced by absolute address. EA mode 7. */
5383 /* Immediate operand that doesn't require extension word. */
5386 /* Immediate 16 bit operand. */
5389 /* Immediate 32 bit operand. */
5393 /* Return type of memory ADDR_RTX refers to. */
5394 static enum attr_op_type
5395 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5397 struct m68k_address address
;
5399 if (symbolic_operand (addr_rtx
, VOIDmode
))
5400 return OP_TYPE_MEM7
;
5402 if (!m68k_decompose_address (mode
, addr_rtx
,
5403 reload_completed
, &address
))
5405 gcc_assert (!reload_completed
);
5406 /* Reload will likely fix the address to be in the register. */
5407 return OP_TYPE_MEM234
;
5410 if (address
.scale
!= 0)
5411 return OP_TYPE_MEM6
;
5413 if (address
.base
!= NULL_RTX
)
5415 if (address
.offset
== NULL_RTX
)
5416 return OP_TYPE_MEM234
;
5418 return OP_TYPE_MEM5
;
5421 gcc_assert (address
.offset
!= NULL_RTX
);
5423 return OP_TYPE_MEM7
;
5426 /* Return X or Y (depending on OPX_P) operand of INSN. */
5428 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5432 if (recog_memoized (insn
) < 0)
5435 extract_constrain_insn_cached (insn
);
5438 i
= get_attr_opx (insn
);
5440 i
= get_attr_opy (insn
);
5442 if (i
>= recog_data
.n_operands
)
5445 return recog_data
.operand
[i
];
5448 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5449 If ADDRESS_P is true, return type of memory location operand refers to. */
5450 static enum attr_op_type
5451 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5455 op
= sched_get_operand (insn
, opx_p
);
5459 gcc_assert (!reload_completed
);
5464 return sched_address_type (QImode
, op
);
5466 if (memory_operand (op
, VOIDmode
))
5467 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5469 if (register_operand (op
, VOIDmode
))
5471 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5472 || (reload_completed
&& FP_REG_P (op
)))
5478 if (GET_CODE (op
) == CONST_INT
)
5484 /* Check for quick constants. */
5485 switch (get_attr_type (insn
))
5488 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5489 return OP_TYPE_IMM_Q
;
5491 gcc_assert (!reload_completed
);
5495 if (USE_MOVQ (ival
))
5496 return OP_TYPE_IMM_Q
;
5498 gcc_assert (!reload_completed
);
5502 if (valid_mov3q_const (ival
))
5503 return OP_TYPE_IMM_Q
;
5505 gcc_assert (!reload_completed
);
5512 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5513 return OP_TYPE_IMM_W
;
5515 return OP_TYPE_IMM_L
;
5518 if (GET_CODE (op
) == CONST_DOUBLE
)
5520 switch (GET_MODE (op
))
5523 return OP_TYPE_IMM_W
;
5527 return OP_TYPE_IMM_L
;
5534 if (GET_CODE (op
) == CONST
5535 || symbolic_operand (op
, VOIDmode
)
5538 switch (GET_MODE (op
))
5541 return OP_TYPE_IMM_Q
;
5544 return OP_TYPE_IMM_W
;
5547 return OP_TYPE_IMM_L
;
5550 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5552 return OP_TYPE_IMM_W
;
5554 return OP_TYPE_IMM_L
;
5558 gcc_assert (!reload_completed
);
5560 if (FLOAT_MODE_P (GET_MODE (op
)))
5566 /* Implement opx_type attribute.
5567 Return type of INSN's operand X.
5568 If ADDRESS_P is true, return type of memory location operand refers to. */
5570 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5572 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5578 return OPX_TYPE_FPN
;
5581 return OPX_TYPE_MEM1
;
5583 case OP_TYPE_MEM234
:
5584 return OPX_TYPE_MEM234
;
5587 return OPX_TYPE_MEM5
;
5590 return OPX_TYPE_MEM6
;
5593 return OPX_TYPE_MEM7
;
5596 return OPX_TYPE_IMM_Q
;
5599 return OPX_TYPE_IMM_W
;
5602 return OPX_TYPE_IMM_L
;
5609 /* Implement opy_type attribute.
5610 Return type of INSN's operand Y.
5611 If ADDRESS_P is true, return type of memory location operand refers to. */
5613 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5615 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5621 return OPY_TYPE_FPN
;
5624 return OPY_TYPE_MEM1
;
5626 case OP_TYPE_MEM234
:
5627 return OPY_TYPE_MEM234
;
5630 return OPY_TYPE_MEM5
;
5633 return OPY_TYPE_MEM6
;
5636 return OPY_TYPE_MEM7
;
5639 return OPY_TYPE_IMM_Q
;
5642 return OPY_TYPE_IMM_W
;
5645 return OPY_TYPE_IMM_L
;
5652 /* Return size of INSN as int. */
5654 sched_get_attr_size_int (rtx_insn
*insn
)
5658 switch (get_attr_type (insn
))
5661 /* There should be no references to m68k_sched_attr_size for 'ignore'
5675 switch (get_attr_opx_type (insn
))
5681 case OPX_TYPE_MEM234
:
5682 case OPY_TYPE_IMM_Q
:
5687 /* Here we assume that most absolute references are short. */
5689 case OPY_TYPE_IMM_W
:
5693 case OPY_TYPE_IMM_L
:
5701 switch (get_attr_opy_type (insn
))
5707 case OPY_TYPE_MEM234
:
5708 case OPY_TYPE_IMM_Q
:
5713 /* Here we assume that most absolute references are short. */
5715 case OPY_TYPE_IMM_W
:
5719 case OPY_TYPE_IMM_L
:
5729 gcc_assert (!reload_completed
);
5737 /* Return size of INSN as attribute enum value. */
5739 m68k_sched_attr_size (rtx_insn
*insn
)
5741 switch (sched_get_attr_size_int (insn
))
5757 /* Return operand X or Y (depending on OPX_P) of INSN,
5758 if it is a MEM, or NULL overwise. */
5759 static enum attr_op_type
5760 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5764 switch (get_attr_opx_type (insn
))
5769 case OPX_TYPE_IMM_Q
:
5770 case OPX_TYPE_IMM_W
:
5771 case OPX_TYPE_IMM_L
:
5775 case OPX_TYPE_MEM234
:
5778 return OP_TYPE_MEM1
;
5781 return OP_TYPE_MEM6
;
5789 switch (get_attr_opy_type (insn
))
5794 case OPY_TYPE_IMM_Q
:
5795 case OPY_TYPE_IMM_W
:
5796 case OPY_TYPE_IMM_L
:
5800 case OPY_TYPE_MEM234
:
5803 return OP_TYPE_MEM1
;
5806 return OP_TYPE_MEM6
;
5814 /* Implement op_mem attribute. */
5816 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5818 enum attr_op_type opx
;
5819 enum attr_op_type opy
;
5821 opx
= sched_get_opxy_mem_type (insn
, true);
5822 opy
= sched_get_opxy_mem_type (insn
, false);
5824 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5827 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5829 switch (get_attr_opx_access (insn
))
5845 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5847 switch (get_attr_opx_access (insn
))
5863 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5866 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5868 switch (get_attr_opx_access (insn
))
5874 gcc_assert (!reload_completed
);
5879 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5881 switch (get_attr_opx_access (insn
))
5887 gcc_assert (!reload_completed
);
5892 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5895 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5897 switch (get_attr_opx_access (insn
))
5903 gcc_assert (!reload_completed
);
5908 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5909 gcc_assert (!reload_completed
);
5913 /* Data for ColdFire V4 index bypass.
5914 Producer modifies register that is used as index in consumer with
5918 /* Producer instruction. */
5921 /* Consumer instruction. */
5924 /* Scale of indexed memory access within consumer.
5925 Or zero if bypass should not be effective at the moment. */
5927 } sched_cfv4_bypass_data
;
5929 /* An empty state that is used in m68k_sched_adjust_cost. */
5930 static state_t sched_adjust_cost_state
;
5932 /* Implement adjust_cost scheduler hook.
5933 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5935 m68k_sched_adjust_cost (rtx_insn
*insn
, int, rtx_insn
*def_insn
, int cost
,
5940 if (recog_memoized (def_insn
) < 0
5941 || recog_memoized (insn
) < 0)
5944 if (sched_cfv4_bypass_data
.scale
== 1)
5945 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5947 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5948 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5949 that the data in sched_cfv4_bypass_data is up to date. */
5950 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5951 && sched_cfv4_bypass_data
.con
== insn
);
5956 sched_cfv4_bypass_data
.pro
= NULL
;
5957 sched_cfv4_bypass_data
.con
= NULL
;
5958 sched_cfv4_bypass_data
.scale
= 0;
5961 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
5962 && sched_cfv4_bypass_data
.con
== NULL
5963 && sched_cfv4_bypass_data
.scale
== 0);
5965 /* Don't try to issue INSN earlier than DFA permits.
5966 This is especially useful for instructions that write to memory,
5967 as their true dependence (default) latency is better to be set to 0
5968 to workaround alias analysis limitations.
5969 This is, in fact, a machine independent tweak, so, probably,
5970 it should be moved to haifa-sched.c: insn_cost (). */
5971 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
5978 /* Return maximal number of insns that can be scheduled on a single cycle. */
5980 m68k_sched_issue_rate (void)
5982 switch (m68k_sched_cpu
)
5998 /* Maximal length of instruction for current CPU.
5999 E.g. it is 3 for any ColdFire core. */
6000 static int max_insn_size
;
6002 /* Data to model instruction buffer of CPU. */
6005 /* True if instruction buffer model is modeled for current CPU. */
6008 /* Size of the instruction buffer in words. */
6011 /* Number of filled words in the instruction buffer. */
6014 /* Additional information about instruction buffer for CPUs that have
6015 a buffer of instruction records, rather then a plain buffer
6016 of instruction words. */
6017 struct _sched_ib_records
6019 /* Size of buffer in records. */
6022 /* Array to hold data on adjustements made to the size of the buffer. */
6025 /* Index of the above array. */
6029 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6033 static struct _sched_ib sched_ib
;
6035 /* ID of memory unit. */
6036 static int sched_mem_unit_code
;
6038 /* Implementation of the targetm.sched.variable_issue () hook.
6039 It is called after INSN was issued. It returns the number of insns
6040 that can possibly get scheduled on the current cycle.
6041 It is used here to determine the effect of INSN on the instruction
6044 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6045 int sched_verbose ATTRIBUTE_UNUSED
,
6046 rtx_insn
*insn
, int can_issue_more
)
6050 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6052 switch (m68k_sched_cpu
)
6056 insn_size
= sched_get_attr_size_int (insn
);
6060 insn_size
= sched_get_attr_size_int (insn
);
6062 /* ColdFire V3 and V4 cores have instruction buffers that can
6063 accumulate up to 8 instructions regardless of instructions'
6064 sizes. So we should take care not to "prefetch" 24 one-word
6065 or 12 two-words instructions.
6066 To model this behavior we temporarily decrease size of the
6067 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6071 adjust
= max_insn_size
- insn_size
;
6072 sched_ib
.size
-= adjust
;
6074 if (sched_ib
.filled
> sched_ib
.size
)
6075 sched_ib
.filled
= sched_ib
.size
;
6077 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6080 ++sched_ib
.records
.adjust_index
;
6081 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6082 sched_ib
.records
.adjust_index
= 0;
6084 /* Undo adjustement we did 7 instructions ago. */
6086 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6091 gcc_assert (!sched_ib
.enabled_p
);
6099 if (insn_size
> sched_ib
.filled
)
6100 /* Scheduling for register pressure does not always take DFA into
6101 account. Workaround instruction buffer not being filled enough. */
6103 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6104 insn_size
= sched_ib
.filled
;
6109 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6110 || asm_noperands (PATTERN (insn
)) >= 0)
6111 insn_size
= sched_ib
.filled
;
6115 sched_ib
.filled
-= insn_size
;
6117 return can_issue_more
;
6120 /* Return how many instructions should scheduler lookahead to choose the
6123 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6125 return m68k_sched_issue_rate () - 1;
6128 /* Implementation of targetm.sched.init_global () hook.
6129 It is invoked once per scheduling pass and is used here
6130 to initialize scheduler constants. */
6132 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6133 int sched_verbose ATTRIBUTE_UNUSED
,
6134 int n_insns ATTRIBUTE_UNUSED
)
6136 /* Check that all instructions have DFA reservations and
6137 that all instructions can be issued from a clean state. */
6143 state
= alloca (state_size ());
6145 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6147 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6149 gcc_assert (insn_has_dfa_reservation_p (insn
));
6151 state_reset (state
);
6152 if (state_transition (state
, insn
) >= 0)
6158 /* Setup target cpu. */
6160 /* ColdFire V4 has a set of features to keep its instruction buffer full
6161 (e.g., a separate memory bus for instructions) and, hence, we do not model
6162 buffer for this CPU. */
6163 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6165 switch (m68k_sched_cpu
)
6168 sched_ib
.filled
= 0;
6175 sched_ib
.records
.n_insns
= 0;
6176 sched_ib
.records
.adjust
= NULL
;
6181 sched_ib
.records
.n_insns
= 8;
6182 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6189 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6191 sched_adjust_cost_state
= xmalloc (state_size ());
6192 state_reset (sched_adjust_cost_state
);
6195 emit_insn (gen_ib ());
6196 sched_ib
.insn
= get_insns ();
6200 /* Scheduling pass is now finished. Free/reset static variables. */
6202 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6203 int verbose ATTRIBUTE_UNUSED
)
6205 sched_ib
.insn
= NULL
;
6207 free (sched_adjust_cost_state
);
6208 sched_adjust_cost_state
= NULL
;
6210 sched_mem_unit_code
= 0;
6212 free (sched_ib
.records
.adjust
);
6213 sched_ib
.records
.adjust
= NULL
;
6214 sched_ib
.records
.n_insns
= 0;
6218 /* Implementation of targetm.sched.init () hook.
6219 It is invoked each time scheduler starts on the new block (basic block or
6220 extended basic block). */
6222 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6223 int sched_verbose ATTRIBUTE_UNUSED
,
6224 int n_insns ATTRIBUTE_UNUSED
)
6226 switch (m68k_sched_cpu
)
6234 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6236 memset (sched_ib
.records
.adjust
, 0,
6237 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6238 sched_ib
.records
.adjust_index
= 0;
6242 gcc_assert (!sched_ib
.enabled_p
);
6250 if (sched_ib
.enabled_p
)
6251 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6252 the first cycle. Workaround that. */
6253 sched_ib
.filled
= -2;
6256 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6257 It is invoked just before current cycle finishes and is used here
6258 to track if instruction buffer got its two words this cycle. */
6260 m68k_sched_dfa_pre_advance_cycle (void)
6262 if (!sched_ib
.enabled_p
)
6265 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6267 sched_ib
.filled
+= 2;
6269 if (sched_ib
.filled
> sched_ib
.size
)
6270 sched_ib
.filled
= sched_ib
.size
;
6274 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6275 It is invoked just after new cycle begins and is used here
6276 to setup number of filled words in the instruction buffer so that
6277 instructions which won't have all their words prefetched would be
6278 stalled for a cycle. */
6280 m68k_sched_dfa_post_advance_cycle (void)
6284 if (!sched_ib
.enabled_p
)
6287 /* Setup number of prefetched instruction words in the instruction
6289 i
= max_insn_size
- sched_ib
.filled
;
6293 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6294 /* Pick up scheduler state. */
6299 /* Return X or Y (depending on OPX_P) operand of INSN,
6300 if it is an integer register, or NULL overwise. */
6302 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6308 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6310 op
= sched_get_operand (insn
, true);
6311 gcc_assert (op
!= NULL
);
6313 if (!reload_completed
&& !REG_P (op
))
6319 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6321 op
= sched_get_operand (insn
, false);
6322 gcc_assert (op
!= NULL
);
6324 if (!reload_completed
&& !REG_P (op
))
6332 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6335 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6337 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6348 /* Return X or Y (depending on OPX_P) operand of INSN,
6349 if it is a MEM, or NULL overwise. */
6351 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6371 if (opy_p
&& sched_mem_operand_p (insn
, false))
6372 return sched_get_operand (insn
, false);
6374 if (opx_p
&& sched_mem_operand_p (insn
, true))
6375 return sched_get_operand (insn
, true);
6381 /* Return non-zero if PRO modifies register used as part of
6384 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6389 pro_x
= sched_get_reg_operand (pro
, true);
6393 con_mem_read
= sched_get_mem_operand (con
, true, false);
6394 gcc_assert (con_mem_read
!= NULL
);
6396 if (reg_mentioned_p (pro_x
, con_mem_read
))
6402 /* Helper function for m68k_sched_indexed_address_bypass_p.
6403 if PRO modifies register used as index in CON,
6404 return scale of indexed memory access in CON. Return zero overwise. */
6406 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6410 struct m68k_address address
;
6412 reg
= sched_get_reg_operand (pro
, true);
6416 mem
= sched_get_mem_operand (con
, true, false);
6417 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6419 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6423 if (REGNO (reg
) == REGNO (address
.index
))
6425 gcc_assert (address
.scale
!= 0);
6426 return address
.scale
;
6432 /* Return non-zero if PRO modifies register used
6433 as index with scale 2 or 4 in CON. */
6435 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6437 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6438 && sched_cfv4_bypass_data
.con
== NULL
6439 && sched_cfv4_bypass_data
.scale
== 0);
6441 switch (sched_get_indexed_address_scale (pro
, con
))
6444 /* We can't have a variable latency bypass, so
6445 remember to adjust the insn cost in adjust_cost hook. */
6446 sched_cfv4_bypass_data
.pro
= pro
;
6447 sched_cfv4_bypass_data
.con
= con
;
6448 sched_cfv4_bypass_data
.scale
= 1;
6460 /* We generate a two-instructions program at M_TRAMP :
6461 movea.l &CHAIN_VALUE,%a0
6463 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6466 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6468 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6471 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6473 mem
= adjust_address (m_tramp
, HImode
, 0);
6474 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6475 mem
= adjust_address (m_tramp
, SImode
, 2);
6476 emit_move_insn (mem
, chain_value
);
6478 mem
= adjust_address (m_tramp
, HImode
, 6);
6479 emit_move_insn (mem
, GEN_INT(0x4EF9));
6480 mem
= adjust_address (m_tramp
, SImode
, 8);
6481 emit_move_insn (mem
, fnaddr
);
6483 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6486 /* On the 68000, the RTS insn cannot pop anything.
6487 On the 68010, the RTD insn may be used to pop them if the number
6488 of args is fixed, but if the number is variable then the caller
6489 must pop them all. RTD can't be used for library calls now
6490 because the library is compiled with the Unix compiler.
6491 Use of RTD is a selectable option, since it is incompatible with
6492 standard Unix calling sequences. If the option is not selected,
6493 the caller must always pop the args. */
6496 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6500 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6501 && (!stdarg_p (funtype
)))
6505 /* Make sure everything's fine if we *don't* have a given processor.
6506 This assumes that putting a register in fixed_regs will keep the
6507 compiler's mitts completely off it. We don't bother to zero it out
6508 of register classes. */
6511 m68k_conditional_register_usage (void)
6515 if (!TARGET_HARD_FLOAT
)
6517 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6518 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6519 if (TEST_HARD_REG_BIT (x
, i
))
6520 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6523 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6527 m68k_init_sync_libfuncs (void)
6529 init_sync_libfuncs (UNITS_PER_WORD
);
6532 /* Implements EPILOGUE_USES. All registers are live on exit from an
6533 interrupt routine. */
6535 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6537 return (reload_completed
6538 && (m68k_get_function_kind (current_function_decl
)
6539 == m68k_fk_interrupt_handler
));
6543 /* Implement TARGET_C_EXCESS_PRECISION.
6545 Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
6546 instructions, we get proper intermediate rounding, otherwise we
6547 get extended precision results. */
6549 static enum flt_eval_method
6550 m68k_excess_precision (enum excess_precision_type type
)
6554 case EXCESS_PRECISION_TYPE_FAST
:
6555 /* The fastest type to promote to will always be the native type,
6556 whether that occurs with implicit excess precision or
6558 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6559 case EXCESS_PRECISION_TYPE_STANDARD
:
6560 case EXCESS_PRECISION_TYPE_IMPLICIT
:
6561 /* Otherwise, the excess precision we want when we are
6562 in a standards compliant mode, and the implicit precision we
6563 provide can be identical. */
6564 if (TARGET_68040
|| ! TARGET_68881
)
6565 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6567 return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE
;
6571 return FLT_EVAL_METHOD_UNPREDICTABLE
;
6574 #include "gt-m68k.h"