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[thirdparty/gcc.git] / gcc / config / m68k / m68k.h
1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
20 Boston, MA 02110-1301, USA. */
21
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
26 #if MOTOROLA /* Use the Motorola assembly syntax. */
27 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
28 #else
29 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
30 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
31 #endif
32
33 /* Handle --with-cpu default option from configure script. */
34 #define OPTION_DEFAULT_SPECS \
35 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
36 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
37 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
38 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" },
39
40 /* Pass flags to gas indicating which type of processor we have. This
41 can be simplified when we can rely on the assembler supporting .cpu
42 and .arch directives. */
43
44 #define ASM_CPU_SPEC "\
45 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
46 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\
47 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\
48 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
49 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
50 "
51
52 #define ASM_SPEC "%(asm_cpu_spec)"
53
54 #define EXTRA_SPECS \
55 { "asm_cpu_spec", ASM_CPU_SPEC }, \
56 SUBTARGET_EXTRA_SPECS
57
58 #define SUBTARGET_EXTRA_SPECS
59
60 /* Note that some other tm.h files include this one and then override
61 many of the definitions that relate to assembler syntax. */
62
63 #define TARGET_CPU_CPP_BUILTINS() \
64 do \
65 { \
66 builtin_define ("__m68k__"); \
67 builtin_define_std ("mc68000"); \
68 /* The other mc680x0 macros have traditionally been derived \
69 from the tuning setting. For example, -m68020-60 defines \
70 m68060, even though it generates pure 68020 code. */ \
71 switch (m68k_tune) \
72 { \
73 case u68010: \
74 builtin_define_std ("mc68010"); \
75 break; \
76 \
77 case u68020: \
78 builtin_define_std ("mc68020"); \
79 break; \
80 \
81 case u68030: \
82 builtin_define_std ("mc68030"); \
83 break; \
84 \
85 case u68040: \
86 builtin_define_std ("mc68040"); \
87 break; \
88 \
89 case u68060: \
90 builtin_define_std ("mc68060"); \
91 break; \
92 \
93 case u68020_60: \
94 builtin_define_std ("mc68060"); \
95 /* Fall through. */ \
96 case u68020_40: \
97 builtin_define_std ("mc68040"); \
98 builtin_define_std ("mc68030"); \
99 builtin_define_std ("mc68020"); \
100 break; \
101 \
102 case ucpu32: \
103 builtin_define_std ("mc68332"); \
104 builtin_define_std ("mcpu32"); \
105 builtin_define_std ("mc68020"); \
106 break; \
107 \
108 case ucfv2: \
109 builtin_define ("__mcfv2__"); \
110 break; \
111 \
112 case ucfv3: \
113 builtin_define ("__mcfv3__"); \
114 break; \
115 \
116 case ucfv4: \
117 builtin_define ("__mcfv4__"); \
118 break; \
119 \
120 case ucfv4e: \
121 builtin_define ("__mcfv4e__"); \
122 break; \
123 \
124 case ucfv5: \
125 builtin_define ("__mcfv5__"); \
126 break; \
127 \
128 default: \
129 break; \
130 } \
131 \
132 if (TARGET_68881) \
133 builtin_define ("__HAVE_68881__"); \
134 \
135 if (TARGET_COLDFIRE) \
136 { \
137 const char *tmp; \
138 \
139 tmp = m68k_cpp_cpu_ident ("cf"); \
140 if (tmp) \
141 builtin_define (tmp); \
142 tmp = m68k_cpp_cpu_family ("cf"); \
143 if (tmp) \
144 builtin_define (tmp); \
145 builtin_define ("__mcoldfire__"); \
146 \
147 if (TARGET_ISAC) \
148 builtin_define ("__mcfisac__"); \
149 else if (TARGET_ISAB) \
150 { \
151 builtin_define ("__mcfisab__"); \
152 /* ISA_B: Legacy 5407 defines. */ \
153 builtin_define ("__mcf5400__"); \
154 builtin_define ("__mcf5407__"); \
155 } \
156 else if (TARGET_ISAAPLUS) \
157 { \
158 builtin_define ("__mcfisaaplus__"); \
159 /* ISA_A+: legacy defines. */ \
160 builtin_define ("__mcf528x__"); \
161 builtin_define ("__mcf5200__"); \
162 } \
163 else \
164 { \
165 builtin_define ("__mcfisaa__"); \
166 /* ISA_A: legacy defines. */ \
167 switch (m68k_tune) \
168 { \
169 case ucfv2: \
170 builtin_define ("__mcf5200__"); \
171 break; \
172 \
173 case ucfv3: \
174 builtin_define ("__mcf5307__"); \
175 builtin_define ("__mcf5300__"); \
176 break; \
177 \
178 default: \
179 break; \
180 } \
181 } \
182 } \
183 \
184 if (TARGET_COLDFIRE_FPU) \
185 builtin_define ("__mcffpu__"); \
186 \
187 if (TARGET_CF_HWDIV) \
188 builtin_define ("__mcfhwdiv__"); \
189 \
190 builtin_assert ("cpu=m68k"); \
191 builtin_assert ("machine=m68k"); \
192 } \
193 while (0)
194
195 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
196 quantities. */
197 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
198 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
199 #define INT_OP_NO_DOT 2 /* byte, short, long */
200 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
201
202 /* Set the default. */
203 #define INT_OP_GROUP INT_OP_DOT_WORD
204
205 /* Bit values used by m68k-devices.def to identify processor capabilities. */
206 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
207 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
208 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
209 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
210 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
211 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
212 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
213 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
214 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
215 #define FL_ISA_68000 (1 << 9)
216 #define FL_ISA_68010 (1 << 10)
217 #define FL_ISA_68020 (1 << 11)
218 #define FL_ISA_68040 (1 << 12)
219 #define FL_ISA_A (1 << 13)
220 #define FL_ISA_APLUS (1 << 14)
221 #define FL_ISA_B (1 << 15)
222 #define FL_ISA_C (1 << 16)
223 #define FL_MMU 0 /* Used by multilib machinery. */
224
225 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
226 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
227 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
228 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
229 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
230 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
231
232 /* Size (in bytes) of FPU registers. */
233 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
234
235 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
236 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
237 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
238
239 #define TUNE_68000 (m68k_tune == u68000)
240 #define TUNE_68010 (m68k_tune == u68010)
241 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
242 #define TUNE_68030 (m68k_tune == u68030 \
243 || m68k_tune == u68020_40 \
244 || m68k_tune == u68020_60)
245 #define TUNE_68040 (m68k_tune == u68040 \
246 || m68k_tune == u68020_40 \
247 || m68k_tune == u68020_60)
248 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
249 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
250 #define TUNE_CPU32 (m68k_tune == ucpu32)
251 #define TUNE_CFV2 (m68k_tune == ucfv2)
252
253 #define OVERRIDE_OPTIONS override_options()
254
255 /* These are meant to be redefined in the host dependent files */
256 #define SUBTARGET_OVERRIDE_OPTIONS
257 \f
258 /* target machine storage layout */
259
260 /* "long double" is the same as "double" on ColdFire targets. */
261
262 #define LONG_DOUBLE_TYPE_SIZE (TARGET_COLDFIRE ? 64 : 80)
263
264 /* We need to know the size of long double at compile-time in libgcc2. */
265
266 #ifdef __mcoldfire__
267 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
268 #else
269 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
270 #endif
271
272 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
273 instructions, we get proper intermediate rounding, otherwise we
274 get extended precision results. */
275 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
276
277 #define BITS_BIG_ENDIAN 1
278 #define BYTES_BIG_ENDIAN 1
279 #define WORDS_BIG_ENDIAN 1
280
281 #define UNITS_PER_WORD 4
282
283 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
284 #define STACK_BOUNDARY 16
285 #define FUNCTION_BOUNDARY 16
286 #define EMPTY_FIELD_BOUNDARY 16
287 /* ColdFire strongly prefers a 32-bit aligned stack. */
288 #define PREFERRED_STACK_BOUNDARY (TARGET_COLDFIRE ? 32 : 16)
289
290 /* No data type wants to be aligned rounder than this.
291 Most published ABIs say that ints should be aligned on 16-bit
292 boundaries, but CPUs with 32-bit busses get better performance
293 aligned on 32-bit boundaries. ColdFires without a misalignment
294 module require 32-bit alignment. */
295 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
296
297 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
298
299 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
300
301 /* Define these to avoid dependence on meaning of `int'. */
302 #define WCHAR_TYPE "long int"
303 #define WCHAR_TYPE_SIZE 32
304
305 /* Maximum number of library IDs we permit with -mid-shared-library. */
306 #define MAX_LIBRARY_ID 255
307
308 \f
309 /* Standard register usage. */
310
311 /* For the m68k, we give the data registers numbers 0-7,
312 the address registers numbers 010-017 (8-15),
313 and the 68881 floating point registers numbers 020-027 (16-23).
314 We also have a fake `arg-pointer' register 030 (24) used for
315 register elimination. */
316 #define FIRST_PSEUDO_REGISTER 25
317
318 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
319 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
320
321 /* 1 for registers that have pervasive standard uses
322 and are not available for the register allocator.
323 On the m68k, only the stack pointer is such.
324 Our fake arg-pointer is obviously fixed as well. */
325 #define FIXED_REGISTERS \
326 {/* Data registers. */ \
327 0, 0, 0, 0, 0, 0, 0, 0, \
328 \
329 /* Address registers. */ \
330 0, 0, 0, 0, 0, 0, 0, 1, \
331 \
332 /* Floating point registers \
333 (if available). */ \
334 0, 0, 0, 0, 0, 0, 0, 0, \
335 \
336 /* Arg pointer. */ \
337 1 }
338
339 /* 1 for registers not available across function calls.
340 These must include the FIXED_REGISTERS and also any
341 registers that can be used without being saved.
342 The latter must include the registers where values are returned
343 and the register where structure-value addresses are passed.
344 Aside from that, you can include as many other registers as you like. */
345 #define CALL_USED_REGISTERS \
346 {/* Data registers. */ \
347 1, 1, 0, 0, 0, 0, 0, 0, \
348 \
349 /* Address registers. */ \
350 1, 1, 0, 0, 0, 0, 0, 1, \
351 \
352 /* Floating point registers \
353 (if available). */ \
354 1, 1, 0, 0, 0, 0, 0, 0, \
355 \
356 /* Arg pointer. */ \
357 1 }
358
359 #define REG_ALLOC_ORDER \
360 { /* d0/d1/a0/a1 */ \
361 0, 1, 8, 9, \
362 /* d2-d7 */ \
363 2, 3, 4, 5, 6, 7, \
364 /* a2-a7/arg */ \
365 10, 11, 12, 13, 14, 15, 24, \
366 /* fp0-fp7 */ \
367 16, 17, 18, 19, 20, 21, 22, 23\
368 }
369
370
371 /* Make sure everything's fine if we *don't* have a given processor.
372 This assumes that putting a register in fixed_regs will keep the
373 compiler's mitts completely off it. We don't bother to zero it out
374 of register classes. */
375 #define CONDITIONAL_REGISTER_USAGE \
376 { \
377 int i; \
378 HARD_REG_SET x; \
379 if (!TARGET_HARD_FLOAT) \
380 { \
381 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
382 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
383 if (TEST_HARD_REG_BIT (x, i)) \
384 fixed_regs[i] = call_used_regs[i] = 1; \
385 } \
386 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
387 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
388 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
389 }
390
391 /* On the m68k, ordinary registers hold 32 bits worth;
392 for the 68881 registers, a single register is always enough for
393 anything that can be stored in them at all. */
394 #define HARD_REGNO_NREGS(REGNO, MODE) \
395 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
396 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
397
398 /* A C expression that is nonzero if hard register NEW_REG can be
399 considered for use as a rename register for OLD_REG register. */
400
401 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
402 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
403
404 /* Value is true if hard register REGNO can hold a value of machine-mode MODE.
405 On the 68000, the cpu registers can hold any mode except bytes in
406 address registers, the 68881 registers can hold only SFmode or DFmode. */
407
408 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
409 m68k_regno_mode_ok ((REGNO), (MODE))
410
411 #define MODES_TIEABLE_P(MODE1, MODE2) \
412 (! TARGET_HARD_FLOAT \
413 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
414 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
415 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
416 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
417
418 /* Specify the registers used for certain standard purposes.
419 The values of these macros are register numbers. */
420
421 #define STACK_POINTER_REGNUM 15
422
423 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
424 ABI uses %a6 for shared library calls, therefore the frame
425 pointer is shifted to %a5 on this target. */
426 #define FRAME_POINTER_REGNUM 14
427
428 #define FRAME_POINTER_REQUIRED 0
429
430 /* Base register for access to arguments of the function.
431 * This isn't a hardware register. It will be eliminated to the
432 * stack pointer or frame pointer.
433 */
434 #define ARG_POINTER_REGNUM 24
435
436 #define STATIC_CHAIN_REGNUM 8
437 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
438
439 /* Register in which address to store a structure value
440 is passed to a function. */
441 #define M68K_STRUCT_VALUE_REGNUM 9
442
443 \f
444
445 /* The m68k has three kinds of registers, so eight classes would be
446 a complete set. One of them is not needed. */
447 enum reg_class {
448 NO_REGS, DATA_REGS,
449 ADDR_REGS, FP_REGS,
450 GENERAL_REGS, DATA_OR_FP_REGS,
451 ADDR_OR_FP_REGS, ALL_REGS,
452 LIM_REG_CLASSES };
453
454 #define N_REG_CLASSES (int) LIM_REG_CLASSES
455
456 #define REG_CLASS_NAMES \
457 { "NO_REGS", "DATA_REGS", \
458 "ADDR_REGS", "FP_REGS", \
459 "GENERAL_REGS", "DATA_OR_FP_REGS", \
460 "ADDR_OR_FP_REGS", "ALL_REGS" }
461
462 #define REG_CLASS_CONTENTS \
463 { \
464 {0x00000000}, /* NO_REGS */ \
465 {0x000000ff}, /* DATA_REGS */ \
466 {0x0100ff00}, /* ADDR_REGS */ \
467 {0x00ff0000}, /* FP_REGS */ \
468 {0x0100ffff}, /* GENERAL_REGS */ \
469 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
470 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
471 {0x01ffffff}, /* ALL_REGS */ \
472 }
473
474 extern enum reg_class regno_reg_class[];
475 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
476 #define INDEX_REG_CLASS GENERAL_REGS
477 #define BASE_REG_CLASS ADDR_REGS
478
479 /* We do a trick here to modify the effective constraints on the
480 machine description; we zorch the constraint letters that aren't
481 appropriate for a specific target. This allows us to guarantee
482 that a specific kind of register will not be used for a given target
483 without fiddling with the register classes above. */
484 #define REG_CLASS_FROM_LETTER(C) \
485 ((C) == 'a' ? ADDR_REGS : \
486 ((C) == 'd' ? DATA_REGS : \
487 ((C) == 'f' ? (TARGET_HARD_FLOAT ? \
488 FP_REGS : NO_REGS) : \
489 NO_REGS)))
490
491 /* For the m68k, `I' is used for the range 1 to 8
492 allowed as immediate shift counts and in addq.
493 `J' is used for the range of signed numbers that fit in 16 bits.
494 `K' is for numbers that moveq can't handle.
495 `L' is for range -8 to -1, range of values that can be added with subq.
496 `M' is for numbers that moveq+notb can't handle.
497 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
498 'O' is for 16 (for rotate using swap).
499 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate.
500 'R' is for numbers that mov3q can handle. */
501 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
502 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
503 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
504 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
505 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
506 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
507 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
508 (C) == 'O' ? (VALUE) == 16 : \
509 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : \
510 (C) == 'R' ? valid_mov3q_const (VALUE) : 0)
511
512 /* "G" defines all of the floating constants that are *NOT* 68881
513 constants. This is so 68881 constants get reloaded and the
514 fpmovecr is used. */
515 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
516 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
517
518 /* `Q' means address register indirect addressing mode.
519 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
520 `T' is for operands that satisfy 's' when -mpcrel is not in effect.
521 `U' is for register offset addressing.
522 `W' is for const_call_operands. */
523 #define EXTRA_CONSTRAINT(OP,CODE) \
524 ((CODE) == 'S' \
525 ? (TARGET_PCREL \
526 && GET_CODE (OP) == MEM \
527 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
528 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
529 || GET_CODE (XEXP (OP, 0)) == CONST)) \
530 : \
531 (CODE) == 'T' \
532 ? (!flag_pic \
533 && (GET_CODE (OP) == SYMBOL_REF \
534 || GET_CODE (OP) == LABEL_REF \
535 || GET_CODE (OP) == CONST)) \
536 : \
537 (CODE) == 'Q' \
538 ? (GET_CODE (OP) == MEM \
539 && GET_CODE (XEXP (OP, 0)) == REG) \
540 : \
541 (CODE) == 'U' \
542 ? (GET_CODE (OP) == MEM \
543 && GET_CODE (XEXP (OP, 0)) == PLUS \
544 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
545 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
546 : \
547 (CODE) == 'W' \
548 ? const_call_operand (OP, VOIDmode) \
549 : 0)
550
551 /* On the m68k, use a data reg if possible when the
552 value is a constant in the range where moveq could be used
553 and we ensure that QImodes are reloaded into data regs. */
554 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
555 ((GET_CODE (X) == CONST_INT \
556 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
557 && (CLASS) != ADDR_REGS) \
558 ? DATA_REGS \
559 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
560 ? DATA_REGS \
561 : (GET_CODE (X) == CONST_DOUBLE \
562 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
563 ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
564 ? FP_REGS : NO_REGS) \
565 : (TARGET_PCREL \
566 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
567 || GET_CODE (X) == LABEL_REF)) \
568 ? ADDR_REGS \
569 : (CLASS))
570
571 /* Force QImode output reloads from subregs to be allocated to data regs,
572 since QImode stores from address regs are not supported. We make the
573 assumption that if the class is not ADDR_REGS, then it must be a superset
574 of DATA_REGS. */
575 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
576 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
577 ? DATA_REGS \
578 : (CLASS))
579
580 /* On the m68k, this is the size of MODE in words,
581 except in the FP regs, where a single reg is always enough. */
582 #define CLASS_MAX_NREGS(CLASS, MODE) \
583 ((CLASS) == FP_REGS ? 1 \
584 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
585
586 /* Moves between fp regs and other regs are two insns. */
587 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
588 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
589 \f
590 /* Stack layout; function entry, exit and calling. */
591
592 #define STACK_GROWS_DOWNWARD 1
593 #define FRAME_GROWS_DOWNWARD 1
594 #define STARTING_FRAME_OFFSET 0
595
596 /* On the 680x0, sp@- in a byte insn really pushes a word.
597 On the ColdFire, sp@- in a byte insn pushes just a byte. */
598 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
599
600 #define FIRST_PARM_OFFSET(FNDECL) 8
601
602 /* On the 68000, the RTS insn cannot pop anything.
603 On the 68010, the RTD insn may be used to pop them if the number
604 of args is fixed, but if the number is variable then the caller
605 must pop them all. RTD can't be used for library calls now
606 because the library is compiled with the Unix compiler.
607 Use of RTD is a selectable option, since it is incompatible with
608 standard Unix calling sequences. If the option is not selected,
609 the caller must always pop the args. */
610 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
611 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
612 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
613 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
614 == void_type_node))) \
615 ? (SIZE) : 0)
616
617 /* On the m68k the return value defaults to D0. */
618 #define FUNCTION_VALUE(VALTYPE, FUNC) \
619 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
620
621 /* On the m68k the return value defaults to D0. */
622 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
623
624 /* On the m68k, D0 is usually the only register used. */
625 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
626
627 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
628 more than one register.
629 XXX This macro is m68k specific and used only for m68kemb.h. */
630 #define NEEDS_UNTYPED_CALL 0
631
632 /* On the m68k, all arguments are usually pushed on the stack. */
633 #define FUNCTION_ARG_REGNO_P(N) 0
634 \f
635 /* On the m68k, this is a single integer, which is a number of bytes
636 of arguments scanned so far. */
637 #define CUMULATIVE_ARGS int
638
639 /* On the m68k, the offset starts at 0. */
640 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
641 ((CUM) = 0)
642
643 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
644 ((CUM) += ((MODE) != BLKmode \
645 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
646 : (int_size_in_bytes (TYPE) + 3) & ~3))
647
648 /* On the m68k all args are always pushed. */
649 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
650
651 #define FUNCTION_PROFILER(FILE, LABELNO) \
652 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
653
654 #define EXIT_IGNORE_STACK 1
655
656 /* Output assembler code for a block containing the constant parts
657 of a trampoline, leaving space for the variable parts.
658
659 On the m68k, the trampoline looks like this:
660 movl #STATIC,a0
661 jmp FUNCTION
662
663 WARNING: Targets that may run on 68040+ cpus must arrange for
664 the instruction cache to be flushed. Previous incarnations of
665 the m68k trampoline code attempted to get around this by either
666 using an out-of-line transfer function or pc-relative data, but
667 the fact remains that the code to jump to the transfer function
668 or the code to load the pc-relative data needs to be flushed
669 just as much as the "variable" portion of the trampoline.
670 Recognizing that a cache flush is going to be required anyway,
671 dispense with such notions and build a smaller trampoline.
672
673 Since more instructions are required to move a template into
674 place than to create it on the spot, don't use a template. */
675
676 #define TRAMPOLINE_SIZE 12
677 #define TRAMPOLINE_ALIGNMENT 16
678
679 /* Targets redefine this to invoke code to either flush the cache,
680 or enable stack execution (or both). */
681 #ifndef FINALIZE_TRAMPOLINE
682 #define FINALIZE_TRAMPOLINE(TRAMP)
683 #endif
684
685 /* We generate a two-instructions program at address TRAMP :
686 movea.l &CXT,%a0
687 jmp FNADDR */
688 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
689 { \
690 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \
691 GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \
692 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
693 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
694 GEN_INT(0x4EF9)); \
695 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
696 FINALIZE_TRAMPOLINE(TRAMP); \
697 }
698
699 /* This is the library routine that is used to transfer control from the
700 trampoline to the actual nested function. It is defined for backward
701 compatibility, for linking with object code that used the old trampoline
702 definition.
703
704 A colon is used with no explicit operands to cause the template string
705 to be scanned for %-constructs.
706
707 The function name __transfer_from_trampoline is not actually used.
708 The function definition just permits use of "asm with operands"
709 (though the operand list is empty). */
710 #define TRANSFER_FROM_TRAMPOLINE \
711 void \
712 __transfer_from_trampoline () \
713 { \
714 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
715 asm (GLOBAL_ASM_OP "___trampoline"); \
716 asm ("___trampoline:"); \
717 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
718 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
719 asm ("rts":); \
720 }
721 \f
722 /* There are two registers that can always be eliminated on the m68k.
723 The frame pointer and the arg pointer can be replaced by either the
724 hard frame pointer or to the stack pointer, depending upon the
725 circumstances. The hard frame pointer is not used before reload and
726 so it is not eligible for elimination. */
727 #define ELIMINABLE_REGS \
728 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
729 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
730 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
731
732 #define CAN_ELIMINATE(FROM, TO) \
733 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
734
735 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
736 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
737 \f
738 /* Addressing modes, and classification of registers for them. */
739
740 #define HAVE_POST_INCREMENT 1
741 #define HAVE_PRE_DECREMENT 1
742
743 /* Macros to check register numbers against specific register classes. */
744
745 /* True for data registers, D0 through D7. */
746 #define DATA_REGNO_P(REGNO) ((unsigned int) (REGNO) < 8)
747
748 /* True for address registers, A0 through A7. */
749 #define ADDRESS_REGNO_P(REGNO) (((unsigned int) (REGNO) - 8) < 8)
750
751 /* True for integer registers, D0 through D7 and A0 through A7. */
752 #define INT_REGNO_P(REGNO) ((unsigned int) (REGNO) < 16)
753
754 /* True for floating point registers, FP0 through FP7. */
755 #define FP_REGNO_P(REGNO) (((unsigned int) (REGNO) - 16) < 8)
756
757 #define REGNO_OK_FOR_INDEX_P(REGNO) \
758 (INT_REGNO_P (REGNO) \
759 || INT_REGNO_P (reg_renumber[REGNO]))
760
761 #define REGNO_OK_FOR_BASE_P(REGNO) \
762 (ADDRESS_REGNO_P (REGNO) \
763 || ADDRESS_REGNO_P (reg_renumber[REGNO]))
764
765 #define REGNO_OK_FOR_DATA_P(REGNO) \
766 (DATA_REGNO_P (REGNO) \
767 || DATA_REGNO_P (reg_renumber[REGNO]))
768
769 #define REGNO_OK_FOR_FP_P(REGNO) \
770 (FP_REGNO_P (REGNO) \
771 || FP_REGNO_P (reg_renumber[REGNO]))
772
773 /* Now macros that check whether X is a register and also,
774 strictly, whether it is in a specified class.
775
776 These macros are specific to the m68k, and may be used only
777 in code for printing assembler insns and in conditions for
778 define_optimization. */
779
780 /* 1 if X is a data register. */
781 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
782
783 /* 1 if X is an fp register. */
784 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
785
786 /* 1 if X is an address register */
787 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
788 \f
789
790 #define MAX_REGS_PER_ADDRESS 2
791
792 #define CONSTANT_ADDRESS_P(X) \
793 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
794 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
795 || GET_CODE (X) == HIGH)
796
797 /* Nonzero if the constant value X is a legitimate general operand.
798 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
799 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
800
801 #ifndef REG_OK_STRICT
802 #define PCREL_GENERAL_OPERAND_OK 0
803 #else
804 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
805 #endif
806
807 #define LEGITIMATE_PIC_OPERAND_P(X) \
808 (! symbolic_operand (X, VOIDmode) \
809 || PCREL_GENERAL_OPERAND_OK)
810
811 #ifndef REG_OK_STRICT
812
813 /* Nonzero if X is a hard reg that can be used as an index
814 or if it is a pseudo reg. */
815 #define REG_OK_FOR_INDEX_P(X) !FP_REGNO_P (REGNO (X))
816 /* Nonzero if X is a hard reg that can be used as a base reg
817 or if it is a pseudo reg. */
818 #define REG_OK_FOR_BASE_P(X) \
819 (!DATA_REGNO_P (REGNO (X)) && !FP_REGNO_P (REGNO (X)))
820
821 #else
822
823 /* Nonzero if X is a hard reg that can be used as an index. */
824 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
825 /* Nonzero if X is a hard reg that can be used as a base reg. */
826 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
827
828 #endif
829 \f
830 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
831 that is a valid memory address for an instruction.
832 The MODE argument is the machine mode for the MEM expression
833 that wants to use this address.
834
835 When generating PIC, an address involving a SYMBOL_REF is legitimate
836 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
837 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
838 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
839
840 Likewise for a LABEL_REF when generating PIC.
841
842 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
843
844 /* Allow SUBREG everywhere we allow REG. This results in better code. It
845 also makes function inlining work when inline functions are called with
846 arguments that are SUBREGs. */
847
848 #define LEGITIMATE_BASE_REG_P(X) \
849 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
850 || (GET_CODE (X) == SUBREG \
851 && GET_CODE (SUBREG_REG (X)) == REG \
852 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
853
854 #define INDIRECTABLE_1_ADDRESS_P(X) \
855 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
856 || LEGITIMATE_BASE_REG_P (X) \
857 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
858 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
859 || (GET_CODE (X) == PLUS \
860 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
861 && GET_CODE (XEXP (X, 1)) == CONST_INT \
862 && (TARGET_68020 \
863 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
864 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
865 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
866 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
867 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
868
869 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
870 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
871
872 /* Only labels on dispatch tables are valid for indexing from. */
873 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
874 { rtx temp; \
875 if (GET_CODE (X) == LABEL_REF \
876 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
877 && GET_CODE (temp) == JUMP_INSN \
878 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
879 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
880 goto ADDR; \
881 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
882
883 #define GO_IF_INDEXING(X, ADDR) \
884 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
885 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
886 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
887 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
888
889 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
890 { GO_IF_INDEXING (X, ADDR); \
891 if (GET_CODE (X) == PLUS) \
892 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
893 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
894 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
895 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
896 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
897 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
898
899 /* ColdFire/5200 does not allow HImode index registers. */
900 #define LEGITIMATE_INDEX_REG_P(X) \
901 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
902 || (! TARGET_COLDFIRE \
903 && GET_CODE (X) == SIGN_EXTEND \
904 && GET_CODE (XEXP (X, 0)) == REG \
905 && GET_MODE (XEXP (X, 0)) == HImode \
906 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
907 || (GET_CODE (X) == SUBREG \
908 && GET_CODE (SUBREG_REG (X)) == REG \
909 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
910
911 #define LEGITIMATE_INDEX_P(X) \
912 (LEGITIMATE_INDEX_REG_P (X) \
913 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
914 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
915 && GET_CODE (XEXP (X, 1)) == CONST_INT \
916 && (INTVAL (XEXP (X, 1)) == 2 \
917 || INTVAL (XEXP (X, 1)) == 4 \
918 || (INTVAL (XEXP (X, 1)) == 8 \
919 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))))
920
921 /* ColdFire FPU only accepts addressing modes 2-5. */
922 #define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
923 { if (LEGITIMATE_BASE_REG_P (X) \
924 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
925 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
926 || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
927 && (GET_CODE (XEXP (X, 1)) == CONST_INT) \
928 && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \
929 goto ADDR;}
930
931 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
932 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
933 { if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
934 { \
935 GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \
936 } \
937 else \
938 { \
939 GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
940 GO_IF_INDEXED_ADDRESS (X, ADDR); \
941 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
942 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
943 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
944 goto ADDR; \
945 }}
946
947 /* Don't call memory_address_noforce for the address to fetch
948 the switch offset. This address is ok as it stands (see above),
949 but memory_address_noforce would alter it. */
950 #define PIC_CASE_VECTOR_ADDRESS(index) index
951 \f
952 /* For the 68000, we handle X+REG by loading X into a register R and
953 using R+REG. R will go in an address reg and indexing will be used.
954 However, if REG is a broken-out memory address or multiplication,
955 nothing needs to be done because REG can certainly go in an address reg. */
956 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
957 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
958 { register int ch = (X) != (OLDX); \
959 if (GET_CODE (X) == PLUS) \
960 { int copied = 0; \
961 if (GET_CODE (XEXP (X, 0)) == MULT) \
962 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
963 if (GET_CODE (XEXP (X, 1)) == MULT) \
964 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
965 if (ch && GET_CODE (XEXP (X, 1)) == REG \
966 && GET_CODE (XEXP (X, 0)) == REG) \
967 { if (TARGET_COLDFIRE_FPU \
968 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
969 { COPY_ONCE (X); X = force_operand (X, 0);} \
970 goto WIN; } \
971 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
972 if (GET_CODE (XEXP (X, 0)) == REG \
973 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
974 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
975 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
976 { register rtx temp = gen_reg_rtx (Pmode); \
977 register rtx val = force_operand (XEXP (X, 1), 0); \
978 emit_move_insn (temp, val); \
979 COPY_ONCE (X); \
980 XEXP (X, 1) = temp; \
981 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
982 && GET_CODE (XEXP (X, 0)) == REG) \
983 X = force_operand (X, 0); \
984 goto WIN; } \
985 else if (GET_CODE (XEXP (X, 1)) == REG \
986 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
987 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
988 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
989 { register rtx temp = gen_reg_rtx (Pmode); \
990 register rtx val = force_operand (XEXP (X, 0), 0); \
991 emit_move_insn (temp, val); \
992 COPY_ONCE (X); \
993 XEXP (X, 0) = temp; \
994 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
995 && GET_CODE (XEXP (X, 1)) == REG) \
996 X = force_operand (X, 0); \
997 goto WIN; }}}
998
999 /* On the 68000, only predecrement and postincrement address depend thus
1000 (the amount of decrement or increment being the length of the operand).
1001 These are now treated generically in recog.c. */
1002 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1003 \f
1004 #define CASE_VECTOR_MODE HImode
1005 #define CASE_VECTOR_PC_RELATIVE 1
1006
1007 #define DEFAULT_SIGNED_CHAR 1
1008 #define MOVE_MAX 4
1009 #define SLOW_BYTE_ACCESS 0
1010
1011 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1012
1013 /* The ColdFire FF1 instruction returns 32 for zero. */
1014 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
1015
1016 #define STORE_FLAG_VALUE (-1)
1017
1018 #define Pmode SImode
1019 #define FUNCTION_MODE QImode
1020
1021 \f
1022 /* Tell final.c how to eliminate redundant test instructions. */
1023
1024 /* Here we define machine-dependent flags and fields in cc_status
1025 (see `conditions.h'). */
1026
1027 /* Set if the cc value is actually in the 68881, so a floating point
1028 conditional branch must be output. */
1029 #define CC_IN_68881 04000
1030
1031 /* On the 68000, all the insns to store in an address register fail to
1032 set the cc's. However, in some cases these instructions can make it
1033 possibly invalid to use the saved cc's. In those cases we clear out
1034 some or all of the saved cc's so they won't be used. */
1035 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1036
1037 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1038 do { if (cc_prev_status.flags & CC_IN_68881) \
1039 return FLOAT; \
1040 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1041 return NO_OV; \
1042 return NORMAL; } while (0)
1043 \f
1044 /* Control the assembler format that we output. */
1045
1046 #define ASM_APP_ON "#APP\n"
1047 #define ASM_APP_OFF "#NO_APP\n"
1048 #define TEXT_SECTION_ASM_OP "\t.text"
1049 #define DATA_SECTION_ASM_OP "\t.data"
1050 #define GLOBAL_ASM_OP "\t.globl\t"
1051 #define REGISTER_PREFIX ""
1052 #define LOCAL_LABEL_PREFIX ""
1053 #define USER_LABEL_PREFIX "_"
1054 #define IMMEDIATE_PREFIX "#"
1055
1056 #define REGISTER_NAMES \
1057 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
1058 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
1059 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
1060 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
1061 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
1062 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
1063 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
1064 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
1065 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
1066
1067 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
1068
1069 /* Return a register name by index, handling %fp nicely.
1070 We don't replace %fp for targets that don't map it to %a6
1071 since it may confuse GAS. */
1072 #define M68K_REGNAME(r) ( \
1073 ((FRAME_POINTER_REGNUM == 14) \
1074 && ((r) == FRAME_POINTER_REGNUM) \
1075 && frame_pointer_needed) ? \
1076 M68K_FP_REG_NAME : reg_names[(r)])
1077
1078 /* On the Sun-3, the floating point registers have numbers
1079 18 to 25, not 16 to 23 as they do in the compiler. */
1080 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1081
1082 /* Before the prologue, RA is at 0(%sp). */
1083 #define INCOMING_RETURN_ADDR_RTX \
1084 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1085
1086 /* After the prologue, RA is at 4(AP) in the current frame. */
1087 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1088 ((COUNT) == 0 \
1089 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
1090 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
1091
1092 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1093 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1094 Instead use the identity mapping. */
1095 #define DWARF_FRAME_REGNUM(REG) REG
1096
1097 /* Before the prologue, the top of the frame is at 4(%sp). */
1098 #define INCOMING_FRAME_SP_OFFSET 4
1099
1100 /* Describe how we implement __builtin_eh_return. */
1101 #define EH_RETURN_DATA_REGNO(N) \
1102 ((N) < 2 ? (N) : INVALID_REGNUM)
1103 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG)
1104 #define EH_RETURN_HANDLER_RTX \
1105 gen_rtx_MEM (Pmode, \
1106 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1107 plus_constant (EH_RETURN_STACKADJ_RTX, \
1108 UNITS_PER_WORD)))
1109
1110 /* Select a format to encode pointers in exception handling data. CODE
1111 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1112 true if the symbol may be affected by dynamic relocations.
1113
1114 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
1115 a read-only text segment without imposing a fixed gap between the
1116 text and data segments. As a result, the text segment cannot refer
1117 to anything in the data segment, even in PC-relative form. Because
1118 .eh_frame refers to both code and data, it follows that .eh_frame
1119 must be in the data segment itself, and that the offset between
1120 .eh_frame and code will not be a link-time constant.
1121
1122 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
1123 | DW_EH_PE_indirect for all code references. However, gcc currently
1124 handles indirect references using a per-TU constant pool. This means
1125 that if a function and its eh_frame are removed by the linker, the
1126 eh_frame's indirect references to the removed function will not be
1127 removed, leading to an unresolved symbol error.
1128
1129 It isn't clear that any -msep-data or -mid-shared-library target
1130 would benefit from a read-only .eh_frame anyway. In particular,
1131 no known target that supports these options has a feature like
1132 PT_GNU_RELRO. Without any such feature to motivate them, indirect
1133 references would be unnecessary bloat, so we simply use an absolute
1134 pointer for code and global references. We still use pc-relative
1135 references to data, as this avoids a relocation. */
1136 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1137 (flag_pic \
1138 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \
1139 && ((GLOBAL) || (CODE))) \
1140 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1141 : DW_EH_PE_absptr)
1142
1143 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1144 asm_fprintf (FILE, "%U%s", NAME)
1145
1146 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1147 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1148
1149 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1150 asm_fprintf (FILE, (MOTOROLA \
1151 ? "\tmove.l %s,-(%Rsp)\n" \
1152 : "\tmovel %s,%Rsp@-\n"), \
1153 reg_names[REGNO])
1154
1155 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1156 asm_fprintf (FILE, (MOTOROLA \
1157 ? "\tmove.l (%Rsp)+,%s\n" \
1158 : "\tmovel %Rsp@+,%s\n"), \
1159 reg_names[REGNO])
1160
1161 /* The m68k does not use absolute case-vectors, but we must define this macro
1162 anyway. */
1163 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1164 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1165
1166 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1167 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1168
1169 /* We don't have a way to align to more than a two-byte boundary, so do the
1170 best we can and don't complain. */
1171 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1172 if ((LOG) >= 1) \
1173 fprintf (FILE, "\t.even\n");
1174
1175 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1176 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1177
1178 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1179 ( fputs (".comm ", (FILE)), \
1180 assemble_name ((FILE), (NAME)), \
1181 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1182
1183 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1184 ( fputs (".lcomm ", (FILE)), \
1185 assemble_name ((FILE), (NAME)), \
1186 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1187
1188 /* Output a float value (represented as a C double) as an immediate operand.
1189 This macro is m68k-specific. */
1190 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1191 do { \
1192 if (CODE == 'f') \
1193 { \
1194 char dstr[30]; \
1195 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1196 asm_fprintf ((FILE), "%I0r%s", dstr); \
1197 } \
1198 else \
1199 { \
1200 long l; \
1201 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1202 asm_fprintf ((FILE), "%I0x%lx", l); \
1203 } \
1204 } while (0)
1205
1206 /* Output a double value (represented as a C double) as an immediate operand.
1207 This macro is m68k-specific. */
1208 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1209 do { char dstr[30]; \
1210 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1211 asm_fprintf (FILE, "%I0r%s", dstr); \
1212 } while (0)
1213
1214 /* Note, long double immediate operands are not actually
1215 generated by m68k.md. */
1216 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1217 do { char dstr[30]; \
1218 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1219 asm_fprintf (FILE, "%I0r%s", dstr); \
1220 } while (0)
1221
1222 /* On the 68000, we use several CODE characters:
1223 '.' for dot needed in Motorola-style opcode names.
1224 '-' for an operand pushing on the stack:
1225 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1226 '+' for an operand pushing on the stack:
1227 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1228 '@' for a reference to the top word on the stack:
1229 sp@, (sp) or (%sp) depending on the style of syntax.
1230 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1231 but & in SGS syntax).
1232 '!' for the fpcr register (used in some float-to-fixed conversions).
1233 '$' for the letter `s' in an op code, but only on the 68040.
1234 '&' for the letter `d' in an op code, but only on the 68040.
1235 '/' for register prefix needed by longlong.h.
1236
1237 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1238 'd' to force memory addressing to be absolute, not relative.
1239 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1240 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1241 or print pair of registers as rx:ry. */
1242
1243 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1244 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1245 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1246 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1247
1248
1249 /* See m68k.c for the m68k specific codes. */
1250 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1251
1252 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1253
1254 /* Values used in the MICROARCH argument to M68K_DEVICE. */
1255 enum uarch_type
1256 {
1257 u68000,
1258 u68010,
1259 u68020,
1260 u68020_40,
1261 u68020_60,
1262 u68030,
1263 u68040,
1264 u68060,
1265 ucpu32,
1266 ucfv2,
1267 ucfv3,
1268 ucfv4,
1269 ucfv4e,
1270 ucfv5,
1271 unk_arch
1272 };
1273
1274 /* An enumeration of all supported target devices. */
1275 enum target_device
1276 {
1277 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
1278 ENUM_VALUE,
1279 #include "m68k-devices.def"
1280 #undef M68K_DEVICE
1281 unk_device
1282 };
1283
1284 enum fpu_type
1285 {
1286 FPUTYPE_NONE,
1287 FPUTYPE_68881,
1288 FPUTYPE_COLDFIRE
1289 };
1290
1291 /* Variables in m68k.c; see there for details. */
1292 extern const char *m68k_library_id_string;
1293 extern int m68k_last_compare_had_fp_operands;
1294 extern enum target_device m68k_cpu;
1295 extern enum uarch_type m68k_tune;
1296 extern enum fpu_type m68k_fpu;
1297 extern unsigned int m68k_cpu_flags;
1298 extern const char *m68k_symbolic_call;
1299 extern const char *m68k_symbolic_jump;
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