1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93-98, 1999 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
521 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
540 if (ADDRESS_REG_P (operands[0])
541 && GET_CODE (operands[1]) == CONST_INT
542 && INTVAL (operands[1]) < 0x8000
543 && INTVAL (operands[1]) >= -0x8000)
546 return \"cmp%.w %0,%1\";
548 return \"cmp%.w %1,%0\";
552 return \"cmp%.l %d0,%d1\";
554 return \"cmp%.l %d1,%d0\";
560 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
561 (match_operand:SI 1 "general_operand" "r,mrKs")))]
565 if (REG_P (operands[1])
566 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
567 { cc_status.flags |= CC_REVERSED;
569 return \"cmp%.l %d1,%d0\";
571 return \"cmp%.l %d0,%d1\";
575 return \"cmp%.l %d0,%d1\";
577 return \"cmp%.l %d1,%d0\";
581 (define_expand "cmphi"
583 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
584 (match_operand:HI 1 "general_src_operand" "")))]
586 "m68k_last_compare_had_fp_operands = 0;")
590 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
591 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
595 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
597 return \"cmpm%.w %0,%1\";
599 return \"cmpm%.w %1,%0\";
601 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
602 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
603 { cc_status.flags |= CC_REVERSED;
605 return \"cmp%.w %d1,%d0\";
607 return \"cmp%.w %d0,%d1\";
611 return \"cmp%.w %d0,%d1\";
613 return \"cmp%.w %d1,%d0\";
617 (define_expand "cmpqi"
619 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
620 (match_operand:QI 1 "general_src_operand" "")))]
622 "m68k_last_compare_had_fp_operands = 0;")
626 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
627 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
631 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
633 return \"cmpm%.b %0,%1\";
635 return \"cmpm%.b %1,%0\";
637 if (REG_P (operands[1])
638 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
639 { cc_status.flags |= CC_REVERSED;
641 return \"cmp%.b %d1,%d0\";
643 return \"cmp%.b %d0,%d1\";
647 return \"cmp%.b %d0,%d1\";
649 return \"cmp%.b %d1,%d0\";
653 (define_expand "cmpdf"
655 (compare (match_operand:DF 0 "general_operand" "")
656 (match_operand:DF 1 "general_operand" "")))]
657 "TARGET_68881 || TARGET_FPA"
660 m68k_last_compare_had_fp_operands = 1;
663 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
668 (define_insn "cmpdf_fpa"
670 (compare (match_operand:DF 0 "general_operand" "x,y")
671 (match_operand:DF 1 "general_operand" "xH,rmF")))
672 (clobber (match_scratch:SI 2 "=d,d"))]
674 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
678 (compare (match_operand:DF 0 "general_operand" "f,mG")
679 (match_operand:DF 1 "general_operand" "fmG,f")))]
683 cc_status.flags = CC_IN_68881;
685 if (REG_P (operands[0]))
687 if (REG_P (operands[1]))
688 return \"fcmp%.x %0,%1\";
690 return \"fcmp%.d %0,%f1\";
692 cc_status.flags |= CC_REVERSED;
693 return \"fcmp%.d %1,%f0\";
695 if (REG_P (operands[0]))
697 if (REG_P (operands[1]))
698 return \"fcmp%.x %1,%0\";
700 return \"fcmp%.d %f1,%0\";
702 cc_status.flags |= CC_REVERSED;
703 return \"fcmp%.d %f0,%1\";
707 (define_expand "cmpsf"
709 (compare (match_operand:SF 0 "general_operand" "")
710 (match_operand:SF 1 "general_operand" "")))]
711 "TARGET_68881 || TARGET_FPA"
714 m68k_last_compare_had_fp_operands = 1;
717 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
722 (define_insn "cmpsf_fpa"
724 (compare (match_operand:SF 0 "general_operand" "x,y")
725 (match_operand:SF 1 "general_operand" "xH,rmF")))
726 (clobber (match_scratch:SI 2 "=d,d"))]
728 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
732 (compare (match_operand:SF 0 "general_operand" "f,mdG")
733 (match_operand:SF 1 "general_operand" "fmdG,f")))]
737 cc_status.flags = CC_IN_68881;
739 if (FP_REG_P (operands[0]))
741 if (FP_REG_P (operands[1]))
742 return \"fcmp%.x %0,%1\";
744 return \"fcmp%.s %0,%f1\";
746 cc_status.flags |= CC_REVERSED;
747 return \"fcmp%.s %1,%f0\";
749 if (FP_REG_P (operands[0]))
751 if (FP_REG_P (operands[1]))
752 return \"fcmp%.x %1,%0\";
754 return \"fcmp%.s %f1,%0\";
756 cc_status.flags |= CC_REVERSED;
757 return \"fcmp%.s %f0,%1\";
761 ;; Recognizers for btst instructions.
763 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
764 ;; specified as a constant, so we must disable all patterns that may extract
765 ;; from a MEM at a constant bit position if we can't use this as a constraint.
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "di"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
775 ;; This is the same as the above pattern except for the constraints. The 'i'
779 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
781 (minus:SI (const_int 7)
782 (match_operand:SI 1 "general_operand" "d"))))]
784 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
787 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
789 (minus:SI (const_int 31)
790 (match_operand:SI 1 "general_operand" "di"))))]
792 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
794 ;; The following two patterns are like the previous two
795 ;; except that they use the fact that bit-number operands
796 ;; are automatically masked to 3 or 5 bits.
799 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
801 (minus:SI (const_int 7)
803 (match_operand:SI 1 "register_operand" "d")
806 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
809 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
811 (minus:SI (const_int 31)
813 (match_operand:SI 1 "register_operand" "d")
816 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
818 ;; Nonoffsettable mem refs are ok in this one pattern
819 ;; since we don't try to adjust them.
821 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
823 (match_operand:SI 1 "const_int_operand" "n")))]
824 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
827 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
828 return output_btst (operands, operands[1], operands[0], insn, 7);
832 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
834 (match_operand:SI 1 "const_int_operand" "n")))]
838 if (GET_CODE (operands[0]) == MEM)
840 operands[0] = adj_offsettable_operand (operands[0],
841 INTVAL (operands[1]) / 8);
842 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
843 return output_btst (operands, operands[1], operands[0], insn, 7);
845 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
846 return output_btst (operands, operands[1], operands[0], insn, 31);
849 ;; This is the same as the above pattern except for the constraints.
850 ;; The 'o' has been replaced with 'Q'.
853 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
855 (match_operand:SI 1 "const_int_operand" "n")))]
859 if (GET_CODE (operands[0]) == MEM)
861 operands[0] = adj_offsettable_operand (operands[0],
862 INTVAL (operands[1]) / 8);
863 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
864 return output_btst (operands, operands[1], operands[0], insn, 7);
866 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
867 return output_btst (operands, operands[1], operands[0], insn, 31);
873 ;; A special case in which it is not desirable
874 ;; to reload the constant into a data register.
875 (define_insn "pushexthisi_const"
876 [(set (match_operand:SI 0 "push_operand" "=m")
877 (match_operand:SI 1 "const_int_operand" "J"))]
878 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
881 if (operands[1] == const0_rtx)
882 return \"clr%.l %0\";
887 ;(define_insn "swapsi"
888 ; [(set (match_operand:SI 0 "general_operand" "+r")
889 ; (match_operand:SI 1 "general_operand" "+r"))
890 ; (set (match_dup 1) (match_dup 0))]
894 ;; Special case of fullword move when source is zero.
895 ;; The reason this is special is to avoid loading a zero
896 ;; into a data reg with moveq in order to store it elsewhere.
898 (define_insn "movsi_const0"
899 [(set (match_operand:SI 0 "general_operand" "=g")
901 ;; clr insns on 68000 read before writing.
902 ;; This isn't so on the 68010, but we have no TARGET_68010.
903 "((TARGET_68020 || TARGET_5200)
904 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
907 if (ADDRESS_REG_P (operands[0]))
909 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
910 if (!TARGET_68040 && !TARGET_68060)
911 return \"sub%.l %0,%0\";
916 /* Many SGS assemblers croak on size specifiers for constants. */
919 return \"lea 0.w,%0\";
922 return \"lea 0:w,%0\";
926 /* moveq is faster on the 68000. */
927 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
928 #if defined(MOTOROLA) && !defined(CRDS)
929 return \"moveq%.l %#0,%0\";
931 return \"moveq %#0,%0\";
933 return \"clr%.l %0\";
936 ;; General case of fullword move.
938 ;; This is the main "hook" for PIC code. When generating
939 ;; PIC, movsi is responsible for determining when the source address
940 ;; needs PIC relocation and appropriately calling legitimize_pic_address
941 ;; to perform the actual relocation.
943 ;; In both the PIC and non-PIC cases the patterns generated will
944 ;; matched by the next define_insn.
945 (define_expand "movsi"
946 [(set (match_operand:SI 0 "general_operand" "")
947 (match_operand:SI 1 "general_operand" ""))]
951 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
953 /* The source is an address which requires PIC relocation.
954 Call legitimize_pic_address with the source, mode, and a relocation
955 register (a new pseudo, or the final destination if reload_in_progress
956 is set). Then fall through normally */
957 extern rtx legitimize_pic_address();
958 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
959 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
961 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
963 /* Don't allow writes to memory except via a register;
964 the m68k doesn't consider PC-relative addresses to be writable. */
965 if (symbolic_operand (operands[0], SImode))
966 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
967 else if (GET_CODE (operands[0]) == MEM
968 && symbolic_operand (XEXP (operands[0], 0), SImode))
969 operands[0] = gen_rtx (MEM, SImode,
970 force_reg (SImode, XEXP (operands[0], 0)));
974 ;; General case of fullword move. The register constraints
975 ;; force integer constants in range for a moveq to be reloaded
976 ;; if they are headed for memory.
978 ;; Notes: make sure no alternative allows g vs g.
979 ;; We don't allow f-regs since fixed point cannot go in them.
980 ;; We do allow y and x regs since fixed point is allowed in them.
981 [(set (match_operand:SI 0 "general_operand" "=g,d,a<,y,!*x*r*m")
982 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
987 if (which_alternative == 4)
988 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
989 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
990 return \"fpmove%.l %x1,%x0\";
991 return output_move_simode (operands);
995 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
996 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
998 "* return output_move_simode (operands);")
1000 ;; Special case of fullword move, where we need to get a non-GOT PIC
1001 ;; reference into an address register.
1003 [(set (match_operand:SI 0 "general_operand" "=a<")
1004 (match_operand:SI 1 "pcrel_address" ""))]
1008 if (push_operand (operands[0], SImode))
1010 return \"lea %a1,%0\";
1013 (define_expand "movhi"
1014 [(set (match_operand:HI 0 "general_operand" "")
1015 (match_operand:HI 1 "general_operand" ""))]
1020 [(set (match_operand:HI 0 "general_operand" "=g")
1021 (match_operand:HI 1 "general_src_operand" "gS"))]
1023 "* return output_move_himode (operands);")
1026 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
1027 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
1029 "* return output_move_himode (operands);")
1031 (define_expand "movstricthi"
1032 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1033 (match_operand:HI 1 "general_src_operand" ""))]
1038 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1039 (match_operand:HI 1 "general_src_operand" "rmSn"))]
1041 "* return output_move_stricthi (operands);")
1044 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1045 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
1047 "* return output_move_stricthi (operands);")
1049 (define_expand "movqi"
1050 [(set (match_operand:QI 0 "general_operand" "")
1051 (match_operand:QI 1 "general_src_operand" ""))]
1056 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1057 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
1059 "* return output_move_qimode (operands);")
1062 [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
1063 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
1065 "* return output_move_qimode (operands);")
1067 (define_expand "movstrictqi"
1068 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1069 (match_operand:QI 1 "general_src_operand" ""))]
1074 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1075 (match_operand:QI 1 "general_src_operand" "dmSn"))]
1077 "* return output_move_strictqi (operands);")
1080 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1081 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
1083 "* return output_move_strictqi (operands);")
1085 (define_expand "movsf"
1086 [(set (match_operand:SF 0 "general_operand" "")
1087 (match_operand:SF 1 "general_operand" ""))]
1092 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1093 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1094 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1095 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1099 if (which_alternative >= 4)
1100 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1101 if (FPA_REG_P (operands[0]))
1103 if (FPA_REG_P (operands[1]))
1104 return \"fpmove%.s %x1,%x0\";
1105 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1106 return output_move_const_single (operands);
1107 else if (FP_REG_P (operands[1]))
1108 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1109 return \"fpmove%.s %x1,%x0\";
1111 if (FPA_REG_P (operands[1]))
1113 if (FP_REG_P (operands[0]))
1114 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1116 return \"fpmove%.s %x1,%x0\";
1118 if (FP_REG_P (operands[0]))
1120 if (FP_REG_P (operands[1]))
1121 return \"f%$move%.x %1,%0\";
1122 else if (ADDRESS_REG_P (operands[1]))
1123 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1124 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1125 return output_move_const_single (operands);
1126 return \"f%$move%.s %f1,%0\";
1128 if (FP_REG_P (operands[1]))
1130 if (ADDRESS_REG_P (operands[0]))
1131 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1132 return \"fmove%.s %f1,%0\";
1134 if (operands[1] == CONST0_RTX (SFmode)
1135 /* clr insns on 68000 read before writing.
1136 This isn't so on the 68010, but we have no TARGET_68010. */
1137 && ((TARGET_68020 || TARGET_5200)
1138 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1140 if (ADDRESS_REG_P (operands[0]))
1142 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1143 if (!TARGET_68040 && !TARGET_68060)
1144 return \"sub%.l %0,%0\";
1149 /* Many SGS assemblers croak on size specifiers for constants. */
1150 return \"lea 0,%0\";
1152 return \"lea 0.w,%0\";
1155 return \"lea 0:w,%0\";
1159 /* moveq is faster on the 68000. */
1160 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1162 #if defined(MOTOROLA) && !defined(CRDS)
1163 return \"moveq%.l %#0,%0\";
1165 return \"moveq %#0,%0\";
1168 return \"clr%.l %0\";
1170 return \"move%.l %1,%0\";
1174 [(set (match_operand:SF 0 "general_operand" "=r,g")
1175 (match_operand:SF 1 "general_operand" "g,r"))]
1177 "* return \"move%.l %1,%0\";")
1179 (define_expand "movdf"
1180 [(set (match_operand:DF 0 "general_operand" "")
1181 (match_operand:DF 1 "general_operand" ""))]
1186 [(set (match_operand:DF 0 "general_operand"
1187 "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
1188 (match_operand:DF 1 "general_operand"
1189 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
1190 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1191 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1195 if (which_alternative == 7)
1196 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1197 if (FPA_REG_P (operands[0]))
1199 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1200 return output_move_const_double (operands);
1201 if (FP_REG_P (operands[1]))
1202 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1203 return \"fpmove%.d %x1,%x0\";
1205 else if (FPA_REG_P (operands[1]))
1207 if (FP_REG_P(operands[0]))
1208 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1210 return \"fpmove%.d %x1,%x0\";
1212 if (FP_REG_P (operands[0]))
1214 if (FP_REG_P (operands[1]))
1215 return \"f%&move%.x %1,%0\";
1216 if (REG_P (operands[1]))
1219 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1220 output_asm_insn (\"move%.l %1,%-\", xoperands);
1221 output_asm_insn (\"move%.l %1,%-\", operands);
1222 return \"f%&move%.d %+,%0\";
1224 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1225 return output_move_const_double (operands);
1226 return \"f%&move%.d %f1,%0\";
1228 else if (FP_REG_P (operands[1]))
1230 if (REG_P (operands[0]))
1232 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1233 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1234 return \"move%.l %+,%0\";
1237 return \"fmove%.d %f1,%0\";
1239 return output_move_double (operands);
1243 [(set (match_operand:DF 0 "general_operand" "=r,g")
1244 (match_operand:DF 1 "general_operand" "g,r"))]
1246 "* return output_move_double (operands);")
1248 (define_expand "movxf"
1249 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1250 (match_operand:XF 1 "general_operand" ""))]
1254 if (CONSTANT_P (operands[1]))
1256 operands[1] = force_const_mem (XFmode, operands[1]);
1257 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1258 && ! reload_in_progress)
1259 operands[1] = change_address (operands[1], XFmode,
1260 XEXP (operands[1], 0));
1262 if (flag_pic && TARGET_PCREL && ! reload_in_progress)
1264 /* Don't allow writes to memory except via a register;
1265 the m68k doesn't consider PC-relative addresses to be writable. */
1266 if (GET_CODE (operands[0]) == MEM
1267 && symbolic_operand (XEXP (operands[0], 0), SImode))
1268 operands[0] = gen_rtx (MEM, XFmode,
1269 force_reg (SImode, XEXP (operands[0], 0)));
1274 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1275 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1279 if (FP_REG_P (operands[0]))
1281 if (FP_REG_P (operands[1]))
1282 return \"fmove%.x %1,%0\";
1283 if (REG_P (operands[1]))
1286 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1287 output_asm_insn (\"move%.l %1,%-\", xoperands);
1288 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1289 output_asm_insn (\"move%.l %1,%-\", xoperands);
1290 output_asm_insn (\"move%.l %1,%-\", operands);
1291 return \"fmove%.x %+,%0\";
1293 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1294 return \"fmove%.x %1,%0\";
1295 return \"fmove%.x %f1,%0\";
1297 if (FP_REG_P (operands[1]))
1299 if (REG_P (operands[0]))
1301 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1302 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1303 output_asm_insn (\"move%.l %+,%0\", operands);
1304 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1305 return \"move%.l %+,%0\";
1307 /* Must be memory destination. */
1308 return \"fmove%.x %f1,%0\";
1310 return output_move_double (operands);
1315 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1316 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1317 "! TARGET_68881 && ! TARGET_5200"
1320 if (FP_REG_P (operands[0]))
1322 if (FP_REG_P (operands[1]))
1323 return \"fmove%.x %1,%0\";
1324 if (REG_P (operands[1]))
1327 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1328 output_asm_insn (\"move%.l %1,%-\", xoperands);
1329 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1330 output_asm_insn (\"move%.l %1,%-\", xoperands);
1331 output_asm_insn (\"move%.l %1,%-\", operands);
1332 return \"fmove%.x %+,%0\";
1334 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1335 return \"fmove%.x %1,%0\";
1336 return \"fmove%.x %f1,%0\";
1338 if (FP_REG_P (operands[1]))
1340 if (REG_P (operands[0]))
1342 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1343 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1344 output_asm_insn (\"move%.l %+,%0\", operands);
1345 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1346 return \"move%.l %+,%0\";
1349 return \"fmove%.x %f1,%0\";
1351 return output_move_double (operands);
1356 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1357 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1358 "! TARGET_68881 && TARGET_5200"
1359 "* return output_move_double (operands);")
1361 (define_expand "movdi"
1362 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1363 [(set (match_operand:DI 0 "general_operand" "")
1364 (match_operand:DI 1 "general_operand" ""))]
1368 ;; movdi can apply to fp regs in some cases
1370 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1371 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1372 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1373 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1374 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1375 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1376 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1380 if (which_alternative == 8)
1381 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1382 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1383 return \"fpmove%.d %x1,%x0\";
1384 if (FP_REG_P (operands[0]))
1386 if (FP_REG_P (operands[1]))
1387 return \"fmove%.x %1,%0\";
1388 if (REG_P (operands[1]))
1391 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1392 output_asm_insn (\"move%.l %1,%-\", xoperands);
1393 output_asm_insn (\"move%.l %1,%-\", operands);
1394 return \"fmove%.d %+,%0\";
1396 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1397 return output_move_const_double (operands);
1398 return \"fmove%.d %f1,%0\";
1400 else if (FP_REG_P (operands[1]))
1402 if (REG_P (operands[0]))
1404 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1405 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1406 return \"move%.l %+,%0\";
1409 return \"fmove%.d %f1,%0\";
1411 return output_move_double (operands);
1415 [(set (match_operand:DI 0 "general_operand" "=r,g")
1416 (match_operand:DI 1 "general_operand" "g,r"))]
1418 "* return output_move_double (operands);")
1420 ;; Thus goes after the move instructions
1421 ;; because the move instructions are better (require no spilling)
1422 ;; when they can apply. It goes before the add/sub insns
1423 ;; so we will prefer it to them.
1425 (define_insn "pushasi"
1426 [(set (match_operand:SI 0 "push_operand" "=m")
1427 (match_operand:SI 1 "address_operand" "p"))]
1431 ;; truncation instructions
1432 (define_insn "truncsiqi2"
1433 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1435 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1439 if (GET_CODE (operands[0]) == REG)
1441 /* Must clear condition codes, since the move.l bases them on
1442 the entire 32 bits, not just the desired 8 bits. */
1444 return \"move%.l %1,%0\";
1446 if (GET_CODE (operands[1]) == MEM)
1447 operands[1] = adj_offsettable_operand (operands[1], 3);
1448 return \"move%.b %1,%0\";
1451 (define_insn "trunchiqi2"
1452 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1454 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1458 if (GET_CODE (operands[0]) == REG
1459 && (GET_CODE (operands[1]) == MEM
1460 || GET_CODE (operands[1]) == CONST_INT))
1462 /* Must clear condition codes, since the move.w bases them on
1463 the entire 16 bits, not just the desired 8 bits. */
1465 return \"move%.w %1,%0\";
1467 if (GET_CODE (operands[0]) == REG)
1469 /* Must clear condition codes, since the move.l bases them on
1470 the entire 32 bits, not just the desired 8 bits. */
1472 return \"move%.l %1,%0\";
1474 if (GET_CODE (operands[1]) == MEM)
1475 operands[1] = adj_offsettable_operand (operands[1], 1);
1476 return \"move%.b %1,%0\";
1479 (define_insn "truncsihi2"
1480 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1482 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1486 if (GET_CODE (operands[0]) == REG)
1488 /* Must clear condition codes, since the move.l bases them on
1489 the entire 32 bits, not just the desired 8 bits. */
1491 return \"move%.l %1,%0\";
1493 if (GET_CODE (operands[1]) == MEM)
1494 operands[1] = adj_offsettable_operand (operands[1], 2);
1495 return \"move%.w %1,%0\";
1498 ;; zero extension instructions
1500 (define_insn "zero_extendqidi2"
1501 [(set (match_operand:DI 0 "general_operand" "=&d")
1502 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1507 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1508 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1511 (define_insn "zero_extendhidi2"
1512 [(set (match_operand:DI 0 "general_operand" "=&d")
1513 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1518 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1519 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1522 ;; this is the canonical form for (lshiftrt:DI x 32)
1523 (define_insn "zero_extendsidi2"
1524 [(set (match_operand:DI 0 "general_operand" "rm")
1525 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1530 if (GET_CODE (operands[0]) == REG)
1531 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1532 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1533 return \"move%.l %1,%0\;clr%.l %0\";
1534 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1535 return \"clr%.l %0\;move%.l %1,%0\";
1537 operands[2] = adj_offsettable_operand (operands[0], 4);
1538 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1539 || REGNO (operands[1]) != REGNO (operands[2]))
1540 output_asm_insn (\"move%.l %1,%2\", operands);
1541 if (ADDRESS_REG_P (operands[0]))
1542 return \"sub%.l %0,%0\";
1544 return \"clr%.l %0\";
1547 (define_expand "zero_extendhisi2"
1548 [(set (match_operand:SI 0 "register_operand" "")
1550 (set (strict_low_part (match_dup 2))
1551 (match_operand:HI 1 "general_operand" ""))]
1555 operands[1] = make_safe_from (operands[1], operands[0]);
1556 if (GET_CODE (operands[0]) == SUBREG)
1557 operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
1558 SUBREG_WORD (operands[0]));
1560 operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
1563 (define_expand "zero_extendqihi2"
1564 [(set (match_operand:HI 0 "register_operand" "")
1566 (set (strict_low_part (match_dup 2))
1567 (match_operand:QI 1 "general_operand" ""))]
1571 operands[1] = make_safe_from (operands[1], operands[0]);
1572 if (GET_CODE (operands[0]) == SUBREG)
1573 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1574 SUBREG_WORD (operands[0]));
1576 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1579 (define_expand "zero_extendqisi2"
1580 [(set (match_operand:SI 0 "register_operand" "")
1582 (set (strict_low_part (match_dup 2))
1583 (match_operand:QI 1 "general_operand" ""))]
1587 operands[1] = make_safe_from (operands[1], operands[0]);
1588 if (GET_CODE (operands[0]) == SUBREG)
1589 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1590 SUBREG_WORD (operands[0]));
1592 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1595 ;; Patterns to recognize zero-extend insns produced by the combiner.
1596 ;; We don't allow both operands in memory, because of aliasing problems.
1597 ;; Explicitly disallow two memory operands via the condition since reloading
1598 ;; of this case will result in worse code than the uncombined patterns.
1601 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1602 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1603 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1606 if (DATA_REG_P (operands[0]))
1608 if (GET_CODE (operands[1]) == REG
1609 && REGNO (operands[0]) == REGNO (operands[1]))
1610 return \"and%.l %#0xFFFF,%0\";
1611 if (reg_mentioned_p (operands[0], operands[1]))
1612 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1613 return \"clr%.l %0\;move%.w %1,%0\";
1615 else if (GET_CODE (operands[0]) == MEM
1616 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1617 return \"move%.w %1,%0\;clr%.w %0\";
1618 else if (GET_CODE (operands[0]) == MEM
1619 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1620 return \"clr%.w %0\;move%.w %1,%0\";
1623 output_asm_insn (\"clr%.w %0\", operands);
1624 operands[0] = adj_offsettable_operand (operands[0], 2);
1625 return \"move%.w %1,%0\";
1630 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1631 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1632 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1635 if (DATA_REG_P (operands[0]))
1637 if (GET_CODE (operands[1]) == REG
1638 && REGNO (operands[0]) == REGNO (operands[1]))
1639 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1640 if (reg_mentioned_p (operands[0], operands[1]))
1641 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1642 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1643 return \"clr%.w %0\;move%.b %1,%0\";
1645 else if (GET_CODE (operands[0]) == MEM
1646 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1648 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1649 == STACK_POINTER_REGNUM)
1651 output_asm_insn (\"clr%.w %-\", operands);
1652 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1653 plus_constant (stack_pointer_rtx, 1));
1654 return \"move%.b %1,%0\";
1657 return \"move%.b %1,%0\;clr%.b %0\";
1659 else if (GET_CODE (operands[0]) == MEM
1660 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1661 return \"clr%.b %0\;move%.b %1,%0\";
1664 output_asm_insn (\"clr%.b %0\", operands);
1665 operands[0] = adj_offsettable_operand (operands[0], 1);
1666 return \"move%.b %1,%0\";
1671 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1672 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1673 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1676 if (DATA_REG_P (operands[0]))
1678 if (GET_CODE (operands[1]) == REG
1679 && REGNO (operands[0]) == REGNO (operands[1]))
1680 return \"and%.l %#0xFF,%0\";
1681 if (reg_mentioned_p (operands[0], operands[1]))
1682 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1683 return \"clr%.l %0\;move%.b %1,%0\";
1685 else if (GET_CODE (operands[0]) == MEM
1686 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1688 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1691 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1693 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1696 return \"clrl %0@-\;moveb %1,%0@(3)\";
1699 else if (GET_CODE (operands[0]) == MEM
1700 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1702 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1705 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1707 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1710 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1715 output_asm_insn (\"clr%.l %0\", operands);
1716 operands[0] = adj_offsettable_operand (operands[0], 3);
1717 return \"move%.b %1,%0\";
1721 ;; sign extension instructions
1723 (define_insn "extendqidi2"
1724 [(set (match_operand:DI 0 "general_operand" "=d")
1725 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1730 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1731 if (TARGET_68020 || TARGET_5200)
1732 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1734 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1737 (define_insn "extendhidi2"
1738 [(set (match_operand:DI 0 "general_operand" "=d")
1740 (match_operand:HI 1 "general_src_operand" "rmS")))]
1745 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1746 if (TARGET_68020 || TARGET_5200)
1747 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1749 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1752 (define_insn "extendsidi2"
1753 [(set (match_operand:DI 0 "general_operand" "=d")
1755 (match_operand:SI 1 "general_operand" "rm")))]
1760 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1761 if (TARGET_68020 || TARGET_5200)
1762 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1764 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1767 ;; Special case when one can avoid register clobbering, copy and test
1768 ;; Maybe there is a way to make that the general case, by forcing the
1769 ;; result of the SI tree to be in the lower register of the DI target
1771 (define_insn "extendplussidi"
1772 [(set (match_operand:DI 0 "register_operand" "=d")
1773 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1774 (match_operand:SI 2 "general_operand" "rmn"))))]
1779 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1780 if (GET_CODE (operands[1]) == CONST_INT
1781 && (unsigned) INTVAL (operands[1]) > 8)
1783 rtx tmp = operands[1];
1785 operands[1] = operands[2];
1788 if (GET_CODE (operands[1]) == REG
1789 && REGNO (operands[1]) == REGNO (operands[3]))
1790 output_asm_insn (\"add%.l %2,%3\", operands);
1792 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1793 if (TARGET_68020 || TARGET_5200)
1794 return \"smi %0\;extb%.l %0\";
1796 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1799 (define_insn "extendhisi2"
1800 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1802 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1806 if (ADDRESS_REG_P (operands[0]))
1807 return \"move%.w %1,%0\";
1808 return \"ext%.l %0\";
1811 (define_insn "extendqihi2"
1812 [(set (match_operand:HI 0 "general_operand" "=d")
1813 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1817 (define_insn "extendqisi2"
1818 [(set (match_operand:SI 0 "general_operand" "=d")
1819 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1820 "TARGET_68020 || TARGET_5200"
1823 ;; Conversions between float and double.
1825 (define_expand "extendsfdf2"
1826 [(set (match_operand:DF 0 "general_operand" "")
1828 (match_operand:SF 1 "general_operand" "")))]
1829 "TARGET_68881 || TARGET_FPA"
1833 [(set (match_operand:DF 0 "general_operand" "=x,y")
1835 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1840 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1842 (match_operand:SF 1 "general_operand" "f,dmF")))]
1846 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1848 if (REGNO (operands[0]) == REGNO (operands[1]))
1850 /* Extending float to double in an fp-reg is a no-op.
1851 NOTICE_UPDATE_CC has already assumed that the
1852 cc will be set. So cancel what it did. */
1853 cc_status = cc_prev_status;
1856 return \"f%&move%.x %1,%0\";
1858 if (FP_REG_P (operands[0]))
1859 return \"f%&move%.s %f1,%0\";
1860 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1862 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1863 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1864 return \"move%.l %+,%0\";
1866 return \"fmove%.d %f1,%0\";
1869 ;; This cannot output into an f-reg because there is no way to be
1870 ;; sure of truncating in that case.
1871 ;; But on the Sun FPA, we can be sure.
1872 (define_expand "truncdfsf2"
1873 [(set (match_operand:SF 0 "general_operand" "")
1875 (match_operand:DF 1 "general_operand" "")))]
1876 "TARGET_68881 || TARGET_FPA"
1880 [(set (match_operand:SF 0 "general_operand" "=x,y")
1882 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1886 ;; On the '040 we can truncate in a register accurately and easily.
1888 [(set (match_operand:SF 0 "general_operand" "=f")
1890 (match_operand:DF 1 "general_operand" "fmG")))]
1894 if (FP_REG_P (operands[1]))
1895 return \"f%$move%.x %1,%0\";
1896 return \"f%$move%.d %f1,%0\";
1900 [(set (match_operand:SF 0 "general_operand" "=dm")
1902 (match_operand:DF 1 "general_operand" "f")))]
1906 ;; Conversion between fixed point and floating point.
1907 ;; Note that among the fix-to-float insns
1908 ;; the ones that start with SImode come first.
1909 ;; That is so that an operand that is a CONST_INT
1910 ;; (and therefore lacks a specific machine mode).
1911 ;; will be recognized as SImode (which is always valid)
1912 ;; rather than as QImode or HImode.
1914 (define_expand "floatsisf2"
1915 [(set (match_operand:SF 0 "general_operand" "")
1916 (float:SF (match_operand:SI 1 "general_operand" "")))]
1917 "TARGET_68881 || TARGET_FPA"
1921 [(set (match_operand:SF 0 "general_operand" "=y,x")
1922 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1927 [(set (match_operand:SF 0 "general_operand" "=f")
1928 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1932 (define_expand "floatsidf2"
1933 [(set (match_operand:DF 0 "general_operand" "")
1934 (float:DF (match_operand:SI 1 "general_operand" "")))]
1935 "TARGET_68881 || TARGET_FPA"
1939 [(set (match_operand:DF 0 "general_operand" "=y,x")
1940 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1945 [(set (match_operand:DF 0 "general_operand" "=f")
1946 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1950 (define_insn "floathisf2"
1951 [(set (match_operand:SF 0 "general_operand" "=f")
1952 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1956 (define_insn "floathidf2"
1957 [(set (match_operand:DF 0 "general_operand" "=f")
1958 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1962 (define_insn "floatqisf2"
1963 [(set (match_operand:SF 0 "general_operand" "=f")
1964 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1968 (define_insn "floatqidf2"
1969 [(set (match_operand:DF 0 "general_operand" "=f")
1970 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1974 ;; New routines to convert floating-point values to integers
1975 ;; to be used on the '040. These should be faster than trapping
1976 ;; into the kernel to emulate fintrz. They should also be faster
1977 ;; than calling the subroutines fixsfsi or fixdfsi.
1979 (define_insn "fix_truncdfsi2"
1980 [(set (match_operand:SI 0 "general_operand" "=dm")
1981 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1982 (clobber (match_scratch:SI 2 "=d"))
1983 (clobber (match_scratch:SI 3 "=d"))]
1984 "TARGET_68881 && TARGET_68040"
1988 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1991 (define_insn "fix_truncdfhi2"
1992 [(set (match_operand:HI 0 "general_operand" "=dm")
1993 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1994 (clobber (match_scratch:SI 2 "=d"))
1995 (clobber (match_scratch:SI 3 "=d"))]
1996 "TARGET_68881 && TARGET_68040"
2000 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
2003 (define_insn "fix_truncdfqi2"
2004 [(set (match_operand:QI 0 "general_operand" "=dm")
2005 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2006 (clobber (match_scratch:SI 2 "=d"))
2007 (clobber (match_scratch:SI 3 "=d"))]
2008 "TARGET_68881 && TARGET_68040"
2012 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
2015 ;; Convert a float to a float whose value is an integer.
2016 ;; This is the first stage of converting it to an integer type.
2018 (define_insn "ftruncdf2"
2019 [(set (match_operand:DF 0 "general_operand" "=f")
2020 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
2021 "TARGET_68881 && !TARGET_68040"
2024 if (FP_REG_P (operands[1]))
2025 return \"fintrz%.x %f1,%0\";
2026 return \"fintrz%.d %f1,%0\";
2029 (define_insn "ftruncsf2"
2030 [(set (match_operand:SF 0 "general_operand" "=f")
2031 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
2032 "TARGET_68881 && !TARGET_68040"
2035 if (FP_REG_P (operands[1]))
2036 return \"fintrz%.x %f1,%0\";
2037 return \"fintrz%.s %f1,%0\";
2040 ;; Convert a float whose value is an integer
2041 ;; to an actual integer. Second stage of converting float to integer type.
2042 (define_insn "fixsfqi2"
2043 [(set (match_operand:QI 0 "general_operand" "=dm")
2044 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2048 (define_insn "fixsfhi2"
2049 [(set (match_operand:HI 0 "general_operand" "=dm")
2050 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2054 (define_insn "fixsfsi2"
2055 [(set (match_operand:SI 0 "general_operand" "=dm")
2056 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2060 (define_insn "fixdfqi2"
2061 [(set (match_operand:QI 0 "general_operand" "=dm")
2062 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2066 (define_insn "fixdfhi2"
2067 [(set (match_operand:HI 0 "general_operand" "=dm")
2068 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2072 (define_insn "fixdfsi2"
2073 [(set (match_operand:SI 0 "general_operand" "=dm")
2074 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2078 ;; Convert a float to an integer.
2079 ;; On the Sun FPA, this is done in one step.
2082 [(set (match_operand:SI 0 "general_operand" "=x,y")
2083 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2088 [(set (match_operand:SI 0 "general_operand" "=x,y")
2089 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2095 (define_insn "adddi_lshrdi_63"
2096 [(set (match_operand:DI 0 "general_operand" "=d")
2097 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2100 (clobber (match_scratch:SI 2 "=d"))]
2104 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2105 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2107 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2108 if (GET_CODE (operands[1]) == REG)
2109 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2110 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2111 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2112 operands[4] = operands[1];
2114 operands[4] = adj_offsettable_operand (operands[1], 4);
2115 if (GET_CODE (operands[1]) == MEM
2116 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2117 output_asm_insn (\"move%.l %4,%3\", operands);
2118 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2119 if (TARGET_68020 || TARGET_5200)
2120 output_asm_insn (\"extb%.l %2\", operands);
2122 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2123 if (GET_CODE (operands[1]) != MEM
2124 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2125 output_asm_insn (\"move%.l %4,%3\", operands);
2126 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2129 (define_insn "adddi_sexthishl32"
2130 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2131 (plus:DI (ashift:DI (sign_extend:DI
2132 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2134 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2135 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2140 if (ADDRESS_REG_P (operands[0]))
2141 return \"add%.w %1,%0\";
2142 else if (ADDRESS_REG_P (operands[3]))
2143 return \"move%.w %1,%3\;add%.l %3,%0\";
2145 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2148 (define_insn "adddi_dilshr32"
2149 [(set (match_operand:DI 0 "general_operand" "=d,o")
2150 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2151 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2152 ;; (const_int 32))))]
2153 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
2155 (match_operand:DI 2 "general_operand" "0,0")))]
2160 if (GET_CODE (operands[0]) == REG)
2161 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2163 operands[2] = adj_offsettable_operand (operands[0], 4);
2164 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2167 (define_insn "adddi_dishl32"
2168 [(set (match_operand:DI 0 "general_operand" "=r,o")
2169 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2170 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2171 ;; (const_int 32))))]
2172 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
2174 (match_operand:DI 2 "general_operand" "0,0")))]
2179 if (GET_CODE (operands[1]) == REG)
2180 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2182 operands[1] = adj_offsettable_operand (operands[1], 4);
2183 return \"add%.l %1,%0\";
2186 (define_insn "adddi3"
2187 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2188 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2189 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2190 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2194 if (DATA_REG_P (operands[0]))
2196 if (DATA_REG_P (operands[2]))
2197 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2198 else if (GET_CODE (operands[2]) == MEM
2199 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2200 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2206 if (GET_CODE (operands[2]) == REG)
2208 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2211 else if (CONSTANT_P (operands[2]))
2212 split_double (operands[2], &high, &low);
2215 low = adj_offsettable_operand (operands[2], 4);
2219 operands[1] = low, operands[2] = high;
2220 xoperands[0] = operands[3];
2221 if (GET_CODE (operands[1]) == CONST_INT
2222 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2223 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2225 xoperands[1] = operands[2];
2227 output_asm_insn (output_move_simode (xoperands), xoperands);
2228 if (GET_CODE (operands[1]) == CONST_INT)
2230 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2233 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2235 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2238 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2240 operands[1] = GEN_INT (-INTVAL (operands[1]));
2242 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2244 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2248 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2251 else if (GET_CODE (operands[0]) == MEM)
2253 if (GET_CODE (operands[2]) == MEM
2254 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2255 return \"add%.l %2,%0\;addx%.l %2,%0\";
2257 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2259 operands[1] = gen_rtx_MEM (SImode,
2260 plus_constant (XEXP(operands[0], 0), -8));
2261 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2263 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2265 operands[1] = XEXP(operands[0], 0);
2266 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2270 operands[1] = adj_offsettable_operand (operands[0], 4);
2271 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2278 (define_insn "addsi_lshrsi_31"
2279 [(set (match_operand:SI 0 "general_operand" "=dm")
2280 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2286 operands[2] = operands[0];
2287 operands[3] = gen_label_rtx();
2288 if (GET_CODE (operands[0]) == MEM)
2290 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2291 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2292 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2293 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2295 output_asm_insn (\"move%.l %1,%0\", operands);
2297 output_asm_insn (\"jbpl %l3\", operands);
2299 output_asm_insn (\"jpl %l3\", operands);
2302 output_asm_insn (\"addq%.l %#1,%2\", operands);
2304 output_asm_insn (\"add%.l %#1,%2\", operands);
2306 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2307 CODE_LABEL_NUMBER (operands[3]));
2311 (define_expand "addsi3"
2312 [(set (match_operand:SI 0 "general_operand" "")
2313 (plus:SI (match_operand:SI 1 "general_operand" "")
2314 (match_operand:SI 2 "general_src_operand" "")))]
2318 ;; Note that the middle two alternatives are near-duplicates
2319 ;; in order to handle insns generated by reload.
2320 ;; This is needed since they are not themselves reloaded,
2321 ;; so commutativity won't apply to them.
2322 (define_insn "*addsi3_internal"
2323 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,d,a")
2324 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2325 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2329 "* return output_addsi3 (operands);")
2331 (define_insn "*addsi3_5200"
2332 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2333 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2334 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2336 "* return output_addsi3 (operands);")
2339 [(set (match_operand:SI 0 "general_operand" "=a")
2340 (plus:SI (match_operand:SI 1 "general_operand" "0")
2342 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2346 (define_insn "addhi3"
2347 [(set (match_operand:HI 0 "general_operand" "=m,r")
2348 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2349 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2353 if (GET_CODE (operands[2]) == CONST_INT)
2356 /* If the constant would be a negative number when interpreted as
2357 HImode, make it negative. This is usually, but not always, done
2358 elsewhere in the compiler. First check for constants out of range,
2359 which could confuse us. */
2361 if (INTVAL (operands[2]) >= 32768)
2362 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2364 if (INTVAL (operands[2]) > 0
2365 && INTVAL (operands[2]) <= 8)
2366 return \"addq%.w %2,%0\";
2367 if (INTVAL (operands[2]) < 0
2368 && INTVAL (operands[2]) >= -8)
2370 operands[2] = GEN_INT (- INTVAL (operands[2]));
2371 return \"subq%.w %2,%0\";
2373 /* On the CPU32 it is faster to use two addqw instructions to
2374 add a small integer (8 < N <= 16) to a register.
2375 Likewise for subqw. */
2376 if (TARGET_CPU32 && REG_P (operands[0]))
2378 if (INTVAL (operands[2]) > 8
2379 && INTVAL (operands[2]) <= 16)
2381 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2382 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2384 if (INTVAL (operands[2]) < -8
2385 && INTVAL (operands[2]) >= -16)
2387 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2388 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2392 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2394 return \"lea (%c2,%0),%0\";
2396 return \"lea %0@(%c2),%0\";
2399 return \"add%.w %2,%0\";
2402 ;; These insns must use MATCH_DUP instead of the more expected
2403 ;; use of a matching constraint because the "output" here is also
2404 ;; an input, so you can't use the matching constraint. That also means
2405 ;; that you can't use the "%", so you need patterns with the matched
2406 ;; operand in both positions.
2409 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2410 (plus:HI (match_dup 0)
2411 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2415 if (GET_CODE (operands[1]) == CONST_INT)
2418 /* If the constant would be a negative number when interpreted as
2419 HImode, make it negative. This is usually, but not always, done
2420 elsewhere in the compiler. First check for constants out of range,
2421 which could confuse us. */
2423 if (INTVAL (operands[1]) >= 32768)
2424 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2426 if (INTVAL (operands[1]) > 0
2427 && INTVAL (operands[1]) <= 8)
2428 return \"addq%.w %1,%0\";
2429 if (INTVAL (operands[1]) < 0
2430 && INTVAL (operands[1]) >= -8)
2432 operands[1] = GEN_INT (- INTVAL (operands[1]));
2433 return \"subq%.w %1,%0\";
2435 /* On the CPU32 it is faster to use two addqw instructions to
2436 add a small integer (8 < N <= 16) to a register.
2437 Likewise for subqw. */
2438 if (TARGET_CPU32 && REG_P (operands[0]))
2440 if (INTVAL (operands[1]) > 8
2441 && INTVAL (operands[1]) <= 16)
2443 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2444 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2446 if (INTVAL (operands[1]) < -8
2447 && INTVAL (operands[1]) >= -16)
2449 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2450 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2454 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2456 return \"lea (%c1,%0),%0\";
2458 return \"lea %0@(%c1),%0\";
2461 return \"add%.w %1,%0\";
2465 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2466 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2471 if (GET_CODE (operands[1]) == CONST_INT)
2474 /* If the constant would be a negative number when interpreted as
2475 HImode, make it negative. This is usually, but not always, done
2476 elsewhere in the compiler. First check for constants out of range,
2477 which could confuse us. */
2479 if (INTVAL (operands[1]) >= 32768)
2480 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2482 if (INTVAL (operands[1]) > 0
2483 && INTVAL (operands[1]) <= 8)
2484 return \"addq%.w %1,%0\";
2485 if (INTVAL (operands[1]) < 0
2486 && INTVAL (operands[1]) >= -8)
2488 operands[1] = GEN_INT (- INTVAL (operands[1]));
2489 return \"subq%.w %1,%0\";
2491 /* On the CPU32 it is faster to use two addqw instructions to
2492 add a small integer (8 < N <= 16) to a register.
2493 Likewise for subqw. */
2494 if (TARGET_CPU32 && REG_P (operands[0]))
2496 if (INTVAL (operands[1]) > 8
2497 && INTVAL (operands[1]) <= 16)
2499 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2500 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2502 if (INTVAL (operands[1]) < -8
2503 && INTVAL (operands[1]) >= -16)
2505 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2506 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2510 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2512 return \"lea (%c1,%0),%0\";
2514 return \"lea %0@(%c1),%0\";
2517 return \"add%.w %1,%0\";
2520 (define_insn "addqi3"
2521 [(set (match_operand:QI 0 "general_operand" "=m,d")
2522 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2523 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2528 if (GET_CODE (operands[2]) == CONST_INT)
2530 if (INTVAL (operands[2]) >= 128)
2531 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2533 if (INTVAL (operands[2]) > 0
2534 && INTVAL (operands[2]) <= 8)
2535 return \"addq%.b %2,%0\";
2536 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2538 operands[2] = GEN_INT (- INTVAL (operands[2]));
2539 return \"subq%.b %2,%0\";
2543 return \"add%.b %2,%0\";
2547 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2548 (plus:QI (match_dup 0)
2549 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2554 if (GET_CODE (operands[1]) == CONST_INT)
2556 if (INTVAL (operands[1]) >= 128)
2557 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2559 if (INTVAL (operands[1]) > 0
2560 && INTVAL (operands[1]) <= 8)
2561 return \"addq%.b %1,%0\";
2562 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2564 operands[1] = GEN_INT (- INTVAL (operands[1]));
2565 return \"subq%.b %1,%0\";
2569 return \"add%.b %1,%0\";
2573 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2574 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2580 if (GET_CODE (operands[1]) == CONST_INT)
2582 if (INTVAL (operands[1]) >= 128)
2583 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2585 if (INTVAL (operands[1]) > 0
2586 && INTVAL (operands[1]) <= 8)
2587 return \"addq%.b %1,%0\";
2588 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2590 operands[1] = GEN_INT (- INTVAL (operands[1]));
2591 return \"subq%.b %1,%0\";
2595 return \"add%.b %1,%0\";
2598 (define_expand "adddf3"
2599 [(set (match_operand:DF 0 "general_operand" "")
2600 (plus:DF (match_operand:DF 1 "general_operand" "")
2601 (match_operand:DF 2 "general_operand" "")))]
2602 "TARGET_68881 || TARGET_FPA"
2606 [(set (match_operand:DF 0 "general_operand" "=x,y")
2607 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2608 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2612 if (rtx_equal_p (operands[0], operands[1]))
2613 return \"fpadd%.d %y2,%0\";
2614 if (rtx_equal_p (operands[0], operands[2]))
2615 return \"fpadd%.d %y1,%0\";
2616 if (which_alternative == 0)
2617 return \"fpadd3%.d %w2,%w1,%0\";
2618 return \"fpadd3%.d %x2,%x1,%0\";
2622 [(set (match_operand:DF 0 "general_operand" "=f")
2623 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2624 (match_operand:DF 1 "general_operand" "0")))]
2629 [(set (match_operand:DF 0 "general_operand" "=f")
2630 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2631 (match_operand:DF 1 "general_operand" "0")))]
2636 [(set (match_operand:DF 0 "general_operand" "=f")
2637 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2638 (match_operand:DF 1 "general_operand" "0")))]
2643 [(set (match_operand:DF 0 "general_operand" "=f")
2644 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2645 (match_operand:DF 2 "general_operand" "fmG")))]
2649 if (REG_P (operands[2]))
2650 return \"f%&add%.x %2,%0\";
2651 return \"f%&add%.d %f2,%0\";
2654 (define_expand "addsf3"
2655 [(set (match_operand:SF 0 "general_operand" "")
2656 (plus:SF (match_operand:SF 1 "general_operand" "")
2657 (match_operand:SF 2 "general_operand" "")))]
2658 "TARGET_68881 || TARGET_FPA"
2662 [(set (match_operand:SF 0 "general_operand" "=x,y")
2663 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2664 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2668 if (rtx_equal_p (operands[0], operands[1]))
2669 return \"fpadd%.s %w2,%0\";
2670 if (rtx_equal_p (operands[0], operands[2]))
2671 return \"fpadd%.s %w1,%0\";
2672 if (which_alternative == 0)
2673 return \"fpadd3%.s %w2,%w1,%0\";
2674 return \"fpadd3%.s %2,%1,%0\";
2678 [(set (match_operand:SF 0 "general_operand" "=f")
2679 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2680 (match_operand:SF 1 "general_operand" "0")))]
2685 [(set (match_operand:SF 0 "general_operand" "=f")
2686 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2687 (match_operand:SF 1 "general_operand" "0")))]
2692 [(set (match_operand:SF 0 "general_operand" "=f")
2693 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2694 (match_operand:SF 1 "general_operand" "0")))]
2699 [(set (match_operand:SF 0 "general_operand" "=f")
2700 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2701 (match_operand:SF 2 "general_operand" "fdmF")))]
2705 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2706 return \"f%$add%.x %2,%0\";
2707 return \"f%$add%.s %f2,%0\";
2710 ;; subtract instructions
2712 (define_insn "subdi_sexthishl32"
2713 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2714 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2715 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2717 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2722 if (ADDRESS_REG_P (operands[0]))
2723 return \"sub%.w %2,%0\";
2724 else if (ADDRESS_REG_P (operands[3]))
2725 return \"move%.w %2,%3\;sub%.l %3,%0\";
2727 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2730 (define_insn "subdi_dishl32"
2731 [(set (match_operand:DI 0 "general_operand" "+ro")
2732 (minus:DI (match_dup 0)
2733 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2739 if (GET_CODE (operands[1]) == REG)
2740 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2742 operands[1] = adj_offsettable_operand (operands[1], 4);
2743 return \"sub%.l %1,%0\";
2746 (define_insn "subdi3"
2747 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2748 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2749 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2750 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2754 if (DATA_REG_P (operands[0]))
2756 if (DATA_REG_P (operands[2]))
2757 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2758 else if (GET_CODE (operands[2]) == MEM
2759 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2761 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2768 if (GET_CODE (operands[2]) == REG)
2770 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2773 else if (CONSTANT_P (operands[2]))
2774 split_double (operands[2], &high, &low);
2777 low = adj_offsettable_operand (operands[2], 4);
2781 operands[1] = low, operands[2] = high;
2782 xoperands[0] = operands[3];
2783 if (GET_CODE (operands[1]) == CONST_INT
2784 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2785 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2787 xoperands[1] = operands[2];
2789 output_asm_insn (output_move_simode (xoperands), xoperands);
2790 if (GET_CODE (operands[1]) == CONST_INT)
2792 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2795 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2797 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2800 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2802 operands[1] = GEN_INT (-INTVAL (operands[1]));
2804 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2806 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2810 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2813 else if (GET_CODE (operands[0]) == MEM)
2815 if (GET_CODE (operands[2]) == MEM
2816 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2817 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2819 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2822 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2823 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2825 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2827 operands[1] = XEXP(operands[0], 0);
2828 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2832 operands[1] = adj_offsettable_operand (operands[0], 4);
2833 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2840 (define_insn "subsi3"
2841 [(set (match_operand:SI 0 "general_operand" "=m,d,a")
2842 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2843 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2848 [(set (match_operand:SI 0 "general_operand" "=a")
2849 (minus:SI (match_operand:SI 1 "general_operand" "0")
2851 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2855 (define_insn "subhi3"
2856 [(set (match_operand:HI 0 "general_operand" "=m,r")
2857 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2858 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2863 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2864 (minus:HI (match_dup 0)
2865 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2869 (define_insn "subqi3"
2870 [(set (match_operand:QI 0 "general_operand" "=m,d")
2871 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2872 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2877 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2878 (minus:QI (match_dup 0)
2879 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2883 (define_expand "subdf3"
2884 [(set (match_operand:DF 0 "general_operand" "")
2885 (minus:DF (match_operand:DF 1 "general_operand" "")
2886 (match_operand:DF 2 "general_operand" "")))]
2887 "TARGET_68881 || TARGET_FPA"
2891 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2892 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2893 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2897 if (rtx_equal_p (operands[0], operands[2]))
2898 return \"fprsub%.d %y1,%0\";
2899 if (rtx_equal_p (operands[0], operands[1]))
2900 return \"fpsub%.d %y2,%0\";
2901 if (which_alternative == 0)
2902 return \"fpsub3%.d %w2,%w1,%0\";
2903 return \"fpsub3%.d %x2,%x1,%0\";
2907 [(set (match_operand:DF 0 "general_operand" "=f")
2908 (minus:DF (match_operand:DF 1 "general_operand" "0")
2909 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2914 [(set (match_operand:DF 0 "general_operand" "=f")
2915 (minus:DF (match_operand:DF 1 "general_operand" "0")
2916 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2921 [(set (match_operand:DF 0 "general_operand" "=f")
2922 (minus:DF (match_operand:DF 1 "general_operand" "0")
2923 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2928 [(set (match_operand:DF 0 "general_operand" "=f")
2929 (minus:DF (match_operand:DF 1 "general_operand" "0")
2930 (match_operand:DF 2 "general_operand" "fmG")))]
2934 if (REG_P (operands[2]))
2935 return \"f%&sub%.x %2,%0\";
2936 return \"f%&sub%.d %f2,%0\";
2939 (define_expand "subsf3"
2940 [(set (match_operand:SF 0 "general_operand" "")
2941 (minus:SF (match_operand:SF 1 "general_operand" "")
2942 (match_operand:SF 2 "general_operand" "")))]
2943 "TARGET_68881 || TARGET_FPA"
2947 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2948 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2949 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2953 if (rtx_equal_p (operands[0], operands[2]))
2954 return \"fprsub%.s %w1,%0\";
2955 if (rtx_equal_p (operands[0], operands[1]))
2956 return \"fpsub%.s %w2,%0\";
2957 if (which_alternative == 0)
2958 return \"fpsub3%.s %w2,%w1,%0\";
2959 return \"fpsub3%.s %2,%1,%0\";
2963 [(set (match_operand:SF 0 "general_operand" "=f")
2964 (minus:SF (match_operand:SF 1 "general_operand" "0")
2965 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2970 [(set (match_operand:SF 0 "general_operand" "=f")
2971 (minus:SF (match_operand:SF 1 "general_operand" "0")
2972 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2977 [(set (match_operand:SF 0 "general_operand" "=f")
2978 (minus:SF (match_operand:SF 1 "general_operand" "0")
2979 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2984 [(set (match_operand:SF 0 "general_operand" "=f")
2985 (minus:SF (match_operand:SF 1 "general_operand" "0")
2986 (match_operand:SF 2 "general_operand" "fdmF")))]
2990 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2991 return \"f%$sub%.x %2,%0\";
2992 return \"f%$sub%.s %f2,%0\";
2995 ;; multiply instructions
2997 (define_insn "mulhi3"
2998 [(set (match_operand:HI 0 "general_operand" "=d")
2999 (mult:HI (match_operand:HI 1 "general_operand" "%0")
3000 (match_operand:HI 2 "general_src_operand" "dmSn")))]
3004 #if defined(MOTOROLA) && !defined(CRDS)
3005 return \"muls%.w %2,%0\";
3007 return \"muls %2,%0\";
3011 (define_insn "mulhisi3"
3012 [(set (match_operand:SI 0 "general_operand" "=d")
3013 (mult:SI (sign_extend:SI
3014 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3016 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3020 #if defined(MOTOROLA) && !defined(CRDS)
3021 return \"muls%.w %2,%0\";
3023 return \"muls %2,%0\";
3028 [(set (match_operand:SI 0 "general_operand" "=d")
3029 (mult:SI (sign_extend:SI
3030 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3031 (match_operand:SI 2 "const_int_operand" "n")))]
3032 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
3035 #if defined(MOTOROLA) && !defined(CRDS)
3036 return \"muls%.w %2,%0\";
3038 return \"muls %2,%0\";
3042 (define_expand "mulsi3"
3043 [(set (match_operand:SI 0 "general_operand" "")
3044 (mult:SI (match_operand:SI 1 "general_operand" "")
3045 (match_operand:SI 2 "general_operand" "")))]
3046 "TARGET_68020 || TARGET_5200"
3050 [(set (match_operand:SI 0 "general_operand" "=d")
3051 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3052 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
3058 [(set (match_operand:SI 0 "general_operand" "=d")
3059 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3060 (match_operand:SI 2 "general_operand" "d<Q>")))]
3064 (define_insn "umulhisi3"
3065 [(set (match_operand:SI 0 "general_operand" "=d")
3066 (mult:SI (zero_extend:SI
3067 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3069 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3073 #if defined(MOTOROLA) && !defined(CRDS)
3074 return \"mulu%.w %2,%0\";
3076 return \"mulu %2,%0\";
3081 [(set (match_operand:SI 0 "general_operand" "=d")
3082 (mult:SI (zero_extend:SI
3083 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3084 (match_operand:SI 2 "const_int_operand" "n")))]
3085 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3088 #if defined(MOTOROLA) && !defined(CRDS)
3089 return \"mulu%.w %2,%0\";
3091 return \"mulu %2,%0\";
3095 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3096 ;; proper matching constraint. This is because the matching is between
3097 ;; the high-numbered word of the DImode operand[0] and operand[1].
3098 (define_expand "umulsidi3"
3100 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3101 (mult:SI (match_operand:SI 1 "register_operand" "")
3102 (match_operand:SI 2 "nonimmediate_operand" "")))
3103 (set (subreg:SI (match_dup 0) 0)
3104 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3105 (zero_extend:DI (match_dup 2)))
3106 (const_int 32))))])]
3107 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3111 [(set (match_operand:SI 0 "register_operand" "=d")
3112 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3113 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3114 (set (match_operand:SI 3 "register_operand" "=d")
3115 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3116 (zero_extend:DI (match_dup 2)))
3118 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3121 ; Match immediate case. For 2.4 only match things < 2^31.
3122 ; It's tricky with larger values in these patterns since we need to match
3123 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3126 [(set (match_operand:SI 0 "register_operand" "=d")
3127 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3128 (match_operand:SI 2 "const_int_operand" "n")))
3129 (set (match_operand:SI 3 "register_operand" "=d")
3130 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3133 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3134 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3137 (define_expand "mulsidi3"
3139 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3140 (mult:SI (match_operand:SI 1 "register_operand" "")
3141 (match_operand:SI 2 "nonimmediate_operand" "")))
3142 (set (subreg:SI (match_dup 0) 0)
3143 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3144 (sign_extend:DI (match_dup 2)))
3145 (const_int 32))))])]
3146 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3150 [(set (match_operand:SI 0 "register_operand" "=d")
3151 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3152 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3153 (set (match_operand:SI 3 "register_operand" "=d")
3154 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3155 (sign_extend:DI (match_dup 2)))
3157 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3161 [(set (match_operand:SI 0 "register_operand" "=d")
3162 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3163 (match_operand:SI 2 "const_sint32_operand" "")))
3164 (set (match_operand:SI 3 "register_operand" "=d")
3165 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3168 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3171 (define_expand "umulsi3_highpart"
3173 [(set (match_operand:SI 0 "register_operand" "")
3176 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3177 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3179 (clobber (match_dup 3))])]
3180 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3183 operands[3] = gen_reg_rtx (SImode);
3184 if (GET_CODE (operands[2]) == CONST_INT
3185 || GET_CODE (operands[2]) == CONST_DOUBLE)
3187 if (! const_uint32_operand (operands[2], VOIDmode))
3189 /* We have to adjust the operand order for the matching constraints. */
3190 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3191 operands[1], operands[2]));
3197 [(set (match_operand:SI 0 "register_operand" "=d")
3200 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3201 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3203 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3204 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3207 (define_insn "const_umulsi3_highpart"
3208 [(set (match_operand:SI 0 "register_operand" "=d")
3211 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3212 (match_operand 3 "const_uint32_operand" ""))
3214 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3215 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3218 (define_expand "smulsi3_highpart"
3220 [(set (match_operand:SI 0 "register_operand" "")
3223 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3224 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3226 (clobber (match_dup 3))])]
3227 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3230 operands[3] = gen_reg_rtx (SImode);
3231 if (GET_CODE (operands[2]) == CONST_INT
3232 || GET_CODE (operands[2]) == CONST_DOUBLE)
3234 if (! const_sint32_operand (operands[2], VOIDmode))
3236 /* We have to adjust the operand order for the matching constraints. */
3237 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3238 operands[1], operands[2]));
3244 [(set (match_operand:SI 0 "register_operand" "=d")
3247 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3248 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3250 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3251 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3254 (define_insn "const_smulsi3_highpart"
3255 [(set (match_operand:SI 0 "register_operand" "=d")
3258 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3259 (match_operand 3 "const_sint32_operand" ""))
3261 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3262 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3265 (define_expand "muldf3"
3266 [(set (match_operand:DF 0 "general_operand" "")
3267 (mult:DF (match_operand:DF 1 "general_operand" "")
3268 (match_operand:DF 2 "general_operand" "")))]
3269 "TARGET_68881 || TARGET_FPA"
3273 [(set (match_operand:DF 0 "general_operand" "=x,y")
3274 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3275 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3279 if (rtx_equal_p (operands[1], operands[2]))
3280 return \"fpsqr%.d %y1,%0\";
3281 if (rtx_equal_p (operands[0], operands[1]))
3282 return \"fpmul%.d %y2,%0\";
3283 if (rtx_equal_p (operands[0], operands[2]))
3284 return \"fpmul%.d %y1,%0\";
3285 if (which_alternative == 0)
3286 return \"fpmul3%.d %w2,%w1,%0\";
3287 return \"fpmul3%.d %x2,%x1,%0\";
3291 [(set (match_operand:DF 0 "general_operand" "=f")
3292 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3293 (match_operand:DF 1 "general_operand" "0")))]
3298 [(set (match_operand:DF 0 "general_operand" "=f")
3299 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3300 (match_operand:DF 1 "general_operand" "0")))]
3305 [(set (match_operand:DF 0 "general_operand" "=f")
3306 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3307 (match_operand:DF 1 "general_operand" "0")))]
3312 [(set (match_operand:DF 0 "general_operand" "=f")
3313 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3314 (match_operand:DF 2 "general_operand" "fmG")))]
3318 if (GET_CODE (operands[2]) == CONST_DOUBLE
3319 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3321 int i = floating_exact_log2 (operands[2]);
3322 operands[2] = GEN_INT (i);
3323 return \"fscale%.l %2,%0\";
3325 if (REG_P (operands[2]))
3326 return \"f%&mul%.x %2,%0\";
3327 return \"f%&mul%.d %f2,%0\";
3330 (define_expand "mulsf3"
3331 [(set (match_operand:SF 0 "general_operand" "")
3332 (mult:SF (match_operand:SF 1 "general_operand" "")
3333 (match_operand:SF 2 "general_operand" "")))]
3334 "TARGET_68881 || TARGET_FPA"
3338 [(set (match_operand:SF 0 "general_operand" "=x,y")
3339 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3340 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3344 if (rtx_equal_p (operands[1], operands[2]))
3345 return \"fpsqr%.s %w1,%0\";
3346 if (rtx_equal_p (operands[0], operands[1]))
3347 return \"fpmul%.s %w2,%0\";
3348 if (rtx_equal_p (operands[0], operands[2]))
3349 return \"fpmul%.s %w1,%0\";
3350 if (which_alternative == 0)
3351 return \"fpmul3%.s %w2,%w1,%0\";
3352 return \"fpmul3%.s %2,%1,%0\";
3356 [(set (match_operand:SF 0 "general_operand" "=f")
3357 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3358 (match_operand:SF 1 "general_operand" "0")))]
3362 return (TARGET_68040_ONLY
3363 ? \"fsmul%.l %2,%0\"
3364 : \"fsglmul%.l %2,%0\");
3368 [(set (match_operand:SF 0 "general_operand" "=f")
3369 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3370 (match_operand:SF 1 "general_operand" "0")))]
3374 return (TARGET_68040_ONLY
3375 ? \"fsmul%.w %2,%0\"
3376 : \"fsglmul%.w %2,%0\");
3380 [(set (match_operand:SF 0 "general_operand" "=f")
3381 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3382 (match_operand:SF 1 "general_operand" "0")))]
3386 return (TARGET_68040_ONLY
3387 ? \"fsmul%.b %2,%0\"
3388 : \"fsglmul%.b %2,%0\");
3392 [(set (match_operand:SF 0 "general_operand" "=f")
3393 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3394 (match_operand:SF 2 "general_operand" "fdmF")))]
3398 #ifdef FSGLMUL_USE_S
3399 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3400 return (TARGET_68040_ONLY
3401 ? \"fsmul%.s %2,%0\"
3402 : \"fsglmul%.s %2,%0\");
3404 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3405 return (TARGET_68040_ONLY
3406 ? \"fsmul%.x %2,%0\"
3407 : \"fsglmul%.x %2,%0\");
3409 return (TARGET_68040_ONLY
3410 ? \"fsmul%.s %f2,%0\"
3411 : \"fsglmul%.s %f2,%0\");
3414 ;; divide instructions
3416 (define_expand "divdf3"
3417 [(set (match_operand:DF 0 "general_operand" "")
3418 (div:DF (match_operand:DF 1 "general_operand" "")
3419 (match_operand:DF 2 "general_operand" "")))]
3420 "TARGET_68881 || TARGET_FPA"
3424 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3425 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3426 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3430 if (rtx_equal_p (operands[0], operands[2]))
3431 return \"fprdiv%.d %y1,%0\";
3432 if (rtx_equal_p (operands[0], operands[1]))
3433 return \"fpdiv%.d %y2,%0\";
3434 if (which_alternative == 0)
3435 return \"fpdiv3%.d %w2,%w1,%0\";
3436 return \"fpdiv3%.d %x2,%x1,%x0\";
3440 [(set (match_operand:DF 0 "general_operand" "=f")
3441 (div:DF (match_operand:DF 1 "general_operand" "0")
3442 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3447 [(set (match_operand:DF 0 "general_operand" "=f")
3448 (div:DF (match_operand:DF 1 "general_operand" "0")
3449 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3454 [(set (match_operand:DF 0 "general_operand" "=f")
3455 (div:DF (match_operand:DF 1 "general_operand" "0")
3456 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3461 [(set (match_operand:DF 0 "general_operand" "=f")
3462 (div:DF (match_operand:DF 1 "general_operand" "0")
3463 (match_operand:DF 2 "general_operand" "fmG")))]
3467 if (REG_P (operands[2]))
3468 return \"f%&div%.x %2,%0\";
3469 return \"f%&div%.d %f2,%0\";
3472 (define_expand "divsf3"
3473 [(set (match_operand:SF 0 "general_operand" "")
3474 (div:SF (match_operand:SF 1 "general_operand" "")
3475 (match_operand:SF 2 "general_operand" "")))]
3476 "TARGET_68881 || TARGET_FPA"
3480 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3481 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3482 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3486 if (rtx_equal_p (operands[0], operands[1]))
3487 return \"fpdiv%.s %w2,%0\";
3488 if (rtx_equal_p (operands[0], operands[2]))
3489 return \"fprdiv%.s %w1,%0\";
3490 if (which_alternative == 0)
3491 return \"fpdiv3%.s %w2,%w1,%0\";
3492 return \"fpdiv3%.s %2,%1,%0\";
3496 [(set (match_operand:SF 0 "general_operand" "=f")
3497 (div:SF (match_operand:SF 1 "general_operand" "0")
3498 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3502 return (TARGET_68040_ONLY
3503 ? \"fsdiv%.l %2,%0\"
3504 : \"fsgldiv%.l %2,%0\");
3508 [(set (match_operand:SF 0 "general_operand" "=f")
3509 (div:SF (match_operand:SF 1 "general_operand" "0")
3510 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3514 return (TARGET_68040_ONLY
3515 ? \"fsdiv%.w %2,%0\"
3516 : \"fsgldiv%.w %2,%0\");
3520 [(set (match_operand:SF 0 "general_operand" "=f")
3521 (div:SF (match_operand:SF 1 "general_operand" "0")
3522 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3526 return (TARGET_68040_ONLY
3527 ? \"fsdiv%.b %2,%0\"
3528 : \"fsgldiv%.b %2,%0\");
3532 [(set (match_operand:SF 0 "general_operand" "=f")
3533 (div:SF (match_operand:SF 1 "general_operand" "0")
3534 (match_operand:SF 2 "general_operand" "fdmF")))]
3538 #ifdef FSGLDIV_USE_S
3539 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3540 return (TARGET_68040_ONLY
3541 ? \"fsdiv%.s %2,%0\"
3542 : \"fsgldiv%.s %2,%0\");
3544 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3545 return (TARGET_68040_ONLY
3546 ? \"fsdiv%.x %2,%0\"
3547 : \"fsgldiv%.x %2,%0\");
3549 return (TARGET_68040_ONLY
3550 ? \"fsdiv%.s %f2,%0\"
3551 : \"fsgldiv%.s %f2,%0\");
3554 ;; Remainder instructions.
3556 (define_insn "divmodsi4"
3557 [(set (match_operand:SI 0 "general_operand" "=d")
3558 (div:SI (match_operand:SI 1 "general_operand" "0")
3559 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3560 (set (match_operand:SI 3 "general_operand" "=d")
3561 (mod:SI (match_dup 1) (match_dup 2)))]
3562 "TARGET_68020 && !TARGET_5200"
3565 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3566 return \"divs%.l %2,%0\";
3568 return \"divsl%.l %2,%3:%0\";
3571 (define_insn "udivmodsi4"
3572 [(set (match_operand:SI 0 "general_operand" "=d")
3573 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3574 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3575 (set (match_operand:SI 3 "general_operand" "=d")
3576 (umod:SI (match_dup 1) (match_dup 2)))]
3577 "TARGET_68020 && !TARGET_5200"
3580 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3581 return \"divu%.l %2,%0\";
3583 return \"divul%.l %2,%3:%0\";
3586 (define_insn "divmodhi4"
3587 [(set (match_operand:HI 0 "general_operand" "=d")
3588 (div:HI (match_operand:HI 1 "general_operand" "0")
3589 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3590 (set (match_operand:HI 3 "general_operand" "=d")
3591 (mod:HI (match_dup 1) (match_dup 2)))]
3596 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3598 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3600 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3603 return \"move%.l %0,%3\;swap %3\";
3609 (define_insn "udivmodhi4"
3610 [(set (match_operand:HI 0 "general_operand" "=d")
3611 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3612 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3613 (set (match_operand:HI 3 "general_operand" "=d")
3614 (umod:HI (match_dup 1) (match_dup 2)))]
3619 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3621 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3623 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3626 return \"move%.l %0,%3\;swap %3\";
3632 ;; logical-and instructions
3634 ;; "anddi3" is mainly here to help combine().
3635 (define_insn "anddi3"
3636 [(set (match_operand:DI 0 "general_operand" "=o,d")
3637 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3638 (match_operand:DI 2 "general_operand" "dn,don")))]
3643 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3644 if (CONSTANT_P (operands[2]))
3648 split_double (operands[2], &hi, &lo);
3650 switch (INTVAL (hi))
3653 output_asm_insn (\"clr%.l %0\", operands);
3661 xoperands[0] = operands[0];
3663 output_asm_insn (output_andsi3 (xoperands), xoperands);
3666 if (GET_CODE (operands[0]) == REG)
3667 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3669 operands[0] = adj_offsettable_operand (operands[0], 4);
3670 switch (INTVAL (lo))
3673 output_asm_insn (\"clr%.l %0\", operands);
3681 xoperands[0] = operands[0];
3683 output_asm_insn (output_andsi3 (xoperands), xoperands);
3688 if (GET_CODE (operands[0]) != REG)
3690 operands[1] = adj_offsettable_operand (operands[0], 4);
3691 return \"and%.l %2,%0\;and%.l %R2,%1\";
3693 if (GET_CODE (operands[2]) != REG)
3695 operands[1] = adj_offsettable_operand (operands[2], 4);
3696 return \"and%.l %2,%0\;and%.l %1,%R0\";
3698 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3701 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3702 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3703 ;; can't allocate pseudos into it.
3705 (define_expand "andsi3"
3706 [(set (match_operand:SI 0 "not_sp_operand" "")
3707 (and:SI (match_operand:SI 1 "general_operand" "")
3708 (match_operand:SI 2 "general_src_operand" "")))]
3712 (define_insn "andsi3_internal"
3713 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3714 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3715 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3719 return output_andsi3 (operands);
3722 (define_insn "andsi3_5200"
3723 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3724 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3725 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3729 (define_insn "andhi3"
3730 [(set (match_operand:HI 0 "general_operand" "=m,d")
3731 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3732 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3737 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3738 (and:HI (match_dup 0)
3739 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3744 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3745 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3750 (define_insn "andqi3"
3751 [(set (match_operand:QI 0 "general_operand" "=m,d")
3752 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3753 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3758 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3759 (and:QI (match_dup 0)
3760 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3765 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3766 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3771 ;; inclusive-or instructions
3773 (define_insn "iordi_zext"
3774 [(set (match_operand:DI 0 "general_operand" "=o,d")
3775 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3776 (match_operand:DI 2 "general_operand" "0,0")))]
3783 if (GET_CODE (operands[0]) == REG)
3784 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3786 operands[0] = adj_offsettable_operand (operands[0], 4);
3787 if (GET_MODE (operands[1]) == SImode)
3788 return \"or%.l %1,%0\";
3789 byte_mode = (GET_MODE (operands[1]) == QImode);
3790 if (GET_CODE (operands[0]) == MEM)
3791 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3793 return \"or%.b %1,%0\";
3795 return \"or%.w %1,%0\";
3798 ;; "iordi3" is mainly here to help combine().
3799 (define_insn "iordi3"
3800 [(set (match_operand:DI 0 "general_operand" "=o,d")
3801 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3802 (match_operand:DI 2 "general_operand" "dn,don")))]
3807 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3808 if (CONSTANT_P (operands[2]))
3812 split_double (operands[2], &hi, &lo);
3814 switch (INTVAL (hi))
3819 /* FIXME : a scratch register would be welcome here if operand[0]
3820 is not a register */
3821 output_asm_insn (\"move%.l %#-1,%0\", operands);
3827 xoperands[0] = operands[0];
3829 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3832 if (GET_CODE (operands[0]) == REG)
3833 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3835 operands[0] = adj_offsettable_operand (operands[0], 4);
3836 switch (INTVAL (lo))
3841 /* FIXME : a scratch register would be welcome here if operand[0]
3842 is not a register */
3843 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3849 xoperands[0] = operands[0];
3851 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3856 if (GET_CODE (operands[0]) != REG)
3858 operands[1] = adj_offsettable_operand (operands[0], 4);
3859 return \"or%.l %2,%0\;or%.l %R2,%1\";
3861 if (GET_CODE (operands[2]) != REG)
3863 operands[1] = adj_offsettable_operand (operands[2], 4);
3864 return \"or%.l %2,%0\;or%.l %1,%R0\";
3866 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3869 (define_expand "iorsi3"
3870 [(set (match_operand:SI 0 "general_operand" "")
3871 (ior:SI (match_operand:SI 1 "general_operand" "")
3872 (match_operand:SI 2 "general_src_operand" "")))]
3876 (define_insn "iorsi3_internal"
3877 [(set (match_operand:SI 0 "general_operand" "=m,d")
3878 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3879 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3883 return output_iorsi3 (operands);
3886 (define_insn "iorsi3_5200"
3887 [(set (match_operand:SI 0 "general_operand" "=m,d")
3888 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3889 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3893 (define_insn "iorhi3"
3894 [(set (match_operand:HI 0 "general_operand" "=m,d")
3895 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3896 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3901 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3902 (ior:HI (match_dup 0)
3903 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3908 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3909 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3914 (define_insn "iorqi3"
3915 [(set (match_operand:QI 0 "general_operand" "=m,d")
3916 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3917 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3922 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3923 (ior:QI (match_dup 0)
3924 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3929 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3930 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3935 ;; On all 68k models, this makes faster code in a special case.
3936 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3938 (define_insn "iorsi_zexthi_ashl16"
3939 [(set (match_operand:SI 0 "general_operand" "=&d")
3940 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3941 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3947 if (GET_CODE (operands[2]) != REG)
3948 operands[2] = adj_offsettable_operand (operands[2], 2);
3949 if (GET_CODE (operands[2]) != REG
3950 || REGNO (operands[2]) != REGNO (operands[0]))
3951 output_asm_insn (\"move%.w %2,%0\", operands);
3952 return \"swap %0\;mov%.w %1,%0\";
3955 (define_insn "iorsi_zext"
3956 [(set (match_operand:SI 0 "general_operand" "=o,d")
3957 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3958 (match_operand:SI 2 "general_operand" "0,0")))]
3965 byte_mode = (GET_MODE (operands[1]) == QImode);
3966 if (GET_CODE (operands[0]) == MEM)
3967 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3969 return \"or%.b %1,%0\";
3971 return \"or%.w %1,%0\";
3976 ;; "xordi3" is mainly here to help combine().
3977 (define_insn "xordi3"
3978 [(set (match_operand:DI 0 "general_operand" "=od")
3979 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3980 (match_operand:DI 2 "general_operand" "dn")))]
3985 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3987 if (CONSTANT_P (operands[2]))
3991 split_double (operands[2], &hi, &lo);
3993 switch (INTVAL (hi))
3998 output_asm_insn (\"not%.l %0\", operands);
4001 /* FIXME : a scratch register would be welcome here if
4002 -128 <= INTVAL (hi) < -1 */
4006 xoperands[0] = operands[0];
4008 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4011 if (GET_CODE (operands[0]) == REG)
4012 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4014 operands[0] = adj_offsettable_operand (operands[0], 4);
4015 switch (INTVAL (lo))
4020 output_asm_insn (\"not%.l %0\", operands);
4023 /* FIXME : a scratch register would be welcome here if
4024 -128 <= INTVAL (lo) < -1 */
4026 /* FIXME : this should be merged with xorsi3 */
4030 xoperands[0] = operands[0];
4032 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4037 if (GET_CODE (operands[0]) != REG)
4039 operands[1] = adj_offsettable_operand (operands[0], 4);
4040 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4042 if (GET_CODE (operands[2]) != REG)
4044 operands[1] = adj_offsettable_operand (operands[2], 4);
4045 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4047 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4050 (define_expand "xorsi3"
4051 [(set (match_operand:SI 0 "general_operand" "")
4052 (xor:SI (match_operand:SI 1 "general_operand" "")
4053 (match_operand:SI 2 "general_operand" "")))]
4057 (define_insn "xorsi3_internal"
4058 [(set (match_operand:SI 0 "general_operand" "=do,m")
4059 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4060 (match_operand:SI 2 "general_operand" "di,dKT")))]
4065 return output_xorsi3 (operands);
4068 (define_insn "xorsi3_5200"
4069 [(set (match_operand:SI 0 "general_operand" "=dm,d")
4070 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4071 (match_operand:SI 2 "general_operand" "d,Ks")))]
4075 (define_insn "xorhi3"
4076 [(set (match_operand:HI 0 "general_operand" "=dm")
4077 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4078 (match_operand:HI 2 "general_operand" "dn")))]
4083 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4084 (xor:HI (match_dup 0)
4085 (match_operand:HI 1 "general_operand" "dn")))]
4090 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4091 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4096 (define_insn "xorqi3"
4097 [(set (match_operand:QI 0 "general_operand" "=dm")
4098 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4099 (match_operand:QI 2 "general_operand" "dn")))]
4104 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4105 (xor:QI (match_dup 0)
4106 (match_operand:QI 1 "general_operand" "dn")))]
4111 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4112 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4117 ;; negation instructions
4119 (define_expand "negdi2"
4120 [(set (match_operand:DI 0 "general_operand" "")
4121 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4126 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4128 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4132 (define_insn "negdi2_internal"
4133 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4134 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4138 if (which_alternative == 0)
4139 return \"neg%.l %0\;negx%.l %0\";
4140 if (GET_CODE (operands[0]) == REG)
4141 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4143 operands[1] = adj_offsettable_operand (operands[0], 4);
4144 if (ADDRESS_REG_P (operands[0]))
4145 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4147 return \"neg%.l %1\;negx%.l %0\";
4150 (define_insn "negdi2_5200"
4151 [(set (match_operand:DI 0 "general_operand" "=d")
4152 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4156 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4157 return \"neg%.l %1\;negx%.l %0\";
4160 (define_expand "negsi2"
4161 [(set (match_operand:SI 0 "general_operand" "")
4162 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4167 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4169 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4173 (define_insn "negsi2_internal"
4174 [(set (match_operand:SI 0 "general_operand" "=dm")
4175 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4179 (define_insn "negsi2_5200"
4180 [(set (match_operand:SI 0 "general_operand" "=d")
4181 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4185 (define_insn "neghi2"
4186 [(set (match_operand:HI 0 "general_operand" "=dm")
4187 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4192 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4193 (neg:HI (match_dup 0)))]
4197 (define_insn "negqi2"
4198 [(set (match_operand:QI 0 "general_operand" "=dm")
4199 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4204 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4205 (neg:QI (match_dup 0)))]
4209 ;; If using software floating point, just flip the sign bit.
4211 (define_expand "negsf2"
4212 [(set (match_operand:SF 0 "general_operand" "")
4213 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4217 if (!TARGET_FPA && !TARGET_68881)
4222 target = operand_subword_force (operands[0], 0, SFmode);
4223 result = expand_binop (SImode, xor_optab,
4224 operand_subword_force (operands[1], 0, SFmode),
4225 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4229 if (result != target)
4230 emit_move_insn (result, target);
4232 /* Make a place for REG_EQUAL. */
4233 emit_move_insn (operands[0], operands[0]);
4239 [(set (match_operand:SF 0 "general_operand" "=x,y")
4240 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4245 [(set (match_operand:SF 0 "general_operand" "=f,d")
4246 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4250 if (DATA_REG_P (operands[0]))
4252 operands[1] = GEN_INT (31);
4253 return \"bchg %1,%0\";
4255 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4256 return \"f%$neg%.x %1,%0\";
4257 return \"f%$neg%.s %f1,%0\";
4260 (define_expand "negdf2"
4261 [(set (match_operand:DF 0 "general_operand" "")
4262 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4266 if (!TARGET_FPA && !TARGET_68881)
4273 target = operand_subword (operands[0], 0, 1, DFmode);
4274 result = expand_binop (SImode, xor_optab,
4275 operand_subword_force (operands[1], 0, DFmode),
4276 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4280 if (result != target)
4281 emit_move_insn (result, target);
4283 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4284 operand_subword_force (operands[1], 1, DFmode));
4286 insns = get_insns ();
4289 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4295 [(set (match_operand:DF 0 "general_operand" "=x,y")
4296 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4301 [(set (match_operand:DF 0 "general_operand" "=f,d")
4302 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4306 if (DATA_REG_P (operands[0]))
4308 operands[1] = GEN_INT (31);
4309 return \"bchg %1,%0\";
4311 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4312 return \"f%&neg%.x %1,%0\";
4313 return \"f%&neg%.d %f1,%0\";
4316 ;; Sqrt instruction for the 68881
4318 (define_insn "sqrtsf2"
4319 [(set (match_operand:SF 0 "general_operand" "=f")
4320 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4324 if (FP_REG_P (operands[1]))
4325 return \"f%$sqrt%.x %1,%0\";
4327 return \"f%$sqrt%.s %1,%0\";
4330 (define_insn "sqrtdf2"
4331 [(set (match_operand:DF 0 "general_operand" "=f")
4332 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4336 if (FP_REG_P (operands[1]))
4337 return \"f%&sqrt%.x %1,%0\";
4339 return \"f%&sqrt%.d %1,%0\";
4342 ;; Absolute value instructions
4343 ;; If using software floating point, just zero the sign bit.
4345 (define_expand "abssf2"
4346 [(set (match_operand:SF 0 "general_operand" "")
4347 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4351 if (!TARGET_FPA && !TARGET_68881)
4356 target = operand_subword_force (operands[0], 0, SFmode);
4357 result = expand_binop (SImode, and_optab,
4358 operand_subword_force (operands[1], 0, SFmode),
4359 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4363 if (result != target)
4364 emit_move_insn (result, target);
4366 /* Make a place for REG_EQUAL. */
4367 emit_move_insn (operands[0], operands[0]);
4373 [(set (match_operand:SF 0 "general_operand" "=x,y")
4374 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4379 [(set (match_operand:SF 0 "general_operand" "=f")
4380 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4384 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4385 return \"f%$abs%.x %1,%0\";
4386 return \"f%$abs%.s %f1,%0\";
4389 (define_expand "absdf2"
4390 [(set (match_operand:DF 0 "general_operand" "")
4391 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4395 if (!TARGET_FPA && !TARGET_68881)
4402 target = operand_subword (operands[0], 0, 1, DFmode);
4403 result = expand_binop (SImode, and_optab,
4404 operand_subword_force (operands[1], 0, DFmode),
4405 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4409 if (result != target)
4410 emit_move_insn (result, target);
4412 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4413 operand_subword_force (operands[1], 1, DFmode));
4415 insns = get_insns ();
4418 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4424 [(set (match_operand:DF 0 "general_operand" "=x,y")
4425 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4430 [(set (match_operand:DF 0 "general_operand" "=f")
4431 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4435 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4436 return \"f%&abs%.x %1,%0\";
4437 return \"f%&abs%.d %f1,%0\";
4440 ;; one complement instructions
4442 ;; "one_cmpldi2" is mainly here to help combine().
4443 (define_insn "one_cmpldi2"
4444 [(set (match_operand:DI 0 "general_operand" "=dm")
4445 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4450 if (GET_CODE (operands[0]) == REG)
4451 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4452 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4453 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4454 operands[1] = operands[0];
4456 operands[1] = adj_offsettable_operand (operands[0], 4);
4457 return \"not%.l %1\;not%.l %0\";
4460 (define_expand "one_cmplsi2"
4461 [(set (match_operand:SI 0 "general_operand" "")
4462 (not:SI (match_operand:SI 1 "general_operand" "")))]
4467 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4469 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4473 (define_insn "one_cmplsi2_internal"
4474 [(set (match_operand:SI 0 "general_operand" "=dm")
4475 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4479 (define_insn "one_cmplsi2_5200"
4480 [(set (match_operand:SI 0 "general_operand" "=d")
4481 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4485 (define_insn "one_cmplhi2"
4486 [(set (match_operand:HI 0 "general_operand" "=dm")
4487 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4492 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4493 (not:HI (match_dup 0)))]
4497 (define_insn "one_cmplqi2"
4498 [(set (match_operand:QI 0 "general_operand" "=dm")
4499 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4504 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4505 (not:QI (match_dup 0)))]
4509 ;; arithmetic shift instructions
4510 ;; We don't need the shift memory by 1 bit instruction
4512 (define_insn "ashldi_extsi"
4513 [(set (match_operand:DI 0 "general_operand" "=ro")
4515 (match_operator:DI 2 "extend_operator"
4516 [(match_operand:SI 1 "general_operand" "rm")])
4522 if (GET_CODE (operands[0]) == REG)
4523 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4525 operands[2] = adj_offsettable_operand (operands[0], 4);
4526 if (ADDRESS_REG_P (operands[0]))
4527 return \"move%.l %1,%0\;sub%.l %2,%2\";
4529 return \"move%.l %1,%0\;clr%.l %2\";
4532 (define_insn "ashldi_sexthi"
4533 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4534 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4536 (clobber (match_scratch:SI 2 "=a,X"))]
4541 if (GET_CODE (operands[0]) == MEM)
4543 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4544 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4545 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4546 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4549 operands[3] = adj_offsettable_operand (operands[0], 4);
4550 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4553 else if (DATA_REG_P (operands[0]))
4554 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4556 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4559 (define_insn "ashldi_const32"
4560 [(set (match_operand:DI 0 "general_operand" "=rm")
4561 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4567 if (GET_CODE (operands[1]) == REG)
4568 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4570 operands[3] = adj_offsettable_operand (operands[1], 4);
4571 if (GET_CODE (operands[0]) == REG)
4572 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4573 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4574 return \"clr%.l %0\;move%.l %3,%0\";
4575 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4576 return \"move%.l %3,%0\;clr%.l %0\";
4578 operands[2] = adj_offsettable_operand (operands[0], 4);
4579 if (ADDRESS_REG_P (operands[2]))
4580 return \"move%.l %3,%0\;sub%.l %2,%2\";
4582 return \"move%.l %3,%0\;clr%.l %2\";
4585 ;; The predicate below must be general_operand, because ashldi3 allows that
4586 (define_insn "ashldi_const"
4587 [(set (match_operand:DI 0 "general_operand" "=d")
4588 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4589 (match_operand 2 "const_int_operand" "n")))]
4591 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4592 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4593 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4596 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4597 if (INTVAL (operands[2]) == 1)
4598 return \"add%.l %1,%1\;addx%.l %0,%0\";
4599 else if (INTVAL (operands[2]) == 8)
4600 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4601 else if (INTVAL (operands[2]) == 16)
4602 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4603 else if (INTVAL (operands[2]) == 48)
4604 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4605 else if (INTVAL (operands[2]) == 2)
4606 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4607 else if (INTVAL (operands[2]) == 3)
4608 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4609 else /* 32 < INTVAL (operands[2]) <= 63 */
4611 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4612 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4613 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4614 return \"mov%.l %1,%0\;moveq %#0,%1\";
4618 (define_expand "ashldi3"
4619 [(set (match_operand:DI 0 "general_operand" "")
4620 (ashift:DI (match_operand:DI 1 "general_operand" "")
4621 (match_operand 2 "const_int_operand" "")))]
4625 /* ??? This is a named pattern like this is not allowed to FAIL based
4627 if (GET_CODE (operands[2]) != CONST_INT
4628 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4629 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4630 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4634 ;; On most 68k models, this makes faster code in a special case.
4636 (define_insn "ashlsi_16"
4637 [(set (match_operand:SI 0 "register_operand" "=d")
4638 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4644 return \"swap %0\;clr%.w %0\";
4647 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4648 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4650 ;; On the 68000, this makes faster code in a special case.
4652 (define_insn "ashlsi_17_24"
4653 [(set (match_operand:SI 0 "register_operand" "=d")
4654 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4655 (match_operand:SI 2 "const_int_operand" "n")))]
4656 "(! TARGET_68020 && !TARGET_5200
4657 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4662 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4663 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4666 (define_insn "ashlsi3"
4667 [(set (match_operand:SI 0 "register_operand" "=d")
4668 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4669 (match_operand:SI 2 "general_operand" "dI")))]
4673 if (operands[2] == const1_rtx)
4675 cc_status.flags = CC_NO_OVERFLOW;
4676 return \"add%.l %0,%0\";
4678 return \"lsl%.l %2,%0\";
4681 (define_insn "ashlhi3"
4682 [(set (match_operand:HI 0 "register_operand" "=d")
4683 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4684 (match_operand:HI 2 "general_operand" "dI")))]
4689 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4690 (ashift:HI (match_dup 0)
4691 (match_operand:HI 1 "general_operand" "dI")))]
4695 (define_insn "ashlqi3"
4696 [(set (match_operand:QI 0 "register_operand" "=d")
4697 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4698 (match_operand:QI 2 "general_operand" "dI")))]
4703 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4704 (ashift:QI (match_dup 0)
4705 (match_operand:QI 1 "general_operand" "dI")))]
4709 ;; On most 68k models, this makes faster code in a special case.
4711 (define_insn "ashrsi_16"
4712 [(set (match_operand:SI 0 "register_operand" "=d")
4713 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4716 "swap %0\;ext%.l %0")
4718 ;; On the 68000, this makes faster code in a special case.
4721 [(set (match_operand:SI 0 "register_operand" "=d")
4722 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4723 (match_operand:SI 2 "const_int_operand" "n")))]
4724 "(! TARGET_68020 && !TARGET_5200
4725 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4728 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4729 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4732 (define_insn "subreghi1ashrdi_const32"
4733 [(set (match_operand:HI 0 "general_operand" "=rm")
4734 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4735 (const_int 32)) 1))]
4739 if (GET_CODE (operands[1]) != REG)
4740 operands[1] = adj_offsettable_operand (operands[1], 2);
4741 return \"move%.w %1,%0\";
4744 (define_insn "subregsi1ashrdi_const32"
4745 [(set (match_operand:SI 0 "general_operand" "=rm")
4746 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4747 (const_int 32)) 1))]
4751 return \"move%.l %1,%0\";
4754 (define_insn "ashrdi_const32"
4755 [(set (match_operand:DI 0 "register_operand" "=d")
4756 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4762 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4764 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4766 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4769 (define_insn "ashrdi_const32_mem"
4770 [(set (match_operand:DI 0 "general_operand" "=o,<")
4771 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4773 (clobber (match_scratch:SI 2 "=d,d"))]
4778 if (which_alternative == 1)
4779 operands[3] = operands[0];
4781 operands[3] = adj_offsettable_operand (operands[0], 4);
4783 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4785 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4788 ;; The predicate below must be general_operand, because ashrdi3 allows that
4789 (define_insn "ashrdi_const"
4790 [(set (match_operand:DI 0 "general_operand" "=d")
4791 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4792 (match_operand 2 "const_int_operand" "n")))]
4794 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4795 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4796 || INTVAL (operands[2]) == 31
4797 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4800 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4801 if (INTVAL (operands[2]) == 63)
4802 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4804 if (INTVAL (operands[2]) == 1)
4805 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4806 else if (INTVAL (operands[2]) == 8)
4807 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4808 else if (INTVAL (operands[2]) == 16)
4809 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4810 else if (INTVAL (operands[2]) == 48)
4811 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4812 else if (INTVAL (operands[2]) == 31)
4813 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4814 else if (INTVAL (operands[2]) == 2)
4815 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4816 else if (INTVAL (operands[2]) == 3)
4817 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4818 else /* 32 < INTVAL (operands[2]) <= 63 */
4820 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4821 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4822 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4823 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4824 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4825 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4829 (define_expand "ashrdi3"
4830 [(set (match_operand:DI 0 "general_operand" "")
4831 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4832 (match_operand 2 "const_int_operand" "")))]
4836 /* ??? This is a named pattern like this is not allowed to FAIL based
4838 if (GET_CODE (operands[2]) != CONST_INT
4839 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4840 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4841 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4845 ;; On all 68k models, this makes faster code in a special case.
4847 (define_insn "ashrsi_31"
4848 [(set (match_operand:SI 0 "register_operand" "=d")
4849 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4854 return \"add%.l %0,%0\;subx%.l %0,%0\";
4857 (define_insn "ashrsi3"
4858 [(set (match_operand:SI 0 "register_operand" "=d")
4859 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4860 (match_operand:SI 2 "general_operand" "dI")))]
4864 (define_insn "ashrhi3"
4865 [(set (match_operand:HI 0 "register_operand" "=d")
4866 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4867 (match_operand:HI 2 "general_operand" "dI")))]
4872 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4873 (ashiftrt:HI (match_dup 0)
4874 (match_operand:HI 1 "general_operand" "dI")))]
4878 (define_insn "ashrqi3"
4879 [(set (match_operand:QI 0 "register_operand" "=d")
4880 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4881 (match_operand:QI 2 "general_operand" "dI")))]
4886 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4887 (ashiftrt:QI (match_dup 0)
4888 (match_operand:QI 1 "general_operand" "dI")))]
4892 ;; logical shift instructions
4894 ;; commented out because of reload problems in 950612-1.c
4897 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4898 ;; (const_int 32)) 1))
4899 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4900 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4901 ;; (const_int 32)) 1))]
4905 ;; return \"move%.l %0,%1\";
4910 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4911 ;; (const_int 32)) 0))
4912 ;; (set (match_operand:DI 1 "general_operand" "=do")
4913 ;; (lshiftrt:DI (match_dup 0)
4914 ;; (const_int 32)))]
4918 ;; if (GET_CODE (operands[1]) == REG)
4919 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4921 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4922 ;; return \"move%.l %0,%2\;clr%.l %1\";
4925 (define_insn "subreg1lshrdi_const32"
4926 [(set (match_operand:SI 0 "general_operand" "=rm")
4927 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4928 (const_int 32)) 1))]
4932 return \"move%.l %1,%0\";
4935 (define_insn "lshrdi_const32"
4936 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4937 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4943 if (which_alternative == 1)
4944 return \"move%.l %1,%0\;clr%.l %0\";
4945 if (which_alternative == 2)
4946 return \"clr%.l %0\;move%.l %1,%0\";
4947 if (GET_CODE (operands[0]) == REG)
4948 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4950 operands[2] = adj_offsettable_operand (operands[0], 4);
4951 if (GET_CODE (operands[1]) == REG)
4952 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4954 operands[3] = adj_offsettable_operand (operands[1], 4);
4955 if (ADDRESS_REG_P (operands[0]))
4956 return \"move%.l %1,%2\;sub%.l %0,%0\";
4958 return \"move%.l %1,%2\;clr%.l %0\";
4961 ;; The predicate below must be general_operand, because lshrdi3 allows that
4962 (define_insn "lshrdi_const"
4963 [(set (match_operand:DI 0 "general_operand" "=d")
4964 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4965 (match_operand 2 "const_int_operand" "n")))]
4967 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4968 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4969 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4972 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4973 if (INTVAL (operands[2]) == 63)
4974 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4976 if (INTVAL (operands[2]) == 1)
4977 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4978 else if (INTVAL (operands[2]) == 8)
4979 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4980 else if (INTVAL (operands[2]) == 16)
4981 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4982 else if (INTVAL (operands[2]) == 48)
4983 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4984 else if (INTVAL (operands[2]) == 2)
4985 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4986 else if (INTVAL (operands[2]) == 3)
4987 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4988 else /* 32 < INTVAL (operands[2]) <= 63 */
4990 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4991 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4992 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4993 return \"mov%.l %0,%1\;moveq %#0,%0\";
4997 (define_expand "lshrdi3"
4998 [(set (match_operand:DI 0 "general_operand" "")
4999 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
5000 (match_operand 2 "const_int_operand" "")))]
5004 /* ??? This is a named pattern like this is not allowed to FAIL based
5006 if (GET_CODE (operands[2]) != CONST_INT
5007 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5008 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5009 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5013 ;; On all 68k models, this makes faster code in a special case.
5015 (define_insn "lshrsi_31"
5016 [(set (match_operand:SI 0 "register_operand" "=d")
5017 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5022 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
5025 ;; On most 68k models, this makes faster code in a special case.
5027 (define_insn "lshrsi_16"
5028 [(set (match_operand:SI 0 "register_operand" "=d")
5029 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5035 return \"clr%.w %0\;swap %0\";
5038 ;; On the 68000, this makes faster code in a special case.
5040 (define_insn "lshrsi_17_24"
5041 [(set (match_operand:SI 0 "register_operand" "=d")
5042 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5043 (match_operand:SI 2 "const_int_operand" "n")))]
5044 "(! TARGET_68020 && !TARGET_5200
5045 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
5048 /* I think lsr%.w sets the CC properly. */
5049 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5050 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5053 (define_insn "lshrsi3"
5054 [(set (match_operand:SI 0 "register_operand" "=d")
5055 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5056 (match_operand:SI 2 "general_operand" "dI")))]
5060 (define_insn "lshrhi3"
5061 [(set (match_operand:HI 0 "register_operand" "=d")
5062 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5063 (match_operand:HI 2 "general_operand" "dI")))]
5068 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5069 (lshiftrt:HI (match_dup 0)
5070 (match_operand:HI 1 "general_operand" "dI")))]
5074 (define_insn "lshrqi3"
5075 [(set (match_operand:QI 0 "register_operand" "=d")
5076 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5077 (match_operand:QI 2 "general_operand" "dI")))]
5082 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5083 (lshiftrt:QI (match_dup 0)
5084 (match_operand:QI 1 "general_operand" "dI")))]
5088 ;; rotate instructions
5090 (define_insn "rotlsi3"
5091 [(set (match_operand:SI 0 "register_operand" "=d")
5092 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5093 (match_operand:SI 2 "general_operand" "dINO")))]
5097 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5099 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5101 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5102 return \"ror%.l %2,%0\";
5105 return \"rol%.l %2,%0\";
5108 (define_insn "rotlhi3"
5109 [(set (match_operand:HI 0 "register_operand" "=d")
5110 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5111 (match_operand:HI 2 "general_operand" "dIP")))]
5115 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5117 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5118 return \"ror%.w %2,%0\";
5121 return \"rol%.w %2,%0\";
5125 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5126 (rotate:HI (match_dup 0)
5127 (match_operand:HI 1 "general_operand" "dIP")))]
5131 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5133 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5134 return \"ror%.w %2,%0\";
5137 return \"rol%.w %2,%0\";
5140 (define_insn "rotlqi3"
5141 [(set (match_operand:QI 0 "register_operand" "=d")
5142 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5143 (match_operand:QI 2 "general_operand" "dI")))]
5147 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5149 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5150 return \"ror%.b %2,%0\";
5153 return \"rol%.b %2,%0\";
5157 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5158 (rotate:QI (match_dup 0)
5159 (match_operand:QI 1 "general_operand" "dI")))]
5163 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5165 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5166 return \"ror%.b %2,%0\";
5169 return \"rol%.b %2,%0\";
5172 (define_insn "rotrsi3"
5173 [(set (match_operand:SI 0 "register_operand" "=d")
5174 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5175 (match_operand:SI 2 "general_operand" "dI")))]
5179 (define_insn "rotrhi3"
5180 [(set (match_operand:HI 0 "register_operand" "=d")
5181 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5182 (match_operand:HI 2 "general_operand" "dI")))]
5187 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5188 (rotatert:HI (match_dup 0)
5189 (match_operand:HI 1 "general_operand" "dI")))]
5193 (define_insn "rotrqi3"
5194 [(set (match_operand:QI 0 "register_operand" "=d")
5195 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5196 (match_operand:QI 2 "general_operand" "dI")))]
5201 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5202 (rotatert:QI (match_dup 0)
5203 (match_operand:QI 1 "general_operand" "dI")))]
5208 ;; Bit set/clear in memory byte.
5210 ;; set bit, bit number is int
5211 (define_insn "bsetmemqi"
5212 [(set (match_operand:QI 0 "memory_operand" "+m")
5213 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5214 (match_operand:SI 1 "general_operand" "d")) 0)
5220 return \"bset %1,%0\";
5223 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5225 [(set (match_operand:QI 0 "memory_operand" "+m")
5226 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5227 (match_operator:SI 2 "extend_operator"
5228 [(match_operand 1 "general_operand" "d")])) 0)
5234 return \"bset %1,%0\";
5237 ;; clear bit, bit number is int
5238 (define_insn "bclrmemqi"
5239 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5241 (minus:SI (const_int 7)
5242 (match_operand:SI 1 "general_operand" "d")))
5248 return \"bclr %1,%0\";
5251 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5253 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5255 (minus:SI (const_int 7)
5256 (match_operator:SI 2 "extend_operator"
5257 [(match_operand 1 "general_operand" "d")])))
5263 return \"bclr %1,%0\";
5266 ;; Special cases of bit-field insns which we should
5267 ;; recognize in preference to the general case.
5268 ;; These handle aligned 8-bit and 16-bit fields,
5269 ;; which can usually be done with move instructions.
5272 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5273 ; alignment of structure members is specified.
5275 ; The move is allowed to be odd byte aligned, because that's still faster
5276 ; than an odd byte aligned bit field instruction.
5279 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5281 (match_operand:SI 2 "const_int_operand" "n"))
5282 (match_operand:SI 3 "general_src_operand" "rmSi"))]
5283 "TARGET_68020 && TARGET_BITFIELD
5284 && (INTVAL (operands[2]) % 8) == 0
5285 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5289 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5291 return \"move%.l %3,%0\";
5295 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5296 (match_operand:SI 1 "const_int_operand" "n")
5297 (match_operand:SI 2 "const_int_operand" "n"))
5298 (match_operand:SI 3 "register_operand" "d"))]
5299 "TARGET_68020 && TARGET_BITFIELD
5300 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5301 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5302 && (GET_CODE (operands[0]) == REG
5303 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5306 if (REG_P (operands[0]))
5308 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5309 return \"bfins %3,%0{%b2:%b1}\";
5313 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5315 if (GET_CODE (operands[3]) == MEM)
5316 operands[3] = adj_offsettable_operand (operands[3],
5317 (32 - INTVAL (operands[1])) / 8);
5318 if (INTVAL (operands[1]) == 8)
5319 return \"move%.b %3,%0\";
5320 return \"move%.w %3,%0\";
5325 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5326 ; alignment of structure members is specified.
5328 ; The move is allowed to be odd byte aligned, because that's still faster
5329 ; than an odd byte aligned bit field instruction.
5332 [(set (match_operand:SI 0 "general_operand" "=rm")
5333 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5335 (match_operand:SI 3 "const_int_operand" "n")))]
5336 "TARGET_68020 && TARGET_BITFIELD
5337 && (INTVAL (operands[3]) % 8) == 0
5338 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5342 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5344 return \"move%.l %1,%0\";
5348 [(set (match_operand:SI 0 "general_operand" "=&d")
5349 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5350 (match_operand:SI 2 "const_int_operand" "n")
5351 (match_operand:SI 3 "const_int_operand" "n")))]
5352 "TARGET_68020 && TARGET_BITFIELD
5353 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5354 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5355 && (GET_CODE (operands[1]) == REG
5356 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5359 cc_status.flags |= CC_NOT_NEGATIVE;
5360 if (REG_P (operands[1]))
5362 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5363 return \"bfextu %1{%b3:%b2},%0\";
5367 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5369 output_asm_insn (\"clr%.l %0\", operands);
5370 if (GET_CODE (operands[0]) == MEM)
5371 operands[0] = adj_offsettable_operand (operands[0],
5372 (32 - INTVAL (operands[1])) / 8);
5373 if (INTVAL (operands[2]) == 8)
5374 return \"move%.b %1,%0\";
5375 return \"move%.w %1,%0\";
5379 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5380 ; alignment of structure members is specified.
5382 ; The move is allowed to be odd byte aligned, because that's still faster
5383 ; than an odd byte aligned bit field instruction.
5386 [(set (match_operand:SI 0 "general_operand" "=rm")
5387 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5389 (match_operand:SI 3 "const_int_operand" "n")))]
5390 "TARGET_68020 && TARGET_BITFIELD
5391 && (INTVAL (operands[3]) % 8) == 0
5392 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5396 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5398 return \"move%.l %1,%0\";
5402 [(set (match_operand:SI 0 "general_operand" "=d")
5403 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5404 (match_operand:SI 2 "const_int_operand" "n")
5405 (match_operand:SI 3 "const_int_operand" "n")))]
5406 "TARGET_68020 && TARGET_BITFIELD
5407 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5408 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5409 && (GET_CODE (operands[1]) == REG
5410 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5413 if (REG_P (operands[1]))
5415 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5416 return \"bfexts %1{%b3:%b2},%0\";
5420 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5422 if (INTVAL (operands[2]) == 8)
5423 return \"move%.b %1,%0\;extb%.l %0\";
5424 return \"move%.w %1,%0\;ext%.l %0\";
5427 ;; Bit field instructions, general cases.
5428 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5429 ;; so that its address is reloaded.
5431 (define_expand "extv"
5432 [(set (match_operand:SI 0 "general_operand" "")
5433 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5434 (match_operand:SI 2 "general_operand" "")
5435 (match_operand:SI 3 "general_operand" "")))]
5436 "TARGET_68020 && TARGET_BITFIELD"
5440 [(set (match_operand:SI 0 "general_operand" "=d")
5441 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5442 (match_operand:SI 2 "general_operand" "di")
5443 (match_operand:SI 3 "general_operand" "di")))]
5444 "TARGET_68020 && TARGET_BITFIELD"
5445 "bfexts %1{%b3:%b2},%0")
5447 (define_expand "extzv"
5448 [(set (match_operand:SI 0 "general_operand" "")
5449 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5450 (match_operand:SI 2 "general_operand" "")
5451 (match_operand:SI 3 "general_operand" "")))]
5452 "TARGET_68020 && TARGET_BITFIELD"
5456 [(set (match_operand:SI 0 "general_operand" "=d,d")
5457 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5458 (match_operand:SI 2 "general_operand" "di,di")
5459 (match_operand:SI 3 "general_operand" "di,di")))]
5460 "TARGET_68020 && TARGET_BITFIELD"
5463 if (GET_CODE (operands[2]) == CONST_INT)
5465 if (INTVAL (operands[2]) != 32)
5466 cc_status.flags |= CC_NOT_NEGATIVE;
5472 return \"bfextu %1{%b3:%b2},%0\";
5476 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5477 (match_operand:SI 1 "general_operand" "di")
5478 (match_operand:SI 2 "general_operand" "di"))
5479 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5480 (match_operand 3 "const_int_operand" "n")))]
5481 "TARGET_68020 && TARGET_BITFIELD
5482 && (INTVAL (operands[3]) == -1
5483 || (GET_CODE (operands[1]) == CONST_INT
5484 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5488 return \"bfchg %0{%b2:%b1}\";
5492 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5493 (match_operand:SI 1 "general_operand" "di")
5494 (match_operand:SI 2 "general_operand" "di"))
5496 "TARGET_68020 && TARGET_BITFIELD"
5500 return \"bfclr %0{%b2:%b1}\";
5504 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5505 (match_operand:SI 1 "general_operand" "di")
5506 (match_operand:SI 2 "general_operand" "di"))
5508 "TARGET_68020 && TARGET_BITFIELD"
5512 return \"bfset %0{%b2:%b1}\";
5515 (define_expand "insv"
5516 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5517 (match_operand:SI 1 "general_operand" "")
5518 (match_operand:SI 2 "general_operand" ""))
5519 (match_operand:SI 3 "register_operand" ""))]
5520 "TARGET_68020 && TARGET_BITFIELD"
5524 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5525 (match_operand:SI 1 "general_operand" "di")
5526 (match_operand:SI 2 "general_operand" "di"))
5527 (match_operand:SI 3 "register_operand" "d"))]
5528 "TARGET_68020 && TARGET_BITFIELD"
5529 "bfins %3,%0{%b2:%b1}")
5531 ;; Now recognize bit field insns that operate on registers
5532 ;; (or at least were intended to do so).
5535 [(set (match_operand:SI 0 "general_operand" "=d")
5536 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5537 (match_operand:SI 2 "general_operand" "di")
5538 (match_operand:SI 3 "general_operand" "di")))]
5539 "TARGET_68020 && TARGET_BITFIELD"
5540 "bfexts %1{%b3:%b2},%0")
5543 [(set (match_operand:SI 0 "general_operand" "=d")
5544 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5545 (match_operand:SI 2 "general_operand" "di")
5546 (match_operand:SI 3 "general_operand" "di")))]
5547 "TARGET_68020 && TARGET_BITFIELD"
5550 if (GET_CODE (operands[2]) == CONST_INT)
5552 if (INTVAL (operands[2]) != 32)
5553 cc_status.flags |= CC_NOT_NEGATIVE;
5559 return \"bfextu %1{%b3:%b2},%0\";
5563 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5564 (match_operand:SI 1 "general_operand" "di")
5565 (match_operand:SI 2 "general_operand" "di"))
5567 "TARGET_68020 && TARGET_BITFIELD"
5571 return \"bfclr %0{%b2:%b1}\";
5575 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5576 (match_operand:SI 1 "general_operand" "di")
5577 (match_operand:SI 2 "general_operand" "di"))
5579 "TARGET_68020 && TARGET_BITFIELD"
5583 return \"bfset %0{%b2:%b1}\";
5587 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5588 (match_operand:SI 1 "general_operand" "di")
5589 (match_operand:SI 2 "general_operand" "di"))
5590 (match_operand:SI 3 "register_operand" "d"))]
5591 "TARGET_68020 && TARGET_BITFIELD"
5595 /* These special cases are now recognized by a specific pattern. */
5596 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5597 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5598 return \"move%.w %3,%0\";
5599 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5600 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5601 return \"move%.b %3,%0\";
5603 return \"bfins %3,%0{%b2:%b1}\";
5606 ;; Special patterns for optimizing bit-field instructions.
5610 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5611 (match_operand:SI 1 "const_int_operand" "n")
5612 (match_operand:SI 2 "general_operand" "di")))]
5613 "TARGET_68020 && TARGET_BITFIELD"
5616 if (operands[1] == const1_rtx
5617 && GET_CODE (operands[2]) == CONST_INT)
5619 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5620 return output_btst (operands,
5621 GEN_INT (width - INTVAL (operands[2])),
5622 operands[0], insn, 1000);
5623 /* Pass 1000 as SIGNPOS argument so that btst will
5624 not think we are testing the sign bit for an `and'
5625 and assume that nonzero implies a negative result. */
5627 if (INTVAL (operands[1]) != 32)
5628 cc_status.flags = CC_NOT_NEGATIVE;
5629 return \"bftst %0{%b2:%b1}\";
5633 ;;; now handle the register cases
5636 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5637 (match_operand:SI 1 "const_int_operand" "n")
5638 (match_operand:SI 2 "general_operand" "di")))]
5639 "TARGET_68020 && TARGET_BITFIELD"
5642 if (operands[1] == const1_rtx
5643 && GET_CODE (operands[2]) == CONST_INT)
5645 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5646 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5647 operands[0], insn, 1000);
5648 /* Pass 1000 as SIGNPOS argument so that btst will
5649 not think we are testing the sign bit for an `and'
5650 and assume that nonzero implies a negative result. */
5652 if (INTVAL (operands[1]) != 32)
5653 cc_status.flags = CC_NOT_NEGATIVE;
5654 return \"bftst %0{%b2:%b1}\";
5657 (define_insn "scc0_di"
5658 [(set (match_operand:QI 0 "general_operand" "=dm")
5659 (match_operator 1 "valid_dbcc_comparison_p"
5660 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5664 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5667 (define_insn "scc0_di_5200"
5668 [(set (match_operand:QI 0 "general_operand" "=d")
5669 (match_operator 1 "valid_dbcc_comparison_p"
5670 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5674 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5677 (define_insn "scc_di"
5678 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5679 (match_operator 1 "valid_dbcc_comparison_p"
5680 [(match_operand:DI 2 "general_operand" "ro,r")
5681 (match_operand:DI 3 "general_operand" "r,ro")]))]
5685 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5688 (define_insn "scc_di_5200"
5689 [(set (match_operand:QI 0 "general_operand" "=d,d")
5690 (match_operator 1 "valid_dbcc_comparison_p"
5691 [(match_operand:DI 2 "general_operand" "ro,r")
5692 (match_operand:DI 3 "general_operand" "r,ro")]))]
5696 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5699 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5700 ;; memory, but we cannot allow it to be in memory in case the address
5701 ;; needs to be reloaded.
5703 (define_expand "seq"
5704 [(set (match_operand:QI 0 "register_operand" "")
5705 (eq:QI (cc0) (const_int 0)))]
5709 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5711 m68k_last_compare_had_fp_operands = 0;
5717 [(set (match_operand:QI 0 "register_operand" "=d")
5718 (eq:QI (cc0) (const_int 0)))]
5721 cc_status = cc_prev_status;
5722 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5725 (define_expand "sne"
5726 [(set (match_operand:QI 0 "register_operand" "")
5727 (ne:QI (cc0) (const_int 0)))]
5731 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5733 m68k_last_compare_had_fp_operands = 0;
5739 [(set (match_operand:QI 0 "register_operand" "=d")
5740 (ne:QI (cc0) (const_int 0)))]
5743 cc_status = cc_prev_status;
5744 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5747 (define_expand "sgt"
5748 [(set (match_operand:QI 0 "register_operand" "")
5749 (gt:QI (cc0) (const_int 0)))]
5753 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5755 m68k_last_compare_had_fp_operands = 0;
5761 [(set (match_operand:QI 0 "register_operand" "=d")
5762 (gt:QI (cc0) (const_int 0)))]
5765 cc_status = cc_prev_status;
5766 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5769 (define_expand "sgtu"
5770 [(set (match_operand:QI 0 "register_operand" "")
5771 (gtu:QI (cc0) (const_int 0)))]
5776 [(set (match_operand:QI 0 "register_operand" "=d")
5777 (gtu:QI (cc0) (const_int 0)))]
5780 cc_status = cc_prev_status;
5781 return \"shi %0\"; ")
5783 (define_expand "slt"
5784 [(set (match_operand:QI 0 "register_operand" "")
5785 (lt:QI (cc0) (const_int 0)))]
5789 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5791 m68k_last_compare_had_fp_operands = 0;
5797 [(set (match_operand:QI 0 "register_operand" "=d")
5798 (lt:QI (cc0) (const_int 0)))]
5801 cc_status = cc_prev_status;
5802 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5804 (define_expand "sltu"
5805 [(set (match_operand:QI 0 "register_operand" "")
5806 (ltu:QI (cc0) (const_int 0)))]
5811 [(set (match_operand:QI 0 "register_operand" "=d")
5812 (ltu:QI (cc0) (const_int 0)))]
5815 cc_status = cc_prev_status;
5816 return \"scs %0\"; ")
5818 (define_expand "sge"
5819 [(set (match_operand:QI 0 "register_operand" "")
5820 (ge:QI (cc0) (const_int 0)))]
5824 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5826 m68k_last_compare_had_fp_operands = 0;
5832 [(set (match_operand:QI 0 "register_operand" "=d")
5833 (ge:QI (cc0) (const_int 0)))]
5836 cc_status = cc_prev_status;
5837 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5839 (define_expand "sgeu"
5840 [(set (match_operand:QI 0 "register_operand" "")
5841 (geu:QI (cc0) (const_int 0)))]
5846 [(set (match_operand:QI 0 "register_operand" "=d")
5847 (geu:QI (cc0) (const_int 0)))]
5850 cc_status = cc_prev_status;
5851 return \"scc %0\"; ")
5853 (define_expand "sle"
5854 [(set (match_operand:QI 0 "register_operand" "")
5855 (le:QI (cc0) (const_int 0)))]
5859 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5861 m68k_last_compare_had_fp_operands = 0;
5867 [(set (match_operand:QI 0 "register_operand" "=d")
5868 (le:QI (cc0) (const_int 0)))]
5871 cc_status = cc_prev_status;
5872 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5875 (define_expand "sleu"
5876 [(set (match_operand:QI 0 "register_operand" "")
5877 (leu:QI (cc0) (const_int 0)))]
5882 [(set (match_operand:QI 0 "register_operand" "=d")
5883 (leu:QI (cc0) (const_int 0)))]
5886 cc_status = cc_prev_status;
5887 return \"sls %0\"; ")
5889 ;; Basic conditional jump instructions.
5891 (define_insn "beq0_di"
5893 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5895 (label_ref (match_operand 1 "" ","))
5897 (clobber (match_scratch:SI 2 "=d,d"))]
5902 if (which_alternative == 1)
5904 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5906 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5908 if ((cc_prev_status.value1
5909 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5910 || (cc_prev_status.value2
5911 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5913 cc_status = cc_prev_status;
5915 return \"jbeq %l1\";
5920 if (GET_CODE (operands[0]) == REG)
5921 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5923 operands[3] = adj_offsettable_operand (operands[0], 4);
5924 if (! ADDRESS_REG_P (operands[0]))
5926 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5928 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5931 return \"or%.l %0,%2\;jbeq %l1\";
5933 return \"or%.l %0,%2\;jeq %l1\";
5939 return \"or%.l %3,%2\;jbeq %l1\";
5941 return \"or%.l %3,%2\;jeq %l1\";
5946 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5948 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5951 operands[4] = gen_label_rtx();
5952 if (TARGET_68020 || TARGET_5200)
5955 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5957 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5963 #ifdef SGS_CMP_ORDER
5964 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5966 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5969 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5972 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5973 CODE_LABEL_NUMBER (operands[4]));
5977 (define_insn "bne0_di"
5979 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5981 (label_ref (match_operand 1 "" ","))
5983 (clobber (match_scratch:SI 2 "=d,X"))]
5987 if ((cc_prev_status.value1
5988 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5989 || (cc_prev_status.value2
5990 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5992 cc_status = cc_prev_status;
5994 return \"jbne %l1\";
6000 if (GET_CODE (operands[0]) == REG)
6001 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6003 operands[3] = adj_offsettable_operand (operands[0], 4);
6004 if (!ADDRESS_REG_P (operands[0]))
6006 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6008 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6011 return \"or%.l %0,%2\;jbne %l1\";
6013 return \"or%.l %0,%2\;jne %l1\";
6019 return \"or%.l %3,%2\;jbne %l1\";
6021 return \"or%.l %3,%2\;jne %l1\";
6026 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6028 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6031 if (TARGET_68020 || TARGET_5200)
6034 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6036 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6042 #ifdef SGS_CMP_ORDER
6043 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6045 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6048 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6053 (define_insn "bge0_di"
6055 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6057 (label_ref (match_operand 1 "" ""))
6062 if ((cc_prev_status.value1
6063 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6064 || (cc_prev_status.value2
6065 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6067 cc_status = cc_prev_status;
6068 if (cc_status.flags & CC_REVERSED)
6071 return \"jble %l1\";
6079 return \"jbpl %l1\";
6086 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6087 output_asm_insn(\"tst%.l %0\", operands);
6090 /* On an address reg, cmpw may replace cmpl. */
6091 #ifdef SGS_CMP_ORDER
6092 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6094 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6099 return \"jbpl %l1\";
6105 (define_insn "blt0_di"
6107 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6109 (label_ref (match_operand 1 "" ""))
6114 if ((cc_prev_status.value1
6115 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6116 || (cc_prev_status.value2
6117 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6119 cc_status = cc_prev_status;
6120 if (cc_status.flags & CC_REVERSED)
6123 return \"jbgt %l1\";
6131 return \"jbmi %l1\";
6138 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6139 output_asm_insn(\"tst%.l %0\", operands);
6142 /* On an address reg, cmpw may replace cmpl. */
6143 #ifdef SGS_CMP_ORDER
6144 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6146 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6151 return \"jbmi %l1\";
6159 (if_then_else (eq (cc0)
6161 (label_ref (match_operand 0 "" ""))
6167 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6169 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6175 (if_then_else (ne (cc0)
6177 (label_ref (match_operand 0 "" ""))
6183 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6185 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6191 (if_then_else (gt (cc0)
6193 (label_ref (match_operand 0 "" ""))
6198 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6200 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6206 (if_then_else (gtu (cc0)
6208 (label_ref (match_operand 0 "" ""))
6213 return \"jbhi %l0\";
6221 (if_then_else (lt (cc0)
6223 (label_ref (match_operand 0 "" ""))
6228 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6230 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6236 (if_then_else (ltu (cc0)
6238 (label_ref (match_operand 0 "" ""))
6243 return \"jbcs %l0\";
6251 (if_then_else (ge (cc0)
6253 (label_ref (match_operand 0 "" ""))
6258 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6260 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6266 (if_then_else (geu (cc0)
6268 (label_ref (match_operand 0 "" ""))
6273 return \"jbcc %l0\";
6281 (if_then_else (le (cc0)
6283 (label_ref (match_operand 0 "" ""))
6288 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6290 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6296 (if_then_else (leu (cc0)
6298 (label_ref (match_operand 0 "" ""))
6303 return \"jbls %l0\";
6309 ;; Negated conditional jump instructions.
6313 (if_then_else (eq (cc0)
6316 (label_ref (match_operand 0 "" ""))))]
6321 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6323 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6329 (if_then_else (ne (cc0)
6332 (label_ref (match_operand 0 "" ""))))]
6337 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6339 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6345 (if_then_else (gt (cc0)
6348 (label_ref (match_operand 0 "" ""))))]
6352 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6354 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6360 (if_then_else (gtu (cc0)
6363 (label_ref (match_operand 0 "" ""))))]
6367 return \"jbls %l0\";
6375 (if_then_else (lt (cc0)
6378 (label_ref (match_operand 0 "" ""))))]
6382 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6384 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6390 (if_then_else (ltu (cc0)
6393 (label_ref (match_operand 0 "" ""))))]
6397 return \"jbcc %l0\";
6405 (if_then_else (ge (cc0)
6408 (label_ref (match_operand 0 "" ""))))]
6412 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6414 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6420 (if_then_else (geu (cc0)
6423 (label_ref (match_operand 0 "" ""))))]
6427 return \"jbcs %l0\";
6435 (if_then_else (le (cc0)
6438 (label_ref (match_operand 0 "" ""))))]
6442 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6444 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6450 (if_then_else (leu (cc0)
6453 (label_ref (match_operand 0 "" ""))))]
6457 return \"jbhi %l0\";
6463 ;; Unconditional and other jump instructions
6466 (label_ref (match_operand 0 "" "")))]
6470 return \"jbra %l0\";
6476 ;; We support two different ways of handling dispatch tables.
6477 ;; The NeXT uses absolute tables, and other machines use relative.
6478 ;; This define_expand can generate either kind.
6479 (define_expand "tablejump"
6480 [(parallel [(set (pc) (match_operand 0 "" ""))
6481 (use (label_ref (match_operand 1 "" "")))])]
6485 #ifdef CASE_VECTOR_PC_RELATIVE
6486 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6487 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6491 ;; Jump to variable address from dispatch table of absolute addresses.
6493 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6494 (use (label_ref (match_operand 1 "" "")))]
6498 return \"jmp (%0)\";
6504 ;; Jump to variable address from dispatch table of relative addresses.
6508 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6509 (use (label_ref (match_operand 1 "" "")))]
6512 #ifdef ASM_RETURN_CASE_JUMP
6513 ASM_RETURN_CASE_JUMP;
6516 #ifdef ASM_OUTPUT_CASE_LABEL
6518 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6520 return \"jmp 6(%%pc,%0.w)\";
6525 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6527 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6528 #endif /* end !CRDS */
6533 return \"jmp 2(pc,%0.w)\";
6535 return \"jmp 2(%%pc,%0.w)\";
6536 #endif /* end !CRDS */
6543 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6545 return \"extl %0\;jmp pc@(2,%0:l)\";
6551 return \"jmp (2,pc,%0.w)\";
6553 return \"jmp pc@(2,%0:w)\";
6560 ;; Decrement-and-branch insns.
6564 (ne (match_operand:HI 0 "general_operand" "+d*g")
6566 (label_ref (match_operand 1 "" ""))
6569 (plus:HI (match_dup 0)
6575 if (DATA_REG_P (operands[0]))
6576 return \"dbra %0,%l1\";
6577 if (GET_CODE (operands[0]) == MEM)
6581 return \"sub%.w %#1,%0\;jbcc %l1\";
6583 return \"subq%.w %#1,%0\;jbcc %l1\";
6585 #else /* not MOTOROLA */
6586 return \"subqw %#1,%0\;jcc %l1\";
6590 #ifdef SGS_CMP_ORDER
6592 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6594 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6596 #else /* not SGS_CMP_ORDER */
6597 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6599 #else /* not MOTOROLA */
6600 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6607 (ne (match_operand:SI 0 "general_operand" "+d*g")
6609 (label_ref (match_operand 1 "" ""))
6612 (plus:SI (match_dup 0)
6620 if (DATA_REG_P (operands[0]))
6621 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6622 if (GET_CODE (operands[0]) == MEM)
6623 return \"sub%.l %#1,%0\;jbcc %l1\";
6625 if (DATA_REG_P (operands[0]))
6626 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6627 if (GET_CODE (operands[0]) == MEM)
6628 return \"subq%.l %#1,%0\;jbcc %l1\";
6629 #endif /* NO_ADDSUB_Q */
6630 #ifdef SGS_CMP_ORDER
6632 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6634 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6636 #else /* not SGS_CMP_ORDER */
6637 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6638 #endif /* not SGS_CMP_ORDER */
6639 #else /* not MOTOROLA */
6640 if (DATA_REG_P (operands[0]))
6641 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6642 if (GET_CODE (operands[0]) == MEM)
6643 return \"subql %#1,%0\;jcc %l1\";
6644 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6645 #endif /* not MOTOROLA */
6648 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6653 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6656 (label_ref (match_operand 1 "" ""))
6659 (plus:HI (match_dup 0)
6661 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6667 if (DATA_REG_P (operands[0]))
6668 return \"dbra %0,%l1\";
6669 if (GET_CODE (operands[0]) == MEM)
6670 return \"sub%.w %#1,%0\;jbcc %l1\";
6672 if (DATA_REG_P (operands[0]))
6673 return \"dbra %0,%l1\";
6674 if (GET_CODE (operands[0]) == MEM)
6675 return \"subq%.w %#1,%0\;jbcc %l1\";
6677 #ifdef SGS_CMP_ORDER
6679 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6681 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6683 #else /* not SGS_CMP_ORDER */
6684 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6685 #endif /* not SGS_CMP_ORDER */
6686 #else /* not MOTOROLA */
6687 if (DATA_REG_P (operands[0]))
6688 return \"dbra %0,%l1\";
6689 if (GET_CODE (operands[0]) == MEM)
6690 return \"subqw %#1,%0\;jcc %l1\";
6691 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6692 #endif /* not MOTOROLA */
6695 (define_expand "decrement_and_branch_until_zero"
6696 [(parallel [(set (pc)
6698 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6701 (label_ref (match_operand 1 "" ""))
6704 (plus:SI (match_dup 0)
6712 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6715 (label_ref (match_operand 1 "" ""))
6718 (plus:SI (match_dup 0)
6720 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6726 if (DATA_REG_P (operands[0]))
6727 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6728 if (GET_CODE (operands[0]) == MEM)
6729 return \"sub%.l %#1,%0\;jbcc %l1\";
6731 if (DATA_REG_P (operands[0]))
6732 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6733 if (GET_CODE (operands[0]) == MEM)
6734 return \"subq%.l %#1,%0\;jbcc %l1\";
6736 #ifdef SGS_CMP_ORDER
6738 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6740 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6742 #else /* not SGS_CMP_ORDER */
6743 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6744 #endif /* not SGS_CMP_ORDER */
6745 #else /* not MOTOROLA */
6746 if (DATA_REG_P (operands[0]))
6747 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6748 if (GET_CODE (operands[0]) == MEM)
6749 return \"subql %#1,%0\;jcc %l1\";
6750 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6751 #endif /* not MOTOROLA */
6755 ;; For PIC calls, in order to be able to support
6756 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6757 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6759 ;; PIC calls are handled by loading the address of the function into a
6760 ;; register (via movsi), then emitting a register indirect call using
6761 ;; the "jsr" function call syntax.
6763 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6764 ;; operand to the jbsr statement to indicate that this call should
6765 ;; go through the PLT (why? because this is the way that Sun does it).
6767 ;; We have different patterns for PIC calls and non-PIC calls. The
6768 ;; different patterns are only used to choose the right syntax.
6770 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6771 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6772 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6773 ;; section at link time. However, all global objects reference are still
6774 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6775 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6776 ;; We need to have a way to differentiate these two different operands.
6778 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6779 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6780 ;; to be changed to recognize function calls symbol_ref operand as a valid
6781 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6782 ;; avoid the compiler to load this symbol_ref operand into a register.
6783 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6784 ;; since the value is a PC relative offset, not a real address.
6786 ;; All global objects are treated in the similar way as in SUN3. The only
6787 ;; difference is: on m68k svr4, the reference of such global object needs
6788 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6789 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6792 ;; Call subroutine with no return value.
6793 (define_expand "call"
6794 [(call (match_operand:QI 0 "memory_operand" "")
6795 (match_operand:SI 1 "general_operand" ""))]
6796 ;; Operand 1 not really used on the m68000.
6801 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6802 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6805 ;; This is a normal call sequence.
6807 [(call (match_operand:QI 0 "memory_operand" "o")
6808 (match_operand:SI 1 "general_operand" "g"))]
6809 ;; Operand 1 not really used on the m68000.
6813 #if defined (MOTOROLA) && !defined (USE_GAS)
6815 if (GET_CODE (operands[0]) == MEM
6816 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6825 ;; This is a PIC call sequence.
6827 [(call (match_operand:QI 0 "memory_operand" "o")
6828 (match_operand:SI 1 "general_operand" "g"))]
6829 ;; Operand 1 not really used on the m68000.
6833 if (GET_CODE (operands[0]) == MEM
6834 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6836 if (TARGET_PCREL) return \"bsr.l %o0\";
6839 return \"bsr.l %0\";
6842 return \"bsr.l %0@PLTPC\";
6844 return \"bsr %0@PLTPC\";
6849 return \"bsr.l %0\";
6851 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6852 GAS just plain ignores it. FIXME: not anymore, gas doesnt! */
6853 return \"jbsr %0,a1\";
6860 ;; Call subroutine, returning value in operand 0
6861 ;; (which must be a hard register).
6862 ;; See comments before "call" regarding PIC calls.
6863 (define_expand "call_value"
6864 [(set (match_operand 0 "" "")
6865 (call (match_operand:QI 1 "memory_operand" "")
6866 (match_operand:SI 2 "general_operand" "")))]
6867 ;; Operand 2 not really used on the m68000.
6871 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6872 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6875 ;; This is a normal call_value
6877 [(set (match_operand 0 "" "=rf")
6878 (call (match_operand:QI 1 "memory_operand" "o")
6879 (match_operand:SI 2 "general_operand" "g")))]
6880 ;; Operand 2 not really used on the m68000.
6883 #if defined (MOTOROLA) && !defined (USE_GAS)
6885 if (GET_CODE (operands[1]) == MEM
6886 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6895 ;; This is a PIC call_value
6897 [(set (match_operand 0 "" "=rf")
6898 (call (match_operand:QI 1 "memory_operand" "o")
6899 (match_operand:SI 2 "general_operand" "g")))]
6900 ;; Operand 2 not really used on the m68000.
6903 if (GET_CODE (operands[1]) == MEM
6904 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6906 if (TARGET_PCREL) return \"bsr.l %o1\";
6909 return \"bsr.l %1\";
6912 return \"bsr.l %1@PLTPC\";
6914 return \"bsr %1@PLTPC\";
6919 return \"bsr.l %1\";
6921 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6922 GAS just plain ignores it. FIXME: Not anymore, gas doesnt! */
6923 return \"jbsr %1,a1\";
6930 ;; Call subroutine returning any type.
6932 (define_expand "untyped_call"
6933 [(parallel [(call (match_operand 0 "" "")
6935 (match_operand 1 "" "")
6936 (match_operand 2 "" "")])]
6937 "NEEDS_UNTYPED_CALL"
6942 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6944 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6946 rtx set = XVECEXP (operands[2], 0, i);
6947 emit_move_insn (SET_DEST (set), SET_SRC (set));
6950 /* The optimizer does not know that the call sets the function value
6951 registers we stored in the result block. We avoid problems by
6952 claiming that all hard registers are used and clobbered at this
6954 emit_insn (gen_blockage ());
6959 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6960 ;; all of memory. This blocks insns from being moved across this point.
6962 (define_insn "blockage"
6963 [(unspec_volatile [(const_int 0)] 0)]
6972 (define_insn "probe"
6977 operands[0] = plus_constant (stack_pointer_rtx, NEED_PROBE);
6978 return \"tstl %a0\";
6981 ;; Used for frameless functions which save no regs and allocate no locals.
6982 (define_insn "return"
6987 if (current_function_pops_args == 0)
6989 operands[0] = GEN_INT (current_function_pops_args);
6993 (define_insn "indirect_jump"
6994 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6998 ;; This should not be used unless the add/sub insns can't be.
7001 [(set (match_operand:SI 0 "general_operand" "=a")
7002 (match_operand:QI 1 "address_operand" "p"))]
7007 /* Recognize an insn that refers to a table of offsets. Such an insn will
7008 need to refer to a label on the insn. So output one. Use the
7009 label-number of the table of offsets to generate this label. This code,
7010 and similar code above, assumes that there will be at most one reference
7012 if (GET_CODE (operands[1]) == PLUS
7013 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
7014 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
7016 rtx labelref = XEXP (operands[1], 1);
7017 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
7019 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
7020 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7022 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
7023 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7024 #endif /* not SGS */
7025 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
7026 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
7027 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7028 #ifdef SGS_SWITCH_TABLES
7029 /* Set flag saying we need to define the symbol
7030 LD%n (with value L%n-LI%n) at the end of the switch table. */
7031 switch_table_difference_label_flag = 1;
7032 #endif /* SGS_SWITCH_TABLES */
7033 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7035 #endif /* SGS_NO_LI */
7037 return \"lea %a1,%0\";
7040 ;; This is the first machine-dependent peephole optimization.
7041 ;; It is useful when a floating value is returned from a function call
7042 ;; and then is moved into an FP register.
7043 ;; But it is mainly intended to test the support for these optimizations.
7046 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7047 (set (match_operand:DF 0 "register_operand" "=f")
7048 (match_operand:DF 1 "register_operand" "ad"))]
7049 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7053 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7054 output_asm_insn (\"move%.l %1,%@\", xoperands);
7055 output_asm_insn (\"move%.l %1,%-\", operands);
7056 return \"fmove%.d %+,%0\";
7060 ;; Optimize a stack-adjust followed by a push of an argument.
7061 ;; This is said to happen frequently with -msoft-float
7062 ;; when there are consecutive library calls.
7065 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7066 (match_operand:SI 0 "const_int_operand" "n")))
7067 (set (match_operand:SF 1 "push_operand" "=m")
7068 (match_operand:SF 2 "general_operand" "rmfF"))]
7069 "INTVAL (operands[0]) >= 4
7070 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7073 if (INTVAL (operands[0]) > 4)
7076 xoperands[0] = stack_pointer_rtx;
7077 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7079 if (INTVAL (xoperands[1]) <= 8)
7082 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7084 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7086 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7088 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7089 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7093 if (INTVAL (xoperands[1]) <= 0x7FFF)
7096 output_asm_insn (\"add%.w %1,%0\", xoperands);
7099 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7101 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7105 output_asm_insn (\"add%.l %1,%0\", xoperands);
7107 if (FP_REG_P (operands[2]))
7108 return \"fmove%.s %2,%@\";
7109 return \"move%.l %2,%@\";
7112 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7115 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7116 (match_operand:SI 0 "const_int_operand" "n")))
7117 (set (match_operand:SI 1 "push_operand" "=m")
7118 (match_operand:SI 2 "general_operand" "g"))]
7119 "INTVAL (operands[0]) >= 4
7120 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7123 if (INTVAL (operands[0]) > 4)
7126 xoperands[0] = stack_pointer_rtx;
7127 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7129 if (INTVAL (xoperands[1]) <= 8)
7132 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7134 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7136 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7138 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7139 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7143 if (INTVAL (xoperands[1]) <= 0x7FFF)
7146 output_asm_insn (\"add%.w %1,%0\", xoperands);
7150 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7152 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7157 output_asm_insn (\"add%.l %1,%0\", xoperands);
7159 if (operands[2] == const0_rtx)
7160 return \"clr%.l %@\";
7161 return \"move%.l %2,%@\";
7164 ;; Speed up pushing a single byte but leaving four bytes of space.
7167 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7168 (match_operand:QI 1 "general_operand" "dami"))
7169 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7170 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7175 if (GET_CODE (operands[1]) == REG)
7176 return \"move%.l %1,%-\";
7178 xoperands[1] = operands[1];
7180 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7181 xoperands[3] = stack_pointer_rtx;
7183 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7185 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7190 [(set (match_operand:SI 0 "register_operand" "=d")
7192 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7193 (match_operand:HI 1 "general_operand" "rmn"))]
7194 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7197 if (GET_CODE (operands[1]) == CONST_INT)
7199 if (operands[1] == const0_rtx
7200 && (DATA_REG_P (operands[0])
7201 || GET_CODE (operands[0]) == MEM)
7202 /* clr insns on 68000 read before writing.
7203 This isn't so on the 68010, but we have no TARGET_68010. */
7204 && ((TARGET_68020 || TARGET_5200)
7205 || !(GET_CODE (operands[0]) == MEM
7206 && MEM_VOLATILE_P (operands[0]))))
7207 return \"clr%.w %0\";
7209 return \"move%.w %1,%0\";
7217 ;; jCC label ; abnormal loop termination
7218 ;; dbra dN, loop ; normal loop termination
7226 ;; Which moves the jCC condition outside the inner loop for free.
7229 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7230 [(cc0) (const_int 0)])
7231 (label_ref (match_operand 2 "" ""))
7236 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7239 (label_ref (match_operand 1 "" ""))
7242 (plus:HI (match_dup 0)
7244 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7248 output_dbcc_and_branch (operands);
7253 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7254 [(cc0) (const_int 0)])
7255 (label_ref (match_operand 2 "" ""))
7260 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7263 (label_ref (match_operand 1 "" ""))
7266 (plus:SI (match_dup 0)
7268 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7272 output_dbcc_and_branch (operands);
7277 ;; FPA multiply and add.
7279 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7280 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7281 (match_operand:DF 2 "general_operand" "xH,y,y"))
7282 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7285 fpma%.d %1,%w2,%w3,%0
7286 fpma%.d %x1,%x2,%x3,%0
7287 fpma%.d %x1,%x2,%x3,%0")
7290 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7291 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7292 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7293 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7296 fpma%.s %1,%w2,%w3,%0
7298 fpma%.s %1,%2,%3,%0")
7300 ;; FPA Multiply and subtract
7302 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7303 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7304 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7305 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7308 fpms%.d %3,%w2,%w1,%0
7309 fpms%.d %x3,%2,%x1,%0
7310 fpms%.d %x3,%2,%x1,%0")
7313 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7314 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7315 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7316 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7319 fpms%.s %3,%w2,%w1,%0
7321 fpms%.s %3,%2,%1,%0")
7324 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7325 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7326 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7327 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7330 fpmr%.d %2,%w1,%w3,%0
7331 fpmr%.d %x2,%1,%x3,%0
7332 fpmr%.d %x2,%1,%x3,%0")
7335 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7336 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7337 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7338 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7341 fpmr%.s %2,%w1,%w3,%0
7342 fpmr%.s %x2,%1,%x3,%0
7343 fpmr%.s %x2,%1,%x3,%0")
7345 ;; FPA Add and multiply
7347 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7348 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7349 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7350 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7353 fpam%.d %2,%w1,%w3,%0
7354 fpam%.d %x2,%1,%x3,%0
7355 fpam%.d %x2,%1,%x3,%0")
7358 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7359 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7360 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7361 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7364 fpam%.s %2,%w1,%w3,%0
7365 fpam%.s %x2,%1,%x3,%0
7366 fpam%.s %x2,%1,%x3,%0")
7368 ;;FPA Subtract and multiply
7370 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7371 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7372 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7373 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7376 fpsm%.d %2,%w1,%w3,%0
7377 fpsm%.d %x2,%1,%x3,%0
7378 fpsm%.d %x2,%1,%x3,%0")
7381 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7382 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7383 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7384 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7387 fpsm%.d %3,%w2,%w1,%0
7388 fpsm%.d %x3,%2,%x1,%0
7389 fpsm%.d %x3,%2,%x1,%0")
7392 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7393 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7394 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7395 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7398 fpsm%.s %2,%w1,%w3,%0
7399 fpsm%.s %x2,%1,%x3,%0
7400 fpsm%.s %x2,%1,%x3,%0")
7403 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7404 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7405 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7406 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7409 fpsm%.s %3,%w2,%w1,%0
7410 fpsm%.s %x3,%2,%x1,%0
7411 fpsm%.s %x3,%2,%x1,%0")
7413 (define_expand "tstxf"
7415 (match_operand:XF 0 "nonimmediate_operand" ""))]
7417 "m68k_last_compare_had_fp_operands = 1;")
7421 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7425 cc_status.flags = CC_IN_68881;
7426 return \"ftst%.x %0\";
7429 (define_expand "cmpxf"
7431 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7432 (match_operand:XF 1 "nonimmediate_operand" "")))]
7434 "m68k_last_compare_had_fp_operands = 1;")
7438 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7439 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7443 cc_status.flags = CC_IN_68881;
7444 #ifdef SGS_CMP_ORDER
7445 if (REG_P (operands[0]))
7447 if (REG_P (operands[1]))
7448 return \"fcmp%.x %0,%1\";
7450 return \"fcmp%.x %0,%f1\";
7452 cc_status.flags |= CC_REVERSED;
7453 return \"fcmp%.x %1,%f0\";
7455 if (REG_P (operands[0]))
7457 if (REG_P (operands[1]))
7458 return \"fcmp%.x %1,%0\";
7460 return \"fcmp%.x %f1,%0\";
7462 cc_status.flags |= CC_REVERSED;
7463 return \"fcmp%.x %f0,%1\";
7467 (define_insn "extendsfxf2"
7468 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7469 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7473 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7475 if (REGNO (operands[0]) == REGNO (operands[1]))
7477 /* Extending float to double in an fp-reg is a no-op.
7478 NOTICE_UPDATE_CC has already assumed that the
7479 cc will be set. So cancel what it did. */
7480 cc_status = cc_prev_status;
7483 return \"f%$move%.x %1,%0\";
7485 if (FP_REG_P (operands[0]))
7487 if (FP_REG_P (operands[1]))
7488 return \"f%$move%.x %1,%0\";
7489 else if (ADDRESS_REG_P (operands[1]))
7490 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7491 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7492 return output_move_const_single (operands);
7493 return \"f%$move%.s %f1,%0\";
7495 return \"fmove%.x %f1,%0\";
7499 (define_insn "extenddfxf2"
7500 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7502 (match_operand:DF 1 "general_operand" "f,rmE")))]
7506 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7508 if (REGNO (operands[0]) == REGNO (operands[1]))
7510 /* Extending float to double in an fp-reg is a no-op.
7511 NOTICE_UPDATE_CC has already assumed that the
7512 cc will be set. So cancel what it did. */
7513 cc_status = cc_prev_status;
7516 return \"fmove%.x %1,%0\";
7518 if (FP_REG_P (operands[0]))
7520 if (REG_P (operands[1]))
7523 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7524 output_asm_insn (\"move%.l %1,%-\", xoperands);
7525 output_asm_insn (\"move%.l %1,%-\", operands);
7526 return \"f%&move%.d %+,%0\";
7528 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7529 return output_move_const_double (operands);
7530 return \"f%&move%.d %f1,%0\";
7532 return \"fmove%.x %f1,%0\";
7535 (define_insn "truncxfdf2"
7536 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7538 (match_operand:XF 1 "general_operand" "f,f")))]
7542 if (REG_P (operands[0]))
7544 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7545 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7546 return \"move%.l %+,%0\";
7548 return \"fmove%.d %f1,%0\";
7551 (define_insn "truncxfsf2"
7552 [(set (match_operand:SF 0 "general_operand" "=dm")
7554 (match_operand:XF 1 "general_operand" "f")))]
7558 (define_insn "floatsixf2"
7559 [(set (match_operand:XF 0 "general_operand" "=f")
7560 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7564 (define_insn "floathixf2"
7565 [(set (match_operand:XF 0 "general_operand" "=f")
7566 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7570 (define_insn "floatqixf2"
7571 [(set (match_operand:XF 0 "general_operand" "=f")
7572 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7576 (define_insn "ftruncxf2"
7577 [(set (match_operand:XF 0 "general_operand" "=f")
7578 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7582 if (FP_REG_P (operands[1]))
7583 return \"fintrz%.x %f1,%0\";
7584 return \"fintrz%.x %f1,%0\";
7587 (define_insn "fixxfqi2"
7588 [(set (match_operand:QI 0 "general_operand" "=dm")
7589 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7593 (define_insn "fixxfhi2"
7594 [(set (match_operand:HI 0 "general_operand" "=dm")
7595 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7599 (define_insn "fixxfsi2"
7600 [(set (match_operand:SI 0 "general_operand" "=dm")
7601 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7606 [(set (match_operand:XF 0 "general_operand" "=f")
7607 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7608 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7613 [(set (match_operand:XF 0 "general_operand" "=f")
7614 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7615 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7620 [(set (match_operand:XF 0 "general_operand" "=f")
7621 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7622 (match_operand:XF 1 "general_operand" "0")))]
7626 (define_insn "addxf3"
7627 [(set (match_operand:XF 0 "general_operand" "=f")
7628 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7629 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7633 if (REG_P (operands[2]))
7634 return \"fadd%.x %2,%0\";
7635 return \"fadd%.x %f2,%0\";
7639 [(set (match_operand:XF 0 "general_operand" "=f")
7640 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7641 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7646 [(set (match_operand:XF 0 "general_operand" "=f")
7647 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7648 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7653 [(set (match_operand:XF 0 "general_operand" "=f")
7654 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7655 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7659 (define_insn "subxf3"
7660 [(set (match_operand:XF 0 "general_operand" "=f")
7661 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7662 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7666 if (REG_P (operands[2]))
7667 return \"fsub%.x %2,%0\";
7668 return \"fsub%.x %f2,%0\";
7672 [(set (match_operand:XF 0 "general_operand" "=f")
7673 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7674 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7679 [(set (match_operand:XF 0 "general_operand" "=f")
7680 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7681 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7686 [(set (match_operand:XF 0 "general_operand" "=f")
7687 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7688 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7692 (define_insn "mulxf3"
7693 [(set (match_operand:XF 0 "general_operand" "=f")
7694 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7695 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7699 if (REG_P (operands[2]))
7700 return \"fmul%.x %2,%0\";
7701 return \"fmul%.x %f2,%0\";
7705 [(set (match_operand:XF 0 "general_operand" "=f")
7706 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7707 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7712 [(set (match_operand:XF 0 "general_operand" "=f")
7713 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7714 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7719 [(set (match_operand:XF 0 "general_operand" "=f")
7720 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7721 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7725 (define_insn "divxf3"
7726 [(set (match_operand:XF 0 "general_operand" "=f")
7727 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7728 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7732 if (REG_P (operands[2]))
7733 return \"fdiv%.x %2,%0\";
7734 return \"fdiv%.x %f2,%0\";
7737 (define_expand "negxf2"
7738 [(set (match_operand:XF 0 "general_operand" "")
7739 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7743 /* ??? There isn't an FPA define_insn so we could handle it here too.
7744 For now we don't (paranoia). */
7752 target = operand_subword (operands[0], 0, 1, XFmode);
7753 result = expand_binop (SImode, xor_optab,
7754 operand_subword_force (operands[1], 0, XFmode),
7755 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7759 if (result != target)
7760 emit_move_insn (result, target);
7762 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7763 operand_subword_force (operands[1], 1, XFmode));
7764 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7765 operand_subword_force (operands[1], 2, XFmode));
7767 insns = get_insns ();
7770 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7775 (define_insn "negxf2_68881"
7776 [(set (match_operand:XF 0 "general_operand" "=f")
7777 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7781 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7782 return \"fneg%.x %1,%0\";
7783 return \"fneg%.x %f1,%0\";
7786 (define_expand "absxf2"
7787 [(set (match_operand:XF 0 "general_operand" "")
7788 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7792 /* ??? There isn't an FPA define_insn so we could handle it here too.
7793 For now we don't (paranoia). */
7801 target = operand_subword (operands[0], 0, 1, XFmode);
7802 result = expand_binop (SImode, and_optab,
7803 operand_subword_force (operands[1], 0, XFmode),
7804 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7808 if (result != target)
7809 emit_move_insn (result, target);
7811 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7812 operand_subword_force (operands[1], 1, XFmode));
7813 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7814 operand_subword_force (operands[1], 2, XFmode));
7816 insns = get_insns ();
7819 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7824 (define_insn "absxf2_68881"
7825 [(set (match_operand:XF 0 "general_operand" "=f")
7826 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7830 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7831 return \"fabs%.x %1,%0\";
7832 return \"fabs%.x %f1,%0\";
7835 (define_insn "sqrtxf2"
7836 [(set (match_operand:XF 0 "general_operand" "=f")
7837 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7841 (define_insn "sinsf2"
7842 [(set (match_operand:SF 0 "general_operand" "=f")
7843 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7844 "TARGET_68881 && flag_fast_math"
7847 if (FP_REG_P (operands[1]))
7848 return \"fsin%.x %1,%0\";
7850 return \"fsin%.s %1,%0\";
7853 (define_insn "sindf2"
7854 [(set (match_operand:DF 0 "general_operand" "=f")
7855 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7856 "TARGET_68881 && flag_fast_math"
7859 if (FP_REG_P (operands[1]))
7860 return \"fsin%.x %1,%0\";
7862 return \"fsin%.d %1,%0\";
7865 (define_insn "sinxf2"
7866 [(set (match_operand:XF 0 "general_operand" "=f")
7867 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7868 "TARGET_68881 && flag_fast_math"
7871 (define_insn "cossf2"
7872 [(set (match_operand:SF 0 "general_operand" "=f")
7873 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7874 "TARGET_68881 && flag_fast_math"
7877 if (FP_REG_P (operands[1]))
7878 return \"fcos%.x %1,%0\";
7880 return \"fcos%.s %1,%0\";
7883 (define_insn "cosdf2"
7884 [(set (match_operand:DF 0 "general_operand" "=f")
7885 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7886 "TARGET_68881 && flag_fast_math"
7889 if (FP_REG_P (operands[1]))
7890 return \"fcos%.x %1,%0\";
7892 return \"fcos%.d %1,%0\";
7895 (define_insn "cosxf2"
7896 [(set (match_operand:XF 0 "general_operand" "=f")
7897 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7898 "TARGET_68881 && flag_fast_math"