1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
51 ;;- Immediate Floating point operator constraints
52 ;;- 'G' a floating point constant that is *NOT* one of the standard
53 ;; 68881 constant values (to force calling output_move_const_double
54 ;; to get it from rom if it is a 68881 constant).
56 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
59 ;;- Immediate integer operand constraints:
61 ;;- 'J' -32768 .. 32767
62 ;;- 'K' all integers EXCEPT -128 .. 127
64 ;;- 'M' all integers EXCEPT -256 .. 255
70 ;;- "%." size separator ("." or "") move%.l d0,d1
71 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
72 ;;- "%-" push operand "sp@-" move%.l d0,%-
73 ;;- "%+" pop operand "sp@+" move%.l d0,%+
74 ;;- "%@" top of stack "sp@" move%.l d0,%@
75 ;;- "%!" fpcr register
76 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
77 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;;- Information about 68040 port.
81 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
82 ;;- be emulated in software by the OS. It is faster to avoid these
83 ;;- instructions and issue a library call rather than trapping into
84 ;;- the kernel. The affected instructions are fintrz and fscale. The
85 ;;- TARGET_68040 flag turns the use of the opcodes off.
87 ;;- The '040 also implements a set of new floating-point instructions
88 ;;- which specify the rounding precision in the opcode. This finally
89 ;;- permit the 68k series to be truly IEEE compliant, and solves all
90 ;;- issues of excess precision accumulating in the extended registers.
91 ;;- By default, GCC does not use these instructions, since such code will
92 ;;- not run on an '030. To use these instructions, use the -m68040-only
93 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
94 ;;- you can make these instructions the default.
96 ;;- These new instructions aren't directly in the md. They are brought
97 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
100 ;;- Information about 68060 port.
102 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
103 ;;- be emulated in software by the OS. It is faster to avoid these
104 ;;- instructions and issue a library call rather than trapping into
105 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
106 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
107 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
109 ;;- Some of these insn's are composites of several m68000 op codes.
110 ;;- The assembler (or final @@??) insures that the appropriate one is
120 ;; UNSPEC_VOLATILE usage:
123 [(UNSPECV_BLOCKAGE 0)
127 [(set (match_operand:DF 0 "push_operand" "=m")
128 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
132 if (FP_REG_P (operands[1]))
133 return \"fmove%.d %f1,%0\";
134 return output_move_double (operands);
137 (define_insn "pushdi"
138 [(set (match_operand:DI 0 "push_operand" "=m")
139 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
143 return output_move_double (operands);
146 ;; We don't want to allow a constant operand for test insns because
147 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
148 ;; be folded while optimizing anyway.
150 (define_expand "tstdi"
151 [(parallel [(set (cc0)
152 (match_operand:DI 0 "nonimmediate_operand" ""))
153 (clobber (match_scratch:SI 1 ""))
154 (clobber (match_scratch:DI 2 ""))])]
156 "m68k_last_compare_had_fp_operands = 0;")
160 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
161 (clobber (match_scratch:SI 1 "=X,d"))
162 (clobber (match_scratch:DI 2 "=d,X"))]
166 if (which_alternative == 0)
170 xoperands[0] = operands[2];
171 xoperands[1] = operands[0];
172 output_move_double (xoperands);
173 cc_status.flags |= CC_REVERSED;
174 return \"neg%.l %R2\;negx%.l %2\";
176 if (find_reg_note (insn, REG_DEAD, operands[0]))
178 cc_status.flags |= CC_REVERSED;
179 return \"neg%.l %R0\;negx%.l %0\";
183 ** 'sub' clears %1, and also clears the X cc bit
184 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
185 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
187 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
190 (define_expand "tstsi"
192 (match_operand:SI 0 "nonimmediate_operand" ""))]
194 "m68k_last_compare_had_fp_operands = 0;")
198 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
202 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
203 return \"tst%.l %0\";
204 /* If you think that the 68020 does not support tstl a0,
205 reread page B-167 of the 68020 manual more carefully. */
206 /* On an address reg, cmpw may replace cmpl. */
208 return \"cmp%.w %0,%#0\";
210 return \"cmp%.w %#0,%0\";
214 ;; This can't use an address register, because comparisons
215 ;; with address registers as second operand always test the whole word.
216 (define_expand "tsthi"
218 (match_operand:HI 0 "nonimmediate_operand" ""))]
220 "m68k_last_compare_had_fp_operands = 0;")
224 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
228 (define_expand "tstqi"
230 (match_operand:QI 0 "nonimmediate_operand" ""))]
232 "m68k_last_compare_had_fp_operands = 0;")
236 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
240 (define_expand "tstsf"
242 (match_operand:SF 0 "general_operand" ""))]
246 m68k_last_compare_had_fp_operands = 1;
251 (match_operand:SF 0 "general_operand" "fdm"))]
255 cc_status.flags = CC_IN_68881;
256 if (FP_REG_P (operands[0]))
257 return \"ftst%.x %0\";
258 return \"ftst%.s %0\";
261 (define_expand "tstdf"
263 (match_operand:DF 0 "general_operand" ""))]
267 m68k_last_compare_had_fp_operands = 1;
272 (match_operand:DF 0 "general_operand" "fm"))]
276 cc_status.flags = CC_IN_68881;
277 if (FP_REG_P (operands[0]))
278 return \"ftst%.x %0\";
279 return \"ftst%.d %0\";
282 ;; compare instructions.
284 (define_expand "cmpdi"
287 (compare (match_operand:DI 0 "nonimmediate_operand" "")
288 (match_operand:DI 1 "general_operand" "")))
289 (clobber (match_dup 2))])]
291 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
295 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
296 (match_operand:DI 2 "general_operand" "d,0")))
297 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
301 if (rtx_equal_p (operands[0], operands[1]))
302 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
305 cc_status.flags |= CC_REVERSED;
306 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
310 ;; This is the second "hook" for PIC code (in addition to movsi). See
311 ;; comment of movsi for a description of PIC handling.
312 (define_expand "cmpsi"
314 (compare (match_operand:SI 0 "nonimmediate_operand" "")
315 (match_operand:SI 1 "general_operand" "")))]
319 m68k_last_compare_had_fp_operands = 0;
320 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
322 /* The source is an address which requires PIC relocation.
323 Call legitimize_pic_address with the source, mode, and a relocation
324 register (a new pseudo, or the final destination if reload_in_progress
325 is set). Then fall through normally */
326 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
327 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
331 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
334 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
335 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
339 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
341 return \"cmpm%.l %0,%1\";
343 return \"cmpm%.l %1,%0\";
345 if (REG_P (operands[1])
346 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
347 { cc_status.flags |= CC_REVERSED;
349 return \"cmp%.l %d1,%d0\";
351 return \"cmp%.l %d0,%d1\";
354 if (ADDRESS_REG_P (operands[0])
355 && GET_CODE (operands[1]) == CONST_INT
356 && INTVAL (operands[1]) < 0x8000
357 && INTVAL (operands[1]) >= -0x8000)
360 return \"cmp%.w %0,%1\";
362 return \"cmp%.w %1,%0\";
366 return \"cmp%.l %d0,%d1\";
368 return \"cmp%.l %d1,%d0\";
374 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
375 (match_operand:SI 1 "general_operand" "r,mrKs")))]
379 if (REG_P (operands[1])
380 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
381 { cc_status.flags |= CC_REVERSED;
383 return \"cmp%.l %d1,%d0\";
385 return \"cmp%.l %d0,%d1\";
389 return \"cmp%.l %d0,%d1\";
391 return \"cmp%.l %d1,%d0\";
395 (define_expand "cmphi"
397 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
398 (match_operand:HI 1 "general_src_operand" "")))]
400 "m68k_last_compare_had_fp_operands = 0;")
404 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
405 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
409 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
411 return \"cmpm%.w %0,%1\";
413 return \"cmpm%.w %1,%0\";
415 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
416 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
417 { cc_status.flags |= CC_REVERSED;
419 return \"cmp%.w %d1,%d0\";
421 return \"cmp%.w %d0,%d1\";
425 return \"cmp%.w %d0,%d1\";
427 return \"cmp%.w %d1,%d0\";
431 (define_expand "cmpqi"
433 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
434 (match_operand:QI 1 "general_src_operand" "")))]
436 "m68k_last_compare_had_fp_operands = 0;")
440 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
441 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
445 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
447 return \"cmpm%.b %0,%1\";
449 return \"cmpm%.b %1,%0\";
451 if (REG_P (operands[1])
452 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
453 { cc_status.flags |= CC_REVERSED;
455 return \"cmp%.b %d1,%d0\";
457 return \"cmp%.b %d0,%d1\";
461 return \"cmp%.b %d0,%d1\";
463 return \"cmp%.b %d1,%d0\";
467 (define_expand "cmpdf"
469 (compare (match_operand:DF 0 "general_operand" "")
470 (match_operand:DF 1 "general_operand" "")))]
474 m68k_last_compare_had_fp_operands = 1;
479 (compare (match_operand:DF 0 "general_operand" "f,mG")
480 (match_operand:DF 1 "general_operand" "fmG,f")))]
484 cc_status.flags = CC_IN_68881;
486 if (REG_P (operands[0]))
488 if (REG_P (operands[1]))
489 return \"fcmp%.x %0,%1\";
491 return \"fcmp%.d %0,%f1\";
493 cc_status.flags |= CC_REVERSED;
494 return \"fcmp%.d %1,%f0\";
496 if (REG_P (operands[0]))
498 if (REG_P (operands[1]))
499 return \"fcmp%.x %1,%0\";
501 return \"fcmp%.d %f1,%0\";
503 cc_status.flags |= CC_REVERSED;
504 return \"fcmp%.d %f0,%1\";
508 (define_expand "cmpsf"
510 (compare (match_operand:SF 0 "general_operand" "")
511 (match_operand:SF 1 "general_operand" "")))]
515 m68k_last_compare_had_fp_operands = 1;
520 (compare (match_operand:SF 0 "general_operand" "f,mdG")
521 (match_operand:SF 1 "general_operand" "fmdG,f")))]
525 cc_status.flags = CC_IN_68881;
527 if (FP_REG_P (operands[0]))
529 if (FP_REG_P (operands[1]))
530 return \"fcmp%.x %0,%1\";
532 return \"fcmp%.s %0,%f1\";
534 cc_status.flags |= CC_REVERSED;
535 return \"fcmp%.s %1,%f0\";
537 if (FP_REG_P (operands[0]))
539 if (FP_REG_P (operands[1]))
540 return \"fcmp%.x %1,%0\";
542 return \"fcmp%.s %f1,%0\";
544 cc_status.flags |= CC_REVERSED;
545 return \"fcmp%.s %f0,%1\";
549 ;; Recognizers for btst instructions.
551 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
552 ;; specified as a constant, so we must disable all patterns that may extract
553 ;; from a MEM at a constant bit position if we can't use this as a constraint.
556 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
558 (minus:SI (const_int 7)
559 (match_operand:SI 1 "general_operand" "di"))))]
561 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
563 ;; This is the same as the above pattern except for the constraints. The 'i'
567 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
569 (minus:SI (const_int 7)
570 (match_operand:SI 1 "general_operand" "d"))))]
572 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
575 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
577 (minus:SI (const_int 31)
578 (match_operand:SI 1 "general_operand" "di"))))]
580 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
582 ;; The following two patterns are like the previous two
583 ;; except that they use the fact that bit-number operands
584 ;; are automatically masked to 3 or 5 bits.
587 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
589 (minus:SI (const_int 7)
591 (match_operand:SI 1 "register_operand" "d")
594 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
597 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
599 (minus:SI (const_int 31)
601 (match_operand:SI 1 "register_operand" "d")
604 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
606 ;; Nonoffsettable mem refs are ok in this one pattern
607 ;; since we don't try to adjust them.
609 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
611 (match_operand:SI 1 "const_int_operand" "n")))]
612 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
615 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
616 return output_btst (operands, operands[1], operands[0], insn, 7);
620 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
622 (match_operand:SI 1 "const_int_operand" "n")))]
626 if (GET_CODE (operands[0]) == MEM)
628 operands[0] = adjust_address (operands[0], QImode,
629 INTVAL (operands[1]) / 8);
630 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
631 return output_btst (operands, operands[1], operands[0], insn, 7);
633 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
634 return output_btst (operands, operands[1], operands[0], insn, 31);
637 ;; This is the same as the above pattern except for the constraints.
638 ;; The 'o' has been replaced with 'Q'.
641 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
643 (match_operand:SI 1 "const_int_operand" "n")))]
647 if (GET_CODE (operands[0]) == MEM)
649 operands[0] = adjust_address (operands[0], QImode,
650 INTVAL (operands[1]) / 8);
651 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
652 return output_btst (operands, operands[1], operands[0], insn, 7);
654 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
655 return output_btst (operands, operands[1], operands[0], insn, 31);
661 ;; A special case in which it is not desirable
662 ;; to reload the constant into a data register.
663 (define_insn "pushexthisi_const"
664 [(set (match_operand:SI 0 "push_operand" "=m")
665 (match_operand:SI 1 "const_int_operand" "J"))]
666 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
669 if (operands[1] == const0_rtx)
670 return \"clr%.l %0\";
675 ;(define_insn "swapsi"
676 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
677 ; (match_operand:SI 1 "general_operand" "+r"))
678 ; (set (match_dup 1) (match_dup 0))]
682 ;; Special case of fullword move when source is zero.
683 ;; The reason this is special is to avoid loading a zero
684 ;; into a data reg with moveq in order to store it elsewhere.
686 (define_insn "movsi_const0"
687 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
689 ;; clr insns on 68000 read before writing.
690 ;; This isn't so on the 68010, but we have no TARGET_68010.
691 "((TARGET_68020 || TARGET_COLDFIRE)
692 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
695 if (ADDRESS_REG_P (operands[0]))
697 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
698 if (!TARGET_68040 && !TARGET_68060)
699 return \"sub%.l %0,%0\";
704 /* Many SGS assemblers croak on size specifiers for constants. */
707 return \"lea 0.w,%0\";
710 return \"lea 0:w,%0\";
714 /* moveq is faster on the 68000. */
715 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE))
716 return \"moveq %#0,%0\";
717 return \"clr%.l %0\";
720 ;; General case of fullword move.
722 ;; This is the main "hook" for PIC code. When generating
723 ;; PIC, movsi is responsible for determining when the source address
724 ;; needs PIC relocation and appropriately calling legitimize_pic_address
725 ;; to perform the actual relocation.
727 ;; In both the PIC and non-PIC cases the patterns generated will
728 ;; matched by the next define_insn.
729 (define_expand "movsi"
730 [(set (match_operand:SI 0 "nonimmediate_operand" "")
731 (match_operand:SI 1 "general_operand" ""))]
735 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
737 /* The source is an address which requires PIC relocation.
738 Call legitimize_pic_address with the source, mode, and a relocation
739 register (a new pseudo, or the final destination if reload_in_progress
740 is set). Then fall through normally */
741 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
742 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
744 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
746 /* Don't allow writes to memory except via a register;
747 the m68k doesn't consider PC-relative addresses to be writable. */
748 if (symbolic_operand (operands[0], SImode))
749 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
750 else if (GET_CODE (operands[0]) == MEM
751 && symbolic_operand (XEXP (operands[0], 0), SImode))
752 operands[0] = gen_rtx (MEM, SImode,
753 force_reg (SImode, XEXP (operands[0], 0)));
757 ;; General case of fullword move. The register constraints
758 ;; force integer constants in range for a moveq to be reloaded
759 ;; if they are headed for memory.
761 ;; Notes: make sure no alternative allows g vs g.
762 ;; We don't allow f-regs since fixed point cannot go in them.
763 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
764 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
769 return output_move_simode (operands);
773 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
774 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
776 "* return output_move_simode (operands);")
778 ;; Special case of fullword move, where we need to get a non-GOT PIC
779 ;; reference into an address register.
781 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
782 (match_operand:SI 1 "pcrel_address" ""))]
786 if (push_operand (operands[0], SImode))
788 return \"lea %a1,%0\";
791 (define_expand "movhi"
792 [(set (match_operand:HI 0 "nonimmediate_operand" "")
793 (match_operand:HI 1 "general_operand" ""))]
798 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
799 (match_operand:HI 1 "general_src_operand" "gS"))]
801 "* return output_move_himode (operands);")
804 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
805 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
807 "* return output_move_himode (operands);")
809 (define_expand "movstricthi"
810 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
811 (match_operand:HI 1 "general_src_operand" ""))]
816 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
817 (match_operand:HI 1 "general_src_operand" "rmSn"))]
819 "* return output_move_stricthi (operands);")
822 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
823 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
825 "* return output_move_stricthi (operands);")
827 (define_expand "movqi"
828 [(set (match_operand:QI 0 "nonimmediate_operand" "")
829 (match_operand:QI 1 "general_src_operand" ""))]
834 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
835 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
837 "* return output_move_qimode (operands);")
840 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
841 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
843 "* return output_move_qimode (operands);")
845 (define_expand "movstrictqi"
846 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
847 (match_operand:QI 1 "general_src_operand" ""))]
852 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
853 (match_operand:QI 1 "general_src_operand" "dmSn"))]
855 "* return output_move_strictqi (operands);")
858 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
859 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
861 "* return output_move_strictqi (operands);")
863 (define_expand "pushqi1"
864 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
865 (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
866 (match_operand:QI 0 "general_operand" ""))]
870 (define_expand "movsf"
871 [(set (match_operand:SF 0 "nonimmediate_operand" "")
872 (match_operand:SF 1 "general_operand" ""))]
877 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
878 (match_operand:SF 1 "general_operand" "rmfF"))]
882 if (FP_REG_P (operands[0]))
884 if (FP_REG_P (operands[1]))
885 return \"f%$move%.x %1,%0\";
886 else if (ADDRESS_REG_P (operands[1]))
887 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
888 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
889 return output_move_const_single (operands);
890 return \"f%$move%.s %f1,%0\";
892 if (FP_REG_P (operands[1]))
894 if (ADDRESS_REG_P (operands[0]))
895 return \"fmove%.s %1,%-\;move%.l %+,%0\";
896 return \"fmove%.s %f1,%0\";
898 if (operands[1] == CONST0_RTX (SFmode)
899 /* clr insns on 68000 read before writing.
900 This isn't so on the 68010, but we have no TARGET_68010. */
901 && ((TARGET_68020 || TARGET_COLDFIRE)
902 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
904 if (ADDRESS_REG_P (operands[0]))
906 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
907 if (!TARGET_68040 && !TARGET_68060)
908 return \"sub%.l %0,%0\";
913 /* Many SGS assemblers croak on size specifiers for constants. */
916 return \"lea 0.w,%0\";
919 return \"lea 0:w,%0\";
923 /* moveq is faster on the 68000. */
924 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
926 return \"moveq %#0,%0\";
928 return \"clr%.l %0\";
930 return \"move%.l %1,%0\";
934 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
935 (match_operand:SF 1 "general_operand" "g,r"))]
937 "* return \"move%.l %1,%0\";")
939 (define_expand "movdf"
940 [(set (match_operand:DF 0 "nonimmediate_operand" "")
941 (match_operand:DF 1 "general_operand" ""))]
946 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
947 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
948 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
949 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
953 if (FP_REG_P (operands[0]))
955 if (FP_REG_P (operands[1]))
956 return \"f%&move%.x %1,%0\";
957 if (REG_P (operands[1]))
960 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
961 output_asm_insn (\"move%.l %1,%-\", xoperands);
962 output_asm_insn (\"move%.l %1,%-\", operands);
963 return \"f%&move%.d %+,%0\";
965 if (GET_CODE (operands[1]) == CONST_DOUBLE)
966 return output_move_const_double (operands);
967 return \"f%&move%.d %f1,%0\";
969 else if (FP_REG_P (operands[1]))
971 if (REG_P (operands[0]))
973 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
974 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
975 return \"move%.l %+,%0\";
978 return \"fmove%.d %f1,%0\";
980 return output_move_double (operands);
984 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
985 (match_operand:DF 1 "general_operand" "g,r"))]
987 "* return output_move_double (operands);")
989 ;; ??? The XFmode patterns are schizophrenic about whether constants are
990 ;; allowed. Most but not all have predicates and constraint that disallow
991 ;; constants. Most but not all have output templates that handle constants.
992 ;; See also LEGITIMATE_CONSTANT_P.
994 (define_expand "movxf"
995 [(set (match_operand:XF 0 "nonimmediate_operand" "")
996 (match_operand:XF 1 "general_operand" ""))]
1000 /* We can't rewrite operands during reload. */
1001 if (! reload_in_progress)
1003 if (CONSTANT_P (operands[1]))
1005 operands[1] = force_const_mem (XFmode, operands[1]);
1006 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
1007 operands[1] = adjust_address (operands[1], XFmode, 0);
1009 if (flag_pic && TARGET_PCREL)
1011 /* Don't allow writes to memory except via a register; the
1012 m68k doesn't consider PC-relative addresses to be writable. */
1013 if (GET_CODE (operands[0]) == MEM
1014 && symbolic_operand (XEXP (operands[0], 0), SImode))
1015 operands[0] = gen_rtx (MEM, XFmode,
1016 force_reg (SImode, XEXP (operands[0], 0)));
1022 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1023 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1027 if (FP_REG_P (operands[0]))
1029 if (FP_REG_P (operands[1]))
1030 return \"fmove%.x %1,%0\";
1031 if (REG_P (operands[1]))
1034 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1035 output_asm_insn (\"move%.l %1,%-\", xoperands);
1036 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1037 output_asm_insn (\"move%.l %1,%-\", xoperands);
1038 output_asm_insn (\"move%.l %1,%-\", operands);
1039 return \"fmove%.x %+,%0\";
1041 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1042 return \"fmove%.x %1,%0\";
1043 return \"fmove%.x %f1,%0\";
1045 if (FP_REG_P (operands[1]))
1047 if (REG_P (operands[0]))
1049 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1050 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1051 output_asm_insn (\"move%.l %+,%0\", operands);
1052 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1053 return \"move%.l %+,%0\";
1055 /* Must be memory destination. */
1056 return \"fmove%.x %f1,%0\";
1058 return output_move_double (operands);
1063 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1064 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1065 "! TARGET_68881 && ! TARGET_COLDFIRE"
1068 if (FP_REG_P (operands[0]))
1070 if (FP_REG_P (operands[1]))
1071 return \"fmove%.x %1,%0\";
1072 if (REG_P (operands[1]))
1075 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1076 output_asm_insn (\"move%.l %1,%-\", xoperands);
1077 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1078 output_asm_insn (\"move%.l %1,%-\", xoperands);
1079 output_asm_insn (\"move%.l %1,%-\", operands);
1080 return \"fmove%.x %+,%0\";
1082 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1083 return \"fmove%.x %1,%0\";
1084 return \"fmove%.x %f1,%0\";
1086 if (FP_REG_P (operands[1]))
1088 if (REG_P (operands[0]))
1090 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1091 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1092 output_asm_insn (\"move%.l %+,%0\", operands);
1093 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1094 return \"move%.l %+,%0\";
1097 return \"fmove%.x %f1,%0\";
1099 return output_move_double (operands);
1104 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1105 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1106 "! TARGET_68881 && TARGET_COLDFIRE"
1107 "* return output_move_double (operands);")
1109 (define_expand "movdi"
1110 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1111 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1112 (match_operand:DI 1 "general_operand" ""))]
1116 ;; movdi can apply to fp regs in some cases
1118 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1119 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1120 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1121 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1122 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1123 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1124 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1128 if (FP_REG_P (operands[0]))
1130 if (FP_REG_P (operands[1]))
1131 return \"fmove%.x %1,%0\";
1132 if (REG_P (operands[1]))
1135 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1136 output_asm_insn (\"move%.l %1,%-\", xoperands);
1137 output_asm_insn (\"move%.l %1,%-\", operands);
1138 return \"fmove%.d %+,%0\";
1140 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1141 return output_move_const_double (operands);
1142 return \"fmove%.d %f1,%0\";
1144 else if (FP_REG_P (operands[1]))
1146 if (REG_P (operands[0]))
1148 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1149 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1150 return \"move%.l %+,%0\";
1153 return \"fmove%.d %f1,%0\";
1155 return output_move_double (operands);
1159 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1160 (match_operand:DI 1 "general_operand" "g,r"))]
1162 "* return output_move_double (operands);")
1164 ;; Thus goes after the move instructions
1165 ;; because the move instructions are better (require no spilling)
1166 ;; when they can apply. It goes before the add/sub insns
1167 ;; so we will prefer it to them.
1169 (define_insn "pushasi"
1170 [(set (match_operand:SI 0 "push_operand" "=m")
1171 (match_operand:SI 1 "address_operand" "p"))]
1175 ;; truncation instructions
1176 (define_insn "truncsiqi2"
1177 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1179 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1183 if (GET_CODE (operands[0]) == REG)
1185 /* Must clear condition codes, since the move.l bases them on
1186 the entire 32 bits, not just the desired 8 bits. */
1188 return \"move%.l %1,%0\";
1190 if (GET_CODE (operands[1]) == MEM)
1191 operands[1] = adjust_address (operands[1], QImode, 3);
1192 return \"move%.b %1,%0\";
1195 (define_insn "trunchiqi2"
1196 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1198 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1202 if (GET_CODE (operands[0]) == REG
1203 && (GET_CODE (operands[1]) == MEM
1204 || GET_CODE (operands[1]) == CONST_INT))
1206 /* Must clear condition codes, since the move.w bases them on
1207 the entire 16 bits, not just the desired 8 bits. */
1209 return \"move%.w %1,%0\";
1211 if (GET_CODE (operands[0]) == REG)
1213 /* Must clear condition codes, since the move.l bases them on
1214 the entire 32 bits, not just the desired 8 bits. */
1216 return \"move%.l %1,%0\";
1218 if (GET_CODE (operands[1]) == MEM)
1219 operands[1] = adjust_address (operands[1], QImode, 1);
1220 return \"move%.b %1,%0\";
1223 (define_insn "truncsihi2"
1224 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1226 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1230 if (GET_CODE (operands[0]) == REG)
1232 /* Must clear condition codes, since the move.l bases them on
1233 the entire 32 bits, not just the desired 8 bits. */
1235 return \"move%.l %1,%0\";
1237 if (GET_CODE (operands[1]) == MEM)
1238 operands[1] = adjust_address (operands[1], QImode, 2);
1239 return \"move%.w %1,%0\";
1242 ;; zero extension instructions
1244 (define_insn "zero_extendqidi2"
1245 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1246 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1251 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1252 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1255 (define_insn "zero_extendhidi2"
1256 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1257 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1262 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1263 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1266 ;; this is the canonical form for (lshiftrt:DI x 32)
1267 (define_expand "zero_extendsidi2"
1268 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1269 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1273 (define_insn "*zero_extendsidi2_cf"
1274 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
1275 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
1280 if (GET_CODE (operands[0]) == REG)
1281 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1282 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1283 return \"move%.l %1,%0\;clr%.l %0\";
1284 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1285 return \"clr%.l %0\;move%.l %1,%0\";
1287 operands[2] = adjust_address (operands[0], SImode, 4);
1288 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1289 || REGNO (operands[1]) != REGNO (operands[2]))
1290 output_asm_insn (\"move%.l %1,%2\", operands);
1291 if (ADDRESS_REG_P (operands[0]))
1292 return \"sub%.l %0,%0\";
1294 return \"clr%.l %0\";
1297 (define_insn "*zero_extendsidi2"
1298 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1299 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1304 if (GET_CODE (operands[0]) == REG)
1305 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1306 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1307 return \"move%.l %1,%0\;clr%.l %0\";
1308 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1309 return \"clr%.l %0\;move%.l %1,%0\";
1311 operands[2] = adjust_address (operands[0], SImode, 4);
1312 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1313 || REGNO (operands[1]) != REGNO (operands[2]))
1314 output_asm_insn (\"move%.l %1,%2\", operands);
1315 if (ADDRESS_REG_P (operands[0]))
1316 return \"sub%.l %0,%0\";
1318 return \"clr%.l %0\";
1321 (define_expand "zero_extendhisi2"
1322 [(set (match_operand:SI 0 "register_operand" "")
1324 (set (strict_low_part (match_dup 2))
1325 (match_operand:HI 1 "general_operand" ""))]
1329 operands[1] = make_safe_from (operands[1], operands[0]);
1330 operands[2] = gen_lowpart_SUBREG (HImode, operands[0]);
1333 (define_expand "zero_extendqihi2"
1334 [(set (match_operand:HI 0 "register_operand" "")
1336 (set (strict_low_part (match_dup 2))
1337 (match_operand:QI 1 "general_operand" ""))]
1341 operands[1] = make_safe_from (operands[1], operands[0]);
1342 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1345 (define_expand "zero_extendqisi2"
1346 [(set (match_operand:SI 0 "register_operand" "")
1348 (set (strict_low_part (match_dup 2))
1349 (match_operand:QI 1 "general_operand" ""))]
1353 operands[1] = make_safe_from (operands[1], operands[0]);
1354 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1357 ;; Patterns to recognize zero-extend insns produced by the combiner.
1358 ;; We don't allow both operands in memory, because of aliasing problems.
1359 ;; Explicitly disallow two memory operands via the condition since reloading
1360 ;; of this case will result in worse code than the uncombined patterns.
1363 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d<")
1364 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1365 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1368 if (DATA_REG_P (operands[0]))
1370 if (GET_CODE (operands[1]) == REG
1371 && REGNO (operands[0]) == REGNO (operands[1]))
1372 return \"and%.l %#0xFFFF,%0\";
1373 if (reg_mentioned_p (operands[0], operands[1]))
1374 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1375 return \"clr%.l %0\;move%.w %1,%0\";
1377 else if (GET_CODE (operands[0]) == MEM
1378 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1379 return \"move%.w %1,%0\;clr%.w %0\";
1380 else if (GET_CODE (operands[0]) == MEM
1381 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1382 return \"clr%.w %0\;move%.w %1,%0\";
1385 output_asm_insn (\"clr%.w %0\", operands);
1386 operands[0] = adjust_address (operands[0], HImode, 2);
1387 return \"move%.w %1,%0\";
1392 [(set (match_operand:HI 0 "nonimmediate_operand" "=do<>,d")
1393 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1394 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1397 if (DATA_REG_P (operands[0]))
1399 if (GET_CODE (operands[1]) == REG
1400 && REGNO (operands[0]) == REGNO (operands[1]))
1401 return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1402 if (reg_mentioned_p (operands[0], operands[1]))
1403 return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1404 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1405 return \"clr%.w %0\;move%.b %1,%0\";
1407 else if (GET_CODE (operands[0]) == MEM
1408 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1410 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1411 == STACK_POINTER_REGNUM)
1413 output_asm_insn (\"clr%.w %-\", operands);
1414 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1415 plus_constant (stack_pointer_rtx, 1));
1416 return \"move%.b %1,%0\";
1419 return \"move%.b %1,%0\;clr%.b %0\";
1421 else if (GET_CODE (operands[0]) == MEM
1422 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1423 return \"clr%.b %0\;move%.b %1,%0\";
1426 output_asm_insn (\"clr%.b %0\", operands);
1427 operands[0] = adjust_address (operands[0], QImode, 1);
1428 return \"move%.b %1,%0\";
1433 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d")
1434 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1435 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1438 if (DATA_REG_P (operands[0]))
1440 if (GET_CODE (operands[1]) == REG
1441 && REGNO (operands[0]) == REGNO (operands[1]))
1442 return \"and%.l %#0xFF,%0\";
1443 if (reg_mentioned_p (operands[0], operands[1]))
1444 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1445 return \"clr%.l %0\;move%.b %1,%0\";
1447 else if (GET_CODE (operands[0]) == MEM
1448 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1450 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1453 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1455 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1458 return \"clrl %0@-\;moveb %1,%0@(3)\";
1461 else if (GET_CODE (operands[0]) == MEM
1462 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1464 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1467 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1469 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1472 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1477 output_asm_insn (\"clr%.l %0\", operands);
1478 operands[0] = adjust_address (operands[0], QImode, 3);
1479 return \"move%.b %1,%0\";
1483 ;; sign extension instructions
1485 (define_insn "extendqidi2"
1486 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1487 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1492 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1493 if (TARGET_68020 || TARGET_COLDFIRE)
1494 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1496 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1499 (define_insn "extendhidi2"
1500 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1502 (match_operand:HI 1 "general_src_operand" "rmS")))]
1507 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1508 if (TARGET_68020 || TARGET_COLDFIRE)
1509 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1511 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1514 (define_insn "extendsidi2"
1515 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1517 (match_operand:SI 1 "general_operand" "rm")))]
1522 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1523 if (TARGET_68020 || TARGET_COLDFIRE)
1524 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1526 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1529 ;; Special case when one can avoid register clobbering, copy and test
1530 ;; Maybe there is a way to make that the general case, by forcing the
1531 ;; result of the SI tree to be in the lower register of the DI target
1533 (define_insn "extendplussidi"
1534 [(set (match_operand:DI 0 "register_operand" "=d")
1535 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1536 (match_operand:SI 2 "general_operand" "rmn"))))]
1541 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1542 if (GET_CODE (operands[1]) == CONST_INT
1543 && (unsigned) INTVAL (operands[1]) > 8)
1545 rtx tmp = operands[1];
1547 operands[1] = operands[2];
1550 if (GET_CODE (operands[1]) == REG
1551 && REGNO (operands[1]) == REGNO (operands[3]))
1552 output_asm_insn (\"add%.l %2,%3\", operands);
1554 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1555 if (TARGET_68020 || TARGET_COLDFIRE)
1556 return \"smi %0\;extb%.l %0\";
1558 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1561 (define_insn "extendhisi2"
1562 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1564 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1568 if (ADDRESS_REG_P (operands[0]))
1569 return \"move%.w %1,%0\";
1570 return \"ext%.l %0\";
1573 (define_insn "extendqihi2"
1574 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1575 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1579 (define_insn "extendqisi2"
1580 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1581 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1582 "TARGET_68020 || TARGET_COLDFIRE"
1585 ;; Conversions between float and double.
1587 (define_expand "extendsfdf2"
1588 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1590 (match_operand:SF 1 "general_operand" "")))]
1595 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1597 (match_operand:SF 1 "general_operand" "f,dmF")))]
1601 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1603 if (REGNO (operands[0]) == REGNO (operands[1]))
1605 /* Extending float to double in an fp-reg is a no-op.
1606 NOTICE_UPDATE_CC has already assumed that the
1607 cc will be set. So cancel what it did. */
1608 cc_status = cc_prev_status;
1611 return \"f%&move%.x %1,%0\";
1613 if (FP_REG_P (operands[0]))
1614 return \"f%&move%.s %f1,%0\";
1615 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1617 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1618 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1619 return \"move%.l %+,%0\";
1621 return \"fmove%.d %f1,%0\";
1624 ;; This cannot output into an f-reg because there is no way to be
1625 ;; sure of truncating in that case.
1626 (define_expand "truncdfsf2"
1627 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1629 (match_operand:DF 1 "general_operand" "")))]
1633 ;; On the '040 we can truncate in a register accurately and easily.
1635 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1637 (match_operand:DF 1 "general_operand" "fmG")))]
1641 if (FP_REG_P (operands[1]))
1642 return \"f%$move%.x %1,%0\";
1643 return \"f%$move%.d %f1,%0\";
1647 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1649 (match_operand:DF 1 "general_operand" "f")))]
1653 ;; Conversion between fixed point and floating point.
1654 ;; Note that among the fix-to-float insns
1655 ;; the ones that start with SImode come first.
1656 ;; That is so that an operand that is a CONST_INT
1657 ;; (and therefore lacks a specific machine mode).
1658 ;; will be recognized as SImode (which is always valid)
1659 ;; rather than as QImode or HImode.
1661 (define_expand "floatsisf2"
1662 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1663 (float:SF (match_operand:SI 1 "general_operand" "")))]
1668 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1669 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1673 (define_expand "floatsidf2"
1674 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1675 (float:DF (match_operand:SI 1 "general_operand" "")))]
1680 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1681 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1685 (define_insn "floathisf2"
1686 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1687 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1691 (define_insn "floathidf2"
1692 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1693 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1697 (define_insn "floatqisf2"
1698 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1699 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1703 (define_insn "floatqidf2"
1704 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1705 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1709 ;; New routines to convert floating-point values to integers
1710 ;; to be used on the '040. These should be faster than trapping
1711 ;; into the kernel to emulate fintrz. They should also be faster
1712 ;; than calling the subroutines fixsfsi or fixdfsi.
1714 (define_insn "fix_truncdfsi2"
1715 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1716 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1717 (clobber (match_scratch:SI 2 "=d"))
1718 (clobber (match_scratch:SI 3 "=d"))]
1719 "TARGET_68881 && TARGET_68040"
1723 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1726 (define_insn "fix_truncdfhi2"
1727 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1728 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1729 (clobber (match_scratch:SI 2 "=d"))
1730 (clobber (match_scratch:SI 3 "=d"))]
1731 "TARGET_68881 && TARGET_68040"
1735 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1738 (define_insn "fix_truncdfqi2"
1739 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1740 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1741 (clobber (match_scratch:SI 2 "=d"))
1742 (clobber (match_scratch:SI 3 "=d"))]
1743 "TARGET_68881 && TARGET_68040"
1747 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1750 ;; Convert a float to a float whose value is an integer.
1751 ;; This is the first stage of converting it to an integer type.
1753 (define_insn "ftruncdf2"
1754 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1755 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1756 "TARGET_68881 && !TARGET_68040"
1759 if (FP_REG_P (operands[1]))
1760 return \"fintrz%.x %f1,%0\";
1761 return \"fintrz%.d %f1,%0\";
1764 (define_insn "ftruncsf2"
1765 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1766 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1767 "TARGET_68881 && !TARGET_68040"
1770 if (FP_REG_P (operands[1]))
1771 return \"fintrz%.x %f1,%0\";
1772 return \"fintrz%.s %f1,%0\";
1775 ;; Convert a float whose value is an integer
1776 ;; to an actual integer. Second stage of converting float to integer type.
1777 (define_insn "fixsfqi2"
1778 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1779 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1783 (define_insn "fixsfhi2"
1784 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1785 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1789 (define_insn "fixsfsi2"
1790 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1791 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1795 (define_insn "fixdfqi2"
1796 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1797 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1801 (define_insn "fixdfhi2"
1802 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1803 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1807 (define_insn "fixdfsi2"
1808 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1809 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1815 (define_insn "adddi_lshrdi_63"
1816 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1817 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1820 (clobber (match_scratch:SI 2 "=d"))]
1824 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1825 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1827 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1828 if (GET_CODE (operands[1]) == REG)
1829 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1830 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1831 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1832 operands[4] = operands[1];
1834 operands[4] = adjust_address (operands[1], SImode, 4);
1835 if (GET_CODE (operands[1]) == MEM
1836 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1837 output_asm_insn (\"move%.l %4,%3\", operands);
1838 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1839 if (TARGET_68020 || TARGET_COLDFIRE)
1840 output_asm_insn (\"extb%.l %2\", operands);
1842 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1843 if (GET_CODE (operands[1]) != MEM
1844 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1845 output_asm_insn (\"move%.l %4,%3\", operands);
1846 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1849 (define_insn "adddi_sexthishl32"
1850 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
1851 (plus:DI (ashift:DI (sign_extend:DI
1852 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1854 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1855 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1860 if (ADDRESS_REG_P (operands[0]))
1861 return \"add%.w %1,%0\";
1862 else if (ADDRESS_REG_P (operands[3]))
1863 return \"move%.w %1,%3\;add%.l %3,%0\";
1865 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1868 (define_insn "adddi_dilshr32"
1869 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
1870 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1871 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1872 ;; (const_int 32))))]
1873 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
1875 (match_operand:DI 2 "general_operand" "0,0")))]
1880 if (GET_CODE (operands[0]) == REG)
1881 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1883 operands[2] = adjust_address (operands[0], SImode, 4);
1884 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
1887 (define_insn "adddi_dishl32"
1888 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
1889 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1890 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1891 ;; (const_int 32))))]
1892 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
1894 (match_operand:DI 2 "general_operand" "0,0")))]
1899 if (GET_CODE (operands[1]) == REG)
1900 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1902 operands[1] = adjust_address (operands[1], SImode, 4);
1903 return \"add%.l %1,%0\";
1906 (define_insn "adddi3"
1907 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
1908 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
1909 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
1910 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
1914 if (DATA_REG_P (operands[0]))
1916 if (DATA_REG_P (operands[2]))
1917 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
1918 else if (GET_CODE (operands[2]) == MEM
1919 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
1920 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
1926 if (GET_CODE (operands[2]) == REG)
1928 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
1931 else if (CONSTANT_P (operands[2]))
1932 split_double (operands[2], &high, &low);
1935 low = adjust_address (operands[2], SImode, 4);
1939 operands[1] = low, operands[2] = high;
1940 xoperands[0] = operands[3];
1941 if (GET_CODE (operands[1]) == CONST_INT
1942 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1943 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
1945 xoperands[1] = operands[2];
1947 output_asm_insn (output_move_simode (xoperands), xoperands);
1948 if (GET_CODE (operands[1]) == CONST_INT)
1950 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
1951 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
1952 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1954 operands[1] = GEN_INT (-INTVAL (operands[1]));
1955 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
1958 return \"add%.l %1,%R0\;addx%.l %3,%0\";
1961 else if (GET_CODE (operands[0]) == MEM)
1963 if (GET_CODE (operands[2]) == MEM
1964 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
1965 return \"add%.l %2,%0\;addx%.l %2,%0\";
1967 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1969 operands[1] = gen_rtx_MEM (SImode,
1970 plus_constant (XEXP(operands[0], 0), -8));
1971 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
1973 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1975 operands[1] = XEXP(operands[0], 0);
1976 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
1980 operands[1] = adjust_address (operands[0], SImode, 4);
1981 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
1988 (define_insn "addsi_lshrsi_31"
1989 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1990 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
1996 operands[2] = operands[0];
1997 operands[3] = gen_label_rtx();
1998 if (GET_CODE (operands[0]) == MEM)
2000 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2001 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2002 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2003 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2005 output_asm_insn (\"move%.l %1,%0\", operands);
2007 output_asm_insn (\"jbpl %l3\", operands);
2009 output_asm_insn (\"jpl %l3\", operands);
2011 output_asm_insn (\"addq%.l %#1,%2\", operands);
2012 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2013 CODE_LABEL_NUMBER (operands[3]));
2017 (define_expand "addsi3"
2018 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2019 (plus:SI (match_operand:SI 1 "general_operand" "")
2020 (match_operand:SI 2 "general_src_operand" "")))]
2024 ;; Note that the middle two alternatives are near-duplicates
2025 ;; in order to handle insns generated by reload.
2026 ;; This is needed since they are not themselves reloaded,
2027 ;; so commutativity won't apply to them.
2028 (define_insn "*addsi3_internal"
2029 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2030 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2031 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2035 "* return output_addsi3 (operands);")
2037 (define_insn "*addsi3_5200"
2038 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
2039 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2040 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2042 "* return output_addsi3 (operands);")
2045 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2046 (plus:SI (match_operand:SI 1 "general_operand" "0")
2048 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2052 (define_insn "addhi3"
2053 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2054 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2055 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2059 if (GET_CODE (operands[2]) == CONST_INT)
2061 /* If the constant would be a negative number when interpreted as
2062 HImode, make it negative. This is usually, but not always, done
2063 elsewhere in the compiler. First check for constants out of range,
2064 which could confuse us. */
2066 if (INTVAL (operands[2]) >= 32768)
2067 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2069 if (INTVAL (operands[2]) > 0
2070 && INTVAL (operands[2]) <= 8)
2071 return \"addq%.w %2,%0\";
2072 if (INTVAL (operands[2]) < 0
2073 && INTVAL (operands[2]) >= -8)
2075 operands[2] = GEN_INT (- INTVAL (operands[2]));
2076 return \"subq%.w %2,%0\";
2078 /* On the CPU32 it is faster to use two addqw instructions to
2079 add a small integer (8 < N <= 16) to a register.
2080 Likewise for subqw. */
2081 if (TARGET_CPU32 && REG_P (operands[0]))
2083 if (INTVAL (operands[2]) > 8
2084 && INTVAL (operands[2]) <= 16)
2086 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2087 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2089 if (INTVAL (operands[2]) < -8
2090 && INTVAL (operands[2]) >= -16)
2092 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2093 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2096 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2098 return \"lea (%c2,%0),%0\";
2100 return \"lea %0@(%c2),%0\";
2103 return \"add%.w %2,%0\";
2106 ;; These insns must use MATCH_DUP instead of the more expected
2107 ;; use of a matching constraint because the "output" here is also
2108 ;; an input, so you can't use the matching constraint. That also means
2109 ;; that you can't use the "%", so you need patterns with the matched
2110 ;; operand in both positions.
2113 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2114 (plus:HI (match_dup 0)
2115 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2119 if (GET_CODE (operands[1]) == CONST_INT)
2121 /* If the constant would be a negative number when interpreted as
2122 HImode, make it negative. This is usually, but not always, done
2123 elsewhere in the compiler. First check for constants out of range,
2124 which could confuse us. */
2126 if (INTVAL (operands[1]) >= 32768)
2127 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2129 if (INTVAL (operands[1]) > 0
2130 && INTVAL (operands[1]) <= 8)
2131 return \"addq%.w %1,%0\";
2132 if (INTVAL (operands[1]) < 0
2133 && INTVAL (operands[1]) >= -8)
2135 operands[1] = GEN_INT (- INTVAL (operands[1]));
2136 return \"subq%.w %1,%0\";
2138 /* On the CPU32 it is faster to use two addqw instructions to
2139 add a small integer (8 < N <= 16) to a register.
2140 Likewise for subqw. */
2141 if (TARGET_CPU32 && REG_P (operands[0]))
2143 if (INTVAL (operands[1]) > 8
2144 && INTVAL (operands[1]) <= 16)
2146 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2147 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2149 if (INTVAL (operands[1]) < -8
2150 && INTVAL (operands[1]) >= -16)
2152 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2153 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2156 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2158 return \"lea (%c1,%0),%0\";
2160 return \"lea %0@(%c1),%0\";
2163 return \"add%.w %1,%0\";
2167 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2168 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2173 if (GET_CODE (operands[1]) == CONST_INT)
2175 /* If the constant would be a negative number when interpreted as
2176 HImode, make it negative. This is usually, but not always, done
2177 elsewhere in the compiler. First check for constants out of range,
2178 which could confuse us. */
2180 if (INTVAL (operands[1]) >= 32768)
2181 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2183 if (INTVAL (operands[1]) > 0
2184 && INTVAL (operands[1]) <= 8)
2185 return \"addq%.w %1,%0\";
2186 if (INTVAL (operands[1]) < 0
2187 && INTVAL (operands[1]) >= -8)
2189 operands[1] = GEN_INT (- INTVAL (operands[1]));
2190 return \"subq%.w %1,%0\";
2192 /* On the CPU32 it is faster to use two addqw instructions to
2193 add a small integer (8 < N <= 16) to a register.
2194 Likewise for subqw. */
2195 if (TARGET_CPU32 && REG_P (operands[0]))
2197 if (INTVAL (operands[1]) > 8
2198 && INTVAL (operands[1]) <= 16)
2200 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2201 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2203 if (INTVAL (operands[1]) < -8
2204 && INTVAL (operands[1]) >= -16)
2206 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2207 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2210 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2212 return \"lea (%c1,%0),%0\";
2214 return \"lea %0@(%c1),%0\";
2217 return \"add%.w %1,%0\";
2220 (define_insn "addqi3"
2221 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2222 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2223 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2227 if (GET_CODE (operands[2]) == CONST_INT)
2229 if (INTVAL (operands[2]) >= 128)
2230 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2232 if (INTVAL (operands[2]) > 0
2233 && INTVAL (operands[2]) <= 8)
2234 return \"addq%.b %2,%0\";
2235 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2237 operands[2] = GEN_INT (- INTVAL (operands[2]));
2238 return \"subq%.b %2,%0\";
2241 return \"add%.b %2,%0\";
2245 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2246 (plus:QI (match_dup 0)
2247 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2251 if (GET_CODE (operands[1]) == CONST_INT)
2253 if (INTVAL (operands[1]) >= 128)
2254 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2256 if (INTVAL (operands[1]) > 0
2257 && INTVAL (operands[1]) <= 8)
2258 return \"addq%.b %1,%0\";
2259 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2261 operands[1] = GEN_INT (- INTVAL (operands[1]));
2262 return \"subq%.b %1,%0\";
2265 return \"add%.b %1,%0\";
2269 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2270 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2275 if (GET_CODE (operands[1]) == CONST_INT)
2277 if (INTVAL (operands[1]) >= 128)
2278 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2280 if (INTVAL (operands[1]) > 0
2281 && INTVAL (operands[1]) <= 8)
2282 return \"addq%.b %1,%0\";
2283 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2285 operands[1] = GEN_INT (- INTVAL (operands[1]));
2286 return \"subq%.b %1,%0\";
2289 return \"add%.b %1,%0\";
2292 (define_expand "adddf3"
2293 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2294 (plus:DF (match_operand:DF 1 "general_operand" "")
2295 (match_operand:DF 2 "general_operand" "")))]
2300 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2301 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2302 (match_operand:DF 1 "general_operand" "0")))]
2307 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2308 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2309 (match_operand:DF 1 "general_operand" "0")))]
2314 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2315 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2316 (match_operand:DF 1 "general_operand" "0")))]
2321 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2322 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2323 (match_operand:DF 2 "general_operand" "fmG")))]
2327 if (REG_P (operands[2]))
2328 return \"f%&add%.x %2,%0\";
2329 return \"f%&add%.d %f2,%0\";
2332 (define_expand "addsf3"
2333 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2334 (plus:SF (match_operand:SF 1 "general_operand" "")
2335 (match_operand:SF 2 "general_operand" "")))]
2340 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2341 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2342 (match_operand:SF 1 "general_operand" "0")))]
2347 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2348 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2349 (match_operand:SF 1 "general_operand" "0")))]
2354 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2355 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2356 (match_operand:SF 1 "general_operand" "0")))]
2361 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2362 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2363 (match_operand:SF 2 "general_operand" "fdmF")))]
2367 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2368 return \"f%$add%.x %2,%0\";
2369 return \"f%$add%.s %f2,%0\";
2372 ;; subtract instructions
2374 (define_insn "subdi_sexthishl32"
2375 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2376 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2377 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2379 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2384 if (ADDRESS_REG_P (operands[0]))
2385 return \"sub%.w %2,%0\";
2386 else if (ADDRESS_REG_P (operands[3]))
2387 return \"move%.w %2,%3\;sub%.l %3,%0\";
2389 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2392 (define_insn "subdi_dishl32"
2393 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2394 (minus:DI (match_dup 0)
2395 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2401 if (GET_CODE (operands[1]) == REG)
2402 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2404 operands[1] = adjust_address (operands[1], SImode, 4);
2405 return \"sub%.l %1,%0\";
2408 (define_insn "subdi3"
2409 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
2410 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2411 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2412 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2416 if (DATA_REG_P (operands[0]))
2418 if (DATA_REG_P (operands[2]))
2419 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2420 else if (GET_CODE (operands[2]) == MEM
2421 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2423 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2430 if (GET_CODE (operands[2]) == REG)
2432 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2435 else if (CONSTANT_P (operands[2]))
2436 split_double (operands[2], &high, &low);
2439 low = adjust_address (operands[2], SImode, 4);
2443 operands[1] = low, operands[2] = high;
2444 xoperands[0] = operands[3];
2445 if (GET_CODE (operands[1]) == CONST_INT
2446 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2447 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2449 xoperands[1] = operands[2];
2451 output_asm_insn (output_move_simode (xoperands), xoperands);
2452 if (GET_CODE (operands[1]) == CONST_INT)
2454 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2455 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2456 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2458 operands[1] = GEN_INT (-INTVAL (operands[1]));
2459 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2462 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2465 else if (GET_CODE (operands[0]) == MEM)
2467 if (GET_CODE (operands[2]) == MEM
2468 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2469 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2471 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2474 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2475 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2477 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2479 operands[1] = XEXP(operands[0], 0);
2480 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2484 operands[1] = adjust_address (operands[0], SImode, 4);
2485 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2492 (define_insn "subsi3"
2493 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
2494 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2495 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2500 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2501 (minus:SI (match_operand:SI 1 "general_operand" "0")
2503 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2507 (define_insn "subhi3"
2508 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2509 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2510 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2515 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2516 (minus:HI (match_dup 0)
2517 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2521 (define_insn "subqi3"
2522 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2523 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2524 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2529 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2530 (minus:QI (match_dup 0)
2531 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2535 (define_expand "subdf3"
2536 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2537 (minus:DF (match_operand:DF 1 "general_operand" "")
2538 (match_operand:DF 2 "general_operand" "")))]
2543 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2544 (minus:DF (match_operand:DF 1 "general_operand" "0")
2545 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2550 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2551 (minus:DF (match_operand:DF 1 "general_operand" "0")
2552 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2557 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2558 (minus:DF (match_operand:DF 1 "general_operand" "0")
2559 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2564 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2565 (minus:DF (match_operand:DF 1 "general_operand" "0")
2566 (match_operand:DF 2 "general_operand" "fmG")))]
2570 if (REG_P (operands[2]))
2571 return \"f%&sub%.x %2,%0\";
2572 return \"f%&sub%.d %f2,%0\";
2575 (define_expand "subsf3"
2576 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2577 (minus:SF (match_operand:SF 1 "general_operand" "")
2578 (match_operand:SF 2 "general_operand" "")))]
2583 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2584 (minus:SF (match_operand:SF 1 "general_operand" "0")
2585 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2590 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2591 (minus:SF (match_operand:SF 1 "general_operand" "0")
2592 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2597 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2598 (minus:SF (match_operand:SF 1 "general_operand" "0")
2599 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2604 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2605 (minus:SF (match_operand:SF 1 "general_operand" "0")
2606 (match_operand:SF 2 "general_operand" "fdmF")))]
2610 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2611 return \"f%$sub%.x %2,%0\";
2612 return \"f%$sub%.s %f2,%0\";
2615 ;; multiply instructions
2617 (define_insn "mulhi3"
2618 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2619 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2620 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2624 #if defined(MOTOROLA)
2625 return \"muls%.w %2,%0\";
2627 return \"muls %2,%0\";
2631 (define_insn "mulhisi3"
2632 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2633 (mult:SI (sign_extend:SI
2634 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2636 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2640 #if defined(MOTOROLA)
2641 return \"muls%.w %2,%0\";
2643 return \"muls %2,%0\";
2648 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2649 (mult:SI (sign_extend:SI
2650 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2651 (match_operand:SI 2 "const_int_operand" "n")))]
2652 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2655 #if defined(MOTOROLA)
2656 return \"muls%.w %2,%0\";
2658 return \"muls %2,%0\";
2662 (define_expand "mulsi3"
2663 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2664 (mult:SI (match_operand:SI 1 "general_operand" "")
2665 (match_operand:SI 2 "general_operand" "")))]
2666 "TARGET_68020 || TARGET_COLDFIRE"
2670 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2671 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2672 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
2678 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2679 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2680 (match_operand:SI 2 "general_operand" "d<Q>")))]
2684 (define_insn "umulhisi3"
2685 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2686 (mult:SI (zero_extend:SI
2687 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2689 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2693 #if defined(MOTOROLA)
2694 return \"mulu%.w %2,%0\";
2696 return \"mulu %2,%0\";
2701 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2702 (mult:SI (zero_extend:SI
2703 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2704 (match_operand:SI 2 "const_int_operand" "n")))]
2705 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2708 #if defined(MOTOROLA)
2709 return \"mulu%.w %2,%0\";
2711 return \"mulu %2,%0\";
2715 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2716 ;; proper matching constraint. This is because the matching is between
2717 ;; the high-numbered word of the DImode operand[0] and operand[1].
2718 (define_expand "umulsidi3"
2720 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2721 (mult:SI (match_operand:SI 1 "register_operand" "")
2722 (match_operand:SI 2 "register_operand" "")))
2723 (set (subreg:SI (match_dup 0) 0)
2724 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2725 (zero_extend:DI (match_dup 2)))
2726 (const_int 32))))])]
2727 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2731 [(set (match_operand:SI 0 "register_operand" "=d")
2732 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2733 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2734 (set (match_operand:SI 3 "register_operand" "=d")
2735 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2736 (zero_extend:DI (match_dup 2)))
2738 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2741 ; Match immediate case. For 2.4 only match things < 2^31.
2742 ; It's tricky with larger values in these patterns since we need to match
2743 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2746 [(set (match_operand:SI 0 "register_operand" "=d")
2747 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2748 (match_operand:SI 2 "const_int_operand" "n")))
2749 (set (match_operand:SI 3 "register_operand" "=d")
2750 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2753 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE
2754 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2757 (define_expand "mulsidi3"
2759 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2760 (mult:SI (match_operand:SI 1 "register_operand" "")
2761 (match_operand:SI 2 "register_operand" "")))
2762 (set (subreg:SI (match_dup 0) 0)
2763 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2764 (sign_extend:DI (match_dup 2)))
2765 (const_int 32))))])]
2766 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2770 [(set (match_operand:SI 0 "register_operand" "=d")
2771 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2772 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2773 (set (match_operand:SI 3 "register_operand" "=d")
2774 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2775 (sign_extend:DI (match_dup 2)))
2777 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2781 [(set (match_operand:SI 0 "register_operand" "=d")
2782 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2783 (match_operand:SI 2 "const_int_operand" "n")))
2784 (set (match_operand:SI 3 "register_operand" "=d")
2785 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2788 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2791 (define_expand "umulsi3_highpart"
2793 [(set (match_operand:SI 0 "register_operand" "")
2796 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2797 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2799 (clobber (match_dup 3))])]
2800 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2803 operands[3] = gen_reg_rtx (SImode);
2805 if (GET_CODE (operands[2]) == CONST_INT)
2807 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
2810 /* We have to adjust the operand order for the matching constraints. */
2811 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2812 operands[1], operands[2]));
2818 [(set (match_operand:SI 0 "register_operand" "=d")
2821 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2822 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2824 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2825 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2828 (define_insn "const_umulsi3_highpart"
2829 [(set (match_operand:SI 0 "register_operand" "=d")
2832 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2833 (match_operand:DI 3 "const_uint32_operand" "n"))
2835 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2836 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2839 (define_expand "smulsi3_highpart"
2841 [(set (match_operand:SI 0 "register_operand" "")
2844 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2845 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2847 (clobber (match_dup 3))])]
2848 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2851 operands[3] = gen_reg_rtx (SImode);
2852 if (GET_CODE (operands[2]) == CONST_INT)
2854 /* We have to adjust the operand order for the matching constraints. */
2855 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
2856 operands[1], operands[2]));
2862 [(set (match_operand:SI 0 "register_operand" "=d")
2865 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2866 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2868 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2869 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2872 (define_insn "const_smulsi3_highpart"
2873 [(set (match_operand:SI 0 "register_operand" "=d")
2876 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
2877 (match_operand:DI 3 "const_sint32_operand" "n"))
2879 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2880 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2883 (define_expand "muldf3"
2884 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2885 (mult:DF (match_operand:DF 1 "general_operand" "")
2886 (match_operand:DF 2 "general_operand" "")))]
2891 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2892 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2893 (match_operand:DF 1 "general_operand" "0")))]
2898 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2899 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2900 (match_operand:DF 1 "general_operand" "0")))]
2905 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2906 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2907 (match_operand:DF 1 "general_operand" "0")))]
2912 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2913 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2914 (match_operand:DF 2 "general_operand" "fmG")))]
2918 if (GET_CODE (operands[2]) == CONST_DOUBLE
2919 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
2921 int i = floating_exact_log2 (operands[2]);
2922 operands[2] = GEN_INT (i);
2923 return \"fscale%.l %2,%0\";
2925 if (REG_P (operands[2]))
2926 return \"f%&mul%.x %2,%0\";
2927 return \"f%&mul%.d %f2,%0\";
2930 (define_expand "mulsf3"
2931 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2932 (mult:SF (match_operand:SF 1 "general_operand" "")
2933 (match_operand:SF 2 "general_operand" "")))]
2938 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2939 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2940 (match_operand:SF 1 "general_operand" "0")))]
2944 return (TARGET_68040_ONLY
2945 ? \"fsmul%.l %2,%0\"
2946 : \"fsglmul%.l %2,%0\");
2950 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2951 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2952 (match_operand:SF 1 "general_operand" "0")))]
2956 return (TARGET_68040_ONLY
2957 ? \"fsmul%.w %2,%0\"
2958 : \"fsglmul%.w %2,%0\");
2962 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2963 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2964 (match_operand:SF 1 "general_operand" "0")))]
2968 return (TARGET_68040_ONLY
2969 ? \"fsmul%.b %2,%0\"
2970 : \"fsglmul%.b %2,%0\");
2974 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2975 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2976 (match_operand:SF 2 "general_operand" "fdmF")))]
2980 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2981 return (TARGET_68040_ONLY
2982 ? \"fsmul%.x %2,%0\"
2983 : \"fsglmul%.x %2,%0\");
2984 return (TARGET_68040_ONLY
2985 ? \"fsmul%.s %f2,%0\"
2986 : \"fsglmul%.s %f2,%0\");
2989 ;; divide instructions
2991 (define_expand "divdf3"
2992 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2993 (div:DF (match_operand:DF 1 "general_operand" "")
2994 (match_operand:DF 2 "general_operand" "")))]
2999 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3000 (div:DF (match_operand:DF 1 "general_operand" "0")
3001 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3006 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3007 (div:DF (match_operand:DF 1 "general_operand" "0")
3008 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3013 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3014 (div:DF (match_operand:DF 1 "general_operand" "0")
3015 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3020 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3021 (div:DF (match_operand:DF 1 "general_operand" "0")
3022 (match_operand:DF 2 "general_operand" "fmG")))]
3026 if (REG_P (operands[2]))
3027 return \"f%&div%.x %2,%0\";
3028 return \"f%&div%.d %f2,%0\";
3031 (define_expand "divsf3"
3032 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3033 (div:SF (match_operand:SF 1 "general_operand" "")
3034 (match_operand:SF 2 "general_operand" "")))]
3039 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3040 (div:SF (match_operand:SF 1 "general_operand" "0")
3041 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3045 return (TARGET_68040_ONLY
3046 ? \"fsdiv%.l %2,%0\"
3047 : \"fsgldiv%.l %2,%0\");
3051 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3052 (div:SF (match_operand:SF 1 "general_operand" "0")
3053 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3057 return (TARGET_68040_ONLY
3058 ? \"fsdiv%.w %2,%0\"
3059 : \"fsgldiv%.w %2,%0\");
3063 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3064 (div:SF (match_operand:SF 1 "general_operand" "0")
3065 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3069 return (TARGET_68040_ONLY
3070 ? \"fsdiv%.b %2,%0\"
3071 : \"fsgldiv%.b %2,%0\");
3075 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3076 (div:SF (match_operand:SF 1 "general_operand" "0")
3077 (match_operand:SF 2 "general_operand" "fdmF")))]
3081 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3082 return (TARGET_68040_ONLY
3083 ? \"fsdiv%.x %2,%0\"
3084 : \"fsgldiv%.x %2,%0\");
3085 return (TARGET_68040_ONLY
3086 ? \"fsdiv%.s %f2,%0\"
3087 : \"fsgldiv%.s %f2,%0\");
3090 ;; Remainder instructions.
3092 (define_expand "divmodsi4"
3094 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3095 (div:SI (match_operand:SI 1 "general_operand" "")
3096 (match_operand:SI 2 "general_src_operand" "")))
3097 (set (match_operand:SI 3 "nonimmediate_operand" "")
3098 (mod:SI (match_dup 1) (match_dup 2)))])]
3099 "TARGET_68020 || TARGET_CF_HWDIV"
3103 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3104 (div:SI (match_operand:SI 1 "general_operand" "0")
3105 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3106 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3107 (mod:SI (match_dup 1) (match_dup 2)))]
3111 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3112 return \"divs%.l %2,%0\";
3113 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3114 return \"rems%.l %2,%3:%0\";
3116 return \"rems%.l %2,%3:%0\;divs%.l %2,%0\";
3120 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3121 (div:SI (match_operand:SI 1 "general_operand" "0")
3122 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3123 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3124 (mod:SI (match_dup 1) (match_dup 2)))]
3128 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3129 return \"divs%.l %2,%0\";
3131 return \"divsl%.l %2,%3:%0\";
3134 (define_expand "udivmodsi4"
3136 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3137 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3138 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3139 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3140 (umod:SI (match_dup 1) (match_dup 2)))])]
3141 "TARGET_68020 || TARGET_CF_HWDIV"
3145 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3146 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3147 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3148 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3149 (umod:SI (match_dup 1) (match_dup 2)))]
3153 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3154 return \"divu%.l %2,%0\";
3155 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3156 return \"remu%.l %2,%3:%0\";
3158 return \"remu%.l %2,%3:%0\;divu%.l %2,%0\";
3162 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3163 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3164 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3165 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3166 (umod:SI (match_dup 1) (match_dup 2)))]
3167 "TARGET_68020 && !TARGET_COLDFIRE"
3170 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3171 return \"divu%.l %2,%0\";
3173 return \"divul%.l %2,%3:%0\";
3176 (define_insn "divmodhi4"
3177 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3178 (div:HI (match_operand:HI 1 "general_operand" "0")
3179 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3180 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3181 (mod:HI (match_dup 1) (match_dup 2)))]
3182 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3186 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3188 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3190 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3193 return \"move%.l %0,%3\;swap %3\";
3199 (define_insn "udivmodhi4"
3200 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3201 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3202 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3203 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3204 (umod:HI (match_dup 1) (match_dup 2)))]
3205 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3209 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3211 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3213 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3216 return \"move%.l %0,%3\;swap %3\";
3222 ;; logical-and instructions
3224 ;; "anddi3" is mainly here to help combine().
3225 (define_insn "anddi3"
3226 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3227 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3228 (match_operand:DI 2 "general_operand" "dn,don")))]
3233 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3234 if (CONSTANT_P (operands[2]))
3238 split_double (operands[2], &hi, &lo);
3240 switch (INTVAL (hi))
3243 output_asm_insn (\"clr%.l %0\", operands);
3251 xoperands[0] = operands[0];
3253 output_asm_insn (output_andsi3 (xoperands), xoperands);
3256 if (GET_CODE (operands[0]) == REG)
3257 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3259 operands[0] = adjust_address (operands[0], SImode, 4);
3260 switch (INTVAL (lo))
3263 output_asm_insn (\"clr%.l %0\", operands);
3271 xoperands[0] = operands[0];
3273 output_asm_insn (output_andsi3 (xoperands), xoperands);
3278 if (GET_CODE (operands[0]) != REG)
3280 operands[1] = adjust_address (operands[0], SImode, 4);
3281 return \"and%.l %2,%0\;and%.l %R2,%1\";
3283 if (GET_CODE (operands[2]) != REG)
3285 operands[1] = adjust_address (operands[2], SImode, 4);
3286 return \"and%.l %2,%0\;and%.l %1,%R0\";
3288 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3291 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3292 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3293 ;; can't allocate pseudos into it.
3295 (define_expand "andsi3"
3296 [(set (match_operand:SI 0 "not_sp_operand" "")
3297 (and:SI (match_operand:SI 1 "general_operand" "")
3298 (match_operand:SI 2 "general_src_operand" "")))]
3302 (define_insn "andsi3_internal"
3303 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3304 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3305 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3309 return output_andsi3 (operands);
3312 (define_insn "andsi3_5200"
3313 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3314 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3315 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3319 (define_insn "andhi3"
3320 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3321 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3322 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3327 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3328 (and:HI (match_dup 0)
3329 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3334 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3335 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3340 (define_insn "andqi3"
3341 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3342 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3343 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3348 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3349 (and:QI (match_dup 0)
3350 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3355 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3356 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3361 ;; inclusive-or instructions
3363 (define_insn "iordi_zext"
3364 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3365 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3366 (match_operand:DI 2 "general_operand" "0,0")))]
3373 if (GET_CODE (operands[0]) == REG)
3374 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3376 operands[0] = adjust_address (operands[0], SImode, 4);
3377 if (GET_MODE (operands[1]) == SImode)
3378 return \"or%.l %1,%0\";
3379 byte_mode = (GET_MODE (operands[1]) == QImode);
3380 if (GET_CODE (operands[0]) == MEM)
3381 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3384 return \"or%.b %1,%0\";
3386 return \"or%.w %1,%0\";
3389 ;; "iordi3" is mainly here to help combine().
3390 (define_insn "iordi3"
3391 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3392 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3393 (match_operand:DI 2 "general_operand" "dn,don")))]
3398 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3399 if (CONSTANT_P (operands[2]))
3403 split_double (operands[2], &hi, &lo);
3405 switch (INTVAL (hi))
3410 /* FIXME : a scratch register would be welcome here if operand[0]
3411 is not a register */
3412 output_asm_insn (\"move%.l %#-1,%0\", operands);
3418 xoperands[0] = operands[0];
3420 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3423 if (GET_CODE (operands[0]) == REG)
3424 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3426 operands[0] = adjust_address (operands[0], SImode, 4);
3427 switch (INTVAL (lo))
3432 /* FIXME : a scratch register would be welcome here if operand[0]
3433 is not a register */
3434 output_asm_insn (\"move%.l %#-1,%0\", operands);
3440 xoperands[0] = operands[0];
3442 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3447 if (GET_CODE (operands[0]) != REG)
3449 operands[1] = adjust_address (operands[0], SImode, 4);
3450 return \"or%.l %2,%0\;or%.l %R2,%1\";
3452 if (GET_CODE (operands[2]) != REG)
3454 operands[1] = adjust_address (operands[2], SImode, 4);
3455 return \"or%.l %2,%0\;or%.l %1,%R0\";
3457 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3460 (define_expand "iorsi3"
3461 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3462 (ior:SI (match_operand:SI 1 "general_operand" "")
3463 (match_operand:SI 2 "general_src_operand" "")))]
3467 (define_insn "iorsi3_internal"
3468 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3469 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3470 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3474 return output_iorsi3 (operands);
3477 (define_insn "iorsi3_5200"
3478 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3479 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3480 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3484 (define_insn "iorhi3"
3485 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3486 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3487 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3492 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3493 (ior:HI (match_dup 0)
3494 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3499 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3500 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3505 (define_insn "iorqi3"
3506 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3507 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3508 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3513 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3514 (ior:QI (match_dup 0)
3515 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3520 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3521 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3526 ;; On all 68k models, this makes faster code in a special case.
3527 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3529 (define_insn "iorsi_zexthi_ashl16"
3530 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3531 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3532 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3538 if (GET_CODE (operands[2]) != REG)
3539 operands[2] = adjust_address (operands[2], HImode, 2);
3540 if (GET_CODE (operands[2]) != REG
3541 || REGNO (operands[2]) != REGNO (operands[0]))
3542 output_asm_insn (\"move%.w %2,%0\", operands);
3543 return \"swap %0\;mov%.w %1,%0\";
3546 (define_insn "iorsi_zext"
3547 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3548 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3549 (match_operand:SI 2 "general_operand" "0,0")))]
3556 byte_mode = (GET_MODE (operands[1]) == QImode);
3557 if (GET_CODE (operands[0]) == MEM)
3558 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3561 return \"or%.b %1,%0\";
3563 return \"or%.w %1,%0\";
3568 ;; "xordi3" is mainly here to help combine().
3569 (define_insn "xordi3"
3570 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3571 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3572 (match_operand:DI 2 "general_operand" "dn")))]
3577 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3579 if (CONSTANT_P (operands[2]))
3583 split_double (operands[2], &hi, &lo);
3585 switch (INTVAL (hi))
3590 output_asm_insn (\"not%.l %0\", operands);
3593 /* FIXME : a scratch register would be welcome here if
3594 -128 <= INTVAL (hi) < -1 */
3598 xoperands[0] = operands[0];
3600 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3603 if (GET_CODE (operands[0]) == REG)
3604 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3606 operands[0] = adjust_address (operands[0], SImode, 4);
3607 switch (INTVAL (lo))
3612 output_asm_insn (\"not%.l %0\", operands);
3615 /* FIXME : a scratch register would be welcome here if
3616 -128 <= INTVAL (lo) < -1 */
3618 /* FIXME : this should be merged with xorsi3 */
3622 xoperands[0] = operands[0];
3624 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3629 if (GET_CODE (operands[0]) != REG)
3631 operands[1] = adjust_address (operands[0], SImode, 4);
3632 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3634 if (GET_CODE (operands[2]) != REG)
3636 operands[1] = adjust_address (operands[2], SImode, 4);
3637 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3639 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3642 (define_expand "xorsi3"
3643 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3644 (xor:SI (match_operand:SI 1 "general_operand" "")
3645 (match_operand:SI 2 "general_operand" "")))]
3649 (define_insn "xorsi3_internal"
3650 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3651 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3652 (match_operand:SI 2 "general_operand" "di,dKT")))]
3657 return output_xorsi3 (operands);
3660 (define_insn "xorsi3_5200"
3661 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3662 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3663 (match_operand:SI 2 "general_operand" "d,Ks")))]
3667 (define_insn "xorhi3"
3668 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3669 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3670 (match_operand:HI 2 "general_operand" "dn")))]
3675 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3676 (xor:HI (match_dup 0)
3677 (match_operand:HI 1 "general_operand" "dn")))]
3682 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3683 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3688 (define_insn "xorqi3"
3689 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3690 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3691 (match_operand:QI 2 "general_operand" "dn")))]
3696 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3697 (xor:QI (match_dup 0)
3698 (match_operand:QI 1 "general_operand" "dn")))]
3703 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3704 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3709 ;; negation instructions
3711 (define_expand "negdi2"
3712 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3713 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3717 if (TARGET_COLDFIRE)
3718 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3720 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3724 (define_insn "negdi2_internal"
3725 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
3726 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3730 if (which_alternative == 0)
3731 return \"neg%.l %0\;negx%.l %0\";
3732 if (GET_CODE (operands[0]) == REG)
3733 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3735 operands[1] = adjust_address (operands[0], SImode, 4);
3736 if (ADDRESS_REG_P (operands[0]))
3737 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3739 return \"neg%.l %1\;negx%.l %0\";
3742 (define_insn "negdi2_5200"
3743 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3744 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3748 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3749 return \"neg%.l %1\;negx%.l %0\";
3752 (define_expand "negsi2"
3753 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3754 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3758 if (TARGET_COLDFIRE)
3759 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3761 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3765 (define_insn "negsi2_internal"
3766 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3767 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3771 (define_insn "negsi2_5200"
3772 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3773 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3777 (define_insn "neghi2"
3778 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3779 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3784 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3785 (neg:HI (match_dup 0)))]
3789 (define_insn "negqi2"
3790 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3791 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3796 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3797 (neg:QI (match_dup 0)))]
3801 ;; If using software floating point, just flip the sign bit.
3803 (define_expand "negsf2"
3804 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3805 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3814 target = operand_subword_force (operands[0], 0, SFmode);
3815 result = expand_binop (SImode, xor_optab,
3816 operand_subword_force (operands[1], 0, SFmode),
3817 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3821 if (result != target)
3822 emit_move_insn (result, target);
3824 /* Make a place for REG_EQUAL. */
3825 emit_move_insn (operands[0], operands[0]);
3831 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
3832 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3836 if (DATA_REG_P (operands[0]))
3838 operands[1] = GEN_INT (31);
3839 return \"bchg %1,%0\";
3841 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3842 return \"f%$neg%.x %1,%0\";
3843 return \"f%$neg%.s %f1,%0\";
3846 (define_expand "negdf2"
3847 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3848 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3859 target = operand_subword (operands[0], 0, 1, DFmode);
3860 result = expand_binop (SImode, xor_optab,
3861 operand_subword_force (operands[1], 0, DFmode),
3862 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3866 if (result != target)
3867 emit_move_insn (result, target);
3869 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3870 operand_subword_force (operands[1], 1, DFmode));
3872 insns = get_insns ();
3875 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3881 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
3882 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3886 if (DATA_REG_P (operands[0]))
3888 operands[1] = GEN_INT (31);
3889 return \"bchg %1,%0\";
3891 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3892 return \"f%&neg%.x %1,%0\";
3893 return \"f%&neg%.d %f1,%0\";
3896 ;; Sqrt instruction for the 68881
3898 (define_insn "sqrtsf2"
3899 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3900 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3904 if (FP_REG_P (operands[1]))
3905 return \"f%$sqrt%.x %1,%0\";
3907 return \"f%$sqrt%.s %1,%0\";
3910 (define_insn "sqrtdf2"
3911 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3912 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3916 if (FP_REG_P (operands[1]))
3917 return \"f%&sqrt%.x %1,%0\";
3919 return \"f%&sqrt%.d %1,%0\";
3922 ;; Absolute value instructions
3923 ;; If using software floating point, just zero the sign bit.
3925 (define_expand "abssf2"
3926 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3927 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3936 target = operand_subword_force (operands[0], 0, SFmode);
3937 result = expand_binop (SImode, and_optab,
3938 operand_subword_force (operands[1], 0, SFmode),
3939 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3943 if (result != target)
3944 emit_move_insn (result, target);
3946 /* Make a place for REG_EQUAL. */
3947 emit_move_insn (operands[0], operands[0]);
3953 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3954 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
3958 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3959 return \"f%$abs%.x %1,%0\";
3960 return \"f%$abs%.s %f1,%0\";
3963 (define_expand "absdf2"
3964 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3965 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3976 target = operand_subword (operands[0], 0, 1, DFmode);
3977 result = expand_binop (SImode, and_optab,
3978 operand_subword_force (operands[1], 0, DFmode),
3979 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3983 if (result != target)
3984 emit_move_insn (result, target);
3986 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3987 operand_subword_force (operands[1], 1, DFmode));
3989 insns = get_insns ();
3992 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3998 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3999 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4003 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4004 return \"f%&abs%.x %1,%0\";
4005 return \"f%&abs%.d %f1,%0\";
4008 ;; one complement instructions
4010 ;; "one_cmpldi2" is mainly here to help combine().
4011 (define_insn "one_cmpldi2"
4012 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4013 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4018 if (GET_CODE (operands[0]) == REG)
4019 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4020 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4021 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4022 operands[1] = operands[0];
4024 operands[1] = adjust_address (operands[0], SImode, 4);
4025 return \"not%.l %1\;not%.l %0\";
4028 (define_expand "one_cmplsi2"
4029 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4030 (not:SI (match_operand:SI 1 "general_operand" "")))]
4034 if (TARGET_COLDFIRE)
4035 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4037 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4041 (define_insn "one_cmplsi2_internal"
4042 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4043 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4047 (define_insn "one_cmplsi2_5200"
4048 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4049 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4053 (define_insn "one_cmplhi2"
4054 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4055 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4060 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4061 (not:HI (match_dup 0)))]
4065 (define_insn "one_cmplqi2"
4066 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4067 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4072 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4073 (not:QI (match_dup 0)))]
4077 ;; arithmetic shift instructions
4078 ;; We don't need the shift memory by 1 bit instruction
4080 (define_insn "ashldi_extsi"
4081 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4083 (match_operator:DI 2 "extend_operator"
4084 [(match_operand:SI 1 "general_operand" "rm")])
4090 if (GET_CODE (operands[0]) == REG)
4091 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4093 operands[2] = adjust_address (operands[0], SImode, 4);
4094 if (ADDRESS_REG_P (operands[0]))
4095 return \"move%.l %1,%0\;sub%.l %2,%2\";
4097 return \"move%.l %1,%0\;clr%.l %2\";
4100 (define_insn "ashldi_sexthi"
4101 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4102 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4104 (clobber (match_scratch:SI 2 "=a,X"))]
4109 if (GET_CODE (operands[0]) == MEM)
4111 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4112 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4113 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4114 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4117 operands[3] = adjust_address (operands[0], SImode, 4);
4118 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4121 else if (DATA_REG_P (operands[0]))
4122 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4124 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4127 (define_insn "ashldi_const32"
4128 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
4129 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4135 if (GET_CODE (operands[1]) == REG)
4136 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4138 operands[3] = adjust_address (operands[1], SImode, 4);
4139 if (GET_CODE (operands[0]) == REG)
4140 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4141 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4142 return \"clr%.l %0\;move%.l %3,%0\";
4143 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4144 return \"move%.l %3,%0\;clr%.l %0\";
4146 operands[2] = adjust_address (operands[0], SImode, 4);
4147 if (ADDRESS_REG_P (operands[2]))
4148 return \"move%.l %3,%0\;sub%.l %2,%2\";
4150 return \"move%.l %3,%0\;clr%.l %2\";
4153 ;; The predicate below must be general_operand, because ashldi3 allows that
4154 (define_insn "ashldi_const"
4155 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4156 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4157 (match_operand 2 "const_int_operand" "n")))]
4159 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4160 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4161 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4164 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4165 if (INTVAL (operands[2]) == 1)
4166 return \"add%.l %1,%1\;addx%.l %0,%0\";
4167 else if (INTVAL (operands[2]) == 8)
4168 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4169 else if (INTVAL (operands[2]) == 16)
4170 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4171 else if (INTVAL (operands[2]) == 48)
4172 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4173 else if (INTVAL (operands[2]) == 2)
4174 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4175 else if (INTVAL (operands[2]) == 3)
4176 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4177 else /* 32 < INTVAL (operands[2]) <= 63 */
4179 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4180 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4181 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4182 return \"mov%.l %1,%0\;moveq %#0,%1\";
4186 (define_expand "ashldi3"
4187 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4188 (ashift:DI (match_operand:DI 1 "general_operand" "")
4189 (match_operand 2 "const_int_operand" "")))]
4193 /* ??? This is a named pattern like this is not allowed to FAIL based
4195 if (GET_CODE (operands[2]) != CONST_INT
4196 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4197 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4198 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4202 ;; On most 68k models, this makes faster code in a special case.
4204 (define_insn "ashlsi_16"
4205 [(set (match_operand:SI 0 "register_operand" "=d")
4206 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4212 return \"swap %0\;clr%.w %0\";
4215 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4216 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4218 ;; On the 68000, this makes faster code in a special case.
4220 (define_insn "ashlsi_17_24"
4221 [(set (match_operand:SI 0 "register_operand" "=d")
4222 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4223 (match_operand:SI 2 "const_int_operand" "n")))]
4224 "(! TARGET_68020 && !TARGET_COLDFIRE
4225 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4230 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4231 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4234 (define_insn "ashlsi3"
4235 [(set (match_operand:SI 0 "register_operand" "=d")
4236 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4237 (match_operand:SI 2 "general_operand" "dI")))]
4241 if (operands[2] == const1_rtx)
4243 cc_status.flags = CC_NO_OVERFLOW;
4244 return \"add%.l %0,%0\";
4246 return \"lsl%.l %2,%0\";
4249 (define_insn "ashlhi3"
4250 [(set (match_operand:HI 0 "register_operand" "=d")
4251 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4252 (match_operand:HI 2 "general_operand" "dI")))]
4257 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4258 (ashift:HI (match_dup 0)
4259 (match_operand:HI 1 "general_operand" "dI")))]
4263 (define_insn "ashlqi3"
4264 [(set (match_operand:QI 0 "register_operand" "=d")
4265 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4266 (match_operand:QI 2 "general_operand" "dI")))]
4271 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4272 (ashift:QI (match_dup 0)
4273 (match_operand:QI 1 "general_operand" "dI")))]
4277 ;; On most 68k models, this makes faster code in a special case.
4279 (define_insn "ashrsi_16"
4280 [(set (match_operand:SI 0 "register_operand" "=d")
4281 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4284 "swap %0\;ext%.l %0")
4286 ;; On the 68000, this makes faster code in a special case.
4289 [(set (match_operand:SI 0 "register_operand" "=d")
4290 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4291 (match_operand:SI 2 "const_int_operand" "n")))]
4292 "(! TARGET_68020 && !TARGET_COLDFIRE
4293 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4296 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4297 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4300 (define_insn "subreghi1ashrdi_const32"
4301 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4302 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4303 (const_int 32)) 6))]
4307 if (GET_CODE (operands[1]) != REG)
4308 operands[1] = adjust_address (operands[1], HImode, 2);
4309 return \"move%.w %1,%0\";
4312 (define_insn "subregsi1ashrdi_const32"
4313 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4314 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4315 (const_int 32)) 4))]
4319 return \"move%.l %1,%0\";
4322 (define_insn "ashrdi_const32"
4323 [(set (match_operand:DI 0 "register_operand" "=d")
4324 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4330 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4332 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4334 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4337 (define_insn "ashrdi_const32_mem"
4338 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,<")
4339 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4341 (clobber (match_scratch:SI 2 "=d,d"))]
4346 if (which_alternative == 1)
4347 operands[3] = operands[0];
4349 operands[3] = adjust_address (operands[0], SImode, 4);
4351 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4353 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4356 ;; The predicate below must be general_operand, because ashrdi3 allows that
4357 (define_insn "ashrdi_const"
4358 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4359 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4360 (match_operand 2 "const_int_operand" "n")))]
4362 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4363 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4364 || INTVAL (operands[2]) == 31
4365 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4368 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4369 if (INTVAL (operands[2]) == 63)
4370 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4372 if (INTVAL (operands[2]) == 1)
4373 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4374 else if (INTVAL (operands[2]) == 8)
4375 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4376 else if (INTVAL (operands[2]) == 16)
4377 return \"move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1\";
4378 else if (INTVAL (operands[2]) == 48)
4379 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4380 else if (INTVAL (operands[2]) == 31)
4381 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4382 else if (INTVAL (operands[2]) == 2)
4383 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4384 else if (INTVAL (operands[2]) == 3)
4385 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4386 else /* 32 < INTVAL (operands[2]) <= 63 */
4388 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4389 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4390 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4391 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4392 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4393 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4397 (define_expand "ashrdi3"
4398 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4399 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4400 (match_operand 2 "const_int_operand" "")))]
4404 /* ??? This is a named pattern like this is not allowed to FAIL based
4406 if (GET_CODE (operands[2]) != CONST_INT
4407 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4408 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4409 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4413 ;; On all 68k models, this makes faster code in a special case.
4415 (define_insn "ashrsi_31"
4416 [(set (match_operand:SI 0 "register_operand" "=d")
4417 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4422 return \"add%.l %0,%0\;subx%.l %0,%0\";
4425 (define_insn "ashrsi3"
4426 [(set (match_operand:SI 0 "register_operand" "=d")
4427 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4428 (match_operand:SI 2 "general_operand" "dI")))]
4432 (define_insn "ashrhi3"
4433 [(set (match_operand:HI 0 "register_operand" "=d")
4434 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4435 (match_operand:HI 2 "general_operand" "dI")))]
4440 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4441 (ashiftrt:HI (match_dup 0)
4442 (match_operand:HI 1 "general_operand" "dI")))]
4446 (define_insn "ashrqi3"
4447 [(set (match_operand:QI 0 "register_operand" "=d")
4448 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4449 (match_operand:QI 2 "general_operand" "dI")))]
4454 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4455 (ashiftrt:QI (match_dup 0)
4456 (match_operand:QI 1 "general_operand" "dI")))]
4460 ;; logical shift instructions
4462 ;; commented out because of reload problems in 950612-1.c
4465 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4466 ;; (const_int 32)) 4))
4467 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4468 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4469 ;; (const_int 32)) 4))]
4473 ;; return \"move%.l %0,%1\";
4478 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4479 ;; (const_int 32)) 0))
4480 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4481 ;; (lshiftrt:DI (match_dup 0)
4482 ;; (const_int 32)))]
4486 ;; if (GET_CODE (operands[1]) == REG)
4487 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4489 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4490 ;; return \"move%.l %0,%2\;clr%.l %1\";
4493 (define_insn "subreg1lshrdi_const32"
4494 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4495 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4496 (const_int 32)) 4))]
4500 return \"move%.l %1,%0\";
4503 (define_insn "lshrdi_const32"
4504 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
4505 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4511 if (which_alternative == 1)
4512 return \"move%.l %1,%0\;clr%.l %0\";
4513 if (which_alternative == 2)
4514 return \"clr%.l %0\;move%.l %1,%0\";
4515 if (GET_CODE (operands[0]) == REG)
4516 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4518 operands[2] = adjust_address (operands[0], SImode, 4);
4519 if (GET_CODE (operands[1]) == REG)
4520 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4522 operands[3] = adjust_address (operands[1], SImode, 4);
4523 if (ADDRESS_REG_P (operands[0]))
4524 return \"move%.l %1,%2\;sub%.l %0,%0\";
4526 return \"move%.l %1,%2\;clr%.l %0\";
4529 ;; The predicate below must be general_operand, because lshrdi3 allows that
4530 (define_insn "lshrdi_const"
4531 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4532 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4533 (match_operand 2 "const_int_operand" "n")))]
4535 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4536 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4537 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4540 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4541 if (INTVAL (operands[2]) == 63)
4542 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4544 if (INTVAL (operands[2]) == 1)
4545 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4546 else if (INTVAL (operands[2]) == 8)
4547 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4548 else if (INTVAL (operands[2]) == 16)
4549 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4550 else if (INTVAL (operands[2]) == 48)
4551 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4552 else if (INTVAL (operands[2]) == 2)
4553 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4554 else if (INTVAL (operands[2]) == 3)
4555 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4556 else /* 32 < INTVAL (operands[2]) <= 63 */
4558 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4559 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4560 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4561 return \"mov%.l %0,%1\;moveq %#0,%0\";
4565 (define_expand "lshrdi3"
4566 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4567 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4568 (match_operand 2 "const_int_operand" "")))]
4572 /* ??? This is a named pattern like this is not allowed to FAIL based
4574 if (GET_CODE (operands[2]) != CONST_INT
4575 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4576 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4577 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4581 ;; On all 68k models, this makes faster code in a special case.
4583 (define_insn "lshrsi_31"
4584 [(set (match_operand:SI 0 "register_operand" "=d")
4585 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4590 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4593 ;; On most 68k models, this makes faster code in a special case.
4595 (define_insn "lshrsi_16"
4596 [(set (match_operand:SI 0 "register_operand" "=d")
4597 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4603 return \"clr%.w %0\;swap %0\";
4606 ;; On the 68000, this makes faster code in a special case.
4608 (define_insn "lshrsi_17_24"
4609 [(set (match_operand:SI 0 "register_operand" "=d")
4610 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4611 (match_operand:SI 2 "const_int_operand" "n")))]
4612 "(! TARGET_68020 && !TARGET_COLDFIRE
4613 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4616 /* I think lsr%.w sets the CC properly. */
4617 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4618 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4621 (define_insn "lshrsi3"
4622 [(set (match_operand:SI 0 "register_operand" "=d")
4623 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4624 (match_operand:SI 2 "general_operand" "dI")))]
4628 (define_insn "lshrhi3"
4629 [(set (match_operand:HI 0 "register_operand" "=d")
4630 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4631 (match_operand:HI 2 "general_operand" "dI")))]
4636 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4637 (lshiftrt:HI (match_dup 0)
4638 (match_operand:HI 1 "general_operand" "dI")))]
4642 (define_insn "lshrqi3"
4643 [(set (match_operand:QI 0 "register_operand" "=d")
4644 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4645 (match_operand:QI 2 "general_operand" "dI")))]
4650 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4651 (lshiftrt:QI (match_dup 0)
4652 (match_operand:QI 1 "general_operand" "dI")))]
4656 ;; rotate instructions
4658 (define_insn "rotlsi3"
4659 [(set (match_operand:SI 0 "register_operand" "=d")
4660 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4661 (match_operand:SI 2 "general_operand" "dINO")))]
4665 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4667 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4669 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4670 return \"ror%.l %2,%0\";
4673 return \"rol%.l %2,%0\";
4676 (define_insn "rotlhi3"
4677 [(set (match_operand:HI 0 "register_operand" "=d")
4678 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4679 (match_operand:HI 2 "general_operand" "dIP")))]
4683 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4685 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4686 return \"ror%.w %2,%0\";
4689 return \"rol%.w %2,%0\";
4693 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4694 (rotate:HI (match_dup 0)
4695 (match_operand:HI 1 "general_operand" "dIP")))]
4699 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4701 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4702 return \"ror%.w %2,%0\";
4705 return \"rol%.w %2,%0\";
4708 (define_insn "rotlqi3"
4709 [(set (match_operand:QI 0 "register_operand" "=d")
4710 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4711 (match_operand:QI 2 "general_operand" "dI")))]
4715 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4717 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4718 return \"ror%.b %2,%0\";
4721 return \"rol%.b %2,%0\";
4725 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4726 (rotate:QI (match_dup 0)
4727 (match_operand:QI 1 "general_operand" "dI")))]
4731 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4733 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4734 return \"ror%.b %2,%0\";
4737 return \"rol%.b %2,%0\";
4740 (define_insn "rotrsi3"
4741 [(set (match_operand:SI 0 "register_operand" "=d")
4742 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4743 (match_operand:SI 2 "general_operand" "dI")))]
4747 (define_insn "rotrhi3"
4748 [(set (match_operand:HI 0 "register_operand" "=d")
4749 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4750 (match_operand:HI 2 "general_operand" "dI")))]
4755 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4756 (rotatert:HI (match_dup 0)
4757 (match_operand:HI 1 "general_operand" "dI")))]
4761 (define_insn "rotrqi3"
4762 [(set (match_operand:QI 0 "register_operand" "=d")
4763 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4764 (match_operand:QI 2 "general_operand" "dI")))]
4769 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4770 (rotatert:QI (match_dup 0)
4771 (match_operand:QI 1 "general_operand" "dI")))]
4776 ;; Bit set/clear in memory byte.
4778 ;; set bit, bit number is int
4779 (define_insn "bsetmemqi"
4780 [(set (match_operand:QI 0 "memory_operand" "+m")
4781 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4782 (match_operand:SI 1 "general_operand" "d")) 3)
4788 return \"bset %1,%0\";
4791 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4793 [(set (match_operand:QI 0 "memory_operand" "+m")
4794 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4795 (match_operator:SI 2 "extend_operator"
4796 [(match_operand 1 "general_operand" "d")])) 3)
4802 return \"bset %1,%0\";
4805 ;; clear bit, bit number is int
4806 (define_insn "bclrmemqi"
4807 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4809 (minus:SI (const_int 7)
4810 (match_operand:SI 1 "general_operand" "d")))
4816 return \"bclr %1,%0\";
4819 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4821 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4823 (minus:SI (const_int 7)
4824 (match_operator:SI 2 "extend_operator"
4825 [(match_operand 1 "general_operand" "d")])))
4831 return \"bclr %1,%0\";
4834 ;; Special cases of bit-field insns which we should
4835 ;; recognize in preference to the general case.
4836 ;; These handle aligned 8-bit and 16-bit fields,
4837 ;; which can usually be done with move instructions.
4840 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4841 ; alignment of structure members is specified.
4843 ; The move is allowed to be odd byte aligned, because that's still faster
4844 ; than an odd byte aligned bit field instruction.
4847 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4849 (match_operand:SI 1 "const_int_operand" "n"))
4850 (match_operand:SI 2 "general_src_operand" "rmSi"))]
4851 "TARGET_68020 && TARGET_BITFIELD
4852 && (INTVAL (operands[1]) % 8) == 0
4853 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4857 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
4859 return \"move%.l %2,%0\";
4863 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4864 (match_operand:SI 1 "const_int_operand" "n")
4865 (match_operand:SI 2 "const_int_operand" "n"))
4866 (match_operand:SI 3 "register_operand" "d"))]
4867 "TARGET_68020 && TARGET_BITFIELD
4868 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4869 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4870 && (GET_CODE (operands[0]) == REG
4871 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4874 if (REG_P (operands[0]))
4876 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4877 return \"bfins %3,%0{%b2:%b1}\";
4880 operands[0] = adjust_address (operands[0],
4881 INTVAL (operands[1]) == 8 ? QImode : HImode,
4882 INTVAL (operands[2]) / 8);
4884 if (GET_CODE (operands[3]) == MEM)
4885 operands[3] = adjust_address (operands[3],
4886 INTVAL (operands[1]) == 8 ? QImode : HImode,
4887 (32 - INTVAL (operands[1])) / 8);
4889 if (INTVAL (operands[1]) == 8)
4890 return \"move%.b %3,%0\";
4891 return \"move%.w %3,%0\";
4896 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4897 ; alignment of structure members is specified.
4899 ; The move is allowed to be odd byte aligned, because that's still faster
4900 ; than an odd byte aligned bit field instruction.
4903 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4904 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4906 (match_operand:SI 2 "const_int_operand" "n")))]
4907 "TARGET_68020 && TARGET_BITFIELD
4908 && (INTVAL (operands[2]) % 8) == 0
4909 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4913 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4915 return \"move%.l %1,%0\";
4919 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
4920 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4921 (match_operand:SI 2 "const_int_operand" "n")
4922 (match_operand:SI 3 "const_int_operand" "n")))]
4923 "TARGET_68020 && TARGET_BITFIELD
4924 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4925 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4926 && (GET_CODE (operands[1]) == REG
4927 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4930 cc_status.flags |= CC_NOT_NEGATIVE;
4931 if (REG_P (operands[1]))
4933 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4934 return \"bfextu %1{%b3:%b2},%0\";
4938 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
4940 output_asm_insn (\"clr%.l %0\", operands);
4941 if (GET_CODE (operands[0]) == MEM)
4942 operands[0] = adjust_address (operands[0],
4943 INTVAL (operands[2]) == 8 ? QImode : HImode,
4944 (32 - INTVAL (operands[1])) / 8);
4946 if (INTVAL (operands[2]) == 8)
4947 return \"move%.b %1,%0\";
4948 return \"move%.w %1,%0\";
4952 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4953 ; alignment of structure members is specified.
4955 ; The move is allowed to be odd byte aligned, because that's still faster
4956 ; than an odd byte aligned bit field instruction.
4959 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4960 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4962 (match_operand:SI 2 "const_int_operand" "n")))]
4963 "TARGET_68020 && TARGET_BITFIELD
4964 && (INTVAL (operands[2]) % 8) == 0
4965 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4969 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4971 return \"move%.l %1,%0\";
4975 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4976 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4977 (match_operand:SI 2 "const_int_operand" "n")
4978 (match_operand:SI 3 "const_int_operand" "n")))]
4979 "TARGET_68020 && TARGET_BITFIELD
4980 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4981 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4982 && (GET_CODE (operands[1]) == REG
4983 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4986 if (REG_P (operands[1]))
4988 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4989 return \"bfexts %1{%b3:%b2},%0\";
4993 = adjust_address (operands[1],
4994 INTVAL (operands[2]) == 8 ? QImode : HImode,
4995 INTVAL (operands[3]) / 8);
4997 if (INTVAL (operands[2]) == 8)
4998 return \"move%.b %1,%0\;extb%.l %0\";
4999 return \"move%.w %1,%0\;ext%.l %0\";
5002 ;; Bit field instructions, general cases.
5003 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5004 ;; so that its address is reloaded.
5006 (define_expand "extv"
5007 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5008 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5009 (match_operand:SI 2 "general_operand" "")
5010 (match_operand:SI 3 "general_operand" "")))]
5011 "TARGET_68020 && TARGET_BITFIELD"
5015 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5016 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5017 (match_operand:SI 2 "general_operand" "di")
5018 (match_operand:SI 3 "general_operand" "di")))]
5019 "TARGET_68020 && TARGET_BITFIELD"
5020 "bfexts %1{%b3:%b2},%0")
5022 (define_expand "extzv"
5023 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5024 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5025 (match_operand:SI 2 "general_operand" "")
5026 (match_operand:SI 3 "general_operand" "")))]
5027 "TARGET_68020 && TARGET_BITFIELD"
5031 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
5032 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5033 (match_operand:SI 2 "general_operand" "di,di")
5034 (match_operand:SI 3 "general_operand" "di,di")))]
5035 "TARGET_68020 && TARGET_BITFIELD"
5038 if (GET_CODE (operands[2]) == CONST_INT)
5040 if (INTVAL (operands[2]) != 32)
5041 cc_status.flags |= CC_NOT_NEGATIVE;
5047 return \"bfextu %1{%b3:%b2},%0\";
5051 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5052 (match_operand:SI 1 "general_operand" "di")
5053 (match_operand:SI 2 "general_operand" "di"))
5054 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5055 (match_operand 3 "const_int_operand" "n")))]
5056 "TARGET_68020 && TARGET_BITFIELD
5057 && (INTVAL (operands[3]) == -1
5058 || (GET_CODE (operands[1]) == CONST_INT
5059 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5063 return \"bfchg %0{%b2:%b1}\";
5067 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5068 (match_operand:SI 1 "general_operand" "di")
5069 (match_operand:SI 2 "general_operand" "di"))
5071 "TARGET_68020 && TARGET_BITFIELD"
5075 return \"bfclr %0{%b2:%b1}\";
5079 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5080 (match_operand:SI 1 "general_operand" "di")
5081 (match_operand:SI 2 "general_operand" "di"))
5083 "TARGET_68020 && TARGET_BITFIELD"
5087 return \"bfset %0{%b2:%b1}\";
5090 (define_expand "insv"
5091 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5092 (match_operand:SI 1 "general_operand" "")
5093 (match_operand:SI 2 "general_operand" ""))
5094 (match_operand:SI 3 "register_operand" ""))]
5095 "TARGET_68020 && TARGET_BITFIELD"
5099 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5100 (match_operand:SI 1 "general_operand" "di")
5101 (match_operand:SI 2 "general_operand" "di"))
5102 (match_operand:SI 3 "register_operand" "d"))]
5103 "TARGET_68020 && TARGET_BITFIELD"
5104 "bfins %3,%0{%b2:%b1}")
5106 ;; Now recognize bit field insns that operate on registers
5107 ;; (or at least were intended to do so).
5110 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5111 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5112 (match_operand:SI 2 "general_operand" "di")
5113 (match_operand:SI 3 "general_operand" "di")))]
5114 "TARGET_68020 && TARGET_BITFIELD"
5115 "bfexts %1{%b3:%b2},%0")
5118 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5119 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5120 (match_operand:SI 2 "general_operand" "di")
5121 (match_operand:SI 3 "general_operand" "di")))]
5122 "TARGET_68020 && TARGET_BITFIELD"
5125 if (GET_CODE (operands[2]) == CONST_INT)
5127 if (INTVAL (operands[2]) != 32)
5128 cc_status.flags |= CC_NOT_NEGATIVE;
5134 return \"bfextu %1{%b3:%b2},%0\";
5138 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5139 (match_operand:SI 1 "general_operand" "di")
5140 (match_operand:SI 2 "general_operand" "di"))
5142 "TARGET_68020 && TARGET_BITFIELD"
5146 return \"bfclr %0{%b2:%b1}\";
5150 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5151 (match_operand:SI 1 "general_operand" "di")
5152 (match_operand:SI 2 "general_operand" "di"))
5154 "TARGET_68020 && TARGET_BITFIELD"
5158 return \"bfset %0{%b2:%b1}\";
5162 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5163 (match_operand:SI 1 "general_operand" "di")
5164 (match_operand:SI 2 "general_operand" "di"))
5165 (match_operand:SI 3 "register_operand" "d"))]
5166 "TARGET_68020 && TARGET_BITFIELD"
5170 /* These special cases are now recognized by a specific pattern. */
5171 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5172 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5173 return \"move%.w %3,%0\";
5174 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5175 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5176 return \"move%.b %3,%0\";
5178 return \"bfins %3,%0{%b2:%b1}\";
5181 ;; Special patterns for optimizing bit-field instructions.
5185 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5186 (match_operand:SI 1 "const_int_operand" "n")
5187 (match_operand:SI 2 "general_operand" "di")))]
5188 "TARGET_68020 && TARGET_BITFIELD"
5191 if (operands[1] == const1_rtx
5192 && GET_CODE (operands[2]) == CONST_INT)
5194 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5195 return output_btst (operands,
5196 GEN_INT (width - INTVAL (operands[2])),
5197 operands[0], insn, 1000);
5198 /* Pass 1000 as SIGNPOS argument so that btst will
5199 not think we are testing the sign bit for an `and'
5200 and assume that nonzero implies a negative result. */
5202 if (INTVAL (operands[1]) != 32)
5203 cc_status.flags = CC_NOT_NEGATIVE;
5204 return \"bftst %0{%b2:%b1}\";
5208 ;;; now handle the register cases
5211 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5212 (match_operand:SI 1 "const_int_operand" "n")
5213 (match_operand:SI 2 "general_operand" "di")))]
5214 "TARGET_68020 && TARGET_BITFIELD"
5217 if (operands[1] == const1_rtx
5218 && GET_CODE (operands[2]) == CONST_INT)
5220 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5221 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5222 operands[0], insn, 1000);
5223 /* Pass 1000 as SIGNPOS argument so that btst will
5224 not think we are testing the sign bit for an `and'
5225 and assume that nonzero implies a negative result. */
5227 if (INTVAL (operands[1]) != 32)
5228 cc_status.flags = CC_NOT_NEGATIVE;
5229 return \"bftst %0{%b2:%b1}\";
5232 (define_insn "scc0_di"
5233 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5234 (match_operator 1 "valid_dbcc_comparison_p"
5235 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5239 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5242 (define_insn "scc0_di_5200"
5243 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5244 (match_operator 1 "valid_dbcc_comparison_p"
5245 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5249 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5252 (define_insn "scc_di"
5253 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5254 (match_operator 1 "valid_dbcc_comparison_p"
5255 [(match_operand:DI 2 "general_operand" "ro,r")
5256 (match_operand:DI 3 "general_operand" "r,ro")]))]
5260 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5263 (define_insn "scc_di_5200"
5264 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5265 (match_operator 1 "valid_dbcc_comparison_p"
5266 [(match_operand:DI 2 "general_operand" "ro,r")
5267 (match_operand:DI 3 "general_operand" "r,ro")]))]
5271 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5274 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5275 ;; memory, but we cannot allow it to be in memory in case the address
5276 ;; needs to be reloaded.
5278 (define_expand "seq"
5279 [(set (match_operand:QI 0 "register_operand" "")
5280 (eq:QI (cc0) (const_int 0)))]
5284 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5286 m68k_last_compare_had_fp_operands = 0;
5292 [(set (match_operand:QI 0 "register_operand" "=d")
5293 (eq:QI (cc0) (const_int 0)))]
5296 cc_status = cc_prev_status;
5297 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5300 (define_expand "sne"
5301 [(set (match_operand:QI 0 "register_operand" "")
5302 (ne:QI (cc0) (const_int 0)))]
5306 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5308 m68k_last_compare_had_fp_operands = 0;
5314 [(set (match_operand:QI 0 "register_operand" "=d")
5315 (ne:QI (cc0) (const_int 0)))]
5318 cc_status = cc_prev_status;
5319 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5322 (define_expand "sgt"
5323 [(set (match_operand:QI 0 "register_operand" "")
5324 (gt:QI (cc0) (const_int 0)))]
5328 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5330 m68k_last_compare_had_fp_operands = 0;
5336 [(set (match_operand:QI 0 "register_operand" "=d")
5337 (gt:QI (cc0) (const_int 0)))]
5340 cc_status = cc_prev_status;
5341 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5344 (define_expand "sgtu"
5345 [(set (match_operand:QI 0 "register_operand" "")
5346 (gtu:QI (cc0) (const_int 0)))]
5351 [(set (match_operand:QI 0 "register_operand" "=d")
5352 (gtu:QI (cc0) (const_int 0)))]
5355 cc_status = cc_prev_status;
5356 return \"shi %0\"; ")
5358 (define_expand "slt"
5359 [(set (match_operand:QI 0 "register_operand" "")
5360 (lt:QI (cc0) (const_int 0)))]
5364 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5366 m68k_last_compare_had_fp_operands = 0;
5372 [(set (match_operand:QI 0 "register_operand" "=d")
5373 (lt:QI (cc0) (const_int 0)))]
5376 cc_status = cc_prev_status;
5377 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5379 (define_expand "sltu"
5380 [(set (match_operand:QI 0 "register_operand" "")
5381 (ltu:QI (cc0) (const_int 0)))]
5386 [(set (match_operand:QI 0 "register_operand" "=d")
5387 (ltu:QI (cc0) (const_int 0)))]
5390 cc_status = cc_prev_status;
5391 return \"scs %0\"; ")
5393 (define_expand "sge"
5394 [(set (match_operand:QI 0 "register_operand" "")
5395 (ge:QI (cc0) (const_int 0)))]
5399 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5401 m68k_last_compare_had_fp_operands = 0;
5407 [(set (match_operand:QI 0 "register_operand" "=d")
5408 (ge:QI (cc0) (const_int 0)))]
5411 cc_status = cc_prev_status;
5412 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5414 (define_expand "sgeu"
5415 [(set (match_operand:QI 0 "register_operand" "")
5416 (geu:QI (cc0) (const_int 0)))]
5421 [(set (match_operand:QI 0 "register_operand" "=d")
5422 (geu:QI (cc0) (const_int 0)))]
5425 cc_status = cc_prev_status;
5426 return \"scc %0\"; ")
5428 (define_expand "sle"
5429 [(set (match_operand:QI 0 "register_operand" "")
5430 (le:QI (cc0) (const_int 0)))]
5434 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5436 m68k_last_compare_had_fp_operands = 0;
5442 [(set (match_operand:QI 0 "register_operand" "=d")
5443 (le:QI (cc0) (const_int 0)))]
5446 cc_status = cc_prev_status;
5447 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5450 (define_expand "sleu"
5451 [(set (match_operand:QI 0 "register_operand" "")
5452 (leu:QI (cc0) (const_int 0)))]
5457 [(set (match_operand:QI 0 "register_operand" "=d")
5458 (leu:QI (cc0) (const_int 0)))]
5461 cc_status = cc_prev_status;
5462 return \"sls %0\"; ")
5464 (define_expand "sordered"
5465 [(set (match_operand:QI 0 "register_operand" "")
5466 (ordered:QI (cc0) (const_int 0)))]
5467 "TARGET_68881 && !TARGET_68060"
5469 if (! m68k_last_compare_had_fp_operands)
5471 m68k_last_compare_had_fp_operands = 0;
5474 (define_insn "*sordered_1"
5475 [(set (match_operand:QI 0 "register_operand" "=d")
5476 (ordered:QI (cc0) (const_int 0)))]
5477 "TARGET_68881 && !TARGET_68060"
5479 cc_status = cc_prev_status;
5483 (define_expand "sunordered"
5484 [(set (match_operand:QI 0 "register_operand" "")
5485 (unordered:QI (cc0) (const_int 0)))]
5486 "TARGET_68881 && !TARGET_68060"
5488 if (! m68k_last_compare_had_fp_operands)
5490 m68k_last_compare_had_fp_operands = 0;
5493 (define_insn "*sunordered_1"
5494 [(set (match_operand:QI 0 "register_operand" "=d")
5495 (unordered:QI (cc0) (const_int 0)))]
5496 "TARGET_68881 && !TARGET_68060"
5498 cc_status = cc_prev_status;
5502 (define_expand "suneq"
5503 [(set (match_operand:QI 0 "register_operand" "")
5504 (uneq:QI (cc0) (const_int 0)))]
5505 "TARGET_68881 && !TARGET_68060"
5507 if (! m68k_last_compare_had_fp_operands)
5509 m68k_last_compare_had_fp_operands = 0;
5512 (define_insn "*suneq_1"
5513 [(set (match_operand:QI 0 "register_operand" "=d")
5514 (uneq:QI (cc0) (const_int 0)))]
5515 "TARGET_68881 && !TARGET_68060"
5517 cc_status = cc_prev_status;
5521 (define_expand "sunge"
5522 [(set (match_operand:QI 0 "register_operand" "")
5523 (unge:QI (cc0) (const_int 0)))]
5524 "TARGET_68881 && !TARGET_68060"
5526 if (! m68k_last_compare_had_fp_operands)
5528 m68k_last_compare_had_fp_operands = 0;
5531 (define_insn "*sunge_1"
5532 [(set (match_operand:QI 0 "register_operand" "=d")
5533 (unge:QI (cc0) (const_int 0)))]
5534 "TARGET_68881 && !TARGET_68060"
5536 cc_status = cc_prev_status;
5540 (define_expand "sungt"
5541 [(set (match_operand:QI 0 "register_operand" "")
5542 (ungt:QI (cc0) (const_int 0)))]
5543 "TARGET_68881 && !TARGET_68060"
5545 if (! m68k_last_compare_had_fp_operands)
5547 m68k_last_compare_had_fp_operands = 0;
5550 (define_insn "*sungt_1"
5551 [(set (match_operand:QI 0 "register_operand" "=d")
5552 (ungt:QI (cc0) (const_int 0)))]
5553 "TARGET_68881 && !TARGET_68060"
5555 cc_status = cc_prev_status;
5559 (define_expand "sunle"
5560 [(set (match_operand:QI 0 "register_operand" "")
5561 (unle:QI (cc0) (const_int 0)))]
5562 "TARGET_68881 && !TARGET_68060"
5564 if (! m68k_last_compare_had_fp_operands)
5566 m68k_last_compare_had_fp_operands = 0;
5569 (define_insn "*sunle_1"
5570 [(set (match_operand:QI 0 "register_operand" "=d")
5571 (unle:QI (cc0) (const_int 0)))]
5572 "TARGET_68881 && !TARGET_68060"
5574 cc_status = cc_prev_status;
5578 (define_expand "sunlt"
5579 [(set (match_operand:QI 0 "register_operand" "")
5580 (unlt:QI (cc0) (const_int 0)))]
5581 "TARGET_68881 && !TARGET_68060"
5583 if (! m68k_last_compare_had_fp_operands)
5585 m68k_last_compare_had_fp_operands = 0;
5588 (define_insn "*sunlt_1"
5589 [(set (match_operand:QI 0 "register_operand" "=d")
5590 (unlt:QI (cc0) (const_int 0)))]
5591 "TARGET_68881 && !TARGET_68060"
5593 cc_status = cc_prev_status;
5597 (define_expand "sltgt"
5598 [(set (match_operand:QI 0 "register_operand" "")
5599 (ltgt:QI (cc0) (const_int 0)))]
5600 "TARGET_68881 && !TARGET_68060"
5602 if (! m68k_last_compare_had_fp_operands)
5604 m68k_last_compare_had_fp_operands = 0;
5607 (define_insn "*sltgt_1"
5608 [(set (match_operand:QI 0 "register_operand" "=d")
5609 (ltgt:QI (cc0) (const_int 0)))]
5610 "TARGET_68881 && !TARGET_68060"
5612 cc_status = cc_prev_status;
5616 (define_insn "*fsogt_1"
5617 [(set (match_operand:QI 0 "register_operand" "=d")
5618 (not:QI (unle:QI (cc0) (const_int 0))))]
5619 "TARGET_68881 && !TARGET_68060"
5621 cc_status = cc_prev_status;
5625 (define_insn "*fsoge_1"
5626 [(set (match_operand:QI 0 "register_operand" "=d")
5627 (not:QI (unlt:QI (cc0) (const_int 0))))]
5628 "TARGET_68881 && !TARGET_68060"
5630 cc_status = cc_prev_status;
5634 (define_insn "*fsolt_1"
5635 [(set (match_operand:QI 0 "register_operand" "=d")
5636 (not:QI (unge:QI (cc0) (const_int 0))))]
5637 "TARGET_68881 && !TARGET_68060"
5639 cc_status = cc_prev_status;
5643 (define_insn "*fsole_1"
5644 [(set (match_operand:QI 0 "register_operand" "=d")
5645 (not:QI (ungt:QI (cc0) (const_int 0))))]
5646 "TARGET_68881 && !TARGET_68060"
5648 cc_status = cc_prev_status;
5652 ;; Basic conditional jump instructions.
5654 (define_insn "beq0_di"
5656 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5658 (label_ref (match_operand 1 "" ","))
5660 (clobber (match_scratch:SI 2 "=d,d"))]
5665 if (which_alternative == 1)
5667 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5669 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5671 if ((cc_prev_status.value1
5672 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5673 || (cc_prev_status.value2
5674 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5676 cc_status = cc_prev_status;
5678 return \"jbeq %l1\";
5683 if (GET_CODE (operands[0]) == REG)
5684 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5686 operands[3] = adjust_address (operands[0], SImode, 4);
5687 if (! ADDRESS_REG_P (operands[0]))
5689 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5691 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5694 return \"or%.l %0,%2\;jbeq %l1\";
5696 return \"or%.l %0,%2\;jeq %l1\";
5702 return \"or%.l %3,%2\;jbeq %l1\";
5704 return \"or%.l %3,%2\;jeq %l1\";
5709 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5711 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5714 operands[4] = gen_label_rtx();
5715 if (TARGET_68020 || TARGET_COLDFIRE)
5718 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5720 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5726 #ifdef SGS_CMP_ORDER
5727 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5729 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5732 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5735 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5736 CODE_LABEL_NUMBER (operands[4]));
5740 (define_insn "bne0_di"
5742 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5744 (label_ref (match_operand 1 "" ","))
5746 (clobber (match_scratch:SI 2 "=d,X"))]
5750 if ((cc_prev_status.value1
5751 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5752 || (cc_prev_status.value2
5753 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5755 cc_status = cc_prev_status;
5757 return \"jbne %l1\";
5763 if (GET_CODE (operands[0]) == REG)
5764 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5766 operands[3] = adjust_address (operands[0], SImode, 4);
5767 if (!ADDRESS_REG_P (operands[0]))
5769 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5771 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5774 return \"or%.l %0,%2\;jbne %l1\";
5776 return \"or%.l %0,%2\;jne %l1\";
5782 return \"or%.l %3,%2\;jbne %l1\";
5784 return \"or%.l %3,%2\;jne %l1\";
5789 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5791 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5794 if (TARGET_68020 || TARGET_COLDFIRE)
5797 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5799 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5805 #ifdef SGS_CMP_ORDER
5806 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5808 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5811 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5816 (define_insn "bge0_di"
5818 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5820 (label_ref (match_operand 1 "" ""))
5825 if ((cc_prev_status.value1
5826 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5827 || (cc_prev_status.value2
5828 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5830 cc_status = cc_prev_status;
5831 if (cc_status.flags & CC_REVERSED)
5834 return \"jble %l1\";
5842 return \"jbpl %l1\";
5849 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5850 output_asm_insn(\"tst%.l %0\", operands);
5853 /* On an address reg, cmpw may replace cmpl. */
5854 #ifdef SGS_CMP_ORDER
5855 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5857 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5862 return \"jbpl %l1\";
5868 (define_insn "blt0_di"
5870 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5872 (label_ref (match_operand 1 "" ""))
5877 if ((cc_prev_status.value1
5878 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5879 || (cc_prev_status.value2
5880 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5882 cc_status = cc_prev_status;
5883 if (cc_status.flags & CC_REVERSED)
5886 return \"jbgt %l1\";
5894 return \"jbmi %l1\";
5901 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5902 output_asm_insn(\"tst%.l %0\", operands);
5905 /* On an address reg, cmpw may replace cmpl. */
5906 #ifdef SGS_CMP_ORDER
5907 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5909 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5914 return \"jbmi %l1\";
5922 (if_then_else (eq (cc0)
5924 (label_ref (match_operand 0 "" ""))
5930 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5932 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5938 (if_then_else (ne (cc0)
5940 (label_ref (match_operand 0 "" ""))
5946 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5948 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5954 (if_then_else (gt (cc0)
5956 (label_ref (match_operand 0 "" ""))
5961 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5963 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5969 (if_then_else (gtu (cc0)
5971 (label_ref (match_operand 0 "" ""))
5976 return \"jbhi %l0\";
5984 (if_then_else (lt (cc0)
5986 (label_ref (match_operand 0 "" ""))
5991 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5993 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5999 (if_then_else (ltu (cc0)
6001 (label_ref (match_operand 0 "" ""))
6006 return \"jbcs %l0\";
6014 (if_then_else (ge (cc0)
6016 (label_ref (match_operand 0 "" ""))
6021 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6023 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6029 (if_then_else (geu (cc0)
6031 (label_ref (match_operand 0 "" ""))
6036 return \"jbcc %l0\";
6044 (if_then_else (le (cc0)
6046 (label_ref (match_operand 0 "" ""))
6051 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6053 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6059 (if_then_else (leu (cc0)
6061 (label_ref (match_operand 0 "" ""))
6066 return \"jbls %l0\";
6072 (define_insn "bordered"
6074 (if_then_else (ordered (cc0) (const_int 0))
6075 (label_ref (match_operand 0 "" ""))
6079 if (!(cc_prev_status.flags & CC_IN_68881))
6088 (define_insn "bunordered"
6090 (if_then_else (unordered (cc0) (const_int 0))
6091 (label_ref (match_operand 0 "" ""))
6095 if (!(cc_prev_status.flags & CC_IN_68881))
6104 (define_insn "buneq"
6106 (if_then_else (uneq (cc0) (const_int 0))
6107 (label_ref (match_operand 0 "" ""))
6111 if (!(cc_prev_status.flags & CC_IN_68881))
6120 (define_insn "bunge"
6122 (if_then_else (unge (cc0) (const_int 0))
6123 (label_ref (match_operand 0 "" ""))
6127 if (!(cc_prev_status.flags & CC_IN_68881))
6136 (define_insn "bungt"
6138 (if_then_else (ungt (cc0) (const_int 0))
6139 (label_ref (match_operand 0 "" ""))
6143 if (!(cc_prev_status.flags & CC_IN_68881))
6152 (define_insn "bunle"
6154 (if_then_else (unle (cc0) (const_int 0))
6155 (label_ref (match_operand 0 "" ""))
6159 if (!(cc_prev_status.flags & CC_IN_68881))
6168 (define_insn "bunlt"
6170 (if_then_else (unlt (cc0) (const_int 0))
6171 (label_ref (match_operand 0 "" ""))
6175 if (!(cc_prev_status.flags & CC_IN_68881))
6184 (define_insn "bltgt"
6186 (if_then_else (ltgt (cc0) (const_int 0))
6187 (label_ref (match_operand 0 "" ""))
6191 if (!(cc_prev_status.flags & CC_IN_68881))
6200 ;; Negated conditional jump instructions.
6204 (if_then_else (eq (cc0)
6207 (label_ref (match_operand 0 "" ""))))]
6212 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6214 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6220 (if_then_else (ne (cc0)
6223 (label_ref (match_operand 0 "" ""))))]
6228 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6230 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6236 (if_then_else (gt (cc0)
6239 (label_ref (match_operand 0 "" ""))))]
6243 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6245 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6251 (if_then_else (gtu (cc0)
6254 (label_ref (match_operand 0 "" ""))))]
6258 return \"jbls %l0\";
6266 (if_then_else (lt (cc0)
6269 (label_ref (match_operand 0 "" ""))))]
6273 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6275 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6281 (if_then_else (ltu (cc0)
6284 (label_ref (match_operand 0 "" ""))))]
6288 return \"jbcc %l0\";
6296 (if_then_else (ge (cc0)
6299 (label_ref (match_operand 0 "" ""))))]
6303 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6305 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6311 (if_then_else (geu (cc0)
6314 (label_ref (match_operand 0 "" ""))))]
6318 return \"jbcs %l0\";
6326 (if_then_else (le (cc0)
6329 (label_ref (match_operand 0 "" ""))))]
6333 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6335 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6341 (if_then_else (leu (cc0)
6344 (label_ref (match_operand 0 "" ""))))]
6348 return \"jbhi %l0\";
6354 (define_insn "*bordered_rev"
6356 (if_then_else (ordered (cc0) (const_int 0))
6358 (label_ref (match_operand 0 "" ""))))]
6361 if (!(cc_prev_status.flags & CC_IN_68881))
6370 (define_insn "*bunordered_rev"
6372 (if_then_else (unordered (cc0) (const_int 0))
6374 (label_ref (match_operand 0 "" ""))))]
6377 if (!(cc_prev_status.flags & CC_IN_68881))
6386 (define_insn "*buneq_rev"
6388 (if_then_else (uneq (cc0) (const_int 0))
6390 (label_ref (match_operand 0 "" ""))))]
6393 if (!(cc_prev_status.flags & CC_IN_68881))
6402 (define_insn "*bunge_rev"
6404 (if_then_else (unge (cc0) (const_int 0))
6406 (label_ref (match_operand 0 "" ""))))]
6409 if (!(cc_prev_status.flags & CC_IN_68881))
6418 (define_insn "*bunle_rev"
6420 (if_then_else (unle (cc0) (const_int 0))
6422 (label_ref (match_operand 0 "" ""))))]
6425 if (!(cc_prev_status.flags & CC_IN_68881))
6434 (define_insn "*bunlt_rev"
6436 (if_then_else (unlt (cc0) (const_int 0))
6438 (label_ref (match_operand 0 "" ""))))]
6441 if (!(cc_prev_status.flags & CC_IN_68881))
6450 (define_insn "*bltgt_rev"
6452 (if_then_else (ltgt (cc0) (const_int 0))
6454 (label_ref (match_operand 0 "" ""))))]
6457 if (!(cc_prev_status.flags & CC_IN_68881))
6466 ;; Unconditional and other jump instructions
6469 (label_ref (match_operand 0 "" "")))]
6473 return \"jbra %l0\";
6479 ;; We support two different ways of handling dispatch tables.
6480 ;; The NeXT uses absolute tables, and other machines use relative.
6481 ;; This define_expand can generate either kind.
6482 (define_expand "tablejump"
6483 [(parallel [(set (pc) (match_operand 0 "" ""))
6484 (use (label_ref (match_operand 1 "" "")))])]
6488 #ifdef CASE_VECTOR_PC_RELATIVE
6489 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6490 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6494 ;; Jump to variable address from dispatch table of absolute addresses.
6496 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6497 (use (label_ref (match_operand 1 "" "")))]
6501 return \"jmp (%0)\";
6507 ;; Jump to variable address from dispatch table of relative addresses.
6511 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6512 (use (label_ref (match_operand 1 "" "")))]
6515 #ifdef ASM_RETURN_CASE_JUMP
6516 ASM_RETURN_CASE_JUMP;
6519 #ifdef ASM_OUTPUT_CASE_LABEL
6520 if (TARGET_COLDFIRE)
6522 if (ADDRESS_REG_P (operands[0]))
6523 return \"jmp 6(%%pc,%0.l)\";
6525 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6528 return \"jmp 6(%%pc,%0.w)\";
6530 if (TARGET_COLDFIRE)
6532 if (ADDRESS_REG_P (operands[0]))
6533 return \"jmp 2(%%pc,%0.l)\";
6535 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6538 return \"jmp 2(%%pc,%0.w)\";
6541 if (TARGET_COLDFIRE)
6543 if (ADDRESS_REG_P (operands[0]))
6546 return \"jmp (2,pc,%0.l)\";
6548 return \"jmp pc@(2,%0:l)\";
6554 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6556 return \"extl %0\;jmp pc@(2,%0:l)\";
6563 return \"jmp (2,pc,%0.w)\";
6565 return \"jmp pc@(2,%0:w)\";
6572 ;; Decrement-and-branch insns.
6576 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6578 (label_ref (match_operand 1 "" ""))
6581 (plus:HI (match_dup 0)
6587 if (DATA_REG_P (operands[0]))
6588 return \"dbra %0,%l1\";
6589 if (GET_CODE (operands[0]) == MEM)
6592 return \"subq%.w %#1,%0\;jbcc %l1\";
6593 #else /* not MOTOROLA */
6594 return \"subqw %#1,%0\;jcc %l1\";
6598 #ifdef SGS_CMP_ORDER
6599 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6600 #else /* not SGS_CMP_ORDER */
6601 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6603 #else /* not MOTOROLA */
6604 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6611 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6613 (label_ref (match_operand 1 "" ""))
6616 (plus:SI (match_dup 0)
6623 if (DATA_REG_P (operands[0]))
6624 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6625 if (GET_CODE (operands[0]) == MEM)
6626 return \"subq%.l %#1,%0\;jbcc %l1\";
6627 #ifdef SGS_CMP_ORDER
6628 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6629 #else /* not SGS_CMP_ORDER */
6630 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6631 #endif /* not SGS_CMP_ORDER */
6632 #else /* not MOTOROLA */
6633 if (DATA_REG_P (operands[0]))
6634 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6635 if (GET_CODE (operands[0]) == MEM)
6636 return \"subql %#1,%0\;jcc %l1\";
6637 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6638 #endif /* not MOTOROLA */
6641 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6646 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6649 (label_ref (match_operand 1 "" ""))
6652 (plus:HI (match_dup 0)
6654 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6659 if (DATA_REG_P (operands[0]))
6660 return \"dbra %0,%l1\";
6661 if (GET_CODE (operands[0]) == MEM)
6662 return \"subq%.w %#1,%0\;jbcc %l1\";
6663 #ifdef SGS_CMP_ORDER
6664 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6665 #else /* not SGS_CMP_ORDER */
6666 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6667 #endif /* not SGS_CMP_ORDER */
6668 #else /* not MOTOROLA */
6669 if (DATA_REG_P (operands[0]))
6670 return \"dbra %0,%l1\";
6671 if (GET_CODE (operands[0]) == MEM)
6672 return \"subqw %#1,%0\;jcc %l1\";
6673 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6674 #endif /* not MOTOROLA */
6677 (define_expand "decrement_and_branch_until_zero"
6678 [(parallel [(set (pc)
6680 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6683 (label_ref (match_operand 1 "" ""))
6686 (plus:SI (match_dup 0)
6694 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6697 (label_ref (match_operand 1 "" ""))
6700 (plus:SI (match_dup 0)
6702 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6707 if (DATA_REG_P (operands[0]))
6708 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6709 if (GET_CODE (operands[0]) == MEM)
6710 return \"subq%.l %#1,%0\;jbcc %l1\";
6711 #ifdef SGS_CMP_ORDER
6712 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6713 #else /* not SGS_CMP_ORDER */
6714 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6715 #endif /* not SGS_CMP_ORDER */
6716 #else /* not MOTOROLA */
6717 if (DATA_REG_P (operands[0]))
6718 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6719 if (GET_CODE (operands[0]) == MEM)
6720 return \"subql %#1,%0\;jcc %l1\";
6721 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6722 #endif /* not MOTOROLA */
6726 ;; For PIC calls, in order to be able to support
6727 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6728 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6730 ;; PIC calls are handled by loading the address of the function into a
6731 ;; register (via movsi), then emitting a register indirect call using
6732 ;; the "jsr" function call syntax.
6734 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6735 ;; operand to the jbsr statement to indicate that this call should
6736 ;; go through the PLT (why? because this is the way that Sun does it).
6738 ;; We have different patterns for PIC calls and non-PIC calls. The
6739 ;; different patterns are only used to choose the right syntax.
6741 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6742 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6743 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6744 ;; section at link time. However, all global objects reference are still
6745 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6746 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6747 ;; We need to have a way to differentiate these two different operands.
6749 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6750 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6751 ;; to be changed to recognize function calls symbol_ref operand as a valid
6752 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6753 ;; avoid the compiler to load this symbol_ref operand into a register.
6754 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6755 ;; since the value is a PC relative offset, not a real address.
6757 ;; All global objects are treated in the similar way as in SUN3. The only
6758 ;; difference is: on m68k svr4, the reference of such global object needs
6759 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6760 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6763 ;; Call subroutine with no return value.
6764 (define_expand "call"
6765 [(call (match_operand:QI 0 "memory_operand" "")
6766 (match_operand:SI 1 "general_operand" ""))]
6767 ;; Operand 1 not really used on the m68000.
6772 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6773 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6776 ;; This is a normal call sequence.
6778 [(call (match_operand:QI 0 "memory_operand" "o")
6779 (match_operand:SI 1 "general_operand" "g"))]
6780 ;; Operand 1 not really used on the m68000.
6784 #if defined (MOTOROLA) && !defined (USE_GAS)
6791 ;; This is a PIC call sequence.
6793 [(call (match_operand:QI 0 "memory_operand" "o")
6794 (match_operand:SI 1 "general_operand" "g"))]
6795 ;; Operand 1 not really used on the m68000.
6799 if (GET_CODE (operands[0]) == MEM
6800 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6802 if (TARGET_PCREL) return \"bsr.l %o0\";
6805 return \"bsr.l %0\";
6808 return \"bsr.l %0@PLTPC\";
6810 return \"bsr %0@PLTPC\";
6815 return \"bsr.l %0\";
6817 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6818 GAS just plain ignores it. FIXME: not anymore, gas doesn't! */
6819 return \"jbsr %0,a1\";
6826 ;; Call subroutine, returning value in operand 0
6827 ;; (which must be a hard register).
6828 ;; See comments before "call" regarding PIC calls.
6829 (define_expand "call_value"
6830 [(set (match_operand 0 "" "")
6831 (call (match_operand:QI 1 "memory_operand" "")
6832 (match_operand:SI 2 "general_operand" "")))]
6833 ;; Operand 2 not really used on the m68000.
6837 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6838 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6841 ;; This is a normal call_value
6843 [(set (match_operand 0 "" "=rf")
6844 (call (match_operand:QI 1 "memory_operand" "o")
6845 (match_operand:SI 2 "general_operand" "g")))]
6846 ;; Operand 2 not really used on the m68000.
6849 #if defined (MOTOROLA) && !defined (USE_GAS)
6856 ;; This is a PIC call_value
6858 [(set (match_operand 0 "" "=rf")
6859 (call (match_operand:QI 1 "memory_operand" "o")
6860 (match_operand:SI 2 "general_operand" "g")))]
6861 ;; Operand 2 not really used on the m68000.
6864 if (GET_CODE (operands[1]) == MEM
6865 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6867 if (TARGET_PCREL) return \"bsr.l %o1\";
6870 return \"bsr.l %1\";
6873 return \"bsr.l %1@PLTPC\";
6875 return \"bsr %1@PLTPC\";
6880 return \"bsr.l %1\";
6882 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6883 GAS just plain ignores it. FIXME: Not anymore, gas doesn't! */
6884 return \"jbsr %1,a1\";
6891 ;; Call subroutine returning any type.
6893 (define_expand "untyped_call"
6894 [(parallel [(call (match_operand 0 "" "")
6896 (match_operand 1 "" "")
6897 (match_operand 2 "" "")])]
6898 "NEEDS_UNTYPED_CALL"
6903 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6905 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6907 rtx set = XVECEXP (operands[2], 0, i);
6908 emit_move_insn (SET_DEST (set), SET_SRC (set));
6911 /* The optimizer does not know that the call sets the function value
6912 registers we stored in the result block. We avoid problems by
6913 claiming that all hard registers are used and clobbered at this
6915 emit_insn (gen_blockage ());
6920 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6921 ;; all of memory. This blocks insns from being moved across this point.
6923 (define_insn "blockage"
6924 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6933 ;; Used for frameless functions which save no regs and allocate no locals.
6934 (define_insn "return"
6939 if (current_function_pops_args == 0)
6941 operands[0] = GEN_INT (current_function_pops_args);
6945 (define_insn "indirect_jump"
6946 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6950 ;; This should not be used unless the add/sub insns can't be.
6953 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
6954 (match_operand:QI 1 "address_operand" "p"))]
6958 /* Recognize an insn that refers to a table of offsets. Such an insn will
6959 need to refer to a label on the insn. So output one. Use the
6960 label-number of the table of offsets to generate this label. This code,
6961 and similar code above, assumes that there will be at most one reference
6963 if (GET_CODE (operands[1]) == PLUS
6964 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6965 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6967 rtx labelref = XEXP (operands[1], 1);
6968 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6970 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6971 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6973 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6974 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6975 #endif /* not SGS */
6976 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6977 (*targetm.asm_out.internal_label) (asm_out_file, \"LI\",
6978 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6979 #ifdef SGS_SWITCH_TABLES
6980 /* Set flag saying we need to define the symbol
6981 LD%n (with value L%n-LI%n) at the end of the switch table. */
6982 switch_table_difference_label_flag = 1;
6983 #endif /* SGS_SWITCH_TABLES */
6984 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6987 return \"lea %a1,%0\";
6990 ;; This is the first machine-dependent peephole optimization.
6991 ;; It is useful when a floating value is returned from a function call
6992 ;; and then is moved into an FP register.
6993 ;; But it is mainly intended to test the support for these optimizations.
6996 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6997 (set (match_operand:DF 0 "register_operand" "=f")
6998 (match_operand:DF 1 "register_operand" "ad"))]
6999 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7003 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7004 output_asm_insn (\"move%.l %1,%@\", xoperands);
7005 output_asm_insn (\"move%.l %1,%-\", operands);
7006 return \"fmove%.d %+,%0\";
7010 ;; Optimize a stack-adjust followed by a push of an argument.
7011 ;; This is said to happen frequently with -msoft-float
7012 ;; when there are consecutive library calls.
7015 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7016 (match_operand:SI 0 "const_int_operand" "n")))
7017 (set (match_operand:SF 1 "push_operand" "=m")
7018 (match_operand:SF 2 "general_operand" "rmfF"))]
7019 "INTVAL (operands[0]) >= 4
7020 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7023 if (INTVAL (operands[0]) > 4)
7026 xoperands[0] = stack_pointer_rtx;
7027 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7028 if (INTVAL (xoperands[1]) <= 8)
7030 if (!TARGET_COLDFIRE)
7031 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7033 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7035 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7037 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7038 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7040 else if (INTVAL (xoperands[1]) <= 0x7FFF)
7043 output_asm_insn (\"add%.w %1,%0\", xoperands);
7046 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7048 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7052 output_asm_insn (\"add%.l %1,%0\", xoperands);
7054 if (FP_REG_P (operands[2]))
7055 return \"fmove%.s %2,%@\";
7056 return \"move%.l %2,%@\";
7059 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7062 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7063 (match_operand:SI 0 "const_int_operand" "n")))
7064 (set (match_operand:SI 1 "push_operand" "=m")
7065 (match_operand:SI 2 "general_operand" "g"))]
7066 "INTVAL (operands[0]) >= 4
7067 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7070 if (INTVAL (operands[0]) > 4)
7073 xoperands[0] = stack_pointer_rtx;
7074 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7075 if (INTVAL (xoperands[1]) <= 8)
7077 if (!TARGET_COLDFIRE)
7078 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7080 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7082 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7084 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7085 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7087 else if (INTVAL (xoperands[1]) <= 0x7FFF)
7090 output_asm_insn (\"add%.w %1,%0\", xoperands);
7094 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7096 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7101 output_asm_insn (\"add%.l %1,%0\", xoperands);
7103 if (operands[2] == const0_rtx)
7104 return \"clr%.l %@\";
7105 return \"move%.l %2,%@\";
7108 ;; Speed up pushing a single byte but leaving four bytes of space.
7111 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7112 (match_operand:QI 1 "general_operand" "dami"))
7113 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7114 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7119 if (GET_CODE (operands[1]) == REG)
7120 return \"move%.l %1,%-\";
7122 xoperands[1] = operands[1];
7124 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7125 xoperands[3] = stack_pointer_rtx;
7126 if (!TARGET_COLDFIRE)
7127 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7129 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7134 [(set (match_operand:SI 0 "register_operand" "=d")
7136 (set (strict_low_part (subreg:HI (match_dup 0) 2))
7137 (match_operand:HI 1 "general_operand" "rmn"))]
7138 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7141 if (GET_CODE (operands[1]) == CONST_INT)
7143 if (operands[1] == const0_rtx
7144 && (DATA_REG_P (operands[0])
7145 || GET_CODE (operands[0]) == MEM)
7146 /* clr insns on 68000 read before writing.
7147 This isn't so on the 68010, but we have no TARGET_68010. */
7148 && ((TARGET_68020 || TARGET_COLDFIRE)
7149 || !(GET_CODE (operands[0]) == MEM
7150 && MEM_VOLATILE_P (operands[0]))))
7151 return \"clr%.w %0\";
7153 return \"move%.w %1,%0\";
7161 ;; jCC label ; abnormal loop termination
7162 ;; dbra dN, loop ; normal loop termination
7170 ;; Which moves the jCC condition outside the inner loop for free.
7174 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7175 [(cc0) (const_int 0)])
7176 (label_ref (match_operand 2 "" ""))
7181 (ne (match_operand:HI 0 "register_operand" "")
7183 (label_ref (match_operand 1 "" ""))
7186 (plus:HI (match_dup 0)
7188 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7192 output_dbcc_and_branch (operands);
7197 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7198 [(cc0) (const_int 0)])
7199 (label_ref (match_operand 2 "" ""))
7204 (ne (match_operand:SI 0 "register_operand" "")
7206 (label_ref (match_operand 1 "" ""))
7209 (plus:SI (match_dup 0)
7211 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7215 output_dbcc_and_branch (operands);
7220 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7221 [(cc0) (const_int 0)])
7222 (label_ref (match_operand 2 "" ""))
7227 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
7230 (label_ref (match_operand 1 "" ""))
7233 (plus:HI (match_dup 0)
7235 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7239 output_dbcc_and_branch (operands);
7244 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7245 [(cc0) (const_int 0)])
7246 (label_ref (match_operand 2 "" ""))
7251 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
7254 (label_ref (match_operand 1 "" ""))
7257 (plus:SI (match_dup 0)
7259 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7263 output_dbcc_and_branch (operands);
7268 (define_expand "tstxf"
7270 (match_operand:XF 0 "nonimmediate_operand" ""))]
7272 "m68k_last_compare_had_fp_operands = 1;")
7276 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7280 cc_status.flags = CC_IN_68881;
7281 return \"ftst%.x %0\";
7284 (define_expand "cmpxf"
7286 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7287 (match_operand:XF 1 "nonimmediate_operand" "")))]
7289 "m68k_last_compare_had_fp_operands = 1;")
7293 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7294 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7298 cc_status.flags = CC_IN_68881;
7299 #ifdef SGS_CMP_ORDER
7300 if (REG_P (operands[0]))
7302 if (REG_P (operands[1]))
7303 return \"fcmp%.x %0,%1\";
7305 return \"fcmp%.x %0,%f1\";
7307 cc_status.flags |= CC_REVERSED;
7308 return \"fcmp%.x %1,%f0\";
7310 if (REG_P (operands[0]))
7312 if (REG_P (operands[1]))
7313 return \"fcmp%.x %1,%0\";
7315 return \"fcmp%.x %f1,%0\";
7317 cc_status.flags |= CC_REVERSED;
7318 return \"fcmp%.x %f0,%1\";
7322 (define_insn "extendsfxf2"
7323 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7324 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7328 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7330 if (REGNO (operands[0]) == REGNO (operands[1]))
7332 /* Extending float to double in an fp-reg is a no-op.
7333 NOTICE_UPDATE_CC has already assumed that the
7334 cc will be set. So cancel what it did. */
7335 cc_status = cc_prev_status;
7338 return \"f%$move%.x %1,%0\";
7340 if (FP_REG_P (operands[0]))
7342 if (FP_REG_P (operands[1]))
7343 return \"f%$move%.x %1,%0\";
7344 else if (ADDRESS_REG_P (operands[1]))
7345 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7346 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7347 return output_move_const_single (operands);
7348 return \"f%$move%.s %f1,%0\";
7350 return \"fmove%.x %f1,%0\";
7354 (define_insn "extenddfxf2"
7355 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7357 (match_operand:DF 1 "general_operand" "f,rmE")))]
7361 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7363 if (REGNO (operands[0]) == REGNO (operands[1]))
7365 /* Extending float to double in an fp-reg is a no-op.
7366 NOTICE_UPDATE_CC has already assumed that the
7367 cc will be set. So cancel what it did. */
7368 cc_status = cc_prev_status;
7371 return \"fmove%.x %1,%0\";
7373 if (FP_REG_P (operands[0]))
7375 if (REG_P (operands[1]))
7378 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7379 output_asm_insn (\"move%.l %1,%-\", xoperands);
7380 output_asm_insn (\"move%.l %1,%-\", operands);
7381 return \"f%&move%.d %+,%0\";
7383 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7384 return output_move_const_double (operands);
7385 return \"f%&move%.d %f1,%0\";
7387 return \"fmove%.x %f1,%0\";
7390 (define_insn "truncxfdf2"
7391 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
7393 (match_operand:XF 1 "general_operand" "f,f")))]
7397 if (REG_P (operands[0]))
7399 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7400 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7401 return \"move%.l %+,%0\";
7403 return \"fmove%.d %f1,%0\";
7406 (define_insn "truncxfsf2"
7407 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
7409 (match_operand:XF 1 "general_operand" "f")))]
7413 (define_insn "floatsixf2"
7414 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7415 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7419 (define_insn "floathixf2"
7420 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7421 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7425 (define_insn "floatqixf2"
7426 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7427 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7431 (define_insn "ftruncxf2"
7432 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7433 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7437 if (FP_REG_P (operands[1]))
7438 return \"fintrz%.x %f1,%0\";
7439 return \"fintrz%.x %f1,%0\";
7442 (define_insn "fixxfqi2"
7443 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
7444 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7448 (define_insn "fixxfhi2"
7449 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
7450 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7454 (define_insn "fixxfsi2"
7455 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
7456 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7461 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7462 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7463 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7468 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7469 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7470 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7475 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7476 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7477 (match_operand:XF 1 "general_operand" "0")))]
7481 (define_insn "addxf3"
7482 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7483 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7484 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7488 if (REG_P (operands[2]))
7489 return \"fadd%.x %2,%0\";
7490 return \"fadd%.x %f2,%0\";
7494 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7495 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7496 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7501 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7502 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7503 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7508 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7509 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7510 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7514 (define_insn "subxf3"
7515 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7516 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7517 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7521 if (REG_P (operands[2]))
7522 return \"fsub%.x %2,%0\";
7523 return \"fsub%.x %f2,%0\";
7527 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7528 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7529 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7534 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7535 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7536 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7541 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7542 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7543 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7547 (define_insn "mulxf3"
7548 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7549 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7550 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7554 if (REG_P (operands[2]))
7555 return \"fmul%.x %2,%0\";
7556 return \"fmul%.x %f2,%0\";
7560 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7561 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7562 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7567 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7568 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7569 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7574 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7575 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7576 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7580 (define_insn "divxf3"
7581 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7582 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7583 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7587 if (REG_P (operands[2]))
7588 return \"fdiv%.x %2,%0\";
7589 return \"fdiv%.x %f2,%0\";
7592 (define_expand "negxf2"
7593 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7594 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7605 target = operand_subword (operands[0], 0, 1, XFmode);
7606 result = expand_binop (SImode, xor_optab,
7607 operand_subword_force (operands[1], 0, XFmode),
7608 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7612 if (result != target)
7613 emit_move_insn (result, target);
7615 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7616 operand_subword_force (operands[1], 1, XFmode));
7617 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7618 operand_subword_force (operands[1], 2, XFmode));
7620 insns = get_insns ();
7623 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7628 (define_insn "negxf2_68881"
7629 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7630 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7634 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7635 return \"fneg%.x %1,%0\";
7636 return \"fneg%.x %f1,%0\";
7639 (define_expand "absxf2"
7640 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7641 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7652 target = operand_subword (operands[0], 0, 1, XFmode);
7653 result = expand_binop (SImode, and_optab,
7654 operand_subword_force (operands[1], 0, XFmode),
7655 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7659 if (result != target)
7660 emit_move_insn (result, target);
7662 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7663 operand_subword_force (operands[1], 1, XFmode));
7664 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7665 operand_subword_force (operands[1], 2, XFmode));
7667 insns = get_insns ();
7670 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7675 (define_insn "absxf2_68881"
7676 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7677 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7681 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7682 return \"fabs%.x %1,%0\";
7683 return \"fabs%.x %f1,%0\";
7686 (define_insn "sqrtxf2"
7687 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7688 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7692 (define_insn "sinsf2"
7693 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7694 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_SIN))]
7695 "TARGET_68881 && flag_unsafe_math_optimizations"
7698 if (FP_REG_P (operands[1]))
7699 return \"fsin%.x %1,%0\";
7701 return \"fsin%.s %1,%0\";
7704 (define_insn "sindf2"
7705 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7706 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_SIN))]
7707 "TARGET_68881 && flag_unsafe_math_optimizations"
7710 if (FP_REG_P (operands[1]))
7711 return \"fsin%.x %1,%0\";
7713 return \"fsin%.d %1,%0\";
7716 (define_insn "sinxf2"
7717 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7718 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_SIN))]
7719 "TARGET_68881 && flag_unsafe_math_optimizations"
7722 (define_insn "cossf2"
7723 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7724 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_COS))]
7725 "TARGET_68881 && flag_unsafe_math_optimizations"
7728 if (FP_REG_P (operands[1]))
7729 return \"fcos%.x %1,%0\";
7731 return \"fcos%.s %1,%0\";
7734 (define_insn "cosdf2"
7735 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7736 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_COS))]
7737 "TARGET_68881 && flag_unsafe_math_optimizations"
7740 if (FP_REG_P (operands[1]))
7741 return \"fcos%.x %1,%0\";
7743 return \"fcos%.d %1,%0\";
7746 (define_insn "cosxf2"
7747 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7748 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_COS))]
7749 "TARGET_68881 && flag_unsafe_math_optimizations"
7753 [(trap_if (const_int -1) (const_int 7))]
7757 (define_insn "conditional_trap"
7758 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7759 [(cc0) (const_int 0)])
7760 (match_operand:SI 1 "const_int_operand" "I"))]
7761 "TARGET_68020 && ! flags_in_68881 ()"
7764 switch (GET_CODE (operands[0]))
7766 case EQ: return \"trapeq\";
7767 case NE: return \"trapne\";
7768 case GT: return \"trapgt\";
7769 case GTU: return \"traphi\";
7770 case LT: return \"traplt\";
7771 case LTU: return \"trapcs\";
7772 case GE: return \"trapge\";
7773 case GEU: return \"trapcc\";
7774 case LE: return \"traple\";
7775 case LEU: return \"trapls\";