1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008,
3 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "target-def.h"
47 /* For dumping information about frame sizes. */
48 char * mcore_current_function_name
= 0;
49 long mcore_current_compilation_timestamp
= 0;
51 /* Global variables for machine-dependent things. */
53 /* Provides the class number of the smallest class containing
55 const enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
57 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
58 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
59 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
60 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
61 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
66 int arg_size
; /* Stdarg spills (bytes). */
67 int reg_size
; /* Non-volatile reg saves (bytes). */
68 int reg_mask
; /* Non-volatile reg saves. */
69 int local_size
; /* Locals. */
70 int outbound_size
; /* Arg overflow on calls out. */
74 /* Describe the steps we'll use to grow it. */
75 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
76 int growth
[MAX_STACK_GROWS
];
94 static void output_stack_adjust (int, int);
95 static int calc_live_regs (int *);
96 static int try_constant_tricks (long, HOST_WIDE_INT
*, HOST_WIDE_INT
*);
97 static const char * output_inline_const (enum machine_mode
, rtx
*);
98 static void layout_mcore_frame (struct mcore_frame
*);
99 static void mcore_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
, tree
, int *, int);
100 static cond_type
is_cond_candidate (rtx
);
101 static rtx
emit_new_cond_insn (rtx
, int);
102 static rtx
conditionalize_block (rtx
);
103 static void conditionalize_optimization (void);
104 static void mcore_reorg (void);
105 static rtx
handle_structs_in_regs (enum machine_mode
, const_tree
, int);
106 static void mcore_mark_dllexport (tree
);
107 static void mcore_mark_dllimport (tree
);
108 static int mcore_dllexport_p (tree
);
109 static int mcore_dllimport_p (tree
);
110 static tree
mcore_handle_naked_attribute (tree
*, tree
, tree
, int, bool *);
111 #ifdef OBJECT_FORMAT_ELF
112 static void mcore_asm_named_section (const char *,
115 static void mcore_print_operand (FILE *, rtx
, int);
116 static void mcore_print_operand_address (FILE *, rtx
);
117 static bool mcore_print_operand_punct_valid_p (unsigned char code
);
118 static void mcore_unique_section (tree
, int);
119 static void mcore_encode_section_info (tree
, rtx
, int);
120 static const char *mcore_strip_name_encoding (const char *);
121 static int mcore_const_costs (rtx
, RTX_CODE
);
122 static int mcore_and_cost (rtx
);
123 static int mcore_ior_cost (rtx
);
124 static bool mcore_rtx_costs (rtx
, int, int, int,
126 static void mcore_external_libcall (rtx
);
127 static bool mcore_return_in_memory (const_tree
, const_tree
);
128 static int mcore_arg_partial_bytes (cumulative_args_t
,
131 static rtx
mcore_function_arg (cumulative_args_t
,
134 static void mcore_function_arg_advance (cumulative_args_t
,
137 static unsigned int mcore_function_arg_boundary (enum machine_mode
,
139 static void mcore_asm_trampoline_template (FILE *);
140 static void mcore_trampoline_init (rtx
, tree
, rtx
);
141 static bool mcore_warn_func_return (tree
);
142 static void mcore_option_override (void);
143 static bool mcore_legitimate_constant_p (enum machine_mode
, rtx
);
145 /* MCore specific attributes. */
147 static const struct attribute_spec mcore_attribute_table
[] =
149 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
150 affects_type_identity } */
151 { "dllexport", 0, 0, true, false, false, NULL
, false },
152 { "dllimport", 0, 0, true, false, false, NULL
, false },
153 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
,
155 { NULL
, 0, 0, false, false, false, NULL
, false }
158 /* Initialize the GCC target structure. */
159 #undef TARGET_ASM_EXTERNAL_LIBCALL
160 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
162 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
163 #undef TARGET_MERGE_DECL_ATTRIBUTES
164 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
167 #ifdef OBJECT_FORMAT_ELF
168 #undef TARGET_ASM_UNALIGNED_HI_OP
169 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
170 #undef TARGET_ASM_UNALIGNED_SI_OP
171 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
174 #undef TARGET_PRINT_OPERAND
175 #define TARGET_PRINT_OPERAND mcore_print_operand
176 #undef TARGET_PRINT_OPERAND_ADDRESS
177 #define TARGET_PRINT_OPERAND_ADDRESS mcore_print_operand_address
178 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
179 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mcore_print_operand_punct_valid_p
181 #undef TARGET_ATTRIBUTE_TABLE
182 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
183 #undef TARGET_ASM_UNIQUE_SECTION
184 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
185 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
186 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
187 #undef TARGET_ENCODE_SECTION_INFO
188 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
189 #undef TARGET_STRIP_NAME_ENCODING
190 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
191 #undef TARGET_RTX_COSTS
192 #define TARGET_RTX_COSTS mcore_rtx_costs
193 #undef TARGET_ADDRESS_COST
194 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
195 #undef TARGET_MACHINE_DEPENDENT_REORG
196 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
198 #undef TARGET_PROMOTE_FUNCTION_MODE
199 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
200 #undef TARGET_PROMOTE_PROTOTYPES
201 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
203 #undef TARGET_RETURN_IN_MEMORY
204 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
205 #undef TARGET_MUST_PASS_IN_STACK
206 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
207 #undef TARGET_PASS_BY_REFERENCE
208 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
209 #undef TARGET_ARG_PARTIAL_BYTES
210 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
211 #undef TARGET_FUNCTION_ARG
212 #define TARGET_FUNCTION_ARG mcore_function_arg
213 #undef TARGET_FUNCTION_ARG_ADVANCE
214 #define TARGET_FUNCTION_ARG_ADVANCE mcore_function_arg_advance
215 #undef TARGET_FUNCTION_ARG_BOUNDARY
216 #define TARGET_FUNCTION_ARG_BOUNDARY mcore_function_arg_boundary
218 #undef TARGET_SETUP_INCOMING_VARARGS
219 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
221 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
222 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mcore_asm_trampoline_template
223 #undef TARGET_TRAMPOLINE_INIT
224 #define TARGET_TRAMPOLINE_INIT mcore_trampoline_init
226 #undef TARGET_OPTION_OVERRIDE
227 #define TARGET_OPTION_OVERRIDE mcore_option_override
229 #undef TARGET_LEGITIMATE_CONSTANT_P
230 #define TARGET_LEGITIMATE_CONSTANT_P mcore_legitimate_constant_p
232 #undef TARGET_WARN_FUNC_RETURN
233 #define TARGET_WARN_FUNC_RETURN mcore_warn_func_return
235 struct gcc_target targetm
= TARGET_INITIALIZER
;
237 /* Adjust the stack and return the number of bytes taken to do it. */
239 output_stack_adjust (int direction
, int size
)
241 /* If extending stack a lot, we do it incrementally. */
242 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
244 rtx tmp
= gen_rtx_REG (SImode
, 1);
247 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
250 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
251 memref
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
252 MEM_VOLATILE_P (memref
) = 1;
253 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
254 size
-= mcore_stack_increment
;
256 while (size
> mcore_stack_increment
);
258 /* SIZE is now the residual for the last adjustment,
259 which doesn't require a probe. */
265 rtx val
= GEN_INT (size
);
269 rtx nval
= gen_rtx_REG (SImode
, 1);
270 emit_insn (gen_movsi (nval
, val
));
275 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
277 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
283 /* Work out the registers which need to be saved,
284 both as a mask and a count. */
287 calc_live_regs (int * count
)
290 int live_regs_mask
= 0;
294 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
296 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
299 live_regs_mask
|= (1 << reg
);
303 return live_regs_mask
;
306 /* Print the operand address in x to the stream. */
309 mcore_print_operand_address (FILE * stream
, rtx x
)
311 switch (GET_CODE (x
))
314 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
319 rtx base
= XEXP (x
, 0);
320 rtx index
= XEXP (x
, 1);
322 if (GET_CODE (base
) != REG
)
324 /* Ensure that BASE is a register (one of them must be). */
330 switch (GET_CODE (index
))
333 fprintf (stream
, "(%s," HOST_WIDE_INT_PRINT_DEC
")",
334 reg_names
[REGNO(base
)], INTVAL (index
));
345 output_addr_const (stream
, x
);
351 mcore_print_operand_punct_valid_p (unsigned char code
)
353 return (code
== '.' || code
== '#' || code
== '*' || code
== '^'
357 /* Print operand x (an rtx) in assembler syntax to file stream
358 according to modifier code.
360 'R' print the next register or memory location along, i.e. the lsw in
362 'O' print a constant without the #
363 'M' print a constant as its negative
364 'P' print log2 of a power of two
365 'Q' print log2 of an inverse of a power of two
366 'U' print register for ldm/stm instruction
367 'X' print byte number for xtrbN instruction. */
370 mcore_print_operand (FILE * stream
, rtx x
, int code
)
376 fprintf (asm_out_file
, "32");
378 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
381 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) & 0xffffffff));
384 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
387 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
390 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, - INTVAL (x
));
393 /* Next location along in memory or register. */
394 switch (GET_CODE (x
))
397 fputs (reg_names
[REGNO (x
) + 1], (stream
));
400 mcore_print_operand_address
401 (stream
, XEXP (adjust_address (x
, SImode
, 4), 0));
408 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
409 reg_names
[REGNO (x
) + 3]);
412 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
415 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, 3 - INTVAL (x
) / 8);
419 switch (GET_CODE (x
))
422 fputs (reg_names
[REGNO (x
)], (stream
));
425 output_address (XEXP (x
, 0));
428 output_addr_const (stream
, x
);
435 /* What does a constant cost ? */
438 mcore_const_costs (rtx exp
, enum rtx_code code
)
440 HOST_WIDE_INT val
= INTVAL (exp
);
442 /* Easy constants. */
443 if ( CONST_OK_FOR_I (val
)
444 || CONST_OK_FOR_M (val
)
445 || CONST_OK_FOR_N (val
)
446 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
449 && ( CONST_OK_FOR_M (~val
)
450 || CONST_OK_FOR_N (~val
)))
452 else if (code
== PLUS
453 && ( CONST_OK_FOR_I (-val
)
454 || CONST_OK_FOR_M (-val
)
455 || CONST_OK_FOR_N (-val
)))
461 /* What does an and instruction cost - we do this b/c immediates may
462 have been relaxed. We want to ensure that cse will cse relaxed immeds
463 out. Otherwise we'll get bad code (multiple reloads of the same const). */
466 mcore_and_cost (rtx x
)
470 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
473 val
= INTVAL (XEXP (x
, 1));
475 /* Do it directly. */
476 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
478 /* Takes one instruction to load. */
479 else if (const_ok_for_mcore (val
))
481 /* Takes two instructions to load. */
482 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
485 /* Takes a lrw to load. */
489 /* What does an or cost - see and_cost(). */
492 mcore_ior_cost (rtx x
)
496 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
499 val
= INTVAL (XEXP (x
, 1));
501 /* Do it directly with bclri. */
502 if (CONST_OK_FOR_M (val
))
504 /* Takes one instruction to load. */
505 else if (const_ok_for_mcore (val
))
507 /* Takes two instructions to load. */
508 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
511 /* Takes a lrw to load. */
516 mcore_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
517 int * total
, bool speed ATTRIBUTE_UNUSED
)
522 *total
= mcore_const_costs (x
, (enum rtx_code
) outer_code
);
534 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
538 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
547 *total
= COSTS_N_INSNS (100);
555 /* Prepare the operands for a comparison. Return whether the branch/setcc
556 should reverse the operands. */
559 mcore_gen_compare (enum rtx_code code
, rtx op0
, rtx op1
)
561 rtx cc_reg
= gen_rtx_REG (CCmode
, CC_REG
);
564 if (GET_CODE (op1
) == CONST_INT
)
566 HOST_WIDE_INT val
= INTVAL (op1
);
571 /* Unsigned > 0 is the same as != 0; everything else is converted
572 below to LEU (reversed cmphs). */
577 /* Check whether (LE A imm) can become (LT A imm + 1),
578 or (GT A imm) can become (GE A imm + 1). */
581 if (CONST_OK_FOR_J (val
+ 1))
583 op1
= GEN_INT (val
+ 1);
584 code
= code
== LE
? LT
: GE
;
593 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
594 op1
= force_reg (SImode
, op1
);
596 /* cmpnei: 0-31 (K immediate)
597 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
601 case EQ
: /* Use inverted condition, cmpne. */
606 case NE
: /* Use normal condition, cmpne. */
607 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
608 op1
= force_reg (SImode
, op1
);
611 case LE
: /* Use inverted condition, reversed cmplt. */
616 case GT
: /* Use normal condition, reversed cmplt. */
617 if (GET_CODE (op1
) == CONST_INT
)
618 op1
= force_reg (SImode
, op1
);
621 case GE
: /* Use inverted condition, cmplt. */
626 case LT
: /* Use normal condition, cmplt. */
627 if (GET_CODE (op1
) == CONST_INT
&&
628 /* covered by btsti x,31. */
630 ! CONST_OK_FOR_J (INTVAL (op1
)))
631 op1
= force_reg (SImode
, op1
);
634 case GTU
: /* Use inverted condition, cmple. */
635 /* We coped with unsigned > 0 above. */
636 gcc_assert (GET_CODE (op1
) != CONST_INT
|| INTVAL (op1
) != 0);
641 case LEU
: /* Use normal condition, reversed cmphs. */
642 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
643 op1
= force_reg (SImode
, op1
);
646 case LTU
: /* Use inverted condition, cmphs. */
651 case GEU
: /* Use normal condition, cmphs. */
652 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
653 op1
= force_reg (SImode
, op1
);
660 emit_insn (gen_rtx_SET (VOIDmode
,
662 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
)));
667 mcore_symbolic_address_p (rtx x
)
669 switch (GET_CODE (x
))
676 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
677 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
678 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
684 /* Functions to output assembly code for a function call. */
687 mcore_output_call (rtx operands
[], int index
)
689 static char buffer
[20];
690 rtx addr
= operands
[index
];
696 gcc_assert (mcore_current_function_name
);
698 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
702 sprintf (buffer
, "jsr\t%%%d", index
);
708 gcc_assert (mcore_current_function_name
);
709 gcc_assert (GET_CODE (addr
) == SYMBOL_REF
);
711 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
715 sprintf (buffer
, "jbsr\t%%%d", index
);
721 /* Can we load a constant with a single instruction ? */
724 const_ok_for_mcore (HOST_WIDE_INT value
)
726 if (value
>= 0 && value
<= 127)
729 /* Try exact power of two. */
730 if (CONST_OK_FOR_M (value
))
733 /* Try exact power of two - 1. */
734 if (CONST_OK_FOR_N (value
) && value
!= -1)
740 /* Can we load a constant inline with up to 2 instructions ? */
743 mcore_const_ok_for_inline (HOST_WIDE_INT value
)
747 return try_constant_tricks (value
, & x
, & y
) > 0;
750 /* Are we loading the constant using a not ? */
753 mcore_const_trick_uses_not (HOST_WIDE_INT value
)
757 return try_constant_tricks (value
, & x
, & y
) == 2;
760 /* Try tricks to load a constant inline and return the trick number if
761 success (0 is non-inlinable).
764 1: single instruction (do the usual thing)
765 2: single insn followed by a 'not'
766 3: single insn followed by a subi
767 4: single insn followed by an addi
768 5: single insn followed by rsubi
769 6: single insn followed by bseti
770 7: single insn followed by bclri
771 8: single insn followed by rotli
772 9: single insn followed by lsli
773 10: single insn followed by ixh
774 11: single insn followed by ixw. */
777 try_constant_tricks (HOST_WIDE_INT value
, HOST_WIDE_INT
* x
, HOST_WIDE_INT
* y
)
780 unsigned HOST_WIDE_INT bit
, shf
, rot
;
782 if (const_ok_for_mcore (value
))
783 return 1; /* Do the usual thing. */
785 if (! TARGET_HARDLIT
)
788 if (const_ok_for_mcore (~value
))
794 for (i
= 1; i
<= 32; i
++)
796 if (const_ok_for_mcore (value
- i
))
804 if (const_ok_for_mcore (value
+ i
))
815 for (i
= 0; i
<= 31; i
++)
817 if (const_ok_for_mcore (i
- value
))
825 if (const_ok_for_mcore (value
& ~bit
))
832 if (const_ok_for_mcore (value
| bit
))
846 for (i
= 1; i
< 31; i
++)
850 /* MCore has rotate left. */
854 rot
|= c
; /* Simulate rotate. */
856 if (const_ok_for_mcore (rot
))
865 shf
= 0; /* Can't use logical shift, low order bit is one. */
869 if (shf
!= 0 && const_ok_for_mcore (shf
))
878 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
885 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
895 /* Check whether reg is dead at first. This is done by searching ahead
896 for either the next use (i.e., reg is live), a death note, or a set of
897 reg. Don't just use dead_or_set_p() since reload does not always mark
898 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
899 can ignore subregs by extracting the actual register. BRC */
902 mcore_is_dead (rtx first
, rtx reg
)
906 /* For mcore, subregs can't live independently of their parent regs. */
907 if (GET_CODE (reg
) == SUBREG
)
908 reg
= SUBREG_REG (reg
);
910 /* Dies immediately. */
911 if (dead_or_set_p (first
, reg
))
914 /* Look for conclusive evidence of live/death, otherwise we have
915 to assume that it is live. */
916 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
918 if (GET_CODE (insn
) == JUMP_INSN
)
919 return 0; /* We lose track, assume it is alive. */
921 else if (GET_CODE(insn
) == CALL_INSN
)
923 /* Call's might use it for target or register parms. */
924 if (reg_referenced_p (reg
, PATTERN (insn
))
925 || find_reg_fusage (insn
, USE
, reg
))
927 else if (dead_or_set_p (insn
, reg
))
930 else if (GET_CODE (insn
) == INSN
)
932 if (reg_referenced_p (reg
, PATTERN (insn
)))
934 else if (dead_or_set_p (insn
, reg
))
939 /* No conclusive evidence either way, we cannot take the chance
940 that control flow hid the use from us -- "I'm not dead yet". */
944 /* Count the number of ones in mask. */
947 mcore_num_ones (HOST_WIDE_INT mask
)
949 /* A trick to count set bits recently posted on comp.compilers. */
950 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
951 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
952 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
953 mask
= ((mask
>> 8) + mask
);
955 return (mask
+ (mask
>> 16)) & 0xff;
958 /* Count the number of zeros in mask. */
961 mcore_num_zeros (HOST_WIDE_INT mask
)
963 return 32 - mcore_num_ones (mask
);
966 /* Determine byte being masked. */
969 mcore_byte_offset (unsigned int mask
)
971 if (mask
== 0x00ffffffL
)
973 else if (mask
== 0xff00ffffL
)
975 else if (mask
== 0xffff00ffL
)
977 else if (mask
== 0xffffff00L
)
983 /* Determine halfword being masked. */
986 mcore_halfword_offset (unsigned int mask
)
988 if (mask
== 0x0000ffffL
)
990 else if (mask
== 0xffff0000L
)
996 /* Output a series of bseti's corresponding to mask. */
999 mcore_output_bseti (rtx dst
, int mask
)
1001 rtx out_operands
[2];
1004 out_operands
[0] = dst
;
1006 for (bit
= 0; bit
< 32; bit
++)
1008 if ((mask
& 0x1) == 0x1)
1010 out_operands
[1] = GEN_INT (bit
);
1012 output_asm_insn ("bseti\t%0,%1", out_operands
);
1020 /* Output a series of bclri's corresponding to mask. */
1023 mcore_output_bclri (rtx dst
, int mask
)
1025 rtx out_operands
[2];
1028 out_operands
[0] = dst
;
1030 for (bit
= 0; bit
< 32; bit
++)
1032 if ((mask
& 0x1) == 0x0)
1034 out_operands
[1] = GEN_INT (bit
);
1036 output_asm_insn ("bclri\t%0,%1", out_operands
);
1045 /* Output a conditional move of two constants that are +/- 1 within each
1046 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1047 really worth the effort. */
1050 mcore_output_cmov (rtx operands
[], int cmp_t
, const char * test
)
1052 HOST_WIDE_INT load_value
;
1053 HOST_WIDE_INT adjust_value
;
1054 rtx out_operands
[4];
1056 out_operands
[0] = operands
[0];
1058 /* Check to see which constant is loadable. */
1059 if (const_ok_for_mcore (INTVAL (operands
[1])))
1061 out_operands
[1] = operands
[1];
1062 out_operands
[2] = operands
[2];
1064 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1066 out_operands
[1] = operands
[2];
1067 out_operands
[2] = operands
[1];
1069 /* Complement test since constants are swapped. */
1070 cmp_t
= (cmp_t
== 0);
1072 load_value
= INTVAL (out_operands
[1]);
1073 adjust_value
= INTVAL (out_operands
[2]);
1075 /* First output the test if folded into the pattern. */
1078 output_asm_insn (test
, operands
);
1080 /* Load the constant - for now, only support constants that can be
1081 generated with a single instruction. maybe add general inlinable
1082 constants later (this will increase the # of patterns since the
1083 instruction sequence has a different length attribute). */
1084 if (load_value
>= 0 && load_value
<= 127)
1085 output_asm_insn ("movi\t%0,%1", out_operands
);
1086 else if (CONST_OK_FOR_M (load_value
))
1087 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1088 else if (CONST_OK_FOR_N (load_value
))
1089 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1091 /* Output the constant adjustment. */
1092 if (load_value
> adjust_value
)
1095 output_asm_insn ("decf\t%0", out_operands
);
1097 output_asm_insn ("dect\t%0", out_operands
);
1102 output_asm_insn ("incf\t%0", out_operands
);
1104 output_asm_insn ("inct\t%0", out_operands
);
1110 /* Outputs the peephole for moving a constant that gets not'ed followed
1111 by an and (i.e. combine the not and the and into andn). BRC */
1114 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
1117 rtx out_operands
[3];
1118 const char * load_op
;
1122 trick_no
= try_constant_tricks (INTVAL (operands
[1]), &x
, &y
);
1123 gcc_assert (trick_no
== 2);
1125 out_operands
[0] = operands
[0];
1126 out_operands
[1] = GEN_INT (x
);
1127 out_operands
[2] = operands
[2];
1129 if (x
>= 0 && x
<= 127)
1130 load_op
= "movi\t%0,%1";
1132 /* Try exact power of two. */
1133 else if (CONST_OK_FOR_M (x
))
1134 load_op
= "bgeni\t%0,%P1";
1136 /* Try exact power of two - 1. */
1137 else if (CONST_OK_FOR_N (x
))
1138 load_op
= "bmaski\t%0,%N1";
1142 load_op
= "BADMOVI-andn\t%0, %1";
1146 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1147 output_asm_insn (buf
, out_operands
);
1152 /* Output an inline constant. */
1155 output_inline_const (enum machine_mode mode
, rtx operands
[])
1157 HOST_WIDE_INT x
= 0, y
= 0;
1159 rtx out_operands
[3];
1162 const char *dst_fmt
;
1163 HOST_WIDE_INT value
;
1165 value
= INTVAL (operands
[1]);
1167 trick_no
= try_constant_tricks (value
, &x
, &y
);
1168 /* lrw's are handled separately: Large inlinable constants never get
1169 turned into lrw's. Our caller uses try_constant_tricks to back
1170 off to an lrw rather than calling this routine. */
1171 gcc_assert (trick_no
!= 0);
1176 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1177 out_operands
[0] = operands
[0];
1178 out_operands
[1] = GEN_INT (x
);
1181 out_operands
[2] = GEN_INT (y
);
1183 /* Select dst format based on mode. */
1184 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1189 if (x
>= 0 && x
<= 127)
1190 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1192 /* Try exact power of two. */
1193 else if (CONST_OK_FOR_M (x
))
1194 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1196 /* Try exact power of two - 1. */
1197 else if (CONST_OK_FOR_N (x
))
1198 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1202 sprintf (load_op
, "BADMOVI-inline_const %s, %%1", dst_fmt
);
1209 strcpy (buf
, load_op
);
1212 sprintf (buf
, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1215 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1218 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1221 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1222 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1225 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1228 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1231 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1234 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1237 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1240 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1246 output_asm_insn (buf
, out_operands
);
1251 /* Output a move of a word or less value. */
1254 mcore_output_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
1255 enum machine_mode mode ATTRIBUTE_UNUSED
)
1257 rtx dst
= operands
[0];
1258 rtx src
= operands
[1];
1260 if (GET_CODE (dst
) == REG
)
1262 if (GET_CODE (src
) == REG
)
1264 if (REGNO (src
) == CC_REG
) /* r-c */
1267 return "mov\t%0,%1"; /* r-r*/
1269 else if (GET_CODE (src
) == MEM
)
1271 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1272 return "lrw\t%0,[%1]"; /* a-R */
1274 switch (GET_MODE (src
)) /* r-m */
1277 return "ldw\t%0,%1";
1279 return "ld.h\t%0,%1";
1281 return "ld.b\t%0,%1";
1286 else if (GET_CODE (src
) == CONST_INT
)
1290 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1291 return "movi\t%0,%1";
1292 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1293 return "bgeni\t%0,%P1\t// %1 %x1";
1294 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1295 return "bmaski\t%0,%N1\t// %1 %x1";
1296 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1297 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1299 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1302 return "lrw\t%0, %1"; /* Into the literal pool. */
1304 else if (GET_CODE (dst
) == MEM
) /* m-r */
1305 switch (GET_MODE (dst
))
1308 return "stw\t%1,%0";
1310 return "st.h\t%1,%0";
1312 return "st.b\t%1,%0";
1320 /* Return a sequence of instructions to perform DI or DF move.
1321 Since the MCORE cannot move a DI or DF in one instruction, we have
1322 to take care when we see overlapping source and dest registers. */
1325 mcore_output_movedouble (rtx operands
[], enum machine_mode mode ATTRIBUTE_UNUSED
)
1327 rtx dst
= operands
[0];
1328 rtx src
= operands
[1];
1330 if (GET_CODE (dst
) == REG
)
1332 if (GET_CODE (src
) == REG
)
1334 int dstreg
= REGNO (dst
);
1335 int srcreg
= REGNO (src
);
1337 /* Ensure the second source not overwritten. */
1338 if (srcreg
+ 1 == dstreg
)
1339 return "mov %R0,%R1\n\tmov %0,%1";
1341 return "mov %0,%1\n\tmov %R0,%R1";
1343 else if (GET_CODE (src
) == MEM
)
1345 rtx memexp
= memexp
= XEXP (src
, 0);
1346 int dstreg
= REGNO (dst
);
1349 if (GET_CODE (memexp
) == LABEL_REF
)
1350 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1351 else if (GET_CODE (memexp
) == REG
)
1352 basereg
= REGNO (memexp
);
1353 else if (GET_CODE (memexp
) == PLUS
)
1355 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1356 basereg
= REGNO (XEXP (memexp
, 0));
1357 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1358 basereg
= REGNO (XEXP (memexp
, 1));
1365 /* ??? length attribute is wrong here. */
1366 if (dstreg
== basereg
)
1368 /* Just load them in reverse order. */
1369 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1371 /* XXX: alternative: move basereg to basereg+1
1372 and then fall through. */
1375 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1377 else if (GET_CODE (src
) == CONST_INT
)
1379 if (TARGET_LITTLE_END
)
1381 if (CONST_OK_FOR_I (INTVAL (src
)))
1382 output_asm_insn ("movi %0,%1", operands
);
1383 else if (CONST_OK_FOR_M (INTVAL (src
)))
1384 output_asm_insn ("bgeni %0,%P1", operands
);
1385 else if (CONST_OK_FOR_N (INTVAL (src
)))
1386 output_asm_insn ("bmaski %0,%N1", operands
);
1390 if (INTVAL (src
) < 0)
1391 return "bmaski %R0,32";
1393 return "movi %R0,0";
1397 if (CONST_OK_FOR_I (INTVAL (src
)))
1398 output_asm_insn ("movi %R0,%1", operands
);
1399 else if (CONST_OK_FOR_M (INTVAL (src
)))
1400 output_asm_insn ("bgeni %R0,%P1", operands
);
1401 else if (CONST_OK_FOR_N (INTVAL (src
)))
1402 output_asm_insn ("bmaski %R0,%N1", operands
);
1406 if (INTVAL (src
) < 0)
1407 return "bmaski %0,32";
1415 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1416 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1421 /* Predicates used by the templates. */
1424 mcore_arith_S_operand (rtx op
)
1426 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1432 /* Expand insert bit field. BRC */
1435 mcore_expand_insv (rtx operands
[])
1437 int width
= INTVAL (operands
[1]);
1438 int posn
= INTVAL (operands
[2]);
1440 rtx mreg
, sreg
, ereg
;
1442 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1443 for width==1 must be removed. Look around line 368. This is something
1444 we really want the md part to do. */
1445 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1447 /* Do directly with bseti or bclri. */
1448 /* RBE: 2/97 consider only low bit of constant. */
1449 if ((INTVAL (operands
[3]) & 1) == 0)
1451 mask
= ~(1 << posn
);
1452 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1453 gen_rtx_AND (SImode
, operands
[0], GEN_INT (mask
))));
1458 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1459 gen_rtx_IOR (SImode
, operands
[0], GEN_INT (mask
))));
1465 /* Look at some bit-field placements that we aren't interested
1466 in handling ourselves, unless specifically directed to do so. */
1467 if (! TARGET_W_FIELD
)
1468 return 0; /* Generally, give up about now. */
1470 if (width
== 8 && posn
% 8 == 0)
1471 /* Byte sized and aligned; let caller break it up. */
1474 if (width
== 16 && posn
% 16 == 0)
1475 /* Short sized and aligned; let caller break it up. */
1478 /* The general case - we can do this a little bit better than what the
1479 machine independent part tries. This will get rid of all the subregs
1480 that mess up constant folding in combine when working with relaxed
1483 /* If setting the entire field, do it directly. */
1484 if (GET_CODE (operands
[3]) == CONST_INT
1485 && INTVAL (operands
[3]) == ((1 << width
) - 1))
1487 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1488 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1489 gen_rtx_IOR (SImode
, operands
[0], mreg
)));
1493 /* Generate the clear mask. */
1494 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1496 /* Clear the field, to overlay it later with the source. */
1497 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1498 gen_rtx_AND (SImode
, operands
[0], mreg
)));
1500 /* If the source is constant 0, we've nothing to add back. */
1501 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1504 /* XXX: Should we worry about more games with constant values?
1505 We've covered the high profile: set/clear single-bit and many-bit
1506 fields. How often do we see "arbitrary bit pattern" constants? */
1507 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1509 /* Extract src as same width as dst (needed for signed values). We
1510 always have to do this since we widen everything to SImode.
1511 We don't have to mask if we're shifting this up against the
1512 MSB of the register (e.g., the shift will push out any hi-order
1514 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1516 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1517 emit_insn (gen_rtx_SET (SImode
, sreg
,
1518 gen_rtx_AND (SImode
, sreg
, ereg
)));
1521 /* Insert source value in dest. */
1523 emit_insn (gen_rtx_SET (SImode
, sreg
,
1524 gen_rtx_ASHIFT (SImode
, sreg
, GEN_INT (posn
))));
1526 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1527 gen_rtx_IOR (SImode
, operands
[0], sreg
)));
1532 /* ??? Block move stuff stolen from m88k. This code has not been
1533 verified for correctness. */
1535 /* Emit code to perform a block move. Choose the best method.
1537 OPERANDS[0] is the destination.
1538 OPERANDS[1] is the source.
1539 OPERANDS[2] is the size.
1540 OPERANDS[3] is the alignment safe to use. */
1542 /* Emit code to perform a block move with an offset sequence of ldw/st
1543 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1544 known constants. DEST and SRC are registers. OFFSET is the known
1545 starting point for the output pattern. */
1547 static const enum machine_mode mode_from_align
[] =
1549 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1553 block_move_sequence (rtx dst_mem
, rtx src_mem
, int size
, int align
)
1556 enum machine_mode mode
[2];
1565 x
= XEXP (dst_mem
, 0);
1568 x
= force_reg (Pmode
, x
);
1569 dst_mem
= replace_equiv_address (dst_mem
, x
);
1572 x
= XEXP (src_mem
, 0);
1575 x
= force_reg (Pmode
, x
);
1576 src_mem
= replace_equiv_address (src_mem
, x
);
1579 active
[0] = active
[1] = false;
1590 next_amount
= (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
1591 next_amount
= MIN (next_amount
, align
);
1593 amount
[next
] = next_amount
;
1594 mode
[next
] = mode_from_align
[next_amount
];
1595 temp
[next
] = gen_reg_rtx (mode
[next
]);
1597 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1598 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1600 offset_ld
+= next_amount
;
1601 size
-= next_amount
;
1602 active
[next
] = true;
1607 active
[phase
] = false;
1609 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1610 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1612 offset_st
+= amount
[phase
];
1615 while (active
[next
]);
1619 mcore_expand_block_move (rtx
*operands
)
1621 HOST_WIDE_INT align
, bytes
, max
;
1623 if (GET_CODE (operands
[2]) != CONST_INT
)
1626 bytes
= INTVAL (operands
[2]);
1627 align
= INTVAL (operands
[3]);
1656 block_move_sequence (operands
[0], operands
[1], bytes
, align
);
1664 /* Code to generate prologue and epilogue sequences. */
1665 static int number_of_regs_before_varargs
;
1667 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1668 for a varargs function. */
1669 static int current_function_anonymous_args
;
1671 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1672 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1673 #define ADDI_REACH (32) /* Maximum addi operand. */
1676 layout_mcore_frame (struct mcore_frame
* infp
)
1684 unsigned int growths
;
1687 /* Might have to spill bytes to re-assemble a big argument that
1688 was passed partially in registers and partially on the stack. */
1689 nbytes
= crtl
->args
.pretend_args_size
;
1691 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1692 if (current_function_anonymous_args
)
1693 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
1695 infp
->arg_size
= nbytes
;
1697 /* How much space to save non-volatile registers we stomp. */
1698 infp
->reg_mask
= calc_live_regs (& n
);
1699 infp
->reg_size
= n
* 4;
1701 /* And the rest of it... locals and space for overflowed outbounds. */
1702 infp
->local_size
= get_frame_size ();
1703 infp
->outbound_size
= crtl
->outgoing_args_size
;
1705 /* Make sure we have a whole number of words for the locals. */
1706 if (infp
->local_size
% STACK_BYTES
)
1707 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
1709 /* Only thing we know we have to pad is the outbound space, since
1710 we've aligned our locals assuming that base of locals is aligned. */
1711 infp
->pad_local
= 0;
1713 infp
->pad_outbound
= 0;
1714 if (infp
->outbound_size
% STACK_BYTES
)
1715 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
1717 /* Now we see how we want to stage the prologue so that it does
1718 the most appropriate stack growth and register saves to either:
1720 (2) reduce instruction space, or
1721 (3) reduce stack space. */
1722 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
1723 infp
->growth
[i
] = 0;
1725 regarg
= infp
->reg_size
+ infp
->arg_size
;
1726 localregarg
= infp
->local_size
+ regarg
;
1727 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
1730 /* XXX: Consider one where we consider localregarg + outbound too! */
1732 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1733 use stw's with offsets and buy the frame in one shot. */
1734 if (localregarg
<= ADDI_REACH
1735 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1737 /* Make sure we'll be aligned. */
1738 if (localregarg
% STACK_BYTES
)
1739 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1741 step
= localregarg
+ infp
->pad_reg
;
1742 infp
->reg_offset
= infp
->local_size
;
1744 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
1747 infp
->reg_offset
+= outbounds
;
1751 infp
->arg_offset
= step
- 4;
1752 infp
->growth
[growths
++] = step
;
1753 infp
->reg_growth
= growths
;
1754 infp
->local_growth
= growths
;
1756 /* If we haven't already folded it in. */
1758 infp
->growth
[growths
++] = outbounds
;
1763 /* Frame can't be done with a single subi, but can be done with 2
1764 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1765 shift some of the stack purchase into the first subi, so both are
1766 single instructions. */
1767 if (localregarg
<= STORE_REACH
1768 && (infp
->local_size
> ADDI_REACH
)
1769 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1773 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1774 if (localregarg
% STACK_BYTES
)
1775 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1777 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
1778 step
= ADDI_REACH
; /* As much up front as we can. */
1782 /* XXX: Consider whether step will still be aligned; we believe so. */
1783 infp
->arg_offset
= step
- 4;
1784 infp
->growth
[growths
++] = step
;
1785 infp
->reg_growth
= growths
;
1786 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
1789 /* Can we fold in any space required for outbounds? */
1790 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
1796 /* Get the rest of the locals in place. */
1798 infp
->growth
[growths
++] = step
;
1799 infp
->local_growth
= growths
;
1802 gcc_assert (all
== 0);
1804 /* Finish off if we need to do so. */
1806 infp
->growth
[growths
++] = outbounds
;
1811 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1812 Then we buy the rest of the frame in 1 or 2 steps depending on
1813 whether we need a frame pointer. */
1814 if ((regarg
% STACK_BYTES
) == 0)
1816 infp
->growth
[growths
++] = regarg
;
1817 infp
->reg_growth
= growths
;
1818 infp
->arg_offset
= regarg
- 4;
1819 infp
->reg_offset
= 0;
1821 if (infp
->local_size
% STACK_BYTES
)
1822 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1824 step
= infp
->local_size
+ infp
->pad_local
;
1826 if (!frame_pointer_needed
)
1832 infp
->growth
[growths
++] = step
;
1833 infp
->local_growth
= growths
;
1835 /* If there's any left to be done. */
1837 infp
->growth
[growths
++] = outbounds
;
1842 /* XXX: optimizations that we'll want to play with....
1843 -- regarg is not aligned, but it's a small number of registers;
1844 use some of localsize so that regarg is aligned and then
1845 save the registers. */
1847 /* Simple encoding; plods down the stack buying the pieces as it goes.
1848 -- does not optimize space consumption.
1849 -- does not attempt to optimize instruction counts.
1850 -- but it is safe for all alignments. */
1851 if (regarg
% STACK_BYTES
!= 0)
1852 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
1854 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
1855 infp
->reg_growth
= growths
;
1856 infp
->arg_offset
= infp
->growth
[0] - 4;
1857 infp
->reg_offset
= 0;
1859 if (frame_pointer_needed
)
1861 if (infp
->local_size
% STACK_BYTES
!= 0)
1862 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1864 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
1865 infp
->local_growth
= growths
;
1867 infp
->growth
[growths
++] = outbounds
;
1871 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
1872 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
1874 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
1875 infp
->local_growth
= growths
;
1878 /* Anything else that we've forgotten?, plus a few consistency checks. */
1880 gcc_assert (infp
->reg_offset
>= 0);
1881 gcc_assert (growths
<= MAX_STACK_GROWS
);
1883 for (i
= 0; i
< growths
; i
++)
1884 gcc_assert (!(infp
->growth
[i
] % STACK_BYTES
));
1887 /* Define the offset between two registers, one to be eliminated, and
1888 the other its replacement, at the start of a routine. */
1891 mcore_initial_elimination_offset (int from
, int to
)
1895 struct mcore_frame fi
;
1897 layout_mcore_frame (& fi
);
1900 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
1902 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
1904 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1907 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1908 return above_frame
+ below_frame
;
1910 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1916 /* Keep track of some information about varargs for the prolog. */
1919 mcore_setup_incoming_varargs (cumulative_args_t args_so_far_v
,
1920 enum machine_mode mode
, tree type
,
1921 int * ptr_pretend_size ATTRIBUTE_UNUSED
,
1922 int second_time ATTRIBUTE_UNUSED
)
1924 CUMULATIVE_ARGS
*args_so_far
= get_cumulative_args (args_so_far_v
);
1926 current_function_anonymous_args
= 1;
1928 /* We need to know how many argument registers are used before
1929 the varargs start, so that we can push the remaining argument
1930 registers during the prologue. */
1931 number_of_regs_before_varargs
= *args_so_far
+ mcore_num_arg_regs (mode
, type
);
1933 /* There is a bug somewhere in the arg handling code.
1934 Until I can find it this workaround always pushes the
1935 last named argument onto the stack. */
1936 number_of_regs_before_varargs
= *args_so_far
;
1938 /* The last named argument may be split between argument registers
1939 and the stack. Allow for this here. */
1940 if (number_of_regs_before_varargs
> NPARM_REGS
)
1941 number_of_regs_before_varargs
= NPARM_REGS
;
1945 mcore_expand_prolog (void)
1947 struct mcore_frame fi
;
1948 int space_allocated
= 0;
1951 /* Find out what we're doing. */
1952 layout_mcore_frame (&fi
);
1954 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
1955 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
1959 /* Emit a symbol for this routine's frame size. */
1962 x
= DECL_RTL (current_function_decl
);
1964 gcc_assert (GET_CODE (x
) == MEM
);
1968 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1970 free (mcore_current_function_name
);
1972 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
1974 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
1976 if (cfun
->calls_alloca
)
1977 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
1980 We're looking at how the 8byte alignment affects stack layout
1981 and where we had to pad things. This emits information we can
1982 extract which tells us about frame sizes and the like. */
1983 fprintf (asm_out_file
,
1984 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
1985 mcore_current_function_name
,
1986 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
1987 fi
.local_size
, fi
.outbound_size
,
1988 frame_pointer_needed
);
1991 if (mcore_naked_function_p ())
1994 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
1995 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
1997 /* If we have a parameter passed partially in regs and partially in memory,
1998 the registers will have been stored to memory already in function.c. So
1999 we only need to do something here for varargs functions. */
2000 if (fi
.arg_size
!= 0 && crtl
->args
.pretend_args_size
== 0)
2003 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
2004 int remaining
= fi
.arg_size
;
2006 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
2008 emit_insn (gen_movsi
2009 (gen_rtx_MEM (SImode
,
2010 plus_constant (Pmode
, stack_pointer_rtx
,
2012 gen_rtx_REG (SImode
, rn
)));
2016 /* Do we need another stack adjustment before we do the register saves? */
2017 if (growth
< fi
.reg_growth
)
2018 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2020 if (fi
.reg_size
!= 0)
2023 int offs
= fi
.reg_offset
;
2025 for (i
= 15; i
>= 0; i
--)
2027 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2031 while (fi
.reg_mask
& (1 << first_reg
))
2035 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2036 gen_rtx_REG (SImode
, first_reg
),
2037 GEN_INT (16 - first_reg
)));
2039 i
-= (15 - first_reg
);
2040 offs
+= (16 - first_reg
) * 4;
2042 else if (fi
.reg_mask
& (1 << i
))
2044 emit_insn (gen_movsi
2045 (gen_rtx_MEM (SImode
,
2046 plus_constant (Pmode
, stack_pointer_rtx
,
2048 gen_rtx_REG (SImode
, i
)));
2054 /* Figure the locals + outbounds. */
2055 if (frame_pointer_needed
)
2057 /* If we haven't already purchased to 'fp'. */
2058 if (growth
< fi
.local_growth
)
2059 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2061 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2063 /* ... and then go any remaining distance for outbounds, etc. */
2064 if (fi
.growth
[growth
])
2065 output_stack_adjust (-1, fi
.growth
[growth
++]);
2069 if (growth
< fi
.local_growth
)
2070 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2071 if (fi
.growth
[growth
])
2072 output_stack_adjust (-1, fi
.growth
[growth
++]);
2077 mcore_expand_epilog (void)
2079 struct mcore_frame fi
;
2082 int growth
= MAX_STACK_GROWS
- 1 ;
2085 /* Find out what we're doing. */
2086 layout_mcore_frame(&fi
);
2088 if (mcore_naked_function_p ())
2091 /* If we had a frame pointer, restore the sp from that. */
2092 if (frame_pointer_needed
)
2094 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2095 growth
= fi
.local_growth
- 1;
2099 /* XXX: while loop should accumulate and do a single sell. */
2100 while (growth
>= fi
.local_growth
)
2102 if (fi
.growth
[growth
] != 0)
2103 output_stack_adjust (1, fi
.growth
[growth
]);
2108 /* Make sure we've shrunk stack back to the point where the registers
2109 were laid down. This is typically 0/1 iterations. Then pull the
2110 register save information back off the stack. */
2111 while (growth
>= fi
.reg_growth
)
2112 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2114 offs
= fi
.reg_offset
;
2116 for (i
= 15; i
>= 0; i
--)
2118 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2122 /* Find the starting register. */
2125 while (fi
.reg_mask
& (1 << first_reg
))
2130 emit_insn (gen_load_multiple (gen_rtx_REG (SImode
, first_reg
),
2131 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2132 GEN_INT (16 - first_reg
)));
2134 i
-= (15 - first_reg
);
2135 offs
+= (16 - first_reg
) * 4;
2137 else if (fi
.reg_mask
& (1 << i
))
2139 emit_insn (gen_movsi
2140 (gen_rtx_REG (SImode
, i
),
2141 gen_rtx_MEM (SImode
,
2142 plus_constant (Pmode
, stack_pointer_rtx
,
2148 /* Give back anything else. */
2149 /* XXX: Should accumulate total and then give it back. */
2151 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2154 /* This code is borrowed from the SH port. */
2156 /* The MCORE cannot load a large constant into a register, constants have to
2157 come from a pc relative load. The reference of a pc relative load
2158 instruction must be less than 1k in front of the instruction. This
2159 means that we often have to dump a constant inside a function, and
2160 generate code to branch around it.
2162 It is important to minimize this, since the branches will slow things
2163 down and make things bigger.
2165 Worst case code looks like:
2181 We fix this by performing a scan before scheduling, which notices which
2182 instructions need to have their operands fetched from the constant table
2183 and builds the table.
2187 scan, find an instruction which needs a pcrel move. Look forward, find the
2188 last barrier which is within MAX_COUNT bytes of the requirement.
2189 If there isn't one, make one. Process all the instructions between
2190 the find and the barrier.
2192 In the above example, we can tell that L3 is within 1k of L1, so
2193 the first move can be shrunk from the 2 insn+constant sequence into
2194 just 1 insn, and the constant moved to L3 to make:
2204 Then the second move becomes the target for the shortening process. */
2208 rtx value
; /* Value in table. */
2209 rtx label
; /* Label of value. */
2212 /* The maximum number of constants that can fit into one pool, since
2213 the pc relative range is 0...1020 bytes and constants are at least 4
2214 bytes long. We subtract 4 from the range to allow for the case where
2215 we need to add a branch/align before the constant pool. */
2217 #define MAX_COUNT 1016
2218 #define MAX_POOL_SIZE (MAX_COUNT/4)
2219 static pool_node pool_vector
[MAX_POOL_SIZE
];
2220 static int pool_size
;
2222 /* Dump out any constants accumulated in the final pass. These
2223 will only be labels. */
2226 mcore_output_jump_label_table (void)
2232 fprintf (asm_out_file
, "\t.align 2\n");
2234 for (i
= 0; i
< pool_size
; i
++)
2236 pool_node
* p
= pool_vector
+ i
;
2238 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2240 output_asm_insn (".long %0", &p
->value
);
2249 /* Check whether insn is a candidate for a conditional. */
2252 is_cond_candidate (rtx insn
)
2254 /* The only things we conditionalize are those that can be directly
2255 changed into a conditional. Only bother with SImode items. If
2256 we wanted to be a little more aggressive, we could also do other
2257 modes such as DImode with reg-reg move or load 0. */
2258 if (GET_CODE (insn
) == INSN
)
2260 rtx pat
= PATTERN (insn
);
2263 if (GET_CODE (pat
) != SET
)
2266 dst
= XEXP (pat
, 0);
2268 if ((GET_CODE (dst
) != REG
&&
2269 GET_CODE (dst
) != SUBREG
) ||
2270 GET_MODE (dst
) != SImode
)
2273 src
= XEXP (pat
, 1);
2275 if ((GET_CODE (src
) == REG
||
2276 (GET_CODE (src
) == SUBREG
&&
2277 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2278 GET_MODE (src
) == SImode
)
2279 return COND_MOV_INSN
;
2280 else if (GET_CODE (src
) == CONST_INT
&&
2282 return COND_CLR_INSN
;
2283 else if (GET_CODE (src
) == PLUS
&&
2284 (GET_CODE (XEXP (src
, 0)) == REG
||
2285 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2286 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2287 GET_MODE (XEXP (src
, 0)) == SImode
&&
2288 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2289 INTVAL (XEXP (src
, 1)) == 1)
2290 return COND_INC_INSN
;
2291 else if (((GET_CODE (src
) == MINUS
&&
2292 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2293 INTVAL( XEXP (src
, 1)) == 1) ||
2294 (GET_CODE (src
) == PLUS
&&
2295 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2296 INTVAL (XEXP (src
, 1)) == -1)) &&
2297 (GET_CODE (XEXP (src
, 0)) == REG
||
2298 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2299 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2300 GET_MODE (XEXP (src
, 0)) == SImode
)
2301 return COND_DEC_INSN
;
2303 /* Some insns that we don't bother with:
2304 (set (rx:DI) (ry:DI))
2305 (set (rx:DI) (const_int 0))
2309 else if (GET_CODE (insn
) == JUMP_INSN
&&
2310 GET_CODE (PATTERN (insn
)) == SET
&&
2311 GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2312 return COND_BRANCH_INSN
;
2317 /* Emit a conditional version of insn and replace the old insn with the
2318 new one. Return the new insn if emitted. */
2321 emit_new_cond_insn (rtx insn
, int cond
)
2327 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2330 pat
= PATTERN (insn
);
2332 if (GET_CODE (insn
) == INSN
)
2334 dst
= SET_DEST (pat
);
2335 src
= SET_SRC (pat
);
2339 dst
= JUMP_LABEL (insn
);
2348 c_insn
= gen_movt0 (dst
, src
, dst
);
2350 c_insn
= gen_movt0 (dst
, dst
, src
);
2355 c_insn
= gen_incscc (dst
, dst
);
2357 c_insn
= gen_incscc_false (dst
, dst
);
2362 c_insn
= gen_decscc (dst
, dst
);
2364 c_insn
= gen_decscc_false (dst
, dst
);
2367 case COND_BRANCH_INSN
:
2369 c_insn
= gen_branch_true (dst
);
2371 c_insn
= gen_branch_false (dst
);
2378 /* Only copy the notes if they exist. */
2379 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2381 /* We really don't need to bother with the notes and links at this
2382 point, but go ahead and save the notes. This will help is_dead()
2383 when applying peepholes (links don't matter since they are not
2384 used any more beyond this point for the mcore). */
2385 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2388 if (num
== COND_BRANCH_INSN
)
2390 /* For jumps, we need to be a little bit careful and emit the new jump
2391 before the old one and to update the use count for the target label.
2392 This way, the barrier following the old (uncond) jump will get
2393 deleted, but the label won't. */
2394 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2396 ++ LABEL_NUSES (dst
);
2398 JUMP_LABEL (c_insn
) = dst
;
2401 c_insn
= emit_insn_after (c_insn
, insn
);
2408 /* Attempt to change a basic block into a series of conditional insns. This
2409 works by taking the branch at the end of the 1st block and scanning for the
2410 end of the 2nd block. If all instructions in the 2nd block have cond.
2411 versions and the label at the start of block 3 is the same as the target
2412 from the branch at block 1, then conditionalize all insn in block 2 using
2413 the inverse condition of the branch at block 1. (Note I'm bending the
2414 definition of basic block here.)
2418 bt L2 <-- end of block 1 (delete)
2421 br L3 <-- end of block 2
2423 L2: ... <-- start of block 3 (NUSES==1)
2434 we can delete the L2 label if NUSES==1 and re-apply the optimization
2435 starting at the last instruction of block 2. This may allow an entire
2436 if-then-else statement to be conditionalized. BRC */
2438 conditionalize_block (rtx first
)
2442 rtx end_blk_1_br
= 0;
2443 rtx end_blk_2_insn
= 0;
2444 rtx start_blk_3_lab
= 0;
2450 /* Check that the first insn is a candidate conditional jump. This is
2451 the one that we'll eliminate. If not, advance to the next insn to
2453 if (GET_CODE (first
) != JUMP_INSN
||
2454 GET_CODE (PATTERN (first
)) != SET
||
2455 GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2456 return NEXT_INSN (first
);
2458 /* Extract some information we need. */
2459 end_blk_1_br
= first
;
2460 br_pat
= PATTERN (end_blk_1_br
);
2462 /* Complement the condition since we use the reverse cond. for the insns. */
2463 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2465 /* Determine what kind of branch we have. */
2466 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2468 /* A normal branch, so extract label out of first arm. */
2469 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2473 /* An inverse branch, so extract the label out of the 2nd arm
2474 and complement the condition. */
2476 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2479 /* Scan forward for the start of block 2: it must start with a
2480 label and that label must be the same as the branch target
2481 label from block 1. We don't care about whether block 2 actually
2482 ends with a branch or a label (an uncond. branch is
2483 conditionalizable). */
2484 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2488 code
= GET_CODE (insn
);
2490 /* Look for the label at the start of block 3. */
2491 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2494 /* Skip barriers, notes, and conditionalizable insns. If the
2495 insn is not conditionalizable or makes this optimization fail,
2496 just return the next insn so we can start over from that point. */
2497 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2498 return NEXT_INSN (insn
);
2500 /* Remember the last real insn before the label (i.e. end of block 2). */
2501 if (code
== JUMP_INSN
|| code
== INSN
)
2504 end_blk_2_insn
= insn
;
2511 /* It is possible for this optimization to slow performance if the blocks
2512 are long. This really depends upon whether the branch is likely taken
2513 or not. If the branch is taken, we slow performance in many cases. But,
2514 if the branch is not taken, we always help performance (for a single
2515 block, but for a double block (i.e. when the optimization is re-applied)
2516 this is not true since the 'right thing' depends on the overall length of
2517 the collapsed block). As a compromise, don't apply this optimization on
2518 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2519 the best threshold depends on the latencies of the instructions (i.e.,
2520 the branch penalty). */
2521 if (optimize
> 1 && blk_size
> 2)
2524 /* At this point, we've found the start of block 3 and we know that
2525 it is the destination of the branch from block 1. Also, all
2526 instructions in the block 2 are conditionalizable. So, apply the
2527 conditionalization and delete the branch. */
2528 start_blk_3_lab
= insn
;
2530 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2531 insn
= NEXT_INSN (insn
))
2535 if (INSN_DELETED_P (insn
))
2538 /* Try to form a conditional variant of the instruction and emit it. */
2539 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2541 if (end_blk_2_insn
== insn
)
2542 end_blk_2_insn
= newinsn
;
2548 /* Note whether we will delete the label starting blk 3 when the jump
2549 gets deleted. If so, we want to re-apply this optimization at the
2550 last real instruction right before the label. */
2551 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2553 start_blk_3_lab
= 0;
2556 /* ??? we probably should redistribute the death notes for this insn, esp.
2557 the death of cc, but it doesn't really matter this late in the game.
2558 The peepholes all use is_dead() which will find the correct death
2559 regardless of whether there is a note. */
2560 delete_insn (end_blk_1_br
);
2562 if (! start_blk_3_lab
)
2563 return end_blk_2_insn
;
2565 /* Return the insn right after the label at the start of block 3. */
2566 return NEXT_INSN (start_blk_3_lab
);
2569 /* Apply the conditionalization of blocks optimization. This is the
2570 outer loop that traverses through the insns scanning for a branch
2571 that signifies an opportunity to apply the optimization. Note that
2572 this optimization is applied late. If we could apply it earlier,
2573 say before cse 2, it may expose more optimization opportunities.
2574 but, the pay back probably isn't really worth the effort (we'd have
2575 to update all reg/flow/notes/links/etc to make it work - and stick it
2576 in before cse 2). */
2579 conditionalize_optimization (void)
2583 for (insn
= get_insns (); insn
; insn
= conditionalize_block (insn
))
2587 /* This is to handle loads from the constant pool. */
2592 /* Reset this variable. */
2593 current_function_anonymous_args
= 0;
2598 /* Conditionalize blocks where we can. */
2599 conditionalize_optimization ();
2601 /* Literal pool generation is now pushed off until the assembler. */
2605 /* Return true if X is something that can be moved directly into r15. */
2608 mcore_r15_operand_p (rtx x
)
2610 switch (GET_CODE (x
))
2613 return mcore_const_ok_for_inline (INTVAL (x
));
2625 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't
2626 directly move X into it, use r1-r14 as a temporary. */
2629 mcore_secondary_reload_class (enum reg_class rclass
,
2630 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2632 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], 15)
2633 && !mcore_r15_operand_p (x
))
2638 /* Return the reg_class to use when reloading the rtx X into the class
2639 RCLASS. If X is too complex to move directly into r15, prefer to
2640 use LRW_REGS instead. */
2643 mcore_reload_class (rtx x
, enum reg_class rclass
)
2645 if (reg_class_subset_p (LRW_REGS
, rclass
) && !mcore_r15_operand_p (x
))
2651 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2652 register. Note that the current version doesn't worry about whether
2653 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2654 in r2 matches an SImode in r2. Might think in the future about whether
2655 we want to be able to say something about modes. */
2658 mcore_is_same_reg (rtx x
, rtx y
)
2660 /* Strip any and all of the subreg wrappers. */
2661 while (GET_CODE (x
) == SUBREG
)
2664 while (GET_CODE (y
) == SUBREG
)
2667 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
2674 mcore_option_override (void)
2676 /* Only the m340 supports little endian code. */
2677 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
2678 target_flags
|= MASK_M340
;
2682 /* Compute the number of word sized registers needed to
2683 hold a function argument of mode MODE and type TYPE. */
2686 mcore_num_arg_regs (enum machine_mode mode
, const_tree type
)
2690 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2693 if (type
&& mode
== BLKmode
)
2694 size
= int_size_in_bytes (type
);
2696 size
= GET_MODE_SIZE (mode
);
2698 return ROUND_ADVANCE (size
);
2702 handle_structs_in_regs (enum machine_mode mode
, const_tree type
, int reg
)
2706 /* The MCore ABI defines that a structure whose size is not a whole multiple
2707 of bytes is passed packed into registers (or spilled onto the stack if
2708 not enough registers are available) with the last few bytes of the
2709 structure being packed, left-justified, into the last register/stack slot.
2710 GCC handles this correctly if the last word is in a stack slot, but we
2711 have to generate a special, PARALLEL RTX if the last word is in an
2712 argument register. */
2714 && TYPE_MODE (type
) == BLKmode
2715 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
2716 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
2717 && (size
% UNITS_PER_WORD
!= 0)
2718 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
2720 rtx arg_regs
[NPARM_REGS
];
2725 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
2728 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
2729 GEN_INT (nregs
* UNITS_PER_WORD
));
2733 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2734 gcc_assert (ARRAY_SIZE (arg_regs
) == 6);
2735 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
2736 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
2738 result
= gen_rtx_PARALLEL (mode
, rtvec
);
2742 return gen_rtx_REG (mode
, reg
);
2746 mcore_function_value (const_tree valtype
, const_tree func
)
2748 enum machine_mode mode
;
2751 mode
= TYPE_MODE (valtype
);
2753 /* Since we promote return types, we must promote the mode here too. */
2754 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
2756 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
2759 /* Define where to put the arguments to a function.
2760 Value is zero to push the argument on the stack,
2761 or a hard register in which to store the argument.
2763 MODE is the argument's machine mode.
2764 TYPE is the data type of the argument (as a tree).
2765 This is null for libcalls where that information may
2767 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2768 the preceding args and about the function being called.
2769 NAMED is nonzero if this argument is a named parameter
2770 (otherwise it is an extra parameter matching an ellipsis).
2772 On MCore the first args are normally in registers
2773 and the rest are pushed. Any arg that starts within the first
2774 NPARM_REGS words is at least partially passed in a register unless
2775 its data type forbids. */
2778 mcore_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
2779 const_tree type
, bool named
)
2783 if (! named
|| mode
== VOIDmode
)
2786 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2789 arg_reg
= ROUND_REG (*get_cumulative_args (cum
), mode
);
2791 if (arg_reg
< NPARM_REGS
)
2792 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
2798 mcore_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
2799 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2801 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2803 *cum
= (ROUND_REG (*cum
, mode
)
2804 + (int)named
* mcore_num_arg_regs (mode
, type
));
2808 mcore_function_arg_boundary (enum machine_mode mode
,
2809 const_tree type ATTRIBUTE_UNUSED
)
2811 /* Doubles must be aligned to an 8 byte boundary. */
2812 return (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) == 8
2817 /* Returns the number of bytes of argument registers required to hold *part*
2818 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2819 the type is not known). If the argument fits entirely in the argument
2820 registers, or entirely on the stack, then 0 is returned. CUM is the
2821 number of argument registers already used by earlier parameters to
2825 mcore_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
2826 tree type
, bool named
)
2828 int reg
= ROUND_REG (*get_cumulative_args (cum
), mode
);
2833 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2836 /* REG is not the *hardware* register number of the register that holds
2837 the argument, it is the *argument* register number. So for example,
2838 the first argument to a function goes in argument register 0, which
2839 translates (for the MCore) into hardware register 2. The second
2840 argument goes into argument register 1, which translates into hardware
2841 register 3, and so on. NPARM_REGS is the number of argument registers
2842 supported by the target, not the maximum hardware register number of
2844 if (reg
>= NPARM_REGS
)
2847 /* If the argument fits entirely in registers, return 0. */
2848 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
2851 /* The argument overflows the number of available argument registers.
2852 Compute how many argument registers have not yet been assigned to
2853 hold an argument. */
2854 reg
= NPARM_REGS
- reg
;
2856 /* Return partially in registers and partially on the stack. */
2857 return reg
* UNITS_PER_WORD
;
2860 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2863 mcore_dllexport_name_p (const char * symbol
)
2865 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
2868 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2871 mcore_dllimport_name_p (const char * symbol
)
2873 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
2876 /* Mark a DECL as being dllexport'd. */
2879 mcore_mark_dllexport (tree decl
)
2881 const char * oldname
;
2886 rtlname
= XEXP (DECL_RTL (decl
), 0);
2888 if (GET_CODE (rtlname
) == MEM
)
2889 rtlname
= XEXP (rtlname
, 0);
2890 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2891 oldname
= XSTR (rtlname
, 0);
2893 if (mcore_dllexport_name_p (oldname
))
2894 return; /* Already done. */
2896 newname
= XALLOCAVEC (char, strlen (oldname
) + 4);
2897 sprintf (newname
, "@e.%s", oldname
);
2899 /* We pass newname through get_identifier to ensure it has a unique
2900 address. RTL processing can sometimes peek inside the symbol ref
2901 and compare the string's addresses to see if two symbols are
2903 /* ??? At least I think that's why we do this. */
2904 idp
= get_identifier (newname
);
2906 XEXP (DECL_RTL (decl
), 0) =
2907 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2910 /* Mark a DECL as being dllimport'd. */
2913 mcore_mark_dllimport (tree decl
)
2915 const char * oldname
;
2921 rtlname
= XEXP (DECL_RTL (decl
), 0);
2923 if (GET_CODE (rtlname
) == MEM
)
2924 rtlname
= XEXP (rtlname
, 0);
2925 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2926 oldname
= XSTR (rtlname
, 0);
2928 gcc_assert (!mcore_dllexport_name_p (oldname
));
2929 if (mcore_dllimport_name_p (oldname
))
2930 return; /* Already done. */
2932 /* ??? One can well ask why we're making these checks here,
2933 and that would be a good question. */
2935 /* Imported variables can't be initialized. */
2936 if (TREE_CODE (decl
) == VAR_DECL
2937 && !DECL_VIRTUAL_P (decl
)
2938 && DECL_INITIAL (decl
))
2940 error ("initialized variable %q+D is marked dllimport", decl
);
2944 /* `extern' needn't be specified with dllimport.
2945 Specify `extern' now and hope for the best. Sigh. */
2946 if (TREE_CODE (decl
) == VAR_DECL
2947 /* ??? Is this test for vtables needed? */
2948 && !DECL_VIRTUAL_P (decl
))
2950 DECL_EXTERNAL (decl
) = 1;
2951 TREE_PUBLIC (decl
) = 1;
2954 newname
= XALLOCAVEC (char, strlen (oldname
) + 11);
2955 sprintf (newname
, "@i.__imp_%s", oldname
);
2957 /* We pass newname through get_identifier to ensure it has a unique
2958 address. RTL processing can sometimes peek inside the symbol ref
2959 and compare the string's addresses to see if two symbols are
2961 /* ??? At least I think that's why we do this. */
2962 idp
= get_identifier (newname
);
2964 newrtl
= gen_rtx_MEM (Pmode
,
2965 gen_rtx_SYMBOL_REF (Pmode
,
2966 IDENTIFIER_POINTER (idp
)));
2967 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2971 mcore_dllexport_p (tree decl
)
2973 if ( TREE_CODE (decl
) != VAR_DECL
2974 && TREE_CODE (decl
) != FUNCTION_DECL
)
2977 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
2981 mcore_dllimport_p (tree decl
)
2983 if ( TREE_CODE (decl
) != VAR_DECL
2984 && TREE_CODE (decl
) != FUNCTION_DECL
)
2987 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
2990 /* We must mark dll symbols specially. Definitions of dllexport'd objects
2991 install some info in the .drective (PE) or .exports (ELF) sections. */
2994 mcore_encode_section_info (tree decl
, rtx rtl ATTRIBUTE_UNUSED
, int first ATTRIBUTE_UNUSED
)
2996 /* Mark the decl so we can tell from the rtl whether the object is
2997 dllexport'd or dllimport'd. */
2998 if (mcore_dllexport_p (decl
))
2999 mcore_mark_dllexport (decl
);
3000 else if (mcore_dllimport_p (decl
))
3001 mcore_mark_dllimport (decl
);
3003 /* It might be that DECL has already been marked as dllimport, but
3004 a subsequent definition nullified that. The attribute is gone
3005 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3006 else if ((TREE_CODE (decl
) == FUNCTION_DECL
3007 || TREE_CODE (decl
) == VAR_DECL
)
3008 && DECL_RTL (decl
) != NULL_RTX
3009 && GET_CODE (DECL_RTL (decl
)) == MEM
3010 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
3011 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
3012 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
3014 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
3015 tree idp
= get_identifier (oldname
+ 9);
3016 rtx newrtl
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
3018 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3020 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3021 ??? We leave these alone for now. */
3025 /* Undo the effects of the above. */
3028 mcore_strip_name_encoding (const char * str
)
3030 return str
+ (str
[0] == '@' ? 3 : 0);
3033 /* MCore specific attribute support.
3034 dllexport - for exporting a function/variable that will live in a dll
3035 dllimport - for importing a function/variable from a dll
3036 naked - do not create a function prologue/epilogue. */
3038 /* Handle a "naked" attribute; arguments as in
3039 struct attribute_spec.handler. */
3042 mcore_handle_naked_attribute (tree
* node
, tree name
, tree args ATTRIBUTE_UNUSED
,
3043 int flags ATTRIBUTE_UNUSED
, bool * no_add_attrs
)
3045 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3047 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3049 *no_add_attrs
= true;
3055 /* ??? It looks like this is PE specific? Oh well, this is what the
3056 old code did as well. */
3059 mcore_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
3064 const char * prefix
;
3066 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3068 /* Strip off any encoding in name. */
3069 name
= (* targetm
.strip_name_encoding
) (name
);
3071 /* The object is put in, for example, section .text$foo.
3072 The linker will then ultimately place them in .text
3073 (everything from the $ on is stripped). */
3074 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3076 /* For compatibility with EPOC, we ignore the fact that the
3077 section might have relocs against it. */
3078 else if (decl_readonly_section (decl
, 0))
3083 len
= strlen (name
) + strlen (prefix
);
3084 string
= XALLOCAVEC (char, len
+ 1);
3086 sprintf (string
, "%s%s", prefix
, name
);
3088 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
3092 mcore_naked_function_p (void)
3094 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3098 mcore_warn_func_return (tree decl
)
3100 /* Naked functions are implemented entirely in assembly, including the
3101 return sequence, so suppress warnings about this. */
3102 return lookup_attribute ("naked", DECL_ATTRIBUTES (decl
)) == NULL_TREE
;
3105 #ifdef OBJECT_FORMAT_ELF
3107 mcore_asm_named_section (const char *name
,
3108 unsigned int flags ATTRIBUTE_UNUSED
,
3109 tree decl ATTRIBUTE_UNUSED
)
3111 fprintf (asm_out_file
, "\t.section %s\n", name
);
3113 #endif /* OBJECT_FORMAT_ELF */
3115 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3118 mcore_external_libcall (rtx fun
)
3120 fprintf (asm_out_file
, "\t.import\t");
3121 assemble_name (asm_out_file
, XSTR (fun
, 0));
3122 fprintf (asm_out_file
, "\n");
3125 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3128 mcore_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3130 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
3131 return (size
== -1 || size
> 2 * UNITS_PER_WORD
);
3134 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE.
3135 Output assembler code for a block containing the constant parts
3136 of a trampoline, leaving space for the variable parts.
3138 On the MCore, the trampoline looks like:
3146 mcore_asm_trampoline_template (FILE *f
)
3148 fprintf (f
, "\t.short 0x7102\n");
3149 fprintf (f
, "\t.short 0x7d02\n");
3150 fprintf (f
, "\t.short 0x00cd\n");
3151 fprintf (f
, "\t.short 0x1e00\n");
3152 fprintf (f
, "\t.long 0\n");
3153 fprintf (f
, "\t.long 0\n");
3156 /* Worker function for TARGET_TRAMPOLINE_INIT. */
3159 mcore_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
3161 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3164 emit_block_move (m_tramp
, assemble_trampoline_template (),
3165 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
3167 mem
= adjust_address (m_tramp
, SImode
, 8);
3168 emit_move_insn (mem
, chain_value
);
3169 mem
= adjust_address (m_tramp
, SImode
, 12);
3170 emit_move_insn (mem
, fnaddr
);
3173 /* Implement TARGET_LEGITIMATE_CONSTANT_P
3175 On the MCore, allow anything but a double. */
3178 mcore_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3180 return GET_CODE (x
) != CONST_DOUBLE
;