1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
8 by the Free Software Foundation; either version 3, or (at your
9 option) any later version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
30 #include "stringpool.h"
33 #include "diagnostic-core.h"
34 #include "stor-layout.h"
45 /* This file should be included last. */
46 #include "target-def.h"
48 /* For dumping information about frame sizes. */
49 char * mcore_current_function_name
= 0;
50 long mcore_current_compilation_timestamp
= 0;
52 /* Global variables for machine-dependent things. */
54 /* Provides the class number of the smallest class containing
56 const enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
58 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
59 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
60 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
61 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
62 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
67 int arg_size
; /* Stdarg spills (bytes). */
68 int reg_size
; /* Non-volatile reg saves (bytes). */
69 int reg_mask
; /* Non-volatile reg saves. */
70 int local_size
; /* Locals. */
71 int outbound_size
; /* Arg overflow on calls out. */
75 /* Describe the steps we'll use to grow it. */
76 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
77 int growth
[MAX_STACK_GROWS
];
95 static void output_stack_adjust (int, int);
96 static int calc_live_regs (int *);
97 static int try_constant_tricks (HOST_WIDE_INT
, HOST_WIDE_INT
*, HOST_WIDE_INT
*);
98 static const char * output_inline_const (machine_mode
, rtx
*);
99 static void layout_mcore_frame (struct mcore_frame
*);
100 static void mcore_setup_incoming_varargs (cumulative_args_t
, machine_mode
, tree
, int *, int);
101 static cond_type
is_cond_candidate (rtx
);
102 static rtx_insn
*emit_new_cond_insn (rtx_insn
*, int);
103 static rtx_insn
*conditionalize_block (rtx_insn
*);
104 static void conditionalize_optimization (void);
105 static void mcore_reorg (void);
106 static rtx
handle_structs_in_regs (machine_mode
, const_tree
, int);
107 static void mcore_mark_dllexport (tree
);
108 static void mcore_mark_dllimport (tree
);
109 static int mcore_dllexport_p (tree
);
110 static int mcore_dllimport_p (tree
);
111 static tree
mcore_handle_naked_attribute (tree
*, tree
, tree
, int, bool *);
112 #ifdef OBJECT_FORMAT_ELF
113 static void mcore_asm_named_section (const char *,
116 static void mcore_print_operand (FILE *, rtx
, int);
117 static void mcore_print_operand_address (FILE *, machine_mode
, rtx
);
118 static bool mcore_print_operand_punct_valid_p (unsigned char code
);
119 static void mcore_unique_section (tree
, int);
120 static void mcore_encode_section_info (tree
, rtx
, int);
121 static const char *mcore_strip_name_encoding (const char *);
122 static int mcore_const_costs (rtx
, RTX_CODE
);
123 static int mcore_and_cost (rtx
);
124 static int mcore_ior_cost (rtx
);
125 static bool mcore_rtx_costs (rtx
, machine_mode
, int, int,
127 static void mcore_external_libcall (rtx
);
128 static bool mcore_return_in_memory (const_tree
, const_tree
);
129 static int mcore_arg_partial_bytes (cumulative_args_t
,
132 static rtx
mcore_function_arg (cumulative_args_t
,
135 static void mcore_function_arg_advance (cumulative_args_t
,
138 static unsigned int mcore_function_arg_boundary (machine_mode
,
140 static void mcore_asm_trampoline_template (FILE *);
141 static void mcore_trampoline_init (rtx
, tree
, rtx
);
142 static bool mcore_warn_func_return (tree
);
143 static void mcore_option_override (void);
144 static bool mcore_legitimate_constant_p (machine_mode
, rtx
);
145 static bool mcore_legitimate_address_p (machine_mode
, rtx
, bool,
147 static bool mcore_hard_regno_mode_ok (unsigned int, machine_mode
);
149 /* MCore specific attributes. */
151 static const struct attribute_spec mcore_attribute_table
[] =
153 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
154 affects_type_identity } */
155 { "dllexport", 0, 0, true, false, false, NULL
, false },
156 { "dllimport", 0, 0, true, false, false, NULL
, false },
157 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
,
159 { NULL
, 0, 0, false, false, false, NULL
, false }
162 /* Initialize the GCC target structure. */
163 #undef TARGET_ASM_EXTERNAL_LIBCALL
164 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
166 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
167 #undef TARGET_MERGE_DECL_ATTRIBUTES
168 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
171 #ifdef OBJECT_FORMAT_ELF
172 #undef TARGET_ASM_UNALIGNED_HI_OP
173 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
174 #undef TARGET_ASM_UNALIGNED_SI_OP
175 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
178 #undef TARGET_PRINT_OPERAND
179 #define TARGET_PRINT_OPERAND mcore_print_operand
180 #undef TARGET_PRINT_OPERAND_ADDRESS
181 #define TARGET_PRINT_OPERAND_ADDRESS mcore_print_operand_address
182 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
183 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mcore_print_operand_punct_valid_p
185 #undef TARGET_ATTRIBUTE_TABLE
186 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
187 #undef TARGET_ASM_UNIQUE_SECTION
188 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
189 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
190 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
191 #undef TARGET_ENCODE_SECTION_INFO
192 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
193 #undef TARGET_STRIP_NAME_ENCODING
194 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
195 #undef TARGET_RTX_COSTS
196 #define TARGET_RTX_COSTS mcore_rtx_costs
197 #undef TARGET_ADDRESS_COST
198 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
199 #undef TARGET_MACHINE_DEPENDENT_REORG
200 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
202 #undef TARGET_PROMOTE_FUNCTION_MODE
203 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
204 #undef TARGET_PROMOTE_PROTOTYPES
205 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
207 #undef TARGET_RETURN_IN_MEMORY
208 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
209 #undef TARGET_MUST_PASS_IN_STACK
210 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
211 #undef TARGET_PASS_BY_REFERENCE
212 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
213 #undef TARGET_ARG_PARTIAL_BYTES
214 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
215 #undef TARGET_FUNCTION_ARG
216 #define TARGET_FUNCTION_ARG mcore_function_arg
217 #undef TARGET_FUNCTION_ARG_ADVANCE
218 #define TARGET_FUNCTION_ARG_ADVANCE mcore_function_arg_advance
219 #undef TARGET_FUNCTION_ARG_BOUNDARY
220 #define TARGET_FUNCTION_ARG_BOUNDARY mcore_function_arg_boundary
222 #undef TARGET_SETUP_INCOMING_VARARGS
223 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
225 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
226 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mcore_asm_trampoline_template
227 #undef TARGET_TRAMPOLINE_INIT
228 #define TARGET_TRAMPOLINE_INIT mcore_trampoline_init
230 #undef TARGET_OPTION_OVERRIDE
231 #define TARGET_OPTION_OVERRIDE mcore_option_override
233 #undef TARGET_LEGITIMATE_CONSTANT_P
234 #define TARGET_LEGITIMATE_CONSTANT_P mcore_legitimate_constant_p
235 #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
236 #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P mcore_legitimate_address_p
239 #define TARGET_LRA_P hook_bool_void_false
241 #undef TARGET_WARN_FUNC_RETURN
242 #define TARGET_WARN_FUNC_RETURN mcore_warn_func_return
244 #undef TARGET_HARD_REGNO_MODE_OK
245 #define TARGET_HARD_REGNO_MODE_OK mcore_hard_regno_mode_ok
247 struct gcc_target targetm
= TARGET_INITIALIZER
;
249 /* Adjust the stack and return the number of bytes taken to do it. */
251 output_stack_adjust (int direction
, int size
)
253 /* If extending stack a lot, we do it incrementally. */
254 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
256 rtx tmp
= gen_rtx_REG (SImode
, 1);
259 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
262 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
263 memref
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
264 MEM_VOLATILE_P (memref
) = 1;
265 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
266 size
-= mcore_stack_increment
;
268 while (size
> mcore_stack_increment
);
270 /* SIZE is now the residual for the last adjustment,
271 which doesn't require a probe. */
277 rtx val
= GEN_INT (size
);
281 rtx nval
= gen_rtx_REG (SImode
, 1);
282 emit_insn (gen_movsi (nval
, val
));
287 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
289 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
295 /* Work out the registers which need to be saved,
296 both as a mask and a count. */
299 calc_live_regs (int * count
)
302 int live_regs_mask
= 0;
306 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
308 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
311 live_regs_mask
|= (1 << reg
);
315 return live_regs_mask
;
318 /* Print the operand address in x to the stream. */
321 mcore_print_operand_address (FILE * stream
, machine_mode
/*mode*/, rtx x
)
323 switch (GET_CODE (x
))
326 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
331 rtx base
= XEXP (x
, 0);
332 rtx index
= XEXP (x
, 1);
334 if (GET_CODE (base
) != REG
)
336 /* Ensure that BASE is a register (one of them must be). */
342 switch (GET_CODE (index
))
345 fprintf (stream
, "(%s," HOST_WIDE_INT_PRINT_DEC
")",
346 reg_names
[REGNO(base
)], INTVAL (index
));
357 output_addr_const (stream
, x
);
363 mcore_print_operand_punct_valid_p (unsigned char code
)
365 return (code
== '.' || code
== '#' || code
== '*' || code
== '^'
369 /* Print operand x (an rtx) in assembler syntax to file stream
370 according to modifier code.
372 'R' print the next register or memory location along, i.e. the lsw in
374 'O' print a constant without the #
375 'M' print a constant as its negative
376 'P' print log2 of a power of two
377 'Q' print log2 of an inverse of a power of two
378 'U' print register for ldm/stm instruction
379 'X' print byte number for xtrbN instruction. */
382 mcore_print_operand (FILE * stream
, rtx x
, int code
)
388 fprintf (asm_out_file
, "32");
390 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
393 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) & 0xffffffff));
396 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
399 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
402 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, - INTVAL (x
));
405 /* Next location along in memory or register. */
406 switch (GET_CODE (x
))
409 fputs (reg_names
[REGNO (x
) + 1], (stream
));
412 mcore_print_operand_address
413 (stream
, GET_MODE (x
), XEXP (adjust_address (x
, SImode
, 4), 0));
420 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
421 reg_names
[REGNO (x
) + 3]);
424 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
427 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, 3 - INTVAL (x
) / 8);
431 switch (GET_CODE (x
))
434 fputs (reg_names
[REGNO (x
)], (stream
));
437 output_address (GET_MODE (x
), XEXP (x
, 0));
440 output_addr_const (stream
, x
);
447 /* What does a constant cost ? */
450 mcore_const_costs (rtx exp
, enum rtx_code code
)
452 HOST_WIDE_INT val
= INTVAL (exp
);
454 /* Easy constants. */
455 if ( CONST_OK_FOR_I (val
)
456 || CONST_OK_FOR_M (val
)
457 || CONST_OK_FOR_N (val
)
458 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
461 && ( CONST_OK_FOR_M (~val
)
462 || CONST_OK_FOR_N (~val
)))
464 else if (code
== PLUS
465 && ( CONST_OK_FOR_I (-val
)
466 || CONST_OK_FOR_M (-val
)
467 || CONST_OK_FOR_N (-val
)))
473 /* What does an and instruction cost - we do this b/c immediates may
474 have been relaxed. We want to ensure that cse will cse relaxed immeds
475 out. Otherwise we'll get bad code (multiple reloads of the same const). */
478 mcore_and_cost (rtx x
)
482 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
485 val
= INTVAL (XEXP (x
, 1));
487 /* Do it directly. */
488 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
490 /* Takes one instruction to load. */
491 else if (const_ok_for_mcore (val
))
493 /* Takes two instructions to load. */
494 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
497 /* Takes a lrw to load. */
501 /* What does an or cost - see and_cost(). */
504 mcore_ior_cost (rtx x
)
508 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
511 val
= INTVAL (XEXP (x
, 1));
513 /* Do it directly with bclri. */
514 if (CONST_OK_FOR_M (val
))
516 /* Takes one instruction to load. */
517 else if (const_ok_for_mcore (val
))
519 /* Takes two instructions to load. */
520 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
523 /* Takes a lrw to load. */
528 mcore_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
529 int opno ATTRIBUTE_UNUSED
,
530 int * total
, bool speed ATTRIBUTE_UNUSED
)
532 int code
= GET_CODE (x
);
537 *total
= mcore_const_costs (x
, (enum rtx_code
) outer_code
);
549 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
553 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
562 *total
= COSTS_N_INSNS (100);
570 /* Prepare the operands for a comparison. Return whether the branch/setcc
571 should reverse the operands. */
574 mcore_gen_compare (enum rtx_code code
, rtx op0
, rtx op1
)
576 rtx cc_reg
= gen_rtx_REG (CCmode
, CC_REG
);
579 if (GET_CODE (op1
) == CONST_INT
)
581 HOST_WIDE_INT val
= INTVAL (op1
);
586 /* Unsigned > 0 is the same as != 0; everything else is converted
587 below to LEU (reversed cmphs). */
592 /* Check whether (LE A imm) can become (LT A imm + 1),
593 or (GT A imm) can become (GE A imm + 1). */
596 if (CONST_OK_FOR_J (val
+ 1))
598 op1
= GEN_INT (val
+ 1);
599 code
= code
== LE
? LT
: GE
;
608 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
609 op1
= force_reg (SImode
, op1
);
611 /* cmpnei: 0-31 (K immediate)
612 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
616 case EQ
: /* Use inverted condition, cmpne. */
621 case NE
: /* Use normal condition, cmpne. */
622 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
623 op1
= force_reg (SImode
, op1
);
626 case LE
: /* Use inverted condition, reversed cmplt. */
631 case GT
: /* Use normal condition, reversed cmplt. */
632 if (GET_CODE (op1
) == CONST_INT
)
633 op1
= force_reg (SImode
, op1
);
636 case GE
: /* Use inverted condition, cmplt. */
641 case LT
: /* Use normal condition, cmplt. */
642 if (GET_CODE (op1
) == CONST_INT
&&
643 /* covered by btsti x,31. */
645 ! CONST_OK_FOR_J (INTVAL (op1
)))
646 op1
= force_reg (SImode
, op1
);
649 case GTU
: /* Use inverted condition, cmple. */
650 /* We coped with unsigned > 0 above. */
651 gcc_assert (GET_CODE (op1
) != CONST_INT
|| INTVAL (op1
) != 0);
656 case LEU
: /* Use normal condition, reversed cmphs. */
657 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
658 op1
= force_reg (SImode
, op1
);
661 case LTU
: /* Use inverted condition, cmphs. */
666 case GEU
: /* Use normal condition, cmphs. */
667 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
668 op1
= force_reg (SImode
, op1
);
675 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
)));
680 mcore_symbolic_address_p (rtx x
)
682 switch (GET_CODE (x
))
689 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
690 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
691 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
697 /* Functions to output assembly code for a function call. */
700 mcore_output_call (rtx operands
[], int index
)
702 static char buffer
[20];
703 rtx addr
= operands
[index
];
709 gcc_assert (mcore_current_function_name
);
711 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
715 sprintf (buffer
, "jsr\t%%%d", index
);
721 gcc_assert (mcore_current_function_name
);
722 gcc_assert (GET_CODE (addr
) == SYMBOL_REF
);
724 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
728 sprintf (buffer
, "jbsr\t%%%d", index
);
734 /* Can we load a constant with a single instruction ? */
737 const_ok_for_mcore (HOST_WIDE_INT value
)
739 if (value
>= 0 && value
<= 127)
742 /* Try exact power of two. */
743 if (CONST_OK_FOR_M (value
))
746 /* Try exact power of two - 1. */
747 if (CONST_OK_FOR_N (value
) && value
!= -1)
753 /* Can we load a constant inline with up to 2 instructions ? */
756 mcore_const_ok_for_inline (HOST_WIDE_INT value
)
760 return try_constant_tricks (value
, & x
, & y
) > 0;
763 /* Are we loading the constant using a not ? */
766 mcore_const_trick_uses_not (HOST_WIDE_INT value
)
770 return try_constant_tricks (value
, & x
, & y
) == 2;
773 /* Try tricks to load a constant inline and return the trick number if
774 success (0 is non-inlinable).
777 1: single instruction (do the usual thing)
778 2: single insn followed by a 'not'
779 3: single insn followed by a subi
780 4: single insn followed by an addi
781 5: single insn followed by rsubi
782 6: single insn followed by bseti
783 7: single insn followed by bclri
784 8: single insn followed by rotli
785 9: single insn followed by lsli
786 10: single insn followed by ixh
787 11: single insn followed by ixw. */
790 try_constant_tricks (HOST_WIDE_INT value
, HOST_WIDE_INT
* x
, HOST_WIDE_INT
* y
)
793 unsigned HOST_WIDE_INT bit
, shf
, rot
;
795 if (const_ok_for_mcore (value
))
796 return 1; /* Do the usual thing. */
798 if (! TARGET_HARDLIT
)
801 if (const_ok_for_mcore (~value
))
807 for (i
= 1; i
<= 32; i
++)
809 if (const_ok_for_mcore (value
- i
))
817 if (const_ok_for_mcore (value
+ i
))
828 for (i
= 0; i
<= 31; i
++)
830 if (const_ok_for_mcore (i
- value
))
838 if (const_ok_for_mcore (value
& ~bit
))
845 if (const_ok_for_mcore (value
| bit
))
859 for (i
= 1; i
< 31; i
++)
863 /* MCore has rotate left. */
867 rot
|= c
; /* Simulate rotate. */
869 if (const_ok_for_mcore (rot
))
878 shf
= 0; /* Can't use logical shift, low order bit is one. */
882 if (shf
!= 0 && const_ok_for_mcore (shf
))
891 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
898 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
908 /* Check whether reg is dead at first. This is done by searching ahead
909 for either the next use (i.e., reg is live), a death note, or a set of
910 reg. Don't just use dead_or_set_p() since reload does not always mark
911 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
912 can ignore subregs by extracting the actual register. BRC */
915 mcore_is_dead (rtx_insn
*first
, rtx reg
)
919 /* For mcore, subregs can't live independently of their parent regs. */
920 if (GET_CODE (reg
) == SUBREG
)
921 reg
= SUBREG_REG (reg
);
923 /* Dies immediately. */
924 if (dead_or_set_p (first
, reg
))
927 /* Look for conclusive evidence of live/death, otherwise we have
928 to assume that it is live. */
929 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
932 return 0; /* We lose track, assume it is alive. */
934 else if (CALL_P (insn
))
936 /* Call's might use it for target or register parms. */
937 if (reg_referenced_p (reg
, PATTERN (insn
))
938 || find_reg_fusage (insn
, USE
, reg
))
940 else if (dead_or_set_p (insn
, reg
))
943 else if (NONJUMP_INSN_P (insn
))
945 if (reg_referenced_p (reg
, PATTERN (insn
)))
947 else if (dead_or_set_p (insn
, reg
))
952 /* No conclusive evidence either way, we cannot take the chance
953 that control flow hid the use from us -- "I'm not dead yet". */
957 /* Count the number of ones in mask. */
960 mcore_num_ones (HOST_WIDE_INT mask
)
962 /* A trick to count set bits recently posted on comp.compilers. */
963 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
964 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
965 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
966 mask
= ((mask
>> 8) + mask
);
968 return (mask
+ (mask
>> 16)) & 0xff;
971 /* Count the number of zeros in mask. */
974 mcore_num_zeros (HOST_WIDE_INT mask
)
976 return 32 - mcore_num_ones (mask
);
979 /* Determine byte being masked. */
982 mcore_byte_offset (unsigned int mask
)
984 if (mask
== 0x00ffffffL
)
986 else if (mask
== 0xff00ffffL
)
988 else if (mask
== 0xffff00ffL
)
990 else if (mask
== 0xffffff00L
)
996 /* Determine halfword being masked. */
999 mcore_halfword_offset (unsigned int mask
)
1001 if (mask
== 0x0000ffffL
)
1003 else if (mask
== 0xffff0000L
)
1009 /* Output a series of bseti's corresponding to mask. */
1012 mcore_output_bseti (rtx dst
, int mask
)
1014 rtx out_operands
[2];
1017 out_operands
[0] = dst
;
1019 for (bit
= 0; bit
< 32; bit
++)
1021 if ((mask
& 0x1) == 0x1)
1023 out_operands
[1] = GEN_INT (bit
);
1025 output_asm_insn ("bseti\t%0,%1", out_operands
);
1033 /* Output a series of bclri's corresponding to mask. */
1036 mcore_output_bclri (rtx dst
, int mask
)
1038 rtx out_operands
[2];
1041 out_operands
[0] = dst
;
1043 for (bit
= 0; bit
< 32; bit
++)
1045 if ((mask
& 0x1) == 0x0)
1047 out_operands
[1] = GEN_INT (bit
);
1049 output_asm_insn ("bclri\t%0,%1", out_operands
);
1058 /* Output a conditional move of two constants that are +/- 1 within each
1059 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1060 really worth the effort. */
1063 mcore_output_cmov (rtx operands
[], int cmp_t
, const char * test
)
1065 HOST_WIDE_INT load_value
;
1066 HOST_WIDE_INT adjust_value
;
1067 rtx out_operands
[4];
1069 out_operands
[0] = operands
[0];
1071 /* Check to see which constant is loadable. */
1072 if (const_ok_for_mcore (INTVAL (operands
[1])))
1074 out_operands
[1] = operands
[1];
1075 out_operands
[2] = operands
[2];
1077 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1079 out_operands
[1] = operands
[2];
1080 out_operands
[2] = operands
[1];
1082 /* Complement test since constants are swapped. */
1083 cmp_t
= (cmp_t
== 0);
1085 load_value
= INTVAL (out_operands
[1]);
1086 adjust_value
= INTVAL (out_operands
[2]);
1088 /* First output the test if folded into the pattern. */
1091 output_asm_insn (test
, operands
);
1093 /* Load the constant - for now, only support constants that can be
1094 generated with a single instruction. maybe add general inlinable
1095 constants later (this will increase the # of patterns since the
1096 instruction sequence has a different length attribute). */
1097 if (load_value
>= 0 && load_value
<= 127)
1098 output_asm_insn ("movi\t%0,%1", out_operands
);
1099 else if (CONST_OK_FOR_M (load_value
))
1100 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1101 else if (CONST_OK_FOR_N (load_value
))
1102 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1104 /* Output the constant adjustment. */
1105 if (load_value
> adjust_value
)
1108 output_asm_insn ("decf\t%0", out_operands
);
1110 output_asm_insn ("dect\t%0", out_operands
);
1115 output_asm_insn ("incf\t%0", out_operands
);
1117 output_asm_insn ("inct\t%0", out_operands
);
1123 /* Outputs the peephole for moving a constant that gets not'ed followed
1124 by an and (i.e. combine the not and the and into andn). BRC */
1127 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
1130 rtx out_operands
[3];
1131 const char * load_op
;
1135 trick_no
= try_constant_tricks (INTVAL (operands
[1]), &x
, &y
);
1136 gcc_assert (trick_no
== 2);
1138 out_operands
[0] = operands
[0];
1139 out_operands
[1] = GEN_INT (x
);
1140 out_operands
[2] = operands
[2];
1142 if (x
>= 0 && x
<= 127)
1143 load_op
= "movi\t%0,%1";
1145 /* Try exact power of two. */
1146 else if (CONST_OK_FOR_M (x
))
1147 load_op
= "bgeni\t%0,%P1";
1149 /* Try exact power of two - 1. */
1150 else if (CONST_OK_FOR_N (x
))
1151 load_op
= "bmaski\t%0,%N1";
1155 load_op
= "BADMOVI-andn\t%0, %1";
1159 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1160 output_asm_insn (buf
, out_operands
);
1165 /* Output an inline constant. */
1168 output_inline_const (machine_mode mode
, rtx operands
[])
1170 HOST_WIDE_INT x
= 0, y
= 0;
1172 rtx out_operands
[3];
1175 const char *dst_fmt
;
1176 HOST_WIDE_INT value
;
1178 value
= INTVAL (operands
[1]);
1180 trick_no
= try_constant_tricks (value
, &x
, &y
);
1181 /* lrw's are handled separately: Large inlinable constants never get
1182 turned into lrw's. Our caller uses try_constant_tricks to back
1183 off to an lrw rather than calling this routine. */
1184 gcc_assert (trick_no
!= 0);
1189 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1190 out_operands
[0] = operands
[0];
1191 out_operands
[1] = GEN_INT (x
);
1194 out_operands
[2] = GEN_INT (y
);
1196 /* Select dst format based on mode. */
1197 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1202 if (x
>= 0 && x
<= 127)
1203 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1205 /* Try exact power of two. */
1206 else if (CONST_OK_FOR_M (x
))
1207 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1209 /* Try exact power of two - 1. */
1210 else if (CONST_OK_FOR_N (x
))
1211 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1215 sprintf (load_op
, "BADMOVI-inline_const %s, %%1", dst_fmt
);
1222 strcpy (buf
, load_op
);
1225 sprintf (buf
, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1228 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1231 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1234 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1235 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1238 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1241 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1244 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1247 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1250 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1253 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1259 output_asm_insn (buf
, out_operands
);
1264 /* Output a move of a word or less value. */
1267 mcore_output_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
1268 machine_mode mode ATTRIBUTE_UNUSED
)
1270 rtx dst
= operands
[0];
1271 rtx src
= operands
[1];
1273 if (GET_CODE (dst
) == REG
)
1275 if (GET_CODE (src
) == REG
)
1277 if (REGNO (src
) == CC_REG
) /* r-c */
1280 return "mov\t%0,%1"; /* r-r*/
1282 else if (GET_CODE (src
) == MEM
)
1284 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1285 return "lrw\t%0,[%1]"; /* a-R */
1287 switch (GET_MODE (src
)) /* r-m */
1290 return "ldw\t%0,%1";
1292 return "ld.h\t%0,%1";
1294 return "ld.b\t%0,%1";
1299 else if (GET_CODE (src
) == CONST_INT
)
1303 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1304 return "movi\t%0,%1";
1305 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1306 return "bgeni\t%0,%P1\t// %1 %x1";
1307 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1308 return "bmaski\t%0,%N1\t// %1 %x1";
1309 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1310 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1312 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1315 return "lrw\t%0, %1"; /* Into the literal pool. */
1317 else if (GET_CODE (dst
) == MEM
) /* m-r */
1318 switch (GET_MODE (dst
))
1321 return "stw\t%1,%0";
1323 return "st.h\t%1,%0";
1325 return "st.b\t%1,%0";
1333 /* Return a sequence of instructions to perform DI or DF move.
1334 Since the MCORE cannot move a DI or DF in one instruction, we have
1335 to take care when we see overlapping source and dest registers. */
1338 mcore_output_movedouble (rtx operands
[], machine_mode mode ATTRIBUTE_UNUSED
)
1340 rtx dst
= operands
[0];
1341 rtx src
= operands
[1];
1343 if (GET_CODE (dst
) == REG
)
1345 if (GET_CODE (src
) == REG
)
1347 int dstreg
= REGNO (dst
);
1348 int srcreg
= REGNO (src
);
1350 /* Ensure the second source not overwritten. */
1351 if (srcreg
+ 1 == dstreg
)
1352 return "mov %R0,%R1\n\tmov %0,%1";
1354 return "mov %0,%1\n\tmov %R0,%R1";
1356 else if (GET_CODE (src
) == MEM
)
1358 rtx memexp
= XEXP (src
, 0);
1359 int dstreg
= REGNO (dst
);
1362 if (GET_CODE (memexp
) == LABEL_REF
)
1363 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1364 else if (GET_CODE (memexp
) == REG
)
1365 basereg
= REGNO (memexp
);
1366 else if (GET_CODE (memexp
) == PLUS
)
1368 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1369 basereg
= REGNO (XEXP (memexp
, 0));
1370 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1371 basereg
= REGNO (XEXP (memexp
, 1));
1378 /* ??? length attribute is wrong here. */
1379 if (dstreg
== basereg
)
1381 /* Just load them in reverse order. */
1382 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1384 /* XXX: alternative: move basereg to basereg+1
1385 and then fall through. */
1388 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1390 else if (GET_CODE (src
) == CONST_INT
)
1392 if (TARGET_LITTLE_END
)
1394 if (CONST_OK_FOR_I (INTVAL (src
)))
1395 output_asm_insn ("movi %0,%1", operands
);
1396 else if (CONST_OK_FOR_M (INTVAL (src
)))
1397 output_asm_insn ("bgeni %0,%P1", operands
);
1398 else if (CONST_OK_FOR_N (INTVAL (src
)))
1399 output_asm_insn ("bmaski %0,%N1", operands
);
1403 if (INTVAL (src
) < 0)
1404 return "bmaski %R0,32";
1406 return "movi %R0,0";
1410 if (CONST_OK_FOR_I (INTVAL (src
)))
1411 output_asm_insn ("movi %R0,%1", operands
);
1412 else if (CONST_OK_FOR_M (INTVAL (src
)))
1413 output_asm_insn ("bgeni %R0,%P1", operands
);
1414 else if (CONST_OK_FOR_N (INTVAL (src
)))
1415 output_asm_insn ("bmaski %R0,%N1", operands
);
1419 if (INTVAL (src
) < 0)
1420 return "bmaski %0,32";
1428 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1429 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1434 /* Predicates used by the templates. */
1437 mcore_arith_S_operand (rtx op
)
1439 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1445 /* Expand insert bit field. BRC */
1448 mcore_expand_insv (rtx operands
[])
1450 int width
= INTVAL (operands
[1]);
1451 int posn
= INTVAL (operands
[2]);
1453 rtx mreg
, sreg
, ereg
;
1455 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1456 for width==1 must be removed. Look around line 368. This is something
1457 we really want the md part to do. */
1458 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1460 /* Do directly with bseti or bclri. */
1461 /* RBE: 2/97 consider only low bit of constant. */
1462 if ((INTVAL (operands
[3]) & 1) == 0)
1464 mask
= ~(1 << posn
);
1465 emit_insn (gen_rtx_SET (operands
[0],
1466 gen_rtx_AND (SImode
, operands
[0],
1472 emit_insn (gen_rtx_SET (operands
[0],
1473 gen_rtx_IOR (SImode
, operands
[0],
1480 /* Look at some bit-field placements that we aren't interested
1481 in handling ourselves, unless specifically directed to do so. */
1482 if (! TARGET_W_FIELD
)
1483 return 0; /* Generally, give up about now. */
1485 if (width
== 8 && posn
% 8 == 0)
1486 /* Byte sized and aligned; let caller break it up. */
1489 if (width
== 16 && posn
% 16 == 0)
1490 /* Short sized and aligned; let caller break it up. */
1493 /* The general case - we can do this a little bit better than what the
1494 machine independent part tries. This will get rid of all the subregs
1495 that mess up constant folding in combine when working with relaxed
1498 /* If setting the entire field, do it directly. */
1499 if (GET_CODE (operands
[3]) == CONST_INT
1500 && INTVAL (operands
[3]) == ((1 << width
) - 1))
1502 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1503 emit_insn (gen_rtx_SET (operands
[0],
1504 gen_rtx_IOR (SImode
, operands
[0], mreg
)));
1508 /* Generate the clear mask. */
1509 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1511 /* Clear the field, to overlay it later with the source. */
1512 emit_insn (gen_rtx_SET (operands
[0],
1513 gen_rtx_AND (SImode
, operands
[0], mreg
)));
1515 /* If the source is constant 0, we've nothing to add back. */
1516 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1519 /* XXX: Should we worry about more games with constant values?
1520 We've covered the high profile: set/clear single-bit and many-bit
1521 fields. How often do we see "arbitrary bit pattern" constants? */
1522 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1524 /* Extract src as same width as dst (needed for signed values). We
1525 always have to do this since we widen everything to SImode.
1526 We don't have to mask if we're shifting this up against the
1527 MSB of the register (e.g., the shift will push out any hi-order
1529 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1531 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1532 emit_insn (gen_rtx_SET (sreg
, gen_rtx_AND (SImode
, sreg
, ereg
)));
1535 /* Insert source value in dest. */
1537 emit_insn (gen_rtx_SET (sreg
, gen_rtx_ASHIFT (SImode
, sreg
,
1540 emit_insn (gen_rtx_SET (operands
[0],
1541 gen_rtx_IOR (SImode
, operands
[0], sreg
)));
1546 /* ??? Block move stuff stolen from m88k. This code has not been
1547 verified for correctness. */
1549 /* Emit code to perform a block move. Choose the best method.
1551 OPERANDS[0] is the destination.
1552 OPERANDS[1] is the source.
1553 OPERANDS[2] is the size.
1554 OPERANDS[3] is the alignment safe to use. */
1556 /* Emit code to perform a block move with an offset sequence of ldw/st
1557 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1558 known constants. DEST and SRC are registers. OFFSET is the known
1559 starting point for the output pattern. */
1561 static const machine_mode mode_from_align
[] =
1563 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1567 block_move_sequence (rtx dst_mem
, rtx src_mem
, int size
, int align
)
1570 machine_mode mode
[2];
1579 x
= XEXP (dst_mem
, 0);
1582 x
= force_reg (Pmode
, x
);
1583 dst_mem
= replace_equiv_address (dst_mem
, x
);
1586 x
= XEXP (src_mem
, 0);
1589 x
= force_reg (Pmode
, x
);
1590 src_mem
= replace_equiv_address (src_mem
, x
);
1593 active
[0] = active
[1] = false;
1604 next_amount
= (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
1605 next_amount
= MIN (next_amount
, align
);
1607 amount
[next
] = next_amount
;
1608 mode
[next
] = mode_from_align
[next_amount
];
1609 temp
[next
] = gen_reg_rtx (mode
[next
]);
1611 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1612 emit_insn (gen_rtx_SET (temp
[next
], x
));
1614 offset_ld
+= next_amount
;
1615 size
-= next_amount
;
1616 active
[next
] = true;
1621 active
[phase
] = false;
1623 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1624 emit_insn (gen_rtx_SET (x
, temp
[phase
]));
1626 offset_st
+= amount
[phase
];
1629 while (active
[next
]);
1633 mcore_expand_block_move (rtx
*operands
)
1635 HOST_WIDE_INT align
, bytes
, max
;
1637 if (GET_CODE (operands
[2]) != CONST_INT
)
1640 bytes
= INTVAL (operands
[2]);
1641 align
= INTVAL (operands
[3]);
1670 block_move_sequence (operands
[0], operands
[1], bytes
, align
);
1678 /* Code to generate prologue and epilogue sequences. */
1679 static int number_of_regs_before_varargs
;
1681 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1682 for a varargs function. */
1683 static int current_function_anonymous_args
;
1685 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1686 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1687 #define ADDI_REACH (32) /* Maximum addi operand. */
1690 layout_mcore_frame (struct mcore_frame
* infp
)
1698 unsigned int growths
;
1701 /* Might have to spill bytes to re-assemble a big argument that
1702 was passed partially in registers and partially on the stack. */
1703 nbytes
= crtl
->args
.pretend_args_size
;
1705 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1706 if (current_function_anonymous_args
)
1707 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
1709 infp
->arg_size
= nbytes
;
1711 /* How much space to save non-volatile registers we stomp. */
1712 infp
->reg_mask
= calc_live_regs (& n
);
1713 infp
->reg_size
= n
* 4;
1715 /* And the rest of it... locals and space for overflowed outbounds. */
1716 infp
->local_size
= get_frame_size ();
1717 infp
->outbound_size
= crtl
->outgoing_args_size
;
1719 /* Make sure we have a whole number of words for the locals. */
1720 if (infp
->local_size
% STACK_BYTES
)
1721 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
1723 /* Only thing we know we have to pad is the outbound space, since
1724 we've aligned our locals assuming that base of locals is aligned. */
1725 infp
->pad_local
= 0;
1727 infp
->pad_outbound
= 0;
1728 if (infp
->outbound_size
% STACK_BYTES
)
1729 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
1731 /* Now we see how we want to stage the prologue so that it does
1732 the most appropriate stack growth and register saves to either:
1734 (2) reduce instruction space, or
1735 (3) reduce stack space. */
1736 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
1737 infp
->growth
[i
] = 0;
1739 regarg
= infp
->reg_size
+ infp
->arg_size
;
1740 localregarg
= infp
->local_size
+ regarg
;
1741 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
1744 /* XXX: Consider one where we consider localregarg + outbound too! */
1746 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1747 use stw's with offsets and buy the frame in one shot. */
1748 if (localregarg
<= ADDI_REACH
1749 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1751 /* Make sure we'll be aligned. */
1752 if (localregarg
% STACK_BYTES
)
1753 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1755 step
= localregarg
+ infp
->pad_reg
;
1756 infp
->reg_offset
= infp
->local_size
;
1758 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
1761 infp
->reg_offset
+= outbounds
;
1765 infp
->arg_offset
= step
- 4;
1766 infp
->growth
[growths
++] = step
;
1767 infp
->reg_growth
= growths
;
1768 infp
->local_growth
= growths
;
1770 /* If we haven't already folded it in. */
1772 infp
->growth
[growths
++] = outbounds
;
1777 /* Frame can't be done with a single subi, but can be done with 2
1778 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1779 shift some of the stack purchase into the first subi, so both are
1780 single instructions. */
1781 if (localregarg
<= STORE_REACH
1782 && (infp
->local_size
> ADDI_REACH
)
1783 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1787 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1788 if (localregarg
% STACK_BYTES
)
1789 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1791 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
1792 step
= ADDI_REACH
; /* As much up front as we can. */
1796 /* XXX: Consider whether step will still be aligned; we believe so. */
1797 infp
->arg_offset
= step
- 4;
1798 infp
->growth
[growths
++] = step
;
1799 infp
->reg_growth
= growths
;
1800 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
1803 /* Can we fold in any space required for outbounds? */
1804 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
1810 /* Get the rest of the locals in place. */
1812 infp
->growth
[growths
++] = step
;
1813 infp
->local_growth
= growths
;
1816 gcc_assert (all
== 0);
1818 /* Finish off if we need to do so. */
1820 infp
->growth
[growths
++] = outbounds
;
1825 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1826 Then we buy the rest of the frame in 1 or 2 steps depending on
1827 whether we need a frame pointer. */
1828 if ((regarg
% STACK_BYTES
) == 0)
1830 infp
->growth
[growths
++] = regarg
;
1831 infp
->reg_growth
= growths
;
1832 infp
->arg_offset
= regarg
- 4;
1833 infp
->reg_offset
= 0;
1835 if (infp
->local_size
% STACK_BYTES
)
1836 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1838 step
= infp
->local_size
+ infp
->pad_local
;
1840 if (!frame_pointer_needed
)
1846 infp
->growth
[growths
++] = step
;
1847 infp
->local_growth
= growths
;
1849 /* If there's any left to be done. */
1851 infp
->growth
[growths
++] = outbounds
;
1856 /* XXX: optimizations that we'll want to play with....
1857 -- regarg is not aligned, but it's a small number of registers;
1858 use some of localsize so that regarg is aligned and then
1859 save the registers. */
1861 /* Simple encoding; plods down the stack buying the pieces as it goes.
1862 -- does not optimize space consumption.
1863 -- does not attempt to optimize instruction counts.
1864 -- but it is safe for all alignments. */
1865 if (regarg
% STACK_BYTES
!= 0)
1866 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
1868 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
1869 infp
->reg_growth
= growths
;
1870 infp
->arg_offset
= infp
->growth
[0] - 4;
1871 infp
->reg_offset
= 0;
1873 if (frame_pointer_needed
)
1875 if (infp
->local_size
% STACK_BYTES
!= 0)
1876 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1878 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
1879 infp
->local_growth
= growths
;
1881 infp
->growth
[growths
++] = outbounds
;
1885 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
1886 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
1888 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
1889 infp
->local_growth
= growths
;
1892 /* Anything else that we've forgotten?, plus a few consistency checks. */
1894 gcc_assert (infp
->reg_offset
>= 0);
1895 gcc_assert (growths
<= MAX_STACK_GROWS
);
1897 for (i
= 0; i
< growths
; i
++)
1898 gcc_assert (!(infp
->growth
[i
] % STACK_BYTES
));
1901 /* Define the offset between two registers, one to be eliminated, and
1902 the other its replacement, at the start of a routine. */
1905 mcore_initial_elimination_offset (int from
, int to
)
1909 struct mcore_frame fi
;
1911 layout_mcore_frame (& fi
);
1914 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
1916 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
1918 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1921 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1922 return above_frame
+ below_frame
;
1924 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1930 /* Keep track of some information about varargs for the prolog. */
1933 mcore_setup_incoming_varargs (cumulative_args_t args_so_far_v
,
1934 machine_mode mode
, tree type
,
1935 int * ptr_pretend_size ATTRIBUTE_UNUSED
,
1936 int second_time ATTRIBUTE_UNUSED
)
1938 CUMULATIVE_ARGS
*args_so_far
= get_cumulative_args (args_so_far_v
);
1940 current_function_anonymous_args
= 1;
1942 /* We need to know how many argument registers are used before
1943 the varargs start, so that we can push the remaining argument
1944 registers during the prologue. */
1945 number_of_regs_before_varargs
= *args_so_far
+ mcore_num_arg_regs (mode
, type
);
1947 /* There is a bug somewhere in the arg handling code.
1948 Until I can find it this workaround always pushes the
1949 last named argument onto the stack. */
1950 number_of_regs_before_varargs
= *args_so_far
;
1952 /* The last named argument may be split between argument registers
1953 and the stack. Allow for this here. */
1954 if (number_of_regs_before_varargs
> NPARM_REGS
)
1955 number_of_regs_before_varargs
= NPARM_REGS
;
1959 mcore_expand_prolog (void)
1961 struct mcore_frame fi
;
1962 int space_allocated
= 0;
1965 /* Find out what we're doing. */
1966 layout_mcore_frame (&fi
);
1968 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
1969 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
1973 /* Emit a symbol for this routine's frame size. */
1976 x
= DECL_RTL (current_function_decl
);
1978 gcc_assert (GET_CODE (x
) == MEM
);
1982 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1984 free (mcore_current_function_name
);
1986 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
1988 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
1990 if (cfun
->calls_alloca
)
1991 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
1994 We're looking at how the 8byte alignment affects stack layout
1995 and where we had to pad things. This emits information we can
1996 extract which tells us about frame sizes and the like. */
1997 fprintf (asm_out_file
,
1998 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
1999 mcore_current_function_name
,
2000 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
2001 fi
.local_size
, fi
.outbound_size
,
2002 frame_pointer_needed
);
2005 if (mcore_naked_function_p ())
2008 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2009 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2011 /* If we have a parameter passed partially in regs and partially in memory,
2012 the registers will have been stored to memory already in function.c. So
2013 we only need to do something here for varargs functions. */
2014 if (fi
.arg_size
!= 0 && crtl
->args
.pretend_args_size
== 0)
2017 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
2018 int remaining
= fi
.arg_size
;
2020 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
2022 emit_insn (gen_movsi
2023 (gen_rtx_MEM (SImode
,
2024 plus_constant (Pmode
, stack_pointer_rtx
,
2026 gen_rtx_REG (SImode
, rn
)));
2030 /* Do we need another stack adjustment before we do the register saves? */
2031 if (growth
< fi
.reg_growth
)
2032 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2034 if (fi
.reg_size
!= 0)
2037 int offs
= fi
.reg_offset
;
2039 for (i
= 15; i
>= 0; i
--)
2041 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2045 while (fi
.reg_mask
& (1 << first_reg
))
2049 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2050 gen_rtx_REG (SImode
, first_reg
),
2051 GEN_INT (16 - first_reg
)));
2053 i
-= (15 - first_reg
);
2054 offs
+= (16 - first_reg
) * 4;
2056 else if (fi
.reg_mask
& (1 << i
))
2058 emit_insn (gen_movsi
2059 (gen_rtx_MEM (SImode
,
2060 plus_constant (Pmode
, stack_pointer_rtx
,
2062 gen_rtx_REG (SImode
, i
)));
2068 /* Figure the locals + outbounds. */
2069 if (frame_pointer_needed
)
2071 /* If we haven't already purchased to 'fp'. */
2072 if (growth
< fi
.local_growth
)
2073 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2075 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2077 /* ... and then go any remaining distance for outbounds, etc. */
2078 if (fi
.growth
[growth
])
2079 output_stack_adjust (-1, fi
.growth
[growth
++]);
2083 if (growth
< fi
.local_growth
)
2084 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2085 if (fi
.growth
[growth
])
2086 output_stack_adjust (-1, fi
.growth
[growth
++]);
2091 mcore_expand_epilog (void)
2093 struct mcore_frame fi
;
2096 int growth
= MAX_STACK_GROWS
- 1 ;
2099 /* Find out what we're doing. */
2100 layout_mcore_frame(&fi
);
2102 if (mcore_naked_function_p ())
2105 /* If we had a frame pointer, restore the sp from that. */
2106 if (frame_pointer_needed
)
2108 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2109 growth
= fi
.local_growth
- 1;
2113 /* XXX: while loop should accumulate and do a single sell. */
2114 while (growth
>= fi
.local_growth
)
2116 if (fi
.growth
[growth
] != 0)
2117 output_stack_adjust (1, fi
.growth
[growth
]);
2122 /* Make sure we've shrunk stack back to the point where the registers
2123 were laid down. This is typically 0/1 iterations. Then pull the
2124 register save information back off the stack. */
2125 while (growth
>= fi
.reg_growth
)
2126 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2128 offs
= fi
.reg_offset
;
2130 for (i
= 15; i
>= 0; i
--)
2132 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2136 /* Find the starting register. */
2139 while (fi
.reg_mask
& (1 << first_reg
))
2144 emit_insn (gen_load_multiple (gen_rtx_REG (SImode
, first_reg
),
2145 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2146 GEN_INT (16 - first_reg
)));
2148 i
-= (15 - first_reg
);
2149 offs
+= (16 - first_reg
) * 4;
2151 else if (fi
.reg_mask
& (1 << i
))
2153 emit_insn (gen_movsi
2154 (gen_rtx_REG (SImode
, i
),
2155 gen_rtx_MEM (SImode
,
2156 plus_constant (Pmode
, stack_pointer_rtx
,
2162 /* Give back anything else. */
2163 /* XXX: Should accumulate total and then give it back. */
2165 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2168 /* This code is borrowed from the SH port. */
2170 /* The MCORE cannot load a large constant into a register, constants have to
2171 come from a pc relative load. The reference of a pc relative load
2172 instruction must be less than 1k in front of the instruction. This
2173 means that we often have to dump a constant inside a function, and
2174 generate code to branch around it.
2176 It is important to minimize this, since the branches will slow things
2177 down and make things bigger.
2179 Worst case code looks like:
2195 We fix this by performing a scan before scheduling, which notices which
2196 instructions need to have their operands fetched from the constant table
2197 and builds the table.
2201 scan, find an instruction which needs a pcrel move. Look forward, find the
2202 last barrier which is within MAX_COUNT bytes of the requirement.
2203 If there isn't one, make one. Process all the instructions between
2204 the find and the barrier.
2206 In the above example, we can tell that L3 is within 1k of L1, so
2207 the first move can be shrunk from the 2 insn+constant sequence into
2208 just 1 insn, and the constant moved to L3 to make:
2218 Then the second move becomes the target for the shortening process. */
2222 rtx value
; /* Value in table. */
2223 rtx label
; /* Label of value. */
2226 /* The maximum number of constants that can fit into one pool, since
2227 the pc relative range is 0...1020 bytes and constants are at least 4
2228 bytes long. We subtract 4 from the range to allow for the case where
2229 we need to add a branch/align before the constant pool. */
2231 #define MAX_COUNT 1016
2232 #define MAX_POOL_SIZE (MAX_COUNT/4)
2233 static pool_node pool_vector
[MAX_POOL_SIZE
];
2234 static int pool_size
;
2236 /* Dump out any constants accumulated in the final pass. These
2237 will only be labels. */
2240 mcore_output_jump_label_table (void)
2246 fprintf (asm_out_file
, "\t.align 2\n");
2248 for (i
= 0; i
< pool_size
; i
++)
2250 pool_node
* p
= pool_vector
+ i
;
2252 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2254 output_asm_insn (".long %0", &p
->value
);
2263 /* Check whether insn is a candidate for a conditional. */
2266 is_cond_candidate (rtx insn
)
2268 /* The only things we conditionalize are those that can be directly
2269 changed into a conditional. Only bother with SImode items. If
2270 we wanted to be a little more aggressive, we could also do other
2271 modes such as DImode with reg-reg move or load 0. */
2272 if (NONJUMP_INSN_P (insn
))
2274 rtx pat
= PATTERN (insn
);
2277 if (GET_CODE (pat
) != SET
)
2280 dst
= XEXP (pat
, 0);
2282 if ((GET_CODE (dst
) != REG
&&
2283 GET_CODE (dst
) != SUBREG
) ||
2284 GET_MODE (dst
) != SImode
)
2287 src
= XEXP (pat
, 1);
2289 if ((GET_CODE (src
) == REG
||
2290 (GET_CODE (src
) == SUBREG
&&
2291 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2292 GET_MODE (src
) == SImode
)
2293 return COND_MOV_INSN
;
2294 else if (GET_CODE (src
) == CONST_INT
&&
2296 return COND_CLR_INSN
;
2297 else if (GET_CODE (src
) == PLUS
&&
2298 (GET_CODE (XEXP (src
, 0)) == REG
||
2299 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2300 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2301 GET_MODE (XEXP (src
, 0)) == SImode
&&
2302 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2303 INTVAL (XEXP (src
, 1)) == 1)
2304 return COND_INC_INSN
;
2305 else if (((GET_CODE (src
) == MINUS
&&
2306 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2307 INTVAL( XEXP (src
, 1)) == 1) ||
2308 (GET_CODE (src
) == PLUS
&&
2309 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2310 INTVAL (XEXP (src
, 1)) == -1)) &&
2311 (GET_CODE (XEXP (src
, 0)) == REG
||
2312 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2313 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2314 GET_MODE (XEXP (src
, 0)) == SImode
)
2315 return COND_DEC_INSN
;
2317 /* Some insns that we don't bother with:
2318 (set (rx:DI) (ry:DI))
2319 (set (rx:DI) (const_int 0))
2323 else if (JUMP_P (insn
)
2324 && GET_CODE (PATTERN (insn
)) == SET
2325 && GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2326 return COND_BRANCH_INSN
;
2331 /* Emit a conditional version of insn and replace the old insn with the
2332 new one. Return the new insn if emitted. */
2335 emit_new_cond_insn (rtx_insn
*insn
, int cond
)
2341 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2344 pat
= PATTERN (insn
);
2346 if (NONJUMP_INSN_P (insn
))
2348 dst
= SET_DEST (pat
);
2349 src
= SET_SRC (pat
);
2353 dst
= JUMP_LABEL (insn
);
2362 c_insn
= gen_movt0 (dst
, src
, dst
);
2364 c_insn
= gen_movt0 (dst
, dst
, src
);
2369 c_insn
= gen_incscc (dst
, dst
);
2371 c_insn
= gen_incscc_false (dst
, dst
);
2376 c_insn
= gen_decscc (dst
, dst
);
2378 c_insn
= gen_decscc_false (dst
, dst
);
2381 case COND_BRANCH_INSN
:
2383 c_insn
= gen_branch_true (dst
);
2385 c_insn
= gen_branch_false (dst
);
2392 /* Only copy the notes if they exist. */
2393 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2395 /* We really don't need to bother with the notes and links at this
2396 point, but go ahead and save the notes. This will help is_dead()
2397 when applying peepholes (links don't matter since they are not
2398 used any more beyond this point for the mcore). */
2399 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2402 if (num
== COND_BRANCH_INSN
)
2404 /* For jumps, we need to be a little bit careful and emit the new jump
2405 before the old one and to update the use count for the target label.
2406 This way, the barrier following the old (uncond) jump will get
2407 deleted, but the label won't. */
2408 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2410 ++ LABEL_NUSES (dst
);
2412 JUMP_LABEL (c_insn
) = dst
;
2415 c_insn
= emit_insn_after (c_insn
, insn
);
2419 return as_a
<rtx_insn
*> (c_insn
);
2422 /* Attempt to change a basic block into a series of conditional insns. This
2423 works by taking the branch at the end of the 1st block and scanning for the
2424 end of the 2nd block. If all instructions in the 2nd block have cond.
2425 versions and the label at the start of block 3 is the same as the target
2426 from the branch at block 1, then conditionalize all insn in block 2 using
2427 the inverse condition of the branch at block 1. (Note I'm bending the
2428 definition of basic block here.)
2432 bt L2 <-- end of block 1 (delete)
2435 br L3 <-- end of block 2
2437 L2: ... <-- start of block 3 (NUSES==1)
2448 we can delete the L2 label if NUSES==1 and re-apply the optimization
2449 starting at the last instruction of block 2. This may allow an entire
2450 if-then-else statement to be conditionalized. BRC */
2452 conditionalize_block (rtx_insn
*first
)
2456 rtx_insn
*end_blk_1_br
= 0;
2457 rtx_insn
*end_blk_2_insn
= 0;
2458 rtx_insn
*start_blk_3_lab
= 0;
2464 /* Check that the first insn is a candidate conditional jump. This is
2465 the one that we'll eliminate. If not, advance to the next insn to
2467 if (! JUMP_P (first
)
2468 || GET_CODE (PATTERN (first
)) != SET
2469 || GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2470 return NEXT_INSN (first
);
2472 /* Extract some information we need. */
2473 end_blk_1_br
= first
;
2474 br_pat
= PATTERN (end_blk_1_br
);
2476 /* Complement the condition since we use the reverse cond. for the insns. */
2477 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2479 /* Determine what kind of branch we have. */
2480 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2482 /* A normal branch, so extract label out of first arm. */
2483 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2487 /* An inverse branch, so extract the label out of the 2nd arm
2488 and complement the condition. */
2490 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2493 /* Scan forward for the start of block 2: it must start with a
2494 label and that label must be the same as the branch target
2495 label from block 1. We don't care about whether block 2 actually
2496 ends with a branch or a label (an uncond. branch is
2497 conditionalizable). */
2498 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2502 code
= GET_CODE (insn
);
2504 /* Look for the label at the start of block 3. */
2505 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2508 /* Skip barriers, notes, and conditionalizable insns. If the
2509 insn is not conditionalizable or makes this optimization fail,
2510 just return the next insn so we can start over from that point. */
2511 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2512 return NEXT_INSN (insn
);
2514 /* Remember the last real insn before the label (i.e. end of block 2). */
2515 if (code
== JUMP_INSN
|| code
== INSN
)
2518 end_blk_2_insn
= insn
;
2525 /* It is possible for this optimization to slow performance if the blocks
2526 are long. This really depends upon whether the branch is likely taken
2527 or not. If the branch is taken, we slow performance in many cases. But,
2528 if the branch is not taken, we always help performance (for a single
2529 block, but for a double block (i.e. when the optimization is re-applied)
2530 this is not true since the 'right thing' depends on the overall length of
2531 the collapsed block). As a compromise, don't apply this optimization on
2532 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2533 the best threshold depends on the latencies of the instructions (i.e.,
2534 the branch penalty). */
2535 if (optimize
> 1 && blk_size
> 2)
2538 /* At this point, we've found the start of block 3 and we know that
2539 it is the destination of the branch from block 1. Also, all
2540 instructions in the block 2 are conditionalizable. So, apply the
2541 conditionalization and delete the branch. */
2542 start_blk_3_lab
= insn
;
2544 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2545 insn
= NEXT_INSN (insn
))
2549 if (insn
->deleted ())
2552 /* Try to form a conditional variant of the instruction and emit it. */
2553 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2555 if (end_blk_2_insn
== insn
)
2556 end_blk_2_insn
= newinsn
;
2562 /* Note whether we will delete the label starting blk 3 when the jump
2563 gets deleted. If so, we want to re-apply this optimization at the
2564 last real instruction right before the label. */
2565 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2567 start_blk_3_lab
= 0;
2570 /* ??? we probably should redistribute the death notes for this insn, esp.
2571 the death of cc, but it doesn't really matter this late in the game.
2572 The peepholes all use is_dead() which will find the correct death
2573 regardless of whether there is a note. */
2574 delete_insn (end_blk_1_br
);
2576 if (! start_blk_3_lab
)
2577 return end_blk_2_insn
;
2579 /* Return the insn right after the label at the start of block 3. */
2580 return NEXT_INSN (start_blk_3_lab
);
2583 /* Apply the conditionalization of blocks optimization. This is the
2584 outer loop that traverses through the insns scanning for a branch
2585 that signifies an opportunity to apply the optimization. Note that
2586 this optimization is applied late. If we could apply it earlier,
2587 say before cse 2, it may expose more optimization opportunities.
2588 but, the pay back probably isn't really worth the effort (we'd have
2589 to update all reg/flow/notes/links/etc to make it work - and stick it
2590 in before cse 2). */
2593 conditionalize_optimization (void)
2597 for (insn
= get_insns (); insn
; insn
= conditionalize_block (insn
))
2601 /* This is to handle loads from the constant pool. */
2606 /* Reset this variable. */
2607 current_function_anonymous_args
= 0;
2612 /* Conditionalize blocks where we can. */
2613 conditionalize_optimization ();
2615 /* Literal pool generation is now pushed off until the assembler. */
2619 /* Return true if X is something that can be moved directly into r15. */
2622 mcore_r15_operand_p (rtx x
)
2624 switch (GET_CODE (x
))
2627 return mcore_const_ok_for_inline (INTVAL (x
));
2639 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't
2640 directly move X into it, use r1-r14 as a temporary. */
2643 mcore_secondary_reload_class (enum reg_class rclass
,
2644 machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2646 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], 15)
2647 && !mcore_r15_operand_p (x
))
2652 /* Return the reg_class to use when reloading the rtx X into the class
2653 RCLASS. If X is too complex to move directly into r15, prefer to
2654 use LRW_REGS instead. */
2657 mcore_reload_class (rtx x
, enum reg_class rclass
)
2659 if (reg_class_subset_p (LRW_REGS
, rclass
) && !mcore_r15_operand_p (x
))
2665 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2666 register. Note that the current version doesn't worry about whether
2667 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2668 in r2 matches an SImode in r2. Might think in the future about whether
2669 we want to be able to say something about modes. */
2672 mcore_is_same_reg (rtx x
, rtx y
)
2674 /* Strip any and all of the subreg wrappers. */
2675 while (GET_CODE (x
) == SUBREG
)
2678 while (GET_CODE (y
) == SUBREG
)
2681 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
2688 mcore_option_override (void)
2690 /* Only the m340 supports little endian code. */
2691 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
2692 target_flags
|= MASK_M340
;
2696 /* Compute the number of word sized registers needed to
2697 hold a function argument of mode MODE and type TYPE. */
2700 mcore_num_arg_regs (machine_mode mode
, const_tree type
)
2704 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2707 if (type
&& mode
== BLKmode
)
2708 size
= int_size_in_bytes (type
);
2710 size
= GET_MODE_SIZE (mode
);
2712 return ROUND_ADVANCE (size
);
2716 handle_structs_in_regs (machine_mode mode
, const_tree type
, int reg
)
2720 /* The MCore ABI defines that a structure whose size is not a whole multiple
2721 of bytes is passed packed into registers (or spilled onto the stack if
2722 not enough registers are available) with the last few bytes of the
2723 structure being packed, left-justified, into the last register/stack slot.
2724 GCC handles this correctly if the last word is in a stack slot, but we
2725 have to generate a special, PARALLEL RTX if the last word is in an
2726 argument register. */
2728 && TYPE_MODE (type
) == BLKmode
2729 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
2730 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
2731 && (size
% UNITS_PER_WORD
!= 0)
2732 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
2734 rtx arg_regs
[NPARM_REGS
];
2739 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
2742 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
2743 GEN_INT (nregs
* UNITS_PER_WORD
));
2747 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2748 gcc_assert (ARRAY_SIZE (arg_regs
) == 6);
2749 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
2750 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
2752 result
= gen_rtx_PARALLEL (mode
, rtvec
);
2756 return gen_rtx_REG (mode
, reg
);
2760 mcore_function_value (const_tree valtype
, const_tree func
)
2765 mode
= TYPE_MODE (valtype
);
2767 /* Since we promote return types, we must promote the mode here too. */
2768 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
2770 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
2773 /* Define where to put the arguments to a function.
2774 Value is zero to push the argument on the stack,
2775 or a hard register in which to store the argument.
2777 MODE is the argument's machine mode.
2778 TYPE is the data type of the argument (as a tree).
2779 This is null for libcalls where that information may
2781 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2782 the preceding args and about the function being called.
2783 NAMED is nonzero if this argument is a named parameter
2784 (otherwise it is an extra parameter matching an ellipsis).
2786 On MCore the first args are normally in registers
2787 and the rest are pushed. Any arg that starts within the first
2788 NPARM_REGS words is at least partially passed in a register unless
2789 its data type forbids. */
2792 mcore_function_arg (cumulative_args_t cum
, machine_mode mode
,
2793 const_tree type
, bool named
)
2797 if (! named
|| mode
== VOIDmode
)
2800 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2803 arg_reg
= ROUND_REG (*get_cumulative_args (cum
), mode
);
2805 if (arg_reg
< NPARM_REGS
)
2806 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
2812 mcore_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2813 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2815 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2817 *cum
= (ROUND_REG (*cum
, mode
)
2818 + (int)named
* mcore_num_arg_regs (mode
, type
));
2822 mcore_function_arg_boundary (machine_mode mode
,
2823 const_tree type ATTRIBUTE_UNUSED
)
2825 /* Doubles must be aligned to an 8 byte boundary. */
2826 return (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) == 8
2831 /* Returns the number of bytes of argument registers required to hold *part*
2832 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2833 the type is not known). If the argument fits entirely in the argument
2834 registers, or entirely on the stack, then 0 is returned. CUM is the
2835 number of argument registers already used by earlier parameters to
2839 mcore_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
2840 tree type
, bool named
)
2842 int reg
= ROUND_REG (*get_cumulative_args (cum
), mode
);
2847 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2850 /* REG is not the *hardware* register number of the register that holds
2851 the argument, it is the *argument* register number. So for example,
2852 the first argument to a function goes in argument register 0, which
2853 translates (for the MCore) into hardware register 2. The second
2854 argument goes into argument register 1, which translates into hardware
2855 register 3, and so on. NPARM_REGS is the number of argument registers
2856 supported by the target, not the maximum hardware register number of
2858 if (reg
>= NPARM_REGS
)
2861 /* If the argument fits entirely in registers, return 0. */
2862 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
2865 /* The argument overflows the number of available argument registers.
2866 Compute how many argument registers have not yet been assigned to
2867 hold an argument. */
2868 reg
= NPARM_REGS
- reg
;
2870 /* Return partially in registers and partially on the stack. */
2871 return reg
* UNITS_PER_WORD
;
2874 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2877 mcore_dllexport_name_p (const char * symbol
)
2879 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
2882 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2885 mcore_dllimport_name_p (const char * symbol
)
2887 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
2890 /* Mark a DECL as being dllexport'd. */
2893 mcore_mark_dllexport (tree decl
)
2895 const char * oldname
;
2900 rtlname
= XEXP (DECL_RTL (decl
), 0);
2902 if (GET_CODE (rtlname
) == MEM
)
2903 rtlname
= XEXP (rtlname
, 0);
2904 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2905 oldname
= XSTR (rtlname
, 0);
2907 if (mcore_dllexport_name_p (oldname
))
2908 return; /* Already done. */
2910 newname
= XALLOCAVEC (char, strlen (oldname
) + 4);
2911 sprintf (newname
, "@e.%s", oldname
);
2913 /* We pass newname through get_identifier to ensure it has a unique
2914 address. RTL processing can sometimes peek inside the symbol ref
2915 and compare the string's addresses to see if two symbols are
2917 /* ??? At least I think that's why we do this. */
2918 idp
= get_identifier (newname
);
2920 XEXP (DECL_RTL (decl
), 0) =
2921 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2924 /* Mark a DECL as being dllimport'd. */
2927 mcore_mark_dllimport (tree decl
)
2929 const char * oldname
;
2935 rtlname
= XEXP (DECL_RTL (decl
), 0);
2937 if (GET_CODE (rtlname
) == MEM
)
2938 rtlname
= XEXP (rtlname
, 0);
2939 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2940 oldname
= XSTR (rtlname
, 0);
2942 gcc_assert (!mcore_dllexport_name_p (oldname
));
2943 if (mcore_dllimport_name_p (oldname
))
2944 return; /* Already done. */
2946 /* ??? One can well ask why we're making these checks here,
2947 and that would be a good question. */
2949 /* Imported variables can't be initialized. */
2950 if (TREE_CODE (decl
) == VAR_DECL
2951 && !DECL_VIRTUAL_P (decl
)
2952 && DECL_INITIAL (decl
))
2954 error ("initialized variable %q+D is marked dllimport", decl
);
2958 /* `extern' needn't be specified with dllimport.
2959 Specify `extern' now and hope for the best. Sigh. */
2960 if (TREE_CODE (decl
) == VAR_DECL
2961 /* ??? Is this test for vtables needed? */
2962 && !DECL_VIRTUAL_P (decl
))
2964 DECL_EXTERNAL (decl
) = 1;
2965 TREE_PUBLIC (decl
) = 1;
2968 newname
= XALLOCAVEC (char, strlen (oldname
) + 11);
2969 sprintf (newname
, "@i.__imp_%s", oldname
);
2971 /* We pass newname through get_identifier to ensure it has a unique
2972 address. RTL processing can sometimes peek inside the symbol ref
2973 and compare the string's addresses to see if two symbols are
2975 /* ??? At least I think that's why we do this. */
2976 idp
= get_identifier (newname
);
2978 newrtl
= gen_rtx_MEM (Pmode
,
2979 gen_rtx_SYMBOL_REF (Pmode
,
2980 IDENTIFIER_POINTER (idp
)));
2981 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2985 mcore_dllexport_p (tree decl
)
2987 if ( TREE_CODE (decl
) != VAR_DECL
2988 && TREE_CODE (decl
) != FUNCTION_DECL
)
2991 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
2995 mcore_dllimport_p (tree decl
)
2997 if ( TREE_CODE (decl
) != VAR_DECL
2998 && TREE_CODE (decl
) != FUNCTION_DECL
)
3001 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
3004 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3005 install some info in the .drective (PE) or .exports (ELF) sections. */
3008 mcore_encode_section_info (tree decl
, rtx rtl ATTRIBUTE_UNUSED
, int first ATTRIBUTE_UNUSED
)
3010 /* Mark the decl so we can tell from the rtl whether the object is
3011 dllexport'd or dllimport'd. */
3012 if (mcore_dllexport_p (decl
))
3013 mcore_mark_dllexport (decl
);
3014 else if (mcore_dllimport_p (decl
))
3015 mcore_mark_dllimport (decl
);
3017 /* It might be that DECL has already been marked as dllimport, but
3018 a subsequent definition nullified that. The attribute is gone
3019 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3020 else if ((TREE_CODE (decl
) == FUNCTION_DECL
3021 || TREE_CODE (decl
) == VAR_DECL
)
3022 && DECL_RTL (decl
) != NULL_RTX
3023 && GET_CODE (DECL_RTL (decl
)) == MEM
3024 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
3025 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
3026 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
3028 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
3029 tree idp
= get_identifier (oldname
+ 9);
3030 rtx newrtl
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
3032 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3034 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3035 ??? We leave these alone for now. */
3039 /* Undo the effects of the above. */
3042 mcore_strip_name_encoding (const char * str
)
3044 return str
+ (str
[0] == '@' ? 3 : 0);
3047 /* MCore specific attribute support.
3048 dllexport - for exporting a function/variable that will live in a dll
3049 dllimport - for importing a function/variable from a dll
3050 naked - do not create a function prologue/epilogue. */
3052 /* Handle a "naked" attribute; arguments as in
3053 struct attribute_spec.handler. */
3056 mcore_handle_naked_attribute (tree
* node
, tree name
, tree args ATTRIBUTE_UNUSED
,
3057 int flags ATTRIBUTE_UNUSED
, bool * no_add_attrs
)
3059 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3061 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3063 *no_add_attrs
= true;
3069 /* ??? It looks like this is PE specific? Oh well, this is what the
3070 old code did as well. */
3073 mcore_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
3078 const char * prefix
;
3080 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3082 /* Strip off any encoding in name. */
3083 name
= (* targetm
.strip_name_encoding
) (name
);
3085 /* The object is put in, for example, section .text$foo.
3086 The linker will then ultimately place them in .text
3087 (everything from the $ on is stripped). */
3088 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3090 /* For compatibility with EPOC, we ignore the fact that the
3091 section might have relocs against it. */
3092 else if (decl_readonly_section (decl
, 0))
3097 len
= strlen (name
) + strlen (prefix
);
3098 string
= XALLOCAVEC (char, len
+ 1);
3100 sprintf (string
, "%s%s", prefix
, name
);
3102 set_decl_section_name (decl
, string
);
3106 mcore_naked_function_p (void)
3108 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3112 mcore_warn_func_return (tree decl
)
3114 /* Naked functions are implemented entirely in assembly, including the
3115 return sequence, so suppress warnings about this. */
3116 return lookup_attribute ("naked", DECL_ATTRIBUTES (decl
)) == NULL_TREE
;
3119 #ifdef OBJECT_FORMAT_ELF
3121 mcore_asm_named_section (const char *name
,
3122 unsigned int flags ATTRIBUTE_UNUSED
,
3123 tree decl ATTRIBUTE_UNUSED
)
3125 fprintf (asm_out_file
, "\t.section %s\n", name
);
3127 #endif /* OBJECT_FORMAT_ELF */
3129 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3132 mcore_external_libcall (rtx fun
)
3134 fprintf (asm_out_file
, "\t.import\t");
3135 assemble_name (asm_out_file
, XSTR (fun
, 0));
3136 fprintf (asm_out_file
, "\n");
3139 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3142 mcore_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3144 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
3145 return (size
== -1 || size
> 2 * UNITS_PER_WORD
);
3148 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE.
3149 Output assembler code for a block containing the constant parts
3150 of a trampoline, leaving space for the variable parts.
3152 On the MCore, the trampoline looks like:
3160 mcore_asm_trampoline_template (FILE *f
)
3162 fprintf (f
, "\t.short 0x7102\n");
3163 fprintf (f
, "\t.short 0x7d02\n");
3164 fprintf (f
, "\t.short 0x00cd\n");
3165 fprintf (f
, "\t.short 0x1e00\n");
3166 fprintf (f
, "\t.long 0\n");
3167 fprintf (f
, "\t.long 0\n");
3170 /* Worker function for TARGET_TRAMPOLINE_INIT. */
3173 mcore_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
3175 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3178 emit_block_move (m_tramp
, assemble_trampoline_template (),
3179 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
3181 mem
= adjust_address (m_tramp
, SImode
, 8);
3182 emit_move_insn (mem
, chain_value
);
3183 mem
= adjust_address (m_tramp
, SImode
, 12);
3184 emit_move_insn (mem
, fnaddr
);
3187 /* Implement TARGET_LEGITIMATE_CONSTANT_P
3189 On the MCore, allow anything but a double. */
3192 mcore_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3194 return GET_CODE (x
) != CONST_DOUBLE
;
3197 /* Helper function for `mcore_legitimate_address_p'. */
3200 mcore_reg_ok_for_base_p (const_rtx reg
, bool strict_p
)
3203 return REGNO_OK_FOR_BASE_P (REGNO (reg
));
3205 return (REGNO (reg
) <= 16 || !HARD_REGISTER_P (reg
));
3209 mcore_base_register_rtx_p (const_rtx x
, bool strict_p
)
3211 return REG_P(x
) && mcore_reg_ok_for_base_p (x
, strict_p
);
3214 /* A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
3215 and for DI is 0..56 because we use two SI loads, etc. */
3218 mcore_legitimate_index_p (machine_mode mode
, const_rtx op
)
3220 if (CONST_INT_P (op
))
3222 if (GET_MODE_SIZE (mode
) >= 4
3223 && (((unsigned HOST_WIDE_INT
) INTVAL (op
)) % 4) == 0
3224 && ((unsigned HOST_WIDE_INT
) INTVAL (op
))
3225 <= (unsigned HOST_WIDE_INT
) 64 - GET_MODE_SIZE (mode
))
3227 if (GET_MODE_SIZE (mode
) == 2
3228 && (((unsigned HOST_WIDE_INT
) INTVAL (op
)) % 2) == 0
3229 && ((unsigned HOST_WIDE_INT
) INTVAL (op
)) <= 30)
3231 if (GET_MODE_SIZE (mode
) == 1
3232 && ((unsigned HOST_WIDE_INT
) INTVAL (op
)) <= 15)
3239 /* Worker function for TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P.
3245 mcore_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
,
3248 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
3250 if (mcore_base_register_rtx_p (x
, strict_p
))
3252 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == LO_SUM
)
3254 rtx xop0
= XEXP (x
, 0);
3255 rtx xop1
= XEXP (x
, 1);
3256 if (mcore_base_register_rtx_p (xop0
, strict_p
)
3257 && mcore_legitimate_index_p (mode
, xop1
))
3259 if (mcore_base_register_rtx_p (xop1
, strict_p
)
3260 && mcore_legitimate_index_p (mode
, xop0
))
3267 /* Implement TARGET_HARD_REGNO_MODE_OK. We may keep double values in
3271 mcore_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
3273 if (TARGET_8ALIGN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3274 return (regno
& 1) == 0;