1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008,
3 2009, 2010 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
42 #include "diagnostic-core.h"
44 #include "target-def.h"
47 /* For dumping information about frame sizes. */
48 char * mcore_current_function_name
= 0;
49 long mcore_current_compilation_timestamp
= 0;
51 /* Global variables for machine-dependent things. */
53 /* Provides the class number of the smallest class containing
55 const enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
57 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
58 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
59 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
60 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
61 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
66 int arg_size
; /* Stdarg spills (bytes). */
67 int reg_size
; /* Non-volatile reg saves (bytes). */
68 int reg_mask
; /* Non-volatile reg saves. */
69 int local_size
; /* Locals. */
70 int outbound_size
; /* Arg overflow on calls out. */
74 /* Describe the steps we'll use to grow it. */
75 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
76 int growth
[MAX_STACK_GROWS
];
94 static void output_stack_adjust (int, int);
95 static int calc_live_regs (int *);
96 static int try_constant_tricks (long, HOST_WIDE_INT
*, HOST_WIDE_INT
*);
97 static const char * output_inline_const (enum machine_mode
, rtx
*);
98 static void layout_mcore_frame (struct mcore_frame
*);
99 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
, tree
, int *, int);
100 static cond_type
is_cond_candidate (rtx
);
101 static rtx
emit_new_cond_insn (rtx
, int);
102 static rtx
conditionalize_block (rtx
);
103 static void conditionalize_optimization (void);
104 static void mcore_reorg (void);
105 static rtx
handle_structs_in_regs (enum machine_mode
, const_tree
, int);
106 static void mcore_mark_dllexport (tree
);
107 static void mcore_mark_dllimport (tree
);
108 static int mcore_dllexport_p (tree
);
109 static int mcore_dllimport_p (tree
);
110 static tree
mcore_handle_naked_attribute (tree
*, tree
, tree
, int, bool *);
111 #ifdef OBJECT_FORMAT_ELF
112 static void mcore_asm_named_section (const char *,
115 static void mcore_print_operand (FILE *, rtx
, int);
116 static void mcore_print_operand_address (FILE *, rtx
);
117 static bool mcore_print_operand_punct_valid_p (unsigned char code
);
118 static void mcore_unique_section (tree
, int);
119 static void mcore_encode_section_info (tree
, rtx
, int);
120 static const char *mcore_strip_name_encoding (const char *);
121 static int mcore_const_costs (rtx
, RTX_CODE
);
122 static int mcore_and_cost (rtx
);
123 static int mcore_ior_cost (rtx
);
124 static bool mcore_rtx_costs (rtx
, int, int, int *, bool);
125 static void mcore_external_libcall (rtx
);
126 static bool mcore_return_in_memory (const_tree
, const_tree
);
127 static int mcore_arg_partial_bytes (CUMULATIVE_ARGS
*,
130 static rtx
mcore_function_arg (CUMULATIVE_ARGS
*,
133 static void mcore_function_arg_advance (CUMULATIVE_ARGS
*,
136 static unsigned int mcore_function_arg_boundary (enum machine_mode
,
138 static void mcore_asm_trampoline_template (FILE *);
139 static void mcore_trampoline_init (rtx
, tree
, rtx
);
140 static void mcore_option_override (void);
142 /* MCore specific attributes. */
144 static const struct attribute_spec mcore_attribute_table
[] =
146 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
147 affects_type_identity } */
148 { "dllexport", 0, 0, true, false, false, NULL
, false },
149 { "dllimport", 0, 0, true, false, false, NULL
, false },
150 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
,
152 { NULL
, 0, 0, false, false, false, NULL
, false }
155 /* What options are we going to default to specific settings when
156 -O* happens; the user can subsequently override these settings.
158 Omitting the frame pointer is a very good idea on the MCore.
159 Scheduling isn't worth anything on the current MCore implementation. */
161 static const struct default_options mcore_option_optimization_table
[] =
163 { OPT_LEVELS_1_PLUS
, OPT_ffunction_cse
, NULL
, 0 },
164 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
165 { OPT_LEVELS_ALL
, OPT_fcaller_saves
, NULL
, 0 },
166 { OPT_LEVELS_ALL
, OPT_fschedule_insns
, NULL
, 0 },
167 { OPT_LEVELS_ALL
, OPT_fschedule_insns2
, NULL
, 0 },
168 { OPT_LEVELS_SIZE
, OPT_mhardlit
, NULL
, 0 },
169 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
172 /* Initialize the GCC target structure. */
173 #undef TARGET_ASM_EXTERNAL_LIBCALL
174 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
176 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
177 #undef TARGET_MERGE_DECL_ATTRIBUTES
178 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
181 #ifdef OBJECT_FORMAT_ELF
182 #undef TARGET_ASM_UNALIGNED_HI_OP
183 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
184 #undef TARGET_ASM_UNALIGNED_SI_OP
185 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
188 #undef TARGET_PRINT_OPERAND
189 #define TARGET_PRINT_OPERAND mcore_print_operand
190 #undef TARGET_PRINT_OPERAND_ADDRESS
191 #define TARGET_PRINT_OPERAND_ADDRESS mcore_print_operand_address
192 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
193 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mcore_print_operand_punct_valid_p
195 #undef TARGET_ATTRIBUTE_TABLE
196 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
197 #undef TARGET_ASM_UNIQUE_SECTION
198 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
199 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
200 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
201 #undef TARGET_DEFAULT_TARGET_FLAGS
202 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
203 #undef TARGET_ENCODE_SECTION_INFO
204 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
205 #undef TARGET_STRIP_NAME_ENCODING
206 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
207 #undef TARGET_RTX_COSTS
208 #define TARGET_RTX_COSTS mcore_rtx_costs
209 #undef TARGET_ADDRESS_COST
210 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
211 #undef TARGET_MACHINE_DEPENDENT_REORG
212 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
214 #undef TARGET_PROMOTE_FUNCTION_MODE
215 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
216 #undef TARGET_PROMOTE_PROTOTYPES
217 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
219 #undef TARGET_RETURN_IN_MEMORY
220 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
221 #undef TARGET_MUST_PASS_IN_STACK
222 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
223 #undef TARGET_PASS_BY_REFERENCE
224 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
225 #undef TARGET_ARG_PARTIAL_BYTES
226 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
227 #undef TARGET_FUNCTION_ARG
228 #define TARGET_FUNCTION_ARG mcore_function_arg
229 #undef TARGET_FUNCTION_ARG_ADVANCE
230 #define TARGET_FUNCTION_ARG_ADVANCE mcore_function_arg_advance
231 #undef TARGET_FUNCTION_ARG_BOUNDARY
232 #define TARGET_FUNCTION_ARG_BOUNDARY mcore_function_arg_boundary
234 #undef TARGET_SETUP_INCOMING_VARARGS
235 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
237 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
238 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mcore_asm_trampoline_template
239 #undef TARGET_TRAMPOLINE_INIT
240 #define TARGET_TRAMPOLINE_INIT mcore_trampoline_init
242 #undef TARGET_OPTION_OVERRIDE
243 #define TARGET_OPTION_OVERRIDE mcore_option_override
244 #undef TARGET_OPTION_OPTIMIZATION_TABLE
245 #define TARGET_OPTION_OPTIMIZATION_TABLE mcore_option_optimization_table
247 #undef TARGET_EXCEPT_UNWIND_INFO
248 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
250 struct gcc_target targetm
= TARGET_INITIALIZER
;
252 /* Adjust the stack and return the number of bytes taken to do it. */
254 output_stack_adjust (int direction
, int size
)
256 /* If extending stack a lot, we do it incrementally. */
257 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
259 rtx tmp
= gen_rtx_REG (SImode
, 1);
262 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
265 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
266 memref
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
267 MEM_VOLATILE_P (memref
) = 1;
268 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
269 size
-= mcore_stack_increment
;
271 while (size
> mcore_stack_increment
);
273 /* SIZE is now the residual for the last adjustment,
274 which doesn't require a probe. */
280 rtx val
= GEN_INT (size
);
284 rtx nval
= gen_rtx_REG (SImode
, 1);
285 emit_insn (gen_movsi (nval
, val
));
290 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
292 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
298 /* Work out the registers which need to be saved,
299 both as a mask and a count. */
302 calc_live_regs (int * count
)
305 int live_regs_mask
= 0;
309 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
311 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
314 live_regs_mask
|= (1 << reg
);
318 return live_regs_mask
;
321 /* Print the operand address in x to the stream. */
324 mcore_print_operand_address (FILE * stream
, rtx x
)
326 switch (GET_CODE (x
))
329 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
334 rtx base
= XEXP (x
, 0);
335 rtx index
= XEXP (x
, 1);
337 if (GET_CODE (base
) != REG
)
339 /* Ensure that BASE is a register (one of them must be). */
345 switch (GET_CODE (index
))
348 fprintf (stream
, "(%s," HOST_WIDE_INT_PRINT_DEC
")",
349 reg_names
[REGNO(base
)], INTVAL (index
));
360 output_addr_const (stream
, x
);
366 mcore_print_operand_punct_valid_p (unsigned char code
)
368 return (code
== '.' || code
== '#' || code
== '*' || code
== '^'
372 /* Print operand x (an rtx) in assembler syntax to file stream
373 according to modifier code.
375 'R' print the next register or memory location along, i.e. the lsw in
377 'O' print a constant without the #
378 'M' print a constant as its negative
379 'P' print log2 of a power of two
380 'Q' print log2 of an inverse of a power of two
381 'U' print register for ldm/stm instruction
382 'X' print byte number for xtrbN instruction. */
385 mcore_print_operand (FILE * stream
, rtx x
, int code
)
391 fprintf (asm_out_file
, "32");
393 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
396 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) & 0xffffffff));
399 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
402 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
405 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, - INTVAL (x
));
408 /* Next location along in memory or register. */
409 switch (GET_CODE (x
))
412 fputs (reg_names
[REGNO (x
) + 1], (stream
));
415 mcore_print_operand_address
416 (stream
, XEXP (adjust_address (x
, SImode
, 4), 0));
423 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
424 reg_names
[REGNO (x
) + 3]);
427 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
430 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, 3 - INTVAL (x
) / 8);
434 switch (GET_CODE (x
))
437 fputs (reg_names
[REGNO (x
)], (stream
));
440 output_address (XEXP (x
, 0));
443 output_addr_const (stream
, x
);
450 /* What does a constant cost ? */
453 mcore_const_costs (rtx exp
, enum rtx_code code
)
455 HOST_WIDE_INT val
= INTVAL (exp
);
457 /* Easy constants. */
458 if ( CONST_OK_FOR_I (val
)
459 || CONST_OK_FOR_M (val
)
460 || CONST_OK_FOR_N (val
)
461 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
464 && ( CONST_OK_FOR_M (~val
)
465 || CONST_OK_FOR_N (~val
)))
467 else if (code
== PLUS
468 && ( CONST_OK_FOR_I (-val
)
469 || CONST_OK_FOR_M (-val
)
470 || CONST_OK_FOR_N (-val
)))
476 /* What does an and instruction cost - we do this b/c immediates may
477 have been relaxed. We want to ensure that cse will cse relaxed immeds
478 out. Otherwise we'll get bad code (multiple reloads of the same const). */
481 mcore_and_cost (rtx x
)
485 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
488 val
= INTVAL (XEXP (x
, 1));
490 /* Do it directly. */
491 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
493 /* Takes one instruction to load. */
494 else if (const_ok_for_mcore (val
))
496 /* Takes two instructions to load. */
497 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
500 /* Takes a lrw to load. */
504 /* What does an or cost - see and_cost(). */
507 mcore_ior_cost (rtx x
)
511 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
514 val
= INTVAL (XEXP (x
, 1));
516 /* Do it directly with bclri. */
517 if (CONST_OK_FOR_M (val
))
519 /* Takes one instruction to load. */
520 else if (const_ok_for_mcore (val
))
522 /* Takes two instructions to load. */
523 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
526 /* Takes a lrw to load. */
531 mcore_rtx_costs (rtx x
, int code
, int outer_code
, int * total
,
532 bool speed ATTRIBUTE_UNUSED
)
537 *total
= mcore_const_costs (x
, (enum rtx_code
) outer_code
);
549 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
553 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
562 *total
= COSTS_N_INSNS (100);
570 /* Prepare the operands for a comparison. Return whether the branch/setcc
571 should reverse the operands. */
574 mcore_gen_compare (enum rtx_code code
, rtx op0
, rtx op1
)
576 rtx cc_reg
= gen_rtx_REG (CCmode
, CC_REG
);
579 if (GET_CODE (op1
) == CONST_INT
)
581 HOST_WIDE_INT val
= INTVAL (op1
);
586 /* Unsigned > 0 is the same as != 0; everything else is converted
587 below to LEU (reversed cmphs). */
592 /* Check whether (LE A imm) can become (LT A imm + 1),
593 or (GT A imm) can become (GE A imm + 1). */
596 if (CONST_OK_FOR_J (val
+ 1))
598 op1
= GEN_INT (val
+ 1);
599 code
= code
== LE
? LT
: GE
;
608 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
609 op1
= force_reg (SImode
, op1
);
611 /* cmpnei: 0-31 (K immediate)
612 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
616 case EQ
: /* Use inverted condition, cmpne. */
621 case NE
: /* Use normal condition, cmpne. */
622 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
623 op1
= force_reg (SImode
, op1
);
626 case LE
: /* Use inverted condition, reversed cmplt. */
631 case GT
: /* Use normal condition, reversed cmplt. */
632 if (GET_CODE (op1
) == CONST_INT
)
633 op1
= force_reg (SImode
, op1
);
636 case GE
: /* Use inverted condition, cmplt. */
641 case LT
: /* Use normal condition, cmplt. */
642 if (GET_CODE (op1
) == CONST_INT
&&
643 /* covered by btsti x,31. */
645 ! CONST_OK_FOR_J (INTVAL (op1
)))
646 op1
= force_reg (SImode
, op1
);
649 case GTU
: /* Use inverted condition, cmple. */
650 /* We coped with unsigned > 0 above. */
651 gcc_assert (GET_CODE (op1
) != CONST_INT
|| INTVAL (op1
) != 0);
656 case LEU
: /* Use normal condition, reversed cmphs. */
657 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
658 op1
= force_reg (SImode
, op1
);
661 case LTU
: /* Use inverted condition, cmphs. */
666 case GEU
: /* Use normal condition, cmphs. */
667 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
668 op1
= force_reg (SImode
, op1
);
675 emit_insn (gen_rtx_SET (VOIDmode
,
677 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
)));
682 mcore_symbolic_address_p (rtx x
)
684 switch (GET_CODE (x
))
691 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
692 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
693 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
699 /* Functions to output assembly code for a function call. */
702 mcore_output_call (rtx operands
[], int index
)
704 static char buffer
[20];
705 rtx addr
= operands
[index
];
711 gcc_assert (mcore_current_function_name
);
713 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
717 sprintf (buffer
, "jsr\t%%%d", index
);
723 gcc_assert (mcore_current_function_name
);
724 gcc_assert (GET_CODE (addr
) == SYMBOL_REF
);
726 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
730 sprintf (buffer
, "jbsr\t%%%d", index
);
736 /* Can we load a constant with a single instruction ? */
739 const_ok_for_mcore (HOST_WIDE_INT value
)
741 if (value
>= 0 && value
<= 127)
744 /* Try exact power of two. */
745 if (CONST_OK_FOR_M (value
))
748 /* Try exact power of two - 1. */
749 if (CONST_OK_FOR_N (value
) && value
!= -1)
755 /* Can we load a constant inline with up to 2 instructions ? */
758 mcore_const_ok_for_inline (HOST_WIDE_INT value
)
762 return try_constant_tricks (value
, & x
, & y
) > 0;
765 /* Are we loading the constant using a not ? */
768 mcore_const_trick_uses_not (HOST_WIDE_INT value
)
772 return try_constant_tricks (value
, & x
, & y
) == 2;
775 /* Try tricks to load a constant inline and return the trick number if
776 success (0 is non-inlinable).
779 1: single instruction (do the usual thing)
780 2: single insn followed by a 'not'
781 3: single insn followed by a subi
782 4: single insn followed by an addi
783 5: single insn followed by rsubi
784 6: single insn followed by bseti
785 7: single insn followed by bclri
786 8: single insn followed by rotli
787 9: single insn followed by lsli
788 10: single insn followed by ixh
789 11: single insn followed by ixw. */
792 try_constant_tricks (HOST_WIDE_INT value
, HOST_WIDE_INT
* x
, HOST_WIDE_INT
* y
)
795 unsigned HOST_WIDE_INT bit
, shf
, rot
;
797 if (const_ok_for_mcore (value
))
798 return 1; /* Do the usual thing. */
800 if (! TARGET_HARDLIT
)
803 if (const_ok_for_mcore (~value
))
809 for (i
= 1; i
<= 32; i
++)
811 if (const_ok_for_mcore (value
- i
))
819 if (const_ok_for_mcore (value
+ i
))
830 for (i
= 0; i
<= 31; i
++)
832 if (const_ok_for_mcore (i
- value
))
840 if (const_ok_for_mcore (value
& ~bit
))
847 if (const_ok_for_mcore (value
| bit
))
861 for (i
= 1; i
< 31; i
++)
865 /* MCore has rotate left. */
869 rot
|= c
; /* Simulate rotate. */
871 if (const_ok_for_mcore (rot
))
880 shf
= 0; /* Can't use logical shift, low order bit is one. */
884 if (shf
!= 0 && const_ok_for_mcore (shf
))
893 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
900 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
910 /* Check whether reg is dead at first. This is done by searching ahead
911 for either the next use (i.e., reg is live), a death note, or a set of
912 reg. Don't just use dead_or_set_p() since reload does not always mark
913 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
914 can ignore subregs by extracting the actual register. BRC */
917 mcore_is_dead (rtx first
, rtx reg
)
921 /* For mcore, subregs can't live independently of their parent regs. */
922 if (GET_CODE (reg
) == SUBREG
)
923 reg
= SUBREG_REG (reg
);
925 /* Dies immediately. */
926 if (dead_or_set_p (first
, reg
))
929 /* Look for conclusive evidence of live/death, otherwise we have
930 to assume that it is live. */
931 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
933 if (GET_CODE (insn
) == JUMP_INSN
)
934 return 0; /* We lose track, assume it is alive. */
936 else if (GET_CODE(insn
) == CALL_INSN
)
938 /* Call's might use it for target or register parms. */
939 if (reg_referenced_p (reg
, PATTERN (insn
))
940 || find_reg_fusage (insn
, USE
, reg
))
942 else if (dead_or_set_p (insn
, reg
))
945 else if (GET_CODE (insn
) == INSN
)
947 if (reg_referenced_p (reg
, PATTERN (insn
)))
949 else if (dead_or_set_p (insn
, reg
))
954 /* No conclusive evidence either way, we cannot take the chance
955 that control flow hid the use from us -- "I'm not dead yet". */
959 /* Count the number of ones in mask. */
962 mcore_num_ones (HOST_WIDE_INT mask
)
964 /* A trick to count set bits recently posted on comp.compilers. */
965 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
966 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
967 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
968 mask
= ((mask
>> 8) + mask
);
970 return (mask
+ (mask
>> 16)) & 0xff;
973 /* Count the number of zeros in mask. */
976 mcore_num_zeros (HOST_WIDE_INT mask
)
978 return 32 - mcore_num_ones (mask
);
981 /* Determine byte being masked. */
984 mcore_byte_offset (unsigned int mask
)
986 if (mask
== 0x00ffffffL
)
988 else if (mask
== 0xff00ffffL
)
990 else if (mask
== 0xffff00ffL
)
992 else if (mask
== 0xffffff00L
)
998 /* Determine halfword being masked. */
1001 mcore_halfword_offset (unsigned int mask
)
1003 if (mask
== 0x0000ffffL
)
1005 else if (mask
== 0xffff0000L
)
1011 /* Output a series of bseti's corresponding to mask. */
1014 mcore_output_bseti (rtx dst
, int mask
)
1016 rtx out_operands
[2];
1019 out_operands
[0] = dst
;
1021 for (bit
= 0; bit
< 32; bit
++)
1023 if ((mask
& 0x1) == 0x1)
1025 out_operands
[1] = GEN_INT (bit
);
1027 output_asm_insn ("bseti\t%0,%1", out_operands
);
1035 /* Output a series of bclri's corresponding to mask. */
1038 mcore_output_bclri (rtx dst
, int mask
)
1040 rtx out_operands
[2];
1043 out_operands
[0] = dst
;
1045 for (bit
= 0; bit
< 32; bit
++)
1047 if ((mask
& 0x1) == 0x0)
1049 out_operands
[1] = GEN_INT (bit
);
1051 output_asm_insn ("bclri\t%0,%1", out_operands
);
1060 /* Output a conditional move of two constants that are +/- 1 within each
1061 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1062 really worth the effort. */
1065 mcore_output_cmov (rtx operands
[], int cmp_t
, const char * test
)
1067 HOST_WIDE_INT load_value
;
1068 HOST_WIDE_INT adjust_value
;
1069 rtx out_operands
[4];
1071 out_operands
[0] = operands
[0];
1073 /* Check to see which constant is loadable. */
1074 if (const_ok_for_mcore (INTVAL (operands
[1])))
1076 out_operands
[1] = operands
[1];
1077 out_operands
[2] = operands
[2];
1079 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1081 out_operands
[1] = operands
[2];
1082 out_operands
[2] = operands
[1];
1084 /* Complement test since constants are swapped. */
1085 cmp_t
= (cmp_t
== 0);
1087 load_value
= INTVAL (out_operands
[1]);
1088 adjust_value
= INTVAL (out_operands
[2]);
1090 /* First output the test if folded into the pattern. */
1093 output_asm_insn (test
, operands
);
1095 /* Load the constant - for now, only support constants that can be
1096 generated with a single instruction. maybe add general inlinable
1097 constants later (this will increase the # of patterns since the
1098 instruction sequence has a different length attribute). */
1099 if (load_value
>= 0 && load_value
<= 127)
1100 output_asm_insn ("movi\t%0,%1", out_operands
);
1101 else if (CONST_OK_FOR_M (load_value
))
1102 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1103 else if (CONST_OK_FOR_N (load_value
))
1104 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1106 /* Output the constant adjustment. */
1107 if (load_value
> adjust_value
)
1110 output_asm_insn ("decf\t%0", out_operands
);
1112 output_asm_insn ("dect\t%0", out_operands
);
1117 output_asm_insn ("incf\t%0", out_operands
);
1119 output_asm_insn ("inct\t%0", out_operands
);
1125 /* Outputs the peephole for moving a constant that gets not'ed followed
1126 by an and (i.e. combine the not and the and into andn). BRC */
1129 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
1132 rtx out_operands
[3];
1133 const char * load_op
;
1137 trick_no
= try_constant_tricks (INTVAL (operands
[1]), &x
, &y
);
1138 gcc_assert (trick_no
== 2);
1140 out_operands
[0] = operands
[0];
1141 out_operands
[1] = GEN_INT (x
);
1142 out_operands
[2] = operands
[2];
1144 if (x
>= 0 && x
<= 127)
1145 load_op
= "movi\t%0,%1";
1147 /* Try exact power of two. */
1148 else if (CONST_OK_FOR_M (x
))
1149 load_op
= "bgeni\t%0,%P1";
1151 /* Try exact power of two - 1. */
1152 else if (CONST_OK_FOR_N (x
))
1153 load_op
= "bmaski\t%0,%N1";
1157 load_op
= "BADMOVI-andn\t%0, %1";
1161 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1162 output_asm_insn (buf
, out_operands
);
1167 /* Output an inline constant. */
1170 output_inline_const (enum machine_mode mode
, rtx operands
[])
1172 HOST_WIDE_INT x
= 0, y
= 0;
1174 rtx out_operands
[3];
1177 const char *dst_fmt
;
1178 HOST_WIDE_INT value
;
1180 value
= INTVAL (operands
[1]);
1182 trick_no
= try_constant_tricks (value
, &x
, &y
);
1183 /* lrw's are handled separately: Large inlinable constants never get
1184 turned into lrw's. Our caller uses try_constant_tricks to back
1185 off to an lrw rather than calling this routine. */
1186 gcc_assert (trick_no
!= 0);
1191 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1192 out_operands
[0] = operands
[0];
1193 out_operands
[1] = GEN_INT (x
);
1196 out_operands
[2] = GEN_INT (y
);
1198 /* Select dst format based on mode. */
1199 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1204 if (x
>= 0 && x
<= 127)
1205 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1207 /* Try exact power of two. */
1208 else if (CONST_OK_FOR_M (x
))
1209 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1211 /* Try exact power of two - 1. */
1212 else if (CONST_OK_FOR_N (x
))
1213 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1217 sprintf (load_op
, "BADMOVI-inline_const %s, %%1", dst_fmt
);
1224 strcpy (buf
, load_op
);
1227 sprintf (buf
, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1230 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1233 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1236 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1237 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1240 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1243 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1246 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1249 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1252 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1255 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1261 output_asm_insn (buf
, out_operands
);
1266 /* Output a move of a word or less value. */
1269 mcore_output_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
1270 enum machine_mode mode ATTRIBUTE_UNUSED
)
1272 rtx dst
= operands
[0];
1273 rtx src
= operands
[1];
1275 if (GET_CODE (dst
) == REG
)
1277 if (GET_CODE (src
) == REG
)
1279 if (REGNO (src
) == CC_REG
) /* r-c */
1282 return "mov\t%0,%1"; /* r-r*/
1284 else if (GET_CODE (src
) == MEM
)
1286 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1287 return "lrw\t%0,[%1]"; /* a-R */
1289 switch (GET_MODE (src
)) /* r-m */
1292 return "ldw\t%0,%1";
1294 return "ld.h\t%0,%1";
1296 return "ld.b\t%0,%1";
1301 else if (GET_CODE (src
) == CONST_INT
)
1305 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1306 return "movi\t%0,%1";
1307 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1308 return "bgeni\t%0,%P1\t// %1 %x1";
1309 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1310 return "bmaski\t%0,%N1\t// %1 %x1";
1311 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1312 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1314 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1317 return "lrw\t%0, %1"; /* Into the literal pool. */
1319 else if (GET_CODE (dst
) == MEM
) /* m-r */
1320 switch (GET_MODE (dst
))
1323 return "stw\t%1,%0";
1325 return "st.h\t%1,%0";
1327 return "st.b\t%1,%0";
1335 /* Return a sequence of instructions to perform DI or DF move.
1336 Since the MCORE cannot move a DI or DF in one instruction, we have
1337 to take care when we see overlapping source and dest registers. */
1340 mcore_output_movedouble (rtx operands
[], enum machine_mode mode ATTRIBUTE_UNUSED
)
1342 rtx dst
= operands
[0];
1343 rtx src
= operands
[1];
1345 if (GET_CODE (dst
) == REG
)
1347 if (GET_CODE (src
) == REG
)
1349 int dstreg
= REGNO (dst
);
1350 int srcreg
= REGNO (src
);
1352 /* Ensure the second source not overwritten. */
1353 if (srcreg
+ 1 == dstreg
)
1354 return "mov %R0,%R1\n\tmov %0,%1";
1356 return "mov %0,%1\n\tmov %R0,%R1";
1358 else if (GET_CODE (src
) == MEM
)
1360 rtx memexp
= memexp
= XEXP (src
, 0);
1361 int dstreg
= REGNO (dst
);
1364 if (GET_CODE (memexp
) == LABEL_REF
)
1365 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1366 else if (GET_CODE (memexp
) == REG
)
1367 basereg
= REGNO (memexp
);
1368 else if (GET_CODE (memexp
) == PLUS
)
1370 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1371 basereg
= REGNO (XEXP (memexp
, 0));
1372 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1373 basereg
= REGNO (XEXP (memexp
, 1));
1380 /* ??? length attribute is wrong here. */
1381 if (dstreg
== basereg
)
1383 /* Just load them in reverse order. */
1384 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1386 /* XXX: alternative: move basereg to basereg+1
1387 and then fall through. */
1390 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1392 else if (GET_CODE (src
) == CONST_INT
)
1394 if (TARGET_LITTLE_END
)
1396 if (CONST_OK_FOR_I (INTVAL (src
)))
1397 output_asm_insn ("movi %0,%1", operands
);
1398 else if (CONST_OK_FOR_M (INTVAL (src
)))
1399 output_asm_insn ("bgeni %0,%P1", operands
);
1400 else if (CONST_OK_FOR_N (INTVAL (src
)))
1401 output_asm_insn ("bmaski %0,%N1", operands
);
1405 if (INTVAL (src
) < 0)
1406 return "bmaski %R0,32";
1408 return "movi %R0,0";
1412 if (CONST_OK_FOR_I (INTVAL (src
)))
1413 output_asm_insn ("movi %R0,%1", operands
);
1414 else if (CONST_OK_FOR_M (INTVAL (src
)))
1415 output_asm_insn ("bgeni %R0,%P1", operands
);
1416 else if (CONST_OK_FOR_N (INTVAL (src
)))
1417 output_asm_insn ("bmaski %R0,%N1", operands
);
1421 if (INTVAL (src
) < 0)
1422 return "bmaski %0,32";
1430 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1431 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1436 /* Predicates used by the templates. */
1439 mcore_arith_S_operand (rtx op
)
1441 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1447 /* Expand insert bit field. BRC */
1450 mcore_expand_insv (rtx operands
[])
1452 int width
= INTVAL (operands
[1]);
1453 int posn
= INTVAL (operands
[2]);
1455 rtx mreg
, sreg
, ereg
;
1457 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1458 for width==1 must be removed. Look around line 368. This is something
1459 we really want the md part to do. */
1460 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1462 /* Do directly with bseti or bclri. */
1463 /* RBE: 2/97 consider only low bit of constant. */
1464 if ((INTVAL (operands
[3]) & 1) == 0)
1466 mask
= ~(1 << posn
);
1467 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1468 gen_rtx_AND (SImode
, operands
[0], GEN_INT (mask
))));
1473 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1474 gen_rtx_IOR (SImode
, operands
[0], GEN_INT (mask
))));
1480 /* Look at some bit-field placements that we aren't interested
1481 in handling ourselves, unless specifically directed to do so. */
1482 if (! TARGET_W_FIELD
)
1483 return 0; /* Generally, give up about now. */
1485 if (width
== 8 && posn
% 8 == 0)
1486 /* Byte sized and aligned; let caller break it up. */
1489 if (width
== 16 && posn
% 16 == 0)
1490 /* Short sized and aligned; let caller break it up. */
1493 /* The general case - we can do this a little bit better than what the
1494 machine independent part tries. This will get rid of all the subregs
1495 that mess up constant folding in combine when working with relaxed
1498 /* If setting the entire field, do it directly. */
1499 if (GET_CODE (operands
[3]) == CONST_INT
1500 && INTVAL (operands
[3]) == ((1 << width
) - 1))
1502 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1503 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1504 gen_rtx_IOR (SImode
, operands
[0], mreg
)));
1508 /* Generate the clear mask. */
1509 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1511 /* Clear the field, to overlay it later with the source. */
1512 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1513 gen_rtx_AND (SImode
, operands
[0], mreg
)));
1515 /* If the source is constant 0, we've nothing to add back. */
1516 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1519 /* XXX: Should we worry about more games with constant values?
1520 We've covered the high profile: set/clear single-bit and many-bit
1521 fields. How often do we see "arbitrary bit pattern" constants? */
1522 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1524 /* Extract src as same width as dst (needed for signed values). We
1525 always have to do this since we widen everything to SImode.
1526 We don't have to mask if we're shifting this up against the
1527 MSB of the register (e.g., the shift will push out any hi-order
1529 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1531 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1532 emit_insn (gen_rtx_SET (SImode
, sreg
,
1533 gen_rtx_AND (SImode
, sreg
, ereg
)));
1536 /* Insert source value in dest. */
1538 emit_insn (gen_rtx_SET (SImode
, sreg
,
1539 gen_rtx_ASHIFT (SImode
, sreg
, GEN_INT (posn
))));
1541 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1542 gen_rtx_IOR (SImode
, operands
[0], sreg
)));
1547 /* ??? Block move stuff stolen from m88k. This code has not been
1548 verified for correctness. */
1550 /* Emit code to perform a block move. Choose the best method.
1552 OPERANDS[0] is the destination.
1553 OPERANDS[1] is the source.
1554 OPERANDS[2] is the size.
1555 OPERANDS[3] is the alignment safe to use. */
1557 /* Emit code to perform a block move with an offset sequence of ldw/st
1558 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1559 known constants. DEST and SRC are registers. OFFSET is the known
1560 starting point for the output pattern. */
1562 static const enum machine_mode mode_from_align
[] =
1564 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1568 block_move_sequence (rtx dst_mem
, rtx src_mem
, int size
, int align
)
1571 enum machine_mode mode
[2];
1580 x
= XEXP (dst_mem
, 0);
1583 x
= force_reg (Pmode
, x
);
1584 dst_mem
= replace_equiv_address (dst_mem
, x
);
1587 x
= XEXP (src_mem
, 0);
1590 x
= force_reg (Pmode
, x
);
1591 src_mem
= replace_equiv_address (src_mem
, x
);
1594 active
[0] = active
[1] = false;
1605 next_amount
= (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
1606 next_amount
= MIN (next_amount
, align
);
1608 amount
[next
] = next_amount
;
1609 mode
[next
] = mode_from_align
[next_amount
];
1610 temp
[next
] = gen_reg_rtx (mode
[next
]);
1612 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1613 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1615 offset_ld
+= next_amount
;
1616 size
-= next_amount
;
1617 active
[next
] = true;
1622 active
[phase
] = false;
1624 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1625 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1627 offset_st
+= amount
[phase
];
1630 while (active
[next
]);
1634 mcore_expand_block_move (rtx
*operands
)
1636 HOST_WIDE_INT align
, bytes
, max
;
1638 if (GET_CODE (operands
[2]) != CONST_INT
)
1641 bytes
= INTVAL (operands
[2]);
1642 align
= INTVAL (operands
[3]);
1671 block_move_sequence (operands
[0], operands
[1], bytes
, align
);
1679 /* Code to generate prologue and epilogue sequences. */
1680 static int number_of_regs_before_varargs
;
1682 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1683 for a varargs function. */
1684 static int current_function_anonymous_args
;
1686 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1687 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1688 #define ADDI_REACH (32) /* Maximum addi operand. */
1691 layout_mcore_frame (struct mcore_frame
* infp
)
1699 unsigned int growths
;
1702 /* Might have to spill bytes to re-assemble a big argument that
1703 was passed partially in registers and partially on the stack. */
1704 nbytes
= crtl
->args
.pretend_args_size
;
1706 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1707 if (current_function_anonymous_args
)
1708 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
1710 infp
->arg_size
= nbytes
;
1712 /* How much space to save non-volatile registers we stomp. */
1713 infp
->reg_mask
= calc_live_regs (& n
);
1714 infp
->reg_size
= n
* 4;
1716 /* And the rest of it... locals and space for overflowed outbounds. */
1717 infp
->local_size
= get_frame_size ();
1718 infp
->outbound_size
= crtl
->outgoing_args_size
;
1720 /* Make sure we have a whole number of words for the locals. */
1721 if (infp
->local_size
% STACK_BYTES
)
1722 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
1724 /* Only thing we know we have to pad is the outbound space, since
1725 we've aligned our locals assuming that base of locals is aligned. */
1726 infp
->pad_local
= 0;
1728 infp
->pad_outbound
= 0;
1729 if (infp
->outbound_size
% STACK_BYTES
)
1730 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
1732 /* Now we see how we want to stage the prologue so that it does
1733 the most appropriate stack growth and register saves to either:
1735 (2) reduce instruction space, or
1736 (3) reduce stack space. */
1737 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
1738 infp
->growth
[i
] = 0;
1740 regarg
= infp
->reg_size
+ infp
->arg_size
;
1741 localregarg
= infp
->local_size
+ regarg
;
1742 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
1745 /* XXX: Consider one where we consider localregarg + outbound too! */
1747 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1748 use stw's with offsets and buy the frame in one shot. */
1749 if (localregarg
<= ADDI_REACH
1750 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1752 /* Make sure we'll be aligned. */
1753 if (localregarg
% STACK_BYTES
)
1754 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1756 step
= localregarg
+ infp
->pad_reg
;
1757 infp
->reg_offset
= infp
->local_size
;
1759 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
1762 infp
->reg_offset
+= outbounds
;
1766 infp
->arg_offset
= step
- 4;
1767 infp
->growth
[growths
++] = step
;
1768 infp
->reg_growth
= growths
;
1769 infp
->local_growth
= growths
;
1771 /* If we haven't already folded it in. */
1773 infp
->growth
[growths
++] = outbounds
;
1778 /* Frame can't be done with a single subi, but can be done with 2
1779 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1780 shift some of the stack purchase into the first subi, so both are
1781 single instructions. */
1782 if (localregarg
<= STORE_REACH
1783 && (infp
->local_size
> ADDI_REACH
)
1784 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1788 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1789 if (localregarg
% STACK_BYTES
)
1790 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1792 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
1793 step
= ADDI_REACH
; /* As much up front as we can. */
1797 /* XXX: Consider whether step will still be aligned; we believe so. */
1798 infp
->arg_offset
= step
- 4;
1799 infp
->growth
[growths
++] = step
;
1800 infp
->reg_growth
= growths
;
1801 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
1804 /* Can we fold in any space required for outbounds? */
1805 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
1811 /* Get the rest of the locals in place. */
1813 infp
->growth
[growths
++] = step
;
1814 infp
->local_growth
= growths
;
1817 gcc_assert (all
== 0);
1819 /* Finish off if we need to do so. */
1821 infp
->growth
[growths
++] = outbounds
;
1826 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1827 Then we buy the rest of the frame in 1 or 2 steps depending on
1828 whether we need a frame pointer. */
1829 if ((regarg
% STACK_BYTES
) == 0)
1831 infp
->growth
[growths
++] = regarg
;
1832 infp
->reg_growth
= growths
;
1833 infp
->arg_offset
= regarg
- 4;
1834 infp
->reg_offset
= 0;
1836 if (infp
->local_size
% STACK_BYTES
)
1837 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1839 step
= infp
->local_size
+ infp
->pad_local
;
1841 if (!frame_pointer_needed
)
1847 infp
->growth
[growths
++] = step
;
1848 infp
->local_growth
= growths
;
1850 /* If there's any left to be done. */
1852 infp
->growth
[growths
++] = outbounds
;
1857 /* XXX: optimizations that we'll want to play with....
1858 -- regarg is not aligned, but it's a small number of registers;
1859 use some of localsize so that regarg is aligned and then
1860 save the registers. */
1862 /* Simple encoding; plods down the stack buying the pieces as it goes.
1863 -- does not optimize space consumption.
1864 -- does not attempt to optimize instruction counts.
1865 -- but it is safe for all alignments. */
1866 if (regarg
% STACK_BYTES
!= 0)
1867 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
1869 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
1870 infp
->reg_growth
= growths
;
1871 infp
->arg_offset
= infp
->growth
[0] - 4;
1872 infp
->reg_offset
= 0;
1874 if (frame_pointer_needed
)
1876 if (infp
->local_size
% STACK_BYTES
!= 0)
1877 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1879 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
1880 infp
->local_growth
= growths
;
1882 infp
->growth
[growths
++] = outbounds
;
1886 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
1887 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
1889 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
1890 infp
->local_growth
= growths
;
1893 /* Anything else that we've forgotten?, plus a few consistency checks. */
1895 gcc_assert (infp
->reg_offset
>= 0);
1896 gcc_assert (growths
<= MAX_STACK_GROWS
);
1898 for (i
= 0; i
< growths
; i
++)
1899 gcc_assert (!(infp
->growth
[i
] % STACK_BYTES
));
1902 /* Define the offset between two registers, one to be eliminated, and
1903 the other its replacement, at the start of a routine. */
1906 mcore_initial_elimination_offset (int from
, int to
)
1910 struct mcore_frame fi
;
1912 layout_mcore_frame (& fi
);
1915 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
1917 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
1919 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1922 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1923 return above_frame
+ below_frame
;
1925 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1931 /* Keep track of some information about varargs for the prolog. */
1934 mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*args_so_far
,
1935 enum machine_mode mode
, tree type
,
1936 int * ptr_pretend_size ATTRIBUTE_UNUSED
,
1937 int second_time ATTRIBUTE_UNUSED
)
1939 current_function_anonymous_args
= 1;
1941 /* We need to know how many argument registers are used before
1942 the varargs start, so that we can push the remaining argument
1943 registers during the prologue. */
1944 number_of_regs_before_varargs
= *args_so_far
+ mcore_num_arg_regs (mode
, type
);
1946 /* There is a bug somewhere in the arg handling code.
1947 Until I can find it this workaround always pushes the
1948 last named argument onto the stack. */
1949 number_of_regs_before_varargs
= *args_so_far
;
1951 /* The last named argument may be split between argument registers
1952 and the stack. Allow for this here. */
1953 if (number_of_regs_before_varargs
> NPARM_REGS
)
1954 number_of_regs_before_varargs
= NPARM_REGS
;
1958 mcore_expand_prolog (void)
1960 struct mcore_frame fi
;
1961 int space_allocated
= 0;
1964 /* Find out what we're doing. */
1965 layout_mcore_frame (&fi
);
1967 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
1968 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
1972 /* Emit a symbol for this routine's frame size. */
1975 x
= DECL_RTL (current_function_decl
);
1977 gcc_assert (GET_CODE (x
) == MEM
);
1981 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1983 free (mcore_current_function_name
);
1985 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
1987 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
1989 if (cfun
->calls_alloca
)
1990 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
1993 We're looking at how the 8byte alignment affects stack layout
1994 and where we had to pad things. This emits information we can
1995 extract which tells us about frame sizes and the like. */
1996 fprintf (asm_out_file
,
1997 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
1998 mcore_current_function_name
,
1999 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
2000 fi
.local_size
, fi
.outbound_size
,
2001 frame_pointer_needed
);
2004 if (mcore_naked_function_p ())
2007 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2008 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2010 /* If we have a parameter passed partially in regs and partially in memory,
2011 the registers will have been stored to memory already in function.c. So
2012 we only need to do something here for varargs functions. */
2013 if (fi
.arg_size
!= 0 && crtl
->args
.pretend_args_size
== 0)
2016 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
2017 int remaining
= fi
.arg_size
;
2019 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
2021 emit_insn (gen_movsi
2022 (gen_rtx_MEM (SImode
,
2023 plus_constant (stack_pointer_rtx
, offset
)),
2024 gen_rtx_REG (SImode
, rn
)));
2028 /* Do we need another stack adjustment before we do the register saves? */
2029 if (growth
< fi
.reg_growth
)
2030 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2032 if (fi
.reg_size
!= 0)
2035 int offs
= fi
.reg_offset
;
2037 for (i
= 15; i
>= 0; i
--)
2039 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2043 while (fi
.reg_mask
& (1 << first_reg
))
2047 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2048 gen_rtx_REG (SImode
, first_reg
),
2049 GEN_INT (16 - first_reg
)));
2051 i
-= (15 - first_reg
);
2052 offs
+= (16 - first_reg
) * 4;
2054 else if (fi
.reg_mask
& (1 << i
))
2056 emit_insn (gen_movsi
2057 (gen_rtx_MEM (SImode
,
2058 plus_constant (stack_pointer_rtx
, offs
)),
2059 gen_rtx_REG (SImode
, i
)));
2065 /* Figure the locals + outbounds. */
2066 if (frame_pointer_needed
)
2068 /* If we haven't already purchased to 'fp'. */
2069 if (growth
< fi
.local_growth
)
2070 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2072 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2074 /* ... and then go any remaining distance for outbounds, etc. */
2075 if (fi
.growth
[growth
])
2076 output_stack_adjust (-1, fi
.growth
[growth
++]);
2080 if (growth
< fi
.local_growth
)
2081 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2082 if (fi
.growth
[growth
])
2083 output_stack_adjust (-1, fi
.growth
[growth
++]);
2088 mcore_expand_epilog (void)
2090 struct mcore_frame fi
;
2093 int growth
= MAX_STACK_GROWS
- 1 ;
2096 /* Find out what we're doing. */
2097 layout_mcore_frame(&fi
);
2099 if (mcore_naked_function_p ())
2102 /* If we had a frame pointer, restore the sp from that. */
2103 if (frame_pointer_needed
)
2105 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2106 growth
= fi
.local_growth
- 1;
2110 /* XXX: while loop should accumulate and do a single sell. */
2111 while (growth
>= fi
.local_growth
)
2113 if (fi
.growth
[growth
] != 0)
2114 output_stack_adjust (1, fi
.growth
[growth
]);
2119 /* Make sure we've shrunk stack back to the point where the registers
2120 were laid down. This is typically 0/1 iterations. Then pull the
2121 register save information back off the stack. */
2122 while (growth
>= fi
.reg_growth
)
2123 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2125 offs
= fi
.reg_offset
;
2127 for (i
= 15; i
>= 0; i
--)
2129 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2133 /* Find the starting register. */
2136 while (fi
.reg_mask
& (1 << first_reg
))
2141 emit_insn (gen_load_multiple (gen_rtx_REG (SImode
, first_reg
),
2142 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2143 GEN_INT (16 - first_reg
)));
2145 i
-= (15 - first_reg
);
2146 offs
+= (16 - first_reg
) * 4;
2148 else if (fi
.reg_mask
& (1 << i
))
2150 emit_insn (gen_movsi
2151 (gen_rtx_REG (SImode
, i
),
2152 gen_rtx_MEM (SImode
,
2153 plus_constant (stack_pointer_rtx
, offs
))));
2158 /* Give back anything else. */
2159 /* XXX: Should accumulate total and then give it back. */
2161 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2164 /* This code is borrowed from the SH port. */
2166 /* The MCORE cannot load a large constant into a register, constants have to
2167 come from a pc relative load. The reference of a pc relative load
2168 instruction must be less than 1k in front of the instruction. This
2169 means that we often have to dump a constant inside a function, and
2170 generate code to branch around it.
2172 It is important to minimize this, since the branches will slow things
2173 down and make things bigger.
2175 Worst case code looks like:
2191 We fix this by performing a scan before scheduling, which notices which
2192 instructions need to have their operands fetched from the constant table
2193 and builds the table.
2197 scan, find an instruction which needs a pcrel move. Look forward, find the
2198 last barrier which is within MAX_COUNT bytes of the requirement.
2199 If there isn't one, make one. Process all the instructions between
2200 the find and the barrier.
2202 In the above example, we can tell that L3 is within 1k of L1, so
2203 the first move can be shrunk from the 2 insn+constant sequence into
2204 just 1 insn, and the constant moved to L3 to make:
2214 Then the second move becomes the target for the shortening process. */
2218 rtx value
; /* Value in table. */
2219 rtx label
; /* Label of value. */
2222 /* The maximum number of constants that can fit into one pool, since
2223 the pc relative range is 0...1020 bytes and constants are at least 4
2224 bytes long. We subtract 4 from the range to allow for the case where
2225 we need to add a branch/align before the constant pool. */
2227 #define MAX_COUNT 1016
2228 #define MAX_POOL_SIZE (MAX_COUNT/4)
2229 static pool_node pool_vector
[MAX_POOL_SIZE
];
2230 static int pool_size
;
2232 /* Dump out any constants accumulated in the final pass. These
2233 will only be labels. */
2236 mcore_output_jump_label_table (void)
2242 fprintf (asm_out_file
, "\t.align 2\n");
2244 for (i
= 0; i
< pool_size
; i
++)
2246 pool_node
* p
= pool_vector
+ i
;
2248 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2250 output_asm_insn (".long %0", &p
->value
);
2259 /* Check whether insn is a candidate for a conditional. */
2262 is_cond_candidate (rtx insn
)
2264 /* The only things we conditionalize are those that can be directly
2265 changed into a conditional. Only bother with SImode items. If
2266 we wanted to be a little more aggressive, we could also do other
2267 modes such as DImode with reg-reg move or load 0. */
2268 if (GET_CODE (insn
) == INSN
)
2270 rtx pat
= PATTERN (insn
);
2273 if (GET_CODE (pat
) != SET
)
2276 dst
= XEXP (pat
, 0);
2278 if ((GET_CODE (dst
) != REG
&&
2279 GET_CODE (dst
) != SUBREG
) ||
2280 GET_MODE (dst
) != SImode
)
2283 src
= XEXP (pat
, 1);
2285 if ((GET_CODE (src
) == REG
||
2286 (GET_CODE (src
) == SUBREG
&&
2287 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2288 GET_MODE (src
) == SImode
)
2289 return COND_MOV_INSN
;
2290 else if (GET_CODE (src
) == CONST_INT
&&
2292 return COND_CLR_INSN
;
2293 else if (GET_CODE (src
) == PLUS
&&
2294 (GET_CODE (XEXP (src
, 0)) == REG
||
2295 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2296 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2297 GET_MODE (XEXP (src
, 0)) == SImode
&&
2298 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2299 INTVAL (XEXP (src
, 1)) == 1)
2300 return COND_INC_INSN
;
2301 else if (((GET_CODE (src
) == MINUS
&&
2302 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2303 INTVAL( XEXP (src
, 1)) == 1) ||
2304 (GET_CODE (src
) == PLUS
&&
2305 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2306 INTVAL (XEXP (src
, 1)) == -1)) &&
2307 (GET_CODE (XEXP (src
, 0)) == REG
||
2308 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2309 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2310 GET_MODE (XEXP (src
, 0)) == SImode
)
2311 return COND_DEC_INSN
;
2313 /* Some insns that we don't bother with:
2314 (set (rx:DI) (ry:DI))
2315 (set (rx:DI) (const_int 0))
2319 else if (GET_CODE (insn
) == JUMP_INSN
&&
2320 GET_CODE (PATTERN (insn
)) == SET
&&
2321 GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2322 return COND_BRANCH_INSN
;
2327 /* Emit a conditional version of insn and replace the old insn with the
2328 new one. Return the new insn if emitted. */
2331 emit_new_cond_insn (rtx insn
, int cond
)
2337 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2340 pat
= PATTERN (insn
);
2342 if (GET_CODE (insn
) == INSN
)
2344 dst
= SET_DEST (pat
);
2345 src
= SET_SRC (pat
);
2349 dst
= JUMP_LABEL (insn
);
2358 c_insn
= gen_movt0 (dst
, src
, dst
);
2360 c_insn
= gen_movt0 (dst
, dst
, src
);
2365 c_insn
= gen_incscc (dst
, dst
);
2367 c_insn
= gen_incscc_false (dst
, dst
);
2372 c_insn
= gen_decscc (dst
, dst
);
2374 c_insn
= gen_decscc_false (dst
, dst
);
2377 case COND_BRANCH_INSN
:
2379 c_insn
= gen_branch_true (dst
);
2381 c_insn
= gen_branch_false (dst
);
2388 /* Only copy the notes if they exist. */
2389 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2391 /* We really don't need to bother with the notes and links at this
2392 point, but go ahead and save the notes. This will help is_dead()
2393 when applying peepholes (links don't matter since they are not
2394 used any more beyond this point for the mcore). */
2395 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2398 if (num
== COND_BRANCH_INSN
)
2400 /* For jumps, we need to be a little bit careful and emit the new jump
2401 before the old one and to update the use count for the target label.
2402 This way, the barrier following the old (uncond) jump will get
2403 deleted, but the label won't. */
2404 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2406 ++ LABEL_NUSES (dst
);
2408 JUMP_LABEL (c_insn
) = dst
;
2411 c_insn
= emit_insn_after (c_insn
, insn
);
2418 /* Attempt to change a basic block into a series of conditional insns. This
2419 works by taking the branch at the end of the 1st block and scanning for the
2420 end of the 2nd block. If all instructions in the 2nd block have cond.
2421 versions and the label at the start of block 3 is the same as the target
2422 from the branch at block 1, then conditionalize all insn in block 2 using
2423 the inverse condition of the branch at block 1. (Note I'm bending the
2424 definition of basic block here.)
2428 bt L2 <-- end of block 1 (delete)
2431 br L3 <-- end of block 2
2433 L2: ... <-- start of block 3 (NUSES==1)
2444 we can delete the L2 label if NUSES==1 and re-apply the optimization
2445 starting at the last instruction of block 2. This may allow an entire
2446 if-then-else statement to be conditionalized. BRC */
2448 conditionalize_block (rtx first
)
2452 rtx end_blk_1_br
= 0;
2453 rtx end_blk_2_insn
= 0;
2454 rtx start_blk_3_lab
= 0;
2460 /* Check that the first insn is a candidate conditional jump. This is
2461 the one that we'll eliminate. If not, advance to the next insn to
2463 if (GET_CODE (first
) != JUMP_INSN
||
2464 GET_CODE (PATTERN (first
)) != SET
||
2465 GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2466 return NEXT_INSN (first
);
2468 /* Extract some information we need. */
2469 end_blk_1_br
= first
;
2470 br_pat
= PATTERN (end_blk_1_br
);
2472 /* Complement the condition since we use the reverse cond. for the insns. */
2473 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2475 /* Determine what kind of branch we have. */
2476 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2478 /* A normal branch, so extract label out of first arm. */
2479 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2483 /* An inverse branch, so extract the label out of the 2nd arm
2484 and complement the condition. */
2486 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2489 /* Scan forward for the start of block 2: it must start with a
2490 label and that label must be the same as the branch target
2491 label from block 1. We don't care about whether block 2 actually
2492 ends with a branch or a label (an uncond. branch is
2493 conditionalizable). */
2494 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2498 code
= GET_CODE (insn
);
2500 /* Look for the label at the start of block 3. */
2501 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2504 /* Skip barriers, notes, and conditionalizable insns. If the
2505 insn is not conditionalizable or makes this optimization fail,
2506 just return the next insn so we can start over from that point. */
2507 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2508 return NEXT_INSN (insn
);
2510 /* Remember the last real insn before the label (i.e. end of block 2). */
2511 if (code
== JUMP_INSN
|| code
== INSN
)
2514 end_blk_2_insn
= insn
;
2521 /* It is possible for this optimization to slow performance if the blocks
2522 are long. This really depends upon whether the branch is likely taken
2523 or not. If the branch is taken, we slow performance in many cases. But,
2524 if the branch is not taken, we always help performance (for a single
2525 block, but for a double block (i.e. when the optimization is re-applied)
2526 this is not true since the 'right thing' depends on the overall length of
2527 the collapsed block). As a compromise, don't apply this optimization on
2528 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2529 the best threshold depends on the latencies of the instructions (i.e.,
2530 the branch penalty). */
2531 if (optimize
> 1 && blk_size
> 2)
2534 /* At this point, we've found the start of block 3 and we know that
2535 it is the destination of the branch from block 1. Also, all
2536 instructions in the block 2 are conditionalizable. So, apply the
2537 conditionalization and delete the branch. */
2538 start_blk_3_lab
= insn
;
2540 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2541 insn
= NEXT_INSN (insn
))
2545 if (INSN_DELETED_P (insn
))
2548 /* Try to form a conditional variant of the instruction and emit it. */
2549 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2551 if (end_blk_2_insn
== insn
)
2552 end_blk_2_insn
= newinsn
;
2558 /* Note whether we will delete the label starting blk 3 when the jump
2559 gets deleted. If so, we want to re-apply this optimization at the
2560 last real instruction right before the label. */
2561 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2563 start_blk_3_lab
= 0;
2566 /* ??? we probably should redistribute the death notes for this insn, esp.
2567 the death of cc, but it doesn't really matter this late in the game.
2568 The peepholes all use is_dead() which will find the correct death
2569 regardless of whether there is a note. */
2570 delete_insn (end_blk_1_br
);
2572 if (! start_blk_3_lab
)
2573 return end_blk_2_insn
;
2575 /* Return the insn right after the label at the start of block 3. */
2576 return NEXT_INSN (start_blk_3_lab
);
2579 /* Apply the conditionalization of blocks optimization. This is the
2580 outer loop that traverses through the insns scanning for a branch
2581 that signifies an opportunity to apply the optimization. Note that
2582 this optimization is applied late. If we could apply it earlier,
2583 say before cse 2, it may expose more optimization opportunities.
2584 but, the pay back probably isn't really worth the effort (we'd have
2585 to update all reg/flow/notes/links/etc to make it work - and stick it
2586 in before cse 2). */
2589 conditionalize_optimization (void)
2593 for (insn
= get_insns (); insn
; insn
= conditionalize_block (insn
))
2597 static int saved_warn_return_type
= -1;
2598 static int saved_warn_return_type_count
= 0;
2600 /* This is to handle loads from the constant pool. */
2605 /* Reset this variable. */
2606 current_function_anonymous_args
= 0;
2608 /* Restore the warn_return_type if it has been altered. */
2609 if (saved_warn_return_type
!= -1)
2611 /* Only restore the value if we have reached another function.
2612 The test of warn_return_type occurs in final_function () in
2613 c-decl.c a long time after the code for the function is generated,
2614 so we need a counter to tell us when we have finished parsing that
2615 function and can restore the flag. */
2616 if (--saved_warn_return_type_count
== 0)
2618 warn_return_type
= saved_warn_return_type
;
2619 saved_warn_return_type
= -1;
2626 /* Conditionalize blocks where we can. */
2627 conditionalize_optimization ();
2629 /* Literal pool generation is now pushed off until the assembler. */
2633 /* Return true if X is something that can be moved directly into r15. */
2636 mcore_r15_operand_p (rtx x
)
2638 switch (GET_CODE (x
))
2641 return mcore_const_ok_for_inline (INTVAL (x
));
2653 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't
2654 directly move X into it, use r1-r14 as a temporary. */
2657 mcore_secondary_reload_class (enum reg_class rclass
,
2658 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2660 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], 15)
2661 && !mcore_r15_operand_p (x
))
2666 /* Return the reg_class to use when reloading the rtx X into the class
2667 RCLASS. If X is too complex to move directly into r15, prefer to
2668 use LRW_REGS instead. */
2671 mcore_reload_class (rtx x
, enum reg_class rclass
)
2673 if (reg_class_subset_p (LRW_REGS
, rclass
) && !mcore_r15_operand_p (x
))
2679 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2680 register. Note that the current version doesn't worry about whether
2681 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2682 in r2 matches an SImode in r2. Might think in the future about whether
2683 we want to be able to say something about modes. */
2686 mcore_is_same_reg (rtx x
, rtx y
)
2688 /* Strip any and all of the subreg wrappers. */
2689 while (GET_CODE (x
) == SUBREG
)
2692 while (GET_CODE (y
) == SUBREG
)
2695 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
2702 mcore_option_override (void)
2704 /* Only the m340 supports little endian code. */
2705 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
2706 target_flags
|= MASK_M340
;
2710 /* Compute the number of word sized registers needed to
2711 hold a function argument of mode MODE and type TYPE. */
2714 mcore_num_arg_regs (enum machine_mode mode
, const_tree type
)
2718 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2721 if (type
&& mode
== BLKmode
)
2722 size
= int_size_in_bytes (type
);
2724 size
= GET_MODE_SIZE (mode
);
2726 return ROUND_ADVANCE (size
);
2730 handle_structs_in_regs (enum machine_mode mode
, const_tree type
, int reg
)
2734 /* The MCore ABI defines that a structure whose size is not a whole multiple
2735 of bytes is passed packed into registers (or spilled onto the stack if
2736 not enough registers are available) with the last few bytes of the
2737 structure being packed, left-justified, into the last register/stack slot.
2738 GCC handles this correctly if the last word is in a stack slot, but we
2739 have to generate a special, PARALLEL RTX if the last word is in an
2740 argument register. */
2742 && TYPE_MODE (type
) == BLKmode
2743 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
2744 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
2745 && (size
% UNITS_PER_WORD
!= 0)
2746 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
2748 rtx arg_regs
[NPARM_REGS
];
2753 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
2756 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
2757 GEN_INT (nregs
* UNITS_PER_WORD
));
2761 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2762 gcc_assert (ARRAY_SIZE (arg_regs
) == 6);
2763 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
2764 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
2766 result
= gen_rtx_PARALLEL (mode
, rtvec
);
2770 return gen_rtx_REG (mode
, reg
);
2774 mcore_function_value (const_tree valtype
, const_tree func
)
2776 enum machine_mode mode
;
2779 mode
= TYPE_MODE (valtype
);
2781 /* Since we promote return types, we must promote the mode here too. */
2782 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
2784 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
2787 /* Define where to put the arguments to a function.
2788 Value is zero to push the argument on the stack,
2789 or a hard register in which to store the argument.
2791 MODE is the argument's machine mode.
2792 TYPE is the data type of the argument (as a tree).
2793 This is null for libcalls where that information may
2795 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2796 the preceding args and about the function being called.
2797 NAMED is nonzero if this argument is a named parameter
2798 (otherwise it is an extra parameter matching an ellipsis).
2800 On MCore the first args are normally in registers
2801 and the rest are pushed. Any arg that starts within the first
2802 NPARM_REGS words is at least partially passed in a register unless
2803 its data type forbids. */
2806 mcore_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2807 const_tree type
, bool named
)
2811 if (! named
|| mode
== VOIDmode
)
2814 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2817 arg_reg
= ROUND_REG (*cum
, mode
);
2819 if (arg_reg
< NPARM_REGS
)
2820 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
2826 mcore_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2827 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2829 *cum
= (ROUND_REG (*cum
, mode
)
2830 + (int)named
* mcore_num_arg_regs (mode
, type
));
2834 mcore_function_arg_boundary (enum machine_mode mode
,
2835 const_tree type ATTRIBUTE_UNUSED
)
2837 /* Doubles must be aligned to an 8 byte boundary. */
2838 return (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) == 8
2843 /* Returns the number of bytes of argument registers required to hold *part*
2844 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2845 the type is not known). If the argument fits entirely in the argument
2846 registers, or entirely on the stack, then 0 is returned. CUM is the
2847 number of argument registers already used by earlier parameters to
2851 mcore_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2852 tree type
, bool named
)
2854 int reg
= ROUND_REG (*cum
, mode
);
2859 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2862 /* REG is not the *hardware* register number of the register that holds
2863 the argument, it is the *argument* register number. So for example,
2864 the first argument to a function goes in argument register 0, which
2865 translates (for the MCore) into hardware register 2. The second
2866 argument goes into argument register 1, which translates into hardware
2867 register 3, and so on. NPARM_REGS is the number of argument registers
2868 supported by the target, not the maximum hardware register number of
2870 if (reg
>= NPARM_REGS
)
2873 /* If the argument fits entirely in registers, return 0. */
2874 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
2877 /* The argument overflows the number of available argument registers.
2878 Compute how many argument registers have not yet been assigned to
2879 hold an argument. */
2880 reg
= NPARM_REGS
- reg
;
2882 /* Return partially in registers and partially on the stack. */
2883 return reg
* UNITS_PER_WORD
;
2886 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2889 mcore_dllexport_name_p (const char * symbol
)
2891 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
2894 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2897 mcore_dllimport_name_p (const char * symbol
)
2899 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
2902 /* Mark a DECL as being dllexport'd. */
2905 mcore_mark_dllexport (tree decl
)
2907 const char * oldname
;
2912 rtlname
= XEXP (DECL_RTL (decl
), 0);
2914 if (GET_CODE (rtlname
) == MEM
)
2915 rtlname
= XEXP (rtlname
, 0);
2916 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2917 oldname
= XSTR (rtlname
, 0);
2919 if (mcore_dllexport_name_p (oldname
))
2920 return; /* Already done. */
2922 newname
= XALLOCAVEC (char, strlen (oldname
) + 4);
2923 sprintf (newname
, "@e.%s", oldname
);
2925 /* We pass newname through get_identifier to ensure it has a unique
2926 address. RTL processing can sometimes peek inside the symbol ref
2927 and compare the string's addresses to see if two symbols are
2929 /* ??? At least I think that's why we do this. */
2930 idp
= get_identifier (newname
);
2932 XEXP (DECL_RTL (decl
), 0) =
2933 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2936 /* Mark a DECL as being dllimport'd. */
2939 mcore_mark_dllimport (tree decl
)
2941 const char * oldname
;
2947 rtlname
= XEXP (DECL_RTL (decl
), 0);
2949 if (GET_CODE (rtlname
) == MEM
)
2950 rtlname
= XEXP (rtlname
, 0);
2951 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2952 oldname
= XSTR (rtlname
, 0);
2954 gcc_assert (!mcore_dllexport_name_p (oldname
));
2955 if (mcore_dllimport_name_p (oldname
))
2956 return; /* Already done. */
2958 /* ??? One can well ask why we're making these checks here,
2959 and that would be a good question. */
2961 /* Imported variables can't be initialized. */
2962 if (TREE_CODE (decl
) == VAR_DECL
2963 && !DECL_VIRTUAL_P (decl
)
2964 && DECL_INITIAL (decl
))
2966 error ("initialized variable %q+D is marked dllimport", decl
);
2970 /* `extern' needn't be specified with dllimport.
2971 Specify `extern' now and hope for the best. Sigh. */
2972 if (TREE_CODE (decl
) == VAR_DECL
2973 /* ??? Is this test for vtables needed? */
2974 && !DECL_VIRTUAL_P (decl
))
2976 DECL_EXTERNAL (decl
) = 1;
2977 TREE_PUBLIC (decl
) = 1;
2980 newname
= XALLOCAVEC (char, strlen (oldname
) + 11);
2981 sprintf (newname
, "@i.__imp_%s", oldname
);
2983 /* We pass newname through get_identifier to ensure it has a unique
2984 address. RTL processing can sometimes peek inside the symbol ref
2985 and compare the string's addresses to see if two symbols are
2987 /* ??? At least I think that's why we do this. */
2988 idp
= get_identifier (newname
);
2990 newrtl
= gen_rtx_MEM (Pmode
,
2991 gen_rtx_SYMBOL_REF (Pmode
,
2992 IDENTIFIER_POINTER (idp
)));
2993 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2997 mcore_dllexport_p (tree decl
)
2999 if ( TREE_CODE (decl
) != VAR_DECL
3000 && TREE_CODE (decl
) != FUNCTION_DECL
)
3003 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
3007 mcore_dllimport_p (tree decl
)
3009 if ( TREE_CODE (decl
) != VAR_DECL
3010 && TREE_CODE (decl
) != FUNCTION_DECL
)
3013 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
3016 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3017 install some info in the .drective (PE) or .exports (ELF) sections. */
3020 mcore_encode_section_info (tree decl
, rtx rtl ATTRIBUTE_UNUSED
, int first ATTRIBUTE_UNUSED
)
3022 /* Mark the decl so we can tell from the rtl whether the object is
3023 dllexport'd or dllimport'd. */
3024 if (mcore_dllexport_p (decl
))
3025 mcore_mark_dllexport (decl
);
3026 else if (mcore_dllimport_p (decl
))
3027 mcore_mark_dllimport (decl
);
3029 /* It might be that DECL has already been marked as dllimport, but
3030 a subsequent definition nullified that. The attribute is gone
3031 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3032 else if ((TREE_CODE (decl
) == FUNCTION_DECL
3033 || TREE_CODE (decl
) == VAR_DECL
)
3034 && DECL_RTL (decl
) != NULL_RTX
3035 && GET_CODE (DECL_RTL (decl
)) == MEM
3036 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
3037 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
3038 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
3040 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
3041 tree idp
= get_identifier (oldname
+ 9);
3042 rtx newrtl
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
3044 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3046 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3047 ??? We leave these alone for now. */
3051 /* Undo the effects of the above. */
3054 mcore_strip_name_encoding (const char * str
)
3056 return str
+ (str
[0] == '@' ? 3 : 0);
3059 /* MCore specific attribute support.
3060 dllexport - for exporting a function/variable that will live in a dll
3061 dllimport - for importing a function/variable from a dll
3062 naked - do not create a function prologue/epilogue. */
3064 /* Handle a "naked" attribute; arguments as in
3065 struct attribute_spec.handler. */
3068 mcore_handle_naked_attribute (tree
* node
, tree name
, tree args ATTRIBUTE_UNUSED
,
3069 int flags ATTRIBUTE_UNUSED
, bool * no_add_attrs
)
3071 if (TREE_CODE (*node
) == FUNCTION_DECL
)
3073 /* PR14310 - don't complain about lack of return statement
3074 in naked functions. The solution here is a gross hack
3075 but this is the only way to solve the problem without
3076 adding a new feature to GCC. I did try submitting a patch
3077 that would add such a new feature, but it was (rightfully)
3078 rejected on the grounds that it was creeping featurism,
3079 so hence this code. */
3080 if (warn_return_type
)
3082 saved_warn_return_type
= warn_return_type
;
3083 warn_return_type
= 0;
3084 saved_warn_return_type_count
= 2;
3086 else if (saved_warn_return_type_count
)
3087 saved_warn_return_type_count
= 2;
3091 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3093 *no_add_attrs
= true;
3099 /* ??? It looks like this is PE specific? Oh well, this is what the
3100 old code did as well. */
3103 mcore_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
3108 const char * prefix
;
3110 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3112 /* Strip off any encoding in name. */
3113 name
= (* targetm
.strip_name_encoding
) (name
);
3115 /* The object is put in, for example, section .text$foo.
3116 The linker will then ultimately place them in .text
3117 (everything from the $ on is stripped). */
3118 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3120 /* For compatibility with EPOC, we ignore the fact that the
3121 section might have relocs against it. */
3122 else if (decl_readonly_section (decl
, 0))
3127 len
= strlen (name
) + strlen (prefix
);
3128 string
= XALLOCAVEC (char, len
+ 1);
3130 sprintf (string
, "%s%s", prefix
, name
);
3132 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
3136 mcore_naked_function_p (void)
3138 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3141 #ifdef OBJECT_FORMAT_ELF
3143 mcore_asm_named_section (const char *name
,
3144 unsigned int flags ATTRIBUTE_UNUSED
,
3145 tree decl ATTRIBUTE_UNUSED
)
3147 fprintf (asm_out_file
, "\t.section %s\n", name
);
3149 #endif /* OBJECT_FORMAT_ELF */
3151 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3154 mcore_external_libcall (rtx fun
)
3156 fprintf (asm_out_file
, "\t.import\t");
3157 assemble_name (asm_out_file
, XSTR (fun
, 0));
3158 fprintf (asm_out_file
, "\n");
3161 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3164 mcore_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3166 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
3167 return (size
== -1 || size
> 2 * UNITS_PER_WORD
);
3170 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE.
3171 Output assembler code for a block containing the constant parts
3172 of a trampoline, leaving space for the variable parts.
3174 On the MCore, the trampoline looks like:
3182 mcore_asm_trampoline_template (FILE *f
)
3184 fprintf (f
, "\t.short 0x7102\n");
3185 fprintf (f
, "\t.short 0x7d02\n");
3186 fprintf (f
, "\t.short 0x00cd\n");
3187 fprintf (f
, "\t.short 0x1e00\n");
3188 fprintf (f
, "\t.long 0\n");
3189 fprintf (f
, "\t.long 0\n");
3192 /* Worker function for TARGET_TRAMPOLINE_INIT. */
3195 mcore_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
3197 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3200 emit_block_move (m_tramp
, assemble_trampoline_template (),
3201 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
3203 mem
= adjust_address (m_tramp
, SImode
, 8);
3204 emit_move_insn (mem
, chain_value
);
3205 mem
= adjust_address (m_tramp
, SImode
, 12);
3206 emit_move_insn (mem
, fnaddr
);