1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008,
3 2009 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
45 #include "target-def.h"
48 /* Maximum size we are allowed to grow the stack in a single operation.
49 If we want more, we must do it in increments of at most this size.
50 If this value is 0, we don't check at all. */
51 int mcore_stack_increment
= STACK_UNITS_MAXSTEP
;
53 /* For dumping information about frame sizes. */
54 char * mcore_current_function_name
= 0;
55 long mcore_current_compilation_timestamp
= 0;
57 /* Global variables for machine-dependent things. */
59 /* Provides the class number of the smallest class containing
61 const enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
63 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
64 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
65 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
66 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
67 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
70 /* Provide reg_class from a letter such as appears in the machine
72 const enum reg_class reg_class_from_letter
[] =
74 /* a */ LRW_REGS
, /* b */ ONLYR1_REGS
, /* c */ C_REGS
, /* d */ NO_REGS
,
75 /* e */ NO_REGS
, /* f */ NO_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
76 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ NO_REGS
, /* l */ NO_REGS
,
77 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
78 /* q */ NO_REGS
, /* r */ GENERAL_REGS
, /* s */ NO_REGS
, /* t */ NO_REGS
,
79 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ NO_REGS
, /* x */ ALL_REGS
,
80 /* y */ NO_REGS
, /* z */ NO_REGS
85 int arg_size
; /* Stdarg spills (bytes). */
86 int reg_size
; /* Non-volatile reg saves (bytes). */
87 int reg_mask
; /* Non-volatile reg saves. */
88 int local_size
; /* Locals. */
89 int outbound_size
; /* Arg overflow on calls out. */
93 /* Describe the steps we'll use to grow it. */
94 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
95 int growth
[MAX_STACK_GROWS
];
113 static void output_stack_adjust (int, int);
114 static int calc_live_regs (int *);
115 static int try_constant_tricks (long, HOST_WIDE_INT
*, HOST_WIDE_INT
*);
116 static const char * output_inline_const (enum machine_mode
, rtx
*);
117 static void layout_mcore_frame (struct mcore_frame
*);
118 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
, tree
, int *, int);
119 static cond_type
is_cond_candidate (rtx
);
120 static rtx
emit_new_cond_insn (rtx
, int);
121 static rtx
conditionalize_block (rtx
);
122 static void conditionalize_optimization (void);
123 static void mcore_reorg (void);
124 static rtx
handle_structs_in_regs (enum machine_mode
, const_tree
, int);
125 static void mcore_mark_dllexport (tree
);
126 static void mcore_mark_dllimport (tree
);
127 static int mcore_dllexport_p (tree
);
128 static int mcore_dllimport_p (tree
);
129 static tree
mcore_handle_naked_attribute (tree
*, tree
, tree
, int, bool *);
130 #ifdef OBJECT_FORMAT_ELF
131 static void mcore_asm_named_section (const char *,
134 static void mcore_print_operand (FILE *, rtx
, int);
135 static void mcore_print_operand_address (FILE *, rtx
);
136 static bool mcore_print_operand_punct_valid_p (unsigned char code
);
137 static void mcore_unique_section (tree
, int);
138 static void mcore_encode_section_info (tree
, rtx
, int);
139 static const char *mcore_strip_name_encoding (const char *);
140 static int mcore_const_costs (rtx
, RTX_CODE
);
141 static int mcore_and_cost (rtx
);
142 static int mcore_ior_cost (rtx
);
143 static bool mcore_rtx_costs (rtx
, int, int, int *, bool);
144 static void mcore_external_libcall (rtx
);
145 static bool mcore_return_in_memory (const_tree
, const_tree
);
146 static int mcore_arg_partial_bytes (CUMULATIVE_ARGS
*,
149 static void mcore_asm_trampoline_template (FILE *);
150 static void mcore_trampoline_init (rtx
, tree
, rtx
);
152 /* MCore specific attributes. */
154 static const struct attribute_spec mcore_attribute_table
[] =
156 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
157 { "dllexport", 0, 0, true, false, false, NULL
},
158 { "dllimport", 0, 0, true, false, false, NULL
},
159 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
},
160 { NULL
, 0, 0, false, false, false, NULL
}
163 /* Initialize the GCC target structure. */
164 #undef TARGET_ASM_EXTERNAL_LIBCALL
165 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
167 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
168 #undef TARGET_MERGE_DECL_ATTRIBUTES
169 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
172 #ifdef OBJECT_FORMAT_ELF
173 #undef TARGET_ASM_UNALIGNED_HI_OP
174 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
175 #undef TARGET_ASM_UNALIGNED_SI_OP
176 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
179 #undef TARGET_PRINT_OPERAND
180 #define TARGET_PRINT_OPERAND mcore_print_operand
181 #undef TARGET_PRINT_OPERAND_ADDRESS
182 #define TARGET_PRINT_OPERAND_ADDRESS mcore_print_operand_address
183 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
184 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mcore_print_operand_punct_valid_p
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
188 #undef TARGET_ASM_UNIQUE_SECTION
189 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
190 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
191 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
192 #undef TARGET_DEFAULT_TARGET_FLAGS
193 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
194 #undef TARGET_ENCODE_SECTION_INFO
195 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
196 #undef TARGET_STRIP_NAME_ENCODING
197 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
198 #undef TARGET_RTX_COSTS
199 #define TARGET_RTX_COSTS mcore_rtx_costs
200 #undef TARGET_ADDRESS_COST
201 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
202 #undef TARGET_MACHINE_DEPENDENT_REORG
203 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
205 #undef TARGET_PROMOTE_FUNCTION_MODE
206 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
207 #undef TARGET_PROMOTE_PROTOTYPES
208 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
210 #undef TARGET_RETURN_IN_MEMORY
211 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
212 #undef TARGET_MUST_PASS_IN_STACK
213 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
214 #undef TARGET_PASS_BY_REFERENCE
215 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
216 #undef TARGET_ARG_PARTIAL_BYTES
217 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
219 #undef TARGET_SETUP_INCOMING_VARARGS
220 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
222 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
223 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mcore_asm_trampoline_template
224 #undef TARGET_TRAMPOLINE_INIT
225 #define TARGET_TRAMPOLINE_INIT mcore_trampoline_init
227 struct gcc_target targetm
= TARGET_INITIALIZER
;
229 /* Adjust the stack and return the number of bytes taken to do it. */
231 output_stack_adjust (int direction
, int size
)
233 /* If extending stack a lot, we do it incrementally. */
234 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
236 rtx tmp
= gen_rtx_REG (SImode
, 1);
239 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
242 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
243 memref
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
244 MEM_VOLATILE_P (memref
) = 1;
245 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
246 size
-= mcore_stack_increment
;
248 while (size
> mcore_stack_increment
);
250 /* SIZE is now the residual for the last adjustment,
251 which doesn't require a probe. */
257 rtx val
= GEN_INT (size
);
261 rtx nval
= gen_rtx_REG (SImode
, 1);
262 emit_insn (gen_movsi (nval
, val
));
267 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
269 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
275 /* Work out the registers which need to be saved,
276 both as a mask and a count. */
279 calc_live_regs (int * count
)
282 int live_regs_mask
= 0;
286 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
288 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
291 live_regs_mask
|= (1 << reg
);
295 return live_regs_mask
;
298 /* Print the operand address in x to the stream. */
301 mcore_print_operand_address (FILE * stream
, rtx x
)
303 switch (GET_CODE (x
))
306 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
311 rtx base
= XEXP (x
, 0);
312 rtx index
= XEXP (x
, 1);
314 if (GET_CODE (base
) != REG
)
316 /* Ensure that BASE is a register (one of them must be). */
322 switch (GET_CODE (index
))
325 fprintf (stream
, "(%s," HOST_WIDE_INT_PRINT_DEC
")",
326 reg_names
[REGNO(base
)], INTVAL (index
));
337 output_addr_const (stream
, x
);
343 mcore_print_operand_punct_valid_p (unsigned char code
)
345 return (code
== '.' || code
== '#' || code
== '*' || code
== '^'
349 /* Print operand x (an rtx) in assembler syntax to file stream
350 according to modifier code.
352 'R' print the next register or memory location along, i.e. the lsw in
354 'O' print a constant without the #
355 'M' print a constant as its negative
356 'P' print log2 of a power of two
357 'Q' print log2 of an inverse of a power of two
358 'U' print register for ldm/stm instruction
359 'X' print byte number for xtrbN instruction. */
362 mcore_print_operand (FILE * stream
, rtx x
, int code
)
368 fprintf (asm_out_file
, "32");
370 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
373 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) & 0xffffffff));
376 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
379 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
382 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, - INTVAL (x
));
385 /* Next location along in memory or register. */
386 switch (GET_CODE (x
))
389 fputs (reg_names
[REGNO (x
) + 1], (stream
));
392 mcore_print_operand_address
393 (stream
, XEXP (adjust_address (x
, SImode
, 4), 0));
400 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
401 reg_names
[REGNO (x
) + 3]);
404 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
407 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, 3 - INTVAL (x
) / 8);
411 switch (GET_CODE (x
))
414 fputs (reg_names
[REGNO (x
)], (stream
));
417 output_address (XEXP (x
, 0));
420 output_addr_const (stream
, x
);
427 /* What does a constant cost ? */
430 mcore_const_costs (rtx exp
, enum rtx_code code
)
432 HOST_WIDE_INT val
= INTVAL (exp
);
434 /* Easy constants. */
435 if ( CONST_OK_FOR_I (val
)
436 || CONST_OK_FOR_M (val
)
437 || CONST_OK_FOR_N (val
)
438 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
441 && ( CONST_OK_FOR_M (~val
)
442 || CONST_OK_FOR_N (~val
)))
444 else if (code
== PLUS
445 && ( CONST_OK_FOR_I (-val
)
446 || CONST_OK_FOR_M (-val
)
447 || CONST_OK_FOR_N (-val
)))
453 /* What does an and instruction cost - we do this b/c immediates may
454 have been relaxed. We want to ensure that cse will cse relaxed immeds
455 out. Otherwise we'll get bad code (multiple reloads of the same const). */
458 mcore_and_cost (rtx x
)
462 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
465 val
= INTVAL (XEXP (x
, 1));
467 /* Do it directly. */
468 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
470 /* Takes one instruction to load. */
471 else if (const_ok_for_mcore (val
))
473 /* Takes two instructions to load. */
474 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
477 /* Takes a lrw to load. */
481 /* What does an or cost - see and_cost(). */
484 mcore_ior_cost (rtx x
)
488 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
491 val
= INTVAL (XEXP (x
, 1));
493 /* Do it directly with bclri. */
494 if (CONST_OK_FOR_M (val
))
496 /* Takes one instruction to load. */
497 else if (const_ok_for_mcore (val
))
499 /* Takes two instructions to load. */
500 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
503 /* Takes a lrw to load. */
508 mcore_rtx_costs (rtx x
, int code
, int outer_code
, int * total
,
509 bool speed ATTRIBUTE_UNUSED
)
514 *total
= mcore_const_costs (x
, (enum rtx_code
) outer_code
);
526 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
530 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
539 *total
= COSTS_N_INSNS (100);
547 /* Prepare the operands for a comparison. Return whether the branch/setcc
548 should reverse the operands. */
551 mcore_gen_compare (enum rtx_code code
, rtx op0
, rtx op1
)
553 rtx cc_reg
= gen_rtx_REG (CCmode
, CC_REG
);
556 if (GET_CODE (op1
) == CONST_INT
)
558 HOST_WIDE_INT val
= INTVAL (op1
);
563 /* Unsigned > 0 is the same as != 0; everything else is converted
564 below to LEU (reversed cmphs). */
569 /* Check whether (LE A imm) can become (LT A imm + 1),
570 or (GT A imm) can become (GE A imm + 1). */
573 if (CONST_OK_FOR_J (val
+ 1))
575 op1
= GEN_INT (val
+ 1);
576 code
= code
== LE
? LT
: GE
;
585 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
586 op1
= force_reg (SImode
, op1
);
588 /* cmpnei: 0-31 (K immediate)
589 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
593 case EQ
: /* Use inverted condition, cmpne. */
598 case NE
: /* Use normal condition, cmpne. */
599 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
600 op1
= force_reg (SImode
, op1
);
603 case LE
: /* Use inverted condition, reversed cmplt. */
608 case GT
: /* Use normal condition, reversed cmplt. */
609 if (GET_CODE (op1
) == CONST_INT
)
610 op1
= force_reg (SImode
, op1
);
613 case GE
: /* Use inverted condition, cmplt. */
618 case LT
: /* Use normal condition, cmplt. */
619 if (GET_CODE (op1
) == CONST_INT
&&
620 /* covered by btsti x,31. */
622 ! CONST_OK_FOR_J (INTVAL (op1
)))
623 op1
= force_reg (SImode
, op1
);
626 case GTU
: /* Use inverted condition, cmple. */
627 /* We coped with unsigned > 0 above. */
628 gcc_assert (GET_CODE (op1
) != CONST_INT
|| INTVAL (op1
) != 0);
633 case LEU
: /* Use normal condition, reversed cmphs. */
634 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
635 op1
= force_reg (SImode
, op1
);
638 case LTU
: /* Use inverted condition, cmphs. */
643 case GEU
: /* Use normal condition, cmphs. */
644 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
645 op1
= force_reg (SImode
, op1
);
652 emit_insn (gen_rtx_SET (VOIDmode
,
654 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
)));
659 mcore_symbolic_address_p (rtx x
)
661 switch (GET_CODE (x
))
668 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
669 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
670 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
676 /* Functions to output assembly code for a function call. */
679 mcore_output_call (rtx operands
[], int index
)
681 static char buffer
[20];
682 rtx addr
= operands
[index
];
688 gcc_assert (mcore_current_function_name
);
690 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
694 sprintf (buffer
, "jsr\t%%%d", index
);
700 gcc_assert (mcore_current_function_name
);
701 gcc_assert (GET_CODE (addr
) == SYMBOL_REF
);
703 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
707 sprintf (buffer
, "jbsr\t%%%d", index
);
713 /* Can we load a constant with a single instruction ? */
716 const_ok_for_mcore (HOST_WIDE_INT value
)
718 if (value
>= 0 && value
<= 127)
721 /* Try exact power of two. */
722 if (CONST_OK_FOR_M (value
))
725 /* Try exact power of two - 1. */
726 if (CONST_OK_FOR_N (value
) && value
!= -1)
732 /* Can we load a constant inline with up to 2 instructions ? */
735 mcore_const_ok_for_inline (HOST_WIDE_INT value
)
739 return try_constant_tricks (value
, & x
, & y
) > 0;
742 /* Are we loading the constant using a not ? */
745 mcore_const_trick_uses_not (HOST_WIDE_INT value
)
749 return try_constant_tricks (value
, & x
, & y
) == 2;
752 /* Try tricks to load a constant inline and return the trick number if
753 success (0 is non-inlinable).
756 1: single instruction (do the usual thing)
757 2: single insn followed by a 'not'
758 3: single insn followed by a subi
759 4: single insn followed by an addi
760 5: single insn followed by rsubi
761 6: single insn followed by bseti
762 7: single insn followed by bclri
763 8: single insn followed by rotli
764 9: single insn followed by lsli
765 10: single insn followed by ixh
766 11: single insn followed by ixw. */
769 try_constant_tricks (HOST_WIDE_INT value
, HOST_WIDE_INT
* x
, HOST_WIDE_INT
* y
)
772 unsigned HOST_WIDE_INT bit
, shf
, rot
;
774 if (const_ok_for_mcore (value
))
775 return 1; /* Do the usual thing. */
777 if (! TARGET_HARDLIT
)
780 if (const_ok_for_mcore (~value
))
786 for (i
= 1; i
<= 32; i
++)
788 if (const_ok_for_mcore (value
- i
))
796 if (const_ok_for_mcore (value
+ i
))
807 for (i
= 0; i
<= 31; i
++)
809 if (const_ok_for_mcore (i
- value
))
817 if (const_ok_for_mcore (value
& ~bit
))
824 if (const_ok_for_mcore (value
| bit
))
838 for (i
= 1; i
< 31; i
++)
842 /* MCore has rotate left. */
846 rot
|= c
; /* Simulate rotate. */
848 if (const_ok_for_mcore (rot
))
857 shf
= 0; /* Can't use logical shift, low order bit is one. */
861 if (shf
!= 0 && const_ok_for_mcore (shf
))
870 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
877 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
887 /* Check whether reg is dead at first. This is done by searching ahead
888 for either the next use (i.e., reg is live), a death note, or a set of
889 reg. Don't just use dead_or_set_p() since reload does not always mark
890 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
891 can ignore subregs by extracting the actual register. BRC */
894 mcore_is_dead (rtx first
, rtx reg
)
898 /* For mcore, subregs can't live independently of their parent regs. */
899 if (GET_CODE (reg
) == SUBREG
)
900 reg
= SUBREG_REG (reg
);
902 /* Dies immediately. */
903 if (dead_or_set_p (first
, reg
))
906 /* Look for conclusive evidence of live/death, otherwise we have
907 to assume that it is live. */
908 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
910 if (GET_CODE (insn
) == JUMP_INSN
)
911 return 0; /* We lose track, assume it is alive. */
913 else if (GET_CODE(insn
) == CALL_INSN
)
915 /* Call's might use it for target or register parms. */
916 if (reg_referenced_p (reg
, PATTERN (insn
))
917 || find_reg_fusage (insn
, USE
, reg
))
919 else if (dead_or_set_p (insn
, reg
))
922 else if (GET_CODE (insn
) == INSN
)
924 if (reg_referenced_p (reg
, PATTERN (insn
)))
926 else if (dead_or_set_p (insn
, reg
))
931 /* No conclusive evidence either way, we cannot take the chance
932 that control flow hid the use from us -- "I'm not dead yet". */
936 /* Count the number of ones in mask. */
939 mcore_num_ones (HOST_WIDE_INT mask
)
941 /* A trick to count set bits recently posted on comp.compilers. */
942 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
943 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
944 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
945 mask
= ((mask
>> 8) + mask
);
947 return (mask
+ (mask
>> 16)) & 0xff;
950 /* Count the number of zeros in mask. */
953 mcore_num_zeros (HOST_WIDE_INT mask
)
955 return 32 - mcore_num_ones (mask
);
958 /* Determine byte being masked. */
961 mcore_byte_offset (unsigned int mask
)
963 if (mask
== 0x00ffffffL
)
965 else if (mask
== 0xff00ffffL
)
967 else if (mask
== 0xffff00ffL
)
969 else if (mask
== 0xffffff00L
)
975 /* Determine halfword being masked. */
978 mcore_halfword_offset (unsigned int mask
)
980 if (mask
== 0x0000ffffL
)
982 else if (mask
== 0xffff0000L
)
988 /* Output a series of bseti's corresponding to mask. */
991 mcore_output_bseti (rtx dst
, int mask
)
996 out_operands
[0] = dst
;
998 for (bit
= 0; bit
< 32; bit
++)
1000 if ((mask
& 0x1) == 0x1)
1002 out_operands
[1] = GEN_INT (bit
);
1004 output_asm_insn ("bseti\t%0,%1", out_operands
);
1012 /* Output a series of bclri's corresponding to mask. */
1015 mcore_output_bclri (rtx dst
, int mask
)
1017 rtx out_operands
[2];
1020 out_operands
[0] = dst
;
1022 for (bit
= 0; bit
< 32; bit
++)
1024 if ((mask
& 0x1) == 0x0)
1026 out_operands
[1] = GEN_INT (bit
);
1028 output_asm_insn ("bclri\t%0,%1", out_operands
);
1037 /* Output a conditional move of two constants that are +/- 1 within each
1038 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1039 really worth the effort. */
1042 mcore_output_cmov (rtx operands
[], int cmp_t
, const char * test
)
1044 HOST_WIDE_INT load_value
;
1045 HOST_WIDE_INT adjust_value
;
1046 rtx out_operands
[4];
1048 out_operands
[0] = operands
[0];
1050 /* Check to see which constant is loadable. */
1051 if (const_ok_for_mcore (INTVAL (operands
[1])))
1053 out_operands
[1] = operands
[1];
1054 out_operands
[2] = operands
[2];
1056 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1058 out_operands
[1] = operands
[2];
1059 out_operands
[2] = operands
[1];
1061 /* Complement test since constants are swapped. */
1062 cmp_t
= (cmp_t
== 0);
1064 load_value
= INTVAL (out_operands
[1]);
1065 adjust_value
= INTVAL (out_operands
[2]);
1067 /* First output the test if folded into the pattern. */
1070 output_asm_insn (test
, operands
);
1072 /* Load the constant - for now, only support constants that can be
1073 generated with a single instruction. maybe add general inlinable
1074 constants later (this will increase the # of patterns since the
1075 instruction sequence has a different length attribute). */
1076 if (load_value
>= 0 && load_value
<= 127)
1077 output_asm_insn ("movi\t%0,%1", out_operands
);
1078 else if (CONST_OK_FOR_M (load_value
))
1079 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1080 else if (CONST_OK_FOR_N (load_value
))
1081 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1083 /* Output the constant adjustment. */
1084 if (load_value
> adjust_value
)
1087 output_asm_insn ("decf\t%0", out_operands
);
1089 output_asm_insn ("dect\t%0", out_operands
);
1094 output_asm_insn ("incf\t%0", out_operands
);
1096 output_asm_insn ("inct\t%0", out_operands
);
1102 /* Outputs the peephole for moving a constant that gets not'ed followed
1103 by an and (i.e. combine the not and the and into andn). BRC */
1106 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
1109 rtx out_operands
[3];
1110 const char * load_op
;
1114 trick_no
= try_constant_tricks (INTVAL (operands
[1]), &x
, &y
);
1115 gcc_assert (trick_no
== 2);
1117 out_operands
[0] = operands
[0];
1118 out_operands
[1] = GEN_INT (x
);
1119 out_operands
[2] = operands
[2];
1121 if (x
>= 0 && x
<= 127)
1122 load_op
= "movi\t%0,%1";
1124 /* Try exact power of two. */
1125 else if (CONST_OK_FOR_M (x
))
1126 load_op
= "bgeni\t%0,%P1";
1128 /* Try exact power of two - 1. */
1129 else if (CONST_OK_FOR_N (x
))
1130 load_op
= "bmaski\t%0,%N1";
1134 load_op
= "BADMOVI-andn\t%0, %1";
1138 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1139 output_asm_insn (buf
, out_operands
);
1144 /* Output an inline constant. */
1147 output_inline_const (enum machine_mode mode
, rtx operands
[])
1149 HOST_WIDE_INT x
= 0, y
= 0;
1151 rtx out_operands
[3];
1154 const char *dst_fmt
;
1155 HOST_WIDE_INT value
;
1157 value
= INTVAL (operands
[1]);
1159 trick_no
= try_constant_tricks (value
, &x
, &y
);
1160 /* lrw's are handled separately: Large inlinable constants never get
1161 turned into lrw's. Our caller uses try_constant_tricks to back
1162 off to an lrw rather than calling this routine. */
1163 gcc_assert (trick_no
!= 0);
1168 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1169 out_operands
[0] = operands
[0];
1170 out_operands
[1] = GEN_INT (x
);
1173 out_operands
[2] = GEN_INT (y
);
1175 /* Select dst format based on mode. */
1176 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1181 if (x
>= 0 && x
<= 127)
1182 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1184 /* Try exact power of two. */
1185 else if (CONST_OK_FOR_M (x
))
1186 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1188 /* Try exact power of two - 1. */
1189 else if (CONST_OK_FOR_N (x
))
1190 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1194 sprintf (load_op
, "BADMOVI-inline_const %s, %%1", dst_fmt
);
1201 strcpy (buf
, load_op
);
1204 sprintf (buf
, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1207 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1210 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1213 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1214 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1217 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1220 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1223 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1226 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1229 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1232 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1238 output_asm_insn (buf
, out_operands
);
1243 /* Output a move of a word or less value. */
1246 mcore_output_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
1247 enum machine_mode mode ATTRIBUTE_UNUSED
)
1249 rtx dst
= operands
[0];
1250 rtx src
= operands
[1];
1252 if (GET_CODE (dst
) == REG
)
1254 if (GET_CODE (src
) == REG
)
1256 if (REGNO (src
) == CC_REG
) /* r-c */
1259 return "mov\t%0,%1"; /* r-r*/
1261 else if (GET_CODE (src
) == MEM
)
1263 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1264 return "lrw\t%0,[%1]"; /* a-R */
1266 switch (GET_MODE (src
)) /* r-m */
1269 return "ldw\t%0,%1";
1271 return "ld.h\t%0,%1";
1273 return "ld.b\t%0,%1";
1278 else if (GET_CODE (src
) == CONST_INT
)
1282 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1283 return "movi\t%0,%1";
1284 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1285 return "bgeni\t%0,%P1\t// %1 %x1";
1286 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1287 return "bmaski\t%0,%N1\t// %1 %x1";
1288 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1289 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1291 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1294 return "lrw\t%0, %1"; /* Into the literal pool. */
1296 else if (GET_CODE (dst
) == MEM
) /* m-r */
1297 switch (GET_MODE (dst
))
1300 return "stw\t%1,%0";
1302 return "st.h\t%1,%0";
1304 return "st.b\t%1,%0";
1312 /* Return a sequence of instructions to perform DI or DF move.
1313 Since the MCORE cannot move a DI or DF in one instruction, we have
1314 to take care when we see overlapping source and dest registers. */
1317 mcore_output_movedouble (rtx operands
[], enum machine_mode mode ATTRIBUTE_UNUSED
)
1319 rtx dst
= operands
[0];
1320 rtx src
= operands
[1];
1322 if (GET_CODE (dst
) == REG
)
1324 if (GET_CODE (src
) == REG
)
1326 int dstreg
= REGNO (dst
);
1327 int srcreg
= REGNO (src
);
1329 /* Ensure the second source not overwritten. */
1330 if (srcreg
+ 1 == dstreg
)
1331 return "mov %R0,%R1\n\tmov %0,%1";
1333 return "mov %0,%1\n\tmov %R0,%R1";
1335 else if (GET_CODE (src
) == MEM
)
1337 rtx memexp
= memexp
= XEXP (src
, 0);
1338 int dstreg
= REGNO (dst
);
1341 if (GET_CODE (memexp
) == LABEL_REF
)
1342 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1343 else if (GET_CODE (memexp
) == REG
)
1344 basereg
= REGNO (memexp
);
1345 else if (GET_CODE (memexp
) == PLUS
)
1347 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1348 basereg
= REGNO (XEXP (memexp
, 0));
1349 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1350 basereg
= REGNO (XEXP (memexp
, 1));
1357 /* ??? length attribute is wrong here. */
1358 if (dstreg
== basereg
)
1360 /* Just load them in reverse order. */
1361 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1363 /* XXX: alternative: move basereg to basereg+1
1364 and then fall through. */
1367 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1369 else if (GET_CODE (src
) == CONST_INT
)
1371 if (TARGET_LITTLE_END
)
1373 if (CONST_OK_FOR_I (INTVAL (src
)))
1374 output_asm_insn ("movi %0,%1", operands
);
1375 else if (CONST_OK_FOR_M (INTVAL (src
)))
1376 output_asm_insn ("bgeni %0,%P1", operands
);
1377 else if (CONST_OK_FOR_N (INTVAL (src
)))
1378 output_asm_insn ("bmaski %0,%N1", operands
);
1382 if (INTVAL (src
) < 0)
1383 return "bmaski %R0,32";
1385 return "movi %R0,0";
1389 if (CONST_OK_FOR_I (INTVAL (src
)))
1390 output_asm_insn ("movi %R0,%1", operands
);
1391 else if (CONST_OK_FOR_M (INTVAL (src
)))
1392 output_asm_insn ("bgeni %R0,%P1", operands
);
1393 else if (CONST_OK_FOR_N (INTVAL (src
)))
1394 output_asm_insn ("bmaski %R0,%N1", operands
);
1398 if (INTVAL (src
) < 0)
1399 return "bmaski %0,32";
1407 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1408 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1413 /* Predicates used by the templates. */
1416 mcore_arith_S_operand (rtx op
)
1418 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1424 /* Expand insert bit field. BRC */
1427 mcore_expand_insv (rtx operands
[])
1429 int width
= INTVAL (operands
[1]);
1430 int posn
= INTVAL (operands
[2]);
1432 rtx mreg
, sreg
, ereg
;
1434 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1435 for width==1 must be removed. Look around line 368. This is something
1436 we really want the md part to do. */
1437 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1439 /* Do directly with bseti or bclri. */
1440 /* RBE: 2/97 consider only low bit of constant. */
1441 if ((INTVAL (operands
[3]) & 1) == 0)
1443 mask
= ~(1 << posn
);
1444 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1445 gen_rtx_AND (SImode
, operands
[0], GEN_INT (mask
))));
1450 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1451 gen_rtx_IOR (SImode
, operands
[0], GEN_INT (mask
))));
1457 /* Look at some bit-field placements that we aren't interested
1458 in handling ourselves, unless specifically directed to do so. */
1459 if (! TARGET_W_FIELD
)
1460 return 0; /* Generally, give up about now. */
1462 if (width
== 8 && posn
% 8 == 0)
1463 /* Byte sized and aligned; let caller break it up. */
1466 if (width
== 16 && posn
% 16 == 0)
1467 /* Short sized and aligned; let caller break it up. */
1470 /* The general case - we can do this a little bit better than what the
1471 machine independent part tries. This will get rid of all the subregs
1472 that mess up constant folding in combine when working with relaxed
1475 /* If setting the entire field, do it directly. */
1476 if (GET_CODE (operands
[3]) == CONST_INT
1477 && INTVAL (operands
[3]) == ((1 << width
) - 1))
1479 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1480 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1481 gen_rtx_IOR (SImode
, operands
[0], mreg
)));
1485 /* Generate the clear mask. */
1486 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1488 /* Clear the field, to overlay it later with the source. */
1489 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1490 gen_rtx_AND (SImode
, operands
[0], mreg
)));
1492 /* If the source is constant 0, we've nothing to add back. */
1493 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1496 /* XXX: Should we worry about more games with constant values?
1497 We've covered the high profile: set/clear single-bit and many-bit
1498 fields. How often do we see "arbitrary bit pattern" constants? */
1499 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1501 /* Extract src as same width as dst (needed for signed values). We
1502 always have to do this since we widen everything to SImode.
1503 We don't have to mask if we're shifting this up against the
1504 MSB of the register (e.g., the shift will push out any hi-order
1506 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1508 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1509 emit_insn (gen_rtx_SET (SImode
, sreg
,
1510 gen_rtx_AND (SImode
, sreg
, ereg
)));
1513 /* Insert source value in dest. */
1515 emit_insn (gen_rtx_SET (SImode
, sreg
,
1516 gen_rtx_ASHIFT (SImode
, sreg
, GEN_INT (posn
))));
1518 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1519 gen_rtx_IOR (SImode
, operands
[0], sreg
)));
1524 /* ??? Block move stuff stolen from m88k. This code has not been
1525 verified for correctness. */
1527 /* Emit code to perform a block move. Choose the best method.
1529 OPERANDS[0] is the destination.
1530 OPERANDS[1] is the source.
1531 OPERANDS[2] is the size.
1532 OPERANDS[3] is the alignment safe to use. */
1534 /* Emit code to perform a block move with an offset sequence of ldw/st
1535 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1536 known constants. DEST and SRC are registers. OFFSET is the known
1537 starting point for the output pattern. */
1539 static const enum machine_mode mode_from_align
[] =
1541 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1545 block_move_sequence (rtx dst_mem
, rtx src_mem
, int size
, int align
)
1548 enum machine_mode mode
[2];
1557 x
= XEXP (dst_mem
, 0);
1560 x
= force_reg (Pmode
, x
);
1561 dst_mem
= replace_equiv_address (dst_mem
, x
);
1564 x
= XEXP (src_mem
, 0);
1567 x
= force_reg (Pmode
, x
);
1568 src_mem
= replace_equiv_address (src_mem
, x
);
1571 active
[0] = active
[1] = false;
1582 next_amount
= (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
1583 next_amount
= MIN (next_amount
, align
);
1585 amount
[next
] = next_amount
;
1586 mode
[next
] = mode_from_align
[next_amount
];
1587 temp
[next
] = gen_reg_rtx (mode
[next
]);
1589 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1590 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1592 offset_ld
+= next_amount
;
1593 size
-= next_amount
;
1594 active
[next
] = true;
1599 active
[phase
] = false;
1601 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1602 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1604 offset_st
+= amount
[phase
];
1607 while (active
[next
]);
1611 mcore_expand_block_move (rtx
*operands
)
1613 HOST_WIDE_INT align
, bytes
, max
;
1615 if (GET_CODE (operands
[2]) != CONST_INT
)
1618 bytes
= INTVAL (operands
[2]);
1619 align
= INTVAL (operands
[3]);
1648 block_move_sequence (operands
[0], operands
[1], bytes
, align
);
1656 /* Code to generate prologue and epilogue sequences. */
1657 static int number_of_regs_before_varargs
;
1659 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1660 for a varargs function. */
1661 static int current_function_anonymous_args
;
1663 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1664 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1665 #define ADDI_REACH (32) /* Maximum addi operand. */
1668 layout_mcore_frame (struct mcore_frame
* infp
)
1677 unsigned int growths
;
1680 /* Might have to spill bytes to re-assemble a big argument that
1681 was passed partially in registers and partially on the stack. */
1682 nbytes
= crtl
->args
.pretend_args_size
;
1684 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1685 if (current_function_anonymous_args
)
1686 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
1688 infp
->arg_size
= nbytes
;
1690 /* How much space to save non-volatile registers we stomp. */
1691 infp
->reg_mask
= calc_live_regs (& n
);
1692 infp
->reg_size
= n
* 4;
1694 /* And the rest of it... locals and space for overflowed outbounds. */
1695 infp
->local_size
= get_frame_size ();
1696 infp
->outbound_size
= crtl
->outgoing_args_size
;
1698 /* Make sure we have a whole number of words for the locals. */
1699 if (infp
->local_size
% STACK_BYTES
)
1700 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
1702 /* Only thing we know we have to pad is the outbound space, since
1703 we've aligned our locals assuming that base of locals is aligned. */
1704 infp
->pad_local
= 0;
1706 infp
->pad_outbound
= 0;
1707 if (infp
->outbound_size
% STACK_BYTES
)
1708 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
1710 /* Now we see how we want to stage the prologue so that it does
1711 the most appropriate stack growth and register saves to either:
1713 (2) reduce instruction space, or
1714 (3) reduce stack space. */
1715 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
1716 infp
->growth
[i
] = 0;
1718 regarg
= infp
->reg_size
+ infp
->arg_size
;
1719 localregarg
= infp
->local_size
+ regarg
;
1720 localreg
= infp
->local_size
+ infp
->reg_size
;
1721 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
1724 /* XXX: Consider one where we consider localregarg + outbound too! */
1726 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1727 use stw's with offsets and buy the frame in one shot. */
1728 if (localregarg
<= ADDI_REACH
1729 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1731 /* Make sure we'll be aligned. */
1732 if (localregarg
% STACK_BYTES
)
1733 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1735 step
= localregarg
+ infp
->pad_reg
;
1736 infp
->reg_offset
= infp
->local_size
;
1738 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
1741 infp
->reg_offset
+= outbounds
;
1745 infp
->arg_offset
= step
- 4;
1746 infp
->growth
[growths
++] = step
;
1747 infp
->reg_growth
= growths
;
1748 infp
->local_growth
= growths
;
1750 /* If we haven't already folded it in. */
1752 infp
->growth
[growths
++] = outbounds
;
1757 /* Frame can't be done with a single subi, but can be done with 2
1758 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1759 shift some of the stack purchase into the first subi, so both are
1760 single instructions. */
1761 if (localregarg
<= STORE_REACH
1762 && (infp
->local_size
> ADDI_REACH
)
1763 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1767 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1768 if (localregarg
% STACK_BYTES
)
1769 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1771 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
1772 step
= ADDI_REACH
; /* As much up front as we can. */
1776 /* XXX: Consider whether step will still be aligned; we believe so. */
1777 infp
->arg_offset
= step
- 4;
1778 infp
->growth
[growths
++] = step
;
1779 infp
->reg_growth
= growths
;
1780 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
1783 /* Can we fold in any space required for outbounds? */
1784 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
1790 /* Get the rest of the locals in place. */
1792 infp
->growth
[growths
++] = step
;
1793 infp
->local_growth
= growths
;
1798 /* Finish off if we need to do so. */
1800 infp
->growth
[growths
++] = outbounds
;
1805 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1806 Then we buy the rest of the frame in 1 or 2 steps depending on
1807 whether we need a frame pointer. */
1808 if ((regarg
% STACK_BYTES
) == 0)
1810 infp
->growth
[growths
++] = regarg
;
1811 infp
->reg_growth
= growths
;
1812 infp
->arg_offset
= regarg
- 4;
1813 infp
->reg_offset
= 0;
1815 if (infp
->local_size
% STACK_BYTES
)
1816 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1818 step
= infp
->local_size
+ infp
->pad_local
;
1820 if (!frame_pointer_needed
)
1826 infp
->growth
[growths
++] = step
;
1827 infp
->local_growth
= growths
;
1829 /* If there's any left to be done. */
1831 infp
->growth
[growths
++] = outbounds
;
1836 /* XXX: optimizations that we'll want to play with....
1837 -- regarg is not aligned, but it's a small number of registers;
1838 use some of localsize so that regarg is aligned and then
1839 save the registers. */
1841 /* Simple encoding; plods down the stack buying the pieces as it goes.
1842 -- does not optimize space consumption.
1843 -- does not attempt to optimize instruction counts.
1844 -- but it is safe for all alignments. */
1845 if (regarg
% STACK_BYTES
!= 0)
1846 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
1848 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
1849 infp
->reg_growth
= growths
;
1850 infp
->arg_offset
= infp
->growth
[0] - 4;
1851 infp
->reg_offset
= 0;
1853 if (frame_pointer_needed
)
1855 if (infp
->local_size
% STACK_BYTES
!= 0)
1856 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1858 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
1859 infp
->local_growth
= growths
;
1861 infp
->growth
[growths
++] = outbounds
;
1865 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
1866 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
1868 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
1869 infp
->local_growth
= growths
;
1872 /* Anything else that we've forgotten?, plus a few consistency checks. */
1874 assert (infp
->reg_offset
>= 0);
1875 assert (growths
<= MAX_STACK_GROWS
);
1877 for (i
= 0; i
< growths
; i
++)
1878 gcc_assert (!(infp
->growth
[i
] % STACK_BYTES
));
1881 /* Define the offset between two registers, one to be eliminated, and
1882 the other its replacement, at the start of a routine. */
1885 mcore_initial_elimination_offset (int from
, int to
)
1889 struct mcore_frame fi
;
1891 layout_mcore_frame (& fi
);
1894 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
1896 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
1898 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1901 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1902 return above_frame
+ below_frame
;
1904 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1910 /* Keep track of some information about varargs for the prolog. */
1913 mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*args_so_far
,
1914 enum machine_mode mode
, tree type
,
1915 int * ptr_pretend_size ATTRIBUTE_UNUSED
,
1916 int second_time ATTRIBUTE_UNUSED
)
1918 current_function_anonymous_args
= 1;
1920 /* We need to know how many argument registers are used before
1921 the varargs start, so that we can push the remaining argument
1922 registers during the prologue. */
1923 number_of_regs_before_varargs
= *args_so_far
+ mcore_num_arg_regs (mode
, type
);
1925 /* There is a bug somewhere in the arg handling code.
1926 Until I can find it this workaround always pushes the
1927 last named argument onto the stack. */
1928 number_of_regs_before_varargs
= *args_so_far
;
1930 /* The last named argument may be split between argument registers
1931 and the stack. Allow for this here. */
1932 if (number_of_regs_before_varargs
> NPARM_REGS
)
1933 number_of_regs_before_varargs
= NPARM_REGS
;
1937 mcore_expand_prolog (void)
1939 struct mcore_frame fi
;
1940 int space_allocated
= 0;
1943 /* Find out what we're doing. */
1944 layout_mcore_frame (&fi
);
1946 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
1947 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
1951 /* Emit a symbol for this routine's frame size. */
1954 x
= DECL_RTL (current_function_decl
);
1956 gcc_assert (GET_CODE (x
) == MEM
);
1960 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1962 if (mcore_current_function_name
)
1963 free (mcore_current_function_name
);
1965 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
1967 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
1969 if (cfun
->calls_alloca
)
1970 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
1973 We're looking at how the 8byte alignment affects stack layout
1974 and where we had to pad things. This emits information we can
1975 extract which tells us about frame sizes and the like. */
1976 fprintf (asm_out_file
,
1977 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
1978 mcore_current_function_name
,
1979 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
1980 fi
.local_size
, fi
.outbound_size
,
1981 frame_pointer_needed
);
1984 if (mcore_naked_function_p ())
1987 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
1988 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
1990 /* If we have a parameter passed partially in regs and partially in memory,
1991 the registers will have been stored to memory already in function.c. So
1992 we only need to do something here for varargs functions. */
1993 if (fi
.arg_size
!= 0 && crtl
->args
.pretend_args_size
== 0)
1996 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
1997 int remaining
= fi
.arg_size
;
1999 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
2001 emit_insn (gen_movsi
2002 (gen_rtx_MEM (SImode
,
2003 plus_constant (stack_pointer_rtx
, offset
)),
2004 gen_rtx_REG (SImode
, rn
)));
2008 /* Do we need another stack adjustment before we do the register saves? */
2009 if (growth
< fi
.reg_growth
)
2010 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2012 if (fi
.reg_size
!= 0)
2015 int offs
= fi
.reg_offset
;
2017 for (i
= 15; i
>= 0; i
--)
2019 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2023 while (fi
.reg_mask
& (1 << first_reg
))
2027 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2028 gen_rtx_REG (SImode
, first_reg
),
2029 GEN_INT (16 - first_reg
)));
2031 i
-= (15 - first_reg
);
2032 offs
+= (16 - first_reg
) * 4;
2034 else if (fi
.reg_mask
& (1 << i
))
2036 emit_insn (gen_movsi
2037 (gen_rtx_MEM (SImode
,
2038 plus_constant (stack_pointer_rtx
, offs
)),
2039 gen_rtx_REG (SImode
, i
)));
2045 /* Figure the locals + outbounds. */
2046 if (frame_pointer_needed
)
2048 /* If we haven't already purchased to 'fp'. */
2049 if (growth
< fi
.local_growth
)
2050 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2052 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2054 /* ... and then go any remaining distance for outbounds, etc. */
2055 if (fi
.growth
[growth
])
2056 output_stack_adjust (-1, fi
.growth
[growth
++]);
2060 if (growth
< fi
.local_growth
)
2061 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2062 if (fi
.growth
[growth
])
2063 output_stack_adjust (-1, fi
.growth
[growth
++]);
2068 mcore_expand_epilog (void)
2070 struct mcore_frame fi
;
2073 int growth
= MAX_STACK_GROWS
- 1 ;
2076 /* Find out what we're doing. */
2077 layout_mcore_frame(&fi
);
2079 if (mcore_naked_function_p ())
2082 /* If we had a frame pointer, restore the sp from that. */
2083 if (frame_pointer_needed
)
2085 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2086 growth
= fi
.local_growth
- 1;
2090 /* XXX: while loop should accumulate and do a single sell. */
2091 while (growth
>= fi
.local_growth
)
2093 if (fi
.growth
[growth
] != 0)
2094 output_stack_adjust (1, fi
.growth
[growth
]);
2099 /* Make sure we've shrunk stack back to the point where the registers
2100 were laid down. This is typically 0/1 iterations. Then pull the
2101 register save information back off the stack. */
2102 while (growth
>= fi
.reg_growth
)
2103 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2105 offs
= fi
.reg_offset
;
2107 for (i
= 15; i
>= 0; i
--)
2109 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2113 /* Find the starting register. */
2116 while (fi
.reg_mask
& (1 << first_reg
))
2121 emit_insn (gen_load_multiple (gen_rtx_REG (SImode
, first_reg
),
2122 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2123 GEN_INT (16 - first_reg
)));
2125 i
-= (15 - first_reg
);
2126 offs
+= (16 - first_reg
) * 4;
2128 else if (fi
.reg_mask
& (1 << i
))
2130 emit_insn (gen_movsi
2131 (gen_rtx_REG (SImode
, i
),
2132 gen_rtx_MEM (SImode
,
2133 plus_constant (stack_pointer_rtx
, offs
))));
2138 /* Give back anything else. */
2139 /* XXX: Should accumulate total and then give it back. */
2141 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2144 /* This code is borrowed from the SH port. */
2146 /* The MCORE cannot load a large constant into a register, constants have to
2147 come from a pc relative load. The reference of a pc relative load
2148 instruction must be less than 1k in front of the instruction. This
2149 means that we often have to dump a constant inside a function, and
2150 generate code to branch around it.
2152 It is important to minimize this, since the branches will slow things
2153 down and make things bigger.
2155 Worst case code looks like:
2171 We fix this by performing a scan before scheduling, which notices which
2172 instructions need to have their operands fetched from the constant table
2173 and builds the table.
2177 scan, find an instruction which needs a pcrel move. Look forward, find the
2178 last barrier which is within MAX_COUNT bytes of the requirement.
2179 If there isn't one, make one. Process all the instructions between
2180 the find and the barrier.
2182 In the above example, we can tell that L3 is within 1k of L1, so
2183 the first move can be shrunk from the 2 insn+constant sequence into
2184 just 1 insn, and the constant moved to L3 to make:
2194 Then the second move becomes the target for the shortening process. */
2198 rtx value
; /* Value in table. */
2199 rtx label
; /* Label of value. */
2202 /* The maximum number of constants that can fit into one pool, since
2203 the pc relative range is 0...1020 bytes and constants are at least 4
2204 bytes long. We subtract 4 from the range to allow for the case where
2205 we need to add a branch/align before the constant pool. */
2207 #define MAX_COUNT 1016
2208 #define MAX_POOL_SIZE (MAX_COUNT/4)
2209 static pool_node pool_vector
[MAX_POOL_SIZE
];
2210 static int pool_size
;
2212 /* Dump out any constants accumulated in the final pass. These
2213 will only be labels. */
2216 mcore_output_jump_label_table (void)
2222 fprintf (asm_out_file
, "\t.align 2\n");
2224 for (i
= 0; i
< pool_size
; i
++)
2226 pool_node
* p
= pool_vector
+ i
;
2228 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2230 output_asm_insn (".long %0", &p
->value
);
2239 /* Check whether insn is a candidate for a conditional. */
2242 is_cond_candidate (rtx insn
)
2244 /* The only things we conditionalize are those that can be directly
2245 changed into a conditional. Only bother with SImode items. If
2246 we wanted to be a little more aggressive, we could also do other
2247 modes such as DImode with reg-reg move or load 0. */
2248 if (GET_CODE (insn
) == INSN
)
2250 rtx pat
= PATTERN (insn
);
2253 if (GET_CODE (pat
) != SET
)
2256 dst
= XEXP (pat
, 0);
2258 if ((GET_CODE (dst
) != REG
&&
2259 GET_CODE (dst
) != SUBREG
) ||
2260 GET_MODE (dst
) != SImode
)
2263 src
= XEXP (pat
, 1);
2265 if ((GET_CODE (src
) == REG
||
2266 (GET_CODE (src
) == SUBREG
&&
2267 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2268 GET_MODE (src
) == SImode
)
2269 return COND_MOV_INSN
;
2270 else if (GET_CODE (src
) == CONST_INT
&&
2272 return COND_CLR_INSN
;
2273 else if (GET_CODE (src
) == PLUS
&&
2274 (GET_CODE (XEXP (src
, 0)) == REG
||
2275 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2276 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2277 GET_MODE (XEXP (src
, 0)) == SImode
&&
2278 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2279 INTVAL (XEXP (src
, 1)) == 1)
2280 return COND_INC_INSN
;
2281 else if (((GET_CODE (src
) == MINUS
&&
2282 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2283 INTVAL( XEXP (src
, 1)) == 1) ||
2284 (GET_CODE (src
) == PLUS
&&
2285 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2286 INTVAL (XEXP (src
, 1)) == -1)) &&
2287 (GET_CODE (XEXP (src
, 0)) == REG
||
2288 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2289 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2290 GET_MODE (XEXP (src
, 0)) == SImode
)
2291 return COND_DEC_INSN
;
2293 /* Some insns that we don't bother with:
2294 (set (rx:DI) (ry:DI))
2295 (set (rx:DI) (const_int 0))
2299 else if (GET_CODE (insn
) == JUMP_INSN
&&
2300 GET_CODE (PATTERN (insn
)) == SET
&&
2301 GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2302 return COND_BRANCH_INSN
;
2307 /* Emit a conditional version of insn and replace the old insn with the
2308 new one. Return the new insn if emitted. */
2311 emit_new_cond_insn (rtx insn
, int cond
)
2317 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2320 pat
= PATTERN (insn
);
2322 if (GET_CODE (insn
) == INSN
)
2324 dst
= SET_DEST (pat
);
2325 src
= SET_SRC (pat
);
2329 dst
= JUMP_LABEL (insn
);
2338 c_insn
= gen_movt0 (dst
, src
, dst
);
2340 c_insn
= gen_movt0 (dst
, dst
, src
);
2345 c_insn
= gen_incscc (dst
, dst
);
2347 c_insn
= gen_incscc_false (dst
, dst
);
2352 c_insn
= gen_decscc (dst
, dst
);
2354 c_insn
= gen_decscc_false (dst
, dst
);
2357 case COND_BRANCH_INSN
:
2359 c_insn
= gen_branch_true (dst
);
2361 c_insn
= gen_branch_false (dst
);
2368 /* Only copy the notes if they exist. */
2369 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2371 /* We really don't need to bother with the notes and links at this
2372 point, but go ahead and save the notes. This will help is_dead()
2373 when applying peepholes (links don't matter since they are not
2374 used any more beyond this point for the mcore). */
2375 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2378 if (num
== COND_BRANCH_INSN
)
2380 /* For jumps, we need to be a little bit careful and emit the new jump
2381 before the old one and to update the use count for the target label.
2382 This way, the barrier following the old (uncond) jump will get
2383 deleted, but the label won't. */
2384 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2386 ++ LABEL_NUSES (dst
);
2388 JUMP_LABEL (c_insn
) = dst
;
2391 c_insn
= emit_insn_after (c_insn
, insn
);
2398 /* Attempt to change a basic block into a series of conditional insns. This
2399 works by taking the branch at the end of the 1st block and scanning for the
2400 end of the 2nd block. If all instructions in the 2nd block have cond.
2401 versions and the label at the start of block 3 is the same as the target
2402 from the branch at block 1, then conditionalize all insn in block 2 using
2403 the inverse condition of the branch at block 1. (Note I'm bending the
2404 definition of basic block here.)
2408 bt L2 <-- end of block 1 (delete)
2411 br L3 <-- end of block 2
2413 L2: ... <-- start of block 3 (NUSES==1)
2424 we can delete the L2 label if NUSES==1 and re-apply the optimization
2425 starting at the last instruction of block 2. This may allow an entire
2426 if-then-else statement to be conditionalized. BRC */
2428 conditionalize_block (rtx first
)
2432 rtx end_blk_1_br
= 0;
2433 rtx end_blk_2_insn
= 0;
2434 rtx start_blk_3_lab
= 0;
2440 /* Check that the first insn is a candidate conditional jump. This is
2441 the one that we'll eliminate. If not, advance to the next insn to
2443 if (GET_CODE (first
) != JUMP_INSN
||
2444 GET_CODE (PATTERN (first
)) != SET
||
2445 GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2446 return NEXT_INSN (first
);
2448 /* Extract some information we need. */
2449 end_blk_1_br
= first
;
2450 br_pat
= PATTERN (end_blk_1_br
);
2452 /* Complement the condition since we use the reverse cond. for the insns. */
2453 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2455 /* Determine what kind of branch we have. */
2456 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2458 /* A normal branch, so extract label out of first arm. */
2459 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2463 /* An inverse branch, so extract the label out of the 2nd arm
2464 and complement the condition. */
2466 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2469 /* Scan forward for the start of block 2: it must start with a
2470 label and that label must be the same as the branch target
2471 label from block 1. We don't care about whether block 2 actually
2472 ends with a branch or a label (an uncond. branch is
2473 conditionalizable). */
2474 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2478 code
= GET_CODE (insn
);
2480 /* Look for the label at the start of block 3. */
2481 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2484 /* Skip barriers, notes, and conditionalizable insns. If the
2485 insn is not conditionalizable or makes this optimization fail,
2486 just return the next insn so we can start over from that point. */
2487 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2488 return NEXT_INSN (insn
);
2490 /* Remember the last real insn before the label (i.e. end of block 2). */
2491 if (code
== JUMP_INSN
|| code
== INSN
)
2494 end_blk_2_insn
= insn
;
2501 /* It is possible for this optimization to slow performance if the blocks
2502 are long. This really depends upon whether the branch is likely taken
2503 or not. If the branch is taken, we slow performance in many cases. But,
2504 if the branch is not taken, we always help performance (for a single
2505 block, but for a double block (i.e. when the optimization is re-applied)
2506 this is not true since the 'right thing' depends on the overall length of
2507 the collapsed block). As a compromise, don't apply this optimization on
2508 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2509 the best threshold depends on the latencies of the instructions (i.e.,
2510 the branch penalty). */
2511 if (optimize
> 1 && blk_size
> 2)
2514 /* At this point, we've found the start of block 3 and we know that
2515 it is the destination of the branch from block 1. Also, all
2516 instructions in the block 2 are conditionalizable. So, apply the
2517 conditionalization and delete the branch. */
2518 start_blk_3_lab
= insn
;
2520 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2521 insn
= NEXT_INSN (insn
))
2525 if (INSN_DELETED_P (insn
))
2528 /* Try to form a conditional variant of the instruction and emit it. */
2529 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2531 if (end_blk_2_insn
== insn
)
2532 end_blk_2_insn
= newinsn
;
2538 /* Note whether we will delete the label starting blk 3 when the jump
2539 gets deleted. If so, we want to re-apply this optimization at the
2540 last real instruction right before the label. */
2541 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2543 start_blk_3_lab
= 0;
2546 /* ??? we probably should redistribute the death notes for this insn, esp.
2547 the death of cc, but it doesn't really matter this late in the game.
2548 The peepholes all use is_dead() which will find the correct death
2549 regardless of whether there is a note. */
2550 delete_insn (end_blk_1_br
);
2552 if (! start_blk_3_lab
)
2553 return end_blk_2_insn
;
2555 /* Return the insn right after the label at the start of block 3. */
2556 return NEXT_INSN (start_blk_3_lab
);
2559 /* Apply the conditionalization of blocks optimization. This is the
2560 outer loop that traverses through the insns scanning for a branch
2561 that signifies an opportunity to apply the optimization. Note that
2562 this optimization is applied late. If we could apply it earlier,
2563 say before cse 2, it may expose more optimization opportunities.
2564 but, the pay back probably isn't really worth the effort (we'd have
2565 to update all reg/flow/notes/links/etc to make it work - and stick it
2566 in before cse 2). */
2569 conditionalize_optimization (void)
2573 for (insn
= get_insns (); insn
; insn
= conditionalize_block (insn
))
2577 static int saved_warn_return_type
= -1;
2578 static int saved_warn_return_type_count
= 0;
2580 /* This is to handle loads from the constant pool. */
2585 /* Reset this variable. */
2586 current_function_anonymous_args
= 0;
2588 /* Restore the warn_return_type if it has been altered. */
2589 if (saved_warn_return_type
!= -1)
2591 /* Only restore the value if we have reached another function.
2592 The test of warn_return_type occurs in final_function () in
2593 c-decl.c a long time after the code for the function is generated,
2594 so we need a counter to tell us when we have finished parsing that
2595 function and can restore the flag. */
2596 if (--saved_warn_return_type_count
== 0)
2598 warn_return_type
= saved_warn_return_type
;
2599 saved_warn_return_type
= -1;
2606 /* Conditionalize blocks where we can. */
2607 conditionalize_optimization ();
2609 /* Literal pool generation is now pushed off until the assembler. */
2613 /* Return true if X is something that can be moved directly into r15. */
2616 mcore_r15_operand_p (rtx x
)
2618 switch (GET_CODE (x
))
2621 return mcore_const_ok_for_inline (INTVAL (x
));
2633 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't
2634 directly move X into it, use r1-r14 as a temporary. */
2637 mcore_secondary_reload_class (enum reg_class rclass
,
2638 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2640 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], 15)
2641 && !mcore_r15_operand_p (x
))
2646 /* Return the reg_class to use when reloading the rtx X into the class
2647 RCLASS. If X is too complex to move directly into r15, prefer to
2648 use LRW_REGS instead. */
2651 mcore_reload_class (rtx x
, enum reg_class rclass
)
2653 if (reg_class_subset_p (LRW_REGS
, rclass
) && !mcore_r15_operand_p (x
))
2659 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2660 register. Note that the current version doesn't worry about whether
2661 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2662 in r2 matches an SImode in r2. Might think in the future about whether
2663 we want to be able to say something about modes. */
2666 mcore_is_same_reg (rtx x
, rtx y
)
2668 /* Strip any and all of the subreg wrappers. */
2669 while (GET_CODE (x
) == SUBREG
)
2672 while (GET_CODE (y
) == SUBREG
)
2675 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
2682 mcore_override_options (void)
2684 /* Only the m340 supports little endian code. */
2685 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
2686 target_flags
|= MASK_M340
;
2689 /* Compute the number of word sized registers needed to
2690 hold a function argument of mode MODE and type TYPE. */
2693 mcore_num_arg_regs (enum machine_mode mode
, const_tree type
)
2697 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2700 if (type
&& mode
== BLKmode
)
2701 size
= int_size_in_bytes (type
);
2703 size
= GET_MODE_SIZE (mode
);
2705 return ROUND_ADVANCE (size
);
2709 handle_structs_in_regs (enum machine_mode mode
, const_tree type
, int reg
)
2713 /* The MCore ABI defines that a structure whose size is not a whole multiple
2714 of bytes is passed packed into registers (or spilled onto the stack if
2715 not enough registers are available) with the last few bytes of the
2716 structure being packed, left-justified, into the last register/stack slot.
2717 GCC handles this correctly if the last word is in a stack slot, but we
2718 have to generate a special, PARALLEL RTX if the last word is in an
2719 argument register. */
2721 && TYPE_MODE (type
) == BLKmode
2722 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
2723 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
2724 && (size
% UNITS_PER_WORD
!= 0)
2725 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
2727 rtx arg_regs
[NPARM_REGS
];
2732 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
2735 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
2736 GEN_INT (nregs
* UNITS_PER_WORD
));
2740 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2741 assert (ARRAY_SIZE (arg_regs
) == 6);
2742 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
2743 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
2745 result
= gen_rtx_PARALLEL (mode
, rtvec
);
2749 return gen_rtx_REG (mode
, reg
);
2753 mcore_function_value (const_tree valtype
, const_tree func
)
2755 enum machine_mode mode
;
2758 mode
= TYPE_MODE (valtype
);
2760 /* Since we promote return types, we must promote the mode here too. */
2761 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
2763 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
2766 /* Define where to put the arguments to a function.
2767 Value is zero to push the argument on the stack,
2768 or a hard register in which to store the argument.
2770 MODE is the argument's machine mode.
2771 TYPE is the data type of the argument (as a tree).
2772 This is null for libcalls where that information may
2774 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2775 the preceding args and about the function being called.
2776 NAMED is nonzero if this argument is a named parameter
2777 (otherwise it is an extra parameter matching an ellipsis).
2779 On MCore the first args are normally in registers
2780 and the rest are pushed. Any arg that starts within the first
2781 NPARM_REGS words is at least partially passed in a register unless
2782 its data type forbids. */
2785 mcore_function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
,
2786 tree type
, int named
)
2790 if (! named
|| mode
== VOIDmode
)
2793 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2796 arg_reg
= ROUND_REG (cum
, mode
);
2798 if (arg_reg
< NPARM_REGS
)
2799 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
2804 /* Returns the number of bytes of argument registers required to hold *part*
2805 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2806 the type is not known). If the argument fits entirely in the argument
2807 registers, or entirely on the stack, then 0 is returned. CUM is the
2808 number of argument registers already used by earlier parameters to
2812 mcore_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2813 tree type
, bool named
)
2815 int reg
= ROUND_REG (*cum
, mode
);
2820 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2823 /* REG is not the *hardware* register number of the register that holds
2824 the argument, it is the *argument* register number. So for example,
2825 the first argument to a function goes in argument register 0, which
2826 translates (for the MCore) into hardware register 2. The second
2827 argument goes into argument register 1, which translates into hardware
2828 register 3, and so on. NPARM_REGS is the number of argument registers
2829 supported by the target, not the maximum hardware register number of
2831 if (reg
>= NPARM_REGS
)
2834 /* If the argument fits entirely in registers, return 0. */
2835 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
2838 /* The argument overflows the number of available argument registers.
2839 Compute how many argument registers have not yet been assigned to
2840 hold an argument. */
2841 reg
= NPARM_REGS
- reg
;
2843 /* Return partially in registers and partially on the stack. */
2844 return reg
* UNITS_PER_WORD
;
2847 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2850 mcore_dllexport_name_p (const char * symbol
)
2852 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
2855 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2858 mcore_dllimport_name_p (const char * symbol
)
2860 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
2863 /* Mark a DECL as being dllexport'd. */
2866 mcore_mark_dllexport (tree decl
)
2868 const char * oldname
;
2873 rtlname
= XEXP (DECL_RTL (decl
), 0);
2875 if (GET_CODE (rtlname
) == MEM
)
2876 rtlname
= XEXP (rtlname
, 0);
2877 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2878 oldname
= XSTR (rtlname
, 0);
2880 if (mcore_dllexport_name_p (oldname
))
2881 return; /* Already done. */
2883 newname
= XALLOCAVEC (char, strlen (oldname
) + 4);
2884 sprintf (newname
, "@e.%s", oldname
);
2886 /* We pass newname through get_identifier to ensure it has a unique
2887 address. RTL processing can sometimes peek inside the symbol ref
2888 and compare the string's addresses to see if two symbols are
2890 /* ??? At least I think that's why we do this. */
2891 idp
= get_identifier (newname
);
2893 XEXP (DECL_RTL (decl
), 0) =
2894 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2897 /* Mark a DECL as being dllimport'd. */
2900 mcore_mark_dllimport (tree decl
)
2902 const char * oldname
;
2908 rtlname
= XEXP (DECL_RTL (decl
), 0);
2910 if (GET_CODE (rtlname
) == MEM
)
2911 rtlname
= XEXP (rtlname
, 0);
2912 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2913 oldname
= XSTR (rtlname
, 0);
2915 gcc_assert (!mcore_dllexport_name_p (oldname
));
2916 if (mcore_dllimport_name_p (oldname
))
2917 return; /* Already done. */
2919 /* ??? One can well ask why we're making these checks here,
2920 and that would be a good question. */
2922 /* Imported variables can't be initialized. */
2923 if (TREE_CODE (decl
) == VAR_DECL
2924 && !DECL_VIRTUAL_P (decl
)
2925 && DECL_INITIAL (decl
))
2927 error ("initialized variable %q+D is marked dllimport", decl
);
2931 /* `extern' needn't be specified with dllimport.
2932 Specify `extern' now and hope for the best. Sigh. */
2933 if (TREE_CODE (decl
) == VAR_DECL
2934 /* ??? Is this test for vtables needed? */
2935 && !DECL_VIRTUAL_P (decl
))
2937 DECL_EXTERNAL (decl
) = 1;
2938 TREE_PUBLIC (decl
) = 1;
2941 newname
= XALLOCAVEC (char, strlen (oldname
) + 11);
2942 sprintf (newname
, "@i.__imp_%s", oldname
);
2944 /* We pass newname through get_identifier to ensure it has a unique
2945 address. RTL processing can sometimes peek inside the symbol ref
2946 and compare the string's addresses to see if two symbols are
2948 /* ??? At least I think that's why we do this. */
2949 idp
= get_identifier (newname
);
2951 newrtl
= gen_rtx_MEM (Pmode
,
2952 gen_rtx_SYMBOL_REF (Pmode
,
2953 IDENTIFIER_POINTER (idp
)));
2954 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2958 mcore_dllexport_p (tree decl
)
2960 if ( TREE_CODE (decl
) != VAR_DECL
2961 && TREE_CODE (decl
) != FUNCTION_DECL
)
2964 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
2968 mcore_dllimport_p (tree decl
)
2970 if ( TREE_CODE (decl
) != VAR_DECL
2971 && TREE_CODE (decl
) != FUNCTION_DECL
)
2974 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
2977 /* We must mark dll symbols specially. Definitions of dllexport'd objects
2978 install some info in the .drective (PE) or .exports (ELF) sections. */
2981 mcore_encode_section_info (tree decl
, rtx rtl ATTRIBUTE_UNUSED
, int first ATTRIBUTE_UNUSED
)
2983 /* Mark the decl so we can tell from the rtl whether the object is
2984 dllexport'd or dllimport'd. */
2985 if (mcore_dllexport_p (decl
))
2986 mcore_mark_dllexport (decl
);
2987 else if (mcore_dllimport_p (decl
))
2988 mcore_mark_dllimport (decl
);
2990 /* It might be that DECL has already been marked as dllimport, but
2991 a subsequent definition nullified that. The attribute is gone
2992 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
2993 else if ((TREE_CODE (decl
) == FUNCTION_DECL
2994 || TREE_CODE (decl
) == VAR_DECL
)
2995 && DECL_RTL (decl
) != NULL_RTX
2996 && GET_CODE (DECL_RTL (decl
)) == MEM
2997 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
2998 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
2999 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
3001 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
3002 tree idp
= get_identifier (oldname
+ 9);
3003 rtx newrtl
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
3005 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3007 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3008 ??? We leave these alone for now. */
3012 /* Undo the effects of the above. */
3015 mcore_strip_name_encoding (const char * str
)
3017 return str
+ (str
[0] == '@' ? 3 : 0);
3020 /* MCore specific attribute support.
3021 dllexport - for exporting a function/variable that will live in a dll
3022 dllimport - for importing a function/variable from a dll
3023 naked - do not create a function prologue/epilogue. */
3025 /* Handle a "naked" attribute; arguments as in
3026 struct attribute_spec.handler. */
3029 mcore_handle_naked_attribute (tree
* node
, tree name
, tree args ATTRIBUTE_UNUSED
,
3030 int flags ATTRIBUTE_UNUSED
, bool * no_add_attrs
)
3032 if (TREE_CODE (*node
) == FUNCTION_DECL
)
3034 /* PR14310 - don't complain about lack of return statement
3035 in naked functions. The solution here is a gross hack
3036 but this is the only way to solve the problem without
3037 adding a new feature to GCC. I did try submitting a patch
3038 that would add such a new feature, but it was (rightfully)
3039 rejected on the grounds that it was creeping featurism,
3040 so hence this code. */
3041 if (warn_return_type
)
3043 saved_warn_return_type
= warn_return_type
;
3044 warn_return_type
= 0;
3045 saved_warn_return_type_count
= 2;
3047 else if (saved_warn_return_type_count
)
3048 saved_warn_return_type_count
= 2;
3052 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3054 *no_add_attrs
= true;
3060 /* ??? It looks like this is PE specific? Oh well, this is what the
3061 old code did as well. */
3064 mcore_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
3069 const char * prefix
;
3071 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3073 /* Strip off any encoding in name. */
3074 name
= (* targetm
.strip_name_encoding
) (name
);
3076 /* The object is put in, for example, section .text$foo.
3077 The linker will then ultimately place them in .text
3078 (everything from the $ on is stripped). */
3079 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3081 /* For compatibility with EPOC, we ignore the fact that the
3082 section might have relocs against it. */
3083 else if (decl_readonly_section (decl
, 0))
3088 len
= strlen (name
) + strlen (prefix
);
3089 string
= XALLOCAVEC (char, len
+ 1);
3091 sprintf (string
, "%s%s", prefix
, name
);
3093 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
3097 mcore_naked_function_p (void)
3099 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3102 #ifdef OBJECT_FORMAT_ELF
3104 mcore_asm_named_section (const char *name
,
3105 unsigned int flags ATTRIBUTE_UNUSED
,
3106 tree decl ATTRIBUTE_UNUSED
)
3108 fprintf (asm_out_file
, "\t.section %s\n", name
);
3110 #endif /* OBJECT_FORMAT_ELF */
3112 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3115 mcore_external_libcall (rtx fun
)
3117 fprintf (asm_out_file
, "\t.import\t");
3118 assemble_name (asm_out_file
, XSTR (fun
, 0));
3119 fprintf (asm_out_file
, "\n");
3122 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3125 mcore_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3127 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
3128 return (size
== -1 || size
> 2 * UNITS_PER_WORD
);
3131 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE.
3132 Output assembler code for a block containing the constant parts
3133 of a trampoline, leaving space for the variable parts.
3135 On the MCore, the trampoline looks like:
3143 mcore_asm_trampoline_template (FILE *f
)
3145 fprintf (f
, "\t.short 0x7102\n");
3146 fprintf (f
, "\t.short 0x7d02\n");
3147 fprintf (f
, "\t.short 0x00cd\n");
3148 fprintf (f
, "\t.short 0x1e00\n");
3149 fprintf (f
, "\t.long 0\n");
3150 fprintf (f
, "\t.long 0\n");
3153 /* Worker function for TARGET_TRAMPOLINE_INIT. */
3156 mcore_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
3158 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3161 emit_block_move (m_tramp
, assemble_trampoline_template (),
3162 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
3164 mem
= adjust_address (m_tramp
, SImode
, 8);
3165 emit_move_insn (mem
, chain_value
);
3166 mem
= adjust_address (m_tramp
, SImode
, 12);
3167 emit_move_insn (mem
, fnaddr
);