1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
48 /* Maximum size we are allowed to grow the stack in a single operation.
49 If we want more, we must do it in increments of at most this size.
50 If this value is 0, we don't check at all. */
51 int mcore_stack_increment
= STACK_UNITS_MAXSTEP
;
53 /* For dumping information about frame sizes. */
54 char * mcore_current_function_name
= 0;
55 long mcore_current_compilation_timestamp
= 0;
57 /* Global variables for machine-dependent things. */
59 /* Saved operands from the last compare to use when we generate an scc
64 /* Provides the class number of the smallest class containing
66 const int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
68 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
69 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
70 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
71 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
72 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
75 /* Provide reg_class from a letter such as appears in the machine
77 const enum reg_class reg_class_from_letter
[] =
79 /* a */ LRW_REGS
, /* b */ ONLYR1_REGS
, /* c */ C_REGS
, /* d */ NO_REGS
,
80 /* e */ NO_REGS
, /* f */ NO_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
81 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ NO_REGS
, /* l */ NO_REGS
,
82 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
83 /* q */ NO_REGS
, /* r */ GENERAL_REGS
, /* s */ NO_REGS
, /* t */ NO_REGS
,
84 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ NO_REGS
, /* x */ ALL_REGS
,
85 /* y */ NO_REGS
, /* z */ NO_REGS
90 int arg_size
; /* Stdarg spills (bytes). */
91 int reg_size
; /* Non-volatile reg saves (bytes). */
92 int reg_mask
; /* Non-volatile reg saves. */
93 int local_size
; /* Locals. */
94 int outbound_size
; /* Arg overflow on calls out. */
98 /* Describe the steps we'll use to grow it. */
99 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
100 int growth
[MAX_STACK_GROWS
];
118 static void output_stack_adjust (int, int);
119 static int calc_live_regs (int *);
120 static int try_constant_tricks (long, HOST_WIDE_INT
*, HOST_WIDE_INT
*);
121 static const char * output_inline_const (enum machine_mode
, rtx
*);
122 static void layout_mcore_frame (struct mcore_frame
*);
123 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
, tree
, int *, int);
124 static cond_type
is_cond_candidate (rtx
);
125 static rtx
emit_new_cond_insn (rtx
, int);
126 static rtx
conditionalize_block (rtx
);
127 static void conditionalize_optimization (void);
128 static void mcore_reorg (void);
129 static rtx
handle_structs_in_regs (enum machine_mode
, const_tree
, int);
130 static void mcore_mark_dllexport (tree
);
131 static void mcore_mark_dllimport (tree
);
132 static int mcore_dllexport_p (tree
);
133 static int mcore_dllimport_p (tree
);
134 const struct attribute_spec mcore_attribute_table
[];
135 static tree
mcore_handle_naked_attribute (tree
*, tree
, tree
, int, bool *);
136 #ifdef OBJECT_FORMAT_ELF
137 static void mcore_asm_named_section (const char *,
140 static void mcore_unique_section (tree
, int);
141 static void mcore_encode_section_info (tree
, rtx
, int);
142 static const char *mcore_strip_name_encoding (const char *);
143 static int mcore_const_costs (rtx
, RTX_CODE
);
144 static int mcore_and_cost (rtx
);
145 static int mcore_ior_cost (rtx
);
146 static bool mcore_rtx_costs (rtx
, int, int, int *);
147 static void mcore_external_libcall (rtx
);
148 static bool mcore_return_in_memory (const_tree
, const_tree
);
149 static int mcore_arg_partial_bytes (CUMULATIVE_ARGS
*,
154 /* Initialize the GCC target structure. */
155 #undef TARGET_ASM_EXTERNAL_LIBCALL
156 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
158 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
159 #undef TARGET_MERGE_DECL_ATTRIBUTES
160 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
163 #ifdef OBJECT_FORMAT_ELF
164 #undef TARGET_ASM_UNALIGNED_HI_OP
165 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
166 #undef TARGET_ASM_UNALIGNED_SI_OP
167 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
170 #undef TARGET_ATTRIBUTE_TABLE
171 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
172 #undef TARGET_ASM_UNIQUE_SECTION
173 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
174 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
175 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
176 #undef TARGET_DEFAULT_TARGET_FLAGS
177 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
178 #undef TARGET_ENCODE_SECTION_INFO
179 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
180 #undef TARGET_STRIP_NAME_ENCODING
181 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
182 #undef TARGET_RTX_COSTS
183 #define TARGET_RTX_COSTS mcore_rtx_costs
184 #undef TARGET_ADDRESS_COST
185 #define TARGET_ADDRESS_COST hook_int_rtx_0
186 #undef TARGET_MACHINE_DEPENDENT_REORG
187 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
189 #undef TARGET_PROMOTE_FUNCTION_ARGS
190 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
191 #undef TARGET_PROMOTE_FUNCTION_RETURN
192 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
193 #undef TARGET_PROMOTE_PROTOTYPES
194 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
196 #undef TARGET_RETURN_IN_MEMORY
197 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
198 #undef TARGET_MUST_PASS_IN_STACK
199 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
200 #undef TARGET_PASS_BY_REFERENCE
201 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
202 #undef TARGET_ARG_PARTIAL_BYTES
203 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
205 #undef TARGET_SETUP_INCOMING_VARARGS
206 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
208 struct gcc_target targetm
= TARGET_INITIALIZER
;
210 /* Adjust the stack and return the number of bytes taken to do it. */
212 output_stack_adjust (int direction
, int size
)
214 /* If extending stack a lot, we do it incrementally. */
215 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
217 rtx tmp
= gen_rtx_REG (SImode
, 1);
220 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
223 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
224 memref
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
225 MEM_VOLATILE_P (memref
) = 1;
226 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
227 size
-= mcore_stack_increment
;
229 while (size
> mcore_stack_increment
);
231 /* SIZE is now the residual for the last adjustment,
232 which doesn't require a probe. */
238 rtx val
= GEN_INT (size
);
242 rtx nval
= gen_rtx_REG (SImode
, 1);
243 emit_insn (gen_movsi (nval
, val
));
248 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
250 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
256 /* Work out the registers which need to be saved,
257 both as a mask and a count. */
260 calc_live_regs (int * count
)
263 int live_regs_mask
= 0;
267 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
269 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
272 live_regs_mask
|= (1 << reg
);
276 return live_regs_mask
;
279 /* Print the operand address in x to the stream. */
282 mcore_print_operand_address (FILE * stream
, rtx x
)
284 switch (GET_CODE (x
))
287 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
292 rtx base
= XEXP (x
, 0);
293 rtx index
= XEXP (x
, 1);
295 if (GET_CODE (base
) != REG
)
297 /* Ensure that BASE is a register (one of them must be). */
303 switch (GET_CODE (index
))
306 fprintf (stream
, "(%s," HOST_WIDE_INT_PRINT_DEC
")",
307 reg_names
[REGNO(base
)], INTVAL (index
));
318 output_addr_const (stream
, x
);
323 /* Print operand x (an rtx) in assembler syntax to file stream
324 according to modifier code.
326 'R' print the next register or memory location along, i.e. the lsw in
328 'O' print a constant without the #
329 'M' print a constant as its negative
330 'P' print log2 of a power of two
331 'Q' print log2 of an inverse of a power of two
332 'U' print register for ldm/stm instruction
333 'X' print byte number for xtrbN instruction. */
336 mcore_print_operand (FILE * stream
, rtx x
, int code
)
342 fprintf (asm_out_file
, "32");
344 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
347 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) & 0xffffffff));
350 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
353 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
356 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, - INTVAL (x
));
359 /* Next location along in memory or register. */
360 switch (GET_CODE (x
))
363 fputs (reg_names
[REGNO (x
) + 1], (stream
));
366 mcore_print_operand_address
367 (stream
, XEXP (adjust_address (x
, SImode
, 4), 0));
374 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
375 reg_names
[REGNO (x
) + 3]);
378 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
381 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, 3 - INTVAL (x
) / 8);
385 switch (GET_CODE (x
))
388 fputs (reg_names
[REGNO (x
)], (stream
));
391 output_address (XEXP (x
, 0));
394 output_addr_const (stream
, x
);
401 /* What does a constant cost ? */
404 mcore_const_costs (rtx exp
, enum rtx_code code
)
406 HOST_WIDE_INT val
= INTVAL (exp
);
408 /* Easy constants. */
409 if ( CONST_OK_FOR_I (val
)
410 || CONST_OK_FOR_M (val
)
411 || CONST_OK_FOR_N (val
)
412 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
415 && ( CONST_OK_FOR_M (~val
)
416 || CONST_OK_FOR_N (~val
)))
418 else if (code
== PLUS
419 && ( CONST_OK_FOR_I (-val
)
420 || CONST_OK_FOR_M (-val
)
421 || CONST_OK_FOR_N (-val
)))
427 /* What does an and instruction cost - we do this b/c immediates may
428 have been relaxed. We want to ensure that cse will cse relaxed immeds
429 out. Otherwise we'll get bad code (multiple reloads of the same const). */
432 mcore_and_cost (rtx x
)
436 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
439 val
= INTVAL (XEXP (x
, 1));
441 /* Do it directly. */
442 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
444 /* Takes one instruction to load. */
445 else if (const_ok_for_mcore (val
))
447 /* Takes two instructions to load. */
448 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
451 /* Takes a lrw to load. */
455 /* What does an or cost - see and_cost(). */
458 mcore_ior_cost (rtx x
)
462 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
465 val
= INTVAL (XEXP (x
, 1));
467 /* Do it directly with bclri. */
468 if (CONST_OK_FOR_M (val
))
470 /* Takes one instruction to load. */
471 else if (const_ok_for_mcore (val
))
473 /* Takes two instructions to load. */
474 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
477 /* Takes a lrw to load. */
482 mcore_rtx_costs (rtx x
, int code
, int outer_code
, int * total
)
487 *total
= mcore_const_costs (x
, outer_code
);
499 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
503 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
512 *total
= COSTS_N_INSNS (100);
520 /* Check to see if a comparison against a constant can be made more efficient
521 by incrementing/decrementing the constant to get one that is more efficient
525 mcore_modify_comparison (enum rtx_code code
)
527 rtx op1
= arch_compare_op1
;
529 if (GET_CODE (op1
) == CONST_INT
)
531 HOST_WIDE_INT val
= INTVAL (op1
);
536 if (CONST_OK_FOR_J (val
+ 1))
538 arch_compare_op1
= GEN_INT (val
+ 1);
551 /* Prepare the operands for a comparison. */
554 mcore_gen_compare_reg (enum rtx_code code
)
556 rtx op0
= arch_compare_op0
;
557 rtx op1
= arch_compare_op1
;
558 rtx cc_reg
= gen_rtx_REG (CCmode
, CC_REG
);
560 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
561 op1
= force_reg (SImode
, op1
);
563 /* cmpnei: 0-31 (K immediate)
564 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
567 case EQ
: /* Use inverted condition, cmpne. */
571 case NE
: /* Use normal condition, cmpne. */
572 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
573 op1
= force_reg (SImode
, op1
);
576 case LE
: /* Use inverted condition, reversed cmplt. */
580 case GT
: /* Use normal condition, reversed cmplt. */
581 if (GET_CODE (op1
) == CONST_INT
)
582 op1
= force_reg (SImode
, op1
);
585 case GE
: /* Use inverted condition, cmplt. */
589 case LT
: /* Use normal condition, cmplt. */
590 if (GET_CODE (op1
) == CONST_INT
&&
591 /* covered by btsti x,31. */
593 ! CONST_OK_FOR_J (INTVAL (op1
)))
594 op1
= force_reg (SImode
, op1
);
597 case GTU
: /* Use inverted condition, cmple. */
598 /* Unsigned > 0 is the same as != 0, but we need to invert the
599 condition, so we want to set code = EQ. This cannot be done
600 however, as the mcore does not support such a test. Instead
601 we cope with this case in the "bgtu" pattern itself so we
602 should never reach this point. */
603 gcc_assert (GET_CODE (op1
) != CONST_INT
|| INTVAL (op1
) != 0);
607 case LEU
: /* Use normal condition, reversed cmphs. */
608 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
609 op1
= force_reg (SImode
, op1
);
612 case LTU
: /* Use inverted condition, cmphs. */
616 case GEU
: /* Use normal condition, cmphs. */
617 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
618 op1
= force_reg (SImode
, op1
);
625 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
)));
631 mcore_symbolic_address_p (rtx x
)
633 switch (GET_CODE (x
))
640 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
641 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
642 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
648 /* Functions to output assembly code for a function call. */
651 mcore_output_call (rtx operands
[], int index
)
653 static char buffer
[20];
654 rtx addr
= operands
[index
];
660 gcc_assert (mcore_current_function_name
);
662 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
666 sprintf (buffer
, "jsr\t%%%d", index
);
672 gcc_assert (mcore_current_function_name
);
673 gcc_assert (GET_CODE (addr
) == SYMBOL_REF
);
675 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
679 sprintf (buffer
, "jbsr\t%%%d", index
);
685 /* Can we load a constant with a single instruction ? */
688 const_ok_for_mcore (HOST_WIDE_INT value
)
690 if (value
>= 0 && value
<= 127)
693 /* Try exact power of two. */
694 if (CONST_OK_FOR_M (value
))
697 /* Try exact power of two - 1. */
698 if (CONST_OK_FOR_N (value
) && value
!= -1)
704 /* Can we load a constant inline with up to 2 instructions ? */
707 mcore_const_ok_for_inline (HOST_WIDE_INT value
)
711 return try_constant_tricks (value
, & x
, & y
) > 0;
714 /* Are we loading the constant using a not ? */
717 mcore_const_trick_uses_not (HOST_WIDE_INT value
)
721 return try_constant_tricks (value
, & x
, & y
) == 2;
724 /* Try tricks to load a constant inline and return the trick number if
725 success (0 is non-inlinable).
728 1: single instruction (do the usual thing)
729 2: single insn followed by a 'not'
730 3: single insn followed by a subi
731 4: single insn followed by an addi
732 5: single insn followed by rsubi
733 6: single insn followed by bseti
734 7: single insn followed by bclri
735 8: single insn followed by rotli
736 9: single insn followed by lsli
737 10: single insn followed by ixh
738 11: single insn followed by ixw. */
741 try_constant_tricks (HOST_WIDE_INT value
, HOST_WIDE_INT
* x
, HOST_WIDE_INT
* y
)
744 unsigned HOST_WIDE_INT bit
, shf
, rot
;
746 if (const_ok_for_mcore (value
))
747 return 1; /* Do the usual thing. */
749 if (! TARGET_HARDLIT
)
752 if (const_ok_for_mcore (~value
))
758 for (i
= 1; i
<= 32; i
++)
760 if (const_ok_for_mcore (value
- i
))
768 if (const_ok_for_mcore (value
+ i
))
779 for (i
= 0; i
<= 31; i
++)
781 if (const_ok_for_mcore (i
- value
))
789 if (const_ok_for_mcore (value
& ~bit
))
796 if (const_ok_for_mcore (value
| bit
))
810 for (i
= 1; i
< 31; i
++)
814 /* MCore has rotate left. */
818 rot
|= c
; /* Simulate rotate. */
820 if (const_ok_for_mcore (rot
))
829 shf
= 0; /* Can't use logical shift, low order bit is one. */
833 if (shf
!= 0 && const_ok_for_mcore (shf
))
842 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
849 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
859 /* Check whether reg is dead at first. This is done by searching ahead
860 for either the next use (i.e., reg is live), a death note, or a set of
861 reg. Don't just use dead_or_set_p() since reload does not always mark
862 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
863 can ignore subregs by extracting the actual register. BRC */
866 mcore_is_dead (rtx first
, rtx reg
)
870 /* For mcore, subregs can't live independently of their parent regs. */
871 if (GET_CODE (reg
) == SUBREG
)
872 reg
= SUBREG_REG (reg
);
874 /* Dies immediately. */
875 if (dead_or_set_p (first
, reg
))
878 /* Look for conclusive evidence of live/death, otherwise we have
879 to assume that it is live. */
880 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
882 if (GET_CODE (insn
) == JUMP_INSN
)
883 return 0; /* We lose track, assume it is alive. */
885 else if (GET_CODE(insn
) == CALL_INSN
)
887 /* Call's might use it for target or register parms. */
888 if (reg_referenced_p (reg
, PATTERN (insn
))
889 || find_reg_fusage (insn
, USE
, reg
))
891 else if (dead_or_set_p (insn
, reg
))
894 else if (GET_CODE (insn
) == INSN
)
896 if (reg_referenced_p (reg
, PATTERN (insn
)))
898 else if (dead_or_set_p (insn
, reg
))
903 /* No conclusive evidence either way, we cannot take the chance
904 that control flow hid the use from us -- "I'm not dead yet". */
908 /* Count the number of ones in mask. */
911 mcore_num_ones (HOST_WIDE_INT mask
)
913 /* A trick to count set bits recently posted on comp.compilers. */
914 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
915 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
916 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
917 mask
= ((mask
>> 8) + mask
);
919 return (mask
+ (mask
>> 16)) & 0xff;
922 /* Count the number of zeros in mask. */
925 mcore_num_zeros (HOST_WIDE_INT mask
)
927 return 32 - mcore_num_ones (mask
);
930 /* Determine byte being masked. */
933 mcore_byte_offset (unsigned int mask
)
935 if (mask
== 0x00ffffffL
)
937 else if (mask
== 0xff00ffffL
)
939 else if (mask
== 0xffff00ffL
)
941 else if (mask
== 0xffffff00L
)
947 /* Determine halfword being masked. */
950 mcore_halfword_offset (unsigned int mask
)
952 if (mask
== 0x0000ffffL
)
954 else if (mask
== 0xffff0000L
)
960 /* Output a series of bseti's corresponding to mask. */
963 mcore_output_bseti (rtx dst
, int mask
)
968 out_operands
[0] = dst
;
970 for (bit
= 0; bit
< 32; bit
++)
972 if ((mask
& 0x1) == 0x1)
974 out_operands
[1] = GEN_INT (bit
);
976 output_asm_insn ("bseti\t%0,%1", out_operands
);
984 /* Output a series of bclri's corresponding to mask. */
987 mcore_output_bclri (rtx dst
, int mask
)
992 out_operands
[0] = dst
;
994 for (bit
= 0; bit
< 32; bit
++)
996 if ((mask
& 0x1) == 0x0)
998 out_operands
[1] = GEN_INT (bit
);
1000 output_asm_insn ("bclri\t%0,%1", out_operands
);
1009 /* Output a conditional move of two constants that are +/- 1 within each
1010 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1011 really worth the effort. */
1014 mcore_output_cmov (rtx operands
[], int cmp_t
, const char * test
)
1016 HOST_WIDE_INT load_value
;
1017 HOST_WIDE_INT adjust_value
;
1018 rtx out_operands
[4];
1020 out_operands
[0] = operands
[0];
1022 /* Check to see which constant is loadable. */
1023 if (const_ok_for_mcore (INTVAL (operands
[1])))
1025 out_operands
[1] = operands
[1];
1026 out_operands
[2] = operands
[2];
1028 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1030 out_operands
[1] = operands
[2];
1031 out_operands
[2] = operands
[1];
1033 /* Complement test since constants are swapped. */
1034 cmp_t
= (cmp_t
== 0);
1036 load_value
= INTVAL (out_operands
[1]);
1037 adjust_value
= INTVAL (out_operands
[2]);
1039 /* First output the test if folded into the pattern. */
1042 output_asm_insn (test
, operands
);
1044 /* Load the constant - for now, only support constants that can be
1045 generated with a single instruction. maybe add general inlinable
1046 constants later (this will increase the # of patterns since the
1047 instruction sequence has a different length attribute). */
1048 if (load_value
>= 0 && load_value
<= 127)
1049 output_asm_insn ("movi\t%0,%1", out_operands
);
1050 else if (CONST_OK_FOR_M (load_value
))
1051 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1052 else if (CONST_OK_FOR_N (load_value
))
1053 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1055 /* Output the constant adjustment. */
1056 if (load_value
> adjust_value
)
1059 output_asm_insn ("decf\t%0", out_operands
);
1061 output_asm_insn ("dect\t%0", out_operands
);
1066 output_asm_insn ("incf\t%0", out_operands
);
1068 output_asm_insn ("inct\t%0", out_operands
);
1074 /* Outputs the peephole for moving a constant that gets not'ed followed
1075 by an and (i.e. combine the not and the and into andn). BRC */
1078 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
1081 rtx out_operands
[3];
1082 const char * load_op
;
1086 trick_no
= try_constant_tricks (INTVAL (operands
[1]), &x
, &y
);
1087 gcc_assert (trick_no
== 2);
1089 out_operands
[0] = operands
[0];
1090 out_operands
[1] = GEN_INT (x
);
1091 out_operands
[2] = operands
[2];
1093 if (x
>= 0 && x
<= 127)
1094 load_op
= "movi\t%0,%1";
1096 /* Try exact power of two. */
1097 else if (CONST_OK_FOR_M (x
))
1098 load_op
= "bgeni\t%0,%P1";
1100 /* Try exact power of two - 1. */
1101 else if (CONST_OK_FOR_N (x
))
1102 load_op
= "bmaski\t%0,%N1";
1106 load_op
= "BADMOVI-andn\t%0, %1";
1110 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1111 output_asm_insn (buf
, out_operands
);
1116 /* Output an inline constant. */
1119 output_inline_const (enum machine_mode mode
, rtx operands
[])
1121 HOST_WIDE_INT x
= 0, y
= 0;
1123 rtx out_operands
[3];
1126 const char *dst_fmt
;
1127 HOST_WIDE_INT value
;
1129 value
= INTVAL (operands
[1]);
1131 trick_no
= try_constant_tricks (value
, &x
, &y
);
1132 /* lrw's are handled separately: Large inlinable constants never get
1133 turned into lrw's. Our caller uses try_constant_tricks to back
1134 off to an lrw rather than calling this routine. */
1135 gcc_assert (trick_no
!= 0);
1140 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1141 out_operands
[0] = operands
[0];
1142 out_operands
[1] = GEN_INT (x
);
1145 out_operands
[2] = GEN_INT (y
);
1147 /* Select dst format based on mode. */
1148 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1153 if (x
>= 0 && x
<= 127)
1154 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1156 /* Try exact power of two. */
1157 else if (CONST_OK_FOR_M (x
))
1158 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1160 /* Try exact power of two - 1. */
1161 else if (CONST_OK_FOR_N (x
))
1162 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1166 sprintf (load_op
, "BADMOVI-inline_const %s, %%1", dst_fmt
);
1173 strcpy (buf
, load_op
);
1176 sprintf (buf
, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1179 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1182 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1185 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1186 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1189 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1192 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1195 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1198 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1201 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1204 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1210 output_asm_insn (buf
, out_operands
);
1215 /* Output a move of a word or less value. */
1218 mcore_output_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
1219 enum machine_mode mode ATTRIBUTE_UNUSED
)
1221 rtx dst
= operands
[0];
1222 rtx src
= operands
[1];
1224 if (GET_CODE (dst
) == REG
)
1226 if (GET_CODE (src
) == REG
)
1228 if (REGNO (src
) == CC_REG
) /* r-c */
1231 return "mov\t%0,%1"; /* r-r*/
1233 else if (GET_CODE (src
) == MEM
)
1235 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1236 return "lrw\t%0,[%1]"; /* a-R */
1238 switch (GET_MODE (src
)) /* r-m */
1241 return "ldw\t%0,%1";
1243 return "ld.h\t%0,%1";
1245 return "ld.b\t%0,%1";
1250 else if (GET_CODE (src
) == CONST_INT
)
1254 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1255 return "movi\t%0,%1";
1256 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1257 return "bgeni\t%0,%P1\t// %1 %x1";
1258 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1259 return "bmaski\t%0,%N1\t// %1 %x1";
1260 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1261 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1263 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1266 return "lrw\t%0, %1"; /* Into the literal pool. */
1268 else if (GET_CODE (dst
) == MEM
) /* m-r */
1269 switch (GET_MODE (dst
))
1272 return "stw\t%1,%0";
1274 return "st.h\t%1,%0";
1276 return "st.b\t%1,%0";
1284 /* Return a sequence of instructions to perform DI or DF move.
1285 Since the MCORE cannot move a DI or DF in one instruction, we have
1286 to take care when we see overlapping source and dest registers. */
1289 mcore_output_movedouble (rtx operands
[], enum machine_mode mode ATTRIBUTE_UNUSED
)
1291 rtx dst
= operands
[0];
1292 rtx src
= operands
[1];
1294 if (GET_CODE (dst
) == REG
)
1296 if (GET_CODE (src
) == REG
)
1298 int dstreg
= REGNO (dst
);
1299 int srcreg
= REGNO (src
);
1301 /* Ensure the second source not overwritten. */
1302 if (srcreg
+ 1 == dstreg
)
1303 return "mov %R0,%R1\n\tmov %0,%1";
1305 return "mov %0,%1\n\tmov %R0,%R1";
1307 else if (GET_CODE (src
) == MEM
)
1309 rtx memexp
= memexp
= XEXP (src
, 0);
1310 int dstreg
= REGNO (dst
);
1313 if (GET_CODE (memexp
) == LABEL_REF
)
1314 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1315 else if (GET_CODE (memexp
) == REG
)
1316 basereg
= REGNO (memexp
);
1317 else if (GET_CODE (memexp
) == PLUS
)
1319 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1320 basereg
= REGNO (XEXP (memexp
, 0));
1321 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1322 basereg
= REGNO (XEXP (memexp
, 1));
1329 /* ??? length attribute is wrong here. */
1330 if (dstreg
== basereg
)
1332 /* Just load them in reverse order. */
1333 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1335 /* XXX: alternative: move basereg to basereg+1
1336 and then fall through. */
1339 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1341 else if (GET_CODE (src
) == CONST_INT
)
1343 if (TARGET_LITTLE_END
)
1345 if (CONST_OK_FOR_I (INTVAL (src
)))
1346 output_asm_insn ("movi %0,%1", operands
);
1347 else if (CONST_OK_FOR_M (INTVAL (src
)))
1348 output_asm_insn ("bgeni %0,%P1", operands
);
1349 else if (CONST_OK_FOR_N (INTVAL (src
)))
1350 output_asm_insn ("bmaski %0,%N1", operands
);
1354 if (INTVAL (src
) < 0)
1355 return "bmaski %R0,32";
1357 return "movi %R0,0";
1361 if (CONST_OK_FOR_I (INTVAL (src
)))
1362 output_asm_insn ("movi %R0,%1", operands
);
1363 else if (CONST_OK_FOR_M (INTVAL (src
)))
1364 output_asm_insn ("bgeni %R0,%P1", operands
);
1365 else if (CONST_OK_FOR_N (INTVAL (src
)))
1366 output_asm_insn ("bmaski %R0,%N1", operands
);
1370 if (INTVAL (src
) < 0)
1371 return "bmaski %0,32";
1379 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1380 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1385 /* Predicates used by the templates. */
1388 mcore_arith_S_operand (rtx op
)
1390 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1396 /* Expand insert bit field. BRC */
1399 mcore_expand_insv (rtx operands
[])
1401 int width
= INTVAL (operands
[1]);
1402 int posn
= INTVAL (operands
[2]);
1404 rtx mreg
, sreg
, ereg
;
1406 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1407 for width==1 must be removed. Look around line 368. This is something
1408 we really want the md part to do. */
1409 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1411 /* Do directly with bseti or bclri. */
1412 /* RBE: 2/97 consider only low bit of constant. */
1413 if ((INTVAL (operands
[3]) & 1) == 0)
1415 mask
= ~(1 << posn
);
1416 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1417 gen_rtx_AND (SImode
, operands
[0], GEN_INT (mask
))));
1422 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1423 gen_rtx_IOR (SImode
, operands
[0], GEN_INT (mask
))));
1429 /* Look at some bit-field placements that we aren't interested
1430 in handling ourselves, unless specifically directed to do so. */
1431 if (! TARGET_W_FIELD
)
1432 return 0; /* Generally, give up about now. */
1434 if (width
== 8 && posn
% 8 == 0)
1435 /* Byte sized and aligned; let caller break it up. */
1438 if (width
== 16 && posn
% 16 == 0)
1439 /* Short sized and aligned; let caller break it up. */
1442 /* The general case - we can do this a little bit better than what the
1443 machine independent part tries. This will get rid of all the subregs
1444 that mess up constant folding in combine when working with relaxed
1447 /* If setting the entire field, do it directly. */
1448 if (GET_CODE (operands
[3]) == CONST_INT
1449 && INTVAL (operands
[3]) == ((1 << width
) - 1))
1451 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1452 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1453 gen_rtx_IOR (SImode
, operands
[0], mreg
)));
1457 /* Generate the clear mask. */
1458 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1460 /* Clear the field, to overlay it later with the source. */
1461 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1462 gen_rtx_AND (SImode
, operands
[0], mreg
)));
1464 /* If the source is constant 0, we've nothing to add back. */
1465 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1468 /* XXX: Should we worry about more games with constant values?
1469 We've covered the high profile: set/clear single-bit and many-bit
1470 fields. How often do we see "arbitrary bit pattern" constants? */
1471 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1473 /* Extract src as same width as dst (needed for signed values). We
1474 always have to do this since we widen everything to SImode.
1475 We don't have to mask if we're shifting this up against the
1476 MSB of the register (e.g., the shift will push out any hi-order
1478 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1480 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1481 emit_insn (gen_rtx_SET (SImode
, sreg
,
1482 gen_rtx_AND (SImode
, sreg
, ereg
)));
1485 /* Insert source value in dest. */
1487 emit_insn (gen_rtx_SET (SImode
, sreg
,
1488 gen_rtx_ASHIFT (SImode
, sreg
, GEN_INT (posn
))));
1490 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1491 gen_rtx_IOR (SImode
, operands
[0], sreg
)));
1496 /* ??? Block move stuff stolen from m88k. This code has not been
1497 verified for correctness. */
1499 /* Emit code to perform a block move. Choose the best method.
1501 OPERANDS[0] is the destination.
1502 OPERANDS[1] is the source.
1503 OPERANDS[2] is the size.
1504 OPERANDS[3] is the alignment safe to use. */
1506 /* Emit code to perform a block move with an offset sequence of ldw/st
1507 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1508 known constants. DEST and SRC are registers. OFFSET is the known
1509 starting point for the output pattern. */
1511 static const enum machine_mode mode_from_align
[] =
1513 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1517 block_move_sequence (rtx dst_mem
, rtx src_mem
, int size
, int align
)
1520 enum machine_mode mode
[2];
1529 x
= XEXP (dst_mem
, 0);
1532 x
= force_reg (Pmode
, x
);
1533 dst_mem
= replace_equiv_address (dst_mem
, x
);
1536 x
= XEXP (src_mem
, 0);
1539 x
= force_reg (Pmode
, x
);
1540 src_mem
= replace_equiv_address (src_mem
, x
);
1543 active
[0] = active
[1] = false;
1554 next_amount
= (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
1555 next_amount
= MIN (next_amount
, align
);
1557 amount
[next
] = next_amount
;
1558 mode
[next
] = mode_from_align
[next_amount
];
1559 temp
[next
] = gen_reg_rtx (mode
[next
]);
1561 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1562 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1564 offset_ld
+= next_amount
;
1565 size
-= next_amount
;
1566 active
[next
] = true;
1571 active
[phase
] = false;
1573 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1574 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1576 offset_st
+= amount
[phase
];
1579 while (active
[next
]);
1583 mcore_expand_block_move (rtx
*operands
)
1585 HOST_WIDE_INT align
, bytes
, max
;
1587 if (GET_CODE (operands
[2]) != CONST_INT
)
1590 bytes
= INTVAL (operands
[2]);
1591 align
= INTVAL (operands
[3]);
1620 block_move_sequence (operands
[0], operands
[1], bytes
, align
);
1628 /* Code to generate prologue and epilogue sequences. */
1629 static int number_of_regs_before_varargs
;
1631 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1632 for a varargs function. */
1633 static int current_function_anonymous_args
;
1635 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1636 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1637 #define ADDI_REACH (32) /* Maximum addi operand. */
1640 layout_mcore_frame (struct mcore_frame
* infp
)
1649 unsigned int growths
;
1652 /* Might have to spill bytes to re-assemble a big argument that
1653 was passed partially in registers and partially on the stack. */
1654 nbytes
= crtl
->args
.pretend_args_size
;
1656 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1657 if (current_function_anonymous_args
)
1658 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
1660 infp
->arg_size
= nbytes
;
1662 /* How much space to save non-volatile registers we stomp. */
1663 infp
->reg_mask
= calc_live_regs (& n
);
1664 infp
->reg_size
= n
* 4;
1666 /* And the rest of it... locals and space for overflowed outbounds. */
1667 infp
->local_size
= get_frame_size ();
1668 infp
->outbound_size
= crtl
->outgoing_args_size
;
1670 /* Make sure we have a whole number of words for the locals. */
1671 if (infp
->local_size
% STACK_BYTES
)
1672 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
1674 /* Only thing we know we have to pad is the outbound space, since
1675 we've aligned our locals assuming that base of locals is aligned. */
1676 infp
->pad_local
= 0;
1678 infp
->pad_outbound
= 0;
1679 if (infp
->outbound_size
% STACK_BYTES
)
1680 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
1682 /* Now we see how we want to stage the prologue so that it does
1683 the most appropriate stack growth and register saves to either:
1685 (2) reduce instruction space, or
1686 (3) reduce stack space. */
1687 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
1688 infp
->growth
[i
] = 0;
1690 regarg
= infp
->reg_size
+ infp
->arg_size
;
1691 localregarg
= infp
->local_size
+ regarg
;
1692 localreg
= infp
->local_size
+ infp
->reg_size
;
1693 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
1696 /* XXX: Consider one where we consider localregarg + outbound too! */
1698 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1699 use stw's with offsets and buy the frame in one shot. */
1700 if (localregarg
<= ADDI_REACH
1701 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1703 /* Make sure we'll be aligned. */
1704 if (localregarg
% STACK_BYTES
)
1705 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1707 step
= localregarg
+ infp
->pad_reg
;
1708 infp
->reg_offset
= infp
->local_size
;
1710 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
1713 infp
->reg_offset
+= outbounds
;
1717 infp
->arg_offset
= step
- 4;
1718 infp
->growth
[growths
++] = step
;
1719 infp
->reg_growth
= growths
;
1720 infp
->local_growth
= growths
;
1722 /* If we haven't already folded it in. */
1724 infp
->growth
[growths
++] = outbounds
;
1729 /* Frame can't be done with a single subi, but can be done with 2
1730 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1731 shift some of the stack purchase into the first subi, so both are
1732 single instructions. */
1733 if (localregarg
<= STORE_REACH
1734 && (infp
->local_size
> ADDI_REACH
)
1735 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1739 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1740 if (localregarg
% STACK_BYTES
)
1741 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1743 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
1744 step
= ADDI_REACH
; /* As much up front as we can. */
1748 /* XXX: Consider whether step will still be aligned; we believe so. */
1749 infp
->arg_offset
= step
- 4;
1750 infp
->growth
[growths
++] = step
;
1751 infp
->reg_growth
= growths
;
1752 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
1755 /* Can we fold in any space required for outbounds? */
1756 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
1762 /* Get the rest of the locals in place. */
1764 infp
->growth
[growths
++] = step
;
1765 infp
->local_growth
= growths
;
1770 /* Finish off if we need to do so. */
1772 infp
->growth
[growths
++] = outbounds
;
1777 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1778 Then we buy the rest of the frame in 1 or 2 steps depending on
1779 whether we need a frame pointer. */
1780 if ((regarg
% STACK_BYTES
) == 0)
1782 infp
->growth
[growths
++] = regarg
;
1783 infp
->reg_growth
= growths
;
1784 infp
->arg_offset
= regarg
- 4;
1785 infp
->reg_offset
= 0;
1787 if (infp
->local_size
% STACK_BYTES
)
1788 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1790 step
= infp
->local_size
+ infp
->pad_local
;
1792 if (!frame_pointer_needed
)
1798 infp
->growth
[growths
++] = step
;
1799 infp
->local_growth
= growths
;
1801 /* If there's any left to be done. */
1803 infp
->growth
[growths
++] = outbounds
;
1808 /* XXX: optimizations that we'll want to play with....
1809 -- regarg is not aligned, but it's a small number of registers;
1810 use some of localsize so that regarg is aligned and then
1811 save the registers. */
1813 /* Simple encoding; plods down the stack buying the pieces as it goes.
1814 -- does not optimize space consumption.
1815 -- does not attempt to optimize instruction counts.
1816 -- but it is safe for all alignments. */
1817 if (regarg
% STACK_BYTES
!= 0)
1818 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
1820 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
1821 infp
->reg_growth
= growths
;
1822 infp
->arg_offset
= infp
->growth
[0] - 4;
1823 infp
->reg_offset
= 0;
1825 if (frame_pointer_needed
)
1827 if (infp
->local_size
% STACK_BYTES
!= 0)
1828 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1830 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
1831 infp
->local_growth
= growths
;
1833 infp
->growth
[growths
++] = outbounds
;
1837 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
1838 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
1840 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
1841 infp
->local_growth
= growths
;
1844 /* Anything else that we've forgotten?, plus a few consistency checks. */
1846 assert (infp
->reg_offset
>= 0);
1847 assert (growths
<= MAX_STACK_GROWS
);
1849 for (i
= 0; i
< growths
; i
++)
1850 gcc_assert (!(infp
->growth
[i
] % STACK_BYTES
));
1853 /* Define the offset between two registers, one to be eliminated, and
1854 the other its replacement, at the start of a routine. */
1857 mcore_initial_elimination_offset (int from
, int to
)
1861 struct mcore_frame fi
;
1863 layout_mcore_frame (& fi
);
1866 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
1868 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
1870 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1873 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1874 return above_frame
+ below_frame
;
1876 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1882 /* Keep track of some information about varargs for the prolog. */
1885 mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*args_so_far
,
1886 enum machine_mode mode
, tree type
,
1887 int * ptr_pretend_size ATTRIBUTE_UNUSED
,
1888 int second_time ATTRIBUTE_UNUSED
)
1890 current_function_anonymous_args
= 1;
1892 /* We need to know how many argument registers are used before
1893 the varargs start, so that we can push the remaining argument
1894 registers during the prologue. */
1895 number_of_regs_before_varargs
= *args_so_far
+ mcore_num_arg_regs (mode
, type
);
1897 /* There is a bug somewhere in the arg handling code.
1898 Until I can find it this workaround always pushes the
1899 last named argument onto the stack. */
1900 number_of_regs_before_varargs
= *args_so_far
;
1902 /* The last named argument may be split between argument registers
1903 and the stack. Allow for this here. */
1904 if (number_of_regs_before_varargs
> NPARM_REGS
)
1905 number_of_regs_before_varargs
= NPARM_REGS
;
1909 mcore_expand_prolog (void)
1911 struct mcore_frame fi
;
1912 int space_allocated
= 0;
1915 /* Find out what we're doing. */
1916 layout_mcore_frame (&fi
);
1918 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
1919 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
1923 /* Emit a symbol for this routine's frame size. */
1926 x
= DECL_RTL (current_function_decl
);
1928 gcc_assert (GET_CODE (x
) == MEM
);
1932 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1934 if (mcore_current_function_name
)
1935 free (mcore_current_function_name
);
1937 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
1939 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
1941 if (cfun
->calls_alloca
)
1942 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
1945 We're looking at how the 8byte alignment affects stack layout
1946 and where we had to pad things. This emits information we can
1947 extract which tells us about frame sizes and the like. */
1948 fprintf (asm_out_file
,
1949 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
1950 mcore_current_function_name
,
1951 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
1952 fi
.local_size
, fi
.outbound_size
,
1953 frame_pointer_needed
);
1956 if (mcore_naked_function_p ())
1959 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
1960 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
1962 /* If we have a parameter passed partially in regs and partially in memory,
1963 the registers will have been stored to memory already in function.c. So
1964 we only need to do something here for varargs functions. */
1965 if (fi
.arg_size
!= 0 && crtl
->args
.pretend_args_size
== 0)
1968 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
1969 int remaining
= fi
.arg_size
;
1971 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
1973 emit_insn (gen_movsi
1974 (gen_rtx_MEM (SImode
,
1975 plus_constant (stack_pointer_rtx
, offset
)),
1976 gen_rtx_REG (SImode
, rn
)));
1980 /* Do we need another stack adjustment before we do the register saves? */
1981 if (growth
< fi
.reg_growth
)
1982 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
1984 if (fi
.reg_size
!= 0)
1987 int offs
= fi
.reg_offset
;
1989 for (i
= 15; i
>= 0; i
--)
1991 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
1995 while (fi
.reg_mask
& (1 << first_reg
))
1999 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2000 gen_rtx_REG (SImode
, first_reg
),
2001 GEN_INT (16 - first_reg
)));
2003 i
-= (15 - first_reg
);
2004 offs
+= (16 - first_reg
) * 4;
2006 else if (fi
.reg_mask
& (1 << i
))
2008 emit_insn (gen_movsi
2009 (gen_rtx_MEM (SImode
,
2010 plus_constant (stack_pointer_rtx
, offs
)),
2011 gen_rtx_REG (SImode
, i
)));
2017 /* Figure the locals + outbounds. */
2018 if (frame_pointer_needed
)
2020 /* If we haven't already purchased to 'fp'. */
2021 if (growth
< fi
.local_growth
)
2022 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2024 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2026 /* ... and then go any remaining distance for outbounds, etc. */
2027 if (fi
.growth
[growth
])
2028 output_stack_adjust (-1, fi
.growth
[growth
++]);
2032 if (growth
< fi
.local_growth
)
2033 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2034 if (fi
.growth
[growth
])
2035 output_stack_adjust (-1, fi
.growth
[growth
++]);
2040 mcore_expand_epilog (void)
2042 struct mcore_frame fi
;
2045 int growth
= MAX_STACK_GROWS
- 1 ;
2048 /* Find out what we're doing. */
2049 layout_mcore_frame(&fi
);
2051 if (mcore_naked_function_p ())
2054 /* If we had a frame pointer, restore the sp from that. */
2055 if (frame_pointer_needed
)
2057 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2058 growth
= fi
.local_growth
- 1;
2062 /* XXX: while loop should accumulate and do a single sell. */
2063 while (growth
>= fi
.local_growth
)
2065 if (fi
.growth
[growth
] != 0)
2066 output_stack_adjust (1, fi
.growth
[growth
]);
2071 /* Make sure we've shrunk stack back to the point where the registers
2072 were laid down. This is typically 0/1 iterations. Then pull the
2073 register save information back off the stack. */
2074 while (growth
>= fi
.reg_growth
)
2075 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2077 offs
= fi
.reg_offset
;
2079 for (i
= 15; i
>= 0; i
--)
2081 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2085 /* Find the starting register. */
2088 while (fi
.reg_mask
& (1 << first_reg
))
2093 emit_insn (gen_load_multiple (gen_rtx_REG (SImode
, first_reg
),
2094 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2095 GEN_INT (16 - first_reg
)));
2097 i
-= (15 - first_reg
);
2098 offs
+= (16 - first_reg
) * 4;
2100 else if (fi
.reg_mask
& (1 << i
))
2102 emit_insn (gen_movsi
2103 (gen_rtx_REG (SImode
, i
),
2104 gen_rtx_MEM (SImode
,
2105 plus_constant (stack_pointer_rtx
, offs
))));
2110 /* Give back anything else. */
2111 /* XXX: Should accumulate total and then give it back. */
2113 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2116 /* This code is borrowed from the SH port. */
2118 /* The MCORE cannot load a large constant into a register, constants have to
2119 come from a pc relative load. The reference of a pc relative load
2120 instruction must be less than 1k in front of the instruction. This
2121 means that we often have to dump a constant inside a function, and
2122 generate code to branch around it.
2124 It is important to minimize this, since the branches will slow things
2125 down and make things bigger.
2127 Worst case code looks like:
2143 We fix this by performing a scan before scheduling, which notices which
2144 instructions need to have their operands fetched from the constant table
2145 and builds the table.
2149 scan, find an instruction which needs a pcrel move. Look forward, find the
2150 last barrier which is within MAX_COUNT bytes of the requirement.
2151 If there isn't one, make one. Process all the instructions between
2152 the find and the barrier.
2154 In the above example, we can tell that L3 is within 1k of L1, so
2155 the first move can be shrunk from the 2 insn+constant sequence into
2156 just 1 insn, and the constant moved to L3 to make:
2166 Then the second move becomes the target for the shortening process. */
2170 rtx value
; /* Value in table. */
2171 rtx label
; /* Label of value. */
2174 /* The maximum number of constants that can fit into one pool, since
2175 the pc relative range is 0...1020 bytes and constants are at least 4
2176 bytes long. We subtract 4 from the range to allow for the case where
2177 we need to add a branch/align before the constant pool. */
2179 #define MAX_COUNT 1016
2180 #define MAX_POOL_SIZE (MAX_COUNT/4)
2181 static pool_node pool_vector
[MAX_POOL_SIZE
];
2182 static int pool_size
;
2184 /* Dump out any constants accumulated in the final pass. These
2185 will only be labels. */
2188 mcore_output_jump_label_table (void)
2194 fprintf (asm_out_file
, "\t.align 2\n");
2196 for (i
= 0; i
< pool_size
; i
++)
2198 pool_node
* p
= pool_vector
+ i
;
2200 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2202 output_asm_insn (".long %0", &p
->value
);
2211 /* Check whether insn is a candidate for a conditional. */
2214 is_cond_candidate (rtx insn
)
2216 /* The only things we conditionalize are those that can be directly
2217 changed into a conditional. Only bother with SImode items. If
2218 we wanted to be a little more aggressive, we could also do other
2219 modes such as DImode with reg-reg move or load 0. */
2220 if (GET_CODE (insn
) == INSN
)
2222 rtx pat
= PATTERN (insn
);
2225 if (GET_CODE (pat
) != SET
)
2228 dst
= XEXP (pat
, 0);
2230 if ((GET_CODE (dst
) != REG
&&
2231 GET_CODE (dst
) != SUBREG
) ||
2232 GET_MODE (dst
) != SImode
)
2235 src
= XEXP (pat
, 1);
2237 if ((GET_CODE (src
) == REG
||
2238 (GET_CODE (src
) == SUBREG
&&
2239 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2240 GET_MODE (src
) == SImode
)
2241 return COND_MOV_INSN
;
2242 else if (GET_CODE (src
) == CONST_INT
&&
2244 return COND_CLR_INSN
;
2245 else if (GET_CODE (src
) == PLUS
&&
2246 (GET_CODE (XEXP (src
, 0)) == REG
||
2247 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2248 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2249 GET_MODE (XEXP (src
, 0)) == SImode
&&
2250 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2251 INTVAL (XEXP (src
, 1)) == 1)
2252 return COND_INC_INSN
;
2253 else if (((GET_CODE (src
) == MINUS
&&
2254 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2255 INTVAL( XEXP (src
, 1)) == 1) ||
2256 (GET_CODE (src
) == PLUS
&&
2257 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2258 INTVAL (XEXP (src
, 1)) == -1)) &&
2259 (GET_CODE (XEXP (src
, 0)) == REG
||
2260 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2261 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2262 GET_MODE (XEXP (src
, 0)) == SImode
)
2263 return COND_DEC_INSN
;
2265 /* Some insns that we don't bother with:
2266 (set (rx:DI) (ry:DI))
2267 (set (rx:DI) (const_int 0))
2271 else if (GET_CODE (insn
) == JUMP_INSN
&&
2272 GET_CODE (PATTERN (insn
)) == SET
&&
2273 GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2274 return COND_BRANCH_INSN
;
2279 /* Emit a conditional version of insn and replace the old insn with the
2280 new one. Return the new insn if emitted. */
2283 emit_new_cond_insn (rtx insn
, int cond
)
2289 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2292 pat
= PATTERN (insn
);
2294 if (GET_CODE (insn
) == INSN
)
2296 dst
= SET_DEST (pat
);
2297 src
= SET_SRC (pat
);
2301 dst
= JUMP_LABEL (insn
);
2310 c_insn
= gen_movt0 (dst
, src
, dst
);
2312 c_insn
= gen_movt0 (dst
, dst
, src
);
2317 c_insn
= gen_incscc (dst
, dst
);
2319 c_insn
= gen_incscc_false (dst
, dst
);
2324 c_insn
= gen_decscc (dst
, dst
);
2326 c_insn
= gen_decscc_false (dst
, dst
);
2329 case COND_BRANCH_INSN
:
2331 c_insn
= gen_branch_true (dst
);
2333 c_insn
= gen_branch_false (dst
);
2340 /* Only copy the notes if they exist. */
2341 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2343 /* We really don't need to bother with the notes and links at this
2344 point, but go ahead and save the notes. This will help is_dead()
2345 when applying peepholes (links don't matter since they are not
2346 used any more beyond this point for the mcore). */
2347 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2350 if (num
== COND_BRANCH_INSN
)
2352 /* For jumps, we need to be a little bit careful and emit the new jump
2353 before the old one and to update the use count for the target label.
2354 This way, the barrier following the old (uncond) jump will get
2355 deleted, but the label won't. */
2356 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2358 ++ LABEL_NUSES (dst
);
2360 JUMP_LABEL (c_insn
) = dst
;
2363 c_insn
= emit_insn_after (c_insn
, insn
);
2370 /* Attempt to change a basic block into a series of conditional insns. This
2371 works by taking the branch at the end of the 1st block and scanning for the
2372 end of the 2nd block. If all instructions in the 2nd block have cond.
2373 versions and the label at the start of block 3 is the same as the target
2374 from the branch at block 1, then conditionalize all insn in block 2 using
2375 the inverse condition of the branch at block 1. (Note I'm bending the
2376 definition of basic block here.)
2380 bt L2 <-- end of block 1 (delete)
2383 br L3 <-- end of block 2
2385 L2: ... <-- start of block 3 (NUSES==1)
2396 we can delete the L2 label if NUSES==1 and re-apply the optimization
2397 starting at the last instruction of block 2. This may allow an entire
2398 if-then-else statement to be conditionalized. BRC */
2400 conditionalize_block (rtx first
)
2404 rtx end_blk_1_br
= 0;
2405 rtx end_blk_2_insn
= 0;
2406 rtx start_blk_3_lab
= 0;
2412 /* Check that the first insn is a candidate conditional jump. This is
2413 the one that we'll eliminate. If not, advance to the next insn to
2415 if (GET_CODE (first
) != JUMP_INSN
||
2416 GET_CODE (PATTERN (first
)) != SET
||
2417 GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2418 return NEXT_INSN (first
);
2420 /* Extract some information we need. */
2421 end_blk_1_br
= first
;
2422 br_pat
= PATTERN (end_blk_1_br
);
2424 /* Complement the condition since we use the reverse cond. for the insns. */
2425 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2427 /* Determine what kind of branch we have. */
2428 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2430 /* A normal branch, so extract label out of first arm. */
2431 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2435 /* An inverse branch, so extract the label out of the 2nd arm
2436 and complement the condition. */
2438 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2441 /* Scan forward for the start of block 2: it must start with a
2442 label and that label must be the same as the branch target
2443 label from block 1. We don't care about whether block 2 actually
2444 ends with a branch or a label (an uncond. branch is
2445 conditionalizable). */
2446 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2450 code
= GET_CODE (insn
);
2452 /* Look for the label at the start of block 3. */
2453 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2456 /* Skip barriers, notes, and conditionalizable insns. If the
2457 insn is not conditionalizable or makes this optimization fail,
2458 just return the next insn so we can start over from that point. */
2459 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2460 return NEXT_INSN (insn
);
2462 /* Remember the last real insn before the label (i.e. end of block 2). */
2463 if (code
== JUMP_INSN
|| code
== INSN
)
2466 end_blk_2_insn
= insn
;
2473 /* It is possible for this optimization to slow performance if the blocks
2474 are long. This really depends upon whether the branch is likely taken
2475 or not. If the branch is taken, we slow performance in many cases. But,
2476 if the branch is not taken, we always help performance (for a single
2477 block, but for a double block (i.e. when the optimization is re-applied)
2478 this is not true since the 'right thing' depends on the overall length of
2479 the collapsed block). As a compromise, don't apply this optimization on
2480 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2481 the best threshold depends on the latencies of the instructions (i.e.,
2482 the branch penalty). */
2483 if (optimize
> 1 && blk_size
> 2)
2486 /* At this point, we've found the start of block 3 and we know that
2487 it is the destination of the branch from block 1. Also, all
2488 instructions in the block 2 are conditionalizable. So, apply the
2489 conditionalization and delete the branch. */
2490 start_blk_3_lab
= insn
;
2492 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2493 insn
= NEXT_INSN (insn
))
2497 if (INSN_DELETED_P (insn
))
2500 /* Try to form a conditional variant of the instruction and emit it. */
2501 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2503 if (end_blk_2_insn
== insn
)
2504 end_blk_2_insn
= newinsn
;
2510 /* Note whether we will delete the label starting blk 3 when the jump
2511 gets deleted. If so, we want to re-apply this optimization at the
2512 last real instruction right before the label. */
2513 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2515 start_blk_3_lab
= 0;
2518 /* ??? we probably should redistribute the death notes for this insn, esp.
2519 the death of cc, but it doesn't really matter this late in the game.
2520 The peepholes all use is_dead() which will find the correct death
2521 regardless of whether there is a note. */
2522 delete_insn (end_blk_1_br
);
2524 if (! start_blk_3_lab
)
2525 return end_blk_2_insn
;
2527 /* Return the insn right after the label at the start of block 3. */
2528 return NEXT_INSN (start_blk_3_lab
);
2531 /* Apply the conditionalization of blocks optimization. This is the
2532 outer loop that traverses through the insns scanning for a branch
2533 that signifies an opportunity to apply the optimization. Note that
2534 this optimization is applied late. If we could apply it earlier,
2535 say before cse 2, it may expose more optimization opportunities.
2536 but, the pay back probably isn't really worth the effort (we'd have
2537 to update all reg/flow/notes/links/etc to make it work - and stick it
2538 in before cse 2). */
2541 conditionalize_optimization (void)
2545 for (insn
= get_insns (); insn
; insn
= conditionalize_block (insn
))
2549 static int saved_warn_return_type
= -1;
2550 static int saved_warn_return_type_count
= 0;
2552 /* This is to handle loads from the constant pool. */
2557 /* Reset this variable. */
2558 current_function_anonymous_args
= 0;
2560 /* Restore the warn_return_type if it has been altered. */
2561 if (saved_warn_return_type
!= -1)
2563 /* Only restore the value if we have reached another function.
2564 The test of warn_return_type occurs in final_function () in
2565 c-decl.c a long time after the code for the function is generated,
2566 so we need a counter to tell us when we have finished parsing that
2567 function and can restore the flag. */
2568 if (--saved_warn_return_type_count
== 0)
2570 warn_return_type
= saved_warn_return_type
;
2571 saved_warn_return_type
= -1;
2578 /* Conditionalize blocks where we can. */
2579 conditionalize_optimization ();
2581 /* Literal pool generation is now pushed off until the assembler. */
2585 /* Return true if X is something that can be moved directly into r15. */
2588 mcore_r15_operand_p (rtx x
)
2590 switch (GET_CODE (x
))
2593 return mcore_const_ok_for_inline (INTVAL (x
));
2605 /* Implement SECONDARY_RELOAD_CLASS. If CLASS contains r15, and we can't
2606 directly move X into it, use r1-r14 as a temporary. */
2609 mcore_secondary_reload_class (enum reg_class
class,
2610 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2612 if (TEST_HARD_REG_BIT (reg_class_contents
[class], 15)
2613 && !mcore_r15_operand_p (x
))
2618 /* Return the reg_class to use when reloading the rtx X into the class
2619 CLASS. If X is too complex to move directly into r15, prefer to
2620 use LRW_REGS instead. */
2623 mcore_reload_class (rtx x
, enum reg_class
class)
2625 if (reg_class_subset_p (LRW_REGS
, class) && !mcore_r15_operand_p (x
))
2631 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2632 register. Note that the current version doesn't worry about whether
2633 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2634 in r2 matches an SImode in r2. Might think in the future about whether
2635 we want to be able to say something about modes. */
2638 mcore_is_same_reg (rtx x
, rtx y
)
2640 /* Strip any and all of the subreg wrappers. */
2641 while (GET_CODE (x
) == SUBREG
)
2644 while (GET_CODE (y
) == SUBREG
)
2647 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
2654 mcore_override_options (void)
2656 /* Only the m340 supports little endian code. */
2657 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
2658 target_flags
|= MASK_M340
;
2661 /* Compute the number of word sized registers needed to
2662 hold a function argument of mode MODE and type TYPE. */
2665 mcore_num_arg_regs (enum machine_mode mode
, const_tree type
)
2669 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2672 if (type
&& mode
== BLKmode
)
2673 size
= int_size_in_bytes (type
);
2675 size
= GET_MODE_SIZE (mode
);
2677 return ROUND_ADVANCE (size
);
2681 handle_structs_in_regs (enum machine_mode mode
, const_tree type
, int reg
)
2685 /* The MCore ABI defines that a structure whose size is not a whole multiple
2686 of bytes is passed packed into registers (or spilled onto the stack if
2687 not enough registers are available) with the last few bytes of the
2688 structure being packed, left-justified, into the last register/stack slot.
2689 GCC handles this correctly if the last word is in a stack slot, but we
2690 have to generate a special, PARALLEL RTX if the last word is in an
2691 argument register. */
2693 && TYPE_MODE (type
) == BLKmode
2694 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
2695 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
2696 && (size
% UNITS_PER_WORD
!= 0)
2697 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
2699 rtx arg_regs
[NPARM_REGS
];
2704 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
2707 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
2708 GEN_INT (nregs
* UNITS_PER_WORD
));
2712 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2713 assert (ARRAY_SIZE (arg_regs
) == 6);
2714 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
2715 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
2717 result
= gen_rtx_PARALLEL (mode
, rtvec
);
2721 return gen_rtx_REG (mode
, reg
);
2725 mcore_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
2727 enum machine_mode mode
;
2730 mode
= TYPE_MODE (valtype
);
2732 mode
= promote_mode (valtype
, mode
, &unsigned_p
, 1);
2734 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
2737 /* Define where to put the arguments to a function.
2738 Value is zero to push the argument on the stack,
2739 or a hard register in which to store the argument.
2741 MODE is the argument's machine mode.
2742 TYPE is the data type of the argument (as a tree).
2743 This is null for libcalls where that information may
2745 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2746 the preceding args and about the function being called.
2747 NAMED is nonzero if this argument is a named parameter
2748 (otherwise it is an extra parameter matching an ellipsis).
2750 On MCore the first args are normally in registers
2751 and the rest are pushed. Any arg that starts within the first
2752 NPARM_REGS words is at least partially passed in a register unless
2753 its data type forbids. */
2756 mcore_function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
,
2757 tree type
, int named
)
2761 if (! named
|| mode
== VOIDmode
)
2764 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2767 arg_reg
= ROUND_REG (cum
, mode
);
2769 if (arg_reg
< NPARM_REGS
)
2770 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
2775 /* Returns the number of bytes of argument registers required to hold *part*
2776 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2777 the type is not known). If the argument fits entirely in the argument
2778 registers, or entirely on the stack, then 0 is returned. CUM is the
2779 number of argument registers already used by earlier parameters to
2783 mcore_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2784 tree type
, bool named
)
2786 int reg
= ROUND_REG (*cum
, mode
);
2791 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2794 /* REG is not the *hardware* register number of the register that holds
2795 the argument, it is the *argument* register number. So for example,
2796 the first argument to a function goes in argument register 0, which
2797 translates (for the MCore) into hardware register 2. The second
2798 argument goes into argument register 1, which translates into hardware
2799 register 3, and so on. NPARM_REGS is the number of argument registers
2800 supported by the target, not the maximum hardware register number of
2802 if (reg
>= NPARM_REGS
)
2805 /* If the argument fits entirely in registers, return 0. */
2806 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
2809 /* The argument overflows the number of available argument registers.
2810 Compute how many argument registers have not yet been assigned to
2811 hold an argument. */
2812 reg
= NPARM_REGS
- reg
;
2814 /* Return partially in registers and partially on the stack. */
2815 return reg
* UNITS_PER_WORD
;
2818 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2821 mcore_dllexport_name_p (const char * symbol
)
2823 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
2826 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2829 mcore_dllimport_name_p (const char * symbol
)
2831 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
2834 /* Mark a DECL as being dllexport'd. */
2837 mcore_mark_dllexport (tree decl
)
2839 const char * oldname
;
2844 rtlname
= XEXP (DECL_RTL (decl
), 0);
2846 if (GET_CODE (rtlname
) == MEM
)
2847 rtlname
= XEXP (rtlname
, 0);
2848 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2849 oldname
= XSTR (rtlname
, 0);
2851 if (mcore_dllexport_name_p (oldname
))
2852 return; /* Already done. */
2854 newname
= XALLOCAVEC (char, strlen (oldname
) + 4);
2855 sprintf (newname
, "@e.%s", oldname
);
2857 /* We pass newname through get_identifier to ensure it has a unique
2858 address. RTL processing can sometimes peek inside the symbol ref
2859 and compare the string's addresses to see if two symbols are
2861 /* ??? At least I think that's why we do this. */
2862 idp
= get_identifier (newname
);
2864 XEXP (DECL_RTL (decl
), 0) =
2865 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2868 /* Mark a DECL as being dllimport'd. */
2871 mcore_mark_dllimport (tree decl
)
2873 const char * oldname
;
2879 rtlname
= XEXP (DECL_RTL (decl
), 0);
2881 if (GET_CODE (rtlname
) == MEM
)
2882 rtlname
= XEXP (rtlname
, 0);
2883 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2884 oldname
= XSTR (rtlname
, 0);
2886 gcc_assert (!mcore_dllexport_name_p (oldname
));
2887 if (mcore_dllimport_name_p (oldname
))
2888 return; /* Already done. */
2890 /* ??? One can well ask why we're making these checks here,
2891 and that would be a good question. */
2893 /* Imported variables can't be initialized. */
2894 if (TREE_CODE (decl
) == VAR_DECL
2895 && !DECL_VIRTUAL_P (decl
)
2896 && DECL_INITIAL (decl
))
2898 error ("initialized variable %q+D is marked dllimport", decl
);
2902 /* `extern' needn't be specified with dllimport.
2903 Specify `extern' now and hope for the best. Sigh. */
2904 if (TREE_CODE (decl
) == VAR_DECL
2905 /* ??? Is this test for vtables needed? */
2906 && !DECL_VIRTUAL_P (decl
))
2908 DECL_EXTERNAL (decl
) = 1;
2909 TREE_PUBLIC (decl
) = 1;
2912 newname
= XALLOCAVEC (char, strlen (oldname
) + 11);
2913 sprintf (newname
, "@i.__imp_%s", oldname
);
2915 /* We pass newname through get_identifier to ensure it has a unique
2916 address. RTL processing can sometimes peek inside the symbol ref
2917 and compare the string's addresses to see if two symbols are
2919 /* ??? At least I think that's why we do this. */
2920 idp
= get_identifier (newname
);
2922 newrtl
= gen_rtx_MEM (Pmode
,
2923 gen_rtx_SYMBOL_REF (Pmode
,
2924 IDENTIFIER_POINTER (idp
)));
2925 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2929 mcore_dllexport_p (tree decl
)
2931 if ( TREE_CODE (decl
) != VAR_DECL
2932 && TREE_CODE (decl
) != FUNCTION_DECL
)
2935 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
2939 mcore_dllimport_p (tree decl
)
2941 if ( TREE_CODE (decl
) != VAR_DECL
2942 && TREE_CODE (decl
) != FUNCTION_DECL
)
2945 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
2948 /* We must mark dll symbols specially. Definitions of dllexport'd objects
2949 install some info in the .drective (PE) or .exports (ELF) sections. */
2952 mcore_encode_section_info (tree decl
, rtx rtl ATTRIBUTE_UNUSED
, int first ATTRIBUTE_UNUSED
)
2954 /* Mark the decl so we can tell from the rtl whether the object is
2955 dllexport'd or dllimport'd. */
2956 if (mcore_dllexport_p (decl
))
2957 mcore_mark_dllexport (decl
);
2958 else if (mcore_dllimport_p (decl
))
2959 mcore_mark_dllimport (decl
);
2961 /* It might be that DECL has already been marked as dllimport, but
2962 a subsequent definition nullified that. The attribute is gone
2963 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
2964 else if ((TREE_CODE (decl
) == FUNCTION_DECL
2965 || TREE_CODE (decl
) == VAR_DECL
)
2966 && DECL_RTL (decl
) != NULL_RTX
2967 && GET_CODE (DECL_RTL (decl
)) == MEM
2968 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
2969 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
2970 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
2972 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
2973 tree idp
= get_identifier (oldname
+ 9);
2974 rtx newrtl
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2976 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2978 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
2979 ??? We leave these alone for now. */
2983 /* Undo the effects of the above. */
2986 mcore_strip_name_encoding (const char * str
)
2988 return str
+ (str
[0] == '@' ? 3 : 0);
2991 /* MCore specific attribute support.
2992 dllexport - for exporting a function/variable that will live in a dll
2993 dllimport - for importing a function/variable from a dll
2994 naked - do not create a function prologue/epilogue. */
2996 const struct attribute_spec mcore_attribute_table
[] =
2998 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2999 { "dllexport", 0, 0, true, false, false, NULL
},
3000 { "dllimport", 0, 0, true, false, false, NULL
},
3001 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
},
3002 { NULL
, 0, 0, false, false, false, NULL
}
3005 /* Handle a "naked" attribute; arguments as in
3006 struct attribute_spec.handler. */
3009 mcore_handle_naked_attribute (tree
* node
, tree name
, tree args ATTRIBUTE_UNUSED
,
3010 int flags ATTRIBUTE_UNUSED
, bool * no_add_attrs
)
3012 if (TREE_CODE (*node
) == FUNCTION_DECL
)
3014 /* PR14310 - don't complain about lack of return statement
3015 in naked functions. The solution here is a gross hack
3016 but this is the only way to solve the problem without
3017 adding a new feature to GCC. I did try submitting a patch
3018 that would add such a new feature, but it was (rightfully)
3019 rejected on the grounds that it was creeping featurism,
3020 so hence this code. */
3021 if (warn_return_type
)
3023 saved_warn_return_type
= warn_return_type
;
3024 warn_return_type
= 0;
3025 saved_warn_return_type_count
= 2;
3027 else if (saved_warn_return_type_count
)
3028 saved_warn_return_type_count
= 2;
3032 warning (OPT_Wattributes
, "%qs attribute only applies to functions",
3033 IDENTIFIER_POINTER (name
));
3034 *no_add_attrs
= true;
3040 /* ??? It looks like this is PE specific? Oh well, this is what the
3041 old code did as well. */
3044 mcore_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
3049 const char * prefix
;
3051 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3053 /* Strip off any encoding in name. */
3054 name
= (* targetm
.strip_name_encoding
) (name
);
3056 /* The object is put in, for example, section .text$foo.
3057 The linker will then ultimately place them in .text
3058 (everything from the $ on is stripped). */
3059 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3061 /* For compatibility with EPOC, we ignore the fact that the
3062 section might have relocs against it. */
3063 else if (decl_readonly_section (decl
, 0))
3068 len
= strlen (name
) + strlen (prefix
);
3069 string
= XALLOCAVEC (char, len
+ 1);
3071 sprintf (string
, "%s%s", prefix
, name
);
3073 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
3077 mcore_naked_function_p (void)
3079 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3082 #ifdef OBJECT_FORMAT_ELF
3084 mcore_asm_named_section (const char *name
,
3085 unsigned int flags ATTRIBUTE_UNUSED
,
3086 tree decl ATTRIBUTE_UNUSED
)
3088 fprintf (asm_out_file
, "\t.section %s\n", name
);
3090 #endif /* OBJECT_FORMAT_ELF */
3092 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3095 mcore_external_libcall (rtx fun
)
3097 fprintf (asm_out_file
, "\t.import\t");
3098 assemble_name (asm_out_file
, XSTR (fun
, 0));
3099 fprintf (asm_out_file
, "\n");
3102 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3105 mcore_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3107 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
3108 return (size
== -1 || size
> 2 * UNITS_PER_WORD
);