1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008,
3 2009 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
49 /* Maximum size we are allowed to grow the stack in a single operation.
50 If we want more, we must do it in increments of at most this size.
51 If this value is 0, we don't check at all. */
52 int mcore_stack_increment
= STACK_UNITS_MAXSTEP
;
54 /* For dumping information about frame sizes. */
55 char * mcore_current_function_name
= 0;
56 long mcore_current_compilation_timestamp
= 0;
58 /* Global variables for machine-dependent things. */
60 /* Provides the class number of the smallest class containing
62 const int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
64 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
65 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
66 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
67 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
68 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
71 /* Provide reg_class from a letter such as appears in the machine
73 const enum reg_class reg_class_from_letter
[] =
75 /* a */ LRW_REGS
, /* b */ ONLYR1_REGS
, /* c */ C_REGS
, /* d */ NO_REGS
,
76 /* e */ NO_REGS
, /* f */ NO_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
77 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ NO_REGS
, /* l */ NO_REGS
,
78 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
79 /* q */ NO_REGS
, /* r */ GENERAL_REGS
, /* s */ NO_REGS
, /* t */ NO_REGS
,
80 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ NO_REGS
, /* x */ ALL_REGS
,
81 /* y */ NO_REGS
, /* z */ NO_REGS
86 int arg_size
; /* Stdarg spills (bytes). */
87 int reg_size
; /* Non-volatile reg saves (bytes). */
88 int reg_mask
; /* Non-volatile reg saves. */
89 int local_size
; /* Locals. */
90 int outbound_size
; /* Arg overflow on calls out. */
94 /* Describe the steps we'll use to grow it. */
95 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
96 int growth
[MAX_STACK_GROWS
];
114 static void output_stack_adjust (int, int);
115 static int calc_live_regs (int *);
116 static int try_constant_tricks (long, HOST_WIDE_INT
*, HOST_WIDE_INT
*);
117 static const char * output_inline_const (enum machine_mode
, rtx
*);
118 static void layout_mcore_frame (struct mcore_frame
*);
119 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
, tree
, int *, int);
120 static cond_type
is_cond_candidate (rtx
);
121 static rtx
emit_new_cond_insn (rtx
, int);
122 static rtx
conditionalize_block (rtx
);
123 static void conditionalize_optimization (void);
124 static void mcore_reorg (void);
125 static rtx
handle_structs_in_regs (enum machine_mode
, const_tree
, int);
126 static void mcore_mark_dllexport (tree
);
127 static void mcore_mark_dllimport (tree
);
128 static int mcore_dllexport_p (tree
);
129 static int mcore_dllimport_p (tree
);
130 EXPORTED_CONST
struct attribute_spec mcore_attribute_table
[];
131 static tree
mcore_handle_naked_attribute (tree
*, tree
, tree
, int, bool *);
132 #ifdef OBJECT_FORMAT_ELF
133 static void mcore_asm_named_section (const char *,
136 static void mcore_unique_section (tree
, int);
137 static void mcore_encode_section_info (tree
, rtx
, int);
138 static const char *mcore_strip_name_encoding (const char *);
139 static int mcore_const_costs (rtx
, RTX_CODE
);
140 static int mcore_and_cost (rtx
);
141 static int mcore_ior_cost (rtx
);
142 static bool mcore_rtx_costs (rtx
, int, int, int *, bool);
143 static void mcore_external_libcall (rtx
);
144 static bool mcore_return_in_memory (const_tree
, const_tree
);
145 static int mcore_arg_partial_bytes (CUMULATIVE_ARGS
*,
150 /* Initialize the GCC target structure. */
151 #undef TARGET_ASM_EXTERNAL_LIBCALL
152 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
154 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
155 #undef TARGET_MERGE_DECL_ATTRIBUTES
156 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
159 #ifdef OBJECT_FORMAT_ELF
160 #undef TARGET_ASM_UNALIGNED_HI_OP
161 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
162 #undef TARGET_ASM_UNALIGNED_SI_OP
163 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
166 #undef TARGET_ATTRIBUTE_TABLE
167 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
168 #undef TARGET_ASM_UNIQUE_SECTION
169 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
170 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
171 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
172 #undef TARGET_DEFAULT_TARGET_FLAGS
173 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
174 #undef TARGET_ENCODE_SECTION_INFO
175 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
176 #undef TARGET_STRIP_NAME_ENCODING
177 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
178 #undef TARGET_RTX_COSTS
179 #define TARGET_RTX_COSTS mcore_rtx_costs
180 #undef TARGET_ADDRESS_COST
181 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
182 #undef TARGET_MACHINE_DEPENDENT_REORG
183 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
185 #undef TARGET_PROMOTE_FUNCTION_ARGS
186 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
187 #undef TARGET_PROMOTE_FUNCTION_RETURN
188 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
189 #undef TARGET_PROMOTE_PROTOTYPES
190 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
192 #undef TARGET_RETURN_IN_MEMORY
193 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
194 #undef TARGET_MUST_PASS_IN_STACK
195 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
196 #undef TARGET_PASS_BY_REFERENCE
197 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
198 #undef TARGET_ARG_PARTIAL_BYTES
199 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
201 #undef TARGET_SETUP_INCOMING_VARARGS
202 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
204 struct gcc_target targetm
= TARGET_INITIALIZER
;
206 /* Adjust the stack and return the number of bytes taken to do it. */
208 output_stack_adjust (int direction
, int size
)
210 /* If extending stack a lot, we do it incrementally. */
211 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
213 rtx tmp
= gen_rtx_REG (SImode
, 1);
216 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
219 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
220 memref
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
221 MEM_VOLATILE_P (memref
) = 1;
222 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
223 size
-= mcore_stack_increment
;
225 while (size
> mcore_stack_increment
);
227 /* SIZE is now the residual for the last adjustment,
228 which doesn't require a probe. */
234 rtx val
= GEN_INT (size
);
238 rtx nval
= gen_rtx_REG (SImode
, 1);
239 emit_insn (gen_movsi (nval
, val
));
244 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
246 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
252 /* Work out the registers which need to be saved,
253 both as a mask and a count. */
256 calc_live_regs (int * count
)
259 int live_regs_mask
= 0;
263 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
265 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
268 live_regs_mask
|= (1 << reg
);
272 return live_regs_mask
;
275 /* Print the operand address in x to the stream. */
278 mcore_print_operand_address (FILE * stream
, rtx x
)
280 switch (GET_CODE (x
))
283 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
288 rtx base
= XEXP (x
, 0);
289 rtx index
= XEXP (x
, 1);
291 if (GET_CODE (base
) != REG
)
293 /* Ensure that BASE is a register (one of them must be). */
299 switch (GET_CODE (index
))
302 fprintf (stream
, "(%s," HOST_WIDE_INT_PRINT_DEC
")",
303 reg_names
[REGNO(base
)], INTVAL (index
));
314 output_addr_const (stream
, x
);
319 /* Print operand x (an rtx) in assembler syntax to file stream
320 according to modifier code.
322 'R' print the next register or memory location along, i.e. the lsw in
324 'O' print a constant without the #
325 'M' print a constant as its negative
326 'P' print log2 of a power of two
327 'Q' print log2 of an inverse of a power of two
328 'U' print register for ldm/stm instruction
329 'X' print byte number for xtrbN instruction. */
332 mcore_print_operand (FILE * stream
, rtx x
, int code
)
338 fprintf (asm_out_file
, "32");
340 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
343 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) & 0xffffffff));
346 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
349 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
352 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, - INTVAL (x
));
355 /* Next location along in memory or register. */
356 switch (GET_CODE (x
))
359 fputs (reg_names
[REGNO (x
) + 1], (stream
));
362 mcore_print_operand_address
363 (stream
, XEXP (adjust_address (x
, SImode
, 4), 0));
370 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
371 reg_names
[REGNO (x
) + 3]);
374 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
377 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, 3 - INTVAL (x
) / 8);
381 switch (GET_CODE (x
))
384 fputs (reg_names
[REGNO (x
)], (stream
));
387 output_address (XEXP (x
, 0));
390 output_addr_const (stream
, x
);
397 /* What does a constant cost ? */
400 mcore_const_costs (rtx exp
, enum rtx_code code
)
402 HOST_WIDE_INT val
= INTVAL (exp
);
404 /* Easy constants. */
405 if ( CONST_OK_FOR_I (val
)
406 || CONST_OK_FOR_M (val
)
407 || CONST_OK_FOR_N (val
)
408 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
411 && ( CONST_OK_FOR_M (~val
)
412 || CONST_OK_FOR_N (~val
)))
414 else if (code
== PLUS
415 && ( CONST_OK_FOR_I (-val
)
416 || CONST_OK_FOR_M (-val
)
417 || CONST_OK_FOR_N (-val
)))
423 /* What does an and instruction cost - we do this b/c immediates may
424 have been relaxed. We want to ensure that cse will cse relaxed immeds
425 out. Otherwise we'll get bad code (multiple reloads of the same const). */
428 mcore_and_cost (rtx x
)
432 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
435 val
= INTVAL (XEXP (x
, 1));
437 /* Do it directly. */
438 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
440 /* Takes one instruction to load. */
441 else if (const_ok_for_mcore (val
))
443 /* Takes two instructions to load. */
444 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
447 /* Takes a lrw to load. */
451 /* What does an or cost - see and_cost(). */
454 mcore_ior_cost (rtx x
)
458 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
461 val
= INTVAL (XEXP (x
, 1));
463 /* Do it directly with bclri. */
464 if (CONST_OK_FOR_M (val
))
466 /* Takes one instruction to load. */
467 else if (const_ok_for_mcore (val
))
469 /* Takes two instructions to load. */
470 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
473 /* Takes a lrw to load. */
478 mcore_rtx_costs (rtx x
, int code
, int outer_code
, int * total
,
479 bool speed ATTRIBUTE_UNUSED
)
484 *total
= mcore_const_costs (x
, outer_code
);
496 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
500 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
509 *total
= COSTS_N_INSNS (100);
517 /* Prepare the operands for a comparison. Return whether the branch/setcc
518 should reverse the operands. */
521 mcore_gen_compare (enum rtx_code code
, rtx op0
, rtx op1
)
523 rtx cc_reg
= gen_rtx_REG (CCmode
, CC_REG
);
526 if (GET_CODE (op1
) == CONST_INT
)
528 HOST_WIDE_INT val
= INTVAL (op1
);
533 /* Unsigned > 0 is the same as != 0; everything else is converted
534 below to LEU (reversed cmphs). */
539 /* Check whether (LE A imm) can become (LT A imm + 1),
540 or (GT A imm) can become (GE A imm + 1). */
543 if (CONST_OK_FOR_J (val
+ 1))
545 op1
= GEN_INT (val
+ 1);
546 code
= code
== LE
? LT
: GE
;
555 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
556 op1
= force_reg (SImode
, op1
);
558 /* cmpnei: 0-31 (K immediate)
559 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
563 case EQ
: /* Use inverted condition, cmpne. */
568 case NE
: /* Use normal condition, cmpne. */
569 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
570 op1
= force_reg (SImode
, op1
);
573 case LE
: /* Use inverted condition, reversed cmplt. */
578 case GT
: /* Use normal condition, reversed cmplt. */
579 if (GET_CODE (op1
) == CONST_INT
)
580 op1
= force_reg (SImode
, op1
);
583 case GE
: /* Use inverted condition, cmplt. */
588 case LT
: /* Use normal condition, cmplt. */
589 if (GET_CODE (op1
) == CONST_INT
&&
590 /* covered by btsti x,31. */
592 ! CONST_OK_FOR_J (INTVAL (op1
)))
593 op1
= force_reg (SImode
, op1
);
596 case GTU
: /* Use inverted condition, cmple. */
597 /* We coped with unsigned > 0 above. */
598 gcc_assert (GET_CODE (op1
) != CONST_INT
|| INTVAL (op1
) != 0);
603 case LEU
: /* Use normal condition, reversed cmphs. */
604 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
605 op1
= force_reg (SImode
, op1
);
608 case LTU
: /* Use inverted condition, cmphs. */
613 case GEU
: /* Use normal condition, cmphs. */
614 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
615 op1
= force_reg (SImode
, op1
);
622 emit_insn (gen_rtx_SET (VOIDmode
,
624 gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
)));
629 mcore_symbolic_address_p (rtx x
)
631 switch (GET_CODE (x
))
638 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
639 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
640 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
646 /* Functions to output assembly code for a function call. */
649 mcore_output_call (rtx operands
[], int index
)
651 static char buffer
[20];
652 rtx addr
= operands
[index
];
658 gcc_assert (mcore_current_function_name
);
660 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
664 sprintf (buffer
, "jsr\t%%%d", index
);
670 gcc_assert (mcore_current_function_name
);
671 gcc_assert (GET_CODE (addr
) == SYMBOL_REF
);
673 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
677 sprintf (buffer
, "jbsr\t%%%d", index
);
683 /* Can we load a constant with a single instruction ? */
686 const_ok_for_mcore (HOST_WIDE_INT value
)
688 if (value
>= 0 && value
<= 127)
691 /* Try exact power of two. */
692 if (CONST_OK_FOR_M (value
))
695 /* Try exact power of two - 1. */
696 if (CONST_OK_FOR_N (value
) && value
!= -1)
702 /* Can we load a constant inline with up to 2 instructions ? */
705 mcore_const_ok_for_inline (HOST_WIDE_INT value
)
709 return try_constant_tricks (value
, & x
, & y
) > 0;
712 /* Are we loading the constant using a not ? */
715 mcore_const_trick_uses_not (HOST_WIDE_INT value
)
719 return try_constant_tricks (value
, & x
, & y
) == 2;
722 /* Try tricks to load a constant inline and return the trick number if
723 success (0 is non-inlinable).
726 1: single instruction (do the usual thing)
727 2: single insn followed by a 'not'
728 3: single insn followed by a subi
729 4: single insn followed by an addi
730 5: single insn followed by rsubi
731 6: single insn followed by bseti
732 7: single insn followed by bclri
733 8: single insn followed by rotli
734 9: single insn followed by lsli
735 10: single insn followed by ixh
736 11: single insn followed by ixw. */
739 try_constant_tricks (HOST_WIDE_INT value
, HOST_WIDE_INT
* x
, HOST_WIDE_INT
* y
)
742 unsigned HOST_WIDE_INT bit
, shf
, rot
;
744 if (const_ok_for_mcore (value
))
745 return 1; /* Do the usual thing. */
747 if (! TARGET_HARDLIT
)
750 if (const_ok_for_mcore (~value
))
756 for (i
= 1; i
<= 32; i
++)
758 if (const_ok_for_mcore (value
- i
))
766 if (const_ok_for_mcore (value
+ i
))
777 for (i
= 0; i
<= 31; i
++)
779 if (const_ok_for_mcore (i
- value
))
787 if (const_ok_for_mcore (value
& ~bit
))
794 if (const_ok_for_mcore (value
| bit
))
808 for (i
= 1; i
< 31; i
++)
812 /* MCore has rotate left. */
816 rot
|= c
; /* Simulate rotate. */
818 if (const_ok_for_mcore (rot
))
827 shf
= 0; /* Can't use logical shift, low order bit is one. */
831 if (shf
!= 0 && const_ok_for_mcore (shf
))
840 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
847 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
857 /* Check whether reg is dead at first. This is done by searching ahead
858 for either the next use (i.e., reg is live), a death note, or a set of
859 reg. Don't just use dead_or_set_p() since reload does not always mark
860 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
861 can ignore subregs by extracting the actual register. BRC */
864 mcore_is_dead (rtx first
, rtx reg
)
868 /* For mcore, subregs can't live independently of their parent regs. */
869 if (GET_CODE (reg
) == SUBREG
)
870 reg
= SUBREG_REG (reg
);
872 /* Dies immediately. */
873 if (dead_or_set_p (first
, reg
))
876 /* Look for conclusive evidence of live/death, otherwise we have
877 to assume that it is live. */
878 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
880 if (GET_CODE (insn
) == JUMP_INSN
)
881 return 0; /* We lose track, assume it is alive. */
883 else if (GET_CODE(insn
) == CALL_INSN
)
885 /* Call's might use it for target or register parms. */
886 if (reg_referenced_p (reg
, PATTERN (insn
))
887 || find_reg_fusage (insn
, USE
, reg
))
889 else if (dead_or_set_p (insn
, reg
))
892 else if (GET_CODE (insn
) == INSN
)
894 if (reg_referenced_p (reg
, PATTERN (insn
)))
896 else if (dead_or_set_p (insn
, reg
))
901 /* No conclusive evidence either way, we cannot take the chance
902 that control flow hid the use from us -- "I'm not dead yet". */
906 /* Count the number of ones in mask. */
909 mcore_num_ones (HOST_WIDE_INT mask
)
911 /* A trick to count set bits recently posted on comp.compilers. */
912 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
913 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
914 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
915 mask
= ((mask
>> 8) + mask
);
917 return (mask
+ (mask
>> 16)) & 0xff;
920 /* Count the number of zeros in mask. */
923 mcore_num_zeros (HOST_WIDE_INT mask
)
925 return 32 - mcore_num_ones (mask
);
928 /* Determine byte being masked. */
931 mcore_byte_offset (unsigned int mask
)
933 if (mask
== 0x00ffffffL
)
935 else if (mask
== 0xff00ffffL
)
937 else if (mask
== 0xffff00ffL
)
939 else if (mask
== 0xffffff00L
)
945 /* Determine halfword being masked. */
948 mcore_halfword_offset (unsigned int mask
)
950 if (mask
== 0x0000ffffL
)
952 else if (mask
== 0xffff0000L
)
958 /* Output a series of bseti's corresponding to mask. */
961 mcore_output_bseti (rtx dst
, int mask
)
966 out_operands
[0] = dst
;
968 for (bit
= 0; bit
< 32; bit
++)
970 if ((mask
& 0x1) == 0x1)
972 out_operands
[1] = GEN_INT (bit
);
974 output_asm_insn ("bseti\t%0,%1", out_operands
);
982 /* Output a series of bclri's corresponding to mask. */
985 mcore_output_bclri (rtx dst
, int mask
)
990 out_operands
[0] = dst
;
992 for (bit
= 0; bit
< 32; bit
++)
994 if ((mask
& 0x1) == 0x0)
996 out_operands
[1] = GEN_INT (bit
);
998 output_asm_insn ("bclri\t%0,%1", out_operands
);
1007 /* Output a conditional move of two constants that are +/- 1 within each
1008 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1009 really worth the effort. */
1012 mcore_output_cmov (rtx operands
[], int cmp_t
, const char * test
)
1014 HOST_WIDE_INT load_value
;
1015 HOST_WIDE_INT adjust_value
;
1016 rtx out_operands
[4];
1018 out_operands
[0] = operands
[0];
1020 /* Check to see which constant is loadable. */
1021 if (const_ok_for_mcore (INTVAL (operands
[1])))
1023 out_operands
[1] = operands
[1];
1024 out_operands
[2] = operands
[2];
1026 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1028 out_operands
[1] = operands
[2];
1029 out_operands
[2] = operands
[1];
1031 /* Complement test since constants are swapped. */
1032 cmp_t
= (cmp_t
== 0);
1034 load_value
= INTVAL (out_operands
[1]);
1035 adjust_value
= INTVAL (out_operands
[2]);
1037 /* First output the test if folded into the pattern. */
1040 output_asm_insn (test
, operands
);
1042 /* Load the constant - for now, only support constants that can be
1043 generated with a single instruction. maybe add general inlinable
1044 constants later (this will increase the # of patterns since the
1045 instruction sequence has a different length attribute). */
1046 if (load_value
>= 0 && load_value
<= 127)
1047 output_asm_insn ("movi\t%0,%1", out_operands
);
1048 else if (CONST_OK_FOR_M (load_value
))
1049 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1050 else if (CONST_OK_FOR_N (load_value
))
1051 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1053 /* Output the constant adjustment. */
1054 if (load_value
> adjust_value
)
1057 output_asm_insn ("decf\t%0", out_operands
);
1059 output_asm_insn ("dect\t%0", out_operands
);
1064 output_asm_insn ("incf\t%0", out_operands
);
1066 output_asm_insn ("inct\t%0", out_operands
);
1072 /* Outputs the peephole for moving a constant that gets not'ed followed
1073 by an and (i.e. combine the not and the and into andn). BRC */
1076 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
1079 rtx out_operands
[3];
1080 const char * load_op
;
1084 trick_no
= try_constant_tricks (INTVAL (operands
[1]), &x
, &y
);
1085 gcc_assert (trick_no
== 2);
1087 out_operands
[0] = operands
[0];
1088 out_operands
[1] = GEN_INT (x
);
1089 out_operands
[2] = operands
[2];
1091 if (x
>= 0 && x
<= 127)
1092 load_op
= "movi\t%0,%1";
1094 /* Try exact power of two. */
1095 else if (CONST_OK_FOR_M (x
))
1096 load_op
= "bgeni\t%0,%P1";
1098 /* Try exact power of two - 1. */
1099 else if (CONST_OK_FOR_N (x
))
1100 load_op
= "bmaski\t%0,%N1";
1104 load_op
= "BADMOVI-andn\t%0, %1";
1108 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1109 output_asm_insn (buf
, out_operands
);
1114 /* Output an inline constant. */
1117 output_inline_const (enum machine_mode mode
, rtx operands
[])
1119 HOST_WIDE_INT x
= 0, y
= 0;
1121 rtx out_operands
[3];
1124 const char *dst_fmt
;
1125 HOST_WIDE_INT value
;
1127 value
= INTVAL (operands
[1]);
1129 trick_no
= try_constant_tricks (value
, &x
, &y
);
1130 /* lrw's are handled separately: Large inlinable constants never get
1131 turned into lrw's. Our caller uses try_constant_tricks to back
1132 off to an lrw rather than calling this routine. */
1133 gcc_assert (trick_no
!= 0);
1138 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1139 out_operands
[0] = operands
[0];
1140 out_operands
[1] = GEN_INT (x
);
1143 out_operands
[2] = GEN_INT (y
);
1145 /* Select dst format based on mode. */
1146 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1151 if (x
>= 0 && x
<= 127)
1152 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1154 /* Try exact power of two. */
1155 else if (CONST_OK_FOR_M (x
))
1156 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1158 /* Try exact power of two - 1. */
1159 else if (CONST_OK_FOR_N (x
))
1160 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1164 sprintf (load_op
, "BADMOVI-inline_const %s, %%1", dst_fmt
);
1171 strcpy (buf
, load_op
);
1174 sprintf (buf
, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1177 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1180 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1183 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1184 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1187 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1190 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1193 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1196 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1199 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1202 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1208 output_asm_insn (buf
, out_operands
);
1213 /* Output a move of a word or less value. */
1216 mcore_output_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
1217 enum machine_mode mode ATTRIBUTE_UNUSED
)
1219 rtx dst
= operands
[0];
1220 rtx src
= operands
[1];
1222 if (GET_CODE (dst
) == REG
)
1224 if (GET_CODE (src
) == REG
)
1226 if (REGNO (src
) == CC_REG
) /* r-c */
1229 return "mov\t%0,%1"; /* r-r*/
1231 else if (GET_CODE (src
) == MEM
)
1233 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1234 return "lrw\t%0,[%1]"; /* a-R */
1236 switch (GET_MODE (src
)) /* r-m */
1239 return "ldw\t%0,%1";
1241 return "ld.h\t%0,%1";
1243 return "ld.b\t%0,%1";
1248 else if (GET_CODE (src
) == CONST_INT
)
1252 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1253 return "movi\t%0,%1";
1254 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1255 return "bgeni\t%0,%P1\t// %1 %x1";
1256 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1257 return "bmaski\t%0,%N1\t// %1 %x1";
1258 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1259 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1261 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1264 return "lrw\t%0, %1"; /* Into the literal pool. */
1266 else if (GET_CODE (dst
) == MEM
) /* m-r */
1267 switch (GET_MODE (dst
))
1270 return "stw\t%1,%0";
1272 return "st.h\t%1,%0";
1274 return "st.b\t%1,%0";
1282 /* Return a sequence of instructions to perform DI or DF move.
1283 Since the MCORE cannot move a DI or DF in one instruction, we have
1284 to take care when we see overlapping source and dest registers. */
1287 mcore_output_movedouble (rtx operands
[], enum machine_mode mode ATTRIBUTE_UNUSED
)
1289 rtx dst
= operands
[0];
1290 rtx src
= operands
[1];
1292 if (GET_CODE (dst
) == REG
)
1294 if (GET_CODE (src
) == REG
)
1296 int dstreg
= REGNO (dst
);
1297 int srcreg
= REGNO (src
);
1299 /* Ensure the second source not overwritten. */
1300 if (srcreg
+ 1 == dstreg
)
1301 return "mov %R0,%R1\n\tmov %0,%1";
1303 return "mov %0,%1\n\tmov %R0,%R1";
1305 else if (GET_CODE (src
) == MEM
)
1307 rtx memexp
= memexp
= XEXP (src
, 0);
1308 int dstreg
= REGNO (dst
);
1311 if (GET_CODE (memexp
) == LABEL_REF
)
1312 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1313 else if (GET_CODE (memexp
) == REG
)
1314 basereg
= REGNO (memexp
);
1315 else if (GET_CODE (memexp
) == PLUS
)
1317 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1318 basereg
= REGNO (XEXP (memexp
, 0));
1319 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1320 basereg
= REGNO (XEXP (memexp
, 1));
1327 /* ??? length attribute is wrong here. */
1328 if (dstreg
== basereg
)
1330 /* Just load them in reverse order. */
1331 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1333 /* XXX: alternative: move basereg to basereg+1
1334 and then fall through. */
1337 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1339 else if (GET_CODE (src
) == CONST_INT
)
1341 if (TARGET_LITTLE_END
)
1343 if (CONST_OK_FOR_I (INTVAL (src
)))
1344 output_asm_insn ("movi %0,%1", operands
);
1345 else if (CONST_OK_FOR_M (INTVAL (src
)))
1346 output_asm_insn ("bgeni %0,%P1", operands
);
1347 else if (CONST_OK_FOR_N (INTVAL (src
)))
1348 output_asm_insn ("bmaski %0,%N1", operands
);
1352 if (INTVAL (src
) < 0)
1353 return "bmaski %R0,32";
1355 return "movi %R0,0";
1359 if (CONST_OK_FOR_I (INTVAL (src
)))
1360 output_asm_insn ("movi %R0,%1", operands
);
1361 else if (CONST_OK_FOR_M (INTVAL (src
)))
1362 output_asm_insn ("bgeni %R0,%P1", operands
);
1363 else if (CONST_OK_FOR_N (INTVAL (src
)))
1364 output_asm_insn ("bmaski %R0,%N1", operands
);
1368 if (INTVAL (src
) < 0)
1369 return "bmaski %0,32";
1377 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1378 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1383 /* Predicates used by the templates. */
1386 mcore_arith_S_operand (rtx op
)
1388 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1394 /* Expand insert bit field. BRC */
1397 mcore_expand_insv (rtx operands
[])
1399 int width
= INTVAL (operands
[1]);
1400 int posn
= INTVAL (operands
[2]);
1402 rtx mreg
, sreg
, ereg
;
1404 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1405 for width==1 must be removed. Look around line 368. This is something
1406 we really want the md part to do. */
1407 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1409 /* Do directly with bseti or bclri. */
1410 /* RBE: 2/97 consider only low bit of constant. */
1411 if ((INTVAL (operands
[3]) & 1) == 0)
1413 mask
= ~(1 << posn
);
1414 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1415 gen_rtx_AND (SImode
, operands
[0], GEN_INT (mask
))));
1420 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1421 gen_rtx_IOR (SImode
, operands
[0], GEN_INT (mask
))));
1427 /* Look at some bit-field placements that we aren't interested
1428 in handling ourselves, unless specifically directed to do so. */
1429 if (! TARGET_W_FIELD
)
1430 return 0; /* Generally, give up about now. */
1432 if (width
== 8 && posn
% 8 == 0)
1433 /* Byte sized and aligned; let caller break it up. */
1436 if (width
== 16 && posn
% 16 == 0)
1437 /* Short sized and aligned; let caller break it up. */
1440 /* The general case - we can do this a little bit better than what the
1441 machine independent part tries. This will get rid of all the subregs
1442 that mess up constant folding in combine when working with relaxed
1445 /* If setting the entire field, do it directly. */
1446 if (GET_CODE (operands
[3]) == CONST_INT
1447 && INTVAL (operands
[3]) == ((1 << width
) - 1))
1449 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1450 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1451 gen_rtx_IOR (SImode
, operands
[0], mreg
)));
1455 /* Generate the clear mask. */
1456 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1458 /* Clear the field, to overlay it later with the source. */
1459 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1460 gen_rtx_AND (SImode
, operands
[0], mreg
)));
1462 /* If the source is constant 0, we've nothing to add back. */
1463 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1466 /* XXX: Should we worry about more games with constant values?
1467 We've covered the high profile: set/clear single-bit and many-bit
1468 fields. How often do we see "arbitrary bit pattern" constants? */
1469 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1471 /* Extract src as same width as dst (needed for signed values). We
1472 always have to do this since we widen everything to SImode.
1473 We don't have to mask if we're shifting this up against the
1474 MSB of the register (e.g., the shift will push out any hi-order
1476 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1478 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1479 emit_insn (gen_rtx_SET (SImode
, sreg
,
1480 gen_rtx_AND (SImode
, sreg
, ereg
)));
1483 /* Insert source value in dest. */
1485 emit_insn (gen_rtx_SET (SImode
, sreg
,
1486 gen_rtx_ASHIFT (SImode
, sreg
, GEN_INT (posn
))));
1488 emit_insn (gen_rtx_SET (SImode
, operands
[0],
1489 gen_rtx_IOR (SImode
, operands
[0], sreg
)));
1494 /* ??? Block move stuff stolen from m88k. This code has not been
1495 verified for correctness. */
1497 /* Emit code to perform a block move. Choose the best method.
1499 OPERANDS[0] is the destination.
1500 OPERANDS[1] is the source.
1501 OPERANDS[2] is the size.
1502 OPERANDS[3] is the alignment safe to use. */
1504 /* Emit code to perform a block move with an offset sequence of ldw/st
1505 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1506 known constants. DEST and SRC are registers. OFFSET is the known
1507 starting point for the output pattern. */
1509 static const enum machine_mode mode_from_align
[] =
1511 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1515 block_move_sequence (rtx dst_mem
, rtx src_mem
, int size
, int align
)
1518 enum machine_mode mode
[2];
1527 x
= XEXP (dst_mem
, 0);
1530 x
= force_reg (Pmode
, x
);
1531 dst_mem
= replace_equiv_address (dst_mem
, x
);
1534 x
= XEXP (src_mem
, 0);
1537 x
= force_reg (Pmode
, x
);
1538 src_mem
= replace_equiv_address (src_mem
, x
);
1541 active
[0] = active
[1] = false;
1552 next_amount
= (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
1553 next_amount
= MIN (next_amount
, align
);
1555 amount
[next
] = next_amount
;
1556 mode
[next
] = mode_from_align
[next_amount
];
1557 temp
[next
] = gen_reg_rtx (mode
[next
]);
1559 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1560 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1562 offset_ld
+= next_amount
;
1563 size
-= next_amount
;
1564 active
[next
] = true;
1569 active
[phase
] = false;
1571 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1572 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1574 offset_st
+= amount
[phase
];
1577 while (active
[next
]);
1581 mcore_expand_block_move (rtx
*operands
)
1583 HOST_WIDE_INT align
, bytes
, max
;
1585 if (GET_CODE (operands
[2]) != CONST_INT
)
1588 bytes
= INTVAL (operands
[2]);
1589 align
= INTVAL (operands
[3]);
1618 block_move_sequence (operands
[0], operands
[1], bytes
, align
);
1626 /* Code to generate prologue and epilogue sequences. */
1627 static int number_of_regs_before_varargs
;
1629 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1630 for a varargs function. */
1631 static int current_function_anonymous_args
;
1633 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1634 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1635 #define ADDI_REACH (32) /* Maximum addi operand. */
1638 layout_mcore_frame (struct mcore_frame
* infp
)
1647 unsigned int growths
;
1650 /* Might have to spill bytes to re-assemble a big argument that
1651 was passed partially in registers and partially on the stack. */
1652 nbytes
= crtl
->args
.pretend_args_size
;
1654 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1655 if (current_function_anonymous_args
)
1656 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
1658 infp
->arg_size
= nbytes
;
1660 /* How much space to save non-volatile registers we stomp. */
1661 infp
->reg_mask
= calc_live_regs (& n
);
1662 infp
->reg_size
= n
* 4;
1664 /* And the rest of it... locals and space for overflowed outbounds. */
1665 infp
->local_size
= get_frame_size ();
1666 infp
->outbound_size
= crtl
->outgoing_args_size
;
1668 /* Make sure we have a whole number of words for the locals. */
1669 if (infp
->local_size
% STACK_BYTES
)
1670 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
1672 /* Only thing we know we have to pad is the outbound space, since
1673 we've aligned our locals assuming that base of locals is aligned. */
1674 infp
->pad_local
= 0;
1676 infp
->pad_outbound
= 0;
1677 if (infp
->outbound_size
% STACK_BYTES
)
1678 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
1680 /* Now we see how we want to stage the prologue so that it does
1681 the most appropriate stack growth and register saves to either:
1683 (2) reduce instruction space, or
1684 (3) reduce stack space. */
1685 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
1686 infp
->growth
[i
] = 0;
1688 regarg
= infp
->reg_size
+ infp
->arg_size
;
1689 localregarg
= infp
->local_size
+ regarg
;
1690 localreg
= infp
->local_size
+ infp
->reg_size
;
1691 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
1694 /* XXX: Consider one where we consider localregarg + outbound too! */
1696 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1697 use stw's with offsets and buy the frame in one shot. */
1698 if (localregarg
<= ADDI_REACH
1699 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1701 /* Make sure we'll be aligned. */
1702 if (localregarg
% STACK_BYTES
)
1703 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1705 step
= localregarg
+ infp
->pad_reg
;
1706 infp
->reg_offset
= infp
->local_size
;
1708 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
1711 infp
->reg_offset
+= outbounds
;
1715 infp
->arg_offset
= step
- 4;
1716 infp
->growth
[growths
++] = step
;
1717 infp
->reg_growth
= growths
;
1718 infp
->local_growth
= growths
;
1720 /* If we haven't already folded it in. */
1722 infp
->growth
[growths
++] = outbounds
;
1727 /* Frame can't be done with a single subi, but can be done with 2
1728 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1729 shift some of the stack purchase into the first subi, so both are
1730 single instructions. */
1731 if (localregarg
<= STORE_REACH
1732 && (infp
->local_size
> ADDI_REACH
)
1733 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1737 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1738 if (localregarg
% STACK_BYTES
)
1739 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1741 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
1742 step
= ADDI_REACH
; /* As much up front as we can. */
1746 /* XXX: Consider whether step will still be aligned; we believe so. */
1747 infp
->arg_offset
= step
- 4;
1748 infp
->growth
[growths
++] = step
;
1749 infp
->reg_growth
= growths
;
1750 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
1753 /* Can we fold in any space required for outbounds? */
1754 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
1760 /* Get the rest of the locals in place. */
1762 infp
->growth
[growths
++] = step
;
1763 infp
->local_growth
= growths
;
1768 /* Finish off if we need to do so. */
1770 infp
->growth
[growths
++] = outbounds
;
1775 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1776 Then we buy the rest of the frame in 1 or 2 steps depending on
1777 whether we need a frame pointer. */
1778 if ((regarg
% STACK_BYTES
) == 0)
1780 infp
->growth
[growths
++] = regarg
;
1781 infp
->reg_growth
= growths
;
1782 infp
->arg_offset
= regarg
- 4;
1783 infp
->reg_offset
= 0;
1785 if (infp
->local_size
% STACK_BYTES
)
1786 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1788 step
= infp
->local_size
+ infp
->pad_local
;
1790 if (!frame_pointer_needed
)
1796 infp
->growth
[growths
++] = step
;
1797 infp
->local_growth
= growths
;
1799 /* If there's any left to be done. */
1801 infp
->growth
[growths
++] = outbounds
;
1806 /* XXX: optimizations that we'll want to play with....
1807 -- regarg is not aligned, but it's a small number of registers;
1808 use some of localsize so that regarg is aligned and then
1809 save the registers. */
1811 /* Simple encoding; plods down the stack buying the pieces as it goes.
1812 -- does not optimize space consumption.
1813 -- does not attempt to optimize instruction counts.
1814 -- but it is safe for all alignments. */
1815 if (regarg
% STACK_BYTES
!= 0)
1816 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
1818 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
1819 infp
->reg_growth
= growths
;
1820 infp
->arg_offset
= infp
->growth
[0] - 4;
1821 infp
->reg_offset
= 0;
1823 if (frame_pointer_needed
)
1825 if (infp
->local_size
% STACK_BYTES
!= 0)
1826 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1828 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
1829 infp
->local_growth
= growths
;
1831 infp
->growth
[growths
++] = outbounds
;
1835 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
1836 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
1838 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
1839 infp
->local_growth
= growths
;
1842 /* Anything else that we've forgotten?, plus a few consistency checks. */
1844 assert (infp
->reg_offset
>= 0);
1845 assert (growths
<= MAX_STACK_GROWS
);
1847 for (i
= 0; i
< growths
; i
++)
1848 gcc_assert (!(infp
->growth
[i
] % STACK_BYTES
));
1851 /* Define the offset between two registers, one to be eliminated, and
1852 the other its replacement, at the start of a routine. */
1855 mcore_initial_elimination_offset (int from
, int to
)
1859 struct mcore_frame fi
;
1861 layout_mcore_frame (& fi
);
1864 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
1866 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
1868 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1871 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1872 return above_frame
+ below_frame
;
1874 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1880 /* Keep track of some information about varargs for the prolog. */
1883 mcore_setup_incoming_varargs (CUMULATIVE_ARGS
*args_so_far
,
1884 enum machine_mode mode
, tree type
,
1885 int * ptr_pretend_size ATTRIBUTE_UNUSED
,
1886 int second_time ATTRIBUTE_UNUSED
)
1888 current_function_anonymous_args
= 1;
1890 /* We need to know how many argument registers are used before
1891 the varargs start, so that we can push the remaining argument
1892 registers during the prologue. */
1893 number_of_regs_before_varargs
= *args_so_far
+ mcore_num_arg_regs (mode
, type
);
1895 /* There is a bug somewhere in the arg handling code.
1896 Until I can find it this workaround always pushes the
1897 last named argument onto the stack. */
1898 number_of_regs_before_varargs
= *args_so_far
;
1900 /* The last named argument may be split between argument registers
1901 and the stack. Allow for this here. */
1902 if (number_of_regs_before_varargs
> NPARM_REGS
)
1903 number_of_regs_before_varargs
= NPARM_REGS
;
1907 mcore_expand_prolog (void)
1909 struct mcore_frame fi
;
1910 int space_allocated
= 0;
1913 /* Find out what we're doing. */
1914 layout_mcore_frame (&fi
);
1916 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
1917 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
1921 /* Emit a symbol for this routine's frame size. */
1924 x
= DECL_RTL (current_function_decl
);
1926 gcc_assert (GET_CODE (x
) == MEM
);
1930 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1932 if (mcore_current_function_name
)
1933 free (mcore_current_function_name
);
1935 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
1937 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
1939 if (cfun
->calls_alloca
)
1940 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
1943 We're looking at how the 8byte alignment affects stack layout
1944 and where we had to pad things. This emits information we can
1945 extract which tells us about frame sizes and the like. */
1946 fprintf (asm_out_file
,
1947 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
1948 mcore_current_function_name
,
1949 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
1950 fi
.local_size
, fi
.outbound_size
,
1951 frame_pointer_needed
);
1954 if (mcore_naked_function_p ())
1957 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
1958 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
1960 /* If we have a parameter passed partially in regs and partially in memory,
1961 the registers will have been stored to memory already in function.c. So
1962 we only need to do something here for varargs functions. */
1963 if (fi
.arg_size
!= 0 && crtl
->args
.pretend_args_size
== 0)
1966 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
1967 int remaining
= fi
.arg_size
;
1969 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
1971 emit_insn (gen_movsi
1972 (gen_rtx_MEM (SImode
,
1973 plus_constant (stack_pointer_rtx
, offset
)),
1974 gen_rtx_REG (SImode
, rn
)));
1978 /* Do we need another stack adjustment before we do the register saves? */
1979 if (growth
< fi
.reg_growth
)
1980 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
1982 if (fi
.reg_size
!= 0)
1985 int offs
= fi
.reg_offset
;
1987 for (i
= 15; i
>= 0; i
--)
1989 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
1993 while (fi
.reg_mask
& (1 << first_reg
))
1997 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode
, stack_pointer_rtx
),
1998 gen_rtx_REG (SImode
, first_reg
),
1999 GEN_INT (16 - first_reg
)));
2001 i
-= (15 - first_reg
);
2002 offs
+= (16 - first_reg
) * 4;
2004 else if (fi
.reg_mask
& (1 << i
))
2006 emit_insn (gen_movsi
2007 (gen_rtx_MEM (SImode
,
2008 plus_constant (stack_pointer_rtx
, offs
)),
2009 gen_rtx_REG (SImode
, i
)));
2015 /* Figure the locals + outbounds. */
2016 if (frame_pointer_needed
)
2018 /* If we haven't already purchased to 'fp'. */
2019 if (growth
< fi
.local_growth
)
2020 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2022 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2024 /* ... and then go any remaining distance for outbounds, etc. */
2025 if (fi
.growth
[growth
])
2026 output_stack_adjust (-1, fi
.growth
[growth
++]);
2030 if (growth
< fi
.local_growth
)
2031 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2032 if (fi
.growth
[growth
])
2033 output_stack_adjust (-1, fi
.growth
[growth
++]);
2038 mcore_expand_epilog (void)
2040 struct mcore_frame fi
;
2043 int growth
= MAX_STACK_GROWS
- 1 ;
2046 /* Find out what we're doing. */
2047 layout_mcore_frame(&fi
);
2049 if (mcore_naked_function_p ())
2052 /* If we had a frame pointer, restore the sp from that. */
2053 if (frame_pointer_needed
)
2055 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2056 growth
= fi
.local_growth
- 1;
2060 /* XXX: while loop should accumulate and do a single sell. */
2061 while (growth
>= fi
.local_growth
)
2063 if (fi
.growth
[growth
] != 0)
2064 output_stack_adjust (1, fi
.growth
[growth
]);
2069 /* Make sure we've shrunk stack back to the point where the registers
2070 were laid down. This is typically 0/1 iterations. Then pull the
2071 register save information back off the stack. */
2072 while (growth
>= fi
.reg_growth
)
2073 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2075 offs
= fi
.reg_offset
;
2077 for (i
= 15; i
>= 0; i
--)
2079 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2083 /* Find the starting register. */
2086 while (fi
.reg_mask
& (1 << first_reg
))
2091 emit_insn (gen_load_multiple (gen_rtx_REG (SImode
, first_reg
),
2092 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2093 GEN_INT (16 - first_reg
)));
2095 i
-= (15 - first_reg
);
2096 offs
+= (16 - first_reg
) * 4;
2098 else if (fi
.reg_mask
& (1 << i
))
2100 emit_insn (gen_movsi
2101 (gen_rtx_REG (SImode
, i
),
2102 gen_rtx_MEM (SImode
,
2103 plus_constant (stack_pointer_rtx
, offs
))));
2108 /* Give back anything else. */
2109 /* XXX: Should accumulate total and then give it back. */
2111 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2114 /* This code is borrowed from the SH port. */
2116 /* The MCORE cannot load a large constant into a register, constants have to
2117 come from a pc relative load. The reference of a pc relative load
2118 instruction must be less than 1k in front of the instruction. This
2119 means that we often have to dump a constant inside a function, and
2120 generate code to branch around it.
2122 It is important to minimize this, since the branches will slow things
2123 down and make things bigger.
2125 Worst case code looks like:
2141 We fix this by performing a scan before scheduling, which notices which
2142 instructions need to have their operands fetched from the constant table
2143 and builds the table.
2147 scan, find an instruction which needs a pcrel move. Look forward, find the
2148 last barrier which is within MAX_COUNT bytes of the requirement.
2149 If there isn't one, make one. Process all the instructions between
2150 the find and the barrier.
2152 In the above example, we can tell that L3 is within 1k of L1, so
2153 the first move can be shrunk from the 2 insn+constant sequence into
2154 just 1 insn, and the constant moved to L3 to make:
2164 Then the second move becomes the target for the shortening process. */
2168 rtx value
; /* Value in table. */
2169 rtx label
; /* Label of value. */
2172 /* The maximum number of constants that can fit into one pool, since
2173 the pc relative range is 0...1020 bytes and constants are at least 4
2174 bytes long. We subtract 4 from the range to allow for the case where
2175 we need to add a branch/align before the constant pool. */
2177 #define MAX_COUNT 1016
2178 #define MAX_POOL_SIZE (MAX_COUNT/4)
2179 static pool_node pool_vector
[MAX_POOL_SIZE
];
2180 static int pool_size
;
2182 /* Dump out any constants accumulated in the final pass. These
2183 will only be labels. */
2186 mcore_output_jump_label_table (void)
2192 fprintf (asm_out_file
, "\t.align 2\n");
2194 for (i
= 0; i
< pool_size
; i
++)
2196 pool_node
* p
= pool_vector
+ i
;
2198 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2200 output_asm_insn (".long %0", &p
->value
);
2209 /* Check whether insn is a candidate for a conditional. */
2212 is_cond_candidate (rtx insn
)
2214 /* The only things we conditionalize are those that can be directly
2215 changed into a conditional. Only bother with SImode items. If
2216 we wanted to be a little more aggressive, we could also do other
2217 modes such as DImode with reg-reg move or load 0. */
2218 if (GET_CODE (insn
) == INSN
)
2220 rtx pat
= PATTERN (insn
);
2223 if (GET_CODE (pat
) != SET
)
2226 dst
= XEXP (pat
, 0);
2228 if ((GET_CODE (dst
) != REG
&&
2229 GET_CODE (dst
) != SUBREG
) ||
2230 GET_MODE (dst
) != SImode
)
2233 src
= XEXP (pat
, 1);
2235 if ((GET_CODE (src
) == REG
||
2236 (GET_CODE (src
) == SUBREG
&&
2237 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2238 GET_MODE (src
) == SImode
)
2239 return COND_MOV_INSN
;
2240 else if (GET_CODE (src
) == CONST_INT
&&
2242 return COND_CLR_INSN
;
2243 else if (GET_CODE (src
) == PLUS
&&
2244 (GET_CODE (XEXP (src
, 0)) == REG
||
2245 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2246 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2247 GET_MODE (XEXP (src
, 0)) == SImode
&&
2248 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2249 INTVAL (XEXP (src
, 1)) == 1)
2250 return COND_INC_INSN
;
2251 else if (((GET_CODE (src
) == MINUS
&&
2252 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2253 INTVAL( XEXP (src
, 1)) == 1) ||
2254 (GET_CODE (src
) == PLUS
&&
2255 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2256 INTVAL (XEXP (src
, 1)) == -1)) &&
2257 (GET_CODE (XEXP (src
, 0)) == REG
||
2258 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2259 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2260 GET_MODE (XEXP (src
, 0)) == SImode
)
2261 return COND_DEC_INSN
;
2263 /* Some insns that we don't bother with:
2264 (set (rx:DI) (ry:DI))
2265 (set (rx:DI) (const_int 0))
2269 else if (GET_CODE (insn
) == JUMP_INSN
&&
2270 GET_CODE (PATTERN (insn
)) == SET
&&
2271 GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2272 return COND_BRANCH_INSN
;
2277 /* Emit a conditional version of insn and replace the old insn with the
2278 new one. Return the new insn if emitted. */
2281 emit_new_cond_insn (rtx insn
, int cond
)
2287 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2290 pat
= PATTERN (insn
);
2292 if (GET_CODE (insn
) == INSN
)
2294 dst
= SET_DEST (pat
);
2295 src
= SET_SRC (pat
);
2299 dst
= JUMP_LABEL (insn
);
2308 c_insn
= gen_movt0 (dst
, src
, dst
);
2310 c_insn
= gen_movt0 (dst
, dst
, src
);
2315 c_insn
= gen_incscc (dst
, dst
);
2317 c_insn
= gen_incscc_false (dst
, dst
);
2322 c_insn
= gen_decscc (dst
, dst
);
2324 c_insn
= gen_decscc_false (dst
, dst
);
2327 case COND_BRANCH_INSN
:
2329 c_insn
= gen_branch_true (dst
);
2331 c_insn
= gen_branch_false (dst
);
2338 /* Only copy the notes if they exist. */
2339 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2341 /* We really don't need to bother with the notes and links at this
2342 point, but go ahead and save the notes. This will help is_dead()
2343 when applying peepholes (links don't matter since they are not
2344 used any more beyond this point for the mcore). */
2345 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2348 if (num
== COND_BRANCH_INSN
)
2350 /* For jumps, we need to be a little bit careful and emit the new jump
2351 before the old one and to update the use count for the target label.
2352 This way, the barrier following the old (uncond) jump will get
2353 deleted, but the label won't. */
2354 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2356 ++ LABEL_NUSES (dst
);
2358 JUMP_LABEL (c_insn
) = dst
;
2361 c_insn
= emit_insn_after (c_insn
, insn
);
2368 /* Attempt to change a basic block into a series of conditional insns. This
2369 works by taking the branch at the end of the 1st block and scanning for the
2370 end of the 2nd block. If all instructions in the 2nd block have cond.
2371 versions and the label at the start of block 3 is the same as the target
2372 from the branch at block 1, then conditionalize all insn in block 2 using
2373 the inverse condition of the branch at block 1. (Note I'm bending the
2374 definition of basic block here.)
2378 bt L2 <-- end of block 1 (delete)
2381 br L3 <-- end of block 2
2383 L2: ... <-- start of block 3 (NUSES==1)
2394 we can delete the L2 label if NUSES==1 and re-apply the optimization
2395 starting at the last instruction of block 2. This may allow an entire
2396 if-then-else statement to be conditionalized. BRC */
2398 conditionalize_block (rtx first
)
2402 rtx end_blk_1_br
= 0;
2403 rtx end_blk_2_insn
= 0;
2404 rtx start_blk_3_lab
= 0;
2410 /* Check that the first insn is a candidate conditional jump. This is
2411 the one that we'll eliminate. If not, advance to the next insn to
2413 if (GET_CODE (first
) != JUMP_INSN
||
2414 GET_CODE (PATTERN (first
)) != SET
||
2415 GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2416 return NEXT_INSN (first
);
2418 /* Extract some information we need. */
2419 end_blk_1_br
= first
;
2420 br_pat
= PATTERN (end_blk_1_br
);
2422 /* Complement the condition since we use the reverse cond. for the insns. */
2423 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2425 /* Determine what kind of branch we have. */
2426 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2428 /* A normal branch, so extract label out of first arm. */
2429 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2433 /* An inverse branch, so extract the label out of the 2nd arm
2434 and complement the condition. */
2436 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2439 /* Scan forward for the start of block 2: it must start with a
2440 label and that label must be the same as the branch target
2441 label from block 1. We don't care about whether block 2 actually
2442 ends with a branch or a label (an uncond. branch is
2443 conditionalizable). */
2444 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2448 code
= GET_CODE (insn
);
2450 /* Look for the label at the start of block 3. */
2451 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2454 /* Skip barriers, notes, and conditionalizable insns. If the
2455 insn is not conditionalizable or makes this optimization fail,
2456 just return the next insn so we can start over from that point. */
2457 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2458 return NEXT_INSN (insn
);
2460 /* Remember the last real insn before the label (i.e. end of block 2). */
2461 if (code
== JUMP_INSN
|| code
== INSN
)
2464 end_blk_2_insn
= insn
;
2471 /* It is possible for this optimization to slow performance if the blocks
2472 are long. This really depends upon whether the branch is likely taken
2473 or not. If the branch is taken, we slow performance in many cases. But,
2474 if the branch is not taken, we always help performance (for a single
2475 block, but for a double block (i.e. when the optimization is re-applied)
2476 this is not true since the 'right thing' depends on the overall length of
2477 the collapsed block). As a compromise, don't apply this optimization on
2478 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2479 the best threshold depends on the latencies of the instructions (i.e.,
2480 the branch penalty). */
2481 if (optimize
> 1 && blk_size
> 2)
2484 /* At this point, we've found the start of block 3 and we know that
2485 it is the destination of the branch from block 1. Also, all
2486 instructions in the block 2 are conditionalizable. So, apply the
2487 conditionalization and delete the branch. */
2488 start_blk_3_lab
= insn
;
2490 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2491 insn
= NEXT_INSN (insn
))
2495 if (INSN_DELETED_P (insn
))
2498 /* Try to form a conditional variant of the instruction and emit it. */
2499 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2501 if (end_blk_2_insn
== insn
)
2502 end_blk_2_insn
= newinsn
;
2508 /* Note whether we will delete the label starting blk 3 when the jump
2509 gets deleted. If so, we want to re-apply this optimization at the
2510 last real instruction right before the label. */
2511 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2513 start_blk_3_lab
= 0;
2516 /* ??? we probably should redistribute the death notes for this insn, esp.
2517 the death of cc, but it doesn't really matter this late in the game.
2518 The peepholes all use is_dead() which will find the correct death
2519 regardless of whether there is a note. */
2520 delete_insn (end_blk_1_br
);
2522 if (! start_blk_3_lab
)
2523 return end_blk_2_insn
;
2525 /* Return the insn right after the label at the start of block 3. */
2526 return NEXT_INSN (start_blk_3_lab
);
2529 /* Apply the conditionalization of blocks optimization. This is the
2530 outer loop that traverses through the insns scanning for a branch
2531 that signifies an opportunity to apply the optimization. Note that
2532 this optimization is applied late. If we could apply it earlier,
2533 say before cse 2, it may expose more optimization opportunities.
2534 but, the pay back probably isn't really worth the effort (we'd have
2535 to update all reg/flow/notes/links/etc to make it work - and stick it
2536 in before cse 2). */
2539 conditionalize_optimization (void)
2543 for (insn
= get_insns (); insn
; insn
= conditionalize_block (insn
))
2547 static int saved_warn_return_type
= -1;
2548 static int saved_warn_return_type_count
= 0;
2550 /* This is to handle loads from the constant pool. */
2555 /* Reset this variable. */
2556 current_function_anonymous_args
= 0;
2558 /* Restore the warn_return_type if it has been altered. */
2559 if (saved_warn_return_type
!= -1)
2561 /* Only restore the value if we have reached another function.
2562 The test of warn_return_type occurs in final_function () in
2563 c-decl.c a long time after the code for the function is generated,
2564 so we need a counter to tell us when we have finished parsing that
2565 function and can restore the flag. */
2566 if (--saved_warn_return_type_count
== 0)
2568 warn_return_type
= saved_warn_return_type
;
2569 saved_warn_return_type
= -1;
2576 /* Conditionalize blocks where we can. */
2577 conditionalize_optimization ();
2579 /* Literal pool generation is now pushed off until the assembler. */
2583 /* Return true if X is something that can be moved directly into r15. */
2586 mcore_r15_operand_p (rtx x
)
2588 switch (GET_CODE (x
))
2591 return mcore_const_ok_for_inline (INTVAL (x
));
2603 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't
2604 directly move X into it, use r1-r14 as a temporary. */
2607 mcore_secondary_reload_class (enum reg_class rclass
,
2608 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2610 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], 15)
2611 && !mcore_r15_operand_p (x
))
2616 /* Return the reg_class to use when reloading the rtx X into the class
2617 RCLASS. If X is too complex to move directly into r15, prefer to
2618 use LRW_REGS instead. */
2621 mcore_reload_class (rtx x
, enum reg_class rclass
)
2623 if (reg_class_subset_p (LRW_REGS
, rclass
) && !mcore_r15_operand_p (x
))
2629 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2630 register. Note that the current version doesn't worry about whether
2631 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2632 in r2 matches an SImode in r2. Might think in the future about whether
2633 we want to be able to say something about modes. */
2636 mcore_is_same_reg (rtx x
, rtx y
)
2638 /* Strip any and all of the subreg wrappers. */
2639 while (GET_CODE (x
) == SUBREG
)
2642 while (GET_CODE (y
) == SUBREG
)
2645 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
2652 mcore_override_options (void)
2654 /* Only the m340 supports little endian code. */
2655 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
2656 target_flags
|= MASK_M340
;
2659 /* Compute the number of word sized registers needed to
2660 hold a function argument of mode MODE and type TYPE. */
2663 mcore_num_arg_regs (enum machine_mode mode
, const_tree type
)
2667 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2670 if (type
&& mode
== BLKmode
)
2671 size
= int_size_in_bytes (type
);
2673 size
= GET_MODE_SIZE (mode
);
2675 return ROUND_ADVANCE (size
);
2679 handle_structs_in_regs (enum machine_mode mode
, const_tree type
, int reg
)
2683 /* The MCore ABI defines that a structure whose size is not a whole multiple
2684 of bytes is passed packed into registers (or spilled onto the stack if
2685 not enough registers are available) with the last few bytes of the
2686 structure being packed, left-justified, into the last register/stack slot.
2687 GCC handles this correctly if the last word is in a stack slot, but we
2688 have to generate a special, PARALLEL RTX if the last word is in an
2689 argument register. */
2691 && TYPE_MODE (type
) == BLKmode
2692 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
2693 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
2694 && (size
% UNITS_PER_WORD
!= 0)
2695 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
2697 rtx arg_regs
[NPARM_REGS
];
2702 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
2705 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
2706 GEN_INT (nregs
* UNITS_PER_WORD
));
2710 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2711 assert (ARRAY_SIZE (arg_regs
) == 6);
2712 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
2713 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
2715 result
= gen_rtx_PARALLEL (mode
, rtvec
);
2719 return gen_rtx_REG (mode
, reg
);
2723 mcore_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
2725 enum machine_mode mode
;
2728 mode
= TYPE_MODE (valtype
);
2730 mode
= promote_mode (valtype
, mode
, &unsigned_p
, 1);
2732 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
2735 /* Define where to put the arguments to a function.
2736 Value is zero to push the argument on the stack,
2737 or a hard register in which to store the argument.
2739 MODE is the argument's machine mode.
2740 TYPE is the data type of the argument (as a tree).
2741 This is null for libcalls where that information may
2743 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2744 the preceding args and about the function being called.
2745 NAMED is nonzero if this argument is a named parameter
2746 (otherwise it is an extra parameter matching an ellipsis).
2748 On MCore the first args are normally in registers
2749 and the rest are pushed. Any arg that starts within the first
2750 NPARM_REGS words is at least partially passed in a register unless
2751 its data type forbids. */
2754 mcore_function_arg (CUMULATIVE_ARGS cum
, enum machine_mode mode
,
2755 tree type
, int named
)
2759 if (! named
|| mode
== VOIDmode
)
2762 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2765 arg_reg
= ROUND_REG (cum
, mode
);
2767 if (arg_reg
< NPARM_REGS
)
2768 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
2773 /* Returns the number of bytes of argument registers required to hold *part*
2774 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2775 the type is not known). If the argument fits entirely in the argument
2776 registers, or entirely on the stack, then 0 is returned. CUM is the
2777 number of argument registers already used by earlier parameters to
2781 mcore_arg_partial_bytes (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
2782 tree type
, bool named
)
2784 int reg
= ROUND_REG (*cum
, mode
);
2789 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2792 /* REG is not the *hardware* register number of the register that holds
2793 the argument, it is the *argument* register number. So for example,
2794 the first argument to a function goes in argument register 0, which
2795 translates (for the MCore) into hardware register 2. The second
2796 argument goes into argument register 1, which translates into hardware
2797 register 3, and so on. NPARM_REGS is the number of argument registers
2798 supported by the target, not the maximum hardware register number of
2800 if (reg
>= NPARM_REGS
)
2803 /* If the argument fits entirely in registers, return 0. */
2804 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
2807 /* The argument overflows the number of available argument registers.
2808 Compute how many argument registers have not yet been assigned to
2809 hold an argument. */
2810 reg
= NPARM_REGS
- reg
;
2812 /* Return partially in registers and partially on the stack. */
2813 return reg
* UNITS_PER_WORD
;
2816 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2819 mcore_dllexport_name_p (const char * symbol
)
2821 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
2824 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2827 mcore_dllimport_name_p (const char * symbol
)
2829 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
2832 /* Mark a DECL as being dllexport'd. */
2835 mcore_mark_dllexport (tree decl
)
2837 const char * oldname
;
2842 rtlname
= XEXP (DECL_RTL (decl
), 0);
2844 if (GET_CODE (rtlname
) == MEM
)
2845 rtlname
= XEXP (rtlname
, 0);
2846 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2847 oldname
= XSTR (rtlname
, 0);
2849 if (mcore_dllexport_name_p (oldname
))
2850 return; /* Already done. */
2852 newname
= XALLOCAVEC (char, strlen (oldname
) + 4);
2853 sprintf (newname
, "@e.%s", oldname
);
2855 /* We pass newname through get_identifier to ensure it has a unique
2856 address. RTL processing can sometimes peek inside the symbol ref
2857 and compare the string's addresses to see if two symbols are
2859 /* ??? At least I think that's why we do this. */
2860 idp
= get_identifier (newname
);
2862 XEXP (DECL_RTL (decl
), 0) =
2863 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2866 /* Mark a DECL as being dllimport'd. */
2869 mcore_mark_dllimport (tree decl
)
2871 const char * oldname
;
2877 rtlname
= XEXP (DECL_RTL (decl
), 0);
2879 if (GET_CODE (rtlname
) == MEM
)
2880 rtlname
= XEXP (rtlname
, 0);
2881 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2882 oldname
= XSTR (rtlname
, 0);
2884 gcc_assert (!mcore_dllexport_name_p (oldname
));
2885 if (mcore_dllimport_name_p (oldname
))
2886 return; /* Already done. */
2888 /* ??? One can well ask why we're making these checks here,
2889 and that would be a good question. */
2891 /* Imported variables can't be initialized. */
2892 if (TREE_CODE (decl
) == VAR_DECL
2893 && !DECL_VIRTUAL_P (decl
)
2894 && DECL_INITIAL (decl
))
2896 error ("initialized variable %q+D is marked dllimport", decl
);
2900 /* `extern' needn't be specified with dllimport.
2901 Specify `extern' now and hope for the best. Sigh. */
2902 if (TREE_CODE (decl
) == VAR_DECL
2903 /* ??? Is this test for vtables needed? */
2904 && !DECL_VIRTUAL_P (decl
))
2906 DECL_EXTERNAL (decl
) = 1;
2907 TREE_PUBLIC (decl
) = 1;
2910 newname
= XALLOCAVEC (char, strlen (oldname
) + 11);
2911 sprintf (newname
, "@i.__imp_%s", oldname
);
2913 /* We pass newname through get_identifier to ensure it has a unique
2914 address. RTL processing can sometimes peek inside the symbol ref
2915 and compare the string's addresses to see if two symbols are
2917 /* ??? At least I think that's why we do this. */
2918 idp
= get_identifier (newname
);
2920 newrtl
= gen_rtx_MEM (Pmode
,
2921 gen_rtx_SYMBOL_REF (Pmode
,
2922 IDENTIFIER_POINTER (idp
)));
2923 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2927 mcore_dllexport_p (tree decl
)
2929 if ( TREE_CODE (decl
) != VAR_DECL
2930 && TREE_CODE (decl
) != FUNCTION_DECL
)
2933 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
2937 mcore_dllimport_p (tree decl
)
2939 if ( TREE_CODE (decl
) != VAR_DECL
2940 && TREE_CODE (decl
) != FUNCTION_DECL
)
2943 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
2946 /* We must mark dll symbols specially. Definitions of dllexport'd objects
2947 install some info in the .drective (PE) or .exports (ELF) sections. */
2950 mcore_encode_section_info (tree decl
, rtx rtl ATTRIBUTE_UNUSED
, int first ATTRIBUTE_UNUSED
)
2952 /* Mark the decl so we can tell from the rtl whether the object is
2953 dllexport'd or dllimport'd. */
2954 if (mcore_dllexport_p (decl
))
2955 mcore_mark_dllexport (decl
);
2956 else if (mcore_dllimport_p (decl
))
2957 mcore_mark_dllimport (decl
);
2959 /* It might be that DECL has already been marked as dllimport, but
2960 a subsequent definition nullified that. The attribute is gone
2961 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
2962 else if ((TREE_CODE (decl
) == FUNCTION_DECL
2963 || TREE_CODE (decl
) == VAR_DECL
)
2964 && DECL_RTL (decl
) != NULL_RTX
2965 && GET_CODE (DECL_RTL (decl
)) == MEM
2966 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
2967 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
2968 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
2970 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
2971 tree idp
= get_identifier (oldname
+ 9);
2972 rtx newrtl
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2974 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2976 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
2977 ??? We leave these alone for now. */
2981 /* Undo the effects of the above. */
2984 mcore_strip_name_encoding (const char * str
)
2986 return str
+ (str
[0] == '@' ? 3 : 0);
2989 /* MCore specific attribute support.
2990 dllexport - for exporting a function/variable that will live in a dll
2991 dllimport - for importing a function/variable from a dll
2992 naked - do not create a function prologue/epilogue. */
2994 const struct attribute_spec mcore_attribute_table
[] =
2996 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2997 { "dllexport", 0, 0, true, false, false, NULL
},
2998 { "dllimport", 0, 0, true, false, false, NULL
},
2999 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
},
3000 { NULL
, 0, 0, false, false, false, NULL
}
3003 /* Handle a "naked" attribute; arguments as in
3004 struct attribute_spec.handler. */
3007 mcore_handle_naked_attribute (tree
* node
, tree name
, tree args ATTRIBUTE_UNUSED
,
3008 int flags ATTRIBUTE_UNUSED
, bool * no_add_attrs
)
3010 if (TREE_CODE (*node
) == FUNCTION_DECL
)
3012 /* PR14310 - don't complain about lack of return statement
3013 in naked functions. The solution here is a gross hack
3014 but this is the only way to solve the problem without
3015 adding a new feature to GCC. I did try submitting a patch
3016 that would add such a new feature, but it was (rightfully)
3017 rejected on the grounds that it was creeping featurism,
3018 so hence this code. */
3019 if (warn_return_type
)
3021 saved_warn_return_type
= warn_return_type
;
3022 warn_return_type
= 0;
3023 saved_warn_return_type_count
= 2;
3025 else if (saved_warn_return_type_count
)
3026 saved_warn_return_type_count
= 2;
3030 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3032 *no_add_attrs
= true;
3038 /* ??? It looks like this is PE specific? Oh well, this is what the
3039 old code did as well. */
3042 mcore_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
3047 const char * prefix
;
3049 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3051 /* Strip off any encoding in name. */
3052 name
= (* targetm
.strip_name_encoding
) (name
);
3054 /* The object is put in, for example, section .text$foo.
3055 The linker will then ultimately place them in .text
3056 (everything from the $ on is stripped). */
3057 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3059 /* For compatibility with EPOC, we ignore the fact that the
3060 section might have relocs against it. */
3061 else if (decl_readonly_section (decl
, 0))
3066 len
= strlen (name
) + strlen (prefix
);
3067 string
= XALLOCAVEC (char, len
+ 1);
3069 sprintf (string
, "%s%s", prefix
, name
);
3071 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
3075 mcore_naked_function_p (void)
3077 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3080 #ifdef OBJECT_FORMAT_ELF
3082 mcore_asm_named_section (const char *name
,
3083 unsigned int flags ATTRIBUTE_UNUSED
,
3084 tree decl ATTRIBUTE_UNUSED
)
3086 fprintf (asm_out_file
, "\t.section %s\n", name
);
3088 #endif /* OBJECT_FORMAT_ELF */
3090 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3093 mcore_external_libcall (rtx fun
)
3095 fprintf (asm_out_file
, "\t.import\t");
3096 assemble_name (asm_out_file
, XSTR (fun
, 0));
3097 fprintf (asm_out_file
, "\n");
3100 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3103 mcore_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3105 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
3106 return (size
== -1 || size
> 2 * UNITS_PER_WORD
);