gcc/config/mips/5400.md

   1 ;; Copyright (C) 2002-2016 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18 ;;
  19 ;; DFA-based pipeline description for 5400
  20 (define_automaton "vr54")
  21 (define_cpu_unit "vr54_dp0"     "vr54")
  22 (define_cpu_unit "vr54_dp1"     "vr54")
  23 (define_cpu_unit "vr54_mem"     "vr54")
  24 (define_cpu_unit "vr54_mac"     "vr54")
  25
  26 ;;
  27 ;; The ordering of the instruction-execution-path/resource-usage
  28 ;; descriptions (also known as reservation RTL) is roughly ordered
  29 ;; based on the define attribute RTL for the "type" classification.
  30 ;; When modifying, remember that the first test that matches is the
  31 ;; reservation used!
  32 ;;
  33
  34 (define_insn_reservation "ir_vr54_unknown" 1
  35   (and (eq_attr "cpu" "r5400")
  36        (eq_attr "type" "unknown,atomic,syncloop"))
  37   "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")
  38
  39 ;; Assume prediction fails.
  40 (define_insn_reservation "ir_vr54_branch" 3
  41   (and (eq_attr "cpu" "r5400")
  42        (eq_attr "type" "branch,jump,call"))
  43   "vr54_dp0|vr54_dp1")
  44
  45 (define_insn_reservation "ir_vr54_load" 2
  46   (and (eq_attr "cpu" "r5400")
  47        (eq_attr "type" "load,fpload,fpidxload"))
  48   "vr54_mem")
  49
  50 (define_insn_reservation "ir_vr54_store" 1
  51   (and (eq_attr "cpu" "r5400")
  52        (eq_attr "type" "store"))
  53   "vr54_mem")
  54
  55 (define_insn_reservation "ir_vr54_fstore" 1
  56   (and (eq_attr "cpu" "r5400")
  57        (eq_attr "type" "fpstore,fpidxstore"))
  58   "vr54_mem")
  59
  60
  61 ;; This reservation is for conditional move based on integer
  62 ;; or floating point CC.
  63 (define_insn_reservation "ir_vr54_condmove" 4
  64   (and (eq_attr "cpu" "r5400")
  65        (eq_attr "type" "condmove"))
  66   "vr54_dp0|vr54_dp1")
  67
  68 ;; Move to/from FPU registers
  69 (define_insn_reservation "ir_vr54_xfer" 2
  70   (and (eq_attr "cpu" "r5400")
  71        (eq_attr "type" "mfc,mtc"))
  72   "vr54_dp0|vr54_dp1")
  73
  74 (define_insn_reservation "ir_vr54_hilo" 1
  75   (and (eq_attr "cpu" "r5400")
  76        (eq_attr "type" "mthi,mtlo,mfhi,mflo"))
  77   "vr54_dp0|vr54_dp1")
  78
  79 (define_insn_reservation "ir_vr54_arith" 1
  80   (and (eq_attr "cpu" "r5400")
  81        (eq_attr "type" "arith,shift,signext,slt,clz,const,logical,move,nop,trap"))
  82   "vr54_dp0|vr54_dp1")
  83
  84 (define_insn_reservation "ir_vr54_imul_si" 3
  85   (and (eq_attr "cpu" "r5400")
  86        (and (eq_attr "type" "imul,imul3")
  87             (eq_attr "mode" "SI")))
  88   "vr54_dp0|vr54_dp1")
  89
  90 (define_insn_reservation "ir_vr54_imul_di" 4
  91   (and (eq_attr "cpu" "r5400")
  92        (and (eq_attr "type" "imul,imul3")
  93             (eq_attr "mode" "DI")))
  94   "vr54_dp0|vr54_dp1")
  95
  96 (define_insn_reservation "ir_vr54_imadd_si" 3
  97   (and (eq_attr "cpu" "r5400")
  98        (eq_attr "type" "imul,imul3"))
  99   "vr54_mac")
 100
 101 (define_insn_reservation "ir_vr54_idiv_si" 42
 102   (and (eq_attr "cpu" "r5400")
 103        (and (eq_attr "type" "idiv")
 104             (eq_attr "mode" "SI")))
 105   "vr54_dp0|vr54_dp1")
 106
 107 (define_insn_reservation "ir_vr54_idiv_di" 74
 108   (and (eq_attr "cpu" "r5400")
 109        (and (eq_attr "type" "idiv")
 110             (eq_attr "mode" "DI")))
 111   "vr54_dp0|vr54_dp1")
 112
 113 (define_insn_reservation "ir_vr54_fadd" 4
 114   (and (eq_attr "cpu" "r5400")
 115        (eq_attr "type" "fadd"))
 116   "vr54_dp0|vr54_dp1")
 117
 118 (define_insn_reservation "ir_vr54_fmul_sf" 5
 119   (and (eq_attr "cpu" "r5400")
 120        (and (eq_attr "type" "fmul")
 121             (eq_attr "mode" "SF")))
 122   "vr54_dp0|vr54_dp1")
 123
 124 (define_insn_reservation "ir_vr54_fmul_df" 6
 125   (and (eq_attr "cpu" "r5400")
 126        (and (eq_attr "type" "fmul")
 127             (eq_attr "mode" "DF")))
 128   "vr54_dp0|vr54_dp1")
 129
 130 (define_insn_reservation "ir_vr54_fmadd_sf" 9
 131   (and (eq_attr "cpu" "r5400")
 132        (and (eq_attr "type" "fmadd")
 133             (eq_attr "mode" "SF")))
 134   "vr54_dp0|vr54_dp1")
 135
 136 (define_insn_reservation "ir_vr54_fmadd_df" 10
 137   (and (eq_attr "cpu" "r5400")
 138        (and (eq_attr "type" "fmadd")
 139             (eq_attr "mode" "DF")))
 140   "vr54_dp0|vr54_dp1")
 141
 142 (define_insn_reservation "ir_vr54_fdiv_sf" 42
 143   (and (eq_attr "cpu" "r5400")
 144        (and (eq_attr "type" "fdiv,frdiv,fsqrt")
 145             (eq_attr "mode" "SF")))
 146   "vr54_dp0|vr54_dp1")
 147
 148 (define_insn_reservation "ir_vr54_fdiv_df" 72
 149   (and (eq_attr "cpu" "r5400")
 150        (and (eq_attr "type" "fdiv,frdiv,fsqrt")
 151             (eq_attr "mode" "DF")))
 152   "vr54_dp0|vr54_dp1")
 153
 154 (define_insn_reservation "ir_vr54_fabs" 2
 155   (and (eq_attr "cpu" "r5400")
 156        (eq_attr "type" "fabs,fneg,fmove"))
 157   "vr54_dp0|vr54_dp1")
 158
 159 (define_insn_reservation "ir_vr54_fcmp" 2
 160   (and (eq_attr "cpu" "r5400")
 161        (eq_attr "type" "fcmp"))
 162   "vr54_dp0|vr54_dp1")
 163
 164 (define_insn_reservation "ir_vr54_fcvt" 6
 165   (and (eq_attr "cpu" "r5400")
 166        (eq_attr "type" "fcvt"))
 167   "vr54_dp0|vr54_dp1")
 168
 169 (define_insn_reservation "ir_vr54_frsqrt_sf" 61
 170   (and (eq_attr "cpu" "r5400")
 171        (and (eq_attr "type" "frsqrt")
 172             (eq_attr "mode" "SF")))
 173   "vr54_dp0|vr54_dp1")
 174
 175 (define_insn_reservation "ir_vr54_frsqrt_df" 121
 176   (and (eq_attr "cpu" "r5400")
 177        (and (eq_attr "type" "frsqrt")
 178             (eq_attr "mode" "DF")))
 179   "vr54_dp0|vr54_dp1")
 180
 181 (define_insn_reservation "ir_vr54_multi" 1
 182   (and (eq_attr "cpu" "r5400")
 183        (eq_attr "type" "multi"))
 184   "vr54_dp0+vr54_dp1+vr54_mem+vr54_mac")