gcc/config/mips/74k.md

   1 ;; DFA-based pipeline description for MIPS32 model 74k.
   2 ;; Contributed by MIPS Technologies and CodeSourcery.
   3 ;;
   4 ;; Reference:
   5 ;;   "MIPS32 74K Microarchitecure Specification Rev. 01.02 Jun 15, 2006"
   6 ;;   "MIPS32 74Kf Processor Core Datasheet Jun 2, 2006"
   7 ;;
   8 ;; Copyright (C) 2007-2019 Free Software Foundation, Inc.
   9 ;;
  10 ;; This file is part of GCC.
  11 ;;
  12 ;; GCC is free software; you can redistribute it and/or modify it
  13 ;; under the terms of the GNU General Public License as published
  14 ;; by the Free Software Foundation; either version 3, or (at your
  15 ;; option) any later version.
  16
  17 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  18 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  19 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  20 ;; License for more details.
  21
  22 ;; You should have received a copy of the GNU General Public License
  23 ;; along with GCC; see the file COPYING3.  If not see
  24 ;; <http://www.gnu.org/licenses/>.
  25
  26 (define_automaton "r74k_mdu_pipe, r74k_alu_pipe, r74k_agen_pipe, r74k_fpu")
  27 (define_cpu_unit "r74k_mul" "r74k_mdu_pipe")
  28 (define_cpu_unit "r74k_alu" "r74k_alu_pipe")
  29 (define_cpu_unit "r74k_agen" "r74k_agen_pipe")
  30 (define_cpu_unit "r74k_fpu_arith" "r74k_fpu")
  31 (define_cpu_unit "r74k_fpu_ldst" "r74k_fpu")
  32
  33 ;; --------------------------------------------------------------
  34 ;; Producers
  35 ;; --------------------------------------------------------------
  36
  37 ;; ALU: Logicals/Arithmetics
  38 ;; - Logicals, move (addu/addiu with rt = 0), Set less than,
  39 ;;   sign extend - 1 cycle
  40 (define_insn_reservation "r74k_int_logical" 1
  41   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  42        (eq_attr "type" "logical,move,signext,slt"))
  43   "r74k_alu")
  44
  45 ;; - Arithmetics - 2 cycles
  46 (define_insn_reservation "r74k_int_arith" 2
  47   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  48        (eq_attr "type" "arith,const,shift,clz"))
  49   "r74k_alu")
  50
  51 (define_insn_reservation "r74k_int_nop" 0
  52   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  53        (eq_attr "type" "nop"))
  54   "nothing")
  55
  56 (define_insn_reservation "r74k_int_cmove" 4
  57   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  58        (eq_attr "type" "condmove"))
  59   "r74k_agen*2")
  60
  61 ;; MDU: fully pipelined multiplier
  62 ;; mult - delivers result to hi/lo in 4 cycle (pipelined)
  63 (define_insn_reservation "r74k_int_mult" 4
  64   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  65        (eq_attr "type" "imul"))
  66   "r74k_alu+r74k_mul")
  67
  68 ;; madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
  69 (define_insn_reservation "r74k_int_madd" 4
  70   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  71        (eq_attr "type" "imadd"))
  72   "r74k_alu+r74k_mul")
  73
  74 ;; mul - delivers result to general register in 7 cycles
  75 (define_insn_reservation "r74k_int_mul3" 7
  76   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  77        (eq_attr "type" "imul3"))
  78   "r74k_alu+r74k_mul")
  79
  80 ;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
  81 (define_insn_reservation "r74k_int_mfhilo" 7
  82   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  83        (eq_attr "type" "mfhi,mflo"))
  84   "r74k_alu+r74k_mul")
  85
  86 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
  87 (define_insn_reservation "r74k_int_mthilo" 7
  88   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  89        (eq_attr "type" "mthi,mtlo"))
  90   "r74k_alu+r74k_mul")
  91
  92 ;; div - default to 50 cycles for 32bit operands.  Faster for 8 bit,
  93 ;; but is tricky to identify.
  94 (define_insn_reservation "r74k_int_div" 50
  95   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
  96        (eq_attr "type" "idiv"))
  97   "r74k_alu+r74k_mul*50")
  98
  99 ;; call
 100 (define_insn_reservation "r74k_int_call" 1
 101   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 102        (eq_attr "type" "call"))
 103   "r74k_agen")
 104
 105 ;; branch/jump
 106 (define_insn_reservation "r74k_int_jump" 1
 107   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 108        (eq_attr "type" "branch,jump"))
 109   "r74k_agen")
 110
 111 ;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
 112 ;; prefetch: prefetch, prefetchx
 113 (define_insn_reservation "r74k_int_load" 3
 114   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 115        (eq_attr "type" "load,prefetch,prefetchx"))
 116   "r74k_agen")
 117
 118 ;; stores
 119 (define_insn_reservation "r74k_int_store" 1
 120   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 121        (eq_attr "type" "store"))
 122   "r74k_agen")
 123
 124
 125 ;; Unknowns - Currently these include blockage, consttable and alignment
 126 ;;            rtls.  They do not really affect scheduling latency, (blockage
 127 ;;            affects scheduling via log links, but not used here).
 128 ;;
 129 (define_insn_reservation "r74k_unknown" 1
 130   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 131        (eq_attr "type" "unknown,atomic,syncloop"))
 132   "r74k_alu")
 133
 134 (define_insn_reservation "r74k_multi" 10
 135   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 136        (eq_attr "type" "multi"))
 137   "(r74k_alu+r74k_agen)*10")
 138
 139 ;; --------------------------------------------------------------
 140 ;; Bypass to Consumer
 141 ;; --------------------------------------------------------------
 142
 143 ;; load->next use :  3 cycles (Default)
 144 ;; load->load base:  4 cycles
 145 ;; load->store base: 4 cycles
 146 (define_bypass 4 "r74k_int_load" "r74k_int_load")
 147 (define_bypass 4 "r74k_int_load" "r74k_int_store" "!mips_store_data_bypass_p")
 148
 149 ;; logical/move/slt/signext->next use :  1 cycles (Default)
 150 ;; logical/move/slt/signext->load base:  2 cycles
 151 ;; logical/move/slt/signext->store base: 2 cycles
 152 (define_bypass 2 "r74k_int_logical" "r74k_int_load")
 153 (define_bypass 2 "r74k_int_logical" "r74k_int_store"
 154   "!mips_store_data_bypass_p")
 155
 156 ;; arith->next use :  2 cycles (Default)
 157 ;; arith->load base:  3 cycles
 158 ;; arith->store base: 3 cycles
 159 (define_bypass 3 "r74k_int_arith" "r74k_int_load")
 160 (define_bypass 3 "r74k_int_arith" "r74k_int_store" "!mips_store_data_bypass_p")
 161
 162 ;; cmove->next use :  4 cycles (Default)
 163 ;; cmove->load base:  5 cycles
 164 ;; cmove->store base: 5 cycles
 165 (define_bypass 5 "r74k_int_cmove"  "r74k_int_load")
 166 (define_bypass 5 "r74k_int_cmove"  "r74k_int_store"
 167   "!mips_store_data_bypass_p")
 168
 169 ;; mult/madd/msub->int_mfhilo  : 4 cycles (default)
 170 ;; mult->madd/msub             : 1 cycles
 171 ;; madd/msub->madd/msub        : 1 cycles
 172 (define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd"
 173   "mips_linked_madd_p")
 174 (define_bypass 1 "r74k_int_madd" "r74k_int_madd"
 175   "mips_linked_madd_p")
 176
 177
 178 ;; --------------------------------------------------------------
 179 ;; DSP instructions
 180 ;; --------------------------------------------------------------
 181
 182 ;; Non-saturating insn have the same latency as normal ALU operations,
 183 (define_insn_reservation "r74k_dsp_alu" 2
 184   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 185        (eq_attr "type" "dspalu"))
 186   "r74k_alu")
 187
 188 ;; Saturating insn takes an extra cycle.
 189 (define_insn_reservation "r74k_dsp_alu_sat" 3
 190   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 191        (eq_attr "type" "dspalusat"))
 192   "r74k_alu")
 193
 194 ;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq
 195 ;; - delivers result to hi/lo in 6 cycle (bypass at M4)
 196 (define_insn_reservation "r74k_dsp_mac" 6
 197   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 198        (eq_attr "type" "dspmac"))
 199   "r74k_alu+r74k_mul")
 200
 201 ;; dpaq_sa, dpsq_sa, maq_sa
 202 ;; - delivers result to hi/lo in 7 cycle (bypass at WB)
 203 (define_insn_reservation "r74k_dsp_mac_sat" 7
 204   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 205        (eq_attr "type" "dspmacsat"))
 206   "r74k_alu+r74k_mul")
 207
 208 ;; extp, extpdp, extpdpv, extpv, extr, extrv
 209 ;; - same latency as "mul"
 210 (define_insn_reservation "r74k_dsp_acc_ext" 7
 211   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 212        (eq_attr "type" "accext"))
 213   "r74k_alu+r74k_mul")
 214
 215 ;; mthlip, shilo, shilov
 216 ;; - same latency as "mul"
 217 (define_insn_reservation "r74k_dsp_acc_mod" 7
 218   (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
 219        (eq_attr "type" "accmod"))
 220   "r74k_alu+r74k_mul")
 221
 222 ;; dspalu   ->load/store base
 223 ;; dspalusat->load/store base
 224 ;; - we should never see these in real life.
 225
 226 ;; dsp_mac->dsp_mac     : 1 cycles (repeat rate of 1)
 227 ;; dsp_mac->dsp_mac_sat : 1 cycles (repeat rate of 1)
 228 (define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac")
 229 (define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac_sat")
 230
 231 ;; dsp_mac_sat->dsp_mac_sat : 2 cycles (repeat rate of 2)
 232 ;; dsp_mac_sat->dsp_mac     : 2 cycles (repeat rate of 2)
 233 (define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac_sat")
 234 (define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac")
 235
 236 (define_bypass 1 "r74k_int_mult" "r74k_dsp_mac")
 237 (define_bypass 1 "r74k_int_mult" "r74k_dsp_mac_sat")
 238
 239 (define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac" "mips_linked_madd_p")
 240 (define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac_sat" "mips_linked_madd_p")
 241
 242 ;; Assuming the following is true (bypass at M4)
 243 ;;  AP AF AM MB M1 M2 M3 M4 WB GR GC
 244 ;;              AP AF AM MB M1 M2 M3 M4 WB GR GC
 245 ;; dsp_mac->dsp_acc_ext : 4 cycles
 246 ;; dsp_mac->dsp_acc_mod : 4 cycles
 247 (define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_ext")
 248 (define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_mod")
 249
 250 ;; Assuming the following is true (bypass at WB)
 251 ;;  AP AF AM MB M1 M2 M3 M4 WB GR GC
 252 ;;                 AP AF AM MB M1 M2 M3 M4 WB GR GC
 253 ;; dsp_mac_sat->dsp_acc_ext : 5 cycles
 254 ;; dsp_mac_sat->dsp_acc_mod : 5 cycles
 255 (define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_ext")
 256 (define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_mod")
 257
 258
 259 ;; --------------------------------------------------------------
 260 ;; Floating Point Instructions
 261 ;; --------------------------------------------------------------
 262
 263 ;; 74Kf FPU runs at 1:1 or 2:1 core/FPU clock ratio.
 264
 265 ;; fadd, fabs, fneg,
 266 (define_insn_reservation "r74kf1_1_fadd" 4
 267   (and (eq_attr "cpu" "74kf1_1")
 268        (eq_attr "type" "fadd,fabs,fneg"))
 269   "r74k_fpu_arith")
 270
 271 (define_insn_reservation "r74kf2_1_fadd" 8
 272   (and (eq_attr "cpu" "74kf2_1")
 273        (eq_attr "type" "fadd,fabs,fneg"))
 274   "r74k_fpu_arith*2")
 275
 276 (define_insn_reservation "r74kf3_2_fadd" 6
 277   (and (eq_attr "cpu" "74kf3_2")
 278        (eq_attr "type" "fadd,fabs,fneg"))
 279   "r74k_fpu_arith")
 280
 281 ;; fmove, fcmove
 282 (define_insn_reservation "r74kf1_1_fmove" 4
 283   (and (eq_attr "cpu" "74kf1_1")
 284        (eq_attr "type" "fmove"))
 285   "r74k_fpu_arith")
 286
 287 (define_insn_reservation "r74kf2_1_fmove" 8
 288   (and (eq_attr "cpu" "74kf2_1")
 289        (eq_attr "type" "fmove"))
 290   "r74k_fpu_arith*2")
 291
 292 (define_insn_reservation "r74kf3_2_fmove" 6
 293   (and (eq_attr "cpu" "74kf3_2")
 294        (eq_attr "type" "fmove"))
 295   "r74k_fpu_arith")
 296
 297 ;; fload
 298 (define_insn_reservation "r74kf1_1_fload" 4
 299   (and (eq_attr "cpu" "74kf1_1")
 300        (eq_attr "type" "fpload,fpidxload"))
 301   "r74k_agen+r74k_fpu_ldst")
 302
 303 (define_insn_reservation "r74kf2_1_fload" 8
 304   (and (eq_attr "cpu" "74kf2_1")
 305        (eq_attr "type" "fpload,fpidxload"))
 306   "r74k_agen+(r74k_fpu_ldst*2)")
 307
 308 (define_insn_reservation "r74kf3_2_fload" 6
 309   (and (eq_attr "cpu" "74kf3_2")
 310        (eq_attr "type" "fpload,fpidxload"))
 311   "r74k_agen+r74k_fpu_ldst")
 312
 313 ;; fstore
 314 (define_insn_reservation "r74kf1_1_fstore" 1
 315   (and (eq_attr "cpu" "74kf1_1")
 316        (eq_attr "type" "fpstore,fpidxstore"))
 317   "r74k_agen+r74k_fpu_ldst")
 318
 319 (define_insn_reservation "r74kf2_1_fstore" 2
 320   (and (eq_attr "cpu" "74kf2_1")
 321        (eq_attr "type" "fpstore,fpidxstore"))
 322   "r74k_agen+(r74k_fpu_ldst*2)")
 323
 324 (define_insn_reservation "r74kf3_2_fstore" 1
 325   (and (eq_attr "cpu" "74kf3_2")
 326        (eq_attr "type" "fpstore,fpidxstore"))
 327   "r74k_agen+r74k_fpu_ldst")
 328
 329 ;; fmul, fmadd
 330 (define_insn_reservation "r74kf1_1_fmul_sf" 4
 331   (and (eq_attr "cpu" "74kf1_1")
 332        (and (eq_attr "type" "fmul,fmadd")
 333             (eq_attr "mode" "SF")))
 334   "r74k_fpu_arith")
 335
 336 (define_insn_reservation "r74kf2_1_fmul_sf" 8
 337   (and (eq_attr "cpu" "74kf2_1")
 338        (and (eq_attr "type" "fmul,fmadd")
 339             (eq_attr "mode" "SF")))
 340   "r74k_fpu_arith*2")
 341
 342 (define_insn_reservation "r74kf3_2_fmul_sf" 6
 343   (and (eq_attr "cpu" "74kf3_2")
 344        (and (eq_attr "type" "fmul,fmadd")
 345             (eq_attr "mode" "SF")))
 346   "r74k_fpu_arith")
 347
 348 (define_insn_reservation "r74kf1_1_fmul_df" 5
 349   (and (eq_attr "cpu" "74kf1_1")
 350        (and (eq_attr "type" "fmul,fmadd")
 351             (eq_attr "mode" "DF")))
 352   "r74k_fpu_arith*2")
 353
 354 (define_insn_reservation "r74kf2_1_fmul_df" 10
 355   (and (eq_attr "cpu" "74kf2_1")
 356        (and (eq_attr "type" "fmul,fmadd")
 357             (eq_attr "mode" "DF")))
 358   "r74k_fpu_arith*4")
 359
 360 (define_insn_reservation "r74kf3_2_fmul_df" 7
 361   (and (eq_attr "cpu" "74kf3_2")
 362        (and (eq_attr "type" "fmul,fmadd")
 363             (eq_attr "mode" "DF")))
 364   "r74k_fpu_arith*2")
 365
 366 ;; fdiv, fsqrt
 367 (define_insn_reservation "r74kf1_1_fdiv_sf" 17
 368   (and (eq_attr "cpu" "74kf1_1")
 369        (and (eq_attr "type" "fdiv,fsqrt")
 370             (eq_attr "mode" "SF")))
 371   "r74k_fpu_arith*14")
 372
 373 (define_insn_reservation "r74kf2_1_fdiv_sf" 34
 374   (and (eq_attr "cpu" "74kf2_1")
 375        (and (eq_attr "type" "fdiv,fsqrt")
 376             (eq_attr "mode" "SF")))
 377   "r74k_fpu_arith*28")
 378
 379 (define_insn_reservation "r74kf3_2_fdiv_sf" 25
 380   (and (eq_attr "cpu" "74kf3_2")
 381        (and (eq_attr "type" "fdiv,fsqrt")
 382             (eq_attr "mode" "SF")))
 383   "r74k_fpu_arith*14")
 384
 385 (define_insn_reservation "r74kf1_1_fdiv_df" 32
 386   (and (eq_attr "cpu" "74kf1_1")
 387        (and (eq_attr "type" "fdiv,fsqrt")
 388             (eq_attr "mode" "DF")))
 389   "r74k_fpu_arith*29")
 390
 391 (define_insn_reservation "r74kf2_1_fdiv_df" 64
 392   (and (eq_attr "cpu" "74kf2_1")
 393        (and (eq_attr "type" "fdiv,fsqrt")
 394             (eq_attr "mode" "DF")))
 395   "r74k_fpu_arith*58")
 396
 397 (define_insn_reservation "r74kf3_2_fdiv_df" 48
 398   (and (eq_attr "cpu" "74kf3_2")
 399        (and (eq_attr "type" "fdiv,fsqrt")
 400             (eq_attr "mode" "DF")))
 401   "r74k_fpu_arith*29")
 402
 403 ;; frsqrt
 404 (define_insn_reservation "r74kf1_1_frsqrt_sf" 17
 405   (and (eq_attr "cpu" "74kf1_1")
 406        (and (eq_attr "type" "frsqrt")
 407             (eq_attr "mode" "SF")))
 408   "r74k_fpu_arith*14")
 409
 410 (define_insn_reservation "r74kf2_1_frsqrt_sf" 34
 411   (and (eq_attr "cpu" "74kf2_1")
 412        (and (eq_attr "type" "frsqrt")
 413             (eq_attr "mode" "SF")))
 414   "r74k_fpu_arith*28")
 415
 416 (define_insn_reservation "r74kf3_2_frsqrt_sf" 25
 417   (and (eq_attr "cpu" "74kf3_2")
 418        (and (eq_attr "type" "frsqrt")
 419             (eq_attr "mode" "SF")))
 420   "r74k_fpu_arith*14")
 421
 422 (define_insn_reservation "r74kf1_1_frsqrt_df" 36
 423   (and (eq_attr "cpu" "74kf1_1")
 424        (and (eq_attr "type" "frsqrt")
 425             (eq_attr "mode" "DF")))
 426   "r74k_fpu_arith*31")
 427
 428 (define_insn_reservation "r74kf2_1_frsqrt_df" 72
 429   (and (eq_attr "cpu" "74kf2_1")
 430        (and (eq_attr "type" "frsqrt")
 431             (eq_attr "mode" "DF")))
 432   "r74k_fpu_arith*62")
 433
 434 (define_insn_reservation "r74kf3_2_frsqrt_df" 54
 435   (and (eq_attr "cpu" "74kf3_2")
 436        (and (eq_attr "type" "frsqrt")
 437             (eq_attr "mode" "DF")))
 438   "r74k_fpu_arith*31")
 439
 440 ;; fcmp
 441 (define_insn_reservation "r74kf1_1_fcmp" 4
 442   (and (eq_attr "cpu" "74kf1_1")
 443        (eq_attr "type" "fcmp"))
 444   "r74k_fpu_arith")
 445
 446 (define_insn_reservation "r74kf2_1_fcmp" 8
 447   (and (eq_attr "cpu" "74kf2_1")
 448        (eq_attr "type" "fcmp"))
 449   "r74k_fpu_arith*2")
 450
 451 (define_insn_reservation "r74kf3_2_fcmp" 6
 452   (and (eq_attr "cpu" "74kf3_2")
 453        (eq_attr "type" "fcmp"))
 454   "r74k_fpu_arith")
 455
 456 ;; fcvt
 457 (define_insn_reservation "r74kf1_1_fcvt" 4
 458   (and (eq_attr "cpu" "74kf1_1")
 459        (eq_attr "type" "fcvt"))
 460   "r74k_fpu_arith")
 461
 462 (define_insn_reservation "r74kf2_1_fcvt" 8
 463   (and (eq_attr "cpu" "74kf2_1")
 464        (eq_attr "type" "fcvt"))
 465   "r74k_fpu_arith*2")
 466
 467 (define_insn_reservation "r74kf3_2_fcvt" 6
 468   (and (eq_attr "cpu" "74kf3_2")
 469        (eq_attr "type" "fcvt"))
 470   "r74k_fpu_arith")
 471
 472 ;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
 473 (define_insn_reservation "r74kf1_1_fxfer_to_c1" 4
 474   (and (eq_attr "cpu" "74kf1_1")
 475        (eq_attr "type" "mtc"))
 476   "r74k_fpu_arith")
 477
 478 (define_insn_reservation "r74kf2_1_fxfer_to_c1" 8
 479   (and (eq_attr "cpu" "74kf2_1")
 480        (eq_attr "type" "mtc"))
 481   "r74k_fpu_arith*2")
 482
 483 (define_insn_reservation "r74kf3_2_fxfer_to_c1" 6
 484   (and (eq_attr "cpu" "74kf3_2")
 485        (eq_attr "type" "mtc"))
 486   "r74k_fpu_arith")
 487
 488 (define_insn_reservation "r74kf1_1_fxfer_from_c1" 1
 489   (and (eq_attr "cpu" "74kf1_1")
 490        (eq_attr "type" "mfc"))
 491   "r74k_fpu_arith")
 492
 493 (define_insn_reservation "r74kf2_1_fxfer_from_c1" 2
 494   (and (eq_attr "cpu" "74kf2_1")
 495        (eq_attr "type" "mfc"))
 496   "r74k_fpu_arith*2")
 497
 498 (define_insn_reservation "r74kf3_2_fxfer_from_c1" 1
 499   (and (eq_attr "cpu" "74kf3_2")
 500        (eq_attr "type" "mfc"))
 501   "r74k_fpu_arith")