gcc/config/mips/constraints.md

   1 ;; Constraint definitions for MIPS.
   2 ;; Copyright (C) 2006-2014 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; Register constraints
  21
  22 (define_register_constraint "d" "BASE_REG_CLASS"
  23   "An address register.  This is equivalent to @code{r} unless
  24    generating MIPS16 code.")
  25
  26 (define_register_constraint "t" "T_REG"
  27   "@internal")
  28
  29 (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
  30   "A floating-point register (if available).")
  31
  32 (define_register_constraint "h" "NO_REGS"
  33   "Formerly the @code{hi} register.  This constraint is no longer supported.")
  34
  35 (define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
  36   "The @code{lo} register.  Use this register to store values that are
  37    no bigger than a word.")
  38
  39 (define_register_constraint "x" "MD_REGS"
  40   "The concatenated @code{hi} and @code{lo} registers.  Use this register
  41    to store doubleword values.")
  42
  43 (define_register_constraint "b" "ALL_REGS"
  44   "@internal")
  45
  46 (define_register_constraint "u" "M16_REGS"
  47   "@internal")
  48
  49 ;; MIPS16 code always calls through a MIPS16 register; see mips_emit_call_insn
  50 ;; for details.
  51 (define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS
  52                                  : TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
  53                                  : GR_REGS"
  54   "A register suitable for use in an indirect jump.  This will always be
  55    @code{$25} for @option{-mabicalls}.")
  56
  57 (define_register_constraint "e" "LEA_REGS"
  58   "@internal")
  59
  60 (define_register_constraint "j" "PIC_FN_ADDR_REG"
  61   "@internal")
  62
  63 ;; Don't use this constraint in gcc code!  It runs the risk of
  64 ;; introducing a spill failure; see tls_get_tp_<mode>.
  65 (define_register_constraint "v" "V1_REG"
  66   "Register @code{$3}.  Do not use this constraint in new code;
  67    it is retained only for compatibility with glibc.")
  68
  69 (define_register_constraint "y" "GR_REGS"
  70   "Equivalent to @code{r}; retained for backwards compatibility.")
  71
  72 (define_register_constraint "z" "ST_REGS"
  73   "A floating-point condition code register.")
  74
  75 (define_register_constraint "A" "DSP_ACC_REGS"
  76   "@internal")
  77
  78 (define_register_constraint "a" "ACC_REGS"
  79   "@internal")
  80
  81 (define_register_constraint "B" "COP0_REGS"
  82   "@internal")
  83
  84 (define_register_constraint "C" "COP2_REGS"
  85   "@internal")
  86
  87 (define_register_constraint "D" "COP3_REGS"
  88   "@internal")
  89
  90 ;; Registers that can be used as the target of multiply-accumulate
  91 ;; instructions.  The core MIPS32 ISA provides a hi/lo madd,
  92 ;; but the DSP version allows any accumulator target.
  93 (define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS")
  94
  95 ;; The register class to use for an allocatable division result.
  96 ;; MIPS16 uses M16_REGS because LO is fixed.
  97 (define_register_constraint "kl"
  98   "TARGET_MIPS16 ? M16_REGS : TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
  99   "@internal")
 100
 101 (define_constraint "kf"
 102   "@internal"
 103   (match_operand 0 "force_to_mem_operand"))
 104
 105 ;; This is a normal rather than a register constraint because we can
 106 ;; never use the stack pointer as a reload register.
 107 (define_constraint "ks"
 108   "@internal"
 109   (and (match_code "reg")
 110        (match_test "REGNO (op) == STACK_POINTER_REGNUM")))
 111
 112 ;; Integer constraints
 113
 114 (define_constraint "I"
 115   "A signed 16-bit constant (for arithmetic instructions)."
 116   (and (match_code "const_int")
 117        (match_test "SMALL_OPERAND (ival)")))
 118
 119 (define_constraint "J"
 120   "Integer zero."
 121   (and (match_code "const_int")
 122        (match_test "ival == 0")))
 123
 124 (define_constraint "K"
 125   "An unsigned 16-bit constant (for logic instructions)."
 126   (and (match_code "const_int")
 127        (match_test "SMALL_OPERAND_UNSIGNED (ival)")))
 128
 129 (define_constraint "L"
 130   "A signed 32-bit constant in which the lower 16 bits are zero.
 131    Such constants can be loaded using @code{lui}."
 132   (and (match_code "const_int")
 133        (match_test "LUI_OPERAND (ival)")))
 134
 135 (define_constraint "M"
 136   "A constant that cannot be loaded using @code{lui}, @code{addiu}
 137    or @code{ori}."
 138   (and (match_code "const_int")
 139        (not (match_test "SMALL_OPERAND (ival)"))
 140        (not (match_test "SMALL_OPERAND_UNSIGNED (ival)"))
 141        (not (match_test "LUI_OPERAND (ival)"))))
 142
 143 (define_constraint "N"
 144   "A constant in the range -65535 to -1 (inclusive)."
 145   (and (match_code "const_int")
 146        (match_test "ival >= -0xffff && ival < 0")))
 147
 148 (define_constraint "O"
 149   "A signed 15-bit constant."
 150   (and (match_code "const_int")
 151        (match_test "ival >= -0x4000 && ival < 0x4000")))
 152
 153 (define_constraint "P"
 154   "A constant in the range 1 to 65535 (inclusive)."
 155   (and (match_code "const_int")
 156        (match_test "ival > 0 && ival < 0x10000")))
 157
 158 ;; Floating-point constraints
 159
 160 (define_constraint "G"
 161   "Floating-point zero."
 162   (and (match_code "const_double")
 163        (match_test "op == CONST0_RTX (mode)")))
 164
 165 ;; General constraints
 166
 167 (define_constraint "Q"
 168   "@internal"
 169   (match_operand 0 "const_arith_operand"))
 170
 171 (define_memory_constraint "R"
 172   "An address that can be used in a non-macro load or store."
 173   (and (match_code "mem")
 174        (match_test "mips_address_insns (XEXP (op, 0), mode, false) == 1")))
 175
 176 (define_constraint "S"
 177   "@internal
 178    A constant call address."
 179   (and (match_operand 0 "call_insn_operand")
 180        (match_test "CONSTANT_P (op)")))
 181
 182 (define_constraint "Udb7"
 183   "@internal
 184    A decremented unsigned constant of 7 bits."
 185   (match_operand 0 "db7_operand"))
 186
 187 (define_constraint "Udb8"
 188   "@internal
 189    A decremented unsigned constant of 8 bits."
 190   (match_operand 0 "db8_operand"))
 191
 192 (define_constraint "Uead"
 193   "@internal
 194    A microMIPS encoded ADDIUR2 immediate operand."
 195   (match_operand 0 "addiur2_operand"))
 196
 197 (define_constraint "Uean"
 198   "@internal
 199    A microMIPS encoded ANDI operand."
 200   (match_operand 0 "andi16_operand"))
 201
 202 (define_constraint "Uesp"
 203   "@internal
 204    A microMIPS encoded ADDIUSP operand."
 205   (match_operand 0 "addiusp_operand"))
 206
 207 (define_constraint "Uib3"
 208   "@internal
 209    An unsigned, incremented constant of 3 bits."
 210   (match_operand 0 "ib3_operand"))
 211
 212 (define_constraint "Usb4"
 213   "@internal
 214    A signed constant of 4 bits."
 215   (match_operand 0 "sb4_operand"))
 216
 217 (define_constraint "Usb5"
 218   "@internal
 219    A signed constant of 5 bits."
 220   (match_operand 0 "sb5_operand"))
 221
 222 (define_constraint "Usb8"
 223   "@internal
 224    A signed constant of 8 bits."
 225   (match_operand 0 "sb8_operand"))
 226
 227 (define_constraint "Usd8"
 228   "@internal
 229    A signed constant of 8 bits, shifted left three places."
 230   (match_operand 0 "sd8_operand"))
 231
 232 (define_constraint "Uub8"
 233   "@internal
 234    An unsigned constant of 8 bits."
 235   (match_operand 0 "ub8_operand"))
 236
 237 (define_constraint "Uuw5"
 238   "@internal
 239    An unsigned constant of 5 bits, shifted left two places."
 240   (match_operand 0 "uw5_operand"))
 241
 242 (define_constraint "Uuw6"
 243   "@internal
 244    An unsigned constant of 6 bits, shifted left two places."
 245   (match_operand 0 "uw6_operand"))
 246
 247 (define_constraint "Uuw8"
 248   "@internal
 249    An unsigned constant of 8 bits, shifted left two places."
 250   (match_operand 0 "uw8_operand"))
 251
 252 (define_memory_constraint "W"
 253   "@internal
 254    A memory address based on a member of @code{BASE_REG_CLASS}.  This is
 255    true for all non-mips16 references (although it can sometimes be implicit
 256    if @samp{!TARGET_EXPLICIT_RELOCS}).  For MIPS16, it excludes stack and
 257    constant-pool references."
 258   (and (match_code "mem")
 259        (match_operand 0 "memory_operand")
 260        (ior (not (match_test "TARGET_MIPS16"))
 261             (and (not (match_operand 0 "stack_operand"))
 262                  (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
 263
 264 (define_constraint "YG"
 265   "@internal
 266    A vector zero."
 267   (and (match_code "const_vector")
 268        (match_test "op == CONST0_RTX (mode)")))
 269
 270 (define_constraint "YA"
 271   "@internal
 272    An unsigned 6-bit constant."
 273   (and (match_code "const_int")
 274        (match_test "UIMM6_OPERAND (ival)")))
 275
 276 (define_constraint "YB"
 277   "@internal
 278    A signed 10-bit constant."
 279   (and (match_code "const_int")
 280        (match_test "IMM10_OPERAND (ival)")))
 281
 282 (define_constraint "Yb"
 283    "@internal"
 284    (match_operand 0 "qi_mask_operand"))
 285
 286 (define_constraint "Yd"
 287   "@internal
 288    A constant @code{move_operand} that can be safely loaded into @code{$25}
 289    using @code{la}."
 290   (and (match_operand 0 "move_operand")
 291        (match_test "CONSTANT_P (op)")
 292        (not (match_test "mips_dangerous_for_la25_p (op)"))))
 293
 294 (define_constraint "Yf"
 295   "@internal
 296    A constant @code{move_operand} that cannot be safely loaded into @code{$25}
 297    using @code{la}."
 298   (and (match_operand 0 "move_operand")
 299        (match_test "CONSTANT_P (op)")
 300        (match_test "mips_dangerous_for_la25_p (op)")))
 301
 302 (define_constraint "Yh"
 303    "@internal"
 304     (match_operand 0 "hi_mask_operand"))
 305
 306 (define_constraint "Yw"
 307    "@internal"
 308     (match_operand 0 "si_mask_operand"))
 309
 310 (define_constraint "Yx"
 311    "@internal"
 312    (match_operand 0 "low_bitmask_operand"))
 313
 314 (define_memory_constraint "ZC"
 315   "When compiling microMIPS code, this constraint matches a memory operand
 316    whose address is formed from a base register and a 12-bit offset.  These
 317    operands can be used for microMIPS instructions such as @code{ll} and
 318    @code{sc}.  When not compiling for microMIPS code, @code{ZC} is
 319    equivalent to @code{R}."
 320   (and (match_code "mem")
 321        (if_then_else
 322          (match_test "TARGET_MICROMIPS")
 323          (match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)")
 324          (match_test "mips_address_insns (XEXP (op, 0), mode, false)"))))
 325
 326 (define_address_constraint "ZD"
 327   "When compiling microMIPS code, this constraint matches an address operand
 328    that is formed from a base register and a 12-bit offset.  These operands
 329    can be used for microMIPS instructions such as @code{prefetch}.  When
 330    not compiling for microMIPS code, @code{ZD} is equivalent to @code{p}."
 331    (if_then_else (match_test "TARGET_MICROMIPS")
 332                  (match_test "umips_12bit_offset_address_p (op, mode)")
 333                  (match_test "mips_address_insns (op, mode, false)")))
 334
 335 (define_memory_constraint "ZR"
 336  "@internal
 337   An address valid for loading/storing register exclusive"
 338  (match_operand 0 "mem_noofs_operand"))
 339
 340 (define_memory_constraint "ZS"
 341   "@internal
 342    A microMIPS memory operand for use with the LWSP/SWSP insns."
 343   (and (match_code "mem")
 344        (match_operand 0 "lwsp_swsp_operand")))
 345
 346 (define_memory_constraint "ZT"
 347   "@internal
 348    A microMIPS memory operand for use with the LW16/SW16 insns."
 349   (and (match_code "mem")
 350        (match_operand 0 "lw16_sw16_operand")))
 351
 352 (define_memory_constraint "ZU"
 353   "@internal
 354    A microMIPS memory operand for use with the LHU16/SH16 insns."
 355   (and (match_code "mem")
 356        (match_operand 0 "lhu16_sh16_operand")))
 357
 358 (define_memory_constraint "ZV"
 359   "@internal
 360    A microMIPS memory operand for use with the SB16 insn."
 361   (and (match_code "mem")
 362        (match_operand 0 "sb16_operand")))
 363
 364 (define_memory_constraint "ZW"
 365   "@internal
 366    A microMIPS memory operand for use with the LBU16 insn."
 367   (and (match_code "mem")
 368        (match_operand 0 "lbu16_operand")))
 369