gcc/config/mips/gs464e.md

   1 ;; Pipeline model for Loongson gs464e cores.
   2
   3 ;; Copyright (C) 2018-2020 Free Software Foundation, Inc.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; Uncomment the following line to output automata for debugging.
  22 ;; (automata_option "v")
  23
  24 ;; Automaton for integer instructions.
  25 (define_automaton "gs464e_a_alu")
  26
  27 ;; Automaton for floating-point instructions.
  28 (define_automaton "gs464e_a_falu")
  29
  30 ;; Automaton for memory operations.
  31 (define_automaton "gs464e_a_mem")
  32
  33 ;; Describe the resources.
  34
  35 (define_cpu_unit "gs464e_alu1" "gs464e_a_alu")
  36 (define_cpu_unit "gs464e_alu2" "gs464e_a_alu")
  37 (define_cpu_unit "gs464e_mem1" "gs464e_a_mem")
  38 (define_cpu_unit "gs464e_mem2" "gs464e_a_mem")
  39 (define_cpu_unit "gs464e_falu1" "gs464e_a_falu")
  40 (define_cpu_unit "gs464e_falu2" "gs464e_a_falu")
  41
  42 ;; Describe instruction reservations.
  43
  44 (define_insn_reservation "gs464e_arith" 1
  45   (and (eq_attr "cpu" "gs464e")
  46        (eq_attr "type" "arith,clz,const,logical,
  47                         move,nop,shift,signext,slt"))
  48   "gs464e_alu1 | gs464e_alu2")
  49
  50 (define_insn_reservation "gs464e_branch" 1
  51   (and (eq_attr "cpu" "gs464e")
  52        (eq_attr "type" "branch,jump,call,condmove,trap"))
  53   "gs464e_alu1 | gs464e_alu2")
  54
  55 (define_insn_reservation "gs464e_mfhilo" 1
  56   (and (eq_attr "cpu" "gs464e")
  57        (eq_attr "type" "mfhi,mflo,mthi,mtlo"))
  58   "gs464e_alu1 | gs464e_alu2")
  59
  60 ;; Operation imul3nc is fully pipelined.
  61 (define_insn_reservation "gs464e_imul3nc" 5
  62   (and (eq_attr "cpu" "gs464e")
  63        (eq_attr "type" "imul3nc"))
  64   "gs464e_alu1 | gs464e_alu2")
  65
  66 (define_insn_reservation "gs464e_imul" 7
  67   (and (eq_attr "cpu" "gs464e")
  68        (eq_attr "type" "imul,imadd"))
  69   "gs464e_alu1 | gs464e_alu2")
  70
  71 (define_insn_reservation "gs464e_idiv_si" 12
  72   (and (eq_attr "cpu" "gs464e")
  73        (and (eq_attr "type" "idiv")
  74             (eq_attr "mode" "SI")))
  75   "gs464e_alu1 | gs464e_alu2")
  76
  77 (define_insn_reservation "gs464e_idiv_di" 25
  78   (and (eq_attr "cpu" "gs464e")
  79        (and (eq_attr "type" "idiv")
  80             (eq_attr "mode" "DI")))
  81   "gs464e_alu1 | gs464e_alu2")
  82
  83 (define_insn_reservation "gs464e_load" 4
  84   (and (eq_attr "cpu" "gs464e")
  85        (eq_attr "type" "load"))
  86   "gs464e_mem1 | gs464e_mem2")
  87
  88 (define_insn_reservation "gs464e_fpload" 5
  89   (and (eq_attr "cpu" "gs464e")
  90        (eq_attr "type" "load,mfc,mtc"))
  91   "gs464e_mem1 | gs464e_mem2")
  92
  93 (define_insn_reservation "gs464e_prefetch" 0
  94   (and (eq_attr "cpu" "gs464e")
  95        (eq_attr "type" "prefetch,prefetchx"))
  96   "gs464e_mem1 | gs464e_mem2")
  97
  98 (define_insn_reservation "gs464e_store" 0
  99   (and (eq_attr "cpu" "gs464e")
 100        (eq_attr "type" "store,fpstore,fpidxstore"))
 101   "gs464e_mem1 | gs464e_mem2")
 102
 103 (define_insn_reservation "gs464e_fadd" 4
 104   (and (eq_attr "cpu" "gs464e")
 105        (eq_attr "type" "fadd,fmul,fmadd"))
 106   "gs464e_falu1 | gs464e_falu2")
 107
 108 (define_insn_reservation "gs464e_fcmp" 2
 109   (and (eq_attr "cpu" "gs464e")
 110        (eq_attr "type" "fabs,fcmp,fmove,fneg"))
 111   "gs464e_falu1 | gs464e_falu2")
 112
 113 (define_insn_reservation "gs464e_fcvt" 4
 114   (and (eq_attr "cpu" "gs464e")
 115        (eq_attr "type" "fcvt"))
 116   "gs464e_falu1 | gs464e_falu2")
 117
 118 (define_insn_reservation "gs464e_fdiv_sf" 12
 119   (and (eq_attr "cpu" "gs464e")
 120        (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
 121             (eq_attr "mode" "SF")))
 122   "gs464e_falu1 | gs464e_falu2")
 123
 124 (define_insn_reservation "gs464e_fdiv_df" 19
 125   (and (eq_attr "cpu" "gs464e")
 126        (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
 127             (eq_attr "mode" "DF")))
 128   "gs464e_falu1 | gs464e_falu2")
 129
 130 ;; Force single-dispatch for unknown or multi.
 131 (define_insn_reservation "gs464e_unknown" 1
 132   (and (eq_attr "cpu" "gs464e")
 133        (eq_attr "type" "unknown,multi,atomic,syncloop"))
 134   "gs464e_alu1 + gs464e_alu2 + gs464e_falu1
 135    + gs464e_falu2 + gs464e_mem1 + gs464e_mem2")
 136
 137 ;; End of DFA-based pipeline description for gs464e