gcc/config/mips/mips-dsp.md

   1 ;; Copyright (C) 2005-2013 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18
  19 ;; MIPS DSP ASE Revision 0.98 3/24/2005
  20 (define_c_enum "unspec" [
  21   UNSPEC_ADDQ
  22   UNSPEC_ADDQ_S
  23   UNSPEC_SUBQ
  24   UNSPEC_SUBQ_S
  25   UNSPEC_ADDSC
  26   UNSPEC_ADDWC
  27   UNSPEC_MODSUB
  28   UNSPEC_RADDU_W_QB
  29   UNSPEC_ABSQ_S
  30   UNSPEC_PRECRQ_QB_PH
  31   UNSPEC_PRECRQ_PH_W
  32   UNSPEC_PRECRQ_RS_PH_W
  33   UNSPEC_PRECRQU_S_QB_PH
  34   UNSPEC_PRECEQ_W_PHL
  35   UNSPEC_PRECEQ_W_PHR
  36   UNSPEC_PRECEQU_PH_QBL
  37   UNSPEC_PRECEQU_PH_QBR
  38   UNSPEC_PRECEQU_PH_QBLA
  39   UNSPEC_PRECEQU_PH_QBRA
  40   UNSPEC_PRECEU_PH_QBL
  41   UNSPEC_PRECEU_PH_QBR
  42   UNSPEC_PRECEU_PH_QBLA
  43   UNSPEC_PRECEU_PH_QBRA
  44   UNSPEC_SHLL
  45   UNSPEC_SHLL_S
  46   UNSPEC_SHRL_QB
  47   UNSPEC_SHRA_PH
  48   UNSPEC_SHRA_R
  49   UNSPEC_MULEU_S_PH_QBL
  50   UNSPEC_MULEU_S_PH_QBR
  51   UNSPEC_MULQ_RS_PH
  52   UNSPEC_MULEQ_S_W_PHL
  53   UNSPEC_MULEQ_S_W_PHR
  54   UNSPEC_DPAU_H_QBL
  55   UNSPEC_DPAU_H_QBR
  56   UNSPEC_DPSU_H_QBL
  57   UNSPEC_DPSU_H_QBR
  58   UNSPEC_DPAQ_S_W_PH
  59   UNSPEC_DPSQ_S_W_PH
  60   UNSPEC_MULSAQ_S_W_PH
  61   UNSPEC_DPAQ_SA_L_W
  62   UNSPEC_DPSQ_SA_L_W
  63   UNSPEC_MAQ_S_W_PHL
  64   UNSPEC_MAQ_S_W_PHR
  65   UNSPEC_MAQ_SA_W_PHL
  66   UNSPEC_MAQ_SA_W_PHR
  67   UNSPEC_BITREV
  68   UNSPEC_INSV
  69   UNSPEC_REPL_QB
  70   UNSPEC_REPL_PH
  71   UNSPEC_CMP_EQ
  72   UNSPEC_CMP_LT
  73   UNSPEC_CMP_LE
  74   UNSPEC_CMPGU_EQ_QB
  75   UNSPEC_CMPGU_LT_QB
  76   UNSPEC_CMPGU_LE_QB
  77   UNSPEC_PICK
  78   UNSPEC_PACKRL_PH
  79   UNSPEC_EXTR_W
  80   UNSPEC_EXTR_R_W
  81   UNSPEC_EXTR_RS_W
  82   UNSPEC_EXTR_S_H
  83   UNSPEC_EXTP
  84   UNSPEC_EXTPDP
  85   UNSPEC_SHILO
  86   UNSPEC_MTHLIP
  87   UNSPEC_WRDSP
  88   UNSPEC_RDDSP
  89 ])
  90
  91 (define_constants
  92   [(CCDSP_PO_REGNUM     182)
  93    (CCDSP_SC_REGNUM     183)
  94    (CCDSP_CA_REGNUM     184)
  95    (CCDSP_OU_REGNUM     185)
  96    (CCDSP_CC_REGNUM     186)
  97    (CCDSP_EF_REGNUM     187)])
  98
  99 ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE.
 100 (define_mode_iterator DSP [(SI "ISA_HAS_DSP")
 101                            (V2HI "ISA_HAS_DSP")
 102                            (V4QI "ISA_HAS_DSP")])
 103
 104 ;; This mode iterator allows v2hi, v4qi for vector/SIMD data.
 105 (define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP")
 106                             (V4QI "ISA_HAS_DSP")])
 107
 108 ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data.
 109 (define_mode_iterator DSPQ [(SI "ISA_HAS_DSP")
 110                             (V2HI "ISA_HAS_DSP")])
 111
 112 ;; DSP instructions use q for fixed-point data, and u for integer in the infix.
 113 (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
 114
 115 ;; DSP instructions use nothing for fixed-point data, and u for integer in
 116 ;; the infix.
 117 (define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")])
 118
 119 ;; DSP instructions use w, ph, qb in the postfix.
 120 (define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")])
 121
 122 ;; DSP shift masks for SI, V2HI, V4QI.
 123 (define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")])
 124
 125 ;; MIPS DSP ASE Revision 0.98 3/24/2005
 126 ;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic
 127 ;; ADDQ*
 128 (define_insn "add<DSPV:mode>3"
 129   [(parallel
 130     [(set (match_operand:DSPV 0 "register_operand" "=d")
 131           (plus:DSPV (match_operand:DSPV 1 "register_operand" "d")
 132                      (match_operand:DSPV 2 "register_operand" "d")))
 133      (set (reg:CCDSP CCDSP_OU_REGNUM)
 134           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])]
 135   "ISA_HAS_DSP"
 136   "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
 137   [(set_attr "type"     "dspalu")
 138    (set_attr "mode"     "SI")])
 139
 140 (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>"
 141   [(parallel
 142     [(set (match_operand:DSP 0 "register_operand" "=d")
 143           (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
 144                        (match_operand:DSP 2 "register_operand" "d")]
 145                       UNSPEC_ADDQ_S))
 146      (set (reg:CCDSP CCDSP_OU_REGNUM)
 147           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
 148   "ISA_HAS_DSP"
 149   "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
 150   [(set_attr "type"     "dspalusat")
 151    (set_attr "mode"     "SI")])
 152
 153 ;; SUBQ*
 154 (define_insn "sub<DSPV:mode>3"
 155   [(parallel
 156     [(set (match_operand:DSPV 0 "register_operand" "=d")
 157           (minus:DSPV (match_operand:DSPV 1 "register_operand" "d")
 158                       (match_operand:DSPV 2 "register_operand" "d")))
 159      (set (reg:CCDSP CCDSP_OU_REGNUM)
 160           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
 161   "ISA_HAS_DSP"
 162   "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
 163   [(set_attr "type"     "dspalu")
 164    (set_attr "mode"     "SI")])
 165
 166 (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>"
 167   [(parallel
 168     [(set (match_operand:DSP 0 "register_operand" "=d")
 169           (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
 170                        (match_operand:DSP 2 "register_operand" "d")]
 171                       UNSPEC_SUBQ_S))
 172      (set (reg:CCDSP CCDSP_OU_REGNUM)
 173           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
 174   "ISA_HAS_DSP"
 175   "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
 176   [(set_attr "type"     "dspalusat")
 177    (set_attr "mode"     "SI")])
 178
 179 ;; ADDSC
 180 (define_insn "mips_addsc"
 181   [(parallel
 182     [(set (match_operand:SI 0 "register_operand" "=d")
 183           (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 184                       (match_operand:SI 2 "register_operand" "d")]
 185                      UNSPEC_ADDSC))
 186      (set (reg:CCDSP CCDSP_CA_REGNUM)
 187           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
 188   "ISA_HAS_DSP"
 189   "addsc\t%0,%1,%2"
 190   [(set_attr "type"     "dspalu")
 191    (set_attr "mode"     "SI")])
 192
 193 ;; ADDWC
 194 (define_insn "mips_addwc"
 195   [(parallel
 196     [(set (match_operand:SI 0 "register_operand" "=d")
 197           (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 198                       (match_operand:SI 2 "register_operand" "d")
 199                     (reg:CCDSP CCDSP_CA_REGNUM)]
 200                      UNSPEC_ADDWC))
 201      (set (reg:CCDSP CCDSP_OU_REGNUM)
 202           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
 203   "ISA_HAS_DSP"
 204   "addwc\t%0,%1,%2"
 205   [(set_attr "type"     "dspalu")
 206    (set_attr "mode"     "SI")])
 207
 208 ;; MODSUB
 209 (define_insn "mips_modsub"
 210   [(set (match_operand:SI 0 "register_operand" "=d")
 211         (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 212                     (match_operand:SI 2 "register_operand" "d")]
 213                    UNSPEC_MODSUB))]
 214   "ISA_HAS_DSP"
 215   "modsub\t%0,%1,%2"
 216   [(set_attr "type"     "dspalu")
 217    (set_attr "mode"     "SI")])
 218
 219 ;; RADDU*
 220 (define_insn "mips_raddu_w_qb"
 221   [(set (match_operand:SI 0 "register_operand" "=d")
 222         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
 223                    UNSPEC_RADDU_W_QB))]
 224   "ISA_HAS_DSP"
 225   "raddu.w.qb\t%0,%1"
 226   [(set_attr "type"     "dspalu")
 227    (set_attr "mode"     "SI")])
 228
 229 ;; ABSQ*
 230 (define_insn "mips_absq_s_<DSPQ:dspfmt2>"
 231   [(parallel
 232     [(set (match_operand:DSPQ 0 "register_operand" "=d")
 233           (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")]
 234                        UNSPEC_ABSQ_S))
 235      (set (reg:CCDSP CCDSP_OU_REGNUM)
 236           (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
 237   "ISA_HAS_DSP"
 238   "absq_s.<DSPQ:dspfmt2>\t%0,%1"
 239   [(set_attr "type"     "dspalusat")
 240    (set_attr "mode"     "SI")])
 241
 242 ;; PRECRQ*
 243 (define_insn "mips_precrq_qb_ph"
 244   [(set (match_operand:V4QI 0 "register_operand" "=d")
 245         (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
 246                       (match_operand:V2HI 2 "register_operand" "d")]
 247                      UNSPEC_PRECRQ_QB_PH))]
 248   "ISA_HAS_DSP"
 249   "precrq.qb.ph\t%0,%1,%2"
 250   [(set_attr "type"     "dspalu")
 251    (set_attr "mode"     "SI")])
 252
 253 (define_insn "mips_precrq_ph_w"
 254   [(set (match_operand:V2HI 0 "register_operand" "=d")
 255         (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
 256                       (match_operand:SI 2 "register_operand" "d")]
 257                      UNSPEC_PRECRQ_PH_W))]
 258   "ISA_HAS_DSP"
 259   "precrq.ph.w\t%0,%1,%2"
 260   [(set_attr "type"     "dspalu")
 261    (set_attr "mode"     "SI")])
 262
 263 (define_insn "mips_precrq_rs_ph_w"
 264   [(parallel
 265     [(set (match_operand:V2HI 0 "register_operand" "=d")
 266           (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
 267                         (match_operand:SI 2 "register_operand" "d")]
 268                        UNSPEC_PRECRQ_RS_PH_W))
 269      (set (reg:CCDSP CCDSP_OU_REGNUM)
 270           (unspec:CCDSP [(match_dup 1) (match_dup 2)]
 271                         UNSPEC_PRECRQ_RS_PH_W))])]
 272   "ISA_HAS_DSP"
 273   "precrq_rs.ph.w\t%0,%1,%2"
 274   [(set_attr "type"     "dspalu")
 275    (set_attr "mode"     "SI")])
 276
 277 ;; PRECRQU*
 278 (define_insn "mips_precrqu_s_qb_ph"
 279   [(parallel
 280     [(set (match_operand:V4QI 0 "register_operand" "=d")
 281           (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
 282                         (match_operand:V2HI 2 "register_operand" "d")]
 283                        UNSPEC_PRECRQU_S_QB_PH))
 284      (set (reg:CCDSP CCDSP_OU_REGNUM)
 285           (unspec:CCDSP [(match_dup 1) (match_dup 2)]
 286                         UNSPEC_PRECRQU_S_QB_PH))])]
 287   "ISA_HAS_DSP"
 288   "precrqu_s.qb.ph\t%0,%1,%2"
 289   [(set_attr "type"     "dspalusat")
 290    (set_attr "mode"     "SI")])
 291
 292 ;; PRECEQ*
 293 (define_insn "mips_preceq_w_phl"
 294   [(set (match_operand:SI 0 "register_operand" "=d")
 295         (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
 296                    UNSPEC_PRECEQ_W_PHL))]
 297   "ISA_HAS_DSP"
 298   "preceq.w.phl\t%0,%1"
 299   [(set_attr "type"     "dspalu")
 300    (set_attr "mode"     "SI")])
 301
 302 (define_insn "mips_preceq_w_phr"
 303   [(set (match_operand:SI 0 "register_operand" "=d")
 304         (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
 305                    UNSPEC_PRECEQ_W_PHR))]
 306   "ISA_HAS_DSP"
 307   "preceq.w.phr\t%0,%1"
 308   [(set_attr "type"     "dspalu")
 309    (set_attr "mode"     "SI")])
 310
 311 ;; PRECEQU*
 312 (define_insn "mips_precequ_ph_qbl"
 313   [(set (match_operand:V2HI 0 "register_operand" "=d")
 314         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 315                      UNSPEC_PRECEQU_PH_QBL))]
 316   "ISA_HAS_DSP"
 317   "precequ.ph.qbl\t%0,%1"
 318   [(set_attr "type"     "dspalu")
 319    (set_attr "mode"     "SI")])
 320
 321 (define_insn "mips_precequ_ph_qbr"
 322   [(set (match_operand:V2HI 0 "register_operand" "=d")
 323         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 324                      UNSPEC_PRECEQU_PH_QBR))]
 325   "ISA_HAS_DSP"
 326   "precequ.ph.qbr\t%0,%1"
 327   [(set_attr "type"     "dspalu")
 328    (set_attr "mode"     "SI")])
 329
 330 (define_insn "mips_precequ_ph_qbla"
 331   [(set (match_operand:V2HI 0 "register_operand" "=d")
 332         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 333                      UNSPEC_PRECEQU_PH_QBLA))]
 334   "ISA_HAS_DSP"
 335   "precequ.ph.qbla\t%0,%1"
 336   [(set_attr "type"     "dspalu")
 337    (set_attr "mode"     "SI")])
 338
 339 (define_insn "mips_precequ_ph_qbra"
 340   [(set (match_operand:V2HI 0 "register_operand" "=d")
 341         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 342                      UNSPEC_PRECEQU_PH_QBRA))]
 343   "ISA_HAS_DSP"
 344   "precequ.ph.qbra\t%0,%1"
 345   [(set_attr "type"     "dspalu")
 346    (set_attr "mode"     "SI")])
 347
 348 ;; PRECEU*
 349 (define_insn "mips_preceu_ph_qbl"
 350   [(set (match_operand:V2HI 0 "register_operand" "=d")
 351         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 352                      UNSPEC_PRECEU_PH_QBL))]
 353   "ISA_HAS_DSP"
 354   "preceu.ph.qbl\t%0,%1"
 355   [(set_attr "type"     "dspalu")
 356    (set_attr "mode"     "SI")])
 357
 358 (define_insn "mips_preceu_ph_qbr"
 359   [(set (match_operand:V2HI 0 "register_operand" "=d")
 360         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 361                      UNSPEC_PRECEU_PH_QBR))]
 362   "ISA_HAS_DSP"
 363   "preceu.ph.qbr\t%0,%1"
 364   [(set_attr "type"     "dspalu")
 365    (set_attr "mode"     "SI")])
 366
 367 (define_insn "mips_preceu_ph_qbla"
 368   [(set (match_operand:V2HI 0 "register_operand" "=d")
 369         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 370                      UNSPEC_PRECEU_PH_QBLA))]
 371   "ISA_HAS_DSP"
 372   "preceu.ph.qbla\t%0,%1"
 373   [(set_attr "type"     "dspalu")
 374    (set_attr "mode"     "SI")])
 375
 376 (define_insn "mips_preceu_ph_qbra"
 377   [(set (match_operand:V2HI 0 "register_operand" "=d")
 378         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 379                      UNSPEC_PRECEU_PH_QBRA))]
 380   "ISA_HAS_DSP"
 381   "preceu.ph.qbra\t%0,%1"
 382   [(set_attr "type"     "dspalu")
 383    (set_attr "mode"     "SI")])
 384
 385 ;; Table 2-2. MIPS DSP ASE Instructions: Shift
 386 ;; SHLL*
 387 (define_insn "mips_shll_<DSPV:dspfmt2>"
 388   [(parallel
 389     [(set (match_operand:DSPV 0 "register_operand" "=d,d")
 390           (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d")
 391                         (match_operand:SI 2 "arith_operand" "I,d")]
 392                        UNSPEC_SHLL))
 393      (set (reg:CCDSP CCDSP_OU_REGNUM)
 394           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
 395   "ISA_HAS_DSP"
 396 {
 397   if (which_alternative == 0)
 398     {
 399       if (INTVAL (operands[2])
 400           & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>)
 401         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>);
 402       return "shll.<DSPV:dspfmt2>\t%0,%1,%2";
 403     }
 404   return "shllv.<DSPV:dspfmt2>\t%0,%1,%2";
 405 }
 406   [(set_attr "type"     "dspalu")
 407    (set_attr "mode"     "SI")])
 408
 409 (define_insn "mips_shll_s_<DSPQ:dspfmt2>"
 410   [(parallel
 411     [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
 412           (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
 413                         (match_operand:SI 2 "arith_operand" "I,d")]
 414                        UNSPEC_SHLL_S))
 415      (set (reg:CCDSP CCDSP_OU_REGNUM)
 416           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
 417   "ISA_HAS_DSP"
 418 {
 419   if (which_alternative == 0)
 420     {
 421       if (INTVAL (operands[2])
 422           & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
 423         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
 424       return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2";
 425     }
 426   return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2";
 427 }
 428   [(set_attr "type"     "dspalusat")
 429    (set_attr "mode"     "SI")])
 430
 431 ;; SHRL*
 432 (define_insn "mips_shrl_qb"
 433   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 434         (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
 435                       (match_operand:SI 2 "arith_operand" "I,d")]
 436                      UNSPEC_SHRL_QB))]
 437   "ISA_HAS_DSP"
 438 {
 439   if (which_alternative == 0)
 440     {
 441       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7)
 442         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7);
 443       return "shrl.qb\t%0,%1,%2";
 444     }
 445   return "shrlv.qb\t%0,%1,%2";
 446 }
 447   [(set_attr "type"     "dspalu")
 448    (set_attr "mode"     "SI")])
 449
 450 ;; SHRA*
 451 (define_insn "mips_shra_ph"
 452   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 453         (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
 454                       (match_operand:SI 2 "arith_operand" "I,d")]
 455                      UNSPEC_SHRA_PH))]
 456   "ISA_HAS_DSP"
 457 {
 458   if (which_alternative == 0)
 459     {
 460       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf)
 461         operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf);
 462       return "shra.ph\t%0,%1,%2";
 463     }
 464   return "shrav.ph\t%0,%1,%2";
 465 }
 466   [(set_attr "type"     "dspalu")
 467    (set_attr "mode"     "SI")])
 468
 469 (define_insn "mips_shra_r_<DSPQ:dspfmt2>"
 470   [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
 471         (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
 472                       (match_operand:SI 2 "arith_operand" "I,d")]
 473                      UNSPEC_SHRA_R))]
 474   "ISA_HAS_DSP"
 475 {
 476   if (which_alternative == 0)
 477     {
 478       if (INTVAL (operands[2])
 479           & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
 480         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
 481       return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2";
 482     }
 483   return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2";
 484 }
 485   [(set_attr "type"     "dspalu")
 486    (set_attr "mode"     "SI")])
 487
 488 ;; Table 2-3. MIPS DSP ASE Instructions: Multiply
 489 ;; MULEU*
 490 (define_insn "mips_muleu_s_ph_qbl"
 491   [(parallel
 492     [(set (match_operand:V2HI 0 "register_operand" "=d")
 493           (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
 494                         (match_operand:V2HI 2 "register_operand" "d")]
 495                        UNSPEC_MULEU_S_PH_QBL))
 496      (set (reg:CCDSP CCDSP_OU_REGNUM)
 497           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
 498      (clobber (match_scratch:DI 3 "=x"))])]
 499   "ISA_HAS_DSP"
 500   "muleu_s.ph.qbl\t%0,%1,%2"
 501   [(set_attr "type"     "imul3")
 502    (set_attr "mode"     "SI")])
 503
 504 (define_insn "mips_muleu_s_ph_qbr"
 505   [(parallel
 506     [(set (match_operand:V2HI 0 "register_operand" "=d")
 507           (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
 508                         (match_operand:V2HI 2 "register_operand" "d")]
 509                        UNSPEC_MULEU_S_PH_QBR))
 510      (set (reg:CCDSP CCDSP_OU_REGNUM)
 511           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
 512      (clobber (match_scratch:DI 3 "=x"))])]
 513   "ISA_HAS_DSP"
 514   "muleu_s.ph.qbr\t%0,%1,%2"
 515   [(set_attr "type"     "imul3")
 516    (set_attr "mode"     "SI")])
 517
 518 ;; MULQ*
 519 (define_insn "mips_mulq_rs_ph"
 520   [(parallel
 521     [(set (match_operand:V2HI 0 "register_operand" "=d")
 522           (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
 523                         (match_operand:V2HI 2 "register_operand" "d")]
 524                        UNSPEC_MULQ_RS_PH))
 525      (set (reg:CCDSP CCDSP_OU_REGNUM)
 526           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
 527      (clobber (match_scratch:DI 3 "=x"))])]
 528   "ISA_HAS_DSP"
 529   "mulq_rs.ph\t%0,%1,%2"
 530   [(set_attr "type"     "imul3")
 531    (set_attr "mode"     "SI")])
 532
 533 ;; MULEQ*
 534 (define_insn "mips_muleq_s_w_phl"
 535   [(parallel
 536     [(set (match_operand:SI 0 "register_operand" "=d")
 537           (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
 538                       (match_operand:V2HI 2 "register_operand" "d")]
 539                      UNSPEC_MULEQ_S_W_PHL))
 540      (set (reg:CCDSP CCDSP_OU_REGNUM)
 541           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
 542      (clobber (match_scratch:DI 3 "=x"))])]
 543   "ISA_HAS_DSP"
 544   "muleq_s.w.phl\t%0,%1,%2"
 545   [(set_attr "type"     "imul3")
 546    (set_attr "mode"     "SI")])
 547
 548 (define_insn "mips_muleq_s_w_phr"
 549   [(parallel
 550     [(set (match_operand:SI 0 "register_operand" "=d")
 551           (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
 552                       (match_operand:V2HI 2 "register_operand" "d")]
 553                      UNSPEC_MULEQ_S_W_PHR))
 554      (set (reg:CCDSP CCDSP_OU_REGNUM)
 555           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
 556      (clobber (match_scratch:DI 3 "=x"))])]
 557   "ISA_HAS_DSP"
 558   "muleq_s.w.phr\t%0,%1,%2"
 559   [(set_attr "type"     "imul3")
 560    (set_attr "mode"     "SI")])
 561
 562 ;; DPAU*
 563 (define_insn "mips_dpau_h_qbl"
 564   [(set (match_operand:DI 0 "register_operand" "=a")
 565         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 566                     (match_operand:V4QI 2 "register_operand" "d")
 567                     (match_operand:V4QI 3 "register_operand" "d")]
 568                    UNSPEC_DPAU_H_QBL))]
 569   "ISA_HAS_DSP && !TARGET_64BIT"
 570   "dpau.h.qbl\t%q0,%2,%3"
 571   [(set_attr "type"     "dspmac")
 572    (set_attr "accum_in" "1")
 573    (set_attr "mode"     "SI")])
 574
 575 (define_insn "mips_dpau_h_qbr"
 576   [(set (match_operand:DI 0 "register_operand" "=a")
 577         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 578                     (match_operand:V4QI 2 "register_operand" "d")
 579                     (match_operand:V4QI 3 "register_operand" "d")]
 580                    UNSPEC_DPAU_H_QBR))]
 581   "ISA_HAS_DSP && !TARGET_64BIT"
 582   "dpau.h.qbr\t%q0,%2,%3"
 583   [(set_attr "type"     "dspmac")
 584    (set_attr "accum_in" "1")
 585    (set_attr "mode"     "SI")])
 586
 587 ;; DPSU*
 588 (define_insn "mips_dpsu_h_qbl"
 589   [(set (match_operand:DI 0 "register_operand" "=a")
 590         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 591                     (match_operand:V4QI 2 "register_operand" "d")
 592                     (match_operand:V4QI 3 "register_operand" "d")]
 593                    UNSPEC_DPSU_H_QBL))]
 594   "ISA_HAS_DSP && !TARGET_64BIT"
 595   "dpsu.h.qbl\t%q0,%2,%3"
 596   [(set_attr "type"     "dspmac")
 597    (set_attr "accum_in" "1")
 598    (set_attr "mode"     "SI")])
 599
 600 (define_insn "mips_dpsu_h_qbr"
 601   [(set (match_operand:DI 0 "register_operand" "=a")
 602         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 603                     (match_operand:V4QI 2 "register_operand" "d")
 604                     (match_operand:V4QI 3 "register_operand" "d")]
 605                    UNSPEC_DPSU_H_QBR))]
 606   "ISA_HAS_DSP && !TARGET_64BIT"
 607   "dpsu.h.qbr\t%q0,%2,%3"
 608   [(set_attr "type"     "dspmac")
 609    (set_attr "accum_in" "1")
 610    (set_attr "mode"     "SI")])
 611
 612 ;; DPAQ*
 613 (define_insn "mips_dpaq_s_w_ph"
 614   [(parallel
 615     [(set (match_operand:DI 0 "register_operand" "=a")
 616           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 617                       (match_operand:V2HI 2 "register_operand" "d")
 618                       (match_operand:V2HI 3 "register_operand" "d")]
 619                      UNSPEC_DPAQ_S_W_PH))
 620      (set (reg:CCDSP CCDSP_OU_REGNUM)
 621           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 622                         UNSPEC_DPAQ_S_W_PH))])]
 623   "ISA_HAS_DSP && !TARGET_64BIT"
 624   "dpaq_s.w.ph\t%q0,%2,%3"
 625   [(set_attr "type"     "dspmac")
 626    (set_attr "accum_in" "1")
 627    (set_attr "mode"     "SI")])
 628
 629 ;; DPSQ*
 630 (define_insn "mips_dpsq_s_w_ph"
 631   [(parallel
 632     [(set (match_operand:DI 0 "register_operand" "=a")
 633           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 634                       (match_operand:V2HI 2 "register_operand" "d")
 635                       (match_operand:V2HI 3 "register_operand" "d")]
 636                      UNSPEC_DPSQ_S_W_PH))
 637      (set (reg:CCDSP CCDSP_OU_REGNUM)
 638           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 639                         UNSPEC_DPSQ_S_W_PH))])]
 640   "ISA_HAS_DSP && !TARGET_64BIT"
 641   "dpsq_s.w.ph\t%q0,%2,%3"
 642   [(set_attr "type"     "dspmac")
 643    (set_attr "accum_in" "1")
 644    (set_attr "mode"     "SI")])
 645
 646 ;; MULSAQ*
 647 (define_insn "mips_mulsaq_s_w_ph"
 648   [(parallel
 649     [(set (match_operand:DI 0 "register_operand" "=a")
 650           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 651                       (match_operand:V2HI 2 "register_operand" "d")
 652                       (match_operand:V2HI 3 "register_operand" "d")]
 653                      UNSPEC_MULSAQ_S_W_PH))
 654      (set (reg:CCDSP CCDSP_OU_REGNUM)
 655           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 656                         UNSPEC_MULSAQ_S_W_PH))])]
 657   "ISA_HAS_DSP && !TARGET_64BIT"
 658   "mulsaq_s.w.ph\t%q0,%2,%3"
 659   [(set_attr "type"     "dspmac")
 660    (set_attr "accum_in" "1")
 661    (set_attr "mode"     "SI")])
 662
 663 ;; DPAQ*
 664 (define_insn "mips_dpaq_sa_l_w"
 665   [(parallel
 666     [(set (match_operand:DI 0 "register_operand" "=a")
 667           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 668                       (match_operand:SI 2 "register_operand" "d")
 669                       (match_operand:SI 3 "register_operand" "d")]
 670                      UNSPEC_DPAQ_SA_L_W))
 671      (set (reg:CCDSP CCDSP_OU_REGNUM)
 672           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 673                         UNSPEC_DPAQ_SA_L_W))])]
 674   "ISA_HAS_DSP && !TARGET_64BIT"
 675   "dpaq_sa.l.w\t%q0,%2,%3"
 676   [(set_attr "type"     "dspmacsat")
 677    (set_attr "accum_in" "1")
 678    (set_attr "mode"     "SI")])
 679
 680 ;; DPSQ*
 681 (define_insn "mips_dpsq_sa_l_w"
 682   [(parallel
 683     [(set (match_operand:DI 0 "register_operand" "=a")
 684           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 685                       (match_operand:SI 2 "register_operand" "d")
 686                       (match_operand:SI 3 "register_operand" "d")]
 687                      UNSPEC_DPSQ_SA_L_W))
 688      (set (reg:CCDSP CCDSP_OU_REGNUM)
 689           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 690                         UNSPEC_DPSQ_SA_L_W))])]
 691   "ISA_HAS_DSP && !TARGET_64BIT"
 692   "dpsq_sa.l.w\t%q0,%2,%3"
 693   [(set_attr "type"     "dspmacsat")
 694    (set_attr "accum_in" "1")
 695    (set_attr "mode"     "SI")])
 696
 697 ;; MAQ*
 698 (define_insn "mips_maq_s_w_phl"
 699   [(parallel
 700     [(set (match_operand:DI 0 "register_operand" "=a")
 701           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 702                       (match_operand:V2HI 2 "register_operand" "d")
 703                       (match_operand:V2HI 3 "register_operand" "d")]
 704                      UNSPEC_MAQ_S_W_PHL))
 705      (set (reg:CCDSP CCDSP_OU_REGNUM)
 706           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 707                         UNSPEC_MAQ_S_W_PHL))])]
 708   "ISA_HAS_DSP && !TARGET_64BIT"
 709   "maq_s.w.phl\t%q0,%2,%3"
 710   [(set_attr "type"     "dspmac")
 711    (set_attr "accum_in" "1")
 712    (set_attr "mode"     "SI")])
 713
 714 (define_insn "mips_maq_s_w_phr"
 715   [(parallel
 716     [(set (match_operand:DI 0 "register_operand" "=a")
 717           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 718                       (match_operand:V2HI 2 "register_operand" "d")
 719                       (match_operand:V2HI 3 "register_operand" "d")]
 720                      UNSPEC_MAQ_S_W_PHR))
 721      (set (reg:CCDSP CCDSP_OU_REGNUM)
 722           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 723                         UNSPEC_MAQ_S_W_PHR))])]
 724   "ISA_HAS_DSP && !TARGET_64BIT"
 725   "maq_s.w.phr\t%q0,%2,%3"
 726   [(set_attr "type"     "dspmac")
 727    (set_attr "accum_in" "1")
 728    (set_attr "mode"     "SI")])
 729
 730 ;; MAQ_SA*
 731 (define_insn "mips_maq_sa_w_phl"
 732   [(parallel
 733     [(set (match_operand:DI 0 "register_operand" "=a")
 734           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 735                       (match_operand:V2HI 2 "register_operand" "d")
 736                       (match_operand:V2HI 3 "register_operand" "d")]
 737                      UNSPEC_MAQ_SA_W_PHL))
 738      (set (reg:CCDSP CCDSP_OU_REGNUM)
 739           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 740                         UNSPEC_MAQ_SA_W_PHL))])]
 741   "ISA_HAS_DSP && !TARGET_64BIT"
 742   "maq_sa.w.phl\t%q0,%2,%3"
 743   [(set_attr "type"     "dspmacsat")
 744    (set_attr "accum_in" "1")
 745    (set_attr "mode"     "SI")])
 746
 747 (define_insn "mips_maq_sa_w_phr"
 748   [(parallel
 749     [(set (match_operand:DI 0 "register_operand" "=a")
 750           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 751                       (match_operand:V2HI 2 "register_operand" "d")
 752                       (match_operand:V2HI 3 "register_operand" "d")]
 753                      UNSPEC_MAQ_SA_W_PHR))
 754      (set (reg:CCDSP CCDSP_OU_REGNUM)
 755           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 756                         UNSPEC_MAQ_SA_W_PHR))])]
 757   "ISA_HAS_DSP && !TARGET_64BIT"
 758   "maq_sa.w.phr\t%q0,%2,%3"
 759   [(set_attr "type"     "dspmacsat")
 760    (set_attr "accum_in" "1")
 761    (set_attr "mode"     "SI")])
 762
 763 ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation
 764 ;; BITREV
 765 (define_insn "mips_bitrev"
 766   [(set (match_operand:SI 0 "register_operand" "=d")
 767         (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
 768                    UNSPEC_BITREV))]
 769   "ISA_HAS_DSP"
 770   "bitrev\t%0,%1"
 771   [(set_attr "type"     "dspalu")
 772    (set_attr "mode"     "SI")])
 773
 774 ;; INSV
 775 (define_insn "mips_insv"
 776   [(set (match_operand:SI 0 "register_operand" "=d")
 777         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
 778                     (match_operand:SI 2 "register_operand" "d")
 779                     (reg:CCDSP CCDSP_SC_REGNUM)
 780                     (reg:CCDSP CCDSP_PO_REGNUM)]
 781                    UNSPEC_INSV))]
 782   "ISA_HAS_DSP"
 783   "insv\t%0,%2"
 784   [(set_attr "type"     "dspalu")
 785    (set_attr "mode"     "SI")])
 786
 787 ;; REPL*
 788 (define_insn "mips_repl_qb"
 789   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 790         (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
 791                      UNSPEC_REPL_QB))]
 792   "ISA_HAS_DSP"
 793 {
 794   if (which_alternative == 0)
 795     {
 796       if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff)
 797         operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
 798       return "repl.qb\t%0,%1";
 799     }
 800   return "replv.qb\t%0,%1";
 801 }
 802   [(set_attr "type"     "dspalu")
 803    (set_attr "mode"     "SI")])
 804
 805 (define_insn "mips_repl_ph"
 806   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 807         (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
 808                      UNSPEC_REPL_PH))]
 809   "ISA_HAS_DSP"
 810   "@
 811    repl.ph\t%0,%1
 812    replv.ph\t%0,%1"
 813   [(set_attr "type"     "dspalu")
 814    (set_attr "mode"     "SI")])
 815
 816 ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick
 817 ;; CMPU.* CMP.*
 818 (define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>"
 819   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 820         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 821                        (match_operand:DSPV 1 "register_operand" "d")
 822                        (reg:CCDSP CCDSP_CC_REGNUM)]
 823                       UNSPEC_CMP_EQ))]
 824   "ISA_HAS_DSP"
 825   "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1"
 826   [(set_attr "type"     "dspalu")
 827    (set_attr "mode"     "SI")])
 828
 829 (define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>"
 830   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 831         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 832                        (match_operand:DSPV 1 "register_operand" "d")
 833                        (reg:CCDSP CCDSP_CC_REGNUM)]
 834                       UNSPEC_CMP_LT))]
 835   "ISA_HAS_DSP"
 836   "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1"
 837   [(set_attr "type"     "dspalu")
 838    (set_attr "mode"     "SI")])
 839
 840 (define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>"
 841   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 842         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 843                        (match_operand:DSPV 1 "register_operand" "d")
 844                        (reg:CCDSP CCDSP_CC_REGNUM)]
 845                       UNSPEC_CMP_LE))]
 846   "ISA_HAS_DSP"
 847   "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1"
 848   [(set_attr "type"     "dspalu")
 849    (set_attr "mode"     "SI")])
 850
 851 (define_insn "mips_cmpgu_eq_qb"
 852   [(set (match_operand:SI 0 "register_operand" "=d")
 853         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 854                     (match_operand:V4QI 2 "register_operand" "d")]
 855                    UNSPEC_CMPGU_EQ_QB))]
 856   "ISA_HAS_DSP"
 857   "cmpgu.eq.qb\t%0,%1,%2"
 858   [(set_attr "type"     "dspalu")
 859    (set_attr "mode"     "SI")])
 860
 861 (define_insn "mips_cmpgu_lt_qb"
 862   [(set (match_operand:SI 0 "register_operand" "=d")
 863         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 864                     (match_operand:V4QI 2 "register_operand" "d")]
 865                    UNSPEC_CMPGU_LT_QB))]
 866   "ISA_HAS_DSP"
 867   "cmpgu.lt.qb\t%0,%1,%2"
 868   [(set_attr "type"     "dspalu")
 869    (set_attr "mode"     "SI")])
 870
 871 (define_insn "mips_cmpgu_le_qb"
 872   [(set (match_operand:SI 0 "register_operand" "=d")
 873         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 874                     (match_operand:V4QI 2 "register_operand" "d")]
 875                    UNSPEC_CMPGU_LE_QB))]
 876   "ISA_HAS_DSP"
 877   "cmpgu.le.qb\t%0,%1,%2"
 878   [(set_attr "type"     "dspalu")
 879    (set_attr "mode"     "SI")])
 880
 881 ;; PICK*
 882 (define_insn "mips_pick_<DSPV:dspfmt2>"
 883   [(set (match_operand:DSPV 0 "register_operand" "=d")
 884         (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d")
 885                       (match_operand:DSPV 2 "register_operand" "d")
 886                       (reg:CCDSP CCDSP_CC_REGNUM)]
 887                      UNSPEC_PICK))]
 888   "ISA_HAS_DSP"
 889   "pick.<DSPV:dspfmt2>\t%0,%1,%2"
 890   [(set_attr "type"     "dspalu")
 891    (set_attr "mode"     "SI")])
 892
 893 ;; PACKRL*
 894 (define_insn "mips_packrl_ph"
 895   [(set (match_operand:V2HI 0 "register_operand" "=d")
 896         (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
 897                       (match_operand:V2HI 2 "register_operand" "d")]
 898                      UNSPEC_PACKRL_PH))]
 899   "ISA_HAS_DSP"
 900   "packrl.ph\t%0,%1,%2"
 901   [(set_attr "type"     "dspalu")
 902    (set_attr "mode"     "SI")])
 903
 904 ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
 905 ;; EXTR*
 906 (define_insn "mips_extr_w"
 907   [(parallel
 908     [(set (match_operand:SI 0 "register_operand" "=d,d")
 909           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 910                       (match_operand:SI 2 "arith_operand" "I,d")]
 911                      UNSPEC_EXTR_W))
 912      (set (reg:CCDSP CCDSP_OU_REGNUM)
 913           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
 914   "ISA_HAS_DSP && !TARGET_64BIT"
 915 {
 916   if (which_alternative == 0)
 917     {
 918       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 919         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 920       return "extr.w\t%0,%q1,%2";
 921     }
 922   return "extrv.w\t%0,%q1,%2";
 923 }
 924   [(set_attr "type"     "accext")
 925    (set_attr "mode"     "SI")])
 926
 927 (define_insn "mips_extr_r_w"
 928   [(parallel
 929     [(set (match_operand:SI 0 "register_operand" "=d,d")
 930           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 931                       (match_operand:SI 2 "arith_operand" "I,d")]
 932                      UNSPEC_EXTR_R_W))
 933      (set (reg:CCDSP CCDSP_OU_REGNUM)
 934           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
 935   "ISA_HAS_DSP && !TARGET_64BIT"
 936 {
 937   if (which_alternative == 0)
 938     {
 939       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 940         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 941       return "extr_r.w\t%0,%q1,%2";
 942     }
 943   return "extrv_r.w\t%0,%q1,%2";
 944 }
 945   [(set_attr "type"     "accext")
 946    (set_attr "mode"     "SI")])
 947
 948 (define_insn "mips_extr_rs_w"
 949   [(parallel
 950     [(set (match_operand:SI 0 "register_operand" "=d,d")
 951           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 952                       (match_operand:SI 2 "arith_operand" "I,d")]
 953                      UNSPEC_EXTR_RS_W))
 954      (set (reg:CCDSP CCDSP_OU_REGNUM)
 955           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
 956   "ISA_HAS_DSP && !TARGET_64BIT"
 957 {
 958   if (which_alternative == 0)
 959     {
 960       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 961         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 962       return "extr_rs.w\t%0,%q1,%2";
 963     }
 964   return "extrv_rs.w\t%0,%q1,%2";
 965 }
 966   [(set_attr "type"     "accext")
 967    (set_attr "mode"     "SI")])
 968
 969 ;; EXTR*_S.H
 970 (define_insn "mips_extr_s_h"
 971   [(parallel
 972     [(set (match_operand:SI 0 "register_operand" "=d,d")
 973           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 974                       (match_operand:SI 2 "arith_operand" "I,d")]
 975                      UNSPEC_EXTR_S_H))
 976      (set (reg:CCDSP CCDSP_OU_REGNUM)
 977           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
 978   "ISA_HAS_DSP && !TARGET_64BIT"
 979 {
 980   if (which_alternative == 0)
 981     {
 982       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 983         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 984       return "extr_s.h\t%0,%q1,%2";
 985     }
 986   return "extrv_s.h\t%0,%q1,%2";
 987 }
 988   [(set_attr "type"     "accext")
 989    (set_attr "mode"     "SI")])
 990
 991 ;; EXTP*
 992 (define_insn "mips_extp"
 993   [(parallel
 994     [(set (match_operand:SI 0 "register_operand" "=d,d")
 995           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 996                       (match_operand:SI 2 "arith_operand" "I,d")
 997                       (reg:CCDSP CCDSP_PO_REGNUM)]
 998                      UNSPEC_EXTP))
 999      (set (reg:CCDSP CCDSP_EF_REGNUM)
1000           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
1001   "ISA_HAS_DSP && !TARGET_64BIT"
1002 {
1003   if (which_alternative == 0)
1004     {
1005       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
1006         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
1007       return "extp\t%0,%q1,%2";
1008     }
1009   return "extpv\t%0,%q1,%2";
1010 }
1011   [(set_attr "type"     "accext")
1012    (set_attr "mode"     "SI")])
1013
1014 (define_insn "mips_extpdp"
1015   [(parallel
1016     [(set (match_operand:SI 0 "register_operand" "=d,d")
1017           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
1018                       (match_operand:SI 2 "arith_operand" "I,d")
1019                       (reg:CCDSP CCDSP_PO_REGNUM)]
1020                      UNSPEC_EXTPDP))
1021      (set (reg:CCDSP CCDSP_PO_REGNUM)
1022           (unspec:CCDSP [(match_dup 1) (match_dup 2)
1023                          (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
1024      (set (reg:CCDSP CCDSP_EF_REGNUM)
1025           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
1026   "ISA_HAS_DSP && !TARGET_64BIT"
1027 {
1028   if (which_alternative == 0)
1029     {
1030       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
1031         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
1032       return "extpdp\t%0,%q1,%2";
1033     }
1034   return "extpdpv\t%0,%q1,%2";
1035 }
1036   [(set_attr "type"     "accext")
1037    (set_attr "mode"     "SI")])
1038
1039 ;; SHILO*
1040 (define_insn "mips_shilo"
1041   [(set (match_operand:DI 0 "register_operand" "=a,a")
1042         (unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
1043                     (match_operand:SI 2 "arith_operand" "I,d")]
1044                    UNSPEC_SHILO))]
1045   "ISA_HAS_DSP && !TARGET_64BIT"
1046 {
1047   if (which_alternative == 0)
1048     {
1049       if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31)
1050         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
1051       return "shilo\t%q0,%2";
1052     }
1053   return "shilov\t%q0,%2";
1054 }
1055   [(set_attr "type"     "accmod")
1056    (set_attr "mode"     "SI")])
1057
1058 ;; MTHLIP*
1059 (define_insn "mips_mthlip"
1060   [(parallel
1061     [(set (match_operand:DI 0 "register_operand" "=a")
1062           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1063                       (match_operand:SI 2 "register_operand" "d")
1064                       (reg:CCDSP CCDSP_PO_REGNUM)]
1065                      UNSPEC_MTHLIP))
1066      (set (reg:CCDSP CCDSP_PO_REGNUM)
1067           (unspec:CCDSP [(match_dup 1) (match_dup 2)
1068                          (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
1069   "ISA_HAS_DSP && !TARGET_64BIT"
1070   "mthlip\t%2,%q0"
1071   [(set_attr "type"     "accmod")
1072    (set_attr "mode"     "SI")])
1073
1074 ;; WRDSP
1075 (define_insn "mips_wrdsp"
1076   [(parallel
1077     [(set (reg:CCDSP CCDSP_PO_REGNUM)
1078           (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d")
1079                          (match_operand:SI 1 "const_uimm6_operand" "YA")]
1080                          UNSPEC_WRDSP))
1081      (set (reg:CCDSP CCDSP_SC_REGNUM)
1082           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1083      (set (reg:CCDSP CCDSP_CA_REGNUM)
1084           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1085      (set (reg:CCDSP CCDSP_OU_REGNUM)
1086           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1087      (set (reg:CCDSP CCDSP_CC_REGNUM)
1088           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1089      (set (reg:CCDSP CCDSP_EF_REGNUM)
1090           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
1091   "ISA_HAS_DSP"
1092   "wrdsp\t%0,%1"
1093   [(set_attr "type"     "dspalu")
1094    (set_attr "mode"     "SI")])
1095
1096 ;; RDDSP
1097 (define_insn "mips_rddsp"
1098   [(set (match_operand:SI 0 "register_operand" "=d")
1099         (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA")
1100                     (reg:CCDSP CCDSP_PO_REGNUM)
1101                     (reg:CCDSP CCDSP_SC_REGNUM)
1102                     (reg:CCDSP CCDSP_CA_REGNUM)
1103                     (reg:CCDSP CCDSP_OU_REGNUM)
1104                     (reg:CCDSP CCDSP_CC_REGNUM)
1105                     (reg:CCDSP CCDSP_EF_REGNUM)]
1106                    UNSPEC_RDDSP))]
1107   "ISA_HAS_DSP"
1108   "rddsp\t%0,%1"
1109   [(set_attr "type"     "dspalu")
1110    (set_attr "mode"     "SI")])
1111
1112 ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load
1113 ;; L*X
1114 (define_expand "mips_lbux"
1115   [(match_operand:SI 0 "register_operand")
1116    (match_operand 1 "pmode_register_operand")
1117    (match_operand:SI 2 "register_operand")]
1118   "ISA_HAS_DSP"
1119 {
1120   operands[2] = convert_to_mode (Pmode, operands[2], false);
1121   emit_insn (PMODE_INSN (gen_mips_lbux_extsi,
1122                          (operands[0], operands[1], operands[2])));
1123   DONE;
1124 })
1125
1126 (define_insn "mips_l<SHORT:size><u>x_ext<GPR:mode>_<P:mode>"
1127   [(set (match_operand:GPR 0 "register_operand" "=d")
1128         (any_extend:GPR
1129           (mem:SHORT (plus:P (match_operand:P 1 "register_operand" "d")
1130                              (match_operand:P 2 "register_operand" "d")))))]
1131   "ISA_HAS_L<SHORT:SIZE><U>X"
1132   "l<SHORT:size><u>x\t%0,%2(%1)"
1133   [(set_attr "type"     "load")
1134    (set_attr "mode"     "<GPR:MODE>")])
1135
1136 (define_expand "mips_lhx"
1137   [(match_operand:SI 0 "register_operand")
1138    (match_operand 1 "pmode_register_operand")
1139    (match_operand:SI 2 "register_operand")]
1140   "ISA_HAS_DSP"
1141 {
1142   operands[2] = convert_to_mode (Pmode, operands[2], false);
1143   emit_insn (PMODE_INSN (gen_mips_lhx_extsi,
1144                          (operands[0], operands[1], operands[2])));
1145   DONE;
1146 })
1147
1148 (define_expand "mips_l<size>x"
1149   [(match_operand:GPR 0 "register_operand")
1150    (match_operand 1 "pmode_register_operand")
1151    (match_operand:SI 2 "register_operand")]
1152   "ISA_HAS_DSP"
1153 {
1154   operands[2] = convert_to_mode (Pmode, operands[2], false);
1155   emit_insn (PMODE_INSN (gen_mips_l<size>x,
1156                          (operands[0], operands[1], operands[2])));
1157   DONE;
1158 })
1159
1160 (define_insn "mips_l<GPR:size>x_<P:mode>"
1161   [(set (match_operand:GPR 0 "register_operand" "=d")
1162         (mem:GPR (plus:P (match_operand:P 1 "register_operand" "d")
1163                          (match_operand:P 2 "register_operand" "d"))))]
1164   "ISA_HAS_L<GPR:SIZE>X"
1165   "l<GPR:size>x\t%0,%2(%1)"
1166   [(set_attr "type"     "load")
1167    (set_attr "mode"     "<GPR:MODE>")])
1168
1169 (define_insn "*mips_lw<u>x_<P:mode>_ext"
1170   [(set (match_operand:DI 0 "register_operand" "=d")
1171         (any_extend:DI
1172           (mem:SI (plus:P (match_operand:P 1 "register_operand" "d")
1173                              (match_operand:P 2 "register_operand" "d")))))]
1174   "ISA_HAS_LW<U>X && TARGET_64BIT"
1175   "lw<u>x\t%0,%2(%1)"
1176   [(set_attr "type"     "load")
1177    (set_attr "mode"     "DI")])
1178
1179 ;; Table 2-8. MIPS DSP ASE Instructions: Branch
1180 ;; BPOSGE32
1181 (define_insn "mips_bposge"
1182   [(set (pc)
1183         (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM)
1184                           (match_operand:SI 1 "immediate_operand" "I"))
1185                       (label_ref (match_operand 0 "" ""))
1186                       (pc)))]
1187   "ISA_HAS_DSP"
1188   "%*bposge%1\t%0%/"
1189   [(set_attr "type"     "branch")])
1190
1191 (define_expand "mips_madd<u>"
1192   [(set (match_operand:DI 0 "register_operand")
1193         (plus:DI
1194          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1195                   (any_extend:DI (match_operand:SI 3 "register_operand")))
1196          (match_operand:DI 1 "register_operand")))]
1197   "ISA_HAS_DSP && !TARGET_64BIT")
1198
1199 (define_expand "mips_msub<u>"
1200   [(set (match_operand:DI 0 "register_operand")
1201         (minus:DI
1202          (match_operand:DI 1 "register_operand")
1203          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1204                   (any_extend:DI (match_operand:SI 3 "register_operand")))))]
1205   "ISA_HAS_DSP && !TARGET_64BIT")