gcc/config/mips/mips-dsp.md

   1 ;; Copyright (C) 2005, 2006, 2007, 2008, 2010, 2011, 2012
   2 ;; Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; MIPS DSP ASE Revision 0.98 3/24/2005
  21 (define_c_enum "unspec" [
  22   UNSPEC_ADDQ
  23   UNSPEC_ADDQ_S
  24   UNSPEC_SUBQ
  25   UNSPEC_SUBQ_S
  26   UNSPEC_ADDSC
  27   UNSPEC_ADDWC
  28   UNSPEC_MODSUB
  29   UNSPEC_RADDU_W_QB
  30   UNSPEC_ABSQ_S
  31   UNSPEC_PRECRQ_QB_PH
  32   UNSPEC_PRECRQ_PH_W
  33   UNSPEC_PRECRQ_RS_PH_W
  34   UNSPEC_PRECRQU_S_QB_PH
  35   UNSPEC_PRECEQ_W_PHL
  36   UNSPEC_PRECEQ_W_PHR
  37   UNSPEC_PRECEQU_PH_QBL
  38   UNSPEC_PRECEQU_PH_QBR
  39   UNSPEC_PRECEQU_PH_QBLA
  40   UNSPEC_PRECEQU_PH_QBRA
  41   UNSPEC_PRECEU_PH_QBL
  42   UNSPEC_PRECEU_PH_QBR
  43   UNSPEC_PRECEU_PH_QBLA
  44   UNSPEC_PRECEU_PH_QBRA
  45   UNSPEC_SHLL
  46   UNSPEC_SHLL_S
  47   UNSPEC_SHRL_QB
  48   UNSPEC_SHRA_PH
  49   UNSPEC_SHRA_R
  50   UNSPEC_MULEU_S_PH_QBL
  51   UNSPEC_MULEU_S_PH_QBR
  52   UNSPEC_MULQ_RS_PH
  53   UNSPEC_MULEQ_S_W_PHL
  54   UNSPEC_MULEQ_S_W_PHR
  55   UNSPEC_DPAU_H_QBL
  56   UNSPEC_DPAU_H_QBR
  57   UNSPEC_DPSU_H_QBL
  58   UNSPEC_DPSU_H_QBR
  59   UNSPEC_DPAQ_S_W_PH
  60   UNSPEC_DPSQ_S_W_PH
  61   UNSPEC_MULSAQ_S_W_PH
  62   UNSPEC_DPAQ_SA_L_W
  63   UNSPEC_DPSQ_SA_L_W
  64   UNSPEC_MAQ_S_W_PHL
  65   UNSPEC_MAQ_S_W_PHR
  66   UNSPEC_MAQ_SA_W_PHL
  67   UNSPEC_MAQ_SA_W_PHR
  68   UNSPEC_BITREV
  69   UNSPEC_INSV
  70   UNSPEC_REPL_QB
  71   UNSPEC_REPL_PH
  72   UNSPEC_CMP_EQ
  73   UNSPEC_CMP_LT
  74   UNSPEC_CMP_LE
  75   UNSPEC_CMPGU_EQ_QB
  76   UNSPEC_CMPGU_LT_QB
  77   UNSPEC_CMPGU_LE_QB
  78   UNSPEC_PICK
  79   UNSPEC_PACKRL_PH
  80   UNSPEC_EXTR_W
  81   UNSPEC_EXTR_R_W
  82   UNSPEC_EXTR_RS_W
  83   UNSPEC_EXTR_S_H
  84   UNSPEC_EXTP
  85   UNSPEC_EXTPDP
  86   UNSPEC_SHILO
  87   UNSPEC_MTHLIP
  88   UNSPEC_WRDSP
  89   UNSPEC_RDDSP
  90 ])
  91
  92 (define_constants
  93   [(CCDSP_PO_REGNUM     182)
  94    (CCDSP_SC_REGNUM     183)
  95    (CCDSP_CA_REGNUM     184)
  96    (CCDSP_OU_REGNUM     185)
  97    (CCDSP_CC_REGNUM     186)
  98    (CCDSP_EF_REGNUM     187)])
  99
 100 ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE.
 101 (define_mode_iterator DSP [(SI "ISA_HAS_DSP")
 102                            (V2HI "ISA_HAS_DSP")
 103                            (V4QI "ISA_HAS_DSP")])
 104
 105 ;; This mode iterator allows v2hi, v4qi for vector/SIMD data.
 106 (define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP")
 107                             (V4QI "ISA_HAS_DSP")])
 108
 109 ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data.
 110 (define_mode_iterator DSPQ [(SI "ISA_HAS_DSP")
 111                             (V2HI "ISA_HAS_DSP")])
 112
 113 ;; DSP instructions use q for fixed-point data, and u for integer in the infix.
 114 (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
 115
 116 ;; DSP instructions use nothing for fixed-point data, and u for integer in
 117 ;; the infix.
 118 (define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")])
 119
 120 ;; DSP instructions use w, ph, qb in the postfix.
 121 (define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")])
 122
 123 ;; DSP shift masks for SI, V2HI, V4QI.
 124 (define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")])
 125
 126 ;; MIPS DSP ASE Revision 0.98 3/24/2005
 127 ;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic
 128 ;; ADDQ*
 129 (define_insn "add<DSPV:mode>3"
 130   [(parallel
 131     [(set (match_operand:DSPV 0 "register_operand" "=d")
 132           (plus:DSPV (match_operand:DSPV 1 "register_operand" "d")
 133                      (match_operand:DSPV 2 "register_operand" "d")))
 134      (set (reg:CCDSP CCDSP_OU_REGNUM)
 135           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])]
 136   "ISA_HAS_DSP"
 137   "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
 138   [(set_attr "type"     "dspalu")
 139    (set_attr "mode"     "SI")])
 140
 141 (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>"
 142   [(parallel
 143     [(set (match_operand:DSP 0 "register_operand" "=d")
 144           (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
 145                        (match_operand:DSP 2 "register_operand" "d")]
 146                       UNSPEC_ADDQ_S))
 147      (set (reg:CCDSP CCDSP_OU_REGNUM)
 148           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
 149   "ISA_HAS_DSP"
 150   "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
 151   [(set_attr "type"     "dspalusat")
 152    (set_attr "mode"     "SI")])
 153
 154 ;; SUBQ*
 155 (define_insn "sub<DSPV:mode>3"
 156   [(parallel
 157     [(set (match_operand:DSPV 0 "register_operand" "=d")
 158           (minus:DSPV (match_operand:DSPV 1 "register_operand" "d")
 159                       (match_operand:DSPV 2 "register_operand" "d")))
 160      (set (reg:CCDSP CCDSP_OU_REGNUM)
 161           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
 162   "ISA_HAS_DSP"
 163   "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
 164   [(set_attr "type"     "dspalu")
 165    (set_attr "mode"     "SI")])
 166
 167 (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>"
 168   [(parallel
 169     [(set (match_operand:DSP 0 "register_operand" "=d")
 170           (unspec:DSP [(match_operand:DSP 1 "register_operand" "d")
 171                        (match_operand:DSP 2 "register_operand" "d")]
 172                       UNSPEC_SUBQ_S))
 173      (set (reg:CCDSP CCDSP_OU_REGNUM)
 174           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
 175   "ISA_HAS_DSP"
 176   "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
 177   [(set_attr "type"     "dspalusat")
 178    (set_attr "mode"     "SI")])
 179
 180 ;; ADDSC
 181 (define_insn "mips_addsc"
 182   [(parallel
 183     [(set (match_operand:SI 0 "register_operand" "=d")
 184           (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 185                       (match_operand:SI 2 "register_operand" "d")]
 186                      UNSPEC_ADDSC))
 187      (set (reg:CCDSP CCDSP_CA_REGNUM)
 188           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
 189   "ISA_HAS_DSP"
 190   "addsc\t%0,%1,%2"
 191   [(set_attr "type"     "dspalu")
 192    (set_attr "mode"     "SI")])
 193
 194 ;; ADDWC
 195 (define_insn "mips_addwc"
 196   [(parallel
 197     [(set (match_operand:SI 0 "register_operand" "=d")
 198           (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 199                       (match_operand:SI 2 "register_operand" "d")
 200                     (reg:CCDSP CCDSP_CA_REGNUM)]
 201                      UNSPEC_ADDWC))
 202      (set (reg:CCDSP CCDSP_OU_REGNUM)
 203           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
 204   "ISA_HAS_DSP"
 205   "addwc\t%0,%1,%2"
 206   [(set_attr "type"     "dspalu")
 207    (set_attr "mode"     "SI")])
 208
 209 ;; MODSUB
 210 (define_insn "mips_modsub"
 211   [(set (match_operand:SI 0 "register_operand" "=d")
 212         (unspec:SI [(match_operand:SI 1 "register_operand" "d")
 213                     (match_operand:SI 2 "register_operand" "d")]
 214                    UNSPEC_MODSUB))]
 215   "ISA_HAS_DSP"
 216   "modsub\t%0,%1,%2"
 217   [(set_attr "type"     "dspalu")
 218    (set_attr "mode"     "SI")])
 219
 220 ;; RADDU*
 221 (define_insn "mips_raddu_w_qb"
 222   [(set (match_operand:SI 0 "register_operand" "=d")
 223         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")]
 224                    UNSPEC_RADDU_W_QB))]
 225   "ISA_HAS_DSP"
 226   "raddu.w.qb\t%0,%1"
 227   [(set_attr "type"     "dspalu")
 228    (set_attr "mode"     "SI")])
 229
 230 ;; ABSQ*
 231 (define_insn "mips_absq_s_<DSPQ:dspfmt2>"
 232   [(parallel
 233     [(set (match_operand:DSPQ 0 "register_operand" "=d")
 234           (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")]
 235                        UNSPEC_ABSQ_S))
 236      (set (reg:CCDSP CCDSP_OU_REGNUM)
 237           (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
 238   "ISA_HAS_DSP"
 239   "absq_s.<DSPQ:dspfmt2>\t%0,%1"
 240   [(set_attr "type"     "dspalusat")
 241    (set_attr "mode"     "SI")])
 242
 243 ;; PRECRQ*
 244 (define_insn "mips_precrq_qb_ph"
 245   [(set (match_operand:V4QI 0 "register_operand" "=d")
 246         (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
 247                       (match_operand:V2HI 2 "register_operand" "d")]
 248                      UNSPEC_PRECRQ_QB_PH))]
 249   "ISA_HAS_DSP"
 250   "precrq.qb.ph\t%0,%1,%2"
 251   [(set_attr "type"     "dspalu")
 252    (set_attr "mode"     "SI")])
 253
 254 (define_insn "mips_precrq_ph_w"
 255   [(set (match_operand:V2HI 0 "register_operand" "=d")
 256         (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
 257                       (match_operand:SI 2 "register_operand" "d")]
 258                      UNSPEC_PRECRQ_PH_W))]
 259   "ISA_HAS_DSP"
 260   "precrq.ph.w\t%0,%1,%2"
 261   [(set_attr "type"     "dspalu")
 262    (set_attr "mode"     "SI")])
 263
 264 (define_insn "mips_precrq_rs_ph_w"
 265   [(parallel
 266     [(set (match_operand:V2HI 0 "register_operand" "=d")
 267           (unspec:V2HI [(match_operand:SI 1 "register_operand" "d")
 268                         (match_operand:SI 2 "register_operand" "d")]
 269                        UNSPEC_PRECRQ_RS_PH_W))
 270      (set (reg:CCDSP CCDSP_OU_REGNUM)
 271           (unspec:CCDSP [(match_dup 1) (match_dup 2)]
 272                         UNSPEC_PRECRQ_RS_PH_W))])]
 273   "ISA_HAS_DSP"
 274   "precrq_rs.ph.w\t%0,%1,%2"
 275   [(set_attr "type"     "dspalu")
 276    (set_attr "mode"     "SI")])
 277
 278 ;; PRECRQU*
 279 (define_insn "mips_precrqu_s_qb_ph"
 280   [(parallel
 281     [(set (match_operand:V4QI 0 "register_operand" "=d")
 282           (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d")
 283                         (match_operand:V2HI 2 "register_operand" "d")]
 284                        UNSPEC_PRECRQU_S_QB_PH))
 285      (set (reg:CCDSP CCDSP_OU_REGNUM)
 286           (unspec:CCDSP [(match_dup 1) (match_dup 2)]
 287                         UNSPEC_PRECRQU_S_QB_PH))])]
 288   "ISA_HAS_DSP"
 289   "precrqu_s.qb.ph\t%0,%1,%2"
 290   [(set_attr "type"     "dspalusat")
 291    (set_attr "mode"     "SI")])
 292
 293 ;; PRECEQ*
 294 (define_insn "mips_preceq_w_phl"
 295   [(set (match_operand:SI 0 "register_operand" "=d")
 296         (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
 297                    UNSPEC_PRECEQ_W_PHL))]
 298   "ISA_HAS_DSP"
 299   "preceq.w.phl\t%0,%1"
 300   [(set_attr "type"     "dspalu")
 301    (set_attr "mode"     "SI")])
 302
 303 (define_insn "mips_preceq_w_phr"
 304   [(set (match_operand:SI 0 "register_operand" "=d")
 305         (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")]
 306                    UNSPEC_PRECEQ_W_PHR))]
 307   "ISA_HAS_DSP"
 308   "preceq.w.phr\t%0,%1"
 309   [(set_attr "type"     "dspalu")
 310    (set_attr "mode"     "SI")])
 311
 312 ;; PRECEQU*
 313 (define_insn "mips_precequ_ph_qbl"
 314   [(set (match_operand:V2HI 0 "register_operand" "=d")
 315         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 316                      UNSPEC_PRECEQU_PH_QBL))]
 317   "ISA_HAS_DSP"
 318   "precequ.ph.qbl\t%0,%1"
 319   [(set_attr "type"     "dspalu")
 320    (set_attr "mode"     "SI")])
 321
 322 (define_insn "mips_precequ_ph_qbr"
 323   [(set (match_operand:V2HI 0 "register_operand" "=d")
 324         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 325                      UNSPEC_PRECEQU_PH_QBR))]
 326   "ISA_HAS_DSP"
 327   "precequ.ph.qbr\t%0,%1"
 328   [(set_attr "type"     "dspalu")
 329    (set_attr "mode"     "SI")])
 330
 331 (define_insn "mips_precequ_ph_qbla"
 332   [(set (match_operand:V2HI 0 "register_operand" "=d")
 333         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 334                      UNSPEC_PRECEQU_PH_QBLA))]
 335   "ISA_HAS_DSP"
 336   "precequ.ph.qbla\t%0,%1"
 337   [(set_attr "type"     "dspalu")
 338    (set_attr "mode"     "SI")])
 339
 340 (define_insn "mips_precequ_ph_qbra"
 341   [(set (match_operand:V2HI 0 "register_operand" "=d")
 342         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 343                      UNSPEC_PRECEQU_PH_QBRA))]
 344   "ISA_HAS_DSP"
 345   "precequ.ph.qbra\t%0,%1"
 346   [(set_attr "type"     "dspalu")
 347    (set_attr "mode"     "SI")])
 348
 349 ;; PRECEU*
 350 (define_insn "mips_preceu_ph_qbl"
 351   [(set (match_operand:V2HI 0 "register_operand" "=d")
 352         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 353                      UNSPEC_PRECEU_PH_QBL))]
 354   "ISA_HAS_DSP"
 355   "preceu.ph.qbl\t%0,%1"
 356   [(set_attr "type"     "dspalu")
 357    (set_attr "mode"     "SI")])
 358
 359 (define_insn "mips_preceu_ph_qbr"
 360   [(set (match_operand:V2HI 0 "register_operand" "=d")
 361         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 362                      UNSPEC_PRECEU_PH_QBR))]
 363   "ISA_HAS_DSP"
 364   "preceu.ph.qbr\t%0,%1"
 365   [(set_attr "type"     "dspalu")
 366    (set_attr "mode"     "SI")])
 367
 368 (define_insn "mips_preceu_ph_qbla"
 369   [(set (match_operand:V2HI 0 "register_operand" "=d")
 370         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 371                      UNSPEC_PRECEU_PH_QBLA))]
 372   "ISA_HAS_DSP"
 373   "preceu.ph.qbla\t%0,%1"
 374   [(set_attr "type"     "dspalu")
 375    (set_attr "mode"     "SI")])
 376
 377 (define_insn "mips_preceu_ph_qbra"
 378   [(set (match_operand:V2HI 0 "register_operand" "=d")
 379         (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")]
 380                      UNSPEC_PRECEU_PH_QBRA))]
 381   "ISA_HAS_DSP"
 382   "preceu.ph.qbra\t%0,%1"
 383   [(set_attr "type"     "dspalu")
 384    (set_attr "mode"     "SI")])
 385
 386 ;; Table 2-2. MIPS DSP ASE Instructions: Shift
 387 ;; SHLL*
 388 (define_insn "mips_shll_<DSPV:dspfmt2>"
 389   [(parallel
 390     [(set (match_operand:DSPV 0 "register_operand" "=d,d")
 391           (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d")
 392                         (match_operand:SI 2 "arith_operand" "I,d")]
 393                        UNSPEC_SHLL))
 394      (set (reg:CCDSP CCDSP_OU_REGNUM)
 395           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])]
 396   "ISA_HAS_DSP"
 397 {
 398   if (which_alternative == 0)
 399     {
 400       if (INTVAL (operands[2])
 401           & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>)
 402         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>);
 403       return "shll.<DSPV:dspfmt2>\t%0,%1,%2";
 404     }
 405   return "shllv.<DSPV:dspfmt2>\t%0,%1,%2";
 406 }
 407   [(set_attr "type"     "dspalu")
 408    (set_attr "mode"     "SI")])
 409
 410 (define_insn "mips_shll_s_<DSPQ:dspfmt2>"
 411   [(parallel
 412     [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
 413           (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
 414                         (match_operand:SI 2 "arith_operand" "I,d")]
 415                        UNSPEC_SHLL_S))
 416      (set (reg:CCDSP CCDSP_OU_REGNUM)
 417           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])]
 418   "ISA_HAS_DSP"
 419 {
 420   if (which_alternative == 0)
 421     {
 422       if (INTVAL (operands[2])
 423           & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
 424         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
 425       return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2";
 426     }
 427   return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2";
 428 }
 429   [(set_attr "type"     "dspalusat")
 430    (set_attr "mode"     "SI")])
 431
 432 ;; SHRL*
 433 (define_insn "mips_shrl_qb"
 434   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 435         (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d")
 436                       (match_operand:SI 2 "arith_operand" "I,d")]
 437                      UNSPEC_SHRL_QB))]
 438   "ISA_HAS_DSP"
 439 {
 440   if (which_alternative == 0)
 441     {
 442       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7)
 443         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7);
 444       return "shrl.qb\t%0,%1,%2";
 445     }
 446   return "shrlv.qb\t%0,%1,%2";
 447 }
 448   [(set_attr "type"     "dspalu")
 449    (set_attr "mode"     "SI")])
 450
 451 ;; SHRA*
 452 (define_insn "mips_shra_ph"
 453   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 454         (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d")
 455                       (match_operand:SI 2 "arith_operand" "I,d")]
 456                      UNSPEC_SHRA_PH))]
 457   "ISA_HAS_DSP"
 458 {
 459   if (which_alternative == 0)
 460     {
 461       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf)
 462         operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf);
 463       return "shra.ph\t%0,%1,%2";
 464     }
 465   return "shrav.ph\t%0,%1,%2";
 466 }
 467   [(set_attr "type"     "dspalu")
 468    (set_attr "mode"     "SI")])
 469
 470 (define_insn "mips_shra_r_<DSPQ:dspfmt2>"
 471   [(set (match_operand:DSPQ 0 "register_operand" "=d,d")
 472         (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d")
 473                       (match_operand:SI 2 "arith_operand" "I,d")]
 474                      UNSPEC_SHRA_R))]
 475   "ISA_HAS_DSP"
 476 {
 477   if (which_alternative == 0)
 478     {
 479       if (INTVAL (operands[2])
 480           & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>)
 481         operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>);
 482       return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2";
 483     }
 484   return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2";
 485 }
 486   [(set_attr "type"     "dspalu")
 487    (set_attr "mode"     "SI")])
 488
 489 ;; Table 2-3. MIPS DSP ASE Instructions: Multiply
 490 ;; MULEU*
 491 (define_insn "mips_muleu_s_ph_qbl"
 492   [(parallel
 493     [(set (match_operand:V2HI 0 "register_operand" "=d")
 494           (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
 495                         (match_operand:V2HI 2 "register_operand" "d")]
 496                        UNSPEC_MULEU_S_PH_QBL))
 497      (set (reg:CCDSP CCDSP_OU_REGNUM)
 498           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL))
 499      (clobber (match_scratch:DI 3 "=x"))])]
 500   "ISA_HAS_DSP"
 501   "muleu_s.ph.qbl\t%0,%1,%2"
 502   [(set_attr "type"     "imul3")
 503    (set_attr "mode"     "SI")])
 504
 505 (define_insn "mips_muleu_s_ph_qbr"
 506   [(parallel
 507     [(set (match_operand:V2HI 0 "register_operand" "=d")
 508           (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")
 509                         (match_operand:V2HI 2 "register_operand" "d")]
 510                        UNSPEC_MULEU_S_PH_QBR))
 511      (set (reg:CCDSP CCDSP_OU_REGNUM)
 512           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR))
 513      (clobber (match_scratch:DI 3 "=x"))])]
 514   "ISA_HAS_DSP"
 515   "muleu_s.ph.qbr\t%0,%1,%2"
 516   [(set_attr "type"     "imul3")
 517    (set_attr "mode"     "SI")])
 518
 519 ;; MULQ*
 520 (define_insn "mips_mulq_rs_ph"
 521   [(parallel
 522     [(set (match_operand:V2HI 0 "register_operand" "=d")
 523           (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
 524                         (match_operand:V2HI 2 "register_operand" "d")]
 525                        UNSPEC_MULQ_RS_PH))
 526      (set (reg:CCDSP CCDSP_OU_REGNUM)
 527           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
 528      (clobber (match_scratch:DI 3 "=x"))])]
 529   "ISA_HAS_DSP"
 530   "mulq_rs.ph\t%0,%1,%2"
 531   [(set_attr "type"     "imul3")
 532    (set_attr "mode"     "SI")])
 533
 534 ;; MULEQ*
 535 (define_insn "mips_muleq_s_w_phl"
 536   [(parallel
 537     [(set (match_operand:SI 0 "register_operand" "=d")
 538           (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
 539                       (match_operand:V2HI 2 "register_operand" "d")]
 540                      UNSPEC_MULEQ_S_W_PHL))
 541      (set (reg:CCDSP CCDSP_OU_REGNUM)
 542           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL))
 543      (clobber (match_scratch:DI 3 "=x"))])]
 544   "ISA_HAS_DSP"
 545   "muleq_s.w.phl\t%0,%1,%2"
 546   [(set_attr "type"     "imul3")
 547    (set_attr "mode"     "SI")])
 548
 549 (define_insn "mips_muleq_s_w_phr"
 550   [(parallel
 551     [(set (match_operand:SI 0 "register_operand" "=d")
 552           (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")
 553                       (match_operand:V2HI 2 "register_operand" "d")]
 554                      UNSPEC_MULEQ_S_W_PHR))
 555      (set (reg:CCDSP CCDSP_OU_REGNUM)
 556           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR))
 557      (clobber (match_scratch:DI 3 "=x"))])]
 558   "ISA_HAS_DSP"
 559   "muleq_s.w.phr\t%0,%1,%2"
 560   [(set_attr "type"     "imul3")
 561    (set_attr "mode"     "SI")])
 562
 563 ;; DPAU*
 564 (define_insn "mips_dpau_h_qbl"
 565   [(set (match_operand:DI 0 "register_operand" "=a")
 566         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 567                     (match_operand:V4QI 2 "register_operand" "d")
 568                     (match_operand:V4QI 3 "register_operand" "d")]
 569                    UNSPEC_DPAU_H_QBL))]
 570   "ISA_HAS_DSP && !TARGET_64BIT"
 571   "dpau.h.qbl\t%q0,%2,%3"
 572   [(set_attr "type"     "dspmac")
 573    (set_attr "mode"     "SI")])
 574
 575 (define_insn "mips_dpau_h_qbr"
 576   [(set (match_operand:DI 0 "register_operand" "=a")
 577         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 578                     (match_operand:V4QI 2 "register_operand" "d")
 579                     (match_operand:V4QI 3 "register_operand" "d")]
 580                    UNSPEC_DPAU_H_QBR))]
 581   "ISA_HAS_DSP && !TARGET_64BIT"
 582   "dpau.h.qbr\t%q0,%2,%3"
 583   [(set_attr "type"     "dspmac")
 584    (set_attr "mode"     "SI")])
 585
 586 ;; DPSU*
 587 (define_insn "mips_dpsu_h_qbl"
 588   [(set (match_operand:DI 0 "register_operand" "=a")
 589         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 590                     (match_operand:V4QI 2 "register_operand" "d")
 591                     (match_operand:V4QI 3 "register_operand" "d")]
 592                    UNSPEC_DPSU_H_QBL))]
 593   "ISA_HAS_DSP && !TARGET_64BIT"
 594   "dpsu.h.qbl\t%q0,%2,%3"
 595   [(set_attr "type"     "dspmac")
 596    (set_attr "mode"     "SI")])
 597
 598 (define_insn "mips_dpsu_h_qbr"
 599   [(set (match_operand:DI 0 "register_operand" "=a")
 600         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 601                     (match_operand:V4QI 2 "register_operand" "d")
 602                     (match_operand:V4QI 3 "register_operand" "d")]
 603                    UNSPEC_DPSU_H_QBR))]
 604   "ISA_HAS_DSP && !TARGET_64BIT"
 605   "dpsu.h.qbr\t%q0,%2,%3"
 606   [(set_attr "type"     "dspmac")
 607    (set_attr "mode"     "SI")])
 608
 609 ;; DPAQ*
 610 (define_insn "mips_dpaq_s_w_ph"
 611   [(parallel
 612     [(set (match_operand:DI 0 "register_operand" "=a")
 613           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 614                       (match_operand:V2HI 2 "register_operand" "d")
 615                       (match_operand:V2HI 3 "register_operand" "d")]
 616                      UNSPEC_DPAQ_S_W_PH))
 617      (set (reg:CCDSP CCDSP_OU_REGNUM)
 618           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 619                         UNSPEC_DPAQ_S_W_PH))])]
 620   "ISA_HAS_DSP && !TARGET_64BIT"
 621   "dpaq_s.w.ph\t%q0,%2,%3"
 622   [(set_attr "type"     "dspmac")
 623    (set_attr "mode"     "SI")])
 624
 625 ;; DPSQ*
 626 (define_insn "mips_dpsq_s_w_ph"
 627   [(parallel
 628     [(set (match_operand:DI 0 "register_operand" "=a")
 629           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 630                       (match_operand:V2HI 2 "register_operand" "d")
 631                       (match_operand:V2HI 3 "register_operand" "d")]
 632                      UNSPEC_DPSQ_S_W_PH))
 633      (set (reg:CCDSP CCDSP_OU_REGNUM)
 634           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 635                         UNSPEC_DPSQ_S_W_PH))])]
 636   "ISA_HAS_DSP && !TARGET_64BIT"
 637   "dpsq_s.w.ph\t%q0,%2,%3"
 638   [(set_attr "type"     "dspmac")
 639    (set_attr "mode"     "SI")])
 640
 641 ;; MULSAQ*
 642 (define_insn "mips_mulsaq_s_w_ph"
 643   [(parallel
 644     [(set (match_operand:DI 0 "register_operand" "=a")
 645           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 646                       (match_operand:V2HI 2 "register_operand" "d")
 647                       (match_operand:V2HI 3 "register_operand" "d")]
 648                      UNSPEC_MULSAQ_S_W_PH))
 649      (set (reg:CCDSP CCDSP_OU_REGNUM)
 650           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 651                         UNSPEC_MULSAQ_S_W_PH))])]
 652   "ISA_HAS_DSP && !TARGET_64BIT"
 653   "mulsaq_s.w.ph\t%q0,%2,%3"
 654   [(set_attr "type"     "dspmac")
 655    (set_attr "mode"     "SI")])
 656
 657 ;; DPAQ*
 658 (define_insn "mips_dpaq_sa_l_w"
 659   [(parallel
 660     [(set (match_operand:DI 0 "register_operand" "=a")
 661           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 662                       (match_operand:SI 2 "register_operand" "d")
 663                       (match_operand:SI 3 "register_operand" "d")]
 664                      UNSPEC_DPAQ_SA_L_W))
 665      (set (reg:CCDSP CCDSP_OU_REGNUM)
 666           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 667                         UNSPEC_DPAQ_SA_L_W))])]
 668   "ISA_HAS_DSP && !TARGET_64BIT"
 669   "dpaq_sa.l.w\t%q0,%2,%3"
 670   [(set_attr "type"     "dspmacsat")
 671    (set_attr "mode"     "SI")])
 672
 673 ;; DPSQ*
 674 (define_insn "mips_dpsq_sa_l_w"
 675   [(parallel
 676     [(set (match_operand:DI 0 "register_operand" "=a")
 677           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 678                       (match_operand:SI 2 "register_operand" "d")
 679                       (match_operand:SI 3 "register_operand" "d")]
 680                      UNSPEC_DPSQ_SA_L_W))
 681      (set (reg:CCDSP CCDSP_OU_REGNUM)
 682           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 683                         UNSPEC_DPSQ_SA_L_W))])]
 684   "ISA_HAS_DSP && !TARGET_64BIT"
 685   "dpsq_sa.l.w\t%q0,%2,%3"
 686   [(set_attr "type"     "dspmacsat")
 687    (set_attr "mode"     "SI")])
 688
 689 ;; MAQ*
 690 (define_insn "mips_maq_s_w_phl"
 691   [(parallel
 692     [(set (match_operand:DI 0 "register_operand" "=a")
 693           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 694                       (match_operand:V2HI 2 "register_operand" "d")
 695                       (match_operand:V2HI 3 "register_operand" "d")]
 696                      UNSPEC_MAQ_S_W_PHL))
 697      (set (reg:CCDSP CCDSP_OU_REGNUM)
 698           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 699                         UNSPEC_MAQ_S_W_PHL))])]
 700   "ISA_HAS_DSP && !TARGET_64BIT"
 701   "maq_s.w.phl\t%q0,%2,%3"
 702   [(set_attr "type"     "dspmac")
 703    (set_attr "mode"     "SI")])
 704
 705 (define_insn "mips_maq_s_w_phr"
 706   [(parallel
 707     [(set (match_operand:DI 0 "register_operand" "=a")
 708           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 709                       (match_operand:V2HI 2 "register_operand" "d")
 710                       (match_operand:V2HI 3 "register_operand" "d")]
 711                      UNSPEC_MAQ_S_W_PHR))
 712      (set (reg:CCDSP CCDSP_OU_REGNUM)
 713           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 714                         UNSPEC_MAQ_S_W_PHR))])]
 715   "ISA_HAS_DSP && !TARGET_64BIT"
 716   "maq_s.w.phr\t%q0,%2,%3"
 717   [(set_attr "type"     "dspmac")
 718    (set_attr "mode"     "SI")])
 719
 720 ;; MAQ_SA*
 721 (define_insn "mips_maq_sa_w_phl"
 722   [(parallel
 723     [(set (match_operand:DI 0 "register_operand" "=a")
 724           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 725                       (match_operand:V2HI 2 "register_operand" "d")
 726                       (match_operand:V2HI 3 "register_operand" "d")]
 727                      UNSPEC_MAQ_SA_W_PHL))
 728      (set (reg:CCDSP CCDSP_OU_REGNUM)
 729           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 730                         UNSPEC_MAQ_SA_W_PHL))])]
 731   "ISA_HAS_DSP && !TARGET_64BIT"
 732   "maq_sa.w.phl\t%q0,%2,%3"
 733   [(set_attr "type"     "dspmacsat")
 734    (set_attr "mode"     "SI")])
 735
 736 (define_insn "mips_maq_sa_w_phr"
 737   [(parallel
 738     [(set (match_operand:DI 0 "register_operand" "=a")
 739           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 740                       (match_operand:V2HI 2 "register_operand" "d")
 741                       (match_operand:V2HI 3 "register_operand" "d")]
 742                      UNSPEC_MAQ_SA_W_PHR))
 743      (set (reg:CCDSP CCDSP_OU_REGNUM)
 744           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 745                         UNSPEC_MAQ_SA_W_PHR))])]
 746   "ISA_HAS_DSP && !TARGET_64BIT"
 747   "maq_sa.w.phr\t%q0,%2,%3"
 748   [(set_attr "type"     "dspmacsat")
 749    (set_attr "mode"     "SI")])
 750
 751 ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation
 752 ;; BITREV
 753 (define_insn "mips_bitrev"
 754   [(set (match_operand:SI 0 "register_operand" "=d")
 755         (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
 756                    UNSPEC_BITREV))]
 757   "ISA_HAS_DSP"
 758   "bitrev\t%0,%1"
 759   [(set_attr "type"     "dspalu")
 760    (set_attr "mode"     "SI")])
 761
 762 ;; INSV
 763 (define_insn "mips_insv"
 764   [(set (match_operand:SI 0 "register_operand" "=d")
 765         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
 766                     (match_operand:SI 2 "register_operand" "d")
 767                     (reg:CCDSP CCDSP_SC_REGNUM)
 768                     (reg:CCDSP CCDSP_PO_REGNUM)]
 769                    UNSPEC_INSV))]
 770   "ISA_HAS_DSP"
 771   "insv\t%0,%2"
 772   [(set_attr "type"     "dspalu")
 773    (set_attr "mode"     "SI")])
 774
 775 ;; REPL*
 776 (define_insn "mips_repl_qb"
 777   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 778         (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")]
 779                      UNSPEC_REPL_QB))]
 780   "ISA_HAS_DSP"
 781 {
 782   if (which_alternative == 0)
 783     {
 784       if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff)
 785         operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
 786       return "repl.qb\t%0,%1";
 787     }
 788   return "replv.qb\t%0,%1";
 789 }
 790   [(set_attr "type"     "dspalu")
 791    (set_attr "mode"     "SI")])
 792
 793 (define_insn "mips_repl_ph"
 794   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 795         (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")]
 796                      UNSPEC_REPL_PH))]
 797   "ISA_HAS_DSP"
 798   "@
 799    repl.ph\t%0,%1
 800    replv.ph\t%0,%1"
 801   [(set_attr "type"     "dspalu")
 802    (set_attr "mode"     "SI")])
 803
 804 ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick
 805 ;; CMPU.* CMP.*
 806 (define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>"
 807   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 808         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 809                        (match_operand:DSPV 1 "register_operand" "d")
 810                        (reg:CCDSP CCDSP_CC_REGNUM)]
 811                       UNSPEC_CMP_EQ))]
 812   "ISA_HAS_DSP"
 813   "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1"
 814   [(set_attr "type"     "dspalu")
 815    (set_attr "mode"     "SI")])
 816
 817 (define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>"
 818   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 819         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 820                        (match_operand:DSPV 1 "register_operand" "d")
 821                        (reg:CCDSP CCDSP_CC_REGNUM)]
 822                       UNSPEC_CMP_LT))]
 823   "ISA_HAS_DSP"
 824   "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1"
 825   [(set_attr "type"     "dspalu")
 826    (set_attr "mode"     "SI")])
 827
 828 (define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>"
 829   [(set (reg:CCDSP CCDSP_CC_REGNUM)
 830         (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d")
 831                        (match_operand:DSPV 1 "register_operand" "d")
 832                        (reg:CCDSP CCDSP_CC_REGNUM)]
 833                       UNSPEC_CMP_LE))]
 834   "ISA_HAS_DSP"
 835   "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1"
 836   [(set_attr "type"     "dspalu")
 837    (set_attr "mode"     "SI")])
 838
 839 (define_insn "mips_cmpgu_eq_qb"
 840   [(set (match_operand:SI 0 "register_operand" "=d")
 841         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 842                     (match_operand:V4QI 2 "register_operand" "d")]
 843                    UNSPEC_CMPGU_EQ_QB))]
 844   "ISA_HAS_DSP"
 845   "cmpgu.eq.qb\t%0,%1,%2"
 846   [(set_attr "type"     "dspalu")
 847    (set_attr "mode"     "SI")])
 848
 849 (define_insn "mips_cmpgu_lt_qb"
 850   [(set (match_operand:SI 0 "register_operand" "=d")
 851         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 852                     (match_operand:V4QI 2 "register_operand" "d")]
 853                    UNSPEC_CMPGU_LT_QB))]
 854   "ISA_HAS_DSP"
 855   "cmpgu.lt.qb\t%0,%1,%2"
 856   [(set_attr "type"     "dspalu")
 857    (set_attr "mode"     "SI")])
 858
 859 (define_insn "mips_cmpgu_le_qb"
 860   [(set (match_operand:SI 0 "register_operand" "=d")
 861         (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")
 862                     (match_operand:V4QI 2 "register_operand" "d")]
 863                    UNSPEC_CMPGU_LE_QB))]
 864   "ISA_HAS_DSP"
 865   "cmpgu.le.qb\t%0,%1,%2"
 866   [(set_attr "type"     "dspalu")
 867    (set_attr "mode"     "SI")])
 868
 869 ;; PICK*
 870 (define_insn "mips_pick_<DSPV:dspfmt2>"
 871   [(set (match_operand:DSPV 0 "register_operand" "=d")
 872         (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d")
 873                       (match_operand:DSPV 2 "register_operand" "d")
 874                       (reg:CCDSP CCDSP_CC_REGNUM)]
 875                      UNSPEC_PICK))]
 876   "ISA_HAS_DSP"
 877   "pick.<DSPV:dspfmt2>\t%0,%1,%2"
 878   [(set_attr "type"     "dspalu")
 879    (set_attr "mode"     "SI")])
 880
 881 ;; PACKRL*
 882 (define_insn "mips_packrl_ph"
 883   [(set (match_operand:V2HI 0 "register_operand" "=d")
 884         (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d")
 885                       (match_operand:V2HI 2 "register_operand" "d")]
 886                      UNSPEC_PACKRL_PH))]
 887   "ISA_HAS_DSP"
 888   "packrl.ph\t%0,%1,%2"
 889   [(set_attr "type"     "dspalu")
 890    (set_attr "mode"     "SI")])
 891
 892 ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
 893 ;; EXTR*
 894 (define_insn "mips_extr_w"
 895   [(parallel
 896     [(set (match_operand:SI 0 "register_operand" "=d,d")
 897           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 898                       (match_operand:SI 2 "arith_operand" "I,d")]
 899                      UNSPEC_EXTR_W))
 900      (set (reg:CCDSP CCDSP_OU_REGNUM)
 901           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])]
 902   "ISA_HAS_DSP && !TARGET_64BIT"
 903 {
 904   if (which_alternative == 0)
 905     {
 906       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 907         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 908       return "extr.w\t%0,%q1,%2";
 909     }
 910   return "extrv.w\t%0,%q1,%2";
 911 }
 912   [(set_attr "type"     "accext")
 913    (set_attr "mode"     "SI")])
 914
 915 (define_insn "mips_extr_r_w"
 916   [(parallel
 917     [(set (match_operand:SI 0 "register_operand" "=d,d")
 918           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 919                       (match_operand:SI 2 "arith_operand" "I,d")]
 920                      UNSPEC_EXTR_R_W))
 921      (set (reg:CCDSP CCDSP_OU_REGNUM)
 922           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])]
 923   "ISA_HAS_DSP && !TARGET_64BIT"
 924 {
 925   if (which_alternative == 0)
 926     {
 927       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 928         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 929       return "extr_r.w\t%0,%q1,%2";
 930     }
 931   return "extrv_r.w\t%0,%q1,%2";
 932 }
 933   [(set_attr "type"     "accext")
 934    (set_attr "mode"     "SI")])
 935
 936 (define_insn "mips_extr_rs_w"
 937   [(parallel
 938     [(set (match_operand:SI 0 "register_operand" "=d,d")
 939           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 940                       (match_operand:SI 2 "arith_operand" "I,d")]
 941                      UNSPEC_EXTR_RS_W))
 942      (set (reg:CCDSP CCDSP_OU_REGNUM)
 943           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])]
 944   "ISA_HAS_DSP && !TARGET_64BIT"
 945 {
 946   if (which_alternative == 0)
 947     {
 948       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 949         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 950       return "extr_rs.w\t%0,%q1,%2";
 951     }
 952   return "extrv_rs.w\t%0,%q1,%2";
 953 }
 954   [(set_attr "type"     "accext")
 955    (set_attr "mode"     "SI")])
 956
 957 ;; EXTR*_S.H
 958 (define_insn "mips_extr_s_h"
 959   [(parallel
 960     [(set (match_operand:SI 0 "register_operand" "=d,d")
 961           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 962                       (match_operand:SI 2 "arith_operand" "I,d")]
 963                      UNSPEC_EXTR_S_H))
 964      (set (reg:CCDSP CCDSP_OU_REGNUM)
 965           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])]
 966   "ISA_HAS_DSP && !TARGET_64BIT"
 967 {
 968   if (which_alternative == 0)
 969     {
 970       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 971         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 972       return "extr_s.h\t%0,%q1,%2";
 973     }
 974   return "extrv_s.h\t%0,%q1,%2";
 975 }
 976   [(set_attr "type"     "accext")
 977    (set_attr "mode"     "SI")])
 978
 979 ;; EXTP*
 980 (define_insn "mips_extp"
 981   [(parallel
 982     [(set (match_operand:SI 0 "register_operand" "=d,d")
 983           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
 984                       (match_operand:SI 2 "arith_operand" "I,d")
 985                       (reg:CCDSP CCDSP_PO_REGNUM)]
 986                      UNSPEC_EXTP))
 987      (set (reg:CCDSP CCDSP_EF_REGNUM)
 988           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])]
 989   "ISA_HAS_DSP && !TARGET_64BIT"
 990 {
 991   if (which_alternative == 0)
 992     {
 993       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
 994         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 995       return "extp\t%0,%q1,%2";
 996     }
 997   return "extpv\t%0,%q1,%2";
 998 }
 999   [(set_attr "type"     "accext")
1000    (set_attr "mode"     "SI")])
1001
1002 (define_insn "mips_extpdp"
1003   [(parallel
1004     [(set (match_operand:SI 0 "register_operand" "=d,d")
1005           (unspec:SI [(match_operand:DI 1 "register_operand" "a,a")
1006                       (match_operand:SI 2 "arith_operand" "I,d")
1007                       (reg:CCDSP CCDSP_PO_REGNUM)]
1008                      UNSPEC_EXTPDP))
1009      (set (reg:CCDSP CCDSP_PO_REGNUM)
1010           (unspec:CCDSP [(match_dup 1) (match_dup 2)
1011                          (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP))
1012      (set (reg:CCDSP CCDSP_EF_REGNUM)
1013           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])]
1014   "ISA_HAS_DSP && !TARGET_64BIT"
1015 {
1016   if (which_alternative == 0)
1017     {
1018       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f)
1019         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
1020       return "extpdp\t%0,%q1,%2";
1021     }
1022   return "extpdpv\t%0,%q1,%2";
1023 }
1024   [(set_attr "type"     "accext")
1025    (set_attr "mode"     "SI")])
1026
1027 ;; SHILO*
1028 (define_insn "mips_shilo"
1029   [(set (match_operand:DI 0 "register_operand" "=a,a")
1030         (unspec:DI [(match_operand:DI 1 "register_operand" "0,0")
1031                     (match_operand:SI 2 "arith_operand" "I,d")]
1032                    UNSPEC_SHILO))]
1033   "ISA_HAS_DSP && !TARGET_64BIT"
1034 {
1035   if (which_alternative == 0)
1036     {
1037       if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31)
1038         operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
1039       return "shilo\t%q0,%2";
1040     }
1041   return "shilov\t%q0,%2";
1042 }
1043   [(set_attr "type"     "accmod")
1044    (set_attr "mode"     "SI")])
1045
1046 ;; MTHLIP*
1047 (define_insn "mips_mthlip"
1048   [(parallel
1049     [(set (match_operand:DI 0 "register_operand" "=a")
1050           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1051                       (match_operand:SI 2 "register_operand" "d")
1052                       (reg:CCDSP CCDSP_PO_REGNUM)]
1053                      UNSPEC_MTHLIP))
1054      (set (reg:CCDSP CCDSP_PO_REGNUM)
1055           (unspec:CCDSP [(match_dup 1) (match_dup 2)
1056                          (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
1057   "ISA_HAS_DSP && !TARGET_64BIT"
1058   "mthlip\t%2,%q0"
1059   [(set_attr "type"     "accmod")
1060    (set_attr "mode"     "SI")])
1061
1062 ;; WRDSP
1063 (define_insn "mips_wrdsp"
1064   [(parallel
1065     [(set (reg:CCDSP CCDSP_PO_REGNUM)
1066           (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d")
1067                          (match_operand:SI 1 "const_uimm6_operand" "YA")]
1068                          UNSPEC_WRDSP))
1069      (set (reg:CCDSP CCDSP_SC_REGNUM)
1070           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1071      (set (reg:CCDSP CCDSP_CA_REGNUM)
1072           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1073      (set (reg:CCDSP CCDSP_OU_REGNUM)
1074           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1075      (set (reg:CCDSP CCDSP_CC_REGNUM)
1076           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))
1077      (set (reg:CCDSP CCDSP_EF_REGNUM)
1078           (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
1079   "ISA_HAS_DSP"
1080   "wrdsp\t%0,%1"
1081   [(set_attr "type"     "dspalu")
1082    (set_attr "mode"     "SI")])
1083
1084 ;; RDDSP
1085 (define_insn "mips_rddsp"
1086   [(set (match_operand:SI 0 "register_operand" "=d")
1087         (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA")
1088                     (reg:CCDSP CCDSP_PO_REGNUM)
1089                     (reg:CCDSP CCDSP_SC_REGNUM)
1090                     (reg:CCDSP CCDSP_CA_REGNUM)
1091                     (reg:CCDSP CCDSP_OU_REGNUM)
1092                     (reg:CCDSP CCDSP_CC_REGNUM)
1093                     (reg:CCDSP CCDSP_EF_REGNUM)]
1094                    UNSPEC_RDDSP))]
1095   "ISA_HAS_DSP"
1096   "rddsp\t%0,%1"
1097   [(set_attr "type"     "dspalu")
1098    (set_attr "mode"     "SI")])
1099
1100 ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load
1101 ;; L*X
1102 (define_expand "mips_lbux"
1103   [(match_operand:SI 0 "register_operand")
1104    (match_operand 1 "pmode_register_operand")
1105    (match_operand:SI 2 "register_operand")]
1106   "ISA_HAS_DSP"
1107 {
1108   operands[2] = convert_to_mode (Pmode, operands[2], false);
1109   emit_insn (PMODE_INSN (gen_mips_lbux_extsi,
1110                          (operands[0], operands[1], operands[2])));
1111   DONE;
1112 })
1113
1114 (define_insn "mips_l<SHORT:size><u>x_ext<GPR:mode>_<P:mode>"
1115   [(set (match_operand:GPR 0 "register_operand" "=d")
1116         (any_extend:GPR
1117           (mem:SHORT (plus:P (match_operand:P 1 "register_operand" "d")
1118                              (match_operand:P 2 "register_operand" "d")))))]
1119   "ISA_HAS_L<SHORT:SIZE><U>X"
1120   "l<SHORT:size><u>x\t%0,%2(%1)"
1121   [(set_attr "type"     "load")
1122    (set_attr "mode"     "<GPR:MODE>")
1123    (set_attr "length"   "4")])
1124
1125 (define_expand "mips_lhx"
1126   [(match_operand:SI 0 "register_operand")
1127    (match_operand 1 "pmode_register_operand")
1128    (match_operand:SI 2 "register_operand")]
1129   "ISA_HAS_DSP"
1130 {
1131   operands[2] = convert_to_mode (Pmode, operands[2], false);
1132   emit_insn (PMODE_INSN (gen_mips_lhx_extsi,
1133                          (operands[0], operands[1], operands[2])));
1134   DONE;
1135 })
1136
1137 (define_expand "mips_l<size>x"
1138   [(match_operand:GPR 0 "register_operand")
1139    (match_operand 1 "pmode_register_operand")
1140    (match_operand:SI 2 "register_operand")]
1141   "ISA_HAS_DSP"
1142 {
1143   operands[2] = convert_to_mode (Pmode, operands[2], false);
1144   emit_insn (PMODE_INSN (gen_mips_l<size>x,
1145                          (operands[0], operands[1], operands[2])));
1146   DONE;
1147 })
1148
1149 (define_insn "mips_l<GPR:size>x_<P:mode>"
1150   [(set (match_operand:GPR 0 "register_operand" "=d")
1151         (mem:GPR (plus:P (match_operand:P 1 "register_operand" "d")
1152                          (match_operand:P 2 "register_operand" "d"))))]
1153   "ISA_HAS_L<GPR:SIZE>X"
1154   "l<GPR:size>x\t%0,%2(%1)"
1155   [(set_attr "type"     "load")
1156    (set_attr "mode"     "<GPR:MODE>")
1157    (set_attr "length"   "4")])
1158
1159 (define_insn "*mips_lw<u>x_<P:mode>_ext"
1160   [(set (match_operand:DI 0 "register_operand" "=d")
1161         (any_extend:DI
1162           (mem:SI (plus:P (match_operand:P 1 "register_operand" "d")
1163                              (match_operand:P 2 "register_operand" "d")))))]
1164   "ISA_HAS_LW<U>X && TARGET_64BIT"
1165   "lw<u>x\t%0,%2(%1)"
1166   [(set_attr "type"     "load")
1167    (set_attr "mode"     "DI")
1168    (set_attr "length"   "4")])
1169
1170 ;; Table 2-8. MIPS DSP ASE Instructions: Branch
1171 ;; BPOSGE32
1172 (define_insn "mips_bposge"
1173   [(set (pc)
1174         (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM)
1175                           (match_operand:SI 1 "immediate_operand" "I"))
1176                       (label_ref (match_operand 0 "" ""))
1177                       (pc)))]
1178   "ISA_HAS_DSP"
1179   "%*bposge%1\t%0%/"
1180   [(set_attr "type"     "branch")])
1181
1182 (define_expand "mips_madd<u>"
1183   [(set (match_operand:DI 0 "register_operand")
1184         (plus:DI
1185          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1186                   (any_extend:DI (match_operand:SI 3 "register_operand")))
1187          (match_operand:DI 1 "register_operand")))]
1188   "ISA_HAS_DSP && !TARGET_64BIT")
1189
1190 (define_expand "mips_msub<u>"
1191   [(set (match_operand:DI 0 "register_operand")
1192         (minus:DI
1193          (match_operand:DI 1 "register_operand")
1194          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
1195                   (any_extend:DI (match_operand:SI 3 "register_operand")))))]
1196   "ISA_HAS_DSP && !TARGET_64BIT")