gcc/config/mips/mips-dspr2.md

   1 ;; Copyright (C) 2007 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18 ;;
  19 ; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
  20
  21 (define_insn "mips_absq_s_qb"
  22   [(parallel
  23     [(set (match_operand:V4QI 0 "register_operand" "=d")
  24           (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")]
  25                        UNSPEC_ABSQ_S_QB))
  26      (set (reg:CCDSP CCDSP_OU_REGNUM)
  27           (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
  28   "ISA_HAS_DSPR2"
  29   "absq_s.qb\t%0,%z1"
  30   [(set_attr "type"     "arith")
  31    (set_attr "mode"     "SI")])
  32
  33 (define_insn "mips_addu_ph"
  34   [(parallel
  35     [(set (match_operand:V2HI 0 "register_operand" "=d")
  36           (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG")
  37                      (match_operand:V2HI 2 "reg_or_0_operand" "dYG")))
  38      (set (reg:CCDSP CCDSP_OU_REGNUM)
  39           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
  40   "ISA_HAS_DSPR2"
  41   "addu.ph\t%0,%z1,%z2"
  42   [(set_attr "type"     "arith")
  43    (set_attr "mode"     "SI")])
  44
  45 (define_insn "mips_addu_s_ph"
  46   [(parallel
  47     [(set (match_operand:V2HI 0 "register_operand" "=d")
  48           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
  49                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
  50                        UNSPEC_ADDU_S_PH))
  51      (set (reg:CCDSP CCDSP_OU_REGNUM)
  52           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
  53   "ISA_HAS_DSPR2"
  54   "addu_s.ph\t%0,%z1,%z2"
  55   [(set_attr "type"     "arith")
  56    (set_attr "mode"     "SI")])
  57
  58 (define_insn "mips_adduh_qb"
  59   [(set (match_operand:V4QI 0 "register_operand" "=d")
  60         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
  61                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
  62                      UNSPEC_ADDUH_QB))]
  63   "ISA_HAS_DSPR2"
  64   "adduh.qb\t%0,%z1,%z2"
  65   [(set_attr "type"     "arith")
  66    (set_attr "mode"     "SI")])
  67
  68 (define_insn "mips_adduh_r_qb"
  69   [(set (match_operand:V4QI 0 "register_operand" "=d")
  70         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
  71                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
  72                      UNSPEC_ADDUH_R_QB))]
  73   "ISA_HAS_DSPR2"
  74   "adduh_r.qb\t%0,%z1,%z2"
  75   [(set_attr "type"     "arith")
  76    (set_attr "mode"     "SI")])
  77
  78 (define_insn "mips_append"
  79   [(set (match_operand:SI 0 "register_operand" "=d")
  80         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
  81                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
  82                     (match_operand:SI 3 "const_int_operand" "n")]
  83                    UNSPEC_APPEND))]
  84   "ISA_HAS_DSPR2"
  85 {
  86   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
  87     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
  88   return "append\t%0,%z2,%3";
  89 }
  90   [(set_attr "type"     "arith")
  91    (set_attr "mode"     "SI")])
  92
  93 (define_insn "mips_balign"
  94   [(set (match_operand:SI 0 "register_operand" "=d")
  95         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
  96                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
  97                     (match_operand:SI 3 "const_int_operand" "n")]
  98                    UNSPEC_BALIGN))]
  99   "ISA_HAS_DSPR2"
 100 {
 101   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3)
 102     operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
 103   return "balign\t%0,%z2,%3";
 104 }
 105   [(set_attr "type"     "arith")
 106    (set_attr "mode"     "SI")])
 107
 108 (define_insn "mips_cmpgdu_eq_qb"
 109   [(parallel
 110     [(set (match_operand:SI 0 "register_operand" "=d")
 111           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 112                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 113                      UNSPEC_CMPGDU_EQ_QB))
 114      (set (reg:CCDSP CCDSP_CC_REGNUM)
 115           (unspec:CCDSP [(match_dup 1) (match_dup 2)
 116                          (reg:CCDSP CCDSP_CC_REGNUM)]
 117                         UNSPEC_CMPGDU_EQ_QB))])]
 118   "ISA_HAS_DSPR2"
 119   "cmpgdu.eq.qb\t%0,%z1,%z2"
 120   [(set_attr "type"     "arith")
 121    (set_attr "mode"     "SI")])
 122
 123 (define_insn "mips_cmpgdu_lt_qb"
 124   [(parallel
 125     [(set (match_operand:SI 0 "register_operand" "=d")
 126           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 127                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 128                      UNSPEC_CMPGDU_LT_QB))
 129      (set (reg:CCDSP CCDSP_CC_REGNUM)
 130           (unspec:CCDSP [(match_dup 1) (match_dup 2)
 131                          (reg:CCDSP CCDSP_CC_REGNUM)]
 132                         UNSPEC_CMPGDU_LT_QB))])]
 133   "ISA_HAS_DSPR2"
 134   "cmpgdu.lt.qb\t%0,%z1,%z2"
 135   [(set_attr "type"     "arith")
 136    (set_attr "mode"     "SI")])
 137
 138 (define_insn "mips_cmpgdu_le_qb"
 139   [(parallel
 140     [(set (match_operand:SI 0 "register_operand" "=d")
 141           (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 142                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 143                      UNSPEC_CMPGDU_LE_QB))
 144      (set (reg:CCDSP CCDSP_CC_REGNUM)
 145           (unspec:CCDSP [(match_dup 1) (match_dup 2)
 146                          (reg:CCDSP CCDSP_CC_REGNUM)]
 147                         UNSPEC_CMPGDU_LE_QB))])]
 148   "ISA_HAS_DSPR2"
 149   "cmpgdu.le.qb\t%0,%z1,%z2"
 150   [(set_attr "type"     "arith")
 151    (set_attr "mode"     "SI")])
 152
 153 (define_insn "mips_dpa_w_ph"
 154   [(set (match_operand:DI 0 "register_operand" "=a")
 155         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 156                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 157                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 158                    UNSPEC_DPA_W_PH))]
 159   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 160   "dpa.w.ph\t%q0,%z2,%z3"
 161   [(set_attr "type"     "imadd")
 162    (set_attr "mode"     "SI")])
 163
 164 (define_insn "mips_dps_w_ph"
 165   [(set (match_operand:DI 0 "register_operand" "=a")
 166         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 167                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 168                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 169                    UNSPEC_DPS_W_PH))]
 170   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 171   "dps.w.ph\t%q0,%z2,%z3"
 172   [(set_attr "type"     "imadd")
 173    (set_attr "mode"     "SI")])
 174
 175 (define_expand "mips_madd<u>"
 176   [(set (match_operand:DI 0 "register_operand")
 177         (plus:DI
 178          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
 179                   (any_extend:DI (match_operand:SI 3 "register_operand")))
 180          (match_operand:DI 1 "register_operand")))]
 181   "ISA_HAS_DSPR2 && !TARGET_64BIT")
 182
 183 (define_expand "mips_msub<u>"
 184   [(set (match_operand:DI 0 "register_operand")
 185         (minus:DI
 186          (match_operand:DI 1 "register_operand")
 187          (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand"))
 188                   (any_extend:DI (match_operand:SI 3 "register_operand")))))]
 189   "ISA_HAS_DSPR2 && !TARGET_64BIT")
 190
 191 (define_insn "mulv2hi3"
 192   [(parallel
 193     [(set (match_operand:V2HI 0 "register_operand" "=d")
 194           (mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
 195                      (match_operand:V2HI 2 "register_operand" "d")))
 196      (set (reg:CCDSP CCDSP_OU_REGNUM)
 197           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH))
 198      (clobber (match_scratch:DI 3 "=x"))])]
 199   "ISA_HAS_DSPR2"
 200   "mul.ph\t%0,%1,%2"
 201   [(set_attr "type"     "imul3")
 202    (set_attr "mode"     "SI")])
 203
 204 (define_insn "mips_mul_s_ph"
 205   [(parallel
 206     [(set (match_operand:V2HI 0 "register_operand" "=d")
 207           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 208                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 209                        UNSPEC_MUL_S_PH))
 210      (set (reg:CCDSP CCDSP_OU_REGNUM)
 211           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH))
 212      (clobber (match_scratch:DI 3 "=x"))])]
 213   "ISA_HAS_DSPR2"
 214   "mul_s.ph\t%0,%z1,%z2"
 215   [(set_attr "type"     "imul3")
 216    (set_attr "mode"     "SI")])
 217
 218 (define_insn "mips_mulq_rs_w"
 219   [(parallel
 220     [(set (match_operand:SI 0 "register_operand" "=d")
 221           (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 222                       (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 223                      UNSPEC_MULQ_RS_W))
 224      (set (reg:CCDSP CCDSP_OU_REGNUM)
 225           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W))
 226      (clobber (match_scratch:DI 3 "=x"))])]
 227   "ISA_HAS_DSPR2"
 228   "mulq_rs.w\t%0,%z1,%z2"
 229   [(set_attr "type"     "imul3")
 230    (set_attr "mode"     "SI")])
 231
 232 (define_insn "mips_mulq_s_ph"
 233   [(parallel
 234     [(set (match_operand:V2HI 0 "register_operand" "=d")
 235           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 236                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 237                        UNSPEC_MULQ_S_PH))
 238      (set (reg:CCDSP CCDSP_OU_REGNUM)
 239           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH))
 240      (clobber (match_scratch:DI 3 "=x"))])]
 241   "ISA_HAS_DSPR2"
 242   "mulq_s.ph\t%0,%z1,%z2"
 243   [(set_attr "type"     "imul3")
 244    (set_attr "mode"     "SI")])
 245
 246 (define_insn "mips_mulq_s_w"
 247   [(parallel
 248     [(set (match_operand:SI 0 "register_operand" "=d")
 249           (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 250                       (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 251                      UNSPEC_MULQ_S_W))
 252      (set (reg:CCDSP CCDSP_OU_REGNUM)
 253           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W))
 254      (clobber (match_scratch:DI 3 "=x"))])]
 255   "ISA_HAS_DSPR2"
 256   "mulq_s.w\t%0,%z1,%z2"
 257   [(set_attr "type"     "imul3")
 258    (set_attr "mode"     "SI")])
 259
 260 (define_insn "mips_mulsa_w_ph"
 261   [(set (match_operand:DI 0 "register_operand" "=a")
 262         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 263                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 264                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 265                    UNSPEC_MULSA_W_PH))]
 266   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 267   "mulsa.w.ph\t%q0,%z2,%z3"
 268   [(set_attr "type"     "imadd")
 269    (set_attr "mode"     "SI")])
 270
 271 (define_insn "mips_mult"
 272   [(set (match_operand:DI 0 "register_operand" "=a")
 273         (mult:DI
 274          (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
 275          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
 276   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 277   "mult\t%q0,%1,%2"
 278   [(set_attr "type"     "imul")
 279    (set_attr "mode"     "SI")])
 280
 281 (define_insn "mips_multu"
 282   [(set (match_operand:DI 0 "register_operand" "=a")
 283         (mult:DI
 284          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
 285          (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
 286   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 287   "multu\t%q0,%1,%2"
 288   [(set_attr "type"     "imul")
 289    (set_attr "mode"     "SI")])
 290
 291 (define_insn "mips_precr_qb_ph"
 292   [(set (match_operand:V4QI 0 "register_operand" "=d")
 293         (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 294                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 295                      UNSPEC_PRECR_QB_PH))]
 296   "ISA_HAS_DSPR2"
 297   "precr.qb.ph\t%0,%z1,%z2"
 298   [(set_attr "type"     "arith")
 299    (set_attr "mode"     "SI")])
 300
 301 (define_insn "mips_precr_sra_ph_w"
 302   [(set (match_operand:V2HI 0 "register_operand" "=d")
 303         (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
 304                       (match_operand:SI 2 "reg_or_0_operand" "dJ")
 305                       (match_operand:SI 3 "const_int_operand" "n")]
 306                      UNSPEC_PRECR_SRA_PH_W))]
 307   "ISA_HAS_DSPR2"
 308 {
 309   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 310     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 311   return "precr_sra.ph.w\t%0,%z2,%3";
 312 }
 313   [(set_attr "type"     "arith")
 314    (set_attr "mode"     "SI")])
 315
 316 (define_insn "mips_precr_sra_r_ph_w"
 317   [(set (match_operand:V2HI 0 "register_operand" "=d")
 318         (unspec:V2HI [(match_operand:SI 1 "register_operand" "0")
 319                       (match_operand:SI 2 "reg_or_0_operand" "dJ")
 320                       (match_operand:SI 3 "const_int_operand" "n")]
 321                      UNSPEC_PRECR_SRA_R_PH_W))]
 322   "ISA_HAS_DSPR2"
 323 {
 324   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 325     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 326   return "precr_sra_r.ph.w\t%0,%z2,%3";
 327 }
 328   [(set_attr "type"     "arith")
 329    (set_attr "mode"     "SI")])
 330
 331 (define_insn "mips_prepend"
 332   [(set (match_operand:SI 0 "register_operand" "=d")
 333         (unspec:SI [(match_operand:SI 1 "register_operand" "0")
 334                     (match_operand:SI 2 "reg_or_0_operand" "dJ")
 335                     (match_operand:SI 3 "const_int_operand" "n")]
 336                    UNSPEC_PREPEND))]
 337   "ISA_HAS_DSPR2"
 338 {
 339   if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31)
 340     operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
 341   return "prepend\t%0,%z2,%3";
 342 }
 343   [(set_attr "type"     "arith")
 344    (set_attr "mode"     "SI")])
 345
 346 (define_insn "mips_shra_qb"
 347   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 348         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
 349                       (match_operand:SI 2 "arith_operand" "I,d")]
 350                      UNSPEC_SHRA_QB))]
 351   "ISA_HAS_DSPR2"
 352 {
 353   if (which_alternative == 0)
 354     {
 355       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
 356         operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
 357       return "shra.qb\t%0,%z1,%2";
 358     }
 359   return "shrav.qb\t%0,%z1,%2";
 360 }
 361   [(set_attr "type"     "shift")
 362    (set_attr "mode"     "SI")])
 363
 364
 365 (define_insn "mips_shra_r_qb"
 366   [(set (match_operand:V4QI 0 "register_operand" "=d,d")
 367         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG")
 368                       (match_operand:SI 2 "arith_operand" "I,d")]
 369                      UNSPEC_SHRA_R_QB))]
 370   "ISA_HAS_DSPR2"
 371 {
 372   if (which_alternative == 0)
 373     {
 374       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7)
 375         operands[2] = GEN_INT (INTVAL (operands[2]) & 7);
 376       return "shra_r.qb\t%0,%z1,%2";
 377     }
 378   return "shrav_r.qb\t%0,%z1,%2";
 379 }
 380   [(set_attr "type"     "shift")
 381    (set_attr "mode"     "SI")])
 382
 383 (define_insn "mips_shrl_ph"
 384   [(set (match_operand:V2HI 0 "register_operand" "=d,d")
 385         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG")
 386                       (match_operand:SI 2 "arith_operand" "I,d")]
 387                      UNSPEC_SHRL_PH))]
 388   "ISA_HAS_DSPR2"
 389 {
 390   if (which_alternative == 0)
 391     {
 392       if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15)
 393         operands[2] = GEN_INT (INTVAL (operands[2]) & 15);
 394       return "shrl.ph\t%0,%z1,%2";
 395     }
 396   return "shrlv.ph\t%0,%z1,%2";
 397 }
 398   [(set_attr "type"     "shift")
 399    (set_attr "mode"     "SI")])
 400
 401 (define_insn "mips_subu_ph"
 402   [(parallel
 403     [(set (match_operand:V2HI 0 "register_operand" "=d")
 404           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 405                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 406                        UNSPEC_SUBU_PH))
 407      (set (reg:CCDSP CCDSP_OU_REGNUM)
 408           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
 409   "ISA_HAS_DSPR2"
 410   "subu.ph\t%0,%z1,%z2"
 411   [(set_attr "type"     "arith")
 412    (set_attr "mode"     "SI")])
 413
 414 (define_insn "mips_subu_s_ph"
 415   [(parallel
 416     [(set (match_operand:V2HI 0 "register_operand" "=d")
 417           (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 418                         (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 419                        UNSPEC_SUBU_S_PH))
 420      (set (reg:CCDSP CCDSP_OU_REGNUM)
 421           (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
 422   "ISA_HAS_DSPR2"
 423   "subu_s.ph\t%0,%z1,%z2"
 424   [(set_attr "type"     "arith")
 425    (set_attr "mode"     "SI")])
 426
 427 (define_insn "mips_subuh_qb"
 428   [(set (match_operand:V4QI 0 "register_operand" "=d")
 429         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 430                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 431                      UNSPEC_SUBUH_QB))]
 432   "ISA_HAS_DSPR2"
 433   "subuh.qb\t%0,%z1,%z2"
 434   [(set_attr "type"     "arith")
 435    (set_attr "mode"     "SI")])
 436
 437 (define_insn "mips_subuh_r_qb"
 438   [(set (match_operand:V4QI 0 "register_operand" "=d")
 439         (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")
 440                       (match_operand:V4QI 2 "reg_or_0_operand" "dYG")]
 441                      UNSPEC_SUBUH_R_QB))]
 442   "ISA_HAS_DSPR2"
 443   "subuh_r.qb\t%0,%z1,%z2"
 444   [(set_attr "type"     "arith")
 445    (set_attr "mode"     "SI")])
 446
 447 (define_insn "mips_addqh_ph"
 448   [(set (match_operand:V2HI 0 "register_operand" "=d")
 449         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 450                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 451                      UNSPEC_ADDQH_PH))]
 452   "ISA_HAS_DSPR2"
 453   "addqh.ph\t%0,%z1,%z2"
 454   [(set_attr "type"     "arith")
 455    (set_attr "mode"     "SI")])
 456
 457 (define_insn "mips_addqh_r_ph"
 458   [(set (match_operand:V2HI 0 "register_operand" "=d")
 459         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 460                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 461                      UNSPEC_ADDQH_R_PH))]
 462   "ISA_HAS_DSPR2"
 463   "addqh_r.ph\t%0,%z1,%z2"
 464   [(set_attr "type"     "arith")
 465    (set_attr "mode"     "SI")])
 466
 467 (define_insn "mips_addqh_w"
 468   [(set (match_operand:SI 0 "register_operand" "=d")
 469         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 470                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 471                    UNSPEC_ADDQH_W))]
 472   "ISA_HAS_DSPR2"
 473   "addqh.w\t%0,%z1,%z2"
 474   [(set_attr "type"     "arith")
 475    (set_attr "mode"     "SI")])
 476
 477 (define_insn "mips_addqh_r_w"
 478   [(set (match_operand:SI 0 "register_operand" "=d")
 479         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 480                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 481                    UNSPEC_ADDQH_R_W))]
 482   "ISA_HAS_DSPR2"
 483   "addqh_r.w\t%0,%z1,%z2"
 484   [(set_attr "type"     "arith")
 485    (set_attr "mode"     "SI")])
 486
 487 (define_insn "mips_subqh_ph"
 488   [(set (match_operand:V2HI 0 "register_operand" "=d")
 489         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 490                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 491                      UNSPEC_SUBQH_PH))]
 492   "ISA_HAS_DSPR2"
 493   "subqh.ph\t%0,%z1,%z2"
 494   [(set_attr "type"     "arith")
 495    (set_attr "mode"     "SI")])
 496
 497 (define_insn "mips_subqh_r_ph"
 498   [(set (match_operand:V2HI 0 "register_operand" "=d")
 499         (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG")
 500                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")]
 501                      UNSPEC_SUBQH_R_PH))]
 502   "ISA_HAS_DSPR2"
 503   "subqh_r.ph\t%0,%z1,%z2"
 504   [(set_attr "type"     "arith")
 505    (set_attr "mode"     "SI")])
 506
 507 (define_insn "mips_subqh_w"
 508   [(set (match_operand:SI 0 "register_operand" "=d")
 509         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 510                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 511                    UNSPEC_SUBQH_W))]
 512   "ISA_HAS_DSPR2"
 513   "subqh.w\t%0,%z1,%z2"
 514   [(set_attr "type"     "arith")
 515    (set_attr "mode"     "SI")])
 516
 517 (define_insn "mips_subqh_r_w"
 518   [(set (match_operand:SI 0 "register_operand" "=d")
 519         (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ")
 520                     (match_operand:SI 2 "reg_or_0_operand" "dJ")]
 521                    UNSPEC_SUBQH_R_W))]
 522   "ISA_HAS_DSPR2"
 523   "subqh_r.w\t%0,%z1,%z2"
 524   [(set_attr "type"     "arith")
 525    (set_attr "mode"     "SI")])
 526
 527 (define_insn "mips_dpax_w_ph"
 528   [(set (match_operand:DI 0 "register_operand" "=a")
 529         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 530                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 531                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 532                    UNSPEC_DPAX_W_PH))]
 533   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 534   "dpax.w.ph\t%q0,%z2,%z3"
 535   [(set_attr "type"     "imadd")
 536    (set_attr "mode"     "SI")])
 537
 538 (define_insn "mips_dpsx_w_ph"
 539   [(set (match_operand:DI 0 "register_operand" "=a")
 540         (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 541                     (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 542                     (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 543                    UNSPEC_DPSX_W_PH))]
 544   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 545   "dpsx.w.ph\t%q0,%z2,%z3"
 546   [(set_attr "type"     "imadd")
 547    (set_attr "mode"     "SI")])
 548
 549 (define_insn "mips_dpaqx_s_w_ph"
 550   [(parallel
 551     [(set (match_operand:DI 0 "register_operand" "=a")
 552           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 553                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 554                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 555                      UNSPEC_DPAQX_S_W_PH))
 556      (set (reg:CCDSP CCDSP_OU_REGNUM)
 557           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 558                         UNSPEC_DPAQX_S_W_PH))])]
 559   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 560   "dpaqx_s.w.ph\t%q0,%z2,%z3"
 561   [(set_attr "type"     "imadd")
 562    (set_attr "mode"     "SI")])
 563
 564 (define_insn "mips_dpaqx_sa_w_ph"
 565   [(parallel
 566     [(set (match_operand:DI 0 "register_operand" "=a")
 567           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 568                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 569                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 570                      UNSPEC_DPAQX_SA_W_PH))
 571      (set (reg:CCDSP CCDSP_OU_REGNUM)
 572           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 573                         UNSPEC_DPAQX_SA_W_PH))])]
 574   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 575   "dpaqx_sa.w.ph\t%q0,%z2,%z3"
 576   [(set_attr "type"     "imadd")
 577    (set_attr "mode"     "SI")])
 578
 579 (define_insn "mips_dpsqx_s_w_ph"
 580   [(parallel
 581     [(set (match_operand:DI 0 "register_operand" "=a")
 582           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 583                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 584                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 585                      UNSPEC_DPSQX_S_W_PH))
 586      (set (reg:CCDSP CCDSP_OU_REGNUM)
 587           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 588                         UNSPEC_DPSQX_S_W_PH))])]
 589   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 590   "dpsqx_s.w.ph\t%q0,%z2,%z3"
 591   [(set_attr "type"     "imadd")
 592    (set_attr "mode"     "SI")])
 593
 594 (define_insn "mips_dpsqx_sa_w_ph"
 595   [(parallel
 596     [(set (match_operand:DI 0 "register_operand" "=a")
 597           (unspec:DI [(match_operand:DI 1 "register_operand" "0")
 598                       (match_operand:V2HI 2 "reg_or_0_operand" "dYG")
 599                       (match_operand:V2HI 3 "reg_or_0_operand" "dYG")]
 600                      UNSPEC_DPSQX_SA_W_PH))
 601      (set (reg:CCDSP CCDSP_OU_REGNUM)
 602           (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)]
 603                         UNSPEC_DPSQX_SA_W_PH))])]
 604   "ISA_HAS_DSPR2 && !TARGET_64BIT"
 605   "dpsqx_sa.w.ph\t%q0,%z2,%z3"
 606   [(set_attr "type"     "imadd")
 607    (set_attr "mode"     "SI")])