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[thirdparty/gcc.git] / gcc / config / mips / mips-msa.md
1 ;; Machine Description for MIPS MSA ASE
2 ;; Based on the MIPS MSA spec Revision 1.11 8/4/2014
3 ;;
4 ;; Copyright (C) 2015-2024 Free Software Foundation, Inc.
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
21 ;;
22
23 (define_c_enum "unspec" [
24 UNSPEC_MSA_ASUB_S
25 UNSPEC_MSA_ASUB_U
26 UNSPEC_MSA_AVE_S
27 UNSPEC_MSA_AVE_U
28 UNSPEC_MSA_AVER_S
29 UNSPEC_MSA_AVER_U
30 UNSPEC_MSA_BCLR
31 UNSPEC_MSA_BCLRI
32 UNSPEC_MSA_BINSL
33 UNSPEC_MSA_BINSLI
34 UNSPEC_MSA_BINSR
35 UNSPEC_MSA_BINSRI
36 UNSPEC_MSA_BNEG
37 UNSPEC_MSA_BNEGI
38 UNSPEC_MSA_BSET
39 UNSPEC_MSA_BSETI
40 UNSPEC_MSA_BRANCH_V
41 UNSPEC_MSA_BRANCH
42 UNSPEC_MSA_CFCMSA
43 UNSPEC_MSA_CTCMSA
44 UNSPEC_MSA_FCAF
45 UNSPEC_MSA_FCLASS
46 UNSPEC_MSA_FCUNE
47 UNSPEC_MSA_FEXDO
48 UNSPEC_MSA_FEXP2
49 UNSPEC_MSA_FEXUPL
50 UNSPEC_MSA_FEXUPR
51 UNSPEC_MSA_FFQL
52 UNSPEC_MSA_FFQR
53 UNSPEC_MSA_FLOG2
54 UNSPEC_MSA_FRCP
55 UNSPEC_MSA_FRINT
56 UNSPEC_MSA_FRSQRT
57 UNSPEC_MSA_FSAF
58 UNSPEC_MSA_FSEQ
59 UNSPEC_MSA_FSLE
60 UNSPEC_MSA_FSLT
61 UNSPEC_MSA_FSNE
62 UNSPEC_MSA_FSOR
63 UNSPEC_MSA_FSUEQ
64 UNSPEC_MSA_FSULE
65 UNSPEC_MSA_FSULT
66 UNSPEC_MSA_FSUN
67 UNSPEC_MSA_FSUNE
68 UNSPEC_MSA_FTINT_S
69 UNSPEC_MSA_FTINT_U
70 UNSPEC_MSA_FTQ
71 UNSPEC_MSA_MADD_Q
72 UNSPEC_MSA_MADDR_Q
73 UNSPEC_MSA_MSUB_Q
74 UNSPEC_MSA_MSUBR_Q
75 UNSPEC_MSA_MUL_Q
76 UNSPEC_MSA_MULR_Q
77 UNSPEC_MSA_NLOC
78 UNSPEC_MSA_SAT_S
79 UNSPEC_MSA_SAT_U
80 UNSPEC_MSA_SLD
81 UNSPEC_MSA_SLDI
82 UNSPEC_MSA_SPLAT
83 UNSPEC_MSA_SPLATI
84 UNSPEC_MSA_SRAR
85 UNSPEC_MSA_SRARI
86 UNSPEC_MSA_SRLR
87 UNSPEC_MSA_SRLRI
88 UNSPEC_MSA_SUBS_S
89 UNSPEC_MSA_SUBS_U
90 UNSPEC_MSA_SUBSUU_S
91 UNSPEC_MSA_SUBSUS_U
92 UNSPEC_MSA_VSHF
93 ])
94
95 ;; All vector modes with 128 bits.
96 (define_mode_iterator MSA [V2DF V4SF V2DI V4SI V8HI V16QI])
97
98 ;; Same as MSA. Used by vcond to iterate two modes.
99 (define_mode_iterator MSA_2 [V2DF V4SF V2DI V4SI V8HI V16QI])
100
101 ;; Only used for splitting insert_d and copy_{u,s}.d.
102 (define_mode_iterator MSA_D [V2DI V2DF])
103
104 ;; Only used for copy_{u,s}.w.
105 (define_mode_iterator MSA_W [V4SI V4SF])
106
107 ;; Only integer modes.
108 (define_mode_iterator IMSA [V2DI V4SI V8HI V16QI])
109
110 ;; As IMSA but excludes V16QI.
111 (define_mode_iterator IMSA_DWH [V2DI V4SI V8HI])
112
113 ;; As IMSA but excludes V2DI.
114 (define_mode_iterator IMSA_WHB [V4SI V8HI V16QI])
115
116 ;; Only integer modes equal or larger than a word.
117 (define_mode_iterator IMSA_DW [V2DI V4SI])
118
119 ;; Only integer modes smaller than a word.
120 (define_mode_iterator IMSA_HB [V8HI V16QI])
121
122 ;; Only integer modes for fixed-point madd_q/maddr_q.
123 (define_mode_iterator IMSA_WH [V4SI V8HI])
124
125 ;; Only floating-point modes.
126 (define_mode_iterator FMSA [V2DF V4SF])
127
128 ;; Only used for immediate set shuffle elements instruction.
129 (define_mode_iterator MSA_WHB_W [V4SI V8HI V16QI V4SF])
130
131 ;; The attribute gives the integer vector mode with same size.
132 (define_mode_attr VIMODE
133 [(V2DF "V2DI")
134 (V4SF "V4SI")
135 (V2DI "V2DI")
136 (V4SI "V4SI")
137 (V8HI "V8HI")
138 (V16QI "V16QI")])
139
140 ;; The attribute gives half modes for vector modes.
141 (define_mode_attr VHMODE
142 [(V8HI "V16QI")
143 (V4SI "V8HI")
144 (V2DI "V4SI")])
145
146 ;; The attribute gives double modes for vector modes.
147 (define_mode_attr VDMODE
148 [(V4SI "V2DI")
149 (V8HI "V4SI")
150 (V16QI "V8HI")])
151
152 ;; The attribute gives half modes with same number of elements for vector modes.
153 (define_mode_attr VTRUNCMODE
154 [(V8HI "V8QI")
155 (V4SI "V4HI")
156 (V2DI "V2SI")])
157
158 ;; This attribute gives the mode of the result for "copy_s_b, copy_u_b" etc.
159 (define_mode_attr VRES
160 [(V2DF "DF")
161 (V4SF "SF")
162 (V2DI "DI")
163 (V4SI "SI")
164 (V8HI "SI")
165 (V16QI "SI")])
166
167 ;; Only used with MSA_D iterator.
168 (define_mode_attr msa_d
169 [(V2DI "reg_or_0")
170 (V2DF "register")])
171
172 ;; This attribute gives the integer vector mode with same size.
173 (define_mode_attr mode_i
174 [(V2DF "v2di")
175 (V4SF "v4si")
176 (V2DI "v2di")
177 (V4SI "v4si")
178 (V8HI "v8hi")
179 (V16QI "v16qi")])
180
181 ;; This attribute gives suffix for MSA instructions.
182 (define_mode_attr msafmt
183 [(V2DF "d")
184 (V4SF "w")
185 (V2DI "d")
186 (V4SI "w")
187 (V8HI "h")
188 (V16QI "b")])
189
190 ;; This attribute gives suffix for integers in VHMODE.
191 (define_mode_attr hmsafmt
192 [(V2DI "w")
193 (V4SI "h")
194 (V8HI "b")])
195
196 ;; This attribute gives define_insn suffix for MSA instructions that need
197 ;; distinction between integer and floating point.
198 (define_mode_attr msafmt_f
199 [(V2DF "d_f")
200 (V4SF "w_f")
201 (V2DI "d")
202 (V4SI "w")
203 (V8HI "h")
204 (V16QI "b")])
205
206 ;; This is used to form an immediate operand constraint using
207 ;; "const_<indeximm>_operand".
208 (define_mode_attr indeximm
209 [(V2DF "0_or_1")
210 (V4SF "0_to_3")
211 (V2DI "0_or_1")
212 (V4SI "0_to_3")
213 (V8HI "uimm3")
214 (V16QI "uimm4")])
215
216 ;; This attribute represents bitmask needed for vec_merge using
217 ;; "const_<bitmask>_operand".
218 (define_mode_attr bitmask
219 [(V2DF "exp_2")
220 (V4SF "exp_4")
221 (V2DI "exp_2")
222 (V4SI "exp_4")
223 (V8HI "exp_8")
224 (V16QI "exp_16")])
225
226 ;; This attribute is used to form an immediate operand constraint using
227 ;; "const_<bitimm>_operand".
228 (define_mode_attr bitimm
229 [(V16QI "uimm3")
230 (V8HI "uimm4")
231 (V4SI "uimm5")
232 (V2DI "uimm6")])
233
234 (define_expand "vec_init<mode><unitmode>"
235 [(match_operand:MSA 0 "register_operand")
236 (match_operand:MSA 1 "")]
237 "ISA_HAS_MSA"
238 {
239 mips_expand_vector_init (operands[0], operands[1]);
240 DONE;
241 })
242
243 ;; pckev pattern with implicit type conversion.
244 (define_insn "vec_pack_trunc_<mode>"
245 [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
246 (vec_concat:<VHMODE>
247 (truncate:<VTRUNCMODE>
248 (match_operand:IMSA_DWH 1 "register_operand" "f"))
249 (truncate:<VTRUNCMODE>
250 (match_operand:IMSA_DWH 2 "register_operand" "f"))))]
251 "ISA_HAS_MSA"
252 "pckev.<hmsafmt>\t%w0,%w2,%w1"
253 [(set_attr "type" "simd_permute")
254 (set_attr "mode" "<MODE>")])
255
256 (define_expand "vec_unpacks_hi_v4sf"
257 [(set (match_operand:V2DF 0 "register_operand" "=f")
258 (float_extend:V2DF
259 (vec_select:V2SF
260 (match_operand:V4SF 1 "register_operand" "f")
261 (match_dup 2))))]
262 "ISA_HAS_MSA"
263 {
264 operands[2] = mips_msa_vec_parallel_const_half (V4SFmode, true/*high_p*/);
265 })
266
267 (define_expand "vec_unpacks_lo_v4sf"
268 [(set (match_operand:V2DF 0 "register_operand" "=f")
269 (float_extend:V2DF
270 (vec_select:V2SF
271 (match_operand:V4SF 1 "register_operand" "f")
272 (match_dup 2))))]
273 "ISA_HAS_MSA"
274 {
275 operands[2] = mips_msa_vec_parallel_const_half (V4SFmode, false/*high_p*/);
276 })
277
278 (define_expand "vec_unpacks_hi_<mode>"
279 [(match_operand:<VDMODE> 0 "register_operand")
280 (match_operand:IMSA_WHB 1 "register_operand")]
281 "ISA_HAS_MSA"
282 {
283 mips_expand_vec_unpack (operands, false/*unsigned_p*/, true/*high_p*/);
284 DONE;
285 })
286
287 (define_expand "vec_unpacks_lo_<mode>"
288 [(match_operand:<VDMODE> 0 "register_operand")
289 (match_operand:IMSA_WHB 1 "register_operand")]
290 "ISA_HAS_MSA"
291 {
292 mips_expand_vec_unpack (operands, false/*unsigned_p*/, false/*high_p*/);
293 DONE;
294 })
295
296 (define_expand "vec_unpacku_hi_<mode>"
297 [(match_operand:<VDMODE> 0 "register_operand")
298 (match_operand:IMSA_WHB 1 "register_operand")]
299 "ISA_HAS_MSA"
300 {
301 mips_expand_vec_unpack (operands, true/*unsigned_p*/, true/*high_p*/);
302 DONE;
303 })
304
305 (define_expand "vec_unpacku_lo_<mode>"
306 [(match_operand:<VDMODE> 0 "register_operand")
307 (match_operand:IMSA_WHB 1 "register_operand")]
308 "ISA_HAS_MSA"
309 {
310 mips_expand_vec_unpack (operands, true/*unsigned_p*/, false/*high_p*/);
311 DONE;
312 })
313
314 (define_expand "vec_extract<mode><unitmode>"
315 [(match_operand:<UNITMODE> 0 "register_operand")
316 (match_operand:IMSA 1 "register_operand")
317 (match_operand 2 "const_<indeximm>_operand")]
318 "ISA_HAS_MSA"
319 {
320 if (<UNITMODE>mode == QImode || <UNITMODE>mode == HImode)
321 {
322 rtx dest1 = gen_reg_rtx (SImode);
323 emit_insn (gen_msa_copy_s_<msafmt> (dest1, operands[1], operands[2]));
324 emit_move_insn (operands[0],
325 gen_lowpart (<UNITMODE>mode, dest1));
326 }
327 else
328 emit_insn (gen_msa_copy_s_<msafmt> (operands[0], operands[1], operands[2]));
329 DONE;
330 })
331
332 (define_expand "vec_extract<mode><unitmode>"
333 [(match_operand:<UNITMODE> 0 "register_operand")
334 (match_operand:FMSA 1 "register_operand")
335 (match_operand 2 "const_<indeximm>_operand")]
336 "ISA_HAS_MSA"
337 {
338 rtx temp;
339 HOST_WIDE_INT val = INTVAL (operands[2]);
340
341 if (val == 0)
342 temp = operands[1];
343 else
344 {
345 /* We need to do the SLDI operation in V16QImode and adjust
346 operands[2] accordingly. */
347 rtx wd = gen_reg_rtx (V16QImode);
348 rtx ws = gen_reg_rtx (V16QImode);
349 emit_move_insn (ws, gen_lowpart (V16QImode, operands[1]));
350 rtx n = GEN_INT (val * GET_MODE_SIZE (<UNITMODE>mode));
351 gcc_assert (INTVAL (n) < GET_MODE_NUNITS (V16QImode));
352 emit_insn (gen_msa_sldi_b (wd, ws, ws, n));
353 temp = gen_reg_rtx (<MODE>mode);
354 emit_move_insn (temp, gen_lowpart (<MODE>mode, wd));
355 }
356 emit_insn (gen_msa_vec_extract_<msafmt_f> (operands[0], temp));
357 DONE;
358 })
359
360 (define_insn_and_split "msa_vec_extract_<msafmt_f>"
361 [(set (match_operand:<UNITMODE> 0 "register_operand" "=f")
362 (vec_select:<UNITMODE>
363 (match_operand:FMSA 1 "register_operand" "f")
364 (parallel [(const_int 0)])))]
365 "ISA_HAS_MSA"
366 "#"
367 "&& reload_completed"
368 [(set (match_dup 0) (match_dup 1))]
369 {
370 /* An MSA register cannot be reinterpreted as a single precision
371 register when using -mno-odd-spreg and the MSA register is
372 an odd number. */
373 if (<UNITMODE>mode == SFmode && !TARGET_ODD_SPREG
374 && (REGNO (operands[1]) & 1))
375 {
376 emit_move_insn (gen_rtx_REG (<MODE>mode, REGNO (operands[0])),
377 operands[1]);
378 operands[1] = operands[0];
379 }
380 else
381 operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));
382 }
383 [(set_attr "move_type" "fmove")
384 (set_attr "mode" "<UNITMODE>")])
385
386 (define_expand "vec_set<mode>"
387 [(match_operand:IMSA 0 "register_operand")
388 (match_operand:<UNITMODE> 1 "reg_or_0_operand")
389 (match_operand 2 "const_<indeximm>_operand")]
390 "ISA_HAS_MSA"
391 {
392 rtx index = GEN_INT (1 << INTVAL (operands[2]));
393 emit_insn (gen_msa_insert_<msafmt> (operands[0], operands[1],
394 operands[0], index));
395 DONE;
396 })
397
398 (define_expand "vec_set<mode>"
399 [(match_operand:FMSA 0 "register_operand")
400 (match_operand:<UNITMODE> 1 "register_operand")
401 (match_operand 2 "const_<indeximm>_operand")]
402 "ISA_HAS_MSA"
403 {
404 rtx index = GEN_INT (1 << INTVAL (operands[2]));
405 emit_insn (gen_msa_insve_<msafmt_f>_scalar (operands[0], operands[1],
406 operands[0], index));
407 DONE;
408 })
409
410 (define_expand "vcondu<MSA:mode><IMSA:mode>"
411 [(match_operand:MSA 0 "register_operand")
412 (match_operand:MSA 1 "reg_or_m1_operand")
413 (match_operand:MSA 2 "reg_or_0_operand")
414 (match_operator 3 ""
415 [(match_operand:IMSA 4 "register_operand")
416 (match_operand:IMSA 5 "register_operand")])]
417 "ISA_HAS_MSA
418 && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<IMSA:MODE>mode))"
419 {
420 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands);
421 DONE;
422 })
423
424 (define_expand "vcond<MSA:mode><MSA_2:mode>"
425 [(match_operand:MSA 0 "register_operand")
426 (match_operand:MSA 1 "reg_or_m1_operand")
427 (match_operand:MSA 2 "reg_or_0_operand")
428 (match_operator 3 ""
429 [(match_operand:MSA_2 4 "register_operand")
430 (match_operand:MSA_2 5 "register_operand")])]
431 "ISA_HAS_MSA
432 && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<MSA_2:MODE>mode))"
433 {
434 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands);
435 DONE;
436 })
437
438 (define_expand "vec_cmp<MSA:mode><mode_i>"
439 [(match_operand:<VIMODE> 0 "register_operand")
440 (match_operator 1 ""
441 [(match_operand:MSA 2 "register_operand")
442 (match_operand:MSA 3 "register_operand")])]
443 "ISA_HAS_MSA"
444 {
445 mips_expand_vec_cmp_expr (operands);
446 DONE;
447 })
448
449 (define_expand "vec_cmpu<IMSA:mode><mode_i>"
450 [(match_operand:<VIMODE> 0 "register_operand")
451 (match_operator 1 ""
452 [(match_operand:IMSA 2 "register_operand")
453 (match_operand:IMSA 3 "register_operand")])]
454 "ISA_HAS_MSA"
455 {
456 mips_expand_vec_cmp_expr (operands);
457 DONE;
458 })
459
460 (define_insn "msa_insert_<msafmt_f>"
461 [(set (match_operand:MSA 0 "register_operand" "=f,f")
462 (vec_merge:MSA
463 (vec_duplicate:MSA
464 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ,f"))
465 (match_operand:MSA 2 "register_operand" "0,0")
466 (match_operand 3 "const_<bitmask>_operand" "")))]
467 "ISA_HAS_MSA"
468 {
469 if (which_alternative == 1)
470 return "insve.<msafmt>\t%w0[%y3],%w1[0]";
471
472 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
473 return "#";
474 else
475 return "insert.<msafmt>\t%w0[%y3],%z1";
476 }
477 [(set_attr "type" "simd_insert")
478 (set_attr "mode" "<MODE>")])
479
480 (define_split
481 [(set (match_operand:MSA_D 0 "register_operand")
482 (vec_merge:MSA_D
483 (vec_duplicate:MSA_D
484 (match_operand:<UNITMODE> 1 "<MSA_D:msa_d>_operand"))
485 (match_operand:MSA_D 2 "register_operand")
486 (match_operand 3 "const_<bitmask>_operand")))]
487 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
488 [(const_int 0)]
489 {
490 if (REG_P (operands[1]) && FP_REG_P (REGNO (operands[1])))
491 FAIL;
492 mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]);
493 DONE;
494 })
495
496 (define_insn "msa_insve_<msafmt_f>"
497 [(set (match_operand:MSA 0 "register_operand" "=f")
498 (vec_merge:MSA
499 (vec_duplicate:MSA
500 (vec_select:<UNITMODE>
501 (match_operand:MSA 1 "register_operand" "f")
502 (parallel [(const_int 0)])))
503 (match_operand:MSA 2 "register_operand" "0")
504 (match_operand 3 "const_<bitmask>_operand" "")))]
505 "ISA_HAS_MSA"
506 "insve.<msafmt>\t%w0[%y3],%w1[0]"
507 [(set_attr "type" "simd_insert")
508 (set_attr "mode" "<MODE>")])
509
510 ;; Operand 3 is a scalar.
511 (define_insn "msa_insve_<msafmt_f>_scalar"
512 [(set (match_operand:FMSA 0 "register_operand" "=f")
513 (vec_merge:FMSA
514 (vec_duplicate:FMSA
515 (match_operand:<UNITMODE> 1 "register_operand" "f"))
516 (match_operand:FMSA 2 "register_operand" "0")
517 (match_operand 3 "const_<bitmask>_operand" "")))]
518 "ISA_HAS_MSA"
519 "insve.<msafmt>\t%w0[%y3],%w1[0]"
520 [(set_attr "type" "simd_insert")
521 (set_attr "mode" "<MODE>")])
522
523 (define_insn "msa_copy_<su>_<msafmt>"
524 [(set (match_operand:<VRES> 0 "register_operand" "=d")
525 (any_extend:<VRES>
526 (vec_select:<UNITMODE>
527 (match_operand:IMSA_HB 1 "register_operand" "f")
528 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
529 "ISA_HAS_MSA"
530 "copy_<su>.<msafmt>\t%0,%w1[%2]"
531 [(set_attr "type" "simd_copy")
532 (set_attr "mode" "<MODE>")])
533
534 (define_insn "msa_copy_u_w"
535 [(set (match_operand:DI 0 "register_operand" "=d")
536 (zero_extend:DI
537 (vec_select:SI
538 (match_operand:V4SI 1 "register_operand" "f")
539 (parallel [(match_operand 2 "const_0_to_3_operand" "")]))))]
540 "ISA_HAS_MSA && TARGET_64BIT"
541 "copy_u.w\t%0,%w1[%2]"
542 [(set_attr "type" "simd_copy")
543 (set_attr "mode" "V4SI")])
544
545 (define_insn "msa_copy_s_<msafmt_f>_64bit"
546 [(set (match_operand:DI 0 "register_operand" "=d")
547 (sign_extend:DI
548 (vec_select:<UNITMODE>
549 (match_operand:MSA_W 1 "register_operand" "f")
550 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
551 "ISA_HAS_MSA && TARGET_64BIT"
552 "copy_s.<msafmt>\t%0,%w1[%2]"
553 [(set_attr "type" "simd_copy")
554 (set_attr "mode" "<MODE>")])
555
556 (define_insn "msa_copy_s_<msafmt_f>"
557 [(set (match_operand:<UNITMODE> 0 "register_operand" "=d")
558 (vec_select:<UNITMODE>
559 (match_operand:MSA_W 1 "register_operand" "f")
560 (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))]
561 "ISA_HAS_MSA"
562 "copy_s.<msafmt>\t%0,%w1[%2]"
563 [(set_attr "type" "simd_copy")
564 (set_attr "mode" "<MODE>")])
565
566 (define_insn_and_split "msa_copy_s_<msafmt_f>"
567 [(set (match_operand:<UNITMODE> 0 "register_operand" "=d")
568 (vec_select:<UNITMODE>
569 (match_operand:MSA_D 1 "register_operand" "f")
570 (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))]
571 "ISA_HAS_MSA"
572 {
573 if (TARGET_64BIT)
574 return "copy_s.<msafmt>\t%0,%w1[%2]";
575 else
576 return "#";
577 }
578 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
579 [(const_int 0)]
580 {
581 mips_split_msa_copy_d (operands[0], operands[1], operands[2],
582 gen_msa_copy_s_w);
583 DONE;
584 }
585 [(set_attr "type" "simd_copy")
586 (set_attr "mode" "<MODE>")])
587
588 (define_expand "abs<mode>2"
589 [(match_operand:IMSA 0 "register_operand" "=f")
590 (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))]
591 "ISA_HAS_MSA"
592 {
593 rtx reg = gen_reg_rtx (<MODE>mode);
594 emit_move_insn (reg, CONST0_RTX (<MODE>mode));
595 emit_insn (gen_msa_add_a_<msafmt> (operands[0], operands[1], reg));
596 DONE;
597 })
598
599 (define_expand "neg<mode>2"
600 [(set (match_operand:MSA 0 "register_operand")
601 (minus:MSA (match_dup 2)
602 (match_operand:MSA 1 "register_operand")))]
603 "ISA_HAS_MSA"
604 {
605 rtx reg = gen_reg_rtx (<MODE>mode);
606 emit_move_insn (reg, CONST0_RTX (<MODE>mode));
607 operands[2] = reg;
608 })
609
610 (define_expand "msa_ldi<mode>"
611 [(match_operand:IMSA 0 "register_operand")
612 (match_operand 1 "const_imm10_operand")]
613 "ISA_HAS_MSA"
614 {
615 if (<MODE>mode == V16QImode)
616 operands[1] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]),
617 <UNITMODE>mode));
618 emit_move_insn (operands[0],
619 mips_gen_const_int_vector (<MODE>mode, INTVAL (operands[1])));
620 DONE;
621 })
622
623 (define_insn "vec_perm<mode>"
624 [(set (match_operand:MSA 0 "register_operand" "=f")
625 (unspec:MSA [(match_operand:MSA 1 "register_operand" "f")
626 (match_operand:MSA 2 "register_operand" "f")
627 (match_operand:<VIMODE> 3 "register_operand" "0")]
628 UNSPEC_MSA_VSHF))]
629 "ISA_HAS_MSA"
630 "vshf.<msafmt>\t%w0,%w2,%w1"
631 [(set_attr "type" "simd_sld")
632 (set_attr "mode" "<MODE>")])
633
634 (define_expand "mov<mode>"
635 [(set (match_operand:MSA 0)
636 (match_operand:MSA 1))]
637 "ISA_HAS_MSA"
638 {
639 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
640 DONE;
641 })
642
643 (define_expand "movmisalign<mode>"
644 [(set (match_operand:MSA 0)
645 (match_operand:MSA 1))]
646 "ISA_HAS_MSA"
647 {
648 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
649 DONE;
650 })
651
652 ;; 128-bit MSA modes can only exist in MSA registers or memory. An exception
653 ;; is allowing MSA modes for GP registers for arguments and return values.
654 (define_insn "mov<mode>_msa"
655 [(set (match_operand:MSA 0 "nonimmediate_operand" "=f,f,R,*d,*f")
656 (match_operand:MSA 1 "move_operand" "fYGYI,R,f,*f,*d"))]
657 "ISA_HAS_MSA"
658 { return mips_output_move (operands[0], operands[1]); }
659 [(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert")
660 (set_attr "mode" "<MODE>")])
661
662 (define_split
663 [(set (match_operand:MSA 0 "nonimmediate_operand")
664 (match_operand:MSA 1 "move_operand"))]
665 "reload_completed && ISA_HAS_MSA
666 && mips_split_move_insn_p (operands[0], operands[1], insn)"
667 [(const_int 0)]
668 {
669 mips_split_move_insn (operands[0], operands[1], curr_insn);
670 DONE;
671 })
672
673 ;; Offset load
674 (define_expand "msa_ld_<msafmt_f>"
675 [(match_operand:MSA 0 "register_operand")
676 (match_operand 1 "pmode_register_operand")
677 (match_operand 2 "aq10<msafmt>_operand")]
678 "ISA_HAS_MSA"
679 {
680 rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
681 INTVAL (operands[2]));
682 mips_emit_move (operands[0], gen_rtx_MEM (<MODE>mode, addr));
683 DONE;
684 })
685
686 ;; Offset store
687 (define_expand "msa_st_<msafmt_f>"
688 [(match_operand:MSA 0 "register_operand")
689 (match_operand 1 "pmode_register_operand")
690 (match_operand 2 "aq10<msafmt>_operand")]
691 "ISA_HAS_MSA"
692 {
693 rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
694 INTVAL (operands[2]));
695 mips_emit_move (gen_rtx_MEM (<MODE>mode, addr), operands[0]);
696 DONE;
697 })
698
699 ;; Integer operations
700 (define_insn "add<mode>3"
701 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
702 (plus:IMSA
703 (match_operand:IMSA 1 "register_operand" "f,f,f")
704 (match_operand:IMSA 2 "reg_or_vector_same_ximm5_operand" "f,Unv5,Uuv5")))]
705 "ISA_HAS_MSA"
706 {
707 switch (which_alternative)
708 {
709 case 0:
710 return "addv.<msafmt>\t%w0,%w1,%w2";
711 case 1:
712 {
713 HOST_WIDE_INT val = INTVAL (CONST_VECTOR_ELT (operands[2], 0));
714
715 operands[2] = GEN_INT (-val);
716 return "subvi.<msafmt>\t%w0,%w1,%d2";
717 }
718 case 2:
719 return "addvi.<msafmt>\t%w0,%w1,%E2";
720 default:
721 gcc_unreachable ();
722 }
723 }
724 [(set_attr "alu_type" "simd_add")
725 (set_attr "type" "simd_int_arith")
726 (set_attr "mode" "<MODE>")])
727
728 (define_insn "sub<mode>3"
729 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
730 (minus:IMSA
731 (match_operand:IMSA 1 "register_operand" "f,f")
732 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
733 "ISA_HAS_MSA"
734 "@
735 subv.<msafmt>\t%w0,%w1,%w2
736 subvi.<msafmt>\t%w0,%w1,%E2"
737 [(set_attr "alu_type" "simd_add")
738 (set_attr "type" "simd_int_arith")
739 (set_attr "mode" "<MODE>")])
740
741 (define_insn "mul<mode>3"
742 [(set (match_operand:IMSA 0 "register_operand" "=f")
743 (mult:IMSA (match_operand:IMSA 1 "register_operand" "f")
744 (match_operand:IMSA 2 "register_operand" "f")))]
745 "ISA_HAS_MSA"
746 "mulv.<msafmt>\t%w0,%w1,%w2"
747 [(set_attr "type" "simd_mul")
748 (set_attr "mode" "<MODE>")])
749
750 (define_insn "msa_maddv_<msafmt>"
751 [(set (match_operand:IMSA 0 "register_operand" "=f")
752 (plus:IMSA (mult:IMSA (match_operand:IMSA 1 "register_operand" "f")
753 (match_operand:IMSA 2 "register_operand" "f"))
754 (match_operand:IMSA 3 "register_operand" "0")))]
755 "ISA_HAS_MSA"
756 "maddv.<msafmt>\t%w0,%w1,%w2"
757 [(set_attr "type" "simd_mul")
758 (set_attr "mode" "<MODE>")])
759
760 (define_insn "msa_msubv_<msafmt>"
761 [(set (match_operand:IMSA 0 "register_operand" "=f")
762 (minus:IMSA (match_operand:IMSA 1 "register_operand" "0")
763 (mult:IMSA (match_operand:IMSA 2 "register_operand" "f")
764 (match_operand:IMSA 3 "register_operand" "f"))))]
765 "ISA_HAS_MSA"
766 "msubv.<msafmt>\t%w0,%w2,%w3"
767 [(set_attr "type" "simd_mul")
768 (set_attr "mode" "<MODE>")])
769
770 (define_insn "div<mode>3"
771 [(set (match_operand:IMSA 0 "register_operand" "=f")
772 (div:IMSA (match_operand:IMSA 1 "register_operand" "f")
773 (match_operand:IMSA 2 "register_operand" "f")))]
774 "ISA_HAS_MSA"
775 { return mips_msa_output_division ("div_s.<msafmt>\t%w0,%w1,%w2", operands); }
776 [(set_attr "type" "simd_div")
777 (set_attr "mode" "<MODE>")])
778
779 (define_insn "udiv<mode>3"
780 [(set (match_operand:IMSA 0 "register_operand" "=f")
781 (udiv:IMSA (match_operand:IMSA 1 "register_operand" "f")
782 (match_operand:IMSA 2 "register_operand" "f")))]
783 "ISA_HAS_MSA"
784 { return mips_msa_output_division ("div_u.<msafmt>\t%w0,%w1,%w2", operands); }
785 [(set_attr "type" "simd_div")
786 (set_attr "mode" "<MODE>")])
787
788 (define_insn "mod<mode>3"
789 [(set (match_operand:IMSA 0 "register_operand" "=f")
790 (mod:IMSA (match_operand:IMSA 1 "register_operand" "f")
791 (match_operand:IMSA 2 "register_operand" "f")))]
792 "ISA_HAS_MSA"
793 { return mips_msa_output_division ("mod_s.<msafmt>\t%w0,%w1,%w2", operands); }
794 [(set_attr "type" "simd_div")
795 (set_attr "mode" "<MODE>")])
796
797 (define_insn "umod<mode>3"
798 [(set (match_operand:IMSA 0 "register_operand" "=f")
799 (umod:IMSA (match_operand:IMSA 1 "register_operand" "f")
800 (match_operand:IMSA 2 "register_operand" "f")))]
801 "ISA_HAS_MSA"
802 { return mips_msa_output_division ("mod_u.<msafmt>\t%w0,%w1,%w2", operands); }
803 [(set_attr "type" "simd_div")
804 (set_attr "mode" "<MODE>")])
805
806 (define_insn "xor<mode>3"
807 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
808 (xor:IMSA
809 (match_operand:IMSA 1 "register_operand" "f,f,f")
810 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
811 "ISA_HAS_MSA"
812 "@
813 xor.v\t%w0,%w1,%w2
814 bnegi.%v0\t%w0,%w1,%V2
815 xori.b\t%w0,%w1,%B2"
816 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
817 (set_attr "mode" "<MODE>")])
818
819 (define_insn "ior<mode>3"
820 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
821 (ior:IMSA
822 (match_operand:IMSA 1 "register_operand" "f,f,f")
823 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
824 "ISA_HAS_MSA"
825 "@
826 or.v\t%w0,%w1,%w2
827 bseti.%v0\t%w0,%w1,%V2
828 ori.b\t%w0,%w1,%B2"
829 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
830 (set_attr "mode" "<MODE>")])
831
832 (define_insn "and<mode>3"
833 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
834 (and:IMSA
835 (match_operand:IMSA 1 "register_operand" "f,f,f")
836 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
837 "ISA_HAS_MSA"
838 {
839 switch (which_alternative)
840 {
841 case 0:
842 return "and.v\t%w0,%w1,%w2";
843 case 1:
844 {
845 rtx elt0 = CONST_VECTOR_ELT (operands[2], 0);
846 unsigned HOST_WIDE_INT val = ~UINTVAL (elt0);
847 operands[2] = mips_gen_const_int_vector (<MODE>mode, val & (-val));
848 return "bclri.%v0\t%w0,%w1,%V2";
849 }
850 case 2:
851 return "andi.b\t%w0,%w1,%B2";
852 default:
853 gcc_unreachable ();
854 }
855 }
856 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
857 (set_attr "mode" "<MODE>")])
858
859 (define_insn "one_cmpl<mode>2"
860 [(set (match_operand:IMSA 0 "register_operand" "=f")
861 (not:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
862 "ISA_HAS_MSA"
863 "nor.v\t%w0,%w1,%w1"
864 [(set_attr "type" "simd_logic")
865 (set_attr "mode" "TI")])
866
867 (define_insn "vlshr<mode>3"
868 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
869 (lshiftrt:IMSA
870 (match_operand:IMSA 1 "register_operand" "f,f")
871 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
872 "ISA_HAS_MSA"
873 {
874 if (which_alternative == 0)
875 return "srl.<msafmt>\t%w0,%w1,%w2";
876
877 return mips_msa_output_shift_immediate("srli.<msafmt>\t%w0,%w1,%E2", operands);
878 }
879 [(set_attr "type" "simd_shift")
880 (set_attr "mode" "<MODE>")])
881
882 (define_insn "vashr<mode>3"
883 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
884 (ashiftrt:IMSA
885 (match_operand:IMSA 1 "register_operand" "f,f")
886 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
887 "ISA_HAS_MSA"
888 {
889 if (which_alternative == 0)
890 return "sra.<msafmt>\t%w0,%w1,%w2";
891
892 return mips_msa_output_shift_immediate("srai.<msafmt>\t%w0,%w1,%E2", operands);
893 }
894 [(set_attr "type" "simd_shift")
895 (set_attr "mode" "<MODE>")])
896
897 (define_insn "vashl<mode>3"
898 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
899 (ashift:IMSA
900 (match_operand:IMSA 1 "register_operand" "f,f")
901 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
902 "ISA_HAS_MSA"
903 {
904 if (which_alternative == 0)
905 return "sll.<msafmt>\t%w0,%w1,%w2";
906
907 return mips_msa_output_shift_immediate("slli.<msafmt>\t%w0,%w1,%E2", operands);
908 }
909 [(set_attr "type" "simd_shift")
910 (set_attr "mode" "<MODE>")])
911
912 ;; Floating-point operations
913 (define_insn "add<mode>3"
914 [(set (match_operand:FMSA 0 "register_operand" "=f")
915 (plus:FMSA (match_operand:FMSA 1 "register_operand" "f")
916 (match_operand:FMSA 2 "register_operand" "f")))]
917 "ISA_HAS_MSA"
918 "fadd.<msafmt>\t%w0,%w1,%w2"
919 [(set_attr "type" "simd_fadd")
920 (set_attr "mode" "<MODE>")])
921
922 (define_insn "sub<mode>3"
923 [(set (match_operand:FMSA 0 "register_operand" "=f")
924 (minus:FMSA (match_operand:FMSA 1 "register_operand" "f")
925 (match_operand:FMSA 2 "register_operand" "f")))]
926 "ISA_HAS_MSA"
927 "fsub.<msafmt>\t%w0,%w1,%w2"
928 [(set_attr "type" "simd_fadd")
929 (set_attr "mode" "<MODE>")])
930
931 (define_insn "mul<mode>3"
932 [(set (match_operand:FMSA 0 "register_operand" "=f")
933 (mult:FMSA (match_operand:FMSA 1 "register_operand" "f")
934 (match_operand:FMSA 2 "register_operand" "f")))]
935 "ISA_HAS_MSA"
936 "fmul.<msafmt>\t%w0,%w1,%w2"
937 [(set_attr "type" "simd_fmul")
938 (set_attr "mode" "<MODE>")])
939
940 (define_insn "div<mode>3"
941 [(set (match_operand:FMSA 0 "register_operand" "=f")
942 (div:FMSA (match_operand:FMSA 1 "register_operand" "f")
943 (match_operand:FMSA 2 "register_operand" "f")))]
944 "ISA_HAS_MSA"
945 "fdiv.<msafmt>\t%w0,%w1,%w2"
946 [(set_attr "type" "simd_fdiv")
947 (set_attr "mode" "<MODE>")])
948
949 (define_insn "fma<mode>4"
950 [(set (match_operand:FMSA 0 "register_operand" "=f")
951 (fma:FMSA (match_operand:FMSA 1 "register_operand" "f")
952 (match_operand:FMSA 2 "register_operand" "f")
953 (match_operand:FMSA 3 "register_operand" "0")))]
954 "ISA_HAS_MSA"
955 "fmadd.<msafmt>\t%w0,%w1,%w2"
956 [(set_attr "type" "simd_fmadd")
957 (set_attr "mode" "<MODE>")])
958
959 (define_insn "fnma<mode>4"
960 [(set (match_operand:FMSA 0 "register_operand" "=f")
961 (fma:FMSA (neg:FMSA (match_operand:FMSA 1 "register_operand" "f"))
962 (match_operand:FMSA 2 "register_operand" "f")
963 (match_operand:FMSA 3 "register_operand" "0")))]
964 "ISA_HAS_MSA"
965 "fmsub.<msafmt>\t%w0,%w1,%w2"
966 [(set_attr "type" "simd_fmadd")
967 (set_attr "mode" "<MODE>")])
968
969 (define_insn "sqrt<mode>2"
970 [(set (match_operand:FMSA 0 "register_operand" "=f")
971 (sqrt:FMSA (match_operand:FMSA 1 "register_operand" "f")))]
972 "ISA_HAS_MSA"
973 "fsqrt.<msafmt>\t%w0,%w1"
974 [(set_attr "type" "simd_fdiv")
975 (set_attr "mode" "<MODE>")])
976
977 ;; Built-in functions
978 (define_insn "msa_add_a_<msafmt>"
979 [(set (match_operand:IMSA 0 "register_operand" "=f")
980 (plus:IMSA (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
981 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))]
982 "ISA_HAS_MSA"
983 "add_a.<msafmt>\t%w0,%w1,%w2"
984 [(set_attr "type" "simd_int_arith")
985 (set_attr "mode" "<MODE>")])
986
987 (define_insn "msa_adds_a_<msafmt>"
988 [(set (match_operand:IMSA 0 "register_operand" "=f")
989 (ss_plus:IMSA
990 (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
991 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))]
992 "ISA_HAS_MSA"
993 "adds_a.<msafmt>\t%w0,%w1,%w2"
994 [(set_attr "type" "simd_int_arith")
995 (set_attr "mode" "<MODE>")])
996
997 (define_insn "ssadd<mode>3"
998 [(set (match_operand:IMSA 0 "register_operand" "=f")
999 (ss_plus:IMSA (match_operand:IMSA 1 "register_operand" "f")
1000 (match_operand:IMSA 2 "register_operand" "f")))]
1001 "ISA_HAS_MSA"
1002 "adds_s.<msafmt>\t%w0,%w1,%w2"
1003 [(set_attr "type" "simd_int_arith")
1004 (set_attr "mode" "<MODE>")])
1005
1006 (define_insn "usadd<mode>3"
1007 [(set (match_operand:IMSA 0 "register_operand" "=f")
1008 (us_plus:IMSA (match_operand:IMSA 1 "register_operand" "f")
1009 (match_operand:IMSA 2 "register_operand" "f")))]
1010 "ISA_HAS_MSA"
1011 "adds_u.<msafmt>\t%w0,%w1,%w2"
1012 [(set_attr "type" "simd_int_arith")
1013 (set_attr "mode" "<MODE>")])
1014
1015 (define_insn "msa_asub_s_<msafmt>"
1016 [(set (match_operand:IMSA 0 "register_operand" "=f")
1017 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1018 (match_operand:IMSA 2 "register_operand" "f")]
1019 UNSPEC_MSA_ASUB_S))]
1020 "ISA_HAS_MSA"
1021 "asub_s.<msafmt>\t%w0,%w1,%w2"
1022 [(set_attr "type" "simd_int_arith")
1023 (set_attr "mode" "<MODE>")])
1024
1025 (define_insn "msa_asub_u_<msafmt>"
1026 [(set (match_operand:IMSA 0 "register_operand" "=f")
1027 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1028 (match_operand:IMSA 2 "register_operand" "f")]
1029 UNSPEC_MSA_ASUB_U))]
1030 "ISA_HAS_MSA"
1031 "asub_u.<msafmt>\t%w0,%w1,%w2"
1032 [(set_attr "type" "simd_int_arith")
1033 (set_attr "mode" "<MODE>")])
1034
1035 (define_insn "msa_ave_s_<msafmt>"
1036 [(set (match_operand:IMSA 0 "register_operand" "=f")
1037 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1038 (match_operand:IMSA 2 "register_operand" "f")]
1039 UNSPEC_MSA_AVE_S))]
1040 "ISA_HAS_MSA"
1041 "ave_s.<msafmt>\t%w0,%w1,%w2"
1042 [(set_attr "type" "simd_int_arith")
1043 (set_attr "mode" "<MODE>")])
1044
1045 (define_insn "msa_ave_u_<msafmt>"
1046 [(set (match_operand:IMSA 0 "register_operand" "=f")
1047 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1048 (match_operand:IMSA 2 "register_operand" "f")]
1049 UNSPEC_MSA_AVE_U))]
1050 "ISA_HAS_MSA"
1051 "ave_u.<msafmt>\t%w0,%w1,%w2"
1052 [(set_attr "type" "simd_int_arith")
1053 (set_attr "mode" "<MODE>")])
1054
1055 (define_insn "msa_aver_s_<msafmt>"
1056 [(set (match_operand:IMSA 0 "register_operand" "=f")
1057 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1058 (match_operand:IMSA 2 "register_operand" "f")]
1059 UNSPEC_MSA_AVER_S))]
1060 "ISA_HAS_MSA"
1061 "aver_s.<msafmt>\t%w0,%w1,%w2"
1062 [(set_attr "type" "simd_int_arith")
1063 (set_attr "mode" "<MODE>")])
1064
1065 (define_insn "msa_aver_u_<msafmt>"
1066 [(set (match_operand:IMSA 0 "register_operand" "=f")
1067 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1068 (match_operand:IMSA 2 "register_operand" "f")]
1069 UNSPEC_MSA_AVER_U))]
1070 "ISA_HAS_MSA"
1071 "aver_u.<msafmt>\t%w0,%w1,%w2"
1072 [(set_attr "type" "simd_int_arith")
1073 (set_attr "mode" "<MODE>")])
1074
1075 (define_insn "msa_bclr_<msafmt>"
1076 [(set (match_operand:IMSA 0 "register_operand" "=f")
1077 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1078 (match_operand:IMSA 2 "register_operand" "f")]
1079 UNSPEC_MSA_BCLR))]
1080 "ISA_HAS_MSA"
1081 "bclr.<msafmt>\t%w0,%w1,%w2"
1082 [(set_attr "type" "simd_bit")
1083 (set_attr "mode" "<MODE>")])
1084
1085 (define_insn "msa_bclri_<msafmt>"
1086 [(set (match_operand:IMSA 0 "register_operand" "=f")
1087 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1088 (match_operand 2 "const_<bitimm>_operand" "")]
1089 UNSPEC_MSA_BCLRI))]
1090 "ISA_HAS_MSA"
1091 "bclri.<msafmt>\t%w0,%w1,%2"
1092 [(set_attr "type" "simd_bit")
1093 (set_attr "mode" "<MODE>")])
1094
1095 (define_insn "msa_binsl_<msafmt>"
1096 [(set (match_operand:IMSA 0 "register_operand" "=f")
1097 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1098 (match_operand:IMSA 2 "register_operand" "f")
1099 (match_operand:IMSA 3 "register_operand" "f")]
1100 UNSPEC_MSA_BINSL))]
1101 "ISA_HAS_MSA"
1102 "binsl.<msafmt>\t%w0,%w2,%w3"
1103 [(set_attr "type" "simd_bitins")
1104 (set_attr "mode" "<MODE>")])
1105
1106 (define_insn "msa_binsli_<msafmt>"
1107 [(set (match_operand:IMSA 0 "register_operand" "=f")
1108 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1109 (match_operand:IMSA 2 "register_operand" "f")
1110 (match_operand 3 "const_<bitimm>_operand" "")]
1111 UNSPEC_MSA_BINSLI))]
1112 "ISA_HAS_MSA"
1113 "binsli.<msafmt>\t%w0,%w2,%3"
1114 [(set_attr "type" "simd_bitins")
1115 (set_attr "mode" "<MODE>")])
1116
1117 (define_insn "msa_binsr_<msafmt>"
1118 [(set (match_operand:IMSA 0 "register_operand" "=f")
1119 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1120 (match_operand:IMSA 2 "register_operand" "f")
1121 (match_operand:IMSA 3 "register_operand" "f")]
1122 UNSPEC_MSA_BINSR))]
1123 "ISA_HAS_MSA"
1124 "binsr.<msafmt>\t%w0,%w2,%w3"
1125 [(set_attr "type" "simd_bitins")
1126 (set_attr "mode" "<MODE>")])
1127
1128 (define_insn "msa_binsri_<msafmt>"
1129 [(set (match_operand:IMSA 0 "register_operand" "=f")
1130 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1131 (match_operand:IMSA 2 "register_operand" "f")
1132 (match_operand 3 "const_<bitimm>_operand" "")]
1133 UNSPEC_MSA_BINSRI))]
1134 "ISA_HAS_MSA"
1135 "binsri.<msafmt>\t%w0,%w2,%3"
1136 [(set_attr "type" "simd_bitins")
1137 (set_attr "mode" "<MODE>")])
1138
1139 (define_insn "msa_bmnz_<msafmt>"
1140 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1141 (ior:IMSA (and:IMSA (match_operand:IMSA 2 "register_operand" "f,f")
1142 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))
1143 (and:IMSA (not:IMSA (match_dup 3))
1144 (match_operand:IMSA 1 "register_operand" "0,0"))))]
1145 "ISA_HAS_MSA"
1146 "@
1147 bmnz.v\t%w0,%w2,%w3
1148 bmnzi.b\t%w0,%w2,%B3"
1149 [(set_attr "type" "simd_bitmov")
1150 (set_attr "mode" "<MODE>")])
1151
1152 (define_insn "msa_bmz_<msafmt>"
1153 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1154 (ior:IMSA (and:IMSA (not:IMSA
1155 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))
1156 (match_operand:IMSA 2 "register_operand" "f,f"))
1157 (and:IMSA (match_operand:IMSA 1 "register_operand" "0,0")
1158 (match_dup 3))))]
1159 "ISA_HAS_MSA"
1160 "@
1161 bmz.v\t%w0,%w2,%w3
1162 bmzi.b\t%w0,%w2,%B3"
1163 [(set_attr "type" "simd_bitmov")
1164 (set_attr "mode" "<MODE>")])
1165
1166 (define_insn "msa_bneg_<msafmt>"
1167 [(set (match_operand:IMSA 0 "register_operand" "=f")
1168 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1169 (match_operand:IMSA 2 "register_operand" "f")]
1170 UNSPEC_MSA_BNEG))]
1171 "ISA_HAS_MSA"
1172 "bneg.<msafmt>\t%w0,%w1,%w2"
1173 [(set_attr "type" "simd_bit")
1174 (set_attr "mode" "<MODE>")])
1175
1176 (define_insn "msa_bnegi_<msafmt>"
1177 [(set (match_operand:IMSA 0 "register_operand" "=f")
1178 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1179 (match_operand 2 "const_msa_branch_operand" "")]
1180 UNSPEC_MSA_BNEGI))]
1181 "ISA_HAS_MSA"
1182 "bnegi.<msafmt>\t%w0,%w1,%2"
1183 [(set_attr "type" "simd_bit")
1184 (set_attr "mode" "<MODE>")])
1185
1186 (define_insn "msa_bsel_<msafmt>"
1187 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1188 (ior:IMSA (and:IMSA (not:IMSA
1189 (match_operand:IMSA 1 "register_operand" "0,0"))
1190 (match_operand:IMSA 2 "register_operand" "f,f"))
1191 (and:IMSA (match_dup 1)
1192 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))))]
1193 "ISA_HAS_MSA"
1194 "@
1195 bsel.v\t%w0,%w2,%w3
1196 bseli.b\t%w0,%w2,%B3"
1197 [(set_attr "type" "simd_bitmov")
1198 (set_attr "mode" "<MODE>")])
1199
1200 (define_insn "msa_bset_<msafmt>"
1201 [(set (match_operand:IMSA 0 "register_operand" "=f")
1202 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1203 (match_operand:IMSA 2 "register_operand" "f")]
1204 UNSPEC_MSA_BSET))]
1205 "ISA_HAS_MSA"
1206 "bset.<msafmt>\t%w0,%w1,%w2"
1207 [(set_attr "type" "simd_bit")
1208 (set_attr "mode" "<MODE>")])
1209
1210 (define_insn "msa_bseti_<msafmt>"
1211 [(set (match_operand:IMSA 0 "register_operand" "=f")
1212 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1213 (match_operand 2 "const_<bitimm>_operand" "")]
1214 UNSPEC_MSA_BSETI))]
1215 "ISA_HAS_MSA"
1216 "bseti.<msafmt>\t%w0,%w1,%2"
1217 [(set_attr "type" "simd_bit")
1218 (set_attr "mode" "<MODE>")])
1219
1220 (define_code_iterator ICC [eq le leu lt ltu])
1221
1222 (define_code_attr icc
1223 [(eq "eq")
1224 (le "le_s")
1225 (leu "le_u")
1226 (lt "lt_s")
1227 (ltu "lt_u")])
1228
1229 (define_code_attr icci
1230 [(eq "eqi")
1231 (le "lei_s")
1232 (leu "lei_u")
1233 (lt "lti_s")
1234 (ltu "lti_u")])
1235
1236 (define_code_attr cmpi
1237 [(eq "s")
1238 (le "s")
1239 (leu "u")
1240 (lt "s")
1241 (ltu "u")])
1242
1243 (define_insn "msa_c<ICC:icc>_<IMSA:msafmt>"
1244 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1245 (ICC:IMSA
1246 (match_operand:IMSA 1 "register_operand" "f,f")
1247 (match_operand:IMSA 2 "reg_or_vector_same_<ICC:cmpi>imm5_operand" "f,U<ICC:cmpi>v5")))]
1248 "ISA_HAS_MSA"
1249 "@
1250 c<ICC:icc>.<IMSA:msafmt>\t%w0,%w1,%w2
1251 c<ICC:icci>.<IMSA:msafmt>\t%w0,%w1,%E2"
1252 [(set_attr "type" "simd_int_arith")
1253 (set_attr "mode" "<MODE>")])
1254
1255 (define_insn "msa_dotp_<su>_d"
1256 [(set (match_operand:V2DI 0 "register_operand" "=f")
1257 (plus:V2DI
1258 (mult:V2DI
1259 (any_extend:V2DI
1260 (vec_select:V2SI
1261 (match_operand:V4SI 1 "register_operand" "%f")
1262 (parallel [(const_int 0) (const_int 2)])))
1263 (any_extend:V2DI
1264 (vec_select:V2SI
1265 (match_operand:V4SI 2 "register_operand" "f")
1266 (parallel [(const_int 0) (const_int 2)]))))
1267 (mult:V2DI
1268 (any_extend:V2DI
1269 (vec_select:V2SI (match_dup 1)
1270 (parallel [(const_int 1) (const_int 3)])))
1271 (any_extend:V2DI
1272 (vec_select:V2SI (match_dup 2)
1273 (parallel [(const_int 1) (const_int 3)]))))))]
1274 "ISA_HAS_MSA"
1275 "dotp_<su>.d\t%w0,%w1,%w2"
1276 [(set_attr "type" "simd_mul")
1277 (set_attr "mode" "V2DI")])
1278
1279 (define_insn "msa_dotp_<su>_w"
1280 [(set (match_operand:V4SI 0 "register_operand" "=f")
1281 (plus:V4SI
1282 (mult:V4SI
1283 (any_extend:V4SI
1284 (vec_select:V4HI
1285 (match_operand:V8HI 1 "register_operand" "%f")
1286 (parallel [(const_int 0) (const_int 2)
1287 (const_int 4) (const_int 6)])))
1288 (any_extend:V4SI
1289 (vec_select:V4HI
1290 (match_operand:V8HI 2 "register_operand" "f")
1291 (parallel [(const_int 0) (const_int 2)
1292 (const_int 4) (const_int 6)]))))
1293 (mult:V4SI
1294 (any_extend:V4SI
1295 (vec_select:V4HI (match_dup 1)
1296 (parallel [(const_int 1) (const_int 3)
1297 (const_int 5) (const_int 7)])))
1298 (any_extend:V4SI
1299 (vec_select:V4HI (match_dup 2)
1300 (parallel [(const_int 1) (const_int 3)
1301 (const_int 5) (const_int 7)]))))))]
1302 "ISA_HAS_MSA"
1303 "dotp_<su>.w\t%w0,%w1,%w2"
1304 [(set_attr "type" "simd_mul")
1305 (set_attr "mode" "V4SI")])
1306
1307 (define_insn "msa_dotp_<su>_h"
1308 [(set (match_operand:V8HI 0 "register_operand" "=f")
1309 (plus:V8HI
1310 (mult:V8HI
1311 (any_extend:V8HI
1312 (vec_select:V8QI
1313 (match_operand:V16QI 1 "register_operand" "%f")
1314 (parallel [(const_int 0) (const_int 2)
1315 (const_int 4) (const_int 6)
1316 (const_int 8) (const_int 10)
1317 (const_int 12) (const_int 14)])))
1318 (any_extend:V8HI
1319 (vec_select:V8QI
1320 (match_operand:V16QI 2 "register_operand" "f")
1321 (parallel [(const_int 0) (const_int 2)
1322 (const_int 4) (const_int 6)
1323 (const_int 8) (const_int 10)
1324 (const_int 12) (const_int 14)]))))
1325 (mult:V8HI
1326 (any_extend:V8HI
1327 (vec_select:V8QI (match_dup 1)
1328 (parallel [(const_int 1) (const_int 3)
1329 (const_int 5) (const_int 7)
1330 (const_int 9) (const_int 11)
1331 (const_int 13) (const_int 15)])))
1332 (any_extend:V8HI
1333 (vec_select:V8QI (match_dup 2)
1334 (parallel [(const_int 1) (const_int 3)
1335 (const_int 5) (const_int 7)
1336 (const_int 9) (const_int 11)
1337 (const_int 13) (const_int 15)]))))))]
1338 "ISA_HAS_MSA"
1339 "dotp_<su>.h\t%w0,%w1,%w2"
1340 [(set_attr "type" "simd_mul")
1341 (set_attr "mode" "V8HI")])
1342
1343 (define_insn "msa_dpadd_<su>_d"
1344 [(set (match_operand:V2DI 0 "register_operand" "=f")
1345 (plus:V2DI
1346 (plus:V2DI
1347 (mult:V2DI
1348 (any_extend:V2DI
1349 (vec_select:V2SI
1350 (match_operand:V4SI 2 "register_operand" "%f")
1351 (parallel [(const_int 0) (const_int 2)])))
1352 (any_extend:V2DI
1353 (vec_select:V2SI
1354 (match_operand:V4SI 3 "register_operand" "f")
1355 (parallel [(const_int 0) (const_int 2)]))))
1356 (mult:V2DI
1357 (any_extend:V2DI
1358 (vec_select:V2SI (match_dup 2)
1359 (parallel [(const_int 1) (const_int 3)])))
1360 (any_extend:V2DI
1361 (vec_select:V2SI (match_dup 3)
1362 (parallel [(const_int 1) (const_int 3)])))))
1363 (match_operand:V2DI 1 "register_operand" "0")))]
1364 "ISA_HAS_MSA"
1365 "dpadd_<su>.d\t%w0,%w2,%w3"
1366 [(set_attr "type" "simd_mul")
1367 (set_attr "mode" "V2DI")])
1368
1369 (define_insn "msa_dpadd_<su>_w"
1370 [(set (match_operand:V4SI 0 "register_operand" "=f")
1371 (plus:V4SI
1372 (plus:V4SI
1373 (mult:V4SI
1374 (any_extend:V4SI
1375 (vec_select:V4HI
1376 (match_operand:V8HI 2 "register_operand" "%f")
1377 (parallel [(const_int 0) (const_int 2)
1378 (const_int 4) (const_int 6)])))
1379 (any_extend:V4SI
1380 (vec_select:V4HI
1381 (match_operand:V8HI 3 "register_operand" "f")
1382 (parallel [(const_int 0) (const_int 2)
1383 (const_int 4) (const_int 6)]))))
1384 (mult:V4SI
1385 (any_extend:V4SI
1386 (vec_select:V4HI (match_dup 2)
1387 (parallel [(const_int 1) (const_int 3)
1388 (const_int 5) (const_int 7)])))
1389 (any_extend:V4SI
1390 (vec_select:V4HI (match_dup 3)
1391 (parallel [(const_int 1) (const_int 3)
1392 (const_int 5) (const_int 7)])))))
1393 (match_operand:V4SI 1 "register_operand" "0")))]
1394 "ISA_HAS_MSA"
1395 "dpadd_<su>.w\t%w0,%w2,%w3"
1396 [(set_attr "type" "simd_mul")
1397 (set_attr "mode" "V4SI")])
1398
1399 (define_insn "msa_dpadd_<su>_h"
1400 [(set (match_operand:V8HI 0 "register_operand" "=f")
1401 (plus:V8HI
1402 (plus:V8HI
1403 (mult:V8HI
1404 (any_extend:V8HI
1405 (vec_select:V8QI
1406 (match_operand:V16QI 2 "register_operand" "%f")
1407 (parallel [(const_int 0) (const_int 2)
1408 (const_int 4) (const_int 6)
1409 (const_int 8) (const_int 10)
1410 (const_int 12) (const_int 14)])))
1411 (any_extend:V8HI
1412 (vec_select:V8QI
1413 (match_operand:V16QI 3 "register_operand" "f")
1414 (parallel [(const_int 0) (const_int 2)
1415 (const_int 4) (const_int 6)
1416 (const_int 8) (const_int 10)
1417 (const_int 12) (const_int 14)]))))
1418 (mult:V8HI
1419 (any_extend:V8HI
1420 (vec_select:V8QI (match_dup 2)
1421 (parallel [(const_int 1) (const_int 3)
1422 (const_int 5) (const_int 7)
1423 (const_int 9) (const_int 11)
1424 (const_int 13) (const_int 15)])))
1425 (any_extend:V8HI
1426 (vec_select:V8QI (match_dup 3)
1427 (parallel [(const_int 1) (const_int 3)
1428 (const_int 5) (const_int 7)
1429 (const_int 9) (const_int 11)
1430 (const_int 13) (const_int 15)])))))
1431 (match_operand:V8HI 1 "register_operand" "0")))]
1432 "ISA_HAS_MSA"
1433 "dpadd_<su>.h\t%w0,%w2,%w3"
1434 [(set_attr "type" "simd_mul")
1435 (set_attr "mode" "V8HI")])
1436
1437 (define_insn "msa_dpsub_<su>_d"
1438 [(set (match_operand:V2DI 0 "register_operand" "=f")
1439 (minus:V2DI
1440 (match_operand:V2DI 1 "register_operand" "0")
1441 (plus:V2DI
1442 (mult:V2DI
1443 (any_extend:V2DI
1444 (vec_select:V2SI
1445 (match_operand:V4SI 2 "register_operand" "%f")
1446 (parallel [(const_int 0) (const_int 2)])))
1447 (any_extend:V2DI
1448 (vec_select:V2SI
1449 (match_operand:V4SI 3 "register_operand" "f")
1450 (parallel [(const_int 0) (const_int 2)]))))
1451 (mult:V2DI
1452 (any_extend:V2DI
1453 (vec_select:V2SI (match_dup 2)
1454 (parallel [(const_int 1) (const_int 3)])))
1455 (any_extend:V2DI
1456 (vec_select:V2SI (match_dup 3)
1457 (parallel [(const_int 1) (const_int 3)])))))))]
1458 "ISA_HAS_MSA"
1459 "dpsub_<su>.d\t%w0,%w2,%w3"
1460 [(set_attr "type" "simd_mul")
1461 (set_attr "mode" "V2DI")])
1462
1463 (define_insn "msa_dpsub_<su>_w"
1464 [(set (match_operand:V4SI 0 "register_operand" "=f")
1465 (minus:V4SI
1466 (match_operand:V4SI 1 "register_operand" "0")
1467 (plus:V4SI
1468 (mult:V4SI
1469 (any_extend:V4SI
1470 (vec_select:V4HI
1471 (match_operand:V8HI 2 "register_operand" "%f")
1472 (parallel [(const_int 0) (const_int 2)
1473 (const_int 4) (const_int 6)])))
1474 (any_extend:V4SI
1475 (vec_select:V4HI
1476 (match_operand:V8HI 3 "register_operand" "f")
1477 (parallel [(const_int 0) (const_int 2)
1478 (const_int 4) (const_int 6)]))))
1479 (mult:V4SI
1480 (any_extend:V4SI
1481 (vec_select:V4HI (match_dup 2)
1482 (parallel [(const_int 1) (const_int 3)
1483 (const_int 5) (const_int 7)])))
1484 (any_extend:V4SI
1485 (vec_select:V4HI (match_dup 3)
1486 (parallel [(const_int 1) (const_int 3)
1487 (const_int 5) (const_int 7)])))))))]
1488 "ISA_HAS_MSA"
1489 "dpsub_<su>.w\t%w0,%w2,%w3"
1490 [(set_attr "type" "simd_mul")
1491 (set_attr "mode" "V4SI")])
1492
1493 (define_insn "msa_dpsub_<su>_h"
1494 [(set (match_operand:V8HI 0 "register_operand" "=f")
1495 (minus:V8HI
1496 (match_operand:V8HI 1 "register_operand" "0")
1497 (plus:V8HI
1498 (mult:V8HI
1499 (any_extend:V8HI
1500 (vec_select:V8QI
1501 (match_operand:V16QI 2 "register_operand" "%f")
1502 (parallel [(const_int 0) (const_int 2)
1503 (const_int 4) (const_int 6)
1504 (const_int 8) (const_int 10)
1505 (const_int 12) (const_int 14)])))
1506 (any_extend:V8HI
1507 (vec_select:V8QI
1508 (match_operand:V16QI 3 "register_operand" "f")
1509 (parallel [(const_int 0) (const_int 2)
1510 (const_int 4) (const_int 6)
1511 (const_int 8) (const_int 10)
1512 (const_int 12) (const_int 14)]))))
1513 (mult:V8HI
1514 (any_extend:V8HI
1515 (vec_select:V8QI (match_dup 2)
1516 (parallel [(const_int 1) (const_int 3)
1517 (const_int 5) (const_int 7)
1518 (const_int 9) (const_int 11)
1519 (const_int 13) (const_int 15)])))
1520 (any_extend:V8HI
1521 (vec_select:V8QI (match_dup 3)
1522 (parallel [(const_int 1) (const_int 3)
1523 (const_int 5) (const_int 7)
1524 (const_int 9) (const_int 11)
1525 (const_int 13) (const_int 15)])))))))]
1526 "ISA_HAS_MSA"
1527 "dpsub_<su>.h\t%w0,%w2,%w3"
1528 [(set_attr "type" "simd_mul")
1529 (set_attr "mode" "V8HI")])
1530
1531 (define_insn "msa_fclass_<msafmt>"
1532 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1533 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1534 UNSPEC_MSA_FCLASS))]
1535 "ISA_HAS_MSA"
1536 "fclass.<msafmt>\t%w0,%w1"
1537 [(set_attr "type" "simd_fclass")
1538 (set_attr "mode" "<MODE>")])
1539
1540 (define_insn "msa_fcaf_<msafmt>"
1541 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1542 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1543 (match_operand:FMSA 2 "register_operand" "f")]
1544 UNSPEC_MSA_FCAF))]
1545 "ISA_HAS_MSA"
1546 "fcaf.<msafmt>\t%w0,%w1,%w2"
1547 [(set_attr "type" "simd_fcmp")
1548 (set_attr "mode" "<MODE>")])
1549
1550 (define_insn "msa_fcune_<FMSA:msafmt>"
1551 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1552 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1553 (match_operand:FMSA 2 "register_operand" "f")]
1554 UNSPEC_MSA_FCUNE))]
1555 "ISA_HAS_MSA"
1556 "fcune.<FMSA:msafmt>\t%w0,%w1,%w2"
1557 [(set_attr "type" "simd_fcmp")
1558 (set_attr "mode" "<MODE>")])
1559
1560 (define_code_iterator FCC [unordered ordered eq ne le lt uneq unle unlt])
1561
1562 (define_code_attr fcc
1563 [(unordered "fcun")
1564 (ordered "fcor")
1565 (eq "fceq")
1566 (ne "fcne")
1567 (uneq "fcueq")
1568 (unle "fcule")
1569 (unlt "fcult")
1570 (le "fcle")
1571 (lt "fclt")])
1572
1573 (define_int_iterator FSC_UNS [UNSPEC_MSA_FSAF UNSPEC_MSA_FSUN UNSPEC_MSA_FSOR
1574 UNSPEC_MSA_FSEQ UNSPEC_MSA_FSNE UNSPEC_MSA_FSUEQ
1575 UNSPEC_MSA_FSUNE UNSPEC_MSA_FSULE UNSPEC_MSA_FSULT
1576 UNSPEC_MSA_FSLE UNSPEC_MSA_FSLT])
1577
1578 (define_int_attr fsc
1579 [(UNSPEC_MSA_FSAF "fsaf")
1580 (UNSPEC_MSA_FSUN "fsun")
1581 (UNSPEC_MSA_FSOR "fsor")
1582 (UNSPEC_MSA_FSEQ "fseq")
1583 (UNSPEC_MSA_FSNE "fsne")
1584 (UNSPEC_MSA_FSUEQ "fsueq")
1585 (UNSPEC_MSA_FSUNE "fsune")
1586 (UNSPEC_MSA_FSULE "fsule")
1587 (UNSPEC_MSA_FSULT "fsult")
1588 (UNSPEC_MSA_FSLE "fsle")
1589 (UNSPEC_MSA_FSLT "fslt")])
1590
1591 (define_insn "msa_<FCC:fcc>_<FMSA:msafmt>"
1592 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1593 (FCC:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")
1594 (match_operand:FMSA 2 "register_operand" "f")))]
1595 "ISA_HAS_MSA"
1596 "<FCC:fcc>.<FMSA:msafmt>\t%w0,%w1,%w2"
1597 [(set_attr "type" "simd_fcmp")
1598 (set_attr "mode" "<MODE>")])
1599
1600 (define_insn "msa_<fsc>_<FMSA:msafmt>"
1601 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1602 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1603 (match_operand:FMSA 2 "register_operand" "f")]
1604 FSC_UNS))]
1605 "ISA_HAS_MSA"
1606 "<fsc>.<FMSA:msafmt>\t%w0,%w1,%w2"
1607 [(set_attr "type" "simd_fcmp")
1608 (set_attr "mode" "<MODE>")])
1609
1610 (define_insn "msa_fexp2_<msafmt>"
1611 [(set (match_operand:FMSA 0 "register_operand" "=f")
1612 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")
1613 (match_operand:<VIMODE> 2 "register_operand" "f")]
1614 UNSPEC_MSA_FEXP2))]
1615 "ISA_HAS_MSA"
1616 "fexp2.<msafmt>\t%w0,%w1,%w2"
1617 [(set_attr "type" "simd_fexp2")
1618 (set_attr "mode" "<MODE>")])
1619
1620 (define_mode_attr fint
1621 [(V4SF "v4si")
1622 (V2DF "v2di")])
1623
1624 (define_mode_attr FQ
1625 [(V4SF "V8HI")
1626 (V2DF "V4SI")])
1627
1628 (define_mode_attr FINTCNV
1629 [(V4SF "I2S")
1630 (V2DF "I2D")])
1631
1632 (define_mode_attr FINTCNV_2
1633 [(V4SF "S2I")
1634 (V2DF "D2I")])
1635
1636 (define_insn "float<fint><FMSA:mode>2"
1637 [(set (match_operand:FMSA 0 "register_operand" "=f")
1638 (float:FMSA (match_operand:<VIMODE> 1 "register_operand" "f")))]
1639 "ISA_HAS_MSA"
1640 "ffint_s.<msafmt>\t%w0,%w1"
1641 [(set_attr "type" "simd_fcvt")
1642 (set_attr "cnv_mode" "<FINTCNV>")
1643 (set_attr "mode" "<MODE>")])
1644
1645 (define_insn "floatuns<fint><FMSA:mode>2"
1646 [(set (match_operand:FMSA 0 "register_operand" "=f")
1647 (unsigned_float:FMSA
1648 (match_operand:<VIMODE> 1 "register_operand" "f")))]
1649 "ISA_HAS_MSA"
1650 "ffint_u.<msafmt>\t%w0,%w1"
1651 [(set_attr "type" "simd_fcvt")
1652 (set_attr "cnv_mode" "<FINTCNV>")
1653 (set_attr "mode" "<MODE>")])
1654
1655 (define_mode_attr FFQ
1656 [(V4SF "V8HI")
1657 (V2DF "V4SI")])
1658
1659 (define_insn "msa_ffql_<msafmt>"
1660 [(set (match_operand:FMSA 0 "register_operand" "=f")
1661 (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")]
1662 UNSPEC_MSA_FFQL))]
1663 "ISA_HAS_MSA"
1664 "ffql.<msafmt>\t%w0,%w1"
1665 [(set_attr "type" "simd_fcvt")
1666 (set_attr "cnv_mode" "<FINTCNV>")
1667 (set_attr "mode" "<MODE>")])
1668
1669 (define_insn "msa_ffqr_<msafmt>"
1670 [(set (match_operand:FMSA 0 "register_operand" "=f")
1671 (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")]
1672 UNSPEC_MSA_FFQR))]
1673 "ISA_HAS_MSA"
1674 "ffqr.<msafmt>\t%w0,%w1"
1675 [(set_attr "type" "simd_fcvt")
1676 (set_attr "cnv_mode" "<FINTCNV>")
1677 (set_attr "mode" "<MODE>")])
1678
1679 (define_insn "msa_fill_<msafmt_f>"
1680 [(set (match_operand:MSA 0 "register_operand" "=f,f")
1681 (vec_duplicate:MSA
1682 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "d,J")))]
1683 "ISA_HAS_MSA"
1684 {
1685 if (which_alternative == 1)
1686 return "ldi.<msafmt>\t%w0,0";
1687
1688 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
1689 return "#";
1690 else
1691 return "fill.<msafmt>\t%w0,%z1";
1692 }
1693 [(set_attr "type" "simd_fill")
1694 (set_attr "mode" "<MODE>")])
1695
1696 (define_split
1697 [(set (match_operand:MSA_D 0 "register_operand")
1698 (vec_duplicate:MSA_D
1699 (match_operand:<UNITMODE> 1 "register_operand")))]
1700 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
1701 [(const_int 0)]
1702 {
1703 mips_split_msa_fill_d (operands[0], operands[1]);
1704 DONE;
1705 })
1706
1707 (define_insn "msa_flog2_<msafmt>"
1708 [(set (match_operand:FMSA 0 "register_operand" "=f")
1709 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1710 UNSPEC_MSA_FLOG2))]
1711 "ISA_HAS_MSA"
1712 "flog2.<msafmt>\t%w0,%w1"
1713 [(set_attr "type" "simd_flog2")
1714 (set_attr "mode" "<MODE>")])
1715
1716 (define_insn "smax<mode>3"
1717 [(set (match_operand:FMSA 0 "register_operand" "=f")
1718 (smax:FMSA (match_operand:FMSA 1 "register_operand" "f")
1719 (match_operand:FMSA 2 "register_operand" "f")))]
1720 "ISA_HAS_MSA"
1721 "fmax.<msafmt>\t%w0,%w1,%w2"
1722 [(set_attr "type" "simd_fminmax")
1723 (set_attr "mode" "<MODE>")])
1724
1725 (define_insn "msa_fmax_a_<msafmt>"
1726 [(set (match_operand:FMSA 0 "register_operand" "=f")
1727 (if_then_else:FMSA
1728 (gt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
1729 (abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
1730 (match_dup 1)
1731 (match_dup 2)))]
1732 "ISA_HAS_MSA"
1733 "fmax_a.<msafmt>\t%w0,%w1,%w2"
1734 [(set_attr "type" "simd_fminmax")
1735 (set_attr "mode" "<MODE>")])
1736
1737 (define_insn "smin<mode>3"
1738 [(set (match_operand:FMSA 0 "register_operand" "=f")
1739 (smin:FMSA (match_operand:FMSA 1 "register_operand" "f")
1740 (match_operand:FMSA 2 "register_operand" "f")))]
1741 "ISA_HAS_MSA"
1742 "fmin.<msafmt>\t%w0,%w1,%w2"
1743 [(set_attr "type" "simd_fminmax")
1744 (set_attr "mode" "<MODE>")])
1745
1746 (define_insn "msa_fmin_a_<msafmt>"
1747 [(set (match_operand:FMSA 0 "register_operand" "=f")
1748 (if_then_else:FMSA
1749 (lt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
1750 (abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
1751 (match_dup 1)
1752 (match_dup 2)))]
1753 "ISA_HAS_MSA"
1754 "fmin_a.<msafmt>\t%w0,%w1,%w2"
1755 [(set_attr "type" "simd_fminmax")
1756 (set_attr "mode" "<MODE>")])
1757
1758 (define_insn "msa_frcp_<msafmt>"
1759 [(set (match_operand:FMSA 0 "register_operand" "=f")
1760 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1761 UNSPEC_MSA_FRCP))]
1762 "ISA_HAS_MSA"
1763 "frcp.<msafmt>\t%w0,%w1"
1764 [(set_attr "type" "simd_fdiv")
1765 (set_attr "mode" "<MODE>")])
1766
1767 (define_insn "msa_frint_<msafmt>"
1768 [(set (match_operand:FMSA 0 "register_operand" "=f")
1769 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1770 UNSPEC_MSA_FRINT))]
1771 "ISA_HAS_MSA"
1772 "frint.<msafmt>\t%w0,%w1"
1773 [(set_attr "type" "simd_fcvt")
1774 (set_attr "mode" "<MODE>")])
1775
1776 (define_insn "msa_frsqrt_<msafmt>"
1777 [(set (match_operand:FMSA 0 "register_operand" "=f")
1778 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1779 UNSPEC_MSA_FRSQRT))]
1780 "ISA_HAS_MSA"
1781 "frsqrt.<msafmt>\t%w0,%w1"
1782 [(set_attr "type" "simd_fdiv")
1783 (set_attr "mode" "<MODE>")])
1784
1785 (define_insn "msa_ftint_s_<msafmt>"
1786 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1787 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1788 UNSPEC_MSA_FTINT_S))]
1789 "ISA_HAS_MSA"
1790 "ftint_s.<msafmt>\t%w0,%w1"
1791 [(set_attr "type" "simd_fcvt")
1792 (set_attr "cnv_mode" "<FINTCNV_2>")
1793 (set_attr "mode" "<MODE>")])
1794
1795 (define_insn "msa_ftint_u_<msafmt>"
1796 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1797 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1798 UNSPEC_MSA_FTINT_U))]
1799 "ISA_HAS_MSA"
1800 "ftint_u.<msafmt>\t%w0,%w1"
1801 [(set_attr "type" "simd_fcvt")
1802 (set_attr "cnv_mode" "<FINTCNV_2>")
1803 (set_attr "mode" "<MODE>")])
1804
1805 (define_insn "fix_trunc<FMSA:mode><mode_i>2"
1806 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1807 (fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))]
1808 "ISA_HAS_MSA"
1809 "ftrunc_s.<msafmt>\t%w0,%w1"
1810 [(set_attr "type" "simd_fcvt")
1811 (set_attr "cnv_mode" "<FINTCNV_2>")
1812 (set_attr "mode" "<MODE>")])
1813
1814 (define_insn "fixuns_trunc<FMSA:mode><mode_i>2"
1815 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1816 (unsigned_fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))]
1817 "ISA_HAS_MSA"
1818 "ftrunc_u.<msafmt>\t%w0,%w1"
1819 [(set_attr "type" "simd_fcvt")
1820 (set_attr "cnv_mode" "<FINTCNV_2>")
1821 (set_attr "mode" "<MODE>")])
1822
1823 (define_insn "msa_ftq_h"
1824 [(set (match_operand:V8HI 0 "register_operand" "=f")
1825 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f")
1826 (match_operand:V4SF 2 "register_operand" "f")]
1827 UNSPEC_MSA_FTQ))]
1828 "ISA_HAS_MSA"
1829 "ftq.h\t%w0,%w1,%w2"
1830 [(set_attr "type" "simd_fcvt")
1831 (set_attr "cnv_mode" "S2I")
1832 (set_attr "mode" "V4SF")])
1833
1834 (define_insn "msa_ftq_w"
1835 [(set (match_operand:V4SI 0 "register_operand" "=f")
1836 (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f")
1837 (match_operand:V2DF 2 "register_operand" "f")]
1838 UNSPEC_MSA_FTQ))]
1839 "ISA_HAS_MSA"
1840 "ftq.w\t%w0,%w1,%w2"
1841 [(set_attr "type" "simd_fcvt")
1842 (set_attr "cnv_mode" "D2I")
1843 (set_attr "mode" "V2DF")])
1844
1845 (define_insn "msa_h<optab>_<su>_h"
1846 [(set (match_operand:V8HI 0 "register_operand" "=f")
1847 (addsub:V8HI
1848 (any_extend:V8HI
1849 (vec_select:V8QI
1850 (match_operand:V16QI 1 "register_operand" "f")
1851 (parallel [(const_int 1) (const_int 3)
1852 (const_int 5) (const_int 7)
1853 (const_int 9) (const_int 11)
1854 (const_int 13) (const_int 15)])))
1855 (any_extend:V8HI
1856 (vec_select:V8QI
1857 (match_operand:V16QI 2 "register_operand" "f")
1858 (parallel [(const_int 0) (const_int 2)
1859 (const_int 4) (const_int 6)
1860 (const_int 8) (const_int 10)
1861 (const_int 12) (const_int 14)])))))]
1862 "ISA_HAS_MSA"
1863 "h<optab>_<su>.h\t%w0,%w1,%w2"
1864 [(set_attr "type" "simd_int_arith")
1865 (set_attr "mode" "V8HI")])
1866
1867 (define_insn "msa_h<optab>_<su>_w"
1868 [(set (match_operand:V4SI 0 "register_operand" "=f")
1869 (addsub:V4SI
1870 (any_extend:V4SI
1871 (vec_select:V4HI
1872 (match_operand:V8HI 1 "register_operand" "f")
1873 (parallel [(const_int 1) (const_int 3)
1874 (const_int 5) (const_int 7)])))
1875 (any_extend:V4SI
1876 (vec_select:V4HI
1877 (match_operand:V8HI 2 "register_operand" "f")
1878 (parallel [(const_int 0) (const_int 2)
1879 (const_int 4) (const_int 6)])))))]
1880 "ISA_HAS_MSA"
1881 "h<optab>_<su>.w\t%w0,%w1,%w2"
1882 [(set_attr "type" "simd_int_arith")
1883 (set_attr "mode" "V4SI")])
1884
1885 (define_insn "msa_h<optab>_<su>_d"
1886 [(set (match_operand:V2DI 0 "register_operand" "=f")
1887 (addsub:V2DI
1888 (any_extend:V2DI
1889 (vec_select:V2SI
1890 (match_operand:V4SI 1 "register_operand" "f")
1891 (parallel [(const_int 1) (const_int 3)])))
1892 (any_extend:V2DI
1893 (vec_select:V2SI
1894 (match_operand:V4SI 2 "register_operand" "f")
1895 (parallel [(const_int 0) (const_int 2)])))))]
1896 "ISA_HAS_MSA"
1897 "h<optab>_<su>.d\t%w0,%w1,%w2"
1898 [(set_attr "type" "simd_int_arith")
1899 (set_attr "mode" "V2DI")])
1900
1901 (define_insn "msa_ilvev_b"
1902 [(set (match_operand:V16QI 0 "register_operand" "=f")
1903 (vec_select:V16QI
1904 (vec_concat:V32QI
1905 (match_operand:V16QI 1 "register_operand" "f")
1906 (match_operand:V16QI 2 "register_operand" "f"))
1907 (parallel [(const_int 0) (const_int 16)
1908 (const_int 2) (const_int 18)
1909 (const_int 4) (const_int 20)
1910 (const_int 6) (const_int 22)
1911 (const_int 8) (const_int 24)
1912 (const_int 10) (const_int 26)
1913 (const_int 12) (const_int 28)
1914 (const_int 14) (const_int 30)])))]
1915 "ISA_HAS_MSA"
1916 "ilvev.b\t%w0,%w2,%w1"
1917 [(set_attr "type" "simd_permute")
1918 (set_attr "mode" "V16QI")])
1919
1920 (define_insn "msa_ilvev_h"
1921 [(set (match_operand:V8HI 0 "register_operand" "=f")
1922 (vec_select:V8HI
1923 (vec_concat:V16HI
1924 (match_operand:V8HI 1 "register_operand" "f")
1925 (match_operand:V8HI 2 "register_operand" "f"))
1926 (parallel [(const_int 0) (const_int 8)
1927 (const_int 2) (const_int 10)
1928 (const_int 4) (const_int 12)
1929 (const_int 6) (const_int 14)])))]
1930 "ISA_HAS_MSA"
1931 "ilvev.h\t%w0,%w2,%w1"
1932 [(set_attr "type" "simd_permute")
1933 (set_attr "mode" "V8HI")])
1934
1935 (define_insn "msa_ilvev_w"
1936 [(set (match_operand:V4SI 0 "register_operand" "=f")
1937 (vec_select:V4SI
1938 (vec_concat:V8SI
1939 (match_operand:V4SI 1 "register_operand" "f")
1940 (match_operand:V4SI 2 "register_operand" "f"))
1941 (parallel [(const_int 0) (const_int 4)
1942 (const_int 2) (const_int 6)])))]
1943 "ISA_HAS_MSA"
1944 "ilvev.w\t%w0,%w2,%w1"
1945 [(set_attr "type" "simd_permute")
1946 (set_attr "mode" "V4SI")])
1947
1948 (define_insn "msa_ilvev_w_f"
1949 [(set (match_operand:V4SF 0 "register_operand" "=f")
1950 (vec_select:V4SF
1951 (vec_concat:V8SF
1952 (match_operand:V4SF 1 "register_operand" "f")
1953 (match_operand:V4SF 2 "register_operand" "f"))
1954 (parallel [(const_int 0) (const_int 4)
1955 (const_int 2) (const_int 6)])))]
1956 "ISA_HAS_MSA"
1957 "ilvev.w\t%w0,%w2,%w1"
1958 [(set_attr "type" "simd_permute")
1959 (set_attr "mode" "V4SF")])
1960
1961 (define_insn "msa_ilvl_b"
1962 [(set (match_operand:V16QI 0 "register_operand" "=f")
1963 (vec_select:V16QI
1964 (vec_concat:V32QI
1965 (match_operand:V16QI 1 "register_operand" "f")
1966 (match_operand:V16QI 2 "register_operand" "f"))
1967 (parallel [(const_int 8) (const_int 24)
1968 (const_int 9) (const_int 25)
1969 (const_int 10) (const_int 26)
1970 (const_int 11) (const_int 27)
1971 (const_int 12) (const_int 28)
1972 (const_int 13) (const_int 29)
1973 (const_int 14) (const_int 30)
1974 (const_int 15) (const_int 31)])))]
1975 "ISA_HAS_MSA"
1976 "ilvl.b\t%w0,%w2,%w1"
1977 [(set_attr "type" "simd_permute")
1978 (set_attr "mode" "V16QI")])
1979
1980 (define_insn "msa_ilvl_h"
1981 [(set (match_operand:V8HI 0 "register_operand" "=f")
1982 (vec_select:V8HI
1983 (vec_concat:V16HI
1984 (match_operand:V8HI 1 "register_operand" "f")
1985 (match_operand:V8HI 2 "register_operand" "f"))
1986 (parallel [(const_int 4) (const_int 12)
1987 (const_int 5) (const_int 13)
1988 (const_int 6) (const_int 14)
1989 (const_int 7) (const_int 15)])))]
1990 "ISA_HAS_MSA"
1991 "ilvl.h\t%w0,%w2,%w1"
1992 [(set_attr "type" "simd_permute")
1993 (set_attr "mode" "V8HI")])
1994
1995 (define_insn "msa_ilvl_w"
1996 [(set (match_operand:V4SI 0 "register_operand" "=f")
1997 (vec_select:V4SI
1998 (vec_concat:V8SI
1999 (match_operand:V4SI 1 "register_operand" "f")
2000 (match_operand:V4SI 2 "register_operand" "f"))
2001 (parallel [(const_int 2) (const_int 6)
2002 (const_int 3) (const_int 7)])))]
2003 "ISA_HAS_MSA"
2004 "ilvl.w\t%w0,%w2,%w1"
2005 [(set_attr "type" "simd_permute")
2006 (set_attr "mode" "V4SI")])
2007
2008 (define_insn "msa_ilvl_w_f"
2009 [(set (match_operand:V4SF 0 "register_operand" "=f")
2010 (vec_select:V4SF
2011 (vec_concat:V8SF
2012 (match_operand:V4SF 1 "register_operand" "f")
2013 (match_operand:V4SF 2 "register_operand" "f"))
2014 (parallel [(const_int 2) (const_int 6)
2015 (const_int 3) (const_int 7)])))]
2016 "ISA_HAS_MSA"
2017 "ilvl.w\t%w0,%w2,%w1"
2018 [(set_attr "type" "simd_permute")
2019 (set_attr "mode" "V4SF")])
2020
2021 (define_insn "msa_ilvl_d"
2022 [(set (match_operand:V2DI 0 "register_operand" "=f")
2023 (vec_select:V2DI
2024 (vec_concat:V4DI
2025 (match_operand:V2DI 1 "register_operand" "f")
2026 (match_operand:V2DI 2 "register_operand" "f"))
2027 (parallel [(const_int 1) (const_int 3)])))]
2028 "ISA_HAS_MSA"
2029 "ilvl.d\t%w0,%w2,%w1"
2030 [(set_attr "type" "simd_permute")
2031 (set_attr "mode" "V2DI")])
2032
2033 (define_insn "msa_ilvl_d_f"
2034 [(set (match_operand:V2DF 0 "register_operand" "=f")
2035 (vec_select:V2DF
2036 (vec_concat:V4DF
2037 (match_operand:V2DF 1 "register_operand" "f")
2038 (match_operand:V2DF 2 "register_operand" "f"))
2039 (parallel [(const_int 1) (const_int 3)])))]
2040 "ISA_HAS_MSA"
2041 "ilvl.d\t%w0,%w2,%w1"
2042 [(set_attr "type" "simd_permute")
2043 (set_attr "mode" "V2DF")])
2044
2045 (define_insn "msa_ilvod_b"
2046 [(set (match_operand:V16QI 0 "register_operand" "=f")
2047 (vec_select:V16QI
2048 (vec_concat:V32QI
2049 (match_operand:V16QI 1 "register_operand" "f")
2050 (match_operand:V16QI 2 "register_operand" "f"))
2051 (parallel [(const_int 1) (const_int 17)
2052 (const_int 3) (const_int 19)
2053 (const_int 5) (const_int 21)
2054 (const_int 7) (const_int 23)
2055 (const_int 9) (const_int 25)
2056 (const_int 11) (const_int 27)
2057 (const_int 13) (const_int 29)
2058 (const_int 15) (const_int 31)])))]
2059 "ISA_HAS_MSA"
2060 "ilvod.b\t%w0,%w2,%w1"
2061 [(set_attr "type" "simd_permute")
2062 (set_attr "mode" "V16QI")])
2063
2064 (define_insn "msa_ilvod_h"
2065 [(set (match_operand:V8HI 0 "register_operand" "=f")
2066 (vec_select:V8HI
2067 (vec_concat:V16HI
2068 (match_operand:V8HI 1 "register_operand" "f")
2069 (match_operand:V8HI 2 "register_operand" "f"))
2070 (parallel [(const_int 1) (const_int 9)
2071 (const_int 3) (const_int 11)
2072 (const_int 5) (const_int 13)
2073 (const_int 7) (const_int 15)])))]
2074 "ISA_HAS_MSA"
2075 "ilvod.h\t%w0,%w2,%w1"
2076 [(set_attr "type" "simd_permute")
2077 (set_attr "mode" "V8HI")])
2078
2079 (define_insn "msa_ilvod_w"
2080 [(set (match_operand:V4SI 0 "register_operand" "=f")
2081 (vec_select:V4SI
2082 (vec_concat:V8SI
2083 (match_operand:V4SI 1 "register_operand" "f")
2084 (match_operand:V4SI 2 "register_operand" "f"))
2085 (parallel [(const_int 1) (const_int 5)
2086 (const_int 3) (const_int 7)])))]
2087 "ISA_HAS_MSA"
2088 "ilvod.w\t%w0,%w2,%w1"
2089 [(set_attr "type" "simd_permute")
2090 (set_attr "mode" "V4SI")])
2091
2092 (define_insn "msa_ilvod_w_f"
2093 [(set (match_operand:V4SF 0 "register_operand" "=f")
2094 (vec_select:V4SF
2095 (vec_concat:V8SF
2096 (match_operand:V4SF 1 "register_operand" "f")
2097 (match_operand:V4SF 2 "register_operand" "f"))
2098 (parallel [(const_int 1) (const_int 5)
2099 (const_int 3) (const_int 7)])))]
2100 "ISA_HAS_MSA"
2101 "ilvod.w\t%w0,%w2,%w1"
2102 [(set_attr "type" "simd_permute")
2103 (set_attr "mode" "V4SF")])
2104
2105 (define_insn "msa_ilvr_b"
2106 [(set (match_operand:V16QI 0 "register_operand" "=f")
2107 (vec_select:V16QI
2108 (vec_concat:V32QI
2109 (match_operand:V16QI 1 "register_operand" "f")
2110 (match_operand:V16QI 2 "register_operand" "f"))
2111 (parallel [(const_int 0) (const_int 16)
2112 (const_int 1) (const_int 17)
2113 (const_int 2) (const_int 18)
2114 (const_int 3) (const_int 19)
2115 (const_int 4) (const_int 20)
2116 (const_int 5) (const_int 21)
2117 (const_int 6) (const_int 22)
2118 (const_int 7) (const_int 23)])))]
2119 "ISA_HAS_MSA"
2120 "ilvr.b\t%w0,%w2,%w1"
2121 [(set_attr "type" "simd_permute")
2122 (set_attr "mode" "V16QI")])
2123
2124 (define_insn "msa_ilvr_h"
2125 [(set (match_operand:V8HI 0 "register_operand" "=f")
2126 (vec_select:V8HI
2127 (vec_concat:V16HI
2128 (match_operand:V8HI 1 "register_operand" "f")
2129 (match_operand:V8HI 2 "register_operand" "f"))
2130 (parallel [(const_int 0) (const_int 8)
2131 (const_int 1) (const_int 9)
2132 (const_int 2) (const_int 10)
2133 (const_int 3) (const_int 11)])))]
2134 "ISA_HAS_MSA"
2135 "ilvr.h\t%w0,%w2,%w1"
2136 [(set_attr "type" "simd_permute")
2137 (set_attr "mode" "V8HI")])
2138
2139 (define_insn "msa_ilvr_w"
2140 [(set (match_operand:V4SI 0 "register_operand" "=f")
2141 (vec_select:V4SI
2142 (vec_concat:V8SI
2143 (match_operand:V4SI 1 "register_operand" "f")
2144 (match_operand:V4SI 2 "register_operand" "f"))
2145 (parallel [(const_int 0) (const_int 4)
2146 (const_int 1) (const_int 5)])))]
2147 "ISA_HAS_MSA"
2148 "ilvr.w\t%w0,%w2,%w1"
2149 [(set_attr "type" "simd_permute")
2150 (set_attr "mode" "V4SI")])
2151
2152 (define_insn "msa_ilvr_w_f"
2153 [(set (match_operand:V4SF 0 "register_operand" "=f")
2154 (vec_select:V4SF
2155 (vec_concat:V8SF
2156 (match_operand:V4SF 1 "register_operand" "f")
2157 (match_operand:V4SF 2 "register_operand" "f"))
2158 (parallel [(const_int 0) (const_int 4)
2159 (const_int 1) (const_int 5)])))]
2160 "ISA_HAS_MSA"
2161 "ilvr.w\t%w0,%w2,%w1"
2162 [(set_attr "type" "simd_permute")
2163 (set_attr "mode" "V4SF")])
2164
2165 (define_insn "msa_ilvr_d"
2166 [(set (match_operand:V2DI 0 "register_operand" "=f")
2167 (vec_select:V2DI
2168 (vec_concat:V4DI
2169 (match_operand:V2DI 1 "register_operand" "f")
2170 (match_operand:V2DI 2 "register_operand" "f"))
2171 (parallel [(const_int 0) (const_int 2)])))]
2172 "ISA_HAS_MSA"
2173 "ilvr.d\t%w0,%w2,%w1"
2174 [(set_attr "type" "simd_permute")
2175 (set_attr "mode" "V2DI")])
2176
2177 (define_insn "msa_ilvr_d_f"
2178 [(set (match_operand:V2DF 0 "register_operand" "=f")
2179 (vec_select:V2DF
2180 (vec_concat:V4DF
2181 (match_operand:V2DF 1 "register_operand" "f")
2182 (match_operand:V2DF 2 "register_operand" "f"))
2183 (parallel [(const_int 0) (const_int 2)])))]
2184 "ISA_HAS_MSA"
2185 "ilvr.d\t%w0,%w2,%w1"
2186 [(set_attr "type" "simd_permute")
2187 (set_attr "mode" "V2DF")])
2188
2189 (define_insn "msa_madd_q_<msafmt>"
2190 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2191 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2192 (match_operand:IMSA_WH 2 "register_operand" "f")
2193 (match_operand:IMSA_WH 3 "register_operand" "f")]
2194 UNSPEC_MSA_MADD_Q))]
2195 "ISA_HAS_MSA"
2196 "madd_q.<msafmt>\t%w0,%w2,%w3"
2197 [(set_attr "type" "simd_mul")
2198 (set_attr "mode" "<MODE>")])
2199
2200 (define_insn "msa_maddr_q_<msafmt>"
2201 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2202 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2203 (match_operand:IMSA_WH 2 "register_operand" "f")
2204 (match_operand:IMSA_WH 3 "register_operand" "f")]
2205 UNSPEC_MSA_MADDR_Q))]
2206 "ISA_HAS_MSA"
2207 "maddr_q.<msafmt>\t%w0,%w2,%w3"
2208 [(set_attr "type" "simd_mul")
2209 (set_attr "mode" "<MODE>")])
2210
2211 (define_insn "msa_max_a_<msafmt>"
2212 [(set (match_operand:IMSA 0 "register_operand" "=f")
2213 (if_then_else:IMSA
2214 (gt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
2215 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f")))
2216 (match_dup 1)
2217 (match_dup 2)))]
2218 "ISA_HAS_MSA"
2219 "max_a.<msafmt>\t%w0,%w1,%w2"
2220 [(set_attr "type" "simd_int_arith")
2221 (set_attr "mode" "<MODE>")])
2222
2223 (define_insn "smax<mode>3"
2224 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2225 (smax:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2226 (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))]
2227 "ISA_HAS_MSA"
2228 "@
2229 max_s.<msafmt>\t%w0,%w1,%w2
2230 maxi_s.<msafmt>\t%w0,%w1,%E2"
2231 [(set_attr "type" "simd_int_arith")
2232 (set_attr "mode" "<MODE>")])
2233
2234 (define_insn "umax<mode>3"
2235 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2236 (umax:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2237 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
2238 "ISA_HAS_MSA"
2239 "@
2240 max_u.<msafmt>\t%w0,%w1,%w2
2241 maxi_u.<msafmt>\t%w0,%w1,%B2"
2242 [(set_attr "type" "simd_int_arith")
2243 (set_attr "mode" "<MODE>")])
2244
2245 (define_insn "msa_min_a_<msafmt>"
2246 [(set (match_operand:IMSA 0 "register_operand" "=f")
2247 (if_then_else:IMSA
2248 (lt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
2249 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f")))
2250 (match_dup 1)
2251 (match_dup 2)))]
2252 "ISA_HAS_MSA"
2253 "min_a.<msafmt>\t%w0,%w1,%w2"
2254 [(set_attr "type" "simd_int_arith")
2255 (set_attr "mode" "<MODE>")])
2256
2257 (define_insn "smin<mode>3"
2258 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2259 (smin:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2260 (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))]
2261 "ISA_HAS_MSA"
2262 "@
2263 min_s.<msafmt>\t%w0,%w1,%w2
2264 mini_s.<msafmt>\t%w0,%w1,%E2"
2265 [(set_attr "type" "simd_int_arith")
2266 (set_attr "mode" "<MODE>")])
2267
2268 (define_insn "umin<mode>3"
2269 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2270 (umin:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2271 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
2272 "ISA_HAS_MSA"
2273 "@
2274 min_u.<msafmt>\t%w0,%w1,%w2
2275 mini_u.<msafmt>\t%w0,%w1,%B2"
2276 [(set_attr "type" "simd_int_arith")
2277 (set_attr "mode" "<MODE>")])
2278
2279 (define_insn "msa_msub_q_<msafmt>"
2280 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2281 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2282 (match_operand:IMSA_WH 2 "register_operand" "f")
2283 (match_operand:IMSA_WH 3 "register_operand" "f")]
2284 UNSPEC_MSA_MSUB_Q))]
2285 "ISA_HAS_MSA"
2286 "msub_q.<msafmt>\t%w0,%w2,%w3"
2287 [(set_attr "type" "simd_mul")
2288 (set_attr "mode" "<MODE>")])
2289
2290 (define_insn "msa_msubr_q_<msafmt>"
2291 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2292 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2293 (match_operand:IMSA_WH 2 "register_operand" "f")
2294 (match_operand:IMSA_WH 3 "register_operand" "f")]
2295 UNSPEC_MSA_MSUBR_Q))]
2296 "ISA_HAS_MSA"
2297 "msubr_q.<msafmt>\t%w0,%w2,%w3"
2298 [(set_attr "type" "simd_mul")
2299 (set_attr "mode" "<MODE>")])
2300
2301 (define_insn "msa_mul_q_<msafmt>"
2302 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2303 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f")
2304 (match_operand:IMSA_WH 2 "register_operand" "f")]
2305 UNSPEC_MSA_MUL_Q))]
2306 "ISA_HAS_MSA"
2307 "mul_q.<msafmt>\t%w0,%w1,%w2"
2308 [(set_attr "type" "simd_mul")
2309 (set_attr "mode" "<MODE>")])
2310
2311 (define_insn "msa_mulr_q_<msafmt>"
2312 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2313 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f")
2314 (match_operand:IMSA_WH 2 "register_operand" "f")]
2315 UNSPEC_MSA_MULR_Q))]
2316 "ISA_HAS_MSA"
2317 "mulr_q.<msafmt>\t%w0,%w1,%w2"
2318 [(set_attr "type" "simd_mul")
2319 (set_attr "mode" "<MODE>")])
2320
2321 (define_insn "msa_nloc_<msafmt>"
2322 [(set (match_operand:IMSA 0 "register_operand" "=f")
2323 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")]
2324 UNSPEC_MSA_NLOC))]
2325 "ISA_HAS_MSA"
2326 "nloc.<msafmt>\t%w0,%w1"
2327 [(set_attr "type" "simd_bit")
2328 (set_attr "mode" "<MODE>")])
2329
2330 (define_insn "clz<mode>2"
2331 [(set (match_operand:IMSA 0 "register_operand" "=f")
2332 (clz:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
2333 "ISA_HAS_MSA"
2334 "nlzc.<msafmt>\t%w0,%w1"
2335 [(set_attr "type" "simd_bit")
2336 (set_attr "mode" "<MODE>")])
2337
2338 (define_insn "msa_nor_<msafmt>"
2339 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2340 (and:IMSA (not:IMSA (match_operand:IMSA 1 "register_operand" "f,f"))
2341 (not:IMSA (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,Urv8"))))]
2342 "ISA_HAS_MSA"
2343 "@
2344 nor.v\t%w0,%w1,%w2
2345 nori.b\t%w0,%w1,%B2"
2346 [(set_attr "type" "simd_logic")
2347 (set_attr "mode" "<MODE>")])
2348
2349 (define_insn "msa_pckev_b"
2350 [(set (match_operand:V16QI 0 "register_operand" "=f")
2351 (vec_select:V16QI
2352 (vec_concat:V32QI
2353 (match_operand:V16QI 1 "register_operand" "f")
2354 (match_operand:V16QI 2 "register_operand" "f"))
2355 (parallel [(const_int 0) (const_int 2)
2356 (const_int 4) (const_int 6)
2357 (const_int 8) (const_int 10)
2358 (const_int 12) (const_int 14)
2359 (const_int 16) (const_int 18)
2360 (const_int 20) (const_int 22)
2361 (const_int 24) (const_int 26)
2362 (const_int 28) (const_int 30)])))]
2363 "ISA_HAS_MSA"
2364 "pckev.b\t%w0,%w2,%w1"
2365 [(set_attr "type" "simd_permute")
2366 (set_attr "mode" "V16QI")])
2367
2368 (define_insn "msa_pckev_h"
2369 [(set (match_operand:V8HI 0 "register_operand" "=f")
2370 (vec_select:V8HI
2371 (vec_concat:V16HI
2372 (match_operand:V8HI 1 "register_operand" "f")
2373 (match_operand:V8HI 2 "register_operand" "f"))
2374 (parallel [(const_int 0) (const_int 2)
2375 (const_int 4) (const_int 6)
2376 (const_int 8) (const_int 10)
2377 (const_int 12) (const_int 14)])))]
2378 "ISA_HAS_MSA"
2379 "pckev.h\t%w0,%w2,%w1"
2380 [(set_attr "type" "simd_permute")
2381 (set_attr "mode" "V8HI")])
2382
2383 (define_insn "msa_pckev_w"
2384 [(set (match_operand:V4SI 0 "register_operand" "=f")
2385 (vec_select:V4SI
2386 (vec_concat:V8SI
2387 (match_operand:V4SI 1 "register_operand" "f")
2388 (match_operand:V4SI 2 "register_operand" "f"))
2389 (parallel [(const_int 0) (const_int 2)
2390 (const_int 4) (const_int 6)])))]
2391 "ISA_HAS_MSA"
2392 "pckev.w\t%w0,%w2,%w1"
2393 [(set_attr "type" "simd_permute")
2394 (set_attr "mode" "V4SI")])
2395
2396 (define_insn "msa_pckev_w_f"
2397 [(set (match_operand:V4SF 0 "register_operand" "=f")
2398 (vec_select:V4SF
2399 (vec_concat:V8SF
2400 (match_operand:V4SF 1 "register_operand" "f")
2401 (match_operand:V4SF 2 "register_operand" "f"))
2402 (parallel [(const_int 0) (const_int 2)
2403 (const_int 4) (const_int 6)])))]
2404 "ISA_HAS_MSA"
2405 "pckev.w\t%w0,%w2,%w1"
2406 [(set_attr "type" "simd_permute")
2407 (set_attr "mode" "V4SF")])
2408
2409 (define_insn "msa_pckod_b"
2410 [(set (match_operand:V16QI 0 "register_operand" "=f")
2411 (vec_select:V16QI
2412 (vec_concat:V32QI
2413 (match_operand:V16QI 1 "register_operand" "f")
2414 (match_operand:V16QI 2 "register_operand" "f"))
2415 (parallel [(const_int 1) (const_int 3)
2416 (const_int 5) (const_int 7)
2417 (const_int 9) (const_int 11)
2418 (const_int 13) (const_int 15)
2419 (const_int 17) (const_int 19)
2420 (const_int 21) (const_int 23)
2421 (const_int 25) (const_int 27)
2422 (const_int 29) (const_int 31)])))]
2423 "ISA_HAS_MSA"
2424 "pckod.b\t%w0,%w2,%w1"
2425 [(set_attr "type" "simd_permute")
2426 (set_attr "mode" "V16QI")])
2427
2428 (define_insn "msa_pckod_h"
2429 [(set (match_operand:V8HI 0 "register_operand" "=f")
2430 (vec_select:V8HI
2431 (vec_concat:V16HI
2432 (match_operand:V8HI 1 "register_operand" "f")
2433 (match_operand:V8HI 2 "register_operand" "f"))
2434 (parallel [(const_int 1) (const_int 3)
2435 (const_int 5) (const_int 7)
2436 (const_int 9) (const_int 11)
2437 (const_int 13) (const_int 15)])))]
2438 "ISA_HAS_MSA"
2439 "pckod.h\t%w0,%w2,%w1"
2440 [(set_attr "type" "simd_permute")
2441 (set_attr "mode" "V8HI")])
2442
2443 (define_insn "msa_pckod_w"
2444 [(set (match_operand:V4SI 0 "register_operand" "=f")
2445 (vec_select:V4SI
2446 (vec_concat:V8SI
2447 (match_operand:V4SI 1 "register_operand" "f")
2448 (match_operand:V4SI 2 "register_operand" "f"))
2449 (parallel [(const_int 1) (const_int 3)
2450 (const_int 5) (const_int 7)])))]
2451 "ISA_HAS_MSA"
2452 "pckod.w\t%w0,%w2,%w1"
2453 [(set_attr "type" "simd_permute")
2454 (set_attr "mode" "V4SI")])
2455
2456 (define_insn "msa_pckod_w_f"
2457 [(set (match_operand:V4SF 0 "register_operand" "=f")
2458 (vec_select:V4SF
2459 (vec_concat:V8SF
2460 (match_operand:V4SF 1 "register_operand" "f")
2461 (match_operand:V4SF 2 "register_operand" "f"))
2462 (parallel [(const_int 1) (const_int 3)
2463 (const_int 5) (const_int 7)])))]
2464 "ISA_HAS_MSA"
2465 "pckod.w\t%w0,%w2,%w1"
2466 [(set_attr "type" "simd_permute")
2467 (set_attr "mode" "V4SF")])
2468
2469 (define_insn "popcount<mode>2"
2470 [(set (match_operand:IMSA 0 "register_operand" "=f")
2471 (popcount:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
2472 "ISA_HAS_MSA"
2473 "pcnt.<msafmt>\t%w0,%w1"
2474 [(set_attr "type" "simd_pcnt")
2475 (set_attr "mode" "<MODE>")])
2476
2477 (define_insn "msa_sat_s_<msafmt>"
2478 [(set (match_operand:IMSA 0 "register_operand" "=f")
2479 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2480 (match_operand 2 "const_<bitimm>_operand" "")]
2481 UNSPEC_MSA_SAT_S))]
2482 "ISA_HAS_MSA"
2483 "sat_s.<msafmt>\t%w0,%w1,%2"
2484 [(set_attr "type" "simd_sat")
2485 (set_attr "mode" "<MODE>")])
2486
2487 (define_insn "msa_sat_u_<msafmt>"
2488 [(set (match_operand:IMSA 0 "register_operand" "=f")
2489 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2490 (match_operand 2 "const_<bitimm>_operand" "")]
2491 UNSPEC_MSA_SAT_U))]
2492 "ISA_HAS_MSA"
2493 "sat_u.<msafmt>\t%w0,%w1,%2"
2494 [(set_attr "type" "simd_sat")
2495 (set_attr "mode" "<MODE>")])
2496
2497 (define_insn "msa_shf_<msafmt_f>"
2498 [(set (match_operand:MSA_WHB_W 0 "register_operand" "=f")
2499 (vec_select:MSA_WHB_W
2500 (match_operand:MSA_WHB_W 1 "register_operand" "f")
2501 (match_operand 2 "par_const_vector_shf_set_operand" "")))]
2502 "ISA_HAS_MSA"
2503 {
2504 HOST_WIDE_INT val = 0;
2505 unsigned int i;
2506
2507 /* We convert the selection to an immediate. */
2508 for (i = 0; i < 4; i++)
2509 val |= INTVAL (XVECEXP (operands[2], 0, i)) << (2 * i);
2510
2511 operands[2] = GEN_INT (val);
2512 return "shf.<msafmt>\t%w0,%w1,%X2";
2513 }
2514 [(set_attr "type" "simd_shf")
2515 (set_attr "mode" "<MODE>")])
2516
2517 (define_insn "msa_srar_<msafmt>"
2518 [(set (match_operand:IMSA 0 "register_operand" "=f")
2519 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2520 (match_operand:IMSA 2 "register_operand" "f")]
2521 UNSPEC_MSA_SRAR))]
2522 "ISA_HAS_MSA"
2523 "srar.<msafmt>\t%w0,%w1,%w2"
2524 [(set_attr "type" "simd_shift")
2525 (set_attr "mode" "<MODE>")])
2526
2527 (define_insn "msa_srari_<msafmt>"
2528 [(set (match_operand:IMSA 0 "register_operand" "=f")
2529 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2530 (match_operand 2 "const_<bitimm>_operand" "")]
2531 UNSPEC_MSA_SRARI))]
2532 "ISA_HAS_MSA"
2533 "srari.<msafmt>\t%w0,%w1,%2"
2534 [(set_attr "type" "simd_shift")
2535 (set_attr "mode" "<MODE>")])
2536
2537 (define_insn "msa_srlr_<msafmt>"
2538 [(set (match_operand:IMSA 0 "register_operand" "=f")
2539 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2540 (match_operand:IMSA 2 "register_operand" "f")]
2541 UNSPEC_MSA_SRLR))]
2542 "ISA_HAS_MSA"
2543 "srlr.<msafmt>\t%w0,%w1,%w2"
2544 [(set_attr "type" "simd_shift")
2545 (set_attr "mode" "<MODE>")])
2546
2547 (define_insn "msa_srlri_<msafmt>"
2548 [(set (match_operand:IMSA 0 "register_operand" "=f")
2549 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2550 (match_operand 2 "const_<bitimm>_operand" "")]
2551 UNSPEC_MSA_SRLRI))]
2552 "ISA_HAS_MSA"
2553 "srlri.<msafmt>\t%w0,%w1,%2"
2554 [(set_attr "type" "simd_shift")
2555 (set_attr "mode" "<MODE>")])
2556
2557 (define_insn "msa_subs_s_<msafmt>"
2558 [(set (match_operand:IMSA 0 "register_operand" "=f")
2559 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2560 (match_operand:IMSA 2 "register_operand" "f")]
2561 UNSPEC_MSA_SUBS_S))]
2562 "ISA_HAS_MSA"
2563 "subs_s.<msafmt>\t%w0,%w1,%w2"
2564 [(set_attr "type" "simd_int_arith")
2565 (set_attr "mode" "<MODE>")])
2566
2567 (define_insn "msa_subs_u_<msafmt>"
2568 [(set (match_operand:IMSA 0 "register_operand" "=f")
2569 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2570 (match_operand:IMSA 2 "register_operand" "f")]
2571 UNSPEC_MSA_SUBS_U))]
2572 "ISA_HAS_MSA"
2573 "subs_u.<msafmt>\t%w0,%w1,%w2"
2574 [(set_attr "type" "simd_int_arith")
2575 (set_attr "mode" "<MODE>")])
2576
2577 (define_insn "msa_subsuu_s_<msafmt>"
2578 [(set (match_operand:IMSA 0 "register_operand" "=f")
2579 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2580 (match_operand:IMSA 2 "register_operand" "f")]
2581 UNSPEC_MSA_SUBSUU_S))]
2582 "ISA_HAS_MSA"
2583 "subsuu_s.<msafmt>\t%w0,%w1,%w2"
2584 [(set_attr "type" "simd_int_arith")
2585 (set_attr "mode" "<MODE>")])
2586
2587 (define_insn "msa_subsus_u_<msafmt>"
2588 [(set (match_operand:IMSA 0 "register_operand" "=f")
2589 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2590 (match_operand:IMSA 2 "register_operand" "f")]
2591 UNSPEC_MSA_SUBSUS_U))]
2592 "ISA_HAS_MSA"
2593 "subsus_u.<msafmt>\t%w0,%w1,%w2"
2594 [(set_attr "type" "simd_int_arith")
2595 (set_attr "mode" "<MODE>")])
2596
2597 (define_insn "msa_sld_<msafmt_f>"
2598 [(set (match_operand:MSA 0 "register_operand" "=f")
2599 (unspec:MSA [(match_operand:MSA 1 "register_operand" "0")
2600 (match_operand:MSA 2 "register_operand" "f")
2601 (match_operand:SI 3 "reg_or_0_operand" "dJ")]
2602 UNSPEC_MSA_SLD))]
2603 "ISA_HAS_MSA"
2604 "sld.<msafmt>\t%w0,%w2[%z3]"
2605 [(set_attr "type" "simd_sld")
2606 (set_attr "mode" "<MODE>")])
2607
2608 (define_insn "msa_sldi_<msafmt_f>"
2609 [(set (match_operand:MSA 0 "register_operand" "=f")
2610 (unspec:MSA [(match_operand:MSA 1 "register_operand" "0")
2611 (match_operand:MSA 2 "register_operand" "f")
2612 (match_operand 3 "const_<indeximm>_operand" "")]
2613 UNSPEC_MSA_SLDI))]
2614 "ISA_HAS_MSA"
2615 "sldi.<msafmt>\t%w0,%w2[%3]"
2616 [(set_attr "type" "simd_sld")
2617 (set_attr "mode" "<MODE>")])
2618
2619 (define_insn "msa_splat_<msafmt_f>"
2620 [(set (match_operand:MSA 0 "register_operand" "=f")
2621 (unspec:MSA [(match_operand:MSA 1 "register_operand" "f")
2622 (match_operand:SI 2 "register_operand" "d")]
2623 UNSPEC_MSA_SPLAT))]
2624 "ISA_HAS_MSA"
2625 "splat.<msafmt>\t%w0,%w1[%z2]"
2626 [(set_attr "type" "simd_splat")
2627 (set_attr "mode" "<MODE>")])
2628
2629 (define_insn "msa_splati_<msafmt_f>"
2630 [(set (match_operand:MSA 0 "register_operand" "=f")
2631 (vec_duplicate:MSA
2632 (vec_select:<UNITMODE>
2633 (match_operand:MSA 1 "register_operand" "f")
2634 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
2635 "ISA_HAS_MSA"
2636 "splati.<msafmt>\t%w0,%w1[%2]"
2637 [(set_attr "type" "simd_splat")
2638 (set_attr "mode" "<MODE>")])
2639
2640 (define_insn "msa_splati_<msafmt_f>_scalar"
2641 [(set (match_operand:FMSA 0 "register_operand" "=f")
2642 (unspec:FMSA [(match_operand:<UNITMODE> 1 "register_operand" "f")]
2643 UNSPEC_MSA_SPLATI))]
2644 "ISA_HAS_MSA"
2645 "splati.<msafmt>\t%w0,%w1[0]"
2646 [(set_attr "type" "simd_splat")
2647 (set_attr "mode" "<MODE>")])
2648
2649 (define_insn "msa_cfcmsa"
2650 [(set (match_operand:SI 0 "register_operand" "=d")
2651 (unspec_volatile:SI [(match_operand 1 "const_uimm5_operand" "")]
2652 UNSPEC_MSA_CFCMSA))]
2653 "ISA_HAS_MSA"
2654 "cfcmsa\t%0,$%1"
2655 [(set_attr "type" "simd_cmsa")
2656 (set_attr "mode" "SI")])
2657
2658 (define_insn "msa_ctcmsa"
2659 [(unspec_volatile [(match_operand 0 "const_uimm5_operand" "")
2660 (match_operand:SI 1 "register_operand" "d")]
2661 UNSPEC_MSA_CTCMSA)]
2662 "ISA_HAS_MSA"
2663 "ctcmsa\t$%0,%1"
2664 [(set_attr "type" "simd_cmsa")
2665 (set_attr "mode" "SI")])
2666
2667 (define_insn "msa_fexdo_h"
2668 [(set (match_operand:V8HI 0 "register_operand" "=f")
2669 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f")
2670 (match_operand:V4SF 2 "register_operand" "f")]
2671 UNSPEC_MSA_FEXDO))]
2672 "ISA_HAS_MSA"
2673 "fexdo.h\t%w0,%w1,%w2"
2674 [(set_attr "type" "simd_fcvt")
2675 (set_attr "mode" "V8HI")])
2676
2677 (define_insn "vec_pack_trunc_v2df"
2678 [(set (match_operand:V4SF 0 "register_operand" "=f")
2679 (vec_concat:V4SF
2680 (float_truncate:V2SF (match_operand:V2DF 1 "register_operand" "f"))
2681 (float_truncate:V2SF (match_operand:V2DF 2 "register_operand" "f"))))]
2682 "ISA_HAS_MSA"
2683 "fexdo.w\t%w0,%w2,%w1"
2684 [(set_attr "type" "simd_fcvt")
2685 (set_attr "mode" "V4SF")])
2686
2687 (define_insn "msa_fexupl_w"
2688 [(set (match_operand:V4SF 0 "register_operand" "=f")
2689 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")]
2690 UNSPEC_MSA_FEXUPL))]
2691 "ISA_HAS_MSA"
2692 "fexupl.w\t%w0,%w1"
2693 [(set_attr "type" "simd_fcvt")
2694 (set_attr "mode" "V4SF")])
2695
2696 (define_insn "msa_fexupl_d"
2697 [(set (match_operand:V2DF 0 "register_operand" "=f")
2698 (float_extend:V2DF
2699 (vec_select:V2SF
2700 (match_operand:V4SF 1 "register_operand" "f")
2701 (parallel [(const_int 2) (const_int 3)]))))]
2702 "ISA_HAS_MSA"
2703 "fexupl.d\t%w0,%w1"
2704 [(set_attr "type" "simd_fcvt")
2705 (set_attr "mode" "V2DF")])
2706
2707 (define_insn "msa_fexupr_w"
2708 [(set (match_operand:V4SF 0 "register_operand" "=f")
2709 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")]
2710 UNSPEC_MSA_FEXUPR))]
2711 "ISA_HAS_MSA"
2712 "fexupr.w\t%w0,%w1"
2713 [(set_attr "type" "simd_fcvt")
2714 (set_attr "mode" "V4SF")])
2715
2716 (define_insn "msa_fexupr_d"
2717 [(set (match_operand:V2DF 0 "register_operand" "=f")
2718 (float_extend:V2DF
2719 (vec_select:V2SF
2720 (match_operand:V4SF 1 "register_operand" "f")
2721 (parallel [(const_int 0) (const_int 1)]))))]
2722 "ISA_HAS_MSA"
2723 "fexupr.d\t%w0,%w1"
2724 [(set_attr "type" "simd_fcvt")
2725 (set_attr "mode" "V2DF")])
2726
2727 (define_code_attr msabr
2728 [(eq "bz")
2729 (ne "bnz")])
2730
2731 (define_code_attr msabr_neg
2732 [(eq "bnz")
2733 (ne "bz")])
2734
2735 (define_insn "msa_<msabr>_<msafmt_f>"
2736 [(set (pc) (if_then_else
2737 (equality_op
2738 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")]
2739 UNSPEC_MSA_BRANCH)
2740 (match_operand:SI 2 "const_0_operand"))
2741 (label_ref (match_operand 0))
2742 (pc)))]
2743 "ISA_HAS_MSA"
2744 {
2745 return mips_output_conditional_branch (insn, operands,
2746 MIPS_BRANCH ("<msabr>.<msafmt>",
2747 "%w1,%0"),
2748 MIPS_BRANCH ("<msabr_neg>.<msafmt>",
2749 "%w1,%0"));
2750 }
2751 [(set_attr "type" "simd_branch")
2752 (set_attr "mode" "<MODE>")
2753 (set_attr "compact_form" "never")
2754 (set_attr "branch_likely" "no")])
2755
2756 (define_insn "msa_<msabr>_v_<msafmt_f>"
2757 [(set (pc) (if_then_else
2758 (equality_op
2759 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")]
2760 UNSPEC_MSA_BRANCH_V)
2761 (match_operand:SI 2 "const_0_operand"))
2762 (label_ref (match_operand 0))
2763 (pc)))]
2764 "ISA_HAS_MSA"
2765 {
2766 return mips_output_conditional_branch (insn, operands,
2767 MIPS_BRANCH ("<msabr>.v", "%w1,%0"),
2768 MIPS_BRANCH ("<msabr_neg>.v",
2769 "%w1,%0"));
2770 }
2771 [(set_attr "type" "simd_branch")
2772 (set_attr "mode" "TI")
2773 (set_attr "compact_form" "never")
2774 (set_attr "branch_likely" "no")])
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