1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
60 #include "diagnostic.h"
61 #include "target-globals.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type
{
185 /* Enumerates the setting of the -mr10k-cache-barrier option. */
186 enum mips_r10k_cache_barrier_setting
{
187 R10K_CACHE_BARRIER_NONE
,
188 R10K_CACHE_BARRIER_STORE
,
189 R10K_CACHE_BARRIER_LOAD_STORE
192 /* Macros to create an enumeration identifier for a function prototype. */
193 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
194 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
195 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
196 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
198 /* Classifies the prototype of a built-in function. */
199 enum mips_function_type
{
200 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
201 #include "config/mips/mips-ftypes.def"
202 #undef DEF_MIPS_FTYPE
206 /* Specifies how a built-in function should be converted into rtl. */
207 enum mips_builtin_type
{
208 /* The function corresponds directly to an .md pattern. The return
209 value is mapped to operand 0 and the arguments are mapped to
210 operands 1 and above. */
213 /* The function corresponds directly to an .md pattern. There is no return
214 value and the arguments are mapped to operands 0 and above. */
215 MIPS_BUILTIN_DIRECT_NO_TARGET
,
217 /* The function corresponds to a comparison instruction followed by
218 a mips_cond_move_tf_ps pattern. The first two arguments are the
219 values to compare and the second two arguments are the vector
220 operands for the movt.ps or movf.ps instruction (in assembly order). */
224 /* The function corresponds to a V2SF comparison instruction. Operand 0
225 of this instruction is the result of the comparison, which has mode
226 CCV2 or CCV4. The function arguments are mapped to operands 1 and
227 above. The function's return value is an SImode boolean that is
228 true under the following conditions:
230 MIPS_BUILTIN_CMP_ANY: one of the registers is true
231 MIPS_BUILTIN_CMP_ALL: all of the registers are true
232 MIPS_BUILTIN_CMP_LOWER: the first register is true
233 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
234 MIPS_BUILTIN_CMP_ANY
,
235 MIPS_BUILTIN_CMP_ALL
,
236 MIPS_BUILTIN_CMP_UPPER
,
237 MIPS_BUILTIN_CMP_LOWER
,
239 /* As above, but the instruction only sets a single $fcc register. */
240 MIPS_BUILTIN_CMP_SINGLE
,
242 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
243 MIPS_BUILTIN_BPOSGE32
246 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
247 #define MIPS_FP_CONDITIONS(MACRO) \
265 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
266 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
267 enum mips_fp_condition
{
268 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
271 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
272 #define STRINGIFY(X) #X
273 static const char *const mips_fp_conditions
[] = {
274 MIPS_FP_CONDITIONS (STRINGIFY
)
277 /* Information about a function's frame layout. */
278 struct GTY(()) mips_frame_info
{
279 /* The size of the frame in bytes. */
280 HOST_WIDE_INT total_size
;
282 /* The number of bytes allocated to variables. */
283 HOST_WIDE_INT var_size
;
285 /* The number of bytes allocated to outgoing function arguments. */
286 HOST_WIDE_INT args_size
;
288 /* The number of bytes allocated to the .cprestore slot, or 0 if there
290 HOST_WIDE_INT cprestore_size
;
292 /* Bit X is set if the function saves or restores GPR X. */
295 /* Likewise FPR X. */
298 /* Likewise doubleword accumulator X ($acX). */
299 unsigned int acc_mask
;
301 /* The number of GPRs, FPRs, doubleword accumulators and COP0
305 unsigned int num_acc
;
306 unsigned int num_cop0_regs
;
308 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
309 save slots from the top of the frame, or zero if no such slots are
311 HOST_WIDE_INT gp_save_offset
;
312 HOST_WIDE_INT fp_save_offset
;
313 HOST_WIDE_INT acc_save_offset
;
314 HOST_WIDE_INT cop0_save_offset
;
316 /* Likewise, but giving offsets from the bottom of the frame. */
317 HOST_WIDE_INT gp_sp_offset
;
318 HOST_WIDE_INT fp_sp_offset
;
319 HOST_WIDE_INT acc_sp_offset
;
320 HOST_WIDE_INT cop0_sp_offset
;
322 /* Similar, but the value passed to _mcount. */
323 HOST_WIDE_INT ra_fp_offset
;
325 /* The offset of arg_pointer_rtx from the bottom of the frame. */
326 HOST_WIDE_INT arg_pointer_offset
;
328 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
329 HOST_WIDE_INT hard_frame_pointer_offset
;
332 struct GTY(()) machine_function
{
333 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
334 rtx mips16_gp_pseudo_rtx
;
336 /* The number of extra stack bytes taken up by register varargs.
337 This area is allocated by the callee at the very top of the frame. */
340 /* The current frame information, calculated by mips_compute_frame_info. */
341 struct mips_frame_info frame
;
343 /* The register to use as the function's global pointer, or INVALID_REGNUM
344 if the function doesn't need one. */
345 unsigned int global_pointer
;
347 /* How many instructions it takes to load a label into $AT, or 0 if
348 this property hasn't yet been calculated. */
349 unsigned int load_label_length
;
351 /* True if mips_adjust_insn_length should ignore an instruction's
353 bool ignore_hazard_length_p
;
355 /* True if the whole function is suitable for .set noreorder and
357 bool all_noreorder_p
;
359 /* True if the function has "inflexible" and "flexible" references
360 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
361 and mips_cfun_has_flexible_gp_ref_p for details. */
362 bool has_inflexible_gp_insn_p
;
363 bool has_flexible_gp_insn_p
;
365 /* True if the function's prologue must load the global pointer
366 value into pic_offset_table_rtx and store the same value in
367 the function's cprestore slot (if any). Even if this value
368 is currently false, we may decide to set it to true later;
369 see mips_must_initialize_gp_p () for details. */
370 bool must_initialize_gp_p
;
372 /* True if the current function must restore $gp after any potential
373 clobber. This value is only meaningful during the first post-epilogue
374 split_insns pass; see mips_must_initialize_gp_p () for details. */
375 bool must_restore_gp_when_clobbered_p
;
377 /* True if we have emitted an instruction to initialize
378 mips16_gp_pseudo_rtx. */
379 bool initialized_mips16_gp_pseudo_p
;
381 /* True if this is an interrupt handler. */
382 bool interrupt_handler_p
;
384 /* True if this is an interrupt handler that uses shadow registers. */
385 bool use_shadow_register_set_p
;
387 /* True if this is an interrupt handler that should keep interrupts
389 bool keep_interrupts_masked_p
;
391 /* True if this is an interrupt handler that should use DERET
393 bool use_debug_exception_return_p
;
396 /* Information about a single argument. */
397 struct mips_arg_info
{
398 /* True if the argument is passed in a floating-point register, or
399 would have been if we hadn't run out of registers. */
402 /* The number of words passed in registers, rounded up. */
403 unsigned int reg_words
;
405 /* For EABI, the offset of the first register from GP_ARG_FIRST or
406 FP_ARG_FIRST. For other ABIs, the offset of the first register from
407 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
408 comment for details).
410 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
412 unsigned int reg_offset
;
414 /* The number of words that must be passed on the stack, rounded up. */
415 unsigned int stack_words
;
417 /* The offset from the start of the stack overflow area of the argument's
418 first stack word. Only meaningful when STACK_WORDS is nonzero. */
419 unsigned int stack_offset
;
422 /* Information about an address described by mips_address_type.
428 REG is the base register and OFFSET is the constant offset.
431 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
432 is the type of symbol it references.
435 SYMBOL_TYPE is the type of symbol that the address references. */
436 struct mips_address_info
{
437 enum mips_address_type type
;
440 enum mips_symbol_type symbol_type
;
443 /* One stage in a constant building sequence. These sequences have
447 A = A CODE[1] VALUE[1]
448 A = A CODE[2] VALUE[2]
451 where A is an accumulator, each CODE[i] is a binary rtl operation
452 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
453 struct mips_integer_op
{
455 unsigned HOST_WIDE_INT value
;
458 /* The largest number of operations needed to load an integer constant.
459 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
460 When the lowest bit is clear, we can try, but reject a sequence with
461 an extra SLL at the end. */
462 #define MIPS_MAX_INTEGER_OPS 7
464 /* Information about a MIPS16e SAVE or RESTORE instruction. */
465 struct mips16e_save_restore_info
{
466 /* The number of argument registers saved by a SAVE instruction.
467 0 for RESTORE instructions. */
470 /* Bit X is set if the instruction saves or restores GPR X. */
473 /* The total number of bytes to allocate. */
477 /* Costs of various operations on the different architectures. */
479 struct mips_rtx_cost_data
481 unsigned short fp_add
;
482 unsigned short fp_mult_sf
;
483 unsigned short fp_mult_df
;
484 unsigned short fp_div_sf
;
485 unsigned short fp_div_df
;
486 unsigned short int_mult_si
;
487 unsigned short int_mult_di
;
488 unsigned short int_div_si
;
489 unsigned short int_div_di
;
490 unsigned short branch_cost
;
491 unsigned short memory_latency
;
494 /* Global variables for machine-dependent things. */
496 /* The -G setting, or the configuration's default small-data limit if
497 no -G option is given. */
498 static unsigned int mips_small_data_threshold
;
500 /* The number of file directives written by mips_output_filename. */
501 int num_source_filenames
;
503 /* The name that appeared in the last .file directive written by
504 mips_output_filename, or "" if mips_output_filename hasn't
505 written anything yet. */
506 const char *current_function_file
= "";
508 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
511 /* Arrays that map GCC register numbers to debugger register numbers. */
512 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
513 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
515 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
516 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
517 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
518 struct mips_asm_switch mips_noat
= { "at", 0 };
520 /* True if we're writing out a branch-likely instruction rather than a
522 static bool mips_branch_likely
;
524 /* The current instruction-set architecture. */
525 enum processor mips_arch
;
526 const struct mips_cpu_info
*mips_arch_info
;
528 /* The processor that we should tune the code for. */
529 enum processor mips_tune
;
530 const struct mips_cpu_info
*mips_tune_info
;
532 /* The ISA level associated with mips_arch. */
535 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
536 static const struct mips_cpu_info
*mips_isa_option_info
;
538 /* Which ABI to use. */
539 int mips_abi
= MIPS_ABI_DEFAULT
;
541 /* Which cost information to use. */
542 static const struct mips_rtx_cost_data
*mips_cost
;
544 /* The ambient target flags, excluding MASK_MIPS16. */
545 static int mips_base_target_flags
;
547 /* True if MIPS16 is the default mode. */
548 bool mips_base_mips16
;
550 /* The ambient values of other global variables. */
551 static int mips_base_schedule_insns
; /* flag_schedule_insns */
552 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
553 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
554 static int mips_base_align_loops
; /* align_loops */
555 static int mips_base_align_jumps
; /* align_jumps */
556 static int mips_base_align_functions
; /* align_functions */
558 /* The -mcode-readable setting. */
559 enum mips_code_readable_setting mips_code_readable
= CODE_READABLE_YES
;
561 /* The -mr10k-cache-barrier setting. */
562 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier
;
564 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
565 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
567 /* Index C is true if character C is a valid PRINT_OPERAND punctation
569 static bool mips_print_operand_punct
[256];
571 static GTY (()) int mips_output_filename_first_time
= 1;
573 /* mips_split_p[X] is true if symbols of type X can be split by
574 mips_split_symbol. */
575 bool mips_split_p
[NUM_SYMBOL_TYPES
];
577 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
578 can be split by mips_split_symbol. */
579 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
581 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
582 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
583 if they are matched by a special .md file pattern. */
584 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
586 /* Likewise for HIGHs. */
587 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
589 /* Target state for MIPS16. */
590 struct target_globals
*mips16_globals
;
592 /* Index R is the smallest register class that contains register R. */
593 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
594 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
595 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
596 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
597 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
598 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
599 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
600 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
601 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
602 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
603 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
604 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
605 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
606 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
607 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
608 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
609 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
610 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
611 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
612 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
613 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
614 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
615 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
616 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
617 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
618 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
619 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
620 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
621 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
622 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
623 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
624 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
625 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
626 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
627 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
628 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
629 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
630 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
631 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
632 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
633 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
634 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
635 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
636 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
637 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
638 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
639 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
640 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
643 /* The value of TARGET_ATTRIBUTE_TABLE. */
644 static const struct attribute_spec mips_attribute_table
[] = {
645 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
646 { "long_call", 0, 0, false, true, true, NULL
},
647 { "far", 0, 0, false, true, true, NULL
},
648 { "near", 0, 0, false, true, true, NULL
},
649 /* We would really like to treat "mips16" and "nomips16" as type
650 attributes, but GCC doesn't provide the hooks we need to support
651 the right conversion rules. As declaration attributes, they affect
652 code generation but don't carry other semantics. */
653 { "mips16", 0, 0, true, false, false, NULL
},
654 { "nomips16", 0, 0, true, false, false, NULL
},
655 /* Allow functions to be specified as interrupt handlers */
656 { "interrupt", 0, 0, false, true, true, NULL
},
657 { "use_shadow_register_set", 0, 0, false, true, true, NULL
},
658 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
},
659 { "use_debug_exception_return", 0, 0, false, true, true, NULL
},
660 { NULL
, 0, 0, false, false, false, NULL
}
663 /* A table describing all the processors GCC knows about. Names are
664 matched in the order listed. The first mention of an ISA level is
665 taken as the canonical name for that ISA.
667 To ease comparison, please keep this table in the same order
668 as GAS's mips_cpu_info_table. Please also make sure that
669 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
670 options correctly. */
671 static const struct mips_cpu_info mips_cpu_info_table
[] = {
672 /* Entries for generic ISAs. */
673 { "mips1", PROCESSOR_R3000
, 1, 0 },
674 { "mips2", PROCESSOR_R6000
, 2, 0 },
675 { "mips3", PROCESSOR_R4000
, 3, 0 },
676 { "mips4", PROCESSOR_R8000
, 4, 0 },
677 /* Prefer not to use branch-likely instructions for generic MIPS32rX
678 and MIPS64rX code. The instructions were officially deprecated
679 in revisions 2 and earlier, but revision 3 is likely to downgrade
680 that to a recommendation to avoid the instructions in code that
681 isn't tuned to a specific processor. */
682 { "mips32", PROCESSOR_4KC
, 32, PTF_AVOID_BRANCHLIKELY
},
683 { "mips32r2", PROCESSOR_M4K
, 33, PTF_AVOID_BRANCHLIKELY
},
684 { "mips64", PROCESSOR_5KC
, 64, PTF_AVOID_BRANCHLIKELY
},
685 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
686 { "mips64r2", PROCESSOR_5KC
, 65, PTF_AVOID_BRANCHLIKELY
},
688 /* MIPS I processors. */
689 { "r3000", PROCESSOR_R3000
, 1, 0 },
690 { "r2000", PROCESSOR_R3000
, 1, 0 },
691 { "r3900", PROCESSOR_R3900
, 1, 0 },
693 /* MIPS II processors. */
694 { "r6000", PROCESSOR_R6000
, 2, 0 },
696 /* MIPS III processors. */
697 { "r4000", PROCESSOR_R4000
, 3, 0 },
698 { "vr4100", PROCESSOR_R4100
, 3, 0 },
699 { "vr4111", PROCESSOR_R4111
, 3, 0 },
700 { "vr4120", PROCESSOR_R4120
, 3, 0 },
701 { "vr4130", PROCESSOR_R4130
, 3, 0 },
702 { "vr4300", PROCESSOR_R4300
, 3, 0 },
703 { "r4400", PROCESSOR_R4000
, 3, 0 },
704 { "r4600", PROCESSOR_R4600
, 3, 0 },
705 { "orion", PROCESSOR_R4600
, 3, 0 },
706 { "r4650", PROCESSOR_R4650
, 3, 0 },
707 /* ST Loongson 2E/2F processors. */
708 { "loongson2e", PROCESSOR_LOONGSON_2E
, 3, PTF_AVOID_BRANCHLIKELY
},
709 { "loongson2f", PROCESSOR_LOONGSON_2F
, 3, PTF_AVOID_BRANCHLIKELY
},
711 /* MIPS IV processors. */
712 { "r8000", PROCESSOR_R8000
, 4, 0 },
713 { "r10000", PROCESSOR_R10000
, 4, 0 },
714 { "r12000", PROCESSOR_R10000
, 4, 0 },
715 { "r14000", PROCESSOR_R10000
, 4, 0 },
716 { "r16000", PROCESSOR_R10000
, 4, 0 },
717 { "vr5000", PROCESSOR_R5000
, 4, 0 },
718 { "vr5400", PROCESSOR_R5400
, 4, 0 },
719 { "vr5500", PROCESSOR_R5500
, 4, PTF_AVOID_BRANCHLIKELY
},
720 { "rm7000", PROCESSOR_R7000
, 4, 0 },
721 { "rm9000", PROCESSOR_R9000
, 4, 0 },
723 /* MIPS32 processors. */
724 { "4kc", PROCESSOR_4KC
, 32, 0 },
725 { "4km", PROCESSOR_4KC
, 32, 0 },
726 { "4kp", PROCESSOR_4KP
, 32, 0 },
727 { "4ksc", PROCESSOR_4KC
, 32, 0 },
729 /* MIPS32 Release 2 processors. */
730 { "m4k", PROCESSOR_M4K
, 33, 0 },
731 { "4kec", PROCESSOR_4KC
, 33, 0 },
732 { "4kem", PROCESSOR_4KC
, 33, 0 },
733 { "4kep", PROCESSOR_4KP
, 33, 0 },
734 { "4ksd", PROCESSOR_4KC
, 33, 0 },
736 { "24kc", PROCESSOR_24KC
, 33, 0 },
737 { "24kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
738 { "24kf", PROCESSOR_24KF2_1
, 33, 0 },
739 { "24kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
740 { "24kfx", PROCESSOR_24KF1_1
, 33, 0 },
741 { "24kx", PROCESSOR_24KF1_1
, 33, 0 },
743 { "24kec", PROCESSOR_24KC
, 33, 0 }, /* 24K with DSP. */
744 { "24kef2_1", PROCESSOR_24KF2_1
, 33, 0 },
745 { "24kef", PROCESSOR_24KF2_1
, 33, 0 },
746 { "24kef1_1", PROCESSOR_24KF1_1
, 33, 0 },
747 { "24kefx", PROCESSOR_24KF1_1
, 33, 0 },
748 { "24kex", PROCESSOR_24KF1_1
, 33, 0 },
750 { "34kc", PROCESSOR_24KC
, 33, 0 }, /* 34K with MT/DSP. */
751 { "34kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
752 { "34kf", PROCESSOR_24KF2_1
, 33, 0 },
753 { "34kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
754 { "34kfx", PROCESSOR_24KF1_1
, 33, 0 },
755 { "34kx", PROCESSOR_24KF1_1
, 33, 0 },
757 { "74kc", PROCESSOR_74KC
, 33, 0 }, /* 74K with DSPr2. */
758 { "74kf2_1", PROCESSOR_74KF2_1
, 33, 0 },
759 { "74kf", PROCESSOR_74KF2_1
, 33, 0 },
760 { "74kf1_1", PROCESSOR_74KF1_1
, 33, 0 },
761 { "74kfx", PROCESSOR_74KF1_1
, 33, 0 },
762 { "74kx", PROCESSOR_74KF1_1
, 33, 0 },
763 { "74kf3_2", PROCESSOR_74KF3_2
, 33, 0 },
765 { "1004kc", PROCESSOR_24KC
, 33, 0 }, /* 1004K with MT/DSP. */
766 { "1004kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
767 { "1004kf", PROCESSOR_24KF2_1
, 33, 0 },
768 { "1004kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
770 /* MIPS64 processors. */
771 { "5kc", PROCESSOR_5KC
, 64, 0 },
772 { "5kf", PROCESSOR_5KF
, 64, 0 },
773 { "20kc", PROCESSOR_20KC
, 64, PTF_AVOID_BRANCHLIKELY
},
774 { "sb1", PROCESSOR_SB1
, 64, PTF_AVOID_BRANCHLIKELY
},
775 { "sb1a", PROCESSOR_SB1A
, 64, PTF_AVOID_BRANCHLIKELY
},
776 { "sr71000", PROCESSOR_SR71000
, 64, PTF_AVOID_BRANCHLIKELY
},
777 { "xlr", PROCESSOR_XLR
, 64, 0 },
779 /* MIPS64 Release 2 processors. */
780 { "octeon", PROCESSOR_OCTEON
, 65, PTF_AVOID_BRANCHLIKELY
}
783 /* Default costs. If these are used for a processor we should look
784 up the actual costs. */
785 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
786 COSTS_N_INSNS (7), /* fp_mult_sf */ \
787 COSTS_N_INSNS (8), /* fp_mult_df */ \
788 COSTS_N_INSNS (23), /* fp_div_sf */ \
789 COSTS_N_INSNS (36), /* fp_div_df */ \
790 COSTS_N_INSNS (10), /* int_mult_si */ \
791 COSTS_N_INSNS (10), /* int_mult_di */ \
792 COSTS_N_INSNS (69), /* int_div_si */ \
793 COSTS_N_INSNS (69), /* int_div_di */ \
794 2, /* branch_cost */ \
795 4 /* memory_latency */
797 /* Floating-point costs for processors without an FPU. Just assume that
798 all floating-point libcalls are very expensive. */
799 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
800 COSTS_N_INSNS (256), /* fp_mult_sf */ \
801 COSTS_N_INSNS (256), /* fp_mult_df */ \
802 COSTS_N_INSNS (256), /* fp_div_sf */ \
803 COSTS_N_INSNS (256) /* fp_div_df */
805 /* Costs to use when optimizing for size. */
806 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
807 COSTS_N_INSNS (1), /* fp_add */
808 COSTS_N_INSNS (1), /* fp_mult_sf */
809 COSTS_N_INSNS (1), /* fp_mult_df */
810 COSTS_N_INSNS (1), /* fp_div_sf */
811 COSTS_N_INSNS (1), /* fp_div_df */
812 COSTS_N_INSNS (1), /* int_mult_si */
813 COSTS_N_INSNS (1), /* int_mult_di */
814 COSTS_N_INSNS (1), /* int_div_si */
815 COSTS_N_INSNS (1), /* int_div_di */
817 4 /* memory_latency */
820 /* Costs to use when optimizing for speed, indexed by processor. */
821 static const struct mips_rtx_cost_data
822 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
824 COSTS_N_INSNS (2), /* fp_add */
825 COSTS_N_INSNS (4), /* fp_mult_sf */
826 COSTS_N_INSNS (5), /* fp_mult_df */
827 COSTS_N_INSNS (12), /* fp_div_sf */
828 COSTS_N_INSNS (19), /* fp_div_df */
829 COSTS_N_INSNS (12), /* int_mult_si */
830 COSTS_N_INSNS (12), /* int_mult_di */
831 COSTS_N_INSNS (35), /* int_div_si */
832 COSTS_N_INSNS (35), /* int_div_di */
834 4 /* memory_latency */
838 COSTS_N_INSNS (6), /* int_mult_si */
839 COSTS_N_INSNS (6), /* int_mult_di */
840 COSTS_N_INSNS (36), /* int_div_si */
841 COSTS_N_INSNS (36), /* int_div_di */
843 4 /* memory_latency */
847 COSTS_N_INSNS (36), /* int_mult_si */
848 COSTS_N_INSNS (36), /* int_mult_di */
849 COSTS_N_INSNS (37), /* int_div_si */
850 COSTS_N_INSNS (37), /* int_div_di */
852 4 /* memory_latency */
856 COSTS_N_INSNS (4), /* int_mult_si */
857 COSTS_N_INSNS (11), /* int_mult_di */
858 COSTS_N_INSNS (36), /* int_div_si */
859 COSTS_N_INSNS (68), /* int_div_di */
861 4 /* memory_latency */
864 COSTS_N_INSNS (4), /* fp_add */
865 COSTS_N_INSNS (4), /* fp_mult_sf */
866 COSTS_N_INSNS (5), /* fp_mult_df */
867 COSTS_N_INSNS (17), /* fp_div_sf */
868 COSTS_N_INSNS (32), /* fp_div_df */
869 COSTS_N_INSNS (4), /* int_mult_si */
870 COSTS_N_INSNS (11), /* int_mult_di */
871 COSTS_N_INSNS (36), /* int_div_si */
872 COSTS_N_INSNS (68), /* int_div_di */
874 4 /* memory_latency */
877 COSTS_N_INSNS (4), /* fp_add */
878 COSTS_N_INSNS (4), /* fp_mult_sf */
879 COSTS_N_INSNS (5), /* fp_mult_df */
880 COSTS_N_INSNS (17), /* fp_div_sf */
881 COSTS_N_INSNS (32), /* fp_div_df */
882 COSTS_N_INSNS (4), /* int_mult_si */
883 COSTS_N_INSNS (7), /* int_mult_di */
884 COSTS_N_INSNS (42), /* int_div_si */
885 COSTS_N_INSNS (72), /* int_div_di */
887 4 /* memory_latency */
891 COSTS_N_INSNS (5), /* int_mult_si */
892 COSTS_N_INSNS (5), /* int_mult_di */
893 COSTS_N_INSNS (41), /* int_div_si */
894 COSTS_N_INSNS (41), /* int_div_di */
896 4 /* memory_latency */
899 COSTS_N_INSNS (8), /* fp_add */
900 COSTS_N_INSNS (8), /* fp_mult_sf */
901 COSTS_N_INSNS (10), /* fp_mult_df */
902 COSTS_N_INSNS (34), /* fp_div_sf */
903 COSTS_N_INSNS (64), /* fp_div_df */
904 COSTS_N_INSNS (5), /* int_mult_si */
905 COSTS_N_INSNS (5), /* int_mult_di */
906 COSTS_N_INSNS (41), /* int_div_si */
907 COSTS_N_INSNS (41), /* int_div_di */
909 4 /* memory_latency */
912 COSTS_N_INSNS (4), /* fp_add */
913 COSTS_N_INSNS (4), /* fp_mult_sf */
914 COSTS_N_INSNS (5), /* fp_mult_df */
915 COSTS_N_INSNS (17), /* fp_div_sf */
916 COSTS_N_INSNS (32), /* fp_div_df */
917 COSTS_N_INSNS (5), /* int_mult_si */
918 COSTS_N_INSNS (5), /* int_mult_di */
919 COSTS_N_INSNS (41), /* int_div_si */
920 COSTS_N_INSNS (41), /* int_div_di */
922 4 /* memory_latency */
926 COSTS_N_INSNS (5), /* int_mult_si */
927 COSTS_N_INSNS (5), /* int_mult_di */
928 COSTS_N_INSNS (41), /* int_div_si */
929 COSTS_N_INSNS (41), /* int_div_di */
931 4 /* memory_latency */
934 COSTS_N_INSNS (8), /* fp_add */
935 COSTS_N_INSNS (8), /* fp_mult_sf */
936 COSTS_N_INSNS (10), /* fp_mult_df */
937 COSTS_N_INSNS (34), /* fp_div_sf */
938 COSTS_N_INSNS (64), /* fp_div_df */
939 COSTS_N_INSNS (5), /* int_mult_si */
940 COSTS_N_INSNS (5), /* int_mult_di */
941 COSTS_N_INSNS (41), /* int_div_si */
942 COSTS_N_INSNS (41), /* int_div_di */
944 4 /* memory_latency */
947 COSTS_N_INSNS (4), /* fp_add */
948 COSTS_N_INSNS (4), /* fp_mult_sf */
949 COSTS_N_INSNS (5), /* fp_mult_df */
950 COSTS_N_INSNS (17), /* fp_div_sf */
951 COSTS_N_INSNS (32), /* fp_div_df */
952 COSTS_N_INSNS (5), /* int_mult_si */
953 COSTS_N_INSNS (5), /* int_mult_di */
954 COSTS_N_INSNS (41), /* int_div_si */
955 COSTS_N_INSNS (41), /* int_div_di */
957 4 /* memory_latency */
960 COSTS_N_INSNS (6), /* fp_add */
961 COSTS_N_INSNS (6), /* fp_mult_sf */
962 COSTS_N_INSNS (7), /* fp_mult_df */
963 COSTS_N_INSNS (25), /* fp_div_sf */
964 COSTS_N_INSNS (48), /* fp_div_df */
965 COSTS_N_INSNS (5), /* int_mult_si */
966 COSTS_N_INSNS (5), /* int_mult_di */
967 COSTS_N_INSNS (41), /* int_div_si */
968 COSTS_N_INSNS (41), /* int_div_di */
970 4 /* memory_latency */
984 COSTS_N_INSNS (5), /* int_mult_si */
985 COSTS_N_INSNS (5), /* int_mult_di */
986 COSTS_N_INSNS (72), /* int_div_si */
987 COSTS_N_INSNS (72), /* int_div_di */
989 4 /* memory_latency */
992 COSTS_N_INSNS (2), /* fp_add */
993 COSTS_N_INSNS (4), /* fp_mult_sf */
994 COSTS_N_INSNS (5), /* fp_mult_df */
995 COSTS_N_INSNS (12), /* fp_div_sf */
996 COSTS_N_INSNS (19), /* fp_div_df */
997 COSTS_N_INSNS (2), /* int_mult_si */
998 COSTS_N_INSNS (2), /* int_mult_di */
999 COSTS_N_INSNS (35), /* int_div_si */
1000 COSTS_N_INSNS (35), /* int_div_di */
1001 1, /* branch_cost */
1002 4 /* memory_latency */
1005 COSTS_N_INSNS (3), /* fp_add */
1006 COSTS_N_INSNS (5), /* fp_mult_sf */
1007 COSTS_N_INSNS (6), /* fp_mult_df */
1008 COSTS_N_INSNS (15), /* fp_div_sf */
1009 COSTS_N_INSNS (16), /* fp_div_df */
1010 COSTS_N_INSNS (17), /* int_mult_si */
1011 COSTS_N_INSNS (17), /* int_mult_di */
1012 COSTS_N_INSNS (38), /* int_div_si */
1013 COSTS_N_INSNS (38), /* int_div_di */
1014 2, /* branch_cost */
1015 6 /* memory_latency */
1018 COSTS_N_INSNS (6), /* fp_add */
1019 COSTS_N_INSNS (7), /* fp_mult_sf */
1020 COSTS_N_INSNS (8), /* fp_mult_df */
1021 COSTS_N_INSNS (23), /* fp_div_sf */
1022 COSTS_N_INSNS (36), /* fp_div_df */
1023 COSTS_N_INSNS (10), /* int_mult_si */
1024 COSTS_N_INSNS (10), /* int_mult_di */
1025 COSTS_N_INSNS (69), /* int_div_si */
1026 COSTS_N_INSNS (69), /* int_div_di */
1027 2, /* branch_cost */
1028 6 /* memory_latency */
1040 /* The only costs that appear to be updated here are
1041 integer multiplication. */
1043 COSTS_N_INSNS (4), /* int_mult_si */
1044 COSTS_N_INSNS (6), /* int_mult_di */
1045 COSTS_N_INSNS (69), /* int_div_si */
1046 COSTS_N_INSNS (69), /* int_div_di */
1047 1, /* branch_cost */
1048 4 /* memory_latency */
1060 COSTS_N_INSNS (6), /* fp_add */
1061 COSTS_N_INSNS (4), /* fp_mult_sf */
1062 COSTS_N_INSNS (5), /* fp_mult_df */
1063 COSTS_N_INSNS (23), /* fp_div_sf */
1064 COSTS_N_INSNS (36), /* fp_div_df */
1065 COSTS_N_INSNS (5), /* int_mult_si */
1066 COSTS_N_INSNS (5), /* int_mult_di */
1067 COSTS_N_INSNS (36), /* int_div_si */
1068 COSTS_N_INSNS (36), /* int_div_di */
1069 1, /* branch_cost */
1070 4 /* memory_latency */
1073 COSTS_N_INSNS (6), /* fp_add */
1074 COSTS_N_INSNS (5), /* fp_mult_sf */
1075 COSTS_N_INSNS (6), /* fp_mult_df */
1076 COSTS_N_INSNS (30), /* fp_div_sf */
1077 COSTS_N_INSNS (59), /* fp_div_df */
1078 COSTS_N_INSNS (3), /* int_mult_si */
1079 COSTS_N_INSNS (4), /* int_mult_di */
1080 COSTS_N_INSNS (42), /* int_div_si */
1081 COSTS_N_INSNS (74), /* int_div_di */
1082 1, /* branch_cost */
1083 4 /* memory_latency */
1086 COSTS_N_INSNS (6), /* fp_add */
1087 COSTS_N_INSNS (5), /* fp_mult_sf */
1088 COSTS_N_INSNS (6), /* fp_mult_df */
1089 COSTS_N_INSNS (30), /* fp_div_sf */
1090 COSTS_N_INSNS (59), /* fp_div_df */
1091 COSTS_N_INSNS (5), /* int_mult_si */
1092 COSTS_N_INSNS (9), /* int_mult_di */
1093 COSTS_N_INSNS (42), /* int_div_si */
1094 COSTS_N_INSNS (74), /* int_div_di */
1095 1, /* branch_cost */
1096 4 /* memory_latency */
1099 /* The only costs that are changed here are
1100 integer multiplication. */
1101 COSTS_N_INSNS (6), /* fp_add */
1102 COSTS_N_INSNS (7), /* fp_mult_sf */
1103 COSTS_N_INSNS (8), /* fp_mult_df */
1104 COSTS_N_INSNS (23), /* fp_div_sf */
1105 COSTS_N_INSNS (36), /* fp_div_df */
1106 COSTS_N_INSNS (5), /* int_mult_si */
1107 COSTS_N_INSNS (9), /* int_mult_di */
1108 COSTS_N_INSNS (69), /* int_div_si */
1109 COSTS_N_INSNS (69), /* int_div_di */
1110 1, /* branch_cost */
1111 4 /* memory_latency */
1117 /* The only costs that are changed here are
1118 integer multiplication. */
1119 COSTS_N_INSNS (6), /* fp_add */
1120 COSTS_N_INSNS (7), /* fp_mult_sf */
1121 COSTS_N_INSNS (8), /* fp_mult_df */
1122 COSTS_N_INSNS (23), /* fp_div_sf */
1123 COSTS_N_INSNS (36), /* fp_div_df */
1124 COSTS_N_INSNS (3), /* int_mult_si */
1125 COSTS_N_INSNS (8), /* int_mult_di */
1126 COSTS_N_INSNS (69), /* int_div_si */
1127 COSTS_N_INSNS (69), /* int_div_di */
1128 1, /* branch_cost */
1129 4 /* memory_latency */
1132 COSTS_N_INSNS (2), /* fp_add */
1133 COSTS_N_INSNS (2), /* fp_mult_sf */
1134 COSTS_N_INSNS (2), /* fp_mult_df */
1135 COSTS_N_INSNS (12), /* fp_div_sf */
1136 COSTS_N_INSNS (19), /* fp_div_df */
1137 COSTS_N_INSNS (5), /* int_mult_si */
1138 COSTS_N_INSNS (9), /* int_mult_di */
1139 COSTS_N_INSNS (34), /* int_div_si */
1140 COSTS_N_INSNS (66), /* int_div_di */
1141 1, /* branch_cost */
1142 4 /* memory_latency */
1145 /* These costs are the same as the SB-1A below. */
1146 COSTS_N_INSNS (4), /* fp_add */
1147 COSTS_N_INSNS (4), /* fp_mult_sf */
1148 COSTS_N_INSNS (4), /* fp_mult_df */
1149 COSTS_N_INSNS (24), /* fp_div_sf */
1150 COSTS_N_INSNS (32), /* fp_div_df */
1151 COSTS_N_INSNS (3), /* int_mult_si */
1152 COSTS_N_INSNS (4), /* int_mult_di */
1153 COSTS_N_INSNS (36), /* int_div_si */
1154 COSTS_N_INSNS (68), /* int_div_di */
1155 1, /* branch_cost */
1156 4 /* memory_latency */
1159 /* These costs are the same as the SB-1 above. */
1160 COSTS_N_INSNS (4), /* fp_add */
1161 COSTS_N_INSNS (4), /* fp_mult_sf */
1162 COSTS_N_INSNS (4), /* fp_mult_df */
1163 COSTS_N_INSNS (24), /* fp_div_sf */
1164 COSTS_N_INSNS (32), /* fp_div_df */
1165 COSTS_N_INSNS (3), /* int_mult_si */
1166 COSTS_N_INSNS (4), /* int_mult_di */
1167 COSTS_N_INSNS (36), /* int_div_si */
1168 COSTS_N_INSNS (68), /* int_div_di */
1169 1, /* branch_cost */
1170 4 /* memory_latency */
1177 COSTS_N_INSNS (8), /* int_mult_si */
1178 COSTS_N_INSNS (8), /* int_mult_di */
1179 COSTS_N_INSNS (72), /* int_div_si */
1180 COSTS_N_INSNS (72), /* int_div_di */
1181 1, /* branch_cost */
1182 4 /* memory_latency */
1186 static rtx
mips_find_pic_call_symbol (rtx
, rtx
);
1187 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1190 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1191 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1192 struct GTY (()) mflip_mips16_entry
{
1196 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1198 /* Hash table callbacks for mflip_mips16_htab. */
1201 mflip_mips16_htab_hash (const void *entry
)
1203 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1207 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1209 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1210 (const char *) name
) == 0;
1213 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1214 mode, false if it should next add an attribute for the opposite mode. */
1215 static GTY(()) bool mips16_flipper
;
1217 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1218 for -mflip-mips16. Return true if it should use "mips16" and false if
1219 it should use "nomips16". */
1222 mflip_mips16_use_mips16_p (tree decl
)
1224 struct mflip_mips16_entry
*entry
;
1229 /* Use the opposite of the command-line setting for anonymous decls. */
1230 if (!DECL_NAME (decl
))
1231 return !mips_base_mips16
;
1233 if (!mflip_mips16_htab
)
1234 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1235 mflip_mips16_htab_eq
, NULL
);
1237 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1238 hash
= htab_hash_string (name
);
1239 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1240 entry
= (struct mflip_mips16_entry
*) *slot
;
1243 mips16_flipper
= !mips16_flipper
;
1244 entry
= ggc_alloc_mflip_mips16_entry ();
1246 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1249 return entry
->mips16_p
;
1252 /* Predicates to test for presence of "near" and "far"/"long_call"
1253 attributes on the given TYPE. */
1256 mips_near_type_p (const_tree type
)
1258 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1262 mips_far_type_p (const_tree type
)
1264 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1265 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1268 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1271 mips_mips16_decl_p (const_tree decl
)
1273 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1277 mips_nomips16_decl_p (const_tree decl
)
1279 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1282 /* Check if the interrupt attribute is set for a function. */
1285 mips_interrupt_type_p (tree type
)
1287 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1290 /* Check if the attribute to use shadow register set is set for a function. */
1293 mips_use_shadow_register_set_p (tree type
)
1295 return lookup_attribute ("use_shadow_register_set",
1296 TYPE_ATTRIBUTES (type
)) != NULL
;
1299 /* Check if the attribute to keep interrupts masked is set for a function. */
1302 mips_keep_interrupts_masked_p (tree type
)
1304 return lookup_attribute ("keep_interrupts_masked",
1305 TYPE_ATTRIBUTES (type
)) != NULL
;
1308 /* Check if the attribute to use debug exception return is set for
1312 mips_use_debug_exception_return_p (tree type
)
1314 return lookup_attribute ("use_debug_exception_return",
1315 TYPE_ATTRIBUTES (type
)) != NULL
;
1318 /* Return true if function DECL is a MIPS16 function. Return the ambient
1319 setting if DECL is null. */
1322 mips_use_mips16_mode_p (tree decl
)
1326 /* Nested functions must use the same frame pointer as their
1327 parent and must therefore use the same ISA mode. */
1328 tree parent
= decl_function_context (decl
);
1331 if (mips_mips16_decl_p (decl
))
1333 if (mips_nomips16_decl_p (decl
))
1336 return mips_base_mips16
;
1339 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1342 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1344 /* Disallow mixed near/far attributes. */
1345 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1347 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1352 /* Implement TARGET_INSERT_ATTRIBUTES. */
1355 mips_insert_attributes (tree decl
, tree
*attributes
)
1358 bool mips16_p
, nomips16_p
;
1360 /* Check for "mips16" and "nomips16" attributes. */
1361 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1362 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1363 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1366 error ("%qs attribute only applies to functions", "mips16");
1368 error ("%qs attribute only applies to functions", "nomips16");
1372 mips16_p
|= mips_mips16_decl_p (decl
);
1373 nomips16_p
|= mips_nomips16_decl_p (decl
);
1374 if (mips16_p
|| nomips16_p
)
1376 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1377 if (mips16_p
&& nomips16_p
)
1378 error ("%qE cannot have both %<mips16%> and "
1379 "%<nomips16%> attributes",
1382 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1384 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1385 "mips16" attribute, arbitrarily pick one. We must pick the same
1386 setting for duplicate declarations of a function. */
1387 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1388 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1393 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1396 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1398 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1399 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1400 error ("%qE redeclared with conflicting %qs attributes",
1401 DECL_NAME (newdecl
), "mips16");
1402 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1403 error ("%qE redeclared with conflicting %qs attributes",
1404 DECL_NAME (newdecl
), "nomips16");
1406 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1407 DECL_ATTRIBUTES (newdecl
));
1410 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1411 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1414 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1416 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1418 *base_ptr
= XEXP (x
, 0);
1419 *offset_ptr
= INTVAL (XEXP (x
, 1));
1428 static unsigned int mips_build_integer (struct mips_integer_op
*,
1429 unsigned HOST_WIDE_INT
);
1431 /* A subroutine of mips_build_integer, with the same interface.
1432 Assume that the final action in the sequence should be a left shift. */
1435 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1437 unsigned int i
, shift
;
1439 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1440 since signed numbers are easier to load than unsigned ones. */
1442 while ((value
& 1) == 0)
1443 value
/= 2, shift
++;
1445 i
= mips_build_integer (codes
, value
);
1446 codes
[i
].code
= ASHIFT
;
1447 codes
[i
].value
= shift
;
1451 /* As for mips_build_shift, but assume that the final action will be
1452 an IOR or PLUS operation. */
1455 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1457 unsigned HOST_WIDE_INT high
;
1460 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1461 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1463 /* The constant is too complex to load with a simple LUI/ORI pair,
1464 so we want to give the recursive call as many trailing zeros as
1465 possible. In this case, we know bit 16 is set and that the
1466 low 16 bits form a negative number. If we subtract that number
1467 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1468 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1469 codes
[i
].code
= PLUS
;
1470 codes
[i
].value
= CONST_LOW_PART (value
);
1474 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1475 bits gives a value with at least 17 trailing zeros. */
1476 i
= mips_build_integer (codes
, high
);
1477 codes
[i
].code
= IOR
;
1478 codes
[i
].value
= value
& 0xffff;
1483 /* Fill CODES with a sequence of rtl operations to load VALUE.
1484 Return the number of operations needed. */
1487 mips_build_integer (struct mips_integer_op
*codes
,
1488 unsigned HOST_WIDE_INT value
)
1490 if (SMALL_OPERAND (value
)
1491 || SMALL_OPERAND_UNSIGNED (value
)
1492 || LUI_OPERAND (value
))
1494 /* The value can be loaded with a single instruction. */
1495 codes
[0].code
= UNKNOWN
;
1496 codes
[0].value
= value
;
1499 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1501 /* Either the constant is a simple LUI/ORI combination or its
1502 lowest bit is set. We don't want to shift in this case. */
1503 return mips_build_lower (codes
, value
);
1505 else if ((value
& 0xffff) == 0)
1507 /* The constant will need at least three actions. The lowest
1508 16 bits are clear, so the final action will be a shift. */
1509 return mips_build_shift (codes
, value
);
1513 /* The final action could be a shift, add or inclusive OR.
1514 Rather than use a complex condition to select the best
1515 approach, try both mips_build_shift and mips_build_lower
1516 and pick the one that gives the shortest sequence.
1517 Note that this case is only used once per constant. */
1518 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1519 unsigned int cost
, alt_cost
;
1521 cost
= mips_build_shift (codes
, value
);
1522 alt_cost
= mips_build_lower (alt_codes
, value
);
1523 if (alt_cost
< cost
)
1525 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1532 /* Return true if symbols of type TYPE require a GOT access. */
1535 mips_got_symbol_type_p (enum mips_symbol_type type
)
1539 case SYMBOL_GOT_PAGE_OFST
:
1540 case SYMBOL_GOT_DISP
:
1548 /* Return true if X is a thread-local symbol. */
1551 mips_tls_symbol_p (rtx x
)
1553 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1556 /* Return true if SYMBOL_REF X is associated with a global symbol
1557 (in the STB_GLOBAL sense). */
1560 mips_global_symbol_p (const_rtx x
)
1562 const_tree decl
= SYMBOL_REF_DECL (x
);
1565 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1567 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1568 or weak symbols. Relocations in the object file will be against
1569 the target symbol, so it's that symbol's binding that matters here. */
1570 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1573 /* Return true if function X is a libgcc MIPS16 stub function. */
1576 mips16_stub_function_p (const_rtx x
)
1578 return (GET_CODE (x
) == SYMBOL_REF
1579 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1582 /* Return true if function X is a locally-defined and locally-binding
1586 mips16_local_function_p (const_rtx x
)
1588 return (GET_CODE (x
) == SYMBOL_REF
1589 && SYMBOL_REF_LOCAL_P (x
)
1590 && !SYMBOL_REF_EXTERNAL_P (x
)
1591 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x
)));
1594 /* Return true if SYMBOL_REF X binds locally. */
1597 mips_symbol_binds_local_p (const_rtx x
)
1599 return (SYMBOL_REF_DECL (x
)
1600 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1601 : SYMBOL_REF_LOCAL_P (x
));
1604 /* Return true if rtx constants of mode MODE should be put into a small
1608 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1610 return (!TARGET_EMBEDDED_DATA
1611 && TARGET_LOCAL_SDATA
1612 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1615 /* Return true if X should not be moved directly into register $25.
1616 We need this because many versions of GAS will treat "la $25,foo" as
1617 part of a call sequence and so allow a global "foo" to be lazily bound. */
1620 mips_dangerous_for_la25_p (rtx x
)
1622 return (!TARGET_EXPLICIT_RELOCS
1624 && GET_CODE (x
) == SYMBOL_REF
1625 && mips_global_symbol_p (x
));
1628 /* Return true if calls to X might need $25 to be valid on entry. */
1631 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1633 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1636 /* MIPS16 stub functions are guaranteed not to use $25. */
1637 if (mips16_stub_function_p (x
))
1640 if (GET_CODE (x
) == SYMBOL_REF
)
1642 /* If PLTs and copy relocations are available, the static linker
1643 will make sure that $25 is valid on entry to the target function. */
1644 if (TARGET_ABICALLS_PIC0
)
1647 /* Locally-defined functions use absolute accesses to set up
1648 the global pointer. */
1649 if (TARGET_ABSOLUTE_ABICALLS
1650 && mips_symbol_binds_local_p (x
)
1651 && !SYMBOL_REF_EXTERNAL_P (x
))
1658 /* Return the method that should be used to access SYMBOL_REF or
1659 LABEL_REF X in context CONTEXT. */
1661 static enum mips_symbol_type
1662 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1665 return SYMBOL_GOT_DISP
;
1667 if (GET_CODE (x
) == LABEL_REF
)
1669 /* LABEL_REFs are used for jump tables as well as text labels.
1670 Only return SYMBOL_PC_RELATIVE if we know the label is in
1671 the text section. */
1672 if (TARGET_MIPS16_SHORT_JUMP_TABLES
)
1673 return SYMBOL_PC_RELATIVE
;
1675 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1676 return SYMBOL_GOT_PAGE_OFST
;
1678 return SYMBOL_ABSOLUTE
;
1681 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1683 if (SYMBOL_REF_TLS_MODEL (x
))
1686 if (CONSTANT_POOL_ADDRESS_P (x
))
1688 if (TARGET_MIPS16_TEXT_LOADS
)
1689 return SYMBOL_PC_RELATIVE
;
1691 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1692 return SYMBOL_PC_RELATIVE
;
1694 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1695 return SYMBOL_GP_RELATIVE
;
1698 /* Do not use small-data accesses for weak symbols; they may end up
1700 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1701 return SYMBOL_GP_RELATIVE
;
1703 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1705 if (TARGET_ABICALLS_PIC2
1706 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1708 /* There are three cases to consider:
1710 - o32 PIC (either with or without explicit relocs)
1711 - n32/n64 PIC without explicit relocs
1712 - n32/n64 PIC with explicit relocs
1714 In the first case, both local and global accesses will use an
1715 R_MIPS_GOT16 relocation. We must correctly predict which of
1716 the two semantics (local or global) the assembler and linker
1717 will apply. The choice depends on the symbol's binding rather
1718 than its visibility.
1720 In the second case, the assembler will not use R_MIPS_GOT16
1721 relocations, but it chooses between local and global accesses
1722 in the same way as for o32 PIC.
1724 In the third case we have more freedom since both forms of
1725 access will work for any kind of symbol. However, there seems
1726 little point in doing things differently. */
1727 if (mips_global_symbol_p (x
))
1728 return SYMBOL_GOT_DISP
;
1730 return SYMBOL_GOT_PAGE_OFST
;
1733 if (TARGET_MIPS16_PCREL_LOADS
&& context
!= SYMBOL_CONTEXT_CALL
)
1734 return SYMBOL_FORCE_TO_MEM
;
1736 return SYMBOL_ABSOLUTE
;
1739 /* Classify the base of symbolic expression X, given that X appears in
1742 static enum mips_symbol_type
1743 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1747 split_const (x
, &x
, &offset
);
1748 if (UNSPEC_ADDRESS_P (x
))
1749 return UNSPEC_ADDRESS_TYPE (x
);
1751 return mips_classify_symbol (x
, context
);
1754 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1755 is the alignment in bytes of SYMBOL_REF X. */
1758 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1760 HOST_WIDE_INT align
;
1762 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1763 return IN_RANGE (offset
, 0, align
- 1);
1766 /* Return true if X is a symbolic constant that can be used in context
1767 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1770 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1771 enum mips_symbol_type
*symbol_type
)
1775 split_const (x
, &x
, &offset
);
1776 if (UNSPEC_ADDRESS_P (x
))
1778 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1779 x
= UNSPEC_ADDRESS (x
);
1781 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1783 *symbol_type
= mips_classify_symbol (x
, context
);
1784 if (*symbol_type
== SYMBOL_TLS
)
1790 if (offset
== const0_rtx
)
1793 /* Check whether a nonzero offset is valid for the underlying
1795 switch (*symbol_type
)
1797 case SYMBOL_ABSOLUTE
:
1798 case SYMBOL_FORCE_TO_MEM
:
1799 case SYMBOL_32_HIGH
:
1800 case SYMBOL_64_HIGH
:
1803 /* If the target has 64-bit pointers and the object file only
1804 supports 32-bit symbols, the values of those symbols will be
1805 sign-extended. In this case we can't allow an arbitrary offset
1806 in case the 32-bit value X + OFFSET has a different sign from X. */
1807 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1808 return offset_within_block_p (x
, INTVAL (offset
));
1810 /* In other cases the relocations can handle any offset. */
1813 case SYMBOL_PC_RELATIVE
:
1814 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1815 In this case, we no longer have access to the underlying constant,
1816 but the original symbol-based access was known to be valid. */
1817 if (GET_CODE (x
) == LABEL_REF
)
1822 case SYMBOL_GP_RELATIVE
:
1823 /* Make sure that the offset refers to something within the
1824 same object block. This should guarantee that the final
1825 PC- or GP-relative offset is within the 16-bit limit. */
1826 return offset_within_block_p (x
, INTVAL (offset
));
1828 case SYMBOL_GOT_PAGE_OFST
:
1829 case SYMBOL_GOTOFF_PAGE
:
1830 /* If the symbol is global, the GOT entry will contain the symbol's
1831 address, and we will apply a 16-bit offset after loading it.
1832 If the symbol is local, the linker should provide enough local
1833 GOT entries for a 16-bit offset, but larger offsets may lead
1835 return SMALL_INT (offset
);
1839 /* There is no carry between the HI and LO REL relocations, so the
1840 offset is only valid if we know it won't lead to such a carry. */
1841 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1843 case SYMBOL_GOT_DISP
:
1844 case SYMBOL_GOTOFF_DISP
:
1845 case SYMBOL_GOTOFF_CALL
:
1846 case SYMBOL_GOTOFF_LOADGP
:
1849 case SYMBOL_GOTTPREL
:
1857 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1858 single instruction. We rely on the fact that, in the worst case,
1859 all instructions involved in a MIPS16 address calculation are usually
1863 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1867 case SYMBOL_ABSOLUTE
:
1868 /* When using 64-bit symbols, we need 5 preparatory instructions,
1871 lui $at,%highest(symbol)
1872 daddiu $at,$at,%higher(symbol)
1874 daddiu $at,$at,%hi(symbol)
1877 The final address is then $at + %lo(symbol). With 32-bit
1878 symbols we just need a preparatory LUI for normal mode and
1879 a preparatory LI and SLL for MIPS16. */
1880 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1882 case SYMBOL_GP_RELATIVE
:
1883 /* Treat GP-relative accesses as taking a single instruction on
1884 MIPS16 too; the copy of $gp can often be shared. */
1887 case SYMBOL_PC_RELATIVE
:
1888 /* PC-relative constants can be only be used with ADDIUPC,
1889 DADDIUPC, LWPC and LDPC. */
1890 if (mode
== MAX_MACHINE_MODE
1891 || GET_MODE_SIZE (mode
) == 4
1892 || GET_MODE_SIZE (mode
) == 8)
1895 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1898 case SYMBOL_FORCE_TO_MEM
:
1899 /* LEAs will be converted into constant-pool references by
1901 if (mode
== MAX_MACHINE_MODE
)
1904 /* The constant must be loaded and then dereferenced. */
1907 case SYMBOL_GOT_DISP
:
1908 /* The constant will have to be loaded from the GOT before it
1909 is used in an address. */
1910 if (mode
!= MAX_MACHINE_MODE
)
1915 case SYMBOL_GOT_PAGE_OFST
:
1916 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1917 local/global classification is accurate. The worst cases are:
1919 (1) For local symbols when generating o32 or o64 code. The assembler
1925 ...and the final address will be $at + %lo(symbol).
1927 (2) For global symbols when -mxgot. The assembler will use:
1929 lui $at,%got_hi(symbol)
1932 ...and the final address will be $at + %got_lo(symbol). */
1935 case SYMBOL_GOTOFF_PAGE
:
1936 case SYMBOL_GOTOFF_DISP
:
1937 case SYMBOL_GOTOFF_CALL
:
1938 case SYMBOL_GOTOFF_LOADGP
:
1939 case SYMBOL_32_HIGH
:
1940 case SYMBOL_64_HIGH
:
1946 case SYMBOL_GOTTPREL
:
1949 /* A 16-bit constant formed by a single relocation, or a 32-bit
1950 constant formed from a high 16-bit relocation and a low 16-bit
1951 relocation. Use mips_split_p to determine which. 32-bit
1952 constants need an "lui; addiu" sequence for normal mode and
1953 an "li; sll; addiu" sequence for MIPS16 mode. */
1954 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1957 /* We don't treat a bare TLS symbol as a constant. */
1963 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1964 to load symbols of type TYPE into a register. Return 0 if the given
1965 type of symbol cannot be used as an immediate operand.
1967 Otherwise, return the number of instructions needed to load or store
1968 values of mode MODE to or from addresses of type TYPE. Return 0 if
1969 the given type of symbol is not valid in addresses.
1971 In both cases, treat extended MIPS16 instructions as two instructions. */
1974 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1976 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1979 /* A for_each_rtx callback. Stop the search if *X references a
1980 thread-local symbol. */
1983 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1985 return mips_tls_symbol_p (*x
);
1988 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1991 mips_cannot_force_const_mem (rtx x
)
1993 enum mips_symbol_type type
;
1996 /* There is no assembler syntax for expressing an address-sized
1998 if (GET_CODE (x
) == HIGH
)
2001 /* As an optimization, reject constants that mips_legitimize_move
2004 Suppose we have a multi-instruction sequence that loads constant C
2005 into register R. If R does not get allocated a hard register, and
2006 R is used in an operand that allows both registers and memory
2007 references, reload will consider forcing C into memory and using
2008 one of the instruction's memory alternatives. Returning false
2009 here will force it to use an input reload instead. */
2010 if (CONST_INT_P (x
) && LEGITIMATE_CONSTANT_P (x
))
2013 split_const (x
, &base
, &offset
);
2014 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
)
2015 && type
!= SYMBOL_FORCE_TO_MEM
)
2017 /* The same optimization as for CONST_INT. */
2018 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2021 /* If MIPS16 constant pools live in the text section, they should
2022 not refer to anything that might need run-time relocation. */
2023 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2027 /* TLS symbols must be computed by mips_legitimize_move. */
2028 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2034 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2035 constants when we're using a per-function constant pool. */
2038 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2039 const_rtx x ATTRIBUTE_UNUSED
)
2041 return !TARGET_MIPS16_PCREL_LOADS
;
2044 /* Return true if register REGNO is a valid base register for mode MODE.
2045 STRICT_P is true if REG_OK_STRICT is in effect. */
2048 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2051 if (!HARD_REGISTER_NUM_P (regno
))
2055 regno
= reg_renumber
[regno
];
2058 /* These fake registers will be eliminated to either the stack or
2059 hard frame pointer, both of which are usually valid base registers.
2060 Reload deals with the cases where the eliminated form isn't valid. */
2061 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2064 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2065 values, nothing smaller. There are two problems here:
2067 (a) Instantiating virtual registers can introduce new uses of the
2068 stack pointer. If these virtual registers are valid addresses,
2069 the stack pointer should be too.
2071 (b) Most uses of the stack pointer are not made explicit until
2072 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2073 We don't know until that stage whether we'll be eliminating to the
2074 stack pointer (which needs the restriction) or the hard frame
2075 pointer (which doesn't).
2077 All in all, it seems more consistent to only enforce this restriction
2078 during and after reload. */
2079 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2080 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2082 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2085 /* Return true if X is a valid base register for mode MODE.
2086 STRICT_P is true if REG_OK_STRICT is in effect. */
2089 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2091 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2095 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2098 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2099 can address a value of mode MODE. */
2102 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2104 /* Check that X is a signed 16-bit number. */
2105 if (!const_arith_operand (x
, Pmode
))
2108 /* We may need to split multiword moves, so make sure that every word
2110 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2111 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2117 /* Return true if a LO_SUM can address a value of mode MODE when the
2118 LO_SUM symbol has type SYMBOL_TYPE. */
2121 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2123 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2125 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2128 /* Check that there is a known low-part relocation. */
2129 if (mips_lo_relocs
[symbol_type
] == NULL
)
2132 /* We may need to split multiword moves, so make sure that each word
2133 can be accessed without inducing a carry. This is mainly needed
2134 for o64, which has historically only guaranteed 64-bit alignment
2135 for 128-bit types. */
2136 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2137 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2143 /* Return true if X is a valid address for machine mode MODE. If it is,
2144 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2148 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2149 enum machine_mode mode
, bool strict_p
)
2151 switch (GET_CODE (x
))
2155 info
->type
= ADDRESS_REG
;
2157 info
->offset
= const0_rtx
;
2158 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2161 info
->type
= ADDRESS_REG
;
2162 info
->reg
= XEXP (x
, 0);
2163 info
->offset
= XEXP (x
, 1);
2164 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2165 && mips_valid_offset_p (info
->offset
, mode
));
2168 info
->type
= ADDRESS_LO_SUM
;
2169 info
->reg
= XEXP (x
, 0);
2170 info
->offset
= XEXP (x
, 1);
2171 /* We have to trust the creator of the LO_SUM to do something vaguely
2172 sane. Target-independent code that creates a LO_SUM should also
2173 create and verify the matching HIGH. Target-independent code that
2174 adds an offset to a LO_SUM must prove that the offset will not
2175 induce a carry. Failure to do either of these things would be
2176 a bug, and we are not required to check for it here. The MIPS
2177 backend itself should only create LO_SUMs for valid symbolic
2178 constants, with the high part being either a HIGH or a copy
2181 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2182 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2183 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2186 /* Small-integer addresses don't occur very often, but they
2187 are legitimate if $0 is a valid base register. */
2188 info
->type
= ADDRESS_CONST_INT
;
2189 return !TARGET_MIPS16
&& SMALL_INT (x
);
2194 info
->type
= ADDRESS_SYMBOLIC
;
2195 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2197 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2198 && !mips_split_p
[info
->symbol_type
]);
2205 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2208 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2210 struct mips_address_info addr
;
2212 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2215 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2218 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2220 struct mips_address_info addr
;
2222 return (mips_classify_address (&addr
, x
, mode
, false)
2223 && addr
.type
== ADDRESS_REG
2224 && addr
.reg
== stack_pointer_rtx
);
2227 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2228 address instruction. Note that such addresses are not considered
2229 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2230 is so restricted. */
2233 mips_lwxs_address_p (rtx addr
)
2236 && GET_CODE (addr
) == PLUS
2237 && REG_P (XEXP (addr
, 1)))
2239 rtx offset
= XEXP (addr
, 0);
2240 if (GET_CODE (offset
) == MULT
2241 && REG_P (XEXP (offset
, 0))
2242 && CONST_INT_P (XEXP (offset
, 1))
2243 && INTVAL (XEXP (offset
, 1)) == 4)
2249 /* Return true if a value at OFFSET bytes from base register BASE can be
2250 accessed using an unextended MIPS16 instruction. MODE is the mode of
2253 Usually the offset in an unextended instruction is a 5-bit field.
2254 The offset is unsigned and shifted left once for LH and SH, twice
2255 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2256 an 8-bit immediate field that's shifted left twice. */
2259 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2260 unsigned HOST_WIDE_INT offset
)
2262 if (offset
% GET_MODE_SIZE (mode
) == 0)
2264 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2265 return offset
< 256U * GET_MODE_SIZE (mode
);
2266 return offset
< 32U * GET_MODE_SIZE (mode
);
2271 /* Return the number of instructions needed to load or store a value
2272 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2273 Assume that multiword moves may need to be split into word moves
2274 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2277 For MIPS16 code, count extended instructions as two instructions. */
2280 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2282 struct mips_address_info addr
;
2285 /* BLKmode is used for single unaligned loads and stores and should
2286 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2287 meaningless, so we have to single it out as a special case one way
2289 if (mode
!= BLKmode
&& might_split_p
)
2290 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2294 if (mips_classify_address (&addr
, x
, mode
, false))
2299 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2300 UINTVAL (addr
.offset
)))
2304 case ADDRESS_LO_SUM
:
2305 return TARGET_MIPS16
? factor
* 2 : factor
;
2307 case ADDRESS_CONST_INT
:
2310 case ADDRESS_SYMBOLIC
:
2311 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2316 /* Return the number of instructions needed to load constant X.
2317 Return 0 if X isn't a valid constant. */
2320 mips_const_insns (rtx x
)
2322 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2323 enum mips_symbol_type symbol_type
;
2326 switch (GET_CODE (x
))
2329 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2331 || !mips_split_p
[symbol_type
])
2334 /* This is simply an LUI for normal mode. It is an extended
2335 LI followed by an extended SLL for MIPS16. */
2336 return TARGET_MIPS16
? 4 : 1;
2340 /* Unsigned 8-bit constants can be loaded using an unextended
2341 LI instruction. Unsigned 16-bit constants can be loaded
2342 using an extended LI. Negative constants must be loaded
2343 using LI and then negated. */
2344 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2345 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2346 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2347 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2350 return mips_build_integer (codes
, INTVAL (x
));
2354 /* Allow zeros for normal mode, where we can use $0. */
2355 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2361 /* See if we can refer to X directly. */
2362 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2363 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2365 /* Otherwise try splitting the constant into a base and offset.
2366 If the offset is a 16-bit value, we can load the base address
2367 into a register and then use (D)ADDIU to add in the offset.
2368 If the offset is larger, we can load the base and offset
2369 into separate registers and add them together with (D)ADDU.
2370 However, the latter is only possible before reload; during
2371 and after reload, we must have the option of forcing the
2372 constant into the pool instead. */
2373 split_const (x
, &x
, &offset
);
2376 int n
= mips_const_insns (x
);
2379 if (SMALL_INT (offset
))
2381 else if (!targetm
.cannot_force_const_mem (x
))
2382 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2389 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2397 /* X is a doubleword constant that can be handled by splitting it into
2398 two words and loading each word separately. Return the number of
2399 instructions required to do this. */
2402 mips_split_const_insns (rtx x
)
2404 unsigned int low
, high
;
2406 low
= mips_const_insns (mips_subword (x
, false));
2407 high
= mips_const_insns (mips_subword (x
, true));
2408 gcc_assert (low
> 0 && high
> 0);
2412 /* Return the number of instructions needed to implement INSN,
2413 given that it loads from or stores to MEM. Count extended
2414 MIPS16 instructions as two instructions. */
2417 mips_load_store_insns (rtx mem
, rtx insn
)
2419 enum machine_mode mode
;
2423 gcc_assert (MEM_P (mem
));
2424 mode
= GET_MODE (mem
);
2426 /* Try to prove that INSN does not need to be split. */
2427 might_split_p
= true;
2428 if (GET_MODE_BITSIZE (mode
) == 64)
2430 set
= single_set (insn
);
2431 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2432 might_split_p
= false;
2435 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2438 /* Return the number of instructions needed for an integer division. */
2441 mips_idiv_insns (void)
2446 if (TARGET_CHECK_ZERO_DIV
)
2448 if (GENERATE_DIVIDE_TRAPS
)
2454 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2459 /* Emit a move from SRC to DEST. Assume that the move expanders can
2460 handle all moves if !can_create_pseudo_p (). The distinction is
2461 important because, unlike emit_move_insn, the move expanders know
2462 how to force Pmode objects into the constant pool even when the
2463 constant pool address is not itself legitimate. */
2466 mips_emit_move (rtx dest
, rtx src
)
2468 return (can_create_pseudo_p ()
2469 ? emit_move_insn (dest
, src
)
2470 : emit_move_insn_1 (dest
, src
));
2473 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2476 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2478 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2479 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2482 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2483 Return that new register. */
2486 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2490 reg
= gen_reg_rtx (mode
);
2491 mips_emit_unary (code
, reg
, op0
);
2495 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2498 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2500 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2501 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2504 /* Compute (CODE OP0 OP1) and store the result in a new register
2505 of mode MODE. Return that new register. */
2508 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2512 reg
= gen_reg_rtx (mode
);
2513 mips_emit_binary (code
, reg
, op0
, op1
);
2517 /* Copy VALUE to a register and return that register. If new pseudos
2518 are allowed, copy it into a new register, otherwise use DEST. */
2521 mips_force_temporary (rtx dest
, rtx value
)
2523 if (can_create_pseudo_p ())
2524 return force_reg (Pmode
, value
);
2527 mips_emit_move (dest
, value
);
2532 /* Emit a call sequence with call pattern PATTERN and return the call
2533 instruction itself (which is not necessarily the last instruction
2534 emitted). ORIG_ADDR is the original, unlegitimized address,
2535 ADDR is the legitimized form, and LAZY_P is true if the call
2536 address is lazily-bound. */
2539 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2543 insn
= emit_call_insn (pattern
);
2545 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2547 /* MIPS16 JALRs only take MIPS16 registers. If the target
2548 function requires $25 to be valid on entry, we must copy it
2549 there separately. The move instruction can be put in the
2550 call's delay slot. */
2551 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2552 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2553 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2557 /* Lazy-binding stubs require $gp to be valid on entry. */
2558 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2562 /* See the comment above load_call<mode> for details. */
2563 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2564 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2565 emit_insn (gen_update_got_version ());
2570 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2571 then add CONST_INT OFFSET to the result. */
2574 mips_unspec_address_offset (rtx base
, rtx offset
,
2575 enum mips_symbol_type symbol_type
)
2577 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2578 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2579 if (offset
!= const0_rtx
)
2580 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2581 return gen_rtx_CONST (Pmode
, base
);
2584 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2585 type SYMBOL_TYPE. */
2588 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2592 split_const (address
, &base
, &offset
);
2593 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2596 /* If OP is an UNSPEC address, return the address to which it refers,
2597 otherwise return OP itself. */
2600 mips_strip_unspec_address (rtx op
)
2604 split_const (op
, &base
, &offset
);
2605 if (UNSPEC_ADDRESS_P (base
))
2606 op
= plus_constant (UNSPEC_ADDRESS (base
), INTVAL (offset
));
2610 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2611 high part to BASE and return the result. Just return BASE otherwise.
2612 TEMP is as for mips_force_temporary.
2614 The returned expression can be used as the first operand to a LO_SUM. */
2617 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2618 enum mips_symbol_type symbol_type
)
2620 if (mips_split_p
[symbol_type
])
2622 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2623 addr
= mips_force_temporary (temp
, addr
);
2624 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2629 /* Return an instruction that copies $gp into register REG. We want
2630 GCC to treat the register's value as constant, so that its value
2631 can be rematerialized on demand. */
2634 gen_load_const_gp (rtx reg
)
2636 return (Pmode
== SImode
2637 ? gen_load_const_gp_si (reg
)
2638 : gen_load_const_gp_di (reg
));
2641 /* Return a pseudo register that contains the value of $gp throughout
2642 the current function. Such registers are needed by MIPS16 functions,
2643 for which $gp itself is not a valid base register or addition operand. */
2646 mips16_gp_pseudo_reg (void)
2648 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2649 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2651 /* Don't emit an instruction to initialize the pseudo register if
2652 we are being called from the tree optimizers' cost-calculation
2654 if (!cfun
->machine
->initialized_mips16_gp_pseudo_p
2655 && (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
))
2659 push_topmost_sequence ();
2661 scan
= get_insns ();
2662 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2663 scan
= NEXT_INSN (scan
);
2665 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2666 emit_insn_after (insn
, scan
);
2668 pop_topmost_sequence ();
2670 cfun
->machine
->initialized_mips16_gp_pseudo_p
= true;
2673 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2676 /* Return a base register that holds pic_offset_table_rtx.
2677 TEMP, if nonnull, is a scratch Pmode base register. */
2680 mips_pic_base_register (rtx temp
)
2683 return pic_offset_table_rtx
;
2685 if (can_create_pseudo_p ())
2686 return mips16_gp_pseudo_reg ();
2689 /* The first post-reload split exposes all references to $gp
2690 (both uses and definitions). All references must remain
2691 explicit after that point.
2693 It is safe to introduce uses of $gp at any time, so for
2694 simplicity, we do that before the split too. */
2695 mips_emit_move (temp
, pic_offset_table_rtx
);
2697 emit_insn (gen_load_const_gp (temp
));
2701 /* Return the RHS of a load_call<mode> insn. */
2704 mips_unspec_call (rtx reg
, rtx symbol
)
2708 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2709 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2712 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2713 reference. Return NULL_RTX otherwise. */
2716 mips_strip_unspec_call (rtx src
)
2718 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2719 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2723 /* Create and return a GOT reference of type TYPE for address ADDR.
2724 TEMP, if nonnull, is a scratch Pmode base register. */
2727 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2729 rtx base
, high
, lo_sum_symbol
;
2731 base
= mips_pic_base_register (temp
);
2733 /* If we used the temporary register to load $gp, we can't use
2734 it for the high part as well. */
2735 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2738 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2739 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2741 if (type
== SYMBOL_GOTOFF_CALL
)
2742 return mips_unspec_call (high
, lo_sum_symbol
);
2744 return (Pmode
== SImode
2745 ? gen_unspec_gotsi (high
, lo_sum_symbol
)
2746 : gen_unspec_gotdi (high
, lo_sum_symbol
));
2749 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2750 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2751 constant in that context and can be split into high and low parts.
2752 If so, and if LOW_OUT is nonnull, emit the high part and store the
2753 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2755 TEMP is as for mips_force_temporary and is used to load the high
2756 part into a register.
2758 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2759 a legitimize SET_SRC for an .md pattern, otherwise the low part
2760 is guaranteed to be a legitimate address for mode MODE. */
2763 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2765 enum mips_symbol_context context
;
2766 enum mips_symbol_type symbol_type
;
2769 context
= (mode
== MAX_MACHINE_MODE
2770 ? SYMBOL_CONTEXT_LEA
2771 : SYMBOL_CONTEXT_MEM
);
2772 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2774 addr
= XEXP (addr
, 0);
2775 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2776 && mips_symbol_insns (symbol_type
, mode
) > 0
2777 && mips_split_hi_p
[symbol_type
])
2780 switch (symbol_type
)
2782 case SYMBOL_GOT_PAGE_OFST
:
2783 /* The high part of a page/ofst pair is loaded from the GOT. */
2784 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2795 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2796 && mips_symbol_insns (symbol_type
, mode
) > 0
2797 && mips_split_p
[symbol_type
])
2800 switch (symbol_type
)
2802 case SYMBOL_GOT_DISP
:
2803 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2804 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2807 case SYMBOL_GP_RELATIVE
:
2808 high
= mips_pic_base_register (temp
);
2809 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2813 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2814 high
= mips_force_temporary (temp
, high
);
2815 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2824 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2825 mips_force_temporary; it is only needed when OFFSET is not a
2829 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2831 if (!SMALL_OPERAND (offset
))
2837 /* Load the full offset into a register so that we can use
2838 an unextended instruction for the address itself. */
2839 high
= GEN_INT (offset
);
2844 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2845 The addition inside the macro CONST_HIGH_PART may cause an
2846 overflow, so we need to force a sign-extension check. */
2847 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
2848 offset
= CONST_LOW_PART (offset
);
2850 high
= mips_force_temporary (temp
, high
);
2851 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2853 return plus_constant (reg
, offset
);
2856 /* The __tls_get_attr symbol. */
2857 static GTY(()) rtx mips_tls_symbol
;
2859 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2860 the TLS symbol we are referencing and TYPE is the symbol type to use
2861 (either global dynamic or local dynamic). V0 is an RTX for the
2862 return value location. */
2865 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2869 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2871 if (!mips_tls_symbol
)
2872 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2874 loc
= mips_unspec_address (sym
, type
);
2878 emit_insn (gen_rtx_SET (Pmode
, a0
,
2879 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2880 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
2881 const0_rtx
, NULL_RTX
, false);
2882 RTL_CONST_CALL_P (insn
) = 1;
2883 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2884 insn
= get_insns ();
2891 /* Return a pseudo register that contains the current thread pointer. */
2898 tp
= gen_reg_rtx (Pmode
);
2899 if (Pmode
== DImode
)
2900 emit_insn (gen_tls_get_tp_di (tp
));
2902 emit_insn (gen_tls_get_tp_si (tp
));
2906 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2907 its address. The return value will be both a valid address and a valid
2908 SET_SRC (either a REG or a LO_SUM). */
2911 mips_legitimize_tls_address (rtx loc
)
2913 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
;
2914 enum tls_model model
;
2918 sorry ("MIPS16 TLS");
2919 return gen_reg_rtx (Pmode
);
2922 model
= SYMBOL_REF_TLS_MODEL (loc
);
2923 /* Only TARGET_ABICALLS code can have more than one module; other
2924 code must be be static and should not use a GOT. All TLS models
2925 reduce to local exec in this situation. */
2926 if (!TARGET_ABICALLS
)
2927 model
= TLS_MODEL_LOCAL_EXEC
;
2931 case TLS_MODEL_GLOBAL_DYNAMIC
:
2932 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2933 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2934 dest
= gen_reg_rtx (Pmode
);
2935 emit_libcall_block (insn
, dest
, v0
, loc
);
2938 case TLS_MODEL_LOCAL_DYNAMIC
:
2939 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2940 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2941 tmp1
= gen_reg_rtx (Pmode
);
2943 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2944 share the LDM result with other LD model accesses. */
2945 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2947 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2949 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2950 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2951 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2954 case TLS_MODEL_INITIAL_EXEC
:
2955 tp
= mips_get_tp ();
2956 tmp1
= gen_reg_rtx (Pmode
);
2957 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2958 if (Pmode
== DImode
)
2959 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2961 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2962 dest
= gen_reg_rtx (Pmode
);
2963 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
2966 case TLS_MODEL_LOCAL_EXEC
:
2967 tp
= mips_get_tp ();
2968 tmp1
= mips_unspec_offset_high (NULL
, tp
, loc
, SYMBOL_TPREL
);
2969 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2970 mips_unspec_address (loc
, SYMBOL_TPREL
));
2979 /* If X is not a valid address for mode MODE, force it into a register. */
2982 mips_force_address (rtx x
, enum machine_mode mode
)
2984 if (!mips_legitimate_address_p (mode
, x
, false))
2985 x
= force_reg (Pmode
, x
);
2989 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2990 be legitimized in a way that the generic machinery might not expect,
2991 return a new address, otherwise return NULL. MODE is the mode of
2992 the memory being accessed. */
2995 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
2996 enum machine_mode mode
)
2999 HOST_WIDE_INT offset
;
3001 if (mips_tls_symbol_p (x
))
3002 return mips_legitimize_tls_address (x
);
3004 /* See if the address can split into a high part and a LO_SUM. */
3005 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3006 return mips_force_address (addr
, mode
);
3008 /* Handle BASE + OFFSET using mips_add_offset. */
3009 mips_split_plus (x
, &base
, &offset
);
3012 if (!mips_valid_base_register_p (base
, mode
, false))
3013 base
= copy_to_mode_reg (Pmode
, base
);
3014 addr
= mips_add_offset (NULL
, base
, offset
);
3015 return mips_force_address (addr
, mode
);
3021 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3024 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3026 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3027 enum machine_mode mode
;
3028 unsigned int i
, num_ops
;
3031 mode
= GET_MODE (dest
);
3032 num_ops
= mips_build_integer (codes
, value
);
3034 /* Apply each binary operation to X. Invariant: X is a legitimate
3035 source operand for a SET pattern. */
3036 x
= GEN_INT (codes
[0].value
);
3037 for (i
= 1; i
< num_ops
; i
++)
3039 if (!can_create_pseudo_p ())
3041 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3045 x
= force_reg (mode
, x
);
3046 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3049 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3052 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3053 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3057 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3061 /* Split moves of big integers into smaller pieces. */
3062 if (splittable_const_int_operand (src
, mode
))
3064 mips_move_integer (dest
, dest
, INTVAL (src
));
3068 /* Split moves of symbolic constants into high/low pairs. */
3069 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3071 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3075 /* Generate the appropriate access sequences for TLS symbols. */
3076 if (mips_tls_symbol_p (src
))
3078 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3082 /* If we have (const (plus symbol offset)), and that expression cannot
3083 be forced into memory, load the symbol first and add in the offset.
3084 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3085 forced into memory, as it usually produces better code. */
3086 split_const (src
, &base
, &offset
);
3087 if (offset
!= const0_rtx
3088 && (targetm
.cannot_force_const_mem (src
)
3089 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3091 base
= mips_force_temporary (dest
, base
);
3092 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3096 src
= force_const_mem (mode
, src
);
3098 /* When using explicit relocs, constant pool references are sometimes
3099 not legitimate addresses. */
3100 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3101 mips_emit_move (dest
, src
);
3104 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3105 sequence that is valid. */
3108 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3110 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3112 mips_emit_move (dest
, force_reg (mode
, src
));
3116 /* We need to deal with constants that would be legitimate
3117 immediate_operands but aren't legitimate move_operands. */
3118 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3120 mips_legitimize_const_move (mode
, dest
, src
);
3121 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3127 /* Return true if value X in context CONTEXT is a small-data address
3128 that can be rewritten as a LO_SUM. */
3131 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3133 enum mips_symbol_type symbol_type
;
3135 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3136 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3137 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3138 && symbol_type
== SYMBOL_GP_RELATIVE
);
3141 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3142 containing MEM, or null if none. */
3145 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3147 enum mips_symbol_context context
;
3149 if (GET_CODE (*loc
) == LO_SUM
)
3154 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3159 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3160 return mips_rewrite_small_data_p (*loc
, context
);
3163 /* Return true if OP refers to small data symbols directly, not through
3167 mips_small_data_pattern_p (rtx op
)
3169 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3172 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3173 DATA is the containing MEM, or null if none. */
3176 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3178 enum mips_symbol_context context
;
3182 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3186 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3187 if (mips_rewrite_small_data_p (*loc
, context
))
3188 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3190 if (GET_CODE (*loc
) == LO_SUM
)
3196 /* Rewrite instruction pattern PATTERN so that it refers to small data
3197 using explicit relocations. */
3200 mips_rewrite_small_data (rtx pattern
)
3202 pattern
= copy_insn (pattern
);
3203 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3207 /* We need a lot of little routines to check the range of MIPS16 immediate
3211 m16_check_op (rtx op
, int low
, int high
, int mask
)
3213 return (CONST_INT_P (op
)
3214 && IN_RANGE (INTVAL (op
), low
, high
)
3215 && (INTVAL (op
) & mask
) == 0);
3219 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3221 return m16_check_op (op
, 0x1, 0x8, 0);
3225 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3227 return m16_check_op (op
, -0x8, 0x7, 0);
3231 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3233 return m16_check_op (op
, -0x7, 0x8, 0);
3237 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3239 return m16_check_op (op
, -0x10, 0xf, 0);
3243 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3245 return m16_check_op (op
, -0xf, 0x10, 0);
3249 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3251 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
3255 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3257 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
3261 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3263 return m16_check_op (op
, -0x80, 0x7f, 0);
3267 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3269 return m16_check_op (op
, -0x7f, 0x80, 0);
3273 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3275 return m16_check_op (op
, 0x0, 0xff, 0);
3279 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3281 return m16_check_op (op
, -0xff, 0x0, 0);
3285 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3287 return m16_check_op (op
, -0x1, 0xfe, 0);
3291 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3293 return m16_check_op (op
, 0x0, 0xff << 2, 3);
3297 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3299 return m16_check_op (op
, -0xff << 2, 0x0, 3);
3303 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3305 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
3309 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3311 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
3314 /* The cost of loading values from the constant pool. It should be
3315 larger than the cost of any constant we want to synthesize inline. */
3316 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3318 /* Return the cost of X when used as an operand to the MIPS16 instruction
3319 that implements CODE. Return -1 if there is no such instruction, or if
3320 X is not a valid immediate operand for it. */
3323 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3330 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3331 other shifts are extended. The shift patterns truncate the shift
3332 count to the right size, so there are no out-of-range values. */
3333 if (IN_RANGE (x
, 1, 8))
3335 return COSTS_N_INSNS (1);
3338 if (IN_RANGE (x
, -128, 127))
3340 if (SMALL_OPERAND (x
))
3341 return COSTS_N_INSNS (1);
3345 /* Like LE, but reject the always-true case. */
3349 /* We add 1 to the immediate and use SLT. */
3352 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3355 if (IN_RANGE (x
, 0, 255))
3357 if (SMALL_OPERAND_UNSIGNED (x
))
3358 return COSTS_N_INSNS (1);
3363 /* Equality comparisons with 0 are cheap. */
3373 /* Return true if there is a non-MIPS16 instruction that implements CODE
3374 and if that instruction accepts X as an immediate operand. */
3377 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3384 /* All shift counts are truncated to a valid constant. */
3389 /* Likewise rotates, if the target supports rotates at all. */
3395 /* These instructions take 16-bit unsigned immediates. */
3396 return SMALL_OPERAND_UNSIGNED (x
);
3401 /* These instructions take 16-bit signed immediates. */
3402 return SMALL_OPERAND (x
);
3408 /* The "immediate" forms of these instructions are really
3409 implemented as comparisons with register 0. */
3414 /* Likewise, meaning that the only valid immediate operand is 1. */
3418 /* We add 1 to the immediate and use SLT. */
3419 return SMALL_OPERAND (x
+ 1);
3422 /* Likewise SLTU, but reject the always-true case. */
3423 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3427 /* The bit position and size are immediate operands. */
3428 return ISA_HAS_EXT_INS
;
3431 /* By default assume that $0 can be used for 0. */
3436 /* Return the cost of binary operation X, given that the instruction
3437 sequence for a word-sized or smaller operation has cost SINGLE_COST
3438 and that the sequence of a double-word operation has cost DOUBLE_COST.
3439 If SPEED is true, optimize for speed otherwise optimize for size. */
3442 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3446 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3451 + rtx_cost (XEXP (x
, 0), SET
, speed
)
3452 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), speed
));
3455 /* Return the cost of floating-point multiplications of mode MODE. */
3458 mips_fp_mult_cost (enum machine_mode mode
)
3460 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3463 /* Return the cost of floating-point divisions of mode MODE. */
3466 mips_fp_div_cost (enum machine_mode mode
)
3468 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3471 /* Return the cost of sign-extending OP to mode MODE, not including the
3472 cost of OP itself. */
3475 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3478 /* Extended loads are as cheap as unextended ones. */
3481 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3482 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3485 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3486 /* We can use SEB or SEH. */
3487 return COSTS_N_INSNS (1);
3489 /* We need to use a shift left and a shift right. */
3490 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3493 /* Return the cost of zero-extending OP to mode MODE, not including the
3494 cost of OP itself. */
3497 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3500 /* Extended loads are as cheap as unextended ones. */
3503 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3504 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3505 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3507 if (GENERATE_MIPS16E
)
3508 /* We can use ZEB or ZEH. */
3509 return COSTS_N_INSNS (1);
3512 /* We need to load 0xff or 0xffff into a register and use AND. */
3513 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3515 /* We can use ANDI. */
3516 return COSTS_N_INSNS (1);
3519 /* Implement TARGET_RTX_COSTS. */
3522 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
, bool speed
)
3524 enum machine_mode mode
= GET_MODE (x
);
3525 bool float_mode_p
= FLOAT_MODE_P (mode
);
3529 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3530 appear in the instruction stream, and the cost of a comparison is
3531 really the cost of the branch or scc condition. At the time of
3532 writing, GCC only uses an explicit outer COMPARE code when optabs
3533 is testing whether a constant is expensive enough to force into a
3534 register. We want optabs to pass such constants through the MIPS
3535 expanders instead, so make all constants very cheap here. */
3536 if (outer_code
== COMPARE
)
3538 gcc_assert (CONSTANT_P (x
));
3546 /* Treat *clear_upper32-style ANDs as having zero cost in the
3547 second operand. The cost is entirely in the first operand.
3549 ??? This is needed because we would otherwise try to CSE
3550 the constant operand. Although that's the right thing for
3551 instructions that continue to be a register operation throughout
3552 compilation, it is disastrous for instructions that could
3553 later be converted into a memory operation. */
3555 && outer_code
== AND
3556 && UINTVAL (x
) == 0xffffffff)
3564 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3573 /* When not optimizing for size, we care more about the cost
3574 of hot code, and hot code is often in a loop. If a constant
3575 operand needs to be forced into a register, we will often be
3576 able to hoist the constant load out of the loop, so the load
3577 should not contribute to the cost. */
3578 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3590 if (force_to_mem_operand (x
, VOIDmode
))
3592 *total
= COSTS_N_INSNS (1);
3595 cost
= mips_const_insns (x
);
3598 /* If the constant is likely to be stored in a GPR, SETs of
3599 single-insn constants are as cheap as register sets; we
3600 never want to CSE them.
3602 Don't reduce the cost of storing a floating-point zero in
3603 FPRs. If we have a zero in an FPR for other reasons, we
3604 can get better cfg-cleanup and delayed-branch results by
3605 using it consistently, rather than using $0 sometimes and
3606 an FPR at other times. Also, moves between floating-point
3607 registers are sometimes cheaper than (D)MTC1 $0. */
3609 && outer_code
== SET
3610 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3612 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3613 want to CSE the constant itself. It is usually better to
3614 have N copies of the last operation in the sequence and one
3615 shared copy of the other operations. (Note that this is
3616 not true for MIPS16 code, where the final operation in the
3617 sequence is often an extended instruction.)
3619 Also, if we have a CONST_INT, we don't know whether it is
3620 for a word or doubleword operation, so we cannot rely on
3621 the result of mips_build_integer. */
3622 else if (!TARGET_MIPS16
3623 && (outer_code
== SET
|| mode
== VOIDmode
))
3625 *total
= COSTS_N_INSNS (cost
);
3628 /* The value will need to be fetched from the constant pool. */
3629 *total
= CONSTANT_POOL_COST
;
3633 /* If the address is legitimate, return the number of
3634 instructions it needs. */
3636 cost
= mips_address_insns (addr
, mode
, true);
3639 *total
= COSTS_N_INSNS (cost
+ 1);
3642 /* Check for a scaled indexed address. */
3643 if (mips_lwxs_address_p (addr
))
3645 *total
= COSTS_N_INSNS (2);
3648 /* Otherwise use the default handling. */
3652 *total
= COSTS_N_INSNS (6);
3656 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3660 /* Check for a *clear_upper32 pattern and treat it like a zero
3661 extension. See the pattern's comment for details. */
3664 && CONST_INT_P (XEXP (x
, 1))
3665 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3667 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3668 + rtx_cost (XEXP (x
, 0), SET
, speed
));
3675 /* Double-word operations use two single-word operations. */
3676 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3685 if (CONSTANT_P (XEXP (x
, 1)))
3686 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3689 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3695 *total
= mips_cost
->fp_add
;
3697 *total
= COSTS_N_INSNS (4);
3701 /* Low-part immediates need an extended MIPS16 instruction. */
3702 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3703 + rtx_cost (XEXP (x
, 0), SET
, speed
));
3718 /* Branch comparisons have VOIDmode, so use the first operand's
3720 mode
= GET_MODE (XEXP (x
, 0));
3721 if (FLOAT_MODE_P (mode
))
3723 *total
= mips_cost
->fp_add
;
3726 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3732 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3733 && TARGET_FUSED_MADD
3734 && !HONOR_NANS (mode
)
3735 && !HONOR_SIGNED_ZEROS (mode
))
3737 /* See if we can use NMADD or NMSUB. See mips.md for the
3738 associated patterns. */
3739 rtx op0
= XEXP (x
, 0);
3740 rtx op1
= XEXP (x
, 1);
3741 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3743 *total
= (mips_fp_mult_cost (mode
)
3744 + rtx_cost (XEXP (XEXP (op0
, 0), 0), SET
, speed
)
3745 + rtx_cost (XEXP (op0
, 1), SET
, speed
)
3746 + rtx_cost (op1
, SET
, speed
));
3749 if (GET_CODE (op1
) == MULT
)
3751 *total
= (mips_fp_mult_cost (mode
)
3752 + rtx_cost (op0
, SET
, speed
)
3753 + rtx_cost (XEXP (op1
, 0), SET
, speed
)
3754 + rtx_cost (XEXP (op1
, 1), SET
, speed
));
3763 /* If this is part of a MADD or MSUB, treat the PLUS as
3766 && TARGET_FUSED_MADD
3767 && GET_CODE (XEXP (x
, 0)) == MULT
)
3770 *total
= mips_cost
->fp_add
;
3774 /* Double-word operations require three single-word operations and
3775 an SLTU. The MIPS16 version then needs to move the result of
3776 the SLTU from $24 to a MIPS16 register. */
3777 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3778 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3784 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3785 && TARGET_FUSED_MADD
3786 && !HONOR_NANS (mode
)
3787 && HONOR_SIGNED_ZEROS (mode
))
3789 /* See if we can use NMADD or NMSUB. See mips.md for the
3790 associated patterns. */
3791 rtx op
= XEXP (x
, 0);
3792 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3793 && GET_CODE (XEXP (op
, 0)) == MULT
)
3795 *total
= (mips_fp_mult_cost (mode
)
3796 + rtx_cost (XEXP (XEXP (op
, 0), 0), SET
, speed
)
3797 + rtx_cost (XEXP (XEXP (op
, 0), 1), SET
, speed
)
3798 + rtx_cost (XEXP (op
, 1), SET
, speed
));
3804 *total
= mips_cost
->fp_add
;
3806 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3811 *total
= mips_fp_mult_cost (mode
);
3812 else if (mode
== DImode
&& !TARGET_64BIT
)
3813 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3814 where the mulsidi3 always includes an MFHI and an MFLO. */
3816 ? mips_cost
->int_mult_si
* 3 + 6
3817 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3819 *total
= (ISA_HAS_MUL3
? 1 : 2);
3820 else if (mode
== DImode
)
3821 *total
= mips_cost
->int_mult_di
;
3823 *total
= mips_cost
->int_mult_si
;
3827 /* Check for a reciprocal. */
3830 && flag_unsafe_math_optimizations
3831 && XEXP (x
, 0) == CONST1_RTX (mode
))
3833 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3834 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3835 division as being free. */
3836 *total
= rtx_cost (XEXP (x
, 1), SET
, speed
);
3838 *total
= (mips_fp_div_cost (mode
)
3839 + rtx_cost (XEXP (x
, 1), SET
, speed
));
3848 *total
= mips_fp_div_cost (mode
);
3857 /* It is our responsibility to make division by a power of 2
3858 as cheap as 2 register additions if we want the division
3859 expanders to be used for such operations; see the setting
3860 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3861 should always produce shorter code than using
3862 expand_sdiv2_pow2. */
3864 && CONST_INT_P (XEXP (x
, 1))
3865 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3867 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), SET
, speed
);
3870 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3872 else if (mode
== DImode
)
3873 *total
= mips_cost
->int_div_di
;
3875 *total
= mips_cost
->int_div_si
;
3879 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3883 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3887 case UNSIGNED_FLOAT
:
3890 case FLOAT_TRUNCATE
:
3891 *total
= mips_cost
->fp_add
;
3899 /* Implement TARGET_ADDRESS_COST. */
3902 mips_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
3904 return mips_address_insns (addr
, SImode
, false);
3907 /* Information about a single instruction in a multi-instruction
3909 struct mips_multi_member
{
3910 /* True if this is a label, false if it is code. */
3913 /* The output_asm_insn format of the instruction. */
3916 /* The operands to the instruction. */
3917 rtx operands
[MAX_RECOG_OPERANDS
];
3919 typedef struct mips_multi_member mips_multi_member
;
3921 /* Vector definitions for the above. */
3922 DEF_VEC_O(mips_multi_member
);
3923 DEF_VEC_ALLOC_O(mips_multi_member
, heap
);
3925 /* The instructions that make up the current multi-insn sequence. */
3926 static VEC (mips_multi_member
, heap
) *mips_multi_members
;
3928 /* How many instructions (as opposed to labels) are in the current
3929 multi-insn sequence. */
3930 static unsigned int mips_multi_num_insns
;
3932 /* Start a new multi-insn sequence. */
3935 mips_multi_start (void)
3937 VEC_truncate (mips_multi_member
, mips_multi_members
, 0);
3938 mips_multi_num_insns
= 0;
3941 /* Add a new, uninitialized member to the current multi-insn sequence. */
3943 static struct mips_multi_member
*
3944 mips_multi_add (void)
3946 return VEC_safe_push (mips_multi_member
, heap
, mips_multi_members
, 0);
3949 /* Add a normal insn with the given asm format to the current multi-insn
3950 sequence. The other arguments are a null-terminated list of operands. */
3953 mips_multi_add_insn (const char *format
, ...)
3955 struct mips_multi_member
*member
;
3960 member
= mips_multi_add ();
3961 member
->is_label_p
= false;
3962 member
->format
= format
;
3963 va_start (ap
, format
);
3965 while ((op
= va_arg (ap
, rtx
)))
3966 member
->operands
[i
++] = op
;
3968 mips_multi_num_insns
++;
3971 /* Add the given label definition to the current multi-insn sequence.
3972 The definition should include the colon. */
3975 mips_multi_add_label (const char *label
)
3977 struct mips_multi_member
*member
;
3979 member
= mips_multi_add ();
3980 member
->is_label_p
= true;
3981 member
->format
= label
;
3984 /* Return the index of the last member of the current multi-insn sequence. */
3987 mips_multi_last_index (void)
3989 return VEC_length (mips_multi_member
, mips_multi_members
) - 1;
3992 /* Add a copy of an existing instruction to the current multi-insn
3993 sequence. I is the index of the instruction that should be copied. */
3996 mips_multi_copy_insn (unsigned int i
)
3998 struct mips_multi_member
*member
;
4000 member
= mips_multi_add ();
4001 memcpy (member
, VEC_index (mips_multi_member
, mips_multi_members
, i
),
4003 gcc_assert (!member
->is_label_p
);
4006 /* Change the operand of an existing instruction in the current
4007 multi-insn sequence. I is the index of the instruction,
4008 OP is the index of the operand, and X is the new value. */
4011 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4013 VEC_index (mips_multi_member
, mips_multi_members
, i
)->operands
[op
] = x
;
4016 /* Write out the asm code for the current multi-insn sequence. */
4019 mips_multi_write (void)
4021 struct mips_multi_member
*member
;
4024 FOR_EACH_VEC_ELT (mips_multi_member
, mips_multi_members
, i
, member
)
4025 if (member
->is_label_p
)
4026 fprintf (asm_out_file
, "%s\n", member
->format
);
4028 output_asm_insn (member
->format
, member
->operands
);
4031 /* Return one word of double-word value OP, taking into account the fixed
4032 endianness of certain registers. HIGH_P is true to select the high part,
4033 false to select the low part. */
4036 mips_subword (rtx op
, bool high_p
)
4038 unsigned int byte
, offset
;
4039 enum machine_mode mode
;
4041 mode
= GET_MODE (op
);
4042 if (mode
== VOIDmode
)
4043 mode
= TARGET_64BIT
? TImode
: DImode
;
4045 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4046 byte
= UNITS_PER_WORD
;
4050 if (FP_REG_RTX_P (op
))
4052 /* Paired FPRs are always ordered little-endian. */
4053 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4054 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4058 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4060 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4063 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4066 mips_split_64bit_move_p (rtx dest
, rtx src
)
4071 /* FPR-to-FPR moves can be done in a single instruction, if they're
4073 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4076 /* Check for floating-point loads and stores. */
4077 if (ISA_HAS_LDC1_SDC1
)
4079 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4081 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4087 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4088 this function handles 64-bit moves for which mips_split_64bit_move_p
4089 holds. For 64-bit targets, this function handles 128-bit moves. */
4092 mips_split_doubleword_move (rtx dest
, rtx src
)
4096 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4098 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4099 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4100 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4101 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4102 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4103 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4104 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4105 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4106 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4107 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4108 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4109 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4110 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4111 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4115 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4117 low_dest
= mips_subword (dest
, false);
4118 mips_emit_move (low_dest
, mips_subword (src
, false));
4120 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4122 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4124 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4126 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4128 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4130 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4134 /* The operation can be split into two normal moves. Decide in
4135 which order to do them. */
4136 low_dest
= mips_subword (dest
, false);
4137 if (REG_P (low_dest
)
4138 && reg_overlap_mentioned_p (low_dest
, src
))
4140 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4141 mips_emit_move (low_dest
, mips_subword (src
, false));
4145 mips_emit_move (low_dest
, mips_subword (src
, false));
4146 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4151 /* Return the appropriate instructions to move SRC into DEST. Assume
4152 that SRC is operand 1 and DEST is operand 0. */
4155 mips_output_move (rtx dest
, rtx src
)
4157 enum rtx_code dest_code
, src_code
;
4158 enum machine_mode mode
;
4159 enum mips_symbol_type symbol_type
;
4162 dest_code
= GET_CODE (dest
);
4163 src_code
= GET_CODE (src
);
4164 mode
= GET_MODE (dest
);
4165 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4167 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
4170 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4171 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4173 if (dest_code
== REG
)
4175 if (GP_REG_P (REGNO (dest
)))
4176 return "move\t%0,%z1";
4178 /* Moves to HI are handled by special .md insns. */
4179 if (REGNO (dest
) == LO_REGNUM
)
4182 if (DSP_ACC_REG_P (REGNO (dest
)))
4184 static char retval
[] = "mt__\t%z1,%q0";
4186 retval
[2] = reg_names
[REGNO (dest
)][4];
4187 retval
[3] = reg_names
[REGNO (dest
)][5];
4191 if (FP_REG_P (REGNO (dest
)))
4192 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4194 if (ALL_COP_REG_P (REGNO (dest
)))
4196 static char retval
[] = "dmtc_\t%z1,%0";
4198 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4199 return dbl_p
? retval
: retval
+ 1;
4202 if (dest_code
== MEM
)
4203 switch (GET_MODE_SIZE (mode
))
4205 case 1: return "sb\t%z1,%0";
4206 case 2: return "sh\t%z1,%0";
4207 case 4: return "sw\t%z1,%0";
4208 case 8: return "sd\t%z1,%0";
4211 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4213 if (src_code
== REG
)
4215 /* Moves from HI are handled by special .md insns. */
4216 if (REGNO (src
) == LO_REGNUM
)
4218 /* When generating VR4120 or VR4130 code, we use MACC and
4219 DMACC instead of MFLO. This avoids both the normal
4220 MIPS III HI/LO hazards and the errata related to
4223 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4227 if (DSP_ACC_REG_P (REGNO (src
)))
4229 static char retval
[] = "mf__\t%0,%q1";
4231 retval
[2] = reg_names
[REGNO (src
)][4];
4232 retval
[3] = reg_names
[REGNO (src
)][5];
4236 if (FP_REG_P (REGNO (src
)))
4237 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4239 if (ALL_COP_REG_P (REGNO (src
)))
4241 static char retval
[] = "dmfc_\t%0,%1";
4243 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4244 return dbl_p
? retval
: retval
+ 1;
4247 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
4248 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4251 if (src_code
== MEM
)
4252 switch (GET_MODE_SIZE (mode
))
4254 case 1: return "lbu\t%0,%1";
4255 case 2: return "lhu\t%0,%1";
4256 case 4: return "lw\t%0,%1";
4257 case 8: return "ld\t%0,%1";
4260 if (src_code
== CONST_INT
)
4262 /* Don't use the X format for the operand itself, because that
4263 will give out-of-range numbers for 64-bit hosts and 32-bit
4266 return "li\t%0,%1\t\t\t# %X1";
4268 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4271 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4275 if (src_code
== HIGH
)
4276 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4278 if (CONST_GP_P (src
))
4279 return "move\t%0,%1";
4281 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4282 && mips_lo_relocs
[symbol_type
] != 0)
4284 /* A signed 16-bit constant formed by applying a relocation
4285 operator to a symbolic address. */
4286 gcc_assert (!mips_split_p
[symbol_type
]);
4287 return "li\t%0,%R1";
4290 if (symbolic_operand (src
, VOIDmode
))
4292 gcc_assert (TARGET_MIPS16
4293 ? TARGET_MIPS16_TEXT_LOADS
4294 : !TARGET_EXPLICIT_RELOCS
);
4295 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4298 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4300 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4302 if (GET_MODE (dest
) == V2SFmode
)
4303 return "mov.ps\t%0,%1";
4305 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4308 if (dest_code
== MEM
)
4309 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4311 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4313 if (src_code
== MEM
)
4314 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4316 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4318 static char retval
[] = "l_c_\t%0,%1";
4320 retval
[1] = (dbl_p
? 'd' : 'w');
4321 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4324 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4326 static char retval
[] = "s_c_\t%1,%0";
4328 retval
[1] = (dbl_p
? 'd' : 'w');
4329 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4335 /* Return true if CMP1 is a suitable second operand for integer ordering
4336 test CODE. See also the *sCC patterns in mips.md. */
4339 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4345 return reg_or_0_operand (cmp1
, VOIDmode
);
4349 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4353 return arith_operand (cmp1
, VOIDmode
);
4356 return sle_operand (cmp1
, VOIDmode
);
4359 return sleu_operand (cmp1
, VOIDmode
);
4366 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4367 integer ordering test *CODE, or if an equivalent combination can
4368 be formed by adjusting *CODE and *CMP1. When returning true, update
4369 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4373 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4374 enum machine_mode mode
)
4376 HOST_WIDE_INT plus_one
;
4378 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4381 if (CONST_INT_P (*cmp1
))
4385 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4386 if (INTVAL (*cmp1
) < plus_one
)
4389 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4395 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4399 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4410 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4411 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4412 is nonnull, it's OK to set TARGET to the inverse of the result and
4413 flip *INVERT_PTR instead. */
4416 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4417 rtx target
, rtx cmp0
, rtx cmp1
)
4419 enum machine_mode mode
;
4421 /* First see if there is a MIPS instruction that can do this operation.
4422 If not, try doing the same for the inverse operation. If that also
4423 fails, force CMP1 into a register and try again. */
4424 mode
= GET_MODE (cmp0
);
4425 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4426 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4429 enum rtx_code inv_code
= reverse_condition (code
);
4430 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4432 cmp1
= force_reg (mode
, cmp1
);
4433 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4435 else if (invert_ptr
== 0)
4439 inv_target
= mips_force_binary (GET_MODE (target
),
4440 inv_code
, cmp0
, cmp1
);
4441 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4445 *invert_ptr
= !*invert_ptr
;
4446 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4451 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4452 The register will have the same mode as CMP0. */
4455 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4457 if (cmp1
== const0_rtx
)
4460 if (uns_arith_operand (cmp1
, VOIDmode
))
4461 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4462 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4464 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4465 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4468 /* Convert *CODE into a code that can be used in a floating-point
4469 scc instruction (C.cond.fmt). Return true if the values of
4470 the condition code registers will be inverted, with 0 indicating
4471 that the condition holds. */
4474 mips_reversed_fp_cond (enum rtx_code
*code
)
4481 *code
= reverse_condition_maybe_unordered (*code
);
4489 /* Convert a comparison into something that can be used in a branch or
4490 conditional move. On entry, *OP0 and *OP1 are the values being
4491 compared and *CODE is the code used to compare them.
4493 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4494 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4495 otherwise any standard branch condition can be used. The standard branch
4498 - EQ or NE between two registers.
4499 - any comparison between a register and zero. */
4502 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4507 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4509 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4511 else if (*code
== EQ
|| *code
== NE
)
4515 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4519 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4523 /* The comparison needs a separate scc instruction. Store the
4524 result of the scc in *OP0 and compare it against zero. */
4525 bool invert
= false;
4526 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4527 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4528 *code
= (invert
? EQ
: NE
);
4532 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4534 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4535 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4541 enum rtx_code cmp_code
;
4543 /* Floating-point tests use a separate C.cond.fmt comparison to
4544 set a condition code register. The branch or conditional move
4545 will then compare that register against zero.
4547 Set CMP_CODE to the code of the comparison instruction and
4548 *CODE to the code that the branch or move should use. */
4550 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4552 ? gen_reg_rtx (CCmode
)
4553 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4555 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4559 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4560 and OPERAND[3]. Store the result in OPERANDS[0].
4562 On 64-bit targets, the mode of the comparison and target will always be
4563 SImode, thus possibly narrower than that of the comparison's operands. */
4566 mips_expand_scc (rtx operands
[])
4568 rtx target
= operands
[0];
4569 enum rtx_code code
= GET_CODE (operands
[1]);
4570 rtx op0
= operands
[2];
4571 rtx op1
= operands
[3];
4573 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4575 if (code
== EQ
|| code
== NE
)
4578 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4579 mips_emit_binary (code
, target
, op0
, op1
);
4582 rtx zie
= mips_zero_if_equal (op0
, op1
);
4583 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4587 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4590 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4591 CODE and jump to OPERANDS[3] if the condition holds. */
4594 mips_expand_conditional_branch (rtx
*operands
)
4596 enum rtx_code code
= GET_CODE (operands
[0]);
4597 rtx op0
= operands
[1];
4598 rtx op1
= operands
[2];
4601 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4602 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4603 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4608 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4609 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4612 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4613 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4618 reversed_p
= mips_reversed_fp_cond (&cond
);
4619 cmp_result
= gen_reg_rtx (CCV2mode
);
4620 emit_insn (gen_scc_ps (cmp_result
,
4621 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4623 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4626 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4630 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4631 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4634 mips_expand_conditional_move (rtx
*operands
)
4637 enum rtx_code code
= GET_CODE (operands
[1]);
4638 rtx op0
= XEXP (operands
[1], 0);
4639 rtx op1
= XEXP (operands
[1], 1);
4641 mips_emit_compare (&code
, &op0
, &op1
, true);
4642 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4643 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4644 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4645 operands
[2], operands
[3])));
4648 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4651 mips_expand_conditional_trap (rtx comparison
)
4654 enum machine_mode mode
;
4657 /* MIPS conditional trap instructions don't have GT or LE flavors,
4658 so we must swap the operands and convert to LT and GE respectively. */
4659 code
= GET_CODE (comparison
);
4666 code
= swap_condition (code
);
4667 op0
= XEXP (comparison
, 1);
4668 op1
= XEXP (comparison
, 0);
4672 op0
= XEXP (comparison
, 0);
4673 op1
= XEXP (comparison
, 1);
4677 mode
= GET_MODE (XEXP (comparison
, 0));
4678 op0
= force_reg (mode
, op0
);
4679 if (!arith_operand (op1
, mode
))
4680 op1
= force_reg (mode
, op1
);
4682 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4683 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4687 /* Initialize *CUM for a call to a function of type FNTYPE. */
4690 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4692 memset (cum
, 0, sizeof (*cum
));
4693 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4694 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4697 /* Fill INFO with information about a single argument. CUM is the
4698 cumulative state for earlier arguments. MODE is the mode of this
4699 argument and TYPE is its type (if known). NAMED is true if this
4700 is a named (fixed) argument rather than a variable one. */
4703 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4704 enum machine_mode mode
, const_tree type
, bool named
)
4706 bool doubleword_aligned_p
;
4707 unsigned int num_bytes
, num_words
, max_regs
;
4709 /* Work out the size of the argument. */
4710 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4711 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4713 /* Decide whether it should go in a floating-point register, assuming
4714 one is free. Later code checks for availability.
4716 The checks against UNITS_PER_FPVALUE handle the soft-float and
4717 single-float cases. */
4721 /* The EABI conventions have traditionally been defined in terms
4722 of TYPE_MODE, regardless of the actual type. */
4723 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4724 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4725 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4730 /* Only leading floating-point scalars are passed in
4731 floating-point registers. We also handle vector floats the same
4732 say, which is OK because they are not covered by the standard ABI. */
4733 info
->fpr_p
= (!cum
->gp_reg_found
4734 && cum
->arg_number
< 2
4736 || SCALAR_FLOAT_TYPE_P (type
)
4737 || VECTOR_FLOAT_TYPE_P (type
))
4738 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4739 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4740 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4745 /* Scalar, complex and vector floating-point types are passed in
4746 floating-point registers, as long as this is a named rather
4747 than a variable argument. */
4748 info
->fpr_p
= (named
4749 && (type
== 0 || FLOAT_TYPE_P (type
))
4750 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4751 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4752 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4753 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4755 /* ??? According to the ABI documentation, the real and imaginary
4756 parts of complex floats should be passed in individual registers.
4757 The real and imaginary parts of stack arguments are supposed
4758 to be contiguous and there should be an extra word of padding
4761 This has two problems. First, it makes it impossible to use a
4762 single "void *" va_list type, since register and stack arguments
4763 are passed differently. (At the time of writing, MIPSpro cannot
4764 handle complex float varargs correctly.) Second, it's unclear
4765 what should happen when there is only one register free.
4767 For now, we assume that named complex floats should go into FPRs
4768 if there are two FPRs free, otherwise they should be passed in the
4769 same way as a struct containing two floats. */
4771 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4772 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4774 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4775 info
->fpr_p
= false;
4785 /* See whether the argument has doubleword alignment. */
4786 doubleword_aligned_p
= FUNCTION_ARG_BOUNDARY (mode
, type
) > BITS_PER_WORD
;
4788 /* Set REG_OFFSET to the register count we're interested in.
4789 The EABI allocates the floating-point registers separately,
4790 but the other ABIs allocate them like integer registers. */
4791 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4795 /* Advance to an even register if the argument is doubleword-aligned. */
4796 if (doubleword_aligned_p
)
4797 info
->reg_offset
+= info
->reg_offset
& 1;
4799 /* Work out the offset of a stack argument. */
4800 info
->stack_offset
= cum
->stack_words
;
4801 if (doubleword_aligned_p
)
4802 info
->stack_offset
+= info
->stack_offset
& 1;
4804 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4806 /* Partition the argument between registers and stack. */
4807 info
->reg_words
= MIN (num_words
, max_regs
);
4808 info
->stack_words
= num_words
- info
->reg_words
;
4811 /* INFO describes a register argument that has the normal format for the
4812 argument's mode. Return the register it uses, assuming that FPRs are
4813 available if HARD_FLOAT_P. */
4816 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4818 if (!info
->fpr_p
|| !hard_float_p
)
4819 return GP_ARG_FIRST
+ info
->reg_offset
;
4820 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4821 /* In o32, the second argument is always passed in $f14
4822 for TARGET_DOUBLE_FLOAT, regardless of whether the
4823 first argument was a word or doubleword. */
4824 return FP_ARG_FIRST
+ 2;
4826 return FP_ARG_FIRST
+ info
->reg_offset
;
4829 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4832 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4834 return !TARGET_OLDABI
;
4837 /* Implement TARGET_FUNCTION_ARG. */
4840 mips_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4841 const_tree type
, bool named
)
4843 struct mips_arg_info info
;
4845 /* We will be called with a mode of VOIDmode after the last argument
4846 has been seen. Whatever we return will be passed to the call expander.
4847 If we need a MIPS16 fp_code, return a REG with the code stored as
4849 if (mode
== VOIDmode
)
4851 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4852 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4857 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4859 /* Return straight away if the whole argument is passed on the stack. */
4860 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4863 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4864 contains a double in its entirety, then that 64-bit chunk is passed
4865 in a floating-point register. */
4867 && TARGET_HARD_FLOAT
4870 && TREE_CODE (type
) == RECORD_TYPE
4871 && TYPE_SIZE_UNIT (type
)
4872 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
4876 /* First check to see if there is any such field. */
4877 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
4878 if (TREE_CODE (field
) == FIELD_DECL
4879 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4880 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4881 && host_integerp (bit_position (field
), 0)
4882 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4887 /* Now handle the special case by returning a PARALLEL
4888 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4889 chunks are passed in registers. */
4891 HOST_WIDE_INT bitpos
;
4894 /* assign_parms checks the mode of ENTRY_PARM, so we must
4895 use the actual mode here. */
4896 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4899 field
= TYPE_FIELDS (type
);
4900 for (i
= 0; i
< info
.reg_words
; i
++)
4904 for (; field
; field
= DECL_CHAIN (field
))
4905 if (TREE_CODE (field
) == FIELD_DECL
4906 && int_bit_position (field
) >= bitpos
)
4910 && int_bit_position (field
) == bitpos
4911 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4912 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4913 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4915 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4918 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4919 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4921 bitpos
+= BITS_PER_WORD
;
4927 /* Handle the n32/n64 conventions for passing complex floating-point
4928 arguments in FPR pairs. The real part goes in the lower register
4929 and the imaginary part goes in the upper register. */
4932 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4935 enum machine_mode inner
;
4938 inner
= GET_MODE_INNER (mode
);
4939 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
4940 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4942 /* Real part in registers, imaginary part on stack. */
4943 gcc_assert (info
.stack_words
== info
.reg_words
);
4944 return gen_rtx_REG (inner
, regno
);
4948 gcc_assert (info
.stack_words
== 0);
4949 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4950 gen_rtx_REG (inner
, regno
),
4952 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4954 regno
+ info
.reg_words
/ 2),
4955 GEN_INT (GET_MODE_SIZE (inner
)));
4956 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
4960 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
4963 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4966 mips_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4967 const_tree type
, bool named
)
4969 struct mips_arg_info info
;
4971 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4974 cum
->gp_reg_found
= true;
4976 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4977 an explanation of what this code does. It assumes that we're using
4978 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4980 if (cum
->arg_number
< 2 && info
.fpr_p
)
4981 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
4983 /* Advance the register count. This has the effect of setting
4984 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4985 argument required us to skip the final GPR and pass the whole
4986 argument on the stack. */
4987 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4988 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4989 else if (info
.reg_words
> 0)
4990 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
4992 /* Advance the stack word count. */
4993 if (info
.stack_words
> 0)
4994 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4999 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5002 mips_arg_partial_bytes (CUMULATIVE_ARGS
*cum
,
5003 enum machine_mode mode
, tree type
, bool named
)
5005 struct mips_arg_info info
;
5007 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5008 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5011 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
5012 PARM_BOUNDARY bits of alignment, but will be given anything up
5013 to STACK_BOUNDARY bits if the type requires it. */
5016 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5018 unsigned int alignment
;
5020 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5021 if (alignment
< PARM_BOUNDARY
)
5022 alignment
= PARM_BOUNDARY
;
5023 if (alignment
> STACK_BOUNDARY
)
5024 alignment
= STACK_BOUNDARY
;
5028 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5029 upward rather than downward. In other words, return true if the
5030 first byte of the stack slot has useful data, false if the last
5034 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5036 /* On little-endian targets, the first byte of every stack argument
5037 is passed in the first byte of the stack slot. */
5038 if (!BYTES_BIG_ENDIAN
)
5041 /* Otherwise, integral types are padded downward: the last byte of a
5042 stack argument is passed in the last byte of the stack slot. */
5044 ? (INTEGRAL_TYPE_P (type
)
5045 || POINTER_TYPE_P (type
)
5046 || FIXED_POINT_TYPE_P (type
))
5047 : (SCALAR_INT_MODE_P (mode
)
5048 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5051 /* Big-endian o64 pads floating-point arguments downward. */
5052 if (mips_abi
== ABI_O64
)
5053 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5056 /* Other types are padded upward for o32, o64, n32 and n64. */
5057 if (mips_abi
!= ABI_EABI
)
5060 /* Arguments smaller than a stack slot are padded downward. */
5061 if (mode
!= BLKmode
)
5062 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5064 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5067 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5068 if the least significant byte of the register has useful data. Return
5069 the opposite if the most significant byte does. */
5072 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5074 /* No shifting is required for floating-point arguments. */
5075 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5076 return !BYTES_BIG_ENDIAN
;
5078 /* Otherwise, apply the same padding to register arguments as we do
5079 to stack arguments. */
5080 return mips_pad_arg_upward (mode
, type
);
5083 /* Return nonzero when an argument must be passed by reference. */
5086 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5087 enum machine_mode mode
, const_tree type
,
5088 bool named ATTRIBUTE_UNUSED
)
5090 if (mips_abi
== ABI_EABI
)
5094 /* ??? How should SCmode be handled? */
5095 if (mode
== DImode
|| mode
== DFmode
5096 || mode
== DQmode
|| mode
== UDQmode
5097 || mode
== DAmode
|| mode
== UDAmode
)
5100 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5101 return size
== -1 || size
> UNITS_PER_WORD
;
5105 /* If we have a variable-sized parameter, we have no choice. */
5106 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5110 /* Implement TARGET_CALLEE_COPIES. */
5113 mips_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5114 enum machine_mode mode ATTRIBUTE_UNUSED
,
5115 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5117 return mips_abi
== ABI_EABI
&& named
;
5120 /* See whether VALTYPE is a record whose fields should be returned in
5121 floating-point registers. If so, return the number of fields and
5122 list them in FIELDS (which should have two elements). Return 0
5125 For n32 & n64, a structure with one or two fields is returned in
5126 floating-point registers as long as every field has a floating-point
5130 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5138 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5142 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5144 if (TREE_CODE (field
) != FIELD_DECL
)
5147 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5153 fields
[i
++] = field
;
5158 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5159 a value in the most significant part of $2/$3 if:
5161 - the target is big-endian;
5163 - the value has a structure or union type (we generalize this to
5164 cover aggregates from other languages too); and
5166 - the structure is not returned in floating-point registers. */
5169 mips_return_in_msb (const_tree valtype
)
5173 return (TARGET_NEWABI
5174 && TARGET_BIG_ENDIAN
5175 && AGGREGATE_TYPE_P (valtype
)
5176 && mips_fpr_return_fields (valtype
, fields
) == 0);
5179 /* Return true if the function return value MODE will get returned in a
5180 floating-point register. */
5183 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5185 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5186 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
5187 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5188 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5191 /* Return the representation of an FPR return register when the
5192 value being returned in FP_RETURN has mode VALUE_MODE and the
5193 return type itself has mode TYPE_MODE. On NewABI targets,
5194 the two modes may be different for structures like:
5196 struct __attribute__((packed)) foo { float f; }
5198 where we return the SFmode value of "f" in FP_RETURN, but where
5199 the structure itself has mode BLKmode. */
5202 mips_return_fpr_single (enum machine_mode type_mode
,
5203 enum machine_mode value_mode
)
5207 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5208 if (type_mode
!= value_mode
)
5210 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5211 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5216 /* Return a composite value in a pair of floating-point registers.
5217 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5218 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5221 For n32 & n64, $f0 always holds the first value and $f2 the second.
5222 Otherwise the values are packed together as closely as possible. */
5225 mips_return_fpr_pair (enum machine_mode mode
,
5226 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5227 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5231 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5232 return gen_rtx_PARALLEL
5235 gen_rtx_EXPR_LIST (VOIDmode
,
5236 gen_rtx_REG (mode1
, FP_RETURN
),
5238 gen_rtx_EXPR_LIST (VOIDmode
,
5239 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5240 GEN_INT (offset2
))));
5244 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5245 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5246 VALTYPE is null and MODE is the mode of the return value. */
5249 mips_function_value (const_tree valtype
, const_tree func
, enum machine_mode mode
)
5256 mode
= TYPE_MODE (valtype
);
5257 unsigned_p
= TYPE_UNSIGNED (valtype
);
5259 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5260 return values, promote the mode here too. */
5261 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5263 /* Handle structures whose fields are returned in $f0/$f2. */
5264 switch (mips_fpr_return_fields (valtype
, fields
))
5267 return mips_return_fpr_single (mode
,
5268 TYPE_MODE (TREE_TYPE (fields
[0])));
5271 return mips_return_fpr_pair (mode
,
5272 TYPE_MODE (TREE_TYPE (fields
[0])),
5273 int_byte_position (fields
[0]),
5274 TYPE_MODE (TREE_TYPE (fields
[1])),
5275 int_byte_position (fields
[1]));
5278 /* If a value is passed in the most significant part of a register, see
5279 whether we have to round the mode up to a whole number of words. */
5280 if (mips_return_in_msb (valtype
))
5282 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5283 if (size
% UNITS_PER_WORD
!= 0)
5285 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5286 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5290 /* For EABI, the class of return register depends entirely on MODE.
5291 For example, "struct { some_type x; }" and "union { some_type x; }"
5292 are returned in the same way as a bare "some_type" would be.
5293 Other ABIs only use FPRs for scalar, complex or vector types. */
5294 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5295 return gen_rtx_REG (mode
, GP_RETURN
);
5300 /* Handle long doubles for n32 & n64. */
5302 return mips_return_fpr_pair (mode
,
5304 DImode
, GET_MODE_SIZE (mode
) / 2);
5306 if (mips_return_mode_in_fpr_p (mode
))
5308 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5309 return mips_return_fpr_pair (mode
,
5310 GET_MODE_INNER (mode
), 0,
5311 GET_MODE_INNER (mode
),
5312 GET_MODE_SIZE (mode
) / 2);
5314 return gen_rtx_REG (mode
, FP_RETURN
);
5318 return gen_rtx_REG (mode
, GP_RETURN
);
5321 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5322 all BLKmode objects are returned in memory. Under the n32, n64
5323 and embedded ABIs, small structures are returned in a register.
5324 Objects with varying size must still be returned in memory, of
5328 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5330 return (TARGET_OLDABI
5331 ? TYPE_MODE (type
) == BLKmode
5332 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5335 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5338 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5339 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5342 CUMULATIVE_ARGS local_cum
;
5343 int gp_saved
, fp_saved
;
5345 /* The caller has advanced CUM up to, but not beyond, the last named
5346 argument. Advance a local copy of CUM past the last "real" named
5347 argument, to find out how many registers are left over. */
5349 mips_function_arg_advance (&local_cum
, mode
, type
, true);
5351 /* Found out how many registers we need to save. */
5352 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5353 fp_saved
= (EABI_FLOAT_VARARGS_P
5354 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5363 ptr
= plus_constant (virtual_incoming_args_rtx
,
5364 REG_PARM_STACK_SPACE (cfun
->decl
)
5365 - gp_saved
* UNITS_PER_WORD
);
5366 mem
= gen_frame_mem (BLKmode
, ptr
);
5367 set_mem_alias_set (mem
, get_varargs_alias_set ());
5369 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5374 /* We can't use move_block_from_reg, because it will use
5376 enum machine_mode mode
;
5379 /* Set OFF to the offset from virtual_incoming_args_rtx of
5380 the first float register. The FP save area lies below
5381 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5382 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5383 off
-= fp_saved
* UNITS_PER_FPREG
;
5385 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5387 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5388 i
+= MAX_FPRS_PER_FMT
)
5392 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
5393 mem
= gen_frame_mem (mode
, ptr
);
5394 set_mem_alias_set (mem
, get_varargs_alias_set ());
5395 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5396 off
+= UNITS_PER_HWFPVALUE
;
5400 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5401 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5402 + fp_saved
* UNITS_PER_FPREG
);
5405 /* Implement TARGET_BUILTIN_VA_LIST. */
5408 mips_build_builtin_va_list (void)
5410 if (EABI_FLOAT_VARARGS_P
)
5412 /* We keep 3 pointers, and two offsets.
5414 Two pointers are to the overflow area, which starts at the CFA.
5415 One of these is constant, for addressing into the GPR save area
5416 below it. The other is advanced up the stack through the
5419 The third pointer is to the bottom of the GPR save area.
5420 Since the FPR save area is just below it, we can address
5421 FPR slots off this pointer.
5423 We also keep two one-byte offsets, which are to be subtracted
5424 from the constant pointers to yield addresses in the GPR and
5425 FPR save areas. These are downcounted as float or non-float
5426 arguments are used, and when they get to zero, the argument
5427 must be obtained from the overflow region. */
5428 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5431 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5433 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5434 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5436 f_gtop
= build_decl (BUILTINS_LOCATION
,
5437 FIELD_DECL
, get_identifier ("__gpr_top"),
5439 f_ftop
= build_decl (BUILTINS_LOCATION
,
5440 FIELD_DECL
, get_identifier ("__fpr_top"),
5442 f_goff
= build_decl (BUILTINS_LOCATION
,
5443 FIELD_DECL
, get_identifier ("__gpr_offset"),
5444 unsigned_char_type_node
);
5445 f_foff
= build_decl (BUILTINS_LOCATION
,
5446 FIELD_DECL
, get_identifier ("__fpr_offset"),
5447 unsigned_char_type_node
);
5448 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5449 warn on every user file. */
5450 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5451 array
= build_array_type (unsigned_char_type_node
,
5452 build_index_type (index
));
5453 f_res
= build_decl (BUILTINS_LOCATION
,
5454 FIELD_DECL
, get_identifier ("__reserved"), array
);
5456 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5457 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5458 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5459 DECL_FIELD_CONTEXT (f_goff
) = record
;
5460 DECL_FIELD_CONTEXT (f_foff
) = record
;
5461 DECL_FIELD_CONTEXT (f_res
) = record
;
5463 TYPE_FIELDS (record
) = f_ovfl
;
5464 DECL_CHAIN (f_ovfl
) = f_gtop
;
5465 DECL_CHAIN (f_gtop
) = f_ftop
;
5466 DECL_CHAIN (f_ftop
) = f_goff
;
5467 DECL_CHAIN (f_goff
) = f_foff
;
5468 DECL_CHAIN (f_foff
) = f_res
;
5470 layout_type (record
);
5473 else if (TARGET_IRIX6
)
5474 /* On IRIX 6, this type is 'char *'. */
5475 return build_pointer_type (char_type_node
);
5477 /* Otherwise, we use 'void *'. */
5478 return ptr_type_node
;
5481 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5484 mips_va_start (tree valist
, rtx nextarg
)
5486 if (EABI_FLOAT_VARARGS_P
)
5488 const CUMULATIVE_ARGS
*cum
;
5489 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5490 tree ovfl
, gtop
, ftop
, goff
, foff
;
5492 int gpr_save_area_size
;
5493 int fpr_save_area_size
;
5496 cum
= &crtl
->args
.info
;
5498 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5500 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5502 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5503 f_gtop
= DECL_CHAIN (f_ovfl
);
5504 f_ftop
= DECL_CHAIN (f_gtop
);
5505 f_goff
= DECL_CHAIN (f_ftop
);
5506 f_foff
= DECL_CHAIN (f_goff
);
5508 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5510 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5512 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5514 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5516 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5519 /* Emit code to initialize OVFL, which points to the next varargs
5520 stack argument. CUM->STACK_WORDS gives the number of stack
5521 words used by named arguments. */
5522 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5523 if (cum
->stack_words
> 0)
5524 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
5525 size_int (cum
->stack_words
* UNITS_PER_WORD
));
5526 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5527 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5529 /* Emit code to initialize GTOP, the top of the GPR save area. */
5530 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5531 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5532 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5534 /* Emit code to initialize FTOP, the top of the FPR save area.
5535 This address is gpr_save_area_bytes below GTOP, rounded
5536 down to the next fp-aligned boundary. */
5537 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5538 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5539 fpr_offset
&= -UNITS_PER_FPVALUE
;
5541 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ftop
), t
,
5542 size_int (-fpr_offset
));
5543 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5544 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5546 /* Emit code to initialize GOFF, the offset from GTOP of the
5547 next GPR argument. */
5548 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5549 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5550 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5552 /* Likewise emit code to initialize FOFF, the offset from FTOP
5553 of the next FPR argument. */
5554 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5555 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5556 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5560 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
5561 std_expand_builtin_va_start (valist
, nextarg
);
5565 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5568 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5574 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5576 type
= build_pointer_type (type
);
5578 if (!EABI_FLOAT_VARARGS_P
)
5579 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5582 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5583 tree ovfl
, top
, off
, align
;
5584 HOST_WIDE_INT size
, rsize
, osize
;
5587 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5588 f_gtop
= DECL_CHAIN (f_ovfl
);
5589 f_ftop
= DECL_CHAIN (f_gtop
);
5590 f_goff
= DECL_CHAIN (f_ftop
);
5591 f_foff
= DECL_CHAIN (f_goff
);
5595 TOP be the top of the GPR or FPR save area;
5596 OFF be the offset from TOP of the next register;
5597 ADDR_RTX be the address of the argument;
5598 SIZE be the number of bytes in the argument type;
5599 RSIZE be the number of bytes used to store the argument
5600 when it's in the register save area; and
5601 OSIZE be the number of bytes used to store it when it's
5602 in the stack overflow area.
5604 The code we want is:
5606 1: off &= -rsize; // round down
5609 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5614 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5615 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5619 [1] and [9] can sometimes be optimized away. */
5621 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5623 size
= int_size_in_bytes (type
);
5625 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
5626 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
5628 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
5629 unshare_expr (valist
), f_ftop
, NULL_TREE
);
5630 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
5631 unshare_expr (valist
), f_foff
, NULL_TREE
);
5633 /* When va_start saves FPR arguments to the stack, each slot
5634 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5635 argument's precision. */
5636 rsize
= UNITS_PER_HWFPVALUE
;
5638 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5639 (= PARM_BOUNDARY bits). This can be different from RSIZE
5642 (1) On 32-bit targets when TYPE is a structure such as:
5644 struct s { float f; };
5646 Such structures are passed in paired FPRs, so RSIZE
5647 will be 8 bytes. However, the structure only takes
5648 up 4 bytes of memory, so OSIZE will only be 4.
5650 (2) In combinations such as -mgp64 -msingle-float
5651 -fshort-double. Doubles passed in registers will then take
5652 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5653 stack take up UNITS_PER_WORD bytes. */
5654 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
5658 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
5659 unshare_expr (valist
), f_gtop
, NULL_TREE
);
5660 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
5661 unshare_expr (valist
), f_goff
, NULL_TREE
);
5662 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5663 if (rsize
> UNITS_PER_WORD
)
5665 /* [1] Emit code for: off &= -rsize. */
5666 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
5667 build_int_cst (TREE_TYPE (off
), -rsize
));
5668 gimplify_assign (unshare_expr (off
), t
, pre_p
);
5673 /* [2] Emit code to branch if off == 0. */
5674 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
5675 build_int_cst (TREE_TYPE (off
), 0));
5676 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
5678 /* [5] Emit code for: off -= rsize. We do this as a form of
5679 post-decrement not available to C. */
5680 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
5681 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
5683 /* [4] Emit code for:
5684 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5685 t
= fold_convert (sizetype
, t
);
5686 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
5687 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (top
), top
, t
);
5688 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
5690 u
= size_int (rsize
- size
);
5691 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5693 COND_EXPR_THEN (addr
) = t
;
5695 if (osize
> UNITS_PER_WORD
)
5697 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5698 u
= size_int (osize
- 1);
5699 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
),
5700 unshare_expr (ovfl
), u
);
5701 t
= fold_convert (sizetype
, t
);
5702 u
= size_int (-osize
);
5703 t
= build2 (BIT_AND_EXPR
, sizetype
, t
, u
);
5704 t
= fold_convert (TREE_TYPE (ovfl
), t
);
5705 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
5706 unshare_expr (ovfl
), t
);
5711 /* [10, 11] Emit code for:
5712 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5714 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
5715 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5716 if (BYTES_BIG_ENDIAN
&& osize
> size
)
5718 u
= size_int (osize
- size
);
5719 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5722 /* String [9] and [10, 11] together. */
5724 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5725 COND_EXPR_ELSE (addr
) = t
;
5727 addr
= fold_convert (build_pointer_type (type
), addr
);
5728 addr
= build_va_arg_indirect_ref (addr
);
5732 addr
= build_va_arg_indirect_ref (addr
);
5737 /* Start a definition of function NAME. MIPS16_P indicates whether the
5738 function contains MIPS16 code. */
5741 mips_start_function_definition (const char *name
, bool mips16_p
)
5744 fprintf (asm_out_file
, "\t.set\tmips16\n");
5746 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5748 if (!flag_inhibit_size_directive
)
5750 fputs ("\t.ent\t", asm_out_file
);
5751 assemble_name (asm_out_file
, name
);
5752 fputs ("\n", asm_out_file
);
5755 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
5757 /* Start the definition proper. */
5758 assemble_name (asm_out_file
, name
);
5759 fputs (":\n", asm_out_file
);
5762 /* End a function definition started by mips_start_function_definition. */
5765 mips_end_function_definition (const char *name
)
5767 if (!flag_inhibit_size_directive
)
5769 fputs ("\t.end\t", asm_out_file
);
5770 assemble_name (asm_out_file
, name
);
5771 fputs ("\n", asm_out_file
);
5775 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5778 mips_ok_for_lazy_binding_p (rtx x
)
5780 return (TARGET_USE_GOT
5781 && GET_CODE (x
) == SYMBOL_REF
5782 && !SYMBOL_REF_BIND_NOW_P (x
)
5783 && !mips_symbol_binds_local_p (x
));
5786 /* Load function address ADDR into register DEST. TYPE is as for
5787 mips_expand_call. Return true if we used an explicit lazy-binding
5791 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
5793 /* If we're generating PIC, and this call is to a global function,
5794 try to allow its address to be resolved lazily. This isn't
5795 possible for sibcalls when $gp is call-saved because the value
5796 of $gp on entry to the stub would be our caller's gp, not ours. */
5797 if (TARGET_EXPLICIT_RELOCS
5798 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
5799 && mips_ok_for_lazy_binding_p (addr
))
5801 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
5802 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
5807 mips_emit_move (dest
, addr
);
5812 /* Each locally-defined hard-float MIPS16 function has a local symbol
5813 associated with it. This hash table maps the function symbol (FUNC)
5814 to the local symbol (LOCAL). */
5815 struct GTY(()) mips16_local_alias
{
5819 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
5821 /* Hash table callbacks for mips16_local_aliases. */
5824 mips16_local_aliases_hash (const void *entry
)
5826 const struct mips16_local_alias
*alias
;
5828 alias
= (const struct mips16_local_alias
*) entry
;
5829 return htab_hash_string (XSTR (alias
->func
, 0));
5833 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
5835 const struct mips16_local_alias
*alias1
, *alias2
;
5837 alias1
= (const struct mips16_local_alias
*) entry1
;
5838 alias2
= (const struct mips16_local_alias
*) entry2
;
5839 return rtx_equal_p (alias1
->func
, alias2
->func
);
5842 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5843 Return a local alias for it, creating a new one if necessary. */
5846 mips16_local_alias (rtx func
)
5848 struct mips16_local_alias
*alias
, tmp_alias
;
5851 /* Create the hash table if this is the first call. */
5852 if (mips16_local_aliases
== NULL
)
5853 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
5854 mips16_local_aliases_eq
, NULL
);
5856 /* Look up the function symbol, creating a new entry if need be. */
5857 tmp_alias
.func
= func
;
5858 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
5859 gcc_assert (slot
!= NULL
);
5861 alias
= (struct mips16_local_alias
*) *slot
;
5864 const char *func_name
, *local_name
;
5867 /* Create a new SYMBOL_REF for the local symbol. The choice of
5868 __fn_local_* is based on the __fn_stub_* names that we've
5869 traditionally used for the non-MIPS16 stub. */
5870 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
5871 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
5872 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
5873 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
5875 /* Create a new structure to represent the mapping. */
5876 alias
= ggc_alloc_mips16_local_alias ();
5878 alias
->local
= local
;
5881 return alias
->local
;
5884 /* A chained list of functions for which mips16_build_call_stub has already
5885 generated a stub. NAME is the name of the function and FP_RET_P is true
5886 if the function returns a value in floating-point registers. */
5887 struct mips16_stub
{
5888 struct mips16_stub
*next
;
5892 static struct mips16_stub
*mips16_stubs
;
5894 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5897 mips16_stub_function (const char *name
)
5901 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
5902 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
5906 /* Return the two-character string that identifies floating-point
5907 return mode MODE in the name of a MIPS16 function stub. */
5910 mips16_call_stub_mode_suffix (enum machine_mode mode
)
5914 else if (mode
== DFmode
)
5916 else if (mode
== SCmode
)
5918 else if (mode
== DCmode
)
5920 else if (mode
== V2SFmode
)
5926 /* Write instructions to move a 32-bit value between general register
5927 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5928 from GPREG to FPREG and 'f' to move in the opposite direction. */
5931 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5933 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5934 reg_names
[gpreg
], reg_names
[fpreg
]);
5937 /* Likewise for 64-bit values. */
5940 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5943 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
5944 reg_names
[gpreg
], reg_names
[fpreg
]);
5945 else if (TARGET_FLOAT64
)
5947 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5948 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5949 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
5950 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
5954 /* Move the least-significant word. */
5955 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5956 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5957 /* ...then the most significant word. */
5958 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5959 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
5963 /* Write out code to move floating-point arguments into or out of
5964 general registers. FP_CODE is the code describing which arguments
5965 are present (see the comment above the definition of CUMULATIVE_ARGS
5966 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5969 mips_output_args_xfer (int fp_code
, char direction
)
5971 unsigned int gparg
, fparg
, f
;
5972 CUMULATIVE_ARGS cum
;
5974 /* This code only works for o32 and o64. */
5975 gcc_assert (TARGET_OLDABI
);
5977 mips_init_cumulative_args (&cum
, NULL
);
5979 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5981 enum machine_mode mode
;
5982 struct mips_arg_info info
;
5986 else if ((f
& 3) == 2)
5991 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
5992 gparg
= mips_arg_regno (&info
, false);
5993 fparg
= mips_arg_regno (&info
, true);
5996 mips_output_32bit_xfer (direction
, gparg
, fparg
);
5998 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6000 mips_function_arg_advance (&cum
, mode
, NULL
, true);
6004 /* Write a MIPS16 stub for the current function. This stub is used
6005 for functions which take arguments in the floating-point registers.
6006 It is normal-mode code that moves the floating-point arguments
6007 into the general registers and then jumps to the MIPS16 code. */
6010 mips16_build_function_stub (void)
6012 const char *fnname
, *alias_name
, *separator
;
6013 char *secname
, *stubname
;
6018 /* Create the name of the stub, and its unique section. */
6019 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6020 alias
= mips16_local_alias (symbol
);
6022 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6023 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6024 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6025 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6027 /* Build a decl for the stub. */
6028 stubdecl
= build_decl (BUILTINS_LOCATION
,
6029 FUNCTION_DECL
, get_identifier (stubname
),
6030 build_function_type (void_type_node
, NULL_TREE
));
6031 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6032 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6033 RESULT_DECL
, NULL_TREE
, void_type_node
);
6035 /* Output a comment. */
6036 fprintf (asm_out_file
, "\t# Stub function for %s (",
6037 current_function_name ());
6039 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6041 fprintf (asm_out_file
, "%s%s", separator
,
6042 (f
& 3) == 1 ? "float" : "double");
6045 fprintf (asm_out_file
, ")\n");
6047 /* Start the function definition. */
6048 assemble_start_function (stubdecl
, stubname
);
6049 mips_start_function_definition (stubname
, false);
6051 /* If generating pic2 code, either set up the global pointer or
6053 if (TARGET_ABICALLS_PIC2
)
6055 if (TARGET_ABSOLUTE_ABICALLS
)
6056 fprintf (asm_out_file
, "\t.option\tpic0\n");
6059 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6060 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6061 target function is. Use a local GOT access when loading the
6062 symbol, to cut down on the number of unnecessary GOT entries
6063 for stubs that aren't needed. */
6064 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6069 /* Load the address of the MIPS16 function into $25. Do this first so
6070 that targets with coprocessor interlocks can use an MFC1 to fill the
6072 output_asm_insn ("la\t%^,%0", &symbol
);
6074 /* Move the arguments from floating-point registers to general registers. */
6075 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6077 /* Jump to the MIPS16 function. */
6078 output_asm_insn ("jr\t%^", NULL
);
6080 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6081 fprintf (asm_out_file
, "\t.option\tpic2\n");
6083 mips_end_function_definition (stubname
);
6085 /* If the linker needs to create a dynamic symbol for the target
6086 function, it will associate the symbol with the stub (which,
6087 unlike the target function, follows the proper calling conventions).
6088 It is therefore useful to have a local alias for the target function,
6089 so that it can still be identified as MIPS16 code. As an optimization,
6090 this symbol can also be used for indirect MIPS16 references from
6091 within this file. */
6092 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6094 switch_to_section (function_section (current_function_decl
));
6097 /* The current function is a MIPS16 function that returns a value in an FPR.
6098 Copy the return value from its soft-float to its hard-float location.
6099 libgcc2 has special non-MIPS16 helper functions for each case. */
6102 mips16_copy_fpr_return_value (void)
6104 rtx fn
, insn
, retval
;
6106 enum machine_mode return_mode
;
6109 return_type
= DECL_RESULT (current_function_decl
);
6110 return_mode
= DECL_MODE (return_type
);
6112 name
= ACONCAT (("__mips16_ret_",
6113 mips16_call_stub_mode_suffix (return_mode
),
6115 fn
= mips16_stub_function (name
);
6117 /* The function takes arguments in $2 (and possibly $3), so calls
6118 to it cannot be lazily bound. */
6119 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6121 /* Model the call as something that takes the GPR return value as
6122 argument and returns an "updated" value. */
6123 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6124 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6125 const0_rtx
, NULL_RTX
, false);
6126 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6129 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6130 RETVAL is the location of the return value, or null if this is
6131 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6132 arguments and FP_CODE is the code built by mips_function_arg;
6133 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6135 There are three alternatives:
6137 - If a stub was needed, emit the call and return the call insn itself.
6139 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6140 to the new target and return null.
6142 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6145 A stub is needed for calls to functions that, in normal mode,
6146 receive arguments in FPRs or return values in FPRs. The stub
6147 copies the arguments from their soft-float positions to their
6148 hard-float positions, calls the real function, then copies the
6149 return value from its hard-float position to its soft-float
6152 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6153 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6154 automatically redirects the JAL to the stub, otherwise the JAL
6155 continues to call FN directly. */
6158 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6162 struct mips16_stub
*l
;
6165 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6166 we were invoked with the -msoft-float option. */
6167 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6170 /* Figure out whether the value might come back in a floating-point
6172 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6174 /* We don't need to do anything if there were no floating-point
6175 arguments and the value will not be returned in a floating-point
6177 if (fp_code
== 0 && !fp_ret_p
)
6180 /* We don't need to do anything if this is a call to a special
6181 MIPS16 support function. */
6183 if (mips16_stub_function_p (fn
))
6186 /* This code will only work for o32 and o64 abis. The other ABI's
6187 require more sophisticated support. */
6188 gcc_assert (TARGET_OLDABI
);
6190 /* If we're calling via a function pointer, use one of the magic
6191 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6192 Each stub expects the function address to arrive in register $2. */
6193 if (GET_CODE (fn
) != SYMBOL_REF
6194 || !call_insn_operand (fn
, VOIDmode
))
6197 rtx stub_fn
, insn
, addr
;
6200 /* If this is a locally-defined and locally-binding function,
6201 avoid the stub by calling the local alias directly. */
6202 if (mips16_local_function_p (fn
))
6204 *fn_ptr
= mips16_local_alias (fn
);
6208 /* Create a SYMBOL_REF for the libgcc.a function. */
6210 sprintf (buf
, "__mips16_call_stub_%s_%d",
6211 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6214 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6215 stub_fn
= mips16_stub_function (buf
);
6217 /* The function uses $2 as an argument, so calls to it
6218 cannot be lazily bound. */
6219 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6221 /* Load the target function into $2. */
6222 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6223 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6225 /* Emit the call. */
6226 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6227 args_size
, NULL_RTX
, lazy_p
);
6229 /* Tell GCC that this call does indeed use the value of $2. */
6230 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6232 /* If we are handling a floating-point return value, we need to
6233 save $18 in the function prologue. Putting a note on the
6234 call will mean that df_regs_ever_live_p ($18) will be true if the
6235 call is not eliminated, and we can check that in the prologue
6238 CALL_INSN_FUNCTION_USAGE (insn
) =
6239 gen_rtx_EXPR_LIST (VOIDmode
,
6240 gen_rtx_CLOBBER (VOIDmode
,
6241 gen_rtx_REG (word_mode
, 18)),
6242 CALL_INSN_FUNCTION_USAGE (insn
));
6247 /* We know the function we are going to call. If we have already
6248 built a stub, we don't need to do anything further. */
6249 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6250 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6251 if (strcmp (l
->name
, fnname
) == 0)
6256 const char *separator
;
6257 char *secname
, *stubname
;
6258 tree stubid
, stubdecl
;
6261 /* If the function does not return in FPRs, the special stub
6265 If the function does return in FPRs, the stub section is named
6266 .mips16.call.fp.FNNAME
6268 Build a decl for the stub. */
6269 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6271 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6273 stubid
= get_identifier (stubname
);
6274 stubdecl
= build_decl (BUILTINS_LOCATION
,
6275 FUNCTION_DECL
, stubid
,
6276 build_function_type (void_type_node
, NULL_TREE
));
6277 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6278 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6279 RESULT_DECL
, NULL_TREE
,
6282 /* Output a comment. */
6283 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6285 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6289 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6291 fprintf (asm_out_file
, "%s%s", separator
,
6292 (f
& 3) == 1 ? "float" : "double");
6295 fprintf (asm_out_file
, ")\n");
6297 /* Start the function definition. */
6298 assemble_start_function (stubdecl
, stubname
);
6299 mips_start_function_definition (stubname
, false);
6303 /* Load the address of the MIPS16 function into $25. Do this
6304 first so that targets with coprocessor interlocks can use
6305 an MFC1 to fill the delay slot. */
6306 if (TARGET_EXPLICIT_RELOCS
)
6308 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6309 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6312 output_asm_insn ("la\t%^,%0", &fn
);
6315 /* Move the arguments from general registers to floating-point
6317 mips_output_args_xfer (fp_code
, 't');
6321 /* Jump to the previously-loaded address. */
6322 output_asm_insn ("jr\t%^", NULL
);
6326 /* Save the return address in $18 and call the non-MIPS16 function.
6327 The stub's caller knows that $18 might be clobbered, even though
6328 $18 is usually a call-saved register. */
6329 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6330 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6331 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6333 /* Move the result from floating-point registers to
6334 general registers. */
6335 switch (GET_MODE (retval
))
6338 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6340 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6342 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6343 TARGET_LITTLE_ENDIAN
6344 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6346 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6348 /* On 64-bit targets, complex floats are returned in
6349 a single GPR, such that "sd" on a suitably-aligned
6350 target would store the value correctly. */
6351 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6352 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6353 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6354 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6355 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6356 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6357 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6358 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6359 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6360 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6361 reg_names
[GP_RETURN
],
6362 reg_names
[GP_RETURN
],
6363 reg_names
[GP_RETURN
+ 1]);
6368 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6372 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6373 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6377 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6383 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6386 #ifdef ASM_DECLARE_FUNCTION_SIZE
6387 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6390 mips_end_function_definition (stubname
);
6392 /* Record this stub. */
6393 l
= XNEW (struct mips16_stub
);
6394 l
->name
= xstrdup (fnname
);
6395 l
->fp_ret_p
= fp_ret_p
;
6396 l
->next
= mips16_stubs
;
6400 /* If we expect a floating-point return value, but we've built a
6401 stub which does not expect one, then we're in trouble. We can't
6402 use the existing stub, because it won't handle the floating-point
6403 value. We can't build a new stub, because the linker won't know
6404 which stub to use for the various calls in this object file.
6405 Fortunately, this case is illegal, since it means that a function
6406 was declared in two different ways in a single compilation. */
6407 if (fp_ret_p
&& !l
->fp_ret_p
)
6408 error ("cannot handle inconsistent calls to %qs", fnname
);
6410 if (retval
== NULL_RTX
)
6411 insn
= gen_call_internal_direct (fn
, args_size
);
6413 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6414 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6416 /* If we are calling a stub which handles a floating-point return
6417 value, we need to arrange to save $18 in the prologue. We do this
6418 by marking the function call as using the register. The prologue
6419 will later see that it is used, and emit code to save it. */
6421 CALL_INSN_FUNCTION_USAGE (insn
) =
6422 gen_rtx_EXPR_LIST (VOIDmode
,
6423 gen_rtx_CLOBBER (VOIDmode
,
6424 gen_rtx_REG (word_mode
, 18)),
6425 CALL_INSN_FUNCTION_USAGE (insn
));
6430 /* Expand a call of type TYPE. RESULT is where the result will go (null
6431 for "call"s and "sibcall"s), ADDR is the address of the function,
6432 ARGS_SIZE is the size of the arguments and AUX is the value passed
6433 to us by mips_function_arg. LAZY_P is true if this call already
6434 involves a lazily-bound function address (such as when calling
6435 functions through a MIPS16 hard-float stub).
6437 Return the call itself. */
6440 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6441 rtx args_size
, rtx aux
, bool lazy_p
)
6443 rtx orig_addr
, pattern
, insn
;
6446 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6447 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6450 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6455 if (!call_insn_operand (addr
, VOIDmode
))
6457 if (type
== MIPS_CALL_EPILOGUE
)
6458 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6460 addr
= gen_reg_rtx (Pmode
);
6461 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6466 rtx (*fn
) (rtx
, rtx
);
6468 if (type
== MIPS_CALL_SIBCALL
)
6469 fn
= gen_sibcall_internal
;
6471 fn
= gen_call_internal
;
6473 pattern
= fn (addr
, args_size
);
6475 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6477 /* Handle return values created by mips_return_fpr_pair. */
6478 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6481 if (type
== MIPS_CALL_SIBCALL
)
6482 fn
= gen_sibcall_value_multiple_internal
;
6484 fn
= gen_call_value_multiple_internal
;
6486 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6487 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6488 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6492 rtx (*fn
) (rtx
, rtx
, rtx
);
6494 if (type
== MIPS_CALL_SIBCALL
)
6495 fn
= gen_sibcall_value_internal
;
6497 fn
= gen_call_value_internal
;
6499 /* Handle return values created by mips_return_fpr_single. */
6500 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6501 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6502 pattern
= fn (result
, addr
, args_size
);
6505 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6508 /* Split call instruction INSN into a $gp-clobbering call and
6509 (where necessary) an instruction to restore $gp from its save slot.
6510 CALL_PATTERN is the pattern of the new call. */
6513 mips_split_call (rtx insn
, rtx call_pattern
)
6517 new_insn
= emit_call_insn (call_pattern
);
6518 CALL_INSN_FUNCTION_USAGE (new_insn
)
6519 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn
));
6520 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6521 /* Pick a temporary register that is suitable for both MIPS16 and
6522 non-MIPS16 code. $4 and $5 are used for returning complex double
6523 values in soft-float code, so $6 is the first suitable candidate. */
6524 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6527 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6530 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
6532 if (!TARGET_SIBCALLS
)
6535 /* Interrupt handlers need special epilogue code and therefore can't
6537 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
6540 /* We can't do a sibcall if the called function is a MIPS16 function
6541 because there is no direct "jx" instruction equivalent to "jalx" to
6542 switch the ISA mode. We only care about cases where the sibling
6543 and normal calls would both be direct. */
6545 && mips_use_mips16_mode_p (decl
)
6546 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6549 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6550 functions could be MIPS16 ones unless an attribute explicitly tells
6552 if (TARGET_INTERLINK_MIPS16
6554 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
6555 && !mips_nomips16_decl_p (decl
)
6556 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6563 /* Emit code to move general operand SRC into condition-code
6564 register DEST given that SCRATCH is a scratch TFmode FPR.
6571 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6574 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
6578 /* Change the source to SFmode. */
6580 src
= adjust_address (src
, SFmode
, 0);
6581 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
6582 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
6584 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
6585 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
6587 mips_emit_move (copy_rtx (fp1
), src
);
6588 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
6589 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
6592 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6593 Assume that the areas do not overlap. */
6596 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
6598 HOST_WIDE_INT offset
, delta
;
6599 unsigned HOST_WIDE_INT bits
;
6601 enum machine_mode mode
;
6604 /* Work out how many bits to move at a time. If both operands have
6605 half-word alignment, it is usually better to move in half words.
6606 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6607 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6608 Otherwise move word-sized chunks. */
6609 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
6610 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
6611 bits
= BITS_PER_WORD
/ 2;
6613 bits
= BITS_PER_WORD
;
6615 mode
= mode_for_size (bits
, MODE_INT
, 0);
6616 delta
= bits
/ BITS_PER_UNIT
;
6618 /* Allocate a buffer for the temporary registers. */
6619 regs
= XALLOCAVEC (rtx
, length
/ delta
);
6621 /* Load as many BITS-sized chunks as possible. Use a normal load if
6622 the source has enough alignment, otherwise use left/right pairs. */
6623 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6625 regs
[i
] = gen_reg_rtx (mode
);
6626 if (MEM_ALIGN (src
) >= bits
)
6627 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
6630 rtx part
= adjust_address (src
, BLKmode
, offset
);
6631 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0))
6636 /* Copy the chunks to the destination. */
6637 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6638 if (MEM_ALIGN (dest
) >= bits
)
6639 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
6642 rtx part
= adjust_address (dest
, BLKmode
, offset
);
6643 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
6647 /* Mop up any left-over bytes. */
6648 if (offset
< length
)
6650 src
= adjust_address (src
, BLKmode
, offset
);
6651 dest
= adjust_address (dest
, BLKmode
, offset
);
6652 move_by_pieces (dest
, src
, length
- offset
,
6653 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
6657 /* Helper function for doing a loop-based block operation on memory
6658 reference MEM. Each iteration of the loop will operate on LENGTH
6661 Create a new base register for use within the loop and point it to
6662 the start of MEM. Create a new memory reference that uses this
6663 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6666 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
6667 rtx
*loop_reg
, rtx
*loop_mem
)
6669 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
6671 /* Although the new mem does not refer to a known location,
6672 it does keep up to LENGTH bytes of alignment. */
6673 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
6674 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
6677 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6678 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6679 the memory regions do not overlap. */
6682 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
6683 HOST_WIDE_INT bytes_per_iter
)
6685 rtx label
, src_reg
, dest_reg
, final_src
, test
;
6686 HOST_WIDE_INT leftover
;
6688 leftover
= length
% bytes_per_iter
;
6691 /* Create registers and memory references for use within the loop. */
6692 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
6693 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
6695 /* Calculate the value that SRC_REG should have after the last iteration
6697 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
6700 /* Emit the start of the loop. */
6701 label
= gen_label_rtx ();
6704 /* Emit the loop body. */
6705 mips_block_move_straight (dest
, src
, bytes_per_iter
);
6707 /* Move on to the next block. */
6708 mips_emit_move (src_reg
, plus_constant (src_reg
, bytes_per_iter
));
6709 mips_emit_move (dest_reg
, plus_constant (dest_reg
, bytes_per_iter
));
6711 /* Emit the loop condition. */
6712 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
6713 if (Pmode
== DImode
)
6714 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
6716 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
6718 /* Mop up any left-over bytes. */
6720 mips_block_move_straight (dest
, src
, leftover
);
6723 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6724 memory reference SRC to memory reference DEST. */
6727 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
6729 if (CONST_INT_P (length
))
6731 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
6733 mips_block_move_straight (dest
, src
, INTVAL (length
));
6738 mips_block_move_loop (dest
, src
, INTVAL (length
),
6739 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
6746 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6749 mips_expand_synci_loop (rtx begin
, rtx end
)
6751 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
6753 /* Create end_label. */
6754 end_label
= gen_label_rtx ();
6756 /* Check if begin equals end. */
6757 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
6758 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
6760 /* Load INC with the cache line size (rdhwr INC,$1). */
6761 inc
= gen_reg_rtx (Pmode
);
6762 emit_insn (Pmode
== SImode
6763 ? gen_rdhwr_synci_step_si (inc
)
6764 : gen_rdhwr_synci_step_di (inc
));
6766 /* Check if inc is 0. */
6767 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
6768 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
6770 /* Calculate mask. */
6771 mask
= mips_force_unary (Pmode
, NEG
, inc
);
6773 /* Mask out begin by mask. */
6774 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
6776 /* Calculate length. */
6777 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
6779 /* Loop back to here. */
6780 label
= gen_label_rtx ();
6783 emit_insn (gen_synci (begin
));
6785 /* Update length. */
6786 mips_emit_binary (MINUS
, length
, length
, inc
);
6789 mips_emit_binary (PLUS
, begin
, begin
, inc
);
6791 /* Check if length is greater than 0. */
6792 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
6793 emit_jump_insn (gen_condjump (cmp_result
, label
));
6795 emit_label (end_label
);
6798 /* Expand a QI or HI mode atomic memory operation.
6800 GENERATOR contains a pointer to the gen_* function that generates
6801 the SI mode underlying atomic operation using masks that we
6804 RESULT is the return register for the operation. Its value is NULL
6807 MEM is the location of the atomic access.
6809 OLDVAL is the first operand for the operation.
6811 NEWVAL is the optional second operand for the operation. Its value
6812 is NULL if unused. */
6815 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
6816 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
6818 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
6819 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
6821 enum machine_mode mode
;
6823 mode
= GET_MODE (mem
);
6825 /* Compute the address of the containing SImode value. */
6826 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
6827 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
6828 force_reg (Pmode
, GEN_INT (-4)));
6830 /* Create a memory reference for it. */
6831 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
6832 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
6833 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
6835 /* Work out the byte offset of the QImode or HImode value,
6836 counting from the least significant byte. */
6837 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
6838 if (TARGET_BIG_ENDIAN
)
6839 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
6841 /* Multiply by eight to convert the shift value from bytes to bits. */
6842 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
6844 /* Make the final shift an SImode value, so that it can be used in
6845 SImode operations. */
6846 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
6848 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6849 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
6850 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
6851 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
6853 /* Compute the equivalent exclusive mask. */
6854 inverted_mask
= gen_reg_rtx (SImode
);
6855 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
6856 gen_rtx_NOT (SImode
, mask
)));
6858 /* Shift the old value into place. */
6859 if (oldval
!= const0_rtx
)
6861 oldval
= convert_modes (SImode
, mode
, oldval
, true);
6862 oldval
= force_reg (SImode
, oldval
);
6863 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
6866 /* Do the same for the new value. */
6867 if (newval
&& newval
!= const0_rtx
)
6869 newval
= convert_modes (SImode
, mode
, newval
, true);
6870 newval
= force_reg (SImode
, newval
);
6871 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
6874 /* Do the SImode atomic access. */
6876 res
= gen_reg_rtx (SImode
);
6878 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
6880 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
6882 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
6888 /* Shift and convert the result. */
6889 mips_emit_binary (AND
, res
, res
, mask
);
6890 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
6891 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
6895 /* Return true if it is possible to use left/right accesses for a
6896 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6897 returning true, update *OP, *LEFT and *RIGHT as follows:
6899 *OP is a BLKmode reference to the whole field.
6901 *LEFT is a QImode reference to the first byte if big endian or
6902 the last byte if little endian. This address can be used in the
6903 left-side instructions (LWL, SWL, LDL, SDL).
6905 *RIGHT is a QImode reference to the opposite end of the field and
6906 can be used in the patterning right-side instruction. */
6909 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
6910 rtx
*left
, rtx
*right
)
6914 /* Check that the operand really is a MEM. Not all the extv and
6915 extzv predicates are checked. */
6919 /* Check that the size is valid. */
6920 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
6923 /* We can only access byte-aligned values. Since we are always passed
6924 a reference to the first byte of the field, it is not necessary to
6925 do anything with BITPOS after this check. */
6926 if (bitpos
% BITS_PER_UNIT
!= 0)
6929 /* Reject aligned bitfields: we want to use a normal load or store
6930 instead of a left/right pair. */
6931 if (MEM_ALIGN (*op
) >= width
)
6934 /* Adjust *OP to refer to the whole field. This also has the effect
6935 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6936 *op
= adjust_address (*op
, BLKmode
, 0);
6937 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
6939 /* Get references to both ends of the field. We deliberately don't
6940 use the original QImode *OP for FIRST since the new BLKmode one
6941 might have a simpler address. */
6942 first
= adjust_address (*op
, QImode
, 0);
6943 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
6945 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6946 correspond to the MSB and RIGHT to the LSB. */
6947 if (TARGET_BIG_ENDIAN
)
6948 *left
= first
, *right
= last
;
6950 *left
= last
, *right
= first
;
6955 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6956 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6957 the operation is the equivalent of:
6959 (set DEST (*_extract SRC WIDTH BITPOS))
6961 Return true on success. */
6964 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
6965 HOST_WIDE_INT bitpos
)
6967 rtx left
, right
, temp
;
6969 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6970 be a paradoxical word_mode subreg. This is the only case in which
6971 we allow the destination to be larger than the source. */
6972 if (GET_CODE (dest
) == SUBREG
6973 && GET_MODE (dest
) == DImode
6974 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
6975 dest
= SUBREG_REG (dest
);
6977 /* After the above adjustment, the destination must be the same
6978 width as the source. */
6979 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
6982 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
6985 temp
= gen_reg_rtx (GET_MODE (dest
));
6986 if (GET_MODE (dest
) == DImode
)
6988 emit_insn (gen_mov_ldl (temp
, src
, left
));
6989 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
6993 emit_insn (gen_mov_lwl (temp
, src
, left
));
6994 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
6999 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7000 BITPOS and SRC are the operands passed to the expander; the operation
7001 is the equivalent of:
7003 (set (zero_extract DEST WIDTH BITPOS) SRC)
7005 Return true on success. */
7008 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7009 HOST_WIDE_INT bitpos
)
7012 enum machine_mode mode
;
7014 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
7017 mode
= mode_for_size (width
, MODE_INT
, 0);
7018 src
= gen_lowpart (mode
, src
);
7021 emit_insn (gen_mov_sdl (dest
, src
, left
));
7022 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7026 emit_insn (gen_mov_swl (dest
, src
, left
));
7027 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7032 /* Return true if X is a MEM with the same size as MODE. */
7035 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7042 size
= MEM_SIZE (x
);
7043 return size
&& INTVAL (size
) == GET_MODE_SIZE (mode
);
7046 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7047 source of an "ext" instruction or the destination of an "ins"
7048 instruction. OP must be a register operand and the following
7049 conditions must hold:
7051 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7052 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7053 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7055 Also reject lengths equal to a word as they are better handled
7056 by the move patterns. */
7059 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7061 if (!ISA_HAS_EXT_INS
7062 || !register_operand (op
, VOIDmode
)
7063 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7066 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7069 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7075 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7076 operation if MAXLEN is the maxium length of consecutive bits that
7077 can make up MASK. MODE is the mode of the operation. See
7078 mask_low_and_shift_len for the actual definition. */
7081 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7083 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7086 /* Return true iff OP1 and OP2 are valid operands together for the
7087 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7088 see the table in the comment before the pattern. */
7091 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7093 return (memory_operand (op1
, mode
)
7094 ? and_load_operand (op2
, mode
)
7095 : and_reg_operand (op2
, mode
));
7098 /* The canonical form of a mask-low-and-shift-left operation is
7099 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7100 cleared. Thus we need to shift MASK to the right before checking if it
7101 is a valid mask value. MODE is the mode of the operation. If true
7102 return the length of the mask, otherwise return -1. */
7105 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7107 HOST_WIDE_INT shval
;
7109 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7110 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7113 /* Return true if -msplit-addresses is selected and should be honored.
7115 -msplit-addresses is a half-way house between explicit relocations
7116 and the traditional assembler macros. It can split absolute 32-bit
7117 symbolic constants into a high/lo_sum pair but uses macros for other
7120 Like explicit relocation support for REL targets, it relies
7121 on GNU extensions in the assembler and the linker.
7123 Although this code should work for -O0, it has traditionally
7124 been treated as an optimization. */
7127 mips_split_addresses_p (void)
7129 return (TARGET_SPLIT_ADDRESSES
7133 && !ABI_HAS_64BIT_SYMBOLS
);
7136 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7139 mips_init_relocs (void)
7141 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7142 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7143 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7144 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7146 if (ABI_HAS_64BIT_SYMBOLS
)
7148 if (TARGET_EXPLICIT_RELOCS
)
7150 mips_split_p
[SYMBOL_64_HIGH
] = true;
7151 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7152 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7154 mips_split_p
[SYMBOL_64_MID
] = true;
7155 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7156 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7158 mips_split_p
[SYMBOL_64_LOW
] = true;
7159 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7160 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7162 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7163 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7168 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses_p () || TARGET_MIPS16
)
7170 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7171 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7172 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7174 mips_lo_relocs
[SYMBOL_32_HIGH
] = "%hi(";
7180 /* The high part is provided by a pseudo copy of $gp. */
7181 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7182 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7184 else if (TARGET_EXPLICIT_RELOCS
)
7185 /* Small data constants are kept whole until after reload,
7186 then lowered by mips_rewrite_small_data. */
7187 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7189 if (TARGET_EXPLICIT_RELOCS
)
7191 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7194 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7195 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7199 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7200 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7203 /* Expose the use of $28 as soon as possible. */
7204 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7208 /* The HIGH and LO_SUM are matched by special .md patterns. */
7209 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7211 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7212 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7213 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7215 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7216 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7217 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7222 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7224 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7225 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7227 /* Expose the use of $28 as soon as possible. */
7228 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7234 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7235 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7236 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7239 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7240 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7242 mips_split_p
[SYMBOL_DTPREL
] = true;
7243 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7244 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7246 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7248 mips_split_p
[SYMBOL_TPREL
] = true;
7249 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7250 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7252 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7255 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7256 in context CONTEXT. RELOCS is the array of relocations to use. */
7259 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7260 const char **relocs
)
7262 enum mips_symbol_type symbol_type
;
7265 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7266 gcc_assert (relocs
[symbol_type
]);
7268 fputs (relocs
[symbol_type
], file
);
7269 output_addr_const (file
, mips_strip_unspec_address (op
));
7270 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7275 /* Start a new block with the given asm switch enabled. If we need
7276 to print a directive, emit PREFIX before it and SUFFIX after it. */
7279 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7280 const char *prefix
, const char *suffix
)
7282 if (asm_switch
->nesting_level
== 0)
7283 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7284 asm_switch
->nesting_level
++;
7287 /* Likewise, but end a block. */
7290 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7291 const char *prefix
, const char *suffix
)
7293 gcc_assert (asm_switch
->nesting_level
);
7294 asm_switch
->nesting_level
--;
7295 if (asm_switch
->nesting_level
== 0)
7296 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7299 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7300 that either print a complete line or print nothing. */
7303 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7305 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7309 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7311 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7314 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7315 The punctuation characters are:
7317 '(' Start a nested ".set noreorder" block.
7318 ')' End a nested ".set noreorder" block.
7319 '[' Start a nested ".set noat" block.
7320 ']' End a nested ".set noat" block.
7321 '<' Start a nested ".set nomacro" block.
7322 '>' End a nested ".set nomacro" block.
7323 '*' Behave like %(%< if generating a delayed-branch sequence.
7324 '#' Print a nop if in a ".set noreorder" block.
7325 '/' Like '#', but do nothing within a delayed-branch sequence.
7326 '?' Print "l" if mips_branch_likely is true
7327 '~' Print a nop if mips_branch_likely is true
7328 '.' Print the name of the register with a hard-wired zero (zero or $0).
7329 '@' Print the name of the assembler temporary register (at or $1).
7330 '^' Print the name of the pic call-through register (t9 or $25).
7331 '+' Print the name of the gp register (usually gp or $28).
7332 '$' Print the name of the stack pointer register (sp or $29).
7334 See also mips_init_print_operand_pucnt. */
7337 mips_print_operand_punctuation (FILE *file
, int ch
)
7342 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7346 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7350 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7354 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7358 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7362 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7366 if (final_sequence
!= 0)
7368 mips_print_operand_punctuation (file
, '(');
7369 mips_print_operand_punctuation (file
, '<');
7374 if (mips_noreorder
.nesting_level
> 0)
7375 fputs ("\n\tnop", file
);
7379 /* Print an extra newline so that the delayed insn is separated
7380 from the following ones. This looks neater and is consistent
7381 with non-nop delayed sequences. */
7382 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7383 fputs ("\n\tnop\n", file
);
7387 if (mips_branch_likely
)
7392 if (mips_branch_likely
)
7393 fputs ("\n\tnop", file
);
7397 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7401 fputs (reg_names
[AT_REGNUM
], file
);
7405 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7409 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7413 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7422 /* Initialize mips_print_operand_punct. */
7425 mips_init_print_operand_punct (void)
7429 for (p
= "()[]<>*#/?~.@^+$"; *p
; p
++)
7430 mips_print_operand_punct
[(unsigned char) *p
] = true;
7433 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7434 associated with condition CODE. Print the condition part of the
7438 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7452 /* Conveniently, the MIPS names for these conditions are the same
7453 as their RTL equivalents. */
7454 fputs (GET_RTX_NAME (code
), file
);
7458 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7463 /* Likewise floating-point branches. */
7466 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7471 fputs ("c1f", file
);
7475 fputs ("c1t", file
);
7479 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7484 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7487 mips_print_operand_punct_valid_p (unsigned char code
)
7489 return mips_print_operand_punct
[code
];
7492 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7494 'X' Print CONST_INT OP in hexadecimal format.
7495 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7496 'd' Print CONST_INT OP in decimal.
7497 'm' Print one less than CONST_INT OP in decimal.
7498 'h' Print the high-part relocation associated with OP, after stripping
7500 'R' Print the low-part relocation associated with OP.
7501 'C' Print the integer branch condition for comparison OP.
7502 'N' Print the inverse of the integer branch condition for comparison OP.
7503 'F' Print the FPU branch condition for comparison OP.
7504 'W' Print the inverse of the FPU branch condition for comparison OP.
7505 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7506 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7507 't' Like 'T', but with the EQ/NE cases reversed
7508 'Y' Print mips_fp_conditions[INTVAL (OP)]
7509 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7510 'q' Print a DSP accumulator register.
7511 'D' Print the second part of a double-word register or memory operand.
7512 'L' Print the low-order register in a double-word register operand.
7513 'M' Print high-order register in a double-word register operand.
7514 'z' Print $0 if OP is zero, otherwise print OP normally. */
7517 mips_print_operand (FILE *file
, rtx op
, int letter
)
7521 if (mips_print_operand_punct_valid_p (letter
))
7523 mips_print_operand_punctuation (file
, letter
);
7528 code
= GET_CODE (op
);
7533 if (CONST_INT_P (op
))
7534 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
7536 output_operand_lossage ("invalid use of '%%%c'", letter
);
7540 if (CONST_INT_P (op
))
7541 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
7543 output_operand_lossage ("invalid use of '%%%c'", letter
);
7547 if (CONST_INT_P (op
))
7548 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
7550 output_operand_lossage ("invalid use of '%%%c'", letter
);
7554 if (CONST_INT_P (op
))
7555 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
7557 output_operand_lossage ("invalid use of '%%%c'", letter
);
7563 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
7567 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
7571 mips_print_int_branch_condition (file
, code
, letter
);
7575 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
7579 mips_print_float_branch_condition (file
, code
, letter
);
7583 mips_print_float_branch_condition (file
, reverse_condition (code
),
7590 int truth
= (code
== NE
) == (letter
== 'T');
7591 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
7596 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
7597 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
7599 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7606 mips_print_operand (file
, op
, 0);
7612 if (code
== REG
&& MD_REG_P (REGNO (op
)))
7613 fprintf (file
, "$ac0");
7614 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
7615 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
7617 output_operand_lossage ("invalid use of '%%%c'", letter
);
7625 unsigned int regno
= REGNO (op
);
7626 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
7627 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
7630 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
7631 output_operand_lossage ("invalid use of '%%%c'", letter
);
7632 /* We need to print $0 .. $31 for COP0 registers. */
7633 if (COP0_REG_P (regno
))
7634 fprintf (file
, "$%s", ®_names
[regno
][4]);
7636 fprintf (file
, "%s", reg_names
[regno
]);
7642 output_address (plus_constant (XEXP (op
, 0), 4));
7643 else if (letter
&& letter
!= 'z')
7644 output_operand_lossage ("invalid use of '%%%c'", letter
);
7646 output_address (XEXP (op
, 0));
7650 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
7651 fputs (reg_names
[GP_REG_FIRST
], file
);
7652 else if (letter
&& letter
!= 'z')
7653 output_operand_lossage ("invalid use of '%%%c'", letter
);
7654 else if (CONST_GP_P (op
))
7655 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
7657 output_addr_const (file
, mips_strip_unspec_address (op
));
7663 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7666 mips_print_operand_address (FILE *file
, rtx x
)
7668 struct mips_address_info addr
;
7670 if (mips_classify_address (&addr
, x
, word_mode
, true))
7674 mips_print_operand (file
, addr
.offset
, 0);
7675 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
7678 case ADDRESS_LO_SUM
:
7679 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
7681 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
7684 case ADDRESS_CONST_INT
:
7685 output_addr_const (file
, x
);
7686 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
7689 case ADDRESS_SYMBOLIC
:
7690 output_addr_const (file
, mips_strip_unspec_address (x
));
7696 /* Implement TARGET_ENCODE_SECTION_INFO. */
7699 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
7701 default_encode_section_info (decl
, rtl
, first
);
7703 if (TREE_CODE (decl
) == FUNCTION_DECL
)
7705 rtx symbol
= XEXP (rtl
, 0);
7706 tree type
= TREE_TYPE (decl
);
7708 /* Encode whether the symbol is short or long. */
7709 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
7710 || mips_far_type_p (type
))
7711 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
7715 /* Implement TARGET_SELECT_RTX_SECTION. */
7718 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
7719 unsigned HOST_WIDE_INT align
)
7721 /* ??? Consider using mergeable small data sections. */
7722 if (mips_rtx_constant_in_small_data_p (mode
))
7723 return get_named_section (NULL
, ".sdata", 0);
7725 return default_elf_select_rtx_section (mode
, x
, align
);
7728 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7730 The complication here is that, with the combination TARGET_ABICALLS
7731 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7732 absolute addresses, and should therefore not be included in the
7733 read-only part of a DSO. Handle such cases by selecting a normal
7734 data section instead of a read-only one. The logic apes that in
7735 default_function_rodata_section. */
7738 mips_function_rodata_section (tree decl
)
7740 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
7741 return default_function_rodata_section (decl
);
7743 if (decl
&& DECL_SECTION_NAME (decl
))
7745 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7746 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
7748 char *rname
= ASTRDUP (name
);
7750 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
7752 else if (flag_function_sections
7753 && flag_data_sections
7754 && strncmp (name
, ".text.", 6) == 0)
7756 char *rname
= ASTRDUP (name
);
7757 memcpy (rname
+ 1, "data", 4);
7758 return get_section (rname
, SECTION_WRITE
, decl
);
7761 return data_section
;
7764 /* Implement TARGET_IN_SMALL_DATA_P. */
7767 mips_in_small_data_p (const_tree decl
)
7769 unsigned HOST_WIDE_INT size
;
7771 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
7774 /* We don't yet generate small-data references for -mabicalls
7775 or VxWorks RTP code. See the related -G handling in
7776 mips_option_override. */
7777 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
7780 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
7784 /* Reject anything that isn't in a known small-data section. */
7785 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7786 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
7789 /* If a symbol is defined externally, the assembler will use the
7790 usual -G rules when deciding how to implement macros. */
7791 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
7794 else if (TARGET_EMBEDDED_DATA
)
7796 /* Don't put constants into the small data section: we want them
7797 to be in ROM rather than RAM. */
7798 if (TREE_CODE (decl
) != VAR_DECL
)
7801 if (TREE_READONLY (decl
)
7802 && !TREE_SIDE_EFFECTS (decl
)
7803 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
7807 /* Enforce -mlocal-sdata. */
7808 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
7811 /* Enforce -mextern-sdata. */
7812 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
7814 if (DECL_EXTERNAL (decl
))
7816 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
7820 /* We have traditionally not treated zero-sized objects as small data,
7821 so this is now effectively part of the ABI. */
7822 size
= int_size_in_bytes (TREE_TYPE (decl
));
7823 return size
> 0 && size
<= mips_small_data_threshold
;
7826 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7827 anchors for small data: the GP register acts as an anchor in that
7828 case. We also don't want to use them for PC-relative accesses,
7829 where the PC acts as an anchor. */
7832 mips_use_anchors_for_symbol_p (const_rtx symbol
)
7834 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
7836 case SYMBOL_PC_RELATIVE
:
7837 case SYMBOL_GP_RELATIVE
:
7841 return default_use_anchors_for_symbol_p (symbol
);
7845 /* The MIPS debug format wants all automatic variables and arguments
7846 to be in terms of the virtual frame pointer (stack pointer before
7847 any adjustment in the function), while the MIPS 3.0 linker wants
7848 the frame pointer to be the stack pointer after the initial
7849 adjustment. So, we do the adjustment here. The arg pointer (which
7850 is eliminated) points to the virtual frame pointer, while the frame
7851 pointer (which may be eliminated) points to the stack pointer after
7852 the initial adjustments. */
7855 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
7857 rtx offset2
= const0_rtx
;
7858 rtx reg
= eliminate_constant_term (addr
, &offset2
);
7861 offset
= INTVAL (offset2
);
7863 if (reg
== stack_pointer_rtx
7864 || reg
== frame_pointer_rtx
7865 || reg
== hard_frame_pointer_rtx
)
7867 offset
-= cfun
->machine
->frame
.total_size
;
7868 if (reg
== hard_frame_pointer_rtx
)
7869 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
7872 /* sdbout_parms does not want this to crash for unrecognized cases. */
7874 else if (reg
!= arg_pointer_rtx
)
7875 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7882 /* Implement ASM_OUTPUT_EXTERNAL. */
7885 mips_output_external (FILE *file
, tree decl
, const char *name
)
7887 default_elf_asm_output_external (file
, decl
, name
);
7889 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7890 set in order to avoid putting out names that are never really
7892 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
7894 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
7896 /* When using assembler macros, emit .extern directives for
7897 all small-data externs so that the assembler knows how
7900 In most cases it would be safe (though pointless) to emit
7901 .externs for other symbols too. One exception is when an
7902 object is within the -G limit but declared by the user to
7903 be in a section other than .sbss or .sdata. */
7904 fputs ("\t.extern\t", file
);
7905 assemble_name (file
, name
);
7906 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
7907 int_size_in_bytes (TREE_TYPE (decl
)));
7912 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7915 mips_output_filename (FILE *stream
, const char *name
)
7917 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7919 if (write_symbols
== DWARF2_DEBUG
)
7921 else if (mips_output_filename_first_time
)
7923 mips_output_filename_first_time
= 0;
7924 num_source_filenames
+= 1;
7925 current_function_file
= name
;
7926 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7927 output_quoted_string (stream
, name
);
7928 putc ('\n', stream
);
7930 /* If we are emitting stabs, let dbxout.c handle this (except for
7931 the mips_output_filename_first_time case). */
7932 else if (write_symbols
== DBX_DEBUG
)
7934 else if (name
!= current_function_file
7935 && strcmp (name
, current_function_file
) != 0)
7937 num_source_filenames
+= 1;
7938 current_function_file
= name
;
7939 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7940 output_quoted_string (stream
, name
);
7941 putc ('\n', stream
);
7945 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7947 static void ATTRIBUTE_UNUSED
7948 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7953 fputs ("\t.dtprelword\t", file
);
7957 fputs ("\t.dtpreldword\t", file
);
7963 output_addr_const (file
, x
);
7964 fputs ("+0x8000", file
);
7967 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7970 mips_dwarf_register_span (rtx reg
)
7973 enum machine_mode mode
;
7975 /* By default, GCC maps increasing register numbers to increasing
7976 memory locations, but paired FPRs are always little-endian,
7977 regardless of the prevailing endianness. */
7978 mode
= GET_MODE (reg
);
7979 if (FP_REG_P (REGNO (reg
))
7980 && TARGET_BIG_ENDIAN
7981 && MAX_FPRS_PER_FMT
> 1
7982 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
7984 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
7985 high
= mips_subword (reg
, true);
7986 low
= mips_subword (reg
, false);
7987 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
7993 /* Implement ASM_OUTPUT_ASCII. */
7996 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8002 fprintf (stream
, "\t.ascii\t\"");
8003 for (i
= 0; i
< len
; i
++)
8007 c
= (unsigned char) string
[i
];
8010 if (c
== '\\' || c
== '\"')
8012 putc ('\\', stream
);
8020 fprintf (stream
, "\\%03o", c
);
8024 if (cur_pos
> 72 && i
+1 < len
)
8027 fprintf (stream
, "\"\n\t.ascii\t\"");
8030 fprintf (stream
, "\"\n");
8033 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8034 macros, mark the symbol as written so that mips_asm_output_external
8035 won't emit an .extern for it. STREAM is the output file, NAME is the
8036 name of the symbol, INIT_STRING is the string that should be written
8037 before the symbol and FINAL_STRING is the string that should be
8038 written after it. FINAL_STRING is a printf format that consumes the
8039 remaining arguments. */
8042 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8043 const char *final_string
, ...)
8047 fputs (init_string
, stream
);
8048 assemble_name (stream
, name
);
8049 va_start (ap
, final_string
);
8050 vfprintf (stream
, final_string
, ap
);
8053 if (!TARGET_EXPLICIT_RELOCS
)
8055 tree name_tree
= get_identifier (name
);
8056 TREE_ASM_WRITTEN (name_tree
) = 1;
8060 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8061 NAME is the name of the object and ALIGN is the required alignment
8062 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8063 alignment argument. */
8066 mips_declare_common_object (FILE *stream
, const char *name
,
8067 const char *init_string
,
8068 unsigned HOST_WIDE_INT size
,
8069 unsigned int align
, bool takes_alignment_p
)
8071 if (!takes_alignment_p
)
8073 size
+= (align
/ BITS_PER_UNIT
) - 1;
8074 size
-= size
% (align
/ BITS_PER_UNIT
);
8075 mips_declare_object (stream
, name
, init_string
,
8076 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8079 mips_declare_object (stream
, name
, init_string
,
8080 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8081 size
, align
/ BITS_PER_UNIT
);
8084 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8085 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8088 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8089 unsigned HOST_WIDE_INT size
,
8092 /* If the target wants uninitialized const declarations in
8093 .rdata then don't put them in .comm. */
8094 if (TARGET_EMBEDDED_DATA
8095 && TARGET_UNINIT_CONST_IN_RODATA
8096 && TREE_CODE (decl
) == VAR_DECL
8097 && TREE_READONLY (decl
)
8098 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8100 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8101 targetm
.asm_out
.globalize_label (stream
, name
);
8103 switch_to_section (readonly_data_section
);
8104 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8105 mips_declare_object (stream
, name
, "",
8106 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8110 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8114 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8115 extern int size_directive_output
;
8117 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8118 definitions except that it uses mips_declare_object to emit the label. */
8121 mips_declare_object_name (FILE *stream
, const char *name
,
8122 tree decl ATTRIBUTE_UNUSED
)
8124 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8125 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8128 size_directive_output
= 0;
8129 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8133 size_directive_output
= 1;
8134 size
= int_size_in_bytes (TREE_TYPE (decl
));
8135 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8138 mips_declare_object (stream
, name
, "", ":\n");
8141 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8144 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8148 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8149 if (!flag_inhibit_size_directive
8150 && DECL_SIZE (decl
) != 0
8153 && DECL_INITIAL (decl
) == error_mark_node
8154 && !size_directive_output
)
8158 size_directive_output
= 1;
8159 size
= int_size_in_bytes (TREE_TYPE (decl
));
8160 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8165 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8166 with the current ABI. */
8169 mips_mdebug_abi_name (void)
8182 return TARGET_64BIT
? "eabi64" : "eabi32";
8188 /* Implement TARGET_ASM_FILE_START. */
8191 mips_file_start (void)
8193 default_file_start ();
8195 /* Generate a special section to describe the ABI switches used to
8196 produce the resultant binary. This is unnecessary on IRIX and
8197 causes unwanted warnings from the native linker. */
8200 /* Record the ABI itself. Modern versions of binutils encode
8201 this information in the ELF header flags, but GDB needs the
8202 information in order to correctly debug binaries produced by
8203 older binutils. See the function mips_gdbarch_init in
8205 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8206 mips_mdebug_abi_name ());
8208 /* There is no ELF header flag to distinguish long32 forms of the
8209 EABI from long64 forms. Emit a special section to help tools
8210 such as GDB. Do the same for o64, which is sometimes used with
8212 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8213 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8214 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8216 #ifdef HAVE_AS_GNU_ATTRIBUTE
8220 /* No floating-point operations, -mno-float. */
8221 if (TARGET_NO_FLOAT
)
8223 /* Soft-float code, -msoft-float. */
8224 else if (!TARGET_HARD_FLOAT_ABI
)
8226 /* Single-float code, -msingle-float. */
8227 else if (!TARGET_DOUBLE_FLOAT
)
8229 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8230 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8232 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8236 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8241 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8242 if (TARGET_ABICALLS
)
8244 fprintf (asm_out_file
, "\t.abicalls\n");
8245 if (TARGET_ABICALLS_PIC0
)
8246 fprintf (asm_out_file
, "\t.option\tpic0\n");
8249 if (flag_verbose_asm
)
8250 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8252 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8255 /* Make the last instruction frame-related and note that it performs
8256 the operation described by FRAME_PATTERN. */
8259 mips_set_frame_expr (rtx frame_pattern
)
8263 insn
= get_last_insn ();
8264 RTX_FRAME_RELATED_P (insn
) = 1;
8265 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8270 /* Return a frame-related rtx that stores REG at MEM.
8271 REG must be a single register. */
8274 mips_frame_set (rtx mem
, rtx reg
)
8278 /* If we're saving the return address register and the DWARF return
8279 address column differs from the hard register number, adjust the
8280 note reg to refer to the former. */
8281 if (REGNO (reg
) == RETURN_ADDR_REGNUM
8282 && DWARF_FRAME_RETURN_COLUMN
!= RETURN_ADDR_REGNUM
)
8283 reg
= gen_rtx_REG (GET_MODE (reg
), DWARF_FRAME_RETURN_COLUMN
);
8285 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8286 RTX_FRAME_RELATED_P (set
) = 1;
8291 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8292 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8293 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8294 static const unsigned char mips16e_s2_s8_regs
[] = {
8295 30, 23, 22, 21, 20, 19, 18
8297 static const unsigned char mips16e_a0_a3_regs
[] = {
8301 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8302 ordered from the uppermost in memory to the lowest in memory. */
8303 static const unsigned char mips16e_save_restore_regs
[] = {
8304 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8307 /* Return the index of the lowest X in the range [0, SIZE) for which
8308 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8311 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8316 for (i
= 0; i
< size
; i
++)
8317 if (BITSET_P (mask
, regs
[i
]))
8323 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8324 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8325 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8326 is true for all indexes (X, SIZE). */
8329 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8330 unsigned int size
, unsigned int *num_regs_ptr
)
8334 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8335 for (i
++; i
< size
; i
++)
8336 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8339 *mask_ptr
|= 1 << regs
[i
];
8343 /* Return a simplified form of X using the register values in REG_VALUES.
8344 REG_VALUES[R] is the last value assigned to hard register R, or null
8345 if R has not been modified.
8347 This function is rather limited, but is good enough for our purposes. */
8350 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8352 x
= avoid_constant_pool_reference (x
);
8356 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8357 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
8358 x0
, GET_MODE (XEXP (x
, 0)));
8361 if (ARITHMETIC_P (x
))
8363 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8364 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
8365 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
8369 && reg_values
[REGNO (x
)]
8370 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
8371 return reg_values
[REGNO (x
)];
8376 /* Return true if (set DEST SRC) stores an argument register into its
8377 caller-allocated save slot, storing the number of that argument
8378 register in *REGNO_PTR if so. REG_VALUES is as for
8379 mips16e_collect_propagate_value. */
8382 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
8383 unsigned int *regno_ptr
)
8385 unsigned int argno
, regno
;
8386 HOST_WIDE_INT offset
, required_offset
;
8389 /* Check that this is a word-mode store. */
8390 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
8393 /* Check that the register being saved is an unmodified argument
8395 regno
= REGNO (src
);
8396 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
8398 argno
= regno
- GP_ARG_FIRST
;
8400 /* Check whether the address is an appropriate stack-pointer or
8401 frame-pointer access. */
8402 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
8403 mips_split_plus (addr
, &base
, &offset
);
8404 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
8405 if (base
== hard_frame_pointer_rtx
)
8406 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8407 else if (base
!= stack_pointer_rtx
)
8409 if (offset
!= required_offset
)
8416 /* A subroutine of mips_expand_prologue, called only when generating
8417 MIPS16e SAVE instructions. Search the start of the function for any
8418 instructions that save argument registers into their caller-allocated
8419 save slots. Delete such instructions and return a value N such that
8420 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8421 instructions redundant. */
8424 mips16e_collect_argument_saves (void)
8426 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
8427 rtx insn
, next
, set
, dest
, src
;
8428 unsigned int nargs
, regno
;
8430 push_topmost_sequence ();
8432 memset (reg_values
, 0, sizeof (reg_values
));
8433 for (insn
= get_insns (); insn
; insn
= next
)
8435 next
= NEXT_INSN (insn
);
8436 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
8442 set
= PATTERN (insn
);
8443 if (GET_CODE (set
) != SET
)
8446 dest
= SET_DEST (set
);
8447 src
= SET_SRC (set
);
8448 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
8450 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
8453 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
8456 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
8457 reg_values
[REGNO (dest
)]
8458 = mips16e_collect_propagate_value (src
, reg_values
);
8462 pop_topmost_sequence ();
8467 /* Return a move between register REGNO and memory location SP + OFFSET.
8468 Make the move a load if RESTORE_P, otherwise make it a frame-related
8472 mips16e_save_restore_reg (bool restore_p
, HOST_WIDE_INT offset
,
8477 mem
= gen_frame_mem (SImode
, plus_constant (stack_pointer_rtx
, offset
));
8478 reg
= gen_rtx_REG (SImode
, regno
);
8480 ? gen_rtx_SET (VOIDmode
, reg
, mem
)
8481 : mips_frame_set (mem
, reg
));
8484 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8485 The instruction must:
8487 - Allocate or deallocate SIZE bytes in total; SIZE is known
8490 - Save or restore as many registers in *MASK_PTR as possible.
8491 The instruction saves the first registers at the top of the
8492 allocated area, with the other registers below it.
8494 - Save NARGS argument registers above the allocated area.
8496 (NARGS is always zero if RESTORE_P.)
8498 The SAVE and RESTORE instructions cannot save and restore all general
8499 registers, so there may be some registers left over for the caller to
8500 handle. Destructively modify *MASK_PTR so that it contains the registers
8501 that still need to be saved or restored. The caller can save these
8502 registers in the memory immediately below *OFFSET_PTR, which is a
8503 byte offset from the bottom of the allocated stack area. */
8506 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
8507 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
8511 HOST_WIDE_INT offset
, top_offset
;
8512 unsigned int i
, regno
;
8515 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
8517 /* Calculate the number of elements in the PARALLEL. We need one element
8518 for the stack adjustment, one for each argument register save, and one
8519 for each additional register move. */
8521 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8522 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
8525 /* Create the final PARALLEL. */
8526 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
8529 /* Add the stack pointer adjustment. */
8530 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8531 plus_constant (stack_pointer_rtx
,
8532 restore_p
? size
: -size
));
8533 RTX_FRAME_RELATED_P (set
) = 1;
8534 XVECEXP (pattern
, 0, n
++) = set
;
8536 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8537 top_offset
= restore_p
? size
: 0;
8539 /* Save the arguments. */
8540 for (i
= 0; i
< nargs
; i
++)
8542 offset
= top_offset
+ i
* UNITS_PER_WORD
;
8543 set
= mips16e_save_restore_reg (restore_p
, offset
, GP_ARG_FIRST
+ i
);
8544 XVECEXP (pattern
, 0, n
++) = set
;
8547 /* Then fill in the other register moves. */
8548 offset
= top_offset
;
8549 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8551 regno
= mips16e_save_restore_regs
[i
];
8552 if (BITSET_P (*mask_ptr
, regno
))
8554 offset
-= UNITS_PER_WORD
;
8555 set
= mips16e_save_restore_reg (restore_p
, offset
, regno
);
8556 XVECEXP (pattern
, 0, n
++) = set
;
8557 *mask_ptr
&= ~(1 << regno
);
8561 /* Tell the caller what offset it should use for the remaining registers. */
8562 *offset_ptr
= size
+ (offset
- top_offset
);
8564 gcc_assert (n
== XVECLEN (pattern
, 0));
8569 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8570 pointer. Return true if PATTERN matches the kind of instruction
8571 generated by mips16e_build_save_restore. If INFO is nonnull,
8572 initialize it when returning true. */
8575 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
8576 struct mips16e_save_restore_info
*info
)
8578 unsigned int i
, nargs
, mask
, extra
;
8579 HOST_WIDE_INT top_offset
, save_offset
, offset
;
8580 rtx set
, reg
, mem
, base
;
8583 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
8586 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8587 top_offset
= adjust
> 0 ? adjust
: 0;
8589 /* Interpret all other members of the PARALLEL. */
8590 save_offset
= top_offset
- UNITS_PER_WORD
;
8594 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
8596 /* Check that we have a SET. */
8597 set
= XVECEXP (pattern
, 0, n
);
8598 if (GET_CODE (set
) != SET
)
8601 /* Check that the SET is a load (if restoring) or a store
8603 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
8607 /* Check that the address is the sum of the stack pointer and a
8608 possibly-zero constant offset. */
8609 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
8610 if (base
!= stack_pointer_rtx
)
8613 /* Check that SET's other operand is a register. */
8614 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
8618 /* Check for argument saves. */
8619 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
8620 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
8622 else if (offset
== save_offset
)
8624 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
8625 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
8628 mask
|= 1 << REGNO (reg
);
8629 save_offset
-= UNITS_PER_WORD
;
8635 /* Check that the restrictions on register ranges are met. */
8637 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
8638 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
8639 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
8640 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
8644 /* Make sure that the topmost argument register is not saved twice.
8645 The checks above ensure that the same is then true for the other
8646 argument registers. */
8647 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
8650 /* Pass back information, if requested. */
8653 info
->nargs
= nargs
;
8655 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
8661 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8662 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8663 the null terminator. */
8666 mips16e_add_register_range (char *s
, unsigned int min_reg
,
8667 unsigned int max_reg
)
8669 if (min_reg
!= max_reg
)
8670 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
8672 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
8676 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8677 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8680 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
8682 static char buffer
[300];
8684 struct mips16e_save_restore_info info
;
8685 unsigned int i
, end
;
8688 /* Parse the pattern. */
8689 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
8692 /* Add the mnemonic. */
8693 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
8696 /* Save the arguments. */
8698 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
8699 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
8700 else if (info
.nargs
== 1)
8701 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
8703 /* Emit the amount of stack space to allocate or deallocate. */
8704 s
+= sprintf (s
, "%d", (int) info
.size
);
8706 /* Save or restore $16. */
8707 if (BITSET_P (info
.mask
, 16))
8708 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
8710 /* Save or restore $17. */
8711 if (BITSET_P (info
.mask
, 17))
8712 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
8714 /* Save or restore registers in the range $s2...$s8, which
8715 mips16e_s2_s8_regs lists in decreasing order. Note that this
8716 is a software register range; the hardware registers are not
8717 numbered consecutively. */
8718 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
8719 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
8721 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
8722 mips16e_s2_s8_regs
[i
]);
8724 /* Save or restore registers in the range $a0...$a3. */
8725 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
8726 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
8728 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
8729 mips16e_a0_a3_regs
[end
- 1]);
8731 /* Save or restore $31. */
8732 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
8733 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
8738 /* Return true if the current function returns its value in a floating-point
8739 register in MIPS16 mode. */
8742 mips16_cfun_returns_in_fpr_p (void)
8744 tree return_type
= DECL_RESULT (current_function_decl
);
8745 return (TARGET_MIPS16
8746 && TARGET_HARD_FLOAT_ABI
8747 && !aggregate_value_p (return_type
, current_function_decl
)
8748 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
8751 /* Return true if predicate PRED is true for at least one instruction.
8752 Cache the result in *CACHE, and assume that the result is true
8753 if *CACHE is already true. */
8756 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
8762 push_topmost_sequence ();
8763 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8764 if (USEFUL_INSN_P (insn
) && pred (insn
))
8769 pop_topmost_sequence ();
8774 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8775 See mips_cfun_has_inflexible_gp_ref_p for details. */
8778 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
8780 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8781 indicate that the target could be a traditional MIPS
8782 lazily-binding stub. */
8783 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
8786 /* Return true if the current function refers to the global pointer
8787 in a way that forces $28 to be valid. This means that we can't
8788 change the choice of global pointer, even for NewABI code.
8790 One example of this (and one which needs several checks) is that
8791 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8792 (This restriction does not apply to PLTs.) */
8795 mips_cfun_has_inflexible_gp_ref_p (void)
8797 /* If the function has a nonlocal goto, $28 must hold the correct
8798 global pointer for the target function. That is, the target
8799 of the goto implicitly uses $28. */
8800 if (crtl
->has_nonlocal_goto
)
8803 if (TARGET_ABICALLS_PIC2
)
8805 /* Symbolic accesses implicitly use the global pointer unless
8806 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8807 might go to traditional MIPS lazy-binding stubs. */
8808 if (!TARGET_EXPLICIT_RELOCS
)
8811 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8812 can be lazily-bound. */
8816 /* MIPS16 functions that return in FPRs need to call an
8817 external libgcc routine. This call is only made explict
8818 during mips_expand_epilogue, and it too might be lazily bound. */
8819 if (mips16_cfun_returns_in_fpr_p ())
8823 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
8824 mips_insn_has_inflexible_gp_ref_p
);
8827 /* Return true if INSN refers to the global pointer in a "flexible" way.
8828 See mips_cfun_has_flexible_gp_ref_p for details. */
8831 mips_insn_has_flexible_gp_ref_p (rtx insn
)
8833 return (get_attr_got (insn
) != GOT_UNSET
8834 || mips_small_data_pattern_p (PATTERN (insn
))
8835 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
8838 /* Return true if the current function references the global pointer,
8839 but if those references do not inherently require the global pointer
8840 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8843 mips_cfun_has_flexible_gp_ref_p (void)
8845 /* Reload can sometimes introduce constant pool references
8846 into a function that otherwise didn't need them. For example,
8847 suppose we have an instruction like:
8849 (set (reg:DF R1) (float:DF (reg:SI R2)))
8851 If R2 turns out to be a constant such as 1, the instruction may
8852 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8853 the option of using this constant if R2 doesn't get allocated
8856 In cases like these, reload will have added the constant to the
8857 pool but no instruction will yet refer to it. */
8858 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
8861 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
8862 mips_insn_has_flexible_gp_ref_p
);
8865 /* Return the register that should be used as the global pointer
8866 within this function. Return INVALID_REGNUM if the function
8867 doesn't need a global pointer. */
8870 mips_global_pointer (void)
8874 /* $gp is always available unless we're using a GOT. */
8875 if (!TARGET_USE_GOT
)
8876 return GLOBAL_POINTER_REGNUM
;
8878 /* If there are inflexible references to $gp, we must use the
8879 standard register. */
8880 if (mips_cfun_has_inflexible_gp_ref_p ())
8881 return GLOBAL_POINTER_REGNUM
;
8883 /* If there are no current references to $gp, then the only uses
8884 we can introduce later are those involved in long branches. */
8885 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
8886 return INVALID_REGNUM
;
8888 /* If the global pointer is call-saved, try to use a call-clobbered
8890 if (TARGET_CALL_SAVED_GP
&& current_function_is_leaf
)
8891 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
8892 if (!df_regs_ever_live_p (regno
)
8893 && call_really_used_regs
[regno
]
8894 && !fixed_regs
[regno
]
8895 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
8898 return GLOBAL_POINTER_REGNUM
;
8901 /* Return true if the current function's prologue must load the global
8902 pointer value into pic_offset_table_rtx and store the same value in
8903 the function's cprestore slot (if any).
8905 One problem we have to deal with is that, when emitting GOT-based
8906 position independent code, long-branch sequences will need to load
8907 the address of the branch target from the GOT. We don't know until
8908 the very end of compilation whether (and where) the function needs
8909 long branches, so we must ensure that _any_ branch can access the
8910 global pointer in some form. However, we do not want to pessimize
8911 the usual case in which all branches are short.
8913 We handle this as follows:
8915 (1) During reload, we set cfun->machine->global_pointer to
8916 INVALID_REGNUM if we _know_ that the current function
8917 doesn't need a global pointer. This is only valid if
8918 long branches don't need the GOT.
8920 Otherwise, we assume that we might need a global pointer
8921 and pick an appropriate register.
8923 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8924 we ensure that the global pointer is available at every
8925 block boundary bar entry and exit. We do this in one of two ways:
8927 - If the function has a cprestore slot, we ensure that this
8928 slot is valid at every branch. However, as explained in
8929 point (6) below, there is no guarantee that pic_offset_table_rtx
8930 itself is valid if new uses of the global pointer are introduced
8931 after the first post-epilogue split.
8933 We guarantee that the cprestore slot is valid by loading it
8934 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8935 this register live at every block boundary bar function entry
8936 and exit. It is then invalid to move the load (and thus the
8937 preceding store) across a block boundary.
8939 - If the function has no cprestore slot, we guarantee that
8940 pic_offset_table_rtx itself is valid at every branch.
8942 See mips_eh_uses for the handling of the register liveness.
8944 (3) During prologue and epilogue generation, we emit "ghost"
8945 placeholder instructions to manipulate the global pointer.
8947 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8948 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8949 that the function needs a global pointer. (There is no need to set
8950 them earlier than this, and doing it as late as possible leads to
8951 fewer false positives.)
8953 (5) If cfun->machine->must_initialize_gp_p is true during a
8954 split_insns pass, we split the ghost instructions into real
8955 instructions. These split instructions can then be optimized in
8956 the usual way. Otherwise, we keep the ghost instructions intact,
8957 and optimize for the case where they aren't needed. We still
8958 have the option of splitting them later, if we need to introduce
8959 new uses of the global pointer.
8961 For example, the scheduler ignores a ghost instruction that
8962 stores $28 to the stack, but it handles the split form of
8963 the ghost instruction as an ordinary store.
8965 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8966 is true during the first post-epilogue split_insns pass, we split
8967 calls and restore_gp patterns into instructions that explicitly
8968 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8969 we split these patterns into instructions that _don't_ load from
8972 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8973 time of the split, then any instructions that exist at that time
8974 can make free use of pic_offset_table_rtx. However, if we want
8975 to introduce new uses of the global pointer after the split,
8976 we must explicitly load the value from the cprestore slot, since
8977 pic_offset_table_rtx itself might not be valid at a given point
8980 The idea is that we want to be able to delete redundant
8981 loads from the cprestore slot in the usual case where no
8982 long branches are needed.
8984 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8985 of md_reorg, we decide whether the global pointer is needed for
8986 long branches. If so, we set cfun->machine->must_initialize_gp_p
8987 to true and split the ghost instructions into real instructions
8990 Note that the ghost instructions must have a zero length for three reasons:
8992 - Giving the length of the underlying $gp sequence might cause
8993 us to use long branches in cases where they aren't really needed.
8995 - They would perturb things like alignment calculations.
8997 - More importantly, the hazard detection in md_reorg relies on
8998 empty instructions having a zero length.
9000 If we find a long branch and split the ghost instructions at the
9001 end of md_reorg, the split could introduce more long branches.
9002 That isn't a problem though, because we still do the split before
9003 the final shorten_branches pass.
9005 This is extremely ugly, but it seems like the best compromise between
9006 correctness and efficiency. */
9009 mips_must_initialize_gp_p (void)
9011 return cfun
->machine
->must_initialize_gp_p
;
9014 /* Return true if REGNO is a register that is ordinarily call-clobbered
9015 but must nevertheless be preserved by an interrupt handler. */
9018 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9020 if (MD_REG_P (regno
))
9023 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9026 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9028 /* $0 is hard-wired. */
9029 if (regno
== GP_REG_FIRST
)
9032 /* The interrupt handler can treat kernel registers as
9033 scratch registers. */
9034 if (KERNEL_REG_P (regno
))
9037 /* The function will return the stack pointer to its original value
9039 if (regno
== STACK_POINTER_REGNUM
)
9042 /* Otherwise, return true for registers that aren't ordinarily
9044 return call_really_used_regs
[regno
];
9050 /* Return true if the current function should treat register REGNO
9054 mips_cfun_call_saved_reg_p (unsigned int regno
)
9056 /* Interrupt handlers need to save extra registers. */
9057 if (cfun
->machine
->interrupt_handler_p
9058 && mips_interrupt_extra_call_saved_reg_p (regno
))
9061 /* call_insns preserve $28 unless they explicitly say otherwise,
9062 so call_really_used_regs[] treats $28 as call-saved. However,
9063 we want the ABI property rather than the default call_insn
9065 return (regno
== GLOBAL_POINTER_REGNUM
9066 ? TARGET_CALL_SAVED_GP
9067 : !call_really_used_regs
[regno
]);
9070 /* Return true if the function body might clobber register REGNO.
9071 We know that REGNO is call-saved. */
9074 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9076 /* Some functions should be treated as clobbering all call-saved
9078 if (crtl
->saves_all_registers
)
9081 /* DF handles cases where a register is explicitly referenced in
9082 the rtl. Incoming values are passed in call-clobbered registers,
9083 so we can assume that any live call-saved register is set within
9085 if (df_regs_ever_live_p (regno
))
9088 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9089 These clobbers are not explicit in the rtl. */
9090 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9093 /* If we're using a call-saved global pointer, the function's
9094 prologue will need to set it up. */
9095 if (cfun
->machine
->global_pointer
== regno
)
9098 /* The function's prologue will need to set the frame pointer if
9099 frame_pointer_needed. */
9100 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9103 /* If a MIPS16 function returns a value in FPRs, its epilogue
9104 will need to call an external libgcc routine. This yet-to-be
9105 generated call_insn will clobber $31. */
9106 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9109 /* If REGNO is ordinarily call-clobbered, we must assume that any
9110 called function could modify it. */
9111 if (cfun
->machine
->interrupt_handler_p
9112 && !current_function_is_leaf
9113 && mips_interrupt_extra_call_saved_reg_p (regno
))
9119 /* Return true if the current function must save register REGNO. */
9122 mips_save_reg_p (unsigned int regno
)
9124 if (mips_cfun_call_saved_reg_p (regno
))
9126 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9129 /* Save both registers in an FPR pair if either one is used. This is
9130 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9131 register to be used without the even register. */
9132 if (FP_REG_P (regno
)
9133 && MAX_FPRS_PER_FMT
== 2
9134 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9138 /* We need to save the incoming return address if __builtin_eh_return
9139 is being used to set a different return address. */
9140 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9146 /* Populate the current function's mips_frame_info structure.
9148 MIPS stack frames look like:
9150 +-------------------------------+
9152 | incoming stack arguments |
9154 +-------------------------------+
9156 | caller-allocated save area |
9157 A | for register arguments |
9159 +-------------------------------+ <-- incoming stack pointer
9161 | callee-allocated save area |
9162 B | for arguments that are |
9163 | split between registers and |
9166 +-------------------------------+ <-- arg_pointer_rtx
9168 C | callee-allocated save area |
9169 | for register varargs |
9171 +-------------------------------+ <-- frame_pointer_rtx
9172 | | + cop0_sp_offset
9173 | COP0 reg save area | + UNITS_PER_WORD
9175 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9176 | | + UNITS_PER_WORD
9177 | accumulator save area |
9179 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9180 | | + UNITS_PER_HWFPVALUE
9183 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9184 | | + UNITS_PER_WORD
9187 +-------------------------------+ <-- frame_pointer_rtx with
9188 | | \ -fstack-protector
9189 | local variables | | var_size
9191 +-------------------------------+
9193 | $gp save area | | cprestore_size
9195 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9197 | outgoing stack arguments | |
9199 +-------------------------------+ | args_size
9201 | caller-allocated save area | |
9202 | for register arguments | |
9204 +-------------------------------+ <-- stack_pointer_rtx
9205 frame_pointer_rtx without
9207 hard_frame_pointer_rtx for
9210 At least two of A, B and C will be empty.
9212 Dynamic stack allocations such as alloca insert data at point P.
9213 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9214 hard_frame_pointer_rtx unchanged. */
9217 mips_compute_frame_info (void)
9219 struct mips_frame_info
*frame
;
9220 HOST_WIDE_INT offset
, size
;
9221 unsigned int regno
, i
;
9223 /* Set this function's interrupt properties. */
9224 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9227 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9228 else if (TARGET_HARD_FLOAT
)
9229 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9230 else if (TARGET_MIPS16
)
9231 error ("interrupt handlers cannot be MIPS16 functions");
9234 cfun
->machine
->interrupt_handler_p
= true;
9235 cfun
->machine
->use_shadow_register_set_p
=
9236 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9237 cfun
->machine
->keep_interrupts_masked_p
=
9238 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9239 cfun
->machine
->use_debug_exception_return_p
=
9240 mips_use_debug_exception_return_p (TREE_TYPE
9241 (current_function_decl
));
9245 frame
= &cfun
->machine
->frame
;
9246 memset (frame
, 0, sizeof (*frame
));
9247 size
= get_frame_size ();
9249 cfun
->machine
->global_pointer
= mips_global_pointer ();
9251 /* The first two blocks contain the outgoing argument area and the $gp save
9252 slot. This area isn't needed in leaf functions, but if the
9253 target-independent frame size is nonzero, we have already committed to
9254 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9255 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && current_function_is_leaf
)
9257 /* The MIPS 3.0 linker does not like functions that dynamically
9258 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9259 looks like we are trying to create a second frame pointer to the
9260 function, so allocate some stack space to make it happy. */
9261 if (cfun
->calls_alloca
)
9262 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9264 frame
->args_size
= 0;
9265 frame
->cprestore_size
= 0;
9269 frame
->args_size
= crtl
->outgoing_args_size
;
9270 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9272 offset
= frame
->args_size
+ frame
->cprestore_size
;
9274 /* Move above the local variables. */
9275 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9276 offset
+= frame
->var_size
;
9278 /* Find out which GPRs we need to save. */
9279 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9280 if (mips_save_reg_p (regno
))
9283 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9286 /* If this function calls eh_return, we must also save and restore the
9287 EH data registers. */
9288 if (crtl
->calls_eh_return
)
9289 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9292 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9295 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9296 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9297 save all later registers too. */
9298 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9300 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9301 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9302 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9303 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9306 /* Move above the GPR save area. */
9307 if (frame
->num_gp
> 0)
9309 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9310 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9313 /* Find out which FPRs we need to save. This loop must iterate over
9314 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9315 if (TARGET_HARD_FLOAT
)
9316 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9317 if (mips_save_reg_p (regno
))
9319 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9320 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9323 /* Move above the FPR save area. */
9324 if (frame
->num_fp
> 0)
9326 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9327 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9330 /* Add in space for the interrupt context information. */
9331 if (cfun
->machine
->interrupt_handler_p
)
9334 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9337 frame
->acc_mask
|= (1 << 0);
9340 /* Check accumulators 1, 2, 3. */
9341 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
9342 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
9345 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
9348 /* All interrupt context functions need space to preserve STATUS. */
9349 frame
->num_cop0_regs
++;
9351 /* If we don't keep interrupts masked, we need to save EPC. */
9352 if (!cfun
->machine
->keep_interrupts_masked_p
)
9353 frame
->num_cop0_regs
++;
9356 /* Move above the accumulator save area. */
9357 if (frame
->num_acc
> 0)
9359 /* Each accumulator needs 2 words. */
9360 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
9361 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
9364 /* Move above the COP0 register save area. */
9365 if (frame
->num_cop0_regs
> 0)
9367 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
9368 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
9371 /* Move above the callee-allocated varargs save area. */
9372 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
9373 frame
->arg_pointer_offset
= offset
;
9375 /* Move above the callee-allocated area for pretend stack arguments. */
9376 offset
+= crtl
->args
.pretend_args_size
;
9377 frame
->total_size
= offset
;
9379 /* Work out the offsets of the save areas from the top of the frame. */
9380 if (frame
->gp_sp_offset
> 0)
9381 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
9382 if (frame
->fp_sp_offset
> 0)
9383 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
9384 if (frame
->acc_sp_offset
> 0)
9385 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
9386 if (frame
->num_cop0_regs
> 0)
9387 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
9389 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9390 arguments. This tends to increase the chances of using unextended
9391 instructions for local variables and incoming arguments. */
9393 frame
->hard_frame_pointer_offset
= frame
->args_size
;
9396 /* Return the style of GP load sequence that is being used for the
9397 current function. */
9399 enum mips_loadgp_style
9400 mips_current_loadgp_style (void)
9402 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
9408 if (TARGET_ABSOLUTE_ABICALLS
)
9409 return LOADGP_ABSOLUTE
;
9411 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
9414 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9417 mips_frame_pointer_required (void)
9419 /* If the function contains dynamic stack allocations, we need to
9420 use the frame pointer to access the static parts of the frame. */
9421 if (cfun
->calls_alloca
)
9424 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9425 reload may be unable to compute the address of a local variable,
9426 since there is no way to add a large constant to the stack pointer
9427 without using a second temporary register. */
9430 mips_compute_frame_info ();
9431 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
9438 /* Make sure that we're not trying to eliminate to the wrong hard frame
9442 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
9444 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
9447 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9448 or argument pointer. TO is either the stack pointer or hard frame
9452 mips_initial_elimination_offset (int from
, int to
)
9454 HOST_WIDE_INT offset
;
9456 mips_compute_frame_info ();
9458 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9461 case FRAME_POINTER_REGNUM
:
9462 if (FRAME_GROWS_DOWNWARD
)
9463 offset
= (cfun
->machine
->frame
.args_size
9464 + cfun
->machine
->frame
.cprestore_size
9465 + cfun
->machine
->frame
.var_size
);
9470 case ARG_POINTER_REGNUM
:
9471 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
9478 if (to
== HARD_FRAME_POINTER_REGNUM
)
9479 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9484 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9487 mips_extra_live_on_entry (bitmap regs
)
9491 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9492 the global pointer. */
9493 if (!TARGET_ABSOLUTE_ABICALLS
)
9494 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
9496 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9497 the global pointer. */
9499 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
9501 /* See the comment above load_call<mode> for details. */
9502 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
9506 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9510 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
9515 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
9518 /* Emit code to change the current function's return address to
9519 ADDRESS. SCRATCH is available as a scratch register, if needed.
9520 ADDRESS and SCRATCH are both word-mode GPRs. */
9523 mips_set_return_address (rtx address
, rtx scratch
)
9527 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
9528 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
9529 cfun
->machine
->frame
.gp_sp_offset
);
9530 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
9533 /* Return true if the current function has a cprestore slot. */
9536 mips_cfun_has_cprestore_slot_p (void)
9538 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
9539 && cfun
->machine
->frame
.cprestore_size
> 0);
9542 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9543 cprestore slot. LOAD_P is true if the caller wants to load from
9544 the cprestore slot; it is false if the caller wants to store to
9548 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
9551 const struct mips_frame_info
*frame
;
9553 frame
= &cfun
->machine
->frame
;
9554 /* .cprestore always uses the stack pointer instead of the frame pointer.
9555 We have a free choice for direct stores for non-MIPS16 functions,
9556 and for MIPS16 functions whose cprestore slot is in range of the
9557 stack pointer. Using the stack pointer would sometimes give more
9558 (early) scheduling freedom, but using the frame pointer would
9559 sometimes give more (late) scheduling freedom. It's hard to
9560 predict which applies to a given function, so let's keep things
9563 Loads must always use the frame pointer in functions that call
9564 alloca, and there's little benefit to using the stack pointer
9566 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
9568 *base
= hard_frame_pointer_rtx
;
9569 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
9573 *base
= stack_pointer_rtx
;
9574 *offset
= frame
->args_size
;
9578 /* Return true if X is the load or store address of the cprestore slot;
9579 LOAD_P says which. */
9582 mips_cprestore_address_p (rtx x
, bool load_p
)
9584 rtx given_base
, required_base
;
9585 HOST_WIDE_INT given_offset
, required_offset
;
9587 mips_split_plus (x
, &given_base
, &given_offset
);
9588 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
9589 return given_base
== required_base
&& given_offset
== required_offset
;
9592 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9593 going to load from it, false if we are going to store to it.
9594 Use TEMP as a temporary register if need be. */
9597 mips_cprestore_slot (rtx temp
, bool load_p
)
9600 HOST_WIDE_INT offset
;
9602 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
9603 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
9606 /* Emit instructions to save global pointer value GP into cprestore
9607 slot MEM. OFFSET is the offset that MEM applies to the base register.
9609 MEM may not be a legitimate address. If it isn't, TEMP is a
9610 temporary register that can be used, otherwise it is a SCRATCH. */
9613 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
9615 if (TARGET_CPRESTORE_DIRECTIVE
)
9617 gcc_assert (gp
== pic_offset_table_rtx
);
9618 emit_insn (gen_cprestore (mem
, offset
));
9621 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
9624 /* Restore $gp from its save slot, using TEMP as a temporary base register
9625 if need be. This function is for o32 and o64 abicalls only.
9627 See mips_must_initialize_gp_p for details about how we manage the
9631 mips_restore_gp_from_cprestore_slot (rtx temp
)
9633 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
9635 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
9637 emit_note (NOTE_INSN_DELETED
);
9643 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
9644 mips_emit_move (pic_offset_table_rtx
, temp
);
9647 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
9648 if (!TARGET_EXPLICIT_RELOCS
)
9649 emit_insn (gen_blockage ());
9652 /* A function to save or store a register. The first argument is the
9653 register and the second is the stack slot. */
9654 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
9656 /* Use FN to save or restore register REGNO. MODE is the register's
9657 mode and OFFSET is the offset of its save slot from the current
9661 mips_save_restore_reg (enum machine_mode mode
, int regno
,
9662 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
9666 mem
= gen_frame_mem (mode
, plus_constant (stack_pointer_rtx
, offset
));
9667 fn (gen_rtx_REG (mode
, regno
), mem
);
9670 /* Call FN for each accumlator that is saved by the current function.
9671 SP_OFFSET is the offset of the current stack pointer from the start
9675 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
9677 HOST_WIDE_INT offset
;
9680 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
9681 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
9683 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
9684 offset
-= UNITS_PER_WORD
;
9685 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
9686 offset
-= UNITS_PER_WORD
;
9689 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
9690 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
9691 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
9693 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
9694 offset
-= UNITS_PER_WORD
;
9698 /* Call FN for each register that is saved by the current function.
9699 SP_OFFSET is the offset of the current stack pointer from the start
9703 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
9704 mips_save_restore_fn fn
)
9706 enum machine_mode fpr_mode
;
9707 HOST_WIDE_INT offset
;
9710 /* Save registers starting from high to low. The debuggers prefer at least
9711 the return register be stored at func+4, and also it allows us not to
9712 need a nop in the epilogue if at least one register is reloaded in
9713 addition to return address. */
9714 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
9715 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
9716 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
9718 /* Record the ra offset for use by mips_function_profiler. */
9719 if (regno
== RETURN_ADDR_REGNUM
)
9720 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
9721 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
9722 offset
-= UNITS_PER_WORD
;
9725 /* This loop must iterate over the same space as its companion in
9726 mips_compute_frame_info. */
9727 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
9728 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
9729 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
9730 regno
>= FP_REG_FIRST
;
9731 regno
-= MAX_FPRS_PER_FMT
)
9732 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
9734 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
9735 offset
-= GET_MODE_SIZE (fpr_mode
);
9739 /* Return true if a move between register REGNO and its save slot (MEM)
9740 can be done in a single move. LOAD_P is true if we are loading
9741 from the slot, false if we are storing to it. */
9744 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
9746 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9747 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
9750 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
9751 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
9754 /* Emit a move from SRC to DEST, given that one of them is a register
9755 save slot and that the other is a register. TEMP is a temporary
9756 GPR of the same mode that is available if need be. */
9759 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
9766 regno
= REGNO (src
);
9771 regno
= REGNO (dest
);
9775 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
9777 /* We don't yet know whether we'll need this instruction or not.
9778 Postpone the decision by emitting a ghost move. This move
9779 is specifically not frame-related; only the split version is. */
9781 emit_insn (gen_move_gpdi (dest
, src
));
9783 emit_insn (gen_move_gpsi (dest
, src
));
9787 if (regno
== HI_REGNUM
)
9791 mips_emit_move (temp
, src
);
9793 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
9794 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
9796 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
9797 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
9802 emit_insn (gen_mfhidi_ti (temp
,
9803 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
9805 emit_insn (gen_mfhisi_di (temp
,
9806 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
9807 mips_emit_move (dest
, temp
);
9810 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
9811 mips_emit_move (dest
, src
);
9814 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
9815 mips_emit_move (temp
, src
);
9816 mips_emit_move (dest
, temp
);
9819 mips_set_frame_expr (mips_frame_set (dest
, src
));
9822 /* If we're generating n32 or n64 abicalls, and the current function
9823 does not use $28 as its global pointer, emit a cplocal directive.
9824 Use pic_offset_table_rtx as the argument to the directive. */
9827 mips_output_cplocal (void)
9829 if (!TARGET_EXPLICIT_RELOCS
9830 && mips_must_initialize_gp_p ()
9831 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
9832 output_asm_insn (".cplocal %+", 0);
9835 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9838 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
9842 #ifdef SDB_DEBUGGING_INFO
9843 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
9844 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
9847 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9848 floating-point arguments. */
9850 && TARGET_HARD_FLOAT_ABI
9851 && crtl
->args
.info
.fp_code
!= 0)
9852 mips16_build_function_stub ();
9854 /* Get the function name the same way that toplev.c does before calling
9855 assemble_start_function. This is needed so that the name used here
9856 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9857 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9858 mips_start_function_definition (fnname
, TARGET_MIPS16
);
9860 /* Output MIPS-specific frame information. */
9861 if (!flag_inhibit_size_directive
)
9863 const struct mips_frame_info
*frame
;
9865 frame
= &cfun
->machine
->frame
;
9867 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9869 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
9870 "# vars= " HOST_WIDE_INT_PRINT_DEC
9872 ", args= " HOST_WIDE_INT_PRINT_DEC
9873 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
9874 reg_names
[frame_pointer_needed
9875 ? HARD_FRAME_POINTER_REGNUM
9876 : STACK_POINTER_REGNUM
],
9877 (frame_pointer_needed
9878 ? frame
->total_size
- frame
->hard_frame_pointer_offset
9879 : frame
->total_size
),
9880 reg_names
[RETURN_ADDR_REGNUM
],
9882 frame
->num_gp
, frame
->num_fp
,
9884 frame
->cprestore_size
);
9886 /* .mask MASK, OFFSET. */
9887 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
9888 frame
->mask
, frame
->gp_save_offset
);
9890 /* .fmask MASK, OFFSET. */
9891 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
9892 frame
->fmask
, frame
->fp_save_offset
);
9895 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9896 Also emit the ".set noreorder; .set nomacro" sequence for functions
9898 if (mips_must_initialize_gp_p ()
9899 && mips_current_loadgp_style () == LOADGP_OLDABI
)
9903 /* This is a fixed-form sequence. The position of the
9904 first two instructions is important because of the
9905 way _gp_disp is defined. */
9906 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9907 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9908 output_asm_insn ("sll\t$2,16", 0);
9909 output_asm_insn ("addu\t$2,$3", 0);
9913 /* .cpload must be in a .set noreorder but not a
9914 .set nomacro block. */
9915 mips_push_asm_switch (&mips_noreorder
);
9916 output_asm_insn (".cpload\t%^", 0);
9917 if (!cfun
->machine
->all_noreorder_p
)
9918 mips_pop_asm_switch (&mips_noreorder
);
9920 mips_push_asm_switch (&mips_nomacro
);
9923 else if (cfun
->machine
->all_noreorder_p
)
9925 mips_push_asm_switch (&mips_noreorder
);
9926 mips_push_asm_switch (&mips_nomacro
);
9929 /* Tell the assembler which register we're using as the global
9930 pointer. This is needed for thunks, since they can use either
9931 explicit relocs or assembler macros. */
9932 mips_output_cplocal ();
9935 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9938 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9939 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
9943 /* Reinstate the normal $gp. */
9944 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
9945 mips_output_cplocal ();
9947 if (cfun
->machine
->all_noreorder_p
)
9949 mips_pop_asm_switch (&mips_nomacro
);
9950 mips_pop_asm_switch (&mips_noreorder
);
9953 /* Get the function name the same way that toplev.c does before calling
9954 assemble_start_function. This is needed so that the name used here
9955 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9956 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9957 mips_end_function_definition (fnname
);
9960 /* Save register REG to MEM. Make the instruction frame-related. */
9963 mips_save_reg (rtx reg
, rtx mem
)
9965 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
9969 if (mips_split_64bit_move_p (mem
, reg
))
9970 mips_split_doubleword_move (mem
, reg
);
9972 mips_emit_move (mem
, reg
);
9974 x1
= mips_frame_set (mips_subword (mem
, false),
9975 mips_subword (reg
, false));
9976 x2
= mips_frame_set (mips_subword (mem
, true),
9977 mips_subword (reg
, true));
9978 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
9981 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
9984 /* The __gnu_local_gp symbol. */
9986 static GTY(()) rtx mips_gnu_local_gp
;
9988 /* If we're generating n32 or n64 abicalls, emit instructions
9989 to set up the global pointer. */
9992 mips_emit_loadgp (void)
9994 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
9996 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
9997 switch (mips_current_loadgp_style ())
9999 case LOADGP_ABSOLUTE
:
10000 if (mips_gnu_local_gp
== NULL
)
10002 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10003 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10005 emit_insn (Pmode
== SImode
10006 ? gen_loadgp_absolute_si (pic_reg
, mips_gnu_local_gp
)
10007 : gen_loadgp_absolute_di (pic_reg
, mips_gnu_local_gp
));
10010 case LOADGP_OLDABI
:
10011 /* Added by mips_output_function_prologue. */
10014 case LOADGP_NEWABI
:
10015 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10016 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10017 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10018 emit_insn (Pmode
== SImode
10019 ? gen_loadgp_newabi_si (pic_reg
, offset
, incoming_address
)
10020 : gen_loadgp_newabi_di (pic_reg
, offset
, incoming_address
));
10024 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10025 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10026 emit_insn (Pmode
== SImode
10027 ? gen_loadgp_rtp_si (pic_reg
, base
, index
)
10028 : gen_loadgp_rtp_di (pic_reg
, base
, index
));
10036 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx
, pic_reg
));
10038 /* Emit a blockage if there are implicit uses of the GP register.
10039 This includes profiled functions, because FUNCTION_PROFILE uses
10041 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10042 emit_insn (gen_loadgp_blockage ());
10045 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10048 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10050 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10053 /* Expand the "prologue" pattern. */
10056 mips_expand_prologue (void)
10058 const struct mips_frame_info
*frame
;
10059 HOST_WIDE_INT size
;
10060 unsigned int nargs
;
10063 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10065 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10066 or implicitly. If so, we can commit to using a global pointer
10067 straight away, otherwise we need to defer the decision. */
10068 if (mips_cfun_has_inflexible_gp_ref_p ()
10069 || mips_cfun_has_flexible_gp_ref_p ())
10071 cfun
->machine
->must_initialize_gp_p
= true;
10072 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10075 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10078 frame
= &cfun
->machine
->frame
;
10079 size
= frame
->total_size
;
10081 if (flag_stack_usage
)
10082 current_function_static_stack_size
= size
;
10084 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10085 bytes beforehand; this is enough to cover the register save area
10086 without going out of range. */
10087 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
10088 || frame
->num_cop0_regs
> 0)
10090 HOST_WIDE_INT step1
;
10092 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10093 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10095 HOST_WIDE_INT offset
;
10096 unsigned int mask
, regno
;
10098 /* Try to merge argument stores into the save instruction. */
10099 nargs
= mips16e_collect_argument_saves ();
10101 /* Build the save instruction. */
10102 mask
= frame
->mask
;
10103 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
10105 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10108 /* Check if we need to save other registers. */
10109 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10110 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10112 offset
-= UNITS_PER_WORD
;
10113 mips_save_restore_reg (word_mode
, regno
,
10114 offset
, mips_save_reg
);
10119 if (cfun
->machine
->interrupt_handler_p
)
10121 HOST_WIDE_INT offset
;
10124 /* If this interrupt is using a shadow register set, we need to
10125 get the stack pointer from the previous register set. */
10126 if (cfun
->machine
->use_shadow_register_set_p
)
10127 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
10128 stack_pointer_rtx
));
10130 if (!cfun
->machine
->keep_interrupts_masked_p
)
10132 /* Move from COP0 Cause to K0. */
10133 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
10134 gen_rtx_REG (SImode
,
10135 COP0_CAUSE_REG_NUM
)));
10136 /* Move from COP0 EPC to K1. */
10137 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10138 gen_rtx_REG (SImode
,
10139 COP0_EPC_REG_NUM
)));
10142 /* Allocate the first part of the frame. */
10143 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
10145 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10148 /* Start at the uppermost location for saving. */
10149 offset
= frame
->cop0_sp_offset
- size
;
10150 if (!cfun
->machine
->keep_interrupts_masked_p
)
10152 /* Push EPC into its stack slot. */
10153 mem
= gen_frame_mem (word_mode
,
10154 plus_constant (stack_pointer_rtx
,
10156 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10157 offset
-= UNITS_PER_WORD
;
10160 /* Move from COP0 Status to K1. */
10161 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10162 gen_rtx_REG (SImode
,
10163 COP0_STATUS_REG_NUM
)));
10165 /* Right justify the RIPL in k0. */
10166 if (!cfun
->machine
->keep_interrupts_masked_p
)
10167 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
10168 gen_rtx_REG (SImode
, K0_REG_NUM
),
10169 GEN_INT (CAUSE_IPL
)));
10171 /* Push Status into its stack slot. */
10172 mem
= gen_frame_mem (word_mode
,
10173 plus_constant (stack_pointer_rtx
, offset
));
10174 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10175 offset
-= UNITS_PER_WORD
;
10177 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10178 if (!cfun
->machine
->keep_interrupts_masked_p
)
10179 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10182 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10184 if (!cfun
->machine
->keep_interrupts_masked_p
)
10185 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10186 IE is already the correct value, so we don't have to do
10187 anything explicit. */
10188 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10191 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10193 /* Disable interrupts by clearing the KSU, ERL, EXL,
10195 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10198 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10202 insn
= gen_add3_insn (stack_pointer_rtx
,
10205 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10208 mips_for_each_saved_acc (size
, mips_save_reg
);
10209 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
10213 /* Allocate the rest of the frame. */
10216 if (SMALL_OPERAND (-size
))
10217 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
10219 GEN_INT (-size
)))) = 1;
10222 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
10225 /* There are no instructions to add or subtract registers
10226 from the stack pointer, so use the frame pointer as a
10227 temporary. We should always be using a frame pointer
10228 in this case anyway. */
10229 gcc_assert (frame_pointer_needed
);
10230 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10231 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
10232 hard_frame_pointer_rtx
,
10233 MIPS_PROLOGUE_TEMP (Pmode
)));
10234 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
10237 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
10239 MIPS_PROLOGUE_TEMP (Pmode
)));
10241 /* Describe the combined effect of the previous instructions. */
10242 mips_set_frame_expr
10243 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10244 plus_constant (stack_pointer_rtx
, -size
)));
10248 /* Set up the frame pointer, if we're using one. */
10249 if (frame_pointer_needed
)
10251 HOST_WIDE_INT offset
;
10253 offset
= frame
->hard_frame_pointer_offset
;
10256 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10257 RTX_FRAME_RELATED_P (insn
) = 1;
10259 else if (SMALL_OPERAND (offset
))
10261 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
10262 stack_pointer_rtx
, GEN_INT (offset
));
10263 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10267 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
10268 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10269 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
10270 hard_frame_pointer_rtx
,
10271 MIPS_PROLOGUE_TEMP (Pmode
)));
10272 mips_set_frame_expr
10273 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
10274 plus_constant (stack_pointer_rtx
, offset
)));
10278 mips_emit_loadgp ();
10280 /* Initialize the $gp save slot. */
10281 if (mips_cfun_has_cprestore_slot_p ())
10283 rtx base
, mem
, gp
, temp
;
10284 HOST_WIDE_INT offset
;
10286 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
10287 mem
= gen_frame_mem (Pmode
, plus_constant (base
, offset
));
10288 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10289 temp
= (SMALL_OPERAND (offset
)
10290 ? gen_rtx_SCRATCH (Pmode
)
10291 : MIPS_PROLOGUE_TEMP (Pmode
));
10292 emit_insn (gen_potential_cprestore (mem
, GEN_INT (offset
), gp
, temp
));
10294 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
10295 mem
= gen_frame_mem (Pmode
, plus_constant (base
, offset
));
10296 emit_insn (gen_use_cprestore (mem
));
10299 /* We need to search back to the last use of K0 or K1. */
10300 if (cfun
->machine
->interrupt_handler_p
)
10302 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
10304 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
10306 /* Emit a move from K1 to COP0 Status after insn. */
10307 gcc_assert (insn
!= NULL_RTX
);
10308 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10309 gen_rtx_REG (SImode
, K1_REG_NUM
)),
10313 /* If we are profiling, make sure no instructions are scheduled before
10314 the call to mcount. */
10316 emit_insn (gen_blockage ());
10319 /* Emit instructions to restore register REG from slot MEM. */
10322 mips_restore_reg (rtx reg
, rtx mem
)
10324 /* There's no MIPS16 instruction to load $31 directly. Load into
10325 $7 instead and adjust the return insn appropriately. */
10326 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
10327 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
10329 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
10332 /* Emit any instructions needed before a return. */
10335 mips_expand_before_return (void)
10337 /* When using a call-clobbered gp, we start out with unified call
10338 insns that include instructions to restore the gp. We then split
10339 these unified calls after reload. These split calls explicitly
10340 clobber gp, so there is no need to define
10341 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10343 For consistency, we should also insert an explicit clobber of $28
10344 before return insns, so that the post-reload optimizers know that
10345 the register is not live on exit. */
10346 if (TARGET_CALL_CLOBBERED_GP
)
10347 emit_clobber (pic_offset_table_rtx
);
10350 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10354 mips_expand_epilogue (bool sibcall_p
)
10356 const struct mips_frame_info
*frame
;
10357 HOST_WIDE_INT step1
, step2
;
10358 rtx base
, target
, insn
;
10360 if (!sibcall_p
&& mips_can_use_return_insn ())
10362 emit_jump_insn (gen_return ());
10366 /* In MIPS16 mode, if the return value should go into a floating-point
10367 register, we need to call a helper routine to copy it over. */
10368 if (mips16_cfun_returns_in_fpr_p ())
10369 mips16_copy_fpr_return_value ();
10371 /* Split the frame into two. STEP1 is the amount of stack we should
10372 deallocate before restoring the registers. STEP2 is the amount we
10373 should deallocate afterwards.
10375 Start off by assuming that no registers need to be restored. */
10376 frame
= &cfun
->machine
->frame
;
10377 step1
= frame
->total_size
;
10380 /* Work out which register holds the frame address. */
10381 if (!frame_pointer_needed
)
10382 base
= stack_pointer_rtx
;
10385 base
= hard_frame_pointer_rtx
;
10386 step1
-= frame
->hard_frame_pointer_offset
;
10389 /* If we need to restore registers, deallocate as much stack as
10390 possible in the second step without going out of range. */
10391 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
10392 || frame
->num_cop0_regs
> 0)
10394 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
10398 /* Set TARGET to BASE + STEP1. */
10404 /* Get an rtx for STEP1 that we can add to BASE. */
10405 adjust
= GEN_INT (step1
);
10406 if (!SMALL_OPERAND (step1
))
10408 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
10409 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
10412 /* Normal mode code can copy the result straight into $sp. */
10413 if (!TARGET_MIPS16
)
10414 target
= stack_pointer_rtx
;
10416 emit_insn (gen_add3_insn (target
, base
, adjust
));
10419 /* Copy TARGET into the stack pointer. */
10420 if (target
!= stack_pointer_rtx
)
10421 mips_emit_move (stack_pointer_rtx
, target
);
10423 /* If we're using addressing macros, $gp is implicitly used by all
10424 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10426 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
10427 emit_insn (gen_blockage ());
10429 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
10431 unsigned int regno
, mask
;
10432 HOST_WIDE_INT offset
;
10435 /* Generate the restore instruction. */
10436 mask
= frame
->mask
;
10437 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
10439 /* Restore any other registers manually. */
10440 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10441 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10443 offset
-= UNITS_PER_WORD
;
10444 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
10447 /* Restore the remaining registers and deallocate the final bit
10449 emit_insn (restore
);
10453 /* Restore the registers. */
10454 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
10455 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
10458 if (cfun
->machine
->interrupt_handler_p
)
10460 HOST_WIDE_INT offset
;
10463 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
10464 if (!cfun
->machine
->keep_interrupts_masked_p
)
10466 /* Restore the original EPC. */
10467 mem
= gen_frame_mem (word_mode
,
10468 plus_constant (stack_pointer_rtx
, offset
));
10469 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10470 offset
-= UNITS_PER_WORD
;
10472 /* Move to COP0 EPC. */
10473 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
10474 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10477 /* Restore the original Status. */
10478 mem
= gen_frame_mem (word_mode
,
10479 plus_constant (stack_pointer_rtx
, offset
));
10480 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10481 offset
-= UNITS_PER_WORD
;
10483 /* If we don't use shoadow register set, we need to update SP. */
10484 if (!cfun
->machine
->use_shadow_register_set_p
&& step2
> 0)
10485 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10489 /* Move to COP0 Status. */
10490 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10491 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10495 /* Deallocate the final bit of the frame. */
10497 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10503 /* Add in the __builtin_eh_return stack adjustment. We need to
10504 use a temporary in MIPS16 code. */
10505 if (crtl
->calls_eh_return
)
10509 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
10510 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
10511 MIPS_EPILOGUE_TEMP (Pmode
),
10512 EH_RETURN_STACKADJ_RTX
));
10513 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
10516 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10518 EH_RETURN_STACKADJ_RTX
));
10523 mips_expand_before_return ();
10524 if (cfun
->machine
->interrupt_handler_p
)
10526 /* Interrupt handlers generate eret or deret. */
10527 if (cfun
->machine
->use_debug_exception_return_p
)
10528 emit_jump_insn (gen_mips_deret ());
10530 emit_jump_insn (gen_mips_eret ());
10534 unsigned int regno
;
10536 /* When generating MIPS16 code, the normal
10537 mips_for_each_saved_gpr_and_fpr path will restore the return
10538 address into $7 rather than $31. */
10540 && !GENERATE_MIPS16E_SAVE_RESTORE
10541 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
10542 regno
= GP_REG_FIRST
+ 7;
10544 regno
= RETURN_ADDR_REGNUM
;
10545 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, regno
)));
10549 /* Search from the beginning to the first use of K0 or K1. */
10550 if (cfun
->machine
->interrupt_handler_p
10551 && !cfun
->machine
->keep_interrupts_masked_p
)
10553 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
10555 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
10557 gcc_assert (insn
!= NULL_RTX
);
10558 /* Insert disable interrupts before the first use of K0 or K1. */
10559 emit_insn_before (gen_mips_di (), insn
);
10560 emit_insn_before (gen_mips_ehb (), insn
);
10564 /* Return nonzero if this function is known to have a null epilogue.
10565 This allows the optimizer to omit jumps to jumps if no stack
10569 mips_can_use_return_insn (void)
10571 /* Interrupt handlers need to go through the epilogue. */
10572 if (cfun
->machine
->interrupt_handler_p
)
10575 if (!reload_completed
)
10581 /* In MIPS16 mode, a function that returns a floating-point value
10582 needs to arrange to copy the return value into the floating-point
10584 if (mips16_cfun_returns_in_fpr_p ())
10587 return cfun
->machine
->frame
.total_size
== 0;
10590 /* Return true if register REGNO can store a value of mode MODE.
10591 The result of this function is cached in mips_hard_regno_mode_ok. */
10594 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
10597 enum mode_class mclass
;
10599 if (mode
== CCV2mode
)
10600 return (ISA_HAS_8CC
10601 && ST_REG_P (regno
)
10602 && (regno
- ST_REG_FIRST
) % 2 == 0);
10604 if (mode
== CCV4mode
)
10605 return (ISA_HAS_8CC
10606 && ST_REG_P (regno
)
10607 && (regno
- ST_REG_FIRST
) % 4 == 0);
10609 if (mode
== CCmode
)
10612 return regno
== FPSW_REGNUM
;
10614 return (ST_REG_P (regno
)
10615 || GP_REG_P (regno
)
10616 || FP_REG_P (regno
));
10619 size
= GET_MODE_SIZE (mode
);
10620 mclass
= GET_MODE_CLASS (mode
);
10622 if (GP_REG_P (regno
))
10623 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
10625 if (FP_REG_P (regno
)
10626 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
10627 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
10629 /* Allow TFmode for CCmode reloads. */
10630 if (mode
== TFmode
&& ISA_HAS_8CC
)
10633 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10634 if (TARGET_LOONGSON_VECTORS
10635 && (mode
== V2SImode
10636 || mode
== V4HImode
10637 || mode
== V8QImode
10638 || mode
== DImode
))
10641 if (mclass
== MODE_FLOAT
10642 || mclass
== MODE_COMPLEX_FLOAT
10643 || mclass
== MODE_VECTOR_FLOAT
)
10644 return size
<= UNITS_PER_FPVALUE
;
10646 /* Allow integer modes that fit into a single register. We need
10647 to put integers into FPRs when using instructions like CVT
10648 and TRUNC. There's no point allowing sizes smaller than a word,
10649 because the FPU has no appropriate load/store instructions. */
10650 if (mclass
== MODE_INT
)
10651 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
10654 if (ACC_REG_P (regno
)
10655 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
10657 if (MD_REG_P (regno
))
10659 /* After a multiplication or division, clobbering HI makes
10660 the value of LO unpredictable, and vice versa. This means
10661 that, for all interesting cases, HI and LO are effectively
10664 We model this by requiring that any value that uses HI
10666 if (size
<= UNITS_PER_WORD
* 2)
10667 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
10671 /* DSP accumulators do not have the same restrictions as
10672 HI and LO, so we can treat them as normal doubleword
10674 if (size
<= UNITS_PER_WORD
)
10677 if (size
<= UNITS_PER_WORD
* 2
10678 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
10683 if (ALL_COP_REG_P (regno
))
10684 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
10686 if (regno
== GOT_VERSION_REGNUM
)
10687 return mode
== SImode
;
10692 /* Implement HARD_REGNO_NREGS. */
10695 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
10697 if (ST_REG_P (regno
))
10698 /* The size of FP status registers is always 4, because they only hold
10699 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10700 return (GET_MODE_SIZE (mode
) + 3) / 4;
10702 if (FP_REG_P (regno
))
10703 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
10705 /* All other registers are word-sized. */
10706 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
10709 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10710 in mips_hard_regno_nregs. */
10713 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
10719 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
10720 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
10722 size
= MIN (size
, 4);
10723 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
10725 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
10727 size
= MIN (size
, UNITS_PER_FPREG
);
10728 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
10730 if (!hard_reg_set_empty_p (left
))
10731 size
= MIN (size
, UNITS_PER_WORD
);
10732 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
10735 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10738 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED
,
10739 enum machine_mode to ATTRIBUTE_UNUSED
,
10740 enum reg_class rclass
)
10742 /* There are several problems with changing the modes of values
10743 in floating-point registers:
10745 - When a multi-word value is stored in paired floating-point
10746 registers, the first register always holds the low word.
10747 We therefore can't allow FPRs to change between single-word
10748 and multi-word modes on big-endian targets.
10750 - GCC assumes that each word of a multiword register can be accessed
10751 individually using SUBREGs. This is not true for floating-point
10752 registers if they are bigger than a word.
10754 - Loading a 32-bit value into a 64-bit floating-point register
10755 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10756 We can't allow FPRs to change from SImode to to a wider mode on
10759 - If the FPU has already interpreted a value in one format, we must
10760 not ask it to treat the value as having a different format.
10762 We therefore disallow all mode changes involving FPRs. */
10763 return reg_classes_intersect_p (FP_REGS
, rclass
);
10766 /* Implement target hook small_register_classes_for_mode_p. */
10769 mips_small_register_classes_for_mode_p (enum machine_mode mode
10772 return TARGET_MIPS16
;
10775 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10778 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
10783 return TARGET_HARD_FLOAT
;
10786 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
10789 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
10796 /* Implement MODES_TIEABLE_P. */
10799 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
10801 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10802 prefer to put one of them in FPRs. */
10803 return (mode1
== mode2
10804 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
10805 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
10808 /* Implement PREFERRED_RELOAD_CLASS. */
10811 mips_preferred_reload_class (rtx x
, enum reg_class rclass
)
10813 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
10816 if (reg_class_subset_p (FP_REGS
, rclass
)
10817 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
10820 if (reg_class_subset_p (GR_REGS
, rclass
))
10823 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
10829 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10830 Return a "canonical" class to represent it in later calculations. */
10833 mips_canonicalize_move_class (reg_class_t rclass
)
10835 /* All moves involving accumulator registers have the same cost. */
10836 if (reg_class_subset_p (rclass
, ACC_REGS
))
10839 /* Likewise promote subclasses of general registers to the most
10840 interesting containing class. */
10841 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
10843 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
10844 rclass
= GENERAL_REGS
;
10849 /* Return the cost of moving a value of mode MODE from a register of
10850 class FROM to a GPR. Return 0 for classes that are unions of other
10851 classes handled by this function. */
10854 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
10860 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10864 /* MFLO and MFHI. */
10872 /* LUI followed by MOVF. */
10878 /* This choice of value is historical. */
10886 /* Return the cost of moving a value of mode MODE from a GPR to a
10887 register of class TO. Return 0 for classes that are unions of
10888 other classes handled by this function. */
10891 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
10896 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10900 /* MTLO and MTHI. */
10908 /* A secondary reload through an FPR scratch. */
10909 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
10910 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
10915 /* This choice of value is historical. */
10923 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10924 maximum of the move costs for subclasses; regclass will work out
10925 the maximum for us. */
10928 mips_register_move_cost (enum machine_mode mode
,
10929 reg_class_t from
, reg_class_t to
)
10934 from
= mips_canonicalize_move_class (from
);
10935 to
= mips_canonicalize_move_class (to
);
10937 /* Handle moves that can be done without using general-purpose registers. */
10938 if (from
== FP_REGS
)
10940 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
10944 /* The sequence generated by mips_expand_fcc_reload. */
10948 /* Handle cases in which only one class deviates from the ideal. */
10949 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
10951 return mips_move_from_gpr_cost (mode
, to
);
10953 return mips_move_to_gpr_cost (mode
, from
);
10955 /* Handles cases that require a GPR temporary. */
10956 cost1
= mips_move_to_gpr_cost (mode
, from
);
10959 cost2
= mips_move_from_gpr_cost (mode
, to
);
10961 return cost1
+ cost2
;
10967 /* Implement TARGET_MEMORY_MOVE_COST. */
10970 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
10972 return (mips_cost
->memory_latency
10973 + memory_move_secondary_cost (mode
, rclass
, in
));
10976 /* Implement TARGET_IRA_COVER_CLASSES. */
10978 static const reg_class_t
*
10979 mips_ira_cover_classes (void)
10981 static const reg_class_t acc_classes
[] = {
10982 GR_AND_ACC_REGS
, FP_REGS
, COP0_REGS
, COP2_REGS
, COP3_REGS
,
10983 ST_REGS
, LIM_REG_CLASSES
10985 static const reg_class_t no_acc_classes
[] = {
10986 GR_REGS
, FP_REGS
, COP0_REGS
, COP2_REGS
, COP3_REGS
,
10987 ST_REGS
, LIM_REG_CLASSES
10990 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10991 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10992 as a cover class only works well when we keep per-register costs.
10993 Using it when not optimizing can cause us to think accumulators
10994 have the same cost as GPRs in cases where GPRs are actually much
10996 return TARGET_MIPS16
|| !optimize
? no_acc_classes
: acc_classes
;
10999 /* Return the register class required for a secondary register when
11000 copying between one of the registers in RCLASS and value X, which
11001 has mode MODE. X is the source of the move if IN_P, otherwise it
11002 is the destination. Return NO_REGS if no secondary register is
11006 mips_secondary_reload_class (enum reg_class rclass
,
11007 enum machine_mode mode
, rtx x
, bool in_p
)
11011 /* If X is a constant that cannot be loaded into $25, it must be loaded
11012 into some other GPR. No other register class allows a direct move. */
11013 if (mips_dangerous_for_la25_p (x
))
11014 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
11016 regno
= true_regnum (x
);
11019 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11020 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
11026 /* Copying from accumulator registers to anywhere other than a general
11027 register requires a temporary general register. */
11028 if (reg_class_subset_p (rclass
, ACC_REGS
))
11029 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11030 if (ACC_REG_P (regno
))
11031 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11033 /* We can only copy a value to a condition code register from a
11034 floating-point register, and even then we require a scratch
11035 floating-point register. We can only copy a value out of a
11036 condition-code register into a general register. */
11037 if (reg_class_subset_p (rclass
, ST_REGS
))
11041 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11043 if (ST_REG_P (regno
))
11047 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11050 if (reg_class_subset_p (rclass
, FP_REGS
))
11053 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
11054 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11055 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11058 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
11059 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11062 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (x
))
11063 /* We can force the constant to memory and use lwc1
11064 and ldc1. As above, we will use pairs of lwc1s if
11065 ldc1 is not supported. */
11068 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
11069 /* In this case we can use mov.fmt. */
11072 /* Otherwise, we need to reload through an integer register. */
11075 if (FP_REG_P (regno
))
11076 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11081 /* Implement TARGET_MODE_REP_EXTENDED. */
11084 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
11086 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11087 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
11088 return SIGN_EXTEND
;
11093 /* Implement TARGET_VALID_POINTER_MODE. */
11096 mips_valid_pointer_mode (enum machine_mode mode
)
11098 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
11101 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11104 mips_vector_mode_supported_p (enum machine_mode mode
)
11109 return TARGET_PAIRED_SINGLE_FLOAT
;
11124 return TARGET_LOONGSON_VECTORS
;
11131 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11134 mips_scalar_mode_supported_p (enum machine_mode mode
)
11136 if (ALL_FIXED_POINT_MODE_P (mode
)
11137 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
11140 return default_scalar_mode_supported_p (mode
);
11143 /* Implement TARGET_INIT_LIBFUNCS. */
11145 #include "config/gofast.h"
11148 mips_init_libfuncs (void)
11150 if (TARGET_FIX_VR4120
)
11152 /* Register the special divsi3 and modsi3 functions needed to work
11153 around VR4120 division errata. */
11154 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
11155 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
11158 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
11160 /* Register the MIPS16 -mhard-float stubs. */
11161 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
11162 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
11163 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
11164 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
11166 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
11167 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
11168 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
11169 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
11170 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
11171 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
11172 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
11174 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
11175 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
11176 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
11178 if (TARGET_DOUBLE_FLOAT
)
11180 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
11181 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
11182 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
11183 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
11185 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
11186 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
11187 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
11188 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
11189 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
11190 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
11191 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
11193 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
11194 "__mips16_extendsfdf2");
11195 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
11196 "__mips16_truncdfsf2");
11197 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
11198 "__mips16_fix_truncdfsi");
11199 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
11200 "__mips16_floatsidf");
11201 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
11202 "__mips16_floatunsidf");
11206 /* Register the gofast functions if selected using --enable-gofast. */
11207 gofast_maybe_init_libfuncs ();
11209 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11210 on an external non-MIPS16 routine to implement __sync_synchronize. */
11212 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
11215 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11218 mips_process_load_label (rtx target
)
11220 rtx base
, gp
, intop
;
11221 HOST_WIDE_INT offset
;
11223 mips_multi_start ();
11227 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
11228 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11232 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
11233 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11237 gp
= pic_offset_table_rtx
;
11238 if (mips_cfun_has_cprestore_slot_p ())
11240 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
11241 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11242 if (!SMALL_OPERAND (offset
))
11244 intop
= GEN_INT (CONST_HIGH_PART (offset
));
11245 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
11246 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
11249 offset
= CONST_LOW_PART (offset
);
11251 intop
= GEN_INT (offset
);
11252 if (ISA_HAS_LOAD_DELAY
)
11253 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
11255 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
11257 if (ISA_HAS_LOAD_DELAY
)
11258 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
11260 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
11261 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
11266 /* Return the number of instructions needed to load a label into $AT. */
11268 static unsigned int
11269 mips_load_label_length (void)
11271 if (cfun
->machine
->load_label_length
== 0)
11273 mips_process_load_label (pc_rtx
);
11274 cfun
->machine
->load_label_length
= mips_multi_num_insns
;
11276 return cfun
->machine
->load_label_length
;
11279 /* Emit an asm sequence to start a noat block and load the address
11280 of a label into $1. */
11283 mips_output_load_label (rtx target
)
11285 mips_push_asm_switch (&mips_noat
);
11286 if (TARGET_EXPLICIT_RELOCS
)
11288 mips_process_load_label (target
);
11289 mips_multi_write ();
11293 if (Pmode
== DImode
)
11294 output_asm_insn ("dla\t%@,%0", &target
);
11296 output_asm_insn ("la\t%@,%0", &target
);
11300 /* Return the length of INSN. LENGTH is the initial length computed by
11301 attributes in the machine-description file. */
11304 mips_adjust_insn_length (rtx insn
, int length
)
11306 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11307 of a PIC long-branch sequence. Substitute the correct value. */
11308 if (length
== MAX_PIC_BRANCH_LENGTH
11309 && INSN_CODE (insn
) >= 0
11310 && get_attr_type (insn
) == TYPE_BRANCH
)
11312 /* Add the branch-over instruction and its delay slot, if this
11313 is a conditional branch. */
11314 length
= simplejump_p (insn
) ? 0 : 8;
11316 /* Load the label into $AT and jump to it. Ignore the delay
11317 slot of the jump. */
11318 length
+= mips_load_label_length () + 4;
11321 /* A unconditional jump has an unfilled delay slot if it is not part
11322 of a sequence. A conditional jump normally has a delay slot, but
11323 does not on MIPS16. */
11324 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
11327 /* See how many nops might be needed to avoid hardware hazards. */
11328 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
11329 switch (get_attr_hazard (insn
))
11343 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11344 the .md file length attributes are 4-based for both modes.
11345 Adjust the MIPS16 ones here. */
11352 /* Return the assembly code for INSN, which has the operands given by
11353 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11354 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11355 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11356 version of BRANCH_IF_TRUE. */
11359 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
11360 const char *branch_if_true
,
11361 const char *branch_if_false
)
11363 unsigned int length
;
11364 rtx taken
, not_taken
;
11366 gcc_assert (LABEL_P (operands
[0]));
11368 length
= get_attr_length (insn
);
11371 /* Just a simple conditional branch. */
11372 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
11373 return branch_if_true
;
11376 /* Generate a reversed branch around a direct jump. This fallback does
11377 not use branch-likely instructions. */
11378 mips_branch_likely
= false;
11379 not_taken
= gen_label_rtx ();
11380 taken
= operands
[0];
11382 /* Generate the reversed branch to NOT_TAKEN. */
11383 operands
[0] = not_taken
;
11384 output_asm_insn (branch_if_false
, operands
);
11386 /* If INSN has a delay slot, we must provide delay slots for both the
11387 branch to NOT_TAKEN and the conditional jump. We must also ensure
11388 that INSN's delay slot is executed in the appropriate cases. */
11389 if (final_sequence
)
11391 /* This first delay slot will always be executed, so use INSN's
11392 delay slot if is not annulled. */
11393 if (!INSN_ANNULLED_BRANCH_P (insn
))
11395 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11396 asm_out_file
, optimize
, 1, NULL
);
11397 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11400 output_asm_insn ("nop", 0);
11401 fprintf (asm_out_file
, "\n");
11404 /* Output the unconditional branch to TAKEN. */
11405 if (TARGET_ABSOLUTE_JUMPS
)
11406 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
11409 mips_output_load_label (taken
);
11410 output_asm_insn ("jr\t%@%]%/", 0);
11413 /* Now deal with its delay slot; see above. */
11414 if (final_sequence
)
11416 /* This delay slot will only be executed if the branch is taken.
11417 Use INSN's delay slot if is annulled. */
11418 if (INSN_ANNULLED_BRANCH_P (insn
))
11420 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11421 asm_out_file
, optimize
, 1, NULL
);
11422 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11425 output_asm_insn ("nop", 0);
11426 fprintf (asm_out_file
, "\n");
11429 /* Output NOT_TAKEN. */
11430 targetm
.asm_out
.internal_label (asm_out_file
, "L",
11431 CODE_LABEL_NUMBER (not_taken
));
11435 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11436 if some ordering condition is true. The condition is given by
11437 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11438 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11439 its second is always zero. */
11442 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
11444 const char *branch
[2];
11446 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11447 Make BRANCH[0] branch on the inverse condition. */
11448 switch (GET_CODE (operands
[1]))
11450 /* These cases are equivalent to comparisons against zero. */
11452 inverted_p
= !inverted_p
;
11453 /* Fall through. */
11455 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
11456 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
11459 /* These cases are always true or always false. */
11461 inverted_p
= !inverted_p
;
11462 /* Fall through. */
11464 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
11465 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
11469 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
11470 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
11473 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
11476 /* Start a block of code that needs access to the LL, SC and SYNC
11480 mips_start_ll_sc_sync_block (void)
11482 if (!ISA_HAS_LL_SC
)
11484 output_asm_insn (".set\tpush", 0);
11485 output_asm_insn (".set\tmips2", 0);
11489 /* End a block started by mips_start_ll_sc_sync_block. */
11492 mips_end_ll_sc_sync_block (void)
11494 if (!ISA_HAS_LL_SC
)
11495 output_asm_insn (".set\tpop", 0);
11498 /* Output and/or return the asm template for a sync instruction. */
11501 mips_output_sync (void)
11503 mips_start_ll_sc_sync_block ();
11504 output_asm_insn ("sync", 0);
11505 mips_end_ll_sc_sync_block ();
11509 /* Return the asm template associated with sync_insn1 value TYPE.
11510 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11512 static const char *
11513 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
11517 case SYNC_INSN1_MOVE
:
11518 return "move\t%0,%z2";
11519 case SYNC_INSN1_LI
:
11520 return "li\t%0,%2";
11521 case SYNC_INSN1_ADDU
:
11522 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11523 case SYNC_INSN1_ADDIU
:
11524 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11525 case SYNC_INSN1_SUBU
:
11526 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11527 case SYNC_INSN1_AND
:
11528 return "and\t%0,%1,%z2";
11529 case SYNC_INSN1_ANDI
:
11530 return "andi\t%0,%1,%2";
11531 case SYNC_INSN1_OR
:
11532 return "or\t%0,%1,%z2";
11533 case SYNC_INSN1_ORI
:
11534 return "ori\t%0,%1,%2";
11535 case SYNC_INSN1_XOR
:
11536 return "xor\t%0,%1,%z2";
11537 case SYNC_INSN1_XORI
:
11538 return "xori\t%0,%1,%2";
11540 gcc_unreachable ();
11543 /* Return the asm template associated with sync_insn2 value TYPE. */
11545 static const char *
11546 mips_sync_insn2_template (enum attr_sync_insn2 type
)
11550 case SYNC_INSN2_NOP
:
11551 gcc_unreachable ();
11552 case SYNC_INSN2_AND
:
11553 return "and\t%0,%1,%z2";
11554 case SYNC_INSN2_XOR
:
11555 return "xor\t%0,%1,%z2";
11556 case SYNC_INSN2_NOT
:
11557 return "nor\t%0,%1,%.";
11559 gcc_unreachable ();
11562 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11563 the value of the one of the sync_* attributes. Return the operand
11564 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11565 have the associated attribute. */
11568 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
11571 default_value
= operands
[index
- 1];
11572 return default_value
;
11575 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11576 sequence for it. */
11579 mips_process_sync_loop (rtx insn
, rtx
*operands
)
11581 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
11582 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
;
11583 unsigned int tmp3_insn
;
11584 enum attr_sync_insn1 insn1
;
11585 enum attr_sync_insn2 insn2
;
11588 /* Read an operand from the sync_WHAT attribute and store it in
11589 variable WHAT. DEFAULT is the default value if no attribute
11591 #define READ_OPERAND(WHAT, DEFAULT) \
11592 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11595 /* Read the memory. */
11596 READ_OPERAND (mem
, 0);
11598 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
11600 /* Read the other attributes. */
11601 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
11602 READ_OPERAND (oldval
, at
);
11603 READ_OPERAND (newval
, at
);
11604 READ_OPERAND (inclusive_mask
, 0);
11605 READ_OPERAND (exclusive_mask
, 0);
11606 READ_OPERAND (required_oldval
, 0);
11607 READ_OPERAND (insn1_op2
, 0);
11608 insn1
= get_attr_sync_insn1 (insn
);
11609 insn2
= get_attr_sync_insn2 (insn
);
11611 mips_multi_start ();
11613 /* Output the release side of the memory barrier. */
11614 if (get_attr_sync_release_barrier (insn
) == SYNC_RELEASE_BARRIER_YES
)
11616 if (required_oldval
== 0 && TARGET_OCTEON
)
11618 /* Octeon doesn't reorder reads, so a full barrier can be
11619 created by using SYNCW to order writes combined with the
11620 write from the following SC. When the SC successfully
11621 completes, we know that all preceding writes are also
11622 committed to the coherent memory system. It is possible
11623 for a single SYNCW to fail, but a pair of them will never
11624 fail, so we use two. */
11625 mips_multi_add_insn ("syncw", NULL
);
11626 mips_multi_add_insn ("syncw", NULL
);
11629 mips_multi_add_insn ("sync", NULL
);
11632 /* Output the branch-back label. */
11633 mips_multi_add_label ("1:");
11635 /* OLDVAL = *MEM. */
11636 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
11637 oldval
, mem
, NULL
);
11639 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11640 if (required_oldval
)
11642 if (inclusive_mask
== 0)
11646 gcc_assert (oldval
!= at
);
11647 mips_multi_add_insn ("and\t%0,%1,%2",
11648 at
, oldval
, inclusive_mask
, NULL
);
11651 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
11654 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11655 if (exclusive_mask
== 0)
11659 gcc_assert (oldval
!= at
);
11660 mips_multi_add_insn ("and\t%0,%1,%z2",
11661 at
, oldval
, exclusive_mask
, NULL
);
11665 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11667 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11668 at least one instruction in that case. */
11669 if (insn1
== SYNC_INSN1_MOVE
11670 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
11674 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
11675 newval
, oldval
, insn1_op2
, NULL
);
11679 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11680 if (insn2
== SYNC_INSN2_NOP
)
11684 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
11685 newval
, tmp2
, inclusive_mask
, NULL
);
11688 tmp3_insn
= mips_multi_last_index ();
11690 /* $AT = $TMP1 | $TMP3. */
11691 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
11693 mips_multi_set_operand (tmp3_insn
, 0, at
);
11698 gcc_assert (tmp1
!= tmp3
);
11699 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
11702 /* if (!commit (*MEM = $AT)) goto 1.
11704 This will sometimes be a delayed branch; see the write code below
11706 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
11707 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
11709 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11710 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
11712 mips_multi_copy_insn (tmp3_insn
);
11713 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
11716 mips_multi_add_insn ("nop", NULL
);
11718 /* Output the acquire side of the memory barrier. */
11719 if (TARGET_SYNC_AFTER_SC
)
11720 mips_multi_add_insn ("sync", NULL
);
11722 /* Output the exit label, if needed. */
11723 if (required_oldval
)
11724 mips_multi_add_label ("2:");
11726 #undef READ_OPERAND
11729 /* Output and/or return the asm template for sync loop INSN, which has
11730 the operands given by OPERANDS. */
11733 mips_output_sync_loop (rtx insn
, rtx
*operands
)
11735 mips_process_sync_loop (insn
, operands
);
11737 /* Use branch-likely instructions to work around the LL/SC R10000
11739 mips_branch_likely
= TARGET_FIX_R10000
;
11741 mips_push_asm_switch (&mips_noreorder
);
11742 mips_push_asm_switch (&mips_nomacro
);
11743 mips_push_asm_switch (&mips_noat
);
11744 mips_start_ll_sc_sync_block ();
11746 mips_multi_write ();
11748 mips_end_ll_sc_sync_block ();
11749 mips_pop_asm_switch (&mips_noat
);
11750 mips_pop_asm_switch (&mips_nomacro
);
11751 mips_pop_asm_switch (&mips_noreorder
);
11756 /* Return the number of individual instructions in sync loop INSN,
11757 which has the operands given by OPERANDS. */
11760 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
11762 mips_process_sync_loop (insn
, operands
);
11763 return mips_multi_num_insns
;
11766 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11767 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11769 When working around R4000 and R4400 errata, we need to make sure that
11770 the division is not immediately followed by a shift[1][2]. We also
11771 need to stop the division from being put into a branch delay slot[3].
11772 The easiest way to avoid both problems is to add a nop after the
11773 division. When a divide-by-zero check is needed, this nop can be
11774 used to fill the branch delay slot.
11776 [1] If a double-word or a variable shift executes immediately
11777 after starting an integer division, the shift may give an
11778 incorrect result. See quotations of errata #16 and #28 from
11779 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11780 in mips.md for details.
11782 [2] A similar bug to [1] exists for all revisions of the
11783 R4000 and the R4400 when run in an MC configuration.
11784 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11786 "19. In this following sequence:
11788 ddiv (or ddivu or div or divu)
11789 dsll32 (or dsrl32, dsra32)
11791 if an MPT stall occurs, while the divide is slipping the cpu
11792 pipeline, then the following double shift would end up with an
11795 Workaround: The compiler needs to avoid generating any
11796 sequence with divide followed by extended double shift."
11798 This erratum is also present in "MIPS R4400MC Errata, Processor
11799 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11800 & 3.0" as errata #10 and #4, respectively.
11802 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11803 (also valid for MIPS R4000MC processors):
11805 "52. R4000SC: This bug does not apply for the R4000PC.
11807 There are two flavors of this bug:
11809 1) If the instruction just after divide takes an RF exception
11810 (tlb-refill, tlb-invalid) and gets an instruction cache
11811 miss (both primary and secondary) and the line which is
11812 currently in secondary cache at this index had the first
11813 data word, where the bits 5..2 are set, then R4000 would
11814 get a wrong result for the div.
11819 ------------------- # end-of page. -tlb-refill
11824 ------------------- # end-of page. -tlb-invalid
11827 2) If the divide is in the taken branch delay slot, where the
11828 target takes RF exception and gets an I-cache miss for the
11829 exception vector or where I-cache miss occurs for the
11830 target address, under the above mentioned scenarios, the
11831 div would get wrong results.
11834 j r2 # to next page mapped or unmapped
11835 div r8,r9 # this bug would be there as long
11836 # as there is an ICache miss and
11837 nop # the "data pattern" is present
11840 beq r0, r0, NextPage # to Next page
11844 This bug is present for div, divu, ddiv, and ddivu
11847 Workaround: For item 1), OS could make sure that the next page
11848 after the divide instruction is also mapped. For item 2), the
11849 compiler could make sure that the divide instruction is not in
11850 the branch delay slot."
11852 These processors have PRId values of 0x00004220 and 0x00004300 for
11853 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11856 mips_output_division (const char *division
, rtx
*operands
)
11861 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
11863 output_asm_insn (s
, operands
);
11866 if (TARGET_CHECK_ZERO_DIV
)
11870 output_asm_insn (s
, operands
);
11871 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
11873 else if (GENERATE_DIVIDE_TRAPS
)
11875 /* Avoid long replay penalty on load miss by putting the trap before
11878 output_asm_insn ("teq\t%2,%.,7", operands
);
11881 output_asm_insn (s
, operands
);
11882 s
= "teq\t%2,%.,7";
11887 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
11888 output_asm_insn (s
, operands
);
11889 s
= "break\t7%)\n1:";
11895 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11896 instruction and if OUT_INSN assigns to the accumulator operand. */
11899 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
11903 x
= single_set (in_insn
);
11909 if (GET_CODE (x
) == PLUS
11910 && GET_CODE (XEXP (x
, 0)) == MULT
11911 && reg_set_p (XEXP (x
, 1), out_insn
))
11914 if (GET_CODE (x
) == MINUS
11915 && GET_CODE (XEXP (x
, 1)) == MULT
11916 && reg_set_p (XEXP (x
, 0), out_insn
))
11922 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11923 data rather than the address. We need this because the cprestore
11924 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11925 which causes the default routine to abort. We just return false
11929 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
11931 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
11934 return !store_data_bypass_p (out_insn
, in_insn
);
11938 /* Variables and flags used in scheduler hooks when tuning for
11942 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11945 /* If true, then next ALU1/2 instruction will go to ALU1. */
11948 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11951 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11952 int alu1_core_unit_code
;
11953 int alu2_core_unit_code
;
11954 int falu1_core_unit_code
;
11955 int falu2_core_unit_code
;
11957 /* True if current cycle has a multi instruction.
11958 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11959 bool cycle_has_multi_p
;
11961 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11962 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11964 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11965 instruction to go ALU1. */
11966 rtx alu1_turn_enabled_insn
;
11967 rtx alu2_turn_enabled_insn
;
11968 rtx falu1_turn_enabled_insn
;
11969 rtx falu2_turn_enabled_insn
;
11972 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11973 dependencies have no cost, except on the 20Kc where output-dependence
11974 is treated like input-dependence. */
11977 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
11978 rtx dep ATTRIBUTE_UNUSED
, int cost
)
11980 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
11983 if (REG_NOTE_KIND (link
) != 0)
11988 /* Return the number of instructions that can be issued per cycle. */
11991 mips_issue_rate (void)
11995 case PROCESSOR_74KC
:
11996 case PROCESSOR_74KF2_1
:
11997 case PROCESSOR_74KF1_1
:
11998 case PROCESSOR_74KF3_2
:
11999 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12000 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12001 but in reality only a maximum of 3 insns can be issued as
12002 floating-point loads and stores also require a slot in the
12004 case PROCESSOR_R10000
:
12005 /* All R10K Processors are quad-issue (being the first MIPS
12006 processors to support this feature). */
12009 case PROCESSOR_20KC
:
12010 case PROCESSOR_R4130
:
12011 case PROCESSOR_R5400
:
12012 case PROCESSOR_R5500
:
12013 case PROCESSOR_R7000
:
12014 case PROCESSOR_R9000
:
12015 case PROCESSOR_OCTEON
:
12018 case PROCESSOR_SB1
:
12019 case PROCESSOR_SB1A
:
12020 /* This is actually 4, but we get better performance if we claim 3.
12021 This is partly because of unwanted speculative code motion with the
12022 larger number, and partly because in most common cases we can't
12023 reach the theoretical max of 4. */
12026 case PROCESSOR_LOONGSON_2E
:
12027 case PROCESSOR_LOONGSON_2F
:
12035 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12038 mips_ls2_init_dfa_post_cycle_insn (void)
12041 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12042 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
12046 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12047 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
12051 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12052 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
12056 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12057 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
12060 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
12061 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
12062 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
12063 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
12066 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12067 Init data used in mips_dfa_post_advance_cycle. */
12070 mips_init_dfa_post_cycle_insn (void)
12072 if (TUNE_LOONGSON_2EF
)
12073 mips_ls2_init_dfa_post_cycle_insn ();
12076 /* Initialize STATE when scheduling for Loongson 2E/2F.
12077 Support round-robin dispatch scheme by enabling only one of
12078 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12082 mips_ls2_dfa_post_advance_cycle (state_t state
)
12084 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
12086 /* Though there are no non-pipelined ALU1 insns,
12087 we can get an instruction of type 'multi' before reload. */
12088 gcc_assert (mips_ls2
.cycle_has_multi_p
);
12089 mips_ls2
.alu1_turn_p
= false;
12092 mips_ls2
.cycle_has_multi_p
= false;
12094 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
12095 /* We have a non-pipelined alu instruction in the core,
12096 adjust round-robin counter. */
12097 mips_ls2
.alu1_turn_p
= true;
12099 if (mips_ls2
.alu1_turn_p
)
12101 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
12102 gcc_unreachable ();
12106 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
12107 gcc_unreachable ();
12110 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
12112 /* There are no non-pipelined FALU1 insns. */
12113 gcc_unreachable ();
12114 mips_ls2
.falu1_turn_p
= false;
12117 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
12118 /* We have a non-pipelined falu instruction in the core,
12119 adjust round-robin counter. */
12120 mips_ls2
.falu1_turn_p
= true;
12122 if (mips_ls2
.falu1_turn_p
)
12124 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
12125 gcc_unreachable ();
12129 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
12130 gcc_unreachable ();
12134 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12135 This hook is being called at the start of each cycle. */
12138 mips_dfa_post_advance_cycle (void)
12140 if (TUNE_LOONGSON_2EF
)
12141 mips_ls2_dfa_post_advance_cycle (curr_state
);
12144 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12145 be as wide as the scheduling freedom in the DFA. */
12148 mips_multipass_dfa_lookahead (void)
12150 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12154 if (TUNE_LOONGSON_2EF
)
12163 /* Remove the instruction at index LOWER from ready queue READY and
12164 reinsert it in front of the instruction at index HIGHER. LOWER must
12168 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
12173 new_head
= ready
[lower
];
12174 for (i
= lower
; i
< higher
; i
++)
12175 ready
[i
] = ready
[i
+ 1];
12176 ready
[i
] = new_head
;
12179 /* If the priority of the instruction at POS2 in the ready queue READY
12180 is within LIMIT units of that of the instruction at POS1, swap the
12181 instructions if POS2 is not already less than POS1. */
12184 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
12187 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
12191 temp
= ready
[pos1
];
12192 ready
[pos1
] = ready
[pos2
];
12193 ready
[pos2
] = temp
;
12197 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12198 that may clobber hi or lo. */
12199 static rtx mips_macc_chains_last_hilo
;
12201 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12202 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12205 mips_macc_chains_record (rtx insn
)
12207 if (get_attr_may_clobber_hilo (insn
))
12208 mips_macc_chains_last_hilo
= insn
;
12211 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12212 has NREADY elements, looking for a multiply-add or multiply-subtract
12213 instruction that is cumulative with mips_macc_chains_last_hilo.
12214 If there is one, promote it ahead of anything else that might
12215 clobber hi or lo. */
12218 mips_macc_chains_reorder (rtx
*ready
, int nready
)
12222 if (mips_macc_chains_last_hilo
!= 0)
12223 for (i
= nready
- 1; i
>= 0; i
--)
12224 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
12226 for (j
= nready
- 1; j
> i
; j
--)
12227 if (recog_memoized (ready
[j
]) >= 0
12228 && get_attr_may_clobber_hilo (ready
[j
]))
12230 mips_promote_ready (ready
, i
, j
);
12237 /* The last instruction to be scheduled. */
12238 static rtx vr4130_last_insn
;
12240 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12241 points to an rtx that is initially an instruction. Nullify the rtx
12242 if the instruction uses the value of register X. */
12245 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
12250 insn_ptr
= (rtx
*) data
;
12253 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
12257 /* Return true if there is true register dependence between vr4130_last_insn
12261 vr4130_true_reg_dependence_p (rtx insn
)
12263 note_stores (PATTERN (vr4130_last_insn
),
12264 vr4130_true_reg_dependence_p_1
, &insn
);
12268 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12269 the ready queue and that INSN2 is the instruction after it, return
12270 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12271 in which INSN1 and INSN2 can probably issue in parallel, but for
12272 which (INSN2, INSN1) should be less sensitive to instruction
12273 alignment than (INSN1, INSN2). See 4130.md for more details. */
12276 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
12278 sd_iterator_def sd_it
;
12281 /* Check for the following case:
12283 1) there is some other instruction X with an anti dependence on INSN1;
12284 2) X has a higher priority than INSN2; and
12285 3) X is an arithmetic instruction (and thus has no unit restrictions).
12287 If INSN1 is the last instruction blocking X, it would better to
12288 choose (INSN1, X) over (INSN2, INSN1). */
12289 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
12290 if (DEP_TYPE (dep
) == REG_DEP_ANTI
12291 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
12292 && recog_memoized (DEP_CON (dep
)) >= 0
12293 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
12296 if (vr4130_last_insn
!= 0
12297 && recog_memoized (insn1
) >= 0
12298 && recog_memoized (insn2
) >= 0)
12300 /* See whether INSN1 and INSN2 use different execution units,
12301 or if they are both ALU-type instructions. If so, they can
12302 probably execute in parallel. */
12303 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
12304 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
12305 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
12307 /* If only one of the instructions has a dependence on
12308 vr4130_last_insn, prefer to schedule the other one first. */
12309 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
12310 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
12311 if (dep1_p
!= dep2_p
)
12314 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12315 is not an ALU-type instruction and if INSN1 uses the same
12316 execution unit. (Note that if this condition holds, we already
12317 know that INSN2 uses a different execution unit.) */
12318 if (class1
!= VR4130_CLASS_ALU
12319 && recog_memoized (vr4130_last_insn
) >= 0
12320 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
12327 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12328 queue with at least two instructions. Swap the first two if
12329 vr4130_swap_insns_p says that it could be worthwhile. */
12332 vr4130_reorder (rtx
*ready
, int nready
)
12334 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
12335 mips_promote_ready (ready
, nready
- 2, nready
- 1);
12338 /* Record whether last 74k AGEN instruction was a load or store. */
12339 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12341 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12342 resets to TYPE_UNKNOWN state. */
12345 mips_74k_agen_init (rtx insn
)
12347 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
12348 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12351 enum attr_type type
= get_attr_type (insn
);
12352 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
12353 mips_last_74k_agen_insn
= type
;
12357 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12358 loads to be grouped together, and multiple stores to be grouped
12359 together. Swap things around in the ready queue to make this happen. */
12362 mips_74k_agen_reorder (rtx
*ready
, int nready
)
12365 int store_pos
, load_pos
;
12370 for (i
= nready
- 1; i
>= 0; i
--)
12372 rtx insn
= ready
[i
];
12373 if (USEFUL_INSN_P (insn
))
12374 switch (get_attr_type (insn
))
12377 if (store_pos
== -1)
12382 if (load_pos
== -1)
12391 if (load_pos
== -1 || store_pos
== -1)
12394 switch (mips_last_74k_agen_insn
)
12397 /* Prefer to schedule loads since they have a higher latency. */
12399 /* Swap loads to the front of the queue. */
12400 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
12403 /* Swap stores to the front of the queue. */
12404 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
12411 /* Implement TARGET_SCHED_INIT. */
12414 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12415 int max_ready ATTRIBUTE_UNUSED
)
12417 mips_macc_chains_last_hilo
= 0;
12418 vr4130_last_insn
= 0;
12419 mips_74k_agen_init (NULL_RTX
);
12421 /* When scheduling for Loongson2, branch instructions go to ALU1,
12422 therefore basic block is most likely to start with round-robin counter
12423 pointed to ALU2. */
12424 mips_ls2
.alu1_turn_p
= false;
12425 mips_ls2
.falu1_turn_p
= true;
12428 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12431 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12432 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12434 if (!reload_completed
12435 && TUNE_MACC_CHAINS
12437 mips_macc_chains_reorder (ready
, *nreadyp
);
12439 if (reload_completed
12441 && !TARGET_VR4130_ALIGN
12443 vr4130_reorder (ready
, *nreadyp
);
12446 mips_74k_agen_reorder (ready
, *nreadyp
);
12448 return mips_issue_rate ();
12451 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12454 mips_ls2_variable_issue (rtx insn
)
12456 if (mips_ls2
.alu1_turn_p
)
12458 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
12459 mips_ls2
.alu1_turn_p
= false;
12463 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
12464 mips_ls2
.alu1_turn_p
= true;
12467 if (mips_ls2
.falu1_turn_p
)
12469 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
12470 mips_ls2
.falu1_turn_p
= false;
12474 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
12475 mips_ls2
.falu1_turn_p
= true;
12478 if (recog_memoized (insn
) >= 0)
12479 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
12482 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12485 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12486 rtx insn
, int more
)
12488 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12489 if (USEFUL_INSN_P (insn
))
12491 if (get_attr_type (insn
) != TYPE_GHOST
)
12493 if (!reload_completed
&& TUNE_MACC_CHAINS
)
12494 mips_macc_chains_record (insn
);
12495 vr4130_last_insn
= insn
;
12497 mips_74k_agen_init (insn
);
12498 else if (TUNE_LOONGSON_2EF
)
12499 mips_ls2_variable_issue (insn
);
12502 /* Instructions of type 'multi' should all be split before
12503 the second scheduling pass. */
12504 gcc_assert (!reload_completed
12505 || recog_memoized (insn
) < 0
12506 || get_attr_type (insn
) != TYPE_MULTI
);
12511 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12512 return the first operand of the associated PREF or PREFX insn. */
12515 mips_prefetch_cookie (rtx write
, rtx locality
)
12517 /* store_streamed / load_streamed. */
12518 if (INTVAL (locality
) <= 0)
12519 return GEN_INT (INTVAL (write
) + 4);
12521 /* store / load. */
12522 if (INTVAL (locality
) <= 2)
12525 /* store_retained / load_retained. */
12526 return GEN_INT (INTVAL (write
) + 6);
12529 /* Flags that indicate when a built-in function is available.
12531 BUILTIN_AVAIL_NON_MIPS16
12532 The function is available on the current target, but only
12533 in non-MIPS16 mode. */
12534 #define BUILTIN_AVAIL_NON_MIPS16 1
12536 /* Declare an availability predicate for built-in functions that
12537 require non-MIPS16 mode and also require COND to be true.
12538 NAME is the main part of the predicate's name. */
12539 #define AVAIL_NON_MIPS16(NAME, COND) \
12540 static unsigned int \
12541 mips_builtin_avail_##NAME (void) \
12543 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12546 /* This structure describes a single built-in function. */
12547 struct mips_builtin_description
{
12548 /* The code of the main .md file instruction. See mips_builtin_type
12549 for more information. */
12550 enum insn_code icode
;
12552 /* The floating-point comparison code to use with ICODE, if any. */
12553 enum mips_fp_condition cond
;
12555 /* The name of the built-in function. */
12558 /* Specifies how the function should be expanded. */
12559 enum mips_builtin_type builtin_type
;
12561 /* The function's prototype. */
12562 enum mips_function_type function_type
;
12564 /* Whether the function is available. */
12565 unsigned int (*avail
) (void);
12568 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
12569 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
12570 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
12571 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
12572 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
12573 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
12574 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
12575 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
12576 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
12578 /* Construct a mips_builtin_description from the given arguments.
12580 INSN is the name of the associated instruction pattern, without the
12581 leading CODE_FOR_mips_.
12583 CODE is the floating-point condition code associated with the
12584 function. It can be 'f' if the field is not applicable.
12586 NAME is the name of the function itself, without the leading
12589 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12591 AVAIL is the name of the availability predicate, without the leading
12592 mips_builtin_avail_. */
12593 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12594 FUNCTION_TYPE, AVAIL) \
12595 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12596 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12597 mips_builtin_avail_ ## AVAIL }
12599 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12600 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12601 are as for MIPS_BUILTIN. */
12602 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12603 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12605 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12606 are subject to mips_builtin_avail_<AVAIL>. */
12607 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12608 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12609 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12610 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12611 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12613 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12614 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12615 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12616 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12617 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12618 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12620 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12621 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12623 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12624 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12626 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12627 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12630 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12631 are subject to mips_builtin_avail_mips3d. */
12632 #define CMP_4S_BUILTINS(INSN, COND) \
12633 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12634 MIPS_BUILTIN_CMP_ANY, \
12635 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12636 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12637 MIPS_BUILTIN_CMP_ALL, \
12638 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12640 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12641 instruction requires mips_builtin_avail_<AVAIL>. */
12642 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12643 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12644 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12646 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12647 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12650 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12651 #define CMP_BUILTINS(COND) \
12652 MOVTF_BUILTINS (c, COND, paired_single), \
12653 MOVTF_BUILTINS (cabs, COND, mips3d), \
12654 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12655 CMP_PS_BUILTINS (c, COND, paired_single), \
12656 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12657 CMP_4S_BUILTINS (c, COND), \
12658 CMP_4S_BUILTINS (cabs, COND)
12660 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12661 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12662 and AVAIL are as for MIPS_BUILTIN. */
12663 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12664 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12665 FUNCTION_TYPE, AVAIL)
12667 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12668 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12669 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12670 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12671 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12673 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12674 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12675 builtin_description field. */
12676 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12677 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12678 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12679 FUNCTION_TYPE, mips_builtin_avail_loongson }
12681 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12682 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12683 builtin_description field. */
12684 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12685 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12687 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12688 We use functions of this form when the same insn can be usefully applied
12689 to more than one datatype. */
12690 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12691 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12693 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12694 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12695 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12696 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12697 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12698 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12700 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12701 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12702 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12703 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12704 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12705 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12706 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12707 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12708 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12709 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12710 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12711 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12712 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12713 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12714 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12715 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12716 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12717 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12718 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12719 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12720 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12721 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12722 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12723 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12724 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12725 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12726 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12727 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12728 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12729 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12731 static const struct mips_builtin_description mips_builtins
[] = {
12732 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12733 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12734 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12735 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12736 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
12737 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
12738 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
12739 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
12741 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
12742 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12743 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12744 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12745 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12747 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
12748 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
12749 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12750 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
12751 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
12752 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12754 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
12755 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
12756 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12757 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
12758 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
12759 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12761 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
12763 /* Built-in functions for the SB-1 processor. */
12764 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
12766 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12767 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12768 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12769 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12770 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12771 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12772 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12773 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12774 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12775 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12776 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12777 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12778 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12779 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12780 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
12781 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
12782 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
12783 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
12784 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
12785 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
12786 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
12787 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
12788 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
12789 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12790 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12791 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12792 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12793 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12794 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12795 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12796 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12797 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
12798 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12799 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12800 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12801 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
12802 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12803 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12804 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12805 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
12806 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
12807 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12808 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
12809 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
12810 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
12811 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12812 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
12813 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
12814 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12815 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12816 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12817 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12818 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12819 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12820 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12821 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12822 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12823 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12824 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12825 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12826 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
12827 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
12828 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12829 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12830 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12831 BPOSGE_BUILTIN (32, dsp
),
12833 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12834 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
12835 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12836 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12837 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12838 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12839 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12840 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12841 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12842 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12843 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12844 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12845 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12846 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12847 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12848 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12849 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
12850 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
12851 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
12852 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12853 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
12854 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
12855 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
12856 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12857 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12858 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12859 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12860 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12861 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12862 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12863 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12864 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12865 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12866 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12867 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12869 /* Built-in functions for the DSP ASE (32-bit only). */
12870 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12871 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12872 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12873 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12874 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12875 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12876 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12877 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12878 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12879 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12880 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12881 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12882 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12883 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12884 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12885 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12886 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12887 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12888 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12889 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
12890 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
12892 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12893 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12894 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12895 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dspr2_32
),
12896 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dspr2_32
),
12897 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dspr2_32
),
12898 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dspr2_32
),
12899 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12900 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dspr2_32
),
12901 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dspr2_32
),
12902 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12903 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12904 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12905 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12906 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12907 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12909 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12910 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
12911 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
12912 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
12913 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12914 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12915 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12916 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12917 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12918 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12919 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
12920 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
12921 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12922 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12923 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12924 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12925 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
12926 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12927 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12928 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12929 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
12930 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12931 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12932 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12933 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12934 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12935 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12936 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12937 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12938 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12939 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12940 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12941 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12942 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12943 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12944 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12945 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12946 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12947 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
12948 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
12949 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12950 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12951 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12952 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12953 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12954 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12955 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12956 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12957 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
12958 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12959 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12960 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12961 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12962 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
12963 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
12964 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12965 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12966 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12967 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
12968 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12969 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
12970 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
12971 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI
),
12972 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI
),
12973 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
12974 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
12975 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
12976 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
12977 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
12978 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
12979 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
12980 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
12981 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
12982 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
12983 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
12984 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
12985 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12986 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12987 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12988 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12989 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12990 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12991 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
12992 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
12993 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12994 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12995 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12996 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12997 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12998 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12999 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13000 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13001 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13002 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13003 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13004 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13005 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13006 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13007 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13008 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13010 /* Sundry other built-in functions. */
13011 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
13014 /* MODE is a vector mode whose elements have type TYPE. Return the type
13015 of the vector itself. */
13018 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
13020 static tree types
[2 * (int) MAX_MACHINE_MODE
];
13023 mode_index
= (int) mode
;
13025 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
13026 mode_index
+= MAX_MACHINE_MODE
;
13028 if (types
[mode_index
] == NULL_TREE
)
13029 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
13030 return types
[mode_index
];
13033 /* Return a type for 'const volatile void *'. */
13036 mips_build_cvpointer_type (void)
13040 if (cache
== NULL_TREE
)
13041 cache
= build_pointer_type (build_qualified_type
13043 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
13047 /* Source-level argument types. */
13048 #define MIPS_ATYPE_VOID void_type_node
13049 #define MIPS_ATYPE_INT integer_type_node
13050 #define MIPS_ATYPE_POINTER ptr_type_node
13051 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13053 /* Standard mode-based argument types. */
13054 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13055 #define MIPS_ATYPE_SI intSI_type_node
13056 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13057 #define MIPS_ATYPE_DI intDI_type_node
13058 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13059 #define MIPS_ATYPE_SF float_type_node
13060 #define MIPS_ATYPE_DF double_type_node
13062 /* Vector argument types. */
13063 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13064 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13065 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13066 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13067 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13068 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13069 #define MIPS_ATYPE_UV2SI \
13070 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13071 #define MIPS_ATYPE_UV4HI \
13072 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13073 #define MIPS_ATYPE_UV8QI \
13074 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13076 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13077 their associated MIPS_ATYPEs. */
13078 #define MIPS_FTYPE_ATYPES1(A, B) \
13079 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13081 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13082 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13084 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13085 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13087 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13088 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13091 /* Return the function type associated with function prototype TYPE. */
13094 mips_build_function_type (enum mips_function_type type
)
13096 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
13098 if (types
[(int) type
] == NULL_TREE
)
13101 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13102 case MIPS_FTYPE_NAME##NUM ARGS: \
13103 types[(int) type] \
13104 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13107 #include "config/mips/mips-ftypes.def"
13108 #undef DEF_MIPS_FTYPE
13110 gcc_unreachable ();
13113 return types
[(int) type
];
13116 /* Implement TARGET_INIT_BUILTINS. */
13119 mips_init_builtins (void)
13121 const struct mips_builtin_description
*d
;
13124 /* Iterate through all of the bdesc arrays, initializing all of the
13125 builtin functions. */
13126 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
13128 d
= &mips_builtins
[i
];
13130 add_builtin_function (d
->name
,
13131 mips_build_function_type (d
->function_type
),
13132 i
, BUILT_IN_MD
, NULL
, NULL
);
13136 /* Take argument ARGNO from EXP's argument list and convert it into a
13137 form suitable for input operand OPNO of instruction ICODE. Return the
13141 mips_prepare_builtin_arg (enum insn_code icode
,
13142 unsigned int opno
, tree exp
, unsigned int argno
)
13146 enum machine_mode mode
;
13148 arg
= CALL_EXPR_ARG (exp
, argno
);
13149 value
= expand_normal (arg
);
13150 mode
= insn_data
[icode
].operand
[opno
].mode
;
13151 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
13153 /* We need to get the mode from ARG for two reasons:
13155 - to cope with address operands, where MODE is the mode of the
13156 memory, rather than of VALUE itself.
13158 - to cope with special predicates like pmode_register_operand,
13159 where MODE is VOIDmode. */
13160 value
= copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg
)), value
);
13162 /* Check the predicate again. */
13163 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
13165 error ("invalid argument to built-in function");
13173 /* Return an rtx suitable for output operand OP of instruction ICODE.
13174 If TARGET is non-null, try to use it where possible. */
13177 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
13179 enum machine_mode mode
;
13181 mode
= insn_data
[icode
].operand
[op
].mode
;
13182 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
13183 target
= gen_reg_rtx (mode
);
13188 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13189 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13190 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13191 suggests a good place to put the result. */
13194 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
13197 rtx ops
[MAX_RECOG_OPERANDS
];
13200 /* Map any target to operand 0. */
13204 target
= mips_prepare_builtin_target (icode
, opno
, target
);
13205 ops
[opno
] = target
;
13209 /* Map the arguments to the other operands. The n_operands value
13210 for an expander includes match_dups and match_scratches as well as
13211 match_operands, so n_operands is only an upper bound on the number
13212 of arguments to the expander function. */
13213 gcc_assert (opno
+ call_expr_nargs (exp
) <= insn_data
[icode
].n_operands
);
13214 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++, opno
++)
13215 ops
[opno
] = mips_prepare_builtin_arg (icode
, opno
, exp
, argno
);
13220 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1]));
13224 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2]));
13228 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2], ops
[3]));
13232 gcc_unreachable ();
13237 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13238 function; TYPE says which. EXP is the CALL_EXPR that calls the
13239 function, ICODE is the instruction that should be used to compare
13240 the first two arguments, and COND is the condition it should test.
13241 TARGET, if nonnull, suggests a good place to put the result. */
13244 mips_expand_builtin_movtf (enum mips_builtin_type type
,
13245 enum insn_code icode
, enum mips_fp_condition cond
,
13246 rtx target
, tree exp
)
13248 rtx cmp_result
, op0
, op1
;
13250 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
13251 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 0);
13252 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 1);
13253 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
, GEN_INT (cond
)));
13255 icode
= CODE_FOR_mips_cond_move_tf_ps
;
13256 target
= mips_prepare_builtin_target (icode
, 0, target
);
13257 if (type
== MIPS_BUILTIN_MOVT
)
13259 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 2);
13260 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 3);
13264 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 2);
13265 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 3);
13267 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
13271 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13272 into TARGET otherwise. Return TARGET. */
13275 mips_builtin_branch_and_move (rtx condition
, rtx target
,
13276 rtx value_if_true
, rtx value_if_false
)
13278 rtx true_label
, done_label
;
13280 true_label
= gen_label_rtx ();
13281 done_label
= gen_label_rtx ();
13283 /* First assume that CONDITION is false. */
13284 mips_emit_move (target
, value_if_false
);
13286 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13287 emit_jump_insn (gen_condjump (condition
, true_label
));
13288 emit_jump_insn (gen_jump (done_label
));
13291 /* Fix TARGET if CONDITION is true. */
13292 emit_label (true_label
);
13293 mips_emit_move (target
, value_if_true
);
13295 emit_label (done_label
);
13299 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13300 the CALL_EXPR that calls the function, ICODE is the code of the
13301 comparison instruction, and COND is the condition it should test.
13302 TARGET, if nonnull, suggests a good place to put the boolean result. */
13305 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
13306 enum insn_code icode
, enum mips_fp_condition cond
,
13307 rtx target
, tree exp
)
13309 rtx offset
, condition
, cmp_result
, args
[MAX_RECOG_OPERANDS
];
13312 if (target
== 0 || GET_MODE (target
) != SImode
)
13313 target
= gen_reg_rtx (SImode
);
13315 /* The instruction should have a target operand, an operand for each
13316 argument, and an operand for COND. */
13317 gcc_assert (call_expr_nargs (exp
) + 2 == insn_data
[icode
].n_operands
);
13319 /* Prepare the operands to the comparison. */
13320 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
13321 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
13322 args
[argno
] = mips_prepare_builtin_arg (icode
, argno
+ 1, exp
, argno
);
13324 switch (insn_data
[icode
].n_operands
)
13327 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
13332 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
13333 args
[2], args
[3], GEN_INT (cond
)));
13337 gcc_unreachable ();
13340 /* If the comparison sets more than one register, we define the result
13341 to be 0 if all registers are false and -1 if all registers are true.
13342 The value of the complete result is indeterminate otherwise. */
13343 switch (builtin_type
)
13345 case MIPS_BUILTIN_CMP_ALL
:
13346 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
13347 return mips_builtin_branch_and_move (condition
, target
,
13348 const0_rtx
, const1_rtx
);
13350 case MIPS_BUILTIN_CMP_UPPER
:
13351 case MIPS_BUILTIN_CMP_LOWER
:
13352 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
13353 condition
= gen_single_cc (cmp_result
, offset
);
13354 return mips_builtin_branch_and_move (condition
, target
,
13355 const1_rtx
, const0_rtx
);
13358 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
13359 return mips_builtin_branch_and_move (condition
, target
,
13360 const1_rtx
, const0_rtx
);
13364 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13365 if nonnull, suggests a good place to put the boolean result. */
13368 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
13370 rtx condition
, cmp_result
;
13373 if (target
== 0 || GET_MODE (target
) != SImode
)
13374 target
= gen_reg_rtx (SImode
);
13376 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
13378 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
13383 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
13384 return mips_builtin_branch_and_move (condition
, target
,
13385 const1_rtx
, const0_rtx
);
13388 /* Implement TARGET_EXPAND_BUILTIN. */
13391 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13392 enum machine_mode mode
, int ignore
)
13395 unsigned int fcode
, avail
;
13396 const struct mips_builtin_description
*d
;
13398 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13399 fcode
= DECL_FUNCTION_CODE (fndecl
);
13400 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
13401 d
= &mips_builtins
[fcode
];
13402 avail
= d
->avail ();
13403 gcc_assert (avail
!= 0);
13406 error ("built-in function %qE not supported for MIPS16",
13407 DECL_NAME (fndecl
));
13408 return ignore
? const0_rtx
: CONST0_RTX (mode
);
13410 switch (d
->builtin_type
)
13412 case MIPS_BUILTIN_DIRECT
:
13413 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
13415 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
13416 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
13418 case MIPS_BUILTIN_MOVT
:
13419 case MIPS_BUILTIN_MOVF
:
13420 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
13421 d
->cond
, target
, exp
);
13423 case MIPS_BUILTIN_CMP_ANY
:
13424 case MIPS_BUILTIN_CMP_ALL
:
13425 case MIPS_BUILTIN_CMP_UPPER
:
13426 case MIPS_BUILTIN_CMP_LOWER
:
13427 case MIPS_BUILTIN_CMP_SINGLE
:
13428 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
13429 d
->cond
, target
, exp
);
13431 case MIPS_BUILTIN_BPOSGE32
:
13432 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
13434 gcc_unreachable ();
13437 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13438 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13439 struct mips16_constant
{
13440 struct mips16_constant
*next
;
13443 enum machine_mode mode
;
13446 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13447 first constant, HIGHEST_ADDRESS is the highest address that the first
13448 byte of the pool can have, and INSN_ADDRESS is the current instruction
13450 struct mips16_constant_pool
{
13451 struct mips16_constant
*first
;
13452 int highest_address
;
13456 /* Add constant VALUE to POOL and return its label. MODE is the
13457 value's mode (used for CONST_INTs, etc.). */
13460 mips16_add_constant (struct mips16_constant_pool
*pool
,
13461 rtx value
, enum machine_mode mode
)
13463 struct mips16_constant
**p
, *c
;
13464 bool first_of_size_p
;
13466 /* See whether the constant is already in the pool. If so, return the
13467 existing label, otherwise leave P pointing to the place where the
13468 constant should be added.
13470 Keep the pool sorted in increasing order of mode size so that we can
13471 reduce the number of alignments needed. */
13472 first_of_size_p
= true;
13473 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
13475 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
13476 return (*p
)->label
;
13477 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
13479 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
13480 first_of_size_p
= false;
13483 /* In the worst case, the constant needed by the earliest instruction
13484 will end up at the end of the pool. The entire pool must then be
13485 accessible from that instruction.
13487 When adding the first constant, set the pool's highest address to
13488 the address of the first out-of-range byte. Adjust this address
13489 downwards each time a new constant is added. */
13490 if (pool
->first
== 0)
13491 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13492 of the instruction with the lowest two bits clear. The base PC
13493 value for LDPC has the lowest three bits clear. Assume the worst
13494 case here; namely that the PC-relative instruction occupies the
13495 last 2 bytes in an aligned word. */
13496 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
13497 pool
->highest_address
-= GET_MODE_SIZE (mode
);
13498 if (first_of_size_p
)
13499 /* Take into account the worst possible padding due to alignment. */
13500 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
13502 /* Create a new entry. */
13503 c
= XNEW (struct mips16_constant
);
13506 c
->label
= gen_label_rtx ();
13513 /* Output constant VALUE after instruction INSN and return the last
13514 instruction emitted. MODE is the mode of the constant. */
13517 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
13519 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
13521 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
13522 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
13525 if (SCALAR_FLOAT_MODE_P (mode
))
13526 return emit_insn_after (gen_consttable_float (value
), insn
);
13528 if (VECTOR_MODE_P (mode
))
13532 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
13533 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
13534 CONST_VECTOR_ELT (value
, i
), insn
);
13538 gcc_unreachable ();
13541 /* Dump out the constants in CONSTANTS after INSN. */
13544 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
13546 struct mips16_constant
*c
, *next
;
13550 for (c
= constants
; c
!= NULL
; c
= next
)
13552 /* If necessary, increase the alignment of PC. */
13553 if (align
< GET_MODE_SIZE (c
->mode
))
13555 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
13556 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
13558 align
= GET_MODE_SIZE (c
->mode
);
13560 insn
= emit_label_after (c
->label
, insn
);
13561 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
13567 emit_barrier_after (insn
);
13570 /* Return the length of instruction INSN. */
13573 mips16_insn_length (rtx insn
)
13577 rtx body
= PATTERN (insn
);
13578 if (GET_CODE (body
) == ADDR_VEC
)
13579 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
13580 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
13581 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
13583 return get_attr_length (insn
);
13586 /* If *X is a symbolic constant that refers to the constant pool, add
13587 the constant to POOL and rewrite *X to use the constant's label. */
13590 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
13592 rtx base
, offset
, label
;
13594 split_const (*x
, &base
, &offset
);
13595 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
13597 label
= mips16_add_constant (pool
, get_pool_constant (base
),
13598 get_pool_mode (base
));
13599 base
= gen_rtx_LABEL_REF (Pmode
, label
);
13600 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
13604 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13605 INSN is the instruction we're rewriting and POOL points to the current
13607 struct mips16_rewrite_pool_refs_info
{
13609 struct mips16_constant_pool
*pool
;
13612 /* Rewrite *X so that constant pool references refer to the constant's
13613 label instead. DATA points to a mips16_rewrite_pool_refs_info
13617 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
13619 struct mips16_rewrite_pool_refs_info
*info
=
13620 (struct mips16_rewrite_pool_refs_info
*) data
;
13622 if (force_to_mem_operand (*x
, Pmode
))
13624 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
13625 validate_change (info
->insn
, x
, mem
, false);
13630 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
13634 if (TARGET_MIPS16_TEXT_LOADS
)
13635 mips16_rewrite_pool_constant (info
->pool
, x
);
13637 return GET_CODE (*x
) == CONST
? -1 : 0;
13640 /* Return whether CFG is used in mips_reorg. */
13643 mips_cfg_in_reorg (void)
13645 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
13646 || TARGET_RELAX_PIC_CALLS
);
13649 /* Build MIPS16 constant pools. */
13652 mips16_lay_out_constants (void)
13654 struct mips16_constant_pool pool
;
13655 struct mips16_rewrite_pool_refs_info info
;
13658 if (!TARGET_MIPS16_PCREL_LOADS
)
13661 if (mips_cfg_in_reorg ())
13662 split_all_insns ();
13664 split_all_insns_noflow ();
13666 memset (&pool
, 0, sizeof (pool
));
13667 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13669 /* Rewrite constant pool references in INSN. */
13670 if (USEFUL_INSN_P (insn
))
13674 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
13677 pool
.insn_address
+= mips16_insn_length (insn
);
13679 if (pool
.first
!= NULL
)
13681 /* If there are no natural barriers between the first user of
13682 the pool and the highest acceptable address, we'll need to
13683 create a new instruction to jump around the constant pool.
13684 In the worst case, this instruction will be 4 bytes long.
13686 If it's too late to do this transformation after INSN,
13687 do it immediately before INSN. */
13688 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
13692 label
= gen_label_rtx ();
13694 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
13695 JUMP_LABEL (jump
) = label
;
13696 LABEL_NUSES (label
) = 1;
13697 barrier
= emit_barrier_after (jump
);
13699 emit_label_after (label
, barrier
);
13700 pool
.insn_address
+= 4;
13703 /* See whether the constant pool is now out of range of the first
13704 user. If so, output the constants after the previous barrier.
13705 Note that any instructions between BARRIER and INSN (inclusive)
13706 will use negative offsets to refer to the pool. */
13707 if (pool
.insn_address
> pool
.highest_address
)
13709 mips16_emit_constants (pool
.first
, barrier
);
13713 else if (BARRIER_P (insn
))
13717 mips16_emit_constants (pool
.first
, get_last_insn ());
13720 /* Return true if it is worth r10k_simplify_address's while replacing
13721 an address with X. We are looking for constants, and for addresses
13722 at a known offset from the incoming stack pointer. */
13725 r10k_simplified_address_p (rtx x
)
13727 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
13729 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
13732 /* X is an expression that appears in INSN. Try to use the UD chains
13733 to simplify it, returning the simplified form on success and the
13734 original form otherwise. Replace the incoming value of $sp with
13735 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13738 r10k_simplify_address (rtx x
, rtx insn
)
13740 rtx newx
, op0
, op1
, set
, def_insn
, note
;
13742 struct df_link
*defs
;
13747 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13748 if (op0
!= XEXP (x
, 0))
13749 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
13750 op0
, GET_MODE (XEXP (x
, 0)));
13752 else if (BINARY_P (x
))
13754 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13755 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
13756 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
13757 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
13759 else if (GET_CODE (x
) == LO_SUM
)
13761 /* LO_SUMs can be offset from HIGHs, if we know they won't
13762 overflow. See mips_classify_address for the rationale behind
13764 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13765 if (GET_CODE (op0
) == HIGH
)
13766 newx
= XEXP (x
, 1);
13768 else if (REG_P (x
))
13770 /* Uses are recorded by regno_reg_rtx, not X itself. */
13771 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
13773 defs
= DF_REF_CHAIN (use
);
13775 /* Require a single definition. */
13776 if (defs
&& defs
->next
== NULL
)
13779 if (DF_REF_IS_ARTIFICIAL (def
))
13781 /* Replace the incoming value of $sp with
13782 virtual_incoming_args_rtx. */
13783 if (x
== stack_pointer_rtx
13784 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
13785 newx
= virtual_incoming_args_rtx
;
13787 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
13790 /* Make sure that DEF_INSN is a single set of REG. */
13791 def_insn
= DF_REF_INSN (def
);
13792 if (NONJUMP_INSN_P (def_insn
))
13794 set
= single_set (def_insn
);
13795 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
13797 /* Prefer to use notes, since the def-use chains
13798 are often shorter. */
13799 note
= find_reg_equal_equiv_note (def_insn
);
13801 newx
= XEXP (note
, 0);
13803 newx
= SET_SRC (set
);
13804 newx
= r10k_simplify_address (newx
, def_insn
);
13810 if (newx
&& r10k_simplified_address_p (newx
))
13815 /* Return true if ADDRESS is known to be an uncached address
13816 on R10K systems. */
13819 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
13821 unsigned HOST_WIDE_INT upper
;
13823 /* Check for KSEG1. */
13824 if (address
+ 0x60000000 < 0x20000000)
13827 /* Check for uncached XKPHYS addresses. */
13828 if (Pmode
== DImode
)
13830 upper
= (address
>> 40) & 0xf9ffff;
13831 if (upper
== 0x900000 || upper
== 0xb80000)
13837 /* Return true if we can prove that an access to address X in instruction
13838 INSN would be safe from R10K speculation. This X is a general
13839 expression; it might not be a legitimate address. */
13842 r10k_safe_address_p (rtx x
, rtx insn
)
13845 HOST_WIDE_INT offset_val
;
13847 x
= r10k_simplify_address (x
, insn
);
13849 /* Check for references to the stack frame. It doesn't really matter
13850 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13851 allows us to assume that accesses to any part of the eventual frame
13852 is safe from speculation at any point in the function. */
13853 mips_split_plus (x
, &base
, &offset_val
);
13854 if (base
== virtual_incoming_args_rtx
13855 && offset_val
>= -cfun
->machine
->frame
.total_size
13856 && offset_val
< cfun
->machine
->frame
.args_size
)
13859 /* Check for uncached addresses. */
13860 if (CONST_INT_P (x
))
13861 return r10k_uncached_address_p (INTVAL (x
));
13863 /* Check for accesses to a static object. */
13864 split_const (x
, &base
, &offset
);
13865 return offset_within_block_p (base
, INTVAL (offset
));
13868 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13869 an in-range access to an automatic variable, or to an object with
13870 a link-time-constant address. */
13873 r10k_safe_mem_expr_p (tree expr
, rtx offset
)
13875 if (expr
== NULL_TREE
13876 || offset
== NULL_RTX
13877 || !CONST_INT_P (offset
)
13878 || INTVAL (offset
) < 0
13879 || INTVAL (offset
) >= int_size_in_bytes (TREE_TYPE (expr
)))
13882 while (TREE_CODE (expr
) == COMPONENT_REF
)
13884 expr
= TREE_OPERAND (expr
, 0);
13885 if (expr
== NULL_TREE
)
13889 return DECL_P (expr
);
13892 /* A for_each_rtx callback for which DATA points to the instruction
13893 containing *X. Stop the search if we find a MEM that is not safe
13894 from R10K speculation. */
13897 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
13905 if (r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
13908 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
13914 /* A note_stores callback for which DATA points to an instruction pointer.
13915 If *DATA is nonnull, make it null if it X contains a MEM that is not
13916 safe from R10K speculation. */
13919 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13924 insn_ptr
= (rtx
*) data
;
13925 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
13926 *insn_ptr
= NULL_RTX
;
13929 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13930 Return nonzero if the call is not to a declared function. */
13933 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13942 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
13948 /* Return true if instruction INSN needs to be protected by an R10K
13952 r10k_needs_protection_p (rtx insn
)
13955 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
13957 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
13959 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
13960 return insn
== NULL_RTX
;
13963 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
13966 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13967 edge is unconditional. */
13970 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
13975 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
13976 if (!single_succ_p (e
->src
)
13977 || !TEST_BIT (protected_bbs
, e
->src
->index
)
13978 || (e
->flags
& EDGE_COMPLEX
) != 0)
13983 /* Implement -mr10k-cache-barrier= for the current function. */
13986 r10k_insert_cache_barriers (void)
13988 int *rev_post_order
;
13991 sbitmap protected_bbs
;
13992 rtx insn
, end
, unprotected_region
;
13996 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14000 /* Calculate dominators. */
14001 calculate_dominance_info (CDI_DOMINATORS
);
14003 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14004 X is protected by a cache barrier. */
14005 protected_bbs
= sbitmap_alloc (last_basic_block
);
14006 sbitmap_zero (protected_bbs
);
14008 /* Iterate over the basic blocks in reverse post-order. */
14009 rev_post_order
= XNEWVEC (int, last_basic_block
);
14010 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
14011 for (i
= 0; i
< n
; i
++)
14013 bb
= BASIC_BLOCK (rev_post_order
[i
]);
14015 /* If this block is only reached by unconditional edges, and if the
14016 source of every edge is protected, the beginning of the block is
14018 if (r10k_protected_bb_p (bb
, protected_bbs
))
14019 unprotected_region
= NULL_RTX
;
14021 unprotected_region
= pc_rtx
;
14022 end
= NEXT_INSN (BB_END (bb
));
14024 /* UNPROTECTED_REGION is:
14026 - null if we are processing a protected region,
14027 - pc_rtx if we are processing an unprotected region but have
14028 not yet found the first instruction in it
14029 - the first instruction in an unprotected region otherwise. */
14030 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
14032 if (unprotected_region
&& USEFUL_INSN_P (insn
))
14034 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
14035 /* This CACHE instruction protects the following code. */
14036 unprotected_region
= NULL_RTX
;
14039 /* See if INSN is the first instruction in this
14040 unprotected region. */
14041 if (unprotected_region
== pc_rtx
)
14042 unprotected_region
= insn
;
14044 /* See if INSN needs to be protected. If so,
14045 we must insert a cache barrier somewhere between
14046 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14047 clear which position is better performance-wise,
14048 but as a tie-breaker, we assume that it is better
14049 to allow delay slots to be back-filled where
14050 possible, and that it is better not to insert
14051 barriers in the middle of already-scheduled code.
14052 We therefore insert the barrier at the beginning
14054 if (r10k_needs_protection_p (insn
))
14056 emit_insn_before (gen_r10k_cache_barrier (),
14057 unprotected_region
);
14058 unprotected_region
= NULL_RTX
;
14064 /* The called function is not required to protect the exit path.
14065 The code that follows a call is therefore unprotected. */
14066 unprotected_region
= pc_rtx
;
14069 /* Record whether the end of this block is protected. */
14070 if (unprotected_region
== NULL_RTX
)
14071 SET_BIT (protected_bbs
, bb
->index
);
14073 XDELETEVEC (rev_post_order
);
14075 sbitmap_free (protected_bbs
);
14077 free_dominance_info (CDI_DOMINATORS
);
14080 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14081 otherwise. If INSN has two call rtx, then store the second one in
14085 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
14090 if (!CALL_P (insn
))
14093 x
= PATTERN (insn
);
14094 if (GET_CODE (x
) == PARALLEL
)
14096 /* Calls returning complex values have two CALL rtx. Look for the second
14097 one here, and return it via the SECOND_CALL arg. */
14098 x2
= XVECEXP (x
, 0, 1);
14099 if (GET_CODE (x2
) == SET
)
14101 if (GET_CODE (x2
) == CALL
)
14104 x
= XVECEXP (x
, 0, 0);
14106 if (GET_CODE (x
) == SET
)
14108 gcc_assert (GET_CODE (x
) == CALL
);
14113 /* REG is set in DEF. See if the definition is one of the ways we load a
14114 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
14115 it is return the symbol reference of the function, otherwise return
14119 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
)
14123 if (DF_REF_IS_ARTIFICIAL (def
))
14126 def_insn
= DF_REF_INSN (def
);
14127 set
= single_set (def_insn
);
14128 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
14130 rtx note
, src
, symbol
;
14132 /* First, look at REG_EQUAL/EQUIV notes. */
14133 note
= find_reg_equal_equiv_note (def_insn
);
14134 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
14135 return XEXP (note
, 0);
14137 /* For %call16 references we don't have REG_EQUAL. */
14138 src
= SET_SRC (set
);
14139 symbol
= mips_strip_unspec_call (src
);
14142 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14146 /* Follow simple register copies. */
14148 return mips_find_pic_call_symbol (def_insn
, src
);
14154 /* Find the definition of the use of REG in INSN. See if the definition is
14155 one of the ways we load a register with a symbol address for a
14156 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14157 the function, otherwise return NULL_RTX. */
14160 mips_find_pic_call_symbol (rtx insn
, rtx reg
)
14163 struct df_link
*defs
;
14166 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
14169 defs
= DF_REF_CHAIN (use
);
14172 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
);
14176 /* If we have more than one definition, they need to be identical. */
14177 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
14181 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
);
14182 if (!rtx_equal_p (symbol
, other
))
14189 /* Replace the args_size operand of the call expression CALL with the
14190 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14193 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
14197 args_size
= XEXP (call
, 1);
14198 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
14199 gen_rtvec (2, args_size
, symbol
),
14203 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14204 if instead of the arg_size argument it contains the call attributes. If
14205 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14206 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14210 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
14212 rtx args_size
, symbol
;
14214 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
14217 args_size
= operands
[args_size_opno
];
14218 if (GET_CODE (args_size
) != UNSPEC
)
14220 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
14222 symbol
= XVECEXP (args_size
, 0, 1);
14223 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14225 operands
[args_size_opno
] = symbol
;
14229 /* Use DF to annotate PIC indirect calls with the function symbol they
14233 mips_annotate_pic_calls (void)
14239 FOR_BB_INSNS (bb
, insn
)
14241 rtx call
, reg
, symbol
, second_call
;
14244 call
= mips_call_expr_from_insn (insn
, &second_call
);
14247 gcc_assert (MEM_P (XEXP (call
, 0)));
14248 reg
= XEXP (XEXP (call
, 0), 0);
14252 symbol
= mips_find_pic_call_symbol (insn
, reg
);
14255 mips_annotate_pic_call_expr (call
, symbol
);
14257 mips_annotate_pic_call_expr (second_call
, symbol
);
14262 /* A temporary variable used by for_each_rtx callbacks, etc. */
14263 static rtx mips_sim_insn
;
14265 /* A structure representing the state of the processor pipeline.
14266 Used by the mips_sim_* family of functions. */
14268 /* The maximum number of instructions that can be issued in a cycle.
14269 (Caches mips_issue_rate.) */
14270 unsigned int issue_rate
;
14272 /* The current simulation time. */
14275 /* How many more instructions can be issued in the current cycle. */
14276 unsigned int insns_left
;
14278 /* LAST_SET[X].INSN is the last instruction to set register X.
14279 LAST_SET[X].TIME is the time at which that instruction was issued.
14280 INSN is null if no instruction has yet set register X. */
14284 } last_set
[FIRST_PSEUDO_REGISTER
];
14286 /* The pipeline's current DFA state. */
14290 /* Reset STATE to the initial simulation state. */
14293 mips_sim_reset (struct mips_sim
*state
)
14296 state
->insns_left
= state
->issue_rate
;
14297 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
14298 state_reset (state
->dfa_state
);
14301 /* Initialize STATE before its first use. DFA_STATE points to an
14302 allocated but uninitialized DFA state. */
14305 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
14307 state
->issue_rate
= mips_issue_rate ();
14308 state
->dfa_state
= dfa_state
;
14309 mips_sim_reset (state
);
14312 /* Advance STATE by one clock cycle. */
14315 mips_sim_next_cycle (struct mips_sim
*state
)
14318 state
->insns_left
= state
->issue_rate
;
14319 state_transition (state
->dfa_state
, 0);
14322 /* Advance simulation state STATE until instruction INSN can read
14326 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
14328 unsigned int regno
, end_regno
;
14330 end_regno
= END_REGNO (reg
);
14331 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
14332 if (state
->last_set
[regno
].insn
!= 0)
14336 t
= (state
->last_set
[regno
].time
14337 + insn_latency (state
->last_set
[regno
].insn
, insn
));
14338 while (state
->time
< t
)
14339 mips_sim_next_cycle (state
);
14343 /* A for_each_rtx callback. If *X is a register, advance simulation state
14344 DATA until mips_sim_insn can read the register's value. */
14347 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
14350 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
14354 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14357 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
14359 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
14362 /* Advance simulation state STATE until all of INSN's register
14363 dependencies are satisfied. */
14366 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
14368 mips_sim_insn
= insn
;
14369 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
14372 /* Advance simulation state STATE until the units required by
14373 instruction INSN are available. */
14376 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
14380 tmp_state
= alloca (state_size ());
14381 while (state
->insns_left
== 0
14382 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
14383 state_transition (tmp_state
, insn
) >= 0))
14384 mips_sim_next_cycle (state
);
14387 /* Advance simulation state STATE until INSN is ready to issue. */
14390 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
14392 mips_sim_wait_regs (state
, insn
);
14393 mips_sim_wait_units (state
, insn
);
14396 /* mips_sim_insn has just set X. Update the LAST_SET array
14397 in simulation state DATA. */
14400 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
14402 struct mips_sim
*state
;
14404 state
= (struct mips_sim
*) data
;
14407 unsigned int regno
, end_regno
;
14409 end_regno
= END_REGNO (x
);
14410 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
14412 state
->last_set
[regno
].insn
= mips_sim_insn
;
14413 state
->last_set
[regno
].time
= state
->time
;
14418 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14419 can issue immediately (i.e., that mips_sim_wait_insn has already
14423 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
14425 state_transition (state
->dfa_state
, insn
);
14426 state
->insns_left
--;
14428 mips_sim_insn
= insn
;
14429 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
14432 /* Simulate issuing a NOP in state STATE. */
14435 mips_sim_issue_nop (struct mips_sim
*state
)
14437 if (state
->insns_left
== 0)
14438 mips_sim_next_cycle (state
);
14439 state
->insns_left
--;
14442 /* Update simulation state STATE so that it's ready to accept the instruction
14443 after INSN. INSN should be part of the main rtl chain, not a member of a
14447 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
14449 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14451 mips_sim_issue_nop (state
);
14453 switch (GET_CODE (SEQ_BEGIN (insn
)))
14457 /* We can't predict the processor state after a call or label. */
14458 mips_sim_reset (state
);
14462 /* The delay slots of branch likely instructions are only executed
14463 when the branch is taken. Therefore, if the caller has simulated
14464 the delay slot instruction, STATE does not really reflect the state
14465 of the pipeline for the instruction after the delay slot. Also,
14466 branch likely instructions tend to incur a penalty when not taken,
14467 so there will probably be an extra delay between the branch and
14468 the instruction after the delay slot. */
14469 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
14470 mips_sim_reset (state
);
14478 /* The VR4130 pipeline issues aligned pairs of instructions together,
14479 but it stalls the second instruction if it depends on the first.
14480 In order to cut down the amount of logic required, this dependence
14481 check is not based on a full instruction decode. Instead, any non-SPECIAL
14482 instruction is assumed to modify the register specified by bits 20-16
14483 (which is usually the "rt" field).
14485 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14486 input, so we can end up with a false dependence between the branch
14487 and its delay slot. If this situation occurs in instruction INSN,
14488 try to avoid it by swapping rs and rt. */
14491 vr4130_avoid_branch_rt_conflict (rtx insn
)
14495 first
= SEQ_BEGIN (insn
);
14496 second
= SEQ_END (insn
);
14498 && NONJUMP_INSN_P (second
)
14499 && GET_CODE (PATTERN (first
)) == SET
14500 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
14501 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
14503 /* Check for the right kind of condition. */
14504 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
14505 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
14506 && REG_P (XEXP (cond
, 0))
14507 && REG_P (XEXP (cond
, 1))
14508 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
14509 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
14511 /* SECOND mentions the rt register but not the rs register. */
14512 rtx tmp
= XEXP (cond
, 0);
14513 XEXP (cond
, 0) = XEXP (cond
, 1);
14514 XEXP (cond
, 1) = tmp
;
14519 /* Implement -mvr4130-align. Go through each basic block and simulate the
14520 processor pipeline. If we find that a pair of instructions could execute
14521 in parallel, and the first of those instructions is not 8-byte aligned,
14522 insert a nop to make it aligned. */
14525 vr4130_align_insns (void)
14527 struct mips_sim state
;
14528 rtx insn
, subinsn
, last
, last2
, next
;
14533 /* LAST is the last instruction before INSN to have a nonzero length.
14534 LAST2 is the last such instruction before LAST. */
14538 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14541 mips_sim_init (&state
, alloca (state_size ()));
14542 for (insn
= get_insns (); insn
!= 0; insn
= next
)
14544 unsigned int length
;
14546 next
= NEXT_INSN (insn
);
14548 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14549 This isn't really related to the alignment pass, but we do it on
14550 the fly to avoid a separate instruction walk. */
14551 vr4130_avoid_branch_rt_conflict (insn
);
14553 if (USEFUL_INSN_P (insn
))
14554 FOR_EACH_SUBINSN (subinsn
, insn
)
14556 mips_sim_wait_insn (&state
, subinsn
);
14558 /* If we want this instruction to issue in parallel with the
14559 previous one, make sure that the previous instruction is
14560 aligned. There are several reasons why this isn't worthwhile
14561 when the second instruction is a call:
14563 - Calls are less likely to be performance critical,
14564 - There's a good chance that the delay slot can execute
14565 in parallel with the call.
14566 - The return address would then be unaligned.
14568 In general, if we're going to insert a nop between instructions
14569 X and Y, it's better to insert it immediately after X. That
14570 way, if the nop makes Y aligned, it will also align any labels
14571 between X and Y. */
14572 if (state
.insns_left
!= state
.issue_rate
14573 && !CALL_P (subinsn
))
14575 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
14577 /* SUBINSN is the first instruction in INSN and INSN is
14578 aligned. We want to align the previous instruction
14579 instead, so insert a nop between LAST2 and LAST.
14581 Note that LAST could be either a single instruction
14582 or a branch with a delay slot. In the latter case,
14583 LAST, like INSN, is already aligned, but the delay
14584 slot must have some extra delay that stops it from
14585 issuing at the same time as the branch. We therefore
14586 insert a nop before the branch in order to align its
14588 emit_insn_after (gen_nop (), last2
);
14591 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
14593 /* SUBINSN is the delay slot of INSN, but INSN is
14594 currently unaligned. Insert a nop between
14595 LAST and INSN to align it. */
14596 emit_insn_after (gen_nop (), last
);
14600 mips_sim_issue_insn (&state
, subinsn
);
14602 mips_sim_finish_insn (&state
, insn
);
14604 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14605 length
= get_attr_length (insn
);
14608 /* If the instruction is an asm statement or multi-instruction
14609 mips.md patern, the length is only an estimate. Insert an
14610 8 byte alignment after it so that the following instructions
14611 can be handled correctly. */
14612 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
14613 && (recog_memoized (insn
) < 0 || length
>= 8))
14615 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
14616 next
= NEXT_INSN (next
);
14617 mips_sim_next_cycle (&state
);
14620 else if (length
& 4)
14621 aligned_p
= !aligned_p
;
14626 /* See whether INSN is an aligned label. */
14627 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
14633 /* This structure records that the current function has a LO_SUM
14634 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14635 the largest offset applied to BASE by all such LO_SUMs. */
14636 struct mips_lo_sum_offset
{
14638 HOST_WIDE_INT offset
;
14641 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14644 mips_hash_base (rtx base
)
14646 int do_not_record_p
;
14648 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
14651 /* Hash-table callbacks for mips_lo_sum_offsets. */
14654 mips_lo_sum_offset_hash (const void *entry
)
14656 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
14660 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
14662 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
14663 (const_rtx
) value
);
14666 /* Look up symbolic constant X in HTAB, which is a hash table of
14667 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14668 paired with a recorded LO_SUM, otherwise record X in the table. */
14671 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
14675 struct mips_lo_sum_offset
*entry
;
14677 /* Split X into a base and offset. */
14678 split_const (x
, &base
, &offset
);
14679 if (UNSPEC_ADDRESS_P (base
))
14680 base
= UNSPEC_ADDRESS (base
);
14682 /* Look up the base in the hash table. */
14683 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
14687 entry
= (struct mips_lo_sum_offset
*) *slot
;
14688 if (option
== INSERT
)
14692 entry
= XNEW (struct mips_lo_sum_offset
);
14693 entry
->base
= base
;
14694 entry
->offset
= INTVAL (offset
);
14699 if (INTVAL (offset
) > entry
->offset
)
14700 entry
->offset
= INTVAL (offset
);
14703 return INTVAL (offset
) <= entry
->offset
;
14706 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14707 Record every LO_SUM in *LOC. */
14710 mips_record_lo_sum (rtx
*loc
, void *data
)
14712 if (GET_CODE (*loc
) == LO_SUM
)
14713 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
14717 /* Return true if INSN is a SET of an orphaned high-part relocation.
14718 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14719 LO_SUMs in the current function. */
14722 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
14724 enum mips_symbol_type type
;
14727 set
= single_set (insn
);
14730 /* Check for %his. */
14732 if (GET_CODE (x
) == HIGH
14733 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
14734 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
14736 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14737 if (GET_CODE (x
) == UNSPEC
14738 && XINT (x
, 1) == UNSPEC_LOAD_GOT
14739 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
14740 SYMBOL_CONTEXT_LEA
, &type
)
14741 && type
== SYMBOL_GOTOFF_PAGE
)
14742 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
14747 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14748 INSN and a previous instruction, avoid it by inserting nops after
14751 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14752 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14753 before using the value of that register. *HILO_DELAY counts the
14754 number of instructions since the last hilo hazard (that is,
14755 the number of instructions since the last MFLO or MFHI).
14757 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14758 for the next instruction.
14760 LO_REG is an rtx for the LO register, used in dependence checking. */
14763 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
14764 rtx
*delayed_reg
, rtx lo_reg
)
14769 pattern
= PATTERN (insn
);
14771 /* Do not put the whole function in .set noreorder if it contains
14772 an asm statement. We don't know whether there will be hazards
14773 between the asm statement and the gcc-generated code. */
14774 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
14775 cfun
->machine
->all_noreorder_p
= false;
14777 /* Ignore zero-length instructions (barriers and the like). */
14778 ninsns
= get_attr_length (insn
) / 4;
14782 /* Work out how many nops are needed. Note that we only care about
14783 registers that are explicitly mentioned in the instruction's pattern.
14784 It doesn't matter that calls use the argument registers or that they
14785 clobber hi and lo. */
14786 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
14787 nops
= 2 - *hilo_delay
;
14788 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
14793 /* Insert the nops between this instruction and the previous one.
14794 Each new nop takes us further from the last hilo hazard. */
14795 *hilo_delay
+= nops
;
14797 emit_insn_after (gen_hazard_nop (), after
);
14799 /* Set up the state for the next instruction. */
14800 *hilo_delay
+= ninsns
;
14802 if (INSN_CODE (insn
) >= 0)
14803 switch (get_attr_hazard (insn
))
14813 set
= single_set (insn
);
14815 *delayed_reg
= SET_DEST (set
);
14820 /* Go through the instruction stream and insert nops where necessary.
14821 Also delete any high-part relocations whose partnering low parts
14822 are now all dead. See if the whole function can then be put into
14823 .set noreorder and .set nomacro. */
14826 mips_reorg_process_insns (void)
14828 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
14832 /* Force all instructions to be split into their final form. */
14833 split_all_insns_noflow ();
14835 /* Recalculate instruction lengths without taking nops into account. */
14836 cfun
->machine
->ignore_hazard_length_p
= true;
14837 shorten_branches (get_insns ());
14839 cfun
->machine
->all_noreorder_p
= true;
14841 /* We don't track MIPS16 PC-relative offsets closely enough to make
14842 a good job of "set .noreorder" code in MIPS16 mode. */
14844 cfun
->machine
->all_noreorder_p
= false;
14846 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14847 if (!TARGET_EXPLICIT_RELOCS
)
14848 cfun
->machine
->all_noreorder_p
= false;
14850 /* Profiled functions can't be all noreorder because the profiler
14851 support uses assembler macros. */
14853 cfun
->machine
->all_noreorder_p
= false;
14855 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14856 we rely on the assembler to work around some errata. */
14857 if (TARGET_FIX_VR4120
)
14858 cfun
->machine
->all_noreorder_p
= false;
14860 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14861 MFHI instructions. Note that we avoid using MFLO and MFHI if
14862 the VR4130 MACC and DMACC instructions are available instead;
14863 see the *mfhilo_{si,di}_macc patterns. */
14864 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
14865 cfun
->machine
->all_noreorder_p
= false;
14867 htab
= htab_create (37, mips_lo_sum_offset_hash
,
14868 mips_lo_sum_offset_eq
, free
);
14870 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14871 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
14872 FOR_EACH_SUBINSN (subinsn
, insn
)
14873 if (USEFUL_INSN_P (subinsn
))
14874 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
14879 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
14881 /* Make a second pass over the instructions. Delete orphaned
14882 high-part relocations or turn them into NOPs. Avoid hazards
14883 by inserting NOPs. */
14884 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
14886 next_insn
= NEXT_INSN (insn
);
14887 if (USEFUL_INSN_P (insn
))
14889 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
14891 /* If we find an orphaned high-part relocation in a delay
14892 slot, it's easier to turn that instruction into a NOP than
14893 to delete it. The delay slot will be a NOP either way. */
14894 FOR_EACH_SUBINSN (subinsn
, insn
)
14895 if (INSN_P (subinsn
))
14897 if (mips_orphaned_high_part_p (htab
, subinsn
))
14899 PATTERN (subinsn
) = gen_nop ();
14900 INSN_CODE (subinsn
) = CODE_FOR_nop
;
14902 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
14903 &delayed_reg
, lo_reg
);
14909 /* INSN is a single instruction. Delete it if it's an
14910 orphaned high-part relocation. */
14911 if (mips_orphaned_high_part_p (htab
, insn
))
14912 delete_insn (insn
);
14913 /* Also delete cache barriers if the last instruction
14914 was an annulled branch. INSN will not be speculatively
14916 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
14918 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
14919 delete_insn (insn
);
14922 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
14923 &delayed_reg
, lo_reg
);
14930 htab_delete (htab
);
14933 /* If we are using a GOT, but have not decided to use a global pointer yet,
14934 see whether we need one to implement long branches. Convert the ghost
14935 global-pointer instructions into real ones if so. */
14938 mips_expand_ghost_gp_insns (void)
14943 /* Quick exit if we already know that we will or won't need a
14945 if (!TARGET_USE_GOT
14946 || cfun
->machine
->global_pointer
== INVALID_REGNUM
14947 || mips_must_initialize_gp_p ())
14950 shorten_branches (get_insns ());
14952 /* Look for a branch that is longer than normal. The normal length for
14953 non-MIPS16 branches is 8, because the length includes the delay slot.
14954 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14955 but they have no delay slot. */
14956 normal_length
= (TARGET_MIPS16
? 4 : 8);
14957 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14959 && USEFUL_INSN_P (insn
)
14960 && get_attr_length (insn
) > normal_length
)
14963 if (insn
== NULL_RTX
)
14966 /* We've now established that we need $gp. */
14967 cfun
->machine
->must_initialize_gp_p
= true;
14968 split_all_insns_noflow ();
14973 /* Subroutine of mips_reorg to manage passes that require DF. */
14976 mips_df_reorg (void)
14978 /* Create def-use chains. */
14979 df_set_flags (DF_EQ_NOTES
);
14980 df_chain_add_problem (DF_UD_CHAIN
);
14983 if (TARGET_RELAX_PIC_CALLS
)
14984 mips_annotate_pic_calls ();
14986 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
14987 r10k_insert_cache_barriers ();
14989 df_finish_pass (false);
14992 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
14997 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
14998 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
14999 to date if the CFG is available. */
15000 if (mips_cfg_in_reorg ())
15001 compute_bb_for_insn ();
15002 mips16_lay_out_constants ();
15003 if (mips_cfg_in_reorg ())
15006 free_bb_for_insn ();
15009 if (optimize
> 0 && flag_delayed_branch
)
15010 dbr_schedule (get_insns ());
15011 mips_reorg_process_insns ();
15013 && TARGET_EXPLICIT_RELOCS
15015 && TARGET_VR4130_ALIGN
)
15016 vr4130_align_insns ();
15017 if (mips_expand_ghost_gp_insns ())
15018 /* The expansion could invalidate some of the VR4130 alignment
15019 optimizations, but this should be an extremely rare case anyhow. */
15020 mips_reorg_process_insns ();
15023 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15024 in order to avoid duplicating too much logic from elsewhere. */
15027 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
15028 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
15031 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
15032 bool use_sibcall_p
;
15034 /* Pretend to be a post-reload pass while generating rtl. */
15035 reload_completed
= 1;
15037 /* Mark the end of the (empty) prologue. */
15038 emit_note (NOTE_INSN_PROLOGUE_END
);
15040 /* Determine if we can use a sibcall to call FUNCTION directly. */
15041 fnaddr
= XEXP (DECL_RTL (function
), 0);
15042 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
15043 && const_call_insn_operand (fnaddr
, Pmode
));
15045 /* Determine if we need to load FNADDR from the GOT. */
15047 && (mips_got_symbol_type_p
15048 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
15050 /* Pick a global pointer. Use a call-clobbered register if
15051 TARGET_CALL_SAVED_GP. */
15052 cfun
->machine
->global_pointer
15053 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
15054 cfun
->machine
->must_initialize_gp_p
= true;
15055 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
15057 /* Set up the global pointer for n32 or n64 abicalls. */
15058 mips_emit_loadgp ();
15061 /* We need two temporary registers in some cases. */
15062 temp1
= gen_rtx_REG (Pmode
, 2);
15063 temp2
= gen_rtx_REG (Pmode
, 3);
15065 /* Find out which register contains the "this" pointer. */
15066 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
15067 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
15069 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
15071 /* Add DELTA to THIS_RTX. */
15074 rtx offset
= GEN_INT (delta
);
15075 if (!SMALL_OPERAND (delta
))
15077 mips_emit_move (temp1
, offset
);
15080 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
15083 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15084 if (vcall_offset
!= 0)
15088 /* Set TEMP1 to *THIS_RTX. */
15089 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
15091 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15092 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
15094 /* Load the offset and add it to THIS_RTX. */
15095 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
15096 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
15099 /* Jump to the target function. Use a sibcall if direct jumps are
15100 allowed, otherwise load the address into a register first. */
15103 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
15104 SIBLING_CALL_P (insn
) = 1;
15108 /* This is messy. GAS treats "la $25,foo" as part of a call
15109 sequence and may allow a global "foo" to be lazily bound.
15110 The general move patterns therefore reject this combination.
15112 In this context, lazy binding would actually be OK
15113 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15114 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15115 We must therefore load the address via a temporary
15116 register if mips_dangerous_for_la25_p.
15118 If we jump to the temporary register rather than $25,
15119 the assembler can use the move insn to fill the jump's
15122 We can use the same technique for MIPS16 code, where $25
15123 is not a valid JR register. */
15124 if (TARGET_USE_PIC_FN_ADDR_REG
15126 && !mips_dangerous_for_la25_p (fnaddr
))
15127 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
15128 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
15130 if (TARGET_USE_PIC_FN_ADDR_REG
15131 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
15132 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
15133 emit_jump_insn (gen_indirect_jump (temp1
));
15136 /* Run just enough of rest_of_compilation. This sequence was
15137 "borrowed" from alpha.c. */
15138 insn
= get_insns ();
15139 insn_locators_alloc ();
15140 split_all_insns_noflow ();
15141 mips16_lay_out_constants ();
15142 shorten_branches (insn
);
15143 final_start_function (insn
, file
, 1);
15144 final (insn
, file
, 1);
15145 final_end_function ();
15147 /* Clean up the vars set above. Note that final_end_function resets
15148 the global pointer for us. */
15149 reload_completed
= 0;
15152 /* The last argument passed to mips_set_mips16_mode, or negative if the
15153 function hasn't been called yet.
15155 There are two copies of this information. One is saved and restored
15156 by the PCH process while the other is specific to this compiler
15157 invocation. The information calculated by mips_set_mips16_mode
15158 is invalid unless the two variables are the same. */
15159 static int was_mips16_p
= -1;
15160 static GTY(()) int was_mips16_pch_p
= -1;
15162 /* Set up the target-dependent global state so that it matches the
15163 current function's ISA mode. */
15166 mips_set_mips16_mode (int mips16_p
)
15168 if (mips16_p
== was_mips16_p
15169 && mips16_p
== was_mips16_pch_p
)
15172 /* Restore base settings of various flags. */
15173 target_flags
= mips_base_target_flags
;
15174 flag_schedule_insns
= mips_base_schedule_insns
;
15175 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
15176 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
15177 align_loops
= mips_base_align_loops
;
15178 align_jumps
= mips_base_align_jumps
;
15179 align_functions
= mips_base_align_functions
;
15183 /* Switch to MIPS16 mode. */
15184 target_flags
|= MASK_MIPS16
;
15186 /* Don't run the scheduler before reload, since it tends to
15187 increase register pressure. */
15188 flag_schedule_insns
= 0;
15190 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15191 the whole function to be in a single section. */
15192 flag_reorder_blocks_and_partition
= 0;
15194 /* Don't move loop invariants, because it tends to increase
15195 register pressure. It also introduces an extra move in cases
15196 where the constant is the first operand in a two-operand binary
15197 instruction, or when it forms a register argument to a functon
15199 flag_move_loop_invariants
= 0;
15201 target_flags
|= MASK_EXPLICIT_RELOCS
;
15203 /* Experiments suggest we get the best overall section-anchor
15204 results from using the range of an unextended LW or SW. Code
15205 that makes heavy use of byte or short accesses can do better
15206 with ranges of 0...31 and 0...63 respectively, but most code is
15207 sensitive to the range of LW and SW instead. */
15208 targetm
.min_anchor_offset
= 0;
15209 targetm
.max_anchor_offset
= 127;
15211 targetm
.const_anchor
= 0;
15213 /* MIPS16 has no BAL instruction. */
15214 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
15216 if (flag_pic
&& !TARGET_OLDABI
)
15217 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15220 sorry ("MIPS16 -mxgot code");
15222 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
15223 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15227 /* Switch to normal (non-MIPS16) mode. */
15228 target_flags
&= ~MASK_MIPS16
;
15230 /* Provide default values for align_* for 64-bit targets. */
15233 if (align_loops
== 0)
15235 if (align_jumps
== 0)
15237 if (align_functions
== 0)
15238 align_functions
= 8;
15241 targetm
.min_anchor_offset
= -32768;
15242 targetm
.max_anchor_offset
= 32767;
15244 targetm
.const_anchor
= 0x8000;
15247 /* (Re)initialize MIPS target internals for new ISA. */
15248 mips_init_relocs ();
15252 if (!mips16_globals
)
15253 mips16_globals
= save_target_globals ();
15255 restore_target_globals (mips16_globals
);
15258 restore_target_globals (&default_target_globals
);
15260 was_mips16_p
= mips16_p
;
15261 was_mips16_pch_p
= mips16_p
;
15264 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15265 function should use the MIPS16 ISA and switch modes accordingly. */
15268 mips_set_current_function (tree fndecl
)
15270 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
15273 /* Allocate a chunk of memory for per-function machine-dependent data. */
15275 static struct machine_function
*
15276 mips_init_machine_status (void)
15278 return ggc_alloc_cleared_machine_function ();
15281 /* Return the processor associated with the given ISA level, or null
15282 if the ISA isn't valid. */
15284 static const struct mips_cpu_info
*
15285 mips_cpu_info_from_isa (int isa
)
15289 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15290 if (mips_cpu_info_table
[i
].isa
== isa
)
15291 return mips_cpu_info_table
+ i
;
15296 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15297 with a final "000" replaced by "k". Ignore case.
15299 Note: this function is shared between GCC and GAS. */
15302 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15304 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15305 given
++, canonical
++;
15307 return ((*given
== 0 && *canonical
== 0)
15308 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15311 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15312 CPU name. We've traditionally allowed a lot of variation here.
15314 Note: this function is shared between GCC and GAS. */
15317 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15319 /* First see if the name matches exactly, or with a final "000"
15320 turned into "k". */
15321 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15324 /* If not, try comparing based on numerical designation alone.
15325 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15326 if (TOLOWER (*given
) == 'r')
15328 if (!ISDIGIT (*given
))
15331 /* Skip over some well-known prefixes in the canonical name,
15332 hoping to find a number there too. */
15333 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15335 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15337 else if (TOLOWER (canonical
[0]) == 'r')
15340 return mips_strict_matching_cpu_name_p (canonical
, given
);
15343 /* Return the mips_cpu_info entry for the processor or ISA given
15344 by CPU_STRING. Return null if the string isn't recognized.
15346 A similar function exists in GAS. */
15348 static const struct mips_cpu_info
*
15349 mips_parse_cpu (const char *cpu_string
)
15354 /* In the past, we allowed upper-case CPU names, but it doesn't
15355 work well with the multilib machinery. */
15356 for (s
= cpu_string
; *s
!= 0; s
++)
15359 warning (0, "CPU names must be lower case");
15363 /* 'from-abi' selects the most compatible architecture for the given
15364 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15365 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15367 if (strcasecmp (cpu_string
, "from-abi") == 0)
15368 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
15369 : ABI_NEEDS_64BIT_REGS
? 3
15370 : (TARGET_64BIT
? 3 : 1));
15372 /* 'default' has traditionally been a no-op. Probably not very useful. */
15373 if (strcasecmp (cpu_string
, "default") == 0)
15376 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15377 if (mips_matching_cpu_name_p (mips_cpu_info_table
[i
].name
, cpu_string
))
15378 return mips_cpu_info_table
+ i
;
15383 /* Set up globals to generate code for the ISA or processor
15384 described by INFO. */
15387 mips_set_architecture (const struct mips_cpu_info
*info
)
15391 mips_arch_info
= info
;
15392 mips_arch
= info
->cpu
;
15393 mips_isa
= info
->isa
;
15397 /* Likewise for tuning. */
15400 mips_set_tune (const struct mips_cpu_info
*info
)
15404 mips_tune_info
= info
;
15405 mips_tune
= info
->cpu
;
15409 /* Implement TARGET_HANDLE_OPTION. */
15412 mips_handle_option (size_t code
, const char *arg
, int value
)
15417 g_switch_value
= value
;
15418 g_switch_set
= true;
15422 if (strcmp (arg
, "32") == 0)
15424 else if (strcmp (arg
, "o64") == 0)
15425 mips_abi
= ABI_O64
;
15426 else if (strcmp (arg
, "n32") == 0)
15427 mips_abi
= ABI_N32
;
15428 else if (strcmp (arg
, "64") == 0)
15430 else if (strcmp (arg
, "eabi") == 0)
15431 mips_abi
= ABI_EABI
;
15438 return mips_parse_cpu (arg
) != 0;
15441 mips_isa_option_info
= mips_parse_cpu (ACONCAT (("mips", arg
, NULL
)));
15442 return mips_isa_option_info
!= 0;
15444 case OPT_mno_flush_func
:
15445 mips_cache_flush_func
= NULL
;
15448 case OPT_mcode_readable_
:
15449 if (strcmp (arg
, "yes") == 0)
15450 mips_code_readable
= CODE_READABLE_YES
;
15451 else if (strcmp (arg
, "pcrel") == 0)
15452 mips_code_readable
= CODE_READABLE_PCREL
;
15453 else if (strcmp (arg
, "no") == 0)
15454 mips_code_readable
= CODE_READABLE_NO
;
15459 case OPT_mr10k_cache_barrier_
:
15460 if (strcmp (arg
, "load-store") == 0)
15461 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_LOAD_STORE
;
15462 else if (strcmp (arg
, "store") == 0)
15463 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_STORE
;
15464 else if (strcmp (arg
, "none") == 0)
15465 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
15475 /* Implement TARGET_OPTION_OVERRIDE. */
15478 mips_option_override (void)
15480 int i
, start
, regno
, mode
;
15482 /* Process flags as though we were generating non-MIPS16 code. */
15483 mips_base_mips16
= TARGET_MIPS16
;
15484 target_flags
&= ~MASK_MIPS16
;
15486 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15487 SUBTARGET_OVERRIDE_OPTIONS
;
15490 /* -mno-float overrides -mhard-float and -msoft-float. */
15491 if (TARGET_NO_FLOAT
)
15493 target_flags
|= MASK_SOFT_FLOAT_ABI
;
15494 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
15497 if (TARGET_FLIP_MIPS16
)
15498 TARGET_INTERLINK_MIPS16
= 1;
15500 /* Set the small data limit. */
15501 mips_small_data_threshold
= (g_switch_set
15503 : MIPS_DEFAULT_GVALUE
);
15505 /* The following code determines the architecture and register size.
15506 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15507 The GAS and GCC code should be kept in sync as much as possible. */
15509 if (mips_arch_string
!= 0)
15510 mips_set_architecture (mips_parse_cpu (mips_arch_string
));
15512 if (mips_isa_option_info
!= 0)
15514 if (mips_arch_info
== 0)
15515 mips_set_architecture (mips_isa_option_info
);
15516 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
15517 error ("%<-%s%> conflicts with the other architecture options, "
15518 "which specify a %s processor",
15519 mips_isa_option_info
->name
,
15520 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
15523 if (mips_arch_info
== 0)
15525 #ifdef MIPS_CPU_STRING_DEFAULT
15526 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT
));
15528 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
15532 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
15533 error ("%<-march=%s%> is not compatible with the selected ABI",
15534 mips_arch_info
->name
);
15536 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15537 if (mips_tune_string
!= 0)
15538 mips_set_tune (mips_parse_cpu (mips_tune_string
));
15540 if (mips_tune_info
== 0)
15541 mips_set_tune (mips_arch_info
);
15543 if ((target_flags_explicit
& MASK_64BIT
) != 0)
15545 /* The user specified the size of the integer registers. Make sure
15546 it agrees with the ABI and ISA. */
15547 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
15548 error ("%<-mgp64%> used with a 32-bit processor");
15549 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
15550 error ("%<-mgp32%> used with a 64-bit ABI");
15551 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
15552 error ("%<-mgp64%> used with a 32-bit ABI");
15556 /* Infer the integer register size from the ABI and processor.
15557 Restrict ourselves to 32-bit registers if that's all the
15558 processor has, or if the ABI cannot handle 64-bit registers. */
15559 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
15560 target_flags
&= ~MASK_64BIT
;
15562 target_flags
|= MASK_64BIT
;
15565 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
15567 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
15568 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15569 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
15570 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15571 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
15573 if (!ISA_HAS_MXHC1
)
15574 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15575 " the target supports the mfhc1 and mthc1 instructions");
15576 else if (mips_abi
!= ABI_32
)
15577 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15583 /* -msingle-float selects 32-bit float registers. Otherwise the
15584 float registers should be the same size as the integer ones. */
15585 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
15586 target_flags
|= MASK_FLOAT64
;
15588 target_flags
&= ~MASK_FLOAT64
;
15591 /* End of code shared with GAS. */
15593 /* If no -mlong* option was given, infer it from the other options. */
15594 if ((target_flags_explicit
& MASK_LONG64
) == 0)
15596 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
15597 target_flags
|= MASK_LONG64
;
15599 target_flags
&= ~MASK_LONG64
;
15602 if (!TARGET_OLDABI
)
15603 flag_pcc_struct_return
= 0;
15605 /* Decide which rtx_costs structure to use. */
15607 mips_cost
= &mips_rtx_cost_optimize_size
;
15609 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
15611 /* If the user hasn't specified a branch cost, use the processor's
15613 if (mips_branch_cost
== 0)
15614 mips_branch_cost
= mips_cost
->branch_cost
;
15616 /* If neither -mbranch-likely nor -mno-branch-likely was given
15617 on the command line, set MASK_BRANCHLIKELY based on the target
15618 architecture and tuning flags. Annulled delay slots are a
15619 size win, so we only consider the processor-specific tuning
15620 for !optimize_size. */
15621 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
15623 if (ISA_HAS_BRANCHLIKELY
15625 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
15626 target_flags
|= MASK_BRANCHLIKELY
;
15628 target_flags
&= ~MASK_BRANCHLIKELY
;
15630 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
15631 warning (0, "the %qs architecture does not support branch-likely"
15632 " instructions", mips_arch_info
->name
);
15634 /* The effect of -mabicalls isn't defined for the EABI. */
15635 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
15637 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15638 target_flags
&= ~MASK_ABICALLS
;
15641 if (TARGET_ABICALLS_PIC2
)
15642 /* We need to set flag_pic for executables as well as DSOs
15643 because we may reference symbols that are not defined in
15644 the final executable. (MIPS does not use things like
15645 copy relocs, for example.)
15647 There is a body of code that uses __PIC__ to distinguish
15648 between -mabicalls and -mno-abicalls code. The non-__PIC__
15649 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15650 long as any indirect jumps use $25. */
15653 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15654 faster code, but at the expense of more nops. Enable it at -O3 and
15656 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
15657 target_flags
|= MASK_VR4130_ALIGN
;
15659 /* Prefer a call to memcpy over inline code when optimizing for size,
15660 though see MOVE_RATIO in mips.h. */
15661 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
15662 target_flags
|= MASK_MEMCPY
;
15664 /* If we have a nonzero small-data limit, check that the -mgpopt
15665 setting is consistent with the other target flags. */
15666 if (mips_small_data_threshold
> 0)
15670 if (!TARGET_EXPLICIT_RELOCS
)
15671 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15673 TARGET_LOCAL_SDATA
= false;
15674 TARGET_EXTERN_SDATA
= false;
15678 if (TARGET_VXWORKS_RTP
)
15679 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15681 if (TARGET_ABICALLS
)
15682 warning (0, "cannot use small-data accesses for %qs",
15687 #ifdef MIPS_TFMODE_FORMAT
15688 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
15691 /* Make sure that the user didn't turn off paired single support when
15692 MIPS-3D support is requested. */
15694 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
15695 && !TARGET_PAIRED_SINGLE_FLOAT
)
15696 error ("%<-mips3d%> requires %<-mpaired-single%>");
15698 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15700 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
15702 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15703 and TARGET_HARD_FLOAT_ABI are both true. */
15704 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
15705 error ("%qs must be used with %qs",
15706 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
15707 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
15709 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15711 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
15712 warning (0, "the %qs architecture does not support paired-single"
15713 " instructions", mips_arch_info
->name
);
15715 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
15716 && !TARGET_CACHE_BUILTIN
)
15718 error ("%qs requires a target that provides the %qs instruction",
15719 "-mr10k-cache-barrier", "cache");
15720 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
15723 /* If TARGET_DSPR2, enable MASK_DSP. */
15725 target_flags
|= MASK_DSP
;
15727 /* .eh_frame addresses should be the same width as a C pointer.
15728 Most MIPS ABIs support only one pointer size, so the assembler
15729 will usually know exactly how big an .eh_frame address is.
15731 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15732 originally defined to use 64-bit pointers (i.e. it is LP64), and
15733 this is still the default mode. However, we also support an n32-like
15734 ILP32 mode, which is selected by -mlong32. The problem is that the
15735 assembler has traditionally not had an -mlong option, so it has
15736 traditionally not known whether we're using the ILP32 or LP64 form.
15738 As it happens, gas versions up to and including 2.19 use _32-bit_
15739 addresses for EABI64 .cfi_* directives. This is wrong for the
15740 default LP64 mode, so we can't use the directives by default.
15741 Moreover, since gas's current behavior is at odds with gcc's
15742 default behavior, it seems unwise to rely on future versions
15743 of gas behaving the same way. We therefore avoid using .cfi
15744 directives for -mlong32 as well. */
15745 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
15746 flag_dwarf2_cfi_asm
= 0;
15748 /* .cfi_* directives generate a read-only section, so fall back on
15749 manual .eh_frame creation if we need the section to be writable. */
15750 if (TARGET_WRITABLE_EH_FRAME
)
15751 flag_dwarf2_cfi_asm
= 0;
15753 mips_init_print_operand_punct ();
15755 /* Set up array to map GCC register number to debug register number.
15756 Ignore the special purpose register numbers. */
15758 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
15760 mips_dbx_regno
[i
] = INVALID_REGNUM
;
15761 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
15762 mips_dwarf_regno
[i
] = i
;
15764 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
15767 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
15768 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
15769 mips_dbx_regno
[i
] = i
+ start
;
15771 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
15772 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
15773 mips_dbx_regno
[i
] = i
+ start
;
15775 /* Accumulator debug registers use big-endian ordering. */
15776 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
15777 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
15778 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
15779 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
15780 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
15782 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
15783 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
15786 /* Set up mips_hard_regno_mode_ok. */
15787 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
15788 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
15789 mips_hard_regno_mode_ok
[mode
][regno
]
15790 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
15792 /* Function to allocate machine-dependent function status. */
15793 init_machine_status
= &mips_init_machine_status
;
15795 /* Default to working around R4000 errata only if the processor
15796 was selected explicitly. */
15797 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
15798 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
15799 target_flags
|= MASK_FIX_R4000
;
15801 /* Default to working around R4400 errata only if the processor
15802 was selected explicitly. */
15803 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
15804 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
15805 target_flags
|= MASK_FIX_R4400
;
15807 /* Default to working around R10000 errata only if the processor
15808 was selected explicitly. */
15809 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
15810 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r10000"))
15811 target_flags
|= MASK_FIX_R10000
;
15813 /* Make sure that branch-likely instructions available when using
15814 -mfix-r10000. The instructions are not available if either:
15816 1. -mno-branch-likely was passed.
15817 2. The selected ISA does not support branch-likely and
15818 the command line does not include -mbranch-likely. */
15819 if (TARGET_FIX_R10000
15820 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
15821 ? !ISA_HAS_BRANCHLIKELY
15822 : !TARGET_BRANCHLIKELY
))
15823 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15825 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
15827 warning (0, "the %qs architecture does not support the synci "
15828 "instruction", mips_arch_info
->name
);
15829 target_flags
&= ~MASK_SYNCI
;
15832 /* Only optimize PIC indirect calls if they are actually required. */
15833 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
15834 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
15836 /* Save base state of options. */
15837 mips_base_target_flags
= target_flags
;
15838 mips_base_schedule_insns
= flag_schedule_insns
;
15839 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
15840 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
15841 mips_base_align_loops
= align_loops
;
15842 mips_base_align_jumps
= align_jumps
;
15843 mips_base_align_functions
= align_functions
;
15845 /* Now select the ISA mode.
15847 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15848 MIPS16 mode afterwards if need be. */
15849 mips_set_mips16_mode (false);
15852 /* Swap the register information for registers I and I + 1, which
15853 currently have the wrong endianness. Note that the registers'
15854 fixedness and call-clobberedness might have been set on the
15858 mips_swap_registers (unsigned int i
)
15863 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15864 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15866 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
15867 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
15868 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
15869 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
15875 /* Implement CONDITIONAL_REGISTER_USAGE. */
15878 mips_conditional_register_usage (void)
15883 /* These DSP control register fields are global. */
15884 global_regs
[CCDSP_PO_REGNUM
] = 1;
15885 global_regs
[CCDSP_SC_REGNUM
] = 1;
15891 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
15892 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15894 if (!TARGET_HARD_FLOAT
)
15898 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
15899 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15900 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
15901 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15903 else if (! ISA_HAS_8CC
)
15907 /* We only have a single condition-code register. We implement
15908 this by fixing all the condition-code registers and generating
15909 RTL that refers directly to ST_REG_FIRST. */
15910 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
15911 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15913 /* In MIPS16 mode, we permit the $t temporary registers to be used
15914 for reload. We prohibit the unused $s registers, since they
15915 are call-saved, and saving them via a MIPS16 register would
15916 probably waste more time than just reloading the value. */
15919 fixed_regs
[18] = call_used_regs
[18] = 1;
15920 fixed_regs
[19] = call_used_regs
[19] = 1;
15921 fixed_regs
[20] = call_used_regs
[20] = 1;
15922 fixed_regs
[21] = call_used_regs
[21] = 1;
15923 fixed_regs
[22] = call_used_regs
[22] = 1;
15924 fixed_regs
[23] = call_used_regs
[23] = 1;
15925 fixed_regs
[26] = call_used_regs
[26] = 1;
15926 fixed_regs
[27] = call_used_regs
[27] = 1;
15927 fixed_regs
[30] = call_used_regs
[30] = 1;
15929 /* $f20-$f23 are call-clobbered for n64. */
15930 if (mips_abi
== ABI_64
)
15933 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
15934 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
15936 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15938 if (mips_abi
== ABI_N32
)
15941 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
15942 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
15944 /* Make sure that double-register accumulator values are correctly
15945 ordered for the current endianness. */
15946 if (TARGET_LITTLE_ENDIAN
)
15948 unsigned int regno
;
15950 mips_swap_registers (MD_REG_FIRST
);
15951 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
15952 mips_swap_registers (regno
);
15956 /* Initialize vector TARGET to VALS. */
15959 mips_expand_vector_init (rtx target
, rtx vals
)
15961 enum machine_mode mode
;
15962 enum machine_mode inner
;
15963 unsigned int i
, n_elts
;
15966 mode
= GET_MODE (target
);
15967 inner
= GET_MODE_INNER (mode
);
15968 n_elts
= GET_MODE_NUNITS (mode
);
15970 gcc_assert (VECTOR_MODE_P (mode
));
15972 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
15973 for (i
= 0; i
< n_elts
; i
++)
15974 emit_move_insn (adjust_address_nv (mem
, inner
, i
* GET_MODE_SIZE (inner
)),
15975 XVECEXP (vals
, 0, i
));
15977 emit_move_insn (target
, mem
);
15980 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15981 other registers for instructions for which it is possible. This
15982 encourages the compiler to use CMP in cases where an XOR would
15983 require some register shuffling. */
15986 mips_order_regs_for_local_alloc (void)
15990 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
15991 reg_alloc_order
[i
] = i
;
15995 /* It really doesn't matter where we put register 0, since it is
15996 a fixed register anyhow. */
15997 reg_alloc_order
[0] = 24;
15998 reg_alloc_order
[24] = 0;
16002 /* Implement EH_USES. */
16005 mips_eh_uses (unsigned int regno
)
16007 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
16009 /* We need to force certain registers to be live in order to handle
16010 PIC long branches correctly. See mips_must_initialize_gp_p for
16012 if (mips_cfun_has_cprestore_slot_p ())
16014 if (regno
== CPRESTORE_SLOT_REGNUM
)
16019 if (cfun
->machine
->global_pointer
== regno
)
16027 /* Implement EPILOGUE_USES. */
16030 mips_epilogue_uses (unsigned int regno
)
16032 /* Say that the epilogue uses the return address register. Note that
16033 in the case of sibcalls, the values "used by the epilogue" are
16034 considered live at the start of the called function. */
16035 if (regno
== RETURN_ADDR_REGNUM
)
16038 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16039 See the comment above load_call<mode> for details. */
16040 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
16043 /* An interrupt handler must preserve some registers that are
16044 ordinarily call-clobbered. */
16045 if (cfun
->machine
->interrupt_handler_p
16046 && mips_interrupt_extra_call_saved_reg_p (regno
))
16052 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16055 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
16057 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
16060 /* Return true if INSN needs to be wrapped in ".set noat".
16061 INSN has NOPERANDS operands, stored in OPVEC. */
16064 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
16068 if (recog_memoized (insn
) >= 0)
16069 for (i
= 0; i
< noperands
; i
++)
16070 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
16075 /* Implement FINAL_PRESCAN_INSN. */
16078 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
16080 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
16081 mips_push_asm_switch (&mips_noat
);
16084 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16087 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
16088 rtx
*opvec
, int noperands
)
16090 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
16091 mips_pop_asm_switch (&mips_noat
);
16094 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16095 EXT_CODE is the code of the extension used. Return NULL if widening
16096 multiplication shouldn't be used. */
16099 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
16103 signed_p
= ext_code
== SIGN_EXTEND
;
16106 /* Don't use widening multiplication with MULT when we have DMUL. Even
16107 with the extension of its input operands DMUL is faster. Note that
16108 the extension is not needed for signed multiplication. In order to
16109 ensure that we always remove the redundant sign-extension in this
16110 case we still expand mulsidi3 for DMUL. */
16112 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
16113 if (TARGET_FIX_R4000
)
16115 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
16119 if (TARGET_FIX_R4000
)
16120 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
16122 return signed_p
? gen_mips_mult
: gen_mips_multu
;
16123 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
16127 /* Return the size in bytes of the trampoline code, padded to
16128 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16129 function address immediately follow. */
16132 mips_trampoline_code_size (void)
16134 if (TARGET_USE_PIC_FN_ADDR_REG
)
16136 else if (ptr_mode
== DImode
)
16138 else if (ISA_HAS_LOAD_DELAY
)
16144 /* Implement TARGET_TRAMPOLINE_INIT. */
16147 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
16149 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
16152 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
16154 /* Work out the offsets of the pointers from the start of the
16155 trampoline code. */
16156 end_addr_offset
= mips_trampoline_code_size ();
16157 static_chain_offset
= end_addr_offset
;
16158 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
16160 /* Get pointers to the beginning and end of the code block. */
16161 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
16162 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
16164 #define OP(X) gen_int_mode (X, SImode)
16166 /* Build up the code in TRAMPOLINE. */
16168 if (TARGET_USE_PIC_FN_ADDR_REG
)
16170 /* $25 contains the address of the trampoline. Emit code of the form:
16172 l[wd] $1, target_function_offset($25)
16173 l[wd] $static_chain, static_chain_offset($25)
16176 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
16177 target_function_offset
,
16178 PIC_FUNCTION_ADDR_REGNUM
));
16179 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16180 static_chain_offset
,
16181 PIC_FUNCTION_ADDR_REGNUM
));
16182 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
16183 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
16185 else if (ptr_mode
== DImode
)
16187 /* It's too cumbersome to create the full 64-bit address, so let's
16193 1: l[wd] $25, target_function_offset - 12($31)
16194 l[wd] $static_chain, static_chain_offset - 12($31)
16198 where 12 is the offset of "1:" from the start of the code block. */
16199 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
16200 trampoline
[i
++] = OP (MIPS_BAL (1));
16201 trampoline
[i
++] = OP (MIPS_NOP
);
16202 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16203 target_function_offset
- 12,
16204 RETURN_ADDR_REGNUM
));
16205 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16206 static_chain_offset
- 12,
16207 RETURN_ADDR_REGNUM
));
16208 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16209 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
16213 /* If the target has load delays, emit:
16215 lui $1, %hi(end_addr)
16216 lw $25, %lo(end_addr + ...)($1)
16217 lw $static_chain, %lo(end_addr + ...)($1)
16223 lui $1, %hi(end_addr)
16224 lw $25, %lo(end_addr + ...)($1)
16226 lw $static_chain, %lo(end_addr + ...)($1). */
16228 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16229 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16230 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
16231 NULL
, false, OPTAB_WIDEN
);
16232 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
16233 NULL
, false, OPTAB_WIDEN
);
16234 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
16236 /* Emit the LUI. */
16237 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
16238 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
16239 NULL
, false, OPTAB_WIDEN
);
16241 /* Emit the load of the target function. */
16242 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16243 target_function_offset
- end_addr_offset
,
16245 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16246 NULL
, false, OPTAB_WIDEN
);
16248 /* Emit the JR here, if we can. */
16249 if (!ISA_HAS_LOAD_DELAY
)
16250 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16252 /* Emit the load of the static chain register. */
16253 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16254 static_chain_offset
- end_addr_offset
,
16256 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16257 NULL
, false, OPTAB_WIDEN
);
16259 /* Emit the JR, if we couldn't above. */
16260 if (ISA_HAS_LOAD_DELAY
)
16262 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16263 trampoline
[i
++] = OP (MIPS_NOP
);
16269 /* Copy the trampoline code. Leave any padding uninitialized. */
16270 for (j
= 0; j
< i
; j
++)
16272 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
16273 mips_emit_move (mem
, trampoline
[j
]);
16276 /* Set up the static chain pointer field. */
16277 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
16278 mips_emit_move (mem
, chain_value
);
16280 /* Set up the target function field. */
16281 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
16282 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
16284 /* Flush the code part of the trampoline. */
16285 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
16286 emit_insn (gen_clear_cache (addr
, end_addr
));
16289 /* Implement FUNCTION_PROFILER. */
16291 void mips_function_profiler (FILE *file
)
16294 sorry ("mips16 function profiling");
16295 if (TARGET_LONG_CALLS
)
16297 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16298 if (Pmode
== DImode
)
16299 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
16301 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
16303 mips_push_asm_switch (&mips_noat
);
16304 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
16305 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
16306 /* _mcount treats $2 as the static chain register. */
16307 if (cfun
->static_chain_decl
!= NULL
)
16308 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
16309 reg_names
[STATIC_CHAIN_REGNUM
]);
16310 if (TARGET_MCOUNT_RA_ADDRESS
)
16312 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16313 ra save location. */
16314 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
16315 /* ra not saved, pass zero. */
16316 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
16318 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
16319 Pmode
== DImode
? "dla" : "la", reg_names
[12],
16320 cfun
->machine
->frame
.ra_fp_offset
,
16321 reg_names
[STACK_POINTER_REGNUM
]);
16323 if (!TARGET_NEWABI
)
16325 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16326 TARGET_64BIT
? "dsubu" : "subu",
16327 reg_names
[STACK_POINTER_REGNUM
],
16328 reg_names
[STACK_POINTER_REGNUM
],
16329 Pmode
== DImode
? 16 : 8);
16331 if (TARGET_LONG_CALLS
)
16332 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
16334 fprintf (file
, "\tjal\t_mcount\n");
16335 mips_pop_asm_switch (&mips_noat
);
16336 /* _mcount treats $2 as the static chain register. */
16337 if (cfun
->static_chain_decl
!= NULL
)
16338 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
16342 /* Initialize the GCC target structure. */
16343 #undef TARGET_ASM_ALIGNED_HI_OP
16344 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16345 #undef TARGET_ASM_ALIGNED_SI_OP
16346 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16347 #undef TARGET_ASM_ALIGNED_DI_OP
16348 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16350 #undef TARGET_OPTION_OVERRIDE
16351 #define TARGET_OPTION_OVERRIDE mips_option_override
16353 #undef TARGET_LEGITIMIZE_ADDRESS
16354 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16356 #undef TARGET_ASM_FUNCTION_PROLOGUE
16357 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16358 #undef TARGET_ASM_FUNCTION_EPILOGUE
16359 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16360 #undef TARGET_ASM_SELECT_RTX_SECTION
16361 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16362 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16363 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16365 #undef TARGET_SCHED_INIT
16366 #define TARGET_SCHED_INIT mips_sched_init
16367 #undef TARGET_SCHED_REORDER
16368 #define TARGET_SCHED_REORDER mips_sched_reorder
16369 #undef TARGET_SCHED_REORDER2
16370 #define TARGET_SCHED_REORDER2 mips_sched_reorder
16371 #undef TARGET_SCHED_VARIABLE_ISSUE
16372 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16373 #undef TARGET_SCHED_ADJUST_COST
16374 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16375 #undef TARGET_SCHED_ISSUE_RATE
16376 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16377 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16378 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16379 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16380 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16381 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16382 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16383 mips_multipass_dfa_lookahead
16384 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16385 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16386 mips_small_register_classes_for_mode_p
16388 #undef TARGET_DEFAULT_TARGET_FLAGS
16389 #define TARGET_DEFAULT_TARGET_FLAGS \
16391 | TARGET_CPU_DEFAULT \
16392 | TARGET_ENDIAN_DEFAULT \
16393 | TARGET_FP_EXCEPTIONS_DEFAULT \
16394 | MASK_CHECK_ZERO_DIV \
16396 #undef TARGET_HANDLE_OPTION
16397 #define TARGET_HANDLE_OPTION mips_handle_option
16399 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16400 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16402 #undef TARGET_INSERT_ATTRIBUTES
16403 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16404 #undef TARGET_MERGE_DECL_ATTRIBUTES
16405 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16406 #undef TARGET_SET_CURRENT_FUNCTION
16407 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16409 #undef TARGET_VALID_POINTER_MODE
16410 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16411 #undef TARGET_REGISTER_MOVE_COST
16412 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16413 #undef TARGET_MEMORY_MOVE_COST
16414 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16415 #undef TARGET_RTX_COSTS
16416 #define TARGET_RTX_COSTS mips_rtx_costs
16417 #undef TARGET_ADDRESS_COST
16418 #define TARGET_ADDRESS_COST mips_address_cost
16420 #undef TARGET_IN_SMALL_DATA_P
16421 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16423 #undef TARGET_MACHINE_DEPENDENT_REORG
16424 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16426 #undef TARGET_ASM_FILE_START
16427 #define TARGET_ASM_FILE_START mips_file_start
16428 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16429 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16431 #undef TARGET_INIT_LIBFUNCS
16432 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16434 #undef TARGET_BUILD_BUILTIN_VA_LIST
16435 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16436 #undef TARGET_EXPAND_BUILTIN_VA_START
16437 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16438 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16439 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16441 #undef TARGET_PROMOTE_FUNCTION_MODE
16442 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16443 #undef TARGET_PROMOTE_PROTOTYPES
16444 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16446 #undef TARGET_RETURN_IN_MEMORY
16447 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16448 #undef TARGET_RETURN_IN_MSB
16449 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16451 #undef TARGET_ASM_OUTPUT_MI_THUNK
16452 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16453 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16454 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16456 #undef TARGET_PRINT_OPERAND
16457 #define TARGET_PRINT_OPERAND mips_print_operand
16458 #undef TARGET_PRINT_OPERAND_ADDRESS
16459 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16460 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16461 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16463 #undef TARGET_SETUP_INCOMING_VARARGS
16464 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16465 #undef TARGET_STRICT_ARGUMENT_NAMING
16466 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16467 #undef TARGET_MUST_PASS_IN_STACK
16468 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16469 #undef TARGET_PASS_BY_REFERENCE
16470 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16471 #undef TARGET_CALLEE_COPIES
16472 #define TARGET_CALLEE_COPIES mips_callee_copies
16473 #undef TARGET_ARG_PARTIAL_BYTES
16474 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16475 #undef TARGET_FUNCTION_ARG
16476 #define TARGET_FUNCTION_ARG mips_function_arg
16477 #undef TARGET_FUNCTION_ARG_ADVANCE
16478 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16480 #undef TARGET_MODE_REP_EXTENDED
16481 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16483 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16484 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16486 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16487 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16489 #undef TARGET_INIT_BUILTINS
16490 #define TARGET_INIT_BUILTINS mips_init_builtins
16491 #undef TARGET_EXPAND_BUILTIN
16492 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16494 #undef TARGET_HAVE_TLS
16495 #define TARGET_HAVE_TLS HAVE_AS_TLS
16497 #undef TARGET_CANNOT_FORCE_CONST_MEM
16498 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16500 #undef TARGET_ENCODE_SECTION_INFO
16501 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16503 #undef TARGET_ATTRIBUTE_TABLE
16504 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16505 /* All our function attributes are related to how out-of-line copies should
16506 be compiled or called. They don't in themselves prevent inlining. */
16507 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16508 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16510 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16511 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16513 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16514 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16515 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16516 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16518 #undef TARGET_COMP_TYPE_ATTRIBUTES
16519 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16521 #ifdef HAVE_AS_DTPRELWORD
16522 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16523 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16525 #undef TARGET_DWARF_REGISTER_SPAN
16526 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16528 #undef TARGET_IRA_COVER_CLASSES
16529 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
16531 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16532 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16534 #undef TARGET_LEGITIMATE_ADDRESS_P
16535 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16537 #undef TARGET_FRAME_POINTER_REQUIRED
16538 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16540 #undef TARGET_CAN_ELIMINATE
16541 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16543 #undef TARGET_TRAMPOLINE_INIT
16544 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16546 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16547 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16549 struct gcc_target targetm
= TARGET_INITIALIZER
;
16551 #include "gt-mips.h"