1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
46 #include "hash-table.h"
49 #include "target-def.h"
50 #include "common/common-target.h"
51 #include "langhooks.h"
52 #include "sched-int.h"
56 #include "diagnostic.h"
57 #include "target-globals.h"
59 #include "tree-pass.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
84 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
86 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
87 up to 0x7f8 bytes and can usually save or restore all the registers
88 that we need to save or restore. (Note that we can only use these
89 instructions for o32, for which the stack alignment is 8 bytes.)
91 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
92 RESTORE are not available. We can then use unextended instructions
93 to save and restore registers, and to allocate and deallocate the top
95 #define MIPS_MAX_FIRST_STACK_STEP \
96 (!TARGET_COMPRESSION ? 0x7ff0 \
97 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
98 : TARGET_64BIT ? 0x100 : 0x400)
100 /* True if INSN is a mips.md pattern or asm statement. */
101 /* ??? This test exists through the compiler, perhaps it should be
103 #define USEFUL_INSN_P(INSN) \
104 (NONDEBUG_INSN_P (INSN) \
105 && GET_CODE (PATTERN (INSN)) != USE \
106 && GET_CODE (PATTERN (INSN)) != CLOBBER)
108 /* If INSN is a delayed branch sequence, return the first instruction
109 in the sequence, otherwise return INSN itself. */
110 #define SEQ_BEGIN(INSN) \
111 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
112 ? XVECEXP (PATTERN (INSN), 0, 0) \
115 /* Likewise for the last instruction in a delayed branch sequence. */
116 #define SEQ_END(INSN) \
117 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
118 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
121 /* Execute the following loop body with SUBINSN set to each instruction
122 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
123 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
124 for ((SUBINSN) = SEQ_BEGIN (INSN); \
125 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
126 (SUBINSN) = NEXT_INSN (SUBINSN))
128 /* True if bit BIT is set in VALUE. */
129 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
131 /* Return the opcode for a ptr_mode load of the form:
133 l[wd] DEST, OFFSET(BASE). */
134 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
135 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
140 /* Return the opcode to move register SRC into register DEST. */
141 #define MIPS_MOVE(DEST, SRC) \
142 ((TARGET_64BIT ? 0x2d : 0x21) \
146 /* Return the opcode for:
149 #define MIPS_LUI(DEST, VALUE) \
150 ((0xf << 26) | ((DEST) << 16) | (VALUE))
152 /* Return the opcode to jump to register DEST. */
153 #define MIPS_JR(DEST) \
154 (((DEST) << 21) | 0x8)
156 /* Return the opcode for:
158 bal . + (1 + OFFSET) * 4. */
159 #define MIPS_BAL(OFFSET) \
160 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
162 /* Return the usual opcode for a nop. */
165 /* Classifies an address.
168 A natural register + offset address. The register satisfies
169 mips_valid_base_register_p and the offset is a const_arith_operand.
172 A LO_SUM rtx. The first operand is a valid base register and
173 the second operand is a symbolic address.
176 A signed 16-bit constant address.
179 A constant symbolic address. */
180 enum mips_address_type
{
187 /* Macros to create an enumeration identifier for a function prototype. */
188 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
189 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
190 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
191 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
193 /* Classifies the prototype of a built-in function. */
194 enum mips_function_type
{
195 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
196 #include "config/mips/mips-ftypes.def"
197 #undef DEF_MIPS_FTYPE
201 /* Specifies how a built-in function should be converted into rtl. */
202 enum mips_builtin_type
{
203 /* The function corresponds directly to an .md pattern. The return
204 value is mapped to operand 0 and the arguments are mapped to
205 operands 1 and above. */
208 /* The function corresponds directly to an .md pattern. There is no return
209 value and the arguments are mapped to operands 0 and above. */
210 MIPS_BUILTIN_DIRECT_NO_TARGET
,
212 /* The function corresponds to a comparison instruction followed by
213 a mips_cond_move_tf_ps pattern. The first two arguments are the
214 values to compare and the second two arguments are the vector
215 operands for the movt.ps or movf.ps instruction (in assembly order). */
219 /* The function corresponds to a V2SF comparison instruction. Operand 0
220 of this instruction is the result of the comparison, which has mode
221 CCV2 or CCV4. The function arguments are mapped to operands 1 and
222 above. The function's return value is an SImode boolean that is
223 true under the following conditions:
225 MIPS_BUILTIN_CMP_ANY: one of the registers is true
226 MIPS_BUILTIN_CMP_ALL: all of the registers are true
227 MIPS_BUILTIN_CMP_LOWER: the first register is true
228 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
229 MIPS_BUILTIN_CMP_ANY
,
230 MIPS_BUILTIN_CMP_ALL
,
231 MIPS_BUILTIN_CMP_UPPER
,
232 MIPS_BUILTIN_CMP_LOWER
,
234 /* As above, but the instruction only sets a single $fcc register. */
235 MIPS_BUILTIN_CMP_SINGLE
,
237 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
238 MIPS_BUILTIN_BPOSGE32
241 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
242 #define MIPS_FP_CONDITIONS(MACRO) \
260 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
261 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
262 enum mips_fp_condition
{
263 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
266 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
267 #define STRINGIFY(X) #X
268 static const char *const mips_fp_conditions
[] = {
269 MIPS_FP_CONDITIONS (STRINGIFY
)
272 /* Tuning information that is automatically derived from other sources
273 (such as the scheduler). */
275 /* The architecture and tuning settings that this structure describes. */
279 /* True if this structure describes MIPS16 settings. */
282 /* True if the structure has been initialized. */
285 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
286 when optimizing for speed. */
287 bool fast_mult_zero_zero_p
;
290 /* Information about a function's frame layout. */
291 struct GTY(()) mips_frame_info
{
292 /* The size of the frame in bytes. */
293 HOST_WIDE_INT total_size
;
295 /* The number of bytes allocated to variables. */
296 HOST_WIDE_INT var_size
;
298 /* The number of bytes allocated to outgoing function arguments. */
299 HOST_WIDE_INT args_size
;
301 /* The number of bytes allocated to the .cprestore slot, or 0 if there
303 HOST_WIDE_INT cprestore_size
;
305 /* Bit X is set if the function saves or restores GPR X. */
308 /* Likewise FPR X. */
311 /* Likewise doubleword accumulator X ($acX). */
312 unsigned int acc_mask
;
314 /* The number of GPRs, FPRs, doubleword accumulators and COP0
318 unsigned int num_acc
;
319 unsigned int num_cop0_regs
;
321 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
322 save slots from the top of the frame, or zero if no such slots are
324 HOST_WIDE_INT gp_save_offset
;
325 HOST_WIDE_INT fp_save_offset
;
326 HOST_WIDE_INT acc_save_offset
;
327 HOST_WIDE_INT cop0_save_offset
;
329 /* Likewise, but giving offsets from the bottom of the frame. */
330 HOST_WIDE_INT gp_sp_offset
;
331 HOST_WIDE_INT fp_sp_offset
;
332 HOST_WIDE_INT acc_sp_offset
;
333 HOST_WIDE_INT cop0_sp_offset
;
335 /* Similar, but the value passed to _mcount. */
336 HOST_WIDE_INT ra_fp_offset
;
338 /* The offset of arg_pointer_rtx from the bottom of the frame. */
339 HOST_WIDE_INT arg_pointer_offset
;
341 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
342 HOST_WIDE_INT hard_frame_pointer_offset
;
345 struct GTY(()) machine_function
{
346 /* The next floating-point condition-code register to allocate
347 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
348 unsigned int next_fcc
;
350 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
351 rtx mips16_gp_pseudo_rtx
;
353 /* The number of extra stack bytes taken up by register varargs.
354 This area is allocated by the callee at the very top of the frame. */
357 /* The current frame information, calculated by mips_compute_frame_info. */
358 struct mips_frame_info frame
;
360 /* The register to use as the function's global pointer, or INVALID_REGNUM
361 if the function doesn't need one. */
362 unsigned int global_pointer
;
364 /* How many instructions it takes to load a label into $AT, or 0 if
365 this property hasn't yet been calculated. */
366 unsigned int load_label_num_insns
;
368 /* True if mips_adjust_insn_length should ignore an instruction's
370 bool ignore_hazard_length_p
;
372 /* True if the whole function is suitable for .set noreorder and
374 bool all_noreorder_p
;
376 /* True if the function has "inflexible" and "flexible" references
377 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
378 and mips_cfun_has_flexible_gp_ref_p for details. */
379 bool has_inflexible_gp_insn_p
;
380 bool has_flexible_gp_insn_p
;
382 /* True if the function's prologue must load the global pointer
383 value into pic_offset_table_rtx and store the same value in
384 the function's cprestore slot (if any). Even if this value
385 is currently false, we may decide to set it to true later;
386 see mips_must_initialize_gp_p () for details. */
387 bool must_initialize_gp_p
;
389 /* True if the current function must restore $gp after any potential
390 clobber. This value is only meaningful during the first post-epilogue
391 split_insns pass; see mips_must_initialize_gp_p () for details. */
392 bool must_restore_gp_when_clobbered_p
;
394 /* True if this is an interrupt handler. */
395 bool interrupt_handler_p
;
397 /* True if this is an interrupt handler that uses shadow registers. */
398 bool use_shadow_register_set_p
;
400 /* True if this is an interrupt handler that should keep interrupts
402 bool keep_interrupts_masked_p
;
404 /* True if this is an interrupt handler that should use DERET
406 bool use_debug_exception_return_p
;
409 /* Information about a single argument. */
410 struct mips_arg_info
{
411 /* True if the argument is passed in a floating-point register, or
412 would have been if we hadn't run out of registers. */
415 /* The number of words passed in registers, rounded up. */
416 unsigned int reg_words
;
418 /* For EABI, the offset of the first register from GP_ARG_FIRST or
419 FP_ARG_FIRST. For other ABIs, the offset of the first register from
420 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
421 comment for details).
423 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
425 unsigned int reg_offset
;
427 /* The number of words that must be passed on the stack, rounded up. */
428 unsigned int stack_words
;
430 /* The offset from the start of the stack overflow area of the argument's
431 first stack word. Only meaningful when STACK_WORDS is nonzero. */
432 unsigned int stack_offset
;
435 /* Information about an address described by mips_address_type.
441 REG is the base register and OFFSET is the constant offset.
444 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
445 is the type of symbol it references.
448 SYMBOL_TYPE is the type of symbol that the address references. */
449 struct mips_address_info
{
450 enum mips_address_type type
;
453 enum mips_symbol_type symbol_type
;
456 /* One stage in a constant building sequence. These sequences have
460 A = A CODE[1] VALUE[1]
461 A = A CODE[2] VALUE[2]
464 where A is an accumulator, each CODE[i] is a binary rtl operation
465 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
466 struct mips_integer_op
{
468 unsigned HOST_WIDE_INT value
;
471 /* The largest number of operations needed to load an integer constant.
472 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
473 When the lowest bit is clear, we can try, but reject a sequence with
474 an extra SLL at the end. */
475 #define MIPS_MAX_INTEGER_OPS 7
477 /* Information about a MIPS16e SAVE or RESTORE instruction. */
478 struct mips16e_save_restore_info
{
479 /* The number of argument registers saved by a SAVE instruction.
480 0 for RESTORE instructions. */
483 /* Bit X is set if the instruction saves or restores GPR X. */
486 /* The total number of bytes to allocate. */
490 /* Costs of various operations on the different architectures. */
492 struct mips_rtx_cost_data
494 unsigned short fp_add
;
495 unsigned short fp_mult_sf
;
496 unsigned short fp_mult_df
;
497 unsigned short fp_div_sf
;
498 unsigned short fp_div_df
;
499 unsigned short int_mult_si
;
500 unsigned short int_mult_di
;
501 unsigned short int_div_si
;
502 unsigned short int_div_di
;
503 unsigned short branch_cost
;
504 unsigned short memory_latency
;
507 /* Global variables for machine-dependent things. */
509 /* The -G setting, or the configuration's default small-data limit if
510 no -G option is given. */
511 static unsigned int mips_small_data_threshold
;
513 /* The number of file directives written by mips_output_filename. */
514 int num_source_filenames
;
516 /* The name that appeared in the last .file directive written by
517 mips_output_filename, or "" if mips_output_filename hasn't
518 written anything yet. */
519 const char *current_function_file
= "";
521 /* Arrays that map GCC register numbers to debugger register numbers. */
522 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
523 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
525 /* Information about the current function's epilogue, used only while
528 /* A list of queued REG_CFA_RESTORE notes. */
531 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
533 HOST_WIDE_INT cfa_offset
;
535 /* The offset of the CFA from the stack pointer while restoring
537 HOST_WIDE_INT cfa_restore_sp_offset
;
540 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
541 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
542 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
543 struct mips_asm_switch mips_noat
= { "at", 0 };
545 /* True if we're writing out a branch-likely instruction rather than a
547 static bool mips_branch_likely
;
549 /* The current instruction-set architecture. */
550 enum processor mips_arch
;
551 const struct mips_cpu_info
*mips_arch_info
;
553 /* The processor that we should tune the code for. */
554 enum processor mips_tune
;
555 const struct mips_cpu_info
*mips_tune_info
;
557 /* The ISA level associated with mips_arch. */
560 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
561 static const struct mips_cpu_info
*mips_isa_option_info
;
563 /* Which cost information to use. */
564 static const struct mips_rtx_cost_data
*mips_cost
;
566 /* The ambient target flags, excluding MASK_MIPS16. */
567 static int mips_base_target_flags
;
569 /* The default compression mode. */
570 unsigned int mips_base_compression_flags
;
572 /* The ambient values of other global variables. */
573 static int mips_base_schedule_insns
; /* flag_schedule_insns */
574 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
575 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
576 static int mips_base_align_loops
; /* align_loops */
577 static int mips_base_align_jumps
; /* align_jumps */
578 static int mips_base_align_functions
; /* align_functions */
580 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
581 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
583 /* Index C is true if character C is a valid PRINT_OPERAND punctation
585 static bool mips_print_operand_punct
[256];
587 static GTY (()) int mips_output_filename_first_time
= 1;
589 /* mips_split_p[X] is true if symbols of type X can be split by
590 mips_split_symbol. */
591 bool mips_split_p
[NUM_SYMBOL_TYPES
];
593 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
594 can be split by mips_split_symbol. */
595 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
597 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
598 forced into a PC-relative constant pool. */
599 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
601 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
602 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
603 if they are matched by a special .md file pattern. */
604 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
606 /* Likewise for HIGHs. */
607 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
609 /* Target state for MIPS16. */
610 struct target_globals
*mips16_globals
;
612 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
613 and returned from mips_sched_reorder2. */
614 static int cached_can_issue_more
;
616 /* True if the output uses __mips16_rdhwr. */
617 static bool mips_need_mips16_rdhwr_p
;
619 /* Index R is the smallest register class that contains register R. */
620 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
621 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
622 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
623 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
624 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
625 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
626 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
627 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
628 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
629 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
630 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
631 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
632 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
633 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
634 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
635 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
636 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
637 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
638 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
639 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
640 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
641 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
642 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
643 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
644 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
645 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
646 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
647 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
648 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
649 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
650 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
651 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
652 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
653 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
654 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
655 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
656 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
657 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
658 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
659 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
660 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
661 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
662 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
663 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
664 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
665 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
666 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
667 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
670 /* The value of TARGET_ATTRIBUTE_TABLE. */
671 static const struct attribute_spec mips_attribute_table
[] = {
672 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
674 { "long_call", 0, 0, false, true, true, NULL
, false },
675 { "far", 0, 0, false, true, true, NULL
, false },
676 { "near", 0, 0, false, true, true, NULL
, false },
677 /* We would really like to treat "mips16" and "nomips16" as type
678 attributes, but GCC doesn't provide the hooks we need to support
679 the right conversion rules. As declaration attributes, they affect
680 code generation but don't carry other semantics. */
681 { "mips16", 0, 0, true, false, false, NULL
, false },
682 { "nomips16", 0, 0, true, false, false, NULL
, false },
683 { "micromips", 0, 0, true, false, false, NULL
, false },
684 { "nomicromips", 0, 0, true, false, false, NULL
, false },
685 { "nocompression", 0, 0, true, false, false, NULL
, false },
686 /* Allow functions to be specified as interrupt handlers */
687 { "interrupt", 0, 0, false, true, true, NULL
, false },
688 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
689 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
690 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
691 { NULL
, 0, 0, false, false, false, NULL
, false }
694 /* A table describing all the processors GCC knows about; see
695 mips-cpus.def for details. */
696 static const struct mips_cpu_info mips_cpu_info_table
[] = {
697 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
698 { NAME, CPU, ISA, FLAGS },
699 #include "mips-cpus.def"
703 /* Default costs. If these are used for a processor we should look
704 up the actual costs. */
705 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
706 COSTS_N_INSNS (7), /* fp_mult_sf */ \
707 COSTS_N_INSNS (8), /* fp_mult_df */ \
708 COSTS_N_INSNS (23), /* fp_div_sf */ \
709 COSTS_N_INSNS (36), /* fp_div_df */ \
710 COSTS_N_INSNS (10), /* int_mult_si */ \
711 COSTS_N_INSNS (10), /* int_mult_di */ \
712 COSTS_N_INSNS (69), /* int_div_si */ \
713 COSTS_N_INSNS (69), /* int_div_di */ \
714 2, /* branch_cost */ \
715 4 /* memory_latency */
717 /* Floating-point costs for processors without an FPU. Just assume that
718 all floating-point libcalls are very expensive. */
719 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
720 COSTS_N_INSNS (256), /* fp_mult_sf */ \
721 COSTS_N_INSNS (256), /* fp_mult_df */ \
722 COSTS_N_INSNS (256), /* fp_div_sf */ \
723 COSTS_N_INSNS (256) /* fp_div_df */
725 /* Costs to use when optimizing for size. */
726 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
727 COSTS_N_INSNS (1), /* fp_add */
728 COSTS_N_INSNS (1), /* fp_mult_sf */
729 COSTS_N_INSNS (1), /* fp_mult_df */
730 COSTS_N_INSNS (1), /* fp_div_sf */
731 COSTS_N_INSNS (1), /* fp_div_df */
732 COSTS_N_INSNS (1), /* int_mult_si */
733 COSTS_N_INSNS (1), /* int_mult_di */
734 COSTS_N_INSNS (1), /* int_div_si */
735 COSTS_N_INSNS (1), /* int_div_di */
737 4 /* memory_latency */
740 /* Costs to use when optimizing for speed, indexed by processor. */
741 static const struct mips_rtx_cost_data
742 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
744 COSTS_N_INSNS (2), /* fp_add */
745 COSTS_N_INSNS (4), /* fp_mult_sf */
746 COSTS_N_INSNS (5), /* fp_mult_df */
747 COSTS_N_INSNS (12), /* fp_div_sf */
748 COSTS_N_INSNS (19), /* fp_div_df */
749 COSTS_N_INSNS (12), /* int_mult_si */
750 COSTS_N_INSNS (12), /* int_mult_di */
751 COSTS_N_INSNS (35), /* int_div_si */
752 COSTS_N_INSNS (35), /* int_div_di */
754 4 /* memory_latency */
758 COSTS_N_INSNS (6), /* int_mult_si */
759 COSTS_N_INSNS (6), /* int_mult_di */
760 COSTS_N_INSNS (36), /* int_div_si */
761 COSTS_N_INSNS (36), /* int_div_di */
763 4 /* memory_latency */
767 COSTS_N_INSNS (36), /* int_mult_si */
768 COSTS_N_INSNS (36), /* int_mult_di */
769 COSTS_N_INSNS (37), /* int_div_si */
770 COSTS_N_INSNS (37), /* int_div_di */
772 4 /* memory_latency */
776 COSTS_N_INSNS (4), /* int_mult_si */
777 COSTS_N_INSNS (11), /* int_mult_di */
778 COSTS_N_INSNS (36), /* int_div_si */
779 COSTS_N_INSNS (68), /* int_div_di */
781 4 /* memory_latency */
784 COSTS_N_INSNS (4), /* fp_add */
785 COSTS_N_INSNS (4), /* fp_mult_sf */
786 COSTS_N_INSNS (5), /* fp_mult_df */
787 COSTS_N_INSNS (17), /* fp_div_sf */
788 COSTS_N_INSNS (32), /* fp_div_df */
789 COSTS_N_INSNS (4), /* int_mult_si */
790 COSTS_N_INSNS (11), /* int_mult_di */
791 COSTS_N_INSNS (36), /* int_div_si */
792 COSTS_N_INSNS (68), /* int_div_di */
794 4 /* memory_latency */
797 COSTS_N_INSNS (4), /* fp_add */
798 COSTS_N_INSNS (4), /* fp_mult_sf */
799 COSTS_N_INSNS (5), /* fp_mult_df */
800 COSTS_N_INSNS (17), /* fp_div_sf */
801 COSTS_N_INSNS (32), /* fp_div_df */
802 COSTS_N_INSNS (4), /* int_mult_si */
803 COSTS_N_INSNS (7), /* int_mult_di */
804 COSTS_N_INSNS (42), /* int_div_si */
805 COSTS_N_INSNS (72), /* int_div_di */
807 4 /* memory_latency */
811 COSTS_N_INSNS (5), /* int_mult_si */
812 COSTS_N_INSNS (5), /* int_mult_di */
813 COSTS_N_INSNS (41), /* int_div_si */
814 COSTS_N_INSNS (41), /* int_div_di */
816 4 /* memory_latency */
819 COSTS_N_INSNS (8), /* fp_add */
820 COSTS_N_INSNS (8), /* fp_mult_sf */
821 COSTS_N_INSNS (10), /* fp_mult_df */
822 COSTS_N_INSNS (34), /* fp_div_sf */
823 COSTS_N_INSNS (64), /* fp_div_df */
824 COSTS_N_INSNS (5), /* int_mult_si */
825 COSTS_N_INSNS (5), /* int_mult_di */
826 COSTS_N_INSNS (41), /* int_div_si */
827 COSTS_N_INSNS (41), /* int_div_di */
829 4 /* memory_latency */
832 COSTS_N_INSNS (4), /* fp_add */
833 COSTS_N_INSNS (4), /* fp_mult_sf */
834 COSTS_N_INSNS (5), /* fp_mult_df */
835 COSTS_N_INSNS (17), /* fp_div_sf */
836 COSTS_N_INSNS (32), /* fp_div_df */
837 COSTS_N_INSNS (5), /* int_mult_si */
838 COSTS_N_INSNS (5), /* int_mult_di */
839 COSTS_N_INSNS (41), /* int_div_si */
840 COSTS_N_INSNS (41), /* int_div_di */
842 4 /* memory_latency */
846 COSTS_N_INSNS (5), /* int_mult_si */
847 COSTS_N_INSNS (5), /* int_mult_di */
848 COSTS_N_INSNS (41), /* int_div_si */
849 COSTS_N_INSNS (41), /* int_div_di */
851 4 /* memory_latency */
854 COSTS_N_INSNS (8), /* fp_add */
855 COSTS_N_INSNS (8), /* fp_mult_sf */
856 COSTS_N_INSNS (10), /* fp_mult_df */
857 COSTS_N_INSNS (34), /* fp_div_sf */
858 COSTS_N_INSNS (64), /* fp_div_df */
859 COSTS_N_INSNS (5), /* int_mult_si */
860 COSTS_N_INSNS (5), /* int_mult_di */
861 COSTS_N_INSNS (41), /* int_div_si */
862 COSTS_N_INSNS (41), /* int_div_di */
864 4 /* memory_latency */
867 COSTS_N_INSNS (4), /* fp_add */
868 COSTS_N_INSNS (4), /* fp_mult_sf */
869 COSTS_N_INSNS (5), /* fp_mult_df */
870 COSTS_N_INSNS (17), /* fp_div_sf */
871 COSTS_N_INSNS (32), /* fp_div_df */
872 COSTS_N_INSNS (5), /* int_mult_si */
873 COSTS_N_INSNS (5), /* int_mult_di */
874 COSTS_N_INSNS (41), /* int_div_si */
875 COSTS_N_INSNS (41), /* int_div_di */
877 4 /* memory_latency */
880 COSTS_N_INSNS (6), /* fp_add */
881 COSTS_N_INSNS (6), /* fp_mult_sf */
882 COSTS_N_INSNS (7), /* fp_mult_df */
883 COSTS_N_INSNS (25), /* fp_div_sf */
884 COSTS_N_INSNS (48), /* fp_div_df */
885 COSTS_N_INSNS (5), /* int_mult_si */
886 COSTS_N_INSNS (5), /* int_mult_di */
887 COSTS_N_INSNS (41), /* int_div_si */
888 COSTS_N_INSNS (41), /* int_div_di */
890 4 /* memory_latency */
907 COSTS_N_INSNS (5), /* int_mult_si */
908 COSTS_N_INSNS (5), /* int_mult_di */
909 COSTS_N_INSNS (72), /* int_div_si */
910 COSTS_N_INSNS (72), /* int_div_di */
912 4 /* memory_latency */
917 COSTS_N_INSNS (6), /* int_mult_si */
918 COSTS_N_INSNS (6), /* int_mult_di */
919 COSTS_N_INSNS (18), /* int_div_si */
920 COSTS_N_INSNS (35), /* int_div_di */
922 4 /* memory_latency */
925 COSTS_N_INSNS (2), /* fp_add */
926 COSTS_N_INSNS (4), /* fp_mult_sf */
927 COSTS_N_INSNS (5), /* fp_mult_df */
928 COSTS_N_INSNS (12), /* fp_div_sf */
929 COSTS_N_INSNS (19), /* fp_div_df */
930 COSTS_N_INSNS (2), /* int_mult_si */
931 COSTS_N_INSNS (2), /* int_mult_di */
932 COSTS_N_INSNS (35), /* int_div_si */
933 COSTS_N_INSNS (35), /* int_div_di */
935 4 /* memory_latency */
938 COSTS_N_INSNS (3), /* fp_add */
939 COSTS_N_INSNS (5), /* fp_mult_sf */
940 COSTS_N_INSNS (6), /* fp_mult_df */
941 COSTS_N_INSNS (15), /* fp_div_sf */
942 COSTS_N_INSNS (16), /* fp_div_df */
943 COSTS_N_INSNS (17), /* int_mult_si */
944 COSTS_N_INSNS (17), /* int_mult_di */
945 COSTS_N_INSNS (38), /* int_div_si */
946 COSTS_N_INSNS (38), /* int_div_di */
948 6 /* memory_latency */
951 COSTS_N_INSNS (6), /* fp_add */
952 COSTS_N_INSNS (7), /* fp_mult_sf */
953 COSTS_N_INSNS (8), /* fp_mult_df */
954 COSTS_N_INSNS (23), /* fp_div_sf */
955 COSTS_N_INSNS (36), /* fp_div_df */
956 COSTS_N_INSNS (10), /* int_mult_si */
957 COSTS_N_INSNS (10), /* int_mult_di */
958 COSTS_N_INSNS (69), /* int_div_si */
959 COSTS_N_INSNS (69), /* int_div_di */
961 6 /* memory_latency */
973 /* The only costs that appear to be updated here are
974 integer multiplication. */
976 COSTS_N_INSNS (4), /* int_mult_si */
977 COSTS_N_INSNS (6), /* int_mult_di */
978 COSTS_N_INSNS (69), /* int_div_si */
979 COSTS_N_INSNS (69), /* int_div_di */
981 4 /* memory_latency */
996 COSTS_N_INSNS (6), /* fp_add */
997 COSTS_N_INSNS (4), /* fp_mult_sf */
998 COSTS_N_INSNS (5), /* fp_mult_df */
999 COSTS_N_INSNS (23), /* fp_div_sf */
1000 COSTS_N_INSNS (36), /* fp_div_df */
1001 COSTS_N_INSNS (5), /* int_mult_si */
1002 COSTS_N_INSNS (5), /* int_mult_di */
1003 COSTS_N_INSNS (36), /* int_div_si */
1004 COSTS_N_INSNS (36), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 COSTS_N_INSNS (6), /* fp_add */
1010 COSTS_N_INSNS (5), /* fp_mult_sf */
1011 COSTS_N_INSNS (6), /* fp_mult_df */
1012 COSTS_N_INSNS (30), /* fp_div_sf */
1013 COSTS_N_INSNS (59), /* fp_div_df */
1014 COSTS_N_INSNS (3), /* int_mult_si */
1015 COSTS_N_INSNS (4), /* int_mult_di */
1016 COSTS_N_INSNS (42), /* int_div_si */
1017 COSTS_N_INSNS (74), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1022 COSTS_N_INSNS (6), /* fp_add */
1023 COSTS_N_INSNS (5), /* fp_mult_sf */
1024 COSTS_N_INSNS (6), /* fp_mult_df */
1025 COSTS_N_INSNS (30), /* fp_div_sf */
1026 COSTS_N_INSNS (59), /* fp_div_df */
1027 COSTS_N_INSNS (5), /* int_mult_si */
1028 COSTS_N_INSNS (9), /* int_mult_di */
1029 COSTS_N_INSNS (42), /* int_div_si */
1030 COSTS_N_INSNS (74), /* int_div_di */
1031 1, /* branch_cost */
1032 4 /* memory_latency */
1035 COSTS_N_INSNS (4), /* fp_add */
1036 COSTS_N_INSNS (4), /* fp_mult_sf */
1037 COSTS_N_INSNS (256), /* fp_mult_df */
1038 COSTS_N_INSNS (8), /* fp_div_sf */
1039 COSTS_N_INSNS (256), /* fp_div_df */
1040 COSTS_N_INSNS (4), /* int_mult_si */
1041 COSTS_N_INSNS (256), /* int_mult_di */
1042 COSTS_N_INSNS (37), /* int_div_si */
1043 COSTS_N_INSNS (256), /* int_div_di */
1044 1, /* branch_cost */
1045 4 /* memory_latency */
1048 /* The only costs that are changed here are
1049 integer multiplication. */
1050 COSTS_N_INSNS (6), /* fp_add */
1051 COSTS_N_INSNS (7), /* fp_mult_sf */
1052 COSTS_N_INSNS (8), /* fp_mult_df */
1053 COSTS_N_INSNS (23), /* fp_div_sf */
1054 COSTS_N_INSNS (36), /* fp_div_df */
1055 COSTS_N_INSNS (5), /* int_mult_si */
1056 COSTS_N_INSNS (9), /* int_mult_di */
1057 COSTS_N_INSNS (69), /* int_div_si */
1058 COSTS_N_INSNS (69), /* int_div_di */
1059 1, /* branch_cost */
1060 4 /* memory_latency */
1066 /* The only costs that are changed here are
1067 integer multiplication. */
1068 COSTS_N_INSNS (6), /* fp_add */
1069 COSTS_N_INSNS (7), /* fp_mult_sf */
1070 COSTS_N_INSNS (8), /* fp_mult_df */
1071 COSTS_N_INSNS (23), /* fp_div_sf */
1072 COSTS_N_INSNS (36), /* fp_div_df */
1073 COSTS_N_INSNS (3), /* int_mult_si */
1074 COSTS_N_INSNS (8), /* int_mult_di */
1075 COSTS_N_INSNS (69), /* int_div_si */
1076 COSTS_N_INSNS (69), /* int_div_di */
1077 1, /* branch_cost */
1078 4 /* memory_latency */
1081 COSTS_N_INSNS (2), /* fp_add */
1082 COSTS_N_INSNS (2), /* fp_mult_sf */
1083 COSTS_N_INSNS (2), /* fp_mult_df */
1084 COSTS_N_INSNS (12), /* fp_div_sf */
1085 COSTS_N_INSNS (19), /* fp_div_df */
1086 COSTS_N_INSNS (5), /* int_mult_si */
1087 COSTS_N_INSNS (9), /* int_mult_di */
1088 COSTS_N_INSNS (34), /* int_div_si */
1089 COSTS_N_INSNS (66), /* int_div_di */
1090 1, /* branch_cost */
1091 4 /* memory_latency */
1094 /* These costs are the same as the SB-1A below. */
1095 COSTS_N_INSNS (4), /* fp_add */
1096 COSTS_N_INSNS (4), /* fp_mult_sf */
1097 COSTS_N_INSNS (4), /* fp_mult_df */
1098 COSTS_N_INSNS (24), /* fp_div_sf */
1099 COSTS_N_INSNS (32), /* fp_div_df */
1100 COSTS_N_INSNS (3), /* int_mult_si */
1101 COSTS_N_INSNS (4), /* int_mult_di */
1102 COSTS_N_INSNS (36), /* int_div_si */
1103 COSTS_N_INSNS (68), /* int_div_di */
1104 1, /* branch_cost */
1105 4 /* memory_latency */
1108 /* These costs are the same as the SB-1 above. */
1109 COSTS_N_INSNS (4), /* fp_add */
1110 COSTS_N_INSNS (4), /* fp_mult_sf */
1111 COSTS_N_INSNS (4), /* fp_mult_df */
1112 COSTS_N_INSNS (24), /* fp_div_sf */
1113 COSTS_N_INSNS (32), /* fp_div_df */
1114 COSTS_N_INSNS (3), /* int_mult_si */
1115 COSTS_N_INSNS (4), /* int_mult_di */
1116 COSTS_N_INSNS (36), /* int_div_si */
1117 COSTS_N_INSNS (68), /* int_div_di */
1118 1, /* branch_cost */
1119 4 /* memory_latency */
1126 COSTS_N_INSNS (8), /* int_mult_si */
1127 COSTS_N_INSNS (8), /* int_mult_di */
1128 COSTS_N_INSNS (72), /* int_div_si */
1129 COSTS_N_INSNS (72), /* int_div_di */
1130 1, /* branch_cost */
1131 4 /* memory_latency */
1134 /* These costs are the same as 5KF above. */
1135 COSTS_N_INSNS (4), /* fp_add */
1136 COSTS_N_INSNS (4), /* fp_mult_sf */
1137 COSTS_N_INSNS (5), /* fp_mult_df */
1138 COSTS_N_INSNS (17), /* fp_div_sf */
1139 COSTS_N_INSNS (32), /* fp_div_df */
1140 COSTS_N_INSNS (4), /* int_mult_si */
1141 COSTS_N_INSNS (11), /* int_mult_di */
1142 COSTS_N_INSNS (36), /* int_div_si */
1143 COSTS_N_INSNS (68), /* int_div_di */
1144 1, /* branch_cost */
1145 4 /* memory_latency */
1149 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1150 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1152 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1154 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1155 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1156 struct GTY (()) mflip_mips16_entry
{
1160 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1162 /* Hash table callbacks for mflip_mips16_htab. */
1165 mflip_mips16_htab_hash (const void *entry
)
1167 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1171 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1173 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1174 (const char *) name
) == 0;
1177 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1178 mode, false if it should next add an attribute for the opposite mode. */
1179 static GTY(()) bool mips16_flipper
;
1181 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1182 for -mflip-mips16. Return true if it should use "mips16" and false if
1183 it should use "nomips16". */
1186 mflip_mips16_use_mips16_p (tree decl
)
1188 struct mflip_mips16_entry
*entry
;
1192 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1194 /* Use the opposite of the command-line setting for anonymous decls. */
1195 if (!DECL_NAME (decl
))
1196 return !base_is_mips16
;
1198 if (!mflip_mips16_htab
)
1199 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1200 mflip_mips16_htab_eq
, NULL
);
1202 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1203 hash
= htab_hash_string (name
);
1204 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1205 entry
= (struct mflip_mips16_entry
*) *slot
;
1208 mips16_flipper
= !mips16_flipper
;
1209 entry
= ggc_alloc_mflip_mips16_entry ();
1211 entry
->mips16_p
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1214 return entry
->mips16_p
;
1217 /* Predicates to test for presence of "near" and "far"/"long_call"
1218 attributes on the given TYPE. */
1221 mips_near_type_p (const_tree type
)
1223 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1227 mips_far_type_p (const_tree type
)
1229 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1230 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1234 /* Check if the interrupt attribute is set for a function. */
1237 mips_interrupt_type_p (tree type
)
1239 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1242 /* Check if the attribute to use shadow register set is set for a function. */
1245 mips_use_shadow_register_set_p (tree type
)
1247 return lookup_attribute ("use_shadow_register_set",
1248 TYPE_ATTRIBUTES (type
)) != NULL
;
1251 /* Check if the attribute to keep interrupts masked is set for a function. */
1254 mips_keep_interrupts_masked_p (tree type
)
1256 return lookup_attribute ("keep_interrupts_masked",
1257 TYPE_ATTRIBUTES (type
)) != NULL
;
1260 /* Check if the attribute to use debug exception return is set for
1264 mips_use_debug_exception_return_p (tree type
)
1266 return lookup_attribute ("use_debug_exception_return",
1267 TYPE_ATTRIBUTES (type
)) != NULL
;
1270 /* Return the set of compression modes that are explicitly required
1271 by the attributes in ATTRIBUTES. */
1274 mips_get_compress_on_flags (tree attributes
)
1276 unsigned int flags
= 0;
1278 if (lookup_attribute ("mips16", attributes
) != NULL
)
1279 flags
|= MASK_MIPS16
;
1281 if (lookup_attribute ("micromips", attributes
) != NULL
)
1282 flags
|= MASK_MICROMIPS
;
1287 /* Return the set of compression modes that are explicitly forbidden
1288 by the attributes in ATTRIBUTES. */
1291 mips_get_compress_off_flags (tree attributes
)
1293 unsigned int flags
= 0;
1295 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1296 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1298 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1299 flags
|= MASK_MIPS16
;
1301 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1302 flags
|= MASK_MICROMIPS
;
1307 /* Return the compression mode that should be used for function DECL.
1308 Return the ambient setting if DECL is null. */
1311 mips_get_compress_mode (tree decl
)
1313 unsigned int flags
, force_on
;
1315 flags
= mips_base_compression_flags
;
1318 /* Nested functions must use the same frame pointer as their
1319 parent and must therefore use the same ISA mode. */
1320 tree parent
= decl_function_context (decl
);
1323 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1326 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1331 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1335 mips_get_compress_on_name (unsigned int flags
)
1337 if (flags
== MASK_MIPS16
)
1342 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1346 mips_get_compress_off_name (unsigned int flags
)
1348 if (flags
== MASK_MIPS16
)
1350 if (flags
== MASK_MICROMIPS
)
1351 return "nomicromips";
1352 return "nocompression";
1355 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1358 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1360 /* Disallow mixed near/far attributes. */
1361 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1363 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1368 /* Implement TARGET_INSERT_ATTRIBUTES. */
1371 mips_insert_attributes (tree decl
, tree
*attributes
)
1374 unsigned int compression_flags
, nocompression_flags
;
1376 /* Check for "mips16" and "nomips16" attributes. */
1377 compression_flags
= mips_get_compress_on_flags (*attributes
);
1378 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1380 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1382 if (nocompression_flags
)
1383 error ("%qs attribute only applies to functions",
1384 mips_get_compress_off_name (nocompression_flags
));
1386 if (compression_flags
)
1387 error ("%qs attribute only applies to functions",
1388 mips_get_compress_on_name (nocompression_flags
));
1392 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1393 nocompression_flags
|=
1394 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1396 if (compression_flags
&& nocompression_flags
)
1397 error ("%qE cannot have both %qs and %qs attributes",
1398 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1399 mips_get_compress_off_name (nocompression_flags
));
1401 if (compression_flags
& MASK_MIPS16
1402 && compression_flags
& MASK_MICROMIPS
)
1403 error ("%qE cannot have both %qs and %qs attributes",
1404 DECL_NAME (decl
), "mips16", "micromips");
1406 if (TARGET_FLIP_MIPS16
1407 && !DECL_ARTIFICIAL (decl
)
1408 && compression_flags
== 0
1409 && nocompression_flags
== 0)
1411 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1412 "mips16" attribute, arbitrarily pick one. We must pick the same
1413 setting for duplicate declarations of a function. */
1414 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1415 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1416 name
= "nomicromips";
1417 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1422 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1425 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1429 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1430 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1432 error ("%qE redeclared with conflicting %qs attributes",
1433 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1435 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1436 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1438 error ("%qE redeclared with conflicting %qs attributes",
1439 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1441 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1442 DECL_ATTRIBUTES (newdecl
));
1445 /* Implement TARGET_CAN_INLINE_P. */
1448 mips_can_inline_p (tree caller
, tree callee
)
1450 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1452 return default_target_can_inline_p (caller
, callee
);
1455 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1456 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1459 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1461 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1463 *base_ptr
= XEXP (x
, 0);
1464 *offset_ptr
= INTVAL (XEXP (x
, 1));
1473 static unsigned int mips_build_integer (struct mips_integer_op
*,
1474 unsigned HOST_WIDE_INT
);
1476 /* A subroutine of mips_build_integer, with the same interface.
1477 Assume that the final action in the sequence should be a left shift. */
1480 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1482 unsigned int i
, shift
;
1484 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1485 since signed numbers are easier to load than unsigned ones. */
1487 while ((value
& 1) == 0)
1488 value
/= 2, shift
++;
1490 i
= mips_build_integer (codes
, value
);
1491 codes
[i
].code
= ASHIFT
;
1492 codes
[i
].value
= shift
;
1496 /* As for mips_build_shift, but assume that the final action will be
1497 an IOR or PLUS operation. */
1500 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1502 unsigned HOST_WIDE_INT high
;
1505 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1506 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1508 /* The constant is too complex to load with a simple LUI/ORI pair,
1509 so we want to give the recursive call as many trailing zeros as
1510 possible. In this case, we know bit 16 is set and that the
1511 low 16 bits form a negative number. If we subtract that number
1512 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1513 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1514 codes
[i
].code
= PLUS
;
1515 codes
[i
].value
= CONST_LOW_PART (value
);
1519 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1520 bits gives a value with at least 17 trailing zeros. */
1521 i
= mips_build_integer (codes
, high
);
1522 codes
[i
].code
= IOR
;
1523 codes
[i
].value
= value
& 0xffff;
1528 /* Fill CODES with a sequence of rtl operations to load VALUE.
1529 Return the number of operations needed. */
1532 mips_build_integer (struct mips_integer_op
*codes
,
1533 unsigned HOST_WIDE_INT value
)
1535 if (SMALL_OPERAND (value
)
1536 || SMALL_OPERAND_UNSIGNED (value
)
1537 || LUI_OPERAND (value
))
1539 /* The value can be loaded with a single instruction. */
1540 codes
[0].code
= UNKNOWN
;
1541 codes
[0].value
= value
;
1544 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1546 /* Either the constant is a simple LUI/ORI combination or its
1547 lowest bit is set. We don't want to shift in this case. */
1548 return mips_build_lower (codes
, value
);
1550 else if ((value
& 0xffff) == 0)
1552 /* The constant will need at least three actions. The lowest
1553 16 bits are clear, so the final action will be a shift. */
1554 return mips_build_shift (codes
, value
);
1558 /* The final action could be a shift, add or inclusive OR.
1559 Rather than use a complex condition to select the best
1560 approach, try both mips_build_shift and mips_build_lower
1561 and pick the one that gives the shortest sequence.
1562 Note that this case is only used once per constant. */
1563 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1564 unsigned int cost
, alt_cost
;
1566 cost
= mips_build_shift (codes
, value
);
1567 alt_cost
= mips_build_lower (alt_codes
, value
);
1568 if (alt_cost
< cost
)
1570 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1577 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1580 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1582 return mips_const_insns (x
) > 0;
1585 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1588 mips16_stub_function (const char *name
)
1592 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1593 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1597 /* Return true if symbols of type TYPE require a GOT access. */
1600 mips_got_symbol_type_p (enum mips_symbol_type type
)
1604 case SYMBOL_GOT_PAGE_OFST
:
1605 case SYMBOL_GOT_DISP
:
1613 /* Return true if X is a thread-local symbol. */
1616 mips_tls_symbol_p (rtx x
)
1618 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1621 /* Return true if SYMBOL_REF X is associated with a global symbol
1622 (in the STB_GLOBAL sense). */
1625 mips_global_symbol_p (const_rtx x
)
1627 const_tree decl
= SYMBOL_REF_DECL (x
);
1630 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1632 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1633 or weak symbols. Relocations in the object file will be against
1634 the target symbol, so it's that symbol's binding that matters here. */
1635 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1638 /* Return true if function X is a libgcc MIPS16 stub function. */
1641 mips16_stub_function_p (const_rtx x
)
1643 return (GET_CODE (x
) == SYMBOL_REF
1644 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1647 /* Return true if function X is a locally-defined and locally-binding
1651 mips16_local_function_p (const_rtx x
)
1653 return (GET_CODE (x
) == SYMBOL_REF
1654 && SYMBOL_REF_LOCAL_P (x
)
1655 && !SYMBOL_REF_EXTERNAL_P (x
)
1656 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1659 /* Return true if SYMBOL_REF X binds locally. */
1662 mips_symbol_binds_local_p (const_rtx x
)
1664 return (SYMBOL_REF_DECL (x
)
1665 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1666 : SYMBOL_REF_LOCAL_P (x
));
1669 /* Return true if rtx constants of mode MODE should be put into a small
1673 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1675 return (!TARGET_EMBEDDED_DATA
1676 && TARGET_LOCAL_SDATA
1677 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1680 /* Return true if X should not be moved directly into register $25.
1681 We need this because many versions of GAS will treat "la $25,foo" as
1682 part of a call sequence and so allow a global "foo" to be lazily bound. */
1685 mips_dangerous_for_la25_p (rtx x
)
1687 return (!TARGET_EXPLICIT_RELOCS
1689 && GET_CODE (x
) == SYMBOL_REF
1690 && mips_global_symbol_p (x
));
1693 /* Return true if calls to X might need $25 to be valid on entry. */
1696 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1698 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1701 /* MIPS16 stub functions are guaranteed not to use $25. */
1702 if (mips16_stub_function_p (x
))
1705 if (GET_CODE (x
) == SYMBOL_REF
)
1707 /* If PLTs and copy relocations are available, the static linker
1708 will make sure that $25 is valid on entry to the target function. */
1709 if (TARGET_ABICALLS_PIC0
)
1712 /* Locally-defined functions use absolute accesses to set up
1713 the global pointer. */
1714 if (TARGET_ABSOLUTE_ABICALLS
1715 && mips_symbol_binds_local_p (x
)
1716 && !SYMBOL_REF_EXTERNAL_P (x
))
1723 /* Return the method that should be used to access SYMBOL_REF or
1724 LABEL_REF X in context CONTEXT. */
1726 static enum mips_symbol_type
1727 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1730 return SYMBOL_GOT_DISP
;
1732 if (GET_CODE (x
) == LABEL_REF
)
1734 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1735 code and if we know that the label is in the current function's
1736 text section. LABEL_REFs are used for jump tables as well as
1737 text labels, so we must check whether jump tables live in the
1739 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1740 && !LABEL_REF_NONLOCAL_P (x
))
1741 return SYMBOL_PC_RELATIVE
;
1743 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1744 return SYMBOL_GOT_PAGE_OFST
;
1746 return SYMBOL_ABSOLUTE
;
1749 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1751 if (SYMBOL_REF_TLS_MODEL (x
))
1754 if (CONSTANT_POOL_ADDRESS_P (x
))
1756 if (TARGET_MIPS16_TEXT_LOADS
)
1757 return SYMBOL_PC_RELATIVE
;
1759 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1760 return SYMBOL_PC_RELATIVE
;
1762 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1763 return SYMBOL_GP_RELATIVE
;
1766 /* Do not use small-data accesses for weak symbols; they may end up
1768 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1769 return SYMBOL_GP_RELATIVE
;
1771 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1773 if (TARGET_ABICALLS_PIC2
1774 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1776 /* There are three cases to consider:
1778 - o32 PIC (either with or without explicit relocs)
1779 - n32/n64 PIC without explicit relocs
1780 - n32/n64 PIC with explicit relocs
1782 In the first case, both local and global accesses will use an
1783 R_MIPS_GOT16 relocation. We must correctly predict which of
1784 the two semantics (local or global) the assembler and linker
1785 will apply. The choice depends on the symbol's binding rather
1786 than its visibility.
1788 In the second case, the assembler will not use R_MIPS_GOT16
1789 relocations, but it chooses between local and global accesses
1790 in the same way as for o32 PIC.
1792 In the third case we have more freedom since both forms of
1793 access will work for any kind of symbol. However, there seems
1794 little point in doing things differently. */
1795 if (mips_global_symbol_p (x
))
1796 return SYMBOL_GOT_DISP
;
1798 return SYMBOL_GOT_PAGE_OFST
;
1801 return SYMBOL_ABSOLUTE
;
1804 /* Classify the base of symbolic expression X, given that X appears in
1807 static enum mips_symbol_type
1808 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1812 split_const (x
, &x
, &offset
);
1813 if (UNSPEC_ADDRESS_P (x
))
1814 return UNSPEC_ADDRESS_TYPE (x
);
1816 return mips_classify_symbol (x
, context
);
1819 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1820 is the alignment in bytes of SYMBOL_REF X. */
1823 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1825 HOST_WIDE_INT align
;
1827 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1828 return IN_RANGE (offset
, 0, align
- 1);
1831 /* Return true if X is a symbolic constant that can be used in context
1832 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1835 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1836 enum mips_symbol_type
*symbol_type
)
1840 split_const (x
, &x
, &offset
);
1841 if (UNSPEC_ADDRESS_P (x
))
1843 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1844 x
= UNSPEC_ADDRESS (x
);
1846 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1848 *symbol_type
= mips_classify_symbol (x
, context
);
1849 if (*symbol_type
== SYMBOL_TLS
)
1855 if (offset
== const0_rtx
)
1858 /* Check whether a nonzero offset is valid for the underlying
1860 switch (*symbol_type
)
1862 case SYMBOL_ABSOLUTE
:
1863 case SYMBOL_64_HIGH
:
1866 /* If the target has 64-bit pointers and the object file only
1867 supports 32-bit symbols, the values of those symbols will be
1868 sign-extended. In this case we can't allow an arbitrary offset
1869 in case the 32-bit value X + OFFSET has a different sign from X. */
1870 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1871 return offset_within_block_p (x
, INTVAL (offset
));
1873 /* In other cases the relocations can handle any offset. */
1876 case SYMBOL_PC_RELATIVE
:
1877 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1878 In this case, we no longer have access to the underlying constant,
1879 but the original symbol-based access was known to be valid. */
1880 if (GET_CODE (x
) == LABEL_REF
)
1885 case SYMBOL_GP_RELATIVE
:
1886 /* Make sure that the offset refers to something within the
1887 same object block. This should guarantee that the final
1888 PC- or GP-relative offset is within the 16-bit limit. */
1889 return offset_within_block_p (x
, INTVAL (offset
));
1891 case SYMBOL_GOT_PAGE_OFST
:
1892 case SYMBOL_GOTOFF_PAGE
:
1893 /* If the symbol is global, the GOT entry will contain the symbol's
1894 address, and we will apply a 16-bit offset after loading it.
1895 If the symbol is local, the linker should provide enough local
1896 GOT entries for a 16-bit offset, but larger offsets may lead
1898 return SMALL_INT (offset
);
1902 /* There is no carry between the HI and LO REL relocations, so the
1903 offset is only valid if we know it won't lead to such a carry. */
1904 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1906 case SYMBOL_GOT_DISP
:
1907 case SYMBOL_GOTOFF_DISP
:
1908 case SYMBOL_GOTOFF_CALL
:
1909 case SYMBOL_GOTOFF_LOADGP
:
1912 case SYMBOL_GOTTPREL
:
1920 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1921 single instruction. We rely on the fact that, in the worst case,
1922 all instructions involved in a MIPS16 address calculation are usually
1926 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1928 if (mips_use_pcrel_pool_p
[(int) type
])
1930 if (mode
== MAX_MACHINE_MODE
)
1931 /* LEAs will be converted into constant-pool references by
1933 type
= SYMBOL_PC_RELATIVE
;
1935 /* The constant must be loaded and then dereferenced. */
1941 case SYMBOL_ABSOLUTE
:
1942 /* When using 64-bit symbols, we need 5 preparatory instructions,
1945 lui $at,%highest(symbol)
1946 daddiu $at,$at,%higher(symbol)
1948 daddiu $at,$at,%hi(symbol)
1951 The final address is then $at + %lo(symbol). With 32-bit
1952 symbols we just need a preparatory LUI for normal mode and
1953 a preparatory LI and SLL for MIPS16. */
1954 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1956 case SYMBOL_GP_RELATIVE
:
1957 /* Treat GP-relative accesses as taking a single instruction on
1958 MIPS16 too; the copy of $gp can often be shared. */
1961 case SYMBOL_PC_RELATIVE
:
1962 /* PC-relative constants can be only be used with ADDIUPC,
1963 DADDIUPC, LWPC and LDPC. */
1964 if (mode
== MAX_MACHINE_MODE
1965 || GET_MODE_SIZE (mode
) == 4
1966 || GET_MODE_SIZE (mode
) == 8)
1969 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1972 case SYMBOL_GOT_DISP
:
1973 /* The constant will have to be loaded from the GOT before it
1974 is used in an address. */
1975 if (mode
!= MAX_MACHINE_MODE
)
1980 case SYMBOL_GOT_PAGE_OFST
:
1981 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1982 local/global classification is accurate. The worst cases are:
1984 (1) For local symbols when generating o32 or o64 code. The assembler
1990 ...and the final address will be $at + %lo(symbol).
1992 (2) For global symbols when -mxgot. The assembler will use:
1994 lui $at,%got_hi(symbol)
1997 ...and the final address will be $at + %got_lo(symbol). */
2000 case SYMBOL_GOTOFF_PAGE
:
2001 case SYMBOL_GOTOFF_DISP
:
2002 case SYMBOL_GOTOFF_CALL
:
2003 case SYMBOL_GOTOFF_LOADGP
:
2004 case SYMBOL_64_HIGH
:
2010 case SYMBOL_GOTTPREL
:
2013 /* A 16-bit constant formed by a single relocation, or a 32-bit
2014 constant formed from a high 16-bit relocation and a low 16-bit
2015 relocation. Use mips_split_p to determine which. 32-bit
2016 constants need an "lui; addiu" sequence for normal mode and
2017 an "li; sll; addiu" sequence for MIPS16 mode. */
2018 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2021 /* We don't treat a bare TLS symbol as a constant. */
2027 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2028 to load symbols of type TYPE into a register. Return 0 if the given
2029 type of symbol cannot be used as an immediate operand.
2031 Otherwise, return the number of instructions needed to load or store
2032 values of mode MODE to or from addresses of type TYPE. Return 0 if
2033 the given type of symbol is not valid in addresses.
2035 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2038 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
2040 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2043 /* A for_each_rtx callback. Stop the search if *X references a
2044 thread-local symbol. */
2047 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
2049 return mips_tls_symbol_p (*x
);
2052 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2055 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
2057 enum mips_symbol_type type
;
2060 /* There is no assembler syntax for expressing an address-sized
2062 if (GET_CODE (x
) == HIGH
)
2065 /* As an optimization, reject constants that mips_legitimize_move
2068 Suppose we have a multi-instruction sequence that loads constant C
2069 into register R. If R does not get allocated a hard register, and
2070 R is used in an operand that allows both registers and memory
2071 references, reload will consider forcing C into memory and using
2072 one of the instruction's memory alternatives. Returning false
2073 here will force it to use an input reload instead. */
2074 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2077 split_const (x
, &base
, &offset
);
2078 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2080 /* See whether we explicitly want these symbols in the pool. */
2081 if (mips_use_pcrel_pool_p
[(int) type
])
2084 /* The same optimization as for CONST_INT. */
2085 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2088 /* If MIPS16 constant pools live in the text section, they should
2089 not refer to anything that might need run-time relocation. */
2090 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2094 /* TLS symbols must be computed by mips_legitimize_move. */
2095 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2101 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2102 constants when we're using a per-function constant pool. */
2105 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2106 const_rtx x ATTRIBUTE_UNUSED
)
2108 return !TARGET_MIPS16_PCREL_LOADS
;
2111 /* Return true if register REGNO is a valid base register for mode MODE.
2112 STRICT_P is true if REG_OK_STRICT is in effect. */
2115 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2118 if (!HARD_REGISTER_NUM_P (regno
))
2122 regno
= reg_renumber
[regno
];
2125 /* These fake registers will be eliminated to either the stack or
2126 hard frame pointer, both of which are usually valid base registers.
2127 Reload deals with the cases where the eliminated form isn't valid. */
2128 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2131 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2132 values, nothing smaller. There are two problems here:
2134 (a) Instantiating virtual registers can introduce new uses of the
2135 stack pointer. If these virtual registers are valid addresses,
2136 the stack pointer should be too.
2138 (b) Most uses of the stack pointer are not made explicit until
2139 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2140 We don't know until that stage whether we'll be eliminating to the
2141 stack pointer (which needs the restriction) or the hard frame
2142 pointer (which doesn't).
2144 All in all, it seems more consistent to only enforce this restriction
2145 during and after reload. */
2146 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2147 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2149 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2152 /* Return true if X is a valid base register for mode MODE.
2153 STRICT_P is true if REG_OK_STRICT is in effect. */
2156 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2158 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2162 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2165 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2166 can address a value of mode MODE. */
2169 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2171 /* Check that X is a signed 16-bit number. */
2172 if (!const_arith_operand (x
, Pmode
))
2175 /* We may need to split multiword moves, so make sure that every word
2177 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2178 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2184 /* Return true if a LO_SUM can address a value of mode MODE when the
2185 LO_SUM symbol has type SYMBOL_TYPE. */
2188 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2190 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2192 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2195 /* Check that there is a known low-part relocation. */
2196 if (mips_lo_relocs
[symbol_type
] == NULL
)
2199 /* We may need to split multiword moves, so make sure that each word
2200 can be accessed without inducing a carry. This is mainly needed
2201 for o64, which has historically only guaranteed 64-bit alignment
2202 for 128-bit types. */
2203 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2204 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2210 /* Return true if X is a valid address for machine mode MODE. If it is,
2211 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2215 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2216 enum machine_mode mode
, bool strict_p
)
2218 switch (GET_CODE (x
))
2222 info
->type
= ADDRESS_REG
;
2224 info
->offset
= const0_rtx
;
2225 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2228 info
->type
= ADDRESS_REG
;
2229 info
->reg
= XEXP (x
, 0);
2230 info
->offset
= XEXP (x
, 1);
2231 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2232 && mips_valid_offset_p (info
->offset
, mode
));
2235 info
->type
= ADDRESS_LO_SUM
;
2236 info
->reg
= XEXP (x
, 0);
2237 info
->offset
= XEXP (x
, 1);
2238 /* We have to trust the creator of the LO_SUM to do something vaguely
2239 sane. Target-independent code that creates a LO_SUM should also
2240 create and verify the matching HIGH. Target-independent code that
2241 adds an offset to a LO_SUM must prove that the offset will not
2242 induce a carry. Failure to do either of these things would be
2243 a bug, and we are not required to check for it here. The MIPS
2244 backend itself should only create LO_SUMs for valid symbolic
2245 constants, with the high part being either a HIGH or a copy
2248 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2249 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2250 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2253 /* Small-integer addresses don't occur very often, but they
2254 are legitimate if $0 is a valid base register. */
2255 info
->type
= ADDRESS_CONST_INT
;
2256 return !TARGET_MIPS16
&& SMALL_INT (x
);
2261 info
->type
= ADDRESS_SYMBOLIC
;
2262 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2264 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2265 && !mips_split_p
[info
->symbol_type
]);
2272 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2275 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2277 struct mips_address_info addr
;
2279 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2282 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2285 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2287 struct mips_address_info addr
;
2289 return (mips_classify_address (&addr
, x
, mode
, false)
2290 && addr
.type
== ADDRESS_REG
2291 && addr
.reg
== stack_pointer_rtx
);
2294 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2295 address instruction. Note that such addresses are not considered
2296 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2297 is so restricted. */
2300 mips_lwxs_address_p (rtx addr
)
2303 && GET_CODE (addr
) == PLUS
2304 && REG_P (XEXP (addr
, 1)))
2306 rtx offset
= XEXP (addr
, 0);
2307 if (GET_CODE (offset
) == MULT
2308 && REG_P (XEXP (offset
, 0))
2309 && CONST_INT_P (XEXP (offset
, 1))
2310 && INTVAL (XEXP (offset
, 1)) == 4)
2316 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2317 indexed address instruction. Note that such addresses are
2318 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2319 sense, because their use is so restricted. */
2322 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2324 if (GET_CODE (addr
) != PLUS
2325 || !REG_P (XEXP (addr
, 0))
2326 || !REG_P (XEXP (addr
, 1)))
2328 if (ISA_HAS_LBX
&& mode
== QImode
)
2330 if (ISA_HAS_LHX
&& mode
== HImode
)
2332 if (ISA_HAS_LWX
&& mode
== SImode
)
2334 if (ISA_HAS_LDX
&& mode
== DImode
)
2339 /* Return true if a value at OFFSET bytes from base register BASE can be
2340 accessed using an unextended MIPS16 instruction. MODE is the mode of
2343 Usually the offset in an unextended instruction is a 5-bit field.
2344 The offset is unsigned and shifted left once for LH and SH, twice
2345 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2346 an 8-bit immediate field that's shifted left twice. */
2349 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2350 unsigned HOST_WIDE_INT offset
)
2352 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2354 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2355 return offset
< 256U * GET_MODE_SIZE (mode
);
2356 return offset
< 32U * GET_MODE_SIZE (mode
);
2361 /* Return the number of instructions needed to load or store a value
2362 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2363 length of one instruction. Return 0 if X isn't valid for MODE.
2364 Assume that multiword moves may need to be split into word moves
2365 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2369 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2371 struct mips_address_info addr
;
2374 /* BLKmode is used for single unaligned loads and stores and should
2375 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2376 meaningless, so we have to single it out as a special case one way
2378 if (mode
!= BLKmode
&& might_split_p
)
2379 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2383 if (mips_classify_address (&addr
, x
, mode
, false))
2388 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2389 UINTVAL (addr
.offset
)))
2393 case ADDRESS_LO_SUM
:
2394 return TARGET_MIPS16
? factor
* 2 : factor
;
2396 case ADDRESS_CONST_INT
:
2399 case ADDRESS_SYMBOLIC
:
2400 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2405 /* Return true if X fits within an unsigned field of BITS bits that is
2406 shifted left SHIFT bits before being used. */
2409 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2411 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2414 /* Return true if X fits within a signed field of BITS bits that is
2415 shifted left SHIFT bits before being used. */
2418 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2420 x
+= 1 << (bits
+ shift
- 1);
2421 return mips_unsigned_immediate_p (x
, bits
, shift
);
2424 /* Return true if X is legitimate for accessing values of mode MODE,
2425 if it is based on a MIPS16 register, and if the offset satisfies
2426 OFFSET_PREDICATE. */
2429 m16_based_address_p (rtx x
, enum machine_mode mode
,
2430 insn_operand_predicate_fn offset_predicate
)
2432 struct mips_address_info addr
;
2434 return (mips_classify_address (&addr
, x
, mode
, false)
2435 && addr
.type
== ADDRESS_REG
2436 && M16_REG_P (REGNO (addr
.reg
))
2437 && offset_predicate (addr
.offset
, mode
));
2440 /* Return true if X is a legitimate address that conforms to the requirements
2441 for a microMIPS LWSP or SWSP insn. */
2444 lwsp_swsp_address_p (rtx x
, enum machine_mode mode
)
2446 struct mips_address_info addr
;
2448 return (mips_classify_address (&addr
, x
, mode
, false)
2449 && addr
.type
== ADDRESS_REG
2450 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2451 && uw5_operand (addr
.offset
, mode
));
2454 /* Return true if X is a legitimate address with a 12-bit offset.
2455 MODE is the mode of the value being accessed. */
2458 umips_12bit_offset_address_p (rtx x
, enum machine_mode mode
)
2460 struct mips_address_info addr
;
2462 return (mips_classify_address (&addr
, x
, mode
, false)
2463 && addr
.type
== ADDRESS_REG
2464 && CONST_INT_P (addr
.offset
)
2465 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2468 /* Return the number of instructions needed to load constant X,
2469 assuming that BASE_INSN_LENGTH is the length of one instruction.
2470 Return 0 if X isn't a valid constant. */
2473 mips_const_insns (rtx x
)
2475 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2476 enum mips_symbol_type symbol_type
;
2479 switch (GET_CODE (x
))
2482 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2484 || !mips_split_p
[symbol_type
])
2487 /* This is simply an LUI for normal mode. It is an extended
2488 LI followed by an extended SLL for MIPS16. */
2489 return TARGET_MIPS16
? 4 : 1;
2493 /* Unsigned 8-bit constants can be loaded using an unextended
2494 LI instruction. Unsigned 16-bit constants can be loaded
2495 using an extended LI. Negative constants must be loaded
2496 using LI and then negated. */
2497 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2498 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2499 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2500 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2503 return mips_build_integer (codes
, INTVAL (x
));
2507 /* Allow zeros for normal mode, where we can use $0. */
2508 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2514 /* See if we can refer to X directly. */
2515 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2516 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2518 /* Otherwise try splitting the constant into a base and offset.
2519 If the offset is a 16-bit value, we can load the base address
2520 into a register and then use (D)ADDIU to add in the offset.
2521 If the offset is larger, we can load the base and offset
2522 into separate registers and add them together with (D)ADDU.
2523 However, the latter is only possible before reload; during
2524 and after reload, we must have the option of forcing the
2525 constant into the pool instead. */
2526 split_const (x
, &x
, &offset
);
2529 int n
= mips_const_insns (x
);
2532 if (SMALL_INT (offset
))
2534 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2535 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2542 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2550 /* X is a doubleword constant that can be handled by splitting it into
2551 two words and loading each word separately. Return the number of
2552 instructions required to do this, assuming that BASE_INSN_LENGTH
2553 is the length of one instruction. */
2556 mips_split_const_insns (rtx x
)
2558 unsigned int low
, high
;
2560 low
= mips_const_insns (mips_subword (x
, false));
2561 high
= mips_const_insns (mips_subword (x
, true));
2562 gcc_assert (low
> 0 && high
> 0);
2566 /* Return the number of instructions needed to implement INSN,
2567 given that it loads from or stores to MEM. Assume that
2568 BASE_INSN_LENGTH is the length of one instruction. */
2571 mips_load_store_insns (rtx mem
, rtx insn
)
2573 enum machine_mode mode
;
2577 gcc_assert (MEM_P (mem
));
2578 mode
= GET_MODE (mem
);
2580 /* Try to prove that INSN does not need to be split. */
2581 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2584 set
= single_set (insn
);
2585 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2586 might_split_p
= false;
2589 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2592 /* Return the number of instructions needed for an integer division,
2593 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2596 mips_idiv_insns (void)
2601 if (TARGET_CHECK_ZERO_DIV
)
2603 if (GENERATE_DIVIDE_TRAPS
)
2609 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2614 /* Emit a move from SRC to DEST. Assume that the move expanders can
2615 handle all moves if !can_create_pseudo_p (). The distinction is
2616 important because, unlike emit_move_insn, the move expanders know
2617 how to force Pmode objects into the constant pool even when the
2618 constant pool address is not itself legitimate. */
2621 mips_emit_move (rtx dest
, rtx src
)
2623 return (can_create_pseudo_p ()
2624 ? emit_move_insn (dest
, src
)
2625 : emit_move_insn_1 (dest
, src
));
2628 /* Emit a move from SRC to DEST, splitting compound moves into individual
2629 instructions. SPLIT_TYPE is the type of split to perform. */
2632 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2634 if (mips_split_move_p (dest
, src
, split_type
))
2635 mips_split_move (dest
, src
, split_type
);
2637 mips_emit_move (dest
, src
);
2640 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2643 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2645 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2646 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2649 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2650 Return that new register. */
2653 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2657 reg
= gen_reg_rtx (mode
);
2658 mips_emit_unary (code
, reg
, op0
);
2662 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2665 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2667 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2668 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2671 /* Compute (CODE OP0 OP1) and store the result in a new register
2672 of mode MODE. Return that new register. */
2675 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2679 reg
= gen_reg_rtx (mode
);
2680 mips_emit_binary (code
, reg
, op0
, op1
);
2684 /* Copy VALUE to a register and return that register. If new pseudos
2685 are allowed, copy it into a new register, otherwise use DEST. */
2688 mips_force_temporary (rtx dest
, rtx value
)
2690 if (can_create_pseudo_p ())
2691 return force_reg (Pmode
, value
);
2694 mips_emit_move (dest
, value
);
2699 /* Emit a call sequence with call pattern PATTERN and return the call
2700 instruction itself (which is not necessarily the last instruction
2701 emitted). ORIG_ADDR is the original, unlegitimized address,
2702 ADDR is the legitimized form, and LAZY_P is true if the call
2703 address is lazily-bound. */
2706 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2710 insn
= emit_call_insn (pattern
);
2712 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2714 /* MIPS16 JALRs only take MIPS16 registers. If the target
2715 function requires $25 to be valid on entry, we must copy it
2716 there separately. The move instruction can be put in the
2717 call's delay slot. */
2718 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2719 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2720 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2724 /* Lazy-binding stubs require $gp to be valid on entry. */
2725 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2729 /* See the comment above load_call<mode> for details. */
2730 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2731 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2732 emit_insn (gen_update_got_version ());
2737 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2738 then add CONST_INT OFFSET to the result. */
2741 mips_unspec_address_offset (rtx base
, rtx offset
,
2742 enum mips_symbol_type symbol_type
)
2744 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2745 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2746 if (offset
!= const0_rtx
)
2747 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2748 return gen_rtx_CONST (Pmode
, base
);
2751 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2752 type SYMBOL_TYPE. */
2755 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2759 split_const (address
, &base
, &offset
);
2760 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2763 /* If OP is an UNSPEC address, return the address to which it refers,
2764 otherwise return OP itself. */
2767 mips_strip_unspec_address (rtx op
)
2771 split_const (op
, &base
, &offset
);
2772 if (UNSPEC_ADDRESS_P (base
))
2773 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2777 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2778 high part to BASE and return the result. Just return BASE otherwise.
2779 TEMP is as for mips_force_temporary.
2781 The returned expression can be used as the first operand to a LO_SUM. */
2784 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2785 enum mips_symbol_type symbol_type
)
2787 if (mips_split_p
[symbol_type
])
2789 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2790 addr
= mips_force_temporary (temp
, addr
);
2791 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2796 /* Return an instruction that copies $gp into register REG. We want
2797 GCC to treat the register's value as constant, so that its value
2798 can be rematerialized on demand. */
2801 gen_load_const_gp (rtx reg
)
2803 return PMODE_INSN (gen_load_const_gp
, (reg
));
2806 /* Return a pseudo register that contains the value of $gp throughout
2807 the current function. Such registers are needed by MIPS16 functions,
2808 for which $gp itself is not a valid base register or addition operand. */
2811 mips16_gp_pseudo_reg (void)
2813 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2817 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2819 push_topmost_sequence ();
2821 scan
= get_insns ();
2822 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2823 scan
= NEXT_INSN (scan
);
2825 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2826 insn
= emit_insn_after (insn
, scan
);
2827 INSN_LOCATION (insn
) = 0;
2829 pop_topmost_sequence ();
2832 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2835 /* Return a base register that holds pic_offset_table_rtx.
2836 TEMP, if nonnull, is a scratch Pmode base register. */
2839 mips_pic_base_register (rtx temp
)
2842 return pic_offset_table_rtx
;
2844 if (currently_expanding_to_rtl
)
2845 return mips16_gp_pseudo_reg ();
2847 if (can_create_pseudo_p ())
2848 temp
= gen_reg_rtx (Pmode
);
2851 /* The first post-reload split exposes all references to $gp
2852 (both uses and definitions). All references must remain
2853 explicit after that point.
2855 It is safe to introduce uses of $gp at any time, so for
2856 simplicity, we do that before the split too. */
2857 mips_emit_move (temp
, pic_offset_table_rtx
);
2859 emit_insn (gen_load_const_gp (temp
));
2863 /* Return the RHS of a load_call<mode> insn. */
2866 mips_unspec_call (rtx reg
, rtx symbol
)
2870 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2871 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2874 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2875 reference. Return NULL_RTX otherwise. */
2878 mips_strip_unspec_call (rtx src
)
2880 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2881 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2885 /* Create and return a GOT reference of type TYPE for address ADDR.
2886 TEMP, if nonnull, is a scratch Pmode base register. */
2889 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2891 rtx base
, high
, lo_sum_symbol
;
2893 base
= mips_pic_base_register (temp
);
2895 /* If we used the temporary register to load $gp, we can't use
2896 it for the high part as well. */
2897 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2900 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2901 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2903 if (type
== SYMBOL_GOTOFF_CALL
)
2904 return mips_unspec_call (high
, lo_sum_symbol
);
2906 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
2909 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2910 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2911 constant in that context and can be split into high and low parts.
2912 If so, and if LOW_OUT is nonnull, emit the high part and store the
2913 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2915 TEMP is as for mips_force_temporary and is used to load the high
2916 part into a register.
2918 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2919 a legitimize SET_SRC for an .md pattern, otherwise the low part
2920 is guaranteed to be a legitimate address for mode MODE. */
2923 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2925 enum mips_symbol_context context
;
2926 enum mips_symbol_type symbol_type
;
2929 context
= (mode
== MAX_MACHINE_MODE
2930 ? SYMBOL_CONTEXT_LEA
2931 : SYMBOL_CONTEXT_MEM
);
2932 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2934 addr
= XEXP (addr
, 0);
2935 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2936 && mips_symbol_insns (symbol_type
, mode
) > 0
2937 && mips_split_hi_p
[symbol_type
])
2940 switch (symbol_type
)
2942 case SYMBOL_GOT_PAGE_OFST
:
2943 /* The high part of a page/ofst pair is loaded from the GOT. */
2944 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2955 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2956 && mips_symbol_insns (symbol_type
, mode
) > 0
2957 && mips_split_p
[symbol_type
])
2960 switch (symbol_type
)
2962 case SYMBOL_GOT_DISP
:
2963 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2964 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2967 case SYMBOL_GP_RELATIVE
:
2968 high
= mips_pic_base_register (temp
);
2969 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2973 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2974 high
= mips_force_temporary (temp
, high
);
2975 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2984 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2985 mips_force_temporary; it is only needed when OFFSET is not a
2989 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2991 if (!SMALL_OPERAND (offset
))
2997 /* Load the full offset into a register so that we can use
2998 an unextended instruction for the address itself. */
2999 high
= GEN_INT (offset
);
3004 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3005 The addition inside the macro CONST_HIGH_PART may cause an
3006 overflow, so we need to force a sign-extension check. */
3007 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3008 offset
= CONST_LOW_PART (offset
);
3010 high
= mips_force_temporary (temp
, high
);
3011 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3013 return plus_constant (Pmode
, reg
, offset
);
3016 /* The __tls_get_attr symbol. */
3017 static GTY(()) rtx mips_tls_symbol
;
3019 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3020 the TLS symbol we are referencing and TYPE is the symbol type to use
3021 (either global dynamic or local dynamic). V0 is an RTX for the
3022 return value location. */
3025 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3029 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3031 if (!mips_tls_symbol
)
3032 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3034 loc
= mips_unspec_address (sym
, type
);
3038 emit_insn (gen_rtx_SET (Pmode
, a0
,
3039 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
3040 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3041 const0_rtx
, NULL_RTX
, false);
3042 RTL_CONST_CALL_P (insn
) = 1;
3043 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3044 insn
= get_insns ();
3051 /* Return a pseudo register that contains the current thread pointer. */
3054 mips_expand_thread_pointer (rtx tp
)
3060 mips_need_mips16_rdhwr_p
= true;
3061 fn
= mips16_stub_function ("__mips16_rdhwr");
3062 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
3063 if (!call_insn_operand (fn
, VOIDmode
))
3064 fn
= force_reg (Pmode
, fn
);
3065 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3068 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3075 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3078 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3079 its address. The return value will be both a valid address and a valid
3080 SET_SRC (either a REG or a LO_SUM). */
3083 mips_legitimize_tls_address (rtx loc
)
3085 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3086 enum tls_model model
;
3088 model
= SYMBOL_REF_TLS_MODEL (loc
);
3089 /* Only TARGET_ABICALLS code can have more than one module; other
3090 code must be be static and should not use a GOT. All TLS models
3091 reduce to local exec in this situation. */
3092 if (!TARGET_ABICALLS
)
3093 model
= TLS_MODEL_LOCAL_EXEC
;
3097 case TLS_MODEL_GLOBAL_DYNAMIC
:
3098 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3099 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3100 dest
= gen_reg_rtx (Pmode
);
3101 emit_libcall_block (insn
, dest
, v0
, loc
);
3104 case TLS_MODEL_LOCAL_DYNAMIC
:
3105 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3106 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3107 tmp1
= gen_reg_rtx (Pmode
);
3109 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3110 share the LDM result with other LD model accesses. */
3111 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3113 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3115 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3116 if (mips_split_p
[SYMBOL_DTPREL
])
3118 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3119 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3122 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3123 0, 0, OPTAB_DIRECT
);
3126 case TLS_MODEL_INITIAL_EXEC
:
3127 tp
= mips_get_tp ();
3128 tmp1
= gen_reg_rtx (Pmode
);
3129 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3130 if (Pmode
== DImode
)
3131 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3133 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3134 dest
= gen_reg_rtx (Pmode
);
3135 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3138 case TLS_MODEL_LOCAL_EXEC
:
3139 tmp1
= mips_get_tp ();
3140 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3141 if (mips_split_p
[SYMBOL_TPREL
])
3143 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3144 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3147 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3148 0, 0, OPTAB_DIRECT
);
3157 /* If X is not a valid address for mode MODE, force it into a register. */
3160 mips_force_address (rtx x
, enum machine_mode mode
)
3162 if (!mips_legitimate_address_p (mode
, x
, false))
3163 x
= force_reg (Pmode
, x
);
3167 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3168 be legitimized in a way that the generic machinery might not expect,
3169 return a new address, otherwise return NULL. MODE is the mode of
3170 the memory being accessed. */
3173 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3174 enum machine_mode mode
)
3177 HOST_WIDE_INT offset
;
3179 if (mips_tls_symbol_p (x
))
3180 return mips_legitimize_tls_address (x
);
3182 /* See if the address can split into a high part and a LO_SUM. */
3183 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3184 return mips_force_address (addr
, mode
);
3186 /* Handle BASE + OFFSET using mips_add_offset. */
3187 mips_split_plus (x
, &base
, &offset
);
3190 if (!mips_valid_base_register_p (base
, mode
, false))
3191 base
= copy_to_mode_reg (Pmode
, base
);
3192 addr
= mips_add_offset (NULL
, base
, offset
);
3193 return mips_force_address (addr
, mode
);
3199 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3202 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3204 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3205 enum machine_mode mode
;
3206 unsigned int i
, num_ops
;
3209 mode
= GET_MODE (dest
);
3210 num_ops
= mips_build_integer (codes
, value
);
3212 /* Apply each binary operation to X. Invariant: X is a legitimate
3213 source operand for a SET pattern. */
3214 x
= GEN_INT (codes
[0].value
);
3215 for (i
= 1; i
< num_ops
; i
++)
3217 if (!can_create_pseudo_p ())
3219 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3223 x
= force_reg (mode
, x
);
3224 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3227 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3230 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3231 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3235 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3239 /* Split moves of big integers into smaller pieces. */
3240 if (splittable_const_int_operand (src
, mode
))
3242 mips_move_integer (dest
, dest
, INTVAL (src
));
3246 /* Split moves of symbolic constants into high/low pairs. */
3247 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3249 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3253 /* Generate the appropriate access sequences for TLS symbols. */
3254 if (mips_tls_symbol_p (src
))
3256 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3260 /* If we have (const (plus symbol offset)), and that expression cannot
3261 be forced into memory, load the symbol first and add in the offset.
3262 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3263 forced into memory, as it usually produces better code. */
3264 split_const (src
, &base
, &offset
);
3265 if (offset
!= const0_rtx
3266 && (targetm
.cannot_force_const_mem (mode
, src
)
3267 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3269 base
= mips_force_temporary (dest
, base
);
3270 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3274 src
= force_const_mem (mode
, src
);
3276 /* When using explicit relocs, constant pool references are sometimes
3277 not legitimate addresses. */
3278 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3279 mips_emit_move (dest
, src
);
3282 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3283 sequence that is valid. */
3286 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3288 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3290 mips_emit_move (dest
, force_reg (mode
, src
));
3294 /* We need to deal with constants that would be legitimate
3295 immediate_operands but aren't legitimate move_operands. */
3296 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3298 mips_legitimize_const_move (mode
, dest
, src
);
3299 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3305 /* Return true if value X in context CONTEXT is a small-data address
3306 that can be rewritten as a LO_SUM. */
3309 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3311 enum mips_symbol_type symbol_type
;
3313 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3314 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3315 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3316 && symbol_type
== SYMBOL_GP_RELATIVE
);
3319 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3320 containing MEM, or null if none. */
3323 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3325 enum mips_symbol_context context
;
3327 /* Ignore things like "g" constraints in asms. We make no particular
3328 guarantee about which symbolic constants are acceptable as asm operands
3329 versus which must be forced into a GPR. */
3330 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3335 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3340 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3341 return mips_rewrite_small_data_p (*loc
, context
);
3344 /* Return true if OP refers to small data symbols directly, not through
3348 mips_small_data_pattern_p (rtx op
)
3350 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3353 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3354 DATA is the containing MEM, or null if none. */
3357 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3359 enum mips_symbol_context context
;
3363 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3367 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3368 if (mips_rewrite_small_data_p (*loc
, context
))
3369 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3371 if (GET_CODE (*loc
) == LO_SUM
)
3377 /* Rewrite instruction pattern PATTERN so that it refers to small data
3378 using explicit relocations. */
3381 mips_rewrite_small_data (rtx pattern
)
3383 pattern
= copy_insn (pattern
);
3384 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3388 /* The cost of loading values from the constant pool. It should be
3389 larger than the cost of any constant we want to synthesize inline. */
3390 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3392 /* Return the cost of X when used as an operand to the MIPS16 instruction
3393 that implements CODE. Return -1 if there is no such instruction, or if
3394 X is not a valid immediate operand for it. */
3397 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3404 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3405 other shifts are extended. The shift patterns truncate the shift
3406 count to the right size, so there are no out-of-range values. */
3407 if (IN_RANGE (x
, 1, 8))
3409 return COSTS_N_INSNS (1);
3412 if (IN_RANGE (x
, -128, 127))
3414 if (SMALL_OPERAND (x
))
3415 return COSTS_N_INSNS (1);
3419 /* Like LE, but reject the always-true case. */
3423 /* We add 1 to the immediate and use SLT. */
3426 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3429 if (IN_RANGE (x
, 0, 255))
3431 if (SMALL_OPERAND_UNSIGNED (x
))
3432 return COSTS_N_INSNS (1);
3437 /* Equality comparisons with 0 are cheap. */
3447 /* Return true if there is a non-MIPS16 instruction that implements CODE
3448 and if that instruction accepts X as an immediate operand. */
3451 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3458 /* All shift counts are truncated to a valid constant. */
3463 /* Likewise rotates, if the target supports rotates at all. */
3469 /* These instructions take 16-bit unsigned immediates. */
3470 return SMALL_OPERAND_UNSIGNED (x
);
3475 /* These instructions take 16-bit signed immediates. */
3476 return SMALL_OPERAND (x
);
3482 /* The "immediate" forms of these instructions are really
3483 implemented as comparisons with register 0. */
3488 /* Likewise, meaning that the only valid immediate operand is 1. */
3492 /* We add 1 to the immediate and use SLT. */
3493 return SMALL_OPERAND (x
+ 1);
3496 /* Likewise SLTU, but reject the always-true case. */
3497 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3501 /* The bit position and size are immediate operands. */
3502 return ISA_HAS_EXT_INS
;
3505 /* By default assume that $0 can be used for 0. */
3510 /* Return the cost of binary operation X, given that the instruction
3511 sequence for a word-sized or smaller operation has cost SINGLE_COST
3512 and that the sequence of a double-word operation has cost DOUBLE_COST.
3513 If SPEED is true, optimize for speed otherwise optimize for size. */
3516 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3520 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3525 + set_src_cost (XEXP (x
, 0), speed
)
3526 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3529 /* Return the cost of floating-point multiplications of mode MODE. */
3532 mips_fp_mult_cost (enum machine_mode mode
)
3534 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3537 /* Return the cost of floating-point divisions of mode MODE. */
3540 mips_fp_div_cost (enum machine_mode mode
)
3542 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3545 /* Return the cost of sign-extending OP to mode MODE, not including the
3546 cost of OP itself. */
3549 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3552 /* Extended loads are as cheap as unextended ones. */
3555 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3556 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3559 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3560 /* We can use SEB or SEH. */
3561 return COSTS_N_INSNS (1);
3563 /* We need to use a shift left and a shift right. */
3564 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3567 /* Return the cost of zero-extending OP to mode MODE, not including the
3568 cost of OP itself. */
3571 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3574 /* Extended loads are as cheap as unextended ones. */
3577 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3578 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3579 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3581 if (GENERATE_MIPS16E
)
3582 /* We can use ZEB or ZEH. */
3583 return COSTS_N_INSNS (1);
3586 /* We need to load 0xff or 0xffff into a register and use AND. */
3587 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3589 /* We can use ANDI. */
3590 return COSTS_N_INSNS (1);
3593 /* Return the cost of moving between two registers of mode MODE,
3594 assuming that the move will be in pieces of at most UNITS bytes. */
3597 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3599 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3602 /* Return the cost of moving between two registers of mode MODE. */
3605 mips_set_reg_reg_cost (enum machine_mode mode
)
3607 switch (GET_MODE_CLASS (mode
))
3610 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3613 case MODE_COMPLEX_FLOAT
:
3614 case MODE_VECTOR_FLOAT
:
3615 if (TARGET_HARD_FLOAT
)
3616 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3620 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3624 /* Return the cost of an operand X that can be trucated for free.
3625 SPEED says whether we're optimizing for size or speed. */
3628 mips_truncated_op_cost (rtx x
, bool speed
)
3630 if (GET_CODE (x
) == TRUNCATE
)
3632 return set_src_cost (x
, speed
);
3635 /* Implement TARGET_RTX_COSTS. */
3638 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3639 int *total
, bool speed
)
3641 enum machine_mode mode
= GET_MODE (x
);
3642 bool float_mode_p
= FLOAT_MODE_P (mode
);
3646 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3647 appear in the instruction stream, and the cost of a comparison is
3648 really the cost of the branch or scc condition. At the time of
3649 writing, GCC only uses an explicit outer COMPARE code when optabs
3650 is testing whether a constant is expensive enough to force into a
3651 register. We want optabs to pass such constants through the MIPS
3652 expanders instead, so make all constants very cheap here. */
3653 if (outer_code
== COMPARE
)
3655 gcc_assert (CONSTANT_P (x
));
3663 /* Treat *clear_upper32-style ANDs as having zero cost in the
3664 second operand. The cost is entirely in the first operand.
3666 ??? This is needed because we would otherwise try to CSE
3667 the constant operand. Although that's the right thing for
3668 instructions that continue to be a register operation throughout
3669 compilation, it is disastrous for instructions that could
3670 later be converted into a memory operation. */
3672 && outer_code
== AND
3673 && UINTVAL (x
) == 0xffffffff)
3681 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3690 /* When not optimizing for size, we care more about the cost
3691 of hot code, and hot code is often in a loop. If a constant
3692 operand needs to be forced into a register, we will often be
3693 able to hoist the constant load out of the loop, so the load
3694 should not contribute to the cost. */
3695 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3707 if (force_to_mem_operand (x
, VOIDmode
))
3709 *total
= COSTS_N_INSNS (1);
3712 cost
= mips_const_insns (x
);
3715 /* If the constant is likely to be stored in a GPR, SETs of
3716 single-insn constants are as cheap as register sets; we
3717 never want to CSE them.
3719 Don't reduce the cost of storing a floating-point zero in
3720 FPRs. If we have a zero in an FPR for other reasons, we
3721 can get better cfg-cleanup and delayed-branch results by
3722 using it consistently, rather than using $0 sometimes and
3723 an FPR at other times. Also, moves between floating-point
3724 registers are sometimes cheaper than (D)MTC1 $0. */
3726 && outer_code
== SET
3727 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3729 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3730 want to CSE the constant itself. It is usually better to
3731 have N copies of the last operation in the sequence and one
3732 shared copy of the other operations. (Note that this is
3733 not true for MIPS16 code, where the final operation in the
3734 sequence is often an extended instruction.)
3736 Also, if we have a CONST_INT, we don't know whether it is
3737 for a word or doubleword operation, so we cannot rely on
3738 the result of mips_build_integer. */
3739 else if (!TARGET_MIPS16
3740 && (outer_code
== SET
|| mode
== VOIDmode
))
3742 *total
= COSTS_N_INSNS (cost
);
3745 /* The value will need to be fetched from the constant pool. */
3746 *total
= CONSTANT_POOL_COST
;
3750 /* If the address is legitimate, return the number of
3751 instructions it needs. */
3753 cost
= mips_address_insns (addr
, mode
, true);
3756 *total
= COSTS_N_INSNS (cost
+ 1);
3759 /* Check for a scaled indexed address. */
3760 if (mips_lwxs_address_p (addr
)
3761 || mips_lx_address_p (addr
, mode
))
3763 *total
= COSTS_N_INSNS (2);
3766 /* Otherwise use the default handling. */
3770 *total
= COSTS_N_INSNS (6);
3774 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3778 /* Check for a *clear_upper32 pattern and treat it like a zero
3779 extension. See the pattern's comment for details. */
3782 && CONST_INT_P (XEXP (x
, 1))
3783 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3785 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3786 + set_src_cost (XEXP (x
, 0), speed
));
3789 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3791 rtx op
= XEXP (x
, 0);
3792 if (GET_CODE (op
) == ASHIFT
3793 && CONST_INT_P (XEXP (op
, 1))
3794 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3796 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3800 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3801 a single instruction. */
3803 && GET_CODE (XEXP (x
, 0)) == NOT
3804 && GET_CODE (XEXP (x
, 1)) == NOT
)
3806 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
3807 *total
= (COSTS_N_INSNS (cost
)
3808 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
3809 + set_src_cost (XEXP (XEXP (x
, 1), 0), speed
));
3817 /* Double-word operations use two single-word operations. */
3818 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3827 if (CONSTANT_P (XEXP (x
, 1)))
3828 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3831 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3837 *total
= mips_cost
->fp_add
;
3839 *total
= COSTS_N_INSNS (4);
3843 /* Low-part immediates need an extended MIPS16 instruction. */
3844 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3845 + set_src_cost (XEXP (x
, 0), speed
));
3860 /* Branch comparisons have VOIDmode, so use the first operand's
3862 mode
= GET_MODE (XEXP (x
, 0));
3863 if (FLOAT_MODE_P (mode
))
3865 *total
= mips_cost
->fp_add
;
3868 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3874 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3875 && TARGET_FUSED_MADD
3876 && !HONOR_NANS (mode
)
3877 && !HONOR_SIGNED_ZEROS (mode
))
3879 /* See if we can use NMADD or NMSUB. See mips.md for the
3880 associated patterns. */
3881 rtx op0
= XEXP (x
, 0);
3882 rtx op1
= XEXP (x
, 1);
3883 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3885 *total
= (mips_fp_mult_cost (mode
)
3886 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3887 + set_src_cost (XEXP (op0
, 1), speed
)
3888 + set_src_cost (op1
, speed
));
3891 if (GET_CODE (op1
) == MULT
)
3893 *total
= (mips_fp_mult_cost (mode
)
3894 + set_src_cost (op0
, speed
)
3895 + set_src_cost (XEXP (op1
, 0), speed
)
3896 + set_src_cost (XEXP (op1
, 1), speed
));
3905 /* If this is part of a MADD or MSUB, treat the PLUS as
3907 if ((ISA_HAS_FP_MADD4_MSUB4
|| ISA_HAS_FP_MADD3_MSUB3
)
3908 && TARGET_FUSED_MADD
3909 && GET_CODE (XEXP (x
, 0)) == MULT
)
3912 *total
= mips_cost
->fp_add
;
3916 /* Double-word operations require three single-word operations and
3917 an SLTU. The MIPS16 version then needs to move the result of
3918 the SLTU from $24 to a MIPS16 register. */
3919 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3920 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3926 && (ISA_HAS_NMADD4_NMSUB4
|| ISA_HAS_NMADD3_NMSUB3
)
3927 && TARGET_FUSED_MADD
3928 && !HONOR_NANS (mode
)
3929 && HONOR_SIGNED_ZEROS (mode
))
3931 /* See if we can use NMADD or NMSUB. See mips.md for the
3932 associated patterns. */
3933 rtx op
= XEXP (x
, 0);
3934 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3935 && GET_CODE (XEXP (op
, 0)) == MULT
)
3937 *total
= (mips_fp_mult_cost (mode
)
3938 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3939 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3940 + set_src_cost (XEXP (op
, 1), speed
));
3946 *total
= mips_cost
->fp_add
;
3948 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3953 *total
= mips_fp_mult_cost (mode
);
3954 else if (mode
== DImode
&& !TARGET_64BIT
)
3955 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3956 where the mulsidi3 always includes an MFHI and an MFLO. */
3958 ? mips_cost
->int_mult_si
* 3 + 6
3959 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3961 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2) + 1;
3962 else if (mode
== DImode
)
3963 *total
= mips_cost
->int_mult_di
;
3965 *total
= mips_cost
->int_mult_si
;
3969 /* Check for a reciprocal. */
3972 && flag_unsafe_math_optimizations
3973 && XEXP (x
, 0) == CONST1_RTX (mode
))
3975 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3976 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3977 division as being free. */
3978 *total
= set_src_cost (XEXP (x
, 1), speed
);
3980 *total
= (mips_fp_div_cost (mode
)
3981 + set_src_cost (XEXP (x
, 1), speed
));
3990 *total
= mips_fp_div_cost (mode
);
3999 /* It is our responsibility to make division by a power of 2
4000 as cheap as 2 register additions if we want the division
4001 expanders to be used for such operations; see the setting
4002 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4003 should always produce shorter code than using
4004 expand_sdiv2_pow2. */
4006 && CONST_INT_P (XEXP (x
, 1))
4007 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4009 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
4012 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4014 else if (mode
== DImode
)
4015 *total
= mips_cost
->int_div_di
;
4017 *total
= mips_cost
->int_div_si
;
4021 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4025 if (outer_code
== SET
4027 && GET_MODE (XEXP (x
, 0)) == QImode
4028 && GET_CODE (XEXP (x
, 0)) == PLUS
)
4030 rtx plus
= XEXP (x
, 0);
4031 *total
= (COSTS_N_INSNS (1)
4032 + mips_truncated_op_cost (XEXP (plus
, 0), speed
)
4033 + mips_truncated_op_cost (XEXP (plus
, 1), speed
));
4036 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4040 case UNSIGNED_FLOAT
:
4043 case FLOAT_TRUNCATE
:
4044 *total
= mips_cost
->fp_add
;
4048 if (register_operand (SET_DEST (x
), VOIDmode
)
4049 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4051 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4061 /* Implement TARGET_ADDRESS_COST. */
4064 mips_address_cost (rtx addr
, enum machine_mode mode
,
4065 addr_space_t as ATTRIBUTE_UNUSED
,
4066 bool speed ATTRIBUTE_UNUSED
)
4068 return mips_address_insns (addr
, mode
, false);
4071 /* Information about a single instruction in a multi-instruction
4073 struct mips_multi_member
{
4074 /* True if this is a label, false if it is code. */
4077 /* The output_asm_insn format of the instruction. */
4080 /* The operands to the instruction. */
4081 rtx operands
[MAX_RECOG_OPERANDS
];
4083 typedef struct mips_multi_member mips_multi_member
;
4085 /* The instructions that make up the current multi-insn sequence. */
4086 static vec
<mips_multi_member
> mips_multi_members
;
4088 /* How many instructions (as opposed to labels) are in the current
4089 multi-insn sequence. */
4090 static unsigned int mips_multi_num_insns
;
4092 /* Start a new multi-insn sequence. */
4095 mips_multi_start (void)
4097 mips_multi_members
.truncate (0);
4098 mips_multi_num_insns
= 0;
4101 /* Add a new, uninitialized member to the current multi-insn sequence. */
4103 static struct mips_multi_member
*
4104 mips_multi_add (void)
4106 mips_multi_member empty
;
4107 return mips_multi_members
.safe_push (empty
);
4110 /* Add a normal insn with the given asm format to the current multi-insn
4111 sequence. The other arguments are a null-terminated list of operands. */
4114 mips_multi_add_insn (const char *format
, ...)
4116 struct mips_multi_member
*member
;
4121 member
= mips_multi_add ();
4122 member
->is_label_p
= false;
4123 member
->format
= format
;
4124 va_start (ap
, format
);
4126 while ((op
= va_arg (ap
, rtx
)))
4127 member
->operands
[i
++] = op
;
4129 mips_multi_num_insns
++;
4132 /* Add the given label definition to the current multi-insn sequence.
4133 The definition should include the colon. */
4136 mips_multi_add_label (const char *label
)
4138 struct mips_multi_member
*member
;
4140 member
= mips_multi_add ();
4141 member
->is_label_p
= true;
4142 member
->format
= label
;
4145 /* Return the index of the last member of the current multi-insn sequence. */
4148 mips_multi_last_index (void)
4150 return mips_multi_members
.length () - 1;
4153 /* Add a copy of an existing instruction to the current multi-insn
4154 sequence. I is the index of the instruction that should be copied. */
4157 mips_multi_copy_insn (unsigned int i
)
4159 struct mips_multi_member
*member
;
4161 member
= mips_multi_add ();
4162 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4163 gcc_assert (!member
->is_label_p
);
4166 /* Change the operand of an existing instruction in the current
4167 multi-insn sequence. I is the index of the instruction,
4168 OP is the index of the operand, and X is the new value. */
4171 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4173 mips_multi_members
[i
].operands
[op
] = x
;
4176 /* Write out the asm code for the current multi-insn sequence. */
4179 mips_multi_write (void)
4181 struct mips_multi_member
*member
;
4184 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4185 if (member
->is_label_p
)
4186 fprintf (asm_out_file
, "%s\n", member
->format
);
4188 output_asm_insn (member
->format
, member
->operands
);
4191 /* Return one word of double-word value OP, taking into account the fixed
4192 endianness of certain registers. HIGH_P is true to select the high part,
4193 false to select the low part. */
4196 mips_subword (rtx op
, bool high_p
)
4198 unsigned int byte
, offset
;
4199 enum machine_mode mode
;
4201 mode
= GET_MODE (op
);
4202 if (mode
== VOIDmode
)
4203 mode
= TARGET_64BIT
? TImode
: DImode
;
4205 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4206 byte
= UNITS_PER_WORD
;
4210 if (FP_REG_RTX_P (op
))
4212 /* Paired FPRs are always ordered little-endian. */
4213 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4214 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4218 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4220 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4223 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4224 SPLIT_TYPE is the condition under which moves should be split. */
4227 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4229 return ((split_type
!= SPLIT_FOR_SPEED
4230 || mips_tuning_info
.fast_mult_zero_zero_p
)
4231 && src
== const0_rtx
4233 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4234 && (ISA_HAS_DSP_MULT
4235 ? ACC_REG_P (REGNO (dest
))
4236 : MD_REG_P (REGNO (dest
))));
4239 /* Return true if a move from SRC to DEST should be split into two.
4240 SPLIT_TYPE describes the split condition. */
4243 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4245 /* Check whether the move can be done using some variant of MULT $0,$0. */
4246 if (mips_mult_move_p (dest
, src
, split_type
))
4249 /* FPR-to-FPR moves can be done in a single instruction, if they're
4251 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4252 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4255 /* Check for floating-point loads and stores. */
4256 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4258 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4260 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4264 /* Otherwise split all multiword moves. */
4265 return size
> UNITS_PER_WORD
;
4268 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4269 SPLIT_TYPE describes the split condition. */
4272 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4276 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4277 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4279 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4280 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4281 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4282 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4283 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4284 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4285 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4286 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4287 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4288 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4289 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4290 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4291 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4292 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4296 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4298 low_dest
= mips_subword (dest
, false);
4299 mips_emit_move (low_dest
, mips_subword (src
, false));
4301 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4303 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4305 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4307 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4309 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4311 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4315 /* The operation can be split into two normal moves. Decide in
4316 which order to do them. */
4317 low_dest
= mips_subword (dest
, false);
4318 if (REG_P (low_dest
)
4319 && reg_overlap_mentioned_p (low_dest
, src
))
4321 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4322 mips_emit_move (low_dest
, mips_subword (src
, false));
4326 mips_emit_move (low_dest
, mips_subword (src
, false));
4327 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4332 /* Return the split type for instruction INSN. */
4334 static enum mips_split_type
4335 mips_insn_split_type (rtx insn
)
4337 basic_block bb
= BLOCK_FOR_INSN (insn
);
4340 if (optimize_bb_for_speed_p (bb
))
4341 return SPLIT_FOR_SPEED
;
4343 return SPLIT_FOR_SIZE
;
4345 /* Once CFG information has been removed, we should trust the optimization
4346 decisions made by previous passes and only split where necessary. */
4347 return SPLIT_IF_NECESSARY
;
4350 /* Return true if a move from SRC to DEST in INSN should be split. */
4353 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4355 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4358 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4362 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4364 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4367 /* Return the appropriate instructions to move SRC into DEST. Assume
4368 that SRC is operand 1 and DEST is operand 0. */
4371 mips_output_move (rtx dest
, rtx src
)
4373 enum rtx_code dest_code
, src_code
;
4374 enum machine_mode mode
;
4375 enum mips_symbol_type symbol_type
;
4378 dest_code
= GET_CODE (dest
);
4379 src_code
= GET_CODE (src
);
4380 mode
= GET_MODE (dest
);
4381 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4383 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4386 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4387 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4389 if (dest_code
== REG
)
4391 if (GP_REG_P (REGNO (dest
)))
4392 return "move\t%0,%z1";
4394 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4396 if (ISA_HAS_DSP_MULT
)
4397 return "mult\t%q0,%.,%.";
4399 return "mult\t%.,%.";
4402 /* Moves to HI are handled by special .md insns. */
4403 if (REGNO (dest
) == LO_REGNUM
)
4406 if (DSP_ACC_REG_P (REGNO (dest
)))
4408 static char retval
[] = "mt__\t%z1,%q0";
4410 retval
[2] = reg_names
[REGNO (dest
)][4];
4411 retval
[3] = reg_names
[REGNO (dest
)][5];
4415 if (FP_REG_P (REGNO (dest
)))
4416 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4418 if (ALL_COP_REG_P (REGNO (dest
)))
4420 static char retval
[] = "dmtc_\t%z1,%0";
4422 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4423 return dbl_p
? retval
: retval
+ 1;
4426 if (dest_code
== MEM
)
4427 switch (GET_MODE_SIZE (mode
))
4429 case 1: return "sb\t%z1,%0";
4430 case 2: return "sh\t%z1,%0";
4431 case 4: return "sw\t%z1,%0";
4432 case 8: return "sd\t%z1,%0";
4435 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4437 if (src_code
== REG
)
4439 /* Moves from HI are handled by special .md insns. */
4440 if (REGNO (src
) == LO_REGNUM
)
4442 /* When generating VR4120 or VR4130 code, we use MACC and
4443 DMACC instead of MFLO. This avoids both the normal
4444 MIPS III HI/LO hazards and the errata related to
4447 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4451 if (DSP_ACC_REG_P (REGNO (src
)))
4453 static char retval
[] = "mf__\t%0,%q1";
4455 retval
[2] = reg_names
[REGNO (src
)][4];
4456 retval
[3] = reg_names
[REGNO (src
)][5];
4460 if (FP_REG_P (REGNO (src
)))
4461 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4463 if (ALL_COP_REG_P (REGNO (src
)))
4465 static char retval
[] = "dmfc_\t%0,%1";
4467 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4468 return dbl_p
? retval
: retval
+ 1;
4472 if (src_code
== MEM
)
4473 switch (GET_MODE_SIZE (mode
))
4475 case 1: return "lbu\t%0,%1";
4476 case 2: return "lhu\t%0,%1";
4477 case 4: return "lw\t%0,%1";
4478 case 8: return "ld\t%0,%1";
4481 if (src_code
== CONST_INT
)
4483 /* Don't use the X format for the operand itself, because that
4484 will give out-of-range numbers for 64-bit hosts and 32-bit
4487 return "li\t%0,%1\t\t\t# %X1";
4489 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4492 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4496 if (src_code
== HIGH
)
4497 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4499 if (CONST_GP_P (src
))
4500 return "move\t%0,%1";
4502 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4503 && mips_lo_relocs
[symbol_type
] != 0)
4505 /* A signed 16-bit constant formed by applying a relocation
4506 operator to a symbolic address. */
4507 gcc_assert (!mips_split_p
[symbol_type
]);
4508 return "li\t%0,%R1";
4511 if (symbolic_operand (src
, VOIDmode
))
4513 gcc_assert (TARGET_MIPS16
4514 ? TARGET_MIPS16_TEXT_LOADS
4515 : !TARGET_EXPLICIT_RELOCS
);
4516 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4519 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4521 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4523 if (GET_MODE (dest
) == V2SFmode
)
4524 return "mov.ps\t%0,%1";
4526 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4529 if (dest_code
== MEM
)
4530 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4532 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4534 if (src_code
== MEM
)
4535 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4537 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4539 static char retval
[] = "l_c_\t%0,%1";
4541 retval
[1] = (dbl_p
? 'd' : 'w');
4542 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4545 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4547 static char retval
[] = "s_c_\t%1,%0";
4549 retval
[1] = (dbl_p
? 'd' : 'w');
4550 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4556 /* Return true if CMP1 is a suitable second operand for integer ordering
4557 test CODE. See also the *sCC patterns in mips.md. */
4560 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4566 return reg_or_0_operand (cmp1
, VOIDmode
);
4570 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4574 return arith_operand (cmp1
, VOIDmode
);
4577 return sle_operand (cmp1
, VOIDmode
);
4580 return sleu_operand (cmp1
, VOIDmode
);
4587 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4588 integer ordering test *CODE, or if an equivalent combination can
4589 be formed by adjusting *CODE and *CMP1. When returning true, update
4590 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4594 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4595 enum machine_mode mode
)
4597 HOST_WIDE_INT plus_one
;
4599 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4602 if (CONST_INT_P (*cmp1
))
4606 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4607 if (INTVAL (*cmp1
) < plus_one
)
4610 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4616 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4620 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4631 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4632 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4633 is nonnull, it's OK to set TARGET to the inverse of the result and
4634 flip *INVERT_PTR instead. */
4637 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4638 rtx target
, rtx cmp0
, rtx cmp1
)
4640 enum machine_mode mode
;
4642 /* First see if there is a MIPS instruction that can do this operation.
4643 If not, try doing the same for the inverse operation. If that also
4644 fails, force CMP1 into a register and try again. */
4645 mode
= GET_MODE (cmp0
);
4646 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4647 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4650 enum rtx_code inv_code
= reverse_condition (code
);
4651 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4653 cmp1
= force_reg (mode
, cmp1
);
4654 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4656 else if (invert_ptr
== 0)
4660 inv_target
= mips_force_binary (GET_MODE (target
),
4661 inv_code
, cmp0
, cmp1
);
4662 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4666 *invert_ptr
= !*invert_ptr
;
4667 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4672 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4673 The register will have the same mode as CMP0. */
4676 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4678 if (cmp1
== const0_rtx
)
4681 if (uns_arith_operand (cmp1
, VOIDmode
))
4682 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4683 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4685 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4686 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4689 /* Convert *CODE into a code that can be used in a floating-point
4690 scc instruction (C.cond.fmt). Return true if the values of
4691 the condition code registers will be inverted, with 0 indicating
4692 that the condition holds. */
4695 mips_reversed_fp_cond (enum rtx_code
*code
)
4702 *code
= reverse_condition_maybe_unordered (*code
);
4710 /* Allocate a floating-point condition-code register of mode MODE.
4712 These condition code registers are used for certain kinds
4713 of compound operation, such as compare and branches, vconds,
4714 and built-in functions. At expand time, their use is entirely
4715 controlled by MIPS-specific code and is entirely internal
4716 to these compound operations.
4718 We could (and did in the past) expose condition-code values
4719 as pseudo registers and leave the register allocator to pick
4720 appropriate registers. The problem is that it is not practically
4721 possible for the rtl optimizers to guarantee that no spills will
4722 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4723 therefore need spill and reload sequences to handle the worst case.
4725 Although such sequences do exist, they are very expensive and are
4726 not something we'd want to use. This is especially true of CCV2 and
4727 CCV4, where all the shuffling would greatly outweigh whatever benefit
4728 the vectorization itself provides.
4730 The main benefit of having more than one condition-code register
4731 is to allow the pipelining of operations, especially those involving
4732 comparisons and conditional moves. We don't really expect the
4733 registers to be live for long periods, and certainly never want
4734 them to be live across calls.
4736 Also, there should be no penalty attached to using all the available
4737 registers. They are simply bits in the same underlying FPU control
4740 We therefore expose the hardware registers from the outset and use
4741 a simple round-robin allocation scheme. */
4744 mips_allocate_fcc (enum machine_mode mode
)
4746 unsigned int regno
, count
;
4748 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4752 else if (mode
== CCV2mode
)
4754 else if (mode
== CCV4mode
)
4759 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4760 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4761 cfun
->machine
->next_fcc
= 0;
4762 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4763 cfun
->machine
->next_fcc
+= count
;
4764 return gen_rtx_REG (mode
, regno
);
4767 /* Convert a comparison into something that can be used in a branch or
4768 conditional move. On entry, *OP0 and *OP1 are the values being
4769 compared and *CODE is the code used to compare them.
4771 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4772 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4773 otherwise any standard branch condition can be used. The standard branch
4776 - EQ or NE between two registers.
4777 - any comparison between a register and zero. */
4780 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4785 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4787 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4789 else if (*code
== EQ
|| *code
== NE
)
4793 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4797 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4801 /* The comparison needs a separate scc instruction. Store the
4802 result of the scc in *OP0 and compare it against zero. */
4803 bool invert
= false;
4804 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4805 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4806 *code
= (invert
? EQ
: NE
);
4810 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4812 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4813 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4819 enum rtx_code cmp_code
;
4821 /* Floating-point tests use a separate C.cond.fmt comparison to
4822 set a condition code register. The branch or conditional move
4823 will then compare that register against zero.
4825 Set CMP_CODE to the code of the comparison instruction and
4826 *CODE to the code that the branch or move should use. */
4828 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4830 ? mips_allocate_fcc (CCmode
)
4831 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4833 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4837 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4838 and OPERAND[3]. Store the result in OPERANDS[0].
4840 On 64-bit targets, the mode of the comparison and target will always be
4841 SImode, thus possibly narrower than that of the comparison's operands. */
4844 mips_expand_scc (rtx operands
[])
4846 rtx target
= operands
[0];
4847 enum rtx_code code
= GET_CODE (operands
[1]);
4848 rtx op0
= operands
[2];
4849 rtx op1
= operands
[3];
4851 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4853 if (code
== EQ
|| code
== NE
)
4856 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4857 mips_emit_binary (code
, target
, op0
, op1
);
4860 rtx zie
= mips_zero_if_equal (op0
, op1
);
4861 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4865 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4868 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4869 CODE and jump to OPERANDS[3] if the condition holds. */
4872 mips_expand_conditional_branch (rtx
*operands
)
4874 enum rtx_code code
= GET_CODE (operands
[0]);
4875 rtx op0
= operands
[1];
4876 rtx op1
= operands
[2];
4879 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4880 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4881 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4886 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4887 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4890 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4891 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4896 reversed_p
= mips_reversed_fp_cond (&cond
);
4897 cmp_result
= mips_allocate_fcc (CCV2mode
);
4898 emit_insn (gen_scc_ps (cmp_result
,
4899 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4901 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4904 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4908 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4909 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4912 mips_expand_conditional_move (rtx
*operands
)
4915 enum rtx_code code
= GET_CODE (operands
[1]);
4916 rtx op0
= XEXP (operands
[1], 0);
4917 rtx op1
= XEXP (operands
[1], 1);
4919 mips_emit_compare (&code
, &op0
, &op1
, true);
4920 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4921 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4922 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4923 operands
[2], operands
[3])));
4926 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4929 mips_expand_conditional_trap (rtx comparison
)
4932 enum machine_mode mode
;
4935 /* MIPS conditional trap instructions don't have GT or LE flavors,
4936 so we must swap the operands and convert to LT and GE respectively. */
4937 code
= GET_CODE (comparison
);
4944 code
= swap_condition (code
);
4945 op0
= XEXP (comparison
, 1);
4946 op1
= XEXP (comparison
, 0);
4950 op0
= XEXP (comparison
, 0);
4951 op1
= XEXP (comparison
, 1);
4955 mode
= GET_MODE (XEXP (comparison
, 0));
4956 op0
= force_reg (mode
, op0
);
4957 if (!arith_operand (op1
, mode
))
4958 op1
= force_reg (mode
, op1
);
4960 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4961 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4965 /* Initialize *CUM for a call to a function of type FNTYPE. */
4968 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4970 memset (cum
, 0, sizeof (*cum
));
4971 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4972 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4975 /* Fill INFO with information about a single argument. CUM is the
4976 cumulative state for earlier arguments. MODE is the mode of this
4977 argument and TYPE is its type (if known). NAMED is true if this
4978 is a named (fixed) argument rather than a variable one. */
4981 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4982 enum machine_mode mode
, const_tree type
, bool named
)
4984 bool doubleword_aligned_p
;
4985 unsigned int num_bytes
, num_words
, max_regs
;
4987 /* Work out the size of the argument. */
4988 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4989 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4991 /* Decide whether it should go in a floating-point register, assuming
4992 one is free. Later code checks for availability.
4994 The checks against UNITS_PER_FPVALUE handle the soft-float and
4995 single-float cases. */
4999 /* The EABI conventions have traditionally been defined in terms
5000 of TYPE_MODE, regardless of the actual type. */
5001 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5002 || mode
== V2SFmode
)
5003 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5008 /* Only leading floating-point scalars are passed in
5009 floating-point registers. We also handle vector floats the same
5010 say, which is OK because they are not covered by the standard ABI. */
5011 info
->fpr_p
= (!cum
->gp_reg_found
5012 && cum
->arg_number
< 2
5014 || SCALAR_FLOAT_TYPE_P (type
)
5015 || VECTOR_FLOAT_TYPE_P (type
))
5016 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5017 || mode
== V2SFmode
)
5018 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5023 /* Scalar, complex and vector floating-point types are passed in
5024 floating-point registers, as long as this is a named rather
5025 than a variable argument. */
5026 info
->fpr_p
= (named
5027 && (type
== 0 || FLOAT_TYPE_P (type
))
5028 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5029 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5030 || mode
== V2SFmode
)
5031 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5033 /* ??? According to the ABI documentation, the real and imaginary
5034 parts of complex floats should be passed in individual registers.
5035 The real and imaginary parts of stack arguments are supposed
5036 to be contiguous and there should be an extra word of padding
5039 This has two problems. First, it makes it impossible to use a
5040 single "void *" va_list type, since register and stack arguments
5041 are passed differently. (At the time of writing, MIPSpro cannot
5042 handle complex float varargs correctly.) Second, it's unclear
5043 what should happen when there is only one register free.
5045 For now, we assume that named complex floats should go into FPRs
5046 if there are two FPRs free, otherwise they should be passed in the
5047 same way as a struct containing two floats. */
5049 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5050 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5052 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5053 info
->fpr_p
= false;
5063 /* See whether the argument has doubleword alignment. */
5064 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5067 /* Set REG_OFFSET to the register count we're interested in.
5068 The EABI allocates the floating-point registers separately,
5069 but the other ABIs allocate them like integer registers. */
5070 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5074 /* Advance to an even register if the argument is doubleword-aligned. */
5075 if (doubleword_aligned_p
)
5076 info
->reg_offset
+= info
->reg_offset
& 1;
5078 /* Work out the offset of a stack argument. */
5079 info
->stack_offset
= cum
->stack_words
;
5080 if (doubleword_aligned_p
)
5081 info
->stack_offset
+= info
->stack_offset
& 1;
5083 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5085 /* Partition the argument between registers and stack. */
5086 info
->reg_words
= MIN (num_words
, max_regs
);
5087 info
->stack_words
= num_words
- info
->reg_words
;
5090 /* INFO describes a register argument that has the normal format for the
5091 argument's mode. Return the register it uses, assuming that FPRs are
5092 available if HARD_FLOAT_P. */
5095 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5097 if (!info
->fpr_p
|| !hard_float_p
)
5098 return GP_ARG_FIRST
+ info
->reg_offset
;
5099 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5100 /* In o32, the second argument is always passed in $f14
5101 for TARGET_DOUBLE_FLOAT, regardless of whether the
5102 first argument was a word or doubleword. */
5103 return FP_ARG_FIRST
+ 2;
5105 return FP_ARG_FIRST
+ info
->reg_offset
;
5108 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5111 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5113 return !TARGET_OLDABI
;
5116 /* Implement TARGET_FUNCTION_ARG. */
5119 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5120 const_tree type
, bool named
)
5122 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5123 struct mips_arg_info info
;
5125 /* We will be called with a mode of VOIDmode after the last argument
5126 has been seen. Whatever we return will be passed to the call expander.
5127 If we need a MIPS16 fp_code, return a REG with the code stored as
5129 if (mode
== VOIDmode
)
5131 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5132 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5137 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5139 /* Return straight away if the whole argument is passed on the stack. */
5140 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5143 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5144 contains a double in its entirety, then that 64-bit chunk is passed
5145 in a floating-point register. */
5147 && TARGET_HARD_FLOAT
5150 && TREE_CODE (type
) == RECORD_TYPE
5151 && TYPE_SIZE_UNIT (type
)
5152 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5156 /* First check to see if there is any such field. */
5157 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5158 if (TREE_CODE (field
) == FIELD_DECL
5159 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5160 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5161 && tree_fits_shwi_p (bit_position (field
))
5162 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5167 /* Now handle the special case by returning a PARALLEL
5168 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5169 chunks are passed in registers. */
5171 HOST_WIDE_INT bitpos
;
5174 /* assign_parms checks the mode of ENTRY_PARM, so we must
5175 use the actual mode here. */
5176 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5179 field
= TYPE_FIELDS (type
);
5180 for (i
= 0; i
< info
.reg_words
; i
++)
5184 for (; field
; field
= DECL_CHAIN (field
))
5185 if (TREE_CODE (field
) == FIELD_DECL
5186 && int_bit_position (field
) >= bitpos
)
5190 && int_bit_position (field
) == bitpos
5191 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5192 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5193 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5195 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5198 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5199 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5201 bitpos
+= BITS_PER_WORD
;
5207 /* Handle the n32/n64 conventions for passing complex floating-point
5208 arguments in FPR pairs. The real part goes in the lower register
5209 and the imaginary part goes in the upper register. */
5212 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5215 enum machine_mode inner
;
5218 inner
= GET_MODE_INNER (mode
);
5219 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5220 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5222 /* Real part in registers, imaginary part on stack. */
5223 gcc_assert (info
.stack_words
== info
.reg_words
);
5224 return gen_rtx_REG (inner
, regno
);
5228 gcc_assert (info
.stack_words
== 0);
5229 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5230 gen_rtx_REG (inner
, regno
),
5232 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5234 regno
+ info
.reg_words
/ 2),
5235 GEN_INT (GET_MODE_SIZE (inner
)));
5236 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5240 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5243 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5246 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5247 const_tree type
, bool named
)
5249 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5250 struct mips_arg_info info
;
5252 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5255 cum
->gp_reg_found
= true;
5257 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5258 an explanation of what this code does. It assumes that we're using
5259 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5261 if (cum
->arg_number
< 2 && info
.fpr_p
)
5262 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5264 /* Advance the register count. This has the effect of setting
5265 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5266 argument required us to skip the final GPR and pass the whole
5267 argument on the stack. */
5268 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5269 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5270 else if (info
.reg_words
> 0)
5271 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5273 /* Advance the stack word count. */
5274 if (info
.stack_words
> 0)
5275 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5280 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5283 mips_arg_partial_bytes (cumulative_args_t cum
,
5284 enum machine_mode mode
, tree type
, bool named
)
5286 struct mips_arg_info info
;
5288 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5289 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5292 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5293 least PARM_BOUNDARY bits of alignment, but will be given anything up
5294 to STACK_BOUNDARY bits if the type requires it. */
5297 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5299 unsigned int alignment
;
5301 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5302 if (alignment
< PARM_BOUNDARY
)
5303 alignment
= PARM_BOUNDARY
;
5304 if (alignment
> STACK_BOUNDARY
)
5305 alignment
= STACK_BOUNDARY
;
5309 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5310 upward rather than downward. In other words, return true if the
5311 first byte of the stack slot has useful data, false if the last
5315 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5317 /* On little-endian targets, the first byte of every stack argument
5318 is passed in the first byte of the stack slot. */
5319 if (!BYTES_BIG_ENDIAN
)
5322 /* Otherwise, integral types are padded downward: the last byte of a
5323 stack argument is passed in the last byte of the stack slot. */
5325 ? (INTEGRAL_TYPE_P (type
)
5326 || POINTER_TYPE_P (type
)
5327 || FIXED_POINT_TYPE_P (type
))
5328 : (SCALAR_INT_MODE_P (mode
)
5329 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5332 /* Big-endian o64 pads floating-point arguments downward. */
5333 if (mips_abi
== ABI_O64
)
5334 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5337 /* Other types are padded upward for o32, o64, n32 and n64. */
5338 if (mips_abi
!= ABI_EABI
)
5341 /* Arguments smaller than a stack slot are padded downward. */
5342 if (mode
!= BLKmode
)
5343 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5345 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5348 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5349 if the least significant byte of the register has useful data. Return
5350 the opposite if the most significant byte does. */
5353 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5355 /* No shifting is required for floating-point arguments. */
5356 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5357 return !BYTES_BIG_ENDIAN
;
5359 /* Otherwise, apply the same padding to register arguments as we do
5360 to stack arguments. */
5361 return mips_pad_arg_upward (mode
, type
);
5364 /* Return nonzero when an argument must be passed by reference. */
5367 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5368 enum machine_mode mode
, const_tree type
,
5369 bool named ATTRIBUTE_UNUSED
)
5371 if (mips_abi
== ABI_EABI
)
5375 /* ??? How should SCmode be handled? */
5376 if (mode
== DImode
|| mode
== DFmode
5377 || mode
== DQmode
|| mode
== UDQmode
5378 || mode
== DAmode
|| mode
== UDAmode
)
5381 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5382 return size
== -1 || size
> UNITS_PER_WORD
;
5386 /* If we have a variable-sized parameter, we have no choice. */
5387 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5391 /* Implement TARGET_CALLEE_COPIES. */
5394 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5395 enum machine_mode mode ATTRIBUTE_UNUSED
,
5396 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5398 return mips_abi
== ABI_EABI
&& named
;
5401 /* See whether VALTYPE is a record whose fields should be returned in
5402 floating-point registers. If so, return the number of fields and
5403 list them in FIELDS (which should have two elements). Return 0
5406 For n32 & n64, a structure with one or two fields is returned in
5407 floating-point registers as long as every field has a floating-point
5411 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5419 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5423 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5425 if (TREE_CODE (field
) != FIELD_DECL
)
5428 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5434 fields
[i
++] = field
;
5439 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5440 a value in the most significant part of $2/$3 if:
5442 - the target is big-endian;
5444 - the value has a structure or union type (we generalize this to
5445 cover aggregates from other languages too); and
5447 - the structure is not returned in floating-point registers. */
5450 mips_return_in_msb (const_tree valtype
)
5454 return (TARGET_NEWABI
5455 && TARGET_BIG_ENDIAN
5456 && AGGREGATE_TYPE_P (valtype
)
5457 && mips_fpr_return_fields (valtype
, fields
) == 0);
5460 /* Return true if the function return value MODE will get returned in a
5461 floating-point register. */
5464 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5466 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5468 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5469 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5472 /* Return the representation of an FPR return register when the
5473 value being returned in FP_RETURN has mode VALUE_MODE and the
5474 return type itself has mode TYPE_MODE. On NewABI targets,
5475 the two modes may be different for structures like:
5477 struct __attribute__((packed)) foo { float f; }
5479 where we return the SFmode value of "f" in FP_RETURN, but where
5480 the structure itself has mode BLKmode. */
5483 mips_return_fpr_single (enum machine_mode type_mode
,
5484 enum machine_mode value_mode
)
5488 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5489 if (type_mode
!= value_mode
)
5491 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5492 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5497 /* Return a composite value in a pair of floating-point registers.
5498 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5499 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5502 For n32 & n64, $f0 always holds the first value and $f2 the second.
5503 Otherwise the values are packed together as closely as possible. */
5506 mips_return_fpr_pair (enum machine_mode mode
,
5507 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5508 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5512 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5513 return gen_rtx_PARALLEL
5516 gen_rtx_EXPR_LIST (VOIDmode
,
5517 gen_rtx_REG (mode1
, FP_RETURN
),
5519 gen_rtx_EXPR_LIST (VOIDmode
,
5520 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5521 GEN_INT (offset2
))));
5525 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5526 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5527 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5530 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5531 enum machine_mode mode
)
5539 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5540 func
= fn_decl_or_type
;
5544 mode
= TYPE_MODE (valtype
);
5545 unsigned_p
= TYPE_UNSIGNED (valtype
);
5547 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5548 return values, promote the mode here too. */
5549 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5551 /* Handle structures whose fields are returned in $f0/$f2. */
5552 switch (mips_fpr_return_fields (valtype
, fields
))
5555 return mips_return_fpr_single (mode
,
5556 TYPE_MODE (TREE_TYPE (fields
[0])));
5559 return mips_return_fpr_pair (mode
,
5560 TYPE_MODE (TREE_TYPE (fields
[0])),
5561 int_byte_position (fields
[0]),
5562 TYPE_MODE (TREE_TYPE (fields
[1])),
5563 int_byte_position (fields
[1]));
5566 /* If a value is passed in the most significant part of a register, see
5567 whether we have to round the mode up to a whole number of words. */
5568 if (mips_return_in_msb (valtype
))
5570 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5571 if (size
% UNITS_PER_WORD
!= 0)
5573 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5574 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5578 /* For EABI, the class of return register depends entirely on MODE.
5579 For example, "struct { some_type x; }" and "union { some_type x; }"
5580 are returned in the same way as a bare "some_type" would be.
5581 Other ABIs only use FPRs for scalar, complex or vector types. */
5582 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5583 return gen_rtx_REG (mode
, GP_RETURN
);
5588 /* Handle long doubles for n32 & n64. */
5590 return mips_return_fpr_pair (mode
,
5592 DImode
, GET_MODE_SIZE (mode
) / 2);
5594 if (mips_return_mode_in_fpr_p (mode
))
5596 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5597 return mips_return_fpr_pair (mode
,
5598 GET_MODE_INNER (mode
), 0,
5599 GET_MODE_INNER (mode
),
5600 GET_MODE_SIZE (mode
) / 2);
5602 return gen_rtx_REG (mode
, FP_RETURN
);
5606 return gen_rtx_REG (mode
, GP_RETURN
);
5609 /* Implement TARGET_FUNCTION_VALUE. */
5612 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5613 bool outgoing ATTRIBUTE_UNUSED
)
5615 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5618 /* Implement TARGET_LIBCALL_VALUE. */
5621 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5623 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5626 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5628 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5629 Currently, R2 and F0 are only implemented here (C has no complex type). */
5632 mips_function_value_regno_p (const unsigned int regno
)
5634 if (regno
== GP_RETURN
5635 || regno
== FP_RETURN
5636 || (LONG_DOUBLE_TYPE_SIZE
== 128
5637 && FP_RETURN
!= GP_RETURN
5638 && regno
== FP_RETURN
+ 2))
5644 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5645 all BLKmode objects are returned in memory. Under the n32, n64
5646 and embedded ABIs, small structures are returned in a register.
5647 Objects with varying size must still be returned in memory, of
5651 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5653 return (TARGET_OLDABI
5654 ? TYPE_MODE (type
) == BLKmode
5655 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5658 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5661 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5662 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5665 CUMULATIVE_ARGS local_cum
;
5666 int gp_saved
, fp_saved
;
5668 /* The caller has advanced CUM up to, but not beyond, the last named
5669 argument. Advance a local copy of CUM past the last "real" named
5670 argument, to find out how many registers are left over. */
5671 local_cum
= *get_cumulative_args (cum
);
5672 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5675 /* Found out how many registers we need to save. */
5676 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5677 fp_saved
= (EABI_FLOAT_VARARGS_P
5678 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5687 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5688 REG_PARM_STACK_SPACE (cfun
->decl
)
5689 - gp_saved
* UNITS_PER_WORD
);
5690 mem
= gen_frame_mem (BLKmode
, ptr
);
5691 set_mem_alias_set (mem
, get_varargs_alias_set ());
5693 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5698 /* We can't use move_block_from_reg, because it will use
5700 enum machine_mode mode
;
5703 /* Set OFF to the offset from virtual_incoming_args_rtx of
5704 the first float register. The FP save area lies below
5705 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5706 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5707 off
-= fp_saved
* UNITS_PER_FPREG
;
5709 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5711 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5712 i
+= MAX_FPRS_PER_FMT
)
5716 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5717 mem
= gen_frame_mem (mode
, ptr
);
5718 set_mem_alias_set (mem
, get_varargs_alias_set ());
5719 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5720 off
+= UNITS_PER_HWFPVALUE
;
5724 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5725 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5726 + fp_saved
* UNITS_PER_FPREG
);
5729 /* Implement TARGET_BUILTIN_VA_LIST. */
5732 mips_build_builtin_va_list (void)
5734 if (EABI_FLOAT_VARARGS_P
)
5736 /* We keep 3 pointers, and two offsets.
5738 Two pointers are to the overflow area, which starts at the CFA.
5739 One of these is constant, for addressing into the GPR save area
5740 below it. The other is advanced up the stack through the
5743 The third pointer is to the bottom of the GPR save area.
5744 Since the FPR save area is just below it, we can address
5745 FPR slots off this pointer.
5747 We also keep two one-byte offsets, which are to be subtracted
5748 from the constant pointers to yield addresses in the GPR and
5749 FPR save areas. These are downcounted as float or non-float
5750 arguments are used, and when they get to zero, the argument
5751 must be obtained from the overflow region. */
5752 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5755 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5757 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5758 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5760 f_gtop
= build_decl (BUILTINS_LOCATION
,
5761 FIELD_DECL
, get_identifier ("__gpr_top"),
5763 f_ftop
= build_decl (BUILTINS_LOCATION
,
5764 FIELD_DECL
, get_identifier ("__fpr_top"),
5766 f_goff
= build_decl (BUILTINS_LOCATION
,
5767 FIELD_DECL
, get_identifier ("__gpr_offset"),
5768 unsigned_char_type_node
);
5769 f_foff
= build_decl (BUILTINS_LOCATION
,
5770 FIELD_DECL
, get_identifier ("__fpr_offset"),
5771 unsigned_char_type_node
);
5772 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5773 warn on every user file. */
5774 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5775 array
= build_array_type (unsigned_char_type_node
,
5776 build_index_type (index
));
5777 f_res
= build_decl (BUILTINS_LOCATION
,
5778 FIELD_DECL
, get_identifier ("__reserved"), array
);
5780 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5781 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5782 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5783 DECL_FIELD_CONTEXT (f_goff
) = record
;
5784 DECL_FIELD_CONTEXT (f_foff
) = record
;
5785 DECL_FIELD_CONTEXT (f_res
) = record
;
5787 TYPE_FIELDS (record
) = f_ovfl
;
5788 DECL_CHAIN (f_ovfl
) = f_gtop
;
5789 DECL_CHAIN (f_gtop
) = f_ftop
;
5790 DECL_CHAIN (f_ftop
) = f_goff
;
5791 DECL_CHAIN (f_goff
) = f_foff
;
5792 DECL_CHAIN (f_foff
) = f_res
;
5794 layout_type (record
);
5798 /* Otherwise, we use 'void *'. */
5799 return ptr_type_node
;
5802 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5805 mips_va_start (tree valist
, rtx nextarg
)
5807 if (EABI_FLOAT_VARARGS_P
)
5809 const CUMULATIVE_ARGS
*cum
;
5810 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5811 tree ovfl
, gtop
, ftop
, goff
, foff
;
5813 int gpr_save_area_size
;
5814 int fpr_save_area_size
;
5817 cum
= &crtl
->args
.info
;
5819 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5821 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5823 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5824 f_gtop
= DECL_CHAIN (f_ovfl
);
5825 f_ftop
= DECL_CHAIN (f_gtop
);
5826 f_goff
= DECL_CHAIN (f_ftop
);
5827 f_foff
= DECL_CHAIN (f_goff
);
5829 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5831 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5833 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5835 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5837 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5840 /* Emit code to initialize OVFL, which points to the next varargs
5841 stack argument. CUM->STACK_WORDS gives the number of stack
5842 words used by named arguments. */
5843 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5844 if (cum
->stack_words
> 0)
5845 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5846 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5847 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5849 /* Emit code to initialize GTOP, the top of the GPR save area. */
5850 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5851 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5852 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5854 /* Emit code to initialize FTOP, the top of the FPR save area.
5855 This address is gpr_save_area_bytes below GTOP, rounded
5856 down to the next fp-aligned boundary. */
5857 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5858 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5859 fpr_offset
&= -UNITS_PER_FPVALUE
;
5861 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5862 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5863 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5865 /* Emit code to initialize GOFF, the offset from GTOP of the
5866 next GPR argument. */
5867 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5868 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5869 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5871 /* Likewise emit code to initialize FOFF, the offset from FTOP
5872 of the next FPR argument. */
5873 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5874 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5875 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5879 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
5880 std_expand_builtin_va_start (valist
, nextarg
);
5884 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5888 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5891 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
5892 unsigned HOST_WIDE_INT align
, boundary
;
5895 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5897 type
= build_pointer_type (type
);
5899 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
5900 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
5902 /* When we align parameter on stack for caller, if the parameter
5903 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5904 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5905 here with caller. */
5906 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
5907 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
5909 boundary
/= BITS_PER_UNIT
;
5911 /* Hoist the valist value into a temporary for the moment. */
5912 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
5914 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5915 requires greater alignment, we must perform dynamic alignment. */
5916 if (boundary
> align
)
5918 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5919 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
5920 gimplify_and_add (t
, pre_p
);
5922 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5923 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
5925 build_int_cst (TREE_TYPE (valist
), -boundary
)));
5926 gimplify_and_add (t
, pre_p
);
5931 /* If the actual alignment is less than the alignment of the type,
5932 adjust the type accordingly so that we don't assume strict alignment
5933 when dereferencing the pointer. */
5934 boundary
*= BITS_PER_UNIT
;
5935 if (boundary
< TYPE_ALIGN (type
))
5937 type
= build_variant_type_copy (type
);
5938 TYPE_ALIGN (type
) = boundary
;
5941 /* Compute the rounded size of the type. */
5942 type_size
= size_in_bytes (type
);
5943 rounded_size
= round_up (type_size
, align
);
5945 /* Reduce rounded_size so it's sharable with the postqueue. */
5946 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5950 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
5952 /* Small args are padded downward. */
5953 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
5954 rounded_size
, size_int (align
));
5955 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
5956 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
5957 addr
= fold_build_pointer_plus (addr
, t
);
5960 /* Compute new value for AP. */
5961 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
5962 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
5963 gimplify_and_add (t
, pre_p
);
5965 addr
= fold_convert (build_pointer_type (type
), addr
);
5968 addr
= build_va_arg_indirect_ref (addr
);
5970 return build_va_arg_indirect_ref (addr
);
5973 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5976 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5982 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5984 type
= build_pointer_type (type
);
5986 if (!EABI_FLOAT_VARARGS_P
)
5987 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5990 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5991 tree ovfl
, top
, off
, align
;
5992 HOST_WIDE_INT size
, rsize
, osize
;
5995 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5996 f_gtop
= DECL_CHAIN (f_ovfl
);
5997 f_ftop
= DECL_CHAIN (f_gtop
);
5998 f_goff
= DECL_CHAIN (f_ftop
);
5999 f_foff
= DECL_CHAIN (f_goff
);
6003 TOP be the top of the GPR or FPR save area;
6004 OFF be the offset from TOP of the next register;
6005 ADDR_RTX be the address of the argument;
6006 SIZE be the number of bytes in the argument type;
6007 RSIZE be the number of bytes used to store the argument
6008 when it's in the register save area; and
6009 OSIZE be the number of bytes used to store it when it's
6010 in the stack overflow area.
6012 The code we want is:
6014 1: off &= -rsize; // round down
6017 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6022 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6023 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6027 [1] and [9] can sometimes be optimized away. */
6029 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6031 size
= int_size_in_bytes (type
);
6033 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6034 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6036 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6037 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6038 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6039 unshare_expr (valist
), f_foff
, NULL_TREE
);
6041 /* When va_start saves FPR arguments to the stack, each slot
6042 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6043 argument's precision. */
6044 rsize
= UNITS_PER_HWFPVALUE
;
6046 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6047 (= PARM_BOUNDARY bits). This can be different from RSIZE
6050 (1) On 32-bit targets when TYPE is a structure such as:
6052 struct s { float f; };
6054 Such structures are passed in paired FPRs, so RSIZE
6055 will be 8 bytes. However, the structure only takes
6056 up 4 bytes of memory, so OSIZE will only be 4.
6058 (2) In combinations such as -mgp64 -msingle-float
6059 -fshort-double. Doubles passed in registers will then take
6060 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6061 stack take up UNITS_PER_WORD bytes. */
6062 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6066 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6067 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6068 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6069 unshare_expr (valist
), f_goff
, NULL_TREE
);
6070 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6071 if (rsize
> UNITS_PER_WORD
)
6073 /* [1] Emit code for: off &= -rsize. */
6074 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6075 build_int_cst (TREE_TYPE (off
), -rsize
));
6076 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6081 /* [2] Emit code to branch if off == 0. */
6082 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6083 build_int_cst (TREE_TYPE (off
), 0));
6084 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6086 /* [5] Emit code for: off -= rsize. We do this as a form of
6087 post-decrement not available to C. */
6088 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6089 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6091 /* [4] Emit code for:
6092 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6093 t
= fold_convert (sizetype
, t
);
6094 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6095 t
= fold_build_pointer_plus (top
, t
);
6096 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6097 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6098 COND_EXPR_THEN (addr
) = t
;
6100 if (osize
> UNITS_PER_WORD
)
6102 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6103 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6104 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6105 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6106 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6107 unshare_expr (ovfl
), t
);
6112 /* [10, 11] Emit code for:
6113 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6115 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6116 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6117 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6118 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6120 /* String [9] and [10, 11] together. */
6122 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6123 COND_EXPR_ELSE (addr
) = t
;
6125 addr
= fold_convert (build_pointer_type (type
), addr
);
6126 addr
= build_va_arg_indirect_ref (addr
);
6130 addr
= build_va_arg_indirect_ref (addr
);
6135 /* Declare a unique, locally-binding function called NAME, then start
6139 mips_start_unique_function (const char *name
)
6143 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6144 get_identifier (name
),
6145 build_function_type_list (void_type_node
, NULL_TREE
));
6146 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6147 NULL_TREE
, void_type_node
);
6148 TREE_PUBLIC (decl
) = 1;
6149 TREE_STATIC (decl
) = 1;
6151 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
6153 targetm
.asm_out
.unique_section (decl
, 0);
6154 switch_to_section (get_named_section (decl
, NULL
, 0));
6156 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6157 fputs ("\t.hidden\t", asm_out_file
);
6158 assemble_name (asm_out_file
, name
);
6159 putc ('\n', asm_out_file
);
6162 /* Start a definition of function NAME. MIPS16_P indicates whether the
6163 function contains MIPS16 code. */
6166 mips_start_function_definition (const char *name
, bool mips16_p
)
6169 fprintf (asm_out_file
, "\t.set\tmips16\n");
6171 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6173 if (TARGET_MICROMIPS
)
6174 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6175 #ifdef HAVE_GAS_MICROMIPS
6177 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6180 if (!flag_inhibit_size_directive
)
6182 fputs ("\t.ent\t", asm_out_file
);
6183 assemble_name (asm_out_file
, name
);
6184 fputs ("\n", asm_out_file
);
6187 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6189 /* Start the definition proper. */
6190 assemble_name (asm_out_file
, name
);
6191 fputs (":\n", asm_out_file
);
6194 /* End a function definition started by mips_start_function_definition. */
6197 mips_end_function_definition (const char *name
)
6199 if (!flag_inhibit_size_directive
)
6201 fputs ("\t.end\t", asm_out_file
);
6202 assemble_name (asm_out_file
, name
);
6203 fputs ("\n", asm_out_file
);
6207 /* Output a definition of the __mips16_rdhwr function. */
6210 mips_output_mips16_rdhwr (void)
6214 name
= "__mips16_rdhwr";
6215 mips_start_unique_function (name
);
6216 mips_start_function_definition (name
, false);
6217 fprintf (asm_out_file
,
6219 "\t.set\tmips32r2\n"
6220 "\t.set\tnoreorder\n"
6224 mips_end_function_definition (name
);
6227 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6230 mips_ok_for_lazy_binding_p (rtx x
)
6232 return (TARGET_USE_GOT
6233 && GET_CODE (x
) == SYMBOL_REF
6234 && !SYMBOL_REF_BIND_NOW_P (x
)
6235 && !mips_symbol_binds_local_p (x
));
6238 /* Load function address ADDR into register DEST. TYPE is as for
6239 mips_expand_call. Return true if we used an explicit lazy-binding
6243 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6245 /* If we're generating PIC, and this call is to a global function,
6246 try to allow its address to be resolved lazily. This isn't
6247 possible for sibcalls when $gp is call-saved because the value
6248 of $gp on entry to the stub would be our caller's gp, not ours. */
6249 if (TARGET_EXPLICIT_RELOCS
6250 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6251 && mips_ok_for_lazy_binding_p (addr
))
6253 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6254 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6259 mips_emit_move (dest
, addr
);
6264 /* Each locally-defined hard-float MIPS16 function has a local symbol
6265 associated with it. This hash table maps the function symbol (FUNC)
6266 to the local symbol (LOCAL). */
6267 struct GTY(()) mips16_local_alias
{
6271 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6273 /* Hash table callbacks for mips16_local_aliases. */
6276 mips16_local_aliases_hash (const void *entry
)
6278 const struct mips16_local_alias
*alias
;
6280 alias
= (const struct mips16_local_alias
*) entry
;
6281 return htab_hash_string (XSTR (alias
->func
, 0));
6285 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6287 const struct mips16_local_alias
*alias1
, *alias2
;
6289 alias1
= (const struct mips16_local_alias
*) entry1
;
6290 alias2
= (const struct mips16_local_alias
*) entry2
;
6291 return rtx_equal_p (alias1
->func
, alias2
->func
);
6294 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6295 Return a local alias for it, creating a new one if necessary. */
6298 mips16_local_alias (rtx func
)
6300 struct mips16_local_alias
*alias
, tmp_alias
;
6303 /* Create the hash table if this is the first call. */
6304 if (mips16_local_aliases
== NULL
)
6305 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6306 mips16_local_aliases_eq
, NULL
);
6308 /* Look up the function symbol, creating a new entry if need be. */
6309 tmp_alias
.func
= func
;
6310 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6311 gcc_assert (slot
!= NULL
);
6313 alias
= (struct mips16_local_alias
*) *slot
;
6316 const char *func_name
, *local_name
;
6319 /* Create a new SYMBOL_REF for the local symbol. The choice of
6320 __fn_local_* is based on the __fn_stub_* names that we've
6321 traditionally used for the non-MIPS16 stub. */
6322 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6323 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6324 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6325 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6327 /* Create a new structure to represent the mapping. */
6328 alias
= ggc_alloc_mips16_local_alias ();
6330 alias
->local
= local
;
6333 return alias
->local
;
6336 /* A chained list of functions for which mips16_build_call_stub has already
6337 generated a stub. NAME is the name of the function and FP_RET_P is true
6338 if the function returns a value in floating-point registers. */
6339 struct mips16_stub
{
6340 struct mips16_stub
*next
;
6344 static struct mips16_stub
*mips16_stubs
;
6346 /* Return the two-character string that identifies floating-point
6347 return mode MODE in the name of a MIPS16 function stub. */
6350 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6354 else if (mode
== DFmode
)
6356 else if (mode
== SCmode
)
6358 else if (mode
== DCmode
)
6360 else if (mode
== V2SFmode
)
6366 /* Write instructions to move a 32-bit value between general register
6367 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6368 from GPREG to FPREG and 'f' to move in the opposite direction. */
6371 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6373 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6374 reg_names
[gpreg
], reg_names
[fpreg
]);
6377 /* Likewise for 64-bit values. */
6380 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6383 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6384 reg_names
[gpreg
], reg_names
[fpreg
]);
6385 else if (TARGET_FLOAT64
)
6387 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6388 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6389 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6390 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6394 /* Move the least-significant word. */
6395 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6396 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6397 /* ...then the most significant word. */
6398 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6399 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6403 /* Write out code to move floating-point arguments into or out of
6404 general registers. FP_CODE is the code describing which arguments
6405 are present (see the comment above the definition of CUMULATIVE_ARGS
6406 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6409 mips_output_args_xfer (int fp_code
, char direction
)
6411 unsigned int gparg
, fparg
, f
;
6412 CUMULATIVE_ARGS cum
;
6414 /* This code only works for o32 and o64. */
6415 gcc_assert (TARGET_OLDABI
);
6417 mips_init_cumulative_args (&cum
, NULL
);
6419 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6421 enum machine_mode mode
;
6422 struct mips_arg_info info
;
6426 else if ((f
& 3) == 2)
6431 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6432 gparg
= mips_arg_regno (&info
, false);
6433 fparg
= mips_arg_regno (&info
, true);
6436 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6438 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6440 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6444 /* Write a MIPS16 stub for the current function. This stub is used
6445 for functions which take arguments in the floating-point registers.
6446 It is normal-mode code that moves the floating-point arguments
6447 into the general registers and then jumps to the MIPS16 code. */
6450 mips16_build_function_stub (void)
6452 const char *fnname
, *alias_name
, *separator
;
6453 char *secname
, *stubname
;
6458 /* Create the name of the stub, and its unique section. */
6459 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6460 alias
= mips16_local_alias (symbol
);
6462 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6463 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6464 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6465 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6467 /* Build a decl for the stub. */
6468 stubdecl
= build_decl (BUILTINS_LOCATION
,
6469 FUNCTION_DECL
, get_identifier (stubname
),
6470 build_function_type_list (void_type_node
, NULL_TREE
));
6471 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6472 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6473 RESULT_DECL
, NULL_TREE
, void_type_node
);
6475 /* Output a comment. */
6476 fprintf (asm_out_file
, "\t# Stub function for %s (",
6477 current_function_name ());
6479 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6481 fprintf (asm_out_file
, "%s%s", separator
,
6482 (f
& 3) == 1 ? "float" : "double");
6485 fprintf (asm_out_file
, ")\n");
6487 /* Start the function definition. */
6488 assemble_start_function (stubdecl
, stubname
);
6489 mips_start_function_definition (stubname
, false);
6491 /* If generating pic2 code, either set up the global pointer or
6493 if (TARGET_ABICALLS_PIC2
)
6495 if (TARGET_ABSOLUTE_ABICALLS
)
6496 fprintf (asm_out_file
, "\t.option\tpic0\n");
6499 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6500 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6501 target function is. Use a local GOT access when loading the
6502 symbol, to cut down on the number of unnecessary GOT entries
6503 for stubs that aren't needed. */
6504 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6509 /* Load the address of the MIPS16 function into $25. Do this first so
6510 that targets with coprocessor interlocks can use an MFC1 to fill the
6512 output_asm_insn ("la\t%^,%0", &symbol
);
6514 /* Move the arguments from floating-point registers to general registers. */
6515 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6517 /* Jump to the MIPS16 function. */
6518 output_asm_insn ("jr\t%^", NULL
);
6520 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6521 fprintf (asm_out_file
, "\t.option\tpic2\n");
6523 mips_end_function_definition (stubname
);
6525 /* If the linker needs to create a dynamic symbol for the target
6526 function, it will associate the symbol with the stub (which,
6527 unlike the target function, follows the proper calling conventions).
6528 It is therefore useful to have a local alias for the target function,
6529 so that it can still be identified as MIPS16 code. As an optimization,
6530 this symbol can also be used for indirect MIPS16 references from
6531 within this file. */
6532 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6534 switch_to_section (function_section (current_function_decl
));
6537 /* The current function is a MIPS16 function that returns a value in an FPR.
6538 Copy the return value from its soft-float to its hard-float location.
6539 libgcc2 has special non-MIPS16 helper functions for each case. */
6542 mips16_copy_fpr_return_value (void)
6544 rtx fn
, insn
, retval
;
6546 enum machine_mode return_mode
;
6549 return_type
= DECL_RESULT (current_function_decl
);
6550 return_mode
= DECL_MODE (return_type
);
6552 name
= ACONCAT (("__mips16_ret_",
6553 mips16_call_stub_mode_suffix (return_mode
),
6555 fn
= mips16_stub_function (name
);
6557 /* The function takes arguments in $2 (and possibly $3), so calls
6558 to it cannot be lazily bound. */
6559 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6561 /* Model the call as something that takes the GPR return value as
6562 argument and returns an "updated" value. */
6563 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6564 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6565 const0_rtx
, NULL_RTX
, false);
6566 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6569 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6570 RETVAL is the location of the return value, or null if this is
6571 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6572 arguments and FP_CODE is the code built by mips_function_arg;
6573 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6575 There are three alternatives:
6577 - If a stub was needed, emit the call and return the call insn itself.
6579 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6580 to the new target and return null.
6582 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6585 A stub is needed for calls to functions that, in normal mode,
6586 receive arguments in FPRs or return values in FPRs. The stub
6587 copies the arguments from their soft-float positions to their
6588 hard-float positions, calls the real function, then copies the
6589 return value from its hard-float position to its soft-float
6592 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6593 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6594 automatically redirects the JAL to the stub, otherwise the JAL
6595 continues to call FN directly. */
6598 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6602 struct mips16_stub
*l
;
6605 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6606 we were invoked with the -msoft-float option. */
6607 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6610 /* Figure out whether the value might come back in a floating-point
6612 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6614 /* We don't need to do anything if there were no floating-point
6615 arguments and the value will not be returned in a floating-point
6617 if (fp_code
== 0 && !fp_ret_p
)
6620 /* We don't need to do anything if this is a call to a special
6621 MIPS16 support function. */
6623 if (mips16_stub_function_p (fn
))
6626 /* If we're calling a locally-defined MIPS16 function, we know that
6627 it will return values in both the "soft-float" and "hard-float"
6628 registers. There is no need to use a stub to move the latter
6630 if (fp_code
== 0 && mips16_local_function_p (fn
))
6633 /* This code will only work for o32 and o64 abis. The other ABI's
6634 require more sophisticated support. */
6635 gcc_assert (TARGET_OLDABI
);
6637 /* If we're calling via a function pointer, use one of the magic
6638 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6639 Each stub expects the function address to arrive in register $2. */
6640 if (GET_CODE (fn
) != SYMBOL_REF
6641 || !call_insn_operand (fn
, VOIDmode
))
6644 rtx stub_fn
, insn
, addr
;
6647 /* If this is a locally-defined and locally-binding function,
6648 avoid the stub by calling the local alias directly. */
6649 if (mips16_local_function_p (fn
))
6651 *fn_ptr
= mips16_local_alias (fn
);
6655 /* Create a SYMBOL_REF for the libgcc.a function. */
6657 sprintf (buf
, "__mips16_call_stub_%s_%d",
6658 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6661 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6662 stub_fn
= mips16_stub_function (buf
);
6664 /* The function uses $2 as an argument, so calls to it
6665 cannot be lazily bound. */
6666 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6668 /* Load the target function into $2. */
6669 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6670 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6672 /* Emit the call. */
6673 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6674 args_size
, NULL_RTX
, lazy_p
);
6676 /* Tell GCC that this call does indeed use the value of $2. */
6677 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6679 /* If we are handling a floating-point return value, we need to
6680 save $18 in the function prologue. Putting a note on the
6681 call will mean that df_regs_ever_live_p ($18) will be true if the
6682 call is not eliminated, and we can check that in the prologue
6685 CALL_INSN_FUNCTION_USAGE (insn
) =
6686 gen_rtx_EXPR_LIST (VOIDmode
,
6687 gen_rtx_CLOBBER (VOIDmode
,
6688 gen_rtx_REG (word_mode
, 18)),
6689 CALL_INSN_FUNCTION_USAGE (insn
));
6694 /* We know the function we are going to call. If we have already
6695 built a stub, we don't need to do anything further. */
6696 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6697 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6698 if (strcmp (l
->name
, fnname
) == 0)
6703 const char *separator
;
6704 char *secname
, *stubname
;
6705 tree stubid
, stubdecl
;
6708 /* If the function does not return in FPRs, the special stub
6712 If the function does return in FPRs, the stub section is named
6713 .mips16.call.fp.FNNAME
6715 Build a decl for the stub. */
6716 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6718 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6720 stubid
= get_identifier (stubname
);
6721 stubdecl
= build_decl (BUILTINS_LOCATION
,
6722 FUNCTION_DECL
, stubid
,
6723 build_function_type_list (void_type_node
,
6725 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6726 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6727 RESULT_DECL
, NULL_TREE
,
6730 /* Output a comment. */
6731 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6733 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6737 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6739 fprintf (asm_out_file
, "%s%s", separator
,
6740 (f
& 3) == 1 ? "float" : "double");
6743 fprintf (asm_out_file
, ")\n");
6745 /* Start the function definition. */
6746 assemble_start_function (stubdecl
, stubname
);
6747 mips_start_function_definition (stubname
, false);
6751 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6753 /* Create a fake CFA 4 bytes below the stack pointer.
6754 This works around unwinders (like libgcc's) that expect
6755 the CFA for non-signal frames to be unique. */
6756 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6758 /* "Save" $sp in itself so we don't use the fake CFA.
6759 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6760 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6764 /* Load the address of the MIPS16 function into $25. Do this
6765 first so that targets with coprocessor interlocks can use
6766 an MFC1 to fill the delay slot. */
6767 if (TARGET_EXPLICIT_RELOCS
)
6769 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6770 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6773 output_asm_insn ("la\t%^,%0", &fn
);
6776 /* Move the arguments from general registers to floating-point
6778 mips_output_args_xfer (fp_code
, 't');
6782 /* Save the return address in $18 and call the non-MIPS16 function.
6783 The stub's caller knows that $18 might be clobbered, even though
6784 $18 is usually a call-saved register. */
6785 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6786 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6787 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6788 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6790 /* Move the result from floating-point registers to
6791 general registers. */
6792 switch (GET_MODE (retval
))
6795 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6797 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6799 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6800 TARGET_LITTLE_ENDIAN
6801 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6803 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6805 /* On 64-bit targets, complex floats are returned in
6806 a single GPR, such that "sd" on a suitably-aligned
6807 target would store the value correctly. */
6808 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6809 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6810 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6811 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6812 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6813 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6814 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6815 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6816 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6817 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6818 reg_names
[GP_RETURN
],
6819 reg_names
[GP_RETURN
],
6820 reg_names
[GP_RETURN
+ 1]);
6825 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6829 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6830 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6834 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6840 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6841 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6845 /* Jump to the previously-loaded address. */
6846 output_asm_insn ("jr\t%^", NULL
);
6849 #ifdef ASM_DECLARE_FUNCTION_SIZE
6850 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6853 mips_end_function_definition (stubname
);
6855 /* Record this stub. */
6856 l
= XNEW (struct mips16_stub
);
6857 l
->name
= xstrdup (fnname
);
6858 l
->fp_ret_p
= fp_ret_p
;
6859 l
->next
= mips16_stubs
;
6863 /* If we expect a floating-point return value, but we've built a
6864 stub which does not expect one, then we're in trouble. We can't
6865 use the existing stub, because it won't handle the floating-point
6866 value. We can't build a new stub, because the linker won't know
6867 which stub to use for the various calls in this object file.
6868 Fortunately, this case is illegal, since it means that a function
6869 was declared in two different ways in a single compilation. */
6870 if (fp_ret_p
&& !l
->fp_ret_p
)
6871 error ("cannot handle inconsistent calls to %qs", fnname
);
6873 if (retval
== NULL_RTX
)
6874 insn
= gen_call_internal_direct (fn
, args_size
);
6876 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6877 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6879 /* If we are calling a stub which handles a floating-point return
6880 value, we need to arrange to save $18 in the prologue. We do this
6881 by marking the function call as using the register. The prologue
6882 will later see that it is used, and emit code to save it. */
6884 CALL_INSN_FUNCTION_USAGE (insn
) =
6885 gen_rtx_EXPR_LIST (VOIDmode
,
6886 gen_rtx_CLOBBER (VOIDmode
,
6887 gen_rtx_REG (word_mode
, 18)),
6888 CALL_INSN_FUNCTION_USAGE (insn
));
6893 /* Expand a call of type TYPE. RESULT is where the result will go (null
6894 for "call"s and "sibcall"s), ADDR is the address of the function,
6895 ARGS_SIZE is the size of the arguments and AUX is the value passed
6896 to us by mips_function_arg. LAZY_P is true if this call already
6897 involves a lazily-bound function address (such as when calling
6898 functions through a MIPS16 hard-float stub).
6900 Return the call itself. */
6903 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6904 rtx args_size
, rtx aux
, bool lazy_p
)
6906 rtx orig_addr
, pattern
, insn
;
6909 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6910 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6913 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6918 if (!call_insn_operand (addr
, VOIDmode
))
6920 if (type
== MIPS_CALL_EPILOGUE
)
6921 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6923 addr
= gen_reg_rtx (Pmode
);
6924 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6929 rtx (*fn
) (rtx
, rtx
);
6931 if (type
== MIPS_CALL_SIBCALL
)
6932 fn
= gen_sibcall_internal
;
6934 fn
= gen_call_internal
;
6936 pattern
= fn (addr
, args_size
);
6938 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6940 /* Handle return values created by mips_return_fpr_pair. */
6941 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6944 if (type
== MIPS_CALL_SIBCALL
)
6945 fn
= gen_sibcall_value_multiple_internal
;
6947 fn
= gen_call_value_multiple_internal
;
6949 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6950 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6951 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6955 rtx (*fn
) (rtx
, rtx
, rtx
);
6957 if (type
== MIPS_CALL_SIBCALL
)
6958 fn
= gen_sibcall_value_internal
;
6960 fn
= gen_call_value_internal
;
6962 /* Handle return values created by mips_return_fpr_single. */
6963 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6964 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6965 pattern
= fn (result
, addr
, args_size
);
6968 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6971 /* Split call instruction INSN into a $gp-clobbering call and
6972 (where necessary) an instruction to restore $gp from its save slot.
6973 CALL_PATTERN is the pattern of the new call. */
6976 mips_split_call (rtx insn
, rtx call_pattern
)
6978 emit_call_insn (call_pattern
);
6979 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6980 /* Pick a temporary register that is suitable for both MIPS16 and
6981 non-MIPS16 code. $4 and $5 are used for returning complex double
6982 values in soft-float code, so $6 is the first suitable candidate. */
6983 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6986 /* Return true if a call to DECL may need to use JALX. */
6989 mips_call_may_need_jalx_p (tree decl
)
6991 /* If the current translation unit would use a different mode for DECL,
6992 assume that the call needs JALX. */
6993 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
6996 /* mips_get_compress_mode is always accurate for locally-binding
6997 functions in the current translation unit. */
6998 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7001 /* When -minterlink-compressed is in effect, assume that functions
7002 could use a different encoding mode unless an attribute explicitly
7003 tells us otherwise. */
7004 if (TARGET_INTERLINK_COMPRESSED
)
7006 if (!TARGET_COMPRESSION
7007 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7009 if (TARGET_COMPRESSION
7010 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7017 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7020 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7022 if (!TARGET_SIBCALLS
)
7025 /* Interrupt handlers need special epilogue code and therefore can't
7027 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7030 /* Direct Js are only possible to functions that use the same ISA encoding.
7031 There is no JX counterpoart of JALX. */
7033 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7034 && mips_call_may_need_jalx_p (decl
))
7037 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7038 require $gp to be valid on entry, so sibcalls can only use stubs
7039 if $gp is call-clobbered. */
7041 && TARGET_CALL_SAVED_GP
7042 && !TARGET_ABICALLS_PIC0
7043 && !targetm
.binds_local_p (decl
))
7050 /* Emit code to move general operand SRC into condition-code
7051 register DEST given that SCRATCH is a scratch TFmode FPR.
7058 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
7061 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
7065 /* Change the source to SFmode. */
7067 src
= adjust_address (src
, SFmode
, 0);
7068 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
7069 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
7071 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
7072 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
7074 mips_emit_move (copy_rtx (fp1
), src
);
7075 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
7076 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
7079 /* Implement MOVE_BY_PIECES_P. */
7082 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7086 /* movmemsi is meant to generate code that is at least as good as
7087 move_by_pieces. However, movmemsi effectively uses a by-pieces
7088 implementation both for moves smaller than a word and for
7089 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7090 bytes. We should allow the tree-level optimisers to do such
7091 moves by pieces, as it often exposes other optimization
7092 opportunities. We might as well continue to use movmemsi at
7093 the rtl level though, as it produces better code when
7094 scheduling is disabled (such as at -O). */
7095 if (currently_expanding_to_rtl
)
7097 if (align
< BITS_PER_WORD
)
7098 return size
< UNITS_PER_WORD
;
7099 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7101 /* The default value. If this becomes a target hook, we should
7102 call the default definition instead. */
7103 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7104 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7107 /* Implement STORE_BY_PIECES_P. */
7110 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7112 /* Storing by pieces involves moving constants into registers
7113 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7114 We need to decide whether it is cheaper to load the address of
7115 constant data into a register and use a block move instead. */
7117 /* If the data is only byte aligned, then:
7119 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7120 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7123 (a2) A block move of 4 bytes from aligned source data can use an
7124 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7125 4 SBs that we would generate when storing by pieces. */
7126 if (align
<= BITS_PER_UNIT
)
7129 /* If the data is 2-byte aligned, then:
7131 (b1) A block move of less than 4 bytes would use a combination of LBs,
7132 LHs, SBs and SHs. We get better code by using single-instruction
7133 LIs, SBs and SHs instead.
7135 (b2) A block move of 4 bytes from aligned source data would again use
7136 an LW/SWL/SWR sequence. In most cases, loading the address of
7137 the source data would require at least one extra instruction.
7138 It is often more efficient to use 2 single-instruction LIs and
7141 (b3) A block move of up to 3 additional bytes would be like (b1).
7143 (b4) A block move of 8 bytes from aligned source data can use two
7144 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7145 sequences are better than the 4 LIs and 4 SHs that we'd generate
7146 when storing by pieces.
7148 The reasoning for higher alignments is similar:
7150 (c1) A block move of less than 4 bytes would be the same as (b1).
7152 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7153 loading the address of the source data would typically require
7154 at least one extra instruction. It is generally better to use
7157 (c3) A block move of up to 3 additional bytes would be like (b1).
7159 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7160 LD/SD sequence, and in these cases we've traditionally preferred
7161 the memory copy over the more bulky constant moves. */
7165 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7166 Assume that the areas do not overlap. */
7169 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7171 HOST_WIDE_INT offset
, delta
;
7172 unsigned HOST_WIDE_INT bits
;
7174 enum machine_mode mode
;
7177 /* Work out how many bits to move at a time. If both operands have
7178 half-word alignment, it is usually better to move in half words.
7179 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7180 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7181 Otherwise move word-sized chunks. */
7182 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7183 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7184 bits
= BITS_PER_WORD
/ 2;
7186 bits
= BITS_PER_WORD
;
7188 mode
= mode_for_size (bits
, MODE_INT
, 0);
7189 delta
= bits
/ BITS_PER_UNIT
;
7191 /* Allocate a buffer for the temporary registers. */
7192 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7194 /* Load as many BITS-sized chunks as possible. Use a normal load if
7195 the source has enough alignment, otherwise use left/right pairs. */
7196 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7198 regs
[i
] = gen_reg_rtx (mode
);
7199 if (MEM_ALIGN (src
) >= bits
)
7200 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7203 rtx part
= adjust_address (src
, BLKmode
, offset
);
7204 set_mem_size (part
, delta
);
7205 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7210 /* Copy the chunks to the destination. */
7211 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7212 if (MEM_ALIGN (dest
) >= bits
)
7213 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7216 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7217 set_mem_size (part
, delta
);
7218 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7222 /* Mop up any left-over bytes. */
7223 if (offset
< length
)
7225 src
= adjust_address (src
, BLKmode
, offset
);
7226 dest
= adjust_address (dest
, BLKmode
, offset
);
7227 move_by_pieces (dest
, src
, length
- offset
,
7228 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7232 /* Helper function for doing a loop-based block operation on memory
7233 reference MEM. Each iteration of the loop will operate on LENGTH
7236 Create a new base register for use within the loop and point it to
7237 the start of MEM. Create a new memory reference that uses this
7238 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7241 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7242 rtx
*loop_reg
, rtx
*loop_mem
)
7244 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7246 /* Although the new mem does not refer to a known location,
7247 it does keep up to LENGTH bytes of alignment. */
7248 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7249 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7252 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7253 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7254 the memory regions do not overlap. */
7257 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7258 HOST_WIDE_INT bytes_per_iter
)
7260 rtx label
, src_reg
, dest_reg
, final_src
, test
;
7261 HOST_WIDE_INT leftover
;
7263 leftover
= length
% bytes_per_iter
;
7266 /* Create registers and memory references for use within the loop. */
7267 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7268 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7270 /* Calculate the value that SRC_REG should have after the last iteration
7272 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7275 /* Emit the start of the loop. */
7276 label
= gen_label_rtx ();
7279 /* Emit the loop body. */
7280 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7282 /* Move on to the next block. */
7283 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7284 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7286 /* Emit the loop condition. */
7287 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7288 if (Pmode
== DImode
)
7289 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7291 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7293 /* Mop up any left-over bytes. */
7295 mips_block_move_straight (dest
, src
, leftover
);
7298 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7299 memory reference SRC to memory reference DEST. */
7302 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7304 if (CONST_INT_P (length
))
7306 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7308 mips_block_move_straight (dest
, src
, INTVAL (length
));
7313 mips_block_move_loop (dest
, src
, INTVAL (length
),
7314 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7321 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7324 mips_expand_synci_loop (rtx begin
, rtx end
)
7326 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7328 /* Create end_label. */
7329 end_label
= gen_label_rtx ();
7331 /* Check if begin equals end. */
7332 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7333 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7335 /* Load INC with the cache line size (rdhwr INC,$1). */
7336 inc
= gen_reg_rtx (Pmode
);
7337 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7339 /* Check if inc is 0. */
7340 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7341 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7343 /* Calculate mask. */
7344 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7346 /* Mask out begin by mask. */
7347 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7349 /* Calculate length. */
7350 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7352 /* Loop back to here. */
7353 label
= gen_label_rtx ();
7356 emit_insn (gen_synci (begin
));
7358 /* Update length. */
7359 mips_emit_binary (MINUS
, length
, length
, inc
);
7362 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7364 /* Check if length is greater than 0. */
7365 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7366 emit_jump_insn (gen_condjump (cmp_result
, label
));
7368 emit_label (end_label
);
7371 /* Expand a QI or HI mode atomic memory operation.
7373 GENERATOR contains a pointer to the gen_* function that generates
7374 the SI mode underlying atomic operation using masks that we
7377 RESULT is the return register for the operation. Its value is NULL
7380 MEM is the location of the atomic access.
7382 OLDVAL is the first operand for the operation.
7384 NEWVAL is the optional second operand for the operation. Its value
7385 is NULL if unused. */
7388 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7389 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7391 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7392 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7394 enum machine_mode mode
;
7396 mode
= GET_MODE (mem
);
7398 /* Compute the address of the containing SImode value. */
7399 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7400 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7401 force_reg (Pmode
, GEN_INT (-4)));
7403 /* Create a memory reference for it. */
7404 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7405 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7406 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7408 /* Work out the byte offset of the QImode or HImode value,
7409 counting from the least significant byte. */
7410 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7411 if (TARGET_BIG_ENDIAN
)
7412 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7414 /* Multiply by eight to convert the shift value from bytes to bits. */
7415 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7417 /* Make the final shift an SImode value, so that it can be used in
7418 SImode operations. */
7419 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7421 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7422 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7423 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7424 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7426 /* Compute the equivalent exclusive mask. */
7427 inverted_mask
= gen_reg_rtx (SImode
);
7428 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7429 gen_rtx_NOT (SImode
, mask
)));
7431 /* Shift the old value into place. */
7432 if (oldval
!= const0_rtx
)
7434 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7435 oldval
= force_reg (SImode
, oldval
);
7436 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7439 /* Do the same for the new value. */
7440 if (newval
&& newval
!= const0_rtx
)
7442 newval
= convert_modes (SImode
, mode
, newval
, true);
7443 newval
= force_reg (SImode
, newval
);
7444 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7447 /* Do the SImode atomic access. */
7449 res
= gen_reg_rtx (SImode
);
7451 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7453 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7455 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7461 /* Shift and convert the result. */
7462 mips_emit_binary (AND
, res
, res
, mask
);
7463 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7464 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7468 /* Return true if it is possible to use left/right accesses for a
7469 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7470 When returning true, update *LEFT and *RIGHT as follows:
7472 *LEFT is a QImode reference to the first byte if big endian or
7473 the last byte if little endian. This address can be used in the
7474 left-side instructions (LWL, SWL, LDL, SDL).
7476 *RIGHT is a QImode reference to the opposite end of the field and
7477 can be used in the patterning right-side instruction. */
7480 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7481 rtx
*left
, rtx
*right
)
7485 /* Check that the size is valid. */
7486 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7489 /* We can only access byte-aligned values. Since we are always passed
7490 a reference to the first byte of the field, it is not necessary to
7491 do anything with BITPOS after this check. */
7492 if (bitpos
% BITS_PER_UNIT
!= 0)
7495 /* Reject aligned bitfields: we want to use a normal load or store
7496 instead of a left/right pair. */
7497 if (MEM_ALIGN (op
) >= width
)
7500 /* Get references to both ends of the field. */
7501 first
= adjust_address (op
, QImode
, 0);
7502 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7504 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7505 correspond to the MSB and RIGHT to the LSB. */
7506 if (TARGET_BIG_ENDIAN
)
7507 *left
= first
, *right
= last
;
7509 *left
= last
, *right
= first
;
7514 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7515 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7516 the operation is the equivalent of:
7518 (set DEST (*_extract SRC WIDTH BITPOS))
7520 Return true on success. */
7523 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7524 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7526 rtx left
, right
, temp
;
7527 rtx dest1
= NULL_RTX
;
7529 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7530 be a DImode, create a new temp and emit a zero extend at the end. */
7531 if (GET_MODE (dest
) == DImode
7533 && GET_MODE_BITSIZE (SImode
) == width
)
7536 dest
= gen_reg_rtx (SImode
);
7539 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7542 temp
= gen_reg_rtx (GET_MODE (dest
));
7543 if (GET_MODE (dest
) == DImode
)
7545 emit_insn (gen_mov_ldl (temp
, src
, left
));
7546 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7550 emit_insn (gen_mov_lwl (temp
, src
, left
));
7551 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7554 /* If we were loading 32bits and the original register was DI then
7555 sign/zero extend into the orignal dest. */
7559 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7561 emit_insn (gen_extendsidi2 (dest1
, dest
));
7566 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7567 BITPOS and SRC are the operands passed to the expander; the operation
7568 is the equivalent of:
7570 (set (zero_extract DEST WIDTH BITPOS) SRC)
7572 Return true on success. */
7575 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7576 HOST_WIDE_INT bitpos
)
7579 enum machine_mode mode
;
7581 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7584 mode
= mode_for_size (width
, MODE_INT
, 0);
7585 src
= gen_lowpart (mode
, src
);
7588 emit_insn (gen_mov_sdl (dest
, src
, left
));
7589 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7593 emit_insn (gen_mov_swl (dest
, src
, left
));
7594 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7599 /* Return true if X is a MEM with the same size as MODE. */
7602 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7605 && MEM_SIZE_KNOWN_P (x
)
7606 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7609 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7610 source of an "ext" instruction or the destination of an "ins"
7611 instruction. OP must be a register operand and the following
7612 conditions must hold:
7614 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7615 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7616 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7618 Also reject lengths equal to a word as they are better handled
7619 by the move patterns. */
7622 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7624 if (!ISA_HAS_EXT_INS
7625 || !register_operand (op
, VOIDmode
)
7626 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7629 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7632 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7638 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7639 operation if MAXLEN is the maxium length of consecutive bits that
7640 can make up MASK. MODE is the mode of the operation. See
7641 mask_low_and_shift_len for the actual definition. */
7644 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7646 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7649 /* Return true iff OP1 and OP2 are valid operands together for the
7650 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7651 see the table in the comment before the pattern. */
7654 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7656 return (memory_operand (op1
, mode
)
7657 ? and_load_operand (op2
, mode
)
7658 : and_reg_operand (op2
, mode
));
7661 /* The canonical form of a mask-low-and-shift-left operation is
7662 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7663 cleared. Thus we need to shift MASK to the right before checking if it
7664 is a valid mask value. MODE is the mode of the operation. If true
7665 return the length of the mask, otherwise return -1. */
7668 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7670 HOST_WIDE_INT shval
;
7672 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7673 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7676 /* Return true if -msplit-addresses is selected and should be honored.
7678 -msplit-addresses is a half-way house between explicit relocations
7679 and the traditional assembler macros. It can split absolute 32-bit
7680 symbolic constants into a high/lo_sum pair but uses macros for other
7683 Like explicit relocation support for REL targets, it relies
7684 on GNU extensions in the assembler and the linker.
7686 Although this code should work for -O0, it has traditionally
7687 been treated as an optimization. */
7690 mips_split_addresses_p (void)
7692 return (TARGET_SPLIT_ADDRESSES
7696 && !ABI_HAS_64BIT_SYMBOLS
);
7699 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7702 mips_init_relocs (void)
7704 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7705 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7706 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7707 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7708 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7710 if (TARGET_MIPS16_PCREL_LOADS
)
7711 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7714 if (ABI_HAS_64BIT_SYMBOLS
)
7716 if (TARGET_EXPLICIT_RELOCS
)
7718 mips_split_p
[SYMBOL_64_HIGH
] = true;
7719 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7720 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7722 mips_split_p
[SYMBOL_64_MID
] = true;
7723 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7724 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7726 mips_split_p
[SYMBOL_64_LOW
] = true;
7727 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7728 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7730 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7731 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7736 if (TARGET_EXPLICIT_RELOCS
7737 || mips_split_addresses_p ()
7740 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7741 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7742 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7749 /* The high part is provided by a pseudo copy of $gp. */
7750 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7751 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7753 else if (TARGET_EXPLICIT_RELOCS
)
7754 /* Small data constants are kept whole until after reload,
7755 then lowered by mips_rewrite_small_data. */
7756 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7758 if (TARGET_EXPLICIT_RELOCS
)
7760 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7763 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7764 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7768 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7769 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7772 /* Expose the use of $28 as soon as possible. */
7773 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7777 /* The HIGH and LO_SUM are matched by special .md patterns. */
7778 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7780 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7781 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7782 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7784 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7785 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7786 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7791 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7793 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7794 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7796 /* Expose the use of $28 as soon as possible. */
7797 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7803 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7804 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7805 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7808 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7809 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7811 if (TARGET_MIPS16_PCREL_LOADS
)
7813 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7814 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7818 mips_split_p
[SYMBOL_DTPREL
] = true;
7819 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7820 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7822 mips_split_p
[SYMBOL_TPREL
] = true;
7823 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7824 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7827 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7828 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7831 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7832 in context CONTEXT. RELOCS is the array of relocations to use. */
7835 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7836 const char **relocs
)
7838 enum mips_symbol_type symbol_type
;
7841 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7842 gcc_assert (relocs
[symbol_type
]);
7844 fputs (relocs
[symbol_type
], file
);
7845 output_addr_const (file
, mips_strip_unspec_address (op
));
7846 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7851 /* Start a new block with the given asm switch enabled. If we need
7852 to print a directive, emit PREFIX before it and SUFFIX after it. */
7855 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7856 const char *prefix
, const char *suffix
)
7858 if (asm_switch
->nesting_level
== 0)
7859 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7860 asm_switch
->nesting_level
++;
7863 /* Likewise, but end a block. */
7866 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7867 const char *prefix
, const char *suffix
)
7869 gcc_assert (asm_switch
->nesting_level
);
7870 asm_switch
->nesting_level
--;
7871 if (asm_switch
->nesting_level
== 0)
7872 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7875 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7876 that either print a complete line or print nothing. */
7879 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7881 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7885 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7887 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7890 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7891 The punctuation characters are:
7893 '(' Start a nested ".set noreorder" block.
7894 ')' End a nested ".set noreorder" block.
7895 '[' Start a nested ".set noat" block.
7896 ']' End a nested ".set noat" block.
7897 '<' Start a nested ".set nomacro" block.
7898 '>' End a nested ".set nomacro" block.
7899 '*' Behave like %(%< if generating a delayed-branch sequence.
7900 '#' Print a nop if in a ".set noreorder" block.
7901 '/' Like '#', but do nothing within a delayed-branch sequence.
7902 '?' Print "l" if mips_branch_likely is true
7903 '~' Print a nop if mips_branch_likely is true
7904 '.' Print the name of the register with a hard-wired zero (zero or $0).
7905 '@' Print the name of the assembler temporary register (at or $1).
7906 '^' Print the name of the pic call-through register (t9 or $25).
7907 '+' Print the name of the gp register (usually gp or $28).
7908 '$' Print the name of the stack pointer register (sp or $29).
7909 ':' Print "c" to use the compact version if the delay slot is a nop.
7910 '!' Print "s" to use the short version if the delay slot contains a
7913 See also mips_init_print_operand_pucnt. */
7916 mips_print_operand_punctuation (FILE *file
, int ch
)
7921 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7925 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7929 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7933 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7937 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7941 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7945 if (final_sequence
!= 0)
7947 mips_print_operand_punctuation (file
, '(');
7948 mips_print_operand_punctuation (file
, '<');
7953 if (mips_noreorder
.nesting_level
> 0)
7954 fputs ("\n\tnop", file
);
7958 /* Print an extra newline so that the delayed insn is separated
7959 from the following ones. This looks neater and is consistent
7960 with non-nop delayed sequences. */
7961 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7962 fputs ("\n\tnop\n", file
);
7966 if (mips_branch_likely
)
7971 if (mips_branch_likely
)
7972 fputs ("\n\tnop", file
);
7976 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7980 fputs (reg_names
[AT_REGNUM
], file
);
7984 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7988 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7992 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7996 /* When final_sequence is 0, the delay slot will be a nop. We can
7997 use the compact version for microMIPS. */
7998 if (final_sequence
== 0)
8003 /* If the delay slot instruction is short, then use the
8005 if (final_sequence
== 0
8006 || get_attr_length (XVECEXP (final_sequence
, 0, 1)) == 2)
8016 /* Initialize mips_print_operand_punct. */
8019 mips_init_print_operand_punct (void)
8023 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8024 mips_print_operand_punct
[(unsigned char) *p
] = true;
8027 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8028 associated with condition CODE. Print the condition part of the
8032 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8046 /* Conveniently, the MIPS names for these conditions are the same
8047 as their RTL equivalents. */
8048 fputs (GET_RTX_NAME (code
), file
);
8052 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8057 /* Likewise floating-point branches. */
8060 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8065 fputs ("c1f", file
);
8069 fputs ("c1t", file
);
8073 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8078 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8081 mips_print_operand_punct_valid_p (unsigned char code
)
8083 return mips_print_operand_punct
[code
];
8086 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8088 'X' Print CONST_INT OP in hexadecimal format.
8089 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8090 'd' Print CONST_INT OP in decimal.
8091 'm' Print one less than CONST_INT OP in decimal.
8092 'h' Print the high-part relocation associated with OP, after stripping
8094 'R' Print the low-part relocation associated with OP.
8095 'C' Print the integer branch condition for comparison OP.
8096 'N' Print the inverse of the integer branch condition for comparison OP.
8097 'F' Print the FPU branch condition for comparison OP.
8098 'W' Print the inverse of the FPU branch condition for comparison OP.
8099 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8100 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8101 't' Like 'T', but with the EQ/NE cases reversed
8102 'Y' Print mips_fp_conditions[INTVAL (OP)]
8103 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8104 'q' Print a DSP accumulator register.
8105 'D' Print the second part of a double-word register or memory operand.
8106 'L' Print the low-order register in a double-word register operand.
8107 'M' Print high-order register in a double-word register operand.
8108 'z' Print $0 if OP is zero, otherwise print OP normally.
8109 'b' Print the address of a memory operand, without offset. */
8112 mips_print_operand (FILE *file
, rtx op
, int letter
)
8116 if (mips_print_operand_punct_valid_p (letter
))
8118 mips_print_operand_punctuation (file
, letter
);
8123 code
= GET_CODE (op
);
8128 if (CONST_INT_P (op
))
8129 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8131 output_operand_lossage ("invalid use of '%%%c'", letter
);
8135 if (CONST_INT_P (op
))
8136 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8138 output_operand_lossage ("invalid use of '%%%c'", letter
);
8142 if (CONST_INT_P (op
))
8143 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8145 output_operand_lossage ("invalid use of '%%%c'", letter
);
8149 if (CONST_INT_P (op
))
8150 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8152 output_operand_lossage ("invalid use of '%%%c'", letter
);
8158 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8162 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8166 mips_print_int_branch_condition (file
, code
, letter
);
8170 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8174 mips_print_float_branch_condition (file
, code
, letter
);
8178 mips_print_float_branch_condition (file
, reverse_condition (code
),
8185 int truth
= (code
== NE
) == (letter
== 'T');
8186 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
8191 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8192 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8194 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8201 mips_print_operand (file
, op
, 0);
8207 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8208 fprintf (file
, "$ac0");
8209 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8210 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8212 output_operand_lossage ("invalid use of '%%%c'", letter
);
8220 unsigned int regno
= REGNO (op
);
8221 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8222 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8225 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8226 output_operand_lossage ("invalid use of '%%%c'", letter
);
8227 /* We need to print $0 .. $31 for COP0 registers. */
8228 if (COP0_REG_P (regno
))
8229 fprintf (file
, "$%s", ®_names
[regno
][4]);
8231 fprintf (file
, "%s", reg_names
[regno
]);
8237 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8238 else if (letter
== 'b')
8240 gcc_assert (REG_P (XEXP (op
, 0)));
8241 mips_print_operand (file
, XEXP (op
, 0), 0);
8243 else if (letter
&& letter
!= 'z')
8244 output_operand_lossage ("invalid use of '%%%c'", letter
);
8246 output_address (XEXP (op
, 0));
8250 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8251 fputs (reg_names
[GP_REG_FIRST
], file
);
8252 else if (letter
&& letter
!= 'z')
8253 output_operand_lossage ("invalid use of '%%%c'", letter
);
8254 else if (CONST_GP_P (op
))
8255 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8257 output_addr_const (file
, mips_strip_unspec_address (op
));
8263 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8266 mips_print_operand_address (FILE *file
, rtx x
)
8268 struct mips_address_info addr
;
8270 if (mips_classify_address (&addr
, x
, word_mode
, true))
8274 mips_print_operand (file
, addr
.offset
, 0);
8275 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8278 case ADDRESS_LO_SUM
:
8279 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8281 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8284 case ADDRESS_CONST_INT
:
8285 output_addr_const (file
, x
);
8286 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8289 case ADDRESS_SYMBOLIC
:
8290 output_addr_const (file
, mips_strip_unspec_address (x
));
8296 /* Implement TARGET_ENCODE_SECTION_INFO. */
8299 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8301 default_encode_section_info (decl
, rtl
, first
);
8303 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8305 rtx symbol
= XEXP (rtl
, 0);
8306 tree type
= TREE_TYPE (decl
);
8308 /* Encode whether the symbol is short or long. */
8309 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8310 || mips_far_type_p (type
))
8311 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8315 /* Implement TARGET_SELECT_RTX_SECTION. */
8318 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8319 unsigned HOST_WIDE_INT align
)
8321 /* ??? Consider using mergeable small data sections. */
8322 if (mips_rtx_constant_in_small_data_p (mode
))
8323 return get_named_section (NULL
, ".sdata", 0);
8325 return default_elf_select_rtx_section (mode
, x
, align
);
8328 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8330 The complication here is that, with the combination TARGET_ABICALLS
8331 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8332 absolute addresses, and should therefore not be included in the
8333 read-only part of a DSO. Handle such cases by selecting a normal
8334 data section instead of a read-only one. The logic apes that in
8335 default_function_rodata_section. */
8338 mips_function_rodata_section (tree decl
)
8340 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8341 return default_function_rodata_section (decl
);
8343 if (decl
&& DECL_SECTION_NAME (decl
))
8345 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8346 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8348 char *rname
= ASTRDUP (name
);
8350 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8352 else if (flag_function_sections
8353 && flag_data_sections
8354 && strncmp (name
, ".text.", 6) == 0)
8356 char *rname
= ASTRDUP (name
);
8357 memcpy (rname
+ 1, "data", 4);
8358 return get_section (rname
, SECTION_WRITE
, decl
);
8361 return data_section
;
8364 /* Implement TARGET_IN_SMALL_DATA_P. */
8367 mips_in_small_data_p (const_tree decl
)
8369 unsigned HOST_WIDE_INT size
;
8371 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8374 /* We don't yet generate small-data references for -mabicalls
8375 or VxWorks RTP code. See the related -G handling in
8376 mips_option_override. */
8377 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8380 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8384 /* Reject anything that isn't in a known small-data section. */
8385 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8386 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8389 /* If a symbol is defined externally, the assembler will use the
8390 usual -G rules when deciding how to implement macros. */
8391 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8394 else if (TARGET_EMBEDDED_DATA
)
8396 /* Don't put constants into the small data section: we want them
8397 to be in ROM rather than RAM. */
8398 if (TREE_CODE (decl
) != VAR_DECL
)
8401 if (TREE_READONLY (decl
)
8402 && !TREE_SIDE_EFFECTS (decl
)
8403 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8407 /* Enforce -mlocal-sdata. */
8408 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8411 /* Enforce -mextern-sdata. */
8412 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8414 if (DECL_EXTERNAL (decl
))
8416 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8420 /* We have traditionally not treated zero-sized objects as small data,
8421 so this is now effectively part of the ABI. */
8422 size
= int_size_in_bytes (TREE_TYPE (decl
));
8423 return size
> 0 && size
<= mips_small_data_threshold
;
8426 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8427 anchors for small data: the GP register acts as an anchor in that
8428 case. We also don't want to use them for PC-relative accesses,
8429 where the PC acts as an anchor. */
8432 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8434 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8436 case SYMBOL_PC_RELATIVE
:
8437 case SYMBOL_GP_RELATIVE
:
8441 return default_use_anchors_for_symbol_p (symbol
);
8445 /* The MIPS debug format wants all automatic variables and arguments
8446 to be in terms of the virtual frame pointer (stack pointer before
8447 any adjustment in the function), while the MIPS 3.0 linker wants
8448 the frame pointer to be the stack pointer after the initial
8449 adjustment. So, we do the adjustment here. The arg pointer (which
8450 is eliminated) points to the virtual frame pointer, while the frame
8451 pointer (which may be eliminated) points to the stack pointer after
8452 the initial adjustments. */
8455 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8457 rtx offset2
= const0_rtx
;
8458 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8461 offset
= INTVAL (offset2
);
8463 if (reg
== stack_pointer_rtx
8464 || reg
== frame_pointer_rtx
8465 || reg
== hard_frame_pointer_rtx
)
8467 offset
-= cfun
->machine
->frame
.total_size
;
8468 if (reg
== hard_frame_pointer_rtx
)
8469 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8475 /* Implement ASM_OUTPUT_EXTERNAL. */
8478 mips_output_external (FILE *file
, tree decl
, const char *name
)
8480 default_elf_asm_output_external (file
, decl
, name
);
8482 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8483 set in order to avoid putting out names that are never really
8485 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8487 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8489 /* When using assembler macros, emit .extern directives for
8490 all small-data externs so that the assembler knows how
8493 In most cases it would be safe (though pointless) to emit
8494 .externs for other symbols too. One exception is when an
8495 object is within the -G limit but declared by the user to
8496 be in a section other than .sbss or .sdata. */
8497 fputs ("\t.extern\t", file
);
8498 assemble_name (file
, name
);
8499 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8500 int_size_in_bytes (TREE_TYPE (decl
)));
8505 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8508 mips_output_filename (FILE *stream
, const char *name
)
8510 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8512 if (write_symbols
== DWARF2_DEBUG
)
8514 else if (mips_output_filename_first_time
)
8516 mips_output_filename_first_time
= 0;
8517 num_source_filenames
+= 1;
8518 current_function_file
= name
;
8519 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8520 output_quoted_string (stream
, name
);
8521 putc ('\n', stream
);
8523 /* If we are emitting stabs, let dbxout.c handle this (except for
8524 the mips_output_filename_first_time case). */
8525 else if (write_symbols
== DBX_DEBUG
)
8527 else if (name
!= current_function_file
8528 && strcmp (name
, current_function_file
) != 0)
8530 num_source_filenames
+= 1;
8531 current_function_file
= name
;
8532 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8533 output_quoted_string (stream
, name
);
8534 putc ('\n', stream
);
8538 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8540 static void ATTRIBUTE_UNUSED
8541 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8546 fputs ("\t.dtprelword\t", file
);
8550 fputs ("\t.dtpreldword\t", file
);
8556 output_addr_const (file
, x
);
8557 fputs ("+0x8000", file
);
8560 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8563 mips_dwarf_register_span (rtx reg
)
8566 enum machine_mode mode
;
8568 /* By default, GCC maps increasing register numbers to increasing
8569 memory locations, but paired FPRs are always little-endian,
8570 regardless of the prevailing endianness. */
8571 mode
= GET_MODE (reg
);
8572 if (FP_REG_P (REGNO (reg
))
8573 && TARGET_BIG_ENDIAN
8574 && MAX_FPRS_PER_FMT
> 1
8575 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8577 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8578 high
= mips_subword (reg
, true);
8579 low
= mips_subword (reg
, false);
8580 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8586 /* DSP ALU can bypass data with no delays for the following pairs. */
8587 enum insn_code dspalu_bypass_table
[][2] =
8589 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8590 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8591 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8592 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8593 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8594 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8595 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8596 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8600 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8603 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8604 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8605 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8607 for (i
= 0; i
< num_bypass
; i
++)
8609 if (out_icode
== dspalu_bypass_table
[i
][0]
8610 && in_icode
== dspalu_bypass_table
[i
][1])
8616 /* Implement ASM_OUTPUT_ASCII. */
8619 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8625 fprintf (stream
, "\t.ascii\t\"");
8626 for (i
= 0; i
< len
; i
++)
8630 c
= (unsigned char) string
[i
];
8633 if (c
== '\\' || c
== '\"')
8635 putc ('\\', stream
);
8643 fprintf (stream
, "\\%03o", c
);
8647 if (cur_pos
> 72 && i
+1 < len
)
8650 fprintf (stream
, "\"\n\t.ascii\t\"");
8653 fprintf (stream
, "\"\n");
8656 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8657 Update *ADDR with the operand that should be printed. */
8660 mips_output_tls_reloc_directive (rtx
*addr
)
8662 enum mips_symbol_type type
;
8664 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8665 *addr
= mips_strip_unspec_address (*addr
);
8669 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8672 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8679 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8680 macros, mark the symbol as written so that mips_asm_output_external
8681 won't emit an .extern for it. STREAM is the output file, NAME is the
8682 name of the symbol, INIT_STRING is the string that should be written
8683 before the symbol and FINAL_STRING is the string that should be
8684 written after it. FINAL_STRING is a printf format that consumes the
8685 remaining arguments. */
8688 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8689 const char *final_string
, ...)
8693 fputs (init_string
, stream
);
8694 assemble_name (stream
, name
);
8695 va_start (ap
, final_string
);
8696 vfprintf (stream
, final_string
, ap
);
8699 if (!TARGET_EXPLICIT_RELOCS
)
8701 tree name_tree
= get_identifier (name
);
8702 TREE_ASM_WRITTEN (name_tree
) = 1;
8706 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8707 NAME is the name of the object and ALIGN is the required alignment
8708 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8709 alignment argument. */
8712 mips_declare_common_object (FILE *stream
, const char *name
,
8713 const char *init_string
,
8714 unsigned HOST_WIDE_INT size
,
8715 unsigned int align
, bool takes_alignment_p
)
8717 if (!takes_alignment_p
)
8719 size
+= (align
/ BITS_PER_UNIT
) - 1;
8720 size
-= size
% (align
/ BITS_PER_UNIT
);
8721 mips_declare_object (stream
, name
, init_string
,
8722 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8725 mips_declare_object (stream
, name
, init_string
,
8726 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8727 size
, align
/ BITS_PER_UNIT
);
8730 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8731 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8734 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8735 unsigned HOST_WIDE_INT size
,
8738 /* If the target wants uninitialized const declarations in
8739 .rdata then don't put them in .comm. */
8740 if (TARGET_EMBEDDED_DATA
8741 && TARGET_UNINIT_CONST_IN_RODATA
8742 && TREE_CODE (decl
) == VAR_DECL
8743 && TREE_READONLY (decl
)
8744 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8746 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8747 targetm
.asm_out
.globalize_label (stream
, name
);
8749 switch_to_section (readonly_data_section
);
8750 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8751 mips_declare_object (stream
, name
, "",
8752 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8756 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8760 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8761 extern int size_directive_output
;
8763 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8764 definitions except that it uses mips_declare_object to emit the label. */
8767 mips_declare_object_name (FILE *stream
, const char *name
,
8768 tree decl ATTRIBUTE_UNUSED
)
8770 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8771 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8774 size_directive_output
= 0;
8775 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8779 size_directive_output
= 1;
8780 size
= int_size_in_bytes (TREE_TYPE (decl
));
8781 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8784 mips_declare_object (stream
, name
, "", ":\n");
8787 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8790 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8794 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8795 if (!flag_inhibit_size_directive
8796 && DECL_SIZE (decl
) != 0
8799 && DECL_INITIAL (decl
) == error_mark_node
8800 && !size_directive_output
)
8804 size_directive_output
= 1;
8805 size
= int_size_in_bytes (TREE_TYPE (decl
));
8806 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8811 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8812 with the current ABI. */
8815 mips_mdebug_abi_name (void)
8828 return TARGET_64BIT
? "eabi64" : "eabi32";
8834 /* Implement TARGET_ASM_FILE_START. */
8837 mips_file_start (void)
8839 default_file_start ();
8841 /* Generate a special section to describe the ABI switches used to
8842 produce the resultant binary. */
8844 /* Record the ABI itself. Modern versions of binutils encode
8845 this information in the ELF header flags, but GDB needs the
8846 information in order to correctly debug binaries produced by
8847 older binutils. See the function mips_gdbarch_init in
8849 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8850 mips_mdebug_abi_name ());
8852 /* There is no ELF header flag to distinguish long32 forms of the
8853 EABI from long64 forms. Emit a special section to help tools
8854 such as GDB. Do the same for o64, which is sometimes used with
8856 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8857 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8858 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8860 /* Record the NaN encoding. */
8861 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
8862 fprintf (asm_out_file
, "\t.nan\t%s\n",
8863 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
8865 #ifdef HAVE_AS_GNU_ATTRIBUTE
8869 /* No floating-point operations, -mno-float. */
8870 if (TARGET_NO_FLOAT
)
8872 /* Soft-float code, -msoft-float. */
8873 else if (!TARGET_HARD_FLOAT_ABI
)
8875 /* Single-float code, -msingle-float. */
8876 else if (!TARGET_DOUBLE_FLOAT
)
8878 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8879 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8881 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8885 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8889 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8890 if (TARGET_ABICALLS
)
8892 fprintf (asm_out_file
, "\t.abicalls\n");
8893 if (TARGET_ABICALLS_PIC0
)
8894 fprintf (asm_out_file
, "\t.option\tpic0\n");
8897 if (flag_verbose_asm
)
8898 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8900 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8903 /* Implement TARGET_ASM_CODE_END. */
8906 mips_code_end (void)
8908 if (mips_need_mips16_rdhwr_p
)
8909 mips_output_mips16_rdhwr ();
8912 /* Make the last instruction frame-related and note that it performs
8913 the operation described by FRAME_PATTERN. */
8916 mips_set_frame_expr (rtx frame_pattern
)
8920 insn
= get_last_insn ();
8921 RTX_FRAME_RELATED_P (insn
) = 1;
8922 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8927 /* Return a frame-related rtx that stores REG at MEM.
8928 REG must be a single register. */
8931 mips_frame_set (rtx mem
, rtx reg
)
8935 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8936 RTX_FRAME_RELATED_P (set
) = 1;
8941 /* Record that the epilogue has restored call-saved register REG. */
8944 mips_add_cfa_restore (rtx reg
)
8946 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8947 mips_epilogue
.cfa_restores
);
8950 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8951 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8952 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8953 static const unsigned char mips16e_s2_s8_regs
[] = {
8954 30, 23, 22, 21, 20, 19, 18
8956 static const unsigned char mips16e_a0_a3_regs
[] = {
8960 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8961 ordered from the uppermost in memory to the lowest in memory. */
8962 static const unsigned char mips16e_save_restore_regs
[] = {
8963 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8966 /* Return the index of the lowest X in the range [0, SIZE) for which
8967 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8970 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8975 for (i
= 0; i
< size
; i
++)
8976 if (BITSET_P (mask
, regs
[i
]))
8982 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8983 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8984 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8985 is true for all indexes (X, SIZE). */
8988 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8989 unsigned int size
, unsigned int *num_regs_ptr
)
8993 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8994 for (i
++; i
< size
; i
++)
8995 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8998 *mask_ptr
|= 1 << regs
[i
];
9002 /* Return a simplified form of X using the register values in REG_VALUES.
9003 REG_VALUES[R] is the last value assigned to hard register R, or null
9004 if R has not been modified.
9006 This function is rather limited, but is good enough for our purposes. */
9009 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
9011 x
= avoid_constant_pool_reference (x
);
9015 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9016 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9017 x0
, GET_MODE (XEXP (x
, 0)));
9020 if (ARITHMETIC_P (x
))
9022 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9023 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9024 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9028 && reg_values
[REGNO (x
)]
9029 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9030 return reg_values
[REGNO (x
)];
9035 /* Return true if (set DEST SRC) stores an argument register into its
9036 caller-allocated save slot, storing the number of that argument
9037 register in *REGNO_PTR if so. REG_VALUES is as for
9038 mips16e_collect_propagate_value. */
9041 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9042 unsigned int *regno_ptr
)
9044 unsigned int argno
, regno
;
9045 HOST_WIDE_INT offset
, required_offset
;
9048 /* Check that this is a word-mode store. */
9049 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9052 /* Check that the register being saved is an unmodified argument
9054 regno
= REGNO (src
);
9055 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9057 argno
= regno
- GP_ARG_FIRST
;
9059 /* Check whether the address is an appropriate stack-pointer or
9060 frame-pointer access. */
9061 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9062 mips_split_plus (addr
, &base
, &offset
);
9063 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9064 if (base
== hard_frame_pointer_rtx
)
9065 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9066 else if (base
!= stack_pointer_rtx
)
9068 if (offset
!= required_offset
)
9075 /* A subroutine of mips_expand_prologue, called only when generating
9076 MIPS16e SAVE instructions. Search the start of the function for any
9077 instructions that save argument registers into their caller-allocated
9078 save slots. Delete such instructions and return a value N such that
9079 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9080 instructions redundant. */
9083 mips16e_collect_argument_saves (void)
9085 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9086 rtx insn
, next
, set
, dest
, src
;
9087 unsigned int nargs
, regno
;
9089 push_topmost_sequence ();
9091 memset (reg_values
, 0, sizeof (reg_values
));
9092 for (insn
= get_insns (); insn
; insn
= next
)
9094 next
= NEXT_INSN (insn
);
9095 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9101 set
= PATTERN (insn
);
9102 if (GET_CODE (set
) != SET
)
9105 dest
= SET_DEST (set
);
9106 src
= SET_SRC (set
);
9107 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9109 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9112 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9115 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9116 reg_values
[REGNO (dest
)]
9117 = mips16e_collect_propagate_value (src
, reg_values
);
9121 pop_topmost_sequence ();
9126 /* Return a move between register REGNO and memory location SP + OFFSET.
9127 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9128 Make the move a load if RESTORE_P, otherwise make it a store. */
9131 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9132 HOST_WIDE_INT offset
, unsigned int regno
)
9136 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9138 reg
= gen_rtx_REG (SImode
, regno
);
9141 mips_add_cfa_restore (reg
);
9142 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9145 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9146 return mips_frame_set (mem
, reg
);
9149 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9150 The instruction must:
9152 - Allocate or deallocate SIZE bytes in total; SIZE is known
9155 - Save or restore as many registers in *MASK_PTR as possible.
9156 The instruction saves the first registers at the top of the
9157 allocated area, with the other registers below it.
9159 - Save NARGS argument registers above the allocated area.
9161 (NARGS is always zero if RESTORE_P.)
9163 The SAVE and RESTORE instructions cannot save and restore all general
9164 registers, so there may be some registers left over for the caller to
9165 handle. Destructively modify *MASK_PTR so that it contains the registers
9166 that still need to be saved or restored. The caller can save these
9167 registers in the memory immediately below *OFFSET_PTR, which is a
9168 byte offset from the bottom of the allocated stack area. */
9171 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9172 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9176 HOST_WIDE_INT offset
, top_offset
;
9177 unsigned int i
, regno
;
9180 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9182 /* Calculate the number of elements in the PARALLEL. We need one element
9183 for the stack adjustment, one for each argument register save, and one
9184 for each additional register move. */
9186 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9187 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9190 /* Create the final PARALLEL. */
9191 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9194 /* Add the stack pointer adjustment. */
9195 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9196 plus_constant (Pmode
, stack_pointer_rtx
,
9197 restore_p
? size
: -size
));
9198 RTX_FRAME_RELATED_P (set
) = 1;
9199 XVECEXP (pattern
, 0, n
++) = set
;
9201 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9202 top_offset
= restore_p
? size
: 0;
9204 /* Save the arguments. */
9205 for (i
= 0; i
< nargs
; i
++)
9207 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9208 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9210 XVECEXP (pattern
, 0, n
++) = set
;
9213 /* Then fill in the other register moves. */
9214 offset
= top_offset
;
9215 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9217 regno
= mips16e_save_restore_regs
[i
];
9218 if (BITSET_P (*mask_ptr
, regno
))
9220 offset
-= UNITS_PER_WORD
;
9221 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9222 XVECEXP (pattern
, 0, n
++) = set
;
9223 *mask_ptr
&= ~(1 << regno
);
9227 /* Tell the caller what offset it should use for the remaining registers. */
9228 *offset_ptr
= size
+ (offset
- top_offset
);
9230 gcc_assert (n
== XVECLEN (pattern
, 0));
9235 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9236 pointer. Return true if PATTERN matches the kind of instruction
9237 generated by mips16e_build_save_restore. If INFO is nonnull,
9238 initialize it when returning true. */
9241 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9242 struct mips16e_save_restore_info
*info
)
9244 unsigned int i
, nargs
, mask
, extra
;
9245 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9246 rtx set
, reg
, mem
, base
;
9249 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9252 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9253 top_offset
= adjust
> 0 ? adjust
: 0;
9255 /* Interpret all other members of the PARALLEL. */
9256 save_offset
= top_offset
- UNITS_PER_WORD
;
9260 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9262 /* Check that we have a SET. */
9263 set
= XVECEXP (pattern
, 0, n
);
9264 if (GET_CODE (set
) != SET
)
9267 /* Check that the SET is a load (if restoring) or a store
9269 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9273 /* Check that the address is the sum of the stack pointer and a
9274 possibly-zero constant offset. */
9275 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9276 if (base
!= stack_pointer_rtx
)
9279 /* Check that SET's other operand is a register. */
9280 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9284 /* Check for argument saves. */
9285 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9286 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9288 else if (offset
== save_offset
)
9290 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9291 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9294 mask
|= 1 << REGNO (reg
);
9295 save_offset
-= UNITS_PER_WORD
;
9301 /* Check that the restrictions on register ranges are met. */
9303 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9304 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9305 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9306 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9310 /* Make sure that the topmost argument register is not saved twice.
9311 The checks above ensure that the same is then true for the other
9312 argument registers. */
9313 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9316 /* Pass back information, if requested. */
9319 info
->nargs
= nargs
;
9321 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9327 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9328 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9329 the null terminator. */
9332 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9333 unsigned int max_reg
)
9335 if (min_reg
!= max_reg
)
9336 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9338 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9342 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9343 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9346 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9348 static char buffer
[300];
9350 struct mips16e_save_restore_info info
;
9351 unsigned int i
, end
;
9354 /* Parse the pattern. */
9355 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9358 /* Add the mnemonic. */
9359 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9362 /* Save the arguments. */
9364 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9365 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9366 else if (info
.nargs
== 1)
9367 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9369 /* Emit the amount of stack space to allocate or deallocate. */
9370 s
+= sprintf (s
, "%d", (int) info
.size
);
9372 /* Save or restore $16. */
9373 if (BITSET_P (info
.mask
, 16))
9374 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9376 /* Save or restore $17. */
9377 if (BITSET_P (info
.mask
, 17))
9378 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9380 /* Save or restore registers in the range $s2...$s8, which
9381 mips16e_s2_s8_regs lists in decreasing order. Note that this
9382 is a software register range; the hardware registers are not
9383 numbered consecutively. */
9384 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9385 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9387 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9388 mips16e_s2_s8_regs
[i
]);
9390 /* Save or restore registers in the range $a0...$a3. */
9391 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9392 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9394 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9395 mips16e_a0_a3_regs
[end
- 1]);
9397 /* Save or restore $31. */
9398 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9399 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9404 /* Return true if the current function returns its value in a floating-point
9405 register in MIPS16 mode. */
9408 mips16_cfun_returns_in_fpr_p (void)
9410 tree return_type
= DECL_RESULT (current_function_decl
);
9411 return (TARGET_MIPS16
9412 && TARGET_HARD_FLOAT_ABI
9413 && !aggregate_value_p (return_type
, current_function_decl
)
9414 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9417 /* Return true if predicate PRED is true for at least one instruction.
9418 Cache the result in *CACHE, and assume that the result is true
9419 if *CACHE is already true. */
9422 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9428 push_topmost_sequence ();
9429 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9430 if (USEFUL_INSN_P (insn
) && pred (insn
))
9435 pop_topmost_sequence ();
9440 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9441 See mips_cfun_has_inflexible_gp_ref_p for details. */
9444 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9446 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9447 indicate that the target could be a traditional MIPS
9448 lazily-binding stub. */
9449 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9452 /* Return true if the current function refers to the global pointer
9453 in a way that forces $28 to be valid. This means that we can't
9454 change the choice of global pointer, even for NewABI code.
9456 One example of this (and one which needs several checks) is that
9457 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9458 (This restriction does not apply to PLTs.) */
9461 mips_cfun_has_inflexible_gp_ref_p (void)
9463 /* If the function has a nonlocal goto, $28 must hold the correct
9464 global pointer for the target function. That is, the target
9465 of the goto implicitly uses $28. */
9466 if (crtl
->has_nonlocal_goto
)
9469 if (TARGET_ABICALLS_PIC2
)
9471 /* Symbolic accesses implicitly use the global pointer unless
9472 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9473 might go to traditional MIPS lazy-binding stubs. */
9474 if (!TARGET_EXPLICIT_RELOCS
)
9477 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9478 can be lazily-bound. */
9482 /* MIPS16 functions that return in FPRs need to call an
9483 external libgcc routine. This call is only made explict
9484 during mips_expand_epilogue, and it too might be lazily bound. */
9485 if (mips16_cfun_returns_in_fpr_p ())
9489 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9490 mips_insn_has_inflexible_gp_ref_p
);
9493 /* Return true if INSN refers to the global pointer in a "flexible" way.
9494 See mips_cfun_has_flexible_gp_ref_p for details. */
9497 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9499 return (get_attr_got (insn
) != GOT_UNSET
9500 || mips_small_data_pattern_p (PATTERN (insn
))
9501 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9504 /* Return true if the current function references the global pointer,
9505 but if those references do not inherently require the global pointer
9506 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9509 mips_cfun_has_flexible_gp_ref_p (void)
9511 /* Reload can sometimes introduce constant pool references
9512 into a function that otherwise didn't need them. For example,
9513 suppose we have an instruction like:
9515 (set (reg:DF R1) (float:DF (reg:SI R2)))
9517 If R2 turns out to be a constant such as 1, the instruction may
9518 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9519 the option of using this constant if R2 doesn't get allocated
9522 In cases like these, reload will have added the constant to the
9523 pool but no instruction will yet refer to it. */
9524 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9527 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9528 mips_insn_has_flexible_gp_ref_p
);
9531 /* Return the register that should be used as the global pointer
9532 within this function. Return INVALID_REGNUM if the function
9533 doesn't need a global pointer. */
9536 mips_global_pointer (void)
9540 /* $gp is always available unless we're using a GOT. */
9541 if (!TARGET_USE_GOT
)
9542 return GLOBAL_POINTER_REGNUM
;
9544 /* If there are inflexible references to $gp, we must use the
9545 standard register. */
9546 if (mips_cfun_has_inflexible_gp_ref_p ())
9547 return GLOBAL_POINTER_REGNUM
;
9549 /* If there are no current references to $gp, then the only uses
9550 we can introduce later are those involved in long branches. */
9551 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9552 return INVALID_REGNUM
;
9554 /* If the global pointer is call-saved, try to use a call-clobbered
9556 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9557 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9558 if (!df_regs_ever_live_p (regno
)
9559 && call_really_used_regs
[regno
]
9560 && !fixed_regs
[regno
]
9561 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9564 return GLOBAL_POINTER_REGNUM
;
9567 /* Return true if the current function's prologue must load the global
9568 pointer value into pic_offset_table_rtx and store the same value in
9569 the function's cprestore slot (if any).
9571 One problem we have to deal with is that, when emitting GOT-based
9572 position independent code, long-branch sequences will need to load
9573 the address of the branch target from the GOT. We don't know until
9574 the very end of compilation whether (and where) the function needs
9575 long branches, so we must ensure that _any_ branch can access the
9576 global pointer in some form. However, we do not want to pessimize
9577 the usual case in which all branches are short.
9579 We handle this as follows:
9581 (1) During reload, we set cfun->machine->global_pointer to
9582 INVALID_REGNUM if we _know_ that the current function
9583 doesn't need a global pointer. This is only valid if
9584 long branches don't need the GOT.
9586 Otherwise, we assume that we might need a global pointer
9587 and pick an appropriate register.
9589 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9590 we ensure that the global pointer is available at every
9591 block boundary bar entry and exit. We do this in one of two ways:
9593 - If the function has a cprestore slot, we ensure that this
9594 slot is valid at every branch. However, as explained in
9595 point (6) below, there is no guarantee that pic_offset_table_rtx
9596 itself is valid if new uses of the global pointer are introduced
9597 after the first post-epilogue split.
9599 We guarantee that the cprestore slot is valid by loading it
9600 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9601 this register live at every block boundary bar function entry
9602 and exit. It is then invalid to move the load (and thus the
9603 preceding store) across a block boundary.
9605 - If the function has no cprestore slot, we guarantee that
9606 pic_offset_table_rtx itself is valid at every branch.
9608 See mips_eh_uses for the handling of the register liveness.
9610 (3) During prologue and epilogue generation, we emit "ghost"
9611 placeholder instructions to manipulate the global pointer.
9613 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9614 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9615 that the function needs a global pointer. (There is no need to set
9616 them earlier than this, and doing it as late as possible leads to
9617 fewer false positives.)
9619 (5) If cfun->machine->must_initialize_gp_p is true during a
9620 split_insns pass, we split the ghost instructions into real
9621 instructions. These split instructions can then be optimized in
9622 the usual way. Otherwise, we keep the ghost instructions intact,
9623 and optimize for the case where they aren't needed. We still
9624 have the option of splitting them later, if we need to introduce
9625 new uses of the global pointer.
9627 For example, the scheduler ignores a ghost instruction that
9628 stores $28 to the stack, but it handles the split form of
9629 the ghost instruction as an ordinary store.
9631 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9632 is true during the first post-epilogue split_insns pass, we split
9633 calls and restore_gp patterns into instructions that explicitly
9634 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9635 we split these patterns into instructions that _don't_ load from
9638 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9639 time of the split, then any instructions that exist at that time
9640 can make free use of pic_offset_table_rtx. However, if we want
9641 to introduce new uses of the global pointer after the split,
9642 we must explicitly load the value from the cprestore slot, since
9643 pic_offset_table_rtx itself might not be valid at a given point
9646 The idea is that we want to be able to delete redundant
9647 loads from the cprestore slot in the usual case where no
9648 long branches are needed.
9650 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9651 of md_reorg, we decide whether the global pointer is needed for
9652 long branches. If so, we set cfun->machine->must_initialize_gp_p
9653 to true and split the ghost instructions into real instructions
9656 Note that the ghost instructions must have a zero length for three reasons:
9658 - Giving the length of the underlying $gp sequence might cause
9659 us to use long branches in cases where they aren't really needed.
9661 - They would perturb things like alignment calculations.
9663 - More importantly, the hazard detection in md_reorg relies on
9664 empty instructions having a zero length.
9666 If we find a long branch and split the ghost instructions at the
9667 end of md_reorg, the split could introduce more long branches.
9668 That isn't a problem though, because we still do the split before
9669 the final shorten_branches pass.
9671 This is extremely ugly, but it seems like the best compromise between
9672 correctness and efficiency. */
9675 mips_must_initialize_gp_p (void)
9677 return cfun
->machine
->must_initialize_gp_p
;
9680 /* Return true if REGNO is a register that is ordinarily call-clobbered
9681 but must nevertheless be preserved by an interrupt handler. */
9684 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9686 if (MD_REG_P (regno
))
9689 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9692 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9694 /* $0 is hard-wired. */
9695 if (regno
== GP_REG_FIRST
)
9698 /* The interrupt handler can treat kernel registers as
9699 scratch registers. */
9700 if (KERNEL_REG_P (regno
))
9703 /* The function will return the stack pointer to its original value
9705 if (regno
== STACK_POINTER_REGNUM
)
9708 /* Otherwise, return true for registers that aren't ordinarily
9710 return call_really_used_regs
[regno
];
9716 /* Return true if the current function should treat register REGNO
9720 mips_cfun_call_saved_reg_p (unsigned int regno
)
9722 /* If the user makes an ordinarily-call-saved register global,
9723 that register is no longer call-saved. */
9724 if (global_regs
[regno
])
9727 /* Interrupt handlers need to save extra registers. */
9728 if (cfun
->machine
->interrupt_handler_p
9729 && mips_interrupt_extra_call_saved_reg_p (regno
))
9732 /* call_insns preserve $28 unless they explicitly say otherwise,
9733 so call_really_used_regs[] treats $28 as call-saved. However,
9734 we want the ABI property rather than the default call_insn
9736 return (regno
== GLOBAL_POINTER_REGNUM
9737 ? TARGET_CALL_SAVED_GP
9738 : !call_really_used_regs
[regno
]);
9741 /* Return true if the function body might clobber register REGNO.
9742 We know that REGNO is call-saved. */
9745 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9747 /* Some functions should be treated as clobbering all call-saved
9749 if (crtl
->saves_all_registers
)
9752 /* DF handles cases where a register is explicitly referenced in
9753 the rtl. Incoming values are passed in call-clobbered registers,
9754 so we can assume that any live call-saved register is set within
9756 if (df_regs_ever_live_p (regno
))
9759 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9760 These clobbers are not explicit in the rtl. */
9761 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9764 /* If we're using a call-saved global pointer, the function's
9765 prologue will need to set it up. */
9766 if (cfun
->machine
->global_pointer
== regno
)
9769 /* The function's prologue will need to set the frame pointer if
9770 frame_pointer_needed. */
9771 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9774 /* If a MIPS16 function returns a value in FPRs, its epilogue
9775 will need to call an external libgcc routine. This yet-to-be
9776 generated call_insn will clobber $31. */
9777 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9780 /* If REGNO is ordinarily call-clobbered, we must assume that any
9781 called function could modify it. */
9782 if (cfun
->machine
->interrupt_handler_p
9784 && mips_interrupt_extra_call_saved_reg_p (regno
))
9790 /* Return true if the current function must save register REGNO. */
9793 mips_save_reg_p (unsigned int regno
)
9795 if (mips_cfun_call_saved_reg_p (regno
))
9797 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9800 /* Save both registers in an FPR pair if either one is used. This is
9801 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9802 register to be used without the even register. */
9803 if (FP_REG_P (regno
)
9804 && MAX_FPRS_PER_FMT
== 2
9805 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9809 /* We need to save the incoming return address if __builtin_eh_return
9810 is being used to set a different return address. */
9811 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9817 /* Populate the current function's mips_frame_info structure.
9819 MIPS stack frames look like:
9821 +-------------------------------+
9823 | incoming stack arguments |
9825 +-------------------------------+
9827 | caller-allocated save area |
9828 A | for register arguments |
9830 +-------------------------------+ <-- incoming stack pointer
9832 | callee-allocated save area |
9833 B | for arguments that are |
9834 | split between registers and |
9837 +-------------------------------+ <-- arg_pointer_rtx
9839 C | callee-allocated save area |
9840 | for register varargs |
9842 +-------------------------------+ <-- frame_pointer_rtx
9843 | | + cop0_sp_offset
9844 | COP0 reg save area | + UNITS_PER_WORD
9846 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9847 | | + UNITS_PER_WORD
9848 | accumulator save area |
9850 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9851 | | + UNITS_PER_HWFPVALUE
9854 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9855 | | + UNITS_PER_WORD
9858 +-------------------------------+ <-- frame_pointer_rtx with
9859 | | \ -fstack-protector
9860 | local variables | | var_size
9862 +-------------------------------+
9864 | $gp save area | | cprestore_size
9866 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9868 | outgoing stack arguments | |
9870 +-------------------------------+ | args_size
9872 | caller-allocated save area | |
9873 | for register arguments | |
9875 +-------------------------------+ <-- stack_pointer_rtx
9876 frame_pointer_rtx without
9878 hard_frame_pointer_rtx for
9881 At least two of A, B and C will be empty.
9883 Dynamic stack allocations such as alloca insert data at point P.
9884 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9885 hard_frame_pointer_rtx unchanged. */
9888 mips_compute_frame_info (void)
9890 struct mips_frame_info
*frame
;
9891 HOST_WIDE_INT offset
, size
;
9892 unsigned int regno
, i
;
9894 /* Set this function's interrupt properties. */
9895 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9898 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9899 else if (TARGET_HARD_FLOAT
)
9900 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9901 else if (TARGET_MIPS16
)
9902 error ("interrupt handlers cannot be MIPS16 functions");
9905 cfun
->machine
->interrupt_handler_p
= true;
9906 cfun
->machine
->use_shadow_register_set_p
=
9907 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9908 cfun
->machine
->keep_interrupts_masked_p
=
9909 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9910 cfun
->machine
->use_debug_exception_return_p
=
9911 mips_use_debug_exception_return_p (TREE_TYPE
9912 (current_function_decl
));
9916 frame
= &cfun
->machine
->frame
;
9917 memset (frame
, 0, sizeof (*frame
));
9918 size
= get_frame_size ();
9920 cfun
->machine
->global_pointer
= mips_global_pointer ();
9922 /* The first two blocks contain the outgoing argument area and the $gp save
9923 slot. This area isn't needed in leaf functions, but if the
9924 target-independent frame size is nonzero, we have already committed to
9925 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9926 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
9928 /* The MIPS 3.0 linker does not like functions that dynamically
9929 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9930 looks like we are trying to create a second frame pointer to the
9931 function, so allocate some stack space to make it happy. */
9932 if (cfun
->calls_alloca
)
9933 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9935 frame
->args_size
= 0;
9936 frame
->cprestore_size
= 0;
9940 frame
->args_size
= crtl
->outgoing_args_size
;
9941 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9943 offset
= frame
->args_size
+ frame
->cprestore_size
;
9945 /* Move above the local variables. */
9946 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9947 offset
+= frame
->var_size
;
9949 /* Find out which GPRs we need to save. */
9950 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9951 if (mips_save_reg_p (regno
))
9954 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9957 /* If this function calls eh_return, we must also save and restore the
9958 EH data registers. */
9959 if (crtl
->calls_eh_return
)
9960 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9963 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9966 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9967 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9968 save all later registers too. */
9969 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9971 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9972 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9973 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9974 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9977 /* Move above the GPR save area. */
9978 if (frame
->num_gp
> 0)
9980 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9981 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9984 /* Find out which FPRs we need to save. This loop must iterate over
9985 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9986 if (TARGET_HARD_FLOAT
)
9987 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9988 if (mips_save_reg_p (regno
))
9990 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9991 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9994 /* Move above the FPR save area. */
9995 if (frame
->num_fp
> 0)
9997 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9998 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
10001 /* Add in space for the interrupt context information. */
10002 if (cfun
->machine
->interrupt_handler_p
)
10005 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
10008 frame
->acc_mask
|= (1 << 0);
10011 /* Check accumulators 1, 2, 3. */
10012 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10013 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10016 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10019 /* All interrupt context functions need space to preserve STATUS. */
10020 frame
->num_cop0_regs
++;
10022 /* If we don't keep interrupts masked, we need to save EPC. */
10023 if (!cfun
->machine
->keep_interrupts_masked_p
)
10024 frame
->num_cop0_regs
++;
10027 /* Move above the accumulator save area. */
10028 if (frame
->num_acc
> 0)
10030 /* Each accumulator needs 2 words. */
10031 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10032 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10035 /* Move above the COP0 register save area. */
10036 if (frame
->num_cop0_regs
> 0)
10038 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10039 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10042 /* Move above the callee-allocated varargs save area. */
10043 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10044 frame
->arg_pointer_offset
= offset
;
10046 /* Move above the callee-allocated area for pretend stack arguments. */
10047 offset
+= crtl
->args
.pretend_args_size
;
10048 frame
->total_size
= offset
;
10050 /* Work out the offsets of the save areas from the top of the frame. */
10051 if (frame
->gp_sp_offset
> 0)
10052 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10053 if (frame
->fp_sp_offset
> 0)
10054 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10055 if (frame
->acc_sp_offset
> 0)
10056 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10057 if (frame
->num_cop0_regs
> 0)
10058 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10060 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10061 arguments. This tends to increase the chances of using unextended
10062 instructions for local variables and incoming arguments. */
10064 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10067 /* Return the style of GP load sequence that is being used for the
10068 current function. */
10070 enum mips_loadgp_style
10071 mips_current_loadgp_style (void)
10073 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10074 return LOADGP_NONE
;
10076 if (TARGET_RTP_PIC
)
10079 if (TARGET_ABSOLUTE_ABICALLS
)
10080 return LOADGP_ABSOLUTE
;
10082 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10085 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10088 mips_frame_pointer_required (void)
10090 /* If the function contains dynamic stack allocations, we need to
10091 use the frame pointer to access the static parts of the frame. */
10092 if (cfun
->calls_alloca
)
10095 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10096 reload may be unable to compute the address of a local variable,
10097 since there is no way to add a large constant to the stack pointer
10098 without using a second temporary register. */
10101 mips_compute_frame_info ();
10102 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10109 /* Make sure that we're not trying to eliminate to the wrong hard frame
10113 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10115 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10118 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10119 or argument pointer. TO is either the stack pointer or hard frame
10123 mips_initial_elimination_offset (int from
, int to
)
10125 HOST_WIDE_INT offset
;
10127 mips_compute_frame_info ();
10129 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10132 case FRAME_POINTER_REGNUM
:
10133 if (FRAME_GROWS_DOWNWARD
)
10134 offset
= (cfun
->machine
->frame
.args_size
10135 + cfun
->machine
->frame
.cprestore_size
10136 + cfun
->machine
->frame
.var_size
);
10141 case ARG_POINTER_REGNUM
:
10142 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10146 gcc_unreachable ();
10149 if (to
== HARD_FRAME_POINTER_REGNUM
)
10150 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10155 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10158 mips_extra_live_on_entry (bitmap regs
)
10160 if (TARGET_USE_GOT
)
10162 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10163 the global pointer. */
10164 if (!TARGET_ABSOLUTE_ABICALLS
)
10165 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10167 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10168 the global pointer. */
10170 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10172 /* See the comment above load_call<mode> for details. */
10173 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10177 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10181 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10186 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10189 /* Emit code to change the current function's return address to
10190 ADDRESS. SCRATCH is available as a scratch register, if needed.
10191 ADDRESS and SCRATCH are both word-mode GPRs. */
10194 mips_set_return_address (rtx address
, rtx scratch
)
10198 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10199 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10200 cfun
->machine
->frame
.gp_sp_offset
);
10201 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10204 /* Return true if the current function has a cprestore slot. */
10207 mips_cfun_has_cprestore_slot_p (void)
10209 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10210 && cfun
->machine
->frame
.cprestore_size
> 0);
10213 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10214 cprestore slot. LOAD_P is true if the caller wants to load from
10215 the cprestore slot; it is false if the caller wants to store to
10219 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10222 const struct mips_frame_info
*frame
;
10224 frame
= &cfun
->machine
->frame
;
10225 /* .cprestore always uses the stack pointer instead of the frame pointer.
10226 We have a free choice for direct stores for non-MIPS16 functions,
10227 and for MIPS16 functions whose cprestore slot is in range of the
10228 stack pointer. Using the stack pointer would sometimes give more
10229 (early) scheduling freedom, but using the frame pointer would
10230 sometimes give more (late) scheduling freedom. It's hard to
10231 predict which applies to a given function, so let's keep things
10234 Loads must always use the frame pointer in functions that call
10235 alloca, and there's little benefit to using the stack pointer
10237 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10239 *base
= hard_frame_pointer_rtx
;
10240 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10244 *base
= stack_pointer_rtx
;
10245 *offset
= frame
->args_size
;
10249 /* Return true if X is the load or store address of the cprestore slot;
10250 LOAD_P says which. */
10253 mips_cprestore_address_p (rtx x
, bool load_p
)
10255 rtx given_base
, required_base
;
10256 HOST_WIDE_INT given_offset
, required_offset
;
10258 mips_split_plus (x
, &given_base
, &given_offset
);
10259 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10260 return given_base
== required_base
&& given_offset
== required_offset
;
10263 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10264 going to load from it, false if we are going to store to it.
10265 Use TEMP as a temporary register if need be. */
10268 mips_cprestore_slot (rtx temp
, bool load_p
)
10271 HOST_WIDE_INT offset
;
10273 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10274 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10277 /* Emit instructions to save global pointer value GP into cprestore
10278 slot MEM. OFFSET is the offset that MEM applies to the base register.
10280 MEM may not be a legitimate address. If it isn't, TEMP is a
10281 temporary register that can be used, otherwise it is a SCRATCH. */
10284 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10286 if (TARGET_CPRESTORE_DIRECTIVE
)
10288 gcc_assert (gp
== pic_offset_table_rtx
);
10289 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10292 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10295 /* Restore $gp from its save slot, using TEMP as a temporary base register
10296 if need be. This function is for o32 and o64 abicalls only.
10298 See mips_must_initialize_gp_p for details about how we manage the
10302 mips_restore_gp_from_cprestore_slot (rtx temp
)
10304 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10306 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10308 emit_note (NOTE_INSN_DELETED
);
10314 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10315 mips_emit_move (pic_offset_table_rtx
, temp
);
10318 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10319 if (!TARGET_EXPLICIT_RELOCS
)
10320 emit_insn (gen_blockage ());
10323 /* A function to save or store a register. The first argument is the
10324 register and the second is the stack slot. */
10325 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10327 /* Use FN to save or restore register REGNO. MODE is the register's
10328 mode and OFFSET is the offset of its save slot from the current
10332 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10333 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10337 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10339 fn (gen_rtx_REG (mode
, regno
), mem
);
10342 /* Call FN for each accumlator that is saved by the current function.
10343 SP_OFFSET is the offset of the current stack pointer from the start
10347 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10349 HOST_WIDE_INT offset
;
10352 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10353 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10355 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10356 offset
-= UNITS_PER_WORD
;
10357 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10358 offset
-= UNITS_PER_WORD
;
10361 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10362 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10363 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10365 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10366 offset
-= UNITS_PER_WORD
;
10370 /* Save register REG to MEM. Make the instruction frame-related. */
10373 mips_save_reg (rtx reg
, rtx mem
)
10375 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10379 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10381 x1
= mips_frame_set (mips_subword (mem
, false),
10382 mips_subword (reg
, false));
10383 x2
= mips_frame_set (mips_subword (mem
, true),
10384 mips_subword (reg
, true));
10385 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10388 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10391 /* Capture the register combinations that are allowed in a SWM or LWM
10392 instruction. The entries are ordered by number of registers set in
10393 the mask. We also ignore the single register encodings because a
10394 normal SW/LW is preferred. */
10396 static const unsigned int umips_swm_mask
[17] = {
10397 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10398 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10399 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10400 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10404 static const unsigned int umips_swm_encoding
[17] = {
10405 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10408 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10409 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10410 stack pointer of the topmost save slot.
10412 Remove from *MASK all registers that were handled using LWM and SWM.
10413 Update *OFFSET so that it points to the first unused save slot. */
10416 umips_build_save_restore (mips_save_restore_fn fn
,
10417 unsigned *mask
, HOST_WIDE_INT
*offset
)
10421 rtx pattern
, set
, reg
, mem
;
10422 HOST_WIDE_INT this_offset
;
10425 /* Try matching $16 to $31 (s0 to ra). */
10426 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10427 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10430 if (i
== ARRAY_SIZE (umips_swm_mask
))
10433 /* Get the offset of the lowest save slot. */
10434 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10435 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10437 /* LWM/SWM can only support offsets from -2048 to 2047. */
10438 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10441 /* Create the final PARALLEL. */
10442 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10443 this_base
= stack_pointer_rtx
;
10445 /* For registers $16-$23 and $30. */
10446 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10448 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10449 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10450 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10451 *mask
&= ~(1 << regno
);
10452 reg
= gen_rtx_REG (SImode
, regno
);
10453 if (fn
== mips_save_reg
)
10454 set
= mips_frame_set (mem
, reg
);
10457 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10458 mips_add_cfa_restore (reg
);
10460 XVECEXP (pattern
, 0, j
) = set
;
10463 /* For register $31. */
10464 if (umips_swm_encoding
[i
] >> 4)
10466 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10467 *mask
&= ~(1 << 31);
10468 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10469 reg
= gen_rtx_REG (SImode
, 31);
10470 if (fn
== mips_save_reg
)
10471 set
= mips_frame_set (mem
, reg
);
10474 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
10475 mips_add_cfa_restore (reg
);
10477 XVECEXP (pattern
, 0, j
) = set
;
10480 pattern
= emit_insn (pattern
);
10481 if (fn
== mips_save_reg
)
10482 RTX_FRAME_RELATED_P (pattern
) = 1;
10484 /* Adjust the last offset. */
10485 *offset
-= UNITS_PER_WORD
* nregs
;
10490 /* Call FN for each register that is saved by the current function.
10491 SP_OFFSET is the offset of the current stack pointer from the start
10495 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10496 mips_save_restore_fn fn
)
10498 enum machine_mode fpr_mode
;
10500 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10501 HOST_WIDE_INT offset
;
10504 /* Save registers starting from high to low. The debuggers prefer at least
10505 the return register be stored at func+4, and also it allows us not to
10506 need a nop in the epilogue if at least one register is reloaded in
10507 addition to return address. */
10508 offset
= frame
->gp_sp_offset
- sp_offset
;
10509 mask
= frame
->mask
;
10511 if (TARGET_MICROMIPS
)
10512 umips_build_save_restore (fn
, &mask
, &offset
);
10514 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10515 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10517 /* Record the ra offset for use by mips_function_profiler. */
10518 if (regno
== RETURN_ADDR_REGNUM
)
10519 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10520 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10521 offset
-= UNITS_PER_WORD
;
10524 /* This loop must iterate over the same space as its companion in
10525 mips_compute_frame_info. */
10526 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10527 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10528 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10529 regno
>= FP_REG_FIRST
;
10530 regno
-= MAX_FPRS_PER_FMT
)
10531 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10533 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10534 offset
-= GET_MODE_SIZE (fpr_mode
);
10538 /* Return true if a move between register REGNO and its save slot (MEM)
10539 can be done in a single move. LOAD_P is true if we are loading
10540 from the slot, false if we are storing to it. */
10543 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10545 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10546 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10549 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10550 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10553 /* Emit a move from SRC to DEST, given that one of them is a register
10554 save slot and that the other is a register. TEMP is a temporary
10555 GPR of the same mode that is available if need be. */
10558 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10560 unsigned int regno
;
10565 regno
= REGNO (src
);
10570 regno
= REGNO (dest
);
10574 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10576 /* We don't yet know whether we'll need this instruction or not.
10577 Postpone the decision by emitting a ghost move. This move
10578 is specifically not frame-related; only the split version is. */
10580 emit_insn (gen_move_gpdi (dest
, src
));
10582 emit_insn (gen_move_gpsi (dest
, src
));
10586 if (regno
== HI_REGNUM
)
10590 mips_emit_move (temp
, src
);
10592 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10593 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10595 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10596 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10601 emit_insn (gen_mfhidi_ti (temp
,
10602 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10604 emit_insn (gen_mfhisi_di (temp
,
10605 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10606 mips_emit_move (dest
, temp
);
10609 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10610 mips_emit_move (dest
, src
);
10613 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10614 mips_emit_move (temp
, src
);
10615 mips_emit_move (dest
, temp
);
10618 mips_set_frame_expr (mips_frame_set (dest
, src
));
10621 /* If we're generating n32 or n64 abicalls, and the current function
10622 does not use $28 as its global pointer, emit a cplocal directive.
10623 Use pic_offset_table_rtx as the argument to the directive. */
10626 mips_output_cplocal (void)
10628 if (!TARGET_EXPLICIT_RELOCS
10629 && mips_must_initialize_gp_p ()
10630 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10631 output_asm_insn (".cplocal %+", 0);
10634 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10637 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10639 const char *fnname
;
10641 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10642 floating-point arguments. */
10644 && TARGET_HARD_FLOAT_ABI
10645 && crtl
->args
.info
.fp_code
!= 0)
10646 mips16_build_function_stub ();
10648 /* Get the function name the same way that toplev.c does before calling
10649 assemble_start_function. This is needed so that the name used here
10650 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10651 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10652 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10654 /* Output MIPS-specific frame information. */
10655 if (!flag_inhibit_size_directive
)
10657 const struct mips_frame_info
*frame
;
10659 frame
= &cfun
->machine
->frame
;
10661 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10663 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10664 "# vars= " HOST_WIDE_INT_PRINT_DEC
10666 ", args= " HOST_WIDE_INT_PRINT_DEC
10667 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10668 reg_names
[frame_pointer_needed
10669 ? HARD_FRAME_POINTER_REGNUM
10670 : STACK_POINTER_REGNUM
],
10671 (frame_pointer_needed
10672 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10673 : frame
->total_size
),
10674 reg_names
[RETURN_ADDR_REGNUM
],
10676 frame
->num_gp
, frame
->num_fp
,
10678 frame
->cprestore_size
);
10680 /* .mask MASK, OFFSET. */
10681 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10682 frame
->mask
, frame
->gp_save_offset
);
10684 /* .fmask MASK, OFFSET. */
10685 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10686 frame
->fmask
, frame
->fp_save_offset
);
10689 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10690 Also emit the ".set noreorder; .set nomacro" sequence for functions
10692 if (mips_must_initialize_gp_p ()
10693 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10697 /* This is a fixed-form sequence. The position of the
10698 first two instructions is important because of the
10699 way _gp_disp is defined. */
10700 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10701 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10702 output_asm_insn ("sll\t$2,16", 0);
10703 output_asm_insn ("addu\t$2,$3", 0);
10707 /* .cpload must be in a .set noreorder but not a
10708 .set nomacro block. */
10709 mips_push_asm_switch (&mips_noreorder
);
10710 output_asm_insn (".cpload\t%^", 0);
10711 if (!cfun
->machine
->all_noreorder_p
)
10712 mips_pop_asm_switch (&mips_noreorder
);
10714 mips_push_asm_switch (&mips_nomacro
);
10717 else if (cfun
->machine
->all_noreorder_p
)
10719 mips_push_asm_switch (&mips_noreorder
);
10720 mips_push_asm_switch (&mips_nomacro
);
10723 /* Tell the assembler which register we're using as the global
10724 pointer. This is needed for thunks, since they can use either
10725 explicit relocs or assembler macros. */
10726 mips_output_cplocal ();
10729 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10732 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10733 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10735 const char *fnname
;
10737 /* Reinstate the normal $gp. */
10738 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10739 mips_output_cplocal ();
10741 if (cfun
->machine
->all_noreorder_p
)
10743 mips_pop_asm_switch (&mips_nomacro
);
10744 mips_pop_asm_switch (&mips_noreorder
);
10747 /* Get the function name the same way that toplev.c does before calling
10748 assemble_start_function. This is needed so that the name used here
10749 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10750 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10751 mips_end_function_definition (fnname
);
10754 /* Emit an optimisation barrier for accesses to the current frame. */
10757 mips_frame_barrier (void)
10759 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10763 /* The __gnu_local_gp symbol. */
10765 static GTY(()) rtx mips_gnu_local_gp
;
10767 /* If we're generating n32 or n64 abicalls, emit instructions
10768 to set up the global pointer. */
10771 mips_emit_loadgp (void)
10773 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10775 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10776 switch (mips_current_loadgp_style ())
10778 case LOADGP_ABSOLUTE
:
10779 if (mips_gnu_local_gp
== NULL
)
10781 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10782 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10784 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10785 (pic_reg
, mips_gnu_local_gp
)));
10788 case LOADGP_OLDABI
:
10789 /* Added by mips_output_function_prologue. */
10792 case LOADGP_NEWABI
:
10793 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10794 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10795 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10796 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10797 (pic_reg
, offset
, incoming_address
)));
10801 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10802 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10803 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10811 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10812 (pic_offset_table_rtx
, pic_reg
)));
10814 /* Emit a blockage if there are implicit uses of the GP register.
10815 This includes profiled functions, because FUNCTION_PROFILE uses
10817 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10818 emit_insn (gen_loadgp_blockage ());
10821 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10823 #if PROBE_INTERVAL > 32768
10824 #error Cannot use indexed addressing mode for stack probing
10827 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10828 inclusive. These are offsets from the current stack pointer. */
10831 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10834 sorry ("-fstack-check=specific not implemented for MIPS16");
10836 /* See if we have a constant small number of probes to generate. If so,
10837 that's the easy case. */
10838 if (first
+ size
<= 32768)
10842 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10843 it exceeds SIZE. If only one probe is needed, this will not
10844 generate any code. Then probe at FIRST + SIZE. */
10845 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10846 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10849 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10853 /* Otherwise, do the same as above, but in a loop. Note that we must be
10854 extra careful with variables wrapping around because we might be at
10855 the very top (or the very bottom) of the address space and we have
10856 to be able to handle this case properly; in particular, we use an
10857 equality test for the loop condition. */
10860 HOST_WIDE_INT rounded_size
;
10861 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
10862 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
10864 /* Sanity check for the addressing mode we're going to use. */
10865 gcc_assert (first
<= 32768);
10868 /* Step 1: round SIZE to the previous multiple of the interval. */
10870 rounded_size
= size
& -PROBE_INTERVAL
;
10873 /* Step 2: compute initial and final value of the loop counter. */
10875 /* TEST_ADDR = SP + FIRST. */
10876 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
10877 plus_constant (Pmode
, stack_pointer_rtx
,
10880 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10881 if (rounded_size
> 32768)
10883 emit_move_insn (r12
, GEN_INT (rounded_size
));
10884 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10885 gen_rtx_MINUS (Pmode
, r3
, r12
)));
10888 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10889 plus_constant (Pmode
, r3
, -rounded_size
)));
10892 /* Step 3: the loop
10894 while (TEST_ADDR != LAST_ADDR)
10896 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10900 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10901 until it is equal to ROUNDED_SIZE. */
10903 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
10906 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10907 that SIZE is equal to ROUNDED_SIZE. */
10909 if (size
!= rounded_size
)
10910 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
10913 /* Make sure nothing is scheduled before we are done. */
10914 emit_insn (gen_blockage ());
10917 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10918 absolute addresses. */
10921 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
10923 static int labelno
= 0;
10924 char loop_lab
[32], end_lab
[32], tmp
[64];
10927 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
10928 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
10930 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
10932 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10935 strcpy (tmp
, "%(%<beq\t%0,%1,");
10936 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
10938 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10939 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
10940 if (TARGET_64BIT
&& TARGET_LONG64
)
10941 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
10943 output_asm_insn ("addiu\t%0,%0,%1", xops
);
10945 /* Probe at TEST_ADDR and branch. */
10946 fprintf (asm_out_file
, "\tb\t");
10947 assemble_name_raw (asm_out_file
, loop_lab
);
10948 fputc ('\n', asm_out_file
);
10950 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
10952 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
10954 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
10959 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10962 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10964 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10967 /* Expand the "prologue" pattern. */
10970 mips_expand_prologue (void)
10972 const struct mips_frame_info
*frame
;
10973 HOST_WIDE_INT size
;
10974 unsigned int nargs
;
10977 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10979 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10980 or implicitly. If so, we can commit to using a global pointer
10981 straight away, otherwise we need to defer the decision. */
10982 if (mips_cfun_has_inflexible_gp_ref_p ()
10983 || mips_cfun_has_flexible_gp_ref_p ())
10985 cfun
->machine
->must_initialize_gp_p
= true;
10986 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10989 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10992 frame
= &cfun
->machine
->frame
;
10993 size
= frame
->total_size
;
10995 if (flag_stack_usage_info
)
10996 current_function_static_stack_size
= size
;
10998 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
11000 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
11002 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
11003 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
11004 size
- STACK_CHECK_PROTECT
);
11007 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
11010 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11011 bytes beforehand; this is enough to cover the register save area
11012 without going out of range. */
11013 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
11014 || frame
->num_cop0_regs
> 0)
11016 HOST_WIDE_INT step1
;
11018 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
11019 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11021 HOST_WIDE_INT offset
;
11022 unsigned int mask
, regno
;
11024 /* Try to merge argument stores into the save instruction. */
11025 nargs
= mips16e_collect_argument_saves ();
11027 /* Build the save instruction. */
11028 mask
= frame
->mask
;
11029 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11031 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11032 mips_frame_barrier ();
11035 /* Check if we need to save other registers. */
11036 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11037 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11039 offset
-= UNITS_PER_WORD
;
11040 mips_save_restore_reg (word_mode
, regno
,
11041 offset
, mips_save_reg
);
11046 if (cfun
->machine
->interrupt_handler_p
)
11048 HOST_WIDE_INT offset
;
11051 /* If this interrupt is using a shadow register set, we need to
11052 get the stack pointer from the previous register set. */
11053 if (cfun
->machine
->use_shadow_register_set_p
)
11054 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11055 stack_pointer_rtx
));
11057 if (!cfun
->machine
->keep_interrupts_masked_p
)
11059 /* Move from COP0 Cause to K0. */
11060 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11061 gen_rtx_REG (SImode
,
11062 COP0_CAUSE_REG_NUM
)));
11063 /* Move from COP0 EPC to K1. */
11064 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11065 gen_rtx_REG (SImode
,
11066 COP0_EPC_REG_NUM
)));
11069 /* Allocate the first part of the frame. */
11070 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11072 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11073 mips_frame_barrier ();
11076 /* Start at the uppermost location for saving. */
11077 offset
= frame
->cop0_sp_offset
- size
;
11078 if (!cfun
->machine
->keep_interrupts_masked_p
)
11080 /* Push EPC into its stack slot. */
11081 mem
= gen_frame_mem (word_mode
,
11082 plus_constant (Pmode
, stack_pointer_rtx
,
11084 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11085 offset
-= UNITS_PER_WORD
;
11088 /* Move from COP0 Status to K1. */
11089 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11090 gen_rtx_REG (SImode
,
11091 COP0_STATUS_REG_NUM
)));
11093 /* Right justify the RIPL in k0. */
11094 if (!cfun
->machine
->keep_interrupts_masked_p
)
11095 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11096 gen_rtx_REG (SImode
, K0_REG_NUM
),
11097 GEN_INT (CAUSE_IPL
)));
11099 /* Push Status into its stack slot. */
11100 mem
= gen_frame_mem (word_mode
,
11101 plus_constant (Pmode
, stack_pointer_rtx
,
11103 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11104 offset
-= UNITS_PER_WORD
;
11106 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11107 if (!cfun
->machine
->keep_interrupts_masked_p
)
11108 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11111 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11113 if (!cfun
->machine
->keep_interrupts_masked_p
)
11114 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11115 IE is already the correct value, so we don't have to do
11116 anything explicit. */
11117 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11120 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11122 /* Disable interrupts by clearing the KSU, ERL, EXL,
11124 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11127 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11131 insn
= gen_add3_insn (stack_pointer_rtx
,
11134 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11135 mips_frame_barrier ();
11138 mips_for_each_saved_acc (size
, mips_save_reg
);
11139 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11143 /* Allocate the rest of the frame. */
11146 if (SMALL_OPERAND (-size
))
11147 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11149 GEN_INT (-size
)))) = 1;
11152 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11155 /* There are no instructions to add or subtract registers
11156 from the stack pointer, so use the frame pointer as a
11157 temporary. We should always be using a frame pointer
11158 in this case anyway. */
11159 gcc_assert (frame_pointer_needed
);
11160 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11161 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11162 hard_frame_pointer_rtx
,
11163 MIPS_PROLOGUE_TEMP (Pmode
)));
11164 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11167 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11169 MIPS_PROLOGUE_TEMP (Pmode
)));
11171 /* Describe the combined effect of the previous instructions. */
11172 mips_set_frame_expr
11173 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
11174 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11176 mips_frame_barrier ();
11179 /* Set up the frame pointer, if we're using one. */
11180 if (frame_pointer_needed
)
11182 HOST_WIDE_INT offset
;
11184 offset
= frame
->hard_frame_pointer_offset
;
11187 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11188 RTX_FRAME_RELATED_P (insn
) = 1;
11190 else if (SMALL_OPERAND (offset
))
11192 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11193 stack_pointer_rtx
, GEN_INT (offset
));
11194 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11198 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11199 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11200 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11201 hard_frame_pointer_rtx
,
11202 MIPS_PROLOGUE_TEMP (Pmode
)));
11203 mips_set_frame_expr
11204 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
11205 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11209 mips_emit_loadgp ();
11211 /* Initialize the $gp save slot. */
11212 if (mips_cfun_has_cprestore_slot_p ())
11214 rtx base
, mem
, gp
, temp
;
11215 HOST_WIDE_INT offset
;
11217 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11218 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11219 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11220 temp
= (SMALL_OPERAND (offset
)
11221 ? gen_rtx_SCRATCH (Pmode
)
11222 : MIPS_PROLOGUE_TEMP (Pmode
));
11223 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11224 (mem
, GEN_INT (offset
), gp
, temp
)));
11226 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11227 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11228 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11231 /* We need to search back to the last use of K0 or K1. */
11232 if (cfun
->machine
->interrupt_handler_p
)
11234 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11236 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
11238 /* Emit a move from K1 to COP0 Status after insn. */
11239 gcc_assert (insn
!= NULL_RTX
);
11240 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11241 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11245 /* If we are profiling, make sure no instructions are scheduled before
11246 the call to mcount. */
11248 emit_insn (gen_blockage ());
11251 /* Attach all pending register saves to the previous instruction.
11252 Return that instruction. */
11255 mips_epilogue_emit_cfa_restores (void)
11259 insn
= get_last_insn ();
11260 gcc_assert (insn
&& !REG_NOTES (insn
));
11261 if (mips_epilogue
.cfa_restores
)
11263 RTX_FRAME_RELATED_P (insn
) = 1;
11264 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11265 mips_epilogue
.cfa_restores
= 0;
11270 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11271 now at REG + OFFSET. */
11274 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11278 insn
= mips_epilogue_emit_cfa_restores ();
11279 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11281 RTX_FRAME_RELATED_P (insn
) = 1;
11282 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11283 plus_constant (Pmode
, reg
, offset
),
11285 mips_epilogue
.cfa_reg
= reg
;
11286 mips_epilogue
.cfa_offset
= offset
;
11290 /* Emit instructions to restore register REG from slot MEM. Also update
11291 the cfa_restores list. */
11294 mips_restore_reg (rtx reg
, rtx mem
)
11296 /* There's no MIPS16 instruction to load $31 directly. Load into
11297 $7 instead and adjust the return insn appropriately. */
11298 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11299 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11300 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11302 mips_add_cfa_restore (mips_subword (reg
, true));
11303 mips_add_cfa_restore (mips_subword (reg
, false));
11306 mips_add_cfa_restore (reg
);
11308 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11309 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11310 /* The CFA is currently defined in terms of the register whose
11311 value we have just restored. Redefine the CFA in terms of
11312 the stack pointer. */
11313 mips_epilogue_set_cfa (stack_pointer_rtx
,
11314 mips_epilogue
.cfa_restore_sp_offset
);
11317 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11318 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11319 BASE, if not the stack pointer, is available as a temporary. */
11322 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11324 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11327 mips_frame_barrier ();
11328 if (offset
== const0_rtx
)
11330 emit_move_insn (stack_pointer_rtx
, base
);
11331 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11333 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11335 emit_insn (gen_add3_insn (base
, base
, offset
));
11336 mips_epilogue_set_cfa (base
, new_frame_size
);
11337 emit_move_insn (stack_pointer_rtx
, base
);
11341 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11342 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11346 /* Emit any instructions needed before a return. */
11349 mips_expand_before_return (void)
11351 /* When using a call-clobbered gp, we start out with unified call
11352 insns that include instructions to restore the gp. We then split
11353 these unified calls after reload. These split calls explicitly
11354 clobber gp, so there is no need to define
11355 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11357 For consistency, we should also insert an explicit clobber of $28
11358 before return insns, so that the post-reload optimizers know that
11359 the register is not live on exit. */
11360 if (TARGET_CALL_CLOBBERED_GP
)
11361 emit_clobber (pic_offset_table_rtx
);
11364 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11368 mips_expand_epilogue (bool sibcall_p
)
11370 const struct mips_frame_info
*frame
;
11371 HOST_WIDE_INT step1
, step2
;
11372 rtx base
, adjust
, insn
;
11373 bool use_jraddiusp_p
= false;
11375 if (!sibcall_p
&& mips_can_use_return_insn ())
11377 emit_jump_insn (gen_return ());
11381 /* In MIPS16 mode, if the return value should go into a floating-point
11382 register, we need to call a helper routine to copy it over. */
11383 if (mips16_cfun_returns_in_fpr_p ())
11384 mips16_copy_fpr_return_value ();
11386 /* Split the frame into two. STEP1 is the amount of stack we should
11387 deallocate before restoring the registers. STEP2 is the amount we
11388 should deallocate afterwards.
11390 Start off by assuming that no registers need to be restored. */
11391 frame
= &cfun
->machine
->frame
;
11392 step1
= frame
->total_size
;
11395 /* Work out which register holds the frame address. */
11396 if (!frame_pointer_needed
)
11397 base
= stack_pointer_rtx
;
11400 base
= hard_frame_pointer_rtx
;
11401 step1
-= frame
->hard_frame_pointer_offset
;
11403 mips_epilogue
.cfa_reg
= base
;
11404 mips_epilogue
.cfa_offset
= step1
;
11405 mips_epilogue
.cfa_restores
= NULL_RTX
;
11407 /* If we need to restore registers, deallocate as much stack as
11408 possible in the second step without going out of range. */
11409 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11410 || frame
->num_cop0_regs
> 0)
11412 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11416 /* Get an rtx for STEP1 that we can add to BASE. */
11417 adjust
= GEN_INT (step1
);
11418 if (!SMALL_OPERAND (step1
))
11420 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11421 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11423 mips_deallocate_stack (base
, adjust
, step2
);
11425 /* If we're using addressing macros, $gp is implicitly used by all
11426 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11428 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11429 emit_insn (gen_blockage ());
11431 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11432 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11434 unsigned int regno
, mask
;
11435 HOST_WIDE_INT offset
;
11438 /* Generate the restore instruction. */
11439 mask
= frame
->mask
;
11440 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11442 /* Restore any other registers manually. */
11443 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11444 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11446 offset
-= UNITS_PER_WORD
;
11447 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11450 /* Restore the remaining registers and deallocate the final bit
11452 mips_frame_barrier ();
11453 emit_insn (restore
);
11454 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11458 /* Restore the registers. */
11459 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11460 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11463 if (cfun
->machine
->interrupt_handler_p
)
11465 HOST_WIDE_INT offset
;
11468 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11469 if (!cfun
->machine
->keep_interrupts_masked_p
)
11471 /* Restore the original EPC. */
11472 mem
= gen_frame_mem (word_mode
,
11473 plus_constant (Pmode
, stack_pointer_rtx
,
11475 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11476 offset
-= UNITS_PER_WORD
;
11478 /* Move to COP0 EPC. */
11479 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11480 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11483 /* Restore the original Status. */
11484 mem
= gen_frame_mem (word_mode
,
11485 plus_constant (Pmode
, stack_pointer_rtx
,
11487 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11488 offset
-= UNITS_PER_WORD
;
11490 /* If we don't use shadow register set, we need to update SP. */
11491 if (!cfun
->machine
->use_shadow_register_set_p
)
11492 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11494 /* The choice of position is somewhat arbitrary in this case. */
11495 mips_epilogue_emit_cfa_restores ();
11497 /* Move to COP0 Status. */
11498 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11499 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11501 else if (TARGET_MICROMIPS
11502 && !crtl
->calls_eh_return
11505 && mips_unsigned_immediate_p (step2
, 5, 2))
11506 use_jraddiusp_p
= true;
11508 /* Deallocate the final bit of the frame. */
11509 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11512 if (!use_jraddiusp_p
)
11513 gcc_assert (!mips_epilogue
.cfa_restores
);
11515 /* Add in the __builtin_eh_return stack adjustment. We need to
11516 use a temporary in MIPS16 code. */
11517 if (crtl
->calls_eh_return
)
11521 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11522 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11523 MIPS_EPILOGUE_TEMP (Pmode
),
11524 EH_RETURN_STACKADJ_RTX
));
11525 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11528 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11530 EH_RETURN_STACKADJ_RTX
));
11535 mips_expand_before_return ();
11536 if (cfun
->machine
->interrupt_handler_p
)
11538 /* Interrupt handlers generate eret or deret. */
11539 if (cfun
->machine
->use_debug_exception_return_p
)
11540 emit_jump_insn (gen_mips_deret ());
11542 emit_jump_insn (gen_mips_eret ());
11548 /* When generating MIPS16 code, the normal
11549 mips_for_each_saved_gpr_and_fpr path will restore the return
11550 address into $7 rather than $31. */
11552 && !GENERATE_MIPS16E_SAVE_RESTORE
11553 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11555 /* simple_returns cannot rely on values that are only available
11556 on paths through the epilogue (because return paths that do
11557 not pass through the epilogue may nevertheless reuse a
11558 simple_return that occurs at the end of the epilogue).
11559 Use a normal return here instead. */
11560 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11561 pat
= gen_return_internal (reg
);
11563 else if (use_jraddiusp_p
)
11564 pat
= gen_jraddiusp (GEN_INT (step2
));
11567 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11568 pat
= gen_simple_return_internal (reg
);
11570 emit_jump_insn (pat
);
11571 if (use_jraddiusp_p
)
11572 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11576 /* Search from the beginning to the first use of K0 or K1. */
11577 if (cfun
->machine
->interrupt_handler_p
11578 && !cfun
->machine
->keep_interrupts_masked_p
)
11580 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11582 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11584 gcc_assert (insn
!= NULL_RTX
);
11585 /* Insert disable interrupts before the first use of K0 or K1. */
11586 emit_insn_before (gen_mips_di (), insn
);
11587 emit_insn_before (gen_mips_ehb (), insn
);
11591 /* Return nonzero if this function is known to have a null epilogue.
11592 This allows the optimizer to omit jumps to jumps if no stack
11596 mips_can_use_return_insn (void)
11598 /* Interrupt handlers need to go through the epilogue. */
11599 if (cfun
->machine
->interrupt_handler_p
)
11602 if (!reload_completed
)
11608 /* In MIPS16 mode, a function that returns a floating-point value
11609 needs to arrange to copy the return value into the floating-point
11611 if (mips16_cfun_returns_in_fpr_p ())
11614 return cfun
->machine
->frame
.total_size
== 0;
11617 /* Return true if register REGNO can store a value of mode MODE.
11618 The result of this function is cached in mips_hard_regno_mode_ok. */
11621 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11624 enum mode_class mclass
;
11626 if (mode
== CCV2mode
)
11627 return (ISA_HAS_8CC
11628 && ST_REG_P (regno
)
11629 && (regno
- ST_REG_FIRST
) % 2 == 0);
11631 if (mode
== CCV4mode
)
11632 return (ISA_HAS_8CC
11633 && ST_REG_P (regno
)
11634 && (regno
- ST_REG_FIRST
) % 4 == 0);
11636 if (mode
== CCmode
)
11637 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11639 size
= GET_MODE_SIZE (mode
);
11640 mclass
= GET_MODE_CLASS (mode
);
11642 if (GP_REG_P (regno
))
11643 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11645 if (FP_REG_P (regno
)
11646 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11647 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11649 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11650 if (TARGET_LOONGSON_VECTORS
11651 && (mode
== V2SImode
11652 || mode
== V4HImode
11653 || mode
== V8QImode
11654 || mode
== DImode
))
11657 if (mclass
== MODE_FLOAT
11658 || mclass
== MODE_COMPLEX_FLOAT
11659 || mclass
== MODE_VECTOR_FLOAT
)
11660 return size
<= UNITS_PER_FPVALUE
;
11662 /* Allow integer modes that fit into a single register. We need
11663 to put integers into FPRs when using instructions like CVT
11664 and TRUNC. There's no point allowing sizes smaller than a word,
11665 because the FPU has no appropriate load/store instructions. */
11666 if (mclass
== MODE_INT
)
11667 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11670 if (ACC_REG_P (regno
)
11671 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11673 if (MD_REG_P (regno
))
11675 /* After a multiplication or division, clobbering HI makes
11676 the value of LO unpredictable, and vice versa. This means
11677 that, for all interesting cases, HI and LO are effectively
11680 We model this by requiring that any value that uses HI
11682 if (size
<= UNITS_PER_WORD
* 2)
11683 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11687 /* DSP accumulators do not have the same restrictions as
11688 HI and LO, so we can treat them as normal doubleword
11690 if (size
<= UNITS_PER_WORD
)
11693 if (size
<= UNITS_PER_WORD
* 2
11694 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11699 if (ALL_COP_REG_P (regno
))
11700 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11702 if (regno
== GOT_VERSION_REGNUM
)
11703 return mode
== SImode
;
11708 /* Implement HARD_REGNO_NREGS. */
11711 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11713 if (ST_REG_P (regno
))
11714 /* The size of FP status registers is always 4, because they only hold
11715 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11716 return (GET_MODE_SIZE (mode
) + 3) / 4;
11718 if (FP_REG_P (regno
))
11719 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11721 /* All other registers are word-sized. */
11722 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11725 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11726 in mips_hard_regno_nregs. */
11729 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11735 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11736 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11738 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11739 size
= MIN (size
, 4);
11740 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11742 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11744 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11745 size
= MIN (size
, UNITS_PER_FPREG
);
11746 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11748 if (!hard_reg_set_empty_p (left
))
11749 size
= MIN (size
, UNITS_PER_WORD
);
11750 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11753 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11756 mips_cannot_change_mode_class (enum machine_mode from
,
11757 enum machine_mode to
,
11758 enum reg_class rclass
)
11760 /* Allow conversions between different Loongson integer vectors,
11761 and between those vectors and DImode. */
11762 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11763 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11766 /* Otherwise, there are several problems with changing the modes of
11767 values in floating-point registers:
11769 - When a multi-word value is stored in paired floating-point
11770 registers, the first register always holds the low word. We
11771 therefore can't allow FPRs to change between single-word and
11772 multi-word modes on big-endian targets.
11774 - GCC assumes that each word of a multiword register can be
11775 accessed individually using SUBREGs. This is not true for
11776 floating-point registers if they are bigger than a word.
11778 - Loading a 32-bit value into a 64-bit floating-point register
11779 will not sign-extend the value, despite what LOAD_EXTEND_OP
11780 says. We can't allow FPRs to change from SImode to a wider
11781 mode on 64-bit targets.
11783 - If the FPU has already interpreted a value in one format, we
11784 must not ask it to treat the value as having a different
11787 We therefore disallow all mode changes involving FPRs. */
11789 return reg_classes_intersect_p (FP_REGS
, rclass
);
11792 /* Implement target hook small_register_classes_for_mode_p. */
11795 mips_small_register_classes_for_mode_p (enum machine_mode mode
11798 return TARGET_MIPS16
;
11801 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11804 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11809 return TARGET_HARD_FLOAT
;
11812 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11815 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11822 /* Implement MODES_TIEABLE_P. */
11825 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11827 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11828 prefer to put one of them in FPRs. */
11829 return (mode1
== mode2
11830 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11831 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11834 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11837 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11839 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11842 if (reg_class_subset_p (FP_REGS
, rclass
)
11843 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11846 if (reg_class_subset_p (GR_REGS
, rclass
))
11849 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11855 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11856 Return a "canonical" class to represent it in later calculations. */
11859 mips_canonicalize_move_class (reg_class_t rclass
)
11861 /* All moves involving accumulator registers have the same cost. */
11862 if (reg_class_subset_p (rclass
, ACC_REGS
))
11865 /* Likewise promote subclasses of general registers to the most
11866 interesting containing class. */
11867 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11869 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11870 rclass
= GENERAL_REGS
;
11875 /* Return the cost of moving a value of mode MODE from a register of
11876 class FROM to a GPR. Return 0 for classes that are unions of other
11877 classes handled by this function. */
11880 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11886 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11890 /* MFLO and MFHI. */
11898 /* LUI followed by MOVF. */
11904 /* This choice of value is historical. */
11912 /* Return the cost of moving a value of mode MODE from a GPR to a
11913 register of class TO. Return 0 for classes that are unions of
11914 other classes handled by this function. */
11917 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
11922 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11926 /* MTLO and MTHI. */
11934 /* A secondary reload through an FPR scratch. */
11935 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
11936 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
11941 /* This choice of value is historical. */
11949 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11950 maximum of the move costs for subclasses; regclass will work out
11951 the maximum for us. */
11954 mips_register_move_cost (enum machine_mode mode
,
11955 reg_class_t from
, reg_class_t to
)
11960 from
= mips_canonicalize_move_class (from
);
11961 to
= mips_canonicalize_move_class (to
);
11963 /* Handle moves that can be done without using general-purpose registers. */
11964 if (from
== FP_REGS
)
11966 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
11970 /* The sequence generated by mips_expand_fcc_reload. */
11974 /* Handle cases in which only one class deviates from the ideal. */
11975 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
11977 return mips_move_from_gpr_cost (mode
, to
);
11979 return mips_move_to_gpr_cost (mode
, from
);
11981 /* Handles cases that require a GPR temporary. */
11982 cost1
= mips_move_to_gpr_cost (mode
, from
);
11985 cost2
= mips_move_from_gpr_cost (mode
, to
);
11987 return cost1
+ cost2
;
11993 /* Implement TARGET_MEMORY_MOVE_COST. */
11996 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
11998 return (mips_cost
->memory_latency
11999 + memory_move_secondary_cost (mode
, rclass
, in
));
12002 /* Return the register class required for a secondary register when
12003 copying between one of the registers in RCLASS and value X, which
12004 has mode MODE. X is the source of the move if IN_P, otherwise it
12005 is the destination. Return NO_REGS if no secondary register is
12009 mips_secondary_reload_class (enum reg_class rclass
,
12010 enum machine_mode mode
, rtx x
, bool in_p
)
12014 /* If X is a constant that cannot be loaded into $25, it must be loaded
12015 into some other GPR. No other register class allows a direct move. */
12016 if (mips_dangerous_for_la25_p (x
))
12017 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
12019 regno
= true_regnum (x
);
12022 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12023 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12029 /* Copying from accumulator registers to anywhere other than a general
12030 register requires a temporary general register. */
12031 if (reg_class_subset_p (rclass
, ACC_REGS
))
12032 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12033 if (ACC_REG_P (regno
))
12034 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12036 /* We can only copy a value to a condition code register from a
12037 floating-point register, and even then we require a scratch
12038 floating-point register. We can only copy a value out of a
12039 condition-code register into a general register. */
12040 if (reg_class_subset_p (rclass
, ST_REGS
))
12044 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12046 if (ST_REG_P (regno
))
12050 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12053 if (reg_class_subset_p (rclass
, FP_REGS
))
12056 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
12057 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12058 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12061 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12062 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12065 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12066 /* We can force the constant to memory and use lwc1
12067 and ldc1. As above, we will use pairs of lwc1s if
12068 ldc1 is not supported. */
12071 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12072 /* In this case we can use mov.fmt. */
12075 /* Otherwise, we need to reload through an integer register. */
12078 if (FP_REG_P (regno
))
12079 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12084 /* Implement TARGET_MODE_REP_EXTENDED. */
12087 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
12089 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12090 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12091 return SIGN_EXTEND
;
12096 /* Implement TARGET_VALID_POINTER_MODE. */
12099 mips_valid_pointer_mode (enum machine_mode mode
)
12101 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12104 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12107 mips_vector_mode_supported_p (enum machine_mode mode
)
12112 return TARGET_PAIRED_SINGLE_FLOAT
;
12127 return TARGET_LOONGSON_VECTORS
;
12134 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12137 mips_scalar_mode_supported_p (enum machine_mode mode
)
12139 if (ALL_FIXED_POINT_MODE_P (mode
)
12140 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12143 return default_scalar_mode_supported_p (mode
);
12146 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12148 static enum machine_mode
12149 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
12151 if (TARGET_PAIRED_SINGLE_FLOAT
12157 /* Implement TARGET_INIT_LIBFUNCS. */
12160 mips_init_libfuncs (void)
12162 if (TARGET_FIX_VR4120
)
12164 /* Register the special divsi3 and modsi3 functions needed to work
12165 around VR4120 division errata. */
12166 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12167 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12170 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12172 /* Register the MIPS16 -mhard-float stubs. */
12173 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12174 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12175 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12176 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12178 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12179 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12180 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12181 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12182 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12183 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12184 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12186 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12187 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12188 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12190 if (TARGET_DOUBLE_FLOAT
)
12192 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12193 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12194 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12195 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12197 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12198 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12199 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12200 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12201 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12202 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12203 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12205 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12206 "__mips16_extendsfdf2");
12207 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12208 "__mips16_truncdfsf2");
12209 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12210 "__mips16_fix_truncdfsi");
12211 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12212 "__mips16_floatsidf");
12213 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12214 "__mips16_floatunsidf");
12218 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12219 on an external non-MIPS16 routine to implement __sync_synchronize.
12220 Similarly for the rest of the ll/sc libfuncs. */
12223 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12224 init_sync_libfuncs (UNITS_PER_WORD
);
12228 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12231 mips_process_load_label (rtx target
)
12233 rtx base
, gp
, intop
;
12234 HOST_WIDE_INT offset
;
12236 mips_multi_start ();
12240 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12241 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12245 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12246 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12250 gp
= pic_offset_table_rtx
;
12251 if (mips_cfun_has_cprestore_slot_p ())
12253 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12254 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12255 if (!SMALL_OPERAND (offset
))
12257 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12258 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12259 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12262 offset
= CONST_LOW_PART (offset
);
12264 intop
= GEN_INT (offset
);
12265 if (ISA_HAS_LOAD_DELAY
)
12266 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12268 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12270 if (ISA_HAS_LOAD_DELAY
)
12271 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12273 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12274 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12279 /* Return the number of instructions needed to load a label into $AT. */
12281 static unsigned int
12282 mips_load_label_num_insns (void)
12284 if (cfun
->machine
->load_label_num_insns
== 0)
12286 mips_process_load_label (pc_rtx
);
12287 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12289 return cfun
->machine
->load_label_num_insns
;
12292 /* Emit an asm sequence to start a noat block and load the address
12293 of a label into $1. */
12296 mips_output_load_label (rtx target
)
12298 mips_push_asm_switch (&mips_noat
);
12299 if (TARGET_EXPLICIT_RELOCS
)
12301 mips_process_load_label (target
);
12302 mips_multi_write ();
12306 if (Pmode
== DImode
)
12307 output_asm_insn ("dla\t%@,%0", &target
);
12309 output_asm_insn ("la\t%@,%0", &target
);
12313 /* Return the length of INSN. LENGTH is the initial length computed by
12314 attributes in the machine-description file. */
12317 mips_adjust_insn_length (rtx insn
, int length
)
12319 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12320 of a PIC long-branch sequence. Substitute the correct value. */
12321 if (length
== MAX_PIC_BRANCH_LENGTH
12323 && INSN_CODE (insn
) >= 0
12324 && get_attr_type (insn
) == TYPE_BRANCH
)
12326 /* Add the branch-over instruction and its delay slot, if this
12327 is a conditional branch. */
12328 length
= simplejump_p (insn
) ? 0 : 8;
12330 /* Add the size of a load into $AT. */
12331 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12333 /* Add the length of an indirect jump, ignoring the delay slot. */
12334 length
+= TARGET_COMPRESSION
? 2 : 4;
12337 /* A unconditional jump has an unfilled delay slot if it is not part
12338 of a sequence. A conditional jump normally has a delay slot, but
12339 does not on MIPS16. */
12340 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12341 length
+= TARGET_MIPS16
? 2 : 4;
12343 /* See how many nops might be needed to avoid hardware hazards. */
12344 if (!cfun
->machine
->ignore_hazard_length_p
12346 && INSN_CODE (insn
) >= 0)
12347 switch (get_attr_hazard (insn
))
12353 length
+= NOP_INSN_LENGTH
;
12357 length
+= NOP_INSN_LENGTH
* 2;
12364 /* Return the assembly code for INSN, which has the operands given by
12365 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12366 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12367 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12368 version of BRANCH_IF_TRUE. */
12371 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
12372 const char *branch_if_true
,
12373 const char *branch_if_false
)
12375 unsigned int length
;
12376 rtx taken
, not_taken
;
12378 gcc_assert (LABEL_P (operands
[0]));
12380 length
= get_attr_length (insn
);
12383 /* Just a simple conditional branch. */
12384 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12385 return branch_if_true
;
12388 /* Generate a reversed branch around a direct jump. This fallback does
12389 not use branch-likely instructions. */
12390 mips_branch_likely
= false;
12391 not_taken
= gen_label_rtx ();
12392 taken
= operands
[0];
12394 /* Generate the reversed branch to NOT_TAKEN. */
12395 operands
[0] = not_taken
;
12396 output_asm_insn (branch_if_false
, operands
);
12398 /* If INSN has a delay slot, we must provide delay slots for both the
12399 branch to NOT_TAKEN and the conditional jump. We must also ensure
12400 that INSN's delay slot is executed in the appropriate cases. */
12401 if (final_sequence
)
12403 /* This first delay slot will always be executed, so use INSN's
12404 delay slot if is not annulled. */
12405 if (!INSN_ANNULLED_BRANCH_P (insn
))
12407 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12408 asm_out_file
, optimize
, 1, NULL
);
12409 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12412 output_asm_insn ("nop", 0);
12413 fprintf (asm_out_file
, "\n");
12416 /* Output the unconditional branch to TAKEN. */
12417 if (TARGET_ABSOLUTE_JUMPS
)
12418 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12421 mips_output_load_label (taken
);
12422 output_asm_insn ("jr\t%@%]%/", 0);
12425 /* Now deal with its delay slot; see above. */
12426 if (final_sequence
)
12428 /* This delay slot will only be executed if the branch is taken.
12429 Use INSN's delay slot if is annulled. */
12430 if (INSN_ANNULLED_BRANCH_P (insn
))
12432 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12433 asm_out_file
, optimize
, 1, NULL
);
12434 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12437 output_asm_insn ("nop", 0);
12438 fprintf (asm_out_file
, "\n");
12441 /* Output NOT_TAKEN. */
12442 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12443 CODE_LABEL_NUMBER (not_taken
));
12447 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12448 if some ordering condition is true. The condition is given by
12449 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12450 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12451 its second is always zero. */
12454 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
12456 const char *branch
[2];
12458 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12459 Make BRANCH[0] branch on the inverse condition. */
12460 switch (GET_CODE (operands
[1]))
12462 /* These cases are equivalent to comparisons against zero. */
12464 inverted_p
= !inverted_p
;
12465 /* Fall through. */
12467 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12468 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12471 /* These cases are always true or always false. */
12473 inverted_p
= !inverted_p
;
12474 /* Fall through. */
12476 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12477 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12481 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12482 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12485 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12488 /* Start a block of code that needs access to the LL, SC and SYNC
12492 mips_start_ll_sc_sync_block (void)
12494 if (!ISA_HAS_LL_SC
)
12496 output_asm_insn (".set\tpush", 0);
12498 output_asm_insn (".set\tmips3", 0);
12500 output_asm_insn (".set\tmips2", 0);
12504 /* End a block started by mips_start_ll_sc_sync_block. */
12507 mips_end_ll_sc_sync_block (void)
12509 if (!ISA_HAS_LL_SC
)
12510 output_asm_insn (".set\tpop", 0);
12513 /* Output and/or return the asm template for a sync instruction. */
12516 mips_output_sync (void)
12518 mips_start_ll_sc_sync_block ();
12519 output_asm_insn ("sync", 0);
12520 mips_end_ll_sc_sync_block ();
12524 /* Return the asm template associated with sync_insn1 value TYPE.
12525 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12527 static const char *
12528 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12532 case SYNC_INSN1_MOVE
:
12533 return "move\t%0,%z2";
12534 case SYNC_INSN1_LI
:
12535 return "li\t%0,%2";
12536 case SYNC_INSN1_ADDU
:
12537 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12538 case SYNC_INSN1_ADDIU
:
12539 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12540 case SYNC_INSN1_SUBU
:
12541 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12542 case SYNC_INSN1_AND
:
12543 return "and\t%0,%1,%z2";
12544 case SYNC_INSN1_ANDI
:
12545 return "andi\t%0,%1,%2";
12546 case SYNC_INSN1_OR
:
12547 return "or\t%0,%1,%z2";
12548 case SYNC_INSN1_ORI
:
12549 return "ori\t%0,%1,%2";
12550 case SYNC_INSN1_XOR
:
12551 return "xor\t%0,%1,%z2";
12552 case SYNC_INSN1_XORI
:
12553 return "xori\t%0,%1,%2";
12555 gcc_unreachable ();
12558 /* Return the asm template associated with sync_insn2 value TYPE. */
12560 static const char *
12561 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12565 case SYNC_INSN2_NOP
:
12566 gcc_unreachable ();
12567 case SYNC_INSN2_AND
:
12568 return "and\t%0,%1,%z2";
12569 case SYNC_INSN2_XOR
:
12570 return "xor\t%0,%1,%z2";
12571 case SYNC_INSN2_NOT
:
12572 return "nor\t%0,%1,%.";
12574 gcc_unreachable ();
12577 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12578 the value of the one of the sync_* attributes. Return the operand
12579 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12580 have the associated attribute. */
12583 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12586 default_value
= operands
[index
- 1];
12587 return default_value
;
12590 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12591 sequence for it. */
12594 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12596 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12597 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12598 unsigned int tmp3_insn
;
12599 enum attr_sync_insn1 insn1
;
12600 enum attr_sync_insn2 insn2
;
12603 enum memmodel model
;
12605 /* Read an operand from the sync_WHAT attribute and store it in
12606 variable WHAT. DEFAULT is the default value if no attribute
12608 #define READ_OPERAND(WHAT, DEFAULT) \
12609 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12612 /* Read the memory. */
12613 READ_OPERAND (mem
, 0);
12615 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12617 /* Read the other attributes. */
12618 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12619 READ_OPERAND (oldval
, at
);
12620 READ_OPERAND (cmp
, 0);
12621 READ_OPERAND (newval
, at
);
12622 READ_OPERAND (inclusive_mask
, 0);
12623 READ_OPERAND (exclusive_mask
, 0);
12624 READ_OPERAND (required_oldval
, 0);
12625 READ_OPERAND (insn1_op2
, 0);
12626 insn1
= get_attr_sync_insn1 (insn
);
12627 insn2
= get_attr_sync_insn2 (insn
);
12629 /* Don't bother setting CMP result that is never used. */
12630 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12633 memmodel_attr
= get_attr_sync_memmodel (insn
);
12634 switch (memmodel_attr
)
12637 model
= MEMMODEL_ACQ_REL
;
12640 model
= MEMMODEL_ACQUIRE
;
12643 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12646 mips_multi_start ();
12648 /* Output the release side of the memory barrier. */
12649 if (need_atomic_barrier_p (model
, true))
12651 if (required_oldval
== 0 && TARGET_OCTEON
)
12653 /* Octeon doesn't reorder reads, so a full barrier can be
12654 created by using SYNCW to order writes combined with the
12655 write from the following SC. When the SC successfully
12656 completes, we know that all preceding writes are also
12657 committed to the coherent memory system. It is possible
12658 for a single SYNCW to fail, but a pair of them will never
12659 fail, so we use two. */
12660 mips_multi_add_insn ("syncw", NULL
);
12661 mips_multi_add_insn ("syncw", NULL
);
12664 mips_multi_add_insn ("sync", NULL
);
12667 /* Output the branch-back label. */
12668 mips_multi_add_label ("1:");
12670 /* OLDVAL = *MEM. */
12671 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12672 oldval
, mem
, NULL
);
12674 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12675 if (required_oldval
)
12677 if (inclusive_mask
== 0)
12681 gcc_assert (oldval
!= at
);
12682 mips_multi_add_insn ("and\t%0,%1,%2",
12683 at
, oldval
, inclusive_mask
, NULL
);
12686 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12688 /* CMP = 0 [delay slot]. */
12690 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12693 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12694 if (exclusive_mask
== 0)
12698 gcc_assert (oldval
!= at
);
12699 mips_multi_add_insn ("and\t%0,%1,%z2",
12700 at
, oldval
, exclusive_mask
, NULL
);
12704 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12706 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12707 at least one instruction in that case. */
12708 if (insn1
== SYNC_INSN1_MOVE
12709 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12713 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12714 newval
, oldval
, insn1_op2
, NULL
);
12718 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12719 if (insn2
== SYNC_INSN2_NOP
)
12723 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12724 newval
, tmp2
, inclusive_mask
, NULL
);
12727 tmp3_insn
= mips_multi_last_index ();
12729 /* $AT = $TMP1 | $TMP3. */
12730 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12732 mips_multi_set_operand (tmp3_insn
, 0, at
);
12737 gcc_assert (tmp1
!= tmp3
);
12738 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12741 /* if (!commit (*MEM = $AT)) goto 1.
12743 This will sometimes be a delayed branch; see the write code below
12745 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12746 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12748 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12749 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12751 mips_multi_copy_insn (tmp3_insn
);
12752 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12754 else if (!(required_oldval
&& cmp
))
12755 mips_multi_add_insn ("nop", NULL
);
12757 /* CMP = 1 -- either standalone or in a delay slot. */
12758 if (required_oldval
&& cmp
)
12759 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12761 /* Output the acquire side of the memory barrier. */
12762 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12763 mips_multi_add_insn ("sync", NULL
);
12765 /* Output the exit label, if needed. */
12766 if (required_oldval
)
12767 mips_multi_add_label ("2:");
12769 #undef READ_OPERAND
12772 /* Output and/or return the asm template for sync loop INSN, which has
12773 the operands given by OPERANDS. */
12776 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12778 mips_process_sync_loop (insn
, operands
);
12780 /* Use branch-likely instructions to work around the LL/SC R10000
12782 mips_branch_likely
= TARGET_FIX_R10000
;
12784 mips_push_asm_switch (&mips_noreorder
);
12785 mips_push_asm_switch (&mips_nomacro
);
12786 mips_push_asm_switch (&mips_noat
);
12787 mips_start_ll_sc_sync_block ();
12789 mips_multi_write ();
12791 mips_end_ll_sc_sync_block ();
12792 mips_pop_asm_switch (&mips_noat
);
12793 mips_pop_asm_switch (&mips_nomacro
);
12794 mips_pop_asm_switch (&mips_noreorder
);
12799 /* Return the number of individual instructions in sync loop INSN,
12800 which has the operands given by OPERANDS. */
12803 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12805 mips_process_sync_loop (insn
, operands
);
12806 return mips_multi_num_insns
;
12809 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12810 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12812 When working around R4000 and R4400 errata, we need to make sure that
12813 the division is not immediately followed by a shift[1][2]. We also
12814 need to stop the division from being put into a branch delay slot[3].
12815 The easiest way to avoid both problems is to add a nop after the
12816 division. When a divide-by-zero check is needed, this nop can be
12817 used to fill the branch delay slot.
12819 [1] If a double-word or a variable shift executes immediately
12820 after starting an integer division, the shift may give an
12821 incorrect result. See quotations of errata #16 and #28 from
12822 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12823 in mips.md for details.
12825 [2] A similar bug to [1] exists for all revisions of the
12826 R4000 and the R4400 when run in an MC configuration.
12827 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12829 "19. In this following sequence:
12831 ddiv (or ddivu or div or divu)
12832 dsll32 (or dsrl32, dsra32)
12834 if an MPT stall occurs, while the divide is slipping the cpu
12835 pipeline, then the following double shift would end up with an
12838 Workaround: The compiler needs to avoid generating any
12839 sequence with divide followed by extended double shift."
12841 This erratum is also present in "MIPS R4400MC Errata, Processor
12842 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12843 & 3.0" as errata #10 and #4, respectively.
12845 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12846 (also valid for MIPS R4000MC processors):
12848 "52. R4000SC: This bug does not apply for the R4000PC.
12850 There are two flavors of this bug:
12852 1) If the instruction just after divide takes an RF exception
12853 (tlb-refill, tlb-invalid) and gets an instruction cache
12854 miss (both primary and secondary) and the line which is
12855 currently in secondary cache at this index had the first
12856 data word, where the bits 5..2 are set, then R4000 would
12857 get a wrong result for the div.
12862 ------------------- # end-of page. -tlb-refill
12867 ------------------- # end-of page. -tlb-invalid
12870 2) If the divide is in the taken branch delay slot, where the
12871 target takes RF exception and gets an I-cache miss for the
12872 exception vector or where I-cache miss occurs for the
12873 target address, under the above mentioned scenarios, the
12874 div would get wrong results.
12877 j r2 # to next page mapped or unmapped
12878 div r8,r9 # this bug would be there as long
12879 # as there is an ICache miss and
12880 nop # the "data pattern" is present
12883 beq r0, r0, NextPage # to Next page
12887 This bug is present for div, divu, ddiv, and ddivu
12890 Workaround: For item 1), OS could make sure that the next page
12891 after the divide instruction is also mapped. For item 2), the
12892 compiler could make sure that the divide instruction is not in
12893 the branch delay slot."
12895 These processors have PRId values of 0x00004220 and 0x00004300 for
12896 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12899 mips_output_division (const char *division
, rtx
*operands
)
12904 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12906 output_asm_insn (s
, operands
);
12909 if (TARGET_CHECK_ZERO_DIV
)
12913 output_asm_insn (s
, operands
);
12914 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
12916 else if (GENERATE_DIVIDE_TRAPS
)
12918 /* Avoid long replay penalty on load miss by putting the trap before
12921 output_asm_insn ("teq\t%2,%.,7", operands
);
12924 output_asm_insn (s
, operands
);
12925 s
= "teq\t%2,%.,7";
12930 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
12931 output_asm_insn (s
, operands
);
12932 s
= "break\t7%)\n1:";
12938 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12939 instruction and if OUT_INSN assigns to the accumulator operand. */
12942 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
12944 enum attr_accum_in accum_in
;
12945 int accum_in_opnum
;
12948 if (recog_memoized (in_insn
) < 0)
12951 accum_in
= get_attr_accum_in (in_insn
);
12952 if (accum_in
== ACCUM_IN_NONE
)
12955 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
12957 extract_insn (in_insn
);
12958 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
12959 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
12961 return reg_set_p (accum_in_op
, out_insn
);
12964 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12965 data rather than the address. We need this because the cprestore
12966 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12967 which causes the default routine to abort. We just return false
12971 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
12973 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
12976 return !store_data_bypass_p (out_insn
, in_insn
);
12980 /* Variables and flags used in scheduler hooks when tuning for
12984 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12987 /* If true, then next ALU1/2 instruction will go to ALU1. */
12990 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12993 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12994 int alu1_core_unit_code
;
12995 int alu2_core_unit_code
;
12996 int falu1_core_unit_code
;
12997 int falu2_core_unit_code
;
12999 /* True if current cycle has a multi instruction.
13000 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13001 bool cycle_has_multi_p
;
13003 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13004 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13006 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13007 instruction to go ALU1. */
13008 rtx alu1_turn_enabled_insn
;
13009 rtx alu2_turn_enabled_insn
;
13010 rtx falu1_turn_enabled_insn
;
13011 rtx falu2_turn_enabled_insn
;
13014 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13015 dependencies have no cost, except on the 20Kc where output-dependence
13016 is treated like input-dependence. */
13019 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
13020 rtx dep ATTRIBUTE_UNUSED
, int cost
)
13022 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13025 if (REG_NOTE_KIND (link
) != 0)
13030 /* Return the number of instructions that can be issued per cycle. */
13033 mips_issue_rate (void)
13037 case PROCESSOR_74KC
:
13038 case PROCESSOR_74KF2_1
:
13039 case PROCESSOR_74KF1_1
:
13040 case PROCESSOR_74KF3_2
:
13041 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13042 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13043 but in reality only a maximum of 3 insns can be issued as
13044 floating-point loads and stores also require a slot in the
13046 case PROCESSOR_R10000
:
13047 /* All R10K Processors are quad-issue (being the first MIPS
13048 processors to support this feature). */
13051 case PROCESSOR_20KC
:
13052 case PROCESSOR_R4130
:
13053 case PROCESSOR_R5400
:
13054 case PROCESSOR_R5500
:
13055 case PROCESSOR_R5900
:
13056 case PROCESSOR_R7000
:
13057 case PROCESSOR_R9000
:
13058 case PROCESSOR_OCTEON
:
13059 case PROCESSOR_OCTEON2
:
13062 case PROCESSOR_SB1
:
13063 case PROCESSOR_SB1A
:
13064 /* This is actually 4, but we get better performance if we claim 3.
13065 This is partly because of unwanted speculative code motion with the
13066 larger number, and partly because in most common cases we can't
13067 reach the theoretical max of 4. */
13070 case PROCESSOR_LOONGSON_2E
:
13071 case PROCESSOR_LOONGSON_2F
:
13072 case PROCESSOR_LOONGSON_3A
:
13075 case PROCESSOR_XLP
:
13076 return (reload_completed
? 4 : 3);
13083 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13086 mips_ls2_init_dfa_post_cycle_insn (void)
13089 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13090 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13094 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13095 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13099 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13100 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13104 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13105 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13108 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13109 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13110 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13111 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13114 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13115 Init data used in mips_dfa_post_advance_cycle. */
13118 mips_init_dfa_post_cycle_insn (void)
13120 if (TUNE_LOONGSON_2EF
)
13121 mips_ls2_init_dfa_post_cycle_insn ();
13124 /* Initialize STATE when scheduling for Loongson 2E/2F.
13125 Support round-robin dispatch scheme by enabling only one of
13126 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13130 mips_ls2_dfa_post_advance_cycle (state_t state
)
13132 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13134 /* Though there are no non-pipelined ALU1 insns,
13135 we can get an instruction of type 'multi' before reload. */
13136 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13137 mips_ls2
.alu1_turn_p
= false;
13140 mips_ls2
.cycle_has_multi_p
= false;
13142 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13143 /* We have a non-pipelined alu instruction in the core,
13144 adjust round-robin counter. */
13145 mips_ls2
.alu1_turn_p
= true;
13147 if (mips_ls2
.alu1_turn_p
)
13149 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13150 gcc_unreachable ();
13154 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13155 gcc_unreachable ();
13158 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13160 /* There are no non-pipelined FALU1 insns. */
13161 gcc_unreachable ();
13162 mips_ls2
.falu1_turn_p
= false;
13165 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13166 /* We have a non-pipelined falu instruction in the core,
13167 adjust round-robin counter. */
13168 mips_ls2
.falu1_turn_p
= true;
13170 if (mips_ls2
.falu1_turn_p
)
13172 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13173 gcc_unreachable ();
13177 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13178 gcc_unreachable ();
13182 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13183 This hook is being called at the start of each cycle. */
13186 mips_dfa_post_advance_cycle (void)
13188 if (TUNE_LOONGSON_2EF
)
13189 mips_ls2_dfa_post_advance_cycle (curr_state
);
13192 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13193 be as wide as the scheduling freedom in the DFA. */
13196 mips_multipass_dfa_lookahead (void)
13198 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13202 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13211 /* Remove the instruction at index LOWER from ready queue READY and
13212 reinsert it in front of the instruction at index HIGHER. LOWER must
13216 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
13221 new_head
= ready
[lower
];
13222 for (i
= lower
; i
< higher
; i
++)
13223 ready
[i
] = ready
[i
+ 1];
13224 ready
[i
] = new_head
;
13227 /* If the priority of the instruction at POS2 in the ready queue READY
13228 is within LIMIT units of that of the instruction at POS1, swap the
13229 instructions if POS2 is not already less than POS1. */
13232 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
13235 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13239 temp
= ready
[pos1
];
13240 ready
[pos1
] = ready
[pos2
];
13241 ready
[pos2
] = temp
;
13245 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13246 that may clobber hi or lo. */
13247 static rtx mips_macc_chains_last_hilo
;
13249 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13250 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13253 mips_macc_chains_record (rtx insn
)
13255 if (get_attr_may_clobber_hilo (insn
))
13256 mips_macc_chains_last_hilo
= insn
;
13259 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13260 has NREADY elements, looking for a multiply-add or multiply-subtract
13261 instruction that is cumulative with mips_macc_chains_last_hilo.
13262 If there is one, promote it ahead of anything else that might
13263 clobber hi or lo. */
13266 mips_macc_chains_reorder (rtx
*ready
, int nready
)
13270 if (mips_macc_chains_last_hilo
!= 0)
13271 for (i
= nready
- 1; i
>= 0; i
--)
13272 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13274 for (j
= nready
- 1; j
> i
; j
--)
13275 if (recog_memoized (ready
[j
]) >= 0
13276 && get_attr_may_clobber_hilo (ready
[j
]))
13278 mips_promote_ready (ready
, i
, j
);
13285 /* The last instruction to be scheduled. */
13286 static rtx vr4130_last_insn
;
13288 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13289 points to an rtx that is initially an instruction. Nullify the rtx
13290 if the instruction uses the value of register X. */
13293 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13298 insn_ptr
= (rtx
*) data
;
13301 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13305 /* Return true if there is true register dependence between vr4130_last_insn
13309 vr4130_true_reg_dependence_p (rtx insn
)
13311 note_stores (PATTERN (vr4130_last_insn
),
13312 vr4130_true_reg_dependence_p_1
, &insn
);
13316 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13317 the ready queue and that INSN2 is the instruction after it, return
13318 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13319 in which INSN1 and INSN2 can probably issue in parallel, but for
13320 which (INSN2, INSN1) should be less sensitive to instruction
13321 alignment than (INSN1, INSN2). See 4130.md for more details. */
13324 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
13326 sd_iterator_def sd_it
;
13329 /* Check for the following case:
13331 1) there is some other instruction X with an anti dependence on INSN1;
13332 2) X has a higher priority than INSN2; and
13333 3) X is an arithmetic instruction (and thus has no unit restrictions).
13335 If INSN1 is the last instruction blocking X, it would better to
13336 choose (INSN1, X) over (INSN2, INSN1). */
13337 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13338 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13339 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13340 && recog_memoized (DEP_CON (dep
)) >= 0
13341 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13344 if (vr4130_last_insn
!= 0
13345 && recog_memoized (insn1
) >= 0
13346 && recog_memoized (insn2
) >= 0)
13348 /* See whether INSN1 and INSN2 use different execution units,
13349 or if they are both ALU-type instructions. If so, they can
13350 probably execute in parallel. */
13351 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13352 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13353 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13355 /* If only one of the instructions has a dependence on
13356 vr4130_last_insn, prefer to schedule the other one first. */
13357 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13358 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13359 if (dep1_p
!= dep2_p
)
13362 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13363 is not an ALU-type instruction and if INSN1 uses the same
13364 execution unit. (Note that if this condition holds, we already
13365 know that INSN2 uses a different execution unit.) */
13366 if (class1
!= VR4130_CLASS_ALU
13367 && recog_memoized (vr4130_last_insn
) >= 0
13368 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13375 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13376 queue with at least two instructions. Swap the first two if
13377 vr4130_swap_insns_p says that it could be worthwhile. */
13380 vr4130_reorder (rtx
*ready
, int nready
)
13382 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13383 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13386 /* Record whether last 74k AGEN instruction was a load or store. */
13387 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13389 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13390 resets to TYPE_UNKNOWN state. */
13393 mips_74k_agen_init (rtx insn
)
13395 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13396 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13399 enum attr_type type
= get_attr_type (insn
);
13400 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13401 mips_last_74k_agen_insn
= type
;
13405 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13406 loads to be grouped together, and multiple stores to be grouped
13407 together. Swap things around in the ready queue to make this happen. */
13410 mips_74k_agen_reorder (rtx
*ready
, int nready
)
13413 int store_pos
, load_pos
;
13418 for (i
= nready
- 1; i
>= 0; i
--)
13420 rtx insn
= ready
[i
];
13421 if (USEFUL_INSN_P (insn
))
13422 switch (get_attr_type (insn
))
13425 if (store_pos
== -1)
13430 if (load_pos
== -1)
13439 if (load_pos
== -1 || store_pos
== -1)
13442 switch (mips_last_74k_agen_insn
)
13445 /* Prefer to schedule loads since they have a higher latency. */
13447 /* Swap loads to the front of the queue. */
13448 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13451 /* Swap stores to the front of the queue. */
13452 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13459 /* Implement TARGET_SCHED_INIT. */
13462 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13463 int max_ready ATTRIBUTE_UNUSED
)
13465 mips_macc_chains_last_hilo
= 0;
13466 vr4130_last_insn
= 0;
13467 mips_74k_agen_init (NULL_RTX
);
13469 /* When scheduling for Loongson2, branch instructions go to ALU1,
13470 therefore basic block is most likely to start with round-robin counter
13471 pointed to ALU2. */
13472 mips_ls2
.alu1_turn_p
= false;
13473 mips_ls2
.falu1_turn_p
= true;
13476 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13479 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13480 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13482 if (!reload_completed
13483 && TUNE_MACC_CHAINS
13485 mips_macc_chains_reorder (ready
, *nreadyp
);
13487 if (reload_completed
13489 && !TARGET_VR4130_ALIGN
13491 vr4130_reorder (ready
, *nreadyp
);
13494 mips_74k_agen_reorder (ready
, *nreadyp
);
13497 /* Implement TARGET_SCHED_REORDER. */
13500 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13501 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13503 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13504 return mips_issue_rate ();
13507 /* Implement TARGET_SCHED_REORDER2. */
13510 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13511 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13513 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13514 return cached_can_issue_more
;
13517 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13520 mips_ls2_variable_issue (rtx insn
)
13522 if (mips_ls2
.alu1_turn_p
)
13524 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13525 mips_ls2
.alu1_turn_p
= false;
13529 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13530 mips_ls2
.alu1_turn_p
= true;
13533 if (mips_ls2
.falu1_turn_p
)
13535 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13536 mips_ls2
.falu1_turn_p
= false;
13540 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13541 mips_ls2
.falu1_turn_p
= true;
13544 if (recog_memoized (insn
) >= 0)
13545 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13548 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13551 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13552 rtx insn
, int more
)
13554 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13555 if (USEFUL_INSN_P (insn
))
13557 if (get_attr_type (insn
) != TYPE_GHOST
)
13559 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13560 mips_macc_chains_record (insn
);
13561 vr4130_last_insn
= insn
;
13563 mips_74k_agen_init (insn
);
13564 else if (TUNE_LOONGSON_2EF
)
13565 mips_ls2_variable_issue (insn
);
13568 /* Instructions of type 'multi' should all be split before
13569 the second scheduling pass. */
13570 gcc_assert (!reload_completed
13571 || recog_memoized (insn
) < 0
13572 || get_attr_type (insn
) != TYPE_MULTI
);
13574 cached_can_issue_more
= more
;
13578 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13579 return the first operand of the associated PREF or PREFX insn. */
13582 mips_prefetch_cookie (rtx write
, rtx locality
)
13584 /* store_streamed / load_streamed. */
13585 if (INTVAL (locality
) <= 0)
13586 return GEN_INT (INTVAL (write
) + 4);
13588 /* store / load. */
13589 if (INTVAL (locality
) <= 2)
13592 /* store_retained / load_retained. */
13593 return GEN_INT (INTVAL (write
) + 6);
13596 /* Flags that indicate when a built-in function is available.
13598 BUILTIN_AVAIL_NON_MIPS16
13599 The function is available on the current target, but only
13600 in non-MIPS16 mode. */
13601 #define BUILTIN_AVAIL_NON_MIPS16 1
13603 /* Declare an availability predicate for built-in functions that
13604 require non-MIPS16 mode and also require COND to be true.
13605 NAME is the main part of the predicate's name. */
13606 #define AVAIL_NON_MIPS16(NAME, COND) \
13607 static unsigned int \
13608 mips_builtin_avail_##NAME (void) \
13610 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13613 /* This structure describes a single built-in function. */
13614 struct mips_builtin_description
{
13615 /* The code of the main .md file instruction. See mips_builtin_type
13616 for more information. */
13617 enum insn_code icode
;
13619 /* The floating-point comparison code to use with ICODE, if any. */
13620 enum mips_fp_condition cond
;
13622 /* The name of the built-in function. */
13625 /* Specifies how the function should be expanded. */
13626 enum mips_builtin_type builtin_type
;
13628 /* The function's prototype. */
13629 enum mips_function_type function_type
;
13631 /* Whether the function is available. */
13632 unsigned int (*avail
) (void);
13635 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13636 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13637 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13638 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13639 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13640 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13641 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13642 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13643 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13644 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13646 /* Construct a mips_builtin_description from the given arguments.
13648 INSN is the name of the associated instruction pattern, without the
13649 leading CODE_FOR_mips_.
13651 CODE is the floating-point condition code associated with the
13652 function. It can be 'f' if the field is not applicable.
13654 NAME is the name of the function itself, without the leading
13657 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13659 AVAIL is the name of the availability predicate, without the leading
13660 mips_builtin_avail_. */
13661 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13662 FUNCTION_TYPE, AVAIL) \
13663 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13664 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13665 mips_builtin_avail_ ## AVAIL }
13667 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13668 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13669 are as for MIPS_BUILTIN. */
13670 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13671 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13673 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13674 are subject to mips_builtin_avail_<AVAIL>. */
13675 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13676 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13677 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13678 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13679 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13681 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13682 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13683 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13684 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13685 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13686 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13688 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13689 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13691 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13692 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13694 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13695 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13698 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13699 are subject to mips_builtin_avail_mips3d. */
13700 #define CMP_4S_BUILTINS(INSN, COND) \
13701 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13702 MIPS_BUILTIN_CMP_ANY, \
13703 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13704 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13705 MIPS_BUILTIN_CMP_ALL, \
13706 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13708 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13709 instruction requires mips_builtin_avail_<AVAIL>. */
13710 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13711 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13712 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13714 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13715 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13718 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13719 #define CMP_BUILTINS(COND) \
13720 MOVTF_BUILTINS (c, COND, paired_single), \
13721 MOVTF_BUILTINS (cabs, COND, mips3d), \
13722 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13723 CMP_PS_BUILTINS (c, COND, paired_single), \
13724 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13725 CMP_4S_BUILTINS (c, COND), \
13726 CMP_4S_BUILTINS (cabs, COND)
13728 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13729 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13730 and AVAIL are as for MIPS_BUILTIN. */
13731 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13732 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13733 FUNCTION_TYPE, AVAIL)
13735 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13736 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13737 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13738 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13739 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13741 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13742 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13743 builtin_description field. */
13744 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13745 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13746 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13747 FUNCTION_TYPE, mips_builtin_avail_loongson }
13749 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13750 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13751 builtin_description field. */
13752 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13753 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13755 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13756 We use functions of this form when the same insn can be usefully applied
13757 to more than one datatype. */
13758 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13759 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13761 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13762 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13763 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13764 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13765 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13766 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13767 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13768 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13770 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13771 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13772 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13773 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13774 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13775 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13776 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13777 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13778 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13779 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13780 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13781 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13782 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13783 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13784 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13785 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13786 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13787 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13788 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13789 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13790 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13791 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13792 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13793 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13794 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13795 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13796 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13797 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13798 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13799 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13801 static const struct mips_builtin_description mips_builtins
[] = {
13802 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13803 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13804 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13805 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13806 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13807 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13808 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13809 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13811 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13812 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13813 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13814 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13815 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13817 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13818 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13819 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13820 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13821 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13822 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13824 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13825 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13826 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13827 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13828 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13829 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13831 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13833 /* Built-in functions for the SB-1 processor. */
13834 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13836 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13837 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13838 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13839 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13840 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13841 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13842 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13843 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13844 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13845 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13846 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13847 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13848 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13849 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13850 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13851 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13852 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13853 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13854 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13855 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13856 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13857 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13858 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13859 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13860 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13861 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13862 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13863 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13864 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13865 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13866 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13867 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13868 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13869 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13870 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13871 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13872 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13873 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13874 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13875 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13876 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13877 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13878 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13879 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13880 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
13881 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13882 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
13883 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
13884 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13885 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13886 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13887 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13888 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13889 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13890 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13891 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13892 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13893 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13894 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13895 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13896 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
13897 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
13898 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13899 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13900 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13901 BPOSGE_BUILTIN (32, dsp
),
13903 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13904 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
13905 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13906 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13907 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13908 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13909 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13910 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13911 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13912 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13913 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13914 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13915 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13916 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13917 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13918 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13919 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
13920 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13921 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13922 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13923 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13924 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13925 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
13926 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13927 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13928 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13929 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13930 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13931 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13932 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13933 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13934 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13935 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13936 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13937 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13939 /* Built-in functions for the DSP ASE (32-bit only). */
13940 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13941 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13942 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13943 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13944 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13945 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13946 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13947 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13948 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13949 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13950 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13951 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13952 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13953 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13954 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13955 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13956 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13957 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13958 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13959 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13960 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13961 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13962 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13963 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13964 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13965 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
13966 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
13968 /* Built-in functions for the DSP ASE (64-bit only). */
13969 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
13971 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13972 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13973 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13974 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13975 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13976 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13977 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13978 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13979 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13980 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13982 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13983 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
13984 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
13985 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
13986 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13987 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13988 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13989 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13990 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13991 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13992 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13993 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
13994 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13995 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13996 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13997 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13998 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
13999 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14000 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14001 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14002 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
14003 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14004 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14005 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14006 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14007 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14008 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14009 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14010 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14011 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14012 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14013 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14014 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14015 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14016 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14017 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14018 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14019 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14020 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
14021 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
14022 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14023 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14024 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14025 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14026 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14027 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14028 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14029 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14030 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14031 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14032 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14033 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14034 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14035 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14036 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14037 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14038 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14039 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14040 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14041 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14042 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14043 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14044 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14045 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14046 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14047 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14048 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14049 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14050 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14051 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14052 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14053 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14054 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14055 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14056 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14057 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14058 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14059 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14060 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14061 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14062 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14063 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14064 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14065 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14066 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14067 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14068 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14069 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14070 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14071 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14072 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14073 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14074 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14075 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14076 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14077 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14078 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14079 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14080 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14081 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14083 /* Sundry other built-in functions. */
14084 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14087 /* Index I is the function declaration for mips_builtins[I], or null if the
14088 function isn't defined on this target. */
14089 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14091 /* MODE is a vector mode whose elements have type TYPE. Return the type
14092 of the vector itself. */
14095 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
14097 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14100 mode_index
= (int) mode
;
14102 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14103 mode_index
+= MAX_MACHINE_MODE
;
14105 if (types
[mode_index
] == NULL_TREE
)
14106 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14107 return types
[mode_index
];
14110 /* Return a type for 'const volatile void *'. */
14113 mips_build_cvpointer_type (void)
14117 if (cache
== NULL_TREE
)
14118 cache
= build_pointer_type (build_qualified_type
14120 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14124 /* Source-level argument types. */
14125 #define MIPS_ATYPE_VOID void_type_node
14126 #define MIPS_ATYPE_INT integer_type_node
14127 #define MIPS_ATYPE_POINTER ptr_type_node
14128 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14130 /* Standard mode-based argument types. */
14131 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14132 #define MIPS_ATYPE_SI intSI_type_node
14133 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14134 #define MIPS_ATYPE_DI intDI_type_node
14135 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14136 #define MIPS_ATYPE_SF float_type_node
14137 #define MIPS_ATYPE_DF double_type_node
14139 /* Vector argument types. */
14140 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14141 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14142 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14143 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14144 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14145 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14146 #define MIPS_ATYPE_UV2SI \
14147 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14148 #define MIPS_ATYPE_UV4HI \
14149 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14150 #define MIPS_ATYPE_UV8QI \
14151 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14153 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14154 their associated MIPS_ATYPEs. */
14155 #define MIPS_FTYPE_ATYPES1(A, B) \
14156 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14158 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14159 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14161 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14162 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14164 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14165 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14168 /* Return the function type associated with function prototype TYPE. */
14171 mips_build_function_type (enum mips_function_type type
)
14173 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14175 if (types
[(int) type
] == NULL_TREE
)
14178 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14179 case MIPS_FTYPE_NAME##NUM ARGS: \
14180 types[(int) type] \
14181 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14184 #include "config/mips/mips-ftypes.def"
14185 #undef DEF_MIPS_FTYPE
14187 gcc_unreachable ();
14190 return types
[(int) type
];
14193 /* Implement TARGET_INIT_BUILTINS. */
14196 mips_init_builtins (void)
14198 const struct mips_builtin_description
*d
;
14201 /* Iterate through all of the bdesc arrays, initializing all of the
14202 builtin functions. */
14203 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14205 d
= &mips_builtins
[i
];
14207 mips_builtin_decls
[i
]
14208 = add_builtin_function (d
->name
,
14209 mips_build_function_type (d
->function_type
),
14210 i
, BUILT_IN_MD
, NULL
, NULL
);
14214 /* Implement TARGET_BUILTIN_DECL. */
14217 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14219 if (code
>= ARRAY_SIZE (mips_builtins
))
14220 return error_mark_node
;
14221 return mips_builtin_decls
[code
];
14224 /* Take argument ARGNO from EXP's argument list and convert it into
14225 an expand operand. Store the operand in *OP. */
14228 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14229 unsigned int argno
)
14234 arg
= CALL_EXPR_ARG (exp
, argno
);
14235 value
= expand_normal (arg
);
14236 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14239 /* Expand instruction ICODE as part of a built-in function sequence.
14240 Use the first NOPS elements of OPS as the instruction's operands.
14241 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14242 instruction has no target.
14244 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14247 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14248 struct expand_operand
*ops
, bool has_target_p
)
14250 if (!maybe_expand_insn (icode
, nops
, ops
))
14252 error ("invalid argument to built-in function");
14253 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14255 return has_target_p
? ops
[0].value
: const0_rtx
;
14258 /* Expand a floating-point comparison for built-in function call EXP.
14259 The first NARGS arguments are the values to be compared. ICODE is
14260 the .md pattern that does the comparison and COND is the condition
14261 that is being tested. Return an rtx for the result. */
14264 mips_expand_builtin_compare_1 (enum insn_code icode
,
14265 enum mips_fp_condition cond
,
14266 tree exp
, int nargs
)
14268 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14272 /* The instruction should have a target operand, an operand for each
14273 argument, and an operand for COND. */
14274 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14276 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14278 create_fixed_operand (&ops
[opno
++], output
);
14279 for (argno
= 0; argno
< nargs
; argno
++)
14280 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14281 create_integer_operand (&ops
[opno
++], (int) cond
);
14282 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14285 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14286 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14287 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14288 suggests a good place to put the result. */
14291 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14294 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14297 /* Map any target to operand 0. */
14300 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14302 /* Map the arguments to the other operands. */
14303 gcc_assert (opno
+ call_expr_nargs (exp
)
14304 == insn_data
[icode
].n_generator_args
);
14305 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14306 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14308 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14311 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14312 function; TYPE says which. EXP is the CALL_EXPR that calls the
14313 function, ICODE is the instruction that should be used to compare
14314 the first two arguments, and COND is the condition it should test.
14315 TARGET, if nonnull, suggests a good place to put the result. */
14318 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14319 enum insn_code icode
, enum mips_fp_condition cond
,
14320 rtx target
, tree exp
)
14322 struct expand_operand ops
[4];
14325 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14326 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14327 if (type
== MIPS_BUILTIN_MOVT
)
14329 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14330 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14334 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14335 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14337 create_fixed_operand (&ops
[3], cmp_result
);
14338 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14342 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14343 into TARGET otherwise. Return TARGET. */
14346 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14347 rtx value_if_true
, rtx value_if_false
)
14349 rtx true_label
, done_label
;
14351 true_label
= gen_label_rtx ();
14352 done_label
= gen_label_rtx ();
14354 /* First assume that CONDITION is false. */
14355 mips_emit_move (target
, value_if_false
);
14357 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14358 emit_jump_insn (gen_condjump (condition
, true_label
));
14359 emit_jump_insn (gen_jump (done_label
));
14362 /* Fix TARGET if CONDITION is true. */
14363 emit_label (true_label
);
14364 mips_emit_move (target
, value_if_true
);
14366 emit_label (done_label
);
14370 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14371 the CALL_EXPR that calls the function, ICODE is the code of the
14372 comparison instruction, and COND is the condition it should test.
14373 TARGET, if nonnull, suggests a good place to put the boolean result. */
14376 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14377 enum insn_code icode
, enum mips_fp_condition cond
,
14378 rtx target
, tree exp
)
14380 rtx offset
, condition
, cmp_result
;
14382 if (target
== 0 || GET_MODE (target
) != SImode
)
14383 target
= gen_reg_rtx (SImode
);
14384 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14385 call_expr_nargs (exp
));
14387 /* If the comparison sets more than one register, we define the result
14388 to be 0 if all registers are false and -1 if all registers are true.
14389 The value of the complete result is indeterminate otherwise. */
14390 switch (builtin_type
)
14392 case MIPS_BUILTIN_CMP_ALL
:
14393 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14394 return mips_builtin_branch_and_move (condition
, target
,
14395 const0_rtx
, const1_rtx
);
14397 case MIPS_BUILTIN_CMP_UPPER
:
14398 case MIPS_BUILTIN_CMP_LOWER
:
14399 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14400 condition
= gen_single_cc (cmp_result
, offset
);
14401 return mips_builtin_branch_and_move (condition
, target
,
14402 const1_rtx
, const0_rtx
);
14405 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14406 return mips_builtin_branch_and_move (condition
, target
,
14407 const1_rtx
, const0_rtx
);
14411 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14412 if nonnull, suggests a good place to put the boolean result. */
14415 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14417 rtx condition
, cmp_result
;
14420 if (target
== 0 || GET_MODE (target
) != SImode
)
14421 target
= gen_reg_rtx (SImode
);
14423 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14425 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14430 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14431 return mips_builtin_branch_and_move (condition
, target
,
14432 const1_rtx
, const0_rtx
);
14435 /* Implement TARGET_EXPAND_BUILTIN. */
14438 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14439 enum machine_mode mode
, int ignore
)
14442 unsigned int fcode
, avail
;
14443 const struct mips_builtin_description
*d
;
14445 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14446 fcode
= DECL_FUNCTION_CODE (fndecl
);
14447 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14448 d
= &mips_builtins
[fcode
];
14449 avail
= d
->avail ();
14450 gcc_assert (avail
!= 0);
14453 error ("built-in function %qE not supported for MIPS16",
14454 DECL_NAME (fndecl
));
14455 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14457 switch (d
->builtin_type
)
14459 case MIPS_BUILTIN_DIRECT
:
14460 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14462 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14463 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14465 case MIPS_BUILTIN_MOVT
:
14466 case MIPS_BUILTIN_MOVF
:
14467 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14468 d
->cond
, target
, exp
);
14470 case MIPS_BUILTIN_CMP_ANY
:
14471 case MIPS_BUILTIN_CMP_ALL
:
14472 case MIPS_BUILTIN_CMP_UPPER
:
14473 case MIPS_BUILTIN_CMP_LOWER
:
14474 case MIPS_BUILTIN_CMP_SINGLE
:
14475 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14476 d
->cond
, target
, exp
);
14478 case MIPS_BUILTIN_BPOSGE32
:
14479 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14481 gcc_unreachable ();
14484 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14485 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14486 struct mips16_constant
{
14487 struct mips16_constant
*next
;
14490 enum machine_mode mode
;
14493 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14494 first constant, HIGHEST_ADDRESS is the highest address that the first
14495 byte of the pool can have, and INSN_ADDRESS is the current instruction
14497 struct mips16_constant_pool
{
14498 struct mips16_constant
*first
;
14499 int highest_address
;
14503 /* Add constant VALUE to POOL and return its label. MODE is the
14504 value's mode (used for CONST_INTs, etc.). */
14507 mips16_add_constant (struct mips16_constant_pool
*pool
,
14508 rtx value
, enum machine_mode mode
)
14510 struct mips16_constant
**p
, *c
;
14511 bool first_of_size_p
;
14513 /* See whether the constant is already in the pool. If so, return the
14514 existing label, otherwise leave P pointing to the place where the
14515 constant should be added.
14517 Keep the pool sorted in increasing order of mode size so that we can
14518 reduce the number of alignments needed. */
14519 first_of_size_p
= true;
14520 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14522 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14523 return (*p
)->label
;
14524 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14526 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14527 first_of_size_p
= false;
14530 /* In the worst case, the constant needed by the earliest instruction
14531 will end up at the end of the pool. The entire pool must then be
14532 accessible from that instruction.
14534 When adding the first constant, set the pool's highest address to
14535 the address of the first out-of-range byte. Adjust this address
14536 downwards each time a new constant is added. */
14537 if (pool
->first
== 0)
14538 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14539 of the instruction with the lowest two bits clear. The base PC
14540 value for LDPC has the lowest three bits clear. Assume the worst
14541 case here; namely that the PC-relative instruction occupies the
14542 last 2 bytes in an aligned word. */
14543 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14544 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14545 if (first_of_size_p
)
14546 /* Take into account the worst possible padding due to alignment. */
14547 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14549 /* Create a new entry. */
14550 c
= XNEW (struct mips16_constant
);
14553 c
->label
= gen_label_rtx ();
14560 /* Output constant VALUE after instruction INSN and return the last
14561 instruction emitted. MODE is the mode of the constant. */
14564 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14566 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14568 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14569 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14572 if (SCALAR_FLOAT_MODE_P (mode
))
14573 return emit_insn_after (gen_consttable_float (value
), insn
);
14575 if (VECTOR_MODE_P (mode
))
14579 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14580 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14581 CONST_VECTOR_ELT (value
, i
), insn
);
14585 gcc_unreachable ();
14588 /* Dump out the constants in CONSTANTS after INSN. */
14591 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14593 struct mips16_constant
*c
, *next
;
14597 for (c
= constants
; c
!= NULL
; c
= next
)
14599 /* If necessary, increase the alignment of PC. */
14600 if (align
< GET_MODE_SIZE (c
->mode
))
14602 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14603 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14605 align
= GET_MODE_SIZE (c
->mode
);
14607 insn
= emit_label_after (c
->label
, insn
);
14608 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14614 emit_barrier_after (insn
);
14617 /* Return the length of instruction INSN. */
14620 mips16_insn_length (rtx insn
)
14622 if (JUMP_TABLE_DATA_P (insn
))
14624 rtx body
= PATTERN (insn
);
14625 if (GET_CODE (body
) == ADDR_VEC
)
14626 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14627 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14628 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14630 gcc_unreachable ();
14632 return get_attr_length (insn
);
14635 /* If *X is a symbolic constant that refers to the constant pool, add
14636 the constant to POOL and rewrite *X to use the constant's label. */
14639 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14641 rtx base
, offset
, label
;
14643 split_const (*x
, &base
, &offset
);
14644 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14646 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14647 get_pool_mode (base
));
14648 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14649 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14653 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14654 INSN is the instruction we're rewriting and POOL points to the current
14656 struct mips16_rewrite_pool_refs_info
{
14658 struct mips16_constant_pool
*pool
;
14661 /* Rewrite *X so that constant pool references refer to the constant's
14662 label instead. DATA points to a mips16_rewrite_pool_refs_info
14666 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14668 struct mips16_rewrite_pool_refs_info
*info
=
14669 (struct mips16_rewrite_pool_refs_info
*) data
;
14671 if (force_to_mem_operand (*x
, Pmode
))
14673 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14674 validate_change (info
->insn
, x
, mem
, false);
14679 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14683 /* Don't rewrite the __mips16_rdwr symbol. */
14684 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14687 if (TARGET_MIPS16_TEXT_LOADS
)
14688 mips16_rewrite_pool_constant (info
->pool
, x
);
14690 return GET_CODE (*x
) == CONST
? -1 : 0;
14693 /* Return whether CFG is used in mips_reorg. */
14696 mips_cfg_in_reorg (void)
14698 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14699 || TARGET_RELAX_PIC_CALLS
);
14702 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14703 otherwise assume that they are already split. */
14706 mips16_lay_out_constants (bool split_p
)
14708 struct mips16_constant_pool pool
;
14709 struct mips16_rewrite_pool_refs_info info
;
14712 if (!TARGET_MIPS16_PCREL_LOADS
)
14717 if (mips_cfg_in_reorg ())
14718 split_all_insns ();
14720 split_all_insns_noflow ();
14723 memset (&pool
, 0, sizeof (pool
));
14724 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14726 /* Rewrite constant pool references in INSN. */
14727 if (USEFUL_INSN_P (insn
))
14731 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14734 pool
.insn_address
+= mips16_insn_length (insn
);
14736 if (pool
.first
!= NULL
)
14738 /* If there are no natural barriers between the first user of
14739 the pool and the highest acceptable address, we'll need to
14740 create a new instruction to jump around the constant pool.
14741 In the worst case, this instruction will be 4 bytes long.
14743 If it's too late to do this transformation after INSN,
14744 do it immediately before INSN. */
14745 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14749 label
= gen_label_rtx ();
14751 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14752 JUMP_LABEL (jump
) = label
;
14753 LABEL_NUSES (label
) = 1;
14754 barrier
= emit_barrier_after (jump
);
14756 emit_label_after (label
, barrier
);
14757 pool
.insn_address
+= 4;
14760 /* See whether the constant pool is now out of range of the first
14761 user. If so, output the constants after the previous barrier.
14762 Note that any instructions between BARRIER and INSN (inclusive)
14763 will use negative offsets to refer to the pool. */
14764 if (pool
.insn_address
> pool
.highest_address
)
14766 mips16_emit_constants (pool
.first
, barrier
);
14770 else if (BARRIER_P (insn
))
14774 mips16_emit_constants (pool
.first
, get_last_insn ());
14777 /* Return true if it is worth r10k_simplify_address's while replacing
14778 an address with X. We are looking for constants, and for addresses
14779 at a known offset from the incoming stack pointer. */
14782 r10k_simplified_address_p (rtx x
)
14784 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14786 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14789 /* X is an expression that appears in INSN. Try to use the UD chains
14790 to simplify it, returning the simplified form on success and the
14791 original form otherwise. Replace the incoming value of $sp with
14792 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14795 r10k_simplify_address (rtx x
, rtx insn
)
14797 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14799 struct df_link
*defs
;
14804 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14805 if (op0
!= XEXP (x
, 0))
14806 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14807 op0
, GET_MODE (XEXP (x
, 0)));
14809 else if (BINARY_P (x
))
14811 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14812 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14813 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14814 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14816 else if (GET_CODE (x
) == LO_SUM
)
14818 /* LO_SUMs can be offset from HIGHs, if we know they won't
14819 overflow. See mips_classify_address for the rationale behind
14821 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14822 if (GET_CODE (op0
) == HIGH
)
14823 newx
= XEXP (x
, 1);
14825 else if (REG_P (x
))
14827 /* Uses are recorded by regno_reg_rtx, not X itself. */
14828 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14830 defs
= DF_REF_CHAIN (use
);
14832 /* Require a single definition. */
14833 if (defs
&& defs
->next
== NULL
)
14836 if (DF_REF_IS_ARTIFICIAL (def
))
14838 /* Replace the incoming value of $sp with
14839 virtual_incoming_args_rtx. */
14840 if (x
== stack_pointer_rtx
14841 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
14842 newx
= virtual_incoming_args_rtx
;
14844 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14847 /* Make sure that DEF_INSN is a single set of REG. */
14848 def_insn
= DF_REF_INSN (def
);
14849 if (NONJUMP_INSN_P (def_insn
))
14851 set
= single_set (def_insn
);
14852 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14854 /* Prefer to use notes, since the def-use chains
14855 are often shorter. */
14856 note
= find_reg_equal_equiv_note (def_insn
);
14858 newx
= XEXP (note
, 0);
14860 newx
= SET_SRC (set
);
14861 newx
= r10k_simplify_address (newx
, def_insn
);
14867 if (newx
&& r10k_simplified_address_p (newx
))
14872 /* Return true if ADDRESS is known to be an uncached address
14873 on R10K systems. */
14876 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
14878 unsigned HOST_WIDE_INT upper
;
14880 /* Check for KSEG1. */
14881 if (address
+ 0x60000000 < 0x20000000)
14884 /* Check for uncached XKPHYS addresses. */
14885 if (Pmode
== DImode
)
14887 upper
= (address
>> 40) & 0xf9ffff;
14888 if (upper
== 0x900000 || upper
== 0xb80000)
14894 /* Return true if we can prove that an access to address X in instruction
14895 INSN would be safe from R10K speculation. This X is a general
14896 expression; it might not be a legitimate address. */
14899 r10k_safe_address_p (rtx x
, rtx insn
)
14902 HOST_WIDE_INT offset_val
;
14904 x
= r10k_simplify_address (x
, insn
);
14906 /* Check for references to the stack frame. It doesn't really matter
14907 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14908 allows us to assume that accesses to any part of the eventual frame
14909 is safe from speculation at any point in the function. */
14910 mips_split_plus (x
, &base
, &offset_val
);
14911 if (base
== virtual_incoming_args_rtx
14912 && offset_val
>= -cfun
->machine
->frame
.total_size
14913 && offset_val
< cfun
->machine
->frame
.args_size
)
14916 /* Check for uncached addresses. */
14917 if (CONST_INT_P (x
))
14918 return r10k_uncached_address_p (INTVAL (x
));
14920 /* Check for accesses to a static object. */
14921 split_const (x
, &base
, &offset
);
14922 return offset_within_block_p (base
, INTVAL (offset
));
14925 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14926 an in-range access to an automatic variable, or to an object with
14927 a link-time-constant address. */
14930 r10k_safe_mem_expr_p (tree expr
, HOST_WIDE_INT offset
)
14932 HOST_WIDE_INT bitoffset
, bitsize
;
14933 tree inner
, var_offset
;
14934 enum machine_mode mode
;
14935 int unsigned_p
, volatile_p
;
14937 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
14938 &unsigned_p
, &volatile_p
, false);
14939 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
14942 offset
+= bitoffset
/ BITS_PER_UNIT
;
14943 return offset
>= 0 && offset
< tree_low_cst (DECL_SIZE_UNIT (inner
), 1);
14946 /* A for_each_rtx callback for which DATA points to the instruction
14947 containing *X. Stop the search if we find a MEM that is not safe
14948 from R10K speculation. */
14951 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
14960 && MEM_OFFSET_KNOWN_P (mem
)
14961 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
14964 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
14970 /* A note_stores callback for which DATA points to an instruction pointer.
14971 If *DATA is nonnull, make it null if it X contains a MEM that is not
14972 safe from R10K speculation. */
14975 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14980 insn_ptr
= (rtx
*) data
;
14981 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
14982 *insn_ptr
= NULL_RTX
;
14985 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14986 Return nonzero if the call is not to a declared function. */
14989 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
14998 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
15004 /* Return true if instruction INSN needs to be protected by an R10K
15008 r10k_needs_protection_p (rtx insn
)
15011 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
15013 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
15015 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
15016 return insn
== NULL_RTX
;
15019 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
15022 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15023 edge is unconditional. */
15026 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15031 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15032 if (!single_succ_p (e
->src
)
15033 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15034 || (e
->flags
& EDGE_COMPLEX
) != 0)
15039 /* Implement -mr10k-cache-barrier= for the current function. */
15042 r10k_insert_cache_barriers (void)
15044 int *rev_post_order
;
15047 sbitmap protected_bbs
;
15048 rtx insn
, end
, unprotected_region
;
15052 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15056 /* Calculate dominators. */
15057 calculate_dominance_info (CDI_DOMINATORS
);
15059 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15060 X is protected by a cache barrier. */
15061 protected_bbs
= sbitmap_alloc (last_basic_block
);
15062 bitmap_clear (protected_bbs
);
15064 /* Iterate over the basic blocks in reverse post-order. */
15065 rev_post_order
= XNEWVEC (int, last_basic_block
);
15066 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15067 for (i
= 0; i
< n
; i
++)
15069 bb
= BASIC_BLOCK (rev_post_order
[i
]);
15071 /* If this block is only reached by unconditional edges, and if the
15072 source of every edge is protected, the beginning of the block is
15074 if (r10k_protected_bb_p (bb
, protected_bbs
))
15075 unprotected_region
= NULL_RTX
;
15077 unprotected_region
= pc_rtx
;
15078 end
= NEXT_INSN (BB_END (bb
));
15080 /* UNPROTECTED_REGION is:
15082 - null if we are processing a protected region,
15083 - pc_rtx if we are processing an unprotected region but have
15084 not yet found the first instruction in it
15085 - the first instruction in an unprotected region otherwise. */
15086 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15088 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15090 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15091 /* This CACHE instruction protects the following code. */
15092 unprotected_region
= NULL_RTX
;
15095 /* See if INSN is the first instruction in this
15096 unprotected region. */
15097 if (unprotected_region
== pc_rtx
)
15098 unprotected_region
= insn
;
15100 /* See if INSN needs to be protected. If so,
15101 we must insert a cache barrier somewhere between
15102 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15103 clear which position is better performance-wise,
15104 but as a tie-breaker, we assume that it is better
15105 to allow delay slots to be back-filled where
15106 possible, and that it is better not to insert
15107 barriers in the middle of already-scheduled code.
15108 We therefore insert the barrier at the beginning
15110 if (r10k_needs_protection_p (insn
))
15112 emit_insn_before (gen_r10k_cache_barrier (),
15113 unprotected_region
);
15114 unprotected_region
= NULL_RTX
;
15120 /* The called function is not required to protect the exit path.
15121 The code that follows a call is therefore unprotected. */
15122 unprotected_region
= pc_rtx
;
15125 /* Record whether the end of this block is protected. */
15126 if (unprotected_region
== NULL_RTX
)
15127 bitmap_set_bit (protected_bbs
, bb
->index
);
15129 XDELETEVEC (rev_post_order
);
15131 sbitmap_free (protected_bbs
);
15133 free_dominance_info (CDI_DOMINATORS
);
15136 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15137 otherwise. If INSN has two call rtx, then store the second one in
15141 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
15146 if (!CALL_P (insn
))
15149 x
= PATTERN (insn
);
15150 if (GET_CODE (x
) == PARALLEL
)
15152 /* Calls returning complex values have two CALL rtx. Look for the second
15153 one here, and return it via the SECOND_CALL arg. */
15154 x2
= XVECEXP (x
, 0, 1);
15155 if (GET_CODE (x2
) == SET
)
15157 if (GET_CODE (x2
) == CALL
)
15160 x
= XVECEXP (x
, 0, 0);
15162 if (GET_CODE (x
) == SET
)
15164 gcc_assert (GET_CODE (x
) == CALL
);
15169 /* REG is set in DEF. See if the definition is one of the ways we load a
15170 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15171 If it is, return the symbol reference of the function, otherwise return
15174 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15175 the values of source registers, otherwise treat such registers as
15176 having an unknown value. */
15179 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15183 if (DF_REF_IS_ARTIFICIAL (def
))
15186 def_insn
= DF_REF_INSN (def
);
15187 set
= single_set (def_insn
);
15188 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15190 rtx note
, src
, symbol
;
15192 /* First see whether the source is a plain symbol. This is used
15193 when calling symbols that are not lazily bound. */
15194 src
= SET_SRC (set
);
15195 if (GET_CODE (src
) == SYMBOL_REF
)
15198 /* Handle %call16 references. */
15199 symbol
= mips_strip_unspec_call (src
);
15202 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15206 /* If we have something more complicated, look for a
15207 REG_EQUAL or REG_EQUIV note. */
15208 note
= find_reg_equal_equiv_note (def_insn
);
15209 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15210 return XEXP (note
, 0);
15212 /* Follow at most one simple register copy. Such copies are
15213 interesting in cases like:
15217 locally_binding_fn (...);
15222 locally_binding_fn (...);
15224 locally_binding_fn (...);
15226 where the load of locally_binding_fn can legitimately be
15227 hoisted or shared. However, we do not expect to see complex
15228 chains of copies, so a full worklist solution to the problem
15229 would probably be overkill. */
15230 if (recurse_p
&& REG_P (src
))
15231 return mips_find_pic_call_symbol (def_insn
, src
, false);
15237 /* Find the definition of the use of REG in INSN. See if the definition
15238 is one of the ways we load a register with a symbol address for a
15239 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15240 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15241 mips_pic_call_symbol_from_set. */
15244 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
15247 struct df_link
*defs
;
15250 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15253 defs
= DF_REF_CHAIN (use
);
15256 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15260 /* If we have more than one definition, they need to be identical. */
15261 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15265 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15266 if (!rtx_equal_p (symbol
, other
))
15273 /* Replace the args_size operand of the call expression CALL with the
15274 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15277 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15281 args_size
= XEXP (call
, 1);
15282 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15283 gen_rtvec (2, args_size
, symbol
),
15287 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15288 if instead of the arg_size argument it contains the call attributes. If
15289 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15290 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15294 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15296 rtx args_size
, symbol
;
15298 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15301 args_size
= operands
[args_size_opno
];
15302 if (GET_CODE (args_size
) != UNSPEC
)
15304 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15306 symbol
= XVECEXP (args_size
, 0, 1);
15307 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15309 operands
[args_size_opno
] = symbol
;
15313 /* Use DF to annotate PIC indirect calls with the function symbol they
15317 mips_annotate_pic_calls (void)
15323 FOR_BB_INSNS (bb
, insn
)
15325 rtx call
, reg
, symbol
, second_call
;
15328 call
= mips_call_expr_from_insn (insn
, &second_call
);
15331 gcc_assert (MEM_P (XEXP (call
, 0)));
15332 reg
= XEXP (XEXP (call
, 0), 0);
15336 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15339 mips_annotate_pic_call_expr (call
, symbol
);
15341 mips_annotate_pic_call_expr (second_call
, symbol
);
15346 /* A temporary variable used by for_each_rtx callbacks, etc. */
15347 static rtx mips_sim_insn
;
15349 /* A structure representing the state of the processor pipeline.
15350 Used by the mips_sim_* family of functions. */
15352 /* The maximum number of instructions that can be issued in a cycle.
15353 (Caches mips_issue_rate.) */
15354 unsigned int issue_rate
;
15356 /* The current simulation time. */
15359 /* How many more instructions can be issued in the current cycle. */
15360 unsigned int insns_left
;
15362 /* LAST_SET[X].INSN is the last instruction to set register X.
15363 LAST_SET[X].TIME is the time at which that instruction was issued.
15364 INSN is null if no instruction has yet set register X. */
15368 } last_set
[FIRST_PSEUDO_REGISTER
];
15370 /* The pipeline's current DFA state. */
15374 /* Reset STATE to the initial simulation state. */
15377 mips_sim_reset (struct mips_sim
*state
)
15379 curr_state
= state
->dfa_state
;
15382 state
->insns_left
= state
->issue_rate
;
15383 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15384 state_reset (curr_state
);
15386 targetm
.sched
.init (0, false, 0);
15387 advance_state (curr_state
);
15390 /* Initialize STATE before its first use. DFA_STATE points to an
15391 allocated but uninitialized DFA state. */
15394 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15396 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15397 targetm
.sched
.init_dfa_pre_cycle_insn ();
15399 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15400 targetm
.sched
.init_dfa_post_cycle_insn ();
15402 state
->issue_rate
= mips_issue_rate ();
15403 state
->dfa_state
= dfa_state
;
15404 mips_sim_reset (state
);
15407 /* Advance STATE by one clock cycle. */
15410 mips_sim_next_cycle (struct mips_sim
*state
)
15412 curr_state
= state
->dfa_state
;
15415 state
->insns_left
= state
->issue_rate
;
15416 advance_state (curr_state
);
15419 /* Advance simulation state STATE until instruction INSN can read
15423 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
15425 unsigned int regno
, end_regno
;
15427 end_regno
= END_REGNO (reg
);
15428 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15429 if (state
->last_set
[regno
].insn
!= 0)
15433 t
= (state
->last_set
[regno
].time
15434 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15435 while (state
->time
< t
)
15436 mips_sim_next_cycle (state
);
15440 /* A for_each_rtx callback. If *X is a register, advance simulation state
15441 DATA until mips_sim_insn can read the register's value. */
15444 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
15447 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
15451 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15454 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15456 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
15459 /* Advance simulation state STATE until all of INSN's register
15460 dependencies are satisfied. */
15463 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
15465 mips_sim_insn
= insn
;
15466 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15469 /* Advance simulation state STATE until the units required by
15470 instruction INSN are available. */
15473 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
15477 tmp_state
= alloca (state_size ());
15478 while (state
->insns_left
== 0
15479 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15480 state_transition (tmp_state
, insn
) >= 0))
15481 mips_sim_next_cycle (state
);
15484 /* Advance simulation state STATE until INSN is ready to issue. */
15487 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
15489 mips_sim_wait_regs (state
, insn
);
15490 mips_sim_wait_units (state
, insn
);
15493 /* mips_sim_insn has just set X. Update the LAST_SET array
15494 in simulation state DATA. */
15497 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15499 struct mips_sim
*state
;
15501 state
= (struct mips_sim
*) data
;
15504 unsigned int regno
, end_regno
;
15506 end_regno
= END_REGNO (x
);
15507 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15509 state
->last_set
[regno
].insn
= mips_sim_insn
;
15510 state
->last_set
[regno
].time
= state
->time
;
15515 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15516 can issue immediately (i.e., that mips_sim_wait_insn has already
15520 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
15522 curr_state
= state
->dfa_state
;
15524 state_transition (curr_state
, insn
);
15525 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15526 state
->insns_left
);
15528 mips_sim_insn
= insn
;
15529 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15532 /* Simulate issuing a NOP in state STATE. */
15535 mips_sim_issue_nop (struct mips_sim
*state
)
15537 if (state
->insns_left
== 0)
15538 mips_sim_next_cycle (state
);
15539 state
->insns_left
--;
15542 /* Update simulation state STATE so that it's ready to accept the instruction
15543 after INSN. INSN should be part of the main rtl chain, not a member of a
15547 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
15549 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15551 mips_sim_issue_nop (state
);
15553 switch (GET_CODE (SEQ_BEGIN (insn
)))
15557 /* We can't predict the processor state after a call or label. */
15558 mips_sim_reset (state
);
15562 /* The delay slots of branch likely instructions are only executed
15563 when the branch is taken. Therefore, if the caller has simulated
15564 the delay slot instruction, STATE does not really reflect the state
15565 of the pipeline for the instruction after the delay slot. Also,
15566 branch likely instructions tend to incur a penalty when not taken,
15567 so there will probably be an extra delay between the branch and
15568 the instruction after the delay slot. */
15569 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15570 mips_sim_reset (state
);
15578 /* Use simulator state STATE to calculate the execution time of
15579 instruction sequence SEQ. */
15581 static unsigned int
15582 mips_seq_time (struct mips_sim
*state
, rtx seq
)
15584 mips_sim_reset (state
);
15585 for (rtx insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15587 mips_sim_wait_insn (state
, insn
);
15588 mips_sim_issue_insn (state
, insn
);
15590 return state
->time
;
15593 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15594 setting SETTING, using STATE to simulate instruction sequences. */
15596 static unsigned int
15597 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15599 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15602 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15603 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15604 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15606 /* If the target provides mulsidi3_32bit then that's the most likely
15607 consumer of the result. Test for bypasses. */
15608 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15610 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15611 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15614 unsigned int time
= mips_seq_time (state
, get_insns ());
15619 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15620 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15621 Prefer MULT -- which is shorter -- in the event of a tie. */
15624 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15627 /* No MTLO or MTHI available. */
15628 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15631 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15632 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15633 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15637 /* Set up costs based on the current architecture and tuning settings. */
15640 mips_set_tuning_info (void)
15642 if (mips_tuning_info
.initialized_p
15643 && mips_tuning_info
.arch
== mips_arch
15644 && mips_tuning_info
.tune
== mips_tune
15645 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15648 mips_tuning_info
.arch
= mips_arch
;
15649 mips_tuning_info
.tune
= mips_tune
;
15650 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15651 mips_tuning_info
.initialized_p
= true;
15655 struct mips_sim state
;
15656 mips_sim_init (&state
, alloca (state_size ()));
15658 mips_set_fast_mult_zero_zero_p (&state
);
15663 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15666 mips_expand_to_rtl_hook (void)
15668 /* We need to call this at a point where we can safely create sequences
15669 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15670 need to call it at a point where the DFA infrastructure is not
15671 already in use, so we can't just call it lazily on demand.
15673 At present, mips_tuning_info is only needed during post-expand
15674 RTL passes such as split_insns, so this hook should be early enough.
15675 We may need to move the call elsewhere if mips_tuning_info starts
15676 to be used for other things (such as rtx_costs, or expanders that
15677 could be called during gimple optimization). */
15678 mips_set_tuning_info ();
15681 /* The VR4130 pipeline issues aligned pairs of instructions together,
15682 but it stalls the second instruction if it depends on the first.
15683 In order to cut down the amount of logic required, this dependence
15684 check is not based on a full instruction decode. Instead, any non-SPECIAL
15685 instruction is assumed to modify the register specified by bits 20-16
15686 (which is usually the "rt" field).
15688 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15689 input, so we can end up with a false dependence between the branch
15690 and its delay slot. If this situation occurs in instruction INSN,
15691 try to avoid it by swapping rs and rt. */
15694 vr4130_avoid_branch_rt_conflict (rtx insn
)
15698 first
= SEQ_BEGIN (insn
);
15699 second
= SEQ_END (insn
);
15701 && NONJUMP_INSN_P (second
)
15702 && GET_CODE (PATTERN (first
)) == SET
15703 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15704 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15706 /* Check for the right kind of condition. */
15707 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15708 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15709 && REG_P (XEXP (cond
, 0))
15710 && REG_P (XEXP (cond
, 1))
15711 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15712 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15714 /* SECOND mentions the rt register but not the rs register. */
15715 rtx tmp
= XEXP (cond
, 0);
15716 XEXP (cond
, 0) = XEXP (cond
, 1);
15717 XEXP (cond
, 1) = tmp
;
15722 /* Implement -mvr4130-align. Go through each basic block and simulate the
15723 processor pipeline. If we find that a pair of instructions could execute
15724 in parallel, and the first of those instructions is not 8-byte aligned,
15725 insert a nop to make it aligned. */
15728 vr4130_align_insns (void)
15730 struct mips_sim state
;
15731 rtx insn
, subinsn
, last
, last2
, next
;
15736 /* LAST is the last instruction before INSN to have a nonzero length.
15737 LAST2 is the last such instruction before LAST. */
15741 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15744 mips_sim_init (&state
, alloca (state_size ()));
15745 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15747 unsigned int length
;
15749 next
= NEXT_INSN (insn
);
15751 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15752 This isn't really related to the alignment pass, but we do it on
15753 the fly to avoid a separate instruction walk. */
15754 vr4130_avoid_branch_rt_conflict (insn
);
15756 length
= get_attr_length (insn
);
15757 if (length
> 0 && USEFUL_INSN_P (insn
))
15758 FOR_EACH_SUBINSN (subinsn
, insn
)
15760 mips_sim_wait_insn (&state
, subinsn
);
15762 /* If we want this instruction to issue in parallel with the
15763 previous one, make sure that the previous instruction is
15764 aligned. There are several reasons why this isn't worthwhile
15765 when the second instruction is a call:
15767 - Calls are less likely to be performance critical,
15768 - There's a good chance that the delay slot can execute
15769 in parallel with the call.
15770 - The return address would then be unaligned.
15772 In general, if we're going to insert a nop between instructions
15773 X and Y, it's better to insert it immediately after X. That
15774 way, if the nop makes Y aligned, it will also align any labels
15775 between X and Y. */
15776 if (state
.insns_left
!= state
.issue_rate
15777 && !CALL_P (subinsn
))
15779 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15781 /* SUBINSN is the first instruction in INSN and INSN is
15782 aligned. We want to align the previous instruction
15783 instead, so insert a nop between LAST2 and LAST.
15785 Note that LAST could be either a single instruction
15786 or a branch with a delay slot. In the latter case,
15787 LAST, like INSN, is already aligned, but the delay
15788 slot must have some extra delay that stops it from
15789 issuing at the same time as the branch. We therefore
15790 insert a nop before the branch in order to align its
15792 gcc_assert (last2
);
15793 emit_insn_after (gen_nop (), last2
);
15796 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15798 /* SUBINSN is the delay slot of INSN, but INSN is
15799 currently unaligned. Insert a nop between
15800 LAST and INSN to align it. */
15802 emit_insn_after (gen_nop (), last
);
15806 mips_sim_issue_insn (&state
, subinsn
);
15808 mips_sim_finish_insn (&state
, insn
);
15810 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15811 length
= get_attr_length (insn
);
15814 /* If the instruction is an asm statement or multi-instruction
15815 mips.md patern, the length is only an estimate. Insert an
15816 8 byte alignment after it so that the following instructions
15817 can be handled correctly. */
15818 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15819 && (recog_memoized (insn
) < 0 || length
>= 8))
15821 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15822 next
= NEXT_INSN (next
);
15823 mips_sim_next_cycle (&state
);
15826 else if (length
& 4)
15827 aligned_p
= !aligned_p
;
15832 /* See whether INSN is an aligned label. */
15833 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15839 /* This structure records that the current function has a LO_SUM
15840 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15841 the largest offset applied to BASE by all such LO_SUMs. */
15842 struct mips_lo_sum_offset
{
15844 HOST_WIDE_INT offset
;
15847 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15850 mips_hash_base (rtx base
)
15852 int do_not_record_p
;
15854 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15857 /* Hashtable helpers. */
15859 struct mips_lo_sum_offset_hasher
: typed_free_remove
<mips_lo_sum_offset
>
15861 typedef mips_lo_sum_offset value_type
;
15862 typedef rtx_def compare_type
;
15863 static inline hashval_t
hash (const value_type
*);
15864 static inline bool equal (const value_type
*, const compare_type
*);
15867 /* Hash-table callbacks for mips_lo_sum_offsets. */
15870 mips_lo_sum_offset_hasher::hash (const value_type
*entry
)
15872 return mips_hash_base (entry
->base
);
15876 mips_lo_sum_offset_hasher::equal (const value_type
*entry
,
15877 const compare_type
*value
)
15879 return rtx_equal_p (entry
->base
, value
);
15882 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
15884 /* Look up symbolic constant X in HTAB, which is a hash table of
15885 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15886 paired with a recorded LO_SUM, otherwise record X in the table. */
15889 mips_lo_sum_offset_lookup (mips_offset_table htab
, rtx x
,
15890 enum insert_option option
)
15893 mips_lo_sum_offset
**slot
;
15894 struct mips_lo_sum_offset
*entry
;
15896 /* Split X into a base and offset. */
15897 split_const (x
, &base
, &offset
);
15898 if (UNSPEC_ADDRESS_P (base
))
15899 base
= UNSPEC_ADDRESS (base
);
15901 /* Look up the base in the hash table. */
15902 slot
= htab
.find_slot_with_hash (base
, mips_hash_base (base
), option
);
15906 entry
= (struct mips_lo_sum_offset
*) *slot
;
15907 if (option
== INSERT
)
15911 entry
= XNEW (struct mips_lo_sum_offset
);
15912 entry
->base
= base
;
15913 entry
->offset
= INTVAL (offset
);
15918 if (INTVAL (offset
) > entry
->offset
)
15919 entry
->offset
= INTVAL (offset
);
15922 return INTVAL (offset
) <= entry
->offset
;
15925 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15926 Record every LO_SUM in *LOC. */
15929 mips_record_lo_sum (rtx
*loc
, void *data
)
15931 if (GET_CODE (*loc
) == LO_SUM
)
15932 mips_lo_sum_offset_lookup (*(mips_offset_table
*) data
,
15933 XEXP (*loc
, 1), INSERT
);
15937 /* Return true if INSN is a SET of an orphaned high-part relocation.
15938 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15939 LO_SUMs in the current function. */
15942 mips_orphaned_high_part_p (mips_offset_table htab
, rtx insn
)
15944 enum mips_symbol_type type
;
15947 set
= single_set (insn
);
15950 /* Check for %his. */
15952 if (GET_CODE (x
) == HIGH
15953 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
15954 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
15956 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15957 if (GET_CODE (x
) == UNSPEC
15958 && XINT (x
, 1) == UNSPEC_LOAD_GOT
15959 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
15960 SYMBOL_CONTEXT_LEA
, &type
)
15961 && type
== SYMBOL_GOTOFF_PAGE
)
15962 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
15967 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15968 INSN and a previous instruction, avoid it by inserting nops after
15971 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15972 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15973 before using the value of that register. *HILO_DELAY counts the
15974 number of instructions since the last hilo hazard (that is,
15975 the number of instructions since the last MFLO or MFHI).
15977 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15978 for the next instruction.
15980 LO_REG is an rtx for the LO register, used in dependence checking. */
15983 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
15984 rtx
*delayed_reg
, rtx lo_reg
)
15989 pattern
= PATTERN (insn
);
15991 /* Do not put the whole function in .set noreorder if it contains
15992 an asm statement. We don't know whether there will be hazards
15993 between the asm statement and the gcc-generated code. */
15994 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
15995 cfun
->machine
->all_noreorder_p
= false;
15997 /* Ignore zero-length instructions (barriers and the like). */
15998 ninsns
= get_attr_length (insn
) / 4;
16002 /* Work out how many nops are needed. Note that we only care about
16003 registers that are explicitly mentioned in the instruction's pattern.
16004 It doesn't matter that calls use the argument registers or that they
16005 clobber hi and lo. */
16006 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
16007 nops
= 2 - *hilo_delay
;
16008 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
16013 /* Insert the nops between this instruction and the previous one.
16014 Each new nop takes us further from the last hilo hazard. */
16015 *hilo_delay
+= nops
;
16017 emit_insn_after (gen_hazard_nop (), after
);
16019 /* Set up the state for the next instruction. */
16020 *hilo_delay
+= ninsns
;
16022 if (INSN_CODE (insn
) >= 0)
16023 switch (get_attr_hazard (insn
))
16033 set
= single_set (insn
);
16035 *delayed_reg
= SET_DEST (set
);
16040 /* Go through the instruction stream and insert nops where necessary.
16041 Also delete any high-part relocations whose partnering low parts
16042 are now all dead. See if the whole function can then be put into
16043 .set noreorder and .set nomacro. */
16046 mips_reorg_process_insns (void)
16048 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
16050 mips_offset_table htab
;
16052 /* Force all instructions to be split into their final form. */
16053 split_all_insns_noflow ();
16055 /* Recalculate instruction lengths without taking nops into account. */
16056 cfun
->machine
->ignore_hazard_length_p
= true;
16057 shorten_branches (get_insns ());
16059 cfun
->machine
->all_noreorder_p
= true;
16061 /* We don't track MIPS16 PC-relative offsets closely enough to make
16062 a good job of "set .noreorder" code in MIPS16 mode. */
16064 cfun
->machine
->all_noreorder_p
= false;
16066 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16067 if (!TARGET_EXPLICIT_RELOCS
)
16068 cfun
->machine
->all_noreorder_p
= false;
16070 /* Profiled functions can't be all noreorder because the profiler
16071 support uses assembler macros. */
16073 cfun
->machine
->all_noreorder_p
= false;
16075 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
16076 because we rely on the assembler to work around some errata.
16077 The r5900 too has several bugs. */
16078 if (TARGET_FIX_VR4120
|| TARGET_FIX_24K
|| TARGET_MIPS5900
)
16079 cfun
->machine
->all_noreorder_p
= false;
16081 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16082 MFHI instructions. Note that we avoid using MFLO and MFHI if
16083 the VR4130 MACC and DMACC instructions are available instead;
16084 see the *mfhilo_{si,di}_macc patterns. */
16085 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16086 cfun
->machine
->all_noreorder_p
= false;
16090 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16091 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16092 FOR_EACH_SUBINSN (subinsn
, insn
)
16093 if (USEFUL_INSN_P (subinsn
))
16094 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, &htab
);
16099 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16101 /* Make a second pass over the instructions. Delete orphaned
16102 high-part relocations or turn them into NOPs. Avoid hazards
16103 by inserting NOPs. */
16104 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16106 next_insn
= NEXT_INSN (insn
);
16107 if (USEFUL_INSN_P (insn
))
16109 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16111 /* If we find an orphaned high-part relocation in a delay
16112 slot, it's easier to turn that instruction into a NOP than
16113 to delete it. The delay slot will be a NOP either way. */
16114 FOR_EACH_SUBINSN (subinsn
, insn
)
16115 if (INSN_P (subinsn
))
16117 if (mips_orphaned_high_part_p (htab
, subinsn
))
16119 PATTERN (subinsn
) = gen_nop ();
16120 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16122 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16123 &delayed_reg
, lo_reg
);
16129 /* INSN is a single instruction. Delete it if it's an
16130 orphaned high-part relocation. */
16131 if (mips_orphaned_high_part_p (htab
, insn
))
16132 delete_insn (insn
);
16133 /* Also delete cache barriers if the last instruction
16134 was an annulled branch. INSN will not be speculatively
16136 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16138 && JUMP_P (SEQ_BEGIN (last_insn
))
16139 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16140 delete_insn (insn
);
16143 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16144 &delayed_reg
, lo_reg
);
16154 /* Return true if the function has a long branch instruction. */
16157 mips_has_long_branch_p (void)
16162 /* We need up-to-date instruction lengths. */
16163 shorten_branches (get_insns ());
16165 /* Look for a branch that is longer than normal. The normal length for
16166 non-MIPS16 branches is 8, because the length includes the delay slot.
16167 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16168 but they have no delay slot. */
16169 normal_length
= (TARGET_MIPS16
? 4 : 8);
16170 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16171 FOR_EACH_SUBINSN (subinsn
, insn
)
16172 if (JUMP_P (subinsn
)
16173 && get_attr_length (subinsn
) > normal_length
16174 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16180 /* If we are using a GOT, but have not decided to use a global pointer yet,
16181 see whether we need one to implement long branches. Convert the ghost
16182 global-pointer instructions into real ones if so. */
16185 mips_expand_ghost_gp_insns (void)
16187 /* Quick exit if we already know that we will or won't need a
16189 if (!TARGET_USE_GOT
16190 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16191 || mips_must_initialize_gp_p ())
16194 /* Run a full check for long branches. */
16195 if (!mips_has_long_branch_p ())
16198 /* We've now established that we need $gp. */
16199 cfun
->machine
->must_initialize_gp_p
= true;
16200 split_all_insns_noflow ();
16205 /* Subroutine of mips_reorg to manage passes that require DF. */
16208 mips_df_reorg (void)
16210 /* Create def-use chains. */
16211 df_set_flags (DF_EQ_NOTES
);
16212 df_chain_add_problem (DF_UD_CHAIN
);
16215 if (TARGET_RELAX_PIC_CALLS
)
16216 mips_annotate_pic_calls ();
16218 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16219 r10k_insert_cache_barriers ();
16221 df_finish_pass (false);
16224 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16225 called very late in mips_reorg, but the caller is required to run
16226 mips16_lay_out_constants on the result. */
16229 mips16_load_branch_target (rtx dest
, rtx src
)
16231 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16235 if (mips_cfun_has_cprestore_slot_p ())
16236 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16238 mips_emit_move (dest
, pic_offset_table_rtx
);
16239 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16240 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16241 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16242 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16243 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16244 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16248 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16249 mips_emit_move (dest
, src
);
16253 /* If we're compiling a MIPS16 function, look for and split any long branches.
16254 This must be called after all other instruction modifications in
16258 mips16_split_long_branches (void)
16260 bool something_changed
;
16262 if (!TARGET_MIPS16
)
16265 /* Loop until the alignments for all targets are sufficient. */
16270 shorten_branches (get_insns ());
16271 something_changed
= false;
16272 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16274 && get_attr_length (insn
) > 4
16275 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16277 rtx old_label
, new_label
, temp
, saved_temp
;
16278 rtx target
, jump
, jump_sequence
;
16282 /* Free up a MIPS16 register by saving it in $1. */
16283 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16284 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16285 emit_move_insn (saved_temp
, temp
);
16287 /* Load the branch target into TEMP. */
16288 old_label
= JUMP_LABEL (insn
);
16289 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16290 mips16_load_branch_target (temp
, target
);
16292 /* Jump to the target and restore the register's
16294 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16295 (temp
, temp
, saved_temp
)));
16296 JUMP_LABEL (jump
) = old_label
;
16297 LABEL_NUSES (old_label
)++;
16299 /* Rewrite any symbolic references that are supposed to use
16300 a PC-relative constant pool. */
16301 mips16_lay_out_constants (false);
16303 if (simplejump_p (insn
))
16304 /* We're going to replace INSN with a longer form. */
16305 new_label
= NULL_RTX
;
16308 /* Create a branch-around label for the original
16310 new_label
= gen_label_rtx ();
16311 emit_label (new_label
);
16314 jump_sequence
= get_insns ();
16317 emit_insn_after (jump_sequence
, insn
);
16319 invert_jump (insn
, new_label
, false);
16321 delete_insn (insn
);
16322 something_changed
= true;
16325 while (something_changed
);
16328 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16333 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16334 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16335 to date if the CFG is available. */
16336 if (mips_cfg_in_reorg ())
16337 compute_bb_for_insn ();
16338 mips16_lay_out_constants (true);
16339 if (mips_cfg_in_reorg ())
16342 free_bb_for_insn ();
16346 /* We use a machine specific pass to do a second machine dependent reorg
16347 pass after delay branch scheduling. */
16349 static unsigned int
16350 mips_machine_reorg2 (void)
16352 mips_reorg_process_insns ();
16354 && TARGET_EXPLICIT_RELOCS
16356 && TARGET_VR4130_ALIGN
)
16357 vr4130_align_insns ();
16358 if (mips_expand_ghost_gp_insns ())
16359 /* The expansion could invalidate some of the VR4130 alignment
16360 optimizations, but this should be an extremely rare case anyhow. */
16361 mips_reorg_process_insns ();
16362 mips16_split_long_branches ();
16368 const pass_data pass_data_mips_machine_reorg2
=
16370 RTL_PASS
, /* type */
16371 "mach2", /* name */
16372 OPTGROUP_NONE
, /* optinfo_flags */
16373 false, /* has_gate */
16374 true, /* has_execute */
16375 TV_MACH_DEP
, /* tv_id */
16376 0, /* properties_required */
16377 0, /* properties_provided */
16378 0, /* properties_destroyed */
16379 0, /* todo_flags_start */
16380 TODO_verify_rtl_sharing
, /* todo_flags_finish */
16383 class pass_mips_machine_reorg2
: public rtl_opt_pass
16386 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16387 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16390 /* opt_pass methods: */
16391 unsigned int execute () { return mips_machine_reorg2 (); }
16393 }; // class pass_mips_machine_reorg2
16395 } // anon namespace
16398 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16400 return new pass_mips_machine_reorg2 (ctxt
);
16404 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16405 in order to avoid duplicating too much logic from elsewhere. */
16408 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16409 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16412 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
16413 bool use_sibcall_p
;
16415 /* Pretend to be a post-reload pass while generating rtl. */
16416 reload_completed
= 1;
16418 /* Mark the end of the (empty) prologue. */
16419 emit_note (NOTE_INSN_PROLOGUE_END
);
16421 /* Determine if we can use a sibcall to call FUNCTION directly. */
16422 fnaddr
= XEXP (DECL_RTL (function
), 0);
16423 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16424 && const_call_insn_operand (fnaddr
, Pmode
));
16426 /* Determine if we need to load FNADDR from the GOT. */
16428 && (mips_got_symbol_type_p
16429 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16431 /* Pick a global pointer. Use a call-clobbered register if
16432 TARGET_CALL_SAVED_GP. */
16433 cfun
->machine
->global_pointer
16434 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16435 cfun
->machine
->must_initialize_gp_p
= true;
16436 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16438 /* Set up the global pointer for n32 or n64 abicalls. */
16439 mips_emit_loadgp ();
16442 /* We need two temporary registers in some cases. */
16443 temp1
= gen_rtx_REG (Pmode
, 2);
16444 temp2
= gen_rtx_REG (Pmode
, 3);
16446 /* Find out which register contains the "this" pointer. */
16447 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16448 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16450 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16452 /* Add DELTA to THIS_RTX. */
16455 rtx offset
= GEN_INT (delta
);
16456 if (!SMALL_OPERAND (delta
))
16458 mips_emit_move (temp1
, offset
);
16461 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16464 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16465 if (vcall_offset
!= 0)
16469 /* Set TEMP1 to *THIS_RTX. */
16470 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16472 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16473 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16475 /* Load the offset and add it to THIS_RTX. */
16476 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16477 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16480 /* Jump to the target function. Use a sibcall if direct jumps are
16481 allowed, otherwise load the address into a register first. */
16484 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16485 SIBLING_CALL_P (insn
) = 1;
16489 /* This is messy. GAS treats "la $25,foo" as part of a call
16490 sequence and may allow a global "foo" to be lazily bound.
16491 The general move patterns therefore reject this combination.
16493 In this context, lazy binding would actually be OK
16494 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16495 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16496 We must therefore load the address via a temporary
16497 register if mips_dangerous_for_la25_p.
16499 If we jump to the temporary register rather than $25,
16500 the assembler can use the move insn to fill the jump's
16503 We can use the same technique for MIPS16 code, where $25
16504 is not a valid JR register. */
16505 if (TARGET_USE_PIC_FN_ADDR_REG
16507 && !mips_dangerous_for_la25_p (fnaddr
))
16508 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16509 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16511 if (TARGET_USE_PIC_FN_ADDR_REG
16512 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16513 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16514 emit_jump_insn (gen_indirect_jump (temp1
));
16517 /* Run just enough of rest_of_compilation. This sequence was
16518 "borrowed" from alpha.c. */
16519 insn
= get_insns ();
16520 split_all_insns_noflow ();
16521 mips16_lay_out_constants (true);
16522 shorten_branches (insn
);
16523 final_start_function (insn
, file
, 1);
16524 final (insn
, file
, 1);
16525 final_end_function ();
16527 /* Clean up the vars set above. Note that final_end_function resets
16528 the global pointer for us. */
16529 reload_completed
= 0;
16533 /* The last argument passed to mips_set_compression_mode,
16534 or negative if the function hasn't been called yet. */
16535 static unsigned int old_compression_mode
= -1;
16537 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16538 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16541 mips_set_compression_mode (unsigned int compression_mode
)
16544 if (compression_mode
== old_compression_mode
)
16547 /* Restore base settings of various flags. */
16548 target_flags
= mips_base_target_flags
;
16549 flag_schedule_insns
= mips_base_schedule_insns
;
16550 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16551 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16552 align_loops
= mips_base_align_loops
;
16553 align_jumps
= mips_base_align_jumps
;
16554 align_functions
= mips_base_align_functions
;
16555 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
16556 target_flags
|= compression_mode
;
16558 if (compression_mode
& MASK_MIPS16
)
16560 /* Switch to MIPS16 mode. */
16561 target_flags
|= MASK_MIPS16
;
16563 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16564 target_flags
&= ~MASK_SYNCI
;
16566 /* Don't run the scheduler before reload, since it tends to
16567 increase register pressure. */
16568 flag_schedule_insns
= 0;
16570 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16571 the whole function to be in a single section. */
16572 flag_reorder_blocks_and_partition
= 0;
16574 /* Don't move loop invariants, because it tends to increase
16575 register pressure. It also introduces an extra move in cases
16576 where the constant is the first operand in a two-operand binary
16577 instruction, or when it forms a register argument to a functon
16579 flag_move_loop_invariants
= 0;
16581 target_flags
|= MASK_EXPLICIT_RELOCS
;
16583 /* Experiments suggest we get the best overall section-anchor
16584 results from using the range of an unextended LW or SW. Code
16585 that makes heavy use of byte or short accesses can do better
16586 with ranges of 0...31 and 0...63 respectively, but most code is
16587 sensitive to the range of LW and SW instead. */
16588 targetm
.min_anchor_offset
= 0;
16589 targetm
.max_anchor_offset
= 127;
16591 targetm
.const_anchor
= 0;
16593 /* MIPS16 has no BAL instruction. */
16594 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16596 /* The R4000 errata don't apply to any known MIPS16 cores.
16597 It's simpler to make the R4000 fixes and MIPS16 mode
16598 mutually exclusive. */
16599 target_flags
&= ~MASK_FIX_R4000
;
16601 if (flag_pic
&& !TARGET_OLDABI
)
16602 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16605 sorry ("MIPS16 -mxgot code");
16607 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16608 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16612 /* Switch to microMIPS or the standard encoding. */
16614 if (TARGET_MICROMIPS
)
16615 /* Avoid branch likely. */
16616 target_flags
&= ~MASK_BRANCHLIKELY
;
16618 /* Provide default values for align_* for 64-bit targets. */
16621 if (align_loops
== 0)
16623 if (align_jumps
== 0)
16625 if (align_functions
== 0)
16626 align_functions
= 8;
16629 targetm
.min_anchor_offset
= -32768;
16630 targetm
.max_anchor_offset
= 32767;
16632 targetm
.const_anchor
= 0x8000;
16635 /* (Re)initialize MIPS target internals for new ISA. */
16636 mips_init_relocs ();
16638 if (compression_mode
& MASK_MIPS16
)
16640 if (!mips16_globals
)
16641 mips16_globals
= save_target_globals_default_opts ();
16643 restore_target_globals (mips16_globals
);
16646 restore_target_globals (&default_target_globals
);
16648 old_compression_mode
= compression_mode
;
16651 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16652 function should use the MIPS16 or microMIPS ISA and switch modes
16656 mips_set_current_function (tree fndecl
)
16658 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
16661 /* Allocate a chunk of memory for per-function machine-dependent data. */
16663 static struct machine_function
*
16664 mips_init_machine_status (void)
16666 return ggc_alloc_cleared_machine_function ();
16669 /* Return the processor associated with the given ISA level, or null
16670 if the ISA isn't valid. */
16672 static const struct mips_cpu_info
*
16673 mips_cpu_info_from_isa (int isa
)
16677 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16678 if (mips_cpu_info_table
[i
].isa
== isa
)
16679 return mips_cpu_info_table
+ i
;
16684 /* Return a mips_cpu_info entry determined by an option valued
16687 static const struct mips_cpu_info
*
16688 mips_cpu_info_from_opt (int opt
)
16692 case MIPS_ARCH_OPTION_FROM_ABI
:
16693 /* 'from-abi' selects the most compatible architecture for the
16694 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16695 ABIs. For the EABIs, we have to decide whether we're using
16696 the 32-bit or 64-bit version. */
16697 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16698 : ABI_NEEDS_64BIT_REGS
? 3
16699 : (TARGET_64BIT
? 3 : 1));
16701 case MIPS_ARCH_OPTION_NATIVE
:
16702 gcc_unreachable ();
16705 return &mips_cpu_info_table
[opt
];
16709 /* Return a default mips_cpu_info entry, given that no -march= option
16710 was explicitly specified. */
16712 static const struct mips_cpu_info
*
16713 mips_default_arch (void)
16715 #if defined (MIPS_CPU_STRING_DEFAULT)
16717 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16718 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16719 return mips_cpu_info_table
+ i
;
16720 gcc_unreachable ();
16721 #elif defined (MIPS_ISA_DEFAULT)
16722 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16724 /* 'from-abi' makes a good default: you get whatever the ABI
16726 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16730 /* Set up globals to generate code for the ISA or processor
16731 described by INFO. */
16734 mips_set_architecture (const struct mips_cpu_info
*info
)
16738 mips_arch_info
= info
;
16739 mips_arch
= info
->cpu
;
16740 mips_isa
= info
->isa
;
16744 /* Likewise for tuning. */
16747 mips_set_tune (const struct mips_cpu_info
*info
)
16751 mips_tune_info
= info
;
16752 mips_tune
= info
->cpu
;
16756 /* Implement TARGET_OPTION_OVERRIDE. */
16759 mips_option_override (void)
16761 int i
, start
, regno
, mode
;
16763 if (global_options_set
.x_mips_isa_option
)
16764 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16766 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16767 SUBTARGET_OVERRIDE_OPTIONS
;
16770 /* MIPS16 and microMIPS cannot coexist. */
16771 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
16772 error ("unsupported combination: %s", "-mips16 -mmicromips");
16774 /* Save the base compression state and process flags as though we
16775 were generating uncompressed code. */
16776 mips_base_compression_flags
= TARGET_COMPRESSION
;
16777 target_flags
&= ~TARGET_COMPRESSION
;
16779 /* -mno-float overrides -mhard-float and -msoft-float. */
16780 if (TARGET_NO_FLOAT
)
16782 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16783 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16786 if (TARGET_FLIP_MIPS16
)
16787 TARGET_INTERLINK_COMPRESSED
= 1;
16789 /* Set the small data limit. */
16790 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16792 : MIPS_DEFAULT_GVALUE
);
16794 /* The following code determines the architecture and register size.
16795 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16796 The GAS and GCC code should be kept in sync as much as possible. */
16798 if (global_options_set
.x_mips_arch_option
)
16799 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16801 if (mips_isa_option_info
!= 0)
16803 if (mips_arch_info
== 0)
16804 mips_set_architecture (mips_isa_option_info
);
16805 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16806 error ("%<-%s%> conflicts with the other architecture options, "
16807 "which specify a %s processor",
16808 mips_isa_option_info
->name
,
16809 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16812 if (mips_arch_info
== 0)
16813 mips_set_architecture (mips_default_arch ());
16815 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16816 error ("%<-march=%s%> is not compatible with the selected ABI",
16817 mips_arch_info
->name
);
16819 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16820 if (global_options_set
.x_mips_tune_option
)
16821 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16823 if (mips_tune_info
== 0)
16824 mips_set_tune (mips_arch_info
);
16826 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16828 /* The user specified the size of the integer registers. Make sure
16829 it agrees with the ABI and ISA. */
16830 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16831 error ("%<-mgp64%> used with a 32-bit processor");
16832 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16833 error ("%<-mgp32%> used with a 64-bit ABI");
16834 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16835 error ("%<-mgp64%> used with a 32-bit ABI");
16839 /* Infer the integer register size from the ABI and processor.
16840 Restrict ourselves to 32-bit registers if that's all the
16841 processor has, or if the ABI cannot handle 64-bit registers. */
16842 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16843 target_flags
&= ~MASK_64BIT
;
16845 target_flags
|= MASK_64BIT
;
16848 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16850 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16851 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16852 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
16853 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16854 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
16856 if (!ISA_HAS_MXHC1
)
16857 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16858 " the target supports the mfhc1 and mthc1 instructions");
16859 else if (mips_abi
!= ABI_32
)
16860 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16866 /* -msingle-float selects 32-bit float registers. Otherwise the
16867 float registers should be the same size as the integer ones. */
16868 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
16869 target_flags
|= MASK_FLOAT64
;
16871 target_flags
&= ~MASK_FLOAT64
;
16874 /* End of code shared with GAS. */
16876 /* The R5900 FPU only supports single precision. */
16877 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
16878 error ("unsupported combination: %s",
16879 "-march=r5900 -mhard-float -mdouble-float");
16881 /* If a -mlong* option was given, check that it matches the ABI,
16882 otherwise infer the -mlong* setting from the other options. */
16883 if ((target_flags_explicit
& MASK_LONG64
) != 0)
16887 if (mips_abi
== ABI_N32
)
16888 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16889 else if (mips_abi
== ABI_32
)
16890 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16891 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
16892 /* We have traditionally allowed non-abicalls code to use
16893 an LP64 form of o64. However, it would take a bit more
16894 effort to support the combination of 32-bit GOT entries
16895 and 64-bit pointers, so we treat the abicalls case as
16897 error ("the combination of %qs and %qs is incompatible with %qs",
16898 "-mabi=o64", "-mabicalls", "-mlong64");
16902 if (mips_abi
== ABI_64
)
16903 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16908 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
16909 target_flags
|= MASK_LONG64
;
16911 target_flags
&= ~MASK_LONG64
;
16914 if (!TARGET_OLDABI
)
16915 flag_pcc_struct_return
= 0;
16917 /* Decide which rtx_costs structure to use. */
16919 mips_cost
= &mips_rtx_cost_optimize_size
;
16921 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
16923 /* If the user hasn't specified a branch cost, use the processor's
16925 if (mips_branch_cost
== 0)
16926 mips_branch_cost
= mips_cost
->branch_cost
;
16928 /* If neither -mbranch-likely nor -mno-branch-likely was given
16929 on the command line, set MASK_BRANCHLIKELY based on the target
16930 architecture and tuning flags. Annulled delay slots are a
16931 size win, so we only consider the processor-specific tuning
16932 for !optimize_size. */
16933 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
16935 if (ISA_HAS_BRANCHLIKELY
16937 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
16938 target_flags
|= MASK_BRANCHLIKELY
;
16940 target_flags
&= ~MASK_BRANCHLIKELY
;
16942 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
16943 warning (0, "the %qs architecture does not support branch-likely"
16944 " instructions", mips_arch_info
->name
);
16946 /* If the user hasn't specified -mimadd or -mno-imadd set
16947 MASK_IMADD based on the target architecture and tuning
16949 if ((target_flags_explicit
& MASK_IMADD
) == 0)
16951 if (ISA_HAS_MADD_MSUB
&&
16952 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
16953 target_flags
|= MASK_IMADD
;
16955 target_flags
&= ~MASK_IMADD
;
16957 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
16958 warning (0, "the %qs architecture does not support madd or msub"
16959 " instructions", mips_arch_info
->name
);
16961 /* The effect of -mabicalls isn't defined for the EABI. */
16962 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
16964 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16965 target_flags
&= ~MASK_ABICALLS
;
16968 /* PIC requires -mabicalls. */
16971 if (mips_abi
== ABI_EABI
)
16972 error ("cannot generate position-independent code for %qs",
16974 else if (!TARGET_ABICALLS
)
16975 error ("position-independent code requires %qs", "-mabicalls");
16978 if (TARGET_ABICALLS_PIC2
)
16979 /* We need to set flag_pic for executables as well as DSOs
16980 because we may reference symbols that are not defined in
16981 the final executable. (MIPS does not use things like
16982 copy relocs, for example.)
16984 There is a body of code that uses __PIC__ to distinguish
16985 between -mabicalls and -mno-abicalls code. The non-__PIC__
16986 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16987 long as any indirect jumps use $25. */
16990 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16991 faster code, but at the expense of more nops. Enable it at -O3 and
16993 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
16994 target_flags
|= MASK_VR4130_ALIGN
;
16996 /* Prefer a call to memcpy over inline code when optimizing for size,
16997 though see MOVE_RATIO in mips.h. */
16998 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
16999 target_flags
|= MASK_MEMCPY
;
17001 /* If we have a nonzero small-data limit, check that the -mgpopt
17002 setting is consistent with the other target flags. */
17003 if (mips_small_data_threshold
> 0)
17007 if (!TARGET_EXPLICIT_RELOCS
)
17008 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17010 TARGET_LOCAL_SDATA
= false;
17011 TARGET_EXTERN_SDATA
= false;
17015 if (TARGET_VXWORKS_RTP
)
17016 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17018 if (TARGET_ABICALLS
)
17019 warning (0, "cannot use small-data accesses for %qs",
17024 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17025 for all its floating point. */
17026 if (mips_nan
!= MIPS_IEEE_754_2008
)
17028 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17029 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17030 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17033 /* Make sure that the user didn't turn off paired single support when
17034 MIPS-3D support is requested. */
17036 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17037 && !TARGET_PAIRED_SINGLE_FLOAT
)
17038 error ("%<-mips3d%> requires %<-mpaired-single%>");
17040 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17042 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17044 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17045 and TARGET_HARD_FLOAT_ABI are both true. */
17046 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17047 error ("%qs must be used with %qs",
17048 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17049 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17051 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
17053 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17054 warning (0, "the %qs architecture does not support paired-single"
17055 " instructions", mips_arch_info
->name
);
17057 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17058 && !TARGET_CACHE_BUILTIN
)
17060 error ("%qs requires a target that provides the %qs instruction",
17061 "-mr10k-cache-barrier", "cache");
17062 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17065 /* If TARGET_DSPR2, enable MASK_DSP. */
17067 target_flags
|= MASK_DSP
;
17069 /* .eh_frame addresses should be the same width as a C pointer.
17070 Most MIPS ABIs support only one pointer size, so the assembler
17071 will usually know exactly how big an .eh_frame address is.
17073 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17074 originally defined to use 64-bit pointers (i.e. it is LP64), and
17075 this is still the default mode. However, we also support an n32-like
17076 ILP32 mode, which is selected by -mlong32. The problem is that the
17077 assembler has traditionally not had an -mlong option, so it has
17078 traditionally not known whether we're using the ILP32 or LP64 form.
17080 As it happens, gas versions up to and including 2.19 use _32-bit_
17081 addresses for EABI64 .cfi_* directives. This is wrong for the
17082 default LP64 mode, so we can't use the directives by default.
17083 Moreover, since gas's current behavior is at odds with gcc's
17084 default behavior, it seems unwise to rely on future versions
17085 of gas behaving the same way. We therefore avoid using .cfi
17086 directives for -mlong32 as well. */
17087 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17088 flag_dwarf2_cfi_asm
= 0;
17090 /* .cfi_* directives generate a read-only section, so fall back on
17091 manual .eh_frame creation if we need the section to be writable. */
17092 if (TARGET_WRITABLE_EH_FRAME
)
17093 flag_dwarf2_cfi_asm
= 0;
17095 mips_init_print_operand_punct ();
17097 /* Set up array to map GCC register number to debug register number.
17098 Ignore the special purpose register numbers. */
17100 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17102 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17103 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17104 mips_dwarf_regno
[i
] = i
;
17106 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17109 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17110 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17111 mips_dbx_regno
[i
] = i
+ start
;
17113 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17114 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17115 mips_dbx_regno
[i
] = i
+ start
;
17117 /* Accumulator debug registers use big-endian ordering. */
17118 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17119 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17120 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17121 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17122 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17124 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17125 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17128 /* Set up mips_hard_regno_mode_ok. */
17129 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17130 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17131 mips_hard_regno_mode_ok
[mode
][regno
]
17132 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
17134 /* Function to allocate machine-dependent function status. */
17135 init_machine_status
= &mips_init_machine_status
;
17137 /* Default to working around R4000 errata only if the processor
17138 was selected explicitly. */
17139 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17140 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17141 target_flags
|= MASK_FIX_R4000
;
17143 /* Default to working around R4400 errata only if the processor
17144 was selected explicitly. */
17145 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17146 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17147 target_flags
|= MASK_FIX_R4400
;
17149 /* Default to working around R10000 errata only if the processor
17150 was selected explicitly. */
17151 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17152 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17153 target_flags
|= MASK_FIX_R10000
;
17155 /* Make sure that branch-likely instructions available when using
17156 -mfix-r10000. The instructions are not available if either:
17158 1. -mno-branch-likely was passed.
17159 2. The selected ISA does not support branch-likely and
17160 the command line does not include -mbranch-likely. */
17161 if (TARGET_FIX_R10000
17162 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17163 ? !ISA_HAS_BRANCHLIKELY
17164 : !TARGET_BRANCHLIKELY
))
17165 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17167 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17169 warning (0, "the %qs architecture does not support the synci "
17170 "instruction", mips_arch_info
->name
);
17171 target_flags
&= ~MASK_SYNCI
;
17174 /* Only optimize PIC indirect calls if they are actually required. */
17175 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17176 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17178 /* Save base state of options. */
17179 mips_base_target_flags
= target_flags
;
17180 mips_base_schedule_insns
= flag_schedule_insns
;
17181 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17182 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17183 mips_base_align_loops
= align_loops
;
17184 mips_base_align_jumps
= align_jumps
;
17185 mips_base_align_functions
= align_functions
;
17187 /* Now select the ISA mode.
17189 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17190 later if required. */
17191 mips_set_compression_mode (0);
17193 /* We register a second machine specific reorg pass after delay slot
17194 filling. Registering the pass must be done at start up. It's
17195 convenient to do it here. */
17196 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17197 struct register_pass_info insert_pass_mips_machine_reorg2
=
17199 new_pass
, /* pass */
17200 "dbr", /* reference_pass_name */
17201 1, /* ref_pass_instance_number */
17202 PASS_POS_INSERT_AFTER
/* po_op */
17204 register_pass (&insert_pass_mips_machine_reorg2
);
17206 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17207 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17210 /* Swap the register information for registers I and I + 1, which
17211 currently have the wrong endianness. Note that the registers'
17212 fixedness and call-clobberedness might have been set on the
17216 mips_swap_registers (unsigned int i
)
17221 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17222 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17224 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17225 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17226 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17227 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17233 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17236 mips_conditional_register_usage (void)
17241 /* These DSP control register fields are global. */
17242 global_regs
[CCDSP_PO_REGNUM
] = 1;
17243 global_regs
[CCDSP_SC_REGNUM
] = 1;
17246 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17247 reg_class_contents
[(int) DSP_ACC_REGS
]);
17249 if (!TARGET_HARD_FLOAT
)
17251 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17252 reg_class_contents
[(int) FP_REGS
]);
17253 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17254 reg_class_contents
[(int) ST_REGS
]);
17256 else if (!ISA_HAS_8CC
)
17258 /* We only have a single condition-code register. We implement
17259 this by fixing all the condition-code registers and generating
17260 RTL that refers directly to ST_REG_FIRST. */
17261 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17262 reg_class_contents
[(int) ST_REGS
]);
17263 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17264 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17268 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17269 are call-saved, and saving them via a MIPS16 register would
17270 probably waste more time than just reloading the value.
17272 We permit the $t temporary registers when optimizing for speed
17273 but not when optimizing for space because using them results in
17274 code that is larger (but faster) then not using them. We do
17275 allow $24 (t8) because it is used in CMP and CMPI instructions
17276 and $25 (t9) because it is used as the function call address in
17279 fixed_regs
[18] = call_used_regs
[18] = 1;
17280 fixed_regs
[19] = call_used_regs
[19] = 1;
17281 fixed_regs
[20] = call_used_regs
[20] = 1;
17282 fixed_regs
[21] = call_used_regs
[21] = 1;
17283 fixed_regs
[22] = call_used_regs
[22] = 1;
17284 fixed_regs
[23] = call_used_regs
[23] = 1;
17285 fixed_regs
[26] = call_used_regs
[26] = 1;
17286 fixed_regs
[27] = call_used_regs
[27] = 1;
17287 fixed_regs
[30] = call_used_regs
[30] = 1;
17290 fixed_regs
[8] = call_used_regs
[8] = 1;
17291 fixed_regs
[9] = call_used_regs
[9] = 1;
17292 fixed_regs
[10] = call_used_regs
[10] = 1;
17293 fixed_regs
[11] = call_used_regs
[11] = 1;
17294 fixed_regs
[12] = call_used_regs
[12] = 1;
17295 fixed_regs
[13] = call_used_regs
[13] = 1;
17296 fixed_regs
[14] = call_used_regs
[14] = 1;
17297 fixed_regs
[15] = call_used_regs
[15] = 1;
17300 /* Do not allow HI and LO to be treated as register operands.
17301 There are no MTHI or MTLO instructions (or any real need
17302 for them) and one-way registers cannot easily be reloaded. */
17303 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17304 reg_class_contents
[(int) MD_REGS
]);
17306 /* $f20-$f23 are call-clobbered for n64. */
17307 if (mips_abi
== ABI_64
)
17310 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17311 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17313 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17315 if (mips_abi
== ABI_N32
)
17318 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17319 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17321 /* Make sure that double-register accumulator values are correctly
17322 ordered for the current endianness. */
17323 if (TARGET_LITTLE_ENDIAN
)
17325 unsigned int regno
;
17327 mips_swap_registers (MD_REG_FIRST
);
17328 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17329 mips_swap_registers (regno
);
17333 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
17334 other registers for instructions for which it is possible. This
17335 encourages the compiler to use CMP in cases where an XOR would
17336 require some register shuffling. */
17339 mips_order_regs_for_local_alloc (void)
17343 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17344 reg_alloc_order
[i
] = i
;
17348 /* It really doesn't matter where we put register 0, since it is
17349 a fixed register anyhow. */
17350 reg_alloc_order
[0] = 24;
17351 reg_alloc_order
[24] = 0;
17355 /* Implement EH_USES. */
17358 mips_eh_uses (unsigned int regno
)
17360 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17362 /* We need to force certain registers to be live in order to handle
17363 PIC long branches correctly. See mips_must_initialize_gp_p for
17365 if (mips_cfun_has_cprestore_slot_p ())
17367 if (regno
== CPRESTORE_SLOT_REGNUM
)
17372 if (cfun
->machine
->global_pointer
== regno
)
17380 /* Implement EPILOGUE_USES. */
17383 mips_epilogue_uses (unsigned int regno
)
17385 /* Say that the epilogue uses the return address register. Note that
17386 in the case of sibcalls, the values "used by the epilogue" are
17387 considered live at the start of the called function. */
17388 if (regno
== RETURN_ADDR_REGNUM
)
17391 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17392 See the comment above load_call<mode> for details. */
17393 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17396 /* An interrupt handler must preserve some registers that are
17397 ordinarily call-clobbered. */
17398 if (cfun
->machine
->interrupt_handler_p
17399 && mips_interrupt_extra_call_saved_reg_p (regno
))
17405 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17408 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
17410 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
17413 /* Return true if INSN needs to be wrapped in ".set noat".
17414 INSN has NOPERANDS operands, stored in OPVEC. */
17417 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
17421 if (recog_memoized (insn
) >= 0)
17422 for (i
= 0; i
< noperands
; i
++)
17423 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
17428 /* Implement FINAL_PRESCAN_INSN. */
17431 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
17433 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17434 mips_push_asm_switch (&mips_noat
);
17437 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17440 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
17441 rtx
*opvec
, int noperands
)
17443 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17444 mips_pop_asm_switch (&mips_noat
);
17447 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17448 EXT_CODE is the code of the extension used. Return NULL if widening
17449 multiplication shouldn't be used. */
17452 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17456 signed_p
= ext_code
== SIGN_EXTEND
;
17459 /* Don't use widening multiplication with MULT when we have DMUL. Even
17460 with the extension of its input operands DMUL is faster. Note that
17461 the extension is not needed for signed multiplication. In order to
17462 ensure that we always remove the redundant sign-extension in this
17463 case we still expand mulsidi3 for DMUL. */
17465 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17468 ? gen_mulsidi3_64bit_mips16
17469 : gen_umulsidi3_64bit_mips16
);
17470 if (TARGET_FIX_R4000
)
17472 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17478 ? gen_mulsidi3_32bit_mips16
17479 : gen_umulsidi3_32bit_mips16
);
17480 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17481 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17482 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17486 /* Return true if PATTERN matches the kind of instruction generated by
17487 umips_build_save_restore. SAVE_P is true for store. */
17490 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
17494 HOST_WIDE_INT first_offset
= 0;
17495 rtx first_base
= 0;
17496 unsigned int regmask
= 0;
17498 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
17500 rtx set
, reg
, mem
, this_base
;
17501 HOST_WIDE_INT this_offset
;
17503 /* Check that we have a SET. */
17504 set
= XVECEXP (pattern
, 0, n
);
17505 if (GET_CODE (set
) != SET
)
17508 /* Check that the SET is a load (if restoring) or a store
17510 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17511 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
17514 /* Check that the address is the sum of base and a possibly-zero
17515 constant offset. Determine if the offset is in range. */
17516 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
17517 if (!REG_P (this_base
))
17522 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
17524 first_base
= this_base
;
17525 first_offset
= this_offset
;
17529 /* Check that the save slots are consecutive. */
17530 if (REGNO (this_base
) != REGNO (first_base
)
17531 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
17535 /* Check that SET's other operand is a register. */
17536 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
17540 regmask
|= 1 << REGNO (reg
);
17543 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
17544 if (regmask
== umips_swm_mask
[i
])
17550 /* Return the assembly instruction for microMIPS LWM or SWM.
17551 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17554 umips_output_save_restore (bool save_p
, rtx pattern
)
17556 static char buffer
[300];
17559 HOST_WIDE_INT offset
;
17560 rtx base
, mem
, set
, last_set
, last_reg
;
17562 /* Parse the pattern. */
17563 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
17565 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
17567 n
= XVECLEN (pattern
, 0);
17569 set
= XVECEXP (pattern
, 0, 0);
17570 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
17571 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
17573 last_set
= XVECEXP (pattern
, 0, n
- 1);
17574 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
17576 if (REGNO (last_reg
) == 31)
17579 gcc_assert (n
<= 9);
17583 s
+= sprintf (s
, "%s,", reg_names
[16]);
17585 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
17587 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
17590 if (REGNO (last_reg
) == 31)
17591 s
+= sprintf (s
, "%s,", reg_names
[31]);
17593 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
17597 /* Return true if MEM1 and MEM2 use the same base register, and the
17598 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17599 register into (from) which the contents of MEM1 will be loaded
17600 (stored), depending on the value of LOAD_P.
17601 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17604 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
17605 rtx first_reg
, rtx mem1
, rtx mem2
)
17608 HOST_WIDE_INT offset1
, offset2
;
17610 if (!MEM_P (mem1
) || !MEM_P (mem2
))
17613 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
17614 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
17616 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
17619 /* Avoid invalid load pair instructions. */
17620 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
17623 /* We must avoid this case for anti-dependence.
17626 first_reg is $2, but the base is $3. */
17629 && REGNO (first_reg
) + 1 == REGNO (base1
))
17632 if (offset2
!= offset1
+ 4)
17635 if (!UMIPS_12BIT_OFFSET_P (offset1
))
17641 /* OPERANDS describes the operands to a pair of SETs, in the order
17642 dest1, src1, dest2, src2. Return true if the operands can be used
17643 in an LWP or SWP instruction; LOAD_P says which. */
17646 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
17648 rtx reg1
, reg2
, mem1
, mem2
;
17652 reg1
= operands
[0];
17653 reg2
= operands
[2];
17654 mem1
= operands
[1];
17655 mem2
= operands
[3];
17659 reg1
= operands
[1];
17660 reg2
= operands
[3];
17661 mem1
= operands
[0];
17662 mem2
= operands
[2];
17665 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17666 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
17668 if (REGNO (reg1
) == REGNO (reg2
) + 1)
17669 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
17674 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17675 the first register is REG and the first memory slot is MEM.
17676 LOAD_P is true for LWP. */
17679 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
17681 rtx ops
[] = {reg
, mem
};
17684 output_asm_insn ("lwp\t%0,%1", ops
);
17686 output_asm_insn ("swp\t%0,%1", ops
);
17689 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17690 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17693 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
17695 rtx reg1
, reg2
, mem1
, mem2
;
17698 reg1
= operands
[0];
17699 reg2
= operands
[2];
17700 mem1
= operands
[1];
17701 mem2
= operands
[3];
17705 reg1
= operands
[1];
17706 reg2
= operands
[3];
17707 mem1
= operands
[0];
17708 mem2
= operands
[2];
17711 if (REGNO (reg2
) == REGNO (reg1
) + 1)
17713 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
17717 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
17718 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
17721 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17724 umips_movep_target_p (rtx reg1
, rtx reg2
)
17726 int regno1
, regno2
, pair
;
17728 static const int match
[8] = {
17729 0x00000060, /* 5, 6 */
17730 0x000000a0, /* 5, 7 */
17731 0x000000c0, /* 6, 7 */
17732 0x00200010, /* 4, 21 */
17733 0x00400010, /* 4, 22 */
17734 0x00000030, /* 4, 5 */
17735 0x00000050, /* 4, 6 */
17736 0x00000090 /* 4, 7 */
17739 if (!REG_P (reg1
) || !REG_P (reg2
))
17742 regno1
= REGNO (reg1
);
17743 regno2
= REGNO (reg2
);
17745 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
17748 pair
= (1 << regno1
) | (1 << regno2
);
17750 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
17751 if (pair
== match
[i
])
17757 /* Return the size in bytes of the trampoline code, padded to
17758 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17759 function address immediately follow. */
17762 mips_trampoline_code_size (void)
17764 if (TARGET_USE_PIC_FN_ADDR_REG
)
17766 else if (ptr_mode
== DImode
)
17768 else if (ISA_HAS_LOAD_DELAY
)
17774 /* Implement TARGET_TRAMPOLINE_INIT. */
17777 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
17779 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
17782 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
17784 /* Work out the offsets of the pointers from the start of the
17785 trampoline code. */
17786 end_addr_offset
= mips_trampoline_code_size ();
17787 static_chain_offset
= end_addr_offset
;
17788 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
17790 /* Get pointers to the beginning and end of the code block. */
17791 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
17792 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
17794 #define OP(X) gen_int_mode (X, SImode)
17796 /* Build up the code in TRAMPOLINE. */
17798 if (TARGET_USE_PIC_FN_ADDR_REG
)
17800 /* $25 contains the address of the trampoline. Emit code of the form:
17802 l[wd] $1, target_function_offset($25)
17803 l[wd] $static_chain, static_chain_offset($25)
17806 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
17807 target_function_offset
,
17808 PIC_FUNCTION_ADDR_REGNUM
));
17809 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17810 static_chain_offset
,
17811 PIC_FUNCTION_ADDR_REGNUM
));
17812 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
17813 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
17815 else if (ptr_mode
== DImode
)
17817 /* It's too cumbersome to create the full 64-bit address, so let's
17823 1: l[wd] $25, target_function_offset - 12($31)
17824 l[wd] $static_chain, static_chain_offset - 12($31)
17828 where 12 is the offset of "1:" from the start of the code block. */
17829 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
17830 trampoline
[i
++] = OP (MIPS_BAL (1));
17831 trampoline
[i
++] = OP (MIPS_NOP
);
17832 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17833 target_function_offset
- 12,
17834 RETURN_ADDR_REGNUM
));
17835 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17836 static_chain_offset
- 12,
17837 RETURN_ADDR_REGNUM
));
17838 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17839 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
17843 /* If the target has load delays, emit:
17845 lui $1, %hi(end_addr)
17846 lw $25, %lo(end_addr + ...)($1)
17847 lw $static_chain, %lo(end_addr + ...)($1)
17853 lui $1, %hi(end_addr)
17854 lw $25, %lo(end_addr + ...)($1)
17856 lw $static_chain, %lo(end_addr + ...)($1). */
17858 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17859 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17860 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
17861 NULL
, false, OPTAB_WIDEN
);
17862 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
17863 NULL
, false, OPTAB_WIDEN
);
17864 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
17866 /* Emit the LUI. */
17867 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
17868 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
17869 NULL
, false, OPTAB_WIDEN
);
17871 /* Emit the load of the target function. */
17872 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17873 target_function_offset
- end_addr_offset
,
17875 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17876 NULL
, false, OPTAB_WIDEN
);
17878 /* Emit the JR here, if we can. */
17879 if (!ISA_HAS_LOAD_DELAY
)
17880 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17882 /* Emit the load of the static chain register. */
17883 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17884 static_chain_offset
- end_addr_offset
,
17886 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17887 NULL
, false, OPTAB_WIDEN
);
17889 /* Emit the JR, if we couldn't above. */
17890 if (ISA_HAS_LOAD_DELAY
)
17892 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17893 trampoline
[i
++] = OP (MIPS_NOP
);
17899 /* Copy the trampoline code. Leave any padding uninitialized. */
17900 for (j
= 0; j
< i
; j
++)
17902 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
17903 mips_emit_move (mem
, trampoline
[j
]);
17906 /* Set up the static chain pointer field. */
17907 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
17908 mips_emit_move (mem
, chain_value
);
17910 /* Set up the target function field. */
17911 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
17912 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
17914 /* Flush the code part of the trampoline. */
17915 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
17916 emit_insn (gen_clear_cache (addr
, end_addr
));
17919 /* Implement FUNCTION_PROFILER. */
17921 void mips_function_profiler (FILE *file
)
17924 sorry ("mips16 function profiling");
17925 if (TARGET_LONG_CALLS
)
17927 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17928 if (Pmode
== DImode
)
17929 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
17931 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
17933 mips_push_asm_switch (&mips_noat
);
17934 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
17935 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
17936 /* _mcount treats $2 as the static chain register. */
17937 if (cfun
->static_chain_decl
!= NULL
)
17938 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
17939 reg_names
[STATIC_CHAIN_REGNUM
]);
17940 if (TARGET_MCOUNT_RA_ADDRESS
)
17942 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17943 ra save location. */
17944 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
17945 /* ra not saved, pass zero. */
17946 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
17948 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
17949 Pmode
== DImode
? "dla" : "la", reg_names
[12],
17950 cfun
->machine
->frame
.ra_fp_offset
,
17951 reg_names
[STACK_POINTER_REGNUM
]);
17953 if (!TARGET_NEWABI
)
17955 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17956 TARGET_64BIT
? "dsubu" : "subu",
17957 reg_names
[STACK_POINTER_REGNUM
],
17958 reg_names
[STACK_POINTER_REGNUM
],
17959 Pmode
== DImode
? 16 : 8);
17961 if (TARGET_LONG_CALLS
)
17962 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
17964 fprintf (file
, "\tjal\t_mcount\n");
17965 mips_pop_asm_switch (&mips_noat
);
17966 /* _mcount treats $2 as the static chain register. */
17967 if (cfun
->static_chain_decl
!= NULL
)
17968 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
17972 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17973 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17974 when TARGET_LOONGSON_VECTORS is true. */
17976 static unsigned HOST_WIDE_INT
17977 mips_shift_truncation_mask (enum machine_mode mode
)
17979 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
17982 return GET_MODE_BITSIZE (mode
) - 1;
17985 /* Implement TARGET_PREPARE_PCH_SAVE. */
17988 mips_prepare_pch_save (void)
17990 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17991 setting should be irrelevant. The question then is: which setting
17992 makes most sense at load time?
17994 The PCH is loaded before the first token is read. We should never
17995 have switched into MIPS16 mode by that point, and thus should not
17996 have populated mips16_globals. Nor can we load the entire contents
17997 of mips16_globals from the PCH file, because mips16_globals contains
17998 a combination of GGC and non-GGC data.
18000 There is therefore no point in trying save the GGC part of
18001 mips16_globals to the PCH file, or to preserve MIPS16ness across
18002 the PCH save and load. The loading compiler would not have access
18003 to the non-GGC parts of mips16_globals (either from the PCH file,
18004 or from a copy that the loading compiler generated itself) and would
18005 have to call target_reinit anyway.
18007 It therefore seems best to switch back to non-MIPS16 mode at
18008 save time, and to ensure that mips16_globals remains null after
18010 mips_set_compression_mode (0);
18011 mips16_globals
= 0;
18014 /* Generate or test for an insn that supports a constant permutation. */
18016 #define MAX_VECT_LEN 8
18018 struct expand_vec_perm_d
18020 rtx target
, op0
, op1
;
18021 unsigned char perm
[MAX_VECT_LEN
];
18022 enum machine_mode vmode
;
18023 unsigned char nelt
;
18028 /* Construct (set target (vec_select op0 (parallel perm))) and
18029 return true if that's a valid instruction in the active ISA. */
18032 mips_expand_vselect (rtx target
, rtx op0
,
18033 const unsigned char *perm
, unsigned nelt
)
18035 rtx rperm
[MAX_VECT_LEN
], x
;
18038 for (i
= 0; i
< nelt
; ++i
)
18039 rperm
[i
] = GEN_INT (perm
[i
]);
18041 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18042 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18043 x
= gen_rtx_SET (VOIDmode
, target
, x
);
18046 if (recog_memoized (x
) < 0)
18054 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18057 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18058 const unsigned char *perm
, unsigned nelt
)
18060 enum machine_mode v2mode
;
18063 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18064 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18065 return mips_expand_vselect (target
, x
, perm
, nelt
);
18068 /* Recognize patterns for even-odd extraction. */
18071 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18073 unsigned i
, odd
, nelt
= d
->nelt
;
18074 rtx t0
, t1
, t2
, t3
;
18076 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18078 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18085 for (i
= 1; i
< nelt
; ++i
)
18086 if (d
->perm
[i
] != i
* 2 + odd
)
18092 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18093 t0
= gen_reg_rtx (d
->vmode
);
18094 t1
= gen_reg_rtx (d
->vmode
);
18098 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18099 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18101 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18103 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18107 t2
= gen_reg_rtx (d
->vmode
);
18108 t3
= gen_reg_rtx (d
->vmode
);
18109 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18110 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18111 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18112 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18114 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18116 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18120 gcc_unreachable ();
18125 /* Recognize patterns for the Loongson PSHUFH instruction. */
18128 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18133 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18135 if (d
->vmode
!= V4HImode
)
18140 /* Convert the selector into the packed 8-bit form for pshufh. */
18141 /* Recall that loongson is little-endian only. No big-endian
18142 adjustment required. */
18143 for (i
= mask
= 0; i
< 4; i
++)
18144 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18145 rmask
= force_reg (SImode
, GEN_INT (mask
));
18147 if (d
->one_vector_p
)
18148 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18151 rtx t0
, t1
, x
, merge
, rmerge
[4];
18153 t0
= gen_reg_rtx (V4HImode
);
18154 t1
= gen_reg_rtx (V4HImode
);
18155 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18156 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18158 for (i
= 0; i
< 4; ++i
)
18159 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18160 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18161 merge
= force_reg (V4HImode
, merge
);
18163 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18164 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18166 x
= gen_rtx_NOT (V4HImode
, merge
);
18167 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18168 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18170 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18171 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
18177 /* Recognize broadcast patterns for the Loongson. */
18180 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18185 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18187 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18188 if (d
->vmode
!= V8QImode
)
18190 if (!d
->one_vector_p
)
18194 for (i
= 1; i
< 8; ++i
)
18195 if (d
->perm
[i
] != elt
)
18201 /* With one interleave we put two of the desired element adjacent. */
18202 t0
= gen_reg_rtx (V8QImode
);
18204 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18206 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18208 /* Shuffle that one HImode element into all locations. */
18211 t1
= gen_reg_rtx (V4HImode
);
18212 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18213 force_reg (SImode
, GEN_INT (elt
))));
18215 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18220 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18222 unsigned int i
, nelt
= d
->nelt
;
18223 unsigned char perm2
[MAX_VECT_LEN
];
18225 if (d
->one_vector_p
)
18227 /* Try interleave with alternating operands. */
18228 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18229 for (i
= 1; i
< nelt
; i
+= 2)
18231 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18236 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18240 /* Try again with swapped operands. */
18241 for (i
= 0; i
< nelt
; ++i
)
18242 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18243 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18247 if (mips_expand_vpc_loongson_even_odd (d
))
18249 if (mips_expand_vpc_loongson_pshufh (d
))
18251 if (mips_expand_vpc_loongson_bcast (d
))
18256 /* Expand a vec_perm_const pattern. */
18259 mips_expand_vec_perm_const (rtx operands
[4])
18261 struct expand_vec_perm_d d
;
18262 int i
, nelt
, which
;
18263 unsigned char orig_perm
[MAX_VECT_LEN
];
18267 d
.target
= operands
[0];
18268 d
.op0
= operands
[1];
18269 d
.op1
= operands
[2];
18272 d
.vmode
= GET_MODE (d
.target
);
18273 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18274 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18275 d
.testing_p
= false;
18277 for (i
= which
= 0; i
< nelt
; ++i
)
18279 rtx e
= XVECEXP (sel
, 0, i
);
18280 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18281 which
|= (ei
< nelt
? 1 : 2);
18284 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18292 d
.one_vector_p
= false;
18293 if (!rtx_equal_p (d
.op0
, d
.op1
))
18298 for (i
= 0; i
< nelt
; ++i
)
18299 d
.perm
[i
] &= nelt
- 1;
18301 d
.one_vector_p
= true;
18306 d
.one_vector_p
= true;
18310 ok
= mips_expand_vec_perm_const_1 (&d
);
18312 /* If we were given a two-vector permutation which just happened to
18313 have both input vectors equal, we folded this into a one-vector
18314 permutation. There are several loongson patterns that are matched
18315 via direct vec_select+vec_concat expansion, but we do not have
18316 support in mips_expand_vec_perm_const_1 to guess the adjustment
18317 that should be made for a single operand. Just try again with
18318 the original permutation. */
18319 if (!ok
&& which
== 3)
18321 d
.op0
= operands
[1];
18322 d
.op1
= operands
[2];
18323 d
.one_vector_p
= false;
18324 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18325 ok
= mips_expand_vec_perm_const_1 (&d
);
18331 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18334 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
18335 const unsigned char *sel
)
18337 struct expand_vec_perm_d d
;
18338 unsigned int i
, nelt
, which
;
18342 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18343 d
.testing_p
= true;
18344 memcpy (d
.perm
, sel
, nelt
);
18346 /* Categorize the set of elements in the selector. */
18347 for (i
= which
= 0; i
< nelt
; ++i
)
18349 unsigned char e
= d
.perm
[i
];
18350 gcc_assert (e
< 2 * nelt
);
18351 which
|= (e
< nelt
? 1 : 2);
18354 /* For all elements from second vector, fold the elements to first. */
18356 for (i
= 0; i
< nelt
; ++i
)
18359 /* Check whether the mask can be applied to the vector type. */
18360 d
.one_vector_p
= (which
!= 3);
18362 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18363 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18364 if (!d
.one_vector_p
)
18365 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18368 ret
= mips_expand_vec_perm_const_1 (&d
);
18374 /* Expand an integral vector unpack operation. */
18377 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18379 enum machine_mode imode
= GET_MODE (operands
[1]);
18380 rtx (*unpack
) (rtx
, rtx
, rtx
);
18381 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18382 rtx tmp
, dest
, zero
;
18388 unpack
= gen_loongson_punpckhbh
;
18390 unpack
= gen_loongson_punpcklbh
;
18391 cmpgt
= gen_loongson_pcmpgtb
;
18395 unpack
= gen_loongson_punpckhhw
;
18397 unpack
= gen_loongson_punpcklhw
;
18398 cmpgt
= gen_loongson_pcmpgth
;
18401 gcc_unreachable ();
18404 zero
= force_reg (imode
, CONST0_RTX (imode
));
18409 tmp
= gen_reg_rtx (imode
);
18410 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
18413 dest
= gen_reg_rtx (imode
);
18414 emit_insn (unpack (dest
, operands
[1], tmp
));
18416 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
18419 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18422 mips_constant_elt_p (rtx x
)
18424 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
18427 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18430 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
18432 struct expand_vec_perm_d d
;
18436 if (elt
!= const0_rtx
)
18437 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
18439 elt
= gen_lowpart (DImode
, elt
);
18441 t1
= gen_reg_rtx (vmode
);
18445 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
18448 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
18451 gcc_unreachable ();
18454 memset (&d
, 0, sizeof (d
));
18459 d
.nelt
= GET_MODE_NUNITS (vmode
);
18460 d
.one_vector_p
= true;
18462 ok
= mips_expand_vec_perm_const_1 (&d
);
18466 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18467 elements of VALS with zeros, copy the constant vector to TARGET. */
18470 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
18471 rtx target
, rtx vals
)
18473 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
18476 for (i
= 0; i
< nelt
; ++i
)
18478 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
18479 RTVEC_ELT (vec
, i
) = const0_rtx
;
18482 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
18486 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18489 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
18491 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
18493 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
18494 GEN_INT (one_var
)));
18497 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18500 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
18501 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
18503 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
18504 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
18507 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
18509 for (i
= 0; i
< nelt
; ++i
)
18511 rtx x
= XVECEXP (vals
, 0, i
);
18512 if (!mips_constant_elt_p (x
))
18513 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
18516 emit_move_insn (target
, mem
);
18519 /* Expand a vector initialization. */
18522 mips_expand_vector_init (rtx target
, rtx vals
)
18524 enum machine_mode vmode
= GET_MODE (target
);
18525 enum machine_mode imode
= GET_MODE_INNER (vmode
);
18526 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
18527 unsigned nvar
= 0, one_var
= -1u;
18528 bool all_same
= true;
18531 for (i
= 0; i
< nelt
; ++i
)
18533 x
= XVECEXP (vals
, 0, i
);
18534 if (!mips_constant_elt_p (x
))
18535 nvar
++, one_var
= i
;
18536 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
18540 /* Load constants from the pool, or whatever's handy. */
18543 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
18547 /* For two-part initialization, always use CONCAT. */
18550 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
18551 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
18552 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
18553 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18557 /* Loongson is the only cpu with vectors with more elements. */
18558 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
18560 /* If all values are identical, broadcast the value. */
18563 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
18567 /* If we've only got one non-variable V4HImode, use PINSRH. */
18568 if (nvar
== 1 && vmode
== V4HImode
)
18570 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
18574 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
18577 /* Expand a vector reduction. */
18580 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
18582 enum machine_mode vmode
= GET_MODE (in
);
18583 unsigned char perm2
[2];
18584 rtx last
, next
, fold
, x
;
18588 fold
= gen_reg_rtx (vmode
);
18592 /* Use PUL/PLU to produce { L, H } op { H, L }.
18593 By reversing the pair order, rather than a pure interleave high,
18594 we avoid erroneous exceptional conditions that we might otherwise
18595 produce from the computation of H op H. */
18598 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
18603 /* Use interleave to produce { H, L } op { H, H }. */
18604 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
18608 /* Perform the first reduction with interleave,
18609 and subsequent reductions with shifts. */
18610 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
18612 next
= gen_reg_rtx (vmode
);
18613 emit_insn (gen (next
, last
, fold
));
18616 fold
= gen_reg_rtx (vmode
);
18617 x
= force_reg (SImode
, GEN_INT (16));
18618 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
18622 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
18624 next
= gen_reg_rtx (vmode
);
18625 emit_insn (gen (next
, last
, fold
));
18628 fold
= gen_reg_rtx (vmode
);
18629 x
= force_reg (SImode
, GEN_INT (16));
18630 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18632 next
= gen_reg_rtx (vmode
);
18633 emit_insn (gen (next
, last
, fold
));
18636 fold
= gen_reg_rtx (vmode
);
18637 x
= force_reg (SImode
, GEN_INT (8));
18638 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18642 gcc_unreachable ();
18645 emit_insn (gen (target
, last
, fold
));
18648 /* Expand a vector minimum/maximum. */
18651 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18652 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18654 enum machine_mode vmode
= GET_MODE (target
);
18657 tc
= gen_reg_rtx (vmode
);
18658 t0
= gen_reg_rtx (vmode
);
18659 t1
= gen_reg_rtx (vmode
);
18662 emit_insn (cmp (tc
, op0
, op1
));
18664 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18665 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18667 x
= gen_rtx_NOT (vmode
, tc
);
18668 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18669 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18671 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18672 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18675 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18678 mips_case_values_threshold (void)
18680 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18681 if (TARGET_MIPS16
&& optimize_size
)
18684 return default_case_values_threshold ();
18687 /* Initialize the GCC target structure. */
18688 #undef TARGET_ASM_ALIGNED_HI_OP
18689 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18690 #undef TARGET_ASM_ALIGNED_SI_OP
18691 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18692 #undef TARGET_ASM_ALIGNED_DI_OP
18693 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18695 #undef TARGET_OPTION_OVERRIDE
18696 #define TARGET_OPTION_OVERRIDE mips_option_override
18698 #undef TARGET_LEGITIMIZE_ADDRESS
18699 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18701 #undef TARGET_ASM_FUNCTION_PROLOGUE
18702 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18703 #undef TARGET_ASM_FUNCTION_EPILOGUE
18704 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18705 #undef TARGET_ASM_SELECT_RTX_SECTION
18706 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18707 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18708 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18710 #undef TARGET_SCHED_INIT
18711 #define TARGET_SCHED_INIT mips_sched_init
18712 #undef TARGET_SCHED_REORDER
18713 #define TARGET_SCHED_REORDER mips_sched_reorder
18714 #undef TARGET_SCHED_REORDER2
18715 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18716 #undef TARGET_SCHED_VARIABLE_ISSUE
18717 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18718 #undef TARGET_SCHED_ADJUST_COST
18719 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18720 #undef TARGET_SCHED_ISSUE_RATE
18721 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18722 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18723 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18724 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18725 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18726 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18727 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18728 mips_multipass_dfa_lookahead
18729 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18730 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18731 mips_small_register_classes_for_mode_p
18733 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18734 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18736 #undef TARGET_INSERT_ATTRIBUTES
18737 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18738 #undef TARGET_MERGE_DECL_ATTRIBUTES
18739 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18740 #undef TARGET_CAN_INLINE_P
18741 #define TARGET_CAN_INLINE_P mips_can_inline_p
18742 #undef TARGET_SET_CURRENT_FUNCTION
18743 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18745 #undef TARGET_VALID_POINTER_MODE
18746 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18747 #undef TARGET_REGISTER_MOVE_COST
18748 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18749 #undef TARGET_MEMORY_MOVE_COST
18750 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18751 #undef TARGET_RTX_COSTS
18752 #define TARGET_RTX_COSTS mips_rtx_costs
18753 #undef TARGET_ADDRESS_COST
18754 #define TARGET_ADDRESS_COST mips_address_cost
18756 #undef TARGET_IN_SMALL_DATA_P
18757 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18759 #undef TARGET_MACHINE_DEPENDENT_REORG
18760 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18762 #undef TARGET_PREFERRED_RELOAD_CLASS
18763 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18765 #undef TARGET_EXPAND_TO_RTL_HOOK
18766 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18767 #undef TARGET_ASM_FILE_START
18768 #define TARGET_ASM_FILE_START mips_file_start
18769 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18770 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18771 #undef TARGET_ASM_CODE_END
18772 #define TARGET_ASM_CODE_END mips_code_end
18774 #undef TARGET_INIT_LIBFUNCS
18775 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18777 #undef TARGET_BUILD_BUILTIN_VA_LIST
18778 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18779 #undef TARGET_EXPAND_BUILTIN_VA_START
18780 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18781 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18782 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18784 #undef TARGET_PROMOTE_FUNCTION_MODE
18785 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18786 #undef TARGET_PROMOTE_PROTOTYPES
18787 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18789 #undef TARGET_FUNCTION_VALUE
18790 #define TARGET_FUNCTION_VALUE mips_function_value
18791 #undef TARGET_LIBCALL_VALUE
18792 #define TARGET_LIBCALL_VALUE mips_libcall_value
18793 #undef TARGET_FUNCTION_VALUE_REGNO_P
18794 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18795 #undef TARGET_RETURN_IN_MEMORY
18796 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18797 #undef TARGET_RETURN_IN_MSB
18798 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18800 #undef TARGET_ASM_OUTPUT_MI_THUNK
18801 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18802 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18803 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18805 #undef TARGET_PRINT_OPERAND
18806 #define TARGET_PRINT_OPERAND mips_print_operand
18807 #undef TARGET_PRINT_OPERAND_ADDRESS
18808 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18809 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18810 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18812 #undef TARGET_SETUP_INCOMING_VARARGS
18813 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18814 #undef TARGET_STRICT_ARGUMENT_NAMING
18815 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18816 #undef TARGET_MUST_PASS_IN_STACK
18817 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18818 #undef TARGET_PASS_BY_REFERENCE
18819 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18820 #undef TARGET_CALLEE_COPIES
18821 #define TARGET_CALLEE_COPIES mips_callee_copies
18822 #undef TARGET_ARG_PARTIAL_BYTES
18823 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18824 #undef TARGET_FUNCTION_ARG
18825 #define TARGET_FUNCTION_ARG mips_function_arg
18826 #undef TARGET_FUNCTION_ARG_ADVANCE
18827 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18828 #undef TARGET_FUNCTION_ARG_BOUNDARY
18829 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18831 #undef TARGET_MODE_REP_EXTENDED
18832 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18834 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18835 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18837 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18838 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18840 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18841 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18843 #undef TARGET_INIT_BUILTINS
18844 #define TARGET_INIT_BUILTINS mips_init_builtins
18845 #undef TARGET_BUILTIN_DECL
18846 #define TARGET_BUILTIN_DECL mips_builtin_decl
18847 #undef TARGET_EXPAND_BUILTIN
18848 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18850 #undef TARGET_HAVE_TLS
18851 #define TARGET_HAVE_TLS HAVE_AS_TLS
18853 #undef TARGET_CANNOT_FORCE_CONST_MEM
18854 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18856 #undef TARGET_LEGITIMATE_CONSTANT_P
18857 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18859 #undef TARGET_ENCODE_SECTION_INFO
18860 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18862 #undef TARGET_ATTRIBUTE_TABLE
18863 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18864 /* All our function attributes are related to how out-of-line copies should
18865 be compiled or called. They don't in themselves prevent inlining. */
18866 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18867 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18869 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18870 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18872 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18873 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18874 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18875 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18877 #undef TARGET_COMP_TYPE_ATTRIBUTES
18878 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18880 #ifdef HAVE_AS_DTPRELWORD
18881 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18882 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18884 #undef TARGET_DWARF_REGISTER_SPAN
18885 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18887 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18888 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18890 #undef TARGET_LEGITIMATE_ADDRESS_P
18891 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18893 #undef TARGET_FRAME_POINTER_REQUIRED
18894 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18896 #undef TARGET_CAN_ELIMINATE
18897 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18899 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18900 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18902 #undef TARGET_TRAMPOLINE_INIT
18903 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18905 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18906 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18908 #undef TARGET_SHIFT_TRUNCATION_MASK
18909 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18911 #undef TARGET_PREPARE_PCH_SAVE
18912 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18914 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18915 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18917 #undef TARGET_CASE_VALUES_THRESHOLD
18918 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
18920 struct gcc_target targetm
= TARGET_INITIALIZER
;
18922 #include "gt-mips.h"