1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
33 #include "insn-config.h"
34 #include "conditions.h"
35 #include "insn-attr.h"
39 #include "fold-const.h"
41 #include "stringpool.h"
42 #include "stor-layout.h"
51 #include "insn-codes.h"
59 #include "common/common-target.h"
60 #include "langhooks.h"
65 #include "cfgcleanup.h"
66 #include "sched-int.h"
67 #include "internal-fn.h"
68 #include "gimple-fold.h"
71 #include "diagnostic.h"
72 #include "target-globals.h"
74 #include "tree-pass.h"
80 /* This file should be included last. */
81 #include "target-def.h"
83 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
84 #define UNSPEC_ADDRESS_P(X) \
85 (GET_CODE (X) == UNSPEC \
86 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
87 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
89 /* Extract the symbol or label from UNSPEC wrapper X. */
90 #define UNSPEC_ADDRESS(X) \
93 /* Extract the symbol type from UNSPEC wrapper X. */
94 #define UNSPEC_ADDRESS_TYPE(X) \
95 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
97 /* The maximum distance between the top of the stack frame and the
98 value $sp has when we save and restore registers.
100 The value for normal-mode code must be a SMALL_OPERAND and must
101 preserve the maximum stack alignment. We therefore use a value
102 of 0x7ff0 in this case.
104 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
105 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
107 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
108 up to 0x7f8 bytes and can usually save or restore all the registers
109 that we need to save or restore. (Note that we can only use these
110 instructions for o32, for which the stack alignment is 8 bytes.)
112 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
113 RESTORE are not available. We can then use unextended instructions
114 to save and restore registers, and to allocate and deallocate the top
115 part of the frame. */
116 #define MIPS_MAX_FIRST_STACK_STEP \
117 (!TARGET_COMPRESSION ? 0x7ff0 \
118 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
119 : TARGET_64BIT ? 0x100 : 0x400)
121 /* True if INSN is a mips.md pattern or asm statement. */
122 /* ??? This test exists through the compiler, perhaps it should be
124 #define USEFUL_INSN_P(INSN) \
125 (NONDEBUG_INSN_P (INSN) \
126 && GET_CODE (PATTERN (INSN)) != USE \
127 && GET_CODE (PATTERN (INSN)) != CLOBBER)
129 /* If INSN is a delayed branch sequence, return the first instruction
130 in the sequence, otherwise return INSN itself. */
131 #define SEQ_BEGIN(INSN) \
132 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
133 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
136 /* Likewise for the last instruction in a delayed branch sequence. */
137 #define SEQ_END(INSN) \
138 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
139 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
141 XVECLEN (PATTERN (INSN), 0) - 1)) \
144 /* Execute the following loop body with SUBINSN set to each instruction
145 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
146 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
147 for ((SUBINSN) = SEQ_BEGIN (INSN); \
148 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
149 (SUBINSN) = NEXT_INSN (SUBINSN))
151 /* True if bit BIT is set in VALUE. */
152 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
154 /* Return the opcode for a ptr_mode load of the form:
156 l[wd] DEST, OFFSET(BASE). */
157 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
158 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
163 /* Return the opcode to move register SRC into register DEST. */
164 #define MIPS_MOVE(DEST, SRC) \
165 ((TARGET_64BIT ? 0x2d : 0x21) \
169 /* Return the opcode for:
172 #define MIPS_LUI(DEST, VALUE) \
173 ((0xf << 26) | ((DEST) << 16) | (VALUE))
175 /* Return the opcode to jump to register DEST. When the JR opcode is not
176 available use JALR $0, DEST. */
177 #define MIPS_JR(DEST) \
178 (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9))
180 /* Return the opcode for:
182 bal . + (1 + OFFSET) * 4. */
183 #define MIPS_BAL(OFFSET) \
184 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
186 /* Return the usual opcode for a nop. */
189 /* Classifies an address.
192 A natural register + offset address. The register satisfies
193 mips_valid_base_register_p and the offset is a const_arith_operand.
196 A LO_SUM rtx. The first operand is a valid base register and
197 the second operand is a symbolic address.
200 A signed 16-bit constant address.
203 A constant symbolic address. */
204 enum mips_address_type
{
211 /* Macros to create an enumeration identifier for a function prototype. */
212 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
213 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
214 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
215 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
217 /* Classifies the prototype of a built-in function. */
218 enum mips_function_type
{
219 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
220 #include "config/mips/mips-ftypes.def"
221 #undef DEF_MIPS_FTYPE
225 /* Specifies how a built-in function should be converted into rtl. */
226 enum mips_builtin_type
{
227 /* The function corresponds directly to an .md pattern. The return
228 value is mapped to operand 0 and the arguments are mapped to
229 operands 1 and above. */
232 /* The function corresponds directly to an .md pattern. There is no return
233 value and the arguments are mapped to operands 0 and above. */
234 MIPS_BUILTIN_DIRECT_NO_TARGET
,
236 /* The function corresponds to a comparison instruction followed by
237 a mips_cond_move_tf_ps pattern. The first two arguments are the
238 values to compare and the second two arguments are the vector
239 operands for the movt.ps or movf.ps instruction (in assembly order). */
243 /* The function corresponds to a V2SF comparison instruction. Operand 0
244 of this instruction is the result of the comparison, which has mode
245 CCV2 or CCV4. The function arguments are mapped to operands 1 and
246 above. The function's return value is an SImode boolean that is
247 true under the following conditions:
249 MIPS_BUILTIN_CMP_ANY: one of the registers is true
250 MIPS_BUILTIN_CMP_ALL: all of the registers are true
251 MIPS_BUILTIN_CMP_LOWER: the first register is true
252 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
253 MIPS_BUILTIN_CMP_ANY
,
254 MIPS_BUILTIN_CMP_ALL
,
255 MIPS_BUILTIN_CMP_UPPER
,
256 MIPS_BUILTIN_CMP_LOWER
,
258 /* As above, but the instruction only sets a single $fcc register. */
259 MIPS_BUILTIN_CMP_SINGLE
,
261 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
262 MIPS_BUILTIN_BPOSGE32
265 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
266 #define MIPS_FP_CONDITIONS(MACRO) \
284 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
285 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
286 enum mips_fp_condition
{
287 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
289 #undef DECLARE_MIPS_COND
291 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
292 #define STRINGIFY(X) #X
293 static const char *const mips_fp_conditions
[] = {
294 MIPS_FP_CONDITIONS (STRINGIFY
)
298 /* A class used to control a comdat-style stub that we output in each
299 translation unit that needs it. */
300 class mips_one_only_stub
{
302 virtual ~mips_one_only_stub () {}
304 /* Return the name of the stub. */
305 virtual const char *get_name () = 0;
307 /* Output the body of the function to asm_out_file. */
308 virtual void output_body () = 0;
311 /* Tuning information that is automatically derived from other sources
312 (such as the scheduler). */
314 /* The architecture and tuning settings that this structure describes. */
318 /* True if this structure describes MIPS16 settings. */
321 /* True if the structure has been initialized. */
324 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
325 when optimizing for speed. */
326 bool fast_mult_zero_zero_p
;
329 /* Information about a function's frame layout. */
330 struct GTY(()) mips_frame_info
{
331 /* The size of the frame in bytes. */
332 HOST_WIDE_INT total_size
;
334 /* The number of bytes allocated to variables. */
335 HOST_WIDE_INT var_size
;
337 /* The number of bytes allocated to outgoing function arguments. */
338 HOST_WIDE_INT args_size
;
340 /* The number of bytes allocated to the .cprestore slot, or 0 if there
342 HOST_WIDE_INT cprestore_size
;
344 /* Bit X is set if the function saves or restores GPR X. */
347 /* Likewise FPR X. */
350 /* Likewise doubleword accumulator X ($acX). */
351 unsigned int acc_mask
;
353 /* The number of GPRs, FPRs, doubleword accumulators and COP0
357 unsigned int num_acc
;
358 unsigned int num_cop0_regs
;
360 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
361 save slots from the top of the frame, or zero if no such slots are
363 HOST_WIDE_INT gp_save_offset
;
364 HOST_WIDE_INT fp_save_offset
;
365 HOST_WIDE_INT acc_save_offset
;
366 HOST_WIDE_INT cop0_save_offset
;
368 /* Likewise, but giving offsets from the bottom of the frame. */
369 HOST_WIDE_INT gp_sp_offset
;
370 HOST_WIDE_INT fp_sp_offset
;
371 HOST_WIDE_INT acc_sp_offset
;
372 HOST_WIDE_INT cop0_sp_offset
;
374 /* Similar, but the value passed to _mcount. */
375 HOST_WIDE_INT ra_fp_offset
;
377 /* The offset of arg_pointer_rtx from the bottom of the frame. */
378 HOST_WIDE_INT arg_pointer_offset
;
380 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
381 HOST_WIDE_INT hard_frame_pointer_offset
;
384 struct GTY(()) machine_function
{
385 /* The next floating-point condition-code register to allocate
386 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
387 unsigned int next_fcc
;
389 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
390 rtx mips16_gp_pseudo_rtx
;
392 /* The number of extra stack bytes taken up by register varargs.
393 This area is allocated by the callee at the very top of the frame. */
396 /* The current frame information, calculated by mips_compute_frame_info. */
397 struct mips_frame_info frame
;
399 /* The register to use as the function's global pointer, or INVALID_REGNUM
400 if the function doesn't need one. */
401 unsigned int global_pointer
;
403 /* How many instructions it takes to load a label into $AT, or 0 if
404 this property hasn't yet been calculated. */
405 unsigned int load_label_num_insns
;
407 /* True if mips_adjust_insn_length should ignore an instruction's
409 bool ignore_hazard_length_p
;
411 /* True if the whole function is suitable for .set noreorder and
413 bool all_noreorder_p
;
415 /* True if the function has "inflexible" and "flexible" references
416 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
417 and mips_cfun_has_flexible_gp_ref_p for details. */
418 bool has_inflexible_gp_insn_p
;
419 bool has_flexible_gp_insn_p
;
421 /* True if the function's prologue must load the global pointer
422 value into pic_offset_table_rtx and store the same value in
423 the function's cprestore slot (if any). Even if this value
424 is currently false, we may decide to set it to true later;
425 see mips_must_initialize_gp_p () for details. */
426 bool must_initialize_gp_p
;
428 /* True if the current function must restore $gp after any potential
429 clobber. This value is only meaningful during the first post-epilogue
430 split_insns pass; see mips_must_initialize_gp_p () for details. */
431 bool must_restore_gp_when_clobbered_p
;
433 /* True if this is an interrupt handler. */
434 bool interrupt_handler_p
;
436 /* True if this is an interrupt handler that uses shadow registers. */
437 bool use_shadow_register_set_p
;
439 /* True if this is an interrupt handler that should keep interrupts
441 bool keep_interrupts_masked_p
;
443 /* True if this is an interrupt handler that should use DERET
445 bool use_debug_exception_return_p
;
448 /* Information about a single argument. */
449 struct mips_arg_info
{
450 /* True if the argument is passed in a floating-point register, or
451 would have been if we hadn't run out of registers. */
454 /* The number of words passed in registers, rounded up. */
455 unsigned int reg_words
;
457 /* For EABI, the offset of the first register from GP_ARG_FIRST or
458 FP_ARG_FIRST. For other ABIs, the offset of the first register from
459 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
460 comment for details).
462 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
464 unsigned int reg_offset
;
466 /* The number of words that must be passed on the stack, rounded up. */
467 unsigned int stack_words
;
469 /* The offset from the start of the stack overflow area of the argument's
470 first stack word. Only meaningful when STACK_WORDS is nonzero. */
471 unsigned int stack_offset
;
474 /* Information about an address described by mips_address_type.
480 REG is the base register and OFFSET is the constant offset.
483 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
484 is the type of symbol it references.
487 SYMBOL_TYPE is the type of symbol that the address references. */
488 struct mips_address_info
{
489 enum mips_address_type type
;
492 enum mips_symbol_type symbol_type
;
495 /* One stage in a constant building sequence. These sequences have
499 A = A CODE[1] VALUE[1]
500 A = A CODE[2] VALUE[2]
503 where A is an accumulator, each CODE[i] is a binary rtl operation
504 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
505 struct mips_integer_op
{
507 unsigned HOST_WIDE_INT value
;
510 /* The largest number of operations needed to load an integer constant.
511 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
512 When the lowest bit is clear, we can try, but reject a sequence with
513 an extra SLL at the end. */
514 #define MIPS_MAX_INTEGER_OPS 7
516 /* Information about a MIPS16e SAVE or RESTORE instruction. */
517 struct mips16e_save_restore_info
{
518 /* The number of argument registers saved by a SAVE instruction.
519 0 for RESTORE instructions. */
522 /* Bit X is set if the instruction saves or restores GPR X. */
525 /* The total number of bytes to allocate. */
529 /* Costs of various operations on the different architectures. */
531 struct mips_rtx_cost_data
533 unsigned short fp_add
;
534 unsigned short fp_mult_sf
;
535 unsigned short fp_mult_df
;
536 unsigned short fp_div_sf
;
537 unsigned short fp_div_df
;
538 unsigned short int_mult_si
;
539 unsigned short int_mult_di
;
540 unsigned short int_div_si
;
541 unsigned short int_div_di
;
542 unsigned short branch_cost
;
543 unsigned short memory_latency
;
546 /* Global variables for machine-dependent things. */
548 /* The -G setting, or the configuration's default small-data limit if
549 no -G option is given. */
550 static unsigned int mips_small_data_threshold
;
552 /* The number of file directives written by mips_output_filename. */
553 int num_source_filenames
;
555 /* The name that appeared in the last .file directive written by
556 mips_output_filename, or "" if mips_output_filename hasn't
557 written anything yet. */
558 const char *current_function_file
= "";
560 /* Arrays that map GCC register numbers to debugger register numbers. */
561 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
562 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
564 /* Information about the current function's epilogue, used only while
567 /* A list of queued REG_CFA_RESTORE notes. */
570 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
572 HOST_WIDE_INT cfa_offset
;
574 /* The offset of the CFA from the stack pointer while restoring
576 HOST_WIDE_INT cfa_restore_sp_offset
;
579 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
580 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
581 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
582 struct mips_asm_switch mips_noat
= { "at", 0 };
584 /* True if we're writing out a branch-likely instruction rather than a
586 static bool mips_branch_likely
;
588 /* The current instruction-set architecture. */
589 enum processor mips_arch
;
590 const struct mips_cpu_info
*mips_arch_info
;
592 /* The processor that we should tune the code for. */
593 enum processor mips_tune
;
594 const struct mips_cpu_info
*mips_tune_info
;
596 /* The ISA level associated with mips_arch. */
599 /* The ISA revision level. This is 0 for MIPS I to V and N for
603 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
604 static const struct mips_cpu_info
*mips_isa_option_info
;
606 /* Which cost information to use. */
607 static const struct mips_rtx_cost_data
*mips_cost
;
609 /* The ambient target flags, excluding MASK_MIPS16. */
610 static int mips_base_target_flags
;
612 /* The default compression mode. */
613 unsigned int mips_base_compression_flags
;
615 /* The ambient values of other global variables. */
616 static int mips_base_schedule_insns
; /* flag_schedule_insns */
617 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
618 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
619 static int mips_base_align_loops
; /* align_loops */
620 static int mips_base_align_jumps
; /* align_jumps */
621 static int mips_base_align_functions
; /* align_functions */
623 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
624 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
626 /* Index C is true if character C is a valid PRINT_OPERAND punctation
628 static bool mips_print_operand_punct
[256];
630 static GTY (()) int mips_output_filename_first_time
= 1;
632 /* mips_split_p[X] is true if symbols of type X can be split by
633 mips_split_symbol. */
634 bool mips_split_p
[NUM_SYMBOL_TYPES
];
636 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
637 can be split by mips_split_symbol. */
638 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
640 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
641 forced into a PC-relative constant pool. */
642 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
644 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
645 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
646 if they are matched by a special .md file pattern. */
647 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
649 /* Likewise for HIGHs. */
650 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
652 /* Target state for MIPS16. */
653 struct target_globals
*mips16_globals
;
655 /* Target state for MICROMIPS. */
656 struct target_globals
*micromips_globals
;
658 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
659 and returned from mips_sched_reorder2. */
660 static int cached_can_issue_more
;
662 /* The stubs for various MIPS16 support functions, if used. */
663 static mips_one_only_stub
*mips16_rdhwr_stub
;
664 static mips_one_only_stub
*mips16_get_fcsr_stub
;
665 static mips_one_only_stub
*mips16_set_fcsr_stub
;
667 /* Index R is the smallest register class that contains register R. */
668 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
669 LEA_REGS
, LEA_REGS
, M16_STORE_REGS
, V1_REG
,
670 M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
,
671 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
672 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
673 M16_REGS
, M16_STORE_REGS
, LEA_REGS
, LEA_REGS
,
674 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
675 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
676 LEA_REGS
, M16_SP_REGS
, LEA_REGS
, LEA_REGS
,
678 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
679 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
680 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
681 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
682 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
683 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
684 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
685 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
686 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
687 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
688 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
689 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
690 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
691 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
692 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
693 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
694 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
695 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
696 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
697 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
698 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
699 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
700 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
701 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
702 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
703 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
704 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
705 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
706 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
707 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
708 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
709 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
710 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
711 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
712 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
713 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
714 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
715 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
716 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
719 /* The value of TARGET_ATTRIBUTE_TABLE. */
720 static const struct attribute_spec mips_attribute_table
[] = {
721 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
723 { "long_call", 0, 0, false, true, true, NULL
, false },
724 { "far", 0, 0, false, true, true, NULL
, false },
725 { "near", 0, 0, false, true, true, NULL
, false },
726 /* We would really like to treat "mips16" and "nomips16" as type
727 attributes, but GCC doesn't provide the hooks we need to support
728 the right conversion rules. As declaration attributes, they affect
729 code generation but don't carry other semantics. */
730 { "mips16", 0, 0, true, false, false, NULL
, false },
731 { "nomips16", 0, 0, true, false, false, NULL
, false },
732 { "micromips", 0, 0, true, false, false, NULL
, false },
733 { "nomicromips", 0, 0, true, false, false, NULL
, false },
734 { "nocompression", 0, 0, true, false, false, NULL
, false },
735 /* Allow functions to be specified as interrupt handlers */
736 { "interrupt", 0, 0, false, true, true, NULL
, false },
737 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
738 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
739 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
740 { NULL
, 0, 0, false, false, false, NULL
, false }
743 /* A table describing all the processors GCC knows about; see
744 mips-cpus.def for details. */
745 static const struct mips_cpu_info mips_cpu_info_table
[] = {
746 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
747 { NAME, CPU, ISA, FLAGS },
748 #include "mips-cpus.def"
752 /* Default costs. If these are used for a processor we should look
753 up the actual costs. */
754 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
755 COSTS_N_INSNS (7), /* fp_mult_sf */ \
756 COSTS_N_INSNS (8), /* fp_mult_df */ \
757 COSTS_N_INSNS (23), /* fp_div_sf */ \
758 COSTS_N_INSNS (36), /* fp_div_df */ \
759 COSTS_N_INSNS (10), /* int_mult_si */ \
760 COSTS_N_INSNS (10), /* int_mult_di */ \
761 COSTS_N_INSNS (69), /* int_div_si */ \
762 COSTS_N_INSNS (69), /* int_div_di */ \
763 2, /* branch_cost */ \
764 4 /* memory_latency */
766 /* Floating-point costs for processors without an FPU. Just assume that
767 all floating-point libcalls are very expensive. */
768 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
769 COSTS_N_INSNS (256), /* fp_mult_sf */ \
770 COSTS_N_INSNS (256), /* fp_mult_df */ \
771 COSTS_N_INSNS (256), /* fp_div_sf */ \
772 COSTS_N_INSNS (256) /* fp_div_df */
774 /* Costs to use when optimizing for size. */
775 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
776 COSTS_N_INSNS (1), /* fp_add */
777 COSTS_N_INSNS (1), /* fp_mult_sf */
778 COSTS_N_INSNS (1), /* fp_mult_df */
779 COSTS_N_INSNS (1), /* fp_div_sf */
780 COSTS_N_INSNS (1), /* fp_div_df */
781 COSTS_N_INSNS (1), /* int_mult_si */
782 COSTS_N_INSNS (1), /* int_mult_di */
783 COSTS_N_INSNS (1), /* int_div_si */
784 COSTS_N_INSNS (1), /* int_div_di */
786 4 /* memory_latency */
789 /* Costs to use when optimizing for speed, indexed by processor. */
790 static const struct mips_rtx_cost_data
791 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
793 COSTS_N_INSNS (2), /* fp_add */
794 COSTS_N_INSNS (4), /* fp_mult_sf */
795 COSTS_N_INSNS (5), /* fp_mult_df */
796 COSTS_N_INSNS (12), /* fp_div_sf */
797 COSTS_N_INSNS (19), /* fp_div_df */
798 COSTS_N_INSNS (12), /* int_mult_si */
799 COSTS_N_INSNS (12), /* int_mult_di */
800 COSTS_N_INSNS (35), /* int_div_si */
801 COSTS_N_INSNS (35), /* int_div_di */
803 4 /* memory_latency */
807 COSTS_N_INSNS (6), /* int_mult_si */
808 COSTS_N_INSNS (6), /* int_mult_di */
809 COSTS_N_INSNS (36), /* int_div_si */
810 COSTS_N_INSNS (36), /* int_div_di */
812 4 /* memory_latency */
816 COSTS_N_INSNS (36), /* int_mult_si */
817 COSTS_N_INSNS (36), /* int_mult_di */
818 COSTS_N_INSNS (37), /* int_div_si */
819 COSTS_N_INSNS (37), /* int_div_di */
821 4 /* memory_latency */
825 COSTS_N_INSNS (4), /* int_mult_si */
826 COSTS_N_INSNS (11), /* int_mult_di */
827 COSTS_N_INSNS (36), /* int_div_si */
828 COSTS_N_INSNS (68), /* int_div_di */
830 4 /* memory_latency */
833 COSTS_N_INSNS (4), /* fp_add */
834 COSTS_N_INSNS (4), /* fp_mult_sf */
835 COSTS_N_INSNS (5), /* fp_mult_df */
836 COSTS_N_INSNS (17), /* fp_div_sf */
837 COSTS_N_INSNS (32), /* fp_div_df */
838 COSTS_N_INSNS (4), /* int_mult_si */
839 COSTS_N_INSNS (11), /* int_mult_di */
840 COSTS_N_INSNS (36), /* int_div_si */
841 COSTS_N_INSNS (68), /* int_div_di */
843 4 /* memory_latency */
846 COSTS_N_INSNS (4), /* fp_add */
847 COSTS_N_INSNS (4), /* fp_mult_sf */
848 COSTS_N_INSNS (5), /* fp_mult_df */
849 COSTS_N_INSNS (17), /* fp_div_sf */
850 COSTS_N_INSNS (32), /* fp_div_df */
851 COSTS_N_INSNS (4), /* int_mult_si */
852 COSTS_N_INSNS (7), /* int_mult_di */
853 COSTS_N_INSNS (42), /* int_div_si */
854 COSTS_N_INSNS (72), /* int_div_di */
856 4 /* memory_latency */
860 COSTS_N_INSNS (5), /* int_mult_si */
861 COSTS_N_INSNS (5), /* int_mult_di */
862 COSTS_N_INSNS (41), /* int_div_si */
863 COSTS_N_INSNS (41), /* int_div_di */
865 4 /* memory_latency */
868 COSTS_N_INSNS (8), /* fp_add */
869 COSTS_N_INSNS (8), /* fp_mult_sf */
870 COSTS_N_INSNS (10), /* fp_mult_df */
871 COSTS_N_INSNS (34), /* fp_div_sf */
872 COSTS_N_INSNS (64), /* fp_div_df */
873 COSTS_N_INSNS (5), /* int_mult_si */
874 COSTS_N_INSNS (5), /* int_mult_di */
875 COSTS_N_INSNS (41), /* int_div_si */
876 COSTS_N_INSNS (41), /* int_div_di */
878 4 /* memory_latency */
881 COSTS_N_INSNS (4), /* fp_add */
882 COSTS_N_INSNS (4), /* fp_mult_sf */
883 COSTS_N_INSNS (5), /* fp_mult_df */
884 COSTS_N_INSNS (17), /* fp_div_sf */
885 COSTS_N_INSNS (32), /* fp_div_df */
886 COSTS_N_INSNS (5), /* int_mult_si */
887 COSTS_N_INSNS (5), /* int_mult_di */
888 COSTS_N_INSNS (41), /* int_div_si */
889 COSTS_N_INSNS (41), /* int_div_di */
891 4 /* memory_latency */
895 COSTS_N_INSNS (5), /* int_mult_si */
896 COSTS_N_INSNS (5), /* int_mult_di */
897 COSTS_N_INSNS (41), /* int_div_si */
898 COSTS_N_INSNS (41), /* int_div_di */
900 4 /* memory_latency */
903 COSTS_N_INSNS (8), /* fp_add */
904 COSTS_N_INSNS (8), /* fp_mult_sf */
905 COSTS_N_INSNS (10), /* fp_mult_df */
906 COSTS_N_INSNS (34), /* fp_div_sf */
907 COSTS_N_INSNS (64), /* fp_div_df */
908 COSTS_N_INSNS (5), /* int_mult_si */
909 COSTS_N_INSNS (5), /* int_mult_di */
910 COSTS_N_INSNS (41), /* int_div_si */
911 COSTS_N_INSNS (41), /* int_div_di */
913 4 /* memory_latency */
916 COSTS_N_INSNS (4), /* fp_add */
917 COSTS_N_INSNS (4), /* fp_mult_sf */
918 COSTS_N_INSNS (5), /* fp_mult_df */
919 COSTS_N_INSNS (17), /* fp_div_sf */
920 COSTS_N_INSNS (32), /* fp_div_df */
921 COSTS_N_INSNS (5), /* int_mult_si */
922 COSTS_N_INSNS (5), /* int_mult_di */
923 COSTS_N_INSNS (41), /* int_div_si */
924 COSTS_N_INSNS (41), /* int_div_di */
926 4 /* memory_latency */
929 COSTS_N_INSNS (6), /* fp_add */
930 COSTS_N_INSNS (6), /* fp_mult_sf */
931 COSTS_N_INSNS (7), /* fp_mult_df */
932 COSTS_N_INSNS (25), /* fp_div_sf */
933 COSTS_N_INSNS (48), /* fp_div_df */
934 COSTS_N_INSNS (5), /* int_mult_si */
935 COSTS_N_INSNS (5), /* int_mult_di */
936 COSTS_N_INSNS (41), /* int_div_si */
937 COSTS_N_INSNS (41), /* int_div_di */
939 4 /* memory_latency */
956 COSTS_N_INSNS (5), /* int_mult_si */
957 COSTS_N_INSNS (5), /* int_mult_di */
958 COSTS_N_INSNS (72), /* int_div_si */
959 COSTS_N_INSNS (72), /* int_div_di */
961 4 /* memory_latency */
966 COSTS_N_INSNS (6), /* int_mult_si */
967 COSTS_N_INSNS (6), /* int_mult_di */
968 COSTS_N_INSNS (18), /* int_div_si */
969 COSTS_N_INSNS (35), /* int_div_di */
971 4 /* memory_latency */
975 COSTS_N_INSNS (6), /* fp_add */
976 COSTS_N_INSNS (6), /* fp_mult_sf */
977 COSTS_N_INSNS (7), /* fp_mult_df */
978 COSTS_N_INSNS (25), /* fp_div_sf */
979 COSTS_N_INSNS (48), /* fp_div_df */
980 COSTS_N_INSNS (6), /* int_mult_si */
981 COSTS_N_INSNS (6), /* int_mult_di */
982 COSTS_N_INSNS (18), /* int_div_si */
983 COSTS_N_INSNS (35), /* int_div_di */
985 4 /* memory_latency */
988 COSTS_N_INSNS (2), /* fp_add */
989 COSTS_N_INSNS (4), /* fp_mult_sf */
990 COSTS_N_INSNS (5), /* fp_mult_df */
991 COSTS_N_INSNS (12), /* fp_div_sf */
992 COSTS_N_INSNS (19), /* fp_div_df */
993 COSTS_N_INSNS (2), /* int_mult_si */
994 COSTS_N_INSNS (2), /* int_mult_di */
995 COSTS_N_INSNS (35), /* int_div_si */
996 COSTS_N_INSNS (35), /* int_div_di */
998 4 /* memory_latency */
1001 COSTS_N_INSNS (3), /* fp_add */
1002 COSTS_N_INSNS (5), /* fp_mult_sf */
1003 COSTS_N_INSNS (6), /* fp_mult_df */
1004 COSTS_N_INSNS (15), /* fp_div_sf */
1005 COSTS_N_INSNS (16), /* fp_div_df */
1006 COSTS_N_INSNS (17), /* int_mult_si */
1007 COSTS_N_INSNS (17), /* int_mult_di */
1008 COSTS_N_INSNS (38), /* int_div_si */
1009 COSTS_N_INSNS (38), /* int_div_di */
1010 2, /* branch_cost */
1011 6 /* memory_latency */
1014 COSTS_N_INSNS (6), /* fp_add */
1015 COSTS_N_INSNS (7), /* fp_mult_sf */
1016 COSTS_N_INSNS (8), /* fp_mult_df */
1017 COSTS_N_INSNS (23), /* fp_div_sf */
1018 COSTS_N_INSNS (36), /* fp_div_df */
1019 COSTS_N_INSNS (10), /* int_mult_si */
1020 COSTS_N_INSNS (10), /* int_mult_di */
1021 COSTS_N_INSNS (69), /* int_div_si */
1022 COSTS_N_INSNS (69), /* int_div_di */
1023 2, /* branch_cost */
1024 6 /* memory_latency */
1036 /* The only costs that appear to be updated here are
1037 integer multiplication. */
1039 COSTS_N_INSNS (4), /* int_mult_si */
1040 COSTS_N_INSNS (6), /* int_mult_di */
1041 COSTS_N_INSNS (69), /* int_div_si */
1042 COSTS_N_INSNS (69), /* int_div_di */
1043 1, /* branch_cost */
1044 4 /* memory_latency */
1059 COSTS_N_INSNS (6), /* fp_add */
1060 COSTS_N_INSNS (4), /* fp_mult_sf */
1061 COSTS_N_INSNS (5), /* fp_mult_df */
1062 COSTS_N_INSNS (23), /* fp_div_sf */
1063 COSTS_N_INSNS (36), /* fp_div_df */
1064 COSTS_N_INSNS (5), /* int_mult_si */
1065 COSTS_N_INSNS (5), /* int_mult_di */
1066 COSTS_N_INSNS (36), /* int_div_si */
1067 COSTS_N_INSNS (36), /* int_div_di */
1068 1, /* branch_cost */
1069 4 /* memory_latency */
1072 COSTS_N_INSNS (6), /* fp_add */
1073 COSTS_N_INSNS (5), /* fp_mult_sf */
1074 COSTS_N_INSNS (6), /* fp_mult_df */
1075 COSTS_N_INSNS (30), /* fp_div_sf */
1076 COSTS_N_INSNS (59), /* fp_div_df */
1077 COSTS_N_INSNS (3), /* int_mult_si */
1078 COSTS_N_INSNS (4), /* int_mult_di */
1079 COSTS_N_INSNS (42), /* int_div_si */
1080 COSTS_N_INSNS (74), /* int_div_di */
1081 1, /* branch_cost */
1082 4 /* memory_latency */
1085 COSTS_N_INSNS (6), /* fp_add */
1086 COSTS_N_INSNS (5), /* fp_mult_sf */
1087 COSTS_N_INSNS (6), /* fp_mult_df */
1088 COSTS_N_INSNS (30), /* fp_div_sf */
1089 COSTS_N_INSNS (59), /* fp_div_df */
1090 COSTS_N_INSNS (5), /* int_mult_si */
1091 COSTS_N_INSNS (9), /* int_mult_di */
1092 COSTS_N_INSNS (42), /* int_div_si */
1093 COSTS_N_INSNS (74), /* int_div_di */
1094 1, /* branch_cost */
1095 4 /* memory_latency */
1098 COSTS_N_INSNS (4), /* fp_add */
1099 COSTS_N_INSNS (4), /* fp_mult_sf */
1100 COSTS_N_INSNS (256), /* fp_mult_df */
1101 COSTS_N_INSNS (8), /* fp_div_sf */
1102 COSTS_N_INSNS (256), /* fp_div_df */
1103 COSTS_N_INSNS (4), /* int_mult_si */
1104 COSTS_N_INSNS (256), /* int_mult_di */
1105 COSTS_N_INSNS (37), /* int_div_si */
1106 COSTS_N_INSNS (256), /* int_div_di */
1107 1, /* branch_cost */
1108 4 /* memory_latency */
1111 /* The only costs that are changed here are
1112 integer multiplication. */
1113 COSTS_N_INSNS (6), /* fp_add */
1114 COSTS_N_INSNS (7), /* fp_mult_sf */
1115 COSTS_N_INSNS (8), /* fp_mult_df */
1116 COSTS_N_INSNS (23), /* fp_div_sf */
1117 COSTS_N_INSNS (36), /* fp_div_df */
1118 COSTS_N_INSNS (5), /* int_mult_si */
1119 COSTS_N_INSNS (9), /* int_mult_di */
1120 COSTS_N_INSNS (69), /* int_div_si */
1121 COSTS_N_INSNS (69), /* int_div_di */
1122 1, /* branch_cost */
1123 4 /* memory_latency */
1129 /* The only costs that are changed here are
1130 integer multiplication. */
1131 COSTS_N_INSNS (6), /* fp_add */
1132 COSTS_N_INSNS (7), /* fp_mult_sf */
1133 COSTS_N_INSNS (8), /* fp_mult_df */
1134 COSTS_N_INSNS (23), /* fp_div_sf */
1135 COSTS_N_INSNS (36), /* fp_div_df */
1136 COSTS_N_INSNS (3), /* int_mult_si */
1137 COSTS_N_INSNS (8), /* int_mult_di */
1138 COSTS_N_INSNS (69), /* int_div_si */
1139 COSTS_N_INSNS (69), /* int_div_di */
1140 1, /* branch_cost */
1141 4 /* memory_latency */
1144 COSTS_N_INSNS (2), /* fp_add */
1145 COSTS_N_INSNS (2), /* fp_mult_sf */
1146 COSTS_N_INSNS (2), /* fp_mult_df */
1147 COSTS_N_INSNS (12), /* fp_div_sf */
1148 COSTS_N_INSNS (19), /* fp_div_df */
1149 COSTS_N_INSNS (5), /* int_mult_si */
1150 COSTS_N_INSNS (9), /* int_mult_di */
1151 COSTS_N_INSNS (34), /* int_div_si */
1152 COSTS_N_INSNS (66), /* int_div_di */
1153 1, /* branch_cost */
1154 4 /* memory_latency */
1157 /* These costs are the same as the SB-1A below. */
1158 COSTS_N_INSNS (4), /* fp_add */
1159 COSTS_N_INSNS (4), /* fp_mult_sf */
1160 COSTS_N_INSNS (4), /* fp_mult_df */
1161 COSTS_N_INSNS (24), /* fp_div_sf */
1162 COSTS_N_INSNS (32), /* fp_div_df */
1163 COSTS_N_INSNS (3), /* int_mult_si */
1164 COSTS_N_INSNS (4), /* int_mult_di */
1165 COSTS_N_INSNS (36), /* int_div_si */
1166 COSTS_N_INSNS (68), /* int_div_di */
1167 1, /* branch_cost */
1168 4 /* memory_latency */
1171 /* These costs are the same as the SB-1 above. */
1172 COSTS_N_INSNS (4), /* fp_add */
1173 COSTS_N_INSNS (4), /* fp_mult_sf */
1174 COSTS_N_INSNS (4), /* fp_mult_df */
1175 COSTS_N_INSNS (24), /* fp_div_sf */
1176 COSTS_N_INSNS (32), /* fp_div_df */
1177 COSTS_N_INSNS (3), /* int_mult_si */
1178 COSTS_N_INSNS (4), /* int_mult_di */
1179 COSTS_N_INSNS (36), /* int_div_si */
1180 COSTS_N_INSNS (68), /* int_div_di */
1181 1, /* branch_cost */
1182 4 /* memory_latency */
1189 COSTS_N_INSNS (8), /* int_mult_si */
1190 COSTS_N_INSNS (8), /* int_mult_di */
1191 COSTS_N_INSNS (72), /* int_div_si */
1192 COSTS_N_INSNS (72), /* int_div_di */
1193 1, /* branch_cost */
1194 4 /* memory_latency */
1197 /* These costs are the same as 5KF above. */
1198 COSTS_N_INSNS (4), /* fp_add */
1199 COSTS_N_INSNS (4), /* fp_mult_sf */
1200 COSTS_N_INSNS (5), /* fp_mult_df */
1201 COSTS_N_INSNS (17), /* fp_div_sf */
1202 COSTS_N_INSNS (32), /* fp_div_df */
1203 COSTS_N_INSNS (4), /* int_mult_si */
1204 COSTS_N_INSNS (11), /* int_mult_di */
1205 COSTS_N_INSNS (36), /* int_div_si */
1206 COSTS_N_INSNS (68), /* int_div_di */
1207 1, /* branch_cost */
1208 4 /* memory_latency */
1211 COSTS_N_INSNS (4), /* fp_add */
1212 COSTS_N_INSNS (5), /* fp_mult_sf */
1213 COSTS_N_INSNS (5), /* fp_mult_df */
1214 COSTS_N_INSNS (17), /* fp_div_sf */
1215 COSTS_N_INSNS (17), /* fp_div_df */
1216 COSTS_N_INSNS (5), /* int_mult_si */
1217 COSTS_N_INSNS (5), /* int_mult_di */
1218 COSTS_N_INSNS (8), /* int_div_si */
1219 COSTS_N_INSNS (8), /* int_div_di */
1220 2, /* branch_cost */
1221 4 /* memory_latency */
1224 COSTS_N_INSNS (4), /* fp_add */
1225 COSTS_N_INSNS (4), /* fp_mult_sf */
1226 COSTS_N_INSNS (5), /* fp_mult_df */
1227 COSTS_N_INSNS (17), /* fp_div_sf */
1228 COSTS_N_INSNS (32), /* fp_div_df */
1229 COSTS_N_INSNS (5), /* int_mult_si */
1230 COSTS_N_INSNS (5), /* int_mult_di */
1231 COSTS_N_INSNS (41), /* int_div_si */
1232 COSTS_N_INSNS (41), /* int_div_di */
1233 1, /* branch_cost */
1234 4 /* memory_latency */
1237 COSTS_N_INSNS (4), /* fp_add */
1238 COSTS_N_INSNS (4), /* fp_mult_sf */
1239 COSTS_N_INSNS (5), /* fp_mult_df */
1240 COSTS_N_INSNS (17), /* fp_div_sf */
1241 COSTS_N_INSNS (32), /* fp_div_df */
1242 COSTS_N_INSNS (5), /* int_mult_si */
1243 COSTS_N_INSNS (5), /* int_mult_di */
1244 COSTS_N_INSNS (41), /* int_div_si */
1245 COSTS_N_INSNS (41), /* int_div_di */
1246 1, /* branch_cost */
1247 4 /* memory_latency */
1251 static rtx
mips_find_pic_call_symbol (rtx_insn
*, rtx
, bool);
1252 static int mips_register_move_cost (machine_mode
, reg_class_t
,
1254 static unsigned int mips_function_arg_boundary (machine_mode
, const_tree
);
1255 static machine_mode
mips_get_reg_raw_mode (int regno
);
1257 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1258 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1259 static GTY (()) hash_map
<nofree_string_hash
, bool> *mflip_mips16_htab
;
1261 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1262 mode, false if it should next add an attribute for the opposite mode. */
1263 static GTY(()) bool mips16_flipper
;
1265 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1266 for -mflip-mips16. Return true if it should use "mips16" and false if
1267 it should use "nomips16". */
1270 mflip_mips16_use_mips16_p (tree decl
)
1273 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1275 /* Use the opposite of the command-line setting for anonymous decls. */
1276 if (!DECL_NAME (decl
))
1277 return !base_is_mips16
;
1279 if (!mflip_mips16_htab
)
1280 mflip_mips16_htab
= hash_map
<nofree_string_hash
, bool>::create_ggc (37);
1282 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1285 bool *slot
= &mflip_mips16_htab
->get_or_insert (name
, &existed
);
1288 mips16_flipper
= !mips16_flipper
;
1289 *slot
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1294 /* Predicates to test for presence of "near" and "far"/"long_call"
1295 attributes on the given TYPE. */
1298 mips_near_type_p (const_tree type
)
1300 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1304 mips_far_type_p (const_tree type
)
1306 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1307 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1311 /* Check if the interrupt attribute is set for a function. */
1314 mips_interrupt_type_p (tree type
)
1316 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1319 /* Check if the attribute to use shadow register set is set for a function. */
1322 mips_use_shadow_register_set_p (tree type
)
1324 return lookup_attribute ("use_shadow_register_set",
1325 TYPE_ATTRIBUTES (type
)) != NULL
;
1328 /* Check if the attribute to keep interrupts masked is set for a function. */
1331 mips_keep_interrupts_masked_p (tree type
)
1333 return lookup_attribute ("keep_interrupts_masked",
1334 TYPE_ATTRIBUTES (type
)) != NULL
;
1337 /* Check if the attribute to use debug exception return is set for
1341 mips_use_debug_exception_return_p (tree type
)
1343 return lookup_attribute ("use_debug_exception_return",
1344 TYPE_ATTRIBUTES (type
)) != NULL
;
1347 /* Return the set of compression modes that are explicitly required
1348 by the attributes in ATTRIBUTES. */
1351 mips_get_compress_on_flags (tree attributes
)
1353 unsigned int flags
= 0;
1355 if (lookup_attribute ("mips16", attributes
) != NULL
)
1356 flags
|= MASK_MIPS16
;
1358 if (lookup_attribute ("micromips", attributes
) != NULL
)
1359 flags
|= MASK_MICROMIPS
;
1364 /* Return the set of compression modes that are explicitly forbidden
1365 by the attributes in ATTRIBUTES. */
1368 mips_get_compress_off_flags (tree attributes
)
1370 unsigned int flags
= 0;
1372 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1373 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1375 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1376 flags
|= MASK_MIPS16
;
1378 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1379 flags
|= MASK_MICROMIPS
;
1384 /* Return the compression mode that should be used for function DECL.
1385 Return the ambient setting if DECL is null. */
1388 mips_get_compress_mode (tree decl
)
1390 unsigned int flags
, force_on
;
1392 flags
= mips_base_compression_flags
;
1395 /* Nested functions must use the same frame pointer as their
1396 parent and must therefore use the same ISA mode. */
1397 tree parent
= decl_function_context (decl
);
1400 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1403 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1408 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1412 mips_get_compress_on_name (unsigned int flags
)
1414 if (flags
== MASK_MIPS16
)
1419 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1423 mips_get_compress_off_name (unsigned int flags
)
1425 if (flags
== MASK_MIPS16
)
1427 if (flags
== MASK_MICROMIPS
)
1428 return "nomicromips";
1429 return "nocompression";
1432 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1435 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1437 /* Disallow mixed near/far attributes. */
1438 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1440 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1445 /* Implement TARGET_INSERT_ATTRIBUTES. */
1448 mips_insert_attributes (tree decl
, tree
*attributes
)
1451 unsigned int compression_flags
, nocompression_flags
;
1453 /* Check for "mips16" and "nomips16" attributes. */
1454 compression_flags
= mips_get_compress_on_flags (*attributes
);
1455 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1457 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1459 if (nocompression_flags
)
1460 error ("%qs attribute only applies to functions",
1461 mips_get_compress_off_name (nocompression_flags
));
1463 if (compression_flags
)
1464 error ("%qs attribute only applies to functions",
1465 mips_get_compress_on_name (nocompression_flags
));
1469 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1470 nocompression_flags
|=
1471 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1473 if (compression_flags
&& nocompression_flags
)
1474 error ("%qE cannot have both %qs and %qs attributes",
1475 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1476 mips_get_compress_off_name (nocompression_flags
));
1478 if (compression_flags
& MASK_MIPS16
1479 && compression_flags
& MASK_MICROMIPS
)
1480 error ("%qE cannot have both %qs and %qs attributes",
1481 DECL_NAME (decl
), "mips16", "micromips");
1483 if (TARGET_FLIP_MIPS16
1484 && !DECL_ARTIFICIAL (decl
)
1485 && compression_flags
== 0
1486 && nocompression_flags
== 0)
1488 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1489 "mips16" attribute, arbitrarily pick one. We must pick the same
1490 setting for duplicate declarations of a function. */
1491 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1492 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1493 name
= "nomicromips";
1494 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1499 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1502 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1506 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1507 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1509 error ("%qE redeclared with conflicting %qs attributes",
1510 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1512 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1513 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1515 error ("%qE redeclared with conflicting %qs attributes",
1516 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1518 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1519 DECL_ATTRIBUTES (newdecl
));
1522 /* Implement TARGET_CAN_INLINE_P. */
1525 mips_can_inline_p (tree caller
, tree callee
)
1527 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1529 return default_target_can_inline_p (caller
, callee
);
1532 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1533 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1536 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1538 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1540 *base_ptr
= XEXP (x
, 0);
1541 *offset_ptr
= INTVAL (XEXP (x
, 1));
1550 static unsigned int mips_build_integer (struct mips_integer_op
*,
1551 unsigned HOST_WIDE_INT
);
1553 /* A subroutine of mips_build_integer, with the same interface.
1554 Assume that the final action in the sequence should be a left shift. */
1557 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1559 unsigned int i
, shift
;
1561 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1562 since signed numbers are easier to load than unsigned ones. */
1564 while ((value
& 1) == 0)
1565 value
/= 2, shift
++;
1567 i
= mips_build_integer (codes
, value
);
1568 codes
[i
].code
= ASHIFT
;
1569 codes
[i
].value
= shift
;
1573 /* As for mips_build_shift, but assume that the final action will be
1574 an IOR or PLUS operation. */
1577 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1579 unsigned HOST_WIDE_INT high
;
1582 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1583 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1585 /* The constant is too complex to load with a simple LUI/ORI pair,
1586 so we want to give the recursive call as many trailing zeros as
1587 possible. In this case, we know bit 16 is set and that the
1588 low 16 bits form a negative number. If we subtract that number
1589 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1590 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1591 codes
[i
].code
= PLUS
;
1592 codes
[i
].value
= CONST_LOW_PART (value
);
1596 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1597 bits gives a value with at least 17 trailing zeros. */
1598 i
= mips_build_integer (codes
, high
);
1599 codes
[i
].code
= IOR
;
1600 codes
[i
].value
= value
& 0xffff;
1605 /* Fill CODES with a sequence of rtl operations to load VALUE.
1606 Return the number of operations needed. */
1609 mips_build_integer (struct mips_integer_op
*codes
,
1610 unsigned HOST_WIDE_INT value
)
1612 if (SMALL_OPERAND (value
)
1613 || SMALL_OPERAND_UNSIGNED (value
)
1614 || LUI_OPERAND (value
))
1616 /* The value can be loaded with a single instruction. */
1617 codes
[0].code
= UNKNOWN
;
1618 codes
[0].value
= value
;
1621 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1623 /* Either the constant is a simple LUI/ORI combination or its
1624 lowest bit is set. We don't want to shift in this case. */
1625 return mips_build_lower (codes
, value
);
1627 else if ((value
& 0xffff) == 0)
1629 /* The constant will need at least three actions. The lowest
1630 16 bits are clear, so the final action will be a shift. */
1631 return mips_build_shift (codes
, value
);
1635 /* The final action could be a shift, add or inclusive OR.
1636 Rather than use a complex condition to select the best
1637 approach, try both mips_build_shift and mips_build_lower
1638 and pick the one that gives the shortest sequence.
1639 Note that this case is only used once per constant. */
1640 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1641 unsigned int cost
, alt_cost
;
1643 cost
= mips_build_shift (codes
, value
);
1644 alt_cost
= mips_build_lower (alt_codes
, value
);
1645 if (alt_cost
< cost
)
1647 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1654 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1657 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1659 return mips_const_insns (x
) > 0;
1662 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1665 mips16_stub_function (const char *name
)
1669 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1670 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1674 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1675 support function. */
1678 mips16_stub_call_address (mips_one_only_stub
*stub
)
1680 rtx fn
= mips16_stub_function (stub
->get_name ());
1681 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1682 if (!call_insn_operand (fn
, VOIDmode
))
1683 fn
= force_reg (Pmode
, fn
);
1687 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1689 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1691 virtual const char *get_name ();
1692 virtual void output_body ();
1696 mips16_rdhwr_one_only_stub::get_name ()
1698 return "__mips16_rdhwr";
1702 mips16_rdhwr_one_only_stub::output_body ()
1704 fprintf (asm_out_file
,
1706 "\t.set\tmips32r2\n"
1707 "\t.set\tnoreorder\n"
1713 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1714 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1716 virtual const char *get_name ();
1717 virtual void output_body ();
1721 mips16_get_fcsr_one_only_stub::get_name ()
1723 return "__mips16_get_fcsr";
1727 mips16_get_fcsr_one_only_stub::output_body ()
1729 fprintf (asm_out_file
,
1731 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1734 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1735 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1737 virtual const char *get_name ();
1738 virtual void output_body ();
1742 mips16_set_fcsr_one_only_stub::get_name ()
1744 return "__mips16_set_fcsr";
1748 mips16_set_fcsr_one_only_stub::output_body ()
1750 fprintf (asm_out_file
,
1752 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1755 /* Return true if symbols of type TYPE require a GOT access. */
1758 mips_got_symbol_type_p (enum mips_symbol_type type
)
1762 case SYMBOL_GOT_PAGE_OFST
:
1763 case SYMBOL_GOT_DISP
:
1771 /* Return true if X is a thread-local symbol. */
1774 mips_tls_symbol_p (rtx x
)
1776 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1779 /* Return true if SYMBOL_REF X is associated with a global symbol
1780 (in the STB_GLOBAL sense). */
1783 mips_global_symbol_p (const_rtx x
)
1785 const_tree decl
= SYMBOL_REF_DECL (x
);
1788 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1790 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1791 or weak symbols. Relocations in the object file will be against
1792 the target symbol, so it's that symbol's binding that matters here. */
1793 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1796 /* Return true if function X is a libgcc MIPS16 stub function. */
1799 mips16_stub_function_p (const_rtx x
)
1801 return (GET_CODE (x
) == SYMBOL_REF
1802 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1805 /* Return true if function X is a locally-defined and locally-binding
1809 mips16_local_function_p (const_rtx x
)
1811 return (GET_CODE (x
) == SYMBOL_REF
1812 && SYMBOL_REF_LOCAL_P (x
)
1813 && !SYMBOL_REF_EXTERNAL_P (x
)
1814 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1817 /* Return true if SYMBOL_REF X binds locally. */
1820 mips_symbol_binds_local_p (const_rtx x
)
1822 return (SYMBOL_REF_DECL (x
)
1823 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1824 : SYMBOL_REF_LOCAL_P (x
));
1827 /* Return true if rtx constants of mode MODE should be put into a small
1831 mips_rtx_constant_in_small_data_p (machine_mode mode
)
1833 return (!TARGET_EMBEDDED_DATA
1834 && TARGET_LOCAL_SDATA
1835 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1838 /* Return true if X should not be moved directly into register $25.
1839 We need this because many versions of GAS will treat "la $25,foo" as
1840 part of a call sequence and so allow a global "foo" to be lazily bound. */
1843 mips_dangerous_for_la25_p (rtx x
)
1845 return (!TARGET_EXPLICIT_RELOCS
1847 && GET_CODE (x
) == SYMBOL_REF
1848 && mips_global_symbol_p (x
));
1851 /* Return true if calls to X might need $25 to be valid on entry. */
1854 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1856 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1859 /* MIPS16 stub functions are guaranteed not to use $25. */
1860 if (mips16_stub_function_p (x
))
1863 if (GET_CODE (x
) == SYMBOL_REF
)
1865 /* If PLTs and copy relocations are available, the static linker
1866 will make sure that $25 is valid on entry to the target function. */
1867 if (TARGET_ABICALLS_PIC0
)
1870 /* Locally-defined functions use absolute accesses to set up
1871 the global pointer. */
1872 if (TARGET_ABSOLUTE_ABICALLS
1873 && mips_symbol_binds_local_p (x
)
1874 && !SYMBOL_REF_EXTERNAL_P (x
))
1881 /* Return the method that should be used to access SYMBOL_REF or
1882 LABEL_REF X in context CONTEXT. */
1884 static enum mips_symbol_type
1885 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1888 return SYMBOL_GOT_DISP
;
1890 if (GET_CODE (x
) == LABEL_REF
)
1892 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1893 code and if we know that the label is in the current function's
1894 text section. LABEL_REFs are used for jump tables as well as
1895 text labels, so we must check whether jump tables live in the
1897 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1898 && !LABEL_REF_NONLOCAL_P (x
))
1899 return SYMBOL_PC_RELATIVE
;
1901 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1902 return SYMBOL_GOT_PAGE_OFST
;
1904 return SYMBOL_ABSOLUTE
;
1907 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1909 if (SYMBOL_REF_TLS_MODEL (x
))
1912 if (CONSTANT_POOL_ADDRESS_P (x
))
1914 if (TARGET_MIPS16_TEXT_LOADS
)
1915 return SYMBOL_PC_RELATIVE
;
1917 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1918 return SYMBOL_PC_RELATIVE
;
1920 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1921 return SYMBOL_GP_RELATIVE
;
1924 /* Do not use small-data accesses for weak symbols; they may end up
1926 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1927 return SYMBOL_GP_RELATIVE
;
1929 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1931 if (TARGET_ABICALLS_PIC2
1932 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1934 /* There are three cases to consider:
1936 - o32 PIC (either with or without explicit relocs)
1937 - n32/n64 PIC without explicit relocs
1938 - n32/n64 PIC with explicit relocs
1940 In the first case, both local and global accesses will use an
1941 R_MIPS_GOT16 relocation. We must correctly predict which of
1942 the two semantics (local or global) the assembler and linker
1943 will apply. The choice depends on the symbol's binding rather
1944 than its visibility.
1946 In the second case, the assembler will not use R_MIPS_GOT16
1947 relocations, but it chooses between local and global accesses
1948 in the same way as for o32 PIC.
1950 In the third case we have more freedom since both forms of
1951 access will work for any kind of symbol. However, there seems
1952 little point in doing things differently. */
1953 if (mips_global_symbol_p (x
))
1954 return SYMBOL_GOT_DISP
;
1956 return SYMBOL_GOT_PAGE_OFST
;
1959 return SYMBOL_ABSOLUTE
;
1962 /* Classify the base of symbolic expression X, given that X appears in
1965 static enum mips_symbol_type
1966 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1970 split_const (x
, &x
, &offset
);
1971 if (UNSPEC_ADDRESS_P (x
))
1972 return UNSPEC_ADDRESS_TYPE (x
);
1974 return mips_classify_symbol (x
, context
);
1977 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1978 is the alignment in bytes of SYMBOL_REF X. */
1981 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1983 HOST_WIDE_INT align
;
1985 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1986 return IN_RANGE (offset
, 0, align
- 1);
1989 /* Return true if X is a symbolic constant that can be used in context
1990 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1993 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1994 enum mips_symbol_type
*symbol_type
)
1998 split_const (x
, &x
, &offset
);
1999 if (UNSPEC_ADDRESS_P (x
))
2001 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
2002 x
= UNSPEC_ADDRESS (x
);
2004 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
2006 *symbol_type
= mips_classify_symbol (x
, context
);
2007 if (*symbol_type
== SYMBOL_TLS
)
2013 if (offset
== const0_rtx
)
2016 /* Check whether a nonzero offset is valid for the underlying
2018 switch (*symbol_type
)
2020 case SYMBOL_ABSOLUTE
:
2021 case SYMBOL_64_HIGH
:
2024 /* If the target has 64-bit pointers and the object file only
2025 supports 32-bit symbols, the values of those symbols will be
2026 sign-extended. In this case we can't allow an arbitrary offset
2027 in case the 32-bit value X + OFFSET has a different sign from X. */
2028 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
2029 return offset_within_block_p (x
, INTVAL (offset
));
2031 /* In other cases the relocations can handle any offset. */
2034 case SYMBOL_PC_RELATIVE
:
2035 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2036 In this case, we no longer have access to the underlying constant,
2037 but the original symbol-based access was known to be valid. */
2038 if (GET_CODE (x
) == LABEL_REF
)
2043 case SYMBOL_GP_RELATIVE
:
2044 /* Make sure that the offset refers to something within the
2045 same object block. This should guarantee that the final
2046 PC- or GP-relative offset is within the 16-bit limit. */
2047 return offset_within_block_p (x
, INTVAL (offset
));
2049 case SYMBOL_GOT_PAGE_OFST
:
2050 case SYMBOL_GOTOFF_PAGE
:
2051 /* If the symbol is global, the GOT entry will contain the symbol's
2052 address, and we will apply a 16-bit offset after loading it.
2053 If the symbol is local, the linker should provide enough local
2054 GOT entries for a 16-bit offset, but larger offsets may lead
2056 return SMALL_INT (offset
);
2060 /* There is no carry between the HI and LO REL relocations, so the
2061 offset is only valid if we know it won't lead to such a carry. */
2062 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2064 case SYMBOL_GOT_DISP
:
2065 case SYMBOL_GOTOFF_DISP
:
2066 case SYMBOL_GOTOFF_CALL
:
2067 case SYMBOL_GOTOFF_LOADGP
:
2070 case SYMBOL_GOTTPREL
:
2078 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2079 single instruction. We rely on the fact that, in the worst case,
2080 all instructions involved in a MIPS16 address calculation are usually
2084 mips_symbol_insns_1 (enum mips_symbol_type type
, machine_mode mode
)
2086 if (mips_use_pcrel_pool_p
[(int) type
])
2088 if (mode
== MAX_MACHINE_MODE
)
2089 /* LEAs will be converted into constant-pool references by
2091 type
= SYMBOL_PC_RELATIVE
;
2093 /* The constant must be loaded and then dereferenced. */
2099 case SYMBOL_ABSOLUTE
:
2100 /* When using 64-bit symbols, we need 5 preparatory instructions,
2103 lui $at,%highest(symbol)
2104 daddiu $at,$at,%higher(symbol)
2106 daddiu $at,$at,%hi(symbol)
2109 The final address is then $at + %lo(symbol). With 32-bit
2110 symbols we just need a preparatory LUI for normal mode and
2111 a preparatory LI and SLL for MIPS16. */
2112 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2114 case SYMBOL_GP_RELATIVE
:
2115 /* Treat GP-relative accesses as taking a single instruction on
2116 MIPS16 too; the copy of $gp can often be shared. */
2119 case SYMBOL_PC_RELATIVE
:
2120 /* PC-relative constants can be only be used with ADDIUPC,
2121 DADDIUPC, LWPC and LDPC. */
2122 if (mode
== MAX_MACHINE_MODE
2123 || GET_MODE_SIZE (mode
) == 4
2124 || GET_MODE_SIZE (mode
) == 8)
2127 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2130 case SYMBOL_GOT_DISP
:
2131 /* The constant will have to be loaded from the GOT before it
2132 is used in an address. */
2133 if (mode
!= MAX_MACHINE_MODE
)
2138 case SYMBOL_GOT_PAGE_OFST
:
2139 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2140 local/global classification is accurate. The worst cases are:
2142 (1) For local symbols when generating o32 or o64 code. The assembler
2148 ...and the final address will be $at + %lo(symbol).
2150 (2) For global symbols when -mxgot. The assembler will use:
2152 lui $at,%got_hi(symbol)
2155 ...and the final address will be $at + %got_lo(symbol). */
2158 case SYMBOL_GOTOFF_PAGE
:
2159 case SYMBOL_GOTOFF_DISP
:
2160 case SYMBOL_GOTOFF_CALL
:
2161 case SYMBOL_GOTOFF_LOADGP
:
2162 case SYMBOL_64_HIGH
:
2168 case SYMBOL_GOTTPREL
:
2171 /* A 16-bit constant formed by a single relocation, or a 32-bit
2172 constant formed from a high 16-bit relocation and a low 16-bit
2173 relocation. Use mips_split_p to determine which. 32-bit
2174 constants need an "lui; addiu" sequence for normal mode and
2175 an "li; sll; addiu" sequence for MIPS16 mode. */
2176 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2179 /* We don't treat a bare TLS symbol as a constant. */
2185 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2186 to load symbols of type TYPE into a register. Return 0 if the given
2187 type of symbol cannot be used as an immediate operand.
2189 Otherwise, return the number of instructions needed to load or store
2190 values of mode MODE to or from addresses of type TYPE. Return 0 if
2191 the given type of symbol is not valid in addresses.
2193 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2196 mips_symbol_insns (enum mips_symbol_type type
, machine_mode mode
)
2198 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2201 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2204 mips_cannot_force_const_mem (machine_mode mode
, rtx x
)
2206 enum mips_symbol_type type
;
2209 /* There is no assembler syntax for expressing an address-sized
2211 if (GET_CODE (x
) == HIGH
)
2214 /* As an optimization, reject constants that mips_legitimize_move
2217 Suppose we have a multi-instruction sequence that loads constant C
2218 into register R. If R does not get allocated a hard register, and
2219 R is used in an operand that allows both registers and memory
2220 references, reload will consider forcing C into memory and using
2221 one of the instruction's memory alternatives. Returning false
2222 here will force it to use an input reload instead. */
2223 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2226 split_const (x
, &base
, &offset
);
2227 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2229 /* See whether we explicitly want these symbols in the pool. */
2230 if (mips_use_pcrel_pool_p
[(int) type
])
2233 /* The same optimization as for CONST_INT. */
2234 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2237 /* If MIPS16 constant pools live in the text section, they should
2238 not refer to anything that might need run-time relocation. */
2239 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2243 /* TLS symbols must be computed by mips_legitimize_move. */
2244 if (tls_referenced_p (x
))
2250 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2251 constants when we're using a per-function constant pool. */
2254 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED
,
2255 const_rtx x ATTRIBUTE_UNUSED
)
2257 return !TARGET_MIPS16_PCREL_LOADS
;
2260 /* Return true if register REGNO is a valid base register for mode MODE.
2261 STRICT_P is true if REG_OK_STRICT is in effect. */
2264 mips_regno_mode_ok_for_base_p (int regno
, machine_mode mode
,
2267 if (!HARD_REGISTER_NUM_P (regno
))
2271 regno
= reg_renumber
[regno
];
2274 /* These fake registers will be eliminated to either the stack or
2275 hard frame pointer, both of which are usually valid base registers.
2276 Reload deals with the cases where the eliminated form isn't valid. */
2277 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2280 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2281 values, nothing smaller. */
2282 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2283 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2285 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2288 /* Return true if X is a valid base register for mode MODE.
2289 STRICT_P is true if REG_OK_STRICT is in effect. */
2292 mips_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
2294 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2298 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2301 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2302 can address a value of mode MODE. */
2305 mips_valid_offset_p (rtx x
, machine_mode mode
)
2307 /* Check that X is a signed 16-bit number. */
2308 if (!const_arith_operand (x
, Pmode
))
2311 /* We may need to split multiword moves, so make sure that every word
2313 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2314 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2320 /* Return true if a LO_SUM can address a value of mode MODE when the
2321 LO_SUM symbol has type SYMBOL_TYPE. */
2324 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, machine_mode mode
)
2326 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2328 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2331 /* Check that there is a known low-part relocation. */
2332 if (mips_lo_relocs
[symbol_type
] == NULL
)
2335 /* We may need to split multiword moves, so make sure that each word
2336 can be accessed without inducing a carry. This is mainly needed
2337 for o64, which has historically only guaranteed 64-bit alignment
2338 for 128-bit types. */
2339 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2340 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2346 /* Return true if X is a valid address for machine mode MODE. If it is,
2347 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2351 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2352 machine_mode mode
, bool strict_p
)
2354 switch (GET_CODE (x
))
2358 info
->type
= ADDRESS_REG
;
2360 info
->offset
= const0_rtx
;
2361 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2364 info
->type
= ADDRESS_REG
;
2365 info
->reg
= XEXP (x
, 0);
2366 info
->offset
= XEXP (x
, 1);
2367 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2368 && mips_valid_offset_p (info
->offset
, mode
));
2371 info
->type
= ADDRESS_LO_SUM
;
2372 info
->reg
= XEXP (x
, 0);
2373 info
->offset
= XEXP (x
, 1);
2374 /* We have to trust the creator of the LO_SUM to do something vaguely
2375 sane. Target-independent code that creates a LO_SUM should also
2376 create and verify the matching HIGH. Target-independent code that
2377 adds an offset to a LO_SUM must prove that the offset will not
2378 induce a carry. Failure to do either of these things would be
2379 a bug, and we are not required to check for it here. The MIPS
2380 backend itself should only create LO_SUMs for valid symbolic
2381 constants, with the high part being either a HIGH or a copy
2384 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2385 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2386 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2389 /* Small-integer addresses don't occur very often, but they
2390 are legitimate if $0 is a valid base register. */
2391 info
->type
= ADDRESS_CONST_INT
;
2392 return !TARGET_MIPS16
&& SMALL_INT (x
);
2397 info
->type
= ADDRESS_SYMBOLIC
;
2398 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2400 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2401 && !mips_split_p
[info
->symbol_type
]);
2408 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2411 mips_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2413 struct mips_address_info addr
;
2415 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2418 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2421 mips_stack_address_p (rtx x
, machine_mode mode
)
2423 struct mips_address_info addr
;
2425 return (mips_classify_address (&addr
, x
, mode
, false)
2426 && addr
.type
== ADDRESS_REG
2427 && addr
.reg
== stack_pointer_rtx
);
2430 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2431 address instruction. Note that such addresses are not considered
2432 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2433 is so restricted. */
2436 mips_lwxs_address_p (rtx addr
)
2439 && GET_CODE (addr
) == PLUS
2440 && REG_P (XEXP (addr
, 1)))
2442 rtx offset
= XEXP (addr
, 0);
2443 if (GET_CODE (offset
) == MULT
2444 && REG_P (XEXP (offset
, 0))
2445 && CONST_INT_P (XEXP (offset
, 1))
2446 && INTVAL (XEXP (offset
, 1)) == 4)
2452 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2453 indexed address instruction. Note that such addresses are
2454 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2455 sense, because their use is so restricted. */
2458 mips_lx_address_p (rtx addr
, machine_mode mode
)
2460 if (GET_CODE (addr
) != PLUS
2461 || !REG_P (XEXP (addr
, 0))
2462 || !REG_P (XEXP (addr
, 1)))
2464 if (ISA_HAS_LBX
&& mode
== QImode
)
2466 if (ISA_HAS_LHX
&& mode
== HImode
)
2468 if (ISA_HAS_LWX
&& mode
== SImode
)
2470 if (ISA_HAS_LDX
&& mode
== DImode
)
2475 /* Return true if a value at OFFSET bytes from base register BASE can be
2476 accessed using an unextended MIPS16 instruction. MODE is the mode of
2479 Usually the offset in an unextended instruction is a 5-bit field.
2480 The offset is unsigned and shifted left once for LH and SH, twice
2481 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2482 an 8-bit immediate field that's shifted left twice. */
2485 mips16_unextended_reference_p (machine_mode mode
, rtx base
,
2486 unsigned HOST_WIDE_INT offset
)
2488 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2490 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2491 return offset
< 256U * GET_MODE_SIZE (mode
);
2492 return offset
< 32U * GET_MODE_SIZE (mode
);
2497 /* Return the number of instructions needed to load or store a value
2498 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2499 length of one instruction. Return 0 if X isn't valid for MODE.
2500 Assume that multiword moves may need to be split into word moves
2501 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2505 mips_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
2507 struct mips_address_info addr
;
2510 /* BLKmode is used for single unaligned loads and stores and should
2511 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2512 meaningless, so we have to single it out as a special case one way
2514 if (mode
!= BLKmode
&& might_split_p
)
2515 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2519 if (mips_classify_address (&addr
, x
, mode
, false))
2524 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2525 UINTVAL (addr
.offset
)))
2529 case ADDRESS_LO_SUM
:
2530 return TARGET_MIPS16
? factor
* 2 : factor
;
2532 case ADDRESS_CONST_INT
:
2535 case ADDRESS_SYMBOLIC
:
2536 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2541 /* Return true if X fits within an unsigned field of BITS bits that is
2542 shifted left SHIFT bits before being used. */
2545 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2547 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2550 /* Return true if X fits within a signed field of BITS bits that is
2551 shifted left SHIFT bits before being used. */
2554 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2556 x
+= 1 << (bits
+ shift
- 1);
2557 return mips_unsigned_immediate_p (x
, bits
, shift
);
2560 /* Return true if X is legitimate for accessing values of mode MODE,
2561 if it is based on a MIPS16 register, and if the offset satisfies
2562 OFFSET_PREDICATE. */
2565 m16_based_address_p (rtx x
, machine_mode mode
,
2566 insn_operand_predicate_fn offset_predicate
)
2568 struct mips_address_info addr
;
2570 return (mips_classify_address (&addr
, x
, mode
, false)
2571 && addr
.type
== ADDRESS_REG
2572 && M16_REG_P (REGNO (addr
.reg
))
2573 && offset_predicate (addr
.offset
, mode
));
2576 /* Return true if X is a legitimate address that conforms to the requirements
2577 for a microMIPS LWSP or SWSP insn. */
2580 lwsp_swsp_address_p (rtx x
, machine_mode mode
)
2582 struct mips_address_info addr
;
2584 return (mips_classify_address (&addr
, x
, mode
, false)
2585 && addr
.type
== ADDRESS_REG
2586 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2587 && uw5_operand (addr
.offset
, mode
));
2590 /* Return true if X is a legitimate address with a 12-bit offset.
2591 MODE is the mode of the value being accessed. */
2594 umips_12bit_offset_address_p (rtx x
, machine_mode mode
)
2596 struct mips_address_info addr
;
2598 return (mips_classify_address (&addr
, x
, mode
, false)
2599 && addr
.type
== ADDRESS_REG
2600 && CONST_INT_P (addr
.offset
)
2601 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2604 /* Return true if X is a legitimate address with a 9-bit offset.
2605 MODE is the mode of the value being accessed. */
2608 mips_9bit_offset_address_p (rtx x
, machine_mode mode
)
2610 struct mips_address_info addr
;
2612 return (mips_classify_address (&addr
, x
, mode
, false)
2613 && addr
.type
== ADDRESS_REG
2614 && CONST_INT_P (addr
.offset
)
2615 && MIPS_9BIT_OFFSET_P (INTVAL (addr
.offset
)));
2618 /* Return the number of instructions needed to load constant X,
2619 assuming that BASE_INSN_LENGTH is the length of one instruction.
2620 Return 0 if X isn't a valid constant. */
2623 mips_const_insns (rtx x
)
2625 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2626 enum mips_symbol_type symbol_type
;
2629 switch (GET_CODE (x
))
2632 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2634 || !mips_split_p
[symbol_type
])
2637 /* This is simply an LUI for normal mode. It is an extended
2638 LI followed by an extended SLL for MIPS16. */
2639 return TARGET_MIPS16
? 4 : 1;
2643 /* Unsigned 8-bit constants can be loaded using an unextended
2644 LI instruction. Unsigned 16-bit constants can be loaded
2645 using an extended LI. Negative constants must be loaded
2646 using LI and then negated. */
2647 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2648 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2649 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2650 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2653 return mips_build_integer (codes
, INTVAL (x
));
2657 /* Allow zeros for normal mode, where we can use $0. */
2658 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2664 /* See if we can refer to X directly. */
2665 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2666 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2668 /* Otherwise try splitting the constant into a base and offset.
2669 If the offset is a 16-bit value, we can load the base address
2670 into a register and then use (D)ADDIU to add in the offset.
2671 If the offset is larger, we can load the base and offset
2672 into separate registers and add them together with (D)ADDU.
2673 However, the latter is only possible before reload; during
2674 and after reload, we must have the option of forcing the
2675 constant into the pool instead. */
2676 split_const (x
, &x
, &offset
);
2679 int n
= mips_const_insns (x
);
2682 if (SMALL_INT (offset
))
2684 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2685 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2692 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2700 /* X is a doubleword constant that can be handled by splitting it into
2701 two words and loading each word separately. Return the number of
2702 instructions required to do this, assuming that BASE_INSN_LENGTH
2703 is the length of one instruction. */
2706 mips_split_const_insns (rtx x
)
2708 unsigned int low
, high
;
2710 low
= mips_const_insns (mips_subword (x
, false));
2711 high
= mips_const_insns (mips_subword (x
, true));
2712 gcc_assert (low
> 0 && high
> 0);
2716 /* Return the number of instructions needed to implement INSN,
2717 given that it loads from or stores to MEM. Assume that
2718 BASE_INSN_LENGTH is the length of one instruction. */
2721 mips_load_store_insns (rtx mem
, rtx_insn
*insn
)
2727 gcc_assert (MEM_P (mem
));
2728 mode
= GET_MODE (mem
);
2730 /* Try to prove that INSN does not need to be split. */
2731 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2734 set
= single_set (insn
);
2735 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2736 might_split_p
= false;
2739 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2742 /* Return the number of instructions needed for an integer division,
2743 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2746 mips_idiv_insns (void)
2751 if (TARGET_CHECK_ZERO_DIV
)
2753 if (GENERATE_DIVIDE_TRAPS
)
2759 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2764 /* Emit a move from SRC to DEST. Assume that the move expanders can
2765 handle all moves if !can_create_pseudo_p (). The distinction is
2766 important because, unlike emit_move_insn, the move expanders know
2767 how to force Pmode objects into the constant pool even when the
2768 constant pool address is not itself legitimate. */
2771 mips_emit_move (rtx dest
, rtx src
)
2773 return (can_create_pseudo_p ()
2774 ? emit_move_insn (dest
, src
)
2775 : emit_move_insn_1 (dest
, src
));
2778 /* Emit a move from SRC to DEST, splitting compound moves into individual
2779 instructions. SPLIT_TYPE is the type of split to perform. */
2782 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2784 if (mips_split_move_p (dest
, src
, split_type
))
2785 mips_split_move (dest
, src
, split_type
);
2787 mips_emit_move (dest
, src
);
2790 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2793 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2795 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2798 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2799 Return that new register. */
2802 mips_force_unary (machine_mode mode
, enum rtx_code code
, rtx op0
)
2806 reg
= gen_reg_rtx (mode
);
2807 mips_emit_unary (code
, reg
, op0
);
2811 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2814 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2816 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (code
, GET_MODE (target
),
2820 /* Compute (CODE OP0 OP1) and store the result in a new register
2821 of mode MODE. Return that new register. */
2824 mips_force_binary (machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2828 reg
= gen_reg_rtx (mode
);
2829 mips_emit_binary (code
, reg
, op0
, op1
);
2833 /* Copy VALUE to a register and return that register. If new pseudos
2834 are allowed, copy it into a new register, otherwise use DEST. */
2837 mips_force_temporary (rtx dest
, rtx value
)
2839 if (can_create_pseudo_p ())
2840 return force_reg (Pmode
, value
);
2843 mips_emit_move (dest
, value
);
2848 /* Emit a call sequence with call pattern PATTERN and return the call
2849 instruction itself (which is not necessarily the last instruction
2850 emitted). ORIG_ADDR is the original, unlegitimized address,
2851 ADDR is the legitimized form, and LAZY_P is true if the call
2852 address is lazily-bound. */
2855 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2860 insn
= emit_call_insn (pattern
);
2862 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2864 /* MIPS16 JALRs only take MIPS16 registers. If the target
2865 function requires $25 to be valid on entry, we must copy it
2866 there separately. The move instruction can be put in the
2867 call's delay slot. */
2868 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2869 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2870 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2874 /* Lazy-binding stubs require $gp to be valid on entry. */
2875 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2879 /* See the comment above load_call<mode> for details. */
2880 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2881 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2882 emit_insn (gen_update_got_version ());
2886 && TARGET_EXPLICIT_RELOCS
2887 && TARGET_CALL_CLOBBERED_GP
)
2889 rtx post_call_tmp_reg
= gen_rtx_REG (word_mode
, POST_CALL_TMP_REG
);
2890 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn
), post_call_tmp_reg
);
2896 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2897 then add CONST_INT OFFSET to the result. */
2900 mips_unspec_address_offset (rtx base
, rtx offset
,
2901 enum mips_symbol_type symbol_type
)
2903 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2904 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2905 if (offset
!= const0_rtx
)
2906 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2907 return gen_rtx_CONST (Pmode
, base
);
2910 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2911 type SYMBOL_TYPE. */
2914 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2918 split_const (address
, &base
, &offset
);
2919 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2922 /* If OP is an UNSPEC address, return the address to which it refers,
2923 otherwise return OP itself. */
2926 mips_strip_unspec_address (rtx op
)
2930 split_const (op
, &base
, &offset
);
2931 if (UNSPEC_ADDRESS_P (base
))
2932 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2936 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2937 high part to BASE and return the result. Just return BASE otherwise.
2938 TEMP is as for mips_force_temporary.
2940 The returned expression can be used as the first operand to a LO_SUM. */
2943 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2944 enum mips_symbol_type symbol_type
)
2946 if (mips_split_p
[symbol_type
])
2948 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2949 addr
= mips_force_temporary (temp
, addr
);
2950 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2955 /* Return an instruction that copies $gp into register REG. We want
2956 GCC to treat the register's value as constant, so that its value
2957 can be rematerialized on demand. */
2960 gen_load_const_gp (rtx reg
)
2962 return PMODE_INSN (gen_load_const_gp
, (reg
));
2965 /* Return a pseudo register that contains the value of $gp throughout
2966 the current function. Such registers are needed by MIPS16 functions,
2967 for which $gp itself is not a valid base register or addition operand. */
2970 mips16_gp_pseudo_reg (void)
2972 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2976 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2978 push_topmost_sequence ();
2980 scan
= get_insns ();
2981 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2982 scan
= NEXT_INSN (scan
);
2984 rtx set
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2985 rtx_insn
*insn
= emit_insn_after (set
, scan
);
2986 INSN_LOCATION (insn
) = 0;
2988 pop_topmost_sequence ();
2991 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2994 /* Return a base register that holds pic_offset_table_rtx.
2995 TEMP, if nonnull, is a scratch Pmode base register. */
2998 mips_pic_base_register (rtx temp
)
3001 return pic_offset_table_rtx
;
3003 if (currently_expanding_to_rtl
)
3004 return mips16_gp_pseudo_reg ();
3006 if (can_create_pseudo_p ())
3007 temp
= gen_reg_rtx (Pmode
);
3010 /* The first post-reload split exposes all references to $gp
3011 (both uses and definitions). All references must remain
3012 explicit after that point.
3014 It is safe to introduce uses of $gp at any time, so for
3015 simplicity, we do that before the split too. */
3016 mips_emit_move (temp
, pic_offset_table_rtx
);
3018 emit_insn (gen_load_const_gp (temp
));
3022 /* Return the RHS of a load_call<mode> insn. */
3025 mips_unspec_call (rtx reg
, rtx symbol
)
3029 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
3030 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
3033 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3034 reference. Return NULL_RTX otherwise. */
3037 mips_strip_unspec_call (rtx src
)
3039 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
3040 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
3044 /* Create and return a GOT reference of type TYPE for address ADDR.
3045 TEMP, if nonnull, is a scratch Pmode base register. */
3048 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3050 rtx base
, high
, lo_sum_symbol
;
3052 base
= mips_pic_base_register (temp
);
3054 /* If we used the temporary register to load $gp, we can't use
3055 it for the high part as well. */
3056 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3059 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3060 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3062 if (type
== SYMBOL_GOTOFF_CALL
)
3063 return mips_unspec_call (high
, lo_sum_symbol
);
3065 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3068 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3069 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3070 constant in that context and can be split into high and low parts.
3071 If so, and if LOW_OUT is nonnull, emit the high part and store the
3072 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3074 TEMP is as for mips_force_temporary and is used to load the high
3075 part into a register.
3077 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3078 a legitimize SET_SRC for an .md pattern, otherwise the low part
3079 is guaranteed to be a legitimate address for mode MODE. */
3082 mips_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
3084 enum mips_symbol_context context
;
3085 enum mips_symbol_type symbol_type
;
3088 context
= (mode
== MAX_MACHINE_MODE
3089 ? SYMBOL_CONTEXT_LEA
3090 : SYMBOL_CONTEXT_MEM
);
3091 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3093 addr
= XEXP (addr
, 0);
3094 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3095 && mips_symbol_insns (symbol_type
, mode
) > 0
3096 && mips_split_hi_p
[symbol_type
])
3099 switch (symbol_type
)
3101 case SYMBOL_GOT_PAGE_OFST
:
3102 /* The high part of a page/ofst pair is loaded from the GOT. */
3103 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3114 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3115 && mips_symbol_insns (symbol_type
, mode
) > 0
3116 && mips_split_p
[symbol_type
])
3119 switch (symbol_type
)
3121 case SYMBOL_GOT_DISP
:
3122 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3123 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3126 case SYMBOL_GP_RELATIVE
:
3127 high
= mips_pic_base_register (temp
);
3128 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3132 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3133 high
= mips_force_temporary (temp
, high
);
3134 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3143 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3144 mips_force_temporary; it is only needed when OFFSET is not a
3148 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3150 if (!SMALL_OPERAND (offset
))
3156 /* Load the full offset into a register so that we can use
3157 an unextended instruction for the address itself. */
3158 high
= GEN_INT (offset
);
3163 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3164 The addition inside the macro CONST_HIGH_PART may cause an
3165 overflow, so we need to force a sign-extension check. */
3166 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3167 offset
= CONST_LOW_PART (offset
);
3169 high
= mips_force_temporary (temp
, high
);
3170 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3172 return plus_constant (Pmode
, reg
, offset
);
3175 /* The __tls_get_attr symbol. */
3176 static GTY(()) rtx mips_tls_symbol
;
3178 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3179 the TLS symbol we are referencing and TYPE is the symbol type to use
3180 (either global dynamic or local dynamic). V0 is an RTX for the
3181 return value location. */
3184 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3188 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3190 if (!mips_tls_symbol
)
3191 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3193 loc
= mips_unspec_address (sym
, type
);
3197 emit_insn (gen_rtx_SET (a0
, gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
,
3199 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3200 const0_rtx
, NULL_RTX
, false);
3201 RTL_CONST_CALL_P (insn
) = 1;
3202 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3203 insn
= get_insns ();
3210 /* Return a pseudo register that contains the current thread pointer. */
3213 mips_expand_thread_pointer (rtx tp
)
3219 if (!mips16_rdhwr_stub
)
3220 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3221 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3222 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3225 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3232 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3235 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3236 its address. The return value will be both a valid address and a valid
3237 SET_SRC (either a REG or a LO_SUM). */
3240 mips_legitimize_tls_address (rtx loc
)
3242 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3243 enum tls_model model
;
3245 model
= SYMBOL_REF_TLS_MODEL (loc
);
3246 /* Only TARGET_ABICALLS code can have more than one module; other
3247 code must be be static and should not use a GOT. All TLS models
3248 reduce to local exec in this situation. */
3249 if (!TARGET_ABICALLS
)
3250 model
= TLS_MODEL_LOCAL_EXEC
;
3254 case TLS_MODEL_GLOBAL_DYNAMIC
:
3255 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3256 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3257 dest
= gen_reg_rtx (Pmode
);
3258 emit_libcall_block (insn
, dest
, v0
, loc
);
3261 case TLS_MODEL_LOCAL_DYNAMIC
:
3262 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3263 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3264 tmp1
= gen_reg_rtx (Pmode
);
3266 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3267 share the LDM result with other LD model accesses. */
3268 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3270 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3272 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3273 if (mips_split_p
[SYMBOL_DTPREL
])
3275 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3276 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3279 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3280 0, 0, OPTAB_DIRECT
);
3283 case TLS_MODEL_INITIAL_EXEC
:
3284 tp
= mips_get_tp ();
3285 tmp1
= gen_reg_rtx (Pmode
);
3286 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3287 if (Pmode
== DImode
)
3288 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3290 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3291 dest
= gen_reg_rtx (Pmode
);
3292 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3295 case TLS_MODEL_LOCAL_EXEC
:
3296 tmp1
= mips_get_tp ();
3297 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3298 if (mips_split_p
[SYMBOL_TPREL
])
3300 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3301 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3304 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3305 0, 0, OPTAB_DIRECT
);
3314 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3318 mips16_expand_get_fcsr (rtx target
)
3320 if (!mips16_get_fcsr_stub
)
3321 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3322 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3323 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3324 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3327 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3330 mips16_expand_set_fcsr (rtx newval
)
3332 if (!mips16_set_fcsr_stub
)
3333 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3334 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3335 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3336 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3339 /* If X is not a valid address for mode MODE, force it into a register. */
3342 mips_force_address (rtx x
, machine_mode mode
)
3344 if (!mips_legitimate_address_p (mode
, x
, false))
3345 x
= force_reg (Pmode
, x
);
3349 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3350 be legitimized in a way that the generic machinery might not expect,
3351 return a new address, otherwise return NULL. MODE is the mode of
3352 the memory being accessed. */
3355 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3359 HOST_WIDE_INT offset
;
3361 if (mips_tls_symbol_p (x
))
3362 return mips_legitimize_tls_address (x
);
3364 /* See if the address can split into a high part and a LO_SUM. */
3365 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3366 return mips_force_address (addr
, mode
);
3368 /* Handle BASE + OFFSET using mips_add_offset. */
3369 mips_split_plus (x
, &base
, &offset
);
3372 if (!mips_valid_base_register_p (base
, mode
, false))
3373 base
= copy_to_mode_reg (Pmode
, base
);
3374 addr
= mips_add_offset (NULL
, base
, offset
);
3375 return mips_force_address (addr
, mode
);
3381 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3384 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3386 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3388 unsigned int i
, num_ops
;
3391 mode
= GET_MODE (dest
);
3392 num_ops
= mips_build_integer (codes
, value
);
3394 /* Apply each binary operation to X. Invariant: X is a legitimate
3395 source operand for a SET pattern. */
3396 x
= GEN_INT (codes
[0].value
);
3397 for (i
= 1; i
< num_ops
; i
++)
3399 if (!can_create_pseudo_p ())
3401 emit_insn (gen_rtx_SET (temp
, x
));
3405 x
= force_reg (mode
, x
);
3406 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3409 emit_insn (gen_rtx_SET (dest
, x
));
3412 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3413 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3417 mips_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
3421 /* Split moves of big integers into smaller pieces. */
3422 if (splittable_const_int_operand (src
, mode
))
3424 mips_move_integer (dest
, dest
, INTVAL (src
));
3428 /* Split moves of symbolic constants into high/low pairs. */
3429 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3431 emit_insn (gen_rtx_SET (dest
, src
));
3435 /* Generate the appropriate access sequences for TLS symbols. */
3436 if (mips_tls_symbol_p (src
))
3438 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3442 /* If we have (const (plus symbol offset)), and that expression cannot
3443 be forced into memory, load the symbol first and add in the offset.
3444 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3445 forced into memory, as it usually produces better code. */
3446 split_const (src
, &base
, &offset
);
3447 if (offset
!= const0_rtx
3448 && (targetm
.cannot_force_const_mem (mode
, src
)
3449 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3451 base
= mips_force_temporary (dest
, base
);
3452 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3456 src
= force_const_mem (mode
, src
);
3458 /* When using explicit relocs, constant pool references are sometimes
3459 not legitimate addresses. */
3460 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3461 mips_emit_move (dest
, src
);
3464 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3465 sequence that is valid. */
3468 mips_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
3470 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3472 mips_emit_move (dest
, force_reg (mode
, src
));
3476 /* We need to deal with constants that would be legitimate
3477 immediate_operands but aren't legitimate move_operands. */
3478 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3480 mips_legitimize_const_move (mode
, dest
, src
);
3481 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3487 /* Return true if value X in context CONTEXT is a small-data address
3488 that can be rewritten as a LO_SUM. */
3491 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3493 enum mips_symbol_type symbol_type
;
3495 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3496 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3497 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3498 && symbol_type
== SYMBOL_GP_RELATIVE
);
3501 /* Return true if OP refers to small data symbols directly, not through
3502 a LO_SUM. CONTEXT is the context in which X appears. */
3505 mips_small_data_pattern_1 (rtx x
, enum mips_symbol_context context
)
3507 subrtx_var_iterator::array_type array
;
3508 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
3512 /* Ignore things like "g" constraints in asms. We make no particular
3513 guarantee about which symbolic constants are acceptable as asm operands
3514 versus which must be forced into a GPR. */
3515 if (GET_CODE (x
) == LO_SUM
|| GET_CODE (x
) == ASM_OPERANDS
)
3516 iter
.skip_subrtxes ();
3519 if (mips_small_data_pattern_1 (XEXP (x
, 0), SYMBOL_CONTEXT_MEM
))
3521 iter
.skip_subrtxes ();
3523 else if (mips_rewrite_small_data_p (x
, context
))
3529 /* Return true if OP refers to small data symbols directly, not through
3533 mips_small_data_pattern_p (rtx op
)
3535 return mips_small_data_pattern_1 (op
, SYMBOL_CONTEXT_LEA
);
3538 /* Rewrite *LOC so that it refers to small data using explicit
3539 relocations. CONTEXT is the context in which *LOC appears. */
3542 mips_rewrite_small_data_1 (rtx
*loc
, enum mips_symbol_context context
)
3544 subrtx_ptr_iterator::array_type array
;
3545 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3550 mips_rewrite_small_data_1 (&XEXP (*loc
, 0), SYMBOL_CONTEXT_MEM
);
3551 iter
.skip_subrtxes ();
3553 else if (mips_rewrite_small_data_p (*loc
, context
))
3555 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3556 iter
.skip_subrtxes ();
3558 else if (GET_CODE (*loc
) == LO_SUM
)
3559 iter
.skip_subrtxes ();
3563 /* Rewrite instruction pattern PATTERN so that it refers to small data
3564 using explicit relocations. */
3567 mips_rewrite_small_data (rtx pattern
)
3569 pattern
= copy_insn (pattern
);
3570 mips_rewrite_small_data_1 (&pattern
, SYMBOL_CONTEXT_LEA
);
3574 /* The cost of loading values from the constant pool. It should be
3575 larger than the cost of any constant we want to synthesize inline. */
3576 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3578 /* Return the cost of X when used as an operand to the MIPS16 instruction
3579 that implements CODE. Return -1 if there is no such instruction, or if
3580 X is not a valid immediate operand for it. */
3583 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3590 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3591 other shifts are extended. The shift patterns truncate the shift
3592 count to the right size, so there are no out-of-range values. */
3593 if (IN_RANGE (x
, 1, 8))
3595 return COSTS_N_INSNS (1);
3598 if (IN_RANGE (x
, -128, 127))
3600 if (SMALL_OPERAND (x
))
3601 return COSTS_N_INSNS (1);
3605 /* Like LE, but reject the always-true case. */
3609 /* We add 1 to the immediate and use SLT. */
3612 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3615 if (IN_RANGE (x
, 0, 255))
3617 if (SMALL_OPERAND_UNSIGNED (x
))
3618 return COSTS_N_INSNS (1);
3623 /* Equality comparisons with 0 are cheap. */
3633 /* Return true if there is a non-MIPS16 instruction that implements CODE
3634 and if that instruction accepts X as an immediate operand. */
3637 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3644 /* All shift counts are truncated to a valid constant. */
3649 /* Likewise rotates, if the target supports rotates at all. */
3655 /* These instructions take 16-bit unsigned immediates. */
3656 return SMALL_OPERAND_UNSIGNED (x
);
3661 /* These instructions take 16-bit signed immediates. */
3662 return SMALL_OPERAND (x
);
3668 /* The "immediate" forms of these instructions are really
3669 implemented as comparisons with register 0. */
3674 /* Likewise, meaning that the only valid immediate operand is 1. */
3678 /* We add 1 to the immediate and use SLT. */
3679 return SMALL_OPERAND (x
+ 1);
3682 /* Likewise SLTU, but reject the always-true case. */
3683 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3687 /* The bit position and size are immediate operands. */
3688 return ISA_HAS_EXT_INS
;
3691 /* By default assume that $0 can be used for 0. */
3696 /* Return the cost of binary operation X, given that the instruction
3697 sequence for a word-sized or smaller operation has cost SINGLE_COST
3698 and that the sequence of a double-word operation has cost DOUBLE_COST.
3699 If SPEED is true, optimize for speed otherwise optimize for size. */
3702 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3706 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3711 + set_src_cost (XEXP (x
, 0), speed
)
3712 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3715 /* Return the cost of floating-point multiplications of mode MODE. */
3718 mips_fp_mult_cost (machine_mode mode
)
3720 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3723 /* Return the cost of floating-point divisions of mode MODE. */
3726 mips_fp_div_cost (machine_mode mode
)
3728 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3731 /* Return the cost of sign-extending OP to mode MODE, not including the
3732 cost of OP itself. */
3735 mips_sign_extend_cost (machine_mode mode
, rtx op
)
3738 /* Extended loads are as cheap as unextended ones. */
3741 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3742 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3745 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3746 /* We can use SEB or SEH. */
3747 return COSTS_N_INSNS (1);
3749 /* We need to use a shift left and a shift right. */
3750 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3753 /* Return the cost of zero-extending OP to mode MODE, not including the
3754 cost of OP itself. */
3757 mips_zero_extend_cost (machine_mode mode
, rtx op
)
3760 /* Extended loads are as cheap as unextended ones. */
3763 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3764 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3765 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3767 if (GENERATE_MIPS16E
)
3768 /* We can use ZEB or ZEH. */
3769 return COSTS_N_INSNS (1);
3772 /* We need to load 0xff or 0xffff into a register and use AND. */
3773 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3775 /* We can use ANDI. */
3776 return COSTS_N_INSNS (1);
3779 /* Return the cost of moving between two registers of mode MODE,
3780 assuming that the move will be in pieces of at most UNITS bytes. */
3783 mips_set_reg_reg_piece_cost (machine_mode mode
, unsigned int units
)
3785 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3788 /* Return the cost of moving between two registers of mode MODE. */
3791 mips_set_reg_reg_cost (machine_mode mode
)
3793 switch (GET_MODE_CLASS (mode
))
3796 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3799 case MODE_COMPLEX_FLOAT
:
3800 case MODE_VECTOR_FLOAT
:
3801 if (TARGET_HARD_FLOAT
)
3802 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3806 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3810 /* Implement TARGET_RTX_COSTS. */
3813 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3814 int *total
, bool speed
)
3816 machine_mode mode
= GET_MODE (x
);
3817 bool float_mode_p
= FLOAT_MODE_P (mode
);
3821 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3822 appear in the instruction stream, and the cost of a comparison is
3823 really the cost of the branch or scc condition. At the time of
3824 writing, GCC only uses an explicit outer COMPARE code when optabs
3825 is testing whether a constant is expensive enough to force into a
3826 register. We want optabs to pass such constants through the MIPS
3827 expanders instead, so make all constants very cheap here. */
3828 if (outer_code
== COMPARE
)
3830 gcc_assert (CONSTANT_P (x
));
3838 /* Treat *clear_upper32-style ANDs as having zero cost in the
3839 second operand. The cost is entirely in the first operand.
3841 ??? This is needed because we would otherwise try to CSE
3842 the constant operand. Although that's the right thing for
3843 instructions that continue to be a register operation throughout
3844 compilation, it is disastrous for instructions that could
3845 later be converted into a memory operation. */
3847 && outer_code
== AND
3848 && UINTVAL (x
) == 0xffffffff)
3856 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3865 /* When not optimizing for size, we care more about the cost
3866 of hot code, and hot code is often in a loop. If a constant
3867 operand needs to be forced into a register, we will often be
3868 able to hoist the constant load out of the loop, so the load
3869 should not contribute to the cost. */
3870 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3882 if (force_to_mem_operand (x
, VOIDmode
))
3884 *total
= COSTS_N_INSNS (1);
3887 cost
= mips_const_insns (x
);
3890 /* If the constant is likely to be stored in a GPR, SETs of
3891 single-insn constants are as cheap as register sets; we
3892 never want to CSE them.
3894 Don't reduce the cost of storing a floating-point zero in
3895 FPRs. If we have a zero in an FPR for other reasons, we
3896 can get better cfg-cleanup and delayed-branch results by
3897 using it consistently, rather than using $0 sometimes and
3898 an FPR at other times. Also, moves between floating-point
3899 registers are sometimes cheaper than (D)MTC1 $0. */
3901 && outer_code
== SET
3902 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3904 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3905 want to CSE the constant itself. It is usually better to
3906 have N copies of the last operation in the sequence and one
3907 shared copy of the other operations. (Note that this is
3908 not true for MIPS16 code, where the final operation in the
3909 sequence is often an extended instruction.)
3911 Also, if we have a CONST_INT, we don't know whether it is
3912 for a word or doubleword operation, so we cannot rely on
3913 the result of mips_build_integer. */
3914 else if (!TARGET_MIPS16
3915 && (outer_code
== SET
|| mode
== VOIDmode
))
3917 *total
= COSTS_N_INSNS (cost
);
3920 /* The value will need to be fetched from the constant pool. */
3921 *total
= CONSTANT_POOL_COST
;
3925 /* If the address is legitimate, return the number of
3926 instructions it needs. */
3928 cost
= mips_address_insns (addr
, mode
, true);
3931 *total
= COSTS_N_INSNS (cost
+ 1);
3934 /* Check for a scaled indexed address. */
3935 if (mips_lwxs_address_p (addr
)
3936 || mips_lx_address_p (addr
, mode
))
3938 *total
= COSTS_N_INSNS (2);
3941 /* Otherwise use the default handling. */
3945 *total
= COSTS_N_INSNS (6);
3949 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3953 /* Check for a *clear_upper32 pattern and treat it like a zero
3954 extension. See the pattern's comment for details. */
3957 && CONST_INT_P (XEXP (x
, 1))
3958 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3960 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3961 + set_src_cost (XEXP (x
, 0), speed
));
3964 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3966 rtx op
= XEXP (x
, 0);
3967 if (GET_CODE (op
) == ASHIFT
3968 && CONST_INT_P (XEXP (op
, 1))
3969 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3971 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3975 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3976 a single instruction. */
3978 && GET_CODE (XEXP (x
, 0)) == NOT
3979 && GET_CODE (XEXP (x
, 1)) == NOT
)
3981 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
3982 *total
= (COSTS_N_INSNS (cost
)
3983 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
3984 + set_src_cost (XEXP (XEXP (x
, 1), 0), speed
));
3992 /* Double-word operations use two single-word operations. */
3993 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
4002 if (CONSTANT_P (XEXP (x
, 1)))
4003 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4006 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
4012 *total
= mips_cost
->fp_add
;
4014 *total
= COSTS_N_INSNS (4);
4018 /* Low-part immediates need an extended MIPS16 instruction. */
4019 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
4020 + set_src_cost (XEXP (x
, 0), speed
));
4035 /* Branch comparisons have VOIDmode, so use the first operand's
4037 mode
= GET_MODE (XEXP (x
, 0));
4038 if (FLOAT_MODE_P (mode
))
4040 *total
= mips_cost
->fp_add
;
4043 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4048 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
&& !HONOR_SIGNED_ZEROS (mode
))
4050 /* See if we can use NMADD or NMSUB via the *nmadd4<mode>_fastmath
4051 or *nmsub4<mode>_fastmath patterns. These patterns check for
4052 HONOR_SIGNED_ZEROS so we check here too. */
4053 rtx op0
= XEXP (x
, 0);
4054 rtx op1
= XEXP (x
, 1);
4055 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4057 *total
= (mips_fp_mult_cost (mode
)
4058 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
4059 + set_src_cost (XEXP (op0
, 1), speed
)
4060 + set_src_cost (op1
, speed
));
4063 if (GET_CODE (op1
) == MULT
)
4065 *total
= (mips_fp_mult_cost (mode
)
4066 + set_src_cost (op0
, speed
)
4067 + set_src_cost (XEXP (op1
, 0), speed
)
4068 + set_src_cost (XEXP (op1
, 1), speed
));
4077 /* If this is part of a MADD or MSUB, treat the PLUS as
4079 if (ISA_HAS_UNFUSED_MADD4
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4082 *total
= mips_cost
->fp_add
;
4086 /* If it's an add + mult (which is equivalent to shift left) and
4087 it's immediate operand satisfies const_immlsa_operand predicate. */
4088 if (((ISA_HAS_LSA
&& mode
== SImode
)
4089 || (ISA_HAS_DLSA
&& mode
== DImode
))
4090 && GET_CODE (XEXP (x
, 0)) == MULT
)
4092 rtx op2
= XEXP (XEXP (x
, 0), 1);
4093 if (const_immlsa_operand (op2
, mode
))
4095 *total
= (COSTS_N_INSNS (1)
4096 + set_src_cost (XEXP (XEXP (x
, 0), 0), speed
)
4097 + set_src_cost (XEXP (x
, 1), speed
));
4102 /* Double-word operations require three single-word operations and
4103 an SLTU. The MIPS16 version then needs to move the result of
4104 the SLTU from $24 to a MIPS16 register. */
4105 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4106 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4111 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
)
4113 /* See if we can use NMADD or NMSUB via the *nmadd4<mode> or
4114 *nmsub4<mode> patterns. */
4115 rtx op
= XEXP (x
, 0);
4116 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4117 && GET_CODE (XEXP (op
, 0)) == MULT
)
4119 *total
= (mips_fp_mult_cost (mode
)
4120 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
4121 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
4122 + set_src_cost (XEXP (op
, 1), speed
));
4128 *total
= mips_cost
->fp_add
;
4130 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4134 *total
= mips_fp_mult_cost (mode
);
4139 *total
= mips_fp_mult_cost (mode
);
4140 else if (mode
== DImode
&& !TARGET_64BIT
)
4141 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4142 where the mulsidi3 always includes an MFHI and an MFLO. */
4144 ? mips_cost
->int_mult_si
* 3 + 6
4145 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4147 *total
= COSTS_N_INSNS ((ISA_HAS_MUL3
|| ISA_HAS_R6MUL
) ? 1 : 2) + 1;
4148 else if (mode
== DImode
)
4149 *total
= mips_cost
->int_mult_di
;
4151 *total
= mips_cost
->int_mult_si
;
4155 /* Check for a reciprocal. */
4157 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4158 && flag_unsafe_math_optimizations
4159 && XEXP (x
, 0) == CONST1_RTX (mode
))
4161 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4162 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4163 division as being free. */
4164 *total
= set_src_cost (XEXP (x
, 1), speed
);
4166 *total
= (mips_fp_div_cost (mode
)
4167 + set_src_cost (XEXP (x
, 1), speed
));
4176 *total
= mips_fp_div_cost (mode
);
4185 /* It is our responsibility to make division by a power of 2
4186 as cheap as 2 register additions if we want the division
4187 expanders to be used for such operations; see the setting
4188 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4189 should always produce shorter code than using
4190 expand_sdiv2_pow2. */
4192 && CONST_INT_P (XEXP (x
, 1))
4193 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4195 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
4198 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4200 else if (mode
== DImode
)
4201 *total
= mips_cost
->int_div_di
;
4203 *total
= mips_cost
->int_div_si
;
4207 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4211 if (outer_code
== SET
4213 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4214 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4215 && GET_MODE (XEXP (x
, 0)) == QImode
4216 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4218 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), speed
);
4221 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4224 /* Costings for highpart multiplies. Matching patterns of the form:
4226 (lshiftrt:DI (mult:DI (sign_extend:DI (...)
4227 (sign_extend:DI (...))
4231 && (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4232 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
4233 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4234 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) == 32
4235 && GET_MODE (XEXP (x
, 0)) == DImode
)
4237 && INTVAL (XEXP (XEXP (x
, 0), 1)) == 64
4238 && GET_MODE (XEXP (x
, 0)) == TImode
))
4239 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4240 && ((GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
4241 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SIGN_EXTEND
)
4242 || (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4243 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4247 *total
= COSTS_N_INSNS (1) + 1;
4248 else if (mode
== DImode
)
4249 *total
= mips_cost
->int_mult_di
;
4251 *total
= mips_cost
->int_mult_si
;
4253 /* Sign extension is free, zero extension costs for DImode when
4254 on a 64bit core / when DMUL is present. */
4255 for (int i
= 0; i
< 2; ++i
)
4257 rtx op
= XEXP (XEXP (XEXP (x
, 0), 0), i
);
4259 && GET_CODE (op
) == ZERO_EXTEND
4260 && GET_MODE (op
) == DImode
)
4261 *total
+= rtx_cost (op
, MULT
, i
, speed
);
4263 *total
+= rtx_cost (XEXP (op
, 0), GET_CODE (op
), 0, speed
);
4271 case UNSIGNED_FLOAT
:
4274 case FLOAT_TRUNCATE
:
4275 *total
= mips_cost
->fp_add
;
4279 if (register_operand (SET_DEST (x
), VOIDmode
)
4280 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4282 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4292 /* Implement TARGET_ADDRESS_COST. */
4295 mips_address_cost (rtx addr
, machine_mode mode
,
4296 addr_space_t as ATTRIBUTE_UNUSED
,
4297 bool speed ATTRIBUTE_UNUSED
)
4299 return mips_address_insns (addr
, mode
, false);
4302 /* Information about a single instruction in a multi-instruction
4304 struct mips_multi_member
{
4305 /* True if this is a label, false if it is code. */
4308 /* The output_asm_insn format of the instruction. */
4311 /* The operands to the instruction. */
4312 rtx operands
[MAX_RECOG_OPERANDS
];
4314 typedef struct mips_multi_member mips_multi_member
;
4316 /* The instructions that make up the current multi-insn sequence. */
4317 static vec
<mips_multi_member
> mips_multi_members
;
4319 /* How many instructions (as opposed to labels) are in the current
4320 multi-insn sequence. */
4321 static unsigned int mips_multi_num_insns
;
4323 /* Start a new multi-insn sequence. */
4326 mips_multi_start (void)
4328 mips_multi_members
.truncate (0);
4329 mips_multi_num_insns
= 0;
4332 /* Add a new, uninitialized member to the current multi-insn sequence. */
4334 static struct mips_multi_member
*
4335 mips_multi_add (void)
4337 mips_multi_member empty
;
4338 return mips_multi_members
.safe_push (empty
);
4341 /* Add a normal insn with the given asm format to the current multi-insn
4342 sequence. The other arguments are a null-terminated list of operands. */
4345 mips_multi_add_insn (const char *format
, ...)
4347 struct mips_multi_member
*member
;
4352 member
= mips_multi_add ();
4353 member
->is_label_p
= false;
4354 member
->format
= format
;
4355 va_start (ap
, format
);
4357 while ((op
= va_arg (ap
, rtx
)))
4358 member
->operands
[i
++] = op
;
4360 mips_multi_num_insns
++;
4363 /* Add the given label definition to the current multi-insn sequence.
4364 The definition should include the colon. */
4367 mips_multi_add_label (const char *label
)
4369 struct mips_multi_member
*member
;
4371 member
= mips_multi_add ();
4372 member
->is_label_p
= true;
4373 member
->format
= label
;
4376 /* Return the index of the last member of the current multi-insn sequence. */
4379 mips_multi_last_index (void)
4381 return mips_multi_members
.length () - 1;
4384 /* Add a copy of an existing instruction to the current multi-insn
4385 sequence. I is the index of the instruction that should be copied. */
4388 mips_multi_copy_insn (unsigned int i
)
4390 struct mips_multi_member
*member
;
4392 member
= mips_multi_add ();
4393 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4394 gcc_assert (!member
->is_label_p
);
4397 /* Change the operand of an existing instruction in the current
4398 multi-insn sequence. I is the index of the instruction,
4399 OP is the index of the operand, and X is the new value. */
4402 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4404 mips_multi_members
[i
].operands
[op
] = x
;
4407 /* Write out the asm code for the current multi-insn sequence. */
4410 mips_multi_write (void)
4412 struct mips_multi_member
*member
;
4415 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4416 if (member
->is_label_p
)
4417 fprintf (asm_out_file
, "%s\n", member
->format
);
4419 output_asm_insn (member
->format
, member
->operands
);
4422 /* Return one word of double-word value OP, taking into account the fixed
4423 endianness of certain registers. HIGH_P is true to select the high part,
4424 false to select the low part. */
4427 mips_subword (rtx op
, bool high_p
)
4429 unsigned int byte
, offset
;
4432 mode
= GET_MODE (op
);
4433 if (mode
== VOIDmode
)
4434 mode
= TARGET_64BIT
? TImode
: DImode
;
4436 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4437 byte
= UNITS_PER_WORD
;
4441 if (FP_REG_RTX_P (op
))
4443 /* Paired FPRs are always ordered little-endian. */
4444 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4445 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4449 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4451 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4454 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4455 SPLIT_TYPE is the condition under which moves should be split. */
4458 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4460 return ((split_type
!= SPLIT_FOR_SPEED
4461 || mips_tuning_info
.fast_mult_zero_zero_p
)
4462 && src
== const0_rtx
4464 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4465 && (ISA_HAS_DSP_MULT
4466 ? ACC_REG_P (REGNO (dest
))
4467 : MD_REG_P (REGNO (dest
))));
4470 /* Return true if a move from SRC to DEST should be split into two.
4471 SPLIT_TYPE describes the split condition. */
4474 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4476 /* Check whether the move can be done using some variant of MULT $0,$0. */
4477 if (mips_mult_move_p (dest
, src
, split_type
))
4480 /* FPR-to-FPR moves can be done in a single instruction, if they're
4482 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4483 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4486 /* Check for floating-point loads and stores. */
4487 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4489 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4491 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4495 /* Otherwise split all multiword moves. */
4496 return size
> UNITS_PER_WORD
;
4499 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4500 SPLIT_TYPE describes the split condition. */
4503 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4507 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4508 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4510 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4511 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4512 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4513 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4514 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4515 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4516 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4517 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4518 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4519 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4520 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4521 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4522 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4523 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4527 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4529 low_dest
= mips_subword (dest
, false);
4530 mips_emit_move (low_dest
, mips_subword (src
, false));
4532 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4534 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4536 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4538 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4540 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4542 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4546 /* The operation can be split into two normal moves. Decide in
4547 which order to do them. */
4548 low_dest
= mips_subword (dest
, false);
4549 if (REG_P (low_dest
)
4550 && reg_overlap_mentioned_p (low_dest
, src
))
4552 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4553 mips_emit_move (low_dest
, mips_subword (src
, false));
4557 mips_emit_move (low_dest
, mips_subword (src
, false));
4558 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4563 /* Return the split type for instruction INSN. */
4565 static enum mips_split_type
4566 mips_insn_split_type (rtx insn
)
4568 basic_block bb
= BLOCK_FOR_INSN (insn
);
4571 if (optimize_bb_for_speed_p (bb
))
4572 return SPLIT_FOR_SPEED
;
4574 return SPLIT_FOR_SIZE
;
4576 /* Once CFG information has been removed, we should trust the optimization
4577 decisions made by previous passes and only split where necessary. */
4578 return SPLIT_IF_NECESSARY
;
4581 /* Return true if a move from SRC to DEST in INSN should be split. */
4584 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4586 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4589 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4593 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4595 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4598 /* Return the appropriate instructions to move SRC into DEST. Assume
4599 that SRC is operand 1 and DEST is operand 0. */
4602 mips_output_move (rtx dest
, rtx src
)
4604 enum rtx_code dest_code
, src_code
;
4606 enum mips_symbol_type symbol_type
;
4609 dest_code
= GET_CODE (dest
);
4610 src_code
= GET_CODE (src
);
4611 mode
= GET_MODE (dest
);
4612 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4614 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4617 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4618 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4620 if (dest_code
== REG
)
4622 if (GP_REG_P (REGNO (dest
)))
4623 return "move\t%0,%z1";
4625 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4627 if (ISA_HAS_DSP_MULT
)
4628 return "mult\t%q0,%.,%.";
4630 return "mult\t%.,%.";
4633 /* Moves to HI are handled by special .md insns. */
4634 if (REGNO (dest
) == LO_REGNUM
)
4637 if (DSP_ACC_REG_P (REGNO (dest
)))
4639 static char retval
[] = "mt__\t%z1,%q0";
4641 retval
[2] = reg_names
[REGNO (dest
)][4];
4642 retval
[3] = reg_names
[REGNO (dest
)][5];
4646 if (FP_REG_P (REGNO (dest
)))
4647 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4649 if (ALL_COP_REG_P (REGNO (dest
)))
4651 static char retval
[] = "dmtc_\t%z1,%0";
4653 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4654 return dbl_p
? retval
: retval
+ 1;
4657 if (dest_code
== MEM
)
4658 switch (GET_MODE_SIZE (mode
))
4660 case 1: return "sb\t%z1,%0";
4661 case 2: return "sh\t%z1,%0";
4662 case 4: return "sw\t%z1,%0";
4663 case 8: return "sd\t%z1,%0";
4666 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4668 if (src_code
== REG
)
4670 /* Moves from HI are handled by special .md insns. */
4671 if (REGNO (src
) == LO_REGNUM
)
4673 /* When generating VR4120 or VR4130 code, we use MACC and
4674 DMACC instead of MFLO. This avoids both the normal
4675 MIPS III HI/LO hazards and the errata related to
4678 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4682 if (DSP_ACC_REG_P (REGNO (src
)))
4684 static char retval
[] = "mf__\t%0,%q1";
4686 retval
[2] = reg_names
[REGNO (src
)][4];
4687 retval
[3] = reg_names
[REGNO (src
)][5];
4691 if (FP_REG_P (REGNO (src
)))
4692 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4694 if (ALL_COP_REG_P (REGNO (src
)))
4696 static char retval
[] = "dmfc_\t%0,%1";
4698 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4699 return dbl_p
? retval
: retval
+ 1;
4703 if (src_code
== MEM
)
4704 switch (GET_MODE_SIZE (mode
))
4706 case 1: return "lbu\t%0,%1";
4707 case 2: return "lhu\t%0,%1";
4708 case 4: return "lw\t%0,%1";
4709 case 8: return "ld\t%0,%1";
4712 if (src_code
== CONST_INT
)
4714 /* Don't use the X format for the operand itself, because that
4715 will give out-of-range numbers for 64-bit hosts and 32-bit
4718 return "li\t%0,%1\t\t\t# %X1";
4720 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4723 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4727 if (src_code
== HIGH
)
4728 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4730 if (CONST_GP_P (src
))
4731 return "move\t%0,%1";
4733 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4734 && mips_lo_relocs
[symbol_type
] != 0)
4736 /* A signed 16-bit constant formed by applying a relocation
4737 operator to a symbolic address. */
4738 gcc_assert (!mips_split_p
[symbol_type
]);
4739 return "li\t%0,%R1";
4742 if (symbolic_operand (src
, VOIDmode
))
4744 gcc_assert (TARGET_MIPS16
4745 ? TARGET_MIPS16_TEXT_LOADS
4746 : !TARGET_EXPLICIT_RELOCS
);
4747 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4750 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4752 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4754 if (GET_MODE (dest
) == V2SFmode
)
4755 return "mov.ps\t%0,%1";
4757 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4760 if (dest_code
== MEM
)
4761 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4763 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4765 if (src_code
== MEM
)
4766 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4768 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4770 static char retval
[] = "l_c_\t%0,%1";
4772 retval
[1] = (dbl_p
? 'd' : 'w');
4773 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4776 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4778 static char retval
[] = "s_c_\t%1,%0";
4780 retval
[1] = (dbl_p
? 'd' : 'w');
4781 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4787 /* Return true if CMP1 is a suitable second operand for integer ordering
4788 test CODE. See also the *sCC patterns in mips.md. */
4791 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4797 return reg_or_0_operand (cmp1
, VOIDmode
);
4801 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4805 return arith_operand (cmp1
, VOIDmode
);
4808 return sle_operand (cmp1
, VOIDmode
);
4811 return sleu_operand (cmp1
, VOIDmode
);
4818 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4819 integer ordering test *CODE, or if an equivalent combination can
4820 be formed by adjusting *CODE and *CMP1. When returning true, update
4821 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4825 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4828 HOST_WIDE_INT plus_one
;
4830 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4833 if (CONST_INT_P (*cmp1
))
4837 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4838 if (INTVAL (*cmp1
) < plus_one
)
4841 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4847 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4851 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4862 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4863 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4864 is nonnull, it's OK to set TARGET to the inverse of the result and
4865 flip *INVERT_PTR instead. */
4868 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4869 rtx target
, rtx cmp0
, rtx cmp1
)
4873 /* First see if there is a MIPS instruction that can do this operation.
4874 If not, try doing the same for the inverse operation. If that also
4875 fails, force CMP1 into a register and try again. */
4876 mode
= GET_MODE (cmp0
);
4877 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4878 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4881 enum rtx_code inv_code
= reverse_condition (code
);
4882 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4884 cmp1
= force_reg (mode
, cmp1
);
4885 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4887 else if (invert_ptr
== 0)
4891 inv_target
= mips_force_binary (GET_MODE (target
),
4892 inv_code
, cmp0
, cmp1
);
4893 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4897 *invert_ptr
= !*invert_ptr
;
4898 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4903 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4904 The register will have the same mode as CMP0. */
4907 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4909 if (cmp1
== const0_rtx
)
4912 if (uns_arith_operand (cmp1
, VOIDmode
))
4913 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4914 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4916 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4917 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4920 /* Convert *CODE into a code that can be used in a floating-point
4921 scc instruction (C.cond.fmt). Return true if the values of
4922 the condition code registers will be inverted, with 0 indicating
4923 that the condition holds. */
4926 mips_reversed_fp_cond (enum rtx_code
*code
)
4933 *code
= reverse_condition_maybe_unordered (*code
);
4941 /* Allocate a floating-point condition-code register of mode MODE.
4943 These condition code registers are used for certain kinds
4944 of compound operation, such as compare and branches, vconds,
4945 and built-in functions. At expand time, their use is entirely
4946 controlled by MIPS-specific code and is entirely internal
4947 to these compound operations.
4949 We could (and did in the past) expose condition-code values
4950 as pseudo registers and leave the register allocator to pick
4951 appropriate registers. The problem is that it is not practically
4952 possible for the rtl optimizers to guarantee that no spills will
4953 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4954 therefore need spill and reload sequences to handle the worst case.
4956 Although such sequences do exist, they are very expensive and are
4957 not something we'd want to use. This is especially true of CCV2 and
4958 CCV4, where all the shuffling would greatly outweigh whatever benefit
4959 the vectorization itself provides.
4961 The main benefit of having more than one condition-code register
4962 is to allow the pipelining of operations, especially those involving
4963 comparisons and conditional moves. We don't really expect the
4964 registers to be live for long periods, and certainly never want
4965 them to be live across calls.
4967 Also, there should be no penalty attached to using all the available
4968 registers. They are simply bits in the same underlying FPU control
4971 We therefore expose the hardware registers from the outset and use
4972 a simple round-robin allocation scheme. */
4975 mips_allocate_fcc (machine_mode mode
)
4977 unsigned int regno
, count
;
4979 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4983 else if (mode
== CCV2mode
)
4985 else if (mode
== CCV4mode
)
4990 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4991 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4992 cfun
->machine
->next_fcc
= 0;
4993 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4994 cfun
->machine
->next_fcc
+= count
;
4995 return gen_rtx_REG (mode
, regno
);
4998 /* Convert a comparison into something that can be used in a branch or
4999 conditional move. On entry, *OP0 and *OP1 are the values being
5000 compared and *CODE is the code used to compare them.
5002 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
5003 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
5004 otherwise any standard branch condition can be used. The standard branch
5007 - EQ or NE between two registers.
5008 - any comparison between a register and zero. */
5011 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
5016 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
5018 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
5020 else if (*code
== EQ
|| *code
== NE
)
5024 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
5028 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5032 /* The comparison needs a separate scc instruction. Store the
5033 result of the scc in *OP0 and compare it against zero. */
5034 bool invert
= false;
5035 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
5036 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
5037 *code
= (invert
? EQ
: NE
);
5041 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
5043 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
5044 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
5050 enum rtx_code cmp_code
;
5052 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt
5053 comparison to set a register. The branch or conditional move will
5054 then compare that register against zero.
5056 Set CMP_CODE to the code of the comparison instruction and
5057 *CODE to the code that the branch or move should use. */
5061 /* All FP conditions can be implemented directly with CMP.cond.fmt
5062 or by reversing the operands. */
5064 *op0
= gen_reg_rtx (CCFmode
);
5068 /* Three FP conditions cannot be implemented by reversing the
5069 operands for C.cond.fmt, instead a reversed condition code is
5070 required and a test for false. */
5071 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
5073 *op0
= mips_allocate_fcc (CCmode
);
5075 *op0
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
5079 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
5083 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
5084 and OPERAND[3]. Store the result in OPERANDS[0].
5086 On 64-bit targets, the mode of the comparison and target will always be
5087 SImode, thus possibly narrower than that of the comparison's operands. */
5090 mips_expand_scc (rtx operands
[])
5092 rtx target
= operands
[0];
5093 enum rtx_code code
= GET_CODE (operands
[1]);
5094 rtx op0
= operands
[2];
5095 rtx op1
= operands
[3];
5097 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
5099 if (code
== EQ
|| code
== NE
)
5102 && reg_imm10_operand (op1
, GET_MODE (op1
)))
5103 mips_emit_binary (code
, target
, op0
, op1
);
5106 rtx zie
= mips_zero_if_equal (op0
, op1
);
5107 mips_emit_binary (code
, target
, zie
, const0_rtx
);
5111 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
5114 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5115 CODE and jump to OPERANDS[3] if the condition holds. */
5118 mips_expand_conditional_branch (rtx
*operands
)
5120 enum rtx_code code
= GET_CODE (operands
[0]);
5121 rtx op0
= operands
[1];
5122 rtx op1
= operands
[2];
5125 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5126 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5127 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5132 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5133 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5136 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5137 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5142 reversed_p
= mips_reversed_fp_cond (&cond
);
5143 cmp_result
= mips_allocate_fcc (CCV2mode
);
5144 emit_insn (gen_scc_ps (cmp_result
,
5145 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5147 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5150 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5154 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5155 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5158 mips_expand_conditional_move (rtx
*operands
)
5161 enum rtx_code code
= GET_CODE (operands
[1]);
5162 rtx op0
= XEXP (operands
[1], 0);
5163 rtx op1
= XEXP (operands
[1], 1);
5165 mips_emit_compare (&code
, &op0
, &op1
, true);
5166 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5168 /* There is no direct support for general conditional GP move involving
5169 two registers using SEL. */
5171 && INTEGRAL_MODE_P (GET_MODE (operands
[2]))
5172 && register_operand (operands
[2], VOIDmode
)
5173 && register_operand (operands
[3], VOIDmode
))
5175 machine_mode mode
= GET_MODE (operands
[0]);
5176 rtx temp
= gen_reg_rtx (mode
);
5177 rtx temp2
= gen_reg_rtx (mode
);
5179 emit_insn (gen_rtx_SET (temp
,
5180 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5181 operands
[2], const0_rtx
)));
5183 /* Flip the test for the second operand. */
5184 cond
= gen_rtx_fmt_ee ((code
== EQ
) ? NE
: EQ
, GET_MODE (op0
), op0
, op1
);
5186 emit_insn (gen_rtx_SET (temp2
,
5187 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5188 operands
[3], const0_rtx
)));
5190 /* Merge the two results, at least one is guaranteed to be zero. */
5191 emit_insn (gen_rtx_SET (operands
[0], gen_rtx_IOR (mode
, temp
, temp2
)));
5195 if (FLOAT_MODE_P (GET_MODE (operands
[2])) && !ISA_HAS_SEL
)
5197 operands
[2] = force_reg (GET_MODE (operands
[0]), operands
[2]);
5198 operands
[3] = force_reg (GET_MODE (operands
[0]), operands
[3]);
5201 emit_insn (gen_rtx_SET (operands
[0],
5202 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5203 operands
[2], operands
[3])));
5207 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5210 mips_expand_conditional_trap (rtx comparison
)
5216 /* MIPS conditional trap instructions don't have GT or LE flavors,
5217 so we must swap the operands and convert to LT and GE respectively. */
5218 code
= GET_CODE (comparison
);
5225 code
= swap_condition (code
);
5226 op0
= XEXP (comparison
, 1);
5227 op1
= XEXP (comparison
, 0);
5231 op0
= XEXP (comparison
, 0);
5232 op1
= XEXP (comparison
, 1);
5236 mode
= GET_MODE (XEXP (comparison
, 0));
5237 op0
= force_reg (mode
, op0
);
5238 if (!(ISA_HAS_COND_TRAPI
5239 ? arith_operand (op1
, mode
)
5240 : reg_or_0_operand (op1
, mode
)))
5241 op1
= force_reg (mode
, op1
);
5243 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5244 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5248 /* Initialize *CUM for a call to a function of type FNTYPE. */
5251 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5253 memset (cum
, 0, sizeof (*cum
));
5254 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5255 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5258 /* Fill INFO with information about a single argument. CUM is the
5259 cumulative state for earlier arguments. MODE is the mode of this
5260 argument and TYPE is its type (if known). NAMED is true if this
5261 is a named (fixed) argument rather than a variable one. */
5264 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5265 machine_mode mode
, const_tree type
, bool named
)
5267 bool doubleword_aligned_p
;
5268 unsigned int num_bytes
, num_words
, max_regs
;
5270 /* Work out the size of the argument. */
5271 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5272 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5274 /* Decide whether it should go in a floating-point register, assuming
5275 one is free. Later code checks for availability.
5277 The checks against UNITS_PER_FPVALUE handle the soft-float and
5278 single-float cases. */
5282 /* The EABI conventions have traditionally been defined in terms
5283 of TYPE_MODE, regardless of the actual type. */
5284 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5285 || mode
== V2SFmode
)
5286 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5291 /* Only leading floating-point scalars are passed in
5292 floating-point registers. We also handle vector floats the same
5293 say, which is OK because they are not covered by the standard ABI. */
5294 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5295 info
->fpr_p
= (!cum
->gp_reg_found
5296 && cum
->arg_number
< 2
5298 || SCALAR_FLOAT_TYPE_P (type
)
5299 || VECTOR_FLOAT_TYPE_P (type
))
5300 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5301 || mode
== V2SFmode
)
5302 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5307 /* Scalar, complex and vector floating-point types are passed in
5308 floating-point registers, as long as this is a named rather
5309 than a variable argument. */
5310 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5311 info
->fpr_p
= (named
5312 && (type
== 0 || FLOAT_TYPE_P (type
))
5313 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5314 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5315 || mode
== V2SFmode
)
5316 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5318 /* ??? According to the ABI documentation, the real and imaginary
5319 parts of complex floats should be passed in individual registers.
5320 The real and imaginary parts of stack arguments are supposed
5321 to be contiguous and there should be an extra word of padding
5324 This has two problems. First, it makes it impossible to use a
5325 single "void *" va_list type, since register and stack arguments
5326 are passed differently. (At the time of writing, MIPSpro cannot
5327 handle complex float varargs correctly.) Second, it's unclear
5328 what should happen when there is only one register free.
5330 For now, we assume that named complex floats should go into FPRs
5331 if there are two FPRs free, otherwise they should be passed in the
5332 same way as a struct containing two floats. */
5334 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5335 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5337 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5338 info
->fpr_p
= false;
5348 /* See whether the argument has doubleword alignment. */
5349 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5352 /* Set REG_OFFSET to the register count we're interested in.
5353 The EABI allocates the floating-point registers separately,
5354 but the other ABIs allocate them like integer registers. */
5355 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5359 /* Advance to an even register if the argument is doubleword-aligned. */
5360 if (doubleword_aligned_p
)
5361 info
->reg_offset
+= info
->reg_offset
& 1;
5363 /* Work out the offset of a stack argument. */
5364 info
->stack_offset
= cum
->stack_words
;
5365 if (doubleword_aligned_p
)
5366 info
->stack_offset
+= info
->stack_offset
& 1;
5368 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5370 /* Partition the argument between registers and stack. */
5371 info
->reg_words
= MIN (num_words
, max_regs
);
5372 info
->stack_words
= num_words
- info
->reg_words
;
5375 /* INFO describes a register argument that has the normal format for the
5376 argument's mode. Return the register it uses, assuming that FPRs are
5377 available if HARD_FLOAT_P. */
5380 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5382 if (!info
->fpr_p
|| !hard_float_p
)
5383 return GP_ARG_FIRST
+ info
->reg_offset
;
5384 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5385 /* In o32, the second argument is always passed in $f14
5386 for TARGET_DOUBLE_FLOAT, regardless of whether the
5387 first argument was a word or doubleword. */
5388 return FP_ARG_FIRST
+ 2;
5390 return FP_ARG_FIRST
+ info
->reg_offset
;
5393 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5396 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5398 return !TARGET_OLDABI
;
5401 /* Implement TARGET_FUNCTION_ARG. */
5404 mips_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
5405 const_tree type
, bool named
)
5407 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5408 struct mips_arg_info info
;
5410 /* We will be called with a mode of VOIDmode after the last argument
5411 has been seen. Whatever we return will be passed to the call expander.
5412 If we need a MIPS16 fp_code, return a REG with the code stored as
5414 if (mode
== VOIDmode
)
5416 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5417 return gen_rtx_REG ((machine_mode
) cum
->fp_code
, 0);
5422 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5424 /* Return straight away if the whole argument is passed on the stack. */
5425 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5428 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5429 contains a double in its entirety, then that 64-bit chunk is passed
5430 in a floating-point register. */
5432 && TARGET_HARD_FLOAT
5435 && TREE_CODE (type
) == RECORD_TYPE
5436 && TYPE_SIZE_UNIT (type
)
5437 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5441 /* First check to see if there is any such field. */
5442 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5443 if (TREE_CODE (field
) == FIELD_DECL
5444 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5445 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5446 && tree_fits_shwi_p (bit_position (field
))
5447 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5452 /* Now handle the special case by returning a PARALLEL
5453 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5454 chunks are passed in registers. */
5456 HOST_WIDE_INT bitpos
;
5459 /* assign_parms checks the mode of ENTRY_PARM, so we must
5460 use the actual mode here. */
5461 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5464 field
= TYPE_FIELDS (type
);
5465 for (i
= 0; i
< info
.reg_words
; i
++)
5469 for (; field
; field
= DECL_CHAIN (field
))
5470 if (TREE_CODE (field
) == FIELD_DECL
5471 && int_bit_position (field
) >= bitpos
)
5475 && int_bit_position (field
) == bitpos
5476 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5477 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5478 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5480 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5483 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5484 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5486 bitpos
+= BITS_PER_WORD
;
5492 /* Handle the n32/n64 conventions for passing complex floating-point
5493 arguments in FPR pairs. The real part goes in the lower register
5494 and the imaginary part goes in the upper register. */
5497 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5503 inner
= GET_MODE_INNER (mode
);
5504 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5505 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5507 /* Real part in registers, imaginary part on stack. */
5508 gcc_assert (info
.stack_words
== info
.reg_words
);
5509 return gen_rtx_REG (inner
, regno
);
5513 gcc_assert (info
.stack_words
== 0);
5514 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5515 gen_rtx_REG (inner
, regno
),
5517 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5519 regno
+ info
.reg_words
/ 2),
5520 GEN_INT (GET_MODE_SIZE (inner
)));
5521 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5525 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5528 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5531 mips_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
5532 const_tree type
, bool named
)
5534 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5535 struct mips_arg_info info
;
5537 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5540 cum
->gp_reg_found
= true;
5542 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5543 an explanation of what this code does. It assumes that we're using
5544 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5546 if (cum
->arg_number
< 2 && info
.fpr_p
)
5547 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5549 /* Advance the register count. This has the effect of setting
5550 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5551 argument required us to skip the final GPR and pass the whole
5552 argument on the stack. */
5553 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5554 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5555 else if (info
.reg_words
> 0)
5556 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5558 /* Advance the stack word count. */
5559 if (info
.stack_words
> 0)
5560 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5565 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5568 mips_arg_partial_bytes (cumulative_args_t cum
,
5569 machine_mode mode
, tree type
, bool named
)
5571 struct mips_arg_info info
;
5573 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5574 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5577 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5578 least PARM_BOUNDARY bits of alignment, but will be given anything up
5579 to STACK_BOUNDARY bits if the type requires it. */
5582 mips_function_arg_boundary (machine_mode mode
, const_tree type
)
5584 unsigned int alignment
;
5586 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5587 if (alignment
< PARM_BOUNDARY
)
5588 alignment
= PARM_BOUNDARY
;
5589 if (alignment
> STACK_BOUNDARY
)
5590 alignment
= STACK_BOUNDARY
;
5594 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
5597 mips_get_reg_raw_mode (int regno
)
5599 if (TARGET_FLOATXX
&& FP_REG_P (regno
))
5601 return default_get_reg_raw_mode (regno
);
5604 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5605 upward rather than downward. In other words, return true if the
5606 first byte of the stack slot has useful data, false if the last
5610 mips_pad_arg_upward (machine_mode mode
, const_tree type
)
5612 /* On little-endian targets, the first byte of every stack argument
5613 is passed in the first byte of the stack slot. */
5614 if (!BYTES_BIG_ENDIAN
)
5617 /* Otherwise, integral types are padded downward: the last byte of a
5618 stack argument is passed in the last byte of the stack slot. */
5620 ? (INTEGRAL_TYPE_P (type
)
5621 || POINTER_TYPE_P (type
)
5622 || FIXED_POINT_TYPE_P (type
))
5623 : (SCALAR_INT_MODE_P (mode
)
5624 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5627 /* Big-endian o64 pads floating-point arguments downward. */
5628 if (mips_abi
== ABI_O64
)
5629 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5632 /* Other types are padded upward for o32, o64, n32 and n64. */
5633 if (mips_abi
!= ABI_EABI
)
5636 /* Arguments smaller than a stack slot are padded downward. */
5637 if (mode
!= BLKmode
)
5638 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5640 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5643 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5644 if the least significant byte of the register has useful data. Return
5645 the opposite if the most significant byte does. */
5648 mips_pad_reg_upward (machine_mode mode
, tree type
)
5650 /* No shifting is required for floating-point arguments. */
5651 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5652 return !BYTES_BIG_ENDIAN
;
5654 /* Otherwise, apply the same padding to register arguments as we do
5655 to stack arguments. */
5656 return mips_pad_arg_upward (mode
, type
);
5659 /* Return nonzero when an argument must be passed by reference. */
5662 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5663 machine_mode mode
, const_tree type
,
5664 bool named ATTRIBUTE_UNUSED
)
5666 if (mips_abi
== ABI_EABI
)
5670 /* ??? How should SCmode be handled? */
5671 if (mode
== DImode
|| mode
== DFmode
5672 || mode
== DQmode
|| mode
== UDQmode
5673 || mode
== DAmode
|| mode
== UDAmode
)
5676 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5677 return size
== -1 || size
> UNITS_PER_WORD
;
5681 /* If we have a variable-sized parameter, we have no choice. */
5682 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5686 /* Implement TARGET_CALLEE_COPIES. */
5689 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5690 machine_mode mode ATTRIBUTE_UNUSED
,
5691 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5693 return mips_abi
== ABI_EABI
&& named
;
5696 /* See whether VALTYPE is a record whose fields should be returned in
5697 floating-point registers. If so, return the number of fields and
5698 list them in FIELDS (which should have two elements). Return 0
5701 For n32 & n64, a structure with one or two fields is returned in
5702 floating-point registers as long as every field has a floating-point
5706 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5714 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5718 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5720 if (TREE_CODE (field
) != FIELD_DECL
)
5723 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5729 fields
[i
++] = field
;
5734 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5735 a value in the most significant part of $2/$3 if:
5737 - the target is big-endian;
5739 - the value has a structure or union type (we generalize this to
5740 cover aggregates from other languages too); and
5742 - the structure is not returned in floating-point registers. */
5745 mips_return_in_msb (const_tree valtype
)
5749 return (TARGET_NEWABI
5750 && TARGET_BIG_ENDIAN
5751 && AGGREGATE_TYPE_P (valtype
)
5752 && mips_fpr_return_fields (valtype
, fields
) == 0);
5755 /* Return true if the function return value MODE will get returned in a
5756 floating-point register. */
5759 mips_return_mode_in_fpr_p (machine_mode mode
)
5761 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5762 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5764 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5765 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5768 /* Return the representation of an FPR return register when the
5769 value being returned in FP_RETURN has mode VALUE_MODE and the
5770 return type itself has mode TYPE_MODE. On NewABI targets,
5771 the two modes may be different for structures like:
5773 struct __attribute__((packed)) foo { float f; }
5775 where we return the SFmode value of "f" in FP_RETURN, but where
5776 the structure itself has mode BLKmode. */
5779 mips_return_fpr_single (machine_mode type_mode
,
5780 machine_mode value_mode
)
5784 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5785 if (type_mode
!= value_mode
)
5787 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5788 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5793 /* Return a composite value in a pair of floating-point registers.
5794 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5795 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5798 For n32 & n64, $f0 always holds the first value and $f2 the second.
5799 Otherwise the values are packed together as closely as possible. */
5802 mips_return_fpr_pair (machine_mode mode
,
5803 machine_mode mode1
, HOST_WIDE_INT offset1
,
5804 machine_mode mode2
, HOST_WIDE_INT offset2
)
5808 inc
= (TARGET_NEWABI
|| mips_abi
== ABI_32
? 2 : MAX_FPRS_PER_FMT
);
5809 return gen_rtx_PARALLEL
5812 gen_rtx_EXPR_LIST (VOIDmode
,
5813 gen_rtx_REG (mode1
, FP_RETURN
),
5815 gen_rtx_EXPR_LIST (VOIDmode
,
5816 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5817 GEN_INT (offset2
))));
5821 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5822 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5823 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5826 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5835 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5836 func
= fn_decl_or_type
;
5840 mode
= TYPE_MODE (valtype
);
5841 unsigned_p
= TYPE_UNSIGNED (valtype
);
5843 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5844 return values, promote the mode here too. */
5845 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5847 /* Handle structures whose fields are returned in $f0/$f2. */
5848 switch (mips_fpr_return_fields (valtype
, fields
))
5851 return mips_return_fpr_single (mode
,
5852 TYPE_MODE (TREE_TYPE (fields
[0])));
5855 return mips_return_fpr_pair (mode
,
5856 TYPE_MODE (TREE_TYPE (fields
[0])),
5857 int_byte_position (fields
[0]),
5858 TYPE_MODE (TREE_TYPE (fields
[1])),
5859 int_byte_position (fields
[1]));
5862 /* If a value is passed in the most significant part of a register, see
5863 whether we have to round the mode up to a whole number of words. */
5864 if (mips_return_in_msb (valtype
))
5866 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5867 if (size
% UNITS_PER_WORD
!= 0)
5869 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5870 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5874 /* For EABI, the class of return register depends entirely on MODE.
5875 For example, "struct { some_type x; }" and "union { some_type x; }"
5876 are returned in the same way as a bare "some_type" would be.
5877 Other ABIs only use FPRs for scalar, complex or vector types. */
5878 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5879 return gen_rtx_REG (mode
, GP_RETURN
);
5884 /* Handle long doubles for n32 & n64. */
5886 return mips_return_fpr_pair (mode
,
5888 DImode
, GET_MODE_SIZE (mode
) / 2);
5890 if (mips_return_mode_in_fpr_p (mode
))
5892 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5893 return mips_return_fpr_pair (mode
,
5894 GET_MODE_INNER (mode
), 0,
5895 GET_MODE_INNER (mode
),
5896 GET_MODE_SIZE (mode
) / 2);
5898 return gen_rtx_REG (mode
, FP_RETURN
);
5902 return gen_rtx_REG (mode
, GP_RETURN
);
5905 /* Implement TARGET_FUNCTION_VALUE. */
5908 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5909 bool outgoing ATTRIBUTE_UNUSED
)
5911 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5914 /* Implement TARGET_LIBCALL_VALUE. */
5917 mips_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5919 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5922 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5924 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
5927 mips_function_value_regno_p (const unsigned int regno
)
5929 /* Most types only require one GPR or one FPR for return values but for
5930 hard-float two FPRs can be used for _Complex types (for all ABIs)
5931 and long doubles (for n64). */
5932 if (regno
== GP_RETURN
5933 || regno
== FP_RETURN
5934 || (FP_RETURN
!= GP_RETURN
5935 && regno
== FP_RETURN
+ 2))
5938 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
5939 This does not apply to o32 FPXX as floating-point function argument and
5940 return registers are described as 64-bit even though floating-point
5941 registers are primarily described as 32-bit internally.
5942 See: mips_get_reg_raw_mode. */
5943 if ((mips_abi
== ABI_32
&& TARGET_FLOAT32
)
5944 && FP_RETURN
!= GP_RETURN
5945 && (regno
== FP_RETURN
+ 1
5946 || regno
== FP_RETURN
+ 3))
5952 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5953 all BLKmode objects are returned in memory. Under the n32, n64
5954 and embedded ABIs, small structures are returned in a register.
5955 Objects with varying size must still be returned in memory, of
5959 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5961 return (TARGET_OLDABI
5962 ? TYPE_MODE (type
) == BLKmode
5963 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5966 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5969 mips_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
5970 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5973 CUMULATIVE_ARGS local_cum
;
5974 int gp_saved
, fp_saved
;
5976 /* The caller has advanced CUM up to, but not beyond, the last named
5977 argument. Advance a local copy of CUM past the last "real" named
5978 argument, to find out how many registers are left over. */
5979 local_cum
= *get_cumulative_args (cum
);
5980 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5983 /* Found out how many registers we need to save. */
5984 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5985 fp_saved
= (EABI_FLOAT_VARARGS_P
5986 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5995 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5996 REG_PARM_STACK_SPACE (cfun
->decl
)
5997 - gp_saved
* UNITS_PER_WORD
);
5998 mem
= gen_frame_mem (BLKmode
, ptr
);
5999 set_mem_alias_set (mem
, get_varargs_alias_set ());
6001 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
6006 /* We can't use move_block_from_reg, because it will use
6011 /* Set OFF to the offset from virtual_incoming_args_rtx of
6012 the first float register. The FP save area lies below
6013 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
6014 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
6015 off
-= fp_saved
* UNITS_PER_FPREG
;
6017 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6019 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
6020 i
+= MAX_FPRS_PER_FMT
)
6024 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
6025 mem
= gen_frame_mem (mode
, ptr
);
6026 set_mem_alias_set (mem
, get_varargs_alias_set ());
6027 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
6028 off
+= UNITS_PER_HWFPVALUE
;
6032 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
6033 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
6034 + fp_saved
* UNITS_PER_FPREG
);
6037 /* Implement TARGET_BUILTIN_VA_LIST. */
6040 mips_build_builtin_va_list (void)
6042 if (EABI_FLOAT_VARARGS_P
)
6044 /* We keep 3 pointers, and two offsets.
6046 Two pointers are to the overflow area, which starts at the CFA.
6047 One of these is constant, for addressing into the GPR save area
6048 below it. The other is advanced up the stack through the
6051 The third pointer is to the bottom of the GPR save area.
6052 Since the FPR save area is just below it, we can address
6053 FPR slots off this pointer.
6055 We also keep two one-byte offsets, which are to be subtracted
6056 from the constant pointers to yield addresses in the GPR and
6057 FPR save areas. These are downcounted as float or non-float
6058 arguments are used, and when they get to zero, the argument
6059 must be obtained from the overflow region. */
6060 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
6063 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
6065 f_ovfl
= build_decl (BUILTINS_LOCATION
,
6066 FIELD_DECL
, get_identifier ("__overflow_argptr"),
6068 f_gtop
= build_decl (BUILTINS_LOCATION
,
6069 FIELD_DECL
, get_identifier ("__gpr_top"),
6071 f_ftop
= build_decl (BUILTINS_LOCATION
,
6072 FIELD_DECL
, get_identifier ("__fpr_top"),
6074 f_goff
= build_decl (BUILTINS_LOCATION
,
6075 FIELD_DECL
, get_identifier ("__gpr_offset"),
6076 unsigned_char_type_node
);
6077 f_foff
= build_decl (BUILTINS_LOCATION
,
6078 FIELD_DECL
, get_identifier ("__fpr_offset"),
6079 unsigned_char_type_node
);
6080 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
6081 warn on every user file. */
6082 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
6083 array
= build_array_type (unsigned_char_type_node
,
6084 build_index_type (index
));
6085 f_res
= build_decl (BUILTINS_LOCATION
,
6086 FIELD_DECL
, get_identifier ("__reserved"), array
);
6088 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
6089 DECL_FIELD_CONTEXT (f_gtop
) = record
;
6090 DECL_FIELD_CONTEXT (f_ftop
) = record
;
6091 DECL_FIELD_CONTEXT (f_goff
) = record
;
6092 DECL_FIELD_CONTEXT (f_foff
) = record
;
6093 DECL_FIELD_CONTEXT (f_res
) = record
;
6095 TYPE_FIELDS (record
) = f_ovfl
;
6096 DECL_CHAIN (f_ovfl
) = f_gtop
;
6097 DECL_CHAIN (f_gtop
) = f_ftop
;
6098 DECL_CHAIN (f_ftop
) = f_goff
;
6099 DECL_CHAIN (f_goff
) = f_foff
;
6100 DECL_CHAIN (f_foff
) = f_res
;
6102 layout_type (record
);
6106 /* Otherwise, we use 'void *'. */
6107 return ptr_type_node
;
6110 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6113 mips_va_start (tree valist
, rtx nextarg
)
6115 if (EABI_FLOAT_VARARGS_P
)
6117 const CUMULATIVE_ARGS
*cum
;
6118 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6119 tree ovfl
, gtop
, ftop
, goff
, foff
;
6121 int gpr_save_area_size
;
6122 int fpr_save_area_size
;
6125 cum
= &crtl
->args
.info
;
6127 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
6129 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
6131 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6132 f_gtop
= DECL_CHAIN (f_ovfl
);
6133 f_ftop
= DECL_CHAIN (f_gtop
);
6134 f_goff
= DECL_CHAIN (f_ftop
);
6135 f_foff
= DECL_CHAIN (f_goff
);
6137 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6139 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
6141 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
6143 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
6145 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
6148 /* Emit code to initialize OVFL, which points to the next varargs
6149 stack argument. CUM->STACK_WORDS gives the number of stack
6150 words used by named arguments. */
6151 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
6152 if (cum
->stack_words
> 0)
6153 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
6154 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
6155 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6157 /* Emit code to initialize GTOP, the top of the GPR save area. */
6158 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
6159 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
6160 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6162 /* Emit code to initialize FTOP, the top of the FPR save area.
6163 This address is gpr_save_area_bytes below GTOP, rounded
6164 down to the next fp-aligned boundary. */
6165 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
6166 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
6167 fpr_offset
&= -UNITS_PER_FPVALUE
;
6169 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
6170 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
6171 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6173 /* Emit code to initialize GOFF, the offset from GTOP of the
6174 next GPR argument. */
6175 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
6176 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
6177 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6179 /* Likewise emit code to initialize FOFF, the offset from FTOP
6180 of the next FPR argument. */
6181 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
6182 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
6183 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6187 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6188 std_expand_builtin_va_start (valist
, nextarg
);
6192 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6196 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6199 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6200 unsigned HOST_WIDE_INT align
, boundary
;
6203 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6205 type
= build_pointer_type (type
);
6207 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6208 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6210 /* When we align parameter on stack for caller, if the parameter
6211 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6212 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6213 here with caller. */
6214 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6215 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6217 boundary
/= BITS_PER_UNIT
;
6219 /* Hoist the valist value into a temporary for the moment. */
6220 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6222 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6223 requires greater alignment, we must perform dynamic alignment. */
6224 if (boundary
> align
)
6226 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6227 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6228 gimplify_and_add (t
, pre_p
);
6230 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6231 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6233 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6234 gimplify_and_add (t
, pre_p
);
6239 /* If the actual alignment is less than the alignment of the type,
6240 adjust the type accordingly so that we don't assume strict alignment
6241 when dereferencing the pointer. */
6242 boundary
*= BITS_PER_UNIT
;
6243 if (boundary
< TYPE_ALIGN (type
))
6245 type
= build_variant_type_copy (type
);
6246 TYPE_ALIGN (type
) = boundary
;
6249 /* Compute the rounded size of the type. */
6250 type_size
= size_in_bytes (type
);
6251 rounded_size
= round_up (type_size
, align
);
6253 /* Reduce rounded_size so it's sharable with the postqueue. */
6254 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6258 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6260 /* Small args are padded downward. */
6261 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6262 rounded_size
, size_int (align
));
6263 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6264 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6265 addr
= fold_build_pointer_plus (addr
, t
);
6268 /* Compute new value for AP. */
6269 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6270 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6271 gimplify_and_add (t
, pre_p
);
6273 addr
= fold_convert (build_pointer_type (type
), addr
);
6276 addr
= build_va_arg_indirect_ref (addr
);
6278 return build_va_arg_indirect_ref (addr
);
6281 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6284 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6290 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6292 type
= build_pointer_type (type
);
6294 if (!EABI_FLOAT_VARARGS_P
)
6295 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6298 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6299 tree ovfl
, top
, off
, align
;
6300 HOST_WIDE_INT size
, rsize
, osize
;
6303 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6304 f_gtop
= DECL_CHAIN (f_ovfl
);
6305 f_ftop
= DECL_CHAIN (f_gtop
);
6306 f_goff
= DECL_CHAIN (f_ftop
);
6307 f_foff
= DECL_CHAIN (f_goff
);
6311 TOP be the top of the GPR or FPR save area;
6312 OFF be the offset from TOP of the next register;
6313 ADDR_RTX be the address of the argument;
6314 SIZE be the number of bytes in the argument type;
6315 RSIZE be the number of bytes used to store the argument
6316 when it's in the register save area; and
6317 OSIZE be the number of bytes used to store it when it's
6318 in the stack overflow area.
6320 The code we want is:
6322 1: off &= -rsize; // round down
6325 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6330 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6331 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6335 [1] and [9] can sometimes be optimized away. */
6337 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6339 size
= int_size_in_bytes (type
);
6341 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6342 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6344 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6345 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6346 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6347 unshare_expr (valist
), f_foff
, NULL_TREE
);
6349 /* When va_start saves FPR arguments to the stack, each slot
6350 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6351 argument's precision. */
6352 rsize
= UNITS_PER_HWFPVALUE
;
6354 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6355 (= PARM_BOUNDARY bits). This can be different from RSIZE
6358 (1) On 32-bit targets when TYPE is a structure such as:
6360 struct s { float f; };
6362 Such structures are passed in paired FPRs, so RSIZE
6363 will be 8 bytes. However, the structure only takes
6364 up 4 bytes of memory, so OSIZE will only be 4.
6366 (2) In combinations such as -mgp64 -msingle-float
6367 -fshort-double. Doubles passed in registers will then take
6368 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6369 stack take up UNITS_PER_WORD bytes. */
6370 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6374 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6375 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6376 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6377 unshare_expr (valist
), f_goff
, NULL_TREE
);
6378 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6379 if (rsize
> UNITS_PER_WORD
)
6381 /* [1] Emit code for: off &= -rsize. */
6382 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6383 build_int_cst (TREE_TYPE (off
), -rsize
));
6384 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6389 /* [2] Emit code to branch if off == 0. */
6390 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6391 build_int_cst (TREE_TYPE (off
), 0));
6392 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6394 /* [5] Emit code for: off -= rsize. We do this as a form of
6395 post-decrement not available to C. */
6396 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6397 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6399 /* [4] Emit code for:
6400 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6401 t
= fold_convert (sizetype
, t
);
6402 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6403 t
= fold_build_pointer_plus (top
, t
);
6404 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6405 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6406 COND_EXPR_THEN (addr
) = t
;
6408 if (osize
> UNITS_PER_WORD
)
6410 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6411 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6412 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6413 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6414 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6415 unshare_expr (ovfl
), t
);
6420 /* [10, 11] Emit code for:
6421 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6423 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6424 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6425 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6426 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6428 /* String [9] and [10, 11] together. */
6430 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6431 COND_EXPR_ELSE (addr
) = t
;
6433 addr
= fold_convert (build_pointer_type (type
), addr
);
6434 addr
= build_va_arg_indirect_ref (addr
);
6438 addr
= build_va_arg_indirect_ref (addr
);
6443 /* Declare a unique, locally-binding function called NAME, then start
6447 mips_start_unique_function (const char *name
)
6451 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6452 get_identifier (name
),
6453 build_function_type_list (void_type_node
, NULL_TREE
));
6454 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6455 NULL_TREE
, void_type_node
);
6456 TREE_PUBLIC (decl
) = 1;
6457 TREE_STATIC (decl
) = 1;
6459 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
6461 targetm
.asm_out
.unique_section (decl
, 0);
6462 switch_to_section (get_named_section (decl
, NULL
, 0));
6464 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6465 fputs ("\t.hidden\t", asm_out_file
);
6466 assemble_name (asm_out_file
, name
);
6467 putc ('\n', asm_out_file
);
6470 /* Start a definition of function NAME. MIPS16_P indicates whether the
6471 function contains MIPS16 code. */
6474 mips_start_function_definition (const char *name
, bool mips16_p
)
6477 fprintf (asm_out_file
, "\t.set\tmips16\n");
6479 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6481 if (TARGET_MICROMIPS
)
6482 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6483 #ifdef HAVE_GAS_MICROMIPS
6485 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6488 if (!flag_inhibit_size_directive
)
6490 fputs ("\t.ent\t", asm_out_file
);
6491 assemble_name (asm_out_file
, name
);
6492 fputs ("\n", asm_out_file
);
6495 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6497 /* Start the definition proper. */
6498 assemble_name (asm_out_file
, name
);
6499 fputs (":\n", asm_out_file
);
6502 /* End a function definition started by mips_start_function_definition. */
6505 mips_end_function_definition (const char *name
)
6507 if (!flag_inhibit_size_directive
)
6509 fputs ("\t.end\t", asm_out_file
);
6510 assemble_name (asm_out_file
, name
);
6511 fputs ("\n", asm_out_file
);
6515 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6516 then free *STUB_PTR. */
6519 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
6521 mips_one_only_stub
*stub
= *stub_ptr
;
6525 const char *name
= stub
->get_name ();
6526 mips_start_unique_function (name
);
6527 mips_start_function_definition (name
, false);
6528 stub
->output_body ();
6529 mips_end_function_definition (name
);
6534 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6537 mips_ok_for_lazy_binding_p (rtx x
)
6539 return (TARGET_USE_GOT
6540 && GET_CODE (x
) == SYMBOL_REF
6541 && !SYMBOL_REF_BIND_NOW_P (x
)
6542 && !mips_symbol_binds_local_p (x
));
6545 /* Load function address ADDR into register DEST. TYPE is as for
6546 mips_expand_call. Return true if we used an explicit lazy-binding
6550 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6552 /* If we're generating PIC, and this call is to a global function,
6553 try to allow its address to be resolved lazily. This isn't
6554 possible for sibcalls when $gp is call-saved because the value
6555 of $gp on entry to the stub would be our caller's gp, not ours. */
6556 if (TARGET_EXPLICIT_RELOCS
6557 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6558 && mips_ok_for_lazy_binding_p (addr
))
6560 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6561 emit_insn (gen_rtx_SET (dest
, addr
));
6566 mips_emit_move (dest
, addr
);
6571 /* Each locally-defined hard-float MIPS16 function has a local symbol
6572 associated with it. This hash table maps the function symbol (FUNC)
6573 to the local symbol (LOCAL). */
6574 static GTY (()) hash_map
<nofree_string_hash
, rtx
> *mips16_local_aliases
;
6576 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6577 Return a local alias for it, creating a new one if necessary. */
6580 mips16_local_alias (rtx func
)
6582 /* Create the hash table if this is the first call. */
6583 if (mips16_local_aliases
== NULL
)
6584 mips16_local_aliases
= hash_map
<nofree_string_hash
, rtx
>::create_ggc (37);
6586 /* Look up the function symbol, creating a new entry if need be. */
6588 const char *func_name
= XSTR (func
, 0);
6589 rtx
*slot
= &mips16_local_aliases
->get_or_insert (func_name
, &existed
);
6590 gcc_assert (slot
!= NULL
);
6596 /* Create a new SYMBOL_REF for the local symbol. The choice of
6597 __fn_local_* is based on the __fn_stub_* names that we've
6598 traditionally used for the non-MIPS16 stub. */
6599 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6600 const char *local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6601 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6602 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6604 /* Create a new structure to represent the mapping. */
6610 /* A chained list of functions for which mips16_build_call_stub has already
6611 generated a stub. NAME is the name of the function and FP_RET_P is true
6612 if the function returns a value in floating-point registers. */
6613 struct mips16_stub
{
6614 struct mips16_stub
*next
;
6618 static struct mips16_stub
*mips16_stubs
;
6620 /* Return the two-character string that identifies floating-point
6621 return mode MODE in the name of a MIPS16 function stub. */
6624 mips16_call_stub_mode_suffix (machine_mode mode
)
6628 else if (mode
== DFmode
)
6630 else if (mode
== SCmode
)
6632 else if (mode
== DCmode
)
6634 else if (mode
== V2SFmode
)
6636 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
);
6643 /* Write instructions to move a 32-bit value between general register
6644 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6645 from GPREG to FPREG and 'f' to move in the opposite direction. */
6648 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6650 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6651 reg_names
[gpreg
], reg_names
[fpreg
]);
6654 /* Likewise for 64-bit values. */
6657 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6660 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6661 reg_names
[gpreg
], reg_names
[fpreg
]);
6662 else if (ISA_HAS_MXHC1
)
6664 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6665 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6666 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6667 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6669 else if (TARGET_FLOATXX
&& direction
== 't')
6671 /* Use the argument save area to move via memory. */
6672 fprintf (asm_out_file
, "\tsw\t%s,0($sp)\n", reg_names
[gpreg
]);
6673 fprintf (asm_out_file
, "\tsw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
6674 fprintf (asm_out_file
, "\tldc1\t%s,0($sp)\n", reg_names
[fpreg
]);
6676 else if (TARGET_FLOATXX
&& direction
== 'f')
6678 /* Use the argument save area to move via memory. */
6679 fprintf (asm_out_file
, "\tsdc1\t%s,0($sp)\n", reg_names
[fpreg
]);
6680 fprintf (asm_out_file
, "\tlw\t%s,0($sp)\n", reg_names
[gpreg
]);
6681 fprintf (asm_out_file
, "\tlw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
6685 /* Move the least-significant word. */
6686 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6687 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6688 /* ...then the most significant word. */
6689 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6690 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6694 /* Write out code to move floating-point arguments into or out of
6695 general registers. FP_CODE is the code describing which arguments
6696 are present (see the comment above the definition of CUMULATIVE_ARGS
6697 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6700 mips_output_args_xfer (int fp_code
, char direction
)
6702 unsigned int gparg
, fparg
, f
;
6703 CUMULATIVE_ARGS cum
;
6705 /* This code only works for o32 and o64. */
6706 gcc_assert (TARGET_OLDABI
);
6708 mips_init_cumulative_args (&cum
, NULL
);
6710 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6713 struct mips_arg_info info
;
6717 else if ((f
& 3) == 2)
6722 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6723 gparg
= mips_arg_regno (&info
, false);
6724 fparg
= mips_arg_regno (&info
, true);
6727 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6729 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6731 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6735 /* Write a MIPS16 stub for the current function. This stub is used
6736 for functions which take arguments in the floating-point registers.
6737 It is normal-mode code that moves the floating-point arguments
6738 into the general registers and then jumps to the MIPS16 code. */
6741 mips16_build_function_stub (void)
6743 const char *fnname
, *alias_name
, *separator
;
6744 char *secname
, *stubname
;
6749 /* Create the name of the stub, and its unique section. */
6750 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6751 alias
= mips16_local_alias (symbol
);
6753 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6754 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6755 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6756 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6758 /* Build a decl for the stub. */
6759 stubdecl
= build_decl (BUILTINS_LOCATION
,
6760 FUNCTION_DECL
, get_identifier (stubname
),
6761 build_function_type_list (void_type_node
, NULL_TREE
));
6762 set_decl_section_name (stubdecl
, secname
);
6763 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6764 RESULT_DECL
, NULL_TREE
, void_type_node
);
6766 /* Output a comment. */
6767 fprintf (asm_out_file
, "\t# Stub function for %s (",
6768 current_function_name ());
6770 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6772 fprintf (asm_out_file
, "%s%s", separator
,
6773 (f
& 3) == 1 ? "float" : "double");
6776 fprintf (asm_out_file
, ")\n");
6778 /* Start the function definition. */
6779 assemble_start_function (stubdecl
, stubname
);
6780 mips_start_function_definition (stubname
, false);
6782 /* If generating pic2 code, either set up the global pointer or
6784 if (TARGET_ABICALLS_PIC2
)
6786 if (TARGET_ABSOLUTE_ABICALLS
)
6787 fprintf (asm_out_file
, "\t.option\tpic0\n");
6790 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6791 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6792 target function is. Use a local GOT access when loading the
6793 symbol, to cut down on the number of unnecessary GOT entries
6794 for stubs that aren't needed. */
6795 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6800 /* Load the address of the MIPS16 function into $25. Do this first so
6801 that targets with coprocessor interlocks can use an MFC1 to fill the
6803 output_asm_insn ("la\t%^,%0", &symbol
);
6805 /* Move the arguments from floating-point registers to general registers. */
6806 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6808 /* Jump to the MIPS16 function. */
6809 output_asm_insn ("jr\t%^", NULL
);
6811 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6812 fprintf (asm_out_file
, "\t.option\tpic2\n");
6814 mips_end_function_definition (stubname
);
6816 /* If the linker needs to create a dynamic symbol for the target
6817 function, it will associate the symbol with the stub (which,
6818 unlike the target function, follows the proper calling conventions).
6819 It is therefore useful to have a local alias for the target function,
6820 so that it can still be identified as MIPS16 code. As an optimization,
6821 this symbol can also be used for indirect MIPS16 references from
6822 within this file. */
6823 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6825 switch_to_section (function_section (current_function_decl
));
6828 /* The current function is a MIPS16 function that returns a value in an FPR.
6829 Copy the return value from its soft-float to its hard-float location.
6830 libgcc2 has special non-MIPS16 helper functions for each case. */
6833 mips16_copy_fpr_return_value (void)
6835 rtx fn
, insn
, retval
;
6837 machine_mode return_mode
;
6840 return_type
= DECL_RESULT (current_function_decl
);
6841 return_mode
= DECL_MODE (return_type
);
6843 name
= ACONCAT (("__mips16_ret_",
6844 mips16_call_stub_mode_suffix (return_mode
),
6846 fn
= mips16_stub_function (name
);
6848 /* The function takes arguments in $2 (and possibly $3), so calls
6849 to it cannot be lazily bound. */
6850 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6852 /* Model the call as something that takes the GPR return value as
6853 argument and returns an "updated" value. */
6854 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6855 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6856 const0_rtx
, NULL_RTX
, false);
6857 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6860 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6861 RETVAL is the location of the return value, or null if this is
6862 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6863 arguments and FP_CODE is the code built by mips_function_arg;
6864 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6866 There are three alternatives:
6868 - If a stub was needed, emit the call and return the call insn itself.
6870 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6871 to the new target and return null.
6873 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6876 A stub is needed for calls to functions that, in normal mode,
6877 receive arguments in FPRs or return values in FPRs. The stub
6878 copies the arguments from their soft-float positions to their
6879 hard-float positions, calls the real function, then copies the
6880 return value from its hard-float position to its soft-float
6883 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6884 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6885 automatically redirects the JAL to the stub, otherwise the JAL
6886 continues to call FN directly. */
6889 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6893 struct mips16_stub
*l
;
6897 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6898 we were invoked with the -msoft-float option. */
6899 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6902 /* Figure out whether the value might come back in a floating-point
6904 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6906 /* We don't need to do anything if there were no floating-point
6907 arguments and the value will not be returned in a floating-point
6909 if (fp_code
== 0 && !fp_ret_p
)
6912 /* We don't need to do anything if this is a call to a special
6913 MIPS16 support function. */
6915 if (mips16_stub_function_p (fn
))
6918 /* If we're calling a locally-defined MIPS16 function, we know that
6919 it will return values in both the "soft-float" and "hard-float"
6920 registers. There is no need to use a stub to move the latter
6922 if (fp_code
== 0 && mips16_local_function_p (fn
))
6925 /* This code will only work for o32 and o64 abis. The other ABI's
6926 require more sophisticated support. */
6927 gcc_assert (TARGET_OLDABI
);
6929 /* If we're calling via a function pointer, use one of the magic
6930 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6931 Each stub expects the function address to arrive in register $2. */
6932 if (GET_CODE (fn
) != SYMBOL_REF
6933 || !call_insn_operand (fn
, VOIDmode
))
6940 /* If this is a locally-defined and locally-binding function,
6941 avoid the stub by calling the local alias directly. */
6942 if (mips16_local_function_p (fn
))
6944 *fn_ptr
= mips16_local_alias (fn
);
6948 /* Create a SYMBOL_REF for the libgcc.a function. */
6950 sprintf (buf
, "__mips16_call_stub_%s_%d",
6951 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6954 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6955 stub_fn
= mips16_stub_function (buf
);
6957 /* The function uses $2 as an argument, so calls to it
6958 cannot be lazily bound. */
6959 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6961 /* Load the target function into $2. */
6962 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6963 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6965 /* Emit the call. */
6966 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6967 args_size
, NULL_RTX
, lazy_p
);
6969 /* Tell GCC that this call does indeed use the value of $2. */
6970 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6972 /* If we are handling a floating-point return value, we need to
6973 save $18 in the function prologue. Putting a note on the
6974 call will mean that df_regs_ever_live_p ($18) will be true if the
6975 call is not eliminated, and we can check that in the prologue
6978 CALL_INSN_FUNCTION_USAGE (insn
) =
6979 gen_rtx_EXPR_LIST (VOIDmode
,
6980 gen_rtx_CLOBBER (VOIDmode
,
6981 gen_rtx_REG (word_mode
, 18)),
6982 CALL_INSN_FUNCTION_USAGE (insn
));
6987 /* We know the function we are going to call. If we have already
6988 built a stub, we don't need to do anything further. */
6989 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6990 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6991 if (strcmp (l
->name
, fnname
) == 0)
6996 const char *separator
;
6997 char *secname
, *stubname
;
6998 tree stubid
, stubdecl
;
7001 /* If the function does not return in FPRs, the special stub
7005 If the function does return in FPRs, the stub section is named
7006 .mips16.call.fp.FNNAME
7008 Build a decl for the stub. */
7009 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
7011 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
7013 stubid
= get_identifier (stubname
);
7014 stubdecl
= build_decl (BUILTINS_LOCATION
,
7015 FUNCTION_DECL
, stubid
,
7016 build_function_type_list (void_type_node
,
7018 set_decl_section_name (stubdecl
, secname
);
7019 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7020 RESULT_DECL
, NULL_TREE
,
7023 /* Output a comment. */
7024 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
7026 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
7030 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7032 fprintf (asm_out_file
, "%s%s", separator
,
7033 (f
& 3) == 1 ? "float" : "double");
7036 fprintf (asm_out_file
, ")\n");
7038 /* Start the function definition. */
7039 assemble_start_function (stubdecl
, stubname
);
7040 mips_start_function_definition (stubname
, false);
7044 fprintf (asm_out_file
, "\t.cfi_startproc\n");
7046 /* Create a fake CFA 4 bytes below the stack pointer.
7047 This works around unwinders (like libgcc's) that expect
7048 the CFA for non-signal frames to be unique. */
7049 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
7051 /* "Save" $sp in itself so we don't use the fake CFA.
7052 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
7053 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
7055 /* Save the return address in $18. The stub's caller knows
7056 that $18 might be clobbered, even though $18 is usually
7057 a call-saved register.
7059 Do it early on in case the last move to a floating-point
7060 register can be scheduled into the delay slot of the
7061 call we are about to make. */
7062 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
7063 reg_names
[GP_REG_FIRST
+ 18],
7064 reg_names
[RETURN_ADDR_REGNUM
]);
7068 /* Load the address of the MIPS16 function into $25. Do this
7069 first so that targets with coprocessor interlocks can use
7070 an MFC1 to fill the delay slot. */
7071 if (TARGET_EXPLICIT_RELOCS
)
7073 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
7074 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
7077 output_asm_insn ("la\t%^,%0", &fn
);
7080 /* Move the arguments from general registers to floating-point
7082 mips_output_args_xfer (fp_code
, 't');
7086 /* Now call the non-MIPS16 function. */
7087 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
7088 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
7090 /* Move the result from floating-point registers to
7091 general registers. */
7092 switch (GET_MODE (retval
))
7095 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
7099 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
7100 TARGET_LITTLE_ENDIAN
7103 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
7105 /* On 64-bit targets, complex floats are returned in
7106 a single GPR, such that "sd" on a suitably-aligned
7107 target would store the value correctly. */
7108 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7109 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7110 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7111 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7112 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
7113 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
7114 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
7115 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7116 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7117 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
7118 reg_names
[GP_RETURN
],
7119 reg_names
[GP_RETURN
],
7120 reg_names
[GP_RETURN
+ 1]);
7125 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7129 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
7134 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7135 || GET_MODE (retval
) != V2SFmode
);
7136 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7142 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
7143 fprintf (asm_out_file
, "\t.cfi_endproc\n");
7147 /* Jump to the previously-loaded address. */
7148 output_asm_insn ("jr\t%^", NULL
);
7151 #ifdef ASM_DECLARE_FUNCTION_SIZE
7152 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
7155 mips_end_function_definition (stubname
);
7157 /* Record this stub. */
7158 l
= XNEW (struct mips16_stub
);
7159 l
->name
= xstrdup (fnname
);
7160 l
->fp_ret_p
= fp_ret_p
;
7161 l
->next
= mips16_stubs
;
7165 /* If we expect a floating-point return value, but we've built a
7166 stub which does not expect one, then we're in trouble. We can't
7167 use the existing stub, because it won't handle the floating-point
7168 value. We can't build a new stub, because the linker won't know
7169 which stub to use for the various calls in this object file.
7170 Fortunately, this case is illegal, since it means that a function
7171 was declared in two different ways in a single compilation. */
7172 if (fp_ret_p
&& !l
->fp_ret_p
)
7173 error ("cannot handle inconsistent calls to %qs", fnname
);
7175 if (retval
== NULL_RTX
)
7176 pattern
= gen_call_internal_direct (fn
, args_size
);
7178 pattern
= gen_call_value_internal_direct (retval
, fn
, args_size
);
7179 insn
= mips_emit_call_insn (pattern
, fn
, fn
, false);
7181 /* If we are calling a stub which handles a floating-point return
7182 value, we need to arrange to save $18 in the prologue. We do this
7183 by marking the function call as using the register. The prologue
7184 will later see that it is used, and emit code to save it. */
7186 CALL_INSN_FUNCTION_USAGE (insn
) =
7187 gen_rtx_EXPR_LIST (VOIDmode
,
7188 gen_rtx_CLOBBER (VOIDmode
,
7189 gen_rtx_REG (word_mode
, 18)),
7190 CALL_INSN_FUNCTION_USAGE (insn
));
7195 /* Expand a call of type TYPE. RESULT is where the result will go (null
7196 for "call"s and "sibcall"s), ADDR is the address of the function,
7197 ARGS_SIZE is the size of the arguments and AUX is the value passed
7198 to us by mips_function_arg. LAZY_P is true if this call already
7199 involves a lazily-bound function address (such as when calling
7200 functions through a MIPS16 hard-float stub).
7202 Return the call itself. */
7205 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7206 rtx args_size
, rtx aux
, bool lazy_p
)
7208 rtx orig_addr
, pattern
;
7212 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7213 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7216 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7221 if (!call_insn_operand (addr
, VOIDmode
))
7223 if (type
== MIPS_CALL_EPILOGUE
)
7224 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7226 addr
= gen_reg_rtx (Pmode
);
7227 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7232 rtx (*fn
) (rtx
, rtx
);
7234 if (type
== MIPS_CALL_SIBCALL
)
7235 fn
= gen_sibcall_internal
;
7237 fn
= gen_call_internal
;
7239 pattern
= fn (addr
, args_size
);
7241 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7243 /* Handle return values created by mips_return_fpr_pair. */
7244 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7247 if (type
== MIPS_CALL_SIBCALL
)
7248 fn
= gen_sibcall_value_multiple_internal
;
7250 fn
= gen_call_value_multiple_internal
;
7252 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7253 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7254 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7258 rtx (*fn
) (rtx
, rtx
, rtx
);
7260 if (type
== MIPS_CALL_SIBCALL
)
7261 fn
= gen_sibcall_value_internal
;
7263 fn
= gen_call_value_internal
;
7265 /* Handle return values created by mips_return_fpr_single. */
7266 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7267 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7268 pattern
= fn (result
, addr
, args_size
);
7271 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7274 /* Split call instruction INSN into a $gp-clobbering call and
7275 (where necessary) an instruction to restore $gp from its save slot.
7276 CALL_PATTERN is the pattern of the new call. */
7279 mips_split_call (rtx insn
, rtx call_pattern
)
7281 emit_call_insn (call_pattern
);
7282 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7283 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
,
7284 POST_CALL_TMP_REG
));
7287 /* Return true if a call to DECL may need to use JALX. */
7290 mips_call_may_need_jalx_p (tree decl
)
7292 /* If the current translation unit would use a different mode for DECL,
7293 assume that the call needs JALX. */
7294 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7297 /* mips_get_compress_mode is always accurate for locally-binding
7298 functions in the current translation unit. */
7299 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7302 /* When -minterlink-compressed is in effect, assume that functions
7303 could use a different encoding mode unless an attribute explicitly
7304 tells us otherwise. */
7305 if (TARGET_INTERLINK_COMPRESSED
)
7307 if (!TARGET_COMPRESSION
7308 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7310 if (TARGET_COMPRESSION
7311 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7318 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7321 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7323 if (!TARGET_SIBCALLS
)
7326 /* Interrupt handlers need special epilogue code and therefore can't
7328 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7331 /* Direct Js are only possible to functions that use the same ISA encoding.
7332 There is no JX counterpoart of JALX. */
7334 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7335 && mips_call_may_need_jalx_p (decl
))
7338 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7339 require $gp to be valid on entry, so sibcalls can only use stubs
7340 if $gp is call-clobbered. */
7342 && TARGET_CALL_SAVED_GP
7343 && !TARGET_ABICALLS_PIC0
7344 && !targetm
.binds_local_p (decl
))
7351 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7354 mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
7356 enum by_pieces_operation op
,
7359 if (op
== STORE_BY_PIECES
)
7360 return mips_store_by_pieces_p (size
, align
);
7361 if (op
== MOVE_BY_PIECES
&& HAVE_movmemsi
)
7363 /* movmemsi is meant to generate code that is at least as good as
7364 move_by_pieces. However, movmemsi effectively uses a by-pieces
7365 implementation both for moves smaller than a word and for
7366 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7367 bytes. We should allow the tree-level optimisers to do such
7368 moves by pieces, as it often exposes other optimization
7369 opportunities. We might as well continue to use movmemsi at
7370 the rtl level though, as it produces better code when
7371 scheduling is disabled (such as at -O). */
7372 if (currently_expanding_to_rtl
)
7374 if (align
< BITS_PER_WORD
)
7375 return size
< UNITS_PER_WORD
;
7376 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7379 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
7382 /* Implement a handler for STORE_BY_PIECES operations
7383 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7386 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7388 /* Storing by pieces involves moving constants into registers
7389 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7390 We need to decide whether it is cheaper to load the address of
7391 constant data into a register and use a block move instead. */
7393 /* If the data is only byte aligned, then:
7395 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7396 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7399 (a2) A block move of 4 bytes from aligned source data can use an
7400 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7401 4 SBs that we would generate when storing by pieces. */
7402 if (align
<= BITS_PER_UNIT
)
7405 /* If the data is 2-byte aligned, then:
7407 (b1) A block move of less than 4 bytes would use a combination of LBs,
7408 LHs, SBs and SHs. We get better code by using single-instruction
7409 LIs, SBs and SHs instead.
7411 (b2) A block move of 4 bytes from aligned source data would again use
7412 an LW/SWL/SWR sequence. In most cases, loading the address of
7413 the source data would require at least one extra instruction.
7414 It is often more efficient to use 2 single-instruction LIs and
7417 (b3) A block move of up to 3 additional bytes would be like (b1).
7419 (b4) A block move of 8 bytes from aligned source data can use two
7420 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7421 sequences are better than the 4 LIs and 4 SHs that we'd generate
7422 when storing by pieces.
7424 The reasoning for higher alignments is similar:
7426 (c1) A block move of less than 4 bytes would be the same as (b1).
7428 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7429 loading the address of the source data would typically require
7430 at least one extra instruction. It is generally better to use
7433 (c3) A block move of up to 3 additional bytes would be like (b1).
7435 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7436 LD/SD sequence, and in these cases we've traditionally preferred
7437 the memory copy over the more bulky constant moves. */
7441 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7442 Assume that the areas do not overlap. */
7445 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7447 HOST_WIDE_INT offset
, delta
;
7448 unsigned HOST_WIDE_INT bits
;
7453 /* Work out how many bits to move at a time. If both operands have
7454 half-word alignment, it is usually better to move in half words.
7455 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7456 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7457 Otherwise move word-sized chunks. */
7458 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7459 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7460 bits
= BITS_PER_WORD
/ 2;
7462 bits
= BITS_PER_WORD
;
7464 mode
= mode_for_size (bits
, MODE_INT
, 0);
7465 delta
= bits
/ BITS_PER_UNIT
;
7467 /* Allocate a buffer for the temporary registers. */
7468 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7470 /* Load as many BITS-sized chunks as possible. Use a normal load if
7471 the source has enough alignment, otherwise use left/right pairs. */
7472 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7474 regs
[i
] = gen_reg_rtx (mode
);
7475 if (MEM_ALIGN (src
) >= bits
)
7476 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7479 rtx part
= adjust_address (src
, BLKmode
, offset
);
7480 set_mem_size (part
, delta
);
7481 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7486 /* Copy the chunks to the destination. */
7487 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7488 if (MEM_ALIGN (dest
) >= bits
)
7489 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7492 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7493 set_mem_size (part
, delta
);
7494 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7498 /* Mop up any left-over bytes. */
7499 if (offset
< length
)
7501 src
= adjust_address (src
, BLKmode
, offset
);
7502 dest
= adjust_address (dest
, BLKmode
, offset
);
7503 move_by_pieces (dest
, src
, length
- offset
,
7504 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7508 /* Helper function for doing a loop-based block operation on memory
7509 reference MEM. Each iteration of the loop will operate on LENGTH
7512 Create a new base register for use within the loop and point it to
7513 the start of MEM. Create a new memory reference that uses this
7514 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7517 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7518 rtx
*loop_reg
, rtx
*loop_mem
)
7520 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7522 /* Although the new mem does not refer to a known location,
7523 it does keep up to LENGTH bytes of alignment. */
7524 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7525 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7528 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7529 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7530 the memory regions do not overlap. */
7533 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7534 HOST_WIDE_INT bytes_per_iter
)
7536 rtx_code_label
*label
;
7537 rtx src_reg
, dest_reg
, final_src
, test
;
7538 HOST_WIDE_INT leftover
;
7540 leftover
= length
% bytes_per_iter
;
7543 /* Create registers and memory references for use within the loop. */
7544 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7545 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7547 /* Calculate the value that SRC_REG should have after the last iteration
7549 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7552 /* Emit the start of the loop. */
7553 label
= gen_label_rtx ();
7556 /* Emit the loop body. */
7557 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7559 /* Move on to the next block. */
7560 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7561 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7563 /* Emit the loop condition. */
7564 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7565 if (Pmode
== DImode
)
7566 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7568 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7570 /* Mop up any left-over bytes. */
7572 mips_block_move_straight (dest
, src
, leftover
);
7575 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7576 memory reference SRC to memory reference DEST. */
7579 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7581 /* Disable entirely for R6 initially. */
7582 if (!ISA_HAS_LWL_LWR
)
7585 if (CONST_INT_P (length
))
7587 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7589 mips_block_move_straight (dest
, src
, INTVAL (length
));
7594 mips_block_move_loop (dest
, src
, INTVAL (length
),
7595 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7602 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7605 mips_expand_synci_loop (rtx begin
, rtx end
)
7607 rtx inc
, cmp_result
, mask
, length
;
7608 rtx_code_label
*label
, *end_label
;
7610 /* Create end_label. */
7611 end_label
= gen_label_rtx ();
7613 /* Check if begin equals end. */
7614 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7615 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7617 /* Load INC with the cache line size (rdhwr INC,$1). */
7618 inc
= gen_reg_rtx (Pmode
);
7619 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7621 /* Check if inc is 0. */
7622 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7623 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7625 /* Calculate mask. */
7626 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7628 /* Mask out begin by mask. */
7629 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7631 /* Calculate length. */
7632 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7634 /* Loop back to here. */
7635 label
= gen_label_rtx ();
7638 emit_insn (gen_synci (begin
));
7640 /* Update length. */
7641 mips_emit_binary (MINUS
, length
, length
, inc
);
7644 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7646 /* Check if length is greater than 0. */
7647 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7648 emit_jump_insn (gen_condjump (cmp_result
, label
));
7650 emit_label (end_label
);
7653 /* Expand a QI or HI mode atomic memory operation.
7655 GENERATOR contains a pointer to the gen_* function that generates
7656 the SI mode underlying atomic operation using masks that we
7659 RESULT is the return register for the operation. Its value is NULL
7662 MEM is the location of the atomic access.
7664 OLDVAL is the first operand for the operation.
7666 NEWVAL is the optional second operand for the operation. Its value
7667 is NULL if unused. */
7670 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7671 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7673 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7674 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7678 mode
= GET_MODE (mem
);
7680 /* Compute the address of the containing SImode value. */
7681 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7682 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7683 force_reg (Pmode
, GEN_INT (-4)));
7685 /* Create a memory reference for it. */
7686 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7687 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7688 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7690 /* Work out the byte offset of the QImode or HImode value,
7691 counting from the least significant byte. */
7692 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7693 if (TARGET_BIG_ENDIAN
)
7694 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7696 /* Multiply by eight to convert the shift value from bytes to bits. */
7697 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7699 /* Make the final shift an SImode value, so that it can be used in
7700 SImode operations. */
7701 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7703 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7704 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7705 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7706 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7708 /* Compute the equivalent exclusive mask. */
7709 inverted_mask
= gen_reg_rtx (SImode
);
7710 emit_insn (gen_rtx_SET (inverted_mask
, gen_rtx_NOT (SImode
, mask
)));
7712 /* Shift the old value into place. */
7713 if (oldval
!= const0_rtx
)
7715 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7716 oldval
= force_reg (SImode
, oldval
);
7717 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7720 /* Do the same for the new value. */
7721 if (newval
&& newval
!= const0_rtx
)
7723 newval
= convert_modes (SImode
, mode
, newval
, true);
7724 newval
= force_reg (SImode
, newval
);
7725 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7728 /* Do the SImode atomic access. */
7730 res
= gen_reg_rtx (SImode
);
7732 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7734 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7736 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7742 /* Shift and convert the result. */
7743 mips_emit_binary (AND
, res
, res
, mask
);
7744 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7745 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7749 /* Return true if it is possible to use left/right accesses for a
7750 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7751 When returning true, update *LEFT and *RIGHT as follows:
7753 *LEFT is a QImode reference to the first byte if big endian or
7754 the last byte if little endian. This address can be used in the
7755 left-side instructions (LWL, SWL, LDL, SDL).
7757 *RIGHT is a QImode reference to the opposite end of the field and
7758 can be used in the patterning right-side instruction. */
7761 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7762 rtx
*left
, rtx
*right
)
7766 /* Check that the size is valid. */
7767 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7770 /* We can only access byte-aligned values. Since we are always passed
7771 a reference to the first byte of the field, it is not necessary to
7772 do anything with BITPOS after this check. */
7773 if (bitpos
% BITS_PER_UNIT
!= 0)
7776 /* Reject aligned bitfields: we want to use a normal load or store
7777 instead of a left/right pair. */
7778 if (MEM_ALIGN (op
) >= width
)
7781 /* Get references to both ends of the field. */
7782 first
= adjust_address (op
, QImode
, 0);
7783 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7785 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7786 correspond to the MSB and RIGHT to the LSB. */
7787 if (TARGET_BIG_ENDIAN
)
7788 *left
= first
, *right
= last
;
7790 *left
= last
, *right
= first
;
7795 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7796 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7797 the operation is the equivalent of:
7799 (set DEST (*_extract SRC WIDTH BITPOS))
7801 Return true on success. */
7804 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7805 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7807 rtx left
, right
, temp
;
7808 rtx dest1
= NULL_RTX
;
7810 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7811 be a DImode, create a new temp and emit a zero extend at the end. */
7812 if (GET_MODE (dest
) == DImode
7814 && GET_MODE_BITSIZE (SImode
) == width
)
7817 dest
= gen_reg_rtx (SImode
);
7820 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7823 temp
= gen_reg_rtx (GET_MODE (dest
));
7824 if (GET_MODE (dest
) == DImode
)
7826 emit_insn (gen_mov_ldl (temp
, src
, left
));
7827 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7831 emit_insn (gen_mov_lwl (temp
, src
, left
));
7832 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7835 /* If we were loading 32bits and the original register was DI then
7836 sign/zero extend into the orignal dest. */
7840 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7842 emit_insn (gen_extendsidi2 (dest1
, dest
));
7847 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7848 BITPOS and SRC are the operands passed to the expander; the operation
7849 is the equivalent of:
7851 (set (zero_extract DEST WIDTH BITPOS) SRC)
7853 Return true on success. */
7856 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7857 HOST_WIDE_INT bitpos
)
7862 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7865 mode
= mode_for_size (width
, MODE_INT
, 0);
7866 src
= gen_lowpart (mode
, src
);
7869 emit_insn (gen_mov_sdl (dest
, src
, left
));
7870 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7874 emit_insn (gen_mov_swl (dest
, src
, left
));
7875 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7880 /* Return true if X is a MEM with the same size as MODE. */
7883 mips_mem_fits_mode_p (machine_mode mode
, rtx x
)
7886 && MEM_SIZE_KNOWN_P (x
)
7887 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7890 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7891 source of an "ext" instruction or the destination of an "ins"
7892 instruction. OP must be a register operand and the following
7893 conditions must hold:
7895 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7896 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7897 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7899 Also reject lengths equal to a word as they are better handled
7900 by the move patterns. */
7903 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7905 if (!ISA_HAS_EXT_INS
7906 || !register_operand (op
, VOIDmode
)
7907 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7910 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7913 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7919 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7920 operation if MAXLEN is the maxium length of consecutive bits that
7921 can make up MASK. MODE is the mode of the operation. See
7922 mask_low_and_shift_len for the actual definition. */
7925 mask_low_and_shift_p (machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7927 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7930 /* Return true iff OP1 and OP2 are valid operands together for the
7931 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7932 see the table in the comment before the pattern. */
7935 and_operands_ok (machine_mode mode
, rtx op1
, rtx op2
)
7937 return (memory_operand (op1
, mode
)
7938 ? and_load_operand (op2
, mode
)
7939 : and_reg_operand (op2
, mode
));
7942 /* The canonical form of a mask-low-and-shift-left operation is
7943 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7944 cleared. Thus we need to shift MASK to the right before checking if it
7945 is a valid mask value. MODE is the mode of the operation. If true
7946 return the length of the mask, otherwise return -1. */
7949 mask_low_and_shift_len (machine_mode mode
, rtx mask
, rtx shift
)
7951 HOST_WIDE_INT shval
;
7953 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7954 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7957 /* Return true if -msplit-addresses is selected and should be honored.
7959 -msplit-addresses is a half-way house between explicit relocations
7960 and the traditional assembler macros. It can split absolute 32-bit
7961 symbolic constants into a high/lo_sum pair but uses macros for other
7964 Like explicit relocation support for REL targets, it relies
7965 on GNU extensions in the assembler and the linker.
7967 Although this code should work for -O0, it has traditionally
7968 been treated as an optimization. */
7971 mips_split_addresses_p (void)
7973 return (TARGET_SPLIT_ADDRESSES
7977 && !ABI_HAS_64BIT_SYMBOLS
);
7980 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7983 mips_init_relocs (void)
7985 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7986 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7987 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7988 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7989 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7991 if (TARGET_MIPS16_PCREL_LOADS
)
7992 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7995 if (ABI_HAS_64BIT_SYMBOLS
)
7997 if (TARGET_EXPLICIT_RELOCS
)
7999 mips_split_p
[SYMBOL_64_HIGH
] = true;
8000 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
8001 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
8003 mips_split_p
[SYMBOL_64_MID
] = true;
8004 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
8005 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
8007 mips_split_p
[SYMBOL_64_LOW
] = true;
8008 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
8009 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
8011 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8012 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8017 if (TARGET_EXPLICIT_RELOCS
8018 || mips_split_addresses_p ()
8021 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8022 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
8023 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8030 /* The high part is provided by a pseudo copy of $gp. */
8031 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
8032 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
8034 else if (TARGET_EXPLICIT_RELOCS
)
8035 /* Small data constants are kept whole until after reload,
8036 then lowered by mips_rewrite_small_data. */
8037 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
8039 if (TARGET_EXPLICIT_RELOCS
)
8041 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8044 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
8045 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
8049 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
8050 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
8053 /* Expose the use of $28 as soon as possible. */
8054 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8058 /* The HIGH and LO_SUM are matched by special .md patterns. */
8059 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8061 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
8062 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
8063 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
8065 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
8066 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
8067 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
8072 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
8074 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
8075 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
8077 /* Expose the use of $28 as soon as possible. */
8078 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8084 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
8085 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
8086 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
8089 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
8090 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
8092 if (TARGET_MIPS16_PCREL_LOADS
)
8094 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
8095 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
8099 mips_split_p
[SYMBOL_DTPREL
] = true;
8100 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
8101 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
8103 mips_split_p
[SYMBOL_TPREL
] = true;
8104 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
8105 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
8108 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
8109 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
8112 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8113 in context CONTEXT. RELOCS is the array of relocations to use. */
8116 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
8117 const char **relocs
)
8119 enum mips_symbol_type symbol_type
;
8122 symbol_type
= mips_classify_symbolic_expression (op
, context
);
8123 gcc_assert (relocs
[symbol_type
]);
8125 fputs (relocs
[symbol_type
], file
);
8126 output_addr_const (file
, mips_strip_unspec_address (op
));
8127 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
8132 /* Start a new block with the given asm switch enabled. If we need
8133 to print a directive, emit PREFIX before it and SUFFIX after it. */
8136 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8137 const char *prefix
, const char *suffix
)
8139 if (asm_switch
->nesting_level
== 0)
8140 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
8141 asm_switch
->nesting_level
++;
8144 /* Likewise, but end a block. */
8147 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8148 const char *prefix
, const char *suffix
)
8150 gcc_assert (asm_switch
->nesting_level
);
8151 asm_switch
->nesting_level
--;
8152 if (asm_switch
->nesting_level
== 0)
8153 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
8156 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8157 that either print a complete line or print nothing. */
8160 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
8162 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
8166 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
8168 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
8171 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8172 The punctuation characters are:
8174 '(' Start a nested ".set noreorder" block.
8175 ')' End a nested ".set noreorder" block.
8176 '[' Start a nested ".set noat" block.
8177 ']' End a nested ".set noat" block.
8178 '<' Start a nested ".set nomacro" block.
8179 '>' End a nested ".set nomacro" block.
8180 '*' Behave like %(%< if generating a delayed-branch sequence.
8181 '#' Print a nop if in a ".set noreorder" block.
8182 '/' Like '#', but do nothing within a delayed-branch sequence.
8183 '?' Print "l" if mips_branch_likely is true
8184 '~' Print a nop if mips_branch_likely is true
8185 '.' Print the name of the register with a hard-wired zero (zero or $0).
8186 '@' Print the name of the assembler temporary register (at or $1).
8187 '^' Print the name of the pic call-through register (t9 or $25).
8188 '+' Print the name of the gp register (usually gp or $28).
8189 '$' Print the name of the stack pointer register (sp or $29).
8190 ':' Print "c" to use the compact version if the delay slot is a nop.
8191 '!' Print "s" to use the short version if the delay slot contains a
8194 See also mips_init_print_operand_pucnt. */
8197 mips_print_operand_punctuation (FILE *file
, int ch
)
8202 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8206 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8210 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8214 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8218 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8222 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8226 if (final_sequence
!= 0)
8228 mips_print_operand_punctuation (file
, '(');
8229 mips_print_operand_punctuation (file
, '<');
8234 if (mips_noreorder
.nesting_level
> 0)
8235 fputs ("\n\tnop", file
);
8239 /* Print an extra newline so that the delayed insn is separated
8240 from the following ones. This looks neater and is consistent
8241 with non-nop delayed sequences. */
8242 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8243 fputs ("\n\tnop\n", file
);
8247 if (mips_branch_likely
)
8252 if (mips_branch_likely
)
8253 fputs ("\n\tnop", file
);
8257 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8261 fputs (reg_names
[AT_REGNUM
], file
);
8265 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8269 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8273 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8277 /* When final_sequence is 0, the delay slot will be a nop. We can
8278 use the compact version for microMIPS. */
8279 if (final_sequence
== 0)
8284 /* If the delay slot instruction is short, then use the
8286 if (final_sequence
== 0
8287 || get_attr_length (final_sequence
->insn (1)) == 2)
8297 /* Initialize mips_print_operand_punct. */
8300 mips_init_print_operand_punct (void)
8304 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8305 mips_print_operand_punct
[(unsigned char) *p
] = true;
8308 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8309 associated with condition CODE. Print the condition part of the
8313 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8327 /* Conveniently, the MIPS names for these conditions are the same
8328 as their RTL equivalents. */
8329 fputs (GET_RTX_NAME (code
), file
);
8333 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8338 /* Likewise floating-point branches. */
8341 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8347 fputs ("c1eqz", file
);
8349 fputs ("c1f", file
);
8354 fputs ("c1nez", file
);
8356 fputs ("c1t", file
);
8360 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8365 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8368 mips_print_operand_punct_valid_p (unsigned char code
)
8370 return mips_print_operand_punct
[code
];
8373 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8375 'X' Print CONST_INT OP in hexadecimal format.
8376 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8377 'd' Print CONST_INT OP in decimal.
8378 'm' Print one less than CONST_INT OP in decimal.
8379 'h' Print the high-part relocation associated with OP, after stripping
8381 'R' Print the low-part relocation associated with OP.
8382 'C' Print the integer branch condition for comparison OP.
8383 'N' Print the inverse of the integer branch condition for comparison OP.
8384 'F' Print the FPU branch condition for comparison OP.
8385 'W' Print the inverse of the FPU branch condition for comparison OP.
8386 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8387 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8388 't' Like 'T', but with the EQ/NE cases reversed
8389 'Y' Print mips_fp_conditions[INTVAL (OP)]
8390 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8391 'q' Print a DSP accumulator register.
8392 'D' Print the second part of a double-word register or memory operand.
8393 'L' Print the low-order register in a double-word register operand.
8394 'M' Print high-order register in a double-word register operand.
8395 'z' Print $0 if OP is zero, otherwise print OP normally.
8396 'b' Print the address of a memory operand, without offset. */
8399 mips_print_operand (FILE *file
, rtx op
, int letter
)
8403 if (mips_print_operand_punct_valid_p (letter
))
8405 mips_print_operand_punctuation (file
, letter
);
8410 code
= GET_CODE (op
);
8415 if (CONST_INT_P (op
))
8416 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8418 output_operand_lossage ("invalid use of '%%%c'", letter
);
8422 if (CONST_INT_P (op
))
8423 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8425 output_operand_lossage ("invalid use of '%%%c'", letter
);
8429 if (CONST_INT_P (op
))
8430 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8432 output_operand_lossage ("invalid use of '%%%c'", letter
);
8436 if (CONST_INT_P (op
))
8437 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8439 output_operand_lossage ("invalid use of '%%%c'", letter
);
8445 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8449 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8453 mips_print_int_branch_condition (file
, code
, letter
);
8457 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8461 mips_print_float_branch_condition (file
, code
, letter
);
8465 mips_print_float_branch_condition (file
, reverse_condition (code
),
8472 int truth
= (code
== NE
) == (letter
== 'T');
8473 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
8478 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8479 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8481 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8486 if (ISA_HAS_8CC
|| ISA_HAS_CCF
)
8488 mips_print_operand (file
, op
, 0);
8494 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8495 fprintf (file
, "$ac0");
8496 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8497 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8499 output_operand_lossage ("invalid use of '%%%c'", letter
);
8507 unsigned int regno
= REGNO (op
);
8508 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8509 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8512 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8513 output_operand_lossage ("invalid use of '%%%c'", letter
);
8514 /* We need to print $0 .. $31 for COP0 registers. */
8515 if (COP0_REG_P (regno
))
8516 fprintf (file
, "$%s", ®_names
[regno
][4]);
8518 fprintf (file
, "%s", reg_names
[regno
]);
8524 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8525 else if (letter
== 'b')
8527 gcc_assert (REG_P (XEXP (op
, 0)));
8528 mips_print_operand (file
, XEXP (op
, 0), 0);
8530 else if (letter
&& letter
!= 'z')
8531 output_operand_lossage ("invalid use of '%%%c'", letter
);
8533 output_address (XEXP (op
, 0));
8537 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8538 fputs (reg_names
[GP_REG_FIRST
], file
);
8539 else if (letter
&& letter
!= 'z')
8540 output_operand_lossage ("invalid use of '%%%c'", letter
);
8541 else if (CONST_GP_P (op
))
8542 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8544 output_addr_const (file
, mips_strip_unspec_address (op
));
8550 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8553 mips_print_operand_address (FILE *file
, rtx x
)
8555 struct mips_address_info addr
;
8557 if (mips_classify_address (&addr
, x
, word_mode
, true))
8561 mips_print_operand (file
, addr
.offset
, 0);
8562 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8565 case ADDRESS_LO_SUM
:
8566 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8568 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8571 case ADDRESS_CONST_INT
:
8572 output_addr_const (file
, x
);
8573 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8576 case ADDRESS_SYMBOLIC
:
8577 output_addr_const (file
, mips_strip_unspec_address (x
));
8583 /* Implement TARGET_ENCODE_SECTION_INFO. */
8586 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8588 default_encode_section_info (decl
, rtl
, first
);
8590 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8592 rtx symbol
= XEXP (rtl
, 0);
8593 tree type
= TREE_TYPE (decl
);
8595 /* Encode whether the symbol is short or long. */
8596 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8597 || mips_far_type_p (type
))
8598 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8602 /* Implement TARGET_SELECT_RTX_SECTION. */
8605 mips_select_rtx_section (machine_mode mode
, rtx x
,
8606 unsigned HOST_WIDE_INT align
)
8608 /* ??? Consider using mergeable small data sections. */
8609 if (mips_rtx_constant_in_small_data_p (mode
))
8610 return get_named_section (NULL
, ".sdata", 0);
8612 return default_elf_select_rtx_section (mode
, x
, align
);
8615 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8617 The complication here is that, with the combination TARGET_ABICALLS
8618 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8619 absolute addresses, and should therefore not be included in the
8620 read-only part of a DSO. Handle such cases by selecting a normal
8621 data section instead of a read-only one. The logic apes that in
8622 default_function_rodata_section. */
8625 mips_function_rodata_section (tree decl
)
8627 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8628 return default_function_rodata_section (decl
);
8630 if (decl
&& DECL_SECTION_NAME (decl
))
8632 const char *name
= DECL_SECTION_NAME (decl
);
8633 if (DECL_COMDAT_GROUP (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8635 char *rname
= ASTRDUP (name
);
8637 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8639 else if (flag_function_sections
8640 && flag_data_sections
8641 && strncmp (name
, ".text.", 6) == 0)
8643 char *rname
= ASTRDUP (name
);
8644 memcpy (rname
+ 1, "data", 4);
8645 return get_section (rname
, SECTION_WRITE
, decl
);
8648 return data_section
;
8651 /* Implement TARGET_IN_SMALL_DATA_P. */
8654 mips_in_small_data_p (const_tree decl
)
8656 unsigned HOST_WIDE_INT size
;
8658 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8661 /* We don't yet generate small-data references for -mabicalls
8662 or VxWorks RTP code. See the related -G handling in
8663 mips_option_override. */
8664 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8667 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8671 /* Reject anything that isn't in a known small-data section. */
8672 name
= DECL_SECTION_NAME (decl
);
8673 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8676 /* If a symbol is defined externally, the assembler will use the
8677 usual -G rules when deciding how to implement macros. */
8678 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8681 else if (TARGET_EMBEDDED_DATA
)
8683 /* Don't put constants into the small data section: we want them
8684 to be in ROM rather than RAM. */
8685 if (TREE_CODE (decl
) != VAR_DECL
)
8688 if (TREE_READONLY (decl
)
8689 && !TREE_SIDE_EFFECTS (decl
)
8690 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8694 /* Enforce -mlocal-sdata. */
8695 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8698 /* Enforce -mextern-sdata. */
8699 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8701 if (DECL_EXTERNAL (decl
))
8703 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8707 /* We have traditionally not treated zero-sized objects as small data,
8708 so this is now effectively part of the ABI. */
8709 size
= int_size_in_bytes (TREE_TYPE (decl
));
8710 return size
> 0 && size
<= mips_small_data_threshold
;
8713 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8714 anchors for small data: the GP register acts as an anchor in that
8715 case. We also don't want to use them for PC-relative accesses,
8716 where the PC acts as an anchor. */
8719 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8721 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8723 case SYMBOL_PC_RELATIVE
:
8724 case SYMBOL_GP_RELATIVE
:
8728 return default_use_anchors_for_symbol_p (symbol
);
8732 /* The MIPS debug format wants all automatic variables and arguments
8733 to be in terms of the virtual frame pointer (stack pointer before
8734 any adjustment in the function), while the MIPS 3.0 linker wants
8735 the frame pointer to be the stack pointer after the initial
8736 adjustment. So, we do the adjustment here. The arg pointer (which
8737 is eliminated) points to the virtual frame pointer, while the frame
8738 pointer (which may be eliminated) points to the stack pointer after
8739 the initial adjustments. */
8742 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8744 rtx offset2
= const0_rtx
;
8745 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8748 offset
= INTVAL (offset2
);
8750 if (reg
== stack_pointer_rtx
8751 || reg
== frame_pointer_rtx
8752 || reg
== hard_frame_pointer_rtx
)
8754 offset
-= cfun
->machine
->frame
.total_size
;
8755 if (reg
== hard_frame_pointer_rtx
)
8756 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8762 /* Implement ASM_OUTPUT_EXTERNAL. */
8765 mips_output_external (FILE *file
, tree decl
, const char *name
)
8767 default_elf_asm_output_external (file
, decl
, name
);
8769 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8770 set in order to avoid putting out names that are never really
8772 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8774 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8776 /* When using assembler macros, emit .extern directives for
8777 all small-data externs so that the assembler knows how
8780 In most cases it would be safe (though pointless) to emit
8781 .externs for other symbols too. One exception is when an
8782 object is within the -G limit but declared by the user to
8783 be in a section other than .sbss or .sdata. */
8784 fputs ("\t.extern\t", file
);
8785 assemble_name (file
, name
);
8786 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8787 int_size_in_bytes (TREE_TYPE (decl
)));
8792 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8795 mips_output_filename (FILE *stream
, const char *name
)
8797 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8799 if (write_symbols
== DWARF2_DEBUG
)
8801 else if (mips_output_filename_first_time
)
8803 mips_output_filename_first_time
= 0;
8804 num_source_filenames
+= 1;
8805 current_function_file
= name
;
8806 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8807 output_quoted_string (stream
, name
);
8808 putc ('\n', stream
);
8810 /* If we are emitting stabs, let dbxout.c handle this (except for
8811 the mips_output_filename_first_time case). */
8812 else if (write_symbols
== DBX_DEBUG
)
8814 else if (name
!= current_function_file
8815 && strcmp (name
, current_function_file
) != 0)
8817 num_source_filenames
+= 1;
8818 current_function_file
= name
;
8819 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8820 output_quoted_string (stream
, name
);
8821 putc ('\n', stream
);
8825 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8827 static void ATTRIBUTE_UNUSED
8828 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8833 fputs ("\t.dtprelword\t", file
);
8837 fputs ("\t.dtpreldword\t", file
);
8843 output_addr_const (file
, x
);
8844 fputs ("+0x8000", file
);
8847 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8850 mips_dwarf_register_span (rtx reg
)
8855 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
8856 ensures that double-precision registers are treated as if they were
8857 64-bit physical registers. The code will run correctly with 32-bit or
8858 64-bit registers which means that dwarf information cannot be precise
8859 for all scenarios. We choose to state that the 64-bit values are stored
8860 in a single 64-bit 'piece'. This slightly unusual construct can then be
8861 interpreted as either a pair of registers if the registers are 32-bit or
8862 a single 64-bit register depending on hardware. */
8863 mode
= GET_MODE (reg
);
8864 if (FP_REG_P (REGNO (reg
))
8866 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8868 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, reg
));
8870 /* By default, GCC maps increasing register numbers to increasing
8871 memory locations, but paired FPRs are always little-endian,
8872 regardless of the prevailing endianness. */
8873 else if (FP_REG_P (REGNO (reg
))
8874 && TARGET_BIG_ENDIAN
8875 && MAX_FPRS_PER_FMT
> 1
8876 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8878 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8879 high
= mips_subword (reg
, true);
8880 low
= mips_subword (reg
, false);
8881 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8887 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
8890 mips_dwarf_frame_reg_mode (int regno
)
8892 machine_mode mode
= default_dwarf_frame_reg_mode (regno
);
8894 if (FP_REG_P (regno
) && mips_abi
== ABI_32
&& TARGET_FLOAT64
)
8900 /* DSP ALU can bypass data with no delays for the following pairs. */
8901 enum insn_code dspalu_bypass_table
[][2] =
8903 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8904 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8905 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8906 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8907 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8908 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8909 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8910 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8914 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8917 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8918 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8919 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8921 for (i
= 0; i
< num_bypass
; i
++)
8923 if (out_icode
== dspalu_bypass_table
[i
][0]
8924 && in_icode
== dspalu_bypass_table
[i
][1])
8930 /* Implement ASM_OUTPUT_ASCII. */
8933 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8939 fprintf (stream
, "\t.ascii\t\"");
8940 for (i
= 0; i
< len
; i
++)
8944 c
= (unsigned char) string
[i
];
8947 if (c
== '\\' || c
== '\"')
8949 putc ('\\', stream
);
8957 fprintf (stream
, "\\%03o", c
);
8961 if (cur_pos
> 72 && i
+1 < len
)
8964 fprintf (stream
, "\"\n\t.ascii\t\"");
8967 fprintf (stream
, "\"\n");
8970 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8971 Update *ADDR with the operand that should be printed. */
8974 mips_output_tls_reloc_directive (rtx
*addr
)
8976 enum mips_symbol_type type
;
8978 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8979 *addr
= mips_strip_unspec_address (*addr
);
8983 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8986 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8993 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8994 macros, mark the symbol as written so that mips_asm_output_external
8995 won't emit an .extern for it. STREAM is the output file, NAME is the
8996 name of the symbol, INIT_STRING is the string that should be written
8997 before the symbol and FINAL_STRING is the string that should be
8998 written after it. FINAL_STRING is a printf format that consumes the
8999 remaining arguments. */
9002 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
9003 const char *final_string
, ...)
9007 fputs (init_string
, stream
);
9008 assemble_name (stream
, name
);
9009 va_start (ap
, final_string
);
9010 vfprintf (stream
, final_string
, ap
);
9013 if (!TARGET_EXPLICIT_RELOCS
)
9015 tree name_tree
= get_identifier (name
);
9016 TREE_ASM_WRITTEN (name_tree
) = 1;
9020 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
9021 NAME is the name of the object and ALIGN is the required alignment
9022 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
9023 alignment argument. */
9026 mips_declare_common_object (FILE *stream
, const char *name
,
9027 const char *init_string
,
9028 unsigned HOST_WIDE_INT size
,
9029 unsigned int align
, bool takes_alignment_p
)
9031 if (!takes_alignment_p
)
9033 size
+= (align
/ BITS_PER_UNIT
) - 1;
9034 size
-= size
% (align
/ BITS_PER_UNIT
);
9035 mips_declare_object (stream
, name
, init_string
,
9036 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
9039 mips_declare_object (stream
, name
, init_string
,
9040 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
9041 size
, align
/ BITS_PER_UNIT
);
9044 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
9045 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
9048 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
9049 unsigned HOST_WIDE_INT size
,
9052 /* If the target wants uninitialized const declarations in
9053 .rdata then don't put them in .comm. */
9054 if (TARGET_EMBEDDED_DATA
9055 && TARGET_UNINIT_CONST_IN_RODATA
9056 && TREE_CODE (decl
) == VAR_DECL
9057 && TREE_READONLY (decl
)
9058 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
9060 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
9061 targetm
.asm_out
.globalize_label (stream
, name
);
9063 switch_to_section (readonly_data_section
);
9064 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
9065 mips_declare_object (stream
, name
, "",
9066 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
9070 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
9074 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
9075 extern int size_directive_output
;
9077 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
9078 definitions except that it uses mips_declare_object to emit the label. */
9081 mips_declare_object_name (FILE *stream
, const char *name
,
9082 tree decl ATTRIBUTE_UNUSED
)
9084 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9085 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
9088 size_directive_output
= 0;
9089 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
9093 size_directive_output
= 1;
9094 size
= int_size_in_bytes (TREE_TYPE (decl
));
9095 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9098 mips_declare_object (stream
, name
, "", ":\n");
9101 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
9104 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
9108 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
9109 if (!flag_inhibit_size_directive
9110 && DECL_SIZE (decl
) != 0
9113 && DECL_INITIAL (decl
) == error_mark_node
9114 && !size_directive_output
)
9118 size_directive_output
= 1;
9119 size
= int_size_in_bytes (TREE_TYPE (decl
));
9120 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9125 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9126 with the current ABI. */
9129 mips_mdebug_abi_name (void)
9142 return TARGET_64BIT
? "eabi64" : "eabi32";
9148 /* Implement TARGET_ASM_FILE_START. */
9151 mips_file_start (void)
9153 default_file_start ();
9155 /* Generate a special section to describe the ABI switches used to
9156 produce the resultant binary. */
9158 /* Record the ABI itself. Modern versions of binutils encode
9159 this information in the ELF header flags, but GDB needs the
9160 information in order to correctly debug binaries produced by
9161 older binutils. See the function mips_gdbarch_init in
9163 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
9164 mips_mdebug_abi_name ());
9166 /* There is no ELF header flag to distinguish long32 forms of the
9167 EABI from long64 forms. Emit a special section to help tools
9168 such as GDB. Do the same for o64, which is sometimes used with
9170 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
9171 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
9172 "\t.previous\n", TARGET_LONG64
? 64 : 32);
9174 /* Record the NaN encoding. */
9175 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
9176 fprintf (asm_out_file
, "\t.nan\t%s\n",
9177 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
9179 #ifdef HAVE_AS_DOT_MODULE
9180 /* Record the FP ABI. See below for comments. */
9181 if (TARGET_NO_FLOAT
)
9182 #ifdef HAVE_AS_GNU_ATTRIBUTE
9183 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file
);
9187 else if (!TARGET_HARD_FLOAT_ABI
)
9188 fputs ("\t.module\tsoftfloat\n", asm_out_file
);
9189 else if (!TARGET_DOUBLE_FLOAT
)
9190 fputs ("\t.module\tsinglefloat\n", asm_out_file
);
9191 else if (TARGET_FLOATXX
)
9192 fputs ("\t.module\tfp=xx\n", asm_out_file
);
9193 else if (TARGET_FLOAT64
)
9194 fputs ("\t.module\tfp=64\n", asm_out_file
);
9196 fputs ("\t.module\tfp=32\n", asm_out_file
);
9198 if (TARGET_ODD_SPREG
)
9199 fputs ("\t.module\toddspreg\n", asm_out_file
);
9201 fputs ("\t.module\tnooddspreg\n", asm_out_file
);
9204 #ifdef HAVE_AS_GNU_ATTRIBUTE
9208 /* No floating-point operations, -mno-float. */
9209 if (TARGET_NO_FLOAT
)
9211 /* Soft-float code, -msoft-float. */
9212 else if (!TARGET_HARD_FLOAT_ABI
)
9214 /* Single-float code, -msingle-float. */
9215 else if (!TARGET_DOUBLE_FLOAT
)
9217 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9219 This case used 12 callee-saved double-precision registers
9220 and is deprecated. */
9221 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9222 else if (TARGET_FLOATXX
)
9224 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9225 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
&& TARGET_ODD_SPREG
)
9227 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9228 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9230 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9234 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
9239 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9240 if (TARGET_ABICALLS
)
9242 fprintf (asm_out_file
, "\t.abicalls\n");
9243 if (TARGET_ABICALLS_PIC0
)
9244 fprintf (asm_out_file
, "\t.option\tpic0\n");
9247 if (flag_verbose_asm
)
9248 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9250 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
9253 /* Implement TARGET_ASM_CODE_END. */
9256 mips_code_end (void)
9258 mips_finish_stub (&mips16_rdhwr_stub
);
9259 mips_finish_stub (&mips16_get_fcsr_stub
);
9260 mips_finish_stub (&mips16_set_fcsr_stub
);
9263 /* Make the last instruction frame-related and note that it performs
9264 the operation described by FRAME_PATTERN. */
9267 mips_set_frame_expr (rtx frame_pattern
)
9271 insn
= get_last_insn ();
9272 RTX_FRAME_RELATED_P (insn
) = 1;
9273 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9278 /* Return a frame-related rtx that stores REG at MEM.
9279 REG must be a single register. */
9282 mips_frame_set (rtx mem
, rtx reg
)
9286 set
= gen_rtx_SET (mem
, reg
);
9287 RTX_FRAME_RELATED_P (set
) = 1;
9292 /* Record that the epilogue has restored call-saved register REG. */
9295 mips_add_cfa_restore (rtx reg
)
9297 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
9298 mips_epilogue
.cfa_restores
);
9301 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9302 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9303 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9304 static const unsigned char mips16e_s2_s8_regs
[] = {
9305 30, 23, 22, 21, 20, 19, 18
9307 static const unsigned char mips16e_a0_a3_regs
[] = {
9311 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9312 ordered from the uppermost in memory to the lowest in memory. */
9313 static const unsigned char mips16e_save_restore_regs
[] = {
9314 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9317 /* Return the index of the lowest X in the range [0, SIZE) for which
9318 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9321 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
9326 for (i
= 0; i
< size
; i
++)
9327 if (BITSET_P (mask
, regs
[i
]))
9333 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9334 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9335 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9336 is true for all indexes (X, SIZE). */
9339 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
9340 unsigned int size
, unsigned int *num_regs_ptr
)
9344 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
9345 for (i
++; i
< size
; i
++)
9346 if (!BITSET_P (*mask_ptr
, regs
[i
]))
9349 *mask_ptr
|= 1 << regs
[i
];
9353 /* Return a simplified form of X using the register values in REG_VALUES.
9354 REG_VALUES[R] is the last value assigned to hard register R, or null
9355 if R has not been modified.
9357 This function is rather limited, but is good enough for our purposes. */
9360 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
9362 x
= avoid_constant_pool_reference (x
);
9366 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9367 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9368 x0
, GET_MODE (XEXP (x
, 0)));
9371 if (ARITHMETIC_P (x
))
9373 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9374 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9375 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9379 && reg_values
[REGNO (x
)]
9380 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9381 return reg_values
[REGNO (x
)];
9386 /* Return true if (set DEST SRC) stores an argument register into its
9387 caller-allocated save slot, storing the number of that argument
9388 register in *REGNO_PTR if so. REG_VALUES is as for
9389 mips16e_collect_propagate_value. */
9392 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9393 unsigned int *regno_ptr
)
9395 unsigned int argno
, regno
;
9396 HOST_WIDE_INT offset
, required_offset
;
9399 /* Check that this is a word-mode store. */
9400 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9403 /* Check that the register being saved is an unmodified argument
9405 regno
= REGNO (src
);
9406 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9408 argno
= regno
- GP_ARG_FIRST
;
9410 /* Check whether the address is an appropriate stack-pointer or
9411 frame-pointer access. */
9412 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9413 mips_split_plus (addr
, &base
, &offset
);
9414 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9415 if (base
== hard_frame_pointer_rtx
)
9416 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9417 else if (base
!= stack_pointer_rtx
)
9419 if (offset
!= required_offset
)
9426 /* A subroutine of mips_expand_prologue, called only when generating
9427 MIPS16e SAVE instructions. Search the start of the function for any
9428 instructions that save argument registers into their caller-allocated
9429 save slots. Delete such instructions and return a value N such that
9430 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9431 instructions redundant. */
9434 mips16e_collect_argument_saves (void)
9436 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9437 rtx_insn
*insn
, *next
;
9439 unsigned int nargs
, regno
;
9441 push_topmost_sequence ();
9443 memset (reg_values
, 0, sizeof (reg_values
));
9444 for (insn
= get_insns (); insn
; insn
= next
)
9446 next
= NEXT_INSN (insn
);
9447 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9453 set
= PATTERN (insn
);
9454 if (GET_CODE (set
) != SET
)
9457 dest
= SET_DEST (set
);
9458 src
= SET_SRC (set
);
9459 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9461 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9464 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9467 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9468 reg_values
[REGNO (dest
)]
9469 = mips16e_collect_propagate_value (src
, reg_values
);
9473 pop_topmost_sequence ();
9478 /* Return a move between register REGNO and memory location SP + OFFSET.
9479 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9480 Make the move a load if RESTORE_P, otherwise make it a store. */
9483 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9484 HOST_WIDE_INT offset
, unsigned int regno
)
9488 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9490 reg
= gen_rtx_REG (SImode
, regno
);
9493 mips_add_cfa_restore (reg
);
9494 return gen_rtx_SET (reg
, mem
);
9497 return gen_rtx_SET (mem
, reg
);
9498 return mips_frame_set (mem
, reg
);
9501 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9502 The instruction must:
9504 - Allocate or deallocate SIZE bytes in total; SIZE is known
9507 - Save or restore as many registers in *MASK_PTR as possible.
9508 The instruction saves the first registers at the top of the
9509 allocated area, with the other registers below it.
9511 - Save NARGS argument registers above the allocated area.
9513 (NARGS is always zero if RESTORE_P.)
9515 The SAVE and RESTORE instructions cannot save and restore all general
9516 registers, so there may be some registers left over for the caller to
9517 handle. Destructively modify *MASK_PTR so that it contains the registers
9518 that still need to be saved or restored. The caller can save these
9519 registers in the memory immediately below *OFFSET_PTR, which is a
9520 byte offset from the bottom of the allocated stack area. */
9523 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9524 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9528 HOST_WIDE_INT offset
, top_offset
;
9529 unsigned int i
, regno
;
9532 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9534 /* Calculate the number of elements in the PARALLEL. We need one element
9535 for the stack adjustment, one for each argument register save, and one
9536 for each additional register move. */
9538 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9539 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9542 /* Create the final PARALLEL. */
9543 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9546 /* Add the stack pointer adjustment. */
9547 set
= gen_rtx_SET (stack_pointer_rtx
,
9548 plus_constant (Pmode
, stack_pointer_rtx
,
9549 restore_p
? size
: -size
));
9550 RTX_FRAME_RELATED_P (set
) = 1;
9551 XVECEXP (pattern
, 0, n
++) = set
;
9553 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9554 top_offset
= restore_p
? size
: 0;
9556 /* Save the arguments. */
9557 for (i
= 0; i
< nargs
; i
++)
9559 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9560 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9562 XVECEXP (pattern
, 0, n
++) = set
;
9565 /* Then fill in the other register moves. */
9566 offset
= top_offset
;
9567 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9569 regno
= mips16e_save_restore_regs
[i
];
9570 if (BITSET_P (*mask_ptr
, regno
))
9572 offset
-= UNITS_PER_WORD
;
9573 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9574 XVECEXP (pattern
, 0, n
++) = set
;
9575 *mask_ptr
&= ~(1 << regno
);
9579 /* Tell the caller what offset it should use for the remaining registers. */
9580 *offset_ptr
= size
+ (offset
- top_offset
);
9582 gcc_assert (n
== XVECLEN (pattern
, 0));
9587 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9588 pointer. Return true if PATTERN matches the kind of instruction
9589 generated by mips16e_build_save_restore. If INFO is nonnull,
9590 initialize it when returning true. */
9593 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9594 struct mips16e_save_restore_info
*info
)
9596 unsigned int i
, nargs
, mask
, extra
;
9597 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9598 rtx set
, reg
, mem
, base
;
9601 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9604 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9605 top_offset
= adjust
> 0 ? adjust
: 0;
9607 /* Interpret all other members of the PARALLEL. */
9608 save_offset
= top_offset
- UNITS_PER_WORD
;
9612 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9614 /* Check that we have a SET. */
9615 set
= XVECEXP (pattern
, 0, n
);
9616 if (GET_CODE (set
) != SET
)
9619 /* Check that the SET is a load (if restoring) or a store
9621 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9625 /* Check that the address is the sum of the stack pointer and a
9626 possibly-zero constant offset. */
9627 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9628 if (base
!= stack_pointer_rtx
)
9631 /* Check that SET's other operand is a register. */
9632 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9636 /* Check for argument saves. */
9637 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9638 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9640 else if (offset
== save_offset
)
9642 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9643 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9646 mask
|= 1 << REGNO (reg
);
9647 save_offset
-= UNITS_PER_WORD
;
9653 /* Check that the restrictions on register ranges are met. */
9655 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9656 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9657 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9658 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9662 /* Make sure that the topmost argument register is not saved twice.
9663 The checks above ensure that the same is then true for the other
9664 argument registers. */
9665 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9668 /* Pass back information, if requested. */
9671 info
->nargs
= nargs
;
9673 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9679 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9680 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9681 the null terminator. */
9684 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9685 unsigned int max_reg
)
9687 if (min_reg
!= max_reg
)
9688 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9690 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9694 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9695 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9698 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9700 static char buffer
[300];
9702 struct mips16e_save_restore_info info
;
9703 unsigned int i
, end
;
9706 /* Parse the pattern. */
9707 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9710 /* Add the mnemonic. */
9711 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9714 /* Save the arguments. */
9716 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9717 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9718 else if (info
.nargs
== 1)
9719 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9721 /* Emit the amount of stack space to allocate or deallocate. */
9722 s
+= sprintf (s
, "%d", (int) info
.size
);
9724 /* Save or restore $16. */
9725 if (BITSET_P (info
.mask
, 16))
9726 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9728 /* Save or restore $17. */
9729 if (BITSET_P (info
.mask
, 17))
9730 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9732 /* Save or restore registers in the range $s2...$s8, which
9733 mips16e_s2_s8_regs lists in decreasing order. Note that this
9734 is a software register range; the hardware registers are not
9735 numbered consecutively. */
9736 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9737 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9739 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9740 mips16e_s2_s8_regs
[i
]);
9742 /* Save or restore registers in the range $a0...$a3. */
9743 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9744 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9746 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9747 mips16e_a0_a3_regs
[end
- 1]);
9749 /* Save or restore $31. */
9750 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9751 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9756 /* Return true if the current function returns its value in a floating-point
9757 register in MIPS16 mode. */
9760 mips16_cfun_returns_in_fpr_p (void)
9762 tree return_type
= DECL_RESULT (current_function_decl
);
9763 return (TARGET_MIPS16
9764 && TARGET_HARD_FLOAT_ABI
9765 && !aggregate_value_p (return_type
, current_function_decl
)
9766 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9769 /* Return true if predicate PRED is true for at least one instruction.
9770 Cache the result in *CACHE, and assume that the result is true
9771 if *CACHE is already true. */
9774 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx_insn
*))
9776 rtx_insn
*insn
, *subinsn
;
9780 push_topmost_sequence ();
9781 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9782 FOR_EACH_SUBINSN (subinsn
, insn
)
9783 if (USEFUL_INSN_P (subinsn
) && pred (subinsn
))
9788 pop_topmost_sequence ();
9793 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9794 See mips_cfun_has_inflexible_gp_ref_p for details. */
9797 mips_insn_has_inflexible_gp_ref_p (rtx_insn
*insn
)
9799 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9800 indicate that the target could be a traditional MIPS
9801 lazily-binding stub. */
9802 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9805 /* Return true if the current function refers to the global pointer
9806 in a way that forces $28 to be valid. This means that we can't
9807 change the choice of global pointer, even for NewABI code.
9809 One example of this (and one which needs several checks) is that
9810 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9811 (This restriction does not apply to PLTs.) */
9814 mips_cfun_has_inflexible_gp_ref_p (void)
9816 /* If the function has a nonlocal goto, $28 must hold the correct
9817 global pointer for the target function. That is, the target
9818 of the goto implicitly uses $28. */
9819 if (crtl
->has_nonlocal_goto
)
9822 if (TARGET_ABICALLS_PIC2
)
9824 /* Symbolic accesses implicitly use the global pointer unless
9825 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9826 might go to traditional MIPS lazy-binding stubs. */
9827 if (!TARGET_EXPLICIT_RELOCS
)
9830 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9831 can be lazily-bound. */
9835 /* MIPS16 functions that return in FPRs need to call an
9836 external libgcc routine. This call is only made explict
9837 during mips_expand_epilogue, and it too might be lazily bound. */
9838 if (mips16_cfun_returns_in_fpr_p ())
9842 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9843 mips_insn_has_inflexible_gp_ref_p
);
9846 /* Return true if INSN refers to the global pointer in a "flexible" way.
9847 See mips_cfun_has_flexible_gp_ref_p for details. */
9850 mips_insn_has_flexible_gp_ref_p (rtx_insn
*insn
)
9852 return (get_attr_got (insn
) != GOT_UNSET
9853 || mips_small_data_pattern_p (PATTERN (insn
))
9854 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9857 /* Return true if the current function references the global pointer,
9858 but if those references do not inherently require the global pointer
9859 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9862 mips_cfun_has_flexible_gp_ref_p (void)
9864 /* Reload can sometimes introduce constant pool references
9865 into a function that otherwise didn't need them. For example,
9866 suppose we have an instruction like:
9868 (set (reg:DF R1) (float:DF (reg:SI R2)))
9870 If R2 turns out to be a constant such as 1, the instruction may
9871 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9872 the option of using this constant if R2 doesn't get allocated
9875 In cases like these, reload will have added the constant to the
9876 pool but no instruction will yet refer to it. */
9877 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9880 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9881 mips_insn_has_flexible_gp_ref_p
);
9884 /* Return the register that should be used as the global pointer
9885 within this function. Return INVALID_REGNUM if the function
9886 doesn't need a global pointer. */
9889 mips_global_pointer (void)
9893 /* $gp is always available unless we're using a GOT. */
9894 if (!TARGET_USE_GOT
)
9895 return GLOBAL_POINTER_REGNUM
;
9897 /* If there are inflexible references to $gp, we must use the
9898 standard register. */
9899 if (mips_cfun_has_inflexible_gp_ref_p ())
9900 return GLOBAL_POINTER_REGNUM
;
9902 /* If there are no current references to $gp, then the only uses
9903 we can introduce later are those involved in long branches. */
9904 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9905 return INVALID_REGNUM
;
9907 /* If the global pointer is call-saved, try to use a call-clobbered
9909 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9910 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9911 if (!df_regs_ever_live_p (regno
)
9912 && call_really_used_regs
[regno
]
9913 && !fixed_regs
[regno
]
9914 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9917 return GLOBAL_POINTER_REGNUM
;
9920 /* Return true if the current function's prologue must load the global
9921 pointer value into pic_offset_table_rtx and store the same value in
9922 the function's cprestore slot (if any).
9924 One problem we have to deal with is that, when emitting GOT-based
9925 position independent code, long-branch sequences will need to load
9926 the address of the branch target from the GOT. We don't know until
9927 the very end of compilation whether (and where) the function needs
9928 long branches, so we must ensure that _any_ branch can access the
9929 global pointer in some form. However, we do not want to pessimize
9930 the usual case in which all branches are short.
9932 We handle this as follows:
9934 (1) During reload, we set cfun->machine->global_pointer to
9935 INVALID_REGNUM if we _know_ that the current function
9936 doesn't need a global pointer. This is only valid if
9937 long branches don't need the GOT.
9939 Otherwise, we assume that we might need a global pointer
9940 and pick an appropriate register.
9942 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9943 we ensure that the global pointer is available at every
9944 block boundary bar entry and exit. We do this in one of two ways:
9946 - If the function has a cprestore slot, we ensure that this
9947 slot is valid at every branch. However, as explained in
9948 point (6) below, there is no guarantee that pic_offset_table_rtx
9949 itself is valid if new uses of the global pointer are introduced
9950 after the first post-epilogue split.
9952 We guarantee that the cprestore slot is valid by loading it
9953 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9954 this register live at every block boundary bar function entry
9955 and exit. It is then invalid to move the load (and thus the
9956 preceding store) across a block boundary.
9958 - If the function has no cprestore slot, we guarantee that
9959 pic_offset_table_rtx itself is valid at every branch.
9961 See mips_eh_uses for the handling of the register liveness.
9963 (3) During prologue and epilogue generation, we emit "ghost"
9964 placeholder instructions to manipulate the global pointer.
9966 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9967 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9968 that the function needs a global pointer. (There is no need to set
9969 them earlier than this, and doing it as late as possible leads to
9970 fewer false positives.)
9972 (5) If cfun->machine->must_initialize_gp_p is true during a
9973 split_insns pass, we split the ghost instructions into real
9974 instructions. These split instructions can then be optimized in
9975 the usual way. Otherwise, we keep the ghost instructions intact,
9976 and optimize for the case where they aren't needed. We still
9977 have the option of splitting them later, if we need to introduce
9978 new uses of the global pointer.
9980 For example, the scheduler ignores a ghost instruction that
9981 stores $28 to the stack, but it handles the split form of
9982 the ghost instruction as an ordinary store.
9984 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9985 is true during the first post-epilogue split_insns pass, we split
9986 calls and restore_gp patterns into instructions that explicitly
9987 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9988 we split these patterns into instructions that _don't_ load from
9991 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9992 time of the split, then any instructions that exist at that time
9993 can make free use of pic_offset_table_rtx. However, if we want
9994 to introduce new uses of the global pointer after the split,
9995 we must explicitly load the value from the cprestore slot, since
9996 pic_offset_table_rtx itself might not be valid at a given point
9999 The idea is that we want to be able to delete redundant
10000 loads from the cprestore slot in the usual case where no
10001 long branches are needed.
10003 (7) If cfun->machine->must_initialize_gp_p is still false at the end
10004 of md_reorg, we decide whether the global pointer is needed for
10005 long branches. If so, we set cfun->machine->must_initialize_gp_p
10006 to true and split the ghost instructions into real instructions
10009 Note that the ghost instructions must have a zero length for three reasons:
10011 - Giving the length of the underlying $gp sequence might cause
10012 us to use long branches in cases where they aren't really needed.
10014 - They would perturb things like alignment calculations.
10016 - More importantly, the hazard detection in md_reorg relies on
10017 empty instructions having a zero length.
10019 If we find a long branch and split the ghost instructions at the
10020 end of md_reorg, the split could introduce more long branches.
10021 That isn't a problem though, because we still do the split before
10022 the final shorten_branches pass.
10024 This is extremely ugly, but it seems like the best compromise between
10025 correctness and efficiency. */
10028 mips_must_initialize_gp_p (void)
10030 return cfun
->machine
->must_initialize_gp_p
;
10033 /* Return true if REGNO is a register that is ordinarily call-clobbered
10034 but must nevertheless be preserved by an interrupt handler. */
10037 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
10039 if ((ISA_HAS_HILO
|| TARGET_DSP
)
10040 && MD_REG_P (regno
))
10043 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
10046 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
10048 /* $0 is hard-wired. */
10049 if (regno
== GP_REG_FIRST
)
10052 /* The interrupt handler can treat kernel registers as
10053 scratch registers. */
10054 if (KERNEL_REG_P (regno
))
10057 /* The function will return the stack pointer to its original value
10059 if (regno
== STACK_POINTER_REGNUM
)
10062 /* Otherwise, return true for registers that aren't ordinarily
10064 return call_really_used_regs
[regno
];
10070 /* Return true if the current function should treat register REGNO
10074 mips_cfun_call_saved_reg_p (unsigned int regno
)
10076 /* If the user makes an ordinarily-call-saved register global,
10077 that register is no longer call-saved. */
10078 if (global_regs
[regno
])
10081 /* Interrupt handlers need to save extra registers. */
10082 if (cfun
->machine
->interrupt_handler_p
10083 && mips_interrupt_extra_call_saved_reg_p (regno
))
10086 /* call_insns preserve $28 unless they explicitly say otherwise,
10087 so call_really_used_regs[] treats $28 as call-saved. However,
10088 we want the ABI property rather than the default call_insn
10090 return (regno
== GLOBAL_POINTER_REGNUM
10091 ? TARGET_CALL_SAVED_GP
10092 : !call_really_used_regs
[regno
]);
10095 /* Return true if the function body might clobber register REGNO.
10096 We know that REGNO is call-saved. */
10099 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
10101 /* Some functions should be treated as clobbering all call-saved
10103 if (crtl
->saves_all_registers
)
10106 /* DF handles cases where a register is explicitly referenced in
10107 the rtl. Incoming values are passed in call-clobbered registers,
10108 so we can assume that any live call-saved register is set within
10110 if (df_regs_ever_live_p (regno
))
10113 /* Check for registers that are clobbered by FUNCTION_PROFILER.
10114 These clobbers are not explicit in the rtl. */
10115 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
10118 /* If we're using a call-saved global pointer, the function's
10119 prologue will need to set it up. */
10120 if (cfun
->machine
->global_pointer
== regno
)
10123 /* The function's prologue will need to set the frame pointer if
10124 frame_pointer_needed. */
10125 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
10128 /* If a MIPS16 function returns a value in FPRs, its epilogue
10129 will need to call an external libgcc routine. This yet-to-be
10130 generated call_insn will clobber $31. */
10131 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
10134 /* If REGNO is ordinarily call-clobbered, we must assume that any
10135 called function could modify it. */
10136 if (cfun
->machine
->interrupt_handler_p
10138 && mips_interrupt_extra_call_saved_reg_p (regno
))
10144 /* Return true if the current function must save register REGNO. */
10147 mips_save_reg_p (unsigned int regno
)
10149 if (mips_cfun_call_saved_reg_p (regno
))
10151 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
10154 /* Save both registers in an FPR pair if either one is used. This is
10155 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10156 register to be used without the even register. */
10157 if (FP_REG_P (regno
)
10158 && MAX_FPRS_PER_FMT
== 2
10159 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
10163 /* We need to save the incoming return address if __builtin_eh_return
10164 is being used to set a different return address. */
10165 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
10171 /* Populate the current function's mips_frame_info structure.
10173 MIPS stack frames look like:
10175 +-------------------------------+
10177 | incoming stack arguments |
10179 +-------------------------------+
10181 | caller-allocated save area |
10182 A | for register arguments |
10184 +-------------------------------+ <-- incoming stack pointer
10186 | callee-allocated save area |
10187 B | for arguments that are |
10188 | split between registers and |
10191 +-------------------------------+ <-- arg_pointer_rtx
10193 C | callee-allocated save area |
10194 | for register varargs |
10196 +-------------------------------+ <-- frame_pointer_rtx
10197 | | + cop0_sp_offset
10198 | COP0 reg save area | + UNITS_PER_WORD
10200 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10201 | | + UNITS_PER_WORD
10202 | accumulator save area |
10204 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10205 | | + UNITS_PER_HWFPVALUE
10208 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10209 | | + UNITS_PER_WORD
10212 +-------------------------------+ <-- frame_pointer_rtx with
10213 | | \ -fstack-protector
10214 | local variables | | var_size
10216 +-------------------------------+
10218 | $gp save area | | cprestore_size
10220 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10222 | outgoing stack arguments | |
10224 +-------------------------------+ | args_size
10226 | caller-allocated save area | |
10227 | for register arguments | |
10229 +-------------------------------+ <-- stack_pointer_rtx
10230 frame_pointer_rtx without
10232 hard_frame_pointer_rtx for
10235 At least two of A, B and C will be empty.
10237 Dynamic stack allocations such as alloca insert data at point P.
10238 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10239 hard_frame_pointer_rtx unchanged. */
10242 mips_compute_frame_info (void)
10244 struct mips_frame_info
*frame
;
10245 HOST_WIDE_INT offset
, size
;
10246 unsigned int regno
, i
;
10248 /* Set this function's interrupt properties. */
10249 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
10251 if (mips_isa_rev
< 2)
10252 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10253 else if (TARGET_HARD_FLOAT
)
10254 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10255 else if (TARGET_MIPS16
)
10256 error ("interrupt handlers cannot be MIPS16 functions");
10259 cfun
->machine
->interrupt_handler_p
= true;
10260 cfun
->machine
->use_shadow_register_set_p
=
10261 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
10262 cfun
->machine
->keep_interrupts_masked_p
=
10263 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10264 cfun
->machine
->use_debug_exception_return_p
=
10265 mips_use_debug_exception_return_p (TREE_TYPE
10266 (current_function_decl
));
10270 frame
= &cfun
->machine
->frame
;
10271 memset (frame
, 0, sizeof (*frame
));
10272 size
= get_frame_size ();
10274 cfun
->machine
->global_pointer
= mips_global_pointer ();
10276 /* The first two blocks contain the outgoing argument area and the $gp save
10277 slot. This area isn't needed in leaf functions, but if the
10278 target-independent frame size is nonzero, we have already committed to
10279 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10280 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
10282 /* The MIPS 3.0 linker does not like functions that dynamically
10283 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10284 looks like we are trying to create a second frame pointer to the
10285 function, so allocate some stack space to make it happy. */
10286 if (cfun
->calls_alloca
)
10287 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
10289 frame
->args_size
= 0;
10290 frame
->cprestore_size
= 0;
10294 frame
->args_size
= crtl
->outgoing_args_size
;
10295 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
10297 offset
= frame
->args_size
+ frame
->cprestore_size
;
10299 /* Move above the local variables. */
10300 frame
->var_size
= MIPS_STACK_ALIGN (size
);
10301 offset
+= frame
->var_size
;
10303 /* Find out which GPRs we need to save. */
10304 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10305 if (mips_save_reg_p (regno
))
10308 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
10311 /* If this function calls eh_return, we must also save and restore the
10312 EH data registers. */
10313 if (crtl
->calls_eh_return
)
10314 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
10317 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
10320 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10321 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10322 save all later registers too. */
10323 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10325 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
10326 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
10327 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
10328 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
10331 /* Move above the GPR save area. */
10332 if (frame
->num_gp
> 0)
10334 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
10335 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
10338 /* Find out which FPRs we need to save. This loop must iterate over
10339 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10340 if (TARGET_HARD_FLOAT
)
10341 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
10342 if (mips_save_reg_p (regno
))
10344 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
10345 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
10348 /* Move above the FPR save area. */
10349 if (frame
->num_fp
> 0)
10351 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
10352 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
10355 /* Add in space for the interrupt context information. */
10356 if (cfun
->machine
->interrupt_handler_p
)
10359 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
10362 frame
->acc_mask
|= (1 << 0);
10365 /* Check accumulators 1, 2, 3. */
10366 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10367 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10370 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10373 /* All interrupt context functions need space to preserve STATUS. */
10374 frame
->num_cop0_regs
++;
10376 /* If we don't keep interrupts masked, we need to save EPC. */
10377 if (!cfun
->machine
->keep_interrupts_masked_p
)
10378 frame
->num_cop0_regs
++;
10381 /* Move above the accumulator save area. */
10382 if (frame
->num_acc
> 0)
10384 /* Each accumulator needs 2 words. */
10385 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10386 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10389 /* Move above the COP0 register save area. */
10390 if (frame
->num_cop0_regs
> 0)
10392 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10393 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10396 /* Move above the callee-allocated varargs save area. */
10397 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10398 frame
->arg_pointer_offset
= offset
;
10400 /* Move above the callee-allocated area for pretend stack arguments. */
10401 offset
+= crtl
->args
.pretend_args_size
;
10402 frame
->total_size
= offset
;
10404 /* Work out the offsets of the save areas from the top of the frame. */
10405 if (frame
->gp_sp_offset
> 0)
10406 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10407 if (frame
->fp_sp_offset
> 0)
10408 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10409 if (frame
->acc_sp_offset
> 0)
10410 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10411 if (frame
->num_cop0_regs
> 0)
10412 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10414 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10415 arguments. This tends to increase the chances of using unextended
10416 instructions for local variables and incoming arguments. */
10418 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10421 /* Return the style of GP load sequence that is being used for the
10422 current function. */
10424 enum mips_loadgp_style
10425 mips_current_loadgp_style (void)
10427 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10428 return LOADGP_NONE
;
10430 if (TARGET_RTP_PIC
)
10433 if (TARGET_ABSOLUTE_ABICALLS
)
10434 return LOADGP_ABSOLUTE
;
10436 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10439 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10442 mips_frame_pointer_required (void)
10444 /* If the function contains dynamic stack allocations, we need to
10445 use the frame pointer to access the static parts of the frame. */
10446 if (cfun
->calls_alloca
)
10449 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10450 reload may be unable to compute the address of a local variable,
10451 since there is no way to add a large constant to the stack pointer
10452 without using a second temporary register. */
10455 mips_compute_frame_info ();
10456 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10463 /* Make sure that we're not trying to eliminate to the wrong hard frame
10467 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10469 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10472 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10473 or argument pointer. TO is either the stack pointer or hard frame
10477 mips_initial_elimination_offset (int from
, int to
)
10479 HOST_WIDE_INT offset
;
10481 mips_compute_frame_info ();
10483 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10486 case FRAME_POINTER_REGNUM
:
10487 if (FRAME_GROWS_DOWNWARD
)
10488 offset
= (cfun
->machine
->frame
.args_size
10489 + cfun
->machine
->frame
.cprestore_size
10490 + cfun
->machine
->frame
.var_size
);
10495 case ARG_POINTER_REGNUM
:
10496 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10500 gcc_unreachable ();
10503 if (to
== HARD_FRAME_POINTER_REGNUM
)
10504 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10509 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10512 mips_extra_live_on_entry (bitmap regs
)
10514 if (TARGET_USE_GOT
)
10516 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10517 the global pointer. */
10518 if (!TARGET_ABSOLUTE_ABICALLS
)
10519 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10521 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10522 the global pointer. */
10524 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10526 /* See the comment above load_call<mode> for details. */
10527 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10531 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10535 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10540 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10543 /* Emit code to change the current function's return address to
10544 ADDRESS. SCRATCH is available as a scratch register, if needed.
10545 ADDRESS and SCRATCH are both word-mode GPRs. */
10548 mips_set_return_address (rtx address
, rtx scratch
)
10552 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10553 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10554 cfun
->machine
->frame
.gp_sp_offset
);
10555 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10558 /* Return true if the current function has a cprestore slot. */
10561 mips_cfun_has_cprestore_slot_p (void)
10563 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10564 && cfun
->machine
->frame
.cprestore_size
> 0);
10567 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10568 cprestore slot. LOAD_P is true if the caller wants to load from
10569 the cprestore slot; it is false if the caller wants to store to
10573 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10576 const struct mips_frame_info
*frame
;
10578 frame
= &cfun
->machine
->frame
;
10579 /* .cprestore always uses the stack pointer instead of the frame pointer.
10580 We have a free choice for direct stores for non-MIPS16 functions,
10581 and for MIPS16 functions whose cprestore slot is in range of the
10582 stack pointer. Using the stack pointer would sometimes give more
10583 (early) scheduling freedom, but using the frame pointer would
10584 sometimes give more (late) scheduling freedom. It's hard to
10585 predict which applies to a given function, so let's keep things
10588 Loads must always use the frame pointer in functions that call
10589 alloca, and there's little benefit to using the stack pointer
10591 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10593 *base
= hard_frame_pointer_rtx
;
10594 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10598 *base
= stack_pointer_rtx
;
10599 *offset
= frame
->args_size
;
10603 /* Return true if X is the load or store address of the cprestore slot;
10604 LOAD_P says which. */
10607 mips_cprestore_address_p (rtx x
, bool load_p
)
10609 rtx given_base
, required_base
;
10610 HOST_WIDE_INT given_offset
, required_offset
;
10612 mips_split_plus (x
, &given_base
, &given_offset
);
10613 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10614 return given_base
== required_base
&& given_offset
== required_offset
;
10617 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10618 going to load from it, false if we are going to store to it.
10619 Use TEMP as a temporary register if need be. */
10622 mips_cprestore_slot (rtx temp
, bool load_p
)
10625 HOST_WIDE_INT offset
;
10627 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10628 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10631 /* Emit instructions to save global pointer value GP into cprestore
10632 slot MEM. OFFSET is the offset that MEM applies to the base register.
10634 MEM may not be a legitimate address. If it isn't, TEMP is a
10635 temporary register that can be used, otherwise it is a SCRATCH. */
10638 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10640 if (TARGET_CPRESTORE_DIRECTIVE
)
10642 gcc_assert (gp
== pic_offset_table_rtx
);
10643 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10646 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10649 /* Restore $gp from its save slot, using TEMP as a temporary base register
10650 if need be. This function is for o32 and o64 abicalls only.
10652 See mips_must_initialize_gp_p for details about how we manage the
10656 mips_restore_gp_from_cprestore_slot (rtx temp
)
10658 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10660 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10662 emit_note (NOTE_INSN_DELETED
);
10668 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10669 mips_emit_move (pic_offset_table_rtx
, temp
);
10672 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10673 if (!TARGET_EXPLICIT_RELOCS
)
10674 emit_insn (gen_blockage ());
10677 /* A function to save or store a register. The first argument is the
10678 register and the second is the stack slot. */
10679 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10681 /* Use FN to save or restore register REGNO. MODE is the register's
10682 mode and OFFSET is the offset of its save slot from the current
10686 mips_save_restore_reg (machine_mode mode
, int regno
,
10687 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10691 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10693 fn (gen_rtx_REG (mode
, regno
), mem
);
10696 /* Call FN for each accumlator that is saved by the current function.
10697 SP_OFFSET is the offset of the current stack pointer from the start
10701 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10703 HOST_WIDE_INT offset
;
10706 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10707 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10709 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10710 offset
-= UNITS_PER_WORD
;
10711 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10712 offset
-= UNITS_PER_WORD
;
10715 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10716 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10717 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10719 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10720 offset
-= UNITS_PER_WORD
;
10724 /* Save register REG to MEM. Make the instruction frame-related. */
10727 mips_save_reg (rtx reg
, rtx mem
)
10729 if (GET_MODE (reg
) == DFmode
10730 && (!TARGET_FLOAT64
10731 || mips_abi
== ABI_32
))
10735 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10737 x1
= mips_frame_set (mips_subword (mem
, false),
10738 mips_subword (reg
, false));
10739 x2
= mips_frame_set (mips_subword (mem
, true),
10740 mips_subword (reg
, true));
10741 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10744 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10747 /* Capture the register combinations that are allowed in a SWM or LWM
10748 instruction. The entries are ordered by number of registers set in
10749 the mask. We also ignore the single register encodings because a
10750 normal SW/LW is preferred. */
10752 static const unsigned int umips_swm_mask
[17] = {
10753 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10754 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10755 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10756 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10760 static const unsigned int umips_swm_encoding
[17] = {
10761 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10764 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10765 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10766 stack pointer of the topmost save slot.
10768 Remove from *MASK all registers that were handled using LWM and SWM.
10769 Update *OFFSET so that it points to the first unused save slot. */
10772 umips_build_save_restore (mips_save_restore_fn fn
,
10773 unsigned *mask
, HOST_WIDE_INT
*offset
)
10777 rtx pattern
, set
, reg
, mem
;
10778 HOST_WIDE_INT this_offset
;
10781 /* Try matching $16 to $31 (s0 to ra). */
10782 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10783 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10786 if (i
== ARRAY_SIZE (umips_swm_mask
))
10789 /* Get the offset of the lowest save slot. */
10790 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10791 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10793 /* LWM/SWM can only support offsets from -2048 to 2047. */
10794 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10797 /* Create the final PARALLEL. */
10798 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10799 this_base
= stack_pointer_rtx
;
10801 /* For registers $16-$23 and $30. */
10802 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10804 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10805 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10806 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10807 *mask
&= ~(1 << regno
);
10808 reg
= gen_rtx_REG (SImode
, regno
);
10809 if (fn
== mips_save_reg
)
10810 set
= mips_frame_set (mem
, reg
);
10813 set
= gen_rtx_SET (reg
, mem
);
10814 mips_add_cfa_restore (reg
);
10816 XVECEXP (pattern
, 0, j
) = set
;
10819 /* For register $31. */
10820 if (umips_swm_encoding
[i
] >> 4)
10822 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10823 *mask
&= ~(1 << 31);
10824 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10825 reg
= gen_rtx_REG (SImode
, 31);
10826 if (fn
== mips_save_reg
)
10827 set
= mips_frame_set (mem
, reg
);
10830 set
= gen_rtx_SET (reg
, mem
);
10831 mips_add_cfa_restore (reg
);
10833 XVECEXP (pattern
, 0, j
) = set
;
10836 pattern
= emit_insn (pattern
);
10837 if (fn
== mips_save_reg
)
10838 RTX_FRAME_RELATED_P (pattern
) = 1;
10840 /* Adjust the last offset. */
10841 *offset
-= UNITS_PER_WORD
* nregs
;
10846 /* Call FN for each register that is saved by the current function.
10847 SP_OFFSET is the offset of the current stack pointer from the start
10851 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10852 mips_save_restore_fn fn
)
10854 machine_mode fpr_mode
;
10856 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10857 HOST_WIDE_INT offset
;
10860 /* Save registers starting from high to low. The debuggers prefer at least
10861 the return register be stored at func+4, and also it allows us not to
10862 need a nop in the epilogue if at least one register is reloaded in
10863 addition to return address. */
10864 offset
= frame
->gp_sp_offset
- sp_offset
;
10865 mask
= frame
->mask
;
10867 if (TARGET_MICROMIPS
)
10868 umips_build_save_restore (fn
, &mask
, &offset
);
10870 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10871 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10873 /* Record the ra offset for use by mips_function_profiler. */
10874 if (regno
== RETURN_ADDR_REGNUM
)
10875 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10876 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10877 offset
-= UNITS_PER_WORD
;
10880 /* This loop must iterate over the same space as its companion in
10881 mips_compute_frame_info. */
10882 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10883 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10884 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10885 regno
>= FP_REG_FIRST
;
10886 regno
-= MAX_FPRS_PER_FMT
)
10887 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10889 if (!TARGET_FLOAT64
&& TARGET_DOUBLE_FLOAT
10890 && (fixed_regs
[regno
] || fixed_regs
[regno
+ 1]))
10892 if (fixed_regs
[regno
])
10893 mips_save_restore_reg (SFmode
, regno
+ 1, offset
, fn
);
10895 mips_save_restore_reg (SFmode
, regno
, offset
, fn
);
10898 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10899 offset
-= GET_MODE_SIZE (fpr_mode
);
10903 /* Return true if a move between register REGNO and its save slot (MEM)
10904 can be done in a single move. LOAD_P is true if we are loading
10905 from the slot, false if we are storing to it. */
10908 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10910 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10911 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10914 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10915 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10918 /* Emit a move from SRC to DEST, given that one of them is a register
10919 save slot and that the other is a register. TEMP is a temporary
10920 GPR of the same mode that is available if need be. */
10923 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10925 unsigned int regno
;
10930 regno
= REGNO (src
);
10935 regno
= REGNO (dest
);
10939 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10941 /* We don't yet know whether we'll need this instruction or not.
10942 Postpone the decision by emitting a ghost move. This move
10943 is specifically not frame-related; only the split version is. */
10945 emit_insn (gen_move_gpdi (dest
, src
));
10947 emit_insn (gen_move_gpsi (dest
, src
));
10951 if (regno
== HI_REGNUM
)
10955 mips_emit_move (temp
, src
);
10957 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10958 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10960 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10961 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10966 emit_insn (gen_mfhidi_ti (temp
,
10967 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10969 emit_insn (gen_mfhisi_di (temp
,
10970 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10971 mips_emit_move (dest
, temp
);
10974 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10975 mips_emit_move (dest
, src
);
10978 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10979 mips_emit_move (temp
, src
);
10980 mips_emit_move (dest
, temp
);
10983 mips_set_frame_expr (mips_frame_set (dest
, src
));
10986 /* If we're generating n32 or n64 abicalls, and the current function
10987 does not use $28 as its global pointer, emit a cplocal directive.
10988 Use pic_offset_table_rtx as the argument to the directive. */
10991 mips_output_cplocal (void)
10993 if (!TARGET_EXPLICIT_RELOCS
10994 && mips_must_initialize_gp_p ()
10995 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10996 output_asm_insn (".cplocal %+", 0);
10999 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
11002 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
11004 const char *fnname
;
11006 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
11007 floating-point arguments. */
11009 && TARGET_HARD_FLOAT_ABI
11010 && crtl
->args
.info
.fp_code
!= 0)
11011 mips16_build_function_stub ();
11013 /* Get the function name the same way that toplev.c does before calling
11014 assemble_start_function. This is needed so that the name used here
11015 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11016 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11017 mips_start_function_definition (fnname
, TARGET_MIPS16
);
11019 /* Output MIPS-specific frame information. */
11020 if (!flag_inhibit_size_directive
)
11022 const struct mips_frame_info
*frame
;
11024 frame
= &cfun
->machine
->frame
;
11026 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
11028 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
11029 "# vars= " HOST_WIDE_INT_PRINT_DEC
11031 ", args= " HOST_WIDE_INT_PRINT_DEC
11032 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
11033 reg_names
[frame_pointer_needed
11034 ? HARD_FRAME_POINTER_REGNUM
11035 : STACK_POINTER_REGNUM
],
11036 (frame_pointer_needed
11037 ? frame
->total_size
- frame
->hard_frame_pointer_offset
11038 : frame
->total_size
),
11039 reg_names
[RETURN_ADDR_REGNUM
],
11041 frame
->num_gp
, frame
->num_fp
,
11043 frame
->cprestore_size
);
11045 /* .mask MASK, OFFSET. */
11046 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11047 frame
->mask
, frame
->gp_save_offset
);
11049 /* .fmask MASK, OFFSET. */
11050 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11051 frame
->fmask
, frame
->fp_save_offset
);
11054 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
11055 Also emit the ".set noreorder; .set nomacro" sequence for functions
11057 if (mips_must_initialize_gp_p ()
11058 && mips_current_loadgp_style () == LOADGP_OLDABI
)
11062 /* This is a fixed-form sequence. The position of the
11063 first two instructions is important because of the
11064 way _gp_disp is defined. */
11065 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
11066 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
11067 output_asm_insn ("sll\t$2,16", 0);
11068 output_asm_insn ("addu\t$2,$3", 0);
11072 /* .cpload must be in a .set noreorder but not a
11073 .set nomacro block. */
11074 mips_push_asm_switch (&mips_noreorder
);
11075 output_asm_insn (".cpload\t%^", 0);
11076 if (!cfun
->machine
->all_noreorder_p
)
11077 mips_pop_asm_switch (&mips_noreorder
);
11079 mips_push_asm_switch (&mips_nomacro
);
11082 else if (cfun
->machine
->all_noreorder_p
)
11084 mips_push_asm_switch (&mips_noreorder
);
11085 mips_push_asm_switch (&mips_nomacro
);
11088 /* Tell the assembler which register we're using as the global
11089 pointer. This is needed for thunks, since they can use either
11090 explicit relocs or assembler macros. */
11091 mips_output_cplocal ();
11094 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
11097 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
11098 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
11100 const char *fnname
;
11102 /* Reinstate the normal $gp. */
11103 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
11104 mips_output_cplocal ();
11106 if (cfun
->machine
->all_noreorder_p
)
11108 mips_pop_asm_switch (&mips_nomacro
);
11109 mips_pop_asm_switch (&mips_noreorder
);
11112 /* Get the function name the same way that toplev.c does before calling
11113 assemble_start_function. This is needed so that the name used here
11114 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11115 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11116 mips_end_function_definition (fnname
);
11119 /* Emit an optimisation barrier for accesses to the current frame. */
11122 mips_frame_barrier (void)
11124 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
11128 /* The __gnu_local_gp symbol. */
11130 static GTY(()) rtx mips_gnu_local_gp
;
11132 /* If we're generating n32 or n64 abicalls, emit instructions
11133 to set up the global pointer. */
11136 mips_emit_loadgp (void)
11138 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
11140 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11141 switch (mips_current_loadgp_style ())
11143 case LOADGP_ABSOLUTE
:
11144 if (mips_gnu_local_gp
== NULL
)
11146 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
11147 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
11149 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
11150 (pic_reg
, mips_gnu_local_gp
)));
11153 case LOADGP_OLDABI
:
11154 /* Added by mips_output_function_prologue. */
11157 case LOADGP_NEWABI
:
11158 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
11159 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
11160 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11161 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
11162 (pic_reg
, offset
, incoming_address
)));
11166 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
11167 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
11168 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
11176 emit_insn (PMODE_INSN (gen_copygp_mips16
,
11177 (pic_offset_table_rtx
, pic_reg
)));
11179 /* Emit a blockage if there are implicit uses of the GP register.
11180 This includes profiled functions, because FUNCTION_PROFILE uses
11182 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
11183 emit_insn (gen_loadgp_blockage ());
11186 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11188 #if PROBE_INTERVAL > 32768
11189 #error Cannot use indexed addressing mode for stack probing
11192 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11193 inclusive. These are offsets from the current stack pointer. */
11196 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
11199 sorry ("-fstack-check=specific not implemented for MIPS16");
11201 /* See if we have a constant small number of probes to generate. If so,
11202 that's the easy case. */
11203 if (first
+ size
<= 32768)
11207 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11208 it exceeds SIZE. If only one probe is needed, this will not
11209 generate any code. Then probe at FIRST + SIZE. */
11210 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
11211 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11214 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11218 /* Otherwise, do the same as above, but in a loop. Note that we must be
11219 extra careful with variables wrapping around because we might be at
11220 the very top (or the very bottom) of the address space and we have
11221 to be able to handle this case properly; in particular, we use an
11222 equality test for the loop condition. */
11225 HOST_WIDE_INT rounded_size
;
11226 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
11227 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
11229 /* Sanity check for the addressing mode we're going to use. */
11230 gcc_assert (first
<= 32768);
11233 /* Step 1: round SIZE to the previous multiple of the interval. */
11235 rounded_size
= size
& -PROBE_INTERVAL
;
11238 /* Step 2: compute initial and final value of the loop counter. */
11240 /* TEST_ADDR = SP + FIRST. */
11241 emit_insn (gen_rtx_SET (r3
, plus_constant (Pmode
, stack_pointer_rtx
,
11244 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11245 if (rounded_size
> 32768)
11247 emit_move_insn (r12
, GEN_INT (rounded_size
));
11248 emit_insn (gen_rtx_SET (r12
, gen_rtx_MINUS (Pmode
, r3
, r12
)));
11251 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, r3
,
11255 /* Step 3: the loop
11257 while (TEST_ADDR != LAST_ADDR)
11259 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11263 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11264 until it is equal to ROUNDED_SIZE. */
11266 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
11269 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11270 that SIZE is equal to ROUNDED_SIZE. */
11272 if (size
!= rounded_size
)
11273 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
11276 /* Make sure nothing is scheduled before we are done. */
11277 emit_insn (gen_blockage ());
11280 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11281 absolute addresses. */
11284 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
11286 static int labelno
= 0;
11287 char loop_lab
[32], end_lab
[32], tmp
[64];
11290 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
11291 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
11293 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
11295 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11298 strcpy (tmp
, "%(%<beq\t%0,%1,");
11299 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
11301 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11302 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
11303 if (TARGET_64BIT
&& TARGET_LONG64
)
11304 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
11306 output_asm_insn ("addiu\t%0,%0,%1", xops
);
11308 /* Probe at TEST_ADDR and branch. */
11309 fprintf (asm_out_file
, "\tb\t");
11310 assemble_name_raw (asm_out_file
, loop_lab
);
11311 fputc ('\n', asm_out_file
);
11313 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
11315 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
11317 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
11322 /* Return true if X contains a kernel register. */
11325 mips_refers_to_kernel_reg_p (const_rtx x
)
11327 subrtx_iterator::array_type array
;
11328 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
11329 if (REG_P (*iter
) && KERNEL_REG_P (REGNO (*iter
)))
11334 /* Expand the "prologue" pattern. */
11337 mips_expand_prologue (void)
11339 const struct mips_frame_info
*frame
;
11340 HOST_WIDE_INT size
;
11341 unsigned int nargs
;
11343 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
11345 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11346 or implicitly. If so, we can commit to using a global pointer
11347 straight away, otherwise we need to defer the decision. */
11348 if (mips_cfun_has_inflexible_gp_ref_p ()
11349 || mips_cfun_has_flexible_gp_ref_p ())
11351 cfun
->machine
->must_initialize_gp_p
= true;
11352 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
11355 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11358 frame
= &cfun
->machine
->frame
;
11359 size
= frame
->total_size
;
11361 if (flag_stack_usage_info
)
11362 current_function_static_stack_size
= size
;
11364 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
11366 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
11368 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
11369 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
11370 size
- STACK_CHECK_PROTECT
);
11373 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
11376 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11377 bytes beforehand; this is enough to cover the register save area
11378 without going out of range. */
11379 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
11380 || frame
->num_cop0_regs
> 0)
11382 HOST_WIDE_INT step1
;
11384 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
11385 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11387 HOST_WIDE_INT offset
;
11388 unsigned int mask
, regno
;
11390 /* Try to merge argument stores into the save instruction. */
11391 nargs
= mips16e_collect_argument_saves ();
11393 /* Build the save instruction. */
11394 mask
= frame
->mask
;
11395 rtx insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11397 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11398 mips_frame_barrier ();
11401 /* Check if we need to save other registers. */
11402 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11403 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11405 offset
-= UNITS_PER_WORD
;
11406 mips_save_restore_reg (word_mode
, regno
,
11407 offset
, mips_save_reg
);
11412 if (cfun
->machine
->interrupt_handler_p
)
11414 HOST_WIDE_INT offset
;
11417 /* If this interrupt is using a shadow register set, we need to
11418 get the stack pointer from the previous register set. */
11419 if (cfun
->machine
->use_shadow_register_set_p
)
11420 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11421 stack_pointer_rtx
));
11423 if (!cfun
->machine
->keep_interrupts_masked_p
)
11425 /* Move from COP0 Cause to K0. */
11426 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11427 gen_rtx_REG (SImode
,
11428 COP0_CAUSE_REG_NUM
)));
11429 /* Move from COP0 EPC to K1. */
11430 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11431 gen_rtx_REG (SImode
,
11432 COP0_EPC_REG_NUM
)));
11435 /* Allocate the first part of the frame. */
11436 rtx insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11438 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11439 mips_frame_barrier ();
11442 /* Start at the uppermost location for saving. */
11443 offset
= frame
->cop0_sp_offset
- size
;
11444 if (!cfun
->machine
->keep_interrupts_masked_p
)
11446 /* Push EPC into its stack slot. */
11447 mem
= gen_frame_mem (word_mode
,
11448 plus_constant (Pmode
, stack_pointer_rtx
,
11450 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11451 offset
-= UNITS_PER_WORD
;
11454 /* Move from COP0 Status to K1. */
11455 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11456 gen_rtx_REG (SImode
,
11457 COP0_STATUS_REG_NUM
)));
11459 /* Right justify the RIPL in k0. */
11460 if (!cfun
->machine
->keep_interrupts_masked_p
)
11461 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11462 gen_rtx_REG (SImode
, K0_REG_NUM
),
11463 GEN_INT (CAUSE_IPL
)));
11465 /* Push Status into its stack slot. */
11466 mem
= gen_frame_mem (word_mode
,
11467 plus_constant (Pmode
, stack_pointer_rtx
,
11469 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11470 offset
-= UNITS_PER_WORD
;
11472 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11473 if (!cfun
->machine
->keep_interrupts_masked_p
)
11474 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11477 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11479 if (!cfun
->machine
->keep_interrupts_masked_p
)
11480 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11481 IE is already the correct value, so we don't have to do
11482 anything explicit. */
11483 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11486 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11488 /* Disable interrupts by clearing the KSU, ERL, EXL,
11490 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11493 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11497 rtx insn
= gen_add3_insn (stack_pointer_rtx
,
11500 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11501 mips_frame_barrier ();
11504 mips_for_each_saved_acc (size
, mips_save_reg
);
11505 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11509 /* Allocate the rest of the frame. */
11512 if (SMALL_OPERAND (-size
))
11513 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11515 GEN_INT (-size
)))) = 1;
11518 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11521 /* There are no instructions to add or subtract registers
11522 from the stack pointer, so use the frame pointer as a
11523 temporary. We should always be using a frame pointer
11524 in this case anyway. */
11525 gcc_assert (frame_pointer_needed
);
11526 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11527 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11528 hard_frame_pointer_rtx
,
11529 MIPS_PROLOGUE_TEMP (Pmode
)));
11530 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11533 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11535 MIPS_PROLOGUE_TEMP (Pmode
)));
11537 /* Describe the combined effect of the previous instructions. */
11538 mips_set_frame_expr
11539 (gen_rtx_SET (stack_pointer_rtx
,
11540 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11542 mips_frame_barrier ();
11545 /* Set up the frame pointer, if we're using one. */
11546 if (frame_pointer_needed
)
11548 HOST_WIDE_INT offset
;
11550 offset
= frame
->hard_frame_pointer_offset
;
11553 rtx insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11554 RTX_FRAME_RELATED_P (insn
) = 1;
11556 else if (SMALL_OPERAND (offset
))
11558 rtx insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11559 stack_pointer_rtx
, GEN_INT (offset
));
11560 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11564 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11565 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11566 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11567 hard_frame_pointer_rtx
,
11568 MIPS_PROLOGUE_TEMP (Pmode
)));
11569 mips_set_frame_expr
11570 (gen_rtx_SET (hard_frame_pointer_rtx
,
11571 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11575 mips_emit_loadgp ();
11577 /* Initialize the $gp save slot. */
11578 if (mips_cfun_has_cprestore_slot_p ())
11580 rtx base
, mem
, gp
, temp
;
11581 HOST_WIDE_INT offset
;
11583 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11584 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11585 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11586 temp
= (SMALL_OPERAND (offset
)
11587 ? gen_rtx_SCRATCH (Pmode
)
11588 : MIPS_PROLOGUE_TEMP (Pmode
));
11589 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11590 (mem
, GEN_INT (offset
), gp
, temp
)));
11592 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11593 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11594 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11597 /* We need to search back to the last use of K0 or K1. */
11598 if (cfun
->machine
->interrupt_handler_p
)
11601 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11603 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
11605 /* Emit a move from K1 to COP0 Status after insn. */
11606 gcc_assert (insn
!= NULL_RTX
);
11607 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11608 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11612 /* If we are profiling, make sure no instructions are scheduled before
11613 the call to mcount. */
11615 emit_insn (gen_blockage ());
11618 /* Attach all pending register saves to the previous instruction.
11619 Return that instruction. */
11622 mips_epilogue_emit_cfa_restores (void)
11626 insn
= get_last_insn ();
11627 gcc_assert (insn
&& !REG_NOTES (insn
));
11628 if (mips_epilogue
.cfa_restores
)
11630 RTX_FRAME_RELATED_P (insn
) = 1;
11631 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11632 mips_epilogue
.cfa_restores
= 0;
11637 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11638 now at REG + OFFSET. */
11641 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11645 insn
= mips_epilogue_emit_cfa_restores ();
11646 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11648 RTX_FRAME_RELATED_P (insn
) = 1;
11649 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11650 plus_constant (Pmode
, reg
, offset
),
11652 mips_epilogue
.cfa_reg
= reg
;
11653 mips_epilogue
.cfa_offset
= offset
;
11657 /* Emit instructions to restore register REG from slot MEM. Also update
11658 the cfa_restores list. */
11661 mips_restore_reg (rtx reg
, rtx mem
)
11663 /* There's no MIPS16 instruction to load $31 directly. Load into
11664 $7 instead and adjust the return insn appropriately. */
11665 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11666 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11667 else if (GET_MODE (reg
) == DFmode
11668 && (!TARGET_FLOAT64
11669 || mips_abi
== ABI_32
))
11671 mips_add_cfa_restore (mips_subword (reg
, true));
11672 mips_add_cfa_restore (mips_subword (reg
, false));
11675 mips_add_cfa_restore (reg
);
11677 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11678 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11679 /* The CFA is currently defined in terms of the register whose
11680 value we have just restored. Redefine the CFA in terms of
11681 the stack pointer. */
11682 mips_epilogue_set_cfa (stack_pointer_rtx
,
11683 mips_epilogue
.cfa_restore_sp_offset
);
11686 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11687 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11688 BASE, if not the stack pointer, is available as a temporary. */
11691 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11693 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11696 mips_frame_barrier ();
11697 if (offset
== const0_rtx
)
11699 emit_move_insn (stack_pointer_rtx
, base
);
11700 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11702 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11704 emit_insn (gen_add3_insn (base
, base
, offset
));
11705 mips_epilogue_set_cfa (base
, new_frame_size
);
11706 emit_move_insn (stack_pointer_rtx
, base
);
11710 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11711 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11715 /* Emit any instructions needed before a return. */
11718 mips_expand_before_return (void)
11720 /* When using a call-clobbered gp, we start out with unified call
11721 insns that include instructions to restore the gp. We then split
11722 these unified calls after reload. These split calls explicitly
11723 clobber gp, so there is no need to define
11724 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11726 For consistency, we should also insert an explicit clobber of $28
11727 before return insns, so that the post-reload optimizers know that
11728 the register is not live on exit. */
11729 if (TARGET_CALL_CLOBBERED_GP
)
11730 emit_clobber (pic_offset_table_rtx
);
11733 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11737 mips_expand_epilogue (bool sibcall_p
)
11739 const struct mips_frame_info
*frame
;
11740 HOST_WIDE_INT step1
, step2
;
11743 bool use_jraddiusp_p
= false;
11745 if (!sibcall_p
&& mips_can_use_return_insn ())
11747 emit_jump_insn (gen_return ());
11751 /* In MIPS16 mode, if the return value should go into a floating-point
11752 register, we need to call a helper routine to copy it over. */
11753 if (mips16_cfun_returns_in_fpr_p ())
11754 mips16_copy_fpr_return_value ();
11756 /* Split the frame into two. STEP1 is the amount of stack we should
11757 deallocate before restoring the registers. STEP2 is the amount we
11758 should deallocate afterwards.
11760 Start off by assuming that no registers need to be restored. */
11761 frame
= &cfun
->machine
->frame
;
11762 step1
= frame
->total_size
;
11765 /* Work out which register holds the frame address. */
11766 if (!frame_pointer_needed
)
11767 base
= stack_pointer_rtx
;
11770 base
= hard_frame_pointer_rtx
;
11771 step1
-= frame
->hard_frame_pointer_offset
;
11773 mips_epilogue
.cfa_reg
= base
;
11774 mips_epilogue
.cfa_offset
= step1
;
11775 mips_epilogue
.cfa_restores
= NULL_RTX
;
11777 /* If we need to restore registers, deallocate as much stack as
11778 possible in the second step without going out of range. */
11779 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11780 || frame
->num_cop0_regs
> 0)
11782 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11786 /* Get an rtx for STEP1 that we can add to BASE. */
11787 adjust
= GEN_INT (step1
);
11788 if (!SMALL_OPERAND (step1
))
11790 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11791 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11793 mips_deallocate_stack (base
, adjust
, step2
);
11795 /* If we're using addressing macros, $gp is implicitly used by all
11796 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11798 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11799 emit_insn (gen_blockage ());
11801 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11802 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11804 unsigned int regno
, mask
;
11805 HOST_WIDE_INT offset
;
11808 /* Generate the restore instruction. */
11809 mask
= frame
->mask
;
11810 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11812 /* Restore any other registers manually. */
11813 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11814 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11816 offset
-= UNITS_PER_WORD
;
11817 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11820 /* Restore the remaining registers and deallocate the final bit
11822 mips_frame_barrier ();
11823 emit_insn (restore
);
11824 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11828 /* Restore the registers. */
11829 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11830 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11833 if (cfun
->machine
->interrupt_handler_p
)
11835 HOST_WIDE_INT offset
;
11838 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11839 if (!cfun
->machine
->keep_interrupts_masked_p
)
11841 /* Restore the original EPC. */
11842 mem
= gen_frame_mem (word_mode
,
11843 plus_constant (Pmode
, stack_pointer_rtx
,
11845 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11846 offset
-= UNITS_PER_WORD
;
11848 /* Move to COP0 EPC. */
11849 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11850 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11853 /* Restore the original Status. */
11854 mem
= gen_frame_mem (word_mode
,
11855 plus_constant (Pmode
, stack_pointer_rtx
,
11857 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11858 offset
-= UNITS_PER_WORD
;
11860 /* If we don't use shadow register set, we need to update SP. */
11861 if (!cfun
->machine
->use_shadow_register_set_p
)
11862 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11864 /* The choice of position is somewhat arbitrary in this case. */
11865 mips_epilogue_emit_cfa_restores ();
11867 /* Move to COP0 Status. */
11868 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11869 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11871 else if (TARGET_MICROMIPS
11872 && !crtl
->calls_eh_return
11875 && mips_unsigned_immediate_p (step2
, 5, 2))
11876 use_jraddiusp_p
= true;
11878 /* Deallocate the final bit of the frame. */
11879 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11882 if (!use_jraddiusp_p
)
11883 gcc_assert (!mips_epilogue
.cfa_restores
);
11885 /* Add in the __builtin_eh_return stack adjustment. We need to
11886 use a temporary in MIPS16 code. */
11887 if (crtl
->calls_eh_return
)
11891 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11892 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11893 MIPS_EPILOGUE_TEMP (Pmode
),
11894 EH_RETURN_STACKADJ_RTX
));
11895 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11898 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11900 EH_RETURN_STACKADJ_RTX
));
11905 mips_expand_before_return ();
11906 if (cfun
->machine
->interrupt_handler_p
)
11908 /* Interrupt handlers generate eret or deret. */
11909 if (cfun
->machine
->use_debug_exception_return_p
)
11910 emit_jump_insn (gen_mips_deret ());
11912 emit_jump_insn (gen_mips_eret ());
11918 /* When generating MIPS16 code, the normal
11919 mips_for_each_saved_gpr_and_fpr path will restore the return
11920 address into $7 rather than $31. */
11922 && !GENERATE_MIPS16E_SAVE_RESTORE
11923 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11925 /* simple_returns cannot rely on values that are only available
11926 on paths through the epilogue (because return paths that do
11927 not pass through the epilogue may nevertheless reuse a
11928 simple_return that occurs at the end of the epilogue).
11929 Use a normal return here instead. */
11930 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11931 pat
= gen_return_internal (reg
);
11933 else if (use_jraddiusp_p
)
11934 pat
= gen_jraddiusp (GEN_INT (step2
));
11937 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11938 pat
= gen_simple_return_internal (reg
);
11940 emit_jump_insn (pat
);
11941 if (use_jraddiusp_p
)
11942 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11946 /* Search from the beginning to the first use of K0 or K1. */
11947 if (cfun
->machine
->interrupt_handler_p
11948 && !cfun
->machine
->keep_interrupts_masked_p
)
11950 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11952 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
11954 gcc_assert (insn
!= NULL_RTX
);
11955 /* Insert disable interrupts before the first use of K0 or K1. */
11956 emit_insn_before (gen_mips_di (), insn
);
11957 emit_insn_before (gen_mips_ehb (), insn
);
11961 /* Return nonzero if this function is known to have a null epilogue.
11962 This allows the optimizer to omit jumps to jumps if no stack
11966 mips_can_use_return_insn (void)
11968 /* Interrupt handlers need to go through the epilogue. */
11969 if (cfun
->machine
->interrupt_handler_p
)
11972 if (!reload_completed
)
11978 /* In MIPS16 mode, a function that returns a floating-point value
11979 needs to arrange to copy the return value into the floating-point
11981 if (mips16_cfun_returns_in_fpr_p ())
11984 return cfun
->machine
->frame
.total_size
== 0;
11987 /* Return true if register REGNO can store a value of mode MODE.
11988 The result of this function is cached in mips_hard_regno_mode_ok. */
11991 mips_hard_regno_mode_ok_p (unsigned int regno
, machine_mode mode
)
11994 enum mode_class mclass
;
11996 if (mode
== CCV2mode
)
11997 return (ISA_HAS_8CC
11998 && ST_REG_P (regno
)
11999 && (regno
- ST_REG_FIRST
) % 2 == 0);
12001 if (mode
== CCV4mode
)
12002 return (ISA_HAS_8CC
12003 && ST_REG_P (regno
)
12004 && (regno
- ST_REG_FIRST
) % 4 == 0);
12006 if (mode
== CCmode
)
12007 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
12009 size
= GET_MODE_SIZE (mode
);
12010 mclass
= GET_MODE_CLASS (mode
);
12012 if (GP_REG_P (regno
) && mode
!= CCFmode
)
12013 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
12015 if (FP_REG_P (regno
)
12016 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
12017 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
12019 /* Deny use of odd-numbered registers for 32-bit data for
12020 the o32 FP64A ABI. */
12021 if (TARGET_O32_FP64A_ABI
&& size
<= 4 && (regno
& 1) != 0)
12024 /* The FPXX ABI requires double-precision values to be placed in
12025 even-numbered registers. Disallow odd-numbered registers with
12026 CCFmode because CCFmode double-precision compares will write a
12027 64-bit value to a register. */
12028 if (mode
== CCFmode
)
12029 return !(TARGET_FLOATXX
&& (regno
& 1) != 0);
12031 /* Allow 64-bit vector modes for Loongson-2E/2F. */
12032 if (TARGET_LOONGSON_VECTORS
12033 && (mode
== V2SImode
12034 || mode
== V4HImode
12035 || mode
== V8QImode
12036 || mode
== DImode
))
12039 if (mclass
== MODE_FLOAT
12040 || mclass
== MODE_COMPLEX_FLOAT
12041 || mclass
== MODE_VECTOR_FLOAT
)
12042 return size
<= UNITS_PER_FPVALUE
;
12044 /* Allow integer modes that fit into a single register. We need
12045 to put integers into FPRs when using instructions like CVT
12046 and TRUNC. There's no point allowing sizes smaller than a word,
12047 because the FPU has no appropriate load/store instructions. */
12048 if (mclass
== MODE_INT
)
12049 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
12052 /* Don't allow vector modes in accumulators. */
12053 if (ACC_REG_P (regno
)
12054 && !VECTOR_MODE_P (mode
)
12055 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
12057 if (MD_REG_P (regno
))
12059 /* After a multiplication or division, clobbering HI makes
12060 the value of LO unpredictable, and vice versa. This means
12061 that, for all interesting cases, HI and LO are effectively
12064 We model this by requiring that any value that uses HI
12066 if (size
<= UNITS_PER_WORD
* 2)
12067 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
12071 /* DSP accumulators do not have the same restrictions as
12072 HI and LO, so we can treat them as normal doubleword
12074 if (size
<= UNITS_PER_WORD
)
12077 if (size
<= UNITS_PER_WORD
* 2
12078 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
12083 if (ALL_COP_REG_P (regno
))
12084 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
12086 if (regno
== GOT_VERSION_REGNUM
)
12087 return mode
== SImode
;
12092 /* Implement HARD_REGNO_NREGS. */
12095 mips_hard_regno_nregs (int regno
, machine_mode mode
)
12097 if (ST_REG_P (regno
))
12098 /* The size of FP status registers is always 4, because they only hold
12099 CCmode values, and CCmode is always considered to be 4 bytes wide. */
12100 return (GET_MODE_SIZE (mode
) + 3) / 4;
12102 if (FP_REG_P (regno
))
12103 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
12105 /* All other registers are word-sized. */
12106 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
12109 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
12110 in mips_hard_regno_nregs. */
12113 mips_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
12119 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
12120 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
12122 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
12123 size
= MIN (size
, 4);
12124 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
12126 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
12128 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
12129 size
= MIN (size
, UNITS_PER_FPREG
);
12130 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
12132 if (!hard_reg_set_empty_p (left
))
12133 size
= MIN (size
, UNITS_PER_WORD
);
12134 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
12137 /* Implement CANNOT_CHANGE_MODE_CLASS. */
12140 mips_cannot_change_mode_class (machine_mode from
,
12142 enum reg_class rclass
)
12144 /* Allow conversions between different Loongson integer vectors,
12145 and between those vectors and DImode. */
12146 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
12147 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
12150 /* Otherwise, there are several problems with changing the modes of
12151 values in floating-point registers:
12153 - When a multi-word value is stored in paired floating-point
12154 registers, the first register always holds the low word. We
12155 therefore can't allow FPRs to change between single-word and
12156 multi-word modes on big-endian targets.
12158 - GCC assumes that each word of a multiword register can be
12159 accessed individually using SUBREGs. This is not true for
12160 floating-point registers if they are bigger than a word.
12162 - Loading a 32-bit value into a 64-bit floating-point register
12163 will not sign-extend the value, despite what LOAD_EXTEND_OP
12164 says. We can't allow FPRs to change from SImode to a wider
12165 mode on 64-bit targets.
12167 - If the FPU has already interpreted a value in one format, we
12168 must not ask it to treat the value as having a different
12171 We therefore disallow all mode changes involving FPRs. */
12173 return reg_classes_intersect_p (FP_REGS
, rclass
);
12176 /* Implement target hook small_register_classes_for_mode_p. */
12179 mips_small_register_classes_for_mode_p (machine_mode mode
12182 return TARGET_MIPS16
;
12185 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
12188 mips_mode_ok_for_mov_fmt_p (machine_mode mode
)
12194 return TARGET_HARD_FLOAT
;
12197 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
12200 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
12207 /* Implement MODES_TIEABLE_P. */
12210 mips_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
12212 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
12213 prefer to put one of them in FPRs. */
12214 return (mode1
== mode2
12215 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
12216 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
12219 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12222 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
12224 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
12227 if (reg_class_subset_p (FP_REGS
, rclass
)
12228 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
12231 if (reg_class_subset_p (GR_REGS
, rclass
))
12234 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
12240 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
12241 Return a "canonical" class to represent it in later calculations. */
12244 mips_canonicalize_move_class (reg_class_t rclass
)
12246 /* All moves involving accumulator registers have the same cost. */
12247 if (reg_class_subset_p (rclass
, ACC_REGS
))
12250 /* Likewise promote subclasses of general registers to the most
12251 interesting containing class. */
12252 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
12254 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
12255 rclass
= GENERAL_REGS
;
12260 /* Return the cost of moving a value from a register of class FROM to a GPR.
12261 Return 0 for classes that are unions of other classes handled by this
12265 mips_move_to_gpr_cost (reg_class_t from
)
12271 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12275 /* MFLO and MFHI. */
12285 /* This choice of value is historical. */
12293 /* Return the cost of moving a value from a GPR to a register of class TO.
12294 Return 0 for classes that are unions of other classes handled by this
12298 mips_move_from_gpr_cost (reg_class_t to
)
12304 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12308 /* MTLO and MTHI. */
12318 /* This choice of value is historical. */
12326 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12327 maximum of the move costs for subclasses; regclass will work out
12328 the maximum for us. */
12331 mips_register_move_cost (machine_mode mode
,
12332 reg_class_t from
, reg_class_t to
)
12337 from
= mips_canonicalize_move_class (from
);
12338 to
= mips_canonicalize_move_class (to
);
12340 /* Handle moves that can be done without using general-purpose registers. */
12341 if (from
== FP_REGS
)
12343 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
12348 /* Handle cases in which only one class deviates from the ideal. */
12349 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
12351 return mips_move_from_gpr_cost (to
);
12353 return mips_move_to_gpr_cost (from
);
12355 /* Handles cases that require a GPR temporary. */
12356 cost1
= mips_move_to_gpr_cost (from
);
12359 cost2
= mips_move_from_gpr_cost (to
);
12361 return cost1
+ cost2
;
12367 /* Implement TARGET_REGISTER_PRIORITY. */
12370 mips_register_priority (int hard_regno
)
12372 /* Treat MIPS16 registers with higher priority than other regs. */
12374 && TEST_HARD_REG_BIT (reg_class_contents
[M16_REGS
], hard_regno
))
12379 /* Implement TARGET_MEMORY_MOVE_COST. */
12382 mips_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
12384 return (mips_cost
->memory_latency
12385 + memory_move_secondary_cost (mode
, rclass
, in
));
12388 /* Implement SECONDARY_MEMORY_NEEDED. */
12391 mips_secondary_memory_needed (enum reg_class class1
, enum reg_class class2
,
12394 /* Ignore spilled pseudos. */
12395 if (lra_in_progress
&& (class1
== NO_REGS
|| class2
== NO_REGS
))
12398 if (((class1
== FP_REGS
) != (class2
== FP_REGS
))
12399 && ((TARGET_FLOATXX
&& !ISA_HAS_MXHC1
)
12400 || TARGET_O32_FP64A_ABI
)
12401 && GET_MODE_SIZE (mode
) >= 8)
12407 /* Return the register class required for a secondary register when
12408 copying between one of the registers in RCLASS and value X, which
12409 has mode MODE. X is the source of the move if IN_P, otherwise it
12410 is the destination. Return NO_REGS if no secondary register is
12414 mips_secondary_reload_class (enum reg_class rclass
,
12415 machine_mode mode
, rtx x
, bool)
12419 /* If X is a constant that cannot be loaded into $25, it must be loaded
12420 into some other GPR. No other register class allows a direct move. */
12421 if (mips_dangerous_for_la25_p (x
))
12422 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
12424 regno
= true_regnum (x
);
12427 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12428 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12434 /* Copying from accumulator registers to anywhere other than a general
12435 register requires a temporary general register. */
12436 if (reg_class_subset_p (rclass
, ACC_REGS
))
12437 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12438 if (ACC_REG_P (regno
))
12439 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12441 if (reg_class_subset_p (rclass
, FP_REGS
))
12445 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)))
12446 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12447 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12450 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12451 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12454 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12455 /* We can force the constant to memory and use lwc1
12456 and ldc1. As above, we will use pairs of lwc1s if
12457 ldc1 is not supported. */
12460 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12461 /* In this case we can use mov.fmt. */
12464 /* Otherwise, we need to reload through an integer register. */
12467 if (FP_REG_P (regno
))
12468 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12473 /* Implement TARGET_MODE_REP_EXTENDED. */
12476 mips_mode_rep_extended (machine_mode mode
, machine_mode mode_rep
)
12478 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12479 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12480 return SIGN_EXTEND
;
12485 /* Implement TARGET_VALID_POINTER_MODE. */
12488 mips_valid_pointer_mode (machine_mode mode
)
12490 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12493 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12496 mips_vector_mode_supported_p (machine_mode mode
)
12501 return TARGET_PAIRED_SINGLE_FLOAT
;
12516 return TARGET_LOONGSON_VECTORS
;
12523 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12526 mips_scalar_mode_supported_p (machine_mode mode
)
12528 if (ALL_FIXED_POINT_MODE_P (mode
)
12529 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12532 return default_scalar_mode_supported_p (mode
);
12535 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12537 static machine_mode
12538 mips_preferred_simd_mode (machine_mode mode ATTRIBUTE_UNUSED
)
12540 if (TARGET_PAIRED_SINGLE_FLOAT
12546 /* Implement TARGET_INIT_LIBFUNCS. */
12549 mips_init_libfuncs (void)
12551 if (TARGET_FIX_VR4120
)
12553 /* Register the special divsi3 and modsi3 functions needed to work
12554 around VR4120 division errata. */
12555 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12556 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12559 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12561 /* Register the MIPS16 -mhard-float stubs. */
12562 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12563 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12564 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12565 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12567 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12568 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12569 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12570 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12571 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12572 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12573 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12575 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12576 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12577 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12579 if (TARGET_DOUBLE_FLOAT
)
12581 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12582 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12583 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12584 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12586 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12587 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12588 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12589 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12590 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12591 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12592 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12594 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12595 "__mips16_extendsfdf2");
12596 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12597 "__mips16_truncdfsf2");
12598 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12599 "__mips16_fix_truncdfsi");
12600 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12601 "__mips16_floatsidf");
12602 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12603 "__mips16_floatunsidf");
12607 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12608 on an external non-MIPS16 routine to implement __sync_synchronize.
12609 Similarly for the rest of the ll/sc libfuncs. */
12612 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12613 init_sync_libfuncs (UNITS_PER_WORD
);
12617 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12620 mips_process_load_label (rtx target
)
12622 rtx base
, gp
, intop
;
12623 HOST_WIDE_INT offset
;
12625 mips_multi_start ();
12629 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12630 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12634 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12635 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12639 gp
= pic_offset_table_rtx
;
12640 if (mips_cfun_has_cprestore_slot_p ())
12642 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12643 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12644 if (!SMALL_OPERAND (offset
))
12646 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12647 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12648 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12651 offset
= CONST_LOW_PART (offset
);
12653 intop
= GEN_INT (offset
);
12654 if (ISA_HAS_LOAD_DELAY
)
12655 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12657 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12659 if (ISA_HAS_LOAD_DELAY
)
12660 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12662 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12663 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12668 /* Return the number of instructions needed to load a label into $AT. */
12670 static unsigned int
12671 mips_load_label_num_insns (void)
12673 if (cfun
->machine
->load_label_num_insns
== 0)
12675 mips_process_load_label (pc_rtx
);
12676 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12678 return cfun
->machine
->load_label_num_insns
;
12681 /* Emit an asm sequence to start a noat block and load the address
12682 of a label into $1. */
12685 mips_output_load_label (rtx target
)
12687 mips_push_asm_switch (&mips_noat
);
12688 if (TARGET_EXPLICIT_RELOCS
)
12690 mips_process_load_label (target
);
12691 mips_multi_write ();
12695 if (Pmode
== DImode
)
12696 output_asm_insn ("dla\t%@,%0", &target
);
12698 output_asm_insn ("la\t%@,%0", &target
);
12702 /* Return the length of INSN. LENGTH is the initial length computed by
12703 attributes in the machine-description file. */
12706 mips_adjust_insn_length (rtx_insn
*insn
, int length
)
12708 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12709 of a PIC long-branch sequence. Substitute the correct value. */
12710 if (length
== MAX_PIC_BRANCH_LENGTH
12712 && INSN_CODE (insn
) >= 0
12713 && get_attr_type (insn
) == TYPE_BRANCH
)
12715 /* Add the branch-over instruction and its delay slot, if this
12716 is a conditional branch. */
12717 length
= simplejump_p (insn
) ? 0 : 8;
12719 /* Add the size of a load into $AT. */
12720 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12722 /* Add the length of an indirect jump, ignoring the delay slot. */
12723 length
+= TARGET_COMPRESSION
? 2 : 4;
12726 /* A unconditional jump has an unfilled delay slot if it is not part
12727 of a sequence. A conditional jump normally has a delay slot, but
12728 does not on MIPS16. */
12729 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12730 length
+= TARGET_MIPS16
? 2 : 4;
12732 /* See how many nops might be needed to avoid hardware hazards. */
12733 if (!cfun
->machine
->ignore_hazard_length_p
12735 && INSN_CODE (insn
) >= 0)
12736 switch (get_attr_hazard (insn
))
12742 length
+= NOP_INSN_LENGTH
;
12746 length
+= NOP_INSN_LENGTH
* 2;
12753 /* Return the assembly code for INSN, which has the operands given by
12754 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12755 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12756 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12757 version of BRANCH_IF_TRUE. */
12760 mips_output_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
12761 const char *branch_if_true
,
12762 const char *branch_if_false
)
12764 unsigned int length
;
12767 gcc_assert (LABEL_P (operands
[0]));
12769 length
= get_attr_length (insn
);
12772 /* Just a simple conditional branch. */
12773 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12774 return branch_if_true
;
12777 /* Generate a reversed branch around a direct jump. This fallback does
12778 not use branch-likely instructions. */
12779 mips_branch_likely
= false;
12780 rtx_code_label
*not_taken
= gen_label_rtx ();
12781 taken
= operands
[0];
12783 /* Generate the reversed branch to NOT_TAKEN. */
12784 operands
[0] = not_taken
;
12785 output_asm_insn (branch_if_false
, operands
);
12787 /* If INSN has a delay slot, we must provide delay slots for both the
12788 branch to NOT_TAKEN and the conditional jump. We must also ensure
12789 that INSN's delay slot is executed in the appropriate cases. */
12790 if (final_sequence
)
12792 /* This first delay slot will always be executed, so use INSN's
12793 delay slot if is not annulled. */
12794 if (!INSN_ANNULLED_BRANCH_P (insn
))
12796 final_scan_insn (final_sequence
->insn (1),
12797 asm_out_file
, optimize
, 1, NULL
);
12798 final_sequence
->insn (1)->set_deleted ();
12801 output_asm_insn ("nop", 0);
12802 fprintf (asm_out_file
, "\n");
12805 /* Output the unconditional branch to TAKEN. */
12806 if (TARGET_ABSOLUTE_JUMPS
)
12807 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12810 mips_output_load_label (taken
);
12811 output_asm_insn ("jr\t%@%]%/", 0);
12814 /* Now deal with its delay slot; see above. */
12815 if (final_sequence
)
12817 /* This delay slot will only be executed if the branch is taken.
12818 Use INSN's delay slot if is annulled. */
12819 if (INSN_ANNULLED_BRANCH_P (insn
))
12821 final_scan_insn (final_sequence
->insn (1),
12822 asm_out_file
, optimize
, 1, NULL
);
12823 final_sequence
->insn (1)->set_deleted ();
12826 output_asm_insn ("nop", 0);
12827 fprintf (asm_out_file
, "\n");
12830 /* Output NOT_TAKEN. */
12831 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12832 CODE_LABEL_NUMBER (not_taken
));
12836 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12837 if some ordering condition is true. The condition is given by
12838 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12839 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12840 its second is always zero. */
12843 mips_output_order_conditional_branch (rtx_insn
*insn
, rtx
*operands
, bool inverted_p
)
12845 const char *branch
[2];
12847 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12848 Make BRANCH[0] branch on the inverse condition. */
12849 switch (GET_CODE (operands
[1]))
12851 /* These cases are equivalent to comparisons against zero. */
12853 inverted_p
= !inverted_p
;
12854 /* Fall through. */
12856 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12857 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12860 /* These cases are always true or always false. */
12862 inverted_p
= !inverted_p
;
12863 /* Fall through. */
12865 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12866 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12870 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12871 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12874 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12877 /* Start a block of code that needs access to the LL, SC and SYNC
12881 mips_start_ll_sc_sync_block (void)
12883 if (!ISA_HAS_LL_SC
)
12885 output_asm_insn (".set\tpush", 0);
12887 output_asm_insn (".set\tmips3", 0);
12889 output_asm_insn (".set\tmips2", 0);
12893 /* End a block started by mips_start_ll_sc_sync_block. */
12896 mips_end_ll_sc_sync_block (void)
12898 if (!ISA_HAS_LL_SC
)
12899 output_asm_insn (".set\tpop", 0);
12902 /* Output and/or return the asm template for a sync instruction. */
12905 mips_output_sync (void)
12907 mips_start_ll_sc_sync_block ();
12908 output_asm_insn ("sync", 0);
12909 mips_end_ll_sc_sync_block ();
12913 /* Return the asm template associated with sync_insn1 value TYPE.
12914 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12916 static const char *
12917 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12921 case SYNC_INSN1_MOVE
:
12922 return "move\t%0,%z2";
12923 case SYNC_INSN1_LI
:
12924 return "li\t%0,%2";
12925 case SYNC_INSN1_ADDU
:
12926 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12927 case SYNC_INSN1_ADDIU
:
12928 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12929 case SYNC_INSN1_SUBU
:
12930 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12931 case SYNC_INSN1_AND
:
12932 return "and\t%0,%1,%z2";
12933 case SYNC_INSN1_ANDI
:
12934 return "andi\t%0,%1,%2";
12935 case SYNC_INSN1_OR
:
12936 return "or\t%0,%1,%z2";
12937 case SYNC_INSN1_ORI
:
12938 return "ori\t%0,%1,%2";
12939 case SYNC_INSN1_XOR
:
12940 return "xor\t%0,%1,%z2";
12941 case SYNC_INSN1_XORI
:
12942 return "xori\t%0,%1,%2";
12944 gcc_unreachable ();
12947 /* Return the asm template associated with sync_insn2 value TYPE. */
12949 static const char *
12950 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12954 case SYNC_INSN2_NOP
:
12955 gcc_unreachable ();
12956 case SYNC_INSN2_AND
:
12957 return "and\t%0,%1,%z2";
12958 case SYNC_INSN2_XOR
:
12959 return "xor\t%0,%1,%z2";
12960 case SYNC_INSN2_NOT
:
12961 return "nor\t%0,%1,%.";
12963 gcc_unreachable ();
12966 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12967 the value of the one of the sync_* attributes. Return the operand
12968 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12969 have the associated attribute. */
12972 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12975 default_value
= operands
[index
- 1];
12976 return default_value
;
12979 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12980 sequence for it. */
12983 mips_process_sync_loop (rtx_insn
*insn
, rtx
*operands
)
12985 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12986 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12987 unsigned int tmp3_insn
;
12988 enum attr_sync_insn1 insn1
;
12989 enum attr_sync_insn2 insn2
;
12992 enum memmodel model
;
12994 /* Read an operand from the sync_WHAT attribute and store it in
12995 variable WHAT. DEFAULT is the default value if no attribute
12997 #define READ_OPERAND(WHAT, DEFAULT) \
12998 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
13001 /* Read the memory. */
13002 READ_OPERAND (mem
, 0);
13004 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
13006 /* Read the other attributes. */
13007 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
13008 READ_OPERAND (oldval
, at
);
13009 READ_OPERAND (cmp
, 0);
13010 READ_OPERAND (newval
, at
);
13011 READ_OPERAND (inclusive_mask
, 0);
13012 READ_OPERAND (exclusive_mask
, 0);
13013 READ_OPERAND (required_oldval
, 0);
13014 READ_OPERAND (insn1_op2
, 0);
13015 insn1
= get_attr_sync_insn1 (insn
);
13016 insn2
= get_attr_sync_insn2 (insn
);
13018 /* Don't bother setting CMP result that is never used. */
13019 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
13022 memmodel_attr
= get_attr_sync_memmodel (insn
);
13023 switch (memmodel_attr
)
13026 model
= MEMMODEL_ACQ_REL
;
13029 model
= MEMMODEL_ACQUIRE
;
13032 model
= memmodel_from_int (INTVAL (operands
[memmodel_attr
]));
13035 mips_multi_start ();
13037 /* Output the release side of the memory barrier. */
13038 if (need_atomic_barrier_p (model
, true))
13040 if (required_oldval
== 0 && TARGET_OCTEON
)
13042 /* Octeon doesn't reorder reads, so a full barrier can be
13043 created by using SYNCW to order writes combined with the
13044 write from the following SC. When the SC successfully
13045 completes, we know that all preceding writes are also
13046 committed to the coherent memory system. It is possible
13047 for a single SYNCW to fail, but a pair of them will never
13048 fail, so we use two. */
13049 mips_multi_add_insn ("syncw", NULL
);
13050 mips_multi_add_insn ("syncw", NULL
);
13053 mips_multi_add_insn ("sync", NULL
);
13056 /* Output the branch-back label. */
13057 mips_multi_add_label ("1:");
13059 /* OLDVAL = *MEM. */
13060 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
13061 oldval
, mem
, NULL
);
13063 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
13064 if (required_oldval
)
13066 if (inclusive_mask
== 0)
13070 gcc_assert (oldval
!= at
);
13071 mips_multi_add_insn ("and\t%0,%1,%2",
13072 at
, oldval
, inclusive_mask
, NULL
);
13075 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
13077 /* CMP = 0 [delay slot]. */
13079 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
13082 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
13083 if (exclusive_mask
== 0)
13087 gcc_assert (oldval
!= at
);
13088 mips_multi_add_insn ("and\t%0,%1,%z2",
13089 at
, oldval
, exclusive_mask
, NULL
);
13093 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
13095 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
13096 at least one instruction in that case. */
13097 if (insn1
== SYNC_INSN1_MOVE
13098 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
13102 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
13103 newval
, oldval
, insn1_op2
, NULL
);
13107 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
13108 if (insn2
== SYNC_INSN2_NOP
)
13112 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
13113 newval
, tmp2
, inclusive_mask
, NULL
);
13116 tmp3_insn
= mips_multi_last_index ();
13118 /* $AT = $TMP1 | $TMP3. */
13119 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
13121 mips_multi_set_operand (tmp3_insn
, 0, at
);
13126 gcc_assert (tmp1
!= tmp3
);
13127 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
13130 /* if (!commit (*MEM = $AT)) goto 1.
13132 This will sometimes be a delayed branch; see the write code below
13134 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
13136 /* When using branch likely (-mfix-r10000), the delay slot instruction
13137 will be annulled on false. The normal delay slot instructions
13138 calculate the overall result of the atomic operation and must not
13139 be annulled. To ensure this behaviour unconditionally use a NOP
13140 in the delay slot for the branch likely case. */
13142 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at
, NULL
);
13144 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
13145 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
13147 mips_multi_copy_insn (tmp3_insn
);
13148 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
13150 else if (!(required_oldval
&& cmp
) && !mips_branch_likely
)
13151 mips_multi_add_insn ("nop", NULL
);
13153 /* CMP = 1 -- either standalone or in a delay slot. */
13154 if (required_oldval
&& cmp
)
13155 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
13157 /* Output the acquire side of the memory barrier. */
13158 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
13159 mips_multi_add_insn ("sync", NULL
);
13161 /* Output the exit label, if needed. */
13162 if (required_oldval
)
13163 mips_multi_add_label ("2:");
13165 #undef READ_OPERAND
13168 /* Output and/or return the asm template for sync loop INSN, which has
13169 the operands given by OPERANDS. */
13172 mips_output_sync_loop (rtx_insn
*insn
, rtx
*operands
)
13174 /* Use branch-likely instructions to work around the LL/SC R10000
13176 mips_branch_likely
= TARGET_FIX_R10000
;
13178 mips_process_sync_loop (insn
, operands
);
13180 mips_push_asm_switch (&mips_noreorder
);
13181 mips_push_asm_switch (&mips_nomacro
);
13182 mips_push_asm_switch (&mips_noat
);
13183 mips_start_ll_sc_sync_block ();
13185 mips_multi_write ();
13187 mips_end_ll_sc_sync_block ();
13188 mips_pop_asm_switch (&mips_noat
);
13189 mips_pop_asm_switch (&mips_nomacro
);
13190 mips_pop_asm_switch (&mips_noreorder
);
13195 /* Return the number of individual instructions in sync loop INSN,
13196 which has the operands given by OPERANDS. */
13199 mips_sync_loop_insns (rtx_insn
*insn
, rtx
*operands
)
13201 /* Use branch-likely instructions to work around the LL/SC R10000
13203 mips_branch_likely
= TARGET_FIX_R10000
;
13204 mips_process_sync_loop (insn
, operands
);
13205 return mips_multi_num_insns
;
13208 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
13209 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
13211 When working around R4000 and R4400 errata, we need to make sure that
13212 the division is not immediately followed by a shift[1][2]. We also
13213 need to stop the division from being put into a branch delay slot[3].
13214 The easiest way to avoid both problems is to add a nop after the
13215 division. When a divide-by-zero check is needed, this nop can be
13216 used to fill the branch delay slot.
13218 [1] If a double-word or a variable shift executes immediately
13219 after starting an integer division, the shift may give an
13220 incorrect result. See quotations of errata #16 and #28 from
13221 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13222 in mips.md for details.
13224 [2] A similar bug to [1] exists for all revisions of the
13225 R4000 and the R4400 when run in an MC configuration.
13226 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
13228 "19. In this following sequence:
13230 ddiv (or ddivu or div or divu)
13231 dsll32 (or dsrl32, dsra32)
13233 if an MPT stall occurs, while the divide is slipping the cpu
13234 pipeline, then the following double shift would end up with an
13237 Workaround: The compiler needs to avoid generating any
13238 sequence with divide followed by extended double shift."
13240 This erratum is also present in "MIPS R4400MC Errata, Processor
13241 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
13242 & 3.0" as errata #10 and #4, respectively.
13244 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13245 (also valid for MIPS R4000MC processors):
13247 "52. R4000SC: This bug does not apply for the R4000PC.
13249 There are two flavors of this bug:
13251 1) If the instruction just after divide takes an RF exception
13252 (tlb-refill, tlb-invalid) and gets an instruction cache
13253 miss (both primary and secondary) and the line which is
13254 currently in secondary cache at this index had the first
13255 data word, where the bits 5..2 are set, then R4000 would
13256 get a wrong result for the div.
13261 ------------------- # end-of page. -tlb-refill
13266 ------------------- # end-of page. -tlb-invalid
13269 2) If the divide is in the taken branch delay slot, where the
13270 target takes RF exception and gets an I-cache miss for the
13271 exception vector or where I-cache miss occurs for the
13272 target address, under the above mentioned scenarios, the
13273 div would get wrong results.
13276 j r2 # to next page mapped or unmapped
13277 div r8,r9 # this bug would be there as long
13278 # as there is an ICache miss and
13279 nop # the "data pattern" is present
13282 beq r0, r0, NextPage # to Next page
13286 This bug is present for div, divu, ddiv, and ddivu
13289 Workaround: For item 1), OS could make sure that the next page
13290 after the divide instruction is also mapped. For item 2), the
13291 compiler could make sure that the divide instruction is not in
13292 the branch delay slot."
13294 These processors have PRId values of 0x00004220 and 0x00004300 for
13295 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
13298 mips_output_division (const char *division
, rtx
*operands
)
13303 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
13305 output_asm_insn (s
, operands
);
13308 if (TARGET_CHECK_ZERO_DIV
)
13312 output_asm_insn (s
, operands
);
13313 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
13315 else if (GENERATE_DIVIDE_TRAPS
)
13317 /* Avoid long replay penalty on load miss by putting the trap before
13320 output_asm_insn ("teq\t%2,%.,7", operands
);
13323 output_asm_insn (s
, operands
);
13324 s
= "teq\t%2,%.,7";
13329 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
13330 output_asm_insn (s
, operands
);
13331 s
= "break\t7%)\n1:";
13337 /* Return true if destination of IN_INSN is used as add source in
13338 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13339 madd.s dst, x, y, z
13340 madd.s a, dst, b, c */
13343 mips_fmadd_bypass (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13345 int dst_reg
, src_reg
;
13347 gcc_assert (get_attr_type (in_insn
) == TYPE_FMADD
);
13348 gcc_assert (get_attr_type (out_insn
) == TYPE_FMADD
);
13350 extract_insn (in_insn
);
13351 dst_reg
= REG_P (recog_data
.operand
[0]);
13353 extract_insn (out_insn
);
13354 src_reg
= REG_P (recog_data
.operand
[1]);
13356 if (dst_reg
== src_reg
)
13362 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13363 instruction and if OUT_INSN assigns to the accumulator operand. */
13366 mips_linked_madd_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13368 enum attr_accum_in accum_in
;
13369 int accum_in_opnum
;
13372 if (recog_memoized (in_insn
) < 0)
13375 accum_in
= get_attr_accum_in (in_insn
);
13376 if (accum_in
== ACCUM_IN_NONE
)
13379 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
13381 extract_insn (in_insn
);
13382 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
13383 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
13385 return reg_set_p (accum_in_op
, out_insn
);
13388 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13389 data rather than the address. We need this because the cprestore
13390 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13391 which causes the default routine to abort. We just return false
13395 mips_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13397 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
13400 return !store_data_bypass_p (out_insn
, in_insn
);
13404 /* Variables and flags used in scheduler hooks when tuning for
13408 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13411 /* If true, then next ALU1/2 instruction will go to ALU1. */
13414 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13417 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13418 int alu1_core_unit_code
;
13419 int alu2_core_unit_code
;
13420 int falu1_core_unit_code
;
13421 int falu2_core_unit_code
;
13423 /* True if current cycle has a multi instruction.
13424 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13425 bool cycle_has_multi_p
;
13427 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13428 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13430 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13431 instruction to go ALU1. */
13432 rtx_insn
*alu1_turn_enabled_insn
;
13433 rtx_insn
*alu2_turn_enabled_insn
;
13434 rtx_insn
*falu1_turn_enabled_insn
;
13435 rtx_insn
*falu2_turn_enabled_insn
;
13438 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13439 dependencies have no cost, except on the 20Kc where output-dependence
13440 is treated like input-dependence. */
13443 mips_adjust_cost (rtx_insn
*insn ATTRIBUTE_UNUSED
, rtx link
,
13444 rtx_insn
*dep ATTRIBUTE_UNUSED
, int cost
)
13446 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13449 if (REG_NOTE_KIND (link
) != 0)
13454 /* Return the number of instructions that can be issued per cycle. */
13457 mips_issue_rate (void)
13461 case PROCESSOR_74KC
:
13462 case PROCESSOR_74KF2_1
:
13463 case PROCESSOR_74KF1_1
:
13464 case PROCESSOR_74KF3_2
:
13465 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13466 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13467 but in reality only a maximum of 3 insns can be issued as
13468 floating-point loads and stores also require a slot in the
13470 case PROCESSOR_R10000
:
13471 /* All R10K Processors are quad-issue (being the first MIPS
13472 processors to support this feature). */
13475 case PROCESSOR_20KC
:
13476 case PROCESSOR_R4130
:
13477 case PROCESSOR_R5400
:
13478 case PROCESSOR_R5500
:
13479 case PROCESSOR_R5900
:
13480 case PROCESSOR_R7000
:
13481 case PROCESSOR_R9000
:
13482 case PROCESSOR_OCTEON
:
13483 case PROCESSOR_OCTEON2
:
13484 case PROCESSOR_OCTEON3
:
13487 case PROCESSOR_SB1
:
13488 case PROCESSOR_SB1A
:
13489 /* This is actually 4, but we get better performance if we claim 3.
13490 This is partly because of unwanted speculative code motion with the
13491 larger number, and partly because in most common cases we can't
13492 reach the theoretical max of 4. */
13495 case PROCESSOR_LOONGSON_2E
:
13496 case PROCESSOR_LOONGSON_2F
:
13497 case PROCESSOR_LOONGSON_3A
:
13498 case PROCESSOR_P5600
:
13501 case PROCESSOR_XLP
:
13502 return (reload_completed
? 4 : 3);
13509 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13512 mips_ls2_init_dfa_post_cycle_insn (void)
13515 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13516 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13520 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13521 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13525 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13526 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13530 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13531 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13534 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13535 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13536 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13537 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13540 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13541 Init data used in mips_dfa_post_advance_cycle. */
13544 mips_init_dfa_post_cycle_insn (void)
13546 if (TUNE_LOONGSON_2EF
)
13547 mips_ls2_init_dfa_post_cycle_insn ();
13550 /* Initialize STATE when scheduling for Loongson 2E/2F.
13551 Support round-robin dispatch scheme by enabling only one of
13552 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13556 mips_ls2_dfa_post_advance_cycle (state_t state
)
13558 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13560 /* Though there are no non-pipelined ALU1 insns,
13561 we can get an instruction of type 'multi' before reload. */
13562 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13563 mips_ls2
.alu1_turn_p
= false;
13566 mips_ls2
.cycle_has_multi_p
= false;
13568 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13569 /* We have a non-pipelined alu instruction in the core,
13570 adjust round-robin counter. */
13571 mips_ls2
.alu1_turn_p
= true;
13573 if (mips_ls2
.alu1_turn_p
)
13575 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13576 gcc_unreachable ();
13580 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13581 gcc_unreachable ();
13584 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13586 /* There are no non-pipelined FALU1 insns. */
13587 gcc_unreachable ();
13588 mips_ls2
.falu1_turn_p
= false;
13591 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13592 /* We have a non-pipelined falu instruction in the core,
13593 adjust round-robin counter. */
13594 mips_ls2
.falu1_turn_p
= true;
13596 if (mips_ls2
.falu1_turn_p
)
13598 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13599 gcc_unreachable ();
13603 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13604 gcc_unreachable ();
13608 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13609 This hook is being called at the start of each cycle. */
13612 mips_dfa_post_advance_cycle (void)
13614 if (TUNE_LOONGSON_2EF
)
13615 mips_ls2_dfa_post_advance_cycle (curr_state
);
13618 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13619 be as wide as the scheduling freedom in the DFA. */
13622 mips_multipass_dfa_lookahead (void)
13624 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13628 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13640 /* Remove the instruction at index LOWER from ready queue READY and
13641 reinsert it in front of the instruction at index HIGHER. LOWER must
13645 mips_promote_ready (rtx_insn
**ready
, int lower
, int higher
)
13647 rtx_insn
*new_head
;
13650 new_head
= ready
[lower
];
13651 for (i
= lower
; i
< higher
; i
++)
13652 ready
[i
] = ready
[i
+ 1];
13653 ready
[i
] = new_head
;
13656 /* If the priority of the instruction at POS2 in the ready queue READY
13657 is within LIMIT units of that of the instruction at POS1, swap the
13658 instructions if POS2 is not already less than POS1. */
13661 mips_maybe_swap_ready (rtx_insn
**ready
, int pos1
, int pos2
, int limit
)
13664 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13668 temp
= ready
[pos1
];
13669 ready
[pos1
] = ready
[pos2
];
13670 ready
[pos2
] = temp
;
13674 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13675 that may clobber hi or lo. */
13676 static rtx_insn
*mips_macc_chains_last_hilo
;
13678 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13679 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13682 mips_macc_chains_record (rtx_insn
*insn
)
13684 if (get_attr_may_clobber_hilo (insn
))
13685 mips_macc_chains_last_hilo
= insn
;
13688 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13689 has NREADY elements, looking for a multiply-add or multiply-subtract
13690 instruction that is cumulative with mips_macc_chains_last_hilo.
13691 If there is one, promote it ahead of anything else that might
13692 clobber hi or lo. */
13695 mips_macc_chains_reorder (rtx_insn
**ready
, int nready
)
13699 if (mips_macc_chains_last_hilo
!= 0)
13700 for (i
= nready
- 1; i
>= 0; i
--)
13701 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13703 for (j
= nready
- 1; j
> i
; j
--)
13704 if (recog_memoized (ready
[j
]) >= 0
13705 && get_attr_may_clobber_hilo (ready
[j
]))
13707 mips_promote_ready (ready
, i
, j
);
13714 /* The last instruction to be scheduled. */
13715 static rtx_insn
*vr4130_last_insn
;
13717 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13718 points to an rtx that is initially an instruction. Nullify the rtx
13719 if the instruction uses the value of register X. */
13722 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13727 insn_ptr
= (rtx
*) data
;
13730 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13734 /* Return true if there is true register dependence between vr4130_last_insn
13738 vr4130_true_reg_dependence_p (rtx insn
)
13740 note_stores (PATTERN (vr4130_last_insn
),
13741 vr4130_true_reg_dependence_p_1
, &insn
);
13745 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13746 the ready queue and that INSN2 is the instruction after it, return
13747 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13748 in which INSN1 and INSN2 can probably issue in parallel, but for
13749 which (INSN2, INSN1) should be less sensitive to instruction
13750 alignment than (INSN1, INSN2). See 4130.md for more details. */
13753 vr4130_swap_insns_p (rtx_insn
*insn1
, rtx_insn
*insn2
)
13755 sd_iterator_def sd_it
;
13758 /* Check for the following case:
13760 1) there is some other instruction X with an anti dependence on INSN1;
13761 2) X has a higher priority than INSN2; and
13762 3) X is an arithmetic instruction (and thus has no unit restrictions).
13764 If INSN1 is the last instruction blocking X, it would better to
13765 choose (INSN1, X) over (INSN2, INSN1). */
13766 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13767 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13768 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13769 && recog_memoized (DEP_CON (dep
)) >= 0
13770 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13773 if (vr4130_last_insn
!= 0
13774 && recog_memoized (insn1
) >= 0
13775 && recog_memoized (insn2
) >= 0)
13777 /* See whether INSN1 and INSN2 use different execution units,
13778 or if they are both ALU-type instructions. If so, they can
13779 probably execute in parallel. */
13780 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13781 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13782 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13784 /* If only one of the instructions has a dependence on
13785 vr4130_last_insn, prefer to schedule the other one first. */
13786 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13787 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13788 if (dep1_p
!= dep2_p
)
13791 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13792 is not an ALU-type instruction and if INSN1 uses the same
13793 execution unit. (Note that if this condition holds, we already
13794 know that INSN2 uses a different execution unit.) */
13795 if (class1
!= VR4130_CLASS_ALU
13796 && recog_memoized (vr4130_last_insn
) >= 0
13797 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13804 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13805 queue with at least two instructions. Swap the first two if
13806 vr4130_swap_insns_p says that it could be worthwhile. */
13809 vr4130_reorder (rtx_insn
**ready
, int nready
)
13811 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13812 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13815 /* Record whether last 74k AGEN instruction was a load or store. */
13816 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13818 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13819 resets to TYPE_UNKNOWN state. */
13822 mips_74k_agen_init (rtx_insn
*insn
)
13824 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13825 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13828 enum attr_type type
= get_attr_type (insn
);
13829 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13830 mips_last_74k_agen_insn
= type
;
13834 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13835 loads to be grouped together, and multiple stores to be grouped
13836 together. Swap things around in the ready queue to make this happen. */
13839 mips_74k_agen_reorder (rtx_insn
**ready
, int nready
)
13842 int store_pos
, load_pos
;
13847 for (i
= nready
- 1; i
>= 0; i
--)
13849 rtx_insn
*insn
= ready
[i
];
13850 if (USEFUL_INSN_P (insn
))
13851 switch (get_attr_type (insn
))
13854 if (store_pos
== -1)
13859 if (load_pos
== -1)
13868 if (load_pos
== -1 || store_pos
== -1)
13871 switch (mips_last_74k_agen_insn
)
13874 /* Prefer to schedule loads since they have a higher latency. */
13876 /* Swap loads to the front of the queue. */
13877 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13880 /* Swap stores to the front of the queue. */
13881 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13888 /* Implement TARGET_SCHED_INIT. */
13891 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13892 int max_ready ATTRIBUTE_UNUSED
)
13894 mips_macc_chains_last_hilo
= 0;
13895 vr4130_last_insn
= 0;
13896 mips_74k_agen_init (NULL
);
13898 /* When scheduling for Loongson2, branch instructions go to ALU1,
13899 therefore basic block is most likely to start with round-robin counter
13900 pointed to ALU2. */
13901 mips_ls2
.alu1_turn_p
= false;
13902 mips_ls2
.falu1_turn_p
= true;
13905 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13908 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13909 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13911 if (!reload_completed
13912 && TUNE_MACC_CHAINS
13914 mips_macc_chains_reorder (ready
, *nreadyp
);
13916 if (reload_completed
13918 && !TARGET_VR4130_ALIGN
13920 vr4130_reorder (ready
, *nreadyp
);
13923 mips_74k_agen_reorder (ready
, *nreadyp
);
13926 /* Implement TARGET_SCHED_REORDER. */
13929 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13930 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13932 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13933 return mips_issue_rate ();
13936 /* Implement TARGET_SCHED_REORDER2. */
13939 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13940 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13942 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13943 return cached_can_issue_more
;
13946 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13949 mips_ls2_variable_issue (rtx_insn
*insn
)
13951 if (mips_ls2
.alu1_turn_p
)
13953 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13954 mips_ls2
.alu1_turn_p
= false;
13958 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13959 mips_ls2
.alu1_turn_p
= true;
13962 if (mips_ls2
.falu1_turn_p
)
13964 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13965 mips_ls2
.falu1_turn_p
= false;
13969 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13970 mips_ls2
.falu1_turn_p
= true;
13973 if (recog_memoized (insn
) >= 0)
13974 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13977 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13980 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13981 rtx_insn
*insn
, int more
)
13983 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13984 if (USEFUL_INSN_P (insn
))
13986 if (get_attr_type (insn
) != TYPE_GHOST
)
13988 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13989 mips_macc_chains_record (insn
);
13990 vr4130_last_insn
= insn
;
13992 mips_74k_agen_init (insn
);
13993 else if (TUNE_LOONGSON_2EF
)
13994 mips_ls2_variable_issue (insn
);
13997 /* Instructions of type 'multi' should all be split before
13998 the second scheduling pass. */
13999 gcc_assert (!reload_completed
14000 || recog_memoized (insn
) < 0
14001 || get_attr_type (insn
) != TYPE_MULTI
);
14003 cached_can_issue_more
= more
;
14007 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
14008 return the first operand of the associated PREF or PREFX insn. */
14011 mips_prefetch_cookie (rtx write
, rtx locality
)
14013 /* store_streamed / load_streamed. */
14014 if (INTVAL (locality
) <= 0)
14015 return GEN_INT (INTVAL (write
) + 4);
14017 /* store / load. */
14018 if (INTVAL (locality
) <= 2)
14021 /* store_retained / load_retained. */
14022 return GEN_INT (INTVAL (write
) + 6);
14025 /* Flags that indicate when a built-in function is available.
14027 BUILTIN_AVAIL_NON_MIPS16
14028 The function is available on the current target if !TARGET_MIPS16.
14030 BUILTIN_AVAIL_MIPS16
14031 The function is available on the current target if TARGET_MIPS16. */
14032 #define BUILTIN_AVAIL_NON_MIPS16 1
14033 #define BUILTIN_AVAIL_MIPS16 2
14035 /* Declare an availability predicate for built-in functions that
14036 require non-MIPS16 mode and also require COND to be true.
14037 NAME is the main part of the predicate's name. */
14038 #define AVAIL_NON_MIPS16(NAME, COND) \
14039 static unsigned int \
14040 mips_builtin_avail_##NAME (void) \
14042 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
14045 /* Declare an availability predicate for built-in functions that
14046 support both MIPS16 and non-MIPS16 code and also require COND
14047 to be true. NAME is the main part of the predicate's name. */
14048 #define AVAIL_ALL(NAME, COND) \
14049 static unsigned int \
14050 mips_builtin_avail_##NAME (void) \
14052 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
14055 /* This structure describes a single built-in function. */
14056 struct mips_builtin_description
{
14057 /* The code of the main .md file instruction. See mips_builtin_type
14058 for more information. */
14059 enum insn_code icode
;
14061 /* The floating-point comparison code to use with ICODE, if any. */
14062 enum mips_fp_condition cond
;
14064 /* The name of the built-in function. */
14067 /* Specifies how the function should be expanded. */
14068 enum mips_builtin_type builtin_type
;
14070 /* The function's prototype. */
14071 enum mips_function_type function_type
;
14073 /* Whether the function is available. */
14074 unsigned int (*avail
) (void);
14077 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
14078 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
14079 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
14080 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
14081 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
14082 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
14083 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
14084 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
14085 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
14086 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
14087 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
14089 /* Construct a mips_builtin_description from the given arguments.
14091 INSN is the name of the associated instruction pattern, without the
14092 leading CODE_FOR_mips_.
14094 CODE is the floating-point condition code associated with the
14095 function. It can be 'f' if the field is not applicable.
14097 NAME is the name of the function itself, without the leading
14100 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
14102 AVAIL is the name of the availability predicate, without the leading
14103 mips_builtin_avail_. */
14104 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
14105 FUNCTION_TYPE, AVAIL) \
14106 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
14107 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
14108 mips_builtin_avail_ ## AVAIL }
14110 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
14111 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
14112 are as for MIPS_BUILTIN. */
14113 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14114 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
14116 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
14117 are subject to mips_builtin_avail_<AVAIL>. */
14118 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
14119 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
14120 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
14121 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
14122 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
14124 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
14125 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
14126 while the any and all forms are subject to mips_builtin_avail_mips3d. */
14127 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
14128 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
14129 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
14131 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
14132 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
14134 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
14135 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
14137 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
14138 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
14141 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
14142 are subject to mips_builtin_avail_mips3d. */
14143 #define CMP_4S_BUILTINS(INSN, COND) \
14144 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
14145 MIPS_BUILTIN_CMP_ANY, \
14146 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
14147 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
14148 MIPS_BUILTIN_CMP_ALL, \
14149 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
14151 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
14152 instruction requires mips_builtin_avail_<AVAIL>. */
14153 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
14154 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
14155 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14157 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
14158 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14161 /* Define all the built-in functions related to C.cond.fmt condition COND. */
14162 #define CMP_BUILTINS(COND) \
14163 MOVTF_BUILTINS (c, COND, paired_single), \
14164 MOVTF_BUILTINS (cabs, COND, mips3d), \
14165 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
14166 CMP_PS_BUILTINS (c, COND, paired_single), \
14167 CMP_PS_BUILTINS (cabs, COND, mips3d), \
14168 CMP_4S_BUILTINS (c, COND), \
14169 CMP_4S_BUILTINS (cabs, COND)
14171 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
14172 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
14173 and AVAIL are as for MIPS_BUILTIN. */
14174 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14175 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
14176 FUNCTION_TYPE, AVAIL)
14178 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
14179 branch instruction. AVAIL is as for MIPS_BUILTIN. */
14180 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
14181 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
14182 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
14184 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
14185 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14186 builtin_description field. */
14187 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
14188 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
14189 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
14190 FUNCTION_TYPE, mips_builtin_avail_loongson }
14192 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
14193 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14194 builtin_description field. */
14195 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
14196 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
14198 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
14199 We use functions of this form when the same insn can be usefully applied
14200 to more than one datatype. */
14201 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
14202 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
14204 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
14205 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
14206 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
14207 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
14208 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
14209 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
14210 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
14211 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
14213 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
14214 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
14215 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
14216 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
14217 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
14218 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
14219 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
14220 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
14221 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
14222 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
14223 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
14224 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
14225 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
14226 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
14227 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
14228 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
14229 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
14230 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
14231 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
14232 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
14233 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
14234 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
14235 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
14236 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
14237 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
14238 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
14239 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
14240 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
14241 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
14242 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
14244 static const struct mips_builtin_description mips_builtins
[] = {
14245 #define MIPS_GET_FCSR 0
14246 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
14247 #define MIPS_SET_FCSR 1
14248 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
14250 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14251 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14252 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14253 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14254 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
14255 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
14256 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
14257 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
14259 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
14260 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14261 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14262 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14263 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14265 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
14266 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
14267 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14268 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
14269 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
14270 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14272 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
14273 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
14274 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14275 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
14276 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
14277 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14279 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
14281 /* Built-in functions for the SB-1 processor. */
14282 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
14284 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
14285 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14286 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14287 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14288 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14289 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14290 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14291 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14292 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14293 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14294 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14295 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14296 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14297 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14298 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
14299 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
14300 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
14301 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14302 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
14303 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
14304 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14305 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
14306 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
14307 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14308 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14309 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14310 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14311 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14312 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14313 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14314 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14315 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14316 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14317 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14318 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14319 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14320 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14321 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14322 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14323 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14324 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14325 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14326 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14327 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14328 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
14329 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14330 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
14331 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
14332 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14333 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14334 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14335 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14336 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14337 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14338 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14339 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14340 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14341 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14342 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14343 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14344 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
14345 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
14346 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14347 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14348 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14349 BPOSGE_BUILTIN (32, dsp
),
14351 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14352 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
14353 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14354 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14355 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14356 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14357 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14358 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14359 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14360 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14361 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14362 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14363 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14364 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14365 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14366 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14367 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
14368 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14369 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14370 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14371 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14372 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14373 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
14374 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14375 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14376 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14377 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14378 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14379 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14380 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14381 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14382 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14383 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14384 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14385 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14387 /* Built-in functions for the DSP ASE (32-bit only). */
14388 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14389 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14390 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14391 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14392 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14393 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14394 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14395 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14396 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14397 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14398 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14399 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14400 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14401 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14402 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14403 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14404 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14405 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14406 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14407 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14408 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14409 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14410 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14411 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14412 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14413 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
14414 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
14416 /* Built-in functions for the DSP ASE (64-bit only). */
14417 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
14419 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14420 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14421 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14422 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14423 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14424 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14425 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14426 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14427 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14428 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14430 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14431 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
14432 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
14433 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
14434 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14435 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14436 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14437 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14438 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14439 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14440 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14441 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
14442 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14443 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14444 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14445 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14446 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
14447 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14448 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14449 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14450 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
14451 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14452 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14453 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14454 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14455 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14456 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14457 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14458 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14459 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14460 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14461 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14462 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14463 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14464 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14465 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14466 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14467 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14468 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
14469 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
14470 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14471 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14472 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14473 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14474 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14475 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14476 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14477 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14478 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14479 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14480 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14481 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14482 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14483 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14484 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14485 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14486 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14487 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14488 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14489 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14490 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14491 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14492 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14493 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14494 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14495 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14496 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14497 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14498 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14499 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14500 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14501 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14502 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14503 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14504 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14505 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14506 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14507 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14508 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14509 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14510 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14511 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14512 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14513 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14514 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14515 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14516 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14517 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14518 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14519 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14520 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14521 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14522 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14523 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14524 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14525 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14526 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14527 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14528 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14529 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14531 /* Sundry other built-in functions. */
14532 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14535 /* Index I is the function declaration for mips_builtins[I], or null if the
14536 function isn't defined on this target. */
14537 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14539 /* MODE is a vector mode whose elements have type TYPE. Return the type
14540 of the vector itself. */
14543 mips_builtin_vector_type (tree type
, machine_mode mode
)
14545 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14548 mode_index
= (int) mode
;
14550 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14551 mode_index
+= MAX_MACHINE_MODE
;
14553 if (types
[mode_index
] == NULL_TREE
)
14554 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14555 return types
[mode_index
];
14558 /* Return a type for 'const volatile void *'. */
14561 mips_build_cvpointer_type (void)
14565 if (cache
== NULL_TREE
)
14566 cache
= build_pointer_type (build_qualified_type
14568 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14572 /* Source-level argument types. */
14573 #define MIPS_ATYPE_VOID void_type_node
14574 #define MIPS_ATYPE_INT integer_type_node
14575 #define MIPS_ATYPE_POINTER ptr_type_node
14576 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14578 /* Standard mode-based argument types. */
14579 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14580 #define MIPS_ATYPE_SI intSI_type_node
14581 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14582 #define MIPS_ATYPE_DI intDI_type_node
14583 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14584 #define MIPS_ATYPE_SF float_type_node
14585 #define MIPS_ATYPE_DF double_type_node
14587 /* Vector argument types. */
14588 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14589 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14590 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14591 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14592 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14593 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14594 #define MIPS_ATYPE_UV2SI \
14595 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14596 #define MIPS_ATYPE_UV4HI \
14597 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14598 #define MIPS_ATYPE_UV8QI \
14599 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14601 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14602 their associated MIPS_ATYPEs. */
14603 #define MIPS_FTYPE_ATYPES1(A, B) \
14604 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14606 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14607 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14609 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14610 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14612 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14613 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14616 /* Return the function type associated with function prototype TYPE. */
14619 mips_build_function_type (enum mips_function_type type
)
14621 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14623 if (types
[(int) type
] == NULL_TREE
)
14626 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14627 case MIPS_FTYPE_NAME##NUM ARGS: \
14628 types[(int) type] \
14629 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14632 #include "config/mips/mips-ftypes.def"
14633 #undef DEF_MIPS_FTYPE
14635 gcc_unreachable ();
14638 return types
[(int) type
];
14641 /* Implement TARGET_INIT_BUILTINS. */
14644 mips_init_builtins (void)
14646 const struct mips_builtin_description
*d
;
14649 /* Iterate through all of the bdesc arrays, initializing all of the
14650 builtin functions. */
14651 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14653 d
= &mips_builtins
[i
];
14655 mips_builtin_decls
[i
]
14656 = add_builtin_function (d
->name
,
14657 mips_build_function_type (d
->function_type
),
14658 i
, BUILT_IN_MD
, NULL
, NULL
);
14662 /* Implement TARGET_BUILTIN_DECL. */
14665 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14667 if (code
>= ARRAY_SIZE (mips_builtins
))
14668 return error_mark_node
;
14669 return mips_builtin_decls
[code
];
14672 /* Take argument ARGNO from EXP's argument list and convert it into
14673 an expand operand. Store the operand in *OP. */
14676 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14677 unsigned int argno
)
14682 arg
= CALL_EXPR_ARG (exp
, argno
);
14683 value
= expand_normal (arg
);
14684 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14687 /* Expand instruction ICODE as part of a built-in function sequence.
14688 Use the first NOPS elements of OPS as the instruction's operands.
14689 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14690 instruction has no target.
14692 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14695 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14696 struct expand_operand
*ops
, bool has_target_p
)
14698 if (!maybe_expand_insn (icode
, nops
, ops
))
14700 error ("invalid argument to built-in function");
14701 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14703 return has_target_p
? ops
[0].value
: const0_rtx
;
14706 /* Expand a floating-point comparison for built-in function call EXP.
14707 The first NARGS arguments are the values to be compared. ICODE is
14708 the .md pattern that does the comparison and COND is the condition
14709 that is being tested. Return an rtx for the result. */
14712 mips_expand_builtin_compare_1 (enum insn_code icode
,
14713 enum mips_fp_condition cond
,
14714 tree exp
, int nargs
)
14716 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14720 /* The instruction should have a target operand, an operand for each
14721 argument, and an operand for COND. */
14722 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14724 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14726 create_fixed_operand (&ops
[opno
++], output
);
14727 for (argno
= 0; argno
< nargs
; argno
++)
14728 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14729 create_integer_operand (&ops
[opno
++], (int) cond
);
14730 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14733 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14734 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14735 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14736 suggests a good place to put the result. */
14739 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14742 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14745 /* Map any target to operand 0. */
14748 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14750 /* Map the arguments to the other operands. */
14751 gcc_assert (opno
+ call_expr_nargs (exp
)
14752 == insn_data
[icode
].n_generator_args
);
14753 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14754 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14756 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14759 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14760 function; TYPE says which. EXP is the CALL_EXPR that calls the
14761 function, ICODE is the instruction that should be used to compare
14762 the first two arguments, and COND is the condition it should test.
14763 TARGET, if nonnull, suggests a good place to put the result. */
14766 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14767 enum insn_code icode
, enum mips_fp_condition cond
,
14768 rtx target
, tree exp
)
14770 struct expand_operand ops
[4];
14773 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14774 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14775 if (type
== MIPS_BUILTIN_MOVT
)
14777 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14778 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14782 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14783 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14785 create_fixed_operand (&ops
[3], cmp_result
);
14786 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14790 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14791 into TARGET otherwise. Return TARGET. */
14794 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14795 rtx value_if_true
, rtx value_if_false
)
14797 rtx_code_label
*true_label
, *done_label
;
14799 true_label
= gen_label_rtx ();
14800 done_label
= gen_label_rtx ();
14802 /* First assume that CONDITION is false. */
14803 mips_emit_move (target
, value_if_false
);
14805 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14806 emit_jump_insn (gen_condjump (condition
, true_label
));
14807 emit_jump_insn (gen_jump (done_label
));
14810 /* Fix TARGET if CONDITION is true. */
14811 emit_label (true_label
);
14812 mips_emit_move (target
, value_if_true
);
14814 emit_label (done_label
);
14818 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14819 the CALL_EXPR that calls the function, ICODE is the code of the
14820 comparison instruction, and COND is the condition it should test.
14821 TARGET, if nonnull, suggests a good place to put the boolean result. */
14824 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14825 enum insn_code icode
, enum mips_fp_condition cond
,
14826 rtx target
, tree exp
)
14828 rtx offset
, condition
, cmp_result
;
14830 if (target
== 0 || GET_MODE (target
) != SImode
)
14831 target
= gen_reg_rtx (SImode
);
14832 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14833 call_expr_nargs (exp
));
14835 /* If the comparison sets more than one register, we define the result
14836 to be 0 if all registers are false and -1 if all registers are true.
14837 The value of the complete result is indeterminate otherwise. */
14838 switch (builtin_type
)
14840 case MIPS_BUILTIN_CMP_ALL
:
14841 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14842 return mips_builtin_branch_and_move (condition
, target
,
14843 const0_rtx
, const1_rtx
);
14845 case MIPS_BUILTIN_CMP_UPPER
:
14846 case MIPS_BUILTIN_CMP_LOWER
:
14847 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14848 condition
= gen_single_cc (cmp_result
, offset
);
14849 return mips_builtin_branch_and_move (condition
, target
,
14850 const1_rtx
, const0_rtx
);
14853 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14854 return mips_builtin_branch_and_move (condition
, target
,
14855 const1_rtx
, const0_rtx
);
14859 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14860 if nonnull, suggests a good place to put the boolean result. */
14863 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14865 rtx condition
, cmp_result
;
14868 if (target
== 0 || GET_MODE (target
) != SImode
)
14869 target
= gen_reg_rtx (SImode
);
14871 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14873 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14878 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14879 return mips_builtin_branch_and_move (condition
, target
,
14880 const1_rtx
, const0_rtx
);
14883 /* Implement TARGET_EXPAND_BUILTIN. */
14886 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14887 machine_mode mode
, int ignore
)
14890 unsigned int fcode
, avail
;
14891 const struct mips_builtin_description
*d
;
14893 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14894 fcode
= DECL_FUNCTION_CODE (fndecl
);
14895 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14896 d
= &mips_builtins
[fcode
];
14897 avail
= d
->avail ();
14898 gcc_assert (avail
!= 0);
14899 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
14901 error ("built-in function %qE not supported for MIPS16",
14902 DECL_NAME (fndecl
));
14903 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14905 switch (d
->builtin_type
)
14907 case MIPS_BUILTIN_DIRECT
:
14908 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14910 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14911 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14913 case MIPS_BUILTIN_MOVT
:
14914 case MIPS_BUILTIN_MOVF
:
14915 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14916 d
->cond
, target
, exp
);
14918 case MIPS_BUILTIN_CMP_ANY
:
14919 case MIPS_BUILTIN_CMP_ALL
:
14920 case MIPS_BUILTIN_CMP_UPPER
:
14921 case MIPS_BUILTIN_CMP_LOWER
:
14922 case MIPS_BUILTIN_CMP_SINGLE
:
14923 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14924 d
->cond
, target
, exp
);
14926 case MIPS_BUILTIN_BPOSGE32
:
14927 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14929 gcc_unreachable ();
14932 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14933 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14934 struct mips16_constant
{
14935 struct mips16_constant
*next
;
14937 rtx_code_label
*label
;
14941 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14942 first constant, HIGHEST_ADDRESS is the highest address that the first
14943 byte of the pool can have, and INSN_ADDRESS is the current instruction
14945 struct mips16_constant_pool
{
14946 struct mips16_constant
*first
;
14947 int highest_address
;
14951 /* Add constant VALUE to POOL and return its label. MODE is the
14952 value's mode (used for CONST_INTs, etc.). */
14954 static rtx_code_label
*
14955 mips16_add_constant (struct mips16_constant_pool
*pool
,
14956 rtx value
, machine_mode mode
)
14958 struct mips16_constant
**p
, *c
;
14959 bool first_of_size_p
;
14961 /* See whether the constant is already in the pool. If so, return the
14962 existing label, otherwise leave P pointing to the place where the
14963 constant should be added.
14965 Keep the pool sorted in increasing order of mode size so that we can
14966 reduce the number of alignments needed. */
14967 first_of_size_p
= true;
14968 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14970 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14971 return (*p
)->label
;
14972 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14974 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14975 first_of_size_p
= false;
14978 /* In the worst case, the constant needed by the earliest instruction
14979 will end up at the end of the pool. The entire pool must then be
14980 accessible from that instruction.
14982 When adding the first constant, set the pool's highest address to
14983 the address of the first out-of-range byte. Adjust this address
14984 downwards each time a new constant is added. */
14985 if (pool
->first
== 0)
14986 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14987 of the instruction with the lowest two bits clear. The base PC
14988 value for LDPC has the lowest three bits clear. Assume the worst
14989 case here; namely that the PC-relative instruction occupies the
14990 last 2 bytes in an aligned word. */
14991 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14992 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14993 if (first_of_size_p
)
14994 /* Take into account the worst possible padding due to alignment. */
14995 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14997 /* Create a new entry. */
14998 c
= XNEW (struct mips16_constant
);
15001 c
->label
= gen_label_rtx ();
15008 /* Output constant VALUE after instruction INSN and return the last
15009 instruction emitted. MODE is the mode of the constant. */
15012 mips16_emit_constants_1 (machine_mode mode
, rtx value
, rtx_insn
*insn
)
15014 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
15016 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
15017 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
15020 if (SCALAR_FLOAT_MODE_P (mode
))
15021 return emit_insn_after (gen_consttable_float (value
), insn
);
15023 if (VECTOR_MODE_P (mode
))
15027 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
15028 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
15029 CONST_VECTOR_ELT (value
, i
), insn
);
15033 gcc_unreachable ();
15036 /* Dump out the constants in CONSTANTS after INSN. */
15039 mips16_emit_constants (struct mips16_constant
*constants
, rtx_insn
*insn
)
15041 struct mips16_constant
*c
, *next
;
15045 for (c
= constants
; c
!= NULL
; c
= next
)
15047 /* If necessary, increase the alignment of PC. */
15048 if (align
< GET_MODE_SIZE (c
->mode
))
15050 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
15051 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
15053 align
= GET_MODE_SIZE (c
->mode
);
15055 insn
= emit_label_after (c
->label
, insn
);
15056 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
15062 emit_barrier_after (insn
);
15065 /* Return the length of instruction INSN. */
15068 mips16_insn_length (rtx_insn
*insn
)
15070 if (JUMP_TABLE_DATA_P (insn
))
15072 rtx body
= PATTERN (insn
);
15073 if (GET_CODE (body
) == ADDR_VEC
)
15074 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
15075 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
15076 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
15078 gcc_unreachable ();
15080 return get_attr_length (insn
);
15083 /* If *X is a symbolic constant that refers to the constant pool, add
15084 the constant to POOL and rewrite *X to use the constant's label. */
15087 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
15090 rtx_code_label
*label
;
15092 split_const (*x
, &base
, &offset
);
15093 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
15095 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
15096 get_pool_mode (base
));
15097 base
= gen_rtx_LABEL_REF (Pmode
, label
);
15098 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
15102 /* Rewrite INSN so that constant pool references refer to the constant's
15106 mips16_rewrite_pool_refs (rtx_insn
*insn
, struct mips16_constant_pool
*pool
)
15108 subrtx_ptr_iterator::array_type array
;
15109 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), ALL
)
15113 if (force_to_mem_operand (*loc
, Pmode
))
15115 rtx mem
= force_const_mem (GET_MODE (*loc
), *loc
);
15116 validate_change (insn
, loc
, mem
, false);
15121 mips16_rewrite_pool_constant (pool
, &XEXP (*loc
, 0));
15122 iter
.skip_subrtxes ();
15126 if (TARGET_MIPS16_TEXT_LOADS
)
15127 mips16_rewrite_pool_constant (pool
, loc
);
15128 if (GET_CODE (*loc
) == CONST
15129 /* Don't rewrite the __mips16_rdwr symbol. */
15130 || (GET_CODE (*loc
) == UNSPEC
15131 && XINT (*loc
, 1) == UNSPEC_TLS_GET_TP
))
15132 iter
.skip_subrtxes ();
15137 /* Return whether CFG is used in mips_reorg. */
15140 mips_cfg_in_reorg (void)
15142 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
15143 || TARGET_RELAX_PIC_CALLS
);
15146 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
15147 otherwise assume that they are already split. */
15150 mips16_lay_out_constants (bool split_p
)
15152 struct mips16_constant_pool pool
;
15153 rtx_insn
*insn
, *barrier
;
15155 if (!TARGET_MIPS16_PCREL_LOADS
)
15160 if (mips_cfg_in_reorg ())
15161 split_all_insns ();
15163 split_all_insns_noflow ();
15166 memset (&pool
, 0, sizeof (pool
));
15167 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15169 /* Rewrite constant pool references in INSN. */
15170 if (USEFUL_INSN_P (insn
))
15171 mips16_rewrite_pool_refs (insn
, &pool
);
15173 pool
.insn_address
+= mips16_insn_length (insn
);
15175 if (pool
.first
!= NULL
)
15177 /* If there are no natural barriers between the first user of
15178 the pool and the highest acceptable address, we'll need to
15179 create a new instruction to jump around the constant pool.
15180 In the worst case, this instruction will be 4 bytes long.
15182 If it's too late to do this transformation after INSN,
15183 do it immediately before INSN. */
15184 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
15186 rtx_code_label
*label
;
15189 label
= gen_label_rtx ();
15191 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
15192 JUMP_LABEL (jump
) = label
;
15193 LABEL_NUSES (label
) = 1;
15194 barrier
= emit_barrier_after (jump
);
15196 emit_label_after (label
, barrier
);
15197 pool
.insn_address
+= 4;
15200 /* See whether the constant pool is now out of range of the first
15201 user. If so, output the constants after the previous barrier.
15202 Note that any instructions between BARRIER and INSN (inclusive)
15203 will use negative offsets to refer to the pool. */
15204 if (pool
.insn_address
> pool
.highest_address
)
15206 mips16_emit_constants (pool
.first
, barrier
);
15210 else if (BARRIER_P (insn
))
15214 mips16_emit_constants (pool
.first
, get_last_insn ());
15217 /* Return true if it is worth r10k_simplify_address's while replacing
15218 an address with X. We are looking for constants, and for addresses
15219 at a known offset from the incoming stack pointer. */
15222 r10k_simplified_address_p (rtx x
)
15224 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
15226 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
15229 /* X is an expression that appears in INSN. Try to use the UD chains
15230 to simplify it, returning the simplified form on success and the
15231 original form otherwise. Replace the incoming value of $sp with
15232 virtual_incoming_args_rtx (which should never occur in X otherwise). */
15235 r10k_simplify_address (rtx x
, rtx_insn
*insn
)
15237 rtx newx
, op0
, op1
, set
, note
;
15238 rtx_insn
*def_insn
;
15240 struct df_link
*defs
;
15245 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15246 if (op0
!= XEXP (x
, 0))
15247 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
15248 op0
, GET_MODE (XEXP (x
, 0)));
15250 else if (BINARY_P (x
))
15252 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15253 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
15254 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
15255 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
15257 else if (GET_CODE (x
) == LO_SUM
)
15259 /* LO_SUMs can be offset from HIGHs, if we know they won't
15260 overflow. See mips_classify_address for the rationale behind
15262 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15263 if (GET_CODE (op0
) == HIGH
)
15264 newx
= XEXP (x
, 1);
15266 else if (REG_P (x
))
15268 /* Uses are recorded by regno_reg_rtx, not X itself. */
15269 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
15271 defs
= DF_REF_CHAIN (use
);
15273 /* Require a single definition. */
15274 if (defs
&& defs
->next
== NULL
)
15277 if (DF_REF_IS_ARTIFICIAL (def
))
15279 /* Replace the incoming value of $sp with
15280 virtual_incoming_args_rtx. */
15281 if (x
== stack_pointer_rtx
15282 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
15283 newx
= virtual_incoming_args_rtx
;
15285 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
15288 /* Make sure that DEF_INSN is a single set of REG. */
15289 def_insn
= DF_REF_INSN (def
);
15290 if (NONJUMP_INSN_P (def_insn
))
15292 set
= single_set (def_insn
);
15293 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
15295 /* Prefer to use notes, since the def-use chains
15296 are often shorter. */
15297 note
= find_reg_equal_equiv_note (def_insn
);
15299 newx
= XEXP (note
, 0);
15301 newx
= SET_SRC (set
);
15302 newx
= r10k_simplify_address (newx
, def_insn
);
15308 if (newx
&& r10k_simplified_address_p (newx
))
15313 /* Return true if ADDRESS is known to be an uncached address
15314 on R10K systems. */
15317 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
15319 unsigned HOST_WIDE_INT upper
;
15321 /* Check for KSEG1. */
15322 if (address
+ 0x60000000 < 0x20000000)
15325 /* Check for uncached XKPHYS addresses. */
15326 if (Pmode
== DImode
)
15328 upper
= (address
>> 40) & 0xf9ffff;
15329 if (upper
== 0x900000 || upper
== 0xb80000)
15335 /* Return true if we can prove that an access to address X in instruction
15336 INSN would be safe from R10K speculation. This X is a general
15337 expression; it might not be a legitimate address. */
15340 r10k_safe_address_p (rtx x
, rtx_insn
*insn
)
15343 HOST_WIDE_INT offset_val
;
15345 x
= r10k_simplify_address (x
, insn
);
15347 /* Check for references to the stack frame. It doesn't really matter
15348 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15349 allows us to assume that accesses to any part of the eventual frame
15350 is safe from speculation at any point in the function. */
15351 mips_split_plus (x
, &base
, &offset_val
);
15352 if (base
== virtual_incoming_args_rtx
15353 && offset_val
>= -cfun
->machine
->frame
.total_size
15354 && offset_val
< cfun
->machine
->frame
.args_size
)
15357 /* Check for uncached addresses. */
15358 if (CONST_INT_P (x
))
15359 return r10k_uncached_address_p (INTVAL (x
));
15361 /* Check for accesses to a static object. */
15362 split_const (x
, &base
, &offset
);
15363 return offset_within_block_p (base
, INTVAL (offset
));
15366 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15367 an in-range access to an automatic variable, or to an object with
15368 a link-time-constant address. */
15371 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
15373 HOST_WIDE_INT bitoffset
, bitsize
;
15374 tree inner
, var_offset
;
15376 int unsigned_p
, volatile_p
;
15378 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
15379 &unsigned_p
, &volatile_p
, false);
15380 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
15383 offset
+= bitoffset
/ BITS_PER_UNIT
;
15384 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
15387 /* Return true if X contains a MEM that is not safe from R10K speculation.
15388 INSN is the instruction that contains X. */
15391 r10k_needs_protection_p_1 (rtx x
, rtx_insn
*insn
)
15393 subrtx_var_iterator::array_type array
;
15394 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
15399 if ((MEM_EXPR (mem
)
15400 && MEM_OFFSET_KNOWN_P (mem
)
15401 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
15402 || r10k_safe_address_p (XEXP (mem
, 0), insn
))
15403 iter
.skip_subrtxes ();
15411 /* A note_stores callback for which DATA points to an instruction pointer.
15412 If *DATA is nonnull, make it null if it X contains a MEM that is not
15413 safe from R10K speculation. */
15416 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
15419 rtx_insn
**insn_ptr
;
15421 insn_ptr
= (rtx_insn
**) data
;
15422 if (*insn_ptr
&& r10k_needs_protection_p_1 (x
, *insn_ptr
))
15426 /* X is the pattern of a call instruction. Return true if the call is
15427 not to a declared function. */
15430 r10k_needs_protection_p_call (const_rtx x
)
15432 subrtx_iterator::array_type array
;
15433 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
15435 const_rtx mem
= *iter
;
15438 const_rtx addr
= XEXP (mem
, 0);
15439 if (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_DECL (addr
))
15440 iter
.skip_subrtxes ();
15448 /* Return true if instruction INSN needs to be protected by an R10K
15452 r10k_needs_protection_p (rtx_insn
*insn
)
15455 return r10k_needs_protection_p_call (PATTERN (insn
));
15457 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
15459 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
15460 return insn
== NULL_RTX
;
15463 return r10k_needs_protection_p_1 (PATTERN (insn
), insn
);
15466 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15467 edge is unconditional. */
15470 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15475 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15476 if (!single_succ_p (e
->src
)
15477 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15478 || (e
->flags
& EDGE_COMPLEX
) != 0)
15483 /* Implement -mr10k-cache-barrier= for the current function. */
15486 r10k_insert_cache_barriers (void)
15488 int *rev_post_order
;
15491 sbitmap protected_bbs
;
15492 rtx_insn
*insn
, *end
;
15493 rtx unprotected_region
;
15497 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15501 /* Calculate dominators. */
15502 calculate_dominance_info (CDI_DOMINATORS
);
15504 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15505 X is protected by a cache barrier. */
15506 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
15507 bitmap_clear (protected_bbs
);
15509 /* Iterate over the basic blocks in reverse post-order. */
15510 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
15511 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15512 for (i
= 0; i
< n
; i
++)
15514 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
15516 /* If this block is only reached by unconditional edges, and if the
15517 source of every edge is protected, the beginning of the block is
15519 if (r10k_protected_bb_p (bb
, protected_bbs
))
15520 unprotected_region
= NULL_RTX
;
15522 unprotected_region
= pc_rtx
;
15523 end
= NEXT_INSN (BB_END (bb
));
15525 /* UNPROTECTED_REGION is:
15527 - null if we are processing a protected region,
15528 - pc_rtx if we are processing an unprotected region but have
15529 not yet found the first instruction in it
15530 - the first instruction in an unprotected region otherwise. */
15531 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15533 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15535 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15536 /* This CACHE instruction protects the following code. */
15537 unprotected_region
= NULL_RTX
;
15540 /* See if INSN is the first instruction in this
15541 unprotected region. */
15542 if (unprotected_region
== pc_rtx
)
15543 unprotected_region
= insn
;
15545 /* See if INSN needs to be protected. If so,
15546 we must insert a cache barrier somewhere between
15547 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15548 clear which position is better performance-wise,
15549 but as a tie-breaker, we assume that it is better
15550 to allow delay slots to be back-filled where
15551 possible, and that it is better not to insert
15552 barriers in the middle of already-scheduled code.
15553 We therefore insert the barrier at the beginning
15555 if (r10k_needs_protection_p (insn
))
15557 emit_insn_before (gen_r10k_cache_barrier (),
15558 unprotected_region
);
15559 unprotected_region
= NULL_RTX
;
15565 /* The called function is not required to protect the exit path.
15566 The code that follows a call is therefore unprotected. */
15567 unprotected_region
= pc_rtx
;
15570 /* Record whether the end of this block is protected. */
15571 if (unprotected_region
== NULL_RTX
)
15572 bitmap_set_bit (protected_bbs
, bb
->index
);
15574 XDELETEVEC (rev_post_order
);
15576 sbitmap_free (protected_bbs
);
15578 free_dominance_info (CDI_DOMINATORS
);
15581 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15582 otherwise. If INSN has two call rtx, then store the second one in
15586 mips_call_expr_from_insn (rtx_insn
*insn
, rtx
*second_call
)
15591 if (!CALL_P (insn
))
15594 x
= PATTERN (insn
);
15595 if (GET_CODE (x
) == PARALLEL
)
15597 /* Calls returning complex values have two CALL rtx. Look for the second
15598 one here, and return it via the SECOND_CALL arg. */
15599 x2
= XVECEXP (x
, 0, 1);
15600 if (GET_CODE (x2
) == SET
)
15602 if (GET_CODE (x2
) == CALL
)
15605 x
= XVECEXP (x
, 0, 0);
15607 if (GET_CODE (x
) == SET
)
15609 gcc_assert (GET_CODE (x
) == CALL
);
15614 /* REG is set in DEF. See if the definition is one of the ways we load a
15615 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15616 If it is, return the symbol reference of the function, otherwise return
15619 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15620 the values of source registers, otherwise treat such registers as
15621 having an unknown value. */
15624 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15626 rtx_insn
*def_insn
;
15629 if (DF_REF_IS_ARTIFICIAL (def
))
15632 def_insn
= DF_REF_INSN (def
);
15633 set
= single_set (def_insn
);
15634 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15636 rtx note
, src
, symbol
;
15638 /* First see whether the source is a plain symbol. This is used
15639 when calling symbols that are not lazily bound. */
15640 src
= SET_SRC (set
);
15641 if (GET_CODE (src
) == SYMBOL_REF
)
15644 /* Handle %call16 references. */
15645 symbol
= mips_strip_unspec_call (src
);
15648 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15652 /* If we have something more complicated, look for a
15653 REG_EQUAL or REG_EQUIV note. */
15654 note
= find_reg_equal_equiv_note (def_insn
);
15655 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15656 return XEXP (note
, 0);
15658 /* Follow at most one simple register copy. Such copies are
15659 interesting in cases like:
15663 locally_binding_fn (...);
15668 locally_binding_fn (...);
15670 locally_binding_fn (...);
15672 where the load of locally_binding_fn can legitimately be
15673 hoisted or shared. However, we do not expect to see complex
15674 chains of copies, so a full worklist solution to the problem
15675 would probably be overkill. */
15676 if (recurse_p
&& REG_P (src
))
15677 return mips_find_pic_call_symbol (def_insn
, src
, false);
15683 /* Find the definition of the use of REG in INSN. See if the definition
15684 is one of the ways we load a register with a symbol address for a
15685 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15686 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15687 mips_pic_call_symbol_from_set. */
15690 mips_find_pic_call_symbol (rtx_insn
*insn
, rtx reg
, bool recurse_p
)
15693 struct df_link
*defs
;
15696 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15699 defs
= DF_REF_CHAIN (use
);
15702 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15706 /* If we have more than one definition, they need to be identical. */
15707 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15711 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15712 if (!rtx_equal_p (symbol
, other
))
15719 /* Replace the args_size operand of the call expression CALL with the
15720 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15723 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15727 args_size
= XEXP (call
, 1);
15728 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15729 gen_rtvec (2, args_size
, symbol
),
15733 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15734 if instead of the arg_size argument it contains the call attributes. If
15735 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15736 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15740 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15742 rtx args_size
, symbol
;
15744 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15747 args_size
= operands
[args_size_opno
];
15748 if (GET_CODE (args_size
) != UNSPEC
)
15750 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15752 symbol
= XVECEXP (args_size
, 0, 1);
15753 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15755 operands
[args_size_opno
] = symbol
;
15759 /* Use DF to annotate PIC indirect calls with the function symbol they
15763 mips_annotate_pic_calls (void)
15768 FOR_EACH_BB_FN (bb
, cfun
)
15769 FOR_BB_INSNS (bb
, insn
)
15771 rtx call
, reg
, symbol
, second_call
;
15774 call
= mips_call_expr_from_insn (insn
, &second_call
);
15777 gcc_assert (MEM_P (XEXP (call
, 0)));
15778 reg
= XEXP (XEXP (call
, 0), 0);
15782 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15785 mips_annotate_pic_call_expr (call
, symbol
);
15787 mips_annotate_pic_call_expr (second_call
, symbol
);
15792 /* A temporary variable used by note_uses callbacks, etc. */
15793 static rtx_insn
*mips_sim_insn
;
15795 /* A structure representing the state of the processor pipeline.
15796 Used by the mips_sim_* family of functions. */
15798 /* The maximum number of instructions that can be issued in a cycle.
15799 (Caches mips_issue_rate.) */
15800 unsigned int issue_rate
;
15802 /* The current simulation time. */
15805 /* How many more instructions can be issued in the current cycle. */
15806 unsigned int insns_left
;
15808 /* LAST_SET[X].INSN is the last instruction to set register X.
15809 LAST_SET[X].TIME is the time at which that instruction was issued.
15810 INSN is null if no instruction has yet set register X. */
15814 } last_set
[FIRST_PSEUDO_REGISTER
];
15816 /* The pipeline's current DFA state. */
15820 /* Reset STATE to the initial simulation state. */
15823 mips_sim_reset (struct mips_sim
*state
)
15825 curr_state
= state
->dfa_state
;
15828 state
->insns_left
= state
->issue_rate
;
15829 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15830 state_reset (curr_state
);
15832 targetm
.sched
.init (0, false, 0);
15833 advance_state (curr_state
);
15836 /* Initialize STATE before its first use. DFA_STATE points to an
15837 allocated but uninitialized DFA state. */
15840 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15842 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15843 targetm
.sched
.init_dfa_pre_cycle_insn ();
15845 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15846 targetm
.sched
.init_dfa_post_cycle_insn ();
15848 state
->issue_rate
= mips_issue_rate ();
15849 state
->dfa_state
= dfa_state
;
15850 mips_sim_reset (state
);
15853 /* Advance STATE by one clock cycle. */
15856 mips_sim_next_cycle (struct mips_sim
*state
)
15858 curr_state
= state
->dfa_state
;
15861 state
->insns_left
= state
->issue_rate
;
15862 advance_state (curr_state
);
15865 /* Advance simulation state STATE until instruction INSN can read
15869 mips_sim_wait_reg (struct mips_sim
*state
, rtx_insn
*insn
, rtx reg
)
15871 unsigned int regno
, end_regno
;
15873 end_regno
= END_REGNO (reg
);
15874 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15875 if (state
->last_set
[regno
].insn
!= 0)
15879 t
= (state
->last_set
[regno
].time
15880 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15881 while (state
->time
< t
)
15882 mips_sim_next_cycle (state
);
15886 /* A note_uses callback. For each register in *X, advance simulation
15887 state DATA until mips_sim_insn can read the register's value. */
15890 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15892 subrtx_var_iterator::array_type array
;
15893 FOR_EACH_SUBRTX_VAR (iter
, array
, *x
, NONCONST
)
15895 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *iter
);
15898 /* Advance simulation state STATE until all of INSN's register
15899 dependencies are satisfied. */
15902 mips_sim_wait_regs (struct mips_sim
*state
, rtx_insn
*insn
)
15904 mips_sim_insn
= insn
;
15905 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15908 /* Advance simulation state STATE until the units required by
15909 instruction INSN are available. */
15912 mips_sim_wait_units (struct mips_sim
*state
, rtx_insn
*insn
)
15916 tmp_state
= alloca (state_size ());
15917 while (state
->insns_left
== 0
15918 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15919 state_transition (tmp_state
, insn
) >= 0))
15920 mips_sim_next_cycle (state
);
15923 /* Advance simulation state STATE until INSN is ready to issue. */
15926 mips_sim_wait_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15928 mips_sim_wait_regs (state
, insn
);
15929 mips_sim_wait_units (state
, insn
);
15932 /* mips_sim_insn has just set X. Update the LAST_SET array
15933 in simulation state DATA. */
15936 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15938 struct mips_sim
*state
;
15940 state
= (struct mips_sim
*) data
;
15943 unsigned int regno
, end_regno
;
15945 end_regno
= END_REGNO (x
);
15946 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15948 state
->last_set
[regno
].insn
= mips_sim_insn
;
15949 state
->last_set
[regno
].time
= state
->time
;
15954 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15955 can issue immediately (i.e., that mips_sim_wait_insn has already
15959 mips_sim_issue_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15961 curr_state
= state
->dfa_state
;
15963 state_transition (curr_state
, insn
);
15964 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15965 state
->insns_left
);
15967 mips_sim_insn
= insn
;
15968 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15971 /* Simulate issuing a NOP in state STATE. */
15974 mips_sim_issue_nop (struct mips_sim
*state
)
15976 if (state
->insns_left
== 0)
15977 mips_sim_next_cycle (state
);
15978 state
->insns_left
--;
15981 /* Update simulation state STATE so that it's ready to accept the instruction
15982 after INSN. INSN should be part of the main rtl chain, not a member of a
15986 mips_sim_finish_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15988 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15990 mips_sim_issue_nop (state
);
15992 switch (GET_CODE (SEQ_BEGIN (insn
)))
15996 /* We can't predict the processor state after a call or label. */
15997 mips_sim_reset (state
);
16001 /* The delay slots of branch likely instructions are only executed
16002 when the branch is taken. Therefore, if the caller has simulated
16003 the delay slot instruction, STATE does not really reflect the state
16004 of the pipeline for the instruction after the delay slot. Also,
16005 branch likely instructions tend to incur a penalty when not taken,
16006 so there will probably be an extra delay between the branch and
16007 the instruction after the delay slot. */
16008 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
16009 mips_sim_reset (state
);
16017 /* Use simulator state STATE to calculate the execution time of
16018 instruction sequence SEQ. */
16020 static unsigned int
16021 mips_seq_time (struct mips_sim
*state
, rtx_insn
*seq
)
16023 mips_sim_reset (state
);
16024 for (rtx_insn
*insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
16026 mips_sim_wait_insn (state
, insn
);
16027 mips_sim_issue_insn (state
, insn
);
16029 return state
->time
;
16032 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
16033 setting SETTING, using STATE to simulate instruction sequences. */
16035 static unsigned int
16036 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
16038 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
16041 machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
16042 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
16043 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
16045 /* If the target provides mulsidi3_32bit then that's the most likely
16046 consumer of the result. Test for bypasses. */
16047 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
16049 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
16050 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
16053 unsigned int time
= mips_seq_time (state
, get_insns ());
16058 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
16059 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
16060 Prefer MULT -- which is shorter -- in the event of a tie. */
16063 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
16065 if (TARGET_MIPS16
|| !ISA_HAS_HILO
)
16066 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO
16067 registers then there is no reason to zero them, arbitrarily choose to
16068 say that "MULT $0,$0" would be faster. */
16069 mips_tuning_info
.fast_mult_zero_zero_p
= true;
16072 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
16073 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
16074 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
16078 /* Set up costs based on the current architecture and tuning settings. */
16081 mips_set_tuning_info (void)
16083 if (mips_tuning_info
.initialized_p
16084 && mips_tuning_info
.arch
== mips_arch
16085 && mips_tuning_info
.tune
== mips_tune
16086 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
16089 mips_tuning_info
.arch
= mips_arch
;
16090 mips_tuning_info
.tune
= mips_tune
;
16091 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
16092 mips_tuning_info
.initialized_p
= true;
16096 struct mips_sim state
;
16097 mips_sim_init (&state
, alloca (state_size ()));
16099 mips_set_fast_mult_zero_zero_p (&state
);
16104 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
16107 mips_expand_to_rtl_hook (void)
16109 /* We need to call this at a point where we can safely create sequences
16110 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
16111 need to call it at a point where the DFA infrastructure is not
16112 already in use, so we can't just call it lazily on demand.
16114 At present, mips_tuning_info is only needed during post-expand
16115 RTL passes such as split_insns, so this hook should be early enough.
16116 We may need to move the call elsewhere if mips_tuning_info starts
16117 to be used for other things (such as rtx_costs, or expanders that
16118 could be called during gimple optimization). */
16119 mips_set_tuning_info ();
16122 /* The VR4130 pipeline issues aligned pairs of instructions together,
16123 but it stalls the second instruction if it depends on the first.
16124 In order to cut down the amount of logic required, this dependence
16125 check is not based on a full instruction decode. Instead, any non-SPECIAL
16126 instruction is assumed to modify the register specified by bits 20-16
16127 (which is usually the "rt" field).
16129 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
16130 input, so we can end up with a false dependence between the branch
16131 and its delay slot. If this situation occurs in instruction INSN,
16132 try to avoid it by swapping rs and rt. */
16135 vr4130_avoid_branch_rt_conflict (rtx_insn
*insn
)
16137 rtx_insn
*first
, *second
;
16139 first
= SEQ_BEGIN (insn
);
16140 second
= SEQ_END (insn
);
16142 && NONJUMP_INSN_P (second
)
16143 && GET_CODE (PATTERN (first
)) == SET
16144 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
16145 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
16147 /* Check for the right kind of condition. */
16148 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
16149 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
16150 && REG_P (XEXP (cond
, 0))
16151 && REG_P (XEXP (cond
, 1))
16152 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
16153 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
16155 /* SECOND mentions the rt register but not the rs register. */
16156 rtx tmp
= XEXP (cond
, 0);
16157 XEXP (cond
, 0) = XEXP (cond
, 1);
16158 XEXP (cond
, 1) = tmp
;
16163 /* Implement -mvr4130-align. Go through each basic block and simulate the
16164 processor pipeline. If we find that a pair of instructions could execute
16165 in parallel, and the first of those instructions is not 8-byte aligned,
16166 insert a nop to make it aligned. */
16169 vr4130_align_insns (void)
16171 struct mips_sim state
;
16172 rtx_insn
*insn
, *subinsn
, *last
, *last2
, *next
;
16177 /* LAST is the last instruction before INSN to have a nonzero length.
16178 LAST2 is the last such instruction before LAST. */
16182 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
16185 mips_sim_init (&state
, alloca (state_size ()));
16186 for (insn
= get_insns (); insn
!= 0; insn
= next
)
16188 unsigned int length
;
16190 next
= NEXT_INSN (insn
);
16192 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
16193 This isn't really related to the alignment pass, but we do it on
16194 the fly to avoid a separate instruction walk. */
16195 vr4130_avoid_branch_rt_conflict (insn
);
16197 length
= get_attr_length (insn
);
16198 if (length
> 0 && USEFUL_INSN_P (insn
))
16199 FOR_EACH_SUBINSN (subinsn
, insn
)
16201 mips_sim_wait_insn (&state
, subinsn
);
16203 /* If we want this instruction to issue in parallel with the
16204 previous one, make sure that the previous instruction is
16205 aligned. There are several reasons why this isn't worthwhile
16206 when the second instruction is a call:
16208 - Calls are less likely to be performance critical,
16209 - There's a good chance that the delay slot can execute
16210 in parallel with the call.
16211 - The return address would then be unaligned.
16213 In general, if we're going to insert a nop between instructions
16214 X and Y, it's better to insert it immediately after X. That
16215 way, if the nop makes Y aligned, it will also align any labels
16216 between X and Y. */
16217 if (state
.insns_left
!= state
.issue_rate
16218 && !CALL_P (subinsn
))
16220 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
16222 /* SUBINSN is the first instruction in INSN and INSN is
16223 aligned. We want to align the previous instruction
16224 instead, so insert a nop between LAST2 and LAST.
16226 Note that LAST could be either a single instruction
16227 or a branch with a delay slot. In the latter case,
16228 LAST, like INSN, is already aligned, but the delay
16229 slot must have some extra delay that stops it from
16230 issuing at the same time as the branch. We therefore
16231 insert a nop before the branch in order to align its
16233 gcc_assert (last2
);
16234 emit_insn_after (gen_nop (), last2
);
16237 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
16239 /* SUBINSN is the delay slot of INSN, but INSN is
16240 currently unaligned. Insert a nop between
16241 LAST and INSN to align it. */
16243 emit_insn_after (gen_nop (), last
);
16247 mips_sim_issue_insn (&state
, subinsn
);
16249 mips_sim_finish_insn (&state
, insn
);
16251 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
16252 length
= get_attr_length (insn
);
16255 /* If the instruction is an asm statement or multi-instruction
16256 mips.md patern, the length is only an estimate. Insert an
16257 8 byte alignment after it so that the following instructions
16258 can be handled correctly. */
16259 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
16260 && (recog_memoized (insn
) < 0 || length
>= 8))
16262 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
16263 next
= NEXT_INSN (next
);
16264 mips_sim_next_cycle (&state
);
16267 else if (length
& 4)
16268 aligned_p
= !aligned_p
;
16273 /* See whether INSN is an aligned label. */
16274 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
16280 /* This structure records that the current function has a LO_SUM
16281 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
16282 the largest offset applied to BASE by all such LO_SUMs. */
16283 struct mips_lo_sum_offset
{
16285 HOST_WIDE_INT offset
;
16288 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
16291 mips_hash_base (rtx base
)
16293 int do_not_record_p
;
16295 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
16298 /* Hashtable helpers. */
16300 struct mips_lo_sum_offset_hasher
: free_ptr_hash
<mips_lo_sum_offset
>
16302 typedef rtx_def
*compare_type
;
16303 static inline hashval_t
hash (const mips_lo_sum_offset
*);
16304 static inline bool equal (const mips_lo_sum_offset
*, const rtx_def
*);
16307 /* Hash-table callbacks for mips_lo_sum_offsets. */
16310 mips_lo_sum_offset_hasher::hash (const mips_lo_sum_offset
*entry
)
16312 return mips_hash_base (entry
->base
);
16316 mips_lo_sum_offset_hasher::equal (const mips_lo_sum_offset
*entry
,
16317 const rtx_def
*value
)
16319 return rtx_equal_p (entry
->base
, value
);
16322 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
16324 /* Look up symbolic constant X in HTAB, which is a hash table of
16325 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16326 paired with a recorded LO_SUM, otherwise record X in the table. */
16329 mips_lo_sum_offset_lookup (mips_offset_table
*htab
, rtx x
,
16330 enum insert_option option
)
16333 mips_lo_sum_offset
**slot
;
16334 struct mips_lo_sum_offset
*entry
;
16336 /* Split X into a base and offset. */
16337 split_const (x
, &base
, &offset
);
16338 if (UNSPEC_ADDRESS_P (base
))
16339 base
= UNSPEC_ADDRESS (base
);
16341 /* Look up the base in the hash table. */
16342 slot
= htab
->find_slot_with_hash (base
, mips_hash_base (base
), option
);
16346 entry
= (struct mips_lo_sum_offset
*) *slot
;
16347 if (option
== INSERT
)
16351 entry
= XNEW (struct mips_lo_sum_offset
);
16352 entry
->base
= base
;
16353 entry
->offset
= INTVAL (offset
);
16358 if (INTVAL (offset
) > entry
->offset
)
16359 entry
->offset
= INTVAL (offset
);
16362 return INTVAL (offset
) <= entry
->offset
;
16365 /* Search X for LO_SUMs and record them in HTAB. */
16368 mips_record_lo_sums (const_rtx x
, mips_offset_table
*htab
)
16370 subrtx_iterator::array_type array
;
16371 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
16372 if (GET_CODE (*iter
) == LO_SUM
)
16373 mips_lo_sum_offset_lookup (htab
, XEXP (*iter
, 1), INSERT
);
16376 /* Return true if INSN is a SET of an orphaned high-part relocation.
16377 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16378 LO_SUMs in the current function. */
16381 mips_orphaned_high_part_p (mips_offset_table
*htab
, rtx_insn
*insn
)
16383 enum mips_symbol_type type
;
16386 set
= single_set (insn
);
16389 /* Check for %his. */
16391 if (GET_CODE (x
) == HIGH
16392 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
16393 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
16395 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16396 if (GET_CODE (x
) == UNSPEC
16397 && XINT (x
, 1) == UNSPEC_LOAD_GOT
16398 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
16399 SYMBOL_CONTEXT_LEA
, &type
)
16400 && type
== SYMBOL_GOTOFF_PAGE
)
16401 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
16406 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16407 INSN and a previous instruction, avoid it by inserting nops after
16410 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16411 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16412 before using the value of that register. *HILO_DELAY counts the
16413 number of instructions since the last hilo hazard (that is,
16414 the number of instructions since the last MFLO or MFHI).
16416 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16417 for the next instruction.
16419 LO_REG is an rtx for the LO register, used in dependence checking. */
16422 mips_avoid_hazard (rtx_insn
*after
, rtx_insn
*insn
, int *hilo_delay
,
16423 rtx
*delayed_reg
, rtx lo_reg
)
16428 pattern
= PATTERN (insn
);
16430 /* Do not put the whole function in .set noreorder if it contains
16431 an asm statement. We don't know whether there will be hazards
16432 between the asm statement and the gcc-generated code. */
16433 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
16434 cfun
->machine
->all_noreorder_p
= false;
16436 /* Ignore zero-length instructions (barriers and the like). */
16437 ninsns
= get_attr_length (insn
) / 4;
16441 /* Work out how many nops are needed. Note that we only care about
16442 registers that are explicitly mentioned in the instruction's pattern.
16443 It doesn't matter that calls use the argument registers or that they
16444 clobber hi and lo. */
16445 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
16446 nops
= 2 - *hilo_delay
;
16447 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
16452 /* Insert the nops between this instruction and the previous one.
16453 Each new nop takes us further from the last hilo hazard. */
16454 *hilo_delay
+= nops
;
16456 emit_insn_after (gen_hazard_nop (), after
);
16458 /* Set up the state for the next instruction. */
16459 *hilo_delay
+= ninsns
;
16461 if (INSN_CODE (insn
) >= 0)
16462 switch (get_attr_hazard (insn
))
16472 set
= single_set (insn
);
16474 *delayed_reg
= SET_DEST (set
);
16479 /* Go through the instruction stream and insert nops where necessary.
16480 Also delete any high-part relocations whose partnering low parts
16481 are now all dead. See if the whole function can then be put into
16482 .set noreorder and .set nomacro. */
16485 mips_reorg_process_insns (void)
16487 rtx_insn
*insn
, *last_insn
, *subinsn
, *next_insn
;
16488 rtx lo_reg
, delayed_reg
;
16491 /* Force all instructions to be split into their final form. */
16492 split_all_insns_noflow ();
16494 /* Recalculate instruction lengths without taking nops into account. */
16495 cfun
->machine
->ignore_hazard_length_p
= true;
16496 shorten_branches (get_insns ());
16498 cfun
->machine
->all_noreorder_p
= true;
16500 /* We don't track MIPS16 PC-relative offsets closely enough to make
16501 a good job of "set .noreorder" code in MIPS16 mode. */
16503 cfun
->machine
->all_noreorder_p
= false;
16505 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16506 if (!TARGET_EXPLICIT_RELOCS
)
16507 cfun
->machine
->all_noreorder_p
= false;
16509 /* Profiled functions can't be all noreorder because the profiler
16510 support uses assembler macros. */
16512 cfun
->machine
->all_noreorder_p
= false;
16514 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16515 all noreorder because we rely on the assembler to work around some
16516 errata. The R5900 too has several bugs. */
16517 if (TARGET_FIX_VR4120
16518 || TARGET_FIX_RM7000
16520 || TARGET_MIPS5900
)
16521 cfun
->machine
->all_noreorder_p
= false;
16523 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16524 MFHI instructions. Note that we avoid using MFLO and MFHI if
16525 the VR4130 MACC and DMACC instructions are available instead;
16526 see the *mfhilo_{si,di}_macc patterns. */
16527 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16528 cfun
->machine
->all_noreorder_p
= false;
16530 mips_offset_table
htab (37);
16532 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16533 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16534 FOR_EACH_SUBINSN (subinsn
, insn
)
16535 if (USEFUL_INSN_P (subinsn
))
16537 rtx body
= PATTERN (insn
);
16538 int noperands
= asm_noperands (body
);
16539 if (noperands
>= 0)
16541 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
16542 bool *used
= XALLOCAVEC (bool, noperands
);
16543 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
16545 get_referenced_operands (string
, used
, noperands
);
16546 for (int i
= 0; i
< noperands
; ++i
)
16548 mips_record_lo_sums (ops
[i
], &htab
);
16551 mips_record_lo_sums (PATTERN (subinsn
), &htab
);
16557 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16559 /* Make a second pass over the instructions. Delete orphaned
16560 high-part relocations or turn them into NOPs. Avoid hazards
16561 by inserting NOPs. */
16562 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16564 next_insn
= NEXT_INSN (insn
);
16565 if (USEFUL_INSN_P (insn
))
16567 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16569 /* If we find an orphaned high-part relocation in a delay
16570 slot, it's easier to turn that instruction into a NOP than
16571 to delete it. The delay slot will be a NOP either way. */
16572 FOR_EACH_SUBINSN (subinsn
, insn
)
16573 if (INSN_P (subinsn
))
16575 if (mips_orphaned_high_part_p (&htab
, subinsn
))
16577 PATTERN (subinsn
) = gen_nop ();
16578 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16580 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16581 &delayed_reg
, lo_reg
);
16587 /* INSN is a single instruction. Delete it if it's an
16588 orphaned high-part relocation. */
16589 if (mips_orphaned_high_part_p (&htab
, insn
))
16590 delete_insn (insn
);
16591 /* Also delete cache barriers if the last instruction
16592 was an annulled branch. INSN will not be speculatively
16594 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16596 && JUMP_P (SEQ_BEGIN (last_insn
))
16597 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16598 delete_insn (insn
);
16601 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16602 &delayed_reg
, lo_reg
);
16610 /* Return true if the function has a long branch instruction. */
16613 mips_has_long_branch_p (void)
16615 rtx_insn
*insn
, *subinsn
;
16618 /* We need up-to-date instruction lengths. */
16619 shorten_branches (get_insns ());
16621 /* Look for a branch that is longer than normal. The normal length for
16622 non-MIPS16 branches is 8, because the length includes the delay slot.
16623 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16624 but they have no delay slot. */
16625 normal_length
= (TARGET_MIPS16
? 4 : 8);
16626 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16627 FOR_EACH_SUBINSN (subinsn
, insn
)
16628 if (JUMP_P (subinsn
)
16629 && get_attr_length (subinsn
) > normal_length
16630 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16636 /* If we are using a GOT, but have not decided to use a global pointer yet,
16637 see whether we need one to implement long branches. Convert the ghost
16638 global-pointer instructions into real ones if so. */
16641 mips_expand_ghost_gp_insns (void)
16643 /* Quick exit if we already know that we will or won't need a
16645 if (!TARGET_USE_GOT
16646 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16647 || mips_must_initialize_gp_p ())
16650 /* Run a full check for long branches. */
16651 if (!mips_has_long_branch_p ())
16654 /* We've now established that we need $gp. */
16655 cfun
->machine
->must_initialize_gp_p
= true;
16656 split_all_insns_noflow ();
16661 /* Subroutine of mips_reorg to manage passes that require DF. */
16664 mips_df_reorg (void)
16666 /* Create def-use chains. */
16667 df_set_flags (DF_EQ_NOTES
);
16668 df_chain_add_problem (DF_UD_CHAIN
);
16671 if (TARGET_RELAX_PIC_CALLS
)
16672 mips_annotate_pic_calls ();
16674 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16675 r10k_insert_cache_barriers ();
16677 df_finish_pass (false);
16680 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16681 called very late in mips_reorg, but the caller is required to run
16682 mips16_lay_out_constants on the result. */
16685 mips16_load_branch_target (rtx dest
, rtx src
)
16687 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16691 if (mips_cfun_has_cprestore_slot_p ())
16692 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16694 mips_emit_move (dest
, pic_offset_table_rtx
);
16695 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16696 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16697 emit_insn (gen_rtx_SET (dest
,
16698 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16699 emit_insn (gen_rtx_SET (dest
, gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16703 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16704 mips_emit_move (dest
, src
);
16708 /* If we're compiling a MIPS16 function, look for and split any long branches.
16709 This must be called after all other instruction modifications in
16713 mips16_split_long_branches (void)
16715 bool something_changed
;
16717 if (!TARGET_MIPS16
)
16720 /* Loop until the alignments for all targets are sufficient. */
16724 rtx_jump_insn
*jump_insn
;
16726 shorten_branches (get_insns ());
16727 something_changed
= false;
16728 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16729 if ((jump_insn
= dyn_cast
<rtx_jump_insn
*> (insn
))
16730 && get_attr_length (jump_insn
) > 4
16731 && (any_condjump_p (jump_insn
) || any_uncondjump_p (jump_insn
)))
16733 rtx old_label
, temp
, saved_temp
;
16734 rtx_code_label
*new_label
;
16736 rtx_insn
*jump
, *jump_sequence
;
16740 /* Free up a MIPS16 register by saving it in $1. */
16741 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16742 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16743 emit_move_insn (saved_temp
, temp
);
16745 /* Load the branch target into TEMP. */
16746 old_label
= JUMP_LABEL (jump_insn
);
16747 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16748 mips16_load_branch_target (temp
, target
);
16750 /* Jump to the target and restore the register's
16752 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16753 (temp
, temp
, saved_temp
)));
16754 JUMP_LABEL (jump
) = old_label
;
16755 LABEL_NUSES (old_label
)++;
16757 /* Rewrite any symbolic references that are supposed to use
16758 a PC-relative constant pool. */
16759 mips16_lay_out_constants (false);
16761 if (simplejump_p (jump_insn
))
16762 /* We're going to replace INSN with a longer form. */
16766 /* Create a branch-around label for the original
16768 new_label
= gen_label_rtx ();
16769 emit_label (new_label
);
16772 jump_sequence
= get_insns ();
16775 emit_insn_after (jump_sequence
, jump_insn
);
16777 invert_jump (jump_insn
, new_label
, false);
16779 delete_insn (jump_insn
);
16780 something_changed
= true;
16783 while (something_changed
);
16786 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16791 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16792 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16793 to date if the CFG is available. */
16794 if (mips_cfg_in_reorg ())
16795 compute_bb_for_insn ();
16796 mips16_lay_out_constants (true);
16797 if (mips_cfg_in_reorg ())
16800 free_bb_for_insn ();
16804 /* We use a machine specific pass to do a second machine dependent reorg
16805 pass after delay branch scheduling. */
16807 static unsigned int
16808 mips_machine_reorg2 (void)
16810 mips_reorg_process_insns ();
16812 && TARGET_EXPLICIT_RELOCS
16814 && TARGET_VR4130_ALIGN
)
16815 vr4130_align_insns ();
16816 if (mips_expand_ghost_gp_insns ())
16817 /* The expansion could invalidate some of the VR4130 alignment
16818 optimizations, but this should be an extremely rare case anyhow. */
16819 mips_reorg_process_insns ();
16820 mips16_split_long_branches ();
16826 const pass_data pass_data_mips_machine_reorg2
=
16828 RTL_PASS
, /* type */
16829 "mach2", /* name */
16830 OPTGROUP_NONE
, /* optinfo_flags */
16831 TV_MACH_DEP
, /* tv_id */
16832 0, /* properties_required */
16833 0, /* properties_provided */
16834 0, /* properties_destroyed */
16835 0, /* todo_flags_start */
16836 0, /* todo_flags_finish */
16839 class pass_mips_machine_reorg2
: public rtl_opt_pass
16842 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16843 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16846 /* opt_pass methods: */
16847 virtual unsigned int execute (function
*) { return mips_machine_reorg2 (); }
16849 }; // class pass_mips_machine_reorg2
16851 } // anon namespace
16854 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16856 return new pass_mips_machine_reorg2 (ctxt
);
16860 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16861 in order to avoid duplicating too much logic from elsewhere. */
16864 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16865 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16868 rtx this_rtx
, temp1
, temp2
, fnaddr
;
16870 bool use_sibcall_p
;
16872 /* Pretend to be a post-reload pass while generating rtl. */
16873 reload_completed
= 1;
16875 /* Mark the end of the (empty) prologue. */
16876 emit_note (NOTE_INSN_PROLOGUE_END
);
16878 /* Determine if we can use a sibcall to call FUNCTION directly. */
16879 fnaddr
= XEXP (DECL_RTL (function
), 0);
16880 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16881 && const_call_insn_operand (fnaddr
, Pmode
));
16883 /* Determine if we need to load FNADDR from the GOT. */
16885 && (mips_got_symbol_type_p
16886 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16888 /* Pick a global pointer. Use a call-clobbered register if
16889 TARGET_CALL_SAVED_GP. */
16890 cfun
->machine
->global_pointer
16891 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16892 cfun
->machine
->must_initialize_gp_p
= true;
16893 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16895 /* Set up the global pointer for n32 or n64 abicalls. */
16896 mips_emit_loadgp ();
16899 /* We need two temporary registers in some cases. */
16900 temp1
= gen_rtx_REG (Pmode
, 2);
16901 temp2
= gen_rtx_REG (Pmode
, 3);
16903 /* Find out which register contains the "this" pointer. */
16904 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16905 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16907 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16909 /* Add DELTA to THIS_RTX. */
16912 rtx offset
= GEN_INT (delta
);
16913 if (!SMALL_OPERAND (delta
))
16915 mips_emit_move (temp1
, offset
);
16918 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16921 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16922 if (vcall_offset
!= 0)
16926 /* Set TEMP1 to *THIS_RTX. */
16927 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16929 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16930 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16932 /* Load the offset and add it to THIS_RTX. */
16933 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16934 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16937 /* Jump to the target function. Use a sibcall if direct jumps are
16938 allowed, otherwise load the address into a register first. */
16941 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16942 SIBLING_CALL_P (insn
) = 1;
16946 /* This is messy. GAS treats "la $25,foo" as part of a call
16947 sequence and may allow a global "foo" to be lazily bound.
16948 The general move patterns therefore reject this combination.
16950 In this context, lazy binding would actually be OK
16951 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16952 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16953 We must therefore load the address via a temporary
16954 register if mips_dangerous_for_la25_p.
16956 If we jump to the temporary register rather than $25,
16957 the assembler can use the move insn to fill the jump's
16960 We can use the same technique for MIPS16 code, where $25
16961 is not a valid JR register. */
16962 if (TARGET_USE_PIC_FN_ADDR_REG
16964 && !mips_dangerous_for_la25_p (fnaddr
))
16965 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16966 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16968 if (TARGET_USE_PIC_FN_ADDR_REG
16969 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16970 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16971 emit_jump_insn (gen_indirect_jump (temp1
));
16974 /* Run just enough of rest_of_compilation. This sequence was
16975 "borrowed" from alpha.c. */
16976 insn
= get_insns ();
16977 split_all_insns_noflow ();
16978 mips16_lay_out_constants (true);
16979 shorten_branches (insn
);
16980 final_start_function (insn
, file
, 1);
16981 final (insn
, file
, 1);
16982 final_end_function ();
16984 /* Clean up the vars set above. Note that final_end_function resets
16985 the global pointer for us. */
16986 reload_completed
= 0;
16990 /* The last argument passed to mips_set_compression_mode,
16991 or negative if the function hasn't been called yet. */
16992 static unsigned int old_compression_mode
= -1;
16994 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16995 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16998 mips_set_compression_mode (unsigned int compression_mode
)
17001 if (compression_mode
== old_compression_mode
)
17004 /* Restore base settings of various flags. */
17005 target_flags
= mips_base_target_flags
;
17006 flag_schedule_insns
= mips_base_schedule_insns
;
17007 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
17008 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
17009 align_loops
= mips_base_align_loops
;
17010 align_jumps
= mips_base_align_jumps
;
17011 align_functions
= mips_base_align_functions
;
17012 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
17013 target_flags
|= compression_mode
;
17015 if (compression_mode
& MASK_MIPS16
)
17017 /* Switch to MIPS16 mode. */
17018 target_flags
|= MASK_MIPS16
;
17020 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
17021 target_flags
&= ~MASK_SYNCI
;
17023 /* Don't run the scheduler before reload, since it tends to
17024 increase register pressure. */
17025 flag_schedule_insns
= 0;
17027 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
17028 the whole function to be in a single section. */
17029 flag_reorder_blocks_and_partition
= 0;
17031 /* Don't move loop invariants, because it tends to increase
17032 register pressure. It also introduces an extra move in cases
17033 where the constant is the first operand in a two-operand binary
17034 instruction, or when it forms a register argument to a functon
17036 flag_move_loop_invariants
= 0;
17038 target_flags
|= MASK_EXPLICIT_RELOCS
;
17040 /* Experiments suggest we get the best overall section-anchor
17041 results from using the range of an unextended LW or SW. Code
17042 that makes heavy use of byte or short accesses can do better
17043 with ranges of 0...31 and 0...63 respectively, but most code is
17044 sensitive to the range of LW and SW instead. */
17045 targetm
.min_anchor_offset
= 0;
17046 targetm
.max_anchor_offset
= 127;
17048 targetm
.const_anchor
= 0;
17050 /* MIPS16 has no BAL instruction. */
17051 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17053 /* The R4000 errata don't apply to any known MIPS16 cores.
17054 It's simpler to make the R4000 fixes and MIPS16 mode
17055 mutually exclusive. */
17056 target_flags
&= ~MASK_FIX_R4000
;
17058 if (flag_pic
&& !TARGET_OLDABI
)
17059 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
17062 sorry ("MIPS16 -mxgot code");
17064 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
17065 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
17069 /* Switch to microMIPS or the standard encoding. */
17071 if (TARGET_MICROMIPS
)
17072 /* Avoid branch likely. */
17073 target_flags
&= ~MASK_BRANCHLIKELY
;
17075 /* Provide default values for align_* for 64-bit targets. */
17078 if (align_loops
== 0)
17080 if (align_jumps
== 0)
17082 if (align_functions
== 0)
17083 align_functions
= 8;
17086 targetm
.min_anchor_offset
= -32768;
17087 targetm
.max_anchor_offset
= 32767;
17089 targetm
.const_anchor
= 0x8000;
17092 /* (Re)initialize MIPS target internals for new ISA. */
17093 mips_init_relocs ();
17095 if (compression_mode
& MASK_MIPS16
)
17097 if (!mips16_globals
)
17098 mips16_globals
= save_target_globals_default_opts ();
17100 restore_target_globals (mips16_globals
);
17102 else if (compression_mode
& MASK_MICROMIPS
)
17104 if (!micromips_globals
)
17105 micromips_globals
= save_target_globals_default_opts ();
17107 restore_target_globals (micromips_globals
);
17110 restore_target_globals (&default_target_globals
);
17112 old_compression_mode
= compression_mode
;
17115 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
17116 function should use the MIPS16 or microMIPS ISA and switch modes
17120 mips_set_current_function (tree fndecl
)
17122 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
17125 /* Allocate a chunk of memory for per-function machine-dependent data. */
17127 static struct machine_function
*
17128 mips_init_machine_status (void)
17130 return ggc_cleared_alloc
<machine_function
> ();
17133 /* Return the processor associated with the given ISA level, or null
17134 if the ISA isn't valid. */
17136 static const struct mips_cpu_info
*
17137 mips_cpu_info_from_isa (int isa
)
17141 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
17142 if (mips_cpu_info_table
[i
].isa
== isa
)
17143 return mips_cpu_info_table
+ i
;
17148 /* Return a mips_cpu_info entry determined by an option valued
17151 static const struct mips_cpu_info
*
17152 mips_cpu_info_from_opt (int opt
)
17156 case MIPS_ARCH_OPTION_FROM_ABI
:
17157 /* 'from-abi' selects the most compatible architecture for the
17158 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
17159 ABIs. For the EABIs, we have to decide whether we're using
17160 the 32-bit or 64-bit version. */
17161 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
17162 : ABI_NEEDS_64BIT_REGS
? 3
17163 : (TARGET_64BIT
? 3 : 1));
17165 case MIPS_ARCH_OPTION_NATIVE
:
17166 gcc_unreachable ();
17169 return &mips_cpu_info_table
[opt
];
17173 /* Return a default mips_cpu_info entry, given that no -march= option
17174 was explicitly specified. */
17176 static const struct mips_cpu_info
*
17177 mips_default_arch (void)
17179 #if defined (MIPS_CPU_STRING_DEFAULT)
17181 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
17182 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
17183 return mips_cpu_info_table
+ i
;
17184 gcc_unreachable ();
17185 #elif defined (MIPS_ISA_DEFAULT)
17186 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
17188 /* 'from-abi' makes a good default: you get whatever the ABI
17190 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
17194 /* Set up globals to generate code for the ISA or processor
17195 described by INFO. */
17198 mips_set_architecture (const struct mips_cpu_info
*info
)
17202 mips_arch_info
= info
;
17203 mips_arch
= info
->cpu
;
17204 mips_isa
= info
->isa
;
17208 mips_isa_rev
= (mips_isa
& 31) + 1;
17212 /* Likewise for tuning. */
17215 mips_set_tune (const struct mips_cpu_info
*info
)
17219 mips_tune_info
= info
;
17220 mips_tune
= info
->cpu
;
17224 /* Implement TARGET_OPTION_OVERRIDE. */
17227 mips_option_override (void)
17229 int i
, start
, regno
, mode
;
17231 if (global_options_set
.x_mips_isa_option
)
17232 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
17234 #ifdef SUBTARGET_OVERRIDE_OPTIONS
17235 SUBTARGET_OVERRIDE_OPTIONS
;
17238 /* MIPS16 and microMIPS cannot coexist. */
17239 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
17240 error ("unsupported combination: %s", "-mips16 -mmicromips");
17242 /* Save the base compression state and process flags as though we
17243 were generating uncompressed code. */
17244 mips_base_compression_flags
= TARGET_COMPRESSION
;
17245 target_flags
&= ~TARGET_COMPRESSION
;
17247 /* -mno-float overrides -mhard-float and -msoft-float. */
17248 if (TARGET_NO_FLOAT
)
17250 target_flags
|= MASK_SOFT_FLOAT_ABI
;
17251 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
17254 if (TARGET_FLIP_MIPS16
)
17255 TARGET_INTERLINK_COMPRESSED
= 1;
17257 /* Set the small data limit. */
17258 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
17260 : MIPS_DEFAULT_GVALUE
);
17262 /* The following code determines the architecture and register size.
17263 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
17264 The GAS and GCC code should be kept in sync as much as possible. */
17266 if (global_options_set
.x_mips_arch_option
)
17267 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
17269 if (mips_isa_option_info
!= 0)
17271 if (mips_arch_info
== 0)
17272 mips_set_architecture (mips_isa_option_info
);
17273 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
17274 error ("%<-%s%> conflicts with the other architecture options, "
17275 "which specify a %s processor",
17276 mips_isa_option_info
->name
,
17277 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
17280 if (mips_arch_info
== 0)
17281 mips_set_architecture (mips_default_arch ());
17283 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
17284 error ("%<-march=%s%> is not compatible with the selected ABI",
17285 mips_arch_info
->name
);
17287 /* Optimize for mips_arch, unless -mtune selects a different processor. */
17288 if (global_options_set
.x_mips_tune_option
)
17289 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
17291 if (mips_tune_info
== 0)
17292 mips_set_tune (mips_arch_info
);
17294 if ((target_flags_explicit
& MASK_64BIT
) != 0)
17296 /* The user specified the size of the integer registers. Make sure
17297 it agrees with the ABI and ISA. */
17298 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
17299 error ("%<-mgp64%> used with a 32-bit processor");
17300 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
17301 error ("%<-mgp32%> used with a 64-bit ABI");
17302 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
17303 error ("%<-mgp64%> used with a 32-bit ABI");
17307 /* Infer the integer register size from the ABI and processor.
17308 Restrict ourselves to 32-bit registers if that's all the
17309 processor has, or if the ABI cannot handle 64-bit registers. */
17310 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
17311 target_flags
&= ~MASK_64BIT
;
17313 target_flags
|= MASK_64BIT
;
17316 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
17318 if (mips_isa_rev
>= 6 && !TARGET_FLOAT64
)
17319 error ("the %qs architecture does not support %<-mfp32%>",
17320 mips_arch_info
->name
);
17321 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
17322 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17323 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
17324 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17325 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
17327 if (!ISA_HAS_MXHC1
)
17328 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17329 " the target supports the mfhc1 and mthc1 instructions");
17330 else if (mips_abi
!= ABI_32
)
17331 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17337 /* -msingle-float selects 32-bit float registers. On r6 and later,
17338 -mdouble-float selects 64-bit float registers, since the old paired
17339 register model is not supported. In other cases the float registers
17340 should be the same size as the integer ones. */
17341 if (mips_isa_rev
>= 6 && TARGET_DOUBLE_FLOAT
&& !TARGET_FLOATXX
)
17342 target_flags
|= MASK_FLOAT64
;
17343 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
17344 target_flags
|= MASK_FLOAT64
;
17346 target_flags
&= ~MASK_FLOAT64
;
17349 if (mips_abi
!= ABI_32
&& TARGET_FLOATXX
)
17350 error ("%<-mfpxx%> can only be used with the o32 ABI");
17351 else if (TARGET_FLOAT64
&& TARGET_FLOATXX
)
17352 error ("unsupported combination: %s", "-mfp64 -mfpxx");
17353 else if (ISA_MIPS1
&& !TARGET_FLOAT32
)
17354 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info
->name
);
17355 else if (TARGET_FLOATXX
&& !mips_lra_flag
)
17356 error ("%<-mfpxx%> requires %<-mlra%>");
17358 /* End of code shared with GAS. */
17360 /* The R5900 FPU only supports single precision. */
17361 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
17362 error ("unsupported combination: %s",
17363 "-march=r5900 -mhard-float -mdouble-float");
17365 /* If a -mlong* option was given, check that it matches the ABI,
17366 otherwise infer the -mlong* setting from the other options. */
17367 if ((target_flags_explicit
& MASK_LONG64
) != 0)
17371 if (mips_abi
== ABI_N32
)
17372 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17373 else if (mips_abi
== ABI_32
)
17374 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17375 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
17376 /* We have traditionally allowed non-abicalls code to use
17377 an LP64 form of o64. However, it would take a bit more
17378 effort to support the combination of 32-bit GOT entries
17379 and 64-bit pointers, so we treat the abicalls case as
17381 error ("the combination of %qs and %qs is incompatible with %qs",
17382 "-mabi=o64", "-mabicalls", "-mlong64");
17386 if (mips_abi
== ABI_64
)
17387 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17392 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
17393 target_flags
|= MASK_LONG64
;
17395 target_flags
&= ~MASK_LONG64
;
17398 if (!TARGET_OLDABI
)
17399 flag_pcc_struct_return
= 0;
17401 /* Decide which rtx_costs structure to use. */
17403 mips_cost
= &mips_rtx_cost_optimize_size
;
17405 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
17407 /* If the user hasn't specified a branch cost, use the processor's
17409 if (mips_branch_cost
== 0)
17410 mips_branch_cost
= mips_cost
->branch_cost
;
17412 /* If neither -mbranch-likely nor -mno-branch-likely was given
17413 on the command line, set MASK_BRANCHLIKELY based on the target
17414 architecture and tuning flags. Annulled delay slots are a
17415 size win, so we only consider the processor-specific tuning
17416 for !optimize_size. */
17417 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
17419 if (ISA_HAS_BRANCHLIKELY
17421 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
17422 target_flags
|= MASK_BRANCHLIKELY
;
17424 target_flags
&= ~MASK_BRANCHLIKELY
;
17426 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
17427 warning (0, "the %qs architecture does not support branch-likely"
17428 " instructions", mips_arch_info
->name
);
17430 /* If the user hasn't specified -mimadd or -mno-imadd set
17431 MASK_IMADD based on the target architecture and tuning
17433 if ((target_flags_explicit
& MASK_IMADD
) == 0)
17435 if (ISA_HAS_MADD_MSUB
&&
17436 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
17437 target_flags
|= MASK_IMADD
;
17439 target_flags
&= ~MASK_IMADD
;
17441 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
17442 warning (0, "the %qs architecture does not support madd or msub"
17443 " instructions", mips_arch_info
->name
);
17445 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
17446 line, set MASK_ODD_SPREG based on the ISA and ABI. */
17447 if ((target_flags_explicit
& MASK_ODD_SPREG
) == 0)
17449 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
17450 if (!ISA_HAS_ODD_SPREG
|| TARGET_FLOATXX
)
17451 target_flags
&= ~MASK_ODD_SPREG
;
17453 target_flags
|= MASK_ODD_SPREG
;
17455 else if (TARGET_ODD_SPREG
&& !ISA_HAS_ODD_SPREG
)
17456 warning (0, "the %qs architecture does not support odd single-precision"
17457 " registers", mips_arch_info
->name
);
17459 if (!TARGET_ODD_SPREG
&& TARGET_64BIT
)
17461 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
17462 /* Allow compilation to continue further even though invalid output
17463 will be produced. */
17464 target_flags
|= MASK_ODD_SPREG
;
17467 /* The effect of -mabicalls isn't defined for the EABI. */
17468 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
17470 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17471 target_flags
&= ~MASK_ABICALLS
;
17474 /* PIC requires -mabicalls. */
17477 if (mips_abi
== ABI_EABI
)
17478 error ("cannot generate position-independent code for %qs",
17480 else if (!TARGET_ABICALLS
)
17481 error ("position-independent code requires %qs", "-mabicalls");
17484 if (TARGET_ABICALLS_PIC2
)
17485 /* We need to set flag_pic for executables as well as DSOs
17486 because we may reference symbols that are not defined in
17487 the final executable. (MIPS does not use things like
17488 copy relocs, for example.)
17490 There is a body of code that uses __PIC__ to distinguish
17491 between -mabicalls and -mno-abicalls code. The non-__PIC__
17492 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17493 long as any indirect jumps use $25. */
17496 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17497 faster code, but at the expense of more nops. Enable it at -O3 and
17499 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
17500 target_flags
|= MASK_VR4130_ALIGN
;
17502 /* Prefer a call to memcpy over inline code when optimizing for size,
17503 though see MOVE_RATIO in mips.h. */
17504 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
17505 target_flags
|= MASK_MEMCPY
;
17507 /* If we have a nonzero small-data limit, check that the -mgpopt
17508 setting is consistent with the other target flags. */
17509 if (mips_small_data_threshold
> 0)
17513 if (!TARGET_EXPLICIT_RELOCS
)
17514 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17516 TARGET_LOCAL_SDATA
= false;
17517 TARGET_EXTERN_SDATA
= false;
17521 if (TARGET_VXWORKS_RTP
)
17522 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17524 if (TARGET_ABICALLS
)
17525 warning (0, "cannot use small-data accesses for %qs",
17530 /* Set NaN and ABS defaults. */
17531 if (mips_nan
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
17532 mips_nan
= MIPS_IEEE_754_2008
;
17533 if (mips_abs
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
17534 mips_abs
= MIPS_IEEE_754_2008
;
17536 /* Check for IEEE 754 legacy/2008 support. */
17537 if ((mips_nan
== MIPS_IEEE_754_LEGACY
17538 || mips_abs
== MIPS_IEEE_754_LEGACY
)
17539 && !ISA_HAS_IEEE_754_LEGACY
)
17540 warning (0, "the %qs architecture does not support %<-m%s=legacy%>",
17541 mips_arch_info
->name
,
17542 mips_nan
== MIPS_IEEE_754_LEGACY
? "nan" : "abs");
17544 if ((mips_nan
== MIPS_IEEE_754_2008
17545 || mips_abs
== MIPS_IEEE_754_2008
)
17546 && !ISA_HAS_IEEE_754_2008
)
17547 warning (0, "the %qs architecture does not support %<-m%s=2008%>",
17548 mips_arch_info
->name
,
17549 mips_nan
== MIPS_IEEE_754_2008
? "nan" : "abs");
17551 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17552 for all its floating point. */
17553 if (mips_nan
!= MIPS_IEEE_754_2008
)
17555 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17556 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17557 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17560 /* Make sure that the user didn't turn off paired single support when
17561 MIPS-3D support is requested. */
17563 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17564 && !TARGET_PAIRED_SINGLE_FLOAT
)
17565 error ("%<-mips3d%> requires %<-mpaired-single%>");
17567 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17569 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17571 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17572 and TARGET_HARD_FLOAT_ABI are both true. */
17573 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17575 error ("%qs must be used with %qs",
17576 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17577 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17578 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17582 /* Make sure that -mpaired-single is only used on ISAs that support it.
17583 We must disable it otherwise since it relies on other ISA properties
17584 like ISA_HAS_8CC having their normal values. */
17585 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17587 error ("the %qs architecture does not support paired-single"
17588 " instructions", mips_arch_info
->name
);
17589 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17593 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17594 && !TARGET_CACHE_BUILTIN
)
17596 error ("%qs requires a target that provides the %qs instruction",
17597 "-mr10k-cache-barrier", "cache");
17598 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17601 /* If TARGET_DSPR2, enable TARGET_DSP. */
17605 if (TARGET_DSP
&& mips_isa_rev
>= 6)
17607 error ("the %qs architecture does not support DSP instructions",
17608 mips_arch_info
->name
);
17609 TARGET_DSP
= false;
17610 TARGET_DSPR2
= false;
17613 /* .eh_frame addresses should be the same width as a C pointer.
17614 Most MIPS ABIs support only one pointer size, so the assembler
17615 will usually know exactly how big an .eh_frame address is.
17617 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17618 originally defined to use 64-bit pointers (i.e. it is LP64), and
17619 this is still the default mode. However, we also support an n32-like
17620 ILP32 mode, which is selected by -mlong32. The problem is that the
17621 assembler has traditionally not had an -mlong option, so it has
17622 traditionally not known whether we're using the ILP32 or LP64 form.
17624 As it happens, gas versions up to and including 2.19 use _32-bit_
17625 addresses for EABI64 .cfi_* directives. This is wrong for the
17626 default LP64 mode, so we can't use the directives by default.
17627 Moreover, since gas's current behavior is at odds with gcc's
17628 default behavior, it seems unwise to rely on future versions
17629 of gas behaving the same way. We therefore avoid using .cfi
17630 directives for -mlong32 as well. */
17631 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17632 flag_dwarf2_cfi_asm
= 0;
17634 /* .cfi_* directives generate a read-only section, so fall back on
17635 manual .eh_frame creation if we need the section to be writable. */
17636 if (TARGET_WRITABLE_EH_FRAME
)
17637 flag_dwarf2_cfi_asm
= 0;
17639 mips_init_print_operand_punct ();
17641 /* Set up array to map GCC register number to debug register number.
17642 Ignore the special purpose register numbers. */
17644 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17646 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17647 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17648 mips_dwarf_regno
[i
] = i
;
17650 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17653 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17654 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17655 mips_dbx_regno
[i
] = i
+ start
;
17657 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17658 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17659 mips_dbx_regno
[i
] = i
+ start
;
17661 /* Accumulator debug registers use big-endian ordering. */
17662 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17663 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17664 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17665 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17666 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17668 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17669 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17672 /* Set up mips_hard_regno_mode_ok. */
17673 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17674 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17675 mips_hard_regno_mode_ok
[mode
][regno
]
17676 = mips_hard_regno_mode_ok_p (regno
, (machine_mode
) mode
);
17678 /* Function to allocate machine-dependent function status. */
17679 init_machine_status
= &mips_init_machine_status
;
17681 /* Default to working around R4000 errata only if the processor
17682 was selected explicitly. */
17683 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17684 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17685 target_flags
|= MASK_FIX_R4000
;
17687 /* Default to working around R4400 errata only if the processor
17688 was selected explicitly. */
17689 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17690 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17691 target_flags
|= MASK_FIX_R4400
;
17693 /* Default to working around R10000 errata only if the processor
17694 was selected explicitly. */
17695 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17696 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17697 target_flags
|= MASK_FIX_R10000
;
17699 /* Make sure that branch-likely instructions available when using
17700 -mfix-r10000. The instructions are not available if either:
17702 1. -mno-branch-likely was passed.
17703 2. The selected ISA does not support branch-likely and
17704 the command line does not include -mbranch-likely. */
17705 if (TARGET_FIX_R10000
17706 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17707 ? !ISA_HAS_BRANCHLIKELY
17708 : !TARGET_BRANCHLIKELY
))
17709 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17711 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17713 warning (0, "the %qs architecture does not support the synci "
17714 "instruction", mips_arch_info
->name
);
17715 target_flags
&= ~MASK_SYNCI
;
17718 /* Only optimize PIC indirect calls if they are actually required. */
17719 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17720 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17722 /* Save base state of options. */
17723 mips_base_target_flags
= target_flags
;
17724 mips_base_schedule_insns
= flag_schedule_insns
;
17725 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17726 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17727 mips_base_align_loops
= align_loops
;
17728 mips_base_align_jumps
= align_jumps
;
17729 mips_base_align_functions
= align_functions
;
17731 /* Now select the ISA mode.
17733 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17734 later if required. */
17735 mips_set_compression_mode (0);
17737 /* We register a second machine specific reorg pass after delay slot
17738 filling. Registering the pass must be done at start up. It's
17739 convenient to do it here. */
17740 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17741 struct register_pass_info insert_pass_mips_machine_reorg2
=
17743 new_pass
, /* pass */
17744 "dbr", /* reference_pass_name */
17745 1, /* ref_pass_instance_number */
17746 PASS_POS_INSERT_AFTER
/* po_op */
17748 register_pass (&insert_pass_mips_machine_reorg2
);
17750 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17751 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17754 /* Swap the register information for registers I and I + 1, which
17755 currently have the wrong endianness. Note that the registers'
17756 fixedness and call-clobberedness might have been set on the
17760 mips_swap_registers (unsigned int i
)
17765 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17766 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17768 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17769 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17770 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17771 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17777 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17780 mips_conditional_register_usage (void)
17785 /* These DSP control register fields are global. */
17786 global_regs
[CCDSP_PO_REGNUM
] = 1;
17787 global_regs
[CCDSP_SC_REGNUM
] = 1;
17790 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17791 reg_class_contents
[(int) DSP_ACC_REGS
]);
17794 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17795 reg_class_contents
[(int) MD_REGS
]);
17797 if (!TARGET_HARD_FLOAT
)
17799 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17800 reg_class_contents
[(int) FP_REGS
]);
17801 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17802 reg_class_contents
[(int) ST_REGS
]);
17804 else if (!ISA_HAS_8CC
)
17806 /* We only have a single condition-code register. We implement
17807 this by fixing all the condition-code registers and generating
17808 RTL that refers directly to ST_REG_FIRST. */
17809 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17810 reg_class_contents
[(int) ST_REGS
]);
17812 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17813 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17817 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17818 are call-saved, and saving them via a MIPS16 register would
17819 probably waste more time than just reloading the value.
17821 We permit the $t temporary registers when optimizing for speed
17822 but not when optimizing for space because using them results in
17823 code that is larger (but faster) then not using them. We do
17824 allow $24 (t8) because it is used in CMP and CMPI instructions
17825 and $25 (t9) because it is used as the function call address in
17828 fixed_regs
[18] = call_used_regs
[18] = 1;
17829 fixed_regs
[19] = call_used_regs
[19] = 1;
17830 fixed_regs
[20] = call_used_regs
[20] = 1;
17831 fixed_regs
[21] = call_used_regs
[21] = 1;
17832 fixed_regs
[22] = call_used_regs
[22] = 1;
17833 fixed_regs
[23] = call_used_regs
[23] = 1;
17834 fixed_regs
[26] = call_used_regs
[26] = 1;
17835 fixed_regs
[27] = call_used_regs
[27] = 1;
17836 fixed_regs
[30] = call_used_regs
[30] = 1;
17839 fixed_regs
[8] = call_used_regs
[8] = 1;
17840 fixed_regs
[9] = call_used_regs
[9] = 1;
17841 fixed_regs
[10] = call_used_regs
[10] = 1;
17842 fixed_regs
[11] = call_used_regs
[11] = 1;
17843 fixed_regs
[12] = call_used_regs
[12] = 1;
17844 fixed_regs
[13] = call_used_regs
[13] = 1;
17845 fixed_regs
[14] = call_used_regs
[14] = 1;
17846 fixed_regs
[15] = call_used_regs
[15] = 1;
17849 /* Do not allow HI and LO to be treated as register operands.
17850 There are no MTHI or MTLO instructions (or any real need
17851 for them) and one-way registers cannot easily be reloaded. */
17852 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17853 reg_class_contents
[(int) MD_REGS
]);
17855 /* $f20-$f23 are call-clobbered for n64. */
17856 if (mips_abi
== ABI_64
)
17859 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17860 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17862 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17863 for n32 and o32 FP64. */
17864 if (mips_abi
== ABI_N32
17865 || (mips_abi
== ABI_32
17866 && TARGET_FLOAT64
))
17869 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17870 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17872 /* Make sure that double-register accumulator values are correctly
17873 ordered for the current endianness. */
17874 if (TARGET_LITTLE_ENDIAN
)
17876 unsigned int regno
;
17878 mips_swap_registers (MD_REG_FIRST
);
17879 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17880 mips_swap_registers (regno
);
17884 /* Implement EH_USES. */
17887 mips_eh_uses (unsigned int regno
)
17889 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17891 /* We need to force certain registers to be live in order to handle
17892 PIC long branches correctly. See mips_must_initialize_gp_p for
17894 if (mips_cfun_has_cprestore_slot_p ())
17896 if (regno
== CPRESTORE_SLOT_REGNUM
)
17901 if (cfun
->machine
->global_pointer
== regno
)
17909 /* Implement EPILOGUE_USES. */
17912 mips_epilogue_uses (unsigned int regno
)
17914 /* Say that the epilogue uses the return address register. Note that
17915 in the case of sibcalls, the values "used by the epilogue" are
17916 considered live at the start of the called function. */
17917 if (regno
== RETURN_ADDR_REGNUM
)
17920 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17921 See the comment above load_call<mode> for details. */
17922 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17925 /* An interrupt handler must preserve some registers that are
17926 ordinarily call-clobbered. */
17927 if (cfun
->machine
->interrupt_handler_p
17928 && mips_interrupt_extra_call_saved_reg_p (regno
))
17934 /* Return true if INSN needs to be wrapped in ".set noat".
17935 INSN has NOPERANDS operands, stored in OPVEC. */
17938 mips_need_noat_wrapper_p (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
17940 if (recog_memoized (insn
) >= 0)
17942 subrtx_iterator::array_type array
;
17943 for (int i
= 0; i
< noperands
; i
++)
17944 FOR_EACH_SUBRTX (iter
, array
, opvec
[i
], NONCONST
)
17945 if (REG_P (*iter
) && REGNO (*iter
) == AT_REGNUM
)
17951 /* Implement FINAL_PRESCAN_INSN. */
17954 mips_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
17956 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17957 mips_push_asm_switch (&mips_noat
);
17960 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17963 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx_insn
*insn
,
17964 rtx
*opvec
, int noperands
)
17966 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17967 mips_pop_asm_switch (&mips_noat
);
17970 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17971 EXT_CODE is the code of the extension used. Return NULL if widening
17972 multiplication shouldn't be used. */
17975 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17979 signed_p
= ext_code
== SIGN_EXTEND
;
17982 /* Don't use widening multiplication with MULT when we have DMUL. Even
17983 with the extension of its input operands DMUL is faster. Note that
17984 the extension is not needed for signed multiplication. In order to
17985 ensure that we always remove the redundant sign-extension in this
17986 case we still expand mulsidi3 for DMUL. */
17987 if (ISA_HAS_R6DMUL
)
17988 return signed_p
? gen_mulsidi3_64bit_r6dmul
: NULL
;
17990 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17993 ? gen_mulsidi3_64bit_mips16
17994 : gen_umulsidi3_64bit_mips16
);
17995 if (TARGET_FIX_R4000
)
17997 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
18002 return (signed_p
? gen_mulsidi3_32bit_r6
: gen_umulsidi3_32bit_r6
);
18005 ? gen_mulsidi3_32bit_mips16
18006 : gen_umulsidi3_32bit_mips16
);
18007 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
18008 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
18009 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
18013 /* Return true if PATTERN matches the kind of instruction generated by
18014 umips_build_save_restore. SAVE_P is true for store. */
18017 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
18021 HOST_WIDE_INT first_offset
= 0;
18022 rtx first_base
= 0;
18023 unsigned int regmask
= 0;
18025 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
18027 rtx set
, reg
, mem
, this_base
;
18028 HOST_WIDE_INT this_offset
;
18030 /* Check that we have a SET. */
18031 set
= XVECEXP (pattern
, 0, n
);
18032 if (GET_CODE (set
) != SET
)
18035 /* Check that the SET is a load (if restoring) or a store
18037 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
18038 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
18041 /* Check that the address is the sum of base and a possibly-zero
18042 constant offset. Determine if the offset is in range. */
18043 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
18044 if (!REG_P (this_base
))
18049 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
18051 first_base
= this_base
;
18052 first_offset
= this_offset
;
18056 /* Check that the save slots are consecutive. */
18057 if (REGNO (this_base
) != REGNO (first_base
)
18058 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
18062 /* Check that SET's other operand is a register. */
18063 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
18067 regmask
|= 1 << REGNO (reg
);
18070 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
18071 if (regmask
== umips_swm_mask
[i
])
18077 /* Return the assembly instruction for microMIPS LWM or SWM.
18078 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
18081 umips_output_save_restore (bool save_p
, rtx pattern
)
18083 static char buffer
[300];
18086 HOST_WIDE_INT offset
;
18087 rtx base
, mem
, set
, last_set
, last_reg
;
18089 /* Parse the pattern. */
18090 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
18092 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
18094 n
= XVECLEN (pattern
, 0);
18096 set
= XVECEXP (pattern
, 0, 0);
18097 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
18098 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
18100 last_set
= XVECEXP (pattern
, 0, n
- 1);
18101 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
18103 if (REGNO (last_reg
) == 31)
18106 gcc_assert (n
<= 9);
18110 s
+= sprintf (s
, "%s,", reg_names
[16]);
18112 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
18114 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
18117 if (REGNO (last_reg
) == 31)
18118 s
+= sprintf (s
, "%s,", reg_names
[31]);
18120 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
18124 /* Return true if MEM1 and MEM2 use the same base register, and the
18125 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
18126 register into (from) which the contents of MEM1 will be loaded
18127 (stored), depending on the value of LOAD_P.
18128 SWAP_P is true when the 1st and 2nd instructions are swapped. */
18131 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
18132 rtx first_reg
, rtx mem1
, rtx mem2
)
18135 HOST_WIDE_INT offset1
, offset2
;
18137 if (!MEM_P (mem1
) || !MEM_P (mem2
))
18140 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
18141 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
18143 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
18146 /* Avoid invalid load pair instructions. */
18147 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
18150 /* We must avoid this case for anti-dependence.
18153 first_reg is $2, but the base is $3. */
18156 && REGNO (first_reg
) + 1 == REGNO (base1
))
18159 if (offset2
!= offset1
+ 4)
18162 if (!UMIPS_12BIT_OFFSET_P (offset1
))
18169 mips_load_store_bonding_p (rtx
*operands
, machine_mode mode
, bool load_p
)
18171 rtx reg1
, reg2
, mem1
, mem2
, base1
, base2
;
18172 enum reg_class rc1
, rc2
;
18173 HOST_WIDE_INT offset1
, offset2
;
18177 reg1
= operands
[0];
18178 reg2
= operands
[2];
18179 mem1
= operands
[1];
18180 mem2
= operands
[3];
18184 reg1
= operands
[1];
18185 reg2
= operands
[3];
18186 mem1
= operands
[0];
18187 mem2
= operands
[2];
18190 if (mips_address_insns (XEXP (mem1
, 0), mode
, false) == 0
18191 || mips_address_insns (XEXP (mem2
, 0), mode
, false) == 0)
18194 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
18195 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
18197 /* Base regs do not match. */
18198 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
18201 /* Either of the loads is clobbering base register. It is legitimate to bond
18202 loads if second load clobbers base register. However, hardware does not
18203 support such bonding. */
18205 && (REGNO (reg1
) == REGNO (base1
)
18206 || (REGNO (reg2
) == REGNO (base1
))))
18209 /* Loading in same registers. */
18211 && REGNO (reg1
) == REGNO (reg2
))
18214 /* The loads/stores are not of same type. */
18215 rc1
= REGNO_REG_CLASS (REGNO (reg1
));
18216 rc2
= REGNO_REG_CLASS (REGNO (reg2
));
18218 && !reg_class_subset_p (rc1
, rc2
)
18219 && !reg_class_subset_p (rc2
, rc1
))
18222 if (abs (offset1
- offset2
) != GET_MODE_SIZE (mode
))
18228 /* OPERANDS describes the operands to a pair of SETs, in the order
18229 dest1, src1, dest2, src2. Return true if the operands can be used
18230 in an LWP or SWP instruction; LOAD_P says which. */
18233 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
18235 rtx reg1
, reg2
, mem1
, mem2
;
18239 reg1
= operands
[0];
18240 reg2
= operands
[2];
18241 mem1
= operands
[1];
18242 mem2
= operands
[3];
18246 reg1
= operands
[1];
18247 reg2
= operands
[3];
18248 mem1
= operands
[0];
18249 mem2
= operands
[2];
18252 if (REGNO (reg2
) == REGNO (reg1
) + 1)
18253 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
18255 if (REGNO (reg1
) == REGNO (reg2
) + 1)
18256 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
18261 /* Return the assembly instruction for a microMIPS LWP or SWP in which
18262 the first register is REG and the first memory slot is MEM.
18263 LOAD_P is true for LWP. */
18266 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
18268 rtx ops
[] = {reg
, mem
};
18271 output_asm_insn ("lwp\t%0,%1", ops
);
18273 output_asm_insn ("swp\t%0,%1", ops
);
18276 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
18277 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
18280 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
18282 rtx reg1
, reg2
, mem1
, mem2
;
18285 reg1
= operands
[0];
18286 reg2
= operands
[2];
18287 mem1
= operands
[1];
18288 mem2
= operands
[3];
18292 reg1
= operands
[1];
18293 reg2
= operands
[3];
18294 mem1
= operands
[0];
18295 mem2
= operands
[2];
18298 if (REGNO (reg2
) == REGNO (reg1
) + 1)
18300 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
18304 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
18305 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
18308 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
18311 umips_movep_target_p (rtx reg1
, rtx reg2
)
18313 int regno1
, regno2
, pair
;
18315 static const int match
[8] = {
18316 0x00000060, /* 5, 6 */
18317 0x000000a0, /* 5, 7 */
18318 0x000000c0, /* 6, 7 */
18319 0x00200010, /* 4, 21 */
18320 0x00400010, /* 4, 22 */
18321 0x00000030, /* 4, 5 */
18322 0x00000050, /* 4, 6 */
18323 0x00000090 /* 4, 7 */
18326 if (!REG_P (reg1
) || !REG_P (reg2
))
18329 regno1
= REGNO (reg1
);
18330 regno2
= REGNO (reg2
);
18332 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
18335 pair
= (1 << regno1
) | (1 << regno2
);
18337 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
18338 if (pair
== match
[i
])
18344 /* Return the size in bytes of the trampoline code, padded to
18345 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
18346 function address immediately follow. */
18349 mips_trampoline_code_size (void)
18351 if (TARGET_USE_PIC_FN_ADDR_REG
)
18353 else if (ptr_mode
== DImode
)
18355 else if (ISA_HAS_LOAD_DELAY
)
18361 /* Implement TARGET_TRAMPOLINE_INIT. */
18364 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
18366 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
18369 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
18371 /* Work out the offsets of the pointers from the start of the
18372 trampoline code. */
18373 end_addr_offset
= mips_trampoline_code_size ();
18374 static_chain_offset
= end_addr_offset
;
18375 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
18377 /* Get pointers to the beginning and end of the code block. */
18378 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
18379 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
18381 #define OP(X) gen_int_mode (X, SImode)
18383 /* Build up the code in TRAMPOLINE. */
18385 if (TARGET_USE_PIC_FN_ADDR_REG
)
18387 /* $25 contains the address of the trampoline. Emit code of the form:
18389 l[wd] $1, target_function_offset($25)
18390 l[wd] $static_chain, static_chain_offset($25)
18393 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
18394 target_function_offset
,
18395 PIC_FUNCTION_ADDR_REGNUM
));
18396 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18397 static_chain_offset
,
18398 PIC_FUNCTION_ADDR_REGNUM
));
18399 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
18400 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
18402 else if (ptr_mode
== DImode
)
18404 /* It's too cumbersome to create the full 64-bit address, so let's
18410 1: l[wd] $25, target_function_offset - 12($31)
18411 l[wd] $static_chain, static_chain_offset - 12($31)
18415 where 12 is the offset of "1:" from the start of the code block. */
18416 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
18417 trampoline
[i
++] = OP (MIPS_BAL (1));
18418 trampoline
[i
++] = OP (MIPS_NOP
);
18419 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18420 target_function_offset
- 12,
18421 RETURN_ADDR_REGNUM
));
18422 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18423 static_chain_offset
- 12,
18424 RETURN_ADDR_REGNUM
));
18425 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18426 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
18430 /* If the target has load delays, emit:
18432 lui $1, %hi(end_addr)
18433 lw $25, %lo(end_addr + ...)($1)
18434 lw $static_chain, %lo(end_addr + ...)($1)
18440 lui $1, %hi(end_addr)
18441 lw $25, %lo(end_addr + ...)($1)
18443 lw $static_chain, %lo(end_addr + ...)($1). */
18445 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18446 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18447 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
18448 NULL
, false, OPTAB_WIDEN
);
18449 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
18450 NULL
, false, OPTAB_WIDEN
);
18451 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
18453 /* Emit the LUI. */
18454 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
18455 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
18456 NULL
, false, OPTAB_WIDEN
);
18458 /* Emit the load of the target function. */
18459 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18460 target_function_offset
- end_addr_offset
,
18462 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18463 NULL
, false, OPTAB_WIDEN
);
18465 /* Emit the JR here, if we can. */
18466 if (!ISA_HAS_LOAD_DELAY
)
18467 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18469 /* Emit the load of the static chain register. */
18470 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18471 static_chain_offset
- end_addr_offset
,
18473 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18474 NULL
, false, OPTAB_WIDEN
);
18476 /* Emit the JR, if we couldn't above. */
18477 if (ISA_HAS_LOAD_DELAY
)
18479 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18480 trampoline
[i
++] = OP (MIPS_NOP
);
18486 /* Copy the trampoline code. Leave any padding uninitialized. */
18487 for (j
= 0; j
< i
; j
++)
18489 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
18490 mips_emit_move (mem
, trampoline
[j
]);
18493 /* Set up the static chain pointer field. */
18494 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
18495 mips_emit_move (mem
, chain_value
);
18497 /* Set up the target function field. */
18498 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
18499 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
18501 /* Flush the code part of the trampoline. */
18502 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
18503 emit_insn (gen_clear_cache (addr
, end_addr
));
18506 /* Implement FUNCTION_PROFILER. */
18508 void mips_function_profiler (FILE *file
)
18511 sorry ("mips16 function profiling");
18512 if (TARGET_LONG_CALLS
)
18514 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18515 if (Pmode
== DImode
)
18516 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
18518 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
18520 mips_push_asm_switch (&mips_noat
);
18521 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
18522 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
18523 /* _mcount treats $2 as the static chain register. */
18524 if (cfun
->static_chain_decl
!= NULL
)
18525 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
18526 reg_names
[STATIC_CHAIN_REGNUM
]);
18527 if (TARGET_MCOUNT_RA_ADDRESS
)
18529 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18530 ra save location. */
18531 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
18532 /* ra not saved, pass zero. */
18533 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
18535 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
18536 Pmode
== DImode
? "dla" : "la", reg_names
[12],
18537 cfun
->machine
->frame
.ra_fp_offset
,
18538 reg_names
[STACK_POINTER_REGNUM
]);
18540 if (!TARGET_NEWABI
)
18542 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18543 TARGET_64BIT
? "dsubu" : "subu",
18544 reg_names
[STACK_POINTER_REGNUM
],
18545 reg_names
[STACK_POINTER_REGNUM
],
18546 Pmode
== DImode
? 16 : 8);
18548 if (TARGET_LONG_CALLS
)
18549 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
18551 fprintf (file
, "\tjal\t_mcount\n");
18552 mips_pop_asm_switch (&mips_noat
);
18553 /* _mcount treats $2 as the static chain register. */
18554 if (cfun
->static_chain_decl
!= NULL
)
18555 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
18559 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18560 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18561 when TARGET_LOONGSON_VECTORS is true. */
18563 static unsigned HOST_WIDE_INT
18564 mips_shift_truncation_mask (machine_mode mode
)
18566 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
18569 return GET_MODE_BITSIZE (mode
) - 1;
18572 /* Implement TARGET_PREPARE_PCH_SAVE. */
18575 mips_prepare_pch_save (void)
18577 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18578 setting should be irrelevant. The question then is: which setting
18579 makes most sense at load time?
18581 The PCH is loaded before the first token is read. We should never
18582 have switched into MIPS16 mode by that point, and thus should not
18583 have populated mips16_globals. Nor can we load the entire contents
18584 of mips16_globals from the PCH file, because mips16_globals contains
18585 a combination of GGC and non-GGC data.
18587 There is therefore no point in trying save the GGC part of
18588 mips16_globals to the PCH file, or to preserve MIPS16ness across
18589 the PCH save and load. The loading compiler would not have access
18590 to the non-GGC parts of mips16_globals (either from the PCH file,
18591 or from a copy that the loading compiler generated itself) and would
18592 have to call target_reinit anyway.
18594 It therefore seems best to switch back to non-MIPS16 mode at
18595 save time, and to ensure that mips16_globals remains null after
18597 mips_set_compression_mode (0);
18598 mips16_globals
= 0;
18601 /* Generate or test for an insn that supports a constant permutation. */
18603 #define MAX_VECT_LEN 8
18605 struct expand_vec_perm_d
18607 rtx target
, op0
, op1
;
18608 unsigned char perm
[MAX_VECT_LEN
];
18609 machine_mode vmode
;
18610 unsigned char nelt
;
18615 /* Construct (set target (vec_select op0 (parallel perm))) and
18616 return true if that's a valid instruction in the active ISA. */
18619 mips_expand_vselect (rtx target
, rtx op0
,
18620 const unsigned char *perm
, unsigned nelt
)
18622 rtx rperm
[MAX_VECT_LEN
], x
;
18626 for (i
= 0; i
< nelt
; ++i
)
18627 rperm
[i
] = GEN_INT (perm
[i
]);
18629 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18630 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18631 x
= gen_rtx_SET (target
, x
);
18633 insn
= emit_insn (x
);
18634 if (recog_memoized (insn
) < 0)
18636 remove_insn (insn
);
18642 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18645 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18646 const unsigned char *perm
, unsigned nelt
)
18648 machine_mode v2mode
;
18651 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18652 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18653 return mips_expand_vselect (target
, x
, perm
, nelt
);
18656 /* Recognize patterns for even-odd extraction. */
18659 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18661 unsigned i
, odd
, nelt
= d
->nelt
;
18662 rtx t0
, t1
, t2
, t3
;
18664 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18666 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18673 for (i
= 1; i
< nelt
; ++i
)
18674 if (d
->perm
[i
] != i
* 2 + odd
)
18680 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18681 t0
= gen_reg_rtx (d
->vmode
);
18682 t1
= gen_reg_rtx (d
->vmode
);
18686 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18687 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18689 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18691 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18695 t2
= gen_reg_rtx (d
->vmode
);
18696 t3
= gen_reg_rtx (d
->vmode
);
18697 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18698 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18699 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18700 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18702 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18704 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18708 gcc_unreachable ();
18713 /* Recognize patterns for the Loongson PSHUFH instruction. */
18716 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18721 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18723 if (d
->vmode
!= V4HImode
)
18728 /* Convert the selector into the packed 8-bit form for pshufh. */
18729 /* Recall that loongson is little-endian only. No big-endian
18730 adjustment required. */
18731 for (i
= mask
= 0; i
< 4; i
++)
18732 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18733 rmask
= force_reg (SImode
, GEN_INT (mask
));
18735 if (d
->one_vector_p
)
18736 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18739 rtx t0
, t1
, x
, merge
, rmerge
[4];
18741 t0
= gen_reg_rtx (V4HImode
);
18742 t1
= gen_reg_rtx (V4HImode
);
18743 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18744 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18746 for (i
= 0; i
< 4; ++i
)
18747 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18748 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18749 merge
= force_reg (V4HImode
, merge
);
18751 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18752 emit_insn (gen_rtx_SET (t1
, x
));
18754 x
= gen_rtx_NOT (V4HImode
, merge
);
18755 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18756 emit_insn (gen_rtx_SET (t0
, x
));
18758 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18759 emit_insn (gen_rtx_SET (d
->target
, x
));
18765 /* Recognize broadcast patterns for the Loongson. */
18768 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18773 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18775 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18776 if (d
->vmode
!= V8QImode
)
18778 if (!d
->one_vector_p
)
18782 for (i
= 1; i
< 8; ++i
)
18783 if (d
->perm
[i
] != elt
)
18789 /* With one interleave we put two of the desired element adjacent. */
18790 t0
= gen_reg_rtx (V8QImode
);
18792 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18794 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18796 /* Shuffle that one HImode element into all locations. */
18799 t1
= gen_reg_rtx (V4HImode
);
18800 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18801 force_reg (SImode
, GEN_INT (elt
))));
18803 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18808 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18810 unsigned int i
, nelt
= d
->nelt
;
18811 unsigned char perm2
[MAX_VECT_LEN
];
18813 if (d
->one_vector_p
)
18815 /* Try interleave with alternating operands. */
18816 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18817 for (i
= 1; i
< nelt
; i
+= 2)
18819 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18824 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18828 /* Try again with swapped operands. */
18829 for (i
= 0; i
< nelt
; ++i
)
18830 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18831 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18835 if (mips_expand_vpc_loongson_even_odd (d
))
18837 if (mips_expand_vpc_loongson_pshufh (d
))
18839 if (mips_expand_vpc_loongson_bcast (d
))
18844 /* Expand a vec_perm_const pattern. */
18847 mips_expand_vec_perm_const (rtx operands
[4])
18849 struct expand_vec_perm_d d
;
18850 int i
, nelt
, which
;
18851 unsigned char orig_perm
[MAX_VECT_LEN
];
18855 d
.target
= operands
[0];
18856 d
.op0
= operands
[1];
18857 d
.op1
= operands
[2];
18860 d
.vmode
= GET_MODE (d
.target
);
18861 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18862 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18863 d
.testing_p
= false;
18865 for (i
= which
= 0; i
< nelt
; ++i
)
18867 rtx e
= XVECEXP (sel
, 0, i
);
18868 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18869 which
|= (ei
< nelt
? 1 : 2);
18872 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18880 d
.one_vector_p
= false;
18881 if (!rtx_equal_p (d
.op0
, d
.op1
))
18886 for (i
= 0; i
< nelt
; ++i
)
18887 d
.perm
[i
] &= nelt
- 1;
18889 d
.one_vector_p
= true;
18894 d
.one_vector_p
= true;
18898 ok
= mips_expand_vec_perm_const_1 (&d
);
18900 /* If we were given a two-vector permutation which just happened to
18901 have both input vectors equal, we folded this into a one-vector
18902 permutation. There are several loongson patterns that are matched
18903 via direct vec_select+vec_concat expansion, but we do not have
18904 support in mips_expand_vec_perm_const_1 to guess the adjustment
18905 that should be made for a single operand. Just try again with
18906 the original permutation. */
18907 if (!ok
&& which
== 3)
18909 d
.op0
= operands
[1];
18910 d
.op1
= operands
[2];
18911 d
.one_vector_p
= false;
18912 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18913 ok
= mips_expand_vec_perm_const_1 (&d
);
18919 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18922 mips_vectorize_vec_perm_const_ok (machine_mode vmode
,
18923 const unsigned char *sel
)
18925 struct expand_vec_perm_d d
;
18926 unsigned int i
, nelt
, which
;
18930 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18931 d
.testing_p
= true;
18932 memcpy (d
.perm
, sel
, nelt
);
18934 /* Categorize the set of elements in the selector. */
18935 for (i
= which
= 0; i
< nelt
; ++i
)
18937 unsigned char e
= d
.perm
[i
];
18938 gcc_assert (e
< 2 * nelt
);
18939 which
|= (e
< nelt
? 1 : 2);
18942 /* For all elements from second vector, fold the elements to first. */
18944 for (i
= 0; i
< nelt
; ++i
)
18947 /* Check whether the mask can be applied to the vector type. */
18948 d
.one_vector_p
= (which
!= 3);
18950 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18951 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18952 if (!d
.one_vector_p
)
18953 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18956 ret
= mips_expand_vec_perm_const_1 (&d
);
18962 /* Expand an integral vector unpack operation. */
18965 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18967 machine_mode imode
= GET_MODE (operands
[1]);
18968 rtx (*unpack
) (rtx
, rtx
, rtx
);
18969 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18970 rtx tmp
, dest
, zero
;
18976 unpack
= gen_loongson_punpckhbh
;
18978 unpack
= gen_loongson_punpcklbh
;
18979 cmpgt
= gen_loongson_pcmpgtb
;
18983 unpack
= gen_loongson_punpckhhw
;
18985 unpack
= gen_loongson_punpcklhw
;
18986 cmpgt
= gen_loongson_pcmpgth
;
18989 gcc_unreachable ();
18992 zero
= force_reg (imode
, CONST0_RTX (imode
));
18997 tmp
= gen_reg_rtx (imode
);
18998 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
19001 dest
= gen_reg_rtx (imode
);
19002 emit_insn (unpack (dest
, operands
[1], tmp
));
19004 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
19007 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
19010 mips_constant_elt_p (rtx x
)
19012 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
19015 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
19018 mips_expand_vi_broadcast (machine_mode vmode
, rtx target
, rtx elt
)
19020 struct expand_vec_perm_d d
;
19024 if (elt
!= const0_rtx
)
19025 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
19027 elt
= gen_lowpart (DImode
, elt
);
19029 t1
= gen_reg_rtx (vmode
);
19033 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
19036 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
19039 gcc_unreachable ();
19042 memset (&d
, 0, sizeof (d
));
19047 d
.nelt
= GET_MODE_NUNITS (vmode
);
19048 d
.one_vector_p
= true;
19050 ok
= mips_expand_vec_perm_const_1 (&d
);
19054 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
19055 elements of VALS with zeros, copy the constant vector to TARGET. */
19058 mips_expand_vi_constant (machine_mode vmode
, unsigned nelt
,
19059 rtx target
, rtx vals
)
19061 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
19064 for (i
= 0; i
< nelt
; ++i
)
19066 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
19067 RTVEC_ELT (vec
, i
) = const0_rtx
;
19070 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
19074 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
19077 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
19079 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
19081 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
19082 GEN_INT (one_var
)));
19085 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
19088 mips_expand_vi_general (machine_mode vmode
, machine_mode imode
,
19089 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
19091 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
19092 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
19095 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
19097 for (i
= 0; i
< nelt
; ++i
)
19099 rtx x
= XVECEXP (vals
, 0, i
);
19100 if (!mips_constant_elt_p (x
))
19101 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
19104 emit_move_insn (target
, mem
);
19107 /* Expand a vector initialization. */
19110 mips_expand_vector_init (rtx target
, rtx vals
)
19112 machine_mode vmode
= GET_MODE (target
);
19113 machine_mode imode
= GET_MODE_INNER (vmode
);
19114 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
19115 unsigned nvar
= 0, one_var
= -1u;
19116 bool all_same
= true;
19119 for (i
= 0; i
< nelt
; ++i
)
19121 x
= XVECEXP (vals
, 0, i
);
19122 if (!mips_constant_elt_p (x
))
19123 nvar
++, one_var
= i
;
19124 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
19128 /* Load constants from the pool, or whatever's handy. */
19131 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
19135 /* For two-part initialization, always use CONCAT. */
19138 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
19139 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
19140 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
19141 emit_insn (gen_rtx_SET (target
, x
));
19145 /* Loongson is the only cpu with vectors with more elements. */
19146 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
19148 /* If all values are identical, broadcast the value. */
19151 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
19155 /* If we've only got one non-variable V4HImode, use PINSRH. */
19156 if (nvar
== 1 && vmode
== V4HImode
)
19158 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
19162 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
19165 /* Expand a vector reduction. */
19168 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
19170 machine_mode vmode
= GET_MODE (in
);
19171 unsigned char perm2
[2];
19172 rtx last
, next
, fold
, x
;
19176 fold
= gen_reg_rtx (vmode
);
19180 /* Use PUL/PLU to produce { L, H } op { H, L }.
19181 By reversing the pair order, rather than a pure interleave high,
19182 we avoid erroneous exceptional conditions that we might otherwise
19183 produce from the computation of H op H. */
19186 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
19191 /* Use interleave to produce { H, L } op { H, H }. */
19192 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
19196 /* Perform the first reduction with interleave,
19197 and subsequent reductions with shifts. */
19198 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
19200 next
= gen_reg_rtx (vmode
);
19201 emit_insn (gen (next
, last
, fold
));
19204 fold
= gen_reg_rtx (vmode
);
19205 x
= force_reg (SImode
, GEN_INT (16));
19206 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
19210 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
19212 next
= gen_reg_rtx (vmode
);
19213 emit_insn (gen (next
, last
, fold
));
19216 fold
= gen_reg_rtx (vmode
);
19217 x
= force_reg (SImode
, GEN_INT (16));
19218 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
19220 next
= gen_reg_rtx (vmode
);
19221 emit_insn (gen (next
, last
, fold
));
19224 fold
= gen_reg_rtx (vmode
);
19225 x
= force_reg (SImode
, GEN_INT (8));
19226 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
19230 gcc_unreachable ();
19233 emit_insn (gen (target
, last
, fold
));
19236 /* Expand a vector minimum/maximum. */
19239 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
19240 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
19242 machine_mode vmode
= GET_MODE (target
);
19245 tc
= gen_reg_rtx (vmode
);
19246 t0
= gen_reg_rtx (vmode
);
19247 t1
= gen_reg_rtx (vmode
);
19250 emit_insn (cmp (tc
, op0
, op1
));
19252 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
19253 emit_insn (gen_rtx_SET (t0
, x
));
19255 x
= gen_rtx_NOT (vmode
, tc
);
19256 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
19257 emit_insn (gen_rtx_SET (t1
, x
));
19259 x
= gen_rtx_IOR (vmode
, t0
, t1
);
19260 emit_insn (gen_rtx_SET (target
, x
));
19263 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
19266 mips_hard_regno_caller_save_mode (unsigned int regno
,
19267 unsigned int nregs
,
19270 /* For performance, avoid saving/restoring upper parts of a register
19271 by returning MODE as save mode when the mode is known. */
19272 if (mode
== VOIDmode
)
19273 return choose_hard_reg_mode (regno
, nregs
, false);
19278 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
19281 mips_case_values_threshold (void)
19283 /* In MIPS16 mode using a larger case threshold generates smaller code. */
19284 if (TARGET_MIPS16
&& optimize_size
)
19287 return default_case_values_threshold ();
19290 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
19293 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
19295 if (!TARGET_HARD_FLOAT_ABI
)
19297 tree exceptions_var
= create_tmp_var (MIPS_ATYPE_USI
);
19298 tree fcsr_orig_var
= create_tmp_var (MIPS_ATYPE_USI
);
19299 tree fcsr_mod_var
= create_tmp_var (MIPS_ATYPE_USI
);
19300 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
19301 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
19302 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
19303 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19304 fcsr_orig_var
, get_fcsr_hold_call
);
19305 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
19306 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
19307 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19308 fcsr_mod_var
, hold_mod_val
);
19309 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
19310 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
19311 hold_assign_orig
, hold_assign_mod
);
19312 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
19313 set_fcsr_hold_call
);
19315 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
19317 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
19318 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19319 exceptions_var
, get_fcsr_update_call
);
19320 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
19321 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
19322 set_fcsr_update_call
);
19323 tree atomic_feraiseexcept
19324 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
19325 tree int_exceptions_var
= fold_convert (integer_type_node
,
19327 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
19328 1, int_exceptions_var
);
19329 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
19330 atomic_feraiseexcept_call
);
19333 /* Implement TARGET_SPILL_CLASS. */
19336 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED
,
19337 machine_mode mode ATTRIBUTE_UNUSED
)
19344 /* Implement TARGET_LRA_P. */
19349 return mips_lra_flag
;
19352 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
19355 mips_ira_change_pseudo_allocno_class (int regno
, reg_class_t allocno_class
)
19357 /* LRA will allocate an FPR for an integer mode pseudo instead of spilling
19358 to memory if an FPR is present in the allocno class. It is rare that
19359 we actually need to place an integer mode value in an FPR so where
19360 possible limit the allocation to GR_REGS. This will slightly pessimize
19361 code that involves integer to/from float conversions as these will have
19362 to reload into FPRs in LRA. Such reloads are sometimes eliminated and
19363 sometimes only partially eliminated. We choose to take this penalty
19364 in order to eliminate usage of FPRs in code that does not use floating
19367 This change has a similar effect to increasing the cost of FPR->GPR
19368 register moves for integer modes so that they are higher than the cost
19369 of memory but changing the allocno class is more reliable.
19371 This is also similar to forbidding integer mode values in FPRs entirely
19372 but this would lead to an inconsistency in the integer to/from float
19373 instructions that say integer mode values must be placed in FPRs. */
19374 if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno
)) && allocno_class
== ALL_REGS
)
19376 return allocno_class
;
19379 /* Initialize the GCC target structure. */
19380 #undef TARGET_ASM_ALIGNED_HI_OP
19381 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
19382 #undef TARGET_ASM_ALIGNED_SI_OP
19383 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
19384 #undef TARGET_ASM_ALIGNED_DI_OP
19385 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
19387 #undef TARGET_OPTION_OVERRIDE
19388 #define TARGET_OPTION_OVERRIDE mips_option_override
19390 #undef TARGET_LEGITIMIZE_ADDRESS
19391 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
19393 #undef TARGET_ASM_FUNCTION_PROLOGUE
19394 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
19395 #undef TARGET_ASM_FUNCTION_EPILOGUE
19396 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
19397 #undef TARGET_ASM_SELECT_RTX_SECTION
19398 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
19399 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
19400 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
19402 #undef TARGET_SCHED_INIT
19403 #define TARGET_SCHED_INIT mips_sched_init
19404 #undef TARGET_SCHED_REORDER
19405 #define TARGET_SCHED_REORDER mips_sched_reorder
19406 #undef TARGET_SCHED_REORDER2
19407 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
19408 #undef TARGET_SCHED_VARIABLE_ISSUE
19409 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
19410 #undef TARGET_SCHED_ADJUST_COST
19411 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
19412 #undef TARGET_SCHED_ISSUE_RATE
19413 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
19414 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
19415 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
19416 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
19417 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
19418 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
19419 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
19420 mips_multipass_dfa_lookahead
19421 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
19422 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
19423 mips_small_register_classes_for_mode_p
19425 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
19426 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
19428 #undef TARGET_INSERT_ATTRIBUTES
19429 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
19430 #undef TARGET_MERGE_DECL_ATTRIBUTES
19431 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
19432 #undef TARGET_CAN_INLINE_P
19433 #define TARGET_CAN_INLINE_P mips_can_inline_p
19434 #undef TARGET_SET_CURRENT_FUNCTION
19435 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
19437 #undef TARGET_VALID_POINTER_MODE
19438 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
19439 #undef TARGET_REGISTER_MOVE_COST
19440 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
19441 #undef TARGET_REGISTER_PRIORITY
19442 #define TARGET_REGISTER_PRIORITY mips_register_priority
19443 #undef TARGET_MEMORY_MOVE_COST
19444 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
19445 #undef TARGET_RTX_COSTS
19446 #define TARGET_RTX_COSTS mips_rtx_costs
19447 #undef TARGET_ADDRESS_COST
19448 #define TARGET_ADDRESS_COST mips_address_cost
19450 #undef TARGET_IN_SMALL_DATA_P
19451 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
19453 #undef TARGET_MACHINE_DEPENDENT_REORG
19454 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
19456 #undef TARGET_PREFERRED_RELOAD_CLASS
19457 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
19459 #undef TARGET_EXPAND_TO_RTL_HOOK
19460 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
19461 #undef TARGET_ASM_FILE_START
19462 #define TARGET_ASM_FILE_START mips_file_start
19463 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
19464 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
19465 #undef TARGET_ASM_CODE_END
19466 #define TARGET_ASM_CODE_END mips_code_end
19468 #undef TARGET_INIT_LIBFUNCS
19469 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
19471 #undef TARGET_BUILD_BUILTIN_VA_LIST
19472 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
19473 #undef TARGET_EXPAND_BUILTIN_VA_START
19474 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
19475 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
19476 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
19478 #undef TARGET_PROMOTE_FUNCTION_MODE
19479 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
19480 #undef TARGET_PROMOTE_PROTOTYPES
19481 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
19483 #undef TARGET_FUNCTION_VALUE
19484 #define TARGET_FUNCTION_VALUE mips_function_value
19485 #undef TARGET_LIBCALL_VALUE
19486 #define TARGET_LIBCALL_VALUE mips_libcall_value
19487 #undef TARGET_FUNCTION_VALUE_REGNO_P
19488 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19489 #undef TARGET_RETURN_IN_MEMORY
19490 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19491 #undef TARGET_RETURN_IN_MSB
19492 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19494 #undef TARGET_ASM_OUTPUT_MI_THUNK
19495 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19496 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19497 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19499 #undef TARGET_PRINT_OPERAND
19500 #define TARGET_PRINT_OPERAND mips_print_operand
19501 #undef TARGET_PRINT_OPERAND_ADDRESS
19502 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19503 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19504 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19506 #undef TARGET_SETUP_INCOMING_VARARGS
19507 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19508 #undef TARGET_STRICT_ARGUMENT_NAMING
19509 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19510 #undef TARGET_MUST_PASS_IN_STACK
19511 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19512 #undef TARGET_PASS_BY_REFERENCE
19513 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19514 #undef TARGET_CALLEE_COPIES
19515 #define TARGET_CALLEE_COPIES mips_callee_copies
19516 #undef TARGET_ARG_PARTIAL_BYTES
19517 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19518 #undef TARGET_FUNCTION_ARG
19519 #define TARGET_FUNCTION_ARG mips_function_arg
19520 #undef TARGET_FUNCTION_ARG_ADVANCE
19521 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19522 #undef TARGET_FUNCTION_ARG_BOUNDARY
19523 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19524 #undef TARGET_GET_RAW_RESULT_MODE
19525 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
19526 #undef TARGET_GET_RAW_ARG_MODE
19527 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
19529 #undef TARGET_MODE_REP_EXTENDED
19530 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19532 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19533 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19535 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19536 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19538 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19539 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19541 #undef TARGET_INIT_BUILTINS
19542 #define TARGET_INIT_BUILTINS mips_init_builtins
19543 #undef TARGET_BUILTIN_DECL
19544 #define TARGET_BUILTIN_DECL mips_builtin_decl
19545 #undef TARGET_EXPAND_BUILTIN
19546 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19548 #undef TARGET_HAVE_TLS
19549 #define TARGET_HAVE_TLS HAVE_AS_TLS
19551 #undef TARGET_CANNOT_FORCE_CONST_MEM
19552 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19554 #undef TARGET_LEGITIMATE_CONSTANT_P
19555 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19557 #undef TARGET_ENCODE_SECTION_INFO
19558 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19560 #undef TARGET_ATTRIBUTE_TABLE
19561 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19562 /* All our function attributes are related to how out-of-line copies should
19563 be compiled or called. They don't in themselves prevent inlining. */
19564 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19565 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19567 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19568 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19570 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19571 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19572 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19573 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19575 #undef TARGET_COMP_TYPE_ATTRIBUTES
19576 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19578 #ifdef HAVE_AS_DTPRELWORD
19579 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19580 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19582 #undef TARGET_DWARF_REGISTER_SPAN
19583 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19584 #undef TARGET_DWARF_FRAME_REG_MODE
19585 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
19587 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19588 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19590 #undef TARGET_LEGITIMATE_ADDRESS_P
19591 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19593 #undef TARGET_FRAME_POINTER_REQUIRED
19594 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19596 #undef TARGET_CAN_ELIMINATE
19597 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19599 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19600 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19602 #undef TARGET_TRAMPOLINE_INIT
19603 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19605 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19606 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19608 #undef TARGET_SHIFT_TRUNCATION_MASK
19609 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19611 #undef TARGET_PREPARE_PCH_SAVE
19612 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19614 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19615 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19617 #undef TARGET_CASE_VALUES_THRESHOLD
19618 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19620 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19621 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19623 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19624 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19626 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
19627 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
19628 mips_use_by_pieces_infrastructure_p
19630 #undef TARGET_SPILL_CLASS
19631 #define TARGET_SPILL_CLASS mips_spill_class
19632 #undef TARGET_LRA_P
19633 #define TARGET_LRA_P mips_lra_p
19634 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
19635 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
19637 struct gcc_target targetm
= TARGET_INITIALIZER
;
19639 #include "gt-mips.h"