1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "integrate.h"
54 #include "langhooks.h"
55 #include "cfglayout.h"
56 #include "sched-int.h"
59 #include "diagnostic.h"
60 #include "target-globals.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type
{
185 /* Macros to create an enumeration identifier for a function prototype. */
186 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
187 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
188 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
189 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
191 /* Classifies the prototype of a built-in function. */
192 enum mips_function_type
{
193 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
194 #include "config/mips/mips-ftypes.def"
195 #undef DEF_MIPS_FTYPE
199 /* Specifies how a built-in function should be converted into rtl. */
200 enum mips_builtin_type
{
201 /* The function corresponds directly to an .md pattern. The return
202 value is mapped to operand 0 and the arguments are mapped to
203 operands 1 and above. */
206 /* The function corresponds directly to an .md pattern. There is no return
207 value and the arguments are mapped to operands 0 and above. */
208 MIPS_BUILTIN_DIRECT_NO_TARGET
,
210 /* The function corresponds to a comparison instruction followed by
211 a mips_cond_move_tf_ps pattern. The first two arguments are the
212 values to compare and the second two arguments are the vector
213 operands for the movt.ps or movf.ps instruction (in assembly order). */
217 /* The function corresponds to a V2SF comparison instruction. Operand 0
218 of this instruction is the result of the comparison, which has mode
219 CCV2 or CCV4. The function arguments are mapped to operands 1 and
220 above. The function's return value is an SImode boolean that is
221 true under the following conditions:
223 MIPS_BUILTIN_CMP_ANY: one of the registers is true
224 MIPS_BUILTIN_CMP_ALL: all of the registers are true
225 MIPS_BUILTIN_CMP_LOWER: the first register is true
226 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
227 MIPS_BUILTIN_CMP_ANY
,
228 MIPS_BUILTIN_CMP_ALL
,
229 MIPS_BUILTIN_CMP_UPPER
,
230 MIPS_BUILTIN_CMP_LOWER
,
232 /* As above, but the instruction only sets a single $fcc register. */
233 MIPS_BUILTIN_CMP_SINGLE
,
235 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
236 MIPS_BUILTIN_BPOSGE32
239 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
240 #define MIPS_FP_CONDITIONS(MACRO) \
258 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
259 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
260 enum mips_fp_condition
{
261 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
264 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
265 #define STRINGIFY(X) #X
266 static const char *const mips_fp_conditions
[] = {
267 MIPS_FP_CONDITIONS (STRINGIFY
)
270 /* Information about a function's frame layout. */
271 struct GTY(()) mips_frame_info
{
272 /* The size of the frame in bytes. */
273 HOST_WIDE_INT total_size
;
275 /* The number of bytes allocated to variables. */
276 HOST_WIDE_INT var_size
;
278 /* The number of bytes allocated to outgoing function arguments. */
279 HOST_WIDE_INT args_size
;
281 /* The number of bytes allocated to the .cprestore slot, or 0 if there
283 HOST_WIDE_INT cprestore_size
;
285 /* Bit X is set if the function saves or restores GPR X. */
288 /* Likewise FPR X. */
291 /* Likewise doubleword accumulator X ($acX). */
292 unsigned int acc_mask
;
294 /* The number of GPRs, FPRs, doubleword accumulators and COP0
298 unsigned int num_acc
;
299 unsigned int num_cop0_regs
;
301 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
302 save slots from the top of the frame, or zero if no such slots are
304 HOST_WIDE_INT gp_save_offset
;
305 HOST_WIDE_INT fp_save_offset
;
306 HOST_WIDE_INT acc_save_offset
;
307 HOST_WIDE_INT cop0_save_offset
;
309 /* Likewise, but giving offsets from the bottom of the frame. */
310 HOST_WIDE_INT gp_sp_offset
;
311 HOST_WIDE_INT fp_sp_offset
;
312 HOST_WIDE_INT acc_sp_offset
;
313 HOST_WIDE_INT cop0_sp_offset
;
315 /* Similar, but the value passed to _mcount. */
316 HOST_WIDE_INT ra_fp_offset
;
318 /* The offset of arg_pointer_rtx from the bottom of the frame. */
319 HOST_WIDE_INT arg_pointer_offset
;
321 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
322 HOST_WIDE_INT hard_frame_pointer_offset
;
325 struct GTY(()) machine_function
{
326 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
327 rtx mips16_gp_pseudo_rtx
;
329 /* The number of extra stack bytes taken up by register varargs.
330 This area is allocated by the callee at the very top of the frame. */
333 /* The current frame information, calculated by mips_compute_frame_info. */
334 struct mips_frame_info frame
;
336 /* The register to use as the function's global pointer, or INVALID_REGNUM
337 if the function doesn't need one. */
338 unsigned int global_pointer
;
340 /* How many instructions it takes to load a label into $AT, or 0 if
341 this property hasn't yet been calculated. */
342 unsigned int load_label_num_insns
;
344 /* True if mips_adjust_insn_length should ignore an instruction's
346 bool ignore_hazard_length_p
;
348 /* True if the whole function is suitable for .set noreorder and
350 bool all_noreorder_p
;
352 /* True if the function has "inflexible" and "flexible" references
353 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
354 and mips_cfun_has_flexible_gp_ref_p for details. */
355 bool has_inflexible_gp_insn_p
;
356 bool has_flexible_gp_insn_p
;
358 /* True if the function's prologue must load the global pointer
359 value into pic_offset_table_rtx and store the same value in
360 the function's cprestore slot (if any). Even if this value
361 is currently false, we may decide to set it to true later;
362 see mips_must_initialize_gp_p () for details. */
363 bool must_initialize_gp_p
;
365 /* True if the current function must restore $gp after any potential
366 clobber. This value is only meaningful during the first post-epilogue
367 split_insns pass; see mips_must_initialize_gp_p () for details. */
368 bool must_restore_gp_when_clobbered_p
;
370 /* True if this is an interrupt handler. */
371 bool interrupt_handler_p
;
373 /* True if this is an interrupt handler that uses shadow registers. */
374 bool use_shadow_register_set_p
;
376 /* True if this is an interrupt handler that should keep interrupts
378 bool keep_interrupts_masked_p
;
380 /* True if this is an interrupt handler that should use DERET
382 bool use_debug_exception_return_p
;
385 /* Information about a single argument. */
386 struct mips_arg_info
{
387 /* True if the argument is passed in a floating-point register, or
388 would have been if we hadn't run out of registers. */
391 /* The number of words passed in registers, rounded up. */
392 unsigned int reg_words
;
394 /* For EABI, the offset of the first register from GP_ARG_FIRST or
395 FP_ARG_FIRST. For other ABIs, the offset of the first register from
396 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
397 comment for details).
399 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
401 unsigned int reg_offset
;
403 /* The number of words that must be passed on the stack, rounded up. */
404 unsigned int stack_words
;
406 /* The offset from the start of the stack overflow area of the argument's
407 first stack word. Only meaningful when STACK_WORDS is nonzero. */
408 unsigned int stack_offset
;
411 /* Information about an address described by mips_address_type.
417 REG is the base register and OFFSET is the constant offset.
420 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
421 is the type of symbol it references.
424 SYMBOL_TYPE is the type of symbol that the address references. */
425 struct mips_address_info
{
426 enum mips_address_type type
;
429 enum mips_symbol_type symbol_type
;
432 /* One stage in a constant building sequence. These sequences have
436 A = A CODE[1] VALUE[1]
437 A = A CODE[2] VALUE[2]
440 where A is an accumulator, each CODE[i] is a binary rtl operation
441 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
442 struct mips_integer_op
{
444 unsigned HOST_WIDE_INT value
;
447 /* The largest number of operations needed to load an integer constant.
448 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
449 When the lowest bit is clear, we can try, but reject a sequence with
450 an extra SLL at the end. */
451 #define MIPS_MAX_INTEGER_OPS 7
453 /* Information about a MIPS16e SAVE or RESTORE instruction. */
454 struct mips16e_save_restore_info
{
455 /* The number of argument registers saved by a SAVE instruction.
456 0 for RESTORE instructions. */
459 /* Bit X is set if the instruction saves or restores GPR X. */
462 /* The total number of bytes to allocate. */
466 /* Costs of various operations on the different architectures. */
468 struct mips_rtx_cost_data
470 unsigned short fp_add
;
471 unsigned short fp_mult_sf
;
472 unsigned short fp_mult_df
;
473 unsigned short fp_div_sf
;
474 unsigned short fp_div_df
;
475 unsigned short int_mult_si
;
476 unsigned short int_mult_di
;
477 unsigned short int_div_si
;
478 unsigned short int_div_di
;
479 unsigned short branch_cost
;
480 unsigned short memory_latency
;
483 /* Global variables for machine-dependent things. */
485 /* The -G setting, or the configuration's default small-data limit if
486 no -G option is given. */
487 static unsigned int mips_small_data_threshold
;
489 /* The number of file directives written by mips_output_filename. */
490 int num_source_filenames
;
492 /* The name that appeared in the last .file directive written by
493 mips_output_filename, or "" if mips_output_filename hasn't
494 written anything yet. */
495 const char *current_function_file
= "";
497 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
500 /* Arrays that map GCC register numbers to debugger register numbers. */
501 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
502 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
504 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
505 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
506 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
507 struct mips_asm_switch mips_noat
= { "at", 0 };
509 /* True if we're writing out a branch-likely instruction rather than a
511 static bool mips_branch_likely
;
513 /* The current instruction-set architecture. */
514 enum processor mips_arch
;
515 const struct mips_cpu_info
*mips_arch_info
;
517 /* The processor that we should tune the code for. */
518 enum processor mips_tune
;
519 const struct mips_cpu_info
*mips_tune_info
;
521 /* The ISA level associated with mips_arch. */
524 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
525 static const struct mips_cpu_info
*mips_isa_option_info
;
527 /* Which cost information to use. */
528 static const struct mips_rtx_cost_data
*mips_cost
;
530 /* The ambient target flags, excluding MASK_MIPS16. */
531 static int mips_base_target_flags
;
533 /* True if MIPS16 is the default mode. */
534 bool mips_base_mips16
;
536 /* The ambient values of other global variables. */
537 static int mips_base_schedule_insns
; /* flag_schedule_insns */
538 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
539 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
540 static int mips_base_align_loops
; /* align_loops */
541 static int mips_base_align_jumps
; /* align_jumps */
542 static int mips_base_align_functions
; /* align_functions */
544 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
545 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
547 /* Index C is true if character C is a valid PRINT_OPERAND punctation
549 static bool mips_print_operand_punct
[256];
551 static GTY (()) int mips_output_filename_first_time
= 1;
553 /* mips_split_p[X] is true if symbols of type X can be split by
554 mips_split_symbol. */
555 bool mips_split_p
[NUM_SYMBOL_TYPES
];
557 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
558 can be split by mips_split_symbol. */
559 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
561 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
562 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
563 if they are matched by a special .md file pattern. */
564 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
566 /* Likewise for HIGHs. */
567 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
569 /* Target state for MIPS16. */
570 struct target_globals
*mips16_globals
;
572 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
573 and returned from mips_sched_reorder2. */
574 static int cached_can_issue_more
;
576 /* Index R is the smallest register class that contains register R. */
577 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
578 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
579 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
580 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
581 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
582 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
583 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
584 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
585 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
586 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
587 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
588 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
589 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
590 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
591 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
592 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
593 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
594 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
595 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
596 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
597 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
598 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
599 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
600 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
601 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
602 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
603 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
604 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
605 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
606 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
607 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
608 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
609 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
610 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
611 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
612 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
613 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
614 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
615 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
616 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
617 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
618 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
619 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
620 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
621 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
622 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
623 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
624 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
627 /* The value of TARGET_ATTRIBUTE_TABLE. */
628 static const struct attribute_spec mips_attribute_table
[] = {
629 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
631 { "long_call", 0, 0, false, true, true, NULL
, false },
632 { "far", 0, 0, false, true, true, NULL
, false },
633 { "near", 0, 0, false, true, true, NULL
, false },
634 /* We would really like to treat "mips16" and "nomips16" as type
635 attributes, but GCC doesn't provide the hooks we need to support
636 the right conversion rules. As declaration attributes, they affect
637 code generation but don't carry other semantics. */
638 { "mips16", 0, 0, true, false, false, NULL
, false },
639 { "nomips16", 0, 0, true, false, false, NULL
, false },
640 /* Allow functions to be specified as interrupt handlers */
641 { "interrupt", 0, 0, false, true, true, NULL
, false },
642 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
643 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
644 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
645 { NULL
, 0, 0, false, false, false, NULL
, false }
648 /* A table describing all the processors GCC knows about; see
649 mips-cpus.def for details. */
650 static const struct mips_cpu_info mips_cpu_info_table
[] = {
651 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
652 { NAME, CPU, ISA, FLAGS },
653 #include "mips-cpus.def"
657 /* Default costs. If these are used for a processor we should look
658 up the actual costs. */
659 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
660 COSTS_N_INSNS (7), /* fp_mult_sf */ \
661 COSTS_N_INSNS (8), /* fp_mult_df */ \
662 COSTS_N_INSNS (23), /* fp_div_sf */ \
663 COSTS_N_INSNS (36), /* fp_div_df */ \
664 COSTS_N_INSNS (10), /* int_mult_si */ \
665 COSTS_N_INSNS (10), /* int_mult_di */ \
666 COSTS_N_INSNS (69), /* int_div_si */ \
667 COSTS_N_INSNS (69), /* int_div_di */ \
668 2, /* branch_cost */ \
669 4 /* memory_latency */
671 /* Floating-point costs for processors without an FPU. Just assume that
672 all floating-point libcalls are very expensive. */
673 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
674 COSTS_N_INSNS (256), /* fp_mult_sf */ \
675 COSTS_N_INSNS (256), /* fp_mult_df */ \
676 COSTS_N_INSNS (256), /* fp_div_sf */ \
677 COSTS_N_INSNS (256) /* fp_div_df */
679 /* Costs to use when optimizing for size. */
680 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
681 COSTS_N_INSNS (1), /* fp_add */
682 COSTS_N_INSNS (1), /* fp_mult_sf */
683 COSTS_N_INSNS (1), /* fp_mult_df */
684 COSTS_N_INSNS (1), /* fp_div_sf */
685 COSTS_N_INSNS (1), /* fp_div_df */
686 COSTS_N_INSNS (1), /* int_mult_si */
687 COSTS_N_INSNS (1), /* int_mult_di */
688 COSTS_N_INSNS (1), /* int_div_si */
689 COSTS_N_INSNS (1), /* int_div_di */
691 4 /* memory_latency */
694 /* Costs to use when optimizing for speed, indexed by processor. */
695 static const struct mips_rtx_cost_data
696 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
698 COSTS_N_INSNS (2), /* fp_add */
699 COSTS_N_INSNS (4), /* fp_mult_sf */
700 COSTS_N_INSNS (5), /* fp_mult_df */
701 COSTS_N_INSNS (12), /* fp_div_sf */
702 COSTS_N_INSNS (19), /* fp_div_df */
703 COSTS_N_INSNS (12), /* int_mult_si */
704 COSTS_N_INSNS (12), /* int_mult_di */
705 COSTS_N_INSNS (35), /* int_div_si */
706 COSTS_N_INSNS (35), /* int_div_di */
708 4 /* memory_latency */
712 COSTS_N_INSNS (6), /* int_mult_si */
713 COSTS_N_INSNS (6), /* int_mult_di */
714 COSTS_N_INSNS (36), /* int_div_si */
715 COSTS_N_INSNS (36), /* int_div_di */
717 4 /* memory_latency */
721 COSTS_N_INSNS (36), /* int_mult_si */
722 COSTS_N_INSNS (36), /* int_mult_di */
723 COSTS_N_INSNS (37), /* int_div_si */
724 COSTS_N_INSNS (37), /* int_div_di */
726 4 /* memory_latency */
730 COSTS_N_INSNS (4), /* int_mult_si */
731 COSTS_N_INSNS (11), /* int_mult_di */
732 COSTS_N_INSNS (36), /* int_div_si */
733 COSTS_N_INSNS (68), /* int_div_di */
735 4 /* memory_latency */
738 COSTS_N_INSNS (4), /* fp_add */
739 COSTS_N_INSNS (4), /* fp_mult_sf */
740 COSTS_N_INSNS (5), /* fp_mult_df */
741 COSTS_N_INSNS (17), /* fp_div_sf */
742 COSTS_N_INSNS (32), /* fp_div_df */
743 COSTS_N_INSNS (4), /* int_mult_si */
744 COSTS_N_INSNS (11), /* int_mult_di */
745 COSTS_N_INSNS (36), /* int_div_si */
746 COSTS_N_INSNS (68), /* int_div_di */
748 4 /* memory_latency */
751 COSTS_N_INSNS (4), /* fp_add */
752 COSTS_N_INSNS (4), /* fp_mult_sf */
753 COSTS_N_INSNS (5), /* fp_mult_df */
754 COSTS_N_INSNS (17), /* fp_div_sf */
755 COSTS_N_INSNS (32), /* fp_div_df */
756 COSTS_N_INSNS (4), /* int_mult_si */
757 COSTS_N_INSNS (7), /* int_mult_di */
758 COSTS_N_INSNS (42), /* int_div_si */
759 COSTS_N_INSNS (72), /* int_div_di */
761 4 /* memory_latency */
765 COSTS_N_INSNS (5), /* int_mult_si */
766 COSTS_N_INSNS (5), /* int_mult_di */
767 COSTS_N_INSNS (41), /* int_div_si */
768 COSTS_N_INSNS (41), /* int_div_di */
770 4 /* memory_latency */
773 COSTS_N_INSNS (8), /* fp_add */
774 COSTS_N_INSNS (8), /* fp_mult_sf */
775 COSTS_N_INSNS (10), /* fp_mult_df */
776 COSTS_N_INSNS (34), /* fp_div_sf */
777 COSTS_N_INSNS (64), /* fp_div_df */
778 COSTS_N_INSNS (5), /* int_mult_si */
779 COSTS_N_INSNS (5), /* int_mult_di */
780 COSTS_N_INSNS (41), /* int_div_si */
781 COSTS_N_INSNS (41), /* int_div_di */
783 4 /* memory_latency */
786 COSTS_N_INSNS (4), /* fp_add */
787 COSTS_N_INSNS (4), /* fp_mult_sf */
788 COSTS_N_INSNS (5), /* fp_mult_df */
789 COSTS_N_INSNS (17), /* fp_div_sf */
790 COSTS_N_INSNS (32), /* fp_div_df */
791 COSTS_N_INSNS (5), /* int_mult_si */
792 COSTS_N_INSNS (5), /* int_mult_di */
793 COSTS_N_INSNS (41), /* int_div_si */
794 COSTS_N_INSNS (41), /* int_div_di */
796 4 /* memory_latency */
800 COSTS_N_INSNS (5), /* int_mult_si */
801 COSTS_N_INSNS (5), /* int_mult_di */
802 COSTS_N_INSNS (41), /* int_div_si */
803 COSTS_N_INSNS (41), /* int_div_di */
805 4 /* memory_latency */
808 COSTS_N_INSNS (8), /* fp_add */
809 COSTS_N_INSNS (8), /* fp_mult_sf */
810 COSTS_N_INSNS (10), /* fp_mult_df */
811 COSTS_N_INSNS (34), /* fp_div_sf */
812 COSTS_N_INSNS (64), /* fp_div_df */
813 COSTS_N_INSNS (5), /* int_mult_si */
814 COSTS_N_INSNS (5), /* int_mult_di */
815 COSTS_N_INSNS (41), /* int_div_si */
816 COSTS_N_INSNS (41), /* int_div_di */
818 4 /* memory_latency */
821 COSTS_N_INSNS (4), /* fp_add */
822 COSTS_N_INSNS (4), /* fp_mult_sf */
823 COSTS_N_INSNS (5), /* fp_mult_df */
824 COSTS_N_INSNS (17), /* fp_div_sf */
825 COSTS_N_INSNS (32), /* fp_div_df */
826 COSTS_N_INSNS (5), /* int_mult_si */
827 COSTS_N_INSNS (5), /* int_mult_di */
828 COSTS_N_INSNS (41), /* int_div_si */
829 COSTS_N_INSNS (41), /* int_div_di */
831 4 /* memory_latency */
834 COSTS_N_INSNS (6), /* fp_add */
835 COSTS_N_INSNS (6), /* fp_mult_sf */
836 COSTS_N_INSNS (7), /* fp_mult_df */
837 COSTS_N_INSNS (25), /* fp_div_sf */
838 COSTS_N_INSNS (48), /* fp_div_df */
839 COSTS_N_INSNS (5), /* int_mult_si */
840 COSTS_N_INSNS (5), /* int_mult_di */
841 COSTS_N_INSNS (41), /* int_div_si */
842 COSTS_N_INSNS (41), /* int_div_di */
844 4 /* memory_latency */
861 COSTS_N_INSNS (5), /* int_mult_si */
862 COSTS_N_INSNS (5), /* int_mult_di */
863 COSTS_N_INSNS (72), /* int_div_si */
864 COSTS_N_INSNS (72), /* int_div_di */
866 4 /* memory_latency */
869 COSTS_N_INSNS (2), /* fp_add */
870 COSTS_N_INSNS (4), /* fp_mult_sf */
871 COSTS_N_INSNS (5), /* fp_mult_df */
872 COSTS_N_INSNS (12), /* fp_div_sf */
873 COSTS_N_INSNS (19), /* fp_div_df */
874 COSTS_N_INSNS (2), /* int_mult_si */
875 COSTS_N_INSNS (2), /* int_mult_di */
876 COSTS_N_INSNS (35), /* int_div_si */
877 COSTS_N_INSNS (35), /* int_div_di */
879 4 /* memory_latency */
882 COSTS_N_INSNS (3), /* fp_add */
883 COSTS_N_INSNS (5), /* fp_mult_sf */
884 COSTS_N_INSNS (6), /* fp_mult_df */
885 COSTS_N_INSNS (15), /* fp_div_sf */
886 COSTS_N_INSNS (16), /* fp_div_df */
887 COSTS_N_INSNS (17), /* int_mult_si */
888 COSTS_N_INSNS (17), /* int_mult_di */
889 COSTS_N_INSNS (38), /* int_div_si */
890 COSTS_N_INSNS (38), /* int_div_di */
892 6 /* memory_latency */
895 COSTS_N_INSNS (6), /* fp_add */
896 COSTS_N_INSNS (7), /* fp_mult_sf */
897 COSTS_N_INSNS (8), /* fp_mult_df */
898 COSTS_N_INSNS (23), /* fp_div_sf */
899 COSTS_N_INSNS (36), /* fp_div_df */
900 COSTS_N_INSNS (10), /* int_mult_si */
901 COSTS_N_INSNS (10), /* int_mult_di */
902 COSTS_N_INSNS (69), /* int_div_si */
903 COSTS_N_INSNS (69), /* int_div_di */
905 6 /* memory_latency */
917 /* The only costs that appear to be updated here are
918 integer multiplication. */
920 COSTS_N_INSNS (4), /* int_mult_si */
921 COSTS_N_INSNS (6), /* int_mult_di */
922 COSTS_N_INSNS (69), /* int_div_si */
923 COSTS_N_INSNS (69), /* int_div_di */
925 4 /* memory_latency */
937 COSTS_N_INSNS (6), /* fp_add */
938 COSTS_N_INSNS (4), /* fp_mult_sf */
939 COSTS_N_INSNS (5), /* fp_mult_df */
940 COSTS_N_INSNS (23), /* fp_div_sf */
941 COSTS_N_INSNS (36), /* fp_div_df */
942 COSTS_N_INSNS (5), /* int_mult_si */
943 COSTS_N_INSNS (5), /* int_mult_di */
944 COSTS_N_INSNS (36), /* int_div_si */
945 COSTS_N_INSNS (36), /* int_div_di */
947 4 /* memory_latency */
950 COSTS_N_INSNS (6), /* fp_add */
951 COSTS_N_INSNS (5), /* fp_mult_sf */
952 COSTS_N_INSNS (6), /* fp_mult_df */
953 COSTS_N_INSNS (30), /* fp_div_sf */
954 COSTS_N_INSNS (59), /* fp_div_df */
955 COSTS_N_INSNS (3), /* int_mult_si */
956 COSTS_N_INSNS (4), /* int_mult_di */
957 COSTS_N_INSNS (42), /* int_div_si */
958 COSTS_N_INSNS (74), /* int_div_di */
960 4 /* memory_latency */
963 COSTS_N_INSNS (6), /* fp_add */
964 COSTS_N_INSNS (5), /* fp_mult_sf */
965 COSTS_N_INSNS (6), /* fp_mult_df */
966 COSTS_N_INSNS (30), /* fp_div_sf */
967 COSTS_N_INSNS (59), /* fp_div_df */
968 COSTS_N_INSNS (5), /* int_mult_si */
969 COSTS_N_INSNS (9), /* int_mult_di */
970 COSTS_N_INSNS (42), /* int_div_si */
971 COSTS_N_INSNS (74), /* int_div_di */
973 4 /* memory_latency */
976 /* The only costs that are changed here are
977 integer multiplication. */
978 COSTS_N_INSNS (6), /* fp_add */
979 COSTS_N_INSNS (7), /* fp_mult_sf */
980 COSTS_N_INSNS (8), /* fp_mult_df */
981 COSTS_N_INSNS (23), /* fp_div_sf */
982 COSTS_N_INSNS (36), /* fp_div_df */
983 COSTS_N_INSNS (5), /* int_mult_si */
984 COSTS_N_INSNS (9), /* int_mult_di */
985 COSTS_N_INSNS (69), /* int_div_si */
986 COSTS_N_INSNS (69), /* int_div_di */
988 4 /* memory_latency */
994 /* The only costs that are changed here are
995 integer multiplication. */
996 COSTS_N_INSNS (6), /* fp_add */
997 COSTS_N_INSNS (7), /* fp_mult_sf */
998 COSTS_N_INSNS (8), /* fp_mult_df */
999 COSTS_N_INSNS (23), /* fp_div_sf */
1000 COSTS_N_INSNS (36), /* fp_div_df */
1001 COSTS_N_INSNS (3), /* int_mult_si */
1002 COSTS_N_INSNS (8), /* int_mult_di */
1003 COSTS_N_INSNS (69), /* int_div_si */
1004 COSTS_N_INSNS (69), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 COSTS_N_INSNS (2), /* fp_add */
1010 COSTS_N_INSNS (2), /* fp_mult_sf */
1011 COSTS_N_INSNS (2), /* fp_mult_df */
1012 COSTS_N_INSNS (12), /* fp_div_sf */
1013 COSTS_N_INSNS (19), /* fp_div_df */
1014 COSTS_N_INSNS (5), /* int_mult_si */
1015 COSTS_N_INSNS (9), /* int_mult_di */
1016 COSTS_N_INSNS (34), /* int_div_si */
1017 COSTS_N_INSNS (66), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1022 /* These costs are the same as the SB-1A below. */
1023 COSTS_N_INSNS (4), /* fp_add */
1024 COSTS_N_INSNS (4), /* fp_mult_sf */
1025 COSTS_N_INSNS (4), /* fp_mult_df */
1026 COSTS_N_INSNS (24), /* fp_div_sf */
1027 COSTS_N_INSNS (32), /* fp_div_df */
1028 COSTS_N_INSNS (3), /* int_mult_si */
1029 COSTS_N_INSNS (4), /* int_mult_di */
1030 COSTS_N_INSNS (36), /* int_div_si */
1031 COSTS_N_INSNS (68), /* int_div_di */
1032 1, /* branch_cost */
1033 4 /* memory_latency */
1036 /* These costs are the same as the SB-1 above. */
1037 COSTS_N_INSNS (4), /* fp_add */
1038 COSTS_N_INSNS (4), /* fp_mult_sf */
1039 COSTS_N_INSNS (4), /* fp_mult_df */
1040 COSTS_N_INSNS (24), /* fp_div_sf */
1041 COSTS_N_INSNS (32), /* fp_div_df */
1042 COSTS_N_INSNS (3), /* int_mult_si */
1043 COSTS_N_INSNS (4), /* int_mult_di */
1044 COSTS_N_INSNS (36), /* int_div_si */
1045 COSTS_N_INSNS (68), /* int_div_di */
1046 1, /* branch_cost */
1047 4 /* memory_latency */
1054 COSTS_N_INSNS (8), /* int_mult_si */
1055 COSTS_N_INSNS (8), /* int_mult_di */
1056 COSTS_N_INSNS (72), /* int_div_si */
1057 COSTS_N_INSNS (72), /* int_div_di */
1058 1, /* branch_cost */
1059 4 /* memory_latency */
1063 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1064 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1066 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1068 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1069 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1070 struct GTY (()) mflip_mips16_entry
{
1074 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1076 /* Hash table callbacks for mflip_mips16_htab. */
1079 mflip_mips16_htab_hash (const void *entry
)
1081 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1085 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1087 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1088 (const char *) name
) == 0;
1091 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1092 mode, false if it should next add an attribute for the opposite mode. */
1093 static GTY(()) bool mips16_flipper
;
1095 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1096 for -mflip-mips16. Return true if it should use "mips16" and false if
1097 it should use "nomips16". */
1100 mflip_mips16_use_mips16_p (tree decl
)
1102 struct mflip_mips16_entry
*entry
;
1107 /* Use the opposite of the command-line setting for anonymous decls. */
1108 if (!DECL_NAME (decl
))
1109 return !mips_base_mips16
;
1111 if (!mflip_mips16_htab
)
1112 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1113 mflip_mips16_htab_eq
, NULL
);
1115 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1116 hash
= htab_hash_string (name
);
1117 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1118 entry
= (struct mflip_mips16_entry
*) *slot
;
1121 mips16_flipper
= !mips16_flipper
;
1122 entry
= ggc_alloc_mflip_mips16_entry ();
1124 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1127 return entry
->mips16_p
;
1130 /* Predicates to test for presence of "near" and "far"/"long_call"
1131 attributes on the given TYPE. */
1134 mips_near_type_p (const_tree type
)
1136 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1140 mips_far_type_p (const_tree type
)
1142 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1143 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1146 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1149 mips_mips16_decl_p (const_tree decl
)
1151 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1155 mips_nomips16_decl_p (const_tree decl
)
1157 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1160 /* Check if the interrupt attribute is set for a function. */
1163 mips_interrupt_type_p (tree type
)
1165 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1168 /* Check if the attribute to use shadow register set is set for a function. */
1171 mips_use_shadow_register_set_p (tree type
)
1173 return lookup_attribute ("use_shadow_register_set",
1174 TYPE_ATTRIBUTES (type
)) != NULL
;
1177 /* Check if the attribute to keep interrupts masked is set for a function. */
1180 mips_keep_interrupts_masked_p (tree type
)
1182 return lookup_attribute ("keep_interrupts_masked",
1183 TYPE_ATTRIBUTES (type
)) != NULL
;
1186 /* Check if the attribute to use debug exception return is set for
1190 mips_use_debug_exception_return_p (tree type
)
1192 return lookup_attribute ("use_debug_exception_return",
1193 TYPE_ATTRIBUTES (type
)) != NULL
;
1196 /* Return true if function DECL is a MIPS16 function. Return the ambient
1197 setting if DECL is null. */
1200 mips_use_mips16_mode_p (tree decl
)
1204 /* Nested functions must use the same frame pointer as their
1205 parent and must therefore use the same ISA mode. */
1206 tree parent
= decl_function_context (decl
);
1209 if (mips_mips16_decl_p (decl
))
1211 if (mips_nomips16_decl_p (decl
))
1214 return mips_base_mips16
;
1217 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1220 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1222 /* Disallow mixed near/far attributes. */
1223 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1225 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1230 /* Implement TARGET_INSERT_ATTRIBUTES. */
1233 mips_insert_attributes (tree decl
, tree
*attributes
)
1236 bool mips16_p
, nomips16_p
;
1238 /* Check for "mips16" and "nomips16" attributes. */
1239 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1240 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1241 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1244 error ("%qs attribute only applies to functions", "mips16");
1246 error ("%qs attribute only applies to functions", "nomips16");
1250 mips16_p
|= mips_mips16_decl_p (decl
);
1251 nomips16_p
|= mips_nomips16_decl_p (decl
);
1252 if (mips16_p
|| nomips16_p
)
1254 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1255 if (mips16_p
&& nomips16_p
)
1256 error ("%qE cannot have both %<mips16%> and "
1257 "%<nomips16%> attributes",
1260 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1262 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1263 "mips16" attribute, arbitrarily pick one. We must pick the same
1264 setting for duplicate declarations of a function. */
1265 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1266 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1271 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1274 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1276 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1277 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1278 error ("%qE redeclared with conflicting %qs attributes",
1279 DECL_NAME (newdecl
), "mips16");
1280 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1281 error ("%qE redeclared with conflicting %qs attributes",
1282 DECL_NAME (newdecl
), "nomips16");
1284 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1285 DECL_ATTRIBUTES (newdecl
));
1288 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1289 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1292 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1294 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1296 *base_ptr
= XEXP (x
, 0);
1297 *offset_ptr
= INTVAL (XEXP (x
, 1));
1306 static unsigned int mips_build_integer (struct mips_integer_op
*,
1307 unsigned HOST_WIDE_INT
);
1309 /* A subroutine of mips_build_integer, with the same interface.
1310 Assume that the final action in the sequence should be a left shift. */
1313 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1315 unsigned int i
, shift
;
1317 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1318 since signed numbers are easier to load than unsigned ones. */
1320 while ((value
& 1) == 0)
1321 value
/= 2, shift
++;
1323 i
= mips_build_integer (codes
, value
);
1324 codes
[i
].code
= ASHIFT
;
1325 codes
[i
].value
= shift
;
1329 /* As for mips_build_shift, but assume that the final action will be
1330 an IOR or PLUS operation. */
1333 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1335 unsigned HOST_WIDE_INT high
;
1338 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1339 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1341 /* The constant is too complex to load with a simple LUI/ORI pair,
1342 so we want to give the recursive call as many trailing zeros as
1343 possible. In this case, we know bit 16 is set and that the
1344 low 16 bits form a negative number. If we subtract that number
1345 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1346 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1347 codes
[i
].code
= PLUS
;
1348 codes
[i
].value
= CONST_LOW_PART (value
);
1352 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1353 bits gives a value with at least 17 trailing zeros. */
1354 i
= mips_build_integer (codes
, high
);
1355 codes
[i
].code
= IOR
;
1356 codes
[i
].value
= value
& 0xffff;
1361 /* Fill CODES with a sequence of rtl operations to load VALUE.
1362 Return the number of operations needed. */
1365 mips_build_integer (struct mips_integer_op
*codes
,
1366 unsigned HOST_WIDE_INT value
)
1368 if (SMALL_OPERAND (value
)
1369 || SMALL_OPERAND_UNSIGNED (value
)
1370 || LUI_OPERAND (value
))
1372 /* The value can be loaded with a single instruction. */
1373 codes
[0].code
= UNKNOWN
;
1374 codes
[0].value
= value
;
1377 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1379 /* Either the constant is a simple LUI/ORI combination or its
1380 lowest bit is set. We don't want to shift in this case. */
1381 return mips_build_lower (codes
, value
);
1383 else if ((value
& 0xffff) == 0)
1385 /* The constant will need at least three actions. The lowest
1386 16 bits are clear, so the final action will be a shift. */
1387 return mips_build_shift (codes
, value
);
1391 /* The final action could be a shift, add or inclusive OR.
1392 Rather than use a complex condition to select the best
1393 approach, try both mips_build_shift and mips_build_lower
1394 and pick the one that gives the shortest sequence.
1395 Note that this case is only used once per constant. */
1396 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1397 unsigned int cost
, alt_cost
;
1399 cost
= mips_build_shift (codes
, value
);
1400 alt_cost
= mips_build_lower (alt_codes
, value
);
1401 if (alt_cost
< cost
)
1403 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1410 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1413 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1415 return mips_const_insns (x
) > 0;
1418 /* Return true if symbols of type TYPE require a GOT access. */
1421 mips_got_symbol_type_p (enum mips_symbol_type type
)
1425 case SYMBOL_GOT_PAGE_OFST
:
1426 case SYMBOL_GOT_DISP
:
1434 /* Return true if X is a thread-local symbol. */
1437 mips_tls_symbol_p (rtx x
)
1439 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1442 /* Return true if SYMBOL_REF X is associated with a global symbol
1443 (in the STB_GLOBAL sense). */
1446 mips_global_symbol_p (const_rtx x
)
1448 const_tree decl
= SYMBOL_REF_DECL (x
);
1451 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1453 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1454 or weak symbols. Relocations in the object file will be against
1455 the target symbol, so it's that symbol's binding that matters here. */
1456 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1459 /* Return true if function X is a libgcc MIPS16 stub function. */
1462 mips16_stub_function_p (const_rtx x
)
1464 return (GET_CODE (x
) == SYMBOL_REF
1465 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1468 /* Return true if function X is a locally-defined and locally-binding
1472 mips16_local_function_p (const_rtx x
)
1474 return (GET_CODE (x
) == SYMBOL_REF
1475 && SYMBOL_REF_LOCAL_P (x
)
1476 && !SYMBOL_REF_EXTERNAL_P (x
)
1477 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x
)));
1480 /* Return true if SYMBOL_REF X binds locally. */
1483 mips_symbol_binds_local_p (const_rtx x
)
1485 return (SYMBOL_REF_DECL (x
)
1486 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1487 : SYMBOL_REF_LOCAL_P (x
));
1490 /* Return true if rtx constants of mode MODE should be put into a small
1494 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1496 return (!TARGET_EMBEDDED_DATA
1497 && TARGET_LOCAL_SDATA
1498 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1501 /* Return true if X should not be moved directly into register $25.
1502 We need this because many versions of GAS will treat "la $25,foo" as
1503 part of a call sequence and so allow a global "foo" to be lazily bound. */
1506 mips_dangerous_for_la25_p (rtx x
)
1508 return (!TARGET_EXPLICIT_RELOCS
1510 && GET_CODE (x
) == SYMBOL_REF
1511 && mips_global_symbol_p (x
));
1514 /* Return true if calls to X might need $25 to be valid on entry. */
1517 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1519 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1522 /* MIPS16 stub functions are guaranteed not to use $25. */
1523 if (mips16_stub_function_p (x
))
1526 if (GET_CODE (x
) == SYMBOL_REF
)
1528 /* If PLTs and copy relocations are available, the static linker
1529 will make sure that $25 is valid on entry to the target function. */
1530 if (TARGET_ABICALLS_PIC0
)
1533 /* Locally-defined functions use absolute accesses to set up
1534 the global pointer. */
1535 if (TARGET_ABSOLUTE_ABICALLS
1536 && mips_symbol_binds_local_p (x
)
1537 && !SYMBOL_REF_EXTERNAL_P (x
))
1544 /* Return the method that should be used to access SYMBOL_REF or
1545 LABEL_REF X in context CONTEXT. */
1547 static enum mips_symbol_type
1548 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1551 return SYMBOL_GOT_DISP
;
1553 if (GET_CODE (x
) == LABEL_REF
)
1555 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1556 code and if we know that the label is in the current function's
1557 text section. LABEL_REFs are used for jump tables as well as
1558 text labels, so we must check whether jump tables live in the
1560 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1561 && !LABEL_REF_NONLOCAL_P (x
))
1562 return SYMBOL_PC_RELATIVE
;
1564 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1565 return SYMBOL_GOT_PAGE_OFST
;
1567 return SYMBOL_ABSOLUTE
;
1570 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1572 if (SYMBOL_REF_TLS_MODEL (x
))
1575 if (CONSTANT_POOL_ADDRESS_P (x
))
1577 if (TARGET_MIPS16_TEXT_LOADS
)
1578 return SYMBOL_PC_RELATIVE
;
1580 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1581 return SYMBOL_PC_RELATIVE
;
1583 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1584 return SYMBOL_GP_RELATIVE
;
1587 /* Do not use small-data accesses for weak symbols; they may end up
1589 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1590 return SYMBOL_GP_RELATIVE
;
1592 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1594 if (TARGET_ABICALLS_PIC2
1595 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1597 /* There are three cases to consider:
1599 - o32 PIC (either with or without explicit relocs)
1600 - n32/n64 PIC without explicit relocs
1601 - n32/n64 PIC with explicit relocs
1603 In the first case, both local and global accesses will use an
1604 R_MIPS_GOT16 relocation. We must correctly predict which of
1605 the two semantics (local or global) the assembler and linker
1606 will apply. The choice depends on the symbol's binding rather
1607 than its visibility.
1609 In the second case, the assembler will not use R_MIPS_GOT16
1610 relocations, but it chooses between local and global accesses
1611 in the same way as for o32 PIC.
1613 In the third case we have more freedom since both forms of
1614 access will work for any kind of symbol. However, there seems
1615 little point in doing things differently. */
1616 if (mips_global_symbol_p (x
))
1617 return SYMBOL_GOT_DISP
;
1619 return SYMBOL_GOT_PAGE_OFST
;
1622 if (TARGET_MIPS16_PCREL_LOADS
&& context
!= SYMBOL_CONTEXT_CALL
)
1623 return SYMBOL_FORCE_TO_MEM
;
1625 return SYMBOL_ABSOLUTE
;
1628 /* Classify the base of symbolic expression X, given that X appears in
1631 static enum mips_symbol_type
1632 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1636 split_const (x
, &x
, &offset
);
1637 if (UNSPEC_ADDRESS_P (x
))
1638 return UNSPEC_ADDRESS_TYPE (x
);
1640 return mips_classify_symbol (x
, context
);
1643 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1644 is the alignment in bytes of SYMBOL_REF X. */
1647 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1649 HOST_WIDE_INT align
;
1651 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1652 return IN_RANGE (offset
, 0, align
- 1);
1655 /* Return true if X is a symbolic constant that can be used in context
1656 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1659 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1660 enum mips_symbol_type
*symbol_type
)
1664 split_const (x
, &x
, &offset
);
1665 if (UNSPEC_ADDRESS_P (x
))
1667 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1668 x
= UNSPEC_ADDRESS (x
);
1670 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1672 *symbol_type
= mips_classify_symbol (x
, context
);
1673 if (*symbol_type
== SYMBOL_TLS
)
1679 if (offset
== const0_rtx
)
1682 /* Check whether a nonzero offset is valid for the underlying
1684 switch (*symbol_type
)
1686 case SYMBOL_ABSOLUTE
:
1687 case SYMBOL_FORCE_TO_MEM
:
1688 case SYMBOL_32_HIGH
:
1689 case SYMBOL_64_HIGH
:
1692 /* If the target has 64-bit pointers and the object file only
1693 supports 32-bit symbols, the values of those symbols will be
1694 sign-extended. In this case we can't allow an arbitrary offset
1695 in case the 32-bit value X + OFFSET has a different sign from X. */
1696 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1697 return offset_within_block_p (x
, INTVAL (offset
));
1699 /* In other cases the relocations can handle any offset. */
1702 case SYMBOL_PC_RELATIVE
:
1703 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1704 In this case, we no longer have access to the underlying constant,
1705 but the original symbol-based access was known to be valid. */
1706 if (GET_CODE (x
) == LABEL_REF
)
1711 case SYMBOL_GP_RELATIVE
:
1712 /* Make sure that the offset refers to something within the
1713 same object block. This should guarantee that the final
1714 PC- or GP-relative offset is within the 16-bit limit. */
1715 return offset_within_block_p (x
, INTVAL (offset
));
1717 case SYMBOL_GOT_PAGE_OFST
:
1718 case SYMBOL_GOTOFF_PAGE
:
1719 /* If the symbol is global, the GOT entry will contain the symbol's
1720 address, and we will apply a 16-bit offset after loading it.
1721 If the symbol is local, the linker should provide enough local
1722 GOT entries for a 16-bit offset, but larger offsets may lead
1724 return SMALL_INT (offset
);
1728 /* There is no carry between the HI and LO REL relocations, so the
1729 offset is only valid if we know it won't lead to such a carry. */
1730 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1732 case SYMBOL_GOT_DISP
:
1733 case SYMBOL_GOTOFF_DISP
:
1734 case SYMBOL_GOTOFF_CALL
:
1735 case SYMBOL_GOTOFF_LOADGP
:
1738 case SYMBOL_GOTTPREL
:
1746 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1747 single instruction. We rely on the fact that, in the worst case,
1748 all instructions involved in a MIPS16 address calculation are usually
1752 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1756 case SYMBOL_ABSOLUTE
:
1757 /* When using 64-bit symbols, we need 5 preparatory instructions,
1760 lui $at,%highest(symbol)
1761 daddiu $at,$at,%higher(symbol)
1763 daddiu $at,$at,%hi(symbol)
1766 The final address is then $at + %lo(symbol). With 32-bit
1767 symbols we just need a preparatory LUI for normal mode and
1768 a preparatory LI and SLL for MIPS16. */
1769 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1771 case SYMBOL_GP_RELATIVE
:
1772 /* Treat GP-relative accesses as taking a single instruction on
1773 MIPS16 too; the copy of $gp can often be shared. */
1776 case SYMBOL_PC_RELATIVE
:
1777 /* PC-relative constants can be only be used with ADDIUPC,
1778 DADDIUPC, LWPC and LDPC. */
1779 if (mode
== MAX_MACHINE_MODE
1780 || GET_MODE_SIZE (mode
) == 4
1781 || GET_MODE_SIZE (mode
) == 8)
1784 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1787 case SYMBOL_FORCE_TO_MEM
:
1788 /* LEAs will be converted into constant-pool references by
1790 if (mode
== MAX_MACHINE_MODE
)
1793 /* The constant must be loaded and then dereferenced. */
1796 case SYMBOL_GOT_DISP
:
1797 /* The constant will have to be loaded from the GOT before it
1798 is used in an address. */
1799 if (mode
!= MAX_MACHINE_MODE
)
1804 case SYMBOL_GOT_PAGE_OFST
:
1805 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1806 local/global classification is accurate. The worst cases are:
1808 (1) For local symbols when generating o32 or o64 code. The assembler
1814 ...and the final address will be $at + %lo(symbol).
1816 (2) For global symbols when -mxgot. The assembler will use:
1818 lui $at,%got_hi(symbol)
1821 ...and the final address will be $at + %got_lo(symbol). */
1824 case SYMBOL_GOTOFF_PAGE
:
1825 case SYMBOL_GOTOFF_DISP
:
1826 case SYMBOL_GOTOFF_CALL
:
1827 case SYMBOL_GOTOFF_LOADGP
:
1828 case SYMBOL_32_HIGH
:
1829 case SYMBOL_64_HIGH
:
1835 case SYMBOL_GOTTPREL
:
1838 /* A 16-bit constant formed by a single relocation, or a 32-bit
1839 constant formed from a high 16-bit relocation and a low 16-bit
1840 relocation. Use mips_split_p to determine which. 32-bit
1841 constants need an "lui; addiu" sequence for normal mode and
1842 an "li; sll; addiu" sequence for MIPS16 mode. */
1843 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1846 /* We don't treat a bare TLS symbol as a constant. */
1852 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1853 to load symbols of type TYPE into a register. Return 0 if the given
1854 type of symbol cannot be used as an immediate operand.
1856 Otherwise, return the number of instructions needed to load or store
1857 values of mode MODE to or from addresses of type TYPE. Return 0 if
1858 the given type of symbol is not valid in addresses.
1860 In both cases, treat extended MIPS16 instructions as two instructions. */
1863 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1865 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1868 /* A for_each_rtx callback. Stop the search if *X references a
1869 thread-local symbol. */
1872 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1874 return mips_tls_symbol_p (*x
);
1877 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1880 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
1882 enum mips_symbol_type type
;
1885 /* There is no assembler syntax for expressing an address-sized
1887 if (GET_CODE (x
) == HIGH
)
1890 /* As an optimization, reject constants that mips_legitimize_move
1893 Suppose we have a multi-instruction sequence that loads constant C
1894 into register R. If R does not get allocated a hard register, and
1895 R is used in an operand that allows both registers and memory
1896 references, reload will consider forcing C into memory and using
1897 one of the instruction's memory alternatives. Returning false
1898 here will force it to use an input reload instead. */
1899 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
1902 split_const (x
, &base
, &offset
);
1903 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
)
1904 && type
!= SYMBOL_FORCE_TO_MEM
)
1906 /* The same optimization as for CONST_INT. */
1907 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
1910 /* If MIPS16 constant pools live in the text section, they should
1911 not refer to anything that might need run-time relocation. */
1912 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
1916 /* TLS symbols must be computed by mips_legitimize_move. */
1917 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
1923 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1924 constants when we're using a per-function constant pool. */
1927 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1928 const_rtx x ATTRIBUTE_UNUSED
)
1930 return !TARGET_MIPS16_PCREL_LOADS
;
1933 /* Return true if register REGNO is a valid base register for mode MODE.
1934 STRICT_P is true if REG_OK_STRICT is in effect. */
1937 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
1940 if (!HARD_REGISTER_NUM_P (regno
))
1944 regno
= reg_renumber
[regno
];
1947 /* These fake registers will be eliminated to either the stack or
1948 hard frame pointer, both of which are usually valid base registers.
1949 Reload deals with the cases where the eliminated form isn't valid. */
1950 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
1953 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1954 values, nothing smaller. There are two problems here:
1956 (a) Instantiating virtual registers can introduce new uses of the
1957 stack pointer. If these virtual registers are valid addresses,
1958 the stack pointer should be too.
1960 (b) Most uses of the stack pointer are not made explicit until
1961 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1962 We don't know until that stage whether we'll be eliminating to the
1963 stack pointer (which needs the restriction) or the hard frame
1964 pointer (which doesn't).
1966 All in all, it seems more consistent to only enforce this restriction
1967 during and after reload. */
1968 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
1969 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1971 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
1974 /* Return true if X is a valid base register for mode MODE.
1975 STRICT_P is true if REG_OK_STRICT is in effect. */
1978 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
1980 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1984 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
1987 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1988 can address a value of mode MODE. */
1991 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
1993 /* Check that X is a signed 16-bit number. */
1994 if (!const_arith_operand (x
, Pmode
))
1997 /* We may need to split multiword moves, so make sure that every word
1999 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2000 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2006 /* Return true if a LO_SUM can address a value of mode MODE when the
2007 LO_SUM symbol has type SYMBOL_TYPE. */
2010 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2012 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2014 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2017 /* Check that there is a known low-part relocation. */
2018 if (mips_lo_relocs
[symbol_type
] == NULL
)
2021 /* We may need to split multiword moves, so make sure that each word
2022 can be accessed without inducing a carry. This is mainly needed
2023 for o64, which has historically only guaranteed 64-bit alignment
2024 for 128-bit types. */
2025 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2026 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2032 /* Return true if X is a valid address for machine mode MODE. If it is,
2033 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2037 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2038 enum machine_mode mode
, bool strict_p
)
2040 switch (GET_CODE (x
))
2044 info
->type
= ADDRESS_REG
;
2046 info
->offset
= const0_rtx
;
2047 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2050 info
->type
= ADDRESS_REG
;
2051 info
->reg
= XEXP (x
, 0);
2052 info
->offset
= XEXP (x
, 1);
2053 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2054 && mips_valid_offset_p (info
->offset
, mode
));
2057 info
->type
= ADDRESS_LO_SUM
;
2058 info
->reg
= XEXP (x
, 0);
2059 info
->offset
= XEXP (x
, 1);
2060 /* We have to trust the creator of the LO_SUM to do something vaguely
2061 sane. Target-independent code that creates a LO_SUM should also
2062 create and verify the matching HIGH. Target-independent code that
2063 adds an offset to a LO_SUM must prove that the offset will not
2064 induce a carry. Failure to do either of these things would be
2065 a bug, and we are not required to check for it here. The MIPS
2066 backend itself should only create LO_SUMs for valid symbolic
2067 constants, with the high part being either a HIGH or a copy
2070 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2071 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2072 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2075 /* Small-integer addresses don't occur very often, but they
2076 are legitimate if $0 is a valid base register. */
2077 info
->type
= ADDRESS_CONST_INT
;
2078 return !TARGET_MIPS16
&& SMALL_INT (x
);
2083 info
->type
= ADDRESS_SYMBOLIC
;
2084 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2086 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2087 && !mips_split_p
[info
->symbol_type
]);
2094 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2097 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2099 struct mips_address_info addr
;
2101 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2104 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2107 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2109 struct mips_address_info addr
;
2111 return (mips_classify_address (&addr
, x
, mode
, false)
2112 && addr
.type
== ADDRESS_REG
2113 && addr
.reg
== stack_pointer_rtx
);
2116 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2117 address instruction. Note that such addresses are not considered
2118 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2119 is so restricted. */
2122 mips_lwxs_address_p (rtx addr
)
2125 && GET_CODE (addr
) == PLUS
2126 && REG_P (XEXP (addr
, 1)))
2128 rtx offset
= XEXP (addr
, 0);
2129 if (GET_CODE (offset
) == MULT
2130 && REG_P (XEXP (offset
, 0))
2131 && CONST_INT_P (XEXP (offset
, 1))
2132 && INTVAL (XEXP (offset
, 1)) == 4)
2138 /* Return true if a value at OFFSET bytes from base register BASE can be
2139 accessed using an unextended MIPS16 instruction. MODE is the mode of
2142 Usually the offset in an unextended instruction is a 5-bit field.
2143 The offset is unsigned and shifted left once for LH and SH, twice
2144 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2145 an 8-bit immediate field that's shifted left twice. */
2148 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2149 unsigned HOST_WIDE_INT offset
)
2151 if (offset
% GET_MODE_SIZE (mode
) == 0)
2153 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2154 return offset
< 256U * GET_MODE_SIZE (mode
);
2155 return offset
< 32U * GET_MODE_SIZE (mode
);
2160 /* Return the number of instructions needed to load or store a value
2161 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2162 Assume that multiword moves may need to be split into word moves
2163 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2166 For MIPS16 code, count extended instructions as two instructions. */
2169 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2171 struct mips_address_info addr
;
2174 /* BLKmode is used for single unaligned loads and stores and should
2175 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2176 meaningless, so we have to single it out as a special case one way
2178 if (mode
!= BLKmode
&& might_split_p
)
2179 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2183 if (mips_classify_address (&addr
, x
, mode
, false))
2188 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2189 UINTVAL (addr
.offset
)))
2193 case ADDRESS_LO_SUM
:
2194 return TARGET_MIPS16
? factor
* 2 : factor
;
2196 case ADDRESS_CONST_INT
:
2199 case ADDRESS_SYMBOLIC
:
2200 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2205 /* Return the number of instructions needed to load constant X.
2206 Return 0 if X isn't a valid constant. */
2209 mips_const_insns (rtx x
)
2211 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2212 enum mips_symbol_type symbol_type
;
2215 switch (GET_CODE (x
))
2218 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2220 || !mips_split_p
[symbol_type
])
2223 /* This is simply an LUI for normal mode. It is an extended
2224 LI followed by an extended SLL for MIPS16. */
2225 return TARGET_MIPS16
? 4 : 1;
2229 /* Unsigned 8-bit constants can be loaded using an unextended
2230 LI instruction. Unsigned 16-bit constants can be loaded
2231 using an extended LI. Negative constants must be loaded
2232 using LI and then negated. */
2233 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2234 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2235 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2236 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2239 return mips_build_integer (codes
, INTVAL (x
));
2243 /* Allow zeros for normal mode, where we can use $0. */
2244 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2250 /* See if we can refer to X directly. */
2251 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2252 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2254 /* Otherwise try splitting the constant into a base and offset.
2255 If the offset is a 16-bit value, we can load the base address
2256 into a register and then use (D)ADDIU to add in the offset.
2257 If the offset is larger, we can load the base and offset
2258 into separate registers and add them together with (D)ADDU.
2259 However, the latter is only possible before reload; during
2260 and after reload, we must have the option of forcing the
2261 constant into the pool instead. */
2262 split_const (x
, &x
, &offset
);
2265 int n
= mips_const_insns (x
);
2268 if (SMALL_INT (offset
))
2270 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2271 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2278 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2286 /* X is a doubleword constant that can be handled by splitting it into
2287 two words and loading each word separately. Return the number of
2288 instructions required to do this. */
2291 mips_split_const_insns (rtx x
)
2293 unsigned int low
, high
;
2295 low
= mips_const_insns (mips_subword (x
, false));
2296 high
= mips_const_insns (mips_subword (x
, true));
2297 gcc_assert (low
> 0 && high
> 0);
2301 /* Return the number of instructions needed to implement INSN,
2302 given that it loads from or stores to MEM. Count extended
2303 MIPS16 instructions as two instructions. */
2306 mips_load_store_insns (rtx mem
, rtx insn
)
2308 enum machine_mode mode
;
2312 gcc_assert (MEM_P (mem
));
2313 mode
= GET_MODE (mem
);
2315 /* Try to prove that INSN does not need to be split. */
2316 might_split_p
= true;
2317 if (GET_MODE_BITSIZE (mode
) == 64)
2319 set
= single_set (insn
);
2320 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2321 might_split_p
= false;
2324 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2327 /* Return the number of instructions needed for an integer division. */
2330 mips_idiv_insns (void)
2335 if (TARGET_CHECK_ZERO_DIV
)
2337 if (GENERATE_DIVIDE_TRAPS
)
2343 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2348 /* Emit a move from SRC to DEST. Assume that the move expanders can
2349 handle all moves if !can_create_pseudo_p (). The distinction is
2350 important because, unlike emit_move_insn, the move expanders know
2351 how to force Pmode objects into the constant pool even when the
2352 constant pool address is not itself legitimate. */
2355 mips_emit_move (rtx dest
, rtx src
)
2357 return (can_create_pseudo_p ()
2358 ? emit_move_insn (dest
, src
)
2359 : emit_move_insn_1 (dest
, src
));
2362 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2365 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2367 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2368 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2371 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2372 Return that new register. */
2375 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2379 reg
= gen_reg_rtx (mode
);
2380 mips_emit_unary (code
, reg
, op0
);
2384 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2387 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2389 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2390 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2393 /* Compute (CODE OP0 OP1) and store the result in a new register
2394 of mode MODE. Return that new register. */
2397 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2401 reg
= gen_reg_rtx (mode
);
2402 mips_emit_binary (code
, reg
, op0
, op1
);
2406 /* Copy VALUE to a register and return that register. If new pseudos
2407 are allowed, copy it into a new register, otherwise use DEST. */
2410 mips_force_temporary (rtx dest
, rtx value
)
2412 if (can_create_pseudo_p ())
2413 return force_reg (Pmode
, value
);
2416 mips_emit_move (dest
, value
);
2421 /* Emit a call sequence with call pattern PATTERN and return the call
2422 instruction itself (which is not necessarily the last instruction
2423 emitted). ORIG_ADDR is the original, unlegitimized address,
2424 ADDR is the legitimized form, and LAZY_P is true if the call
2425 address is lazily-bound. */
2428 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2432 insn
= emit_call_insn (pattern
);
2434 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2436 /* MIPS16 JALRs only take MIPS16 registers. If the target
2437 function requires $25 to be valid on entry, we must copy it
2438 there separately. The move instruction can be put in the
2439 call's delay slot. */
2440 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2441 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2442 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2446 /* Lazy-binding stubs require $gp to be valid on entry. */
2447 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2451 /* See the comment above load_call<mode> for details. */
2452 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2453 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2454 emit_insn (gen_update_got_version ());
2459 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2460 then add CONST_INT OFFSET to the result. */
2463 mips_unspec_address_offset (rtx base
, rtx offset
,
2464 enum mips_symbol_type symbol_type
)
2466 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2467 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2468 if (offset
!= const0_rtx
)
2469 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2470 return gen_rtx_CONST (Pmode
, base
);
2473 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2474 type SYMBOL_TYPE. */
2477 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2481 split_const (address
, &base
, &offset
);
2482 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2485 /* If OP is an UNSPEC address, return the address to which it refers,
2486 otherwise return OP itself. */
2489 mips_strip_unspec_address (rtx op
)
2493 split_const (op
, &base
, &offset
);
2494 if (UNSPEC_ADDRESS_P (base
))
2495 op
= plus_constant (UNSPEC_ADDRESS (base
), INTVAL (offset
));
2499 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2500 high part to BASE and return the result. Just return BASE otherwise.
2501 TEMP is as for mips_force_temporary.
2503 The returned expression can be used as the first operand to a LO_SUM. */
2506 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2507 enum mips_symbol_type symbol_type
)
2509 if (mips_split_p
[symbol_type
])
2511 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2512 addr
= mips_force_temporary (temp
, addr
);
2513 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2518 /* Return an instruction that copies $gp into register REG. We want
2519 GCC to treat the register's value as constant, so that its value
2520 can be rematerialized on demand. */
2523 gen_load_const_gp (rtx reg
)
2525 return (Pmode
== SImode
2526 ? gen_load_const_gp_si (reg
)
2527 : gen_load_const_gp_di (reg
));
2530 /* Return a pseudo register that contains the value of $gp throughout
2531 the current function. Such registers are needed by MIPS16 functions,
2532 for which $gp itself is not a valid base register or addition operand. */
2535 mips16_gp_pseudo_reg (void)
2537 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2541 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2543 push_topmost_sequence ();
2545 scan
= get_insns ();
2546 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2547 scan
= NEXT_INSN (scan
);
2549 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2550 emit_insn_after (insn
, scan
);
2552 pop_topmost_sequence ();
2555 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2558 /* Return a base register that holds pic_offset_table_rtx.
2559 TEMP, if nonnull, is a scratch Pmode base register. */
2562 mips_pic_base_register (rtx temp
)
2565 return pic_offset_table_rtx
;
2567 if (currently_expanding_to_rtl
)
2568 return mips16_gp_pseudo_reg ();
2570 if (can_create_pseudo_p ())
2571 temp
= gen_reg_rtx (Pmode
);
2574 /* The first post-reload split exposes all references to $gp
2575 (both uses and definitions). All references must remain
2576 explicit after that point.
2578 It is safe to introduce uses of $gp at any time, so for
2579 simplicity, we do that before the split too. */
2580 mips_emit_move (temp
, pic_offset_table_rtx
);
2582 emit_insn (gen_load_const_gp (temp
));
2586 /* Return the RHS of a load_call<mode> insn. */
2589 mips_unspec_call (rtx reg
, rtx symbol
)
2593 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2594 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2597 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2598 reference. Return NULL_RTX otherwise. */
2601 mips_strip_unspec_call (rtx src
)
2603 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2604 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2608 /* Create and return a GOT reference of type TYPE for address ADDR.
2609 TEMP, if nonnull, is a scratch Pmode base register. */
2612 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2614 rtx base
, high
, lo_sum_symbol
;
2616 base
= mips_pic_base_register (temp
);
2618 /* If we used the temporary register to load $gp, we can't use
2619 it for the high part as well. */
2620 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2623 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2624 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2626 if (type
== SYMBOL_GOTOFF_CALL
)
2627 return mips_unspec_call (high
, lo_sum_symbol
);
2629 return (Pmode
== SImode
2630 ? gen_unspec_gotsi (high
, lo_sum_symbol
)
2631 : gen_unspec_gotdi (high
, lo_sum_symbol
));
2634 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2635 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2636 constant in that context and can be split into high and low parts.
2637 If so, and if LOW_OUT is nonnull, emit the high part and store the
2638 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2640 TEMP is as for mips_force_temporary and is used to load the high
2641 part into a register.
2643 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2644 a legitimize SET_SRC for an .md pattern, otherwise the low part
2645 is guaranteed to be a legitimate address for mode MODE. */
2648 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2650 enum mips_symbol_context context
;
2651 enum mips_symbol_type symbol_type
;
2654 context
= (mode
== MAX_MACHINE_MODE
2655 ? SYMBOL_CONTEXT_LEA
2656 : SYMBOL_CONTEXT_MEM
);
2657 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2659 addr
= XEXP (addr
, 0);
2660 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2661 && mips_symbol_insns (symbol_type
, mode
) > 0
2662 && mips_split_hi_p
[symbol_type
])
2665 switch (symbol_type
)
2667 case SYMBOL_GOT_PAGE_OFST
:
2668 /* The high part of a page/ofst pair is loaded from the GOT. */
2669 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2680 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2681 && mips_symbol_insns (symbol_type
, mode
) > 0
2682 && mips_split_p
[symbol_type
])
2685 switch (symbol_type
)
2687 case SYMBOL_GOT_DISP
:
2688 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2689 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2692 case SYMBOL_GP_RELATIVE
:
2693 high
= mips_pic_base_register (temp
);
2694 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2698 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2699 high
= mips_force_temporary (temp
, high
);
2700 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2709 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2710 mips_force_temporary; it is only needed when OFFSET is not a
2714 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2716 if (!SMALL_OPERAND (offset
))
2722 /* Load the full offset into a register so that we can use
2723 an unextended instruction for the address itself. */
2724 high
= GEN_INT (offset
);
2729 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2730 The addition inside the macro CONST_HIGH_PART may cause an
2731 overflow, so we need to force a sign-extension check. */
2732 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
2733 offset
= CONST_LOW_PART (offset
);
2735 high
= mips_force_temporary (temp
, high
);
2736 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2738 return plus_constant (reg
, offset
);
2741 /* The __tls_get_attr symbol. */
2742 static GTY(()) rtx mips_tls_symbol
;
2744 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2745 the TLS symbol we are referencing and TYPE is the symbol type to use
2746 (either global dynamic or local dynamic). V0 is an RTX for the
2747 return value location. */
2750 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2754 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2756 if (!mips_tls_symbol
)
2757 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2759 loc
= mips_unspec_address (sym
, type
);
2763 emit_insn (gen_rtx_SET (Pmode
, a0
,
2764 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2765 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
2766 const0_rtx
, NULL_RTX
, false);
2767 RTL_CONST_CALL_P (insn
) = 1;
2768 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2769 insn
= get_insns ();
2776 /* Return a pseudo register that contains the current thread pointer. */
2783 tp
= gen_reg_rtx (Pmode
);
2784 if (Pmode
== DImode
)
2785 emit_insn (gen_tls_get_tp_di (tp
));
2787 emit_insn (gen_tls_get_tp_si (tp
));
2791 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2792 its address. The return value will be both a valid address and a valid
2793 SET_SRC (either a REG or a LO_SUM). */
2796 mips_legitimize_tls_address (rtx loc
)
2798 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
;
2799 enum tls_model model
;
2803 sorry ("MIPS16 TLS");
2804 return gen_reg_rtx (Pmode
);
2807 model
= SYMBOL_REF_TLS_MODEL (loc
);
2808 /* Only TARGET_ABICALLS code can have more than one module; other
2809 code must be be static and should not use a GOT. All TLS models
2810 reduce to local exec in this situation. */
2811 if (!TARGET_ABICALLS
)
2812 model
= TLS_MODEL_LOCAL_EXEC
;
2816 case TLS_MODEL_GLOBAL_DYNAMIC
:
2817 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2818 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2819 dest
= gen_reg_rtx (Pmode
);
2820 emit_libcall_block (insn
, dest
, v0
, loc
);
2823 case TLS_MODEL_LOCAL_DYNAMIC
:
2824 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2825 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2826 tmp1
= gen_reg_rtx (Pmode
);
2828 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2829 share the LDM result with other LD model accesses. */
2830 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2832 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2834 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2835 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2836 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2839 case TLS_MODEL_INITIAL_EXEC
:
2840 tp
= mips_get_tp ();
2841 tmp1
= gen_reg_rtx (Pmode
);
2842 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2843 if (Pmode
== DImode
)
2844 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2846 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2847 dest
= gen_reg_rtx (Pmode
);
2848 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
2851 case TLS_MODEL_LOCAL_EXEC
:
2852 tp
= mips_get_tp ();
2853 tmp1
= mips_unspec_offset_high (NULL
, tp
, loc
, SYMBOL_TPREL
);
2854 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2855 mips_unspec_address (loc
, SYMBOL_TPREL
));
2864 /* If X is not a valid address for mode MODE, force it into a register. */
2867 mips_force_address (rtx x
, enum machine_mode mode
)
2869 if (!mips_legitimate_address_p (mode
, x
, false))
2870 x
= force_reg (Pmode
, x
);
2874 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2875 be legitimized in a way that the generic machinery might not expect,
2876 return a new address, otherwise return NULL. MODE is the mode of
2877 the memory being accessed. */
2880 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
2881 enum machine_mode mode
)
2884 HOST_WIDE_INT offset
;
2886 if (mips_tls_symbol_p (x
))
2887 return mips_legitimize_tls_address (x
);
2889 /* See if the address can split into a high part and a LO_SUM. */
2890 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
2891 return mips_force_address (addr
, mode
);
2893 /* Handle BASE + OFFSET using mips_add_offset. */
2894 mips_split_plus (x
, &base
, &offset
);
2897 if (!mips_valid_base_register_p (base
, mode
, false))
2898 base
= copy_to_mode_reg (Pmode
, base
);
2899 addr
= mips_add_offset (NULL
, base
, offset
);
2900 return mips_force_address (addr
, mode
);
2906 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2909 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
2911 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2912 enum machine_mode mode
;
2913 unsigned int i
, num_ops
;
2916 mode
= GET_MODE (dest
);
2917 num_ops
= mips_build_integer (codes
, value
);
2919 /* Apply each binary operation to X. Invariant: X is a legitimate
2920 source operand for a SET pattern. */
2921 x
= GEN_INT (codes
[0].value
);
2922 for (i
= 1; i
< num_ops
; i
++)
2924 if (!can_create_pseudo_p ())
2926 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
2930 x
= force_reg (mode
, x
);
2931 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
2934 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
2937 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2938 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2942 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
2946 /* Split moves of big integers into smaller pieces. */
2947 if (splittable_const_int_operand (src
, mode
))
2949 mips_move_integer (dest
, dest
, INTVAL (src
));
2953 /* Split moves of symbolic constants into high/low pairs. */
2954 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
2956 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
2960 /* Generate the appropriate access sequences for TLS symbols. */
2961 if (mips_tls_symbol_p (src
))
2963 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
2967 /* If we have (const (plus symbol offset)), and that expression cannot
2968 be forced into memory, load the symbol first and add in the offset.
2969 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2970 forced into memory, as it usually produces better code. */
2971 split_const (src
, &base
, &offset
);
2972 if (offset
!= const0_rtx
2973 && (targetm
.cannot_force_const_mem (mode
, src
)
2974 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
2976 base
= mips_force_temporary (dest
, base
);
2977 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
2981 src
= force_const_mem (mode
, src
);
2983 /* When using explicit relocs, constant pool references are sometimes
2984 not legitimate addresses. */
2985 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
2986 mips_emit_move (dest
, src
);
2989 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2990 sequence that is valid. */
2993 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
2995 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
2997 mips_emit_move (dest
, force_reg (mode
, src
));
3001 /* We need to deal with constants that would be legitimate
3002 immediate_operands but aren't legitimate move_operands. */
3003 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3005 mips_legitimize_const_move (mode
, dest
, src
);
3006 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3012 /* Return true if value X in context CONTEXT is a small-data address
3013 that can be rewritten as a LO_SUM. */
3016 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3018 enum mips_symbol_type symbol_type
;
3020 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3021 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3022 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3023 && symbol_type
== SYMBOL_GP_RELATIVE
);
3026 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3027 containing MEM, or null if none. */
3030 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3032 enum mips_symbol_context context
;
3034 if (GET_CODE (*loc
) == LO_SUM
)
3039 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3044 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3045 return mips_rewrite_small_data_p (*loc
, context
);
3048 /* Return true if OP refers to small data symbols directly, not through
3052 mips_small_data_pattern_p (rtx op
)
3054 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3057 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3058 DATA is the containing MEM, or null if none. */
3061 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3063 enum mips_symbol_context context
;
3067 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3071 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3072 if (mips_rewrite_small_data_p (*loc
, context
))
3073 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3075 if (GET_CODE (*loc
) == LO_SUM
)
3081 /* Rewrite instruction pattern PATTERN so that it refers to small data
3082 using explicit relocations. */
3085 mips_rewrite_small_data (rtx pattern
)
3087 pattern
= copy_insn (pattern
);
3088 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3092 /* We need a lot of little routines to check the range of MIPS16 immediate
3096 m16_check_op (rtx op
, int low
, int high
, int mask
)
3098 return (CONST_INT_P (op
)
3099 && IN_RANGE (INTVAL (op
), low
, high
)
3100 && (INTVAL (op
) & mask
) == 0);
3104 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3106 return m16_check_op (op
, 0x1, 0x8, 0);
3110 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3112 return m16_check_op (op
, -0x8, 0x7, 0);
3116 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3118 return m16_check_op (op
, -0x7, 0x8, 0);
3122 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3124 return m16_check_op (op
, -0x10, 0xf, 0);
3128 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3130 return m16_check_op (op
, -0xf, 0x10, 0);
3134 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3136 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
3140 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3142 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
3146 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3148 return m16_check_op (op
, -0x80, 0x7f, 0);
3152 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3154 return m16_check_op (op
, -0x7f, 0x80, 0);
3158 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3160 return m16_check_op (op
, 0x0, 0xff, 0);
3164 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3166 return m16_check_op (op
, -0xff, 0x0, 0);
3170 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3172 return m16_check_op (op
, -0x1, 0xfe, 0);
3176 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3178 return m16_check_op (op
, 0x0, 0xff << 2, 3);
3182 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3184 return m16_check_op (op
, -0xff << 2, 0x0, 3);
3188 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3190 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
3194 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3196 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
3199 /* The cost of loading values from the constant pool. It should be
3200 larger than the cost of any constant we want to synthesize inline. */
3201 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3203 /* Return the cost of X when used as an operand to the MIPS16 instruction
3204 that implements CODE. Return -1 if there is no such instruction, or if
3205 X is not a valid immediate operand for it. */
3208 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3215 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3216 other shifts are extended. The shift patterns truncate the shift
3217 count to the right size, so there are no out-of-range values. */
3218 if (IN_RANGE (x
, 1, 8))
3220 return COSTS_N_INSNS (1);
3223 if (IN_RANGE (x
, -128, 127))
3225 if (SMALL_OPERAND (x
))
3226 return COSTS_N_INSNS (1);
3230 /* Like LE, but reject the always-true case. */
3234 /* We add 1 to the immediate and use SLT. */
3237 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3240 if (IN_RANGE (x
, 0, 255))
3242 if (SMALL_OPERAND_UNSIGNED (x
))
3243 return COSTS_N_INSNS (1);
3248 /* Equality comparisons with 0 are cheap. */
3258 /* Return true if there is a non-MIPS16 instruction that implements CODE
3259 and if that instruction accepts X as an immediate operand. */
3262 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3269 /* All shift counts are truncated to a valid constant. */
3274 /* Likewise rotates, if the target supports rotates at all. */
3280 /* These instructions take 16-bit unsigned immediates. */
3281 return SMALL_OPERAND_UNSIGNED (x
);
3286 /* These instructions take 16-bit signed immediates. */
3287 return SMALL_OPERAND (x
);
3293 /* The "immediate" forms of these instructions are really
3294 implemented as comparisons with register 0. */
3299 /* Likewise, meaning that the only valid immediate operand is 1. */
3303 /* We add 1 to the immediate and use SLT. */
3304 return SMALL_OPERAND (x
+ 1);
3307 /* Likewise SLTU, but reject the always-true case. */
3308 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3312 /* The bit position and size are immediate operands. */
3313 return ISA_HAS_EXT_INS
;
3316 /* By default assume that $0 can be used for 0. */
3321 /* Return the cost of binary operation X, given that the instruction
3322 sequence for a word-sized or smaller operation has cost SINGLE_COST
3323 and that the sequence of a double-word operation has cost DOUBLE_COST.
3324 If SPEED is true, optimize for speed otherwise optimize for size. */
3327 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3331 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3336 + set_src_cost (XEXP (x
, 0), speed
)
3337 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3340 /* Return the cost of floating-point multiplications of mode MODE. */
3343 mips_fp_mult_cost (enum machine_mode mode
)
3345 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3348 /* Return the cost of floating-point divisions of mode MODE. */
3351 mips_fp_div_cost (enum machine_mode mode
)
3353 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3356 /* Return the cost of sign-extending OP to mode MODE, not including the
3357 cost of OP itself. */
3360 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3363 /* Extended loads are as cheap as unextended ones. */
3366 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3367 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3370 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3371 /* We can use SEB or SEH. */
3372 return COSTS_N_INSNS (1);
3374 /* We need to use a shift left and a shift right. */
3375 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3378 /* Return the cost of zero-extending OP to mode MODE, not including the
3379 cost of OP itself. */
3382 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3385 /* Extended loads are as cheap as unextended ones. */
3388 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3389 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3390 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3392 if (GENERATE_MIPS16E
)
3393 /* We can use ZEB or ZEH. */
3394 return COSTS_N_INSNS (1);
3397 /* We need to load 0xff or 0xffff into a register and use AND. */
3398 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3400 /* We can use ANDI. */
3401 return COSTS_N_INSNS (1);
3404 /* Implement TARGET_RTX_COSTS. */
3407 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3408 int *total
, bool speed
)
3410 enum machine_mode mode
= GET_MODE (x
);
3411 bool float_mode_p
= FLOAT_MODE_P (mode
);
3415 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3416 appear in the instruction stream, and the cost of a comparison is
3417 really the cost of the branch or scc condition. At the time of
3418 writing, GCC only uses an explicit outer COMPARE code when optabs
3419 is testing whether a constant is expensive enough to force into a
3420 register. We want optabs to pass such constants through the MIPS
3421 expanders instead, so make all constants very cheap here. */
3422 if (outer_code
== COMPARE
)
3424 gcc_assert (CONSTANT_P (x
));
3432 /* Treat *clear_upper32-style ANDs as having zero cost in the
3433 second operand. The cost is entirely in the first operand.
3435 ??? This is needed because we would otherwise try to CSE
3436 the constant operand. Although that's the right thing for
3437 instructions that continue to be a register operation throughout
3438 compilation, it is disastrous for instructions that could
3439 later be converted into a memory operation. */
3441 && outer_code
== AND
3442 && UINTVAL (x
) == 0xffffffff)
3450 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3459 /* When not optimizing for size, we care more about the cost
3460 of hot code, and hot code is often in a loop. If a constant
3461 operand needs to be forced into a register, we will often be
3462 able to hoist the constant load out of the loop, so the load
3463 should not contribute to the cost. */
3464 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3476 if (force_to_mem_operand (x
, VOIDmode
))
3478 *total
= COSTS_N_INSNS (1);
3481 cost
= mips_const_insns (x
);
3484 /* If the constant is likely to be stored in a GPR, SETs of
3485 single-insn constants are as cheap as register sets; we
3486 never want to CSE them.
3488 Don't reduce the cost of storing a floating-point zero in
3489 FPRs. If we have a zero in an FPR for other reasons, we
3490 can get better cfg-cleanup and delayed-branch results by
3491 using it consistently, rather than using $0 sometimes and
3492 an FPR at other times. Also, moves between floating-point
3493 registers are sometimes cheaper than (D)MTC1 $0. */
3495 && outer_code
== SET
3496 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3498 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3499 want to CSE the constant itself. It is usually better to
3500 have N copies of the last operation in the sequence and one
3501 shared copy of the other operations. (Note that this is
3502 not true for MIPS16 code, where the final operation in the
3503 sequence is often an extended instruction.)
3505 Also, if we have a CONST_INT, we don't know whether it is
3506 for a word or doubleword operation, so we cannot rely on
3507 the result of mips_build_integer. */
3508 else if (!TARGET_MIPS16
3509 && (outer_code
== SET
|| mode
== VOIDmode
))
3511 *total
= COSTS_N_INSNS (cost
);
3514 /* The value will need to be fetched from the constant pool. */
3515 *total
= CONSTANT_POOL_COST
;
3519 /* If the address is legitimate, return the number of
3520 instructions it needs. */
3522 cost
= mips_address_insns (addr
, mode
, true);
3525 *total
= COSTS_N_INSNS (cost
+ 1);
3528 /* Check for a scaled indexed address. */
3529 if (mips_lwxs_address_p (addr
))
3531 *total
= COSTS_N_INSNS (2);
3534 /* Otherwise use the default handling. */
3538 *total
= COSTS_N_INSNS (6);
3542 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3546 /* Check for a *clear_upper32 pattern and treat it like a zero
3547 extension. See the pattern's comment for details. */
3550 && CONST_INT_P (XEXP (x
, 1))
3551 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3553 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3554 + set_src_cost (XEXP (x
, 0), speed
));
3561 /* Double-word operations use two single-word operations. */
3562 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3571 if (CONSTANT_P (XEXP (x
, 1)))
3572 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3575 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3581 *total
= mips_cost
->fp_add
;
3583 *total
= COSTS_N_INSNS (4);
3587 /* Low-part immediates need an extended MIPS16 instruction. */
3588 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3589 + set_src_cost (XEXP (x
, 0), speed
));
3604 /* Branch comparisons have VOIDmode, so use the first operand's
3606 mode
= GET_MODE (XEXP (x
, 0));
3607 if (FLOAT_MODE_P (mode
))
3609 *total
= mips_cost
->fp_add
;
3612 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3618 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3619 && TARGET_FUSED_MADD
3620 && !HONOR_NANS (mode
)
3621 && !HONOR_SIGNED_ZEROS (mode
))
3623 /* See if we can use NMADD or NMSUB. See mips.md for the
3624 associated patterns. */
3625 rtx op0
= XEXP (x
, 0);
3626 rtx op1
= XEXP (x
, 1);
3627 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3629 *total
= (mips_fp_mult_cost (mode
)
3630 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3631 + set_src_cost (XEXP (op0
, 1), speed
)
3632 + set_src_cost (op1
, speed
));
3635 if (GET_CODE (op1
) == MULT
)
3637 *total
= (mips_fp_mult_cost (mode
)
3638 + set_src_cost (op0
, speed
)
3639 + set_src_cost (XEXP (op1
, 0), speed
)
3640 + set_src_cost (XEXP (op1
, 1), speed
));
3649 /* If this is part of a MADD or MSUB, treat the PLUS as
3652 && TARGET_FUSED_MADD
3653 && GET_CODE (XEXP (x
, 0)) == MULT
)
3656 *total
= mips_cost
->fp_add
;
3660 /* Double-word operations require three single-word operations and
3661 an SLTU. The MIPS16 version then needs to move the result of
3662 the SLTU from $24 to a MIPS16 register. */
3663 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3664 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3670 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3671 && TARGET_FUSED_MADD
3672 && !HONOR_NANS (mode
)
3673 && HONOR_SIGNED_ZEROS (mode
))
3675 /* See if we can use NMADD or NMSUB. See mips.md for the
3676 associated patterns. */
3677 rtx op
= XEXP (x
, 0);
3678 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3679 && GET_CODE (XEXP (op
, 0)) == MULT
)
3681 *total
= (mips_fp_mult_cost (mode
)
3682 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3683 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3684 + set_src_cost (XEXP (op
, 1), speed
));
3690 *total
= mips_cost
->fp_add
;
3692 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3697 *total
= mips_fp_mult_cost (mode
);
3698 else if (mode
== DImode
&& !TARGET_64BIT
)
3699 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3700 where the mulsidi3 always includes an MFHI and an MFLO. */
3702 ? mips_cost
->int_mult_si
* 3 + 6
3703 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3705 *total
= (ISA_HAS_MUL3
? 1 : 2);
3706 else if (mode
== DImode
)
3707 *total
= mips_cost
->int_mult_di
;
3709 *total
= mips_cost
->int_mult_si
;
3713 /* Check for a reciprocal. */
3716 && flag_unsafe_math_optimizations
3717 && XEXP (x
, 0) == CONST1_RTX (mode
))
3719 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3720 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3721 division as being free. */
3722 *total
= set_src_cost (XEXP (x
, 1), speed
);
3724 *total
= (mips_fp_div_cost (mode
)
3725 + set_src_cost (XEXP (x
, 1), speed
));
3734 *total
= mips_fp_div_cost (mode
);
3743 /* It is our responsibility to make division by a power of 2
3744 as cheap as 2 register additions if we want the division
3745 expanders to be used for such operations; see the setting
3746 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3747 should always produce shorter code than using
3748 expand_sdiv2_pow2. */
3750 && CONST_INT_P (XEXP (x
, 1))
3751 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3753 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
3756 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3758 else if (mode
== DImode
)
3759 *total
= mips_cost
->int_div_di
;
3761 *total
= mips_cost
->int_div_si
;
3765 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3769 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3773 case UNSIGNED_FLOAT
:
3776 case FLOAT_TRUNCATE
:
3777 *total
= mips_cost
->fp_add
;
3785 /* Implement TARGET_ADDRESS_COST. */
3788 mips_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
3790 return mips_address_insns (addr
, SImode
, false);
3793 /* Information about a single instruction in a multi-instruction
3795 struct mips_multi_member
{
3796 /* True if this is a label, false if it is code. */
3799 /* The output_asm_insn format of the instruction. */
3802 /* The operands to the instruction. */
3803 rtx operands
[MAX_RECOG_OPERANDS
];
3805 typedef struct mips_multi_member mips_multi_member
;
3807 /* Vector definitions for the above. */
3808 DEF_VEC_O(mips_multi_member
);
3809 DEF_VEC_ALLOC_O(mips_multi_member
, heap
);
3811 /* The instructions that make up the current multi-insn sequence. */
3812 static VEC (mips_multi_member
, heap
) *mips_multi_members
;
3814 /* How many instructions (as opposed to labels) are in the current
3815 multi-insn sequence. */
3816 static unsigned int mips_multi_num_insns
;
3818 /* Start a new multi-insn sequence. */
3821 mips_multi_start (void)
3823 VEC_truncate (mips_multi_member
, mips_multi_members
, 0);
3824 mips_multi_num_insns
= 0;
3827 /* Add a new, uninitialized member to the current multi-insn sequence. */
3829 static struct mips_multi_member
*
3830 mips_multi_add (void)
3832 return VEC_safe_push (mips_multi_member
, heap
, mips_multi_members
, 0);
3835 /* Add a normal insn with the given asm format to the current multi-insn
3836 sequence. The other arguments are a null-terminated list of operands. */
3839 mips_multi_add_insn (const char *format
, ...)
3841 struct mips_multi_member
*member
;
3846 member
= mips_multi_add ();
3847 member
->is_label_p
= false;
3848 member
->format
= format
;
3849 va_start (ap
, format
);
3851 while ((op
= va_arg (ap
, rtx
)))
3852 member
->operands
[i
++] = op
;
3854 mips_multi_num_insns
++;
3857 /* Add the given label definition to the current multi-insn sequence.
3858 The definition should include the colon. */
3861 mips_multi_add_label (const char *label
)
3863 struct mips_multi_member
*member
;
3865 member
= mips_multi_add ();
3866 member
->is_label_p
= true;
3867 member
->format
= label
;
3870 /* Return the index of the last member of the current multi-insn sequence. */
3873 mips_multi_last_index (void)
3875 return VEC_length (mips_multi_member
, mips_multi_members
) - 1;
3878 /* Add a copy of an existing instruction to the current multi-insn
3879 sequence. I is the index of the instruction that should be copied. */
3882 mips_multi_copy_insn (unsigned int i
)
3884 struct mips_multi_member
*member
;
3886 member
= mips_multi_add ();
3887 memcpy (member
, VEC_index (mips_multi_member
, mips_multi_members
, i
),
3889 gcc_assert (!member
->is_label_p
);
3892 /* Change the operand of an existing instruction in the current
3893 multi-insn sequence. I is the index of the instruction,
3894 OP is the index of the operand, and X is the new value. */
3897 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
3899 VEC_index (mips_multi_member
, mips_multi_members
, i
)->operands
[op
] = x
;
3902 /* Write out the asm code for the current multi-insn sequence. */
3905 mips_multi_write (void)
3907 struct mips_multi_member
*member
;
3910 FOR_EACH_VEC_ELT (mips_multi_member
, mips_multi_members
, i
, member
)
3911 if (member
->is_label_p
)
3912 fprintf (asm_out_file
, "%s\n", member
->format
);
3914 output_asm_insn (member
->format
, member
->operands
);
3917 /* Return one word of double-word value OP, taking into account the fixed
3918 endianness of certain registers. HIGH_P is true to select the high part,
3919 false to select the low part. */
3922 mips_subword (rtx op
, bool high_p
)
3924 unsigned int byte
, offset
;
3925 enum machine_mode mode
;
3927 mode
= GET_MODE (op
);
3928 if (mode
== VOIDmode
)
3929 mode
= TARGET_64BIT
? TImode
: DImode
;
3931 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
3932 byte
= UNITS_PER_WORD
;
3936 if (FP_REG_RTX_P (op
))
3938 /* Paired FPRs are always ordered little-endian. */
3939 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
3940 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
3944 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
3946 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
3949 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3952 mips_split_64bit_move_p (rtx dest
, rtx src
)
3957 /* FPR-to-FPR moves can be done in a single instruction, if they're
3959 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
3962 /* Check for floating-point loads and stores. */
3963 if (ISA_HAS_LDC1_SDC1
)
3965 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
3967 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
3973 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3974 this function handles 64-bit moves for which mips_split_64bit_move_p
3975 holds. For 64-bit targets, this function handles 128-bit moves. */
3978 mips_split_doubleword_move (rtx dest
, rtx src
)
3982 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
3984 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
3985 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
3986 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
3987 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
3988 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
3989 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
3990 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
3991 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
3992 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
3993 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
3994 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
3995 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
3996 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
3997 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4001 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4003 low_dest
= mips_subword (dest
, false);
4004 mips_emit_move (low_dest
, mips_subword (src
, false));
4006 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4008 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4010 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4012 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4014 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4016 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4020 /* The operation can be split into two normal moves. Decide in
4021 which order to do them. */
4022 low_dest
= mips_subword (dest
, false);
4023 if (REG_P (low_dest
)
4024 && reg_overlap_mentioned_p (low_dest
, src
))
4026 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4027 mips_emit_move (low_dest
, mips_subword (src
, false));
4031 mips_emit_move (low_dest
, mips_subword (src
, false));
4032 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4037 /* Return the appropriate instructions to move SRC into DEST. Assume
4038 that SRC is operand 1 and DEST is operand 0. */
4041 mips_output_move (rtx dest
, rtx src
)
4043 enum rtx_code dest_code
, src_code
;
4044 enum machine_mode mode
;
4045 enum mips_symbol_type symbol_type
;
4048 dest_code
= GET_CODE (dest
);
4049 src_code
= GET_CODE (src
);
4050 mode
= GET_MODE (dest
);
4051 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4053 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
4056 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4057 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4059 if (dest_code
== REG
)
4061 if (GP_REG_P (REGNO (dest
)))
4062 return "move\t%0,%z1";
4064 /* Moves to HI are handled by special .md insns. */
4065 if (REGNO (dest
) == LO_REGNUM
)
4068 if (DSP_ACC_REG_P (REGNO (dest
)))
4070 static char retval
[] = "mt__\t%z1,%q0";
4072 retval
[2] = reg_names
[REGNO (dest
)][4];
4073 retval
[3] = reg_names
[REGNO (dest
)][5];
4077 if (FP_REG_P (REGNO (dest
)))
4078 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4080 if (ALL_COP_REG_P (REGNO (dest
)))
4082 static char retval
[] = "dmtc_\t%z1,%0";
4084 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4085 return dbl_p
? retval
: retval
+ 1;
4088 if (dest_code
== MEM
)
4089 switch (GET_MODE_SIZE (mode
))
4091 case 1: return "sb\t%z1,%0";
4092 case 2: return "sh\t%z1,%0";
4093 case 4: return "sw\t%z1,%0";
4094 case 8: return "sd\t%z1,%0";
4097 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4099 if (src_code
== REG
)
4101 /* Moves from HI are handled by special .md insns. */
4102 if (REGNO (src
) == LO_REGNUM
)
4104 /* When generating VR4120 or VR4130 code, we use MACC and
4105 DMACC instead of MFLO. This avoids both the normal
4106 MIPS III HI/LO hazards and the errata related to
4109 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4113 if (DSP_ACC_REG_P (REGNO (src
)))
4115 static char retval
[] = "mf__\t%0,%q1";
4117 retval
[2] = reg_names
[REGNO (src
)][4];
4118 retval
[3] = reg_names
[REGNO (src
)][5];
4122 if (FP_REG_P (REGNO (src
)))
4123 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4125 if (ALL_COP_REG_P (REGNO (src
)))
4127 static char retval
[] = "dmfc_\t%0,%1";
4129 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4130 return dbl_p
? retval
: retval
+ 1;
4133 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
4134 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4137 if (src_code
== MEM
)
4138 switch (GET_MODE_SIZE (mode
))
4140 case 1: return "lbu\t%0,%1";
4141 case 2: return "lhu\t%0,%1";
4142 case 4: return "lw\t%0,%1";
4143 case 8: return "ld\t%0,%1";
4146 if (src_code
== CONST_INT
)
4148 /* Don't use the X format for the operand itself, because that
4149 will give out-of-range numbers for 64-bit hosts and 32-bit
4152 return "li\t%0,%1\t\t\t# %X1";
4154 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4157 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4161 if (src_code
== HIGH
)
4162 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4164 if (CONST_GP_P (src
))
4165 return "move\t%0,%1";
4167 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4168 && mips_lo_relocs
[symbol_type
] != 0)
4170 /* A signed 16-bit constant formed by applying a relocation
4171 operator to a symbolic address. */
4172 gcc_assert (!mips_split_p
[symbol_type
]);
4173 return "li\t%0,%R1";
4176 if (symbolic_operand (src
, VOIDmode
))
4178 gcc_assert (TARGET_MIPS16
4179 ? TARGET_MIPS16_TEXT_LOADS
4180 : !TARGET_EXPLICIT_RELOCS
);
4181 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4184 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4186 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4188 if (GET_MODE (dest
) == V2SFmode
)
4189 return "mov.ps\t%0,%1";
4191 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4194 if (dest_code
== MEM
)
4195 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4197 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4199 if (src_code
== MEM
)
4200 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4202 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4204 static char retval
[] = "l_c_\t%0,%1";
4206 retval
[1] = (dbl_p
? 'd' : 'w');
4207 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4210 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4212 static char retval
[] = "s_c_\t%1,%0";
4214 retval
[1] = (dbl_p
? 'd' : 'w');
4215 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4221 /* Return true if CMP1 is a suitable second operand for integer ordering
4222 test CODE. See also the *sCC patterns in mips.md. */
4225 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4231 return reg_or_0_operand (cmp1
, VOIDmode
);
4235 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4239 return arith_operand (cmp1
, VOIDmode
);
4242 return sle_operand (cmp1
, VOIDmode
);
4245 return sleu_operand (cmp1
, VOIDmode
);
4252 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4253 integer ordering test *CODE, or if an equivalent combination can
4254 be formed by adjusting *CODE and *CMP1. When returning true, update
4255 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4259 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4260 enum machine_mode mode
)
4262 HOST_WIDE_INT plus_one
;
4264 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4267 if (CONST_INT_P (*cmp1
))
4271 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4272 if (INTVAL (*cmp1
) < plus_one
)
4275 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4281 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4285 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4296 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4297 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4298 is nonnull, it's OK to set TARGET to the inverse of the result and
4299 flip *INVERT_PTR instead. */
4302 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4303 rtx target
, rtx cmp0
, rtx cmp1
)
4305 enum machine_mode mode
;
4307 /* First see if there is a MIPS instruction that can do this operation.
4308 If not, try doing the same for the inverse operation. If that also
4309 fails, force CMP1 into a register and try again. */
4310 mode
= GET_MODE (cmp0
);
4311 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4312 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4315 enum rtx_code inv_code
= reverse_condition (code
);
4316 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4318 cmp1
= force_reg (mode
, cmp1
);
4319 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4321 else if (invert_ptr
== 0)
4325 inv_target
= mips_force_binary (GET_MODE (target
),
4326 inv_code
, cmp0
, cmp1
);
4327 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4331 *invert_ptr
= !*invert_ptr
;
4332 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4337 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4338 The register will have the same mode as CMP0. */
4341 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4343 if (cmp1
== const0_rtx
)
4346 if (uns_arith_operand (cmp1
, VOIDmode
))
4347 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4348 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4350 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4351 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4354 /* Convert *CODE into a code that can be used in a floating-point
4355 scc instruction (C.cond.fmt). Return true if the values of
4356 the condition code registers will be inverted, with 0 indicating
4357 that the condition holds. */
4360 mips_reversed_fp_cond (enum rtx_code
*code
)
4367 *code
= reverse_condition_maybe_unordered (*code
);
4375 /* Convert a comparison into something that can be used in a branch or
4376 conditional move. On entry, *OP0 and *OP1 are the values being
4377 compared and *CODE is the code used to compare them.
4379 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4380 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4381 otherwise any standard branch condition can be used. The standard branch
4384 - EQ or NE between two registers.
4385 - any comparison between a register and zero. */
4388 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4393 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4395 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4397 else if (*code
== EQ
|| *code
== NE
)
4401 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4405 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4409 /* The comparison needs a separate scc instruction. Store the
4410 result of the scc in *OP0 and compare it against zero. */
4411 bool invert
= false;
4412 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4413 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4414 *code
= (invert
? EQ
: NE
);
4418 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4420 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4421 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4427 enum rtx_code cmp_code
;
4429 /* Floating-point tests use a separate C.cond.fmt comparison to
4430 set a condition code register. The branch or conditional move
4431 will then compare that register against zero.
4433 Set CMP_CODE to the code of the comparison instruction and
4434 *CODE to the code that the branch or move should use. */
4436 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4438 ? gen_reg_rtx (CCmode
)
4439 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4441 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4445 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4446 and OPERAND[3]. Store the result in OPERANDS[0].
4448 On 64-bit targets, the mode of the comparison and target will always be
4449 SImode, thus possibly narrower than that of the comparison's operands. */
4452 mips_expand_scc (rtx operands
[])
4454 rtx target
= operands
[0];
4455 enum rtx_code code
= GET_CODE (operands
[1]);
4456 rtx op0
= operands
[2];
4457 rtx op1
= operands
[3];
4459 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4461 if (code
== EQ
|| code
== NE
)
4464 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4465 mips_emit_binary (code
, target
, op0
, op1
);
4468 rtx zie
= mips_zero_if_equal (op0
, op1
);
4469 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4473 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4476 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4477 CODE and jump to OPERANDS[3] if the condition holds. */
4480 mips_expand_conditional_branch (rtx
*operands
)
4482 enum rtx_code code
= GET_CODE (operands
[0]);
4483 rtx op0
= operands
[1];
4484 rtx op1
= operands
[2];
4487 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4488 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4489 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4494 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4495 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4498 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4499 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4504 reversed_p
= mips_reversed_fp_cond (&cond
);
4505 cmp_result
= gen_reg_rtx (CCV2mode
);
4506 emit_insn (gen_scc_ps (cmp_result
,
4507 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4509 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4512 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4516 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4517 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4520 mips_expand_conditional_move (rtx
*operands
)
4523 enum rtx_code code
= GET_CODE (operands
[1]);
4524 rtx op0
= XEXP (operands
[1], 0);
4525 rtx op1
= XEXP (operands
[1], 1);
4527 mips_emit_compare (&code
, &op0
, &op1
, true);
4528 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4529 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4530 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4531 operands
[2], operands
[3])));
4534 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4537 mips_expand_conditional_trap (rtx comparison
)
4540 enum machine_mode mode
;
4543 /* MIPS conditional trap instructions don't have GT or LE flavors,
4544 so we must swap the operands and convert to LT and GE respectively. */
4545 code
= GET_CODE (comparison
);
4552 code
= swap_condition (code
);
4553 op0
= XEXP (comparison
, 1);
4554 op1
= XEXP (comparison
, 0);
4558 op0
= XEXP (comparison
, 0);
4559 op1
= XEXP (comparison
, 1);
4563 mode
= GET_MODE (XEXP (comparison
, 0));
4564 op0
= force_reg (mode
, op0
);
4565 if (!arith_operand (op1
, mode
))
4566 op1
= force_reg (mode
, op1
);
4568 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4569 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4573 /* Initialize *CUM for a call to a function of type FNTYPE. */
4576 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4578 memset (cum
, 0, sizeof (*cum
));
4579 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4580 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4583 /* Fill INFO with information about a single argument. CUM is the
4584 cumulative state for earlier arguments. MODE is the mode of this
4585 argument and TYPE is its type (if known). NAMED is true if this
4586 is a named (fixed) argument rather than a variable one. */
4589 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4590 enum machine_mode mode
, const_tree type
, bool named
)
4592 bool doubleword_aligned_p
;
4593 unsigned int num_bytes
, num_words
, max_regs
;
4595 /* Work out the size of the argument. */
4596 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4597 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4599 /* Decide whether it should go in a floating-point register, assuming
4600 one is free. Later code checks for availability.
4602 The checks against UNITS_PER_FPVALUE handle the soft-float and
4603 single-float cases. */
4607 /* The EABI conventions have traditionally been defined in terms
4608 of TYPE_MODE, regardless of the actual type. */
4609 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4610 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4611 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4616 /* Only leading floating-point scalars are passed in
4617 floating-point registers. We also handle vector floats the same
4618 say, which is OK because they are not covered by the standard ABI. */
4619 info
->fpr_p
= (!cum
->gp_reg_found
4620 && cum
->arg_number
< 2
4622 || SCALAR_FLOAT_TYPE_P (type
)
4623 || VECTOR_FLOAT_TYPE_P (type
))
4624 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4625 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4626 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4631 /* Scalar, complex and vector floating-point types are passed in
4632 floating-point registers, as long as this is a named rather
4633 than a variable argument. */
4634 info
->fpr_p
= (named
4635 && (type
== 0 || FLOAT_TYPE_P (type
))
4636 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4637 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4638 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4639 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4641 /* ??? According to the ABI documentation, the real and imaginary
4642 parts of complex floats should be passed in individual registers.
4643 The real and imaginary parts of stack arguments are supposed
4644 to be contiguous and there should be an extra word of padding
4647 This has two problems. First, it makes it impossible to use a
4648 single "void *" va_list type, since register and stack arguments
4649 are passed differently. (At the time of writing, MIPSpro cannot
4650 handle complex float varargs correctly.) Second, it's unclear
4651 what should happen when there is only one register free.
4653 For now, we assume that named complex floats should go into FPRs
4654 if there are two FPRs free, otherwise they should be passed in the
4655 same way as a struct containing two floats. */
4657 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4658 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4660 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4661 info
->fpr_p
= false;
4671 /* See whether the argument has doubleword alignment. */
4672 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
4675 /* Set REG_OFFSET to the register count we're interested in.
4676 The EABI allocates the floating-point registers separately,
4677 but the other ABIs allocate them like integer registers. */
4678 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4682 /* Advance to an even register if the argument is doubleword-aligned. */
4683 if (doubleword_aligned_p
)
4684 info
->reg_offset
+= info
->reg_offset
& 1;
4686 /* Work out the offset of a stack argument. */
4687 info
->stack_offset
= cum
->stack_words
;
4688 if (doubleword_aligned_p
)
4689 info
->stack_offset
+= info
->stack_offset
& 1;
4691 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4693 /* Partition the argument between registers and stack. */
4694 info
->reg_words
= MIN (num_words
, max_regs
);
4695 info
->stack_words
= num_words
- info
->reg_words
;
4698 /* INFO describes a register argument that has the normal format for the
4699 argument's mode. Return the register it uses, assuming that FPRs are
4700 available if HARD_FLOAT_P. */
4703 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4705 if (!info
->fpr_p
|| !hard_float_p
)
4706 return GP_ARG_FIRST
+ info
->reg_offset
;
4707 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4708 /* In o32, the second argument is always passed in $f14
4709 for TARGET_DOUBLE_FLOAT, regardless of whether the
4710 first argument was a word or doubleword. */
4711 return FP_ARG_FIRST
+ 2;
4713 return FP_ARG_FIRST
+ info
->reg_offset
;
4716 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4719 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
4721 return !TARGET_OLDABI
;
4724 /* Implement TARGET_FUNCTION_ARG. */
4727 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
4728 const_tree type
, bool named
)
4730 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4731 struct mips_arg_info info
;
4733 /* We will be called with a mode of VOIDmode after the last argument
4734 has been seen. Whatever we return will be passed to the call expander.
4735 If we need a MIPS16 fp_code, return a REG with the code stored as
4737 if (mode
== VOIDmode
)
4739 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4740 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4745 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4747 /* Return straight away if the whole argument is passed on the stack. */
4748 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4751 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4752 contains a double in its entirety, then that 64-bit chunk is passed
4753 in a floating-point register. */
4755 && TARGET_HARD_FLOAT
4758 && TREE_CODE (type
) == RECORD_TYPE
4759 && TYPE_SIZE_UNIT (type
)
4760 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
4764 /* First check to see if there is any such field. */
4765 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
4766 if (TREE_CODE (field
) == FIELD_DECL
4767 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4768 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4769 && host_integerp (bit_position (field
), 0)
4770 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4775 /* Now handle the special case by returning a PARALLEL
4776 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4777 chunks are passed in registers. */
4779 HOST_WIDE_INT bitpos
;
4782 /* assign_parms checks the mode of ENTRY_PARM, so we must
4783 use the actual mode here. */
4784 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4787 field
= TYPE_FIELDS (type
);
4788 for (i
= 0; i
< info
.reg_words
; i
++)
4792 for (; field
; field
= DECL_CHAIN (field
))
4793 if (TREE_CODE (field
) == FIELD_DECL
4794 && int_bit_position (field
) >= bitpos
)
4798 && int_bit_position (field
) == bitpos
4799 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4800 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4801 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4803 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4806 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4807 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4809 bitpos
+= BITS_PER_WORD
;
4815 /* Handle the n32/n64 conventions for passing complex floating-point
4816 arguments in FPR pairs. The real part goes in the lower register
4817 and the imaginary part goes in the upper register. */
4820 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4823 enum machine_mode inner
;
4826 inner
= GET_MODE_INNER (mode
);
4827 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
4828 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4830 /* Real part in registers, imaginary part on stack. */
4831 gcc_assert (info
.stack_words
== info
.reg_words
);
4832 return gen_rtx_REG (inner
, regno
);
4836 gcc_assert (info
.stack_words
== 0);
4837 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4838 gen_rtx_REG (inner
, regno
),
4840 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4842 regno
+ info
.reg_words
/ 2),
4843 GEN_INT (GET_MODE_SIZE (inner
)));
4844 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
4848 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
4851 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4854 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
4855 const_tree type
, bool named
)
4857 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
4858 struct mips_arg_info info
;
4860 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4863 cum
->gp_reg_found
= true;
4865 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4866 an explanation of what this code does. It assumes that we're using
4867 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4869 if (cum
->arg_number
< 2 && info
.fpr_p
)
4870 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
4872 /* Advance the register count. This has the effect of setting
4873 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4874 argument required us to skip the final GPR and pass the whole
4875 argument on the stack. */
4876 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4877 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4878 else if (info
.reg_words
> 0)
4879 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
4881 /* Advance the stack word count. */
4882 if (info
.stack_words
> 0)
4883 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4888 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4891 mips_arg_partial_bytes (cumulative_args_t cum
,
4892 enum machine_mode mode
, tree type
, bool named
)
4894 struct mips_arg_info info
;
4896 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
4897 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
4900 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
4901 least PARM_BOUNDARY bits of alignment, but will be given anything up
4902 to STACK_BOUNDARY bits if the type requires it. */
4905 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
4907 unsigned int alignment
;
4909 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
4910 if (alignment
< PARM_BOUNDARY
)
4911 alignment
= PARM_BOUNDARY
;
4912 if (alignment
> STACK_BOUNDARY
)
4913 alignment
= STACK_BOUNDARY
;
4917 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4918 upward rather than downward. In other words, return true if the
4919 first byte of the stack slot has useful data, false if the last
4923 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
4925 /* On little-endian targets, the first byte of every stack argument
4926 is passed in the first byte of the stack slot. */
4927 if (!BYTES_BIG_ENDIAN
)
4930 /* Otherwise, integral types are padded downward: the last byte of a
4931 stack argument is passed in the last byte of the stack slot. */
4933 ? (INTEGRAL_TYPE_P (type
)
4934 || POINTER_TYPE_P (type
)
4935 || FIXED_POINT_TYPE_P (type
))
4936 : (SCALAR_INT_MODE_P (mode
)
4937 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
4940 /* Big-endian o64 pads floating-point arguments downward. */
4941 if (mips_abi
== ABI_O64
)
4942 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4945 /* Other types are padded upward for o32, o64, n32 and n64. */
4946 if (mips_abi
!= ABI_EABI
)
4949 /* Arguments smaller than a stack slot are padded downward. */
4950 if (mode
!= BLKmode
)
4951 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
4953 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
4956 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4957 if the least significant byte of the register has useful data. Return
4958 the opposite if the most significant byte does. */
4961 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
4963 /* No shifting is required for floating-point arguments. */
4964 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4965 return !BYTES_BIG_ENDIAN
;
4967 /* Otherwise, apply the same padding to register arguments as we do
4968 to stack arguments. */
4969 return mips_pad_arg_upward (mode
, type
);
4972 /* Return nonzero when an argument must be passed by reference. */
4975 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
4976 enum machine_mode mode
, const_tree type
,
4977 bool named ATTRIBUTE_UNUSED
)
4979 if (mips_abi
== ABI_EABI
)
4983 /* ??? How should SCmode be handled? */
4984 if (mode
== DImode
|| mode
== DFmode
4985 || mode
== DQmode
|| mode
== UDQmode
4986 || mode
== DAmode
|| mode
== UDAmode
)
4989 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4990 return size
== -1 || size
> UNITS_PER_WORD
;
4994 /* If we have a variable-sized parameter, we have no choice. */
4995 return targetm
.calls
.must_pass_in_stack (mode
, type
);
4999 /* Implement TARGET_CALLEE_COPIES. */
5002 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5003 enum machine_mode mode ATTRIBUTE_UNUSED
,
5004 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5006 return mips_abi
== ABI_EABI
&& named
;
5009 /* See whether VALTYPE is a record whose fields should be returned in
5010 floating-point registers. If so, return the number of fields and
5011 list them in FIELDS (which should have two elements). Return 0
5014 For n32 & n64, a structure with one or two fields is returned in
5015 floating-point registers as long as every field has a floating-point
5019 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5027 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5031 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5033 if (TREE_CODE (field
) != FIELD_DECL
)
5036 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5042 fields
[i
++] = field
;
5047 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5048 a value in the most significant part of $2/$3 if:
5050 - the target is big-endian;
5052 - the value has a structure or union type (we generalize this to
5053 cover aggregates from other languages too); and
5055 - the structure is not returned in floating-point registers. */
5058 mips_return_in_msb (const_tree valtype
)
5062 return (TARGET_NEWABI
5063 && TARGET_BIG_ENDIAN
5064 && AGGREGATE_TYPE_P (valtype
)
5065 && mips_fpr_return_fields (valtype
, fields
) == 0);
5068 /* Return true if the function return value MODE will get returned in a
5069 floating-point register. */
5072 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5074 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5075 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
5076 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5077 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5080 /* Return the representation of an FPR return register when the
5081 value being returned in FP_RETURN has mode VALUE_MODE and the
5082 return type itself has mode TYPE_MODE. On NewABI targets,
5083 the two modes may be different for structures like:
5085 struct __attribute__((packed)) foo { float f; }
5087 where we return the SFmode value of "f" in FP_RETURN, but where
5088 the structure itself has mode BLKmode. */
5091 mips_return_fpr_single (enum machine_mode type_mode
,
5092 enum machine_mode value_mode
)
5096 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5097 if (type_mode
!= value_mode
)
5099 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5100 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5105 /* Return a composite value in a pair of floating-point registers.
5106 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5107 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5110 For n32 & n64, $f0 always holds the first value and $f2 the second.
5111 Otherwise the values are packed together as closely as possible. */
5114 mips_return_fpr_pair (enum machine_mode mode
,
5115 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5116 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5120 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5121 return gen_rtx_PARALLEL
5124 gen_rtx_EXPR_LIST (VOIDmode
,
5125 gen_rtx_REG (mode1
, FP_RETURN
),
5127 gen_rtx_EXPR_LIST (VOIDmode
,
5128 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5129 GEN_INT (offset2
))));
5133 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5134 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5135 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5138 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5139 enum machine_mode mode
)
5147 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5148 func
= fn_decl_or_type
;
5152 mode
= TYPE_MODE (valtype
);
5153 unsigned_p
= TYPE_UNSIGNED (valtype
);
5155 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5156 return values, promote the mode here too. */
5157 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5159 /* Handle structures whose fields are returned in $f0/$f2. */
5160 switch (mips_fpr_return_fields (valtype
, fields
))
5163 return mips_return_fpr_single (mode
,
5164 TYPE_MODE (TREE_TYPE (fields
[0])));
5167 return mips_return_fpr_pair (mode
,
5168 TYPE_MODE (TREE_TYPE (fields
[0])),
5169 int_byte_position (fields
[0]),
5170 TYPE_MODE (TREE_TYPE (fields
[1])),
5171 int_byte_position (fields
[1]));
5174 /* If a value is passed in the most significant part of a register, see
5175 whether we have to round the mode up to a whole number of words. */
5176 if (mips_return_in_msb (valtype
))
5178 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5179 if (size
% UNITS_PER_WORD
!= 0)
5181 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5182 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5186 /* For EABI, the class of return register depends entirely on MODE.
5187 For example, "struct { some_type x; }" and "union { some_type x; }"
5188 are returned in the same way as a bare "some_type" would be.
5189 Other ABIs only use FPRs for scalar, complex or vector types. */
5190 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5191 return gen_rtx_REG (mode
, GP_RETURN
);
5196 /* Handle long doubles for n32 & n64. */
5198 return mips_return_fpr_pair (mode
,
5200 DImode
, GET_MODE_SIZE (mode
) / 2);
5202 if (mips_return_mode_in_fpr_p (mode
))
5204 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5205 return mips_return_fpr_pair (mode
,
5206 GET_MODE_INNER (mode
), 0,
5207 GET_MODE_INNER (mode
),
5208 GET_MODE_SIZE (mode
) / 2);
5210 return gen_rtx_REG (mode
, FP_RETURN
);
5214 return gen_rtx_REG (mode
, GP_RETURN
);
5217 /* Implement TARGET_FUNCTION_VALUE. */
5220 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5221 bool outgoing ATTRIBUTE_UNUSED
)
5223 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5226 /* Implement TARGET_LIBCALL_VALUE. */
5229 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5231 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5234 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5236 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5237 Currently, R2 and F0 are only implemented here (C has no complex type). */
5240 mips_function_value_regno_p (const unsigned int regno
)
5242 if (regno
== GP_RETURN
5243 || regno
== FP_RETURN
5244 || (LONG_DOUBLE_TYPE_SIZE
== 128
5245 && FP_RETURN
!= GP_RETURN
5246 && regno
== FP_RETURN
+ 2))
5252 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5253 all BLKmode objects are returned in memory. Under the n32, n64
5254 and embedded ABIs, small structures are returned in a register.
5255 Objects with varying size must still be returned in memory, of
5259 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5261 return (TARGET_OLDABI
5262 ? TYPE_MODE (type
) == BLKmode
5263 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5266 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5269 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5270 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5273 CUMULATIVE_ARGS local_cum
;
5274 int gp_saved
, fp_saved
;
5276 /* The caller has advanced CUM up to, but not beyond, the last named
5277 argument. Advance a local copy of CUM past the last "real" named
5278 argument, to find out how many registers are left over. */
5279 local_cum
= *get_cumulative_args (cum
);
5280 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5283 /* Found out how many registers we need to save. */
5284 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5285 fp_saved
= (EABI_FLOAT_VARARGS_P
5286 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5295 ptr
= plus_constant (virtual_incoming_args_rtx
,
5296 REG_PARM_STACK_SPACE (cfun
->decl
)
5297 - gp_saved
* UNITS_PER_WORD
);
5298 mem
= gen_frame_mem (BLKmode
, ptr
);
5299 set_mem_alias_set (mem
, get_varargs_alias_set ());
5301 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5306 /* We can't use move_block_from_reg, because it will use
5308 enum machine_mode mode
;
5311 /* Set OFF to the offset from virtual_incoming_args_rtx of
5312 the first float register. The FP save area lies below
5313 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5314 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5315 off
-= fp_saved
* UNITS_PER_FPREG
;
5317 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5319 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5320 i
+= MAX_FPRS_PER_FMT
)
5324 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
5325 mem
= gen_frame_mem (mode
, ptr
);
5326 set_mem_alias_set (mem
, get_varargs_alias_set ());
5327 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5328 off
+= UNITS_PER_HWFPVALUE
;
5332 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5333 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5334 + fp_saved
* UNITS_PER_FPREG
);
5337 /* Implement TARGET_BUILTIN_VA_LIST. */
5340 mips_build_builtin_va_list (void)
5342 if (EABI_FLOAT_VARARGS_P
)
5344 /* We keep 3 pointers, and two offsets.
5346 Two pointers are to the overflow area, which starts at the CFA.
5347 One of these is constant, for addressing into the GPR save area
5348 below it. The other is advanced up the stack through the
5351 The third pointer is to the bottom of the GPR save area.
5352 Since the FPR save area is just below it, we can address
5353 FPR slots off this pointer.
5355 We also keep two one-byte offsets, which are to be subtracted
5356 from the constant pointers to yield addresses in the GPR and
5357 FPR save areas. These are downcounted as float or non-float
5358 arguments are used, and when they get to zero, the argument
5359 must be obtained from the overflow region. */
5360 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5363 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5365 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5366 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5368 f_gtop
= build_decl (BUILTINS_LOCATION
,
5369 FIELD_DECL
, get_identifier ("__gpr_top"),
5371 f_ftop
= build_decl (BUILTINS_LOCATION
,
5372 FIELD_DECL
, get_identifier ("__fpr_top"),
5374 f_goff
= build_decl (BUILTINS_LOCATION
,
5375 FIELD_DECL
, get_identifier ("__gpr_offset"),
5376 unsigned_char_type_node
);
5377 f_foff
= build_decl (BUILTINS_LOCATION
,
5378 FIELD_DECL
, get_identifier ("__fpr_offset"),
5379 unsigned_char_type_node
);
5380 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5381 warn on every user file. */
5382 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5383 array
= build_array_type (unsigned_char_type_node
,
5384 build_index_type (index
));
5385 f_res
= build_decl (BUILTINS_LOCATION
,
5386 FIELD_DECL
, get_identifier ("__reserved"), array
);
5388 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5389 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5390 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5391 DECL_FIELD_CONTEXT (f_goff
) = record
;
5392 DECL_FIELD_CONTEXT (f_foff
) = record
;
5393 DECL_FIELD_CONTEXT (f_res
) = record
;
5395 TYPE_FIELDS (record
) = f_ovfl
;
5396 DECL_CHAIN (f_ovfl
) = f_gtop
;
5397 DECL_CHAIN (f_gtop
) = f_ftop
;
5398 DECL_CHAIN (f_ftop
) = f_goff
;
5399 DECL_CHAIN (f_goff
) = f_foff
;
5400 DECL_CHAIN (f_foff
) = f_res
;
5402 layout_type (record
);
5405 else if (TARGET_IRIX6
)
5406 /* On IRIX 6, this type is 'char *'. */
5407 return build_pointer_type (char_type_node
);
5409 /* Otherwise, we use 'void *'. */
5410 return ptr_type_node
;
5413 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5416 mips_va_start (tree valist
, rtx nextarg
)
5418 if (EABI_FLOAT_VARARGS_P
)
5420 const CUMULATIVE_ARGS
*cum
;
5421 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5422 tree ovfl
, gtop
, ftop
, goff
, foff
;
5424 int gpr_save_area_size
;
5425 int fpr_save_area_size
;
5428 cum
= &crtl
->args
.info
;
5430 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5432 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5434 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5435 f_gtop
= DECL_CHAIN (f_ovfl
);
5436 f_ftop
= DECL_CHAIN (f_gtop
);
5437 f_goff
= DECL_CHAIN (f_ftop
);
5438 f_foff
= DECL_CHAIN (f_goff
);
5440 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5442 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5444 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5446 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5448 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5451 /* Emit code to initialize OVFL, which points to the next varargs
5452 stack argument. CUM->STACK_WORDS gives the number of stack
5453 words used by named arguments. */
5454 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5455 if (cum
->stack_words
> 0)
5456 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5457 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5458 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5460 /* Emit code to initialize GTOP, the top of the GPR save area. */
5461 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5462 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5463 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5465 /* Emit code to initialize FTOP, the top of the FPR save area.
5466 This address is gpr_save_area_bytes below GTOP, rounded
5467 down to the next fp-aligned boundary. */
5468 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5469 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5470 fpr_offset
&= -UNITS_PER_FPVALUE
;
5472 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5473 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5474 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5476 /* Emit code to initialize GOFF, the offset from GTOP of the
5477 next GPR argument. */
5478 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5479 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5480 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5482 /* Likewise emit code to initialize FOFF, the offset from FTOP
5483 of the next FPR argument. */
5484 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5485 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5486 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5490 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
5491 std_expand_builtin_va_start (valist
, nextarg
);
5495 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5498 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5504 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5506 type
= build_pointer_type (type
);
5508 if (!EABI_FLOAT_VARARGS_P
)
5509 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5512 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5513 tree ovfl
, top
, off
, align
;
5514 HOST_WIDE_INT size
, rsize
, osize
;
5517 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5518 f_gtop
= DECL_CHAIN (f_ovfl
);
5519 f_ftop
= DECL_CHAIN (f_gtop
);
5520 f_goff
= DECL_CHAIN (f_ftop
);
5521 f_foff
= DECL_CHAIN (f_goff
);
5525 TOP be the top of the GPR or FPR save area;
5526 OFF be the offset from TOP of the next register;
5527 ADDR_RTX be the address of the argument;
5528 SIZE be the number of bytes in the argument type;
5529 RSIZE be the number of bytes used to store the argument
5530 when it's in the register save area; and
5531 OSIZE be the number of bytes used to store it when it's
5532 in the stack overflow area.
5534 The code we want is:
5536 1: off &= -rsize; // round down
5539 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5544 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5545 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5549 [1] and [9] can sometimes be optimized away. */
5551 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5553 size
= int_size_in_bytes (type
);
5555 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
5556 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
5558 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
5559 unshare_expr (valist
), f_ftop
, NULL_TREE
);
5560 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
5561 unshare_expr (valist
), f_foff
, NULL_TREE
);
5563 /* When va_start saves FPR arguments to the stack, each slot
5564 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5565 argument's precision. */
5566 rsize
= UNITS_PER_HWFPVALUE
;
5568 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5569 (= PARM_BOUNDARY bits). This can be different from RSIZE
5572 (1) On 32-bit targets when TYPE is a structure such as:
5574 struct s { float f; };
5576 Such structures are passed in paired FPRs, so RSIZE
5577 will be 8 bytes. However, the structure only takes
5578 up 4 bytes of memory, so OSIZE will only be 4.
5580 (2) In combinations such as -mgp64 -msingle-float
5581 -fshort-double. Doubles passed in registers will then take
5582 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5583 stack take up UNITS_PER_WORD bytes. */
5584 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
5588 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
5589 unshare_expr (valist
), f_gtop
, NULL_TREE
);
5590 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
5591 unshare_expr (valist
), f_goff
, NULL_TREE
);
5592 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5593 if (rsize
> UNITS_PER_WORD
)
5595 /* [1] Emit code for: off &= -rsize. */
5596 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
5597 build_int_cst (TREE_TYPE (off
), -rsize
));
5598 gimplify_assign (unshare_expr (off
), t
, pre_p
);
5603 /* [2] Emit code to branch if off == 0. */
5604 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
5605 build_int_cst (TREE_TYPE (off
), 0));
5606 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
5608 /* [5] Emit code for: off -= rsize. We do this as a form of
5609 post-decrement not available to C. */
5610 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
5611 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
5613 /* [4] Emit code for:
5614 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5615 t
= fold_convert (sizetype
, t
);
5616 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
5617 t
= fold_build_pointer_plus (top
, t
);
5618 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
5619 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
5620 COND_EXPR_THEN (addr
) = t
;
5622 if (osize
> UNITS_PER_WORD
)
5624 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5625 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
5626 u
= build_int_cst (TREE_TYPE (t
), -osize
);
5627 t
= build2 (BIT_AND_EXPR
, sizetype
, t
, u
);
5628 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
5629 unshare_expr (ovfl
), t
);
5634 /* [10, 11] Emit code for:
5635 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5637 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
5638 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5639 if (BYTES_BIG_ENDIAN
&& osize
> size
)
5640 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
5642 /* String [9] and [10, 11] together. */
5644 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5645 COND_EXPR_ELSE (addr
) = t
;
5647 addr
= fold_convert (build_pointer_type (type
), addr
);
5648 addr
= build_va_arg_indirect_ref (addr
);
5652 addr
= build_va_arg_indirect_ref (addr
);
5657 /* Start a definition of function NAME. MIPS16_P indicates whether the
5658 function contains MIPS16 code. */
5661 mips_start_function_definition (const char *name
, bool mips16_p
)
5664 fprintf (asm_out_file
, "\t.set\tmips16\n");
5666 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5668 if (!flag_inhibit_size_directive
)
5670 fputs ("\t.ent\t", asm_out_file
);
5671 assemble_name (asm_out_file
, name
);
5672 fputs ("\n", asm_out_file
);
5675 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
5677 /* Start the definition proper. */
5678 assemble_name (asm_out_file
, name
);
5679 fputs (":\n", asm_out_file
);
5682 /* End a function definition started by mips_start_function_definition. */
5685 mips_end_function_definition (const char *name
)
5687 if (!flag_inhibit_size_directive
)
5689 fputs ("\t.end\t", asm_out_file
);
5690 assemble_name (asm_out_file
, name
);
5691 fputs ("\n", asm_out_file
);
5695 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5698 mips_ok_for_lazy_binding_p (rtx x
)
5700 return (TARGET_USE_GOT
5701 && GET_CODE (x
) == SYMBOL_REF
5702 && !SYMBOL_REF_BIND_NOW_P (x
)
5703 && !mips_symbol_binds_local_p (x
));
5706 /* Load function address ADDR into register DEST. TYPE is as for
5707 mips_expand_call. Return true if we used an explicit lazy-binding
5711 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
5713 /* If we're generating PIC, and this call is to a global function,
5714 try to allow its address to be resolved lazily. This isn't
5715 possible for sibcalls when $gp is call-saved because the value
5716 of $gp on entry to the stub would be our caller's gp, not ours. */
5717 if (TARGET_EXPLICIT_RELOCS
5718 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
5719 && mips_ok_for_lazy_binding_p (addr
))
5721 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
5722 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
5727 mips_emit_move (dest
, addr
);
5732 /* Each locally-defined hard-float MIPS16 function has a local symbol
5733 associated with it. This hash table maps the function symbol (FUNC)
5734 to the local symbol (LOCAL). */
5735 struct GTY(()) mips16_local_alias
{
5739 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
5741 /* Hash table callbacks for mips16_local_aliases. */
5744 mips16_local_aliases_hash (const void *entry
)
5746 const struct mips16_local_alias
*alias
;
5748 alias
= (const struct mips16_local_alias
*) entry
;
5749 return htab_hash_string (XSTR (alias
->func
, 0));
5753 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
5755 const struct mips16_local_alias
*alias1
, *alias2
;
5757 alias1
= (const struct mips16_local_alias
*) entry1
;
5758 alias2
= (const struct mips16_local_alias
*) entry2
;
5759 return rtx_equal_p (alias1
->func
, alias2
->func
);
5762 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5763 Return a local alias for it, creating a new one if necessary. */
5766 mips16_local_alias (rtx func
)
5768 struct mips16_local_alias
*alias
, tmp_alias
;
5771 /* Create the hash table if this is the first call. */
5772 if (mips16_local_aliases
== NULL
)
5773 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
5774 mips16_local_aliases_eq
, NULL
);
5776 /* Look up the function symbol, creating a new entry if need be. */
5777 tmp_alias
.func
= func
;
5778 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
5779 gcc_assert (slot
!= NULL
);
5781 alias
= (struct mips16_local_alias
*) *slot
;
5784 const char *func_name
, *local_name
;
5787 /* Create a new SYMBOL_REF for the local symbol. The choice of
5788 __fn_local_* is based on the __fn_stub_* names that we've
5789 traditionally used for the non-MIPS16 stub. */
5790 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
5791 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
5792 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
5793 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
5795 /* Create a new structure to represent the mapping. */
5796 alias
= ggc_alloc_mips16_local_alias ();
5798 alias
->local
= local
;
5801 return alias
->local
;
5804 /* A chained list of functions for which mips16_build_call_stub has already
5805 generated a stub. NAME is the name of the function and FP_RET_P is true
5806 if the function returns a value in floating-point registers. */
5807 struct mips16_stub
{
5808 struct mips16_stub
*next
;
5812 static struct mips16_stub
*mips16_stubs
;
5814 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5817 mips16_stub_function (const char *name
)
5821 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
5822 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
5826 /* Return the two-character string that identifies floating-point
5827 return mode MODE in the name of a MIPS16 function stub. */
5830 mips16_call_stub_mode_suffix (enum machine_mode mode
)
5834 else if (mode
== DFmode
)
5836 else if (mode
== SCmode
)
5838 else if (mode
== DCmode
)
5840 else if (mode
== V2SFmode
)
5846 /* Write instructions to move a 32-bit value between general register
5847 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5848 from GPREG to FPREG and 'f' to move in the opposite direction. */
5851 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5853 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5854 reg_names
[gpreg
], reg_names
[fpreg
]);
5857 /* Likewise for 64-bit values. */
5860 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5863 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
5864 reg_names
[gpreg
], reg_names
[fpreg
]);
5865 else if (TARGET_FLOAT64
)
5867 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5868 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5869 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
5870 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
5874 /* Move the least-significant word. */
5875 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5876 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5877 /* ...then the most significant word. */
5878 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5879 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
5883 /* Write out code to move floating-point arguments into or out of
5884 general registers. FP_CODE is the code describing which arguments
5885 are present (see the comment above the definition of CUMULATIVE_ARGS
5886 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5889 mips_output_args_xfer (int fp_code
, char direction
)
5891 unsigned int gparg
, fparg
, f
;
5892 CUMULATIVE_ARGS cum
;
5894 /* This code only works for o32 and o64. */
5895 gcc_assert (TARGET_OLDABI
);
5897 mips_init_cumulative_args (&cum
, NULL
);
5899 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5901 enum machine_mode mode
;
5902 struct mips_arg_info info
;
5906 else if ((f
& 3) == 2)
5911 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
5912 gparg
= mips_arg_regno (&info
, false);
5913 fparg
= mips_arg_regno (&info
, true);
5916 mips_output_32bit_xfer (direction
, gparg
, fparg
);
5918 mips_output_64bit_xfer (direction
, gparg
, fparg
);
5920 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
5924 /* Write a MIPS16 stub for the current function. This stub is used
5925 for functions which take arguments in the floating-point registers.
5926 It is normal-mode code that moves the floating-point arguments
5927 into the general registers and then jumps to the MIPS16 code. */
5930 mips16_build_function_stub (void)
5932 const char *fnname
, *alias_name
, *separator
;
5933 char *secname
, *stubname
;
5938 /* Create the name of the stub, and its unique section. */
5939 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
5940 alias
= mips16_local_alias (symbol
);
5942 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
5943 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
5944 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
5945 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
5947 /* Build a decl for the stub. */
5948 stubdecl
= build_decl (BUILTINS_LOCATION
,
5949 FUNCTION_DECL
, get_identifier (stubname
),
5950 build_function_type_list (void_type_node
, NULL_TREE
));
5951 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
5952 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
5953 RESULT_DECL
, NULL_TREE
, void_type_node
);
5955 /* Output a comment. */
5956 fprintf (asm_out_file
, "\t# Stub function for %s (",
5957 current_function_name ());
5959 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
5961 fprintf (asm_out_file
, "%s%s", separator
,
5962 (f
& 3) == 1 ? "float" : "double");
5965 fprintf (asm_out_file
, ")\n");
5967 /* Start the function definition. */
5968 assemble_start_function (stubdecl
, stubname
);
5969 mips_start_function_definition (stubname
, false);
5971 /* If generating pic2 code, either set up the global pointer or
5973 if (TARGET_ABICALLS_PIC2
)
5975 if (TARGET_ABSOLUTE_ABICALLS
)
5976 fprintf (asm_out_file
, "\t.option\tpic0\n");
5979 output_asm_insn ("%(.cpload\t%^%)", NULL
);
5980 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5981 target function is. Use a local GOT access when loading the
5982 symbol, to cut down on the number of unnecessary GOT entries
5983 for stubs that aren't needed. */
5984 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
5989 /* Load the address of the MIPS16 function into $25. Do this first so
5990 that targets with coprocessor interlocks can use an MFC1 to fill the
5992 output_asm_insn ("la\t%^,%0", &symbol
);
5994 /* Move the arguments from floating-point registers to general registers. */
5995 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
5997 /* Jump to the MIPS16 function. */
5998 output_asm_insn ("jr\t%^", NULL
);
6000 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6001 fprintf (asm_out_file
, "\t.option\tpic2\n");
6003 mips_end_function_definition (stubname
);
6005 /* If the linker needs to create a dynamic symbol for the target
6006 function, it will associate the symbol with the stub (which,
6007 unlike the target function, follows the proper calling conventions).
6008 It is therefore useful to have a local alias for the target function,
6009 so that it can still be identified as MIPS16 code. As an optimization,
6010 this symbol can also be used for indirect MIPS16 references from
6011 within this file. */
6012 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6014 switch_to_section (function_section (current_function_decl
));
6017 /* The current function is a MIPS16 function that returns a value in an FPR.
6018 Copy the return value from its soft-float to its hard-float location.
6019 libgcc2 has special non-MIPS16 helper functions for each case. */
6022 mips16_copy_fpr_return_value (void)
6024 rtx fn
, insn
, retval
;
6026 enum machine_mode return_mode
;
6029 return_type
= DECL_RESULT (current_function_decl
);
6030 return_mode
= DECL_MODE (return_type
);
6032 name
= ACONCAT (("__mips16_ret_",
6033 mips16_call_stub_mode_suffix (return_mode
),
6035 fn
= mips16_stub_function (name
);
6037 /* The function takes arguments in $2 (and possibly $3), so calls
6038 to it cannot be lazily bound. */
6039 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6041 /* Model the call as something that takes the GPR return value as
6042 argument and returns an "updated" value. */
6043 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6044 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6045 const0_rtx
, NULL_RTX
, false);
6046 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6049 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6050 RETVAL is the location of the return value, or null if this is
6051 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6052 arguments and FP_CODE is the code built by mips_function_arg;
6053 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6055 There are three alternatives:
6057 - If a stub was needed, emit the call and return the call insn itself.
6059 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6060 to the new target and return null.
6062 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6065 A stub is needed for calls to functions that, in normal mode,
6066 receive arguments in FPRs or return values in FPRs. The stub
6067 copies the arguments from their soft-float positions to their
6068 hard-float positions, calls the real function, then copies the
6069 return value from its hard-float position to its soft-float
6072 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6073 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6074 automatically redirects the JAL to the stub, otherwise the JAL
6075 continues to call FN directly. */
6078 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6082 struct mips16_stub
*l
;
6085 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6086 we were invoked with the -msoft-float option. */
6087 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6090 /* Figure out whether the value might come back in a floating-point
6092 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6094 /* We don't need to do anything if there were no floating-point
6095 arguments and the value will not be returned in a floating-point
6097 if (fp_code
== 0 && !fp_ret_p
)
6100 /* We don't need to do anything if this is a call to a special
6101 MIPS16 support function. */
6103 if (mips16_stub_function_p (fn
))
6106 /* This code will only work for o32 and o64 abis. The other ABI's
6107 require more sophisticated support. */
6108 gcc_assert (TARGET_OLDABI
);
6110 /* If we're calling via a function pointer, use one of the magic
6111 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6112 Each stub expects the function address to arrive in register $2. */
6113 if (GET_CODE (fn
) != SYMBOL_REF
6114 || !call_insn_operand (fn
, VOIDmode
))
6117 rtx stub_fn
, insn
, addr
;
6120 /* If this is a locally-defined and locally-binding function,
6121 avoid the stub by calling the local alias directly. */
6122 if (mips16_local_function_p (fn
))
6124 *fn_ptr
= mips16_local_alias (fn
);
6128 /* Create a SYMBOL_REF for the libgcc.a function. */
6130 sprintf (buf
, "__mips16_call_stub_%s_%d",
6131 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6134 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6135 stub_fn
= mips16_stub_function (buf
);
6137 /* The function uses $2 as an argument, so calls to it
6138 cannot be lazily bound. */
6139 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6141 /* Load the target function into $2. */
6142 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6143 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6145 /* Emit the call. */
6146 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6147 args_size
, NULL_RTX
, lazy_p
);
6149 /* Tell GCC that this call does indeed use the value of $2. */
6150 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6152 /* If we are handling a floating-point return value, we need to
6153 save $18 in the function prologue. Putting a note on the
6154 call will mean that df_regs_ever_live_p ($18) will be true if the
6155 call is not eliminated, and we can check that in the prologue
6158 CALL_INSN_FUNCTION_USAGE (insn
) =
6159 gen_rtx_EXPR_LIST (VOIDmode
,
6160 gen_rtx_CLOBBER (VOIDmode
,
6161 gen_rtx_REG (word_mode
, 18)),
6162 CALL_INSN_FUNCTION_USAGE (insn
));
6167 /* We know the function we are going to call. If we have already
6168 built a stub, we don't need to do anything further. */
6169 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6170 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6171 if (strcmp (l
->name
, fnname
) == 0)
6176 const char *separator
;
6177 char *secname
, *stubname
;
6178 tree stubid
, stubdecl
;
6181 /* If the function does not return in FPRs, the special stub
6185 If the function does return in FPRs, the stub section is named
6186 .mips16.call.fp.FNNAME
6188 Build a decl for the stub. */
6189 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6191 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6193 stubid
= get_identifier (stubname
);
6194 stubdecl
= build_decl (BUILTINS_LOCATION
,
6195 FUNCTION_DECL
, stubid
,
6196 build_function_type_list (void_type_node
,
6198 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6199 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6200 RESULT_DECL
, NULL_TREE
,
6203 /* Output a comment. */
6204 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6206 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6210 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6212 fprintf (asm_out_file
, "%s%s", separator
,
6213 (f
& 3) == 1 ? "float" : "double");
6216 fprintf (asm_out_file
, ")\n");
6218 /* Start the function definition. */
6219 assemble_start_function (stubdecl
, stubname
);
6220 mips_start_function_definition (stubname
, false);
6224 /* Load the address of the MIPS16 function into $25. Do this
6225 first so that targets with coprocessor interlocks can use
6226 an MFC1 to fill the delay slot. */
6227 if (TARGET_EXPLICIT_RELOCS
)
6229 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6230 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6233 output_asm_insn ("la\t%^,%0", &fn
);
6236 /* Move the arguments from general registers to floating-point
6238 mips_output_args_xfer (fp_code
, 't');
6242 /* Jump to the previously-loaded address. */
6243 output_asm_insn ("jr\t%^", NULL
);
6247 /* Save the return address in $18 and call the non-MIPS16 function.
6248 The stub's caller knows that $18 might be clobbered, even though
6249 $18 is usually a call-saved register. */
6250 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6251 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6252 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6254 /* Move the result from floating-point registers to
6255 general registers. */
6256 switch (GET_MODE (retval
))
6259 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6261 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6263 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6264 TARGET_LITTLE_ENDIAN
6265 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6267 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6269 /* On 64-bit targets, complex floats are returned in
6270 a single GPR, such that "sd" on a suitably-aligned
6271 target would store the value correctly. */
6272 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6273 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6274 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6275 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6276 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6277 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6278 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6279 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6280 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6281 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6282 reg_names
[GP_RETURN
],
6283 reg_names
[GP_RETURN
],
6284 reg_names
[GP_RETURN
+ 1]);
6289 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6293 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6294 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6298 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6304 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6307 #ifdef ASM_DECLARE_FUNCTION_SIZE
6308 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6311 mips_end_function_definition (stubname
);
6313 /* Record this stub. */
6314 l
= XNEW (struct mips16_stub
);
6315 l
->name
= xstrdup (fnname
);
6316 l
->fp_ret_p
= fp_ret_p
;
6317 l
->next
= mips16_stubs
;
6321 /* If we expect a floating-point return value, but we've built a
6322 stub which does not expect one, then we're in trouble. We can't
6323 use the existing stub, because it won't handle the floating-point
6324 value. We can't build a new stub, because the linker won't know
6325 which stub to use for the various calls in this object file.
6326 Fortunately, this case is illegal, since it means that a function
6327 was declared in two different ways in a single compilation. */
6328 if (fp_ret_p
&& !l
->fp_ret_p
)
6329 error ("cannot handle inconsistent calls to %qs", fnname
);
6331 if (retval
== NULL_RTX
)
6332 insn
= gen_call_internal_direct (fn
, args_size
);
6334 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6335 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6337 /* If we are calling a stub which handles a floating-point return
6338 value, we need to arrange to save $18 in the prologue. We do this
6339 by marking the function call as using the register. The prologue
6340 will later see that it is used, and emit code to save it. */
6342 CALL_INSN_FUNCTION_USAGE (insn
) =
6343 gen_rtx_EXPR_LIST (VOIDmode
,
6344 gen_rtx_CLOBBER (VOIDmode
,
6345 gen_rtx_REG (word_mode
, 18)),
6346 CALL_INSN_FUNCTION_USAGE (insn
));
6351 /* Expand a call of type TYPE. RESULT is where the result will go (null
6352 for "call"s and "sibcall"s), ADDR is the address of the function,
6353 ARGS_SIZE is the size of the arguments and AUX is the value passed
6354 to us by mips_function_arg. LAZY_P is true if this call already
6355 involves a lazily-bound function address (such as when calling
6356 functions through a MIPS16 hard-float stub).
6358 Return the call itself. */
6361 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6362 rtx args_size
, rtx aux
, bool lazy_p
)
6364 rtx orig_addr
, pattern
, insn
;
6367 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6368 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6371 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6376 if (!call_insn_operand (addr
, VOIDmode
))
6378 if (type
== MIPS_CALL_EPILOGUE
)
6379 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6381 addr
= gen_reg_rtx (Pmode
);
6382 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6387 rtx (*fn
) (rtx
, rtx
);
6389 if (type
== MIPS_CALL_SIBCALL
)
6390 fn
= gen_sibcall_internal
;
6392 fn
= gen_call_internal
;
6394 pattern
= fn (addr
, args_size
);
6396 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6398 /* Handle return values created by mips_return_fpr_pair. */
6399 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6402 if (type
== MIPS_CALL_SIBCALL
)
6403 fn
= gen_sibcall_value_multiple_internal
;
6405 fn
= gen_call_value_multiple_internal
;
6407 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6408 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6409 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6413 rtx (*fn
) (rtx
, rtx
, rtx
);
6415 if (type
== MIPS_CALL_SIBCALL
)
6416 fn
= gen_sibcall_value_internal
;
6418 fn
= gen_call_value_internal
;
6420 /* Handle return values created by mips_return_fpr_single. */
6421 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6422 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6423 pattern
= fn (result
, addr
, args_size
);
6426 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6429 /* Split call instruction INSN into a $gp-clobbering call and
6430 (where necessary) an instruction to restore $gp from its save slot.
6431 CALL_PATTERN is the pattern of the new call. */
6434 mips_split_call (rtx insn
, rtx call_pattern
)
6436 emit_call_insn (call_pattern
);
6437 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6438 /* Pick a temporary register that is suitable for both MIPS16 and
6439 non-MIPS16 code. $4 and $5 are used for returning complex double
6440 values in soft-float code, so $6 is the first suitable candidate. */
6441 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6444 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6447 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
6449 if (!TARGET_SIBCALLS
)
6452 /* Interrupt handlers need special epilogue code and therefore can't
6454 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
6457 /* We can't do a sibcall if the called function is a MIPS16 function
6458 because there is no direct "jx" instruction equivalent to "jalx" to
6459 switch the ISA mode. We only care about cases where the sibling
6460 and normal calls would both be direct. */
6462 && mips_use_mips16_mode_p (decl
)
6463 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6466 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6467 functions could be MIPS16 ones unless an attribute explicitly tells
6469 if (TARGET_INTERLINK_MIPS16
6471 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
6472 && !mips_nomips16_decl_p (decl
)
6473 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6480 /* Emit code to move general operand SRC into condition-code
6481 register DEST given that SCRATCH is a scratch TFmode FPR.
6488 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6491 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
6495 /* Change the source to SFmode. */
6497 src
= adjust_address (src
, SFmode
, 0);
6498 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
6499 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
6501 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
6502 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
6504 mips_emit_move (copy_rtx (fp1
), src
);
6505 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
6506 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
6509 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6510 Assume that the areas do not overlap. */
6513 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
6515 HOST_WIDE_INT offset
, delta
;
6516 unsigned HOST_WIDE_INT bits
;
6518 enum machine_mode mode
;
6521 /* Work out how many bits to move at a time. If both operands have
6522 half-word alignment, it is usually better to move in half words.
6523 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6524 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6525 Otherwise move word-sized chunks. */
6526 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
6527 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
6528 bits
= BITS_PER_WORD
/ 2;
6530 bits
= BITS_PER_WORD
;
6532 mode
= mode_for_size (bits
, MODE_INT
, 0);
6533 delta
= bits
/ BITS_PER_UNIT
;
6535 /* Allocate a buffer for the temporary registers. */
6536 regs
= XALLOCAVEC (rtx
, length
/ delta
);
6538 /* Load as many BITS-sized chunks as possible. Use a normal load if
6539 the source has enough alignment, otherwise use left/right pairs. */
6540 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6542 regs
[i
] = gen_reg_rtx (mode
);
6543 if (MEM_ALIGN (src
) >= bits
)
6544 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
6547 rtx part
= adjust_address (src
, BLKmode
, offset
);
6548 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0))
6553 /* Copy the chunks to the destination. */
6554 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6555 if (MEM_ALIGN (dest
) >= bits
)
6556 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
6559 rtx part
= adjust_address (dest
, BLKmode
, offset
);
6560 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
6564 /* Mop up any left-over bytes. */
6565 if (offset
< length
)
6567 src
= adjust_address (src
, BLKmode
, offset
);
6568 dest
= adjust_address (dest
, BLKmode
, offset
);
6569 move_by_pieces (dest
, src
, length
- offset
,
6570 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
6574 /* Helper function for doing a loop-based block operation on memory
6575 reference MEM. Each iteration of the loop will operate on LENGTH
6578 Create a new base register for use within the loop and point it to
6579 the start of MEM. Create a new memory reference that uses this
6580 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6583 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
6584 rtx
*loop_reg
, rtx
*loop_mem
)
6586 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
6588 /* Although the new mem does not refer to a known location,
6589 it does keep up to LENGTH bytes of alignment. */
6590 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
6591 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
6594 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6595 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6596 the memory regions do not overlap. */
6599 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
6600 HOST_WIDE_INT bytes_per_iter
)
6602 rtx label
, src_reg
, dest_reg
, final_src
, test
;
6603 HOST_WIDE_INT leftover
;
6605 leftover
= length
% bytes_per_iter
;
6608 /* Create registers and memory references for use within the loop. */
6609 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
6610 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
6612 /* Calculate the value that SRC_REG should have after the last iteration
6614 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
6617 /* Emit the start of the loop. */
6618 label
= gen_label_rtx ();
6621 /* Emit the loop body. */
6622 mips_block_move_straight (dest
, src
, bytes_per_iter
);
6624 /* Move on to the next block. */
6625 mips_emit_move (src_reg
, plus_constant (src_reg
, bytes_per_iter
));
6626 mips_emit_move (dest_reg
, plus_constant (dest_reg
, bytes_per_iter
));
6628 /* Emit the loop condition. */
6629 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
6630 if (Pmode
== DImode
)
6631 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
6633 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
6635 /* Mop up any left-over bytes. */
6637 mips_block_move_straight (dest
, src
, leftover
);
6640 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6641 memory reference SRC to memory reference DEST. */
6644 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
6646 if (CONST_INT_P (length
))
6648 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
6650 mips_block_move_straight (dest
, src
, INTVAL (length
));
6655 mips_block_move_loop (dest
, src
, INTVAL (length
),
6656 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
6663 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6666 mips_expand_synci_loop (rtx begin
, rtx end
)
6668 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
6670 /* Create end_label. */
6671 end_label
= gen_label_rtx ();
6673 /* Check if begin equals end. */
6674 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
6675 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
6677 /* Load INC with the cache line size (rdhwr INC,$1). */
6678 inc
= gen_reg_rtx (Pmode
);
6679 emit_insn (Pmode
== SImode
6680 ? gen_rdhwr_synci_step_si (inc
)
6681 : gen_rdhwr_synci_step_di (inc
));
6683 /* Check if inc is 0. */
6684 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
6685 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
6687 /* Calculate mask. */
6688 mask
= mips_force_unary (Pmode
, NEG
, inc
);
6690 /* Mask out begin by mask. */
6691 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
6693 /* Calculate length. */
6694 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
6696 /* Loop back to here. */
6697 label
= gen_label_rtx ();
6700 emit_insn (gen_synci (begin
));
6702 /* Update length. */
6703 mips_emit_binary (MINUS
, length
, length
, inc
);
6706 mips_emit_binary (PLUS
, begin
, begin
, inc
);
6708 /* Check if length is greater than 0. */
6709 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
6710 emit_jump_insn (gen_condjump (cmp_result
, label
));
6712 emit_label (end_label
);
6715 /* Expand a QI or HI mode atomic memory operation.
6717 GENERATOR contains a pointer to the gen_* function that generates
6718 the SI mode underlying atomic operation using masks that we
6721 RESULT is the return register for the operation. Its value is NULL
6724 MEM is the location of the atomic access.
6726 OLDVAL is the first operand for the operation.
6728 NEWVAL is the optional second operand for the operation. Its value
6729 is NULL if unused. */
6732 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
6733 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
6735 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
6736 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
6738 enum machine_mode mode
;
6740 mode
= GET_MODE (mem
);
6742 /* Compute the address of the containing SImode value. */
6743 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
6744 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
6745 force_reg (Pmode
, GEN_INT (-4)));
6747 /* Create a memory reference for it. */
6748 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
6749 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
6750 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
6752 /* Work out the byte offset of the QImode or HImode value,
6753 counting from the least significant byte. */
6754 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
6755 if (TARGET_BIG_ENDIAN
)
6756 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
6758 /* Multiply by eight to convert the shift value from bytes to bits. */
6759 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
6761 /* Make the final shift an SImode value, so that it can be used in
6762 SImode operations. */
6763 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
6765 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6766 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
6767 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
6768 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
6770 /* Compute the equivalent exclusive mask. */
6771 inverted_mask
= gen_reg_rtx (SImode
);
6772 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
6773 gen_rtx_NOT (SImode
, mask
)));
6775 /* Shift the old value into place. */
6776 if (oldval
!= const0_rtx
)
6778 oldval
= convert_modes (SImode
, mode
, oldval
, true);
6779 oldval
= force_reg (SImode
, oldval
);
6780 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
6783 /* Do the same for the new value. */
6784 if (newval
&& newval
!= const0_rtx
)
6786 newval
= convert_modes (SImode
, mode
, newval
, true);
6787 newval
= force_reg (SImode
, newval
);
6788 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
6791 /* Do the SImode atomic access. */
6793 res
= gen_reg_rtx (SImode
);
6795 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
6797 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
6799 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
6805 /* Shift and convert the result. */
6806 mips_emit_binary (AND
, res
, res
, mask
);
6807 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
6808 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
6812 /* Return true if it is possible to use left/right accesses for a
6813 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6814 returning true, update *OP, *LEFT and *RIGHT as follows:
6816 *OP is a BLKmode reference to the whole field.
6818 *LEFT is a QImode reference to the first byte if big endian or
6819 the last byte if little endian. This address can be used in the
6820 left-side instructions (LWL, SWL, LDL, SDL).
6822 *RIGHT is a QImode reference to the opposite end of the field and
6823 can be used in the patterning right-side instruction. */
6826 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
6827 rtx
*left
, rtx
*right
)
6831 /* Check that the operand really is a MEM. Not all the extv and
6832 extzv predicates are checked. */
6836 /* Check that the size is valid. */
6837 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
6840 /* We can only access byte-aligned values. Since we are always passed
6841 a reference to the first byte of the field, it is not necessary to
6842 do anything with BITPOS after this check. */
6843 if (bitpos
% BITS_PER_UNIT
!= 0)
6846 /* Reject aligned bitfields: we want to use a normal load or store
6847 instead of a left/right pair. */
6848 if (MEM_ALIGN (*op
) >= width
)
6851 /* Adjust *OP to refer to the whole field. This also has the effect
6852 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6853 *op
= adjust_address (*op
, BLKmode
, 0);
6854 set_mem_size (*op
, width
/ BITS_PER_UNIT
);
6856 /* Get references to both ends of the field. We deliberately don't
6857 use the original QImode *OP for FIRST since the new BLKmode one
6858 might have a simpler address. */
6859 first
= adjust_address (*op
, QImode
, 0);
6860 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
6862 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6863 correspond to the MSB and RIGHT to the LSB. */
6864 if (TARGET_BIG_ENDIAN
)
6865 *left
= first
, *right
= last
;
6867 *left
= last
, *right
= first
;
6872 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6873 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6874 the operation is the equivalent of:
6876 (set DEST (*_extract SRC WIDTH BITPOS))
6878 Return true on success. */
6881 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
6882 HOST_WIDE_INT bitpos
)
6884 rtx left
, right
, temp
;
6886 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6887 be a paradoxical word_mode subreg. This is the only case in which
6888 we allow the destination to be larger than the source. */
6889 if (GET_CODE (dest
) == SUBREG
6890 && GET_MODE (dest
) == DImode
6891 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
6892 dest
= SUBREG_REG (dest
);
6894 /* After the above adjustment, the destination must be the same
6895 width as the source. */
6896 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
6899 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
6902 temp
= gen_reg_rtx (GET_MODE (dest
));
6903 if (GET_MODE (dest
) == DImode
)
6905 emit_insn (gen_mov_ldl (temp
, src
, left
));
6906 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
6910 emit_insn (gen_mov_lwl (temp
, src
, left
));
6911 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
6916 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6917 BITPOS and SRC are the operands passed to the expander; the operation
6918 is the equivalent of:
6920 (set (zero_extract DEST WIDTH BITPOS) SRC)
6922 Return true on success. */
6925 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
6926 HOST_WIDE_INT bitpos
)
6929 enum machine_mode mode
;
6931 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
6934 mode
= mode_for_size (width
, MODE_INT
, 0);
6935 src
= gen_lowpart (mode
, src
);
6938 emit_insn (gen_mov_sdl (dest
, src
, left
));
6939 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
6943 emit_insn (gen_mov_swl (dest
, src
, left
));
6944 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
6949 /* Return true if X is a MEM with the same size as MODE. */
6952 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
6955 && MEM_SIZE_KNOWN_P (x
)
6956 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
6959 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6960 source of an "ext" instruction or the destination of an "ins"
6961 instruction. OP must be a register operand and the following
6962 conditions must hold:
6964 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6965 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6966 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6968 Also reject lengths equal to a word as they are better handled
6969 by the move patterns. */
6972 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
6974 if (!ISA_HAS_EXT_INS
6975 || !register_operand (op
, VOIDmode
)
6976 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
6979 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
6982 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
6988 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6989 operation if MAXLEN is the maxium length of consecutive bits that
6990 can make up MASK. MODE is the mode of the operation. See
6991 mask_low_and_shift_len for the actual definition. */
6994 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
6996 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
6999 /* Return true iff OP1 and OP2 are valid operands together for the
7000 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7001 see the table in the comment before the pattern. */
7004 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7006 return (memory_operand (op1
, mode
)
7007 ? and_load_operand (op2
, mode
)
7008 : and_reg_operand (op2
, mode
));
7011 /* The canonical form of a mask-low-and-shift-left operation is
7012 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7013 cleared. Thus we need to shift MASK to the right before checking if it
7014 is a valid mask value. MODE is the mode of the operation. If true
7015 return the length of the mask, otherwise return -1. */
7018 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7020 HOST_WIDE_INT shval
;
7022 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7023 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7026 /* Return true if -msplit-addresses is selected and should be honored.
7028 -msplit-addresses is a half-way house between explicit relocations
7029 and the traditional assembler macros. It can split absolute 32-bit
7030 symbolic constants into a high/lo_sum pair but uses macros for other
7033 Like explicit relocation support for REL targets, it relies
7034 on GNU extensions in the assembler and the linker.
7036 Although this code should work for -O0, it has traditionally
7037 been treated as an optimization. */
7040 mips_split_addresses_p (void)
7042 return (TARGET_SPLIT_ADDRESSES
7046 && !ABI_HAS_64BIT_SYMBOLS
);
7049 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7052 mips_init_relocs (void)
7054 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7055 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7056 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7057 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7059 if (ABI_HAS_64BIT_SYMBOLS
)
7061 if (TARGET_EXPLICIT_RELOCS
)
7063 mips_split_p
[SYMBOL_64_HIGH
] = true;
7064 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7065 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7067 mips_split_p
[SYMBOL_64_MID
] = true;
7068 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7069 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7071 mips_split_p
[SYMBOL_64_LOW
] = true;
7072 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7073 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7075 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7076 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7081 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses_p () || TARGET_MIPS16
)
7083 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7084 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7085 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7087 mips_lo_relocs
[SYMBOL_32_HIGH
] = "%hi(";
7093 /* The high part is provided by a pseudo copy of $gp. */
7094 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7095 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7097 else if (TARGET_EXPLICIT_RELOCS
)
7098 /* Small data constants are kept whole until after reload,
7099 then lowered by mips_rewrite_small_data. */
7100 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7102 if (TARGET_EXPLICIT_RELOCS
)
7104 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7107 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7108 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7112 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7113 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7116 /* Expose the use of $28 as soon as possible. */
7117 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7121 /* The HIGH and LO_SUM are matched by special .md patterns. */
7122 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7124 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7125 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7126 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7128 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7129 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7130 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7135 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7137 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7138 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7140 /* Expose the use of $28 as soon as possible. */
7141 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7147 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7148 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7149 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7152 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7153 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7155 mips_split_p
[SYMBOL_DTPREL
] = true;
7156 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7157 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7159 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7161 mips_split_p
[SYMBOL_TPREL
] = true;
7162 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7163 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7165 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7168 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7169 in context CONTEXT. RELOCS is the array of relocations to use. */
7172 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7173 const char **relocs
)
7175 enum mips_symbol_type symbol_type
;
7178 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7179 gcc_assert (relocs
[symbol_type
]);
7181 fputs (relocs
[symbol_type
], file
);
7182 output_addr_const (file
, mips_strip_unspec_address (op
));
7183 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7188 /* Start a new block with the given asm switch enabled. If we need
7189 to print a directive, emit PREFIX before it and SUFFIX after it. */
7192 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7193 const char *prefix
, const char *suffix
)
7195 if (asm_switch
->nesting_level
== 0)
7196 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7197 asm_switch
->nesting_level
++;
7200 /* Likewise, but end a block. */
7203 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7204 const char *prefix
, const char *suffix
)
7206 gcc_assert (asm_switch
->nesting_level
);
7207 asm_switch
->nesting_level
--;
7208 if (asm_switch
->nesting_level
== 0)
7209 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7212 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7213 that either print a complete line or print nothing. */
7216 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7218 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7222 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7224 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7227 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7228 The punctuation characters are:
7230 '(' Start a nested ".set noreorder" block.
7231 ')' End a nested ".set noreorder" block.
7232 '[' Start a nested ".set noat" block.
7233 ']' End a nested ".set noat" block.
7234 '<' Start a nested ".set nomacro" block.
7235 '>' End a nested ".set nomacro" block.
7236 '*' Behave like %(%< if generating a delayed-branch sequence.
7237 '#' Print a nop if in a ".set noreorder" block.
7238 '/' Like '#', but do nothing within a delayed-branch sequence.
7239 '?' Print "l" if mips_branch_likely is true
7240 '~' Print a nop if mips_branch_likely is true
7241 '.' Print the name of the register with a hard-wired zero (zero or $0).
7242 '@' Print the name of the assembler temporary register (at or $1).
7243 '^' Print the name of the pic call-through register (t9 or $25).
7244 '+' Print the name of the gp register (usually gp or $28).
7245 '$' Print the name of the stack pointer register (sp or $29).
7247 See also mips_init_print_operand_pucnt. */
7250 mips_print_operand_punctuation (FILE *file
, int ch
)
7255 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7259 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7263 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7267 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7271 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7275 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7279 if (final_sequence
!= 0)
7281 mips_print_operand_punctuation (file
, '(');
7282 mips_print_operand_punctuation (file
, '<');
7287 if (mips_noreorder
.nesting_level
> 0)
7288 fputs ("\n\tnop", file
);
7292 /* Print an extra newline so that the delayed insn is separated
7293 from the following ones. This looks neater and is consistent
7294 with non-nop delayed sequences. */
7295 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7296 fputs ("\n\tnop\n", file
);
7300 if (mips_branch_likely
)
7305 if (mips_branch_likely
)
7306 fputs ("\n\tnop", file
);
7310 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7314 fputs (reg_names
[AT_REGNUM
], file
);
7318 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7322 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7326 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7335 /* Initialize mips_print_operand_punct. */
7338 mips_init_print_operand_punct (void)
7342 for (p
= "()[]<>*#/?~.@^+$"; *p
; p
++)
7343 mips_print_operand_punct
[(unsigned char) *p
] = true;
7346 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7347 associated with condition CODE. Print the condition part of the
7351 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7365 /* Conveniently, the MIPS names for these conditions are the same
7366 as their RTL equivalents. */
7367 fputs (GET_RTX_NAME (code
), file
);
7371 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7376 /* Likewise floating-point branches. */
7379 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7384 fputs ("c1f", file
);
7388 fputs ("c1t", file
);
7392 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7397 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7400 mips_print_operand_punct_valid_p (unsigned char code
)
7402 return mips_print_operand_punct
[code
];
7405 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7407 'X' Print CONST_INT OP in hexadecimal format.
7408 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7409 'd' Print CONST_INT OP in decimal.
7410 'm' Print one less than CONST_INT OP in decimal.
7411 'h' Print the high-part relocation associated with OP, after stripping
7413 'R' Print the low-part relocation associated with OP.
7414 'C' Print the integer branch condition for comparison OP.
7415 'N' Print the inverse of the integer branch condition for comparison OP.
7416 'F' Print the FPU branch condition for comparison OP.
7417 'W' Print the inverse of the FPU branch condition for comparison OP.
7418 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7419 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7420 't' Like 'T', but with the EQ/NE cases reversed
7421 'Y' Print mips_fp_conditions[INTVAL (OP)]
7422 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7423 'q' Print a DSP accumulator register.
7424 'D' Print the second part of a double-word register or memory operand.
7425 'L' Print the low-order register in a double-word register operand.
7426 'M' Print high-order register in a double-word register operand.
7427 'z' Print $0 if OP is zero, otherwise print OP normally. */
7430 mips_print_operand (FILE *file
, rtx op
, int letter
)
7434 if (mips_print_operand_punct_valid_p (letter
))
7436 mips_print_operand_punctuation (file
, letter
);
7441 code
= GET_CODE (op
);
7446 if (CONST_INT_P (op
))
7447 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
7449 output_operand_lossage ("invalid use of '%%%c'", letter
);
7453 if (CONST_INT_P (op
))
7454 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
7456 output_operand_lossage ("invalid use of '%%%c'", letter
);
7460 if (CONST_INT_P (op
))
7461 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
7463 output_operand_lossage ("invalid use of '%%%c'", letter
);
7467 if (CONST_INT_P (op
))
7468 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
7470 output_operand_lossage ("invalid use of '%%%c'", letter
);
7476 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
7480 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
7484 mips_print_int_branch_condition (file
, code
, letter
);
7488 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
7492 mips_print_float_branch_condition (file
, code
, letter
);
7496 mips_print_float_branch_condition (file
, reverse_condition (code
),
7503 int truth
= (code
== NE
) == (letter
== 'T');
7504 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
7509 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
7510 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
7512 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7519 mips_print_operand (file
, op
, 0);
7525 if (code
== REG
&& MD_REG_P (REGNO (op
)))
7526 fprintf (file
, "$ac0");
7527 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
7528 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
7530 output_operand_lossage ("invalid use of '%%%c'", letter
);
7538 unsigned int regno
= REGNO (op
);
7539 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
7540 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
7543 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
7544 output_operand_lossage ("invalid use of '%%%c'", letter
);
7545 /* We need to print $0 .. $31 for COP0 registers. */
7546 if (COP0_REG_P (regno
))
7547 fprintf (file
, "$%s", ®_names
[regno
][4]);
7549 fprintf (file
, "%s", reg_names
[regno
]);
7555 output_address (plus_constant (XEXP (op
, 0), 4));
7556 else if (letter
&& letter
!= 'z')
7557 output_operand_lossage ("invalid use of '%%%c'", letter
);
7559 output_address (XEXP (op
, 0));
7563 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
7564 fputs (reg_names
[GP_REG_FIRST
], file
);
7565 else if (letter
&& letter
!= 'z')
7566 output_operand_lossage ("invalid use of '%%%c'", letter
);
7567 else if (CONST_GP_P (op
))
7568 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
7570 output_addr_const (file
, mips_strip_unspec_address (op
));
7576 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7579 mips_print_operand_address (FILE *file
, rtx x
)
7581 struct mips_address_info addr
;
7583 if (mips_classify_address (&addr
, x
, word_mode
, true))
7587 mips_print_operand (file
, addr
.offset
, 0);
7588 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
7591 case ADDRESS_LO_SUM
:
7592 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
7594 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
7597 case ADDRESS_CONST_INT
:
7598 output_addr_const (file
, x
);
7599 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
7602 case ADDRESS_SYMBOLIC
:
7603 output_addr_const (file
, mips_strip_unspec_address (x
));
7609 /* Implement TARGET_ENCODE_SECTION_INFO. */
7612 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
7614 default_encode_section_info (decl
, rtl
, first
);
7616 if (TREE_CODE (decl
) == FUNCTION_DECL
)
7618 rtx symbol
= XEXP (rtl
, 0);
7619 tree type
= TREE_TYPE (decl
);
7621 /* Encode whether the symbol is short or long. */
7622 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
7623 || mips_far_type_p (type
))
7624 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
7628 /* Implement TARGET_SELECT_RTX_SECTION. */
7631 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
7632 unsigned HOST_WIDE_INT align
)
7634 /* ??? Consider using mergeable small data sections. */
7635 if (mips_rtx_constant_in_small_data_p (mode
))
7636 return get_named_section (NULL
, ".sdata", 0);
7638 return default_elf_select_rtx_section (mode
, x
, align
);
7641 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7643 The complication here is that, with the combination TARGET_ABICALLS
7644 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7645 absolute addresses, and should therefore not be included in the
7646 read-only part of a DSO. Handle such cases by selecting a normal
7647 data section instead of a read-only one. The logic apes that in
7648 default_function_rodata_section. */
7651 mips_function_rodata_section (tree decl
)
7653 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
7654 return default_function_rodata_section (decl
);
7656 if (decl
&& DECL_SECTION_NAME (decl
))
7658 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7659 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
7661 char *rname
= ASTRDUP (name
);
7663 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
7665 else if (flag_function_sections
7666 && flag_data_sections
7667 && strncmp (name
, ".text.", 6) == 0)
7669 char *rname
= ASTRDUP (name
);
7670 memcpy (rname
+ 1, "data", 4);
7671 return get_section (rname
, SECTION_WRITE
, decl
);
7674 return data_section
;
7677 /* Implement TARGET_IN_SMALL_DATA_P. */
7680 mips_in_small_data_p (const_tree decl
)
7682 unsigned HOST_WIDE_INT size
;
7684 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
7687 /* We don't yet generate small-data references for -mabicalls
7688 or VxWorks RTP code. See the related -G handling in
7689 mips_option_override. */
7690 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
7693 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
7697 /* Reject anything that isn't in a known small-data section. */
7698 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7699 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
7702 /* If a symbol is defined externally, the assembler will use the
7703 usual -G rules when deciding how to implement macros. */
7704 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
7707 else if (TARGET_EMBEDDED_DATA
)
7709 /* Don't put constants into the small data section: we want them
7710 to be in ROM rather than RAM. */
7711 if (TREE_CODE (decl
) != VAR_DECL
)
7714 if (TREE_READONLY (decl
)
7715 && !TREE_SIDE_EFFECTS (decl
)
7716 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
7720 /* Enforce -mlocal-sdata. */
7721 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
7724 /* Enforce -mextern-sdata. */
7725 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
7727 if (DECL_EXTERNAL (decl
))
7729 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
7733 /* We have traditionally not treated zero-sized objects as small data,
7734 so this is now effectively part of the ABI. */
7735 size
= int_size_in_bytes (TREE_TYPE (decl
));
7736 return size
> 0 && size
<= mips_small_data_threshold
;
7739 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7740 anchors for small data: the GP register acts as an anchor in that
7741 case. We also don't want to use them for PC-relative accesses,
7742 where the PC acts as an anchor. */
7745 mips_use_anchors_for_symbol_p (const_rtx symbol
)
7747 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
7749 case SYMBOL_PC_RELATIVE
:
7750 case SYMBOL_GP_RELATIVE
:
7754 return default_use_anchors_for_symbol_p (symbol
);
7758 /* The MIPS debug format wants all automatic variables and arguments
7759 to be in terms of the virtual frame pointer (stack pointer before
7760 any adjustment in the function), while the MIPS 3.0 linker wants
7761 the frame pointer to be the stack pointer after the initial
7762 adjustment. So, we do the adjustment here. The arg pointer (which
7763 is eliminated) points to the virtual frame pointer, while the frame
7764 pointer (which may be eliminated) points to the stack pointer after
7765 the initial adjustments. */
7768 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
7770 rtx offset2
= const0_rtx
;
7771 rtx reg
= eliminate_constant_term (addr
, &offset2
);
7774 offset
= INTVAL (offset2
);
7776 if (reg
== stack_pointer_rtx
7777 || reg
== frame_pointer_rtx
7778 || reg
== hard_frame_pointer_rtx
)
7780 offset
-= cfun
->machine
->frame
.total_size
;
7781 if (reg
== hard_frame_pointer_rtx
)
7782 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
7785 /* sdbout_parms does not want this to crash for unrecognized cases. */
7787 else if (reg
!= arg_pointer_rtx
)
7788 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7795 /* Implement ASM_OUTPUT_EXTERNAL. */
7798 mips_output_external (FILE *file
, tree decl
, const char *name
)
7800 default_elf_asm_output_external (file
, decl
, name
);
7802 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7803 set in order to avoid putting out names that are never really
7805 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
7807 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
7809 /* When using assembler macros, emit .extern directives for
7810 all small-data externs so that the assembler knows how
7813 In most cases it would be safe (though pointless) to emit
7814 .externs for other symbols too. One exception is when an
7815 object is within the -G limit but declared by the user to
7816 be in a section other than .sbss or .sdata. */
7817 fputs ("\t.extern\t", file
);
7818 assemble_name (file
, name
);
7819 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
7820 int_size_in_bytes (TREE_TYPE (decl
)));
7825 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7828 mips_output_filename (FILE *stream
, const char *name
)
7830 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7832 if (write_symbols
== DWARF2_DEBUG
)
7834 else if (mips_output_filename_first_time
)
7836 mips_output_filename_first_time
= 0;
7837 num_source_filenames
+= 1;
7838 current_function_file
= name
;
7839 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7840 output_quoted_string (stream
, name
);
7841 putc ('\n', stream
);
7843 /* If we are emitting stabs, let dbxout.c handle this (except for
7844 the mips_output_filename_first_time case). */
7845 else if (write_symbols
== DBX_DEBUG
)
7847 else if (name
!= current_function_file
7848 && strcmp (name
, current_function_file
) != 0)
7850 num_source_filenames
+= 1;
7851 current_function_file
= name
;
7852 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7853 output_quoted_string (stream
, name
);
7854 putc ('\n', stream
);
7858 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7860 static void ATTRIBUTE_UNUSED
7861 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7866 fputs ("\t.dtprelword\t", file
);
7870 fputs ("\t.dtpreldword\t", file
);
7876 output_addr_const (file
, x
);
7877 fputs ("+0x8000", file
);
7880 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7883 mips_dwarf_register_span (rtx reg
)
7886 enum machine_mode mode
;
7888 /* By default, GCC maps increasing register numbers to increasing
7889 memory locations, but paired FPRs are always little-endian,
7890 regardless of the prevailing endianness. */
7891 mode
= GET_MODE (reg
);
7892 if (FP_REG_P (REGNO (reg
))
7893 && TARGET_BIG_ENDIAN
7894 && MAX_FPRS_PER_FMT
> 1
7895 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
7897 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
7898 high
= mips_subword (reg
, true);
7899 low
= mips_subword (reg
, false);
7900 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
7906 /* Implement ASM_OUTPUT_ASCII. */
7909 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
7915 fprintf (stream
, "\t.ascii\t\"");
7916 for (i
= 0; i
< len
; i
++)
7920 c
= (unsigned char) string
[i
];
7923 if (c
== '\\' || c
== '\"')
7925 putc ('\\', stream
);
7933 fprintf (stream
, "\\%03o", c
);
7937 if (cur_pos
> 72 && i
+1 < len
)
7940 fprintf (stream
, "\"\n\t.ascii\t\"");
7943 fprintf (stream
, "\"\n");
7946 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7947 macros, mark the symbol as written so that mips_asm_output_external
7948 won't emit an .extern for it. STREAM is the output file, NAME is the
7949 name of the symbol, INIT_STRING is the string that should be written
7950 before the symbol and FINAL_STRING is the string that should be
7951 written after it. FINAL_STRING is a printf format that consumes the
7952 remaining arguments. */
7955 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
7956 const char *final_string
, ...)
7960 fputs (init_string
, stream
);
7961 assemble_name (stream
, name
);
7962 va_start (ap
, final_string
);
7963 vfprintf (stream
, final_string
, ap
);
7966 if (!TARGET_EXPLICIT_RELOCS
)
7968 tree name_tree
= get_identifier (name
);
7969 TREE_ASM_WRITTEN (name_tree
) = 1;
7973 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7974 NAME is the name of the object and ALIGN is the required alignment
7975 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7976 alignment argument. */
7979 mips_declare_common_object (FILE *stream
, const char *name
,
7980 const char *init_string
,
7981 unsigned HOST_WIDE_INT size
,
7982 unsigned int align
, bool takes_alignment_p
)
7984 if (!takes_alignment_p
)
7986 size
+= (align
/ BITS_PER_UNIT
) - 1;
7987 size
-= size
% (align
/ BITS_PER_UNIT
);
7988 mips_declare_object (stream
, name
, init_string
,
7989 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
7992 mips_declare_object (stream
, name
, init_string
,
7993 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
7994 size
, align
/ BITS_PER_UNIT
);
7997 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7998 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8001 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8002 unsigned HOST_WIDE_INT size
,
8005 /* If the target wants uninitialized const declarations in
8006 .rdata then don't put them in .comm. */
8007 if (TARGET_EMBEDDED_DATA
8008 && TARGET_UNINIT_CONST_IN_RODATA
8009 && TREE_CODE (decl
) == VAR_DECL
8010 && TREE_READONLY (decl
)
8011 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8013 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8014 targetm
.asm_out
.globalize_label (stream
, name
);
8016 switch_to_section (readonly_data_section
);
8017 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8018 mips_declare_object (stream
, name
, "",
8019 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8023 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8027 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8028 extern int size_directive_output
;
8030 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8031 definitions except that it uses mips_declare_object to emit the label. */
8034 mips_declare_object_name (FILE *stream
, const char *name
,
8035 tree decl ATTRIBUTE_UNUSED
)
8037 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8038 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8041 size_directive_output
= 0;
8042 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8046 size_directive_output
= 1;
8047 size
= int_size_in_bytes (TREE_TYPE (decl
));
8048 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8051 mips_declare_object (stream
, name
, "", ":\n");
8054 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8057 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8061 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8062 if (!flag_inhibit_size_directive
8063 && DECL_SIZE (decl
) != 0
8066 && DECL_INITIAL (decl
) == error_mark_node
8067 && !size_directive_output
)
8071 size_directive_output
= 1;
8072 size
= int_size_in_bytes (TREE_TYPE (decl
));
8073 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8078 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8079 with the current ABI. */
8082 mips_mdebug_abi_name (void)
8095 return TARGET_64BIT
? "eabi64" : "eabi32";
8101 /* Implement TARGET_ASM_FILE_START. */
8104 mips_file_start (void)
8106 default_file_start ();
8108 /* Generate a special section to describe the ABI switches used to
8109 produce the resultant binary. This is unnecessary on IRIX and
8110 causes unwanted warnings from the native linker. */
8113 /* Record the ABI itself. Modern versions of binutils encode
8114 this information in the ELF header flags, but GDB needs the
8115 information in order to correctly debug binaries produced by
8116 older binutils. See the function mips_gdbarch_init in
8118 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8119 mips_mdebug_abi_name ());
8121 /* There is no ELF header flag to distinguish long32 forms of the
8122 EABI from long64 forms. Emit a special section to help tools
8123 such as GDB. Do the same for o64, which is sometimes used with
8125 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8126 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8127 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8129 #ifdef HAVE_AS_GNU_ATTRIBUTE
8133 /* No floating-point operations, -mno-float. */
8134 if (TARGET_NO_FLOAT
)
8136 /* Soft-float code, -msoft-float. */
8137 else if (!TARGET_HARD_FLOAT_ABI
)
8139 /* Single-float code, -msingle-float. */
8140 else if (!TARGET_DOUBLE_FLOAT
)
8142 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8143 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8145 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8149 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8154 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8155 if (TARGET_ABICALLS
)
8157 fprintf (asm_out_file
, "\t.abicalls\n");
8158 if (TARGET_ABICALLS_PIC0
)
8159 fprintf (asm_out_file
, "\t.option\tpic0\n");
8162 if (flag_verbose_asm
)
8163 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8165 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8168 /* Make the last instruction frame-related and note that it performs
8169 the operation described by FRAME_PATTERN. */
8172 mips_set_frame_expr (rtx frame_pattern
)
8176 insn
= get_last_insn ();
8177 RTX_FRAME_RELATED_P (insn
) = 1;
8178 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8183 /* Return a frame-related rtx that stores REG at MEM.
8184 REG must be a single register. */
8187 mips_frame_set (rtx mem
, rtx reg
)
8191 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8192 RTX_FRAME_RELATED_P (set
) = 1;
8197 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8198 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8199 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8200 static const unsigned char mips16e_s2_s8_regs
[] = {
8201 30, 23, 22, 21, 20, 19, 18
8203 static const unsigned char mips16e_a0_a3_regs
[] = {
8207 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8208 ordered from the uppermost in memory to the lowest in memory. */
8209 static const unsigned char mips16e_save_restore_regs
[] = {
8210 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8213 /* Return the index of the lowest X in the range [0, SIZE) for which
8214 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8217 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8222 for (i
= 0; i
< size
; i
++)
8223 if (BITSET_P (mask
, regs
[i
]))
8229 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8230 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8231 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8232 is true for all indexes (X, SIZE). */
8235 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8236 unsigned int size
, unsigned int *num_regs_ptr
)
8240 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8241 for (i
++; i
< size
; i
++)
8242 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8245 *mask_ptr
|= 1 << regs
[i
];
8249 /* Return a simplified form of X using the register values in REG_VALUES.
8250 REG_VALUES[R] is the last value assigned to hard register R, or null
8251 if R has not been modified.
8253 This function is rather limited, but is good enough for our purposes. */
8256 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8258 x
= avoid_constant_pool_reference (x
);
8262 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8263 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
8264 x0
, GET_MODE (XEXP (x
, 0)));
8267 if (ARITHMETIC_P (x
))
8269 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8270 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
8271 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
8275 && reg_values
[REGNO (x
)]
8276 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
8277 return reg_values
[REGNO (x
)];
8282 /* Return true if (set DEST SRC) stores an argument register into its
8283 caller-allocated save slot, storing the number of that argument
8284 register in *REGNO_PTR if so. REG_VALUES is as for
8285 mips16e_collect_propagate_value. */
8288 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
8289 unsigned int *regno_ptr
)
8291 unsigned int argno
, regno
;
8292 HOST_WIDE_INT offset
, required_offset
;
8295 /* Check that this is a word-mode store. */
8296 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
8299 /* Check that the register being saved is an unmodified argument
8301 regno
= REGNO (src
);
8302 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
8304 argno
= regno
- GP_ARG_FIRST
;
8306 /* Check whether the address is an appropriate stack-pointer or
8307 frame-pointer access. */
8308 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
8309 mips_split_plus (addr
, &base
, &offset
);
8310 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
8311 if (base
== hard_frame_pointer_rtx
)
8312 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8313 else if (base
!= stack_pointer_rtx
)
8315 if (offset
!= required_offset
)
8322 /* A subroutine of mips_expand_prologue, called only when generating
8323 MIPS16e SAVE instructions. Search the start of the function for any
8324 instructions that save argument registers into their caller-allocated
8325 save slots. Delete such instructions and return a value N such that
8326 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8327 instructions redundant. */
8330 mips16e_collect_argument_saves (void)
8332 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
8333 rtx insn
, next
, set
, dest
, src
;
8334 unsigned int nargs
, regno
;
8336 push_topmost_sequence ();
8338 memset (reg_values
, 0, sizeof (reg_values
));
8339 for (insn
= get_insns (); insn
; insn
= next
)
8341 next
= NEXT_INSN (insn
);
8342 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
8348 set
= PATTERN (insn
);
8349 if (GET_CODE (set
) != SET
)
8352 dest
= SET_DEST (set
);
8353 src
= SET_SRC (set
);
8354 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
8356 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
8359 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
8362 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
8363 reg_values
[REGNO (dest
)]
8364 = mips16e_collect_propagate_value (src
, reg_values
);
8368 pop_topmost_sequence ();
8373 /* Return a move between register REGNO and memory location SP + OFFSET.
8374 Make the move a load if RESTORE_P, otherwise make it a frame-related
8378 mips16e_save_restore_reg (bool restore_p
, HOST_WIDE_INT offset
,
8383 mem
= gen_frame_mem (SImode
, plus_constant (stack_pointer_rtx
, offset
));
8384 reg
= gen_rtx_REG (SImode
, regno
);
8386 ? gen_rtx_SET (VOIDmode
, reg
, mem
)
8387 : mips_frame_set (mem
, reg
));
8390 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8391 The instruction must:
8393 - Allocate or deallocate SIZE bytes in total; SIZE is known
8396 - Save or restore as many registers in *MASK_PTR as possible.
8397 The instruction saves the first registers at the top of the
8398 allocated area, with the other registers below it.
8400 - Save NARGS argument registers above the allocated area.
8402 (NARGS is always zero if RESTORE_P.)
8404 The SAVE and RESTORE instructions cannot save and restore all general
8405 registers, so there may be some registers left over for the caller to
8406 handle. Destructively modify *MASK_PTR so that it contains the registers
8407 that still need to be saved or restored. The caller can save these
8408 registers in the memory immediately below *OFFSET_PTR, which is a
8409 byte offset from the bottom of the allocated stack area. */
8412 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
8413 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
8417 HOST_WIDE_INT offset
, top_offset
;
8418 unsigned int i
, regno
;
8421 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
8423 /* Calculate the number of elements in the PARALLEL. We need one element
8424 for the stack adjustment, one for each argument register save, and one
8425 for each additional register move. */
8427 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8428 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
8431 /* Create the final PARALLEL. */
8432 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
8435 /* Add the stack pointer adjustment. */
8436 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8437 plus_constant (stack_pointer_rtx
,
8438 restore_p
? size
: -size
));
8439 RTX_FRAME_RELATED_P (set
) = 1;
8440 XVECEXP (pattern
, 0, n
++) = set
;
8442 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8443 top_offset
= restore_p
? size
: 0;
8445 /* Save the arguments. */
8446 for (i
= 0; i
< nargs
; i
++)
8448 offset
= top_offset
+ i
* UNITS_PER_WORD
;
8449 set
= mips16e_save_restore_reg (restore_p
, offset
, GP_ARG_FIRST
+ i
);
8450 XVECEXP (pattern
, 0, n
++) = set
;
8453 /* Then fill in the other register moves. */
8454 offset
= top_offset
;
8455 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8457 regno
= mips16e_save_restore_regs
[i
];
8458 if (BITSET_P (*mask_ptr
, regno
))
8460 offset
-= UNITS_PER_WORD
;
8461 set
= mips16e_save_restore_reg (restore_p
, offset
, regno
);
8462 XVECEXP (pattern
, 0, n
++) = set
;
8463 *mask_ptr
&= ~(1 << regno
);
8467 /* Tell the caller what offset it should use for the remaining registers. */
8468 *offset_ptr
= size
+ (offset
- top_offset
);
8470 gcc_assert (n
== XVECLEN (pattern
, 0));
8475 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8476 pointer. Return true if PATTERN matches the kind of instruction
8477 generated by mips16e_build_save_restore. If INFO is nonnull,
8478 initialize it when returning true. */
8481 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
8482 struct mips16e_save_restore_info
*info
)
8484 unsigned int i
, nargs
, mask
, extra
;
8485 HOST_WIDE_INT top_offset
, save_offset
, offset
;
8486 rtx set
, reg
, mem
, base
;
8489 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
8492 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8493 top_offset
= adjust
> 0 ? adjust
: 0;
8495 /* Interpret all other members of the PARALLEL. */
8496 save_offset
= top_offset
- UNITS_PER_WORD
;
8500 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
8502 /* Check that we have a SET. */
8503 set
= XVECEXP (pattern
, 0, n
);
8504 if (GET_CODE (set
) != SET
)
8507 /* Check that the SET is a load (if restoring) or a store
8509 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
8513 /* Check that the address is the sum of the stack pointer and a
8514 possibly-zero constant offset. */
8515 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
8516 if (base
!= stack_pointer_rtx
)
8519 /* Check that SET's other operand is a register. */
8520 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
8524 /* Check for argument saves. */
8525 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
8526 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
8528 else if (offset
== save_offset
)
8530 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
8531 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
8534 mask
|= 1 << REGNO (reg
);
8535 save_offset
-= UNITS_PER_WORD
;
8541 /* Check that the restrictions on register ranges are met. */
8543 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
8544 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
8545 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
8546 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
8550 /* Make sure that the topmost argument register is not saved twice.
8551 The checks above ensure that the same is then true for the other
8552 argument registers. */
8553 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
8556 /* Pass back information, if requested. */
8559 info
->nargs
= nargs
;
8561 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
8567 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8568 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8569 the null terminator. */
8572 mips16e_add_register_range (char *s
, unsigned int min_reg
,
8573 unsigned int max_reg
)
8575 if (min_reg
!= max_reg
)
8576 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
8578 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
8582 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8583 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8586 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
8588 static char buffer
[300];
8590 struct mips16e_save_restore_info info
;
8591 unsigned int i
, end
;
8594 /* Parse the pattern. */
8595 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
8598 /* Add the mnemonic. */
8599 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
8602 /* Save the arguments. */
8604 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
8605 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
8606 else if (info
.nargs
== 1)
8607 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
8609 /* Emit the amount of stack space to allocate or deallocate. */
8610 s
+= sprintf (s
, "%d", (int) info
.size
);
8612 /* Save or restore $16. */
8613 if (BITSET_P (info
.mask
, 16))
8614 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
8616 /* Save or restore $17. */
8617 if (BITSET_P (info
.mask
, 17))
8618 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
8620 /* Save or restore registers in the range $s2...$s8, which
8621 mips16e_s2_s8_regs lists in decreasing order. Note that this
8622 is a software register range; the hardware registers are not
8623 numbered consecutively. */
8624 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
8625 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
8627 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
8628 mips16e_s2_s8_regs
[i
]);
8630 /* Save or restore registers in the range $a0...$a3. */
8631 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
8632 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
8634 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
8635 mips16e_a0_a3_regs
[end
- 1]);
8637 /* Save or restore $31. */
8638 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
8639 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
8644 /* Return true if the current function returns its value in a floating-point
8645 register in MIPS16 mode. */
8648 mips16_cfun_returns_in_fpr_p (void)
8650 tree return_type
= DECL_RESULT (current_function_decl
);
8651 return (TARGET_MIPS16
8652 && TARGET_HARD_FLOAT_ABI
8653 && !aggregate_value_p (return_type
, current_function_decl
)
8654 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
8657 /* Return true if predicate PRED is true for at least one instruction.
8658 Cache the result in *CACHE, and assume that the result is true
8659 if *CACHE is already true. */
8662 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
8668 push_topmost_sequence ();
8669 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8670 if (USEFUL_INSN_P (insn
) && pred (insn
))
8675 pop_topmost_sequence ();
8680 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8681 See mips_cfun_has_inflexible_gp_ref_p for details. */
8684 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
8686 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8687 indicate that the target could be a traditional MIPS
8688 lazily-binding stub. */
8689 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
8692 /* Return true if the current function refers to the global pointer
8693 in a way that forces $28 to be valid. This means that we can't
8694 change the choice of global pointer, even for NewABI code.
8696 One example of this (and one which needs several checks) is that
8697 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8698 (This restriction does not apply to PLTs.) */
8701 mips_cfun_has_inflexible_gp_ref_p (void)
8703 /* If the function has a nonlocal goto, $28 must hold the correct
8704 global pointer for the target function. That is, the target
8705 of the goto implicitly uses $28. */
8706 if (crtl
->has_nonlocal_goto
)
8709 if (TARGET_ABICALLS_PIC2
)
8711 /* Symbolic accesses implicitly use the global pointer unless
8712 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8713 might go to traditional MIPS lazy-binding stubs. */
8714 if (!TARGET_EXPLICIT_RELOCS
)
8717 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8718 can be lazily-bound. */
8722 /* MIPS16 functions that return in FPRs need to call an
8723 external libgcc routine. This call is only made explict
8724 during mips_expand_epilogue, and it too might be lazily bound. */
8725 if (mips16_cfun_returns_in_fpr_p ())
8729 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
8730 mips_insn_has_inflexible_gp_ref_p
);
8733 /* Return true if INSN refers to the global pointer in a "flexible" way.
8734 See mips_cfun_has_flexible_gp_ref_p for details. */
8737 mips_insn_has_flexible_gp_ref_p (rtx insn
)
8739 return (get_attr_got (insn
) != GOT_UNSET
8740 || mips_small_data_pattern_p (PATTERN (insn
))
8741 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
8744 /* Return true if the current function references the global pointer,
8745 but if those references do not inherently require the global pointer
8746 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8749 mips_cfun_has_flexible_gp_ref_p (void)
8751 /* Reload can sometimes introduce constant pool references
8752 into a function that otherwise didn't need them. For example,
8753 suppose we have an instruction like:
8755 (set (reg:DF R1) (float:DF (reg:SI R2)))
8757 If R2 turns out to be a constant such as 1, the instruction may
8758 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8759 the option of using this constant if R2 doesn't get allocated
8762 In cases like these, reload will have added the constant to the
8763 pool but no instruction will yet refer to it. */
8764 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
8767 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
8768 mips_insn_has_flexible_gp_ref_p
);
8771 /* Return the register that should be used as the global pointer
8772 within this function. Return INVALID_REGNUM if the function
8773 doesn't need a global pointer. */
8776 mips_global_pointer (void)
8780 /* $gp is always available unless we're using a GOT. */
8781 if (!TARGET_USE_GOT
)
8782 return GLOBAL_POINTER_REGNUM
;
8784 /* If there are inflexible references to $gp, we must use the
8785 standard register. */
8786 if (mips_cfun_has_inflexible_gp_ref_p ())
8787 return GLOBAL_POINTER_REGNUM
;
8789 /* If there are no current references to $gp, then the only uses
8790 we can introduce later are those involved in long branches. */
8791 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
8792 return INVALID_REGNUM
;
8794 /* If the global pointer is call-saved, try to use a call-clobbered
8796 if (TARGET_CALL_SAVED_GP
&& current_function_is_leaf
)
8797 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
8798 if (!df_regs_ever_live_p (regno
)
8799 && call_really_used_regs
[regno
]
8800 && !fixed_regs
[regno
]
8801 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
8804 return GLOBAL_POINTER_REGNUM
;
8807 /* Return true if the current function's prologue must load the global
8808 pointer value into pic_offset_table_rtx and store the same value in
8809 the function's cprestore slot (if any).
8811 One problem we have to deal with is that, when emitting GOT-based
8812 position independent code, long-branch sequences will need to load
8813 the address of the branch target from the GOT. We don't know until
8814 the very end of compilation whether (and where) the function needs
8815 long branches, so we must ensure that _any_ branch can access the
8816 global pointer in some form. However, we do not want to pessimize
8817 the usual case in which all branches are short.
8819 We handle this as follows:
8821 (1) During reload, we set cfun->machine->global_pointer to
8822 INVALID_REGNUM if we _know_ that the current function
8823 doesn't need a global pointer. This is only valid if
8824 long branches don't need the GOT.
8826 Otherwise, we assume that we might need a global pointer
8827 and pick an appropriate register.
8829 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8830 we ensure that the global pointer is available at every
8831 block boundary bar entry and exit. We do this in one of two ways:
8833 - If the function has a cprestore slot, we ensure that this
8834 slot is valid at every branch. However, as explained in
8835 point (6) below, there is no guarantee that pic_offset_table_rtx
8836 itself is valid if new uses of the global pointer are introduced
8837 after the first post-epilogue split.
8839 We guarantee that the cprestore slot is valid by loading it
8840 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8841 this register live at every block boundary bar function entry
8842 and exit. It is then invalid to move the load (and thus the
8843 preceding store) across a block boundary.
8845 - If the function has no cprestore slot, we guarantee that
8846 pic_offset_table_rtx itself is valid at every branch.
8848 See mips_eh_uses for the handling of the register liveness.
8850 (3) During prologue and epilogue generation, we emit "ghost"
8851 placeholder instructions to manipulate the global pointer.
8853 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8854 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8855 that the function needs a global pointer. (There is no need to set
8856 them earlier than this, and doing it as late as possible leads to
8857 fewer false positives.)
8859 (5) If cfun->machine->must_initialize_gp_p is true during a
8860 split_insns pass, we split the ghost instructions into real
8861 instructions. These split instructions can then be optimized in
8862 the usual way. Otherwise, we keep the ghost instructions intact,
8863 and optimize for the case where they aren't needed. We still
8864 have the option of splitting them later, if we need to introduce
8865 new uses of the global pointer.
8867 For example, the scheduler ignores a ghost instruction that
8868 stores $28 to the stack, but it handles the split form of
8869 the ghost instruction as an ordinary store.
8871 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8872 is true during the first post-epilogue split_insns pass, we split
8873 calls and restore_gp patterns into instructions that explicitly
8874 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8875 we split these patterns into instructions that _don't_ load from
8878 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8879 time of the split, then any instructions that exist at that time
8880 can make free use of pic_offset_table_rtx. However, if we want
8881 to introduce new uses of the global pointer after the split,
8882 we must explicitly load the value from the cprestore slot, since
8883 pic_offset_table_rtx itself might not be valid at a given point
8886 The idea is that we want to be able to delete redundant
8887 loads from the cprestore slot in the usual case where no
8888 long branches are needed.
8890 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8891 of md_reorg, we decide whether the global pointer is needed for
8892 long branches. If so, we set cfun->machine->must_initialize_gp_p
8893 to true and split the ghost instructions into real instructions
8896 Note that the ghost instructions must have a zero length for three reasons:
8898 - Giving the length of the underlying $gp sequence might cause
8899 us to use long branches in cases where they aren't really needed.
8901 - They would perturb things like alignment calculations.
8903 - More importantly, the hazard detection in md_reorg relies on
8904 empty instructions having a zero length.
8906 If we find a long branch and split the ghost instructions at the
8907 end of md_reorg, the split could introduce more long branches.
8908 That isn't a problem though, because we still do the split before
8909 the final shorten_branches pass.
8911 This is extremely ugly, but it seems like the best compromise between
8912 correctness and efficiency. */
8915 mips_must_initialize_gp_p (void)
8917 return cfun
->machine
->must_initialize_gp_p
;
8920 /* Return true if REGNO is a register that is ordinarily call-clobbered
8921 but must nevertheless be preserved by an interrupt handler. */
8924 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
8926 if (MD_REG_P (regno
))
8929 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
8932 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
8934 /* $0 is hard-wired. */
8935 if (regno
== GP_REG_FIRST
)
8938 /* The interrupt handler can treat kernel registers as
8939 scratch registers. */
8940 if (KERNEL_REG_P (regno
))
8943 /* The function will return the stack pointer to its original value
8945 if (regno
== STACK_POINTER_REGNUM
)
8948 /* Otherwise, return true for registers that aren't ordinarily
8950 return call_really_used_regs
[regno
];
8956 /* Return true if the current function should treat register REGNO
8960 mips_cfun_call_saved_reg_p (unsigned int regno
)
8962 /* If the user makes an ordinarily-call-saved register global,
8963 that register is no longer call-saved. */
8964 if (global_regs
[regno
])
8967 /* Interrupt handlers need to save extra registers. */
8968 if (cfun
->machine
->interrupt_handler_p
8969 && mips_interrupt_extra_call_saved_reg_p (regno
))
8972 /* call_insns preserve $28 unless they explicitly say otherwise,
8973 so call_really_used_regs[] treats $28 as call-saved. However,
8974 we want the ABI property rather than the default call_insn
8976 return (regno
== GLOBAL_POINTER_REGNUM
8977 ? TARGET_CALL_SAVED_GP
8978 : !call_really_used_regs
[regno
]);
8981 /* Return true if the function body might clobber register REGNO.
8982 We know that REGNO is call-saved. */
8985 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
8987 /* Some functions should be treated as clobbering all call-saved
8989 if (crtl
->saves_all_registers
)
8992 /* DF handles cases where a register is explicitly referenced in
8993 the rtl. Incoming values are passed in call-clobbered registers,
8994 so we can assume that any live call-saved register is set within
8996 if (df_regs_ever_live_p (regno
))
8999 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9000 These clobbers are not explicit in the rtl. */
9001 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9004 /* If we're using a call-saved global pointer, the function's
9005 prologue will need to set it up. */
9006 if (cfun
->machine
->global_pointer
== regno
)
9009 /* The function's prologue will need to set the frame pointer if
9010 frame_pointer_needed. */
9011 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9014 /* If a MIPS16 function returns a value in FPRs, its epilogue
9015 will need to call an external libgcc routine. This yet-to-be
9016 generated call_insn will clobber $31. */
9017 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9020 /* If REGNO is ordinarily call-clobbered, we must assume that any
9021 called function could modify it. */
9022 if (cfun
->machine
->interrupt_handler_p
9023 && !current_function_is_leaf
9024 && mips_interrupt_extra_call_saved_reg_p (regno
))
9030 /* Return true if the current function must save register REGNO. */
9033 mips_save_reg_p (unsigned int regno
)
9035 if (mips_cfun_call_saved_reg_p (regno
))
9037 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9040 /* Save both registers in an FPR pair if either one is used. This is
9041 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9042 register to be used without the even register. */
9043 if (FP_REG_P (regno
)
9044 && MAX_FPRS_PER_FMT
== 2
9045 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9049 /* We need to save the incoming return address if __builtin_eh_return
9050 is being used to set a different return address. */
9051 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9057 /* Populate the current function's mips_frame_info structure.
9059 MIPS stack frames look like:
9061 +-------------------------------+
9063 | incoming stack arguments |
9065 +-------------------------------+
9067 | caller-allocated save area |
9068 A | for register arguments |
9070 +-------------------------------+ <-- incoming stack pointer
9072 | callee-allocated save area |
9073 B | for arguments that are |
9074 | split between registers and |
9077 +-------------------------------+ <-- arg_pointer_rtx
9079 C | callee-allocated save area |
9080 | for register varargs |
9082 +-------------------------------+ <-- frame_pointer_rtx
9083 | | + cop0_sp_offset
9084 | COP0 reg save area | + UNITS_PER_WORD
9086 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9087 | | + UNITS_PER_WORD
9088 | accumulator save area |
9090 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9091 | | + UNITS_PER_HWFPVALUE
9094 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9095 | | + UNITS_PER_WORD
9098 +-------------------------------+ <-- frame_pointer_rtx with
9099 | | \ -fstack-protector
9100 | local variables | | var_size
9102 +-------------------------------+
9104 | $gp save area | | cprestore_size
9106 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9108 | outgoing stack arguments | |
9110 +-------------------------------+ | args_size
9112 | caller-allocated save area | |
9113 | for register arguments | |
9115 +-------------------------------+ <-- stack_pointer_rtx
9116 frame_pointer_rtx without
9118 hard_frame_pointer_rtx for
9121 At least two of A, B and C will be empty.
9123 Dynamic stack allocations such as alloca insert data at point P.
9124 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9125 hard_frame_pointer_rtx unchanged. */
9128 mips_compute_frame_info (void)
9130 struct mips_frame_info
*frame
;
9131 HOST_WIDE_INT offset
, size
;
9132 unsigned int regno
, i
;
9134 /* Set this function's interrupt properties. */
9135 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9138 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9139 else if (TARGET_HARD_FLOAT
)
9140 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9141 else if (TARGET_MIPS16
)
9142 error ("interrupt handlers cannot be MIPS16 functions");
9145 cfun
->machine
->interrupt_handler_p
= true;
9146 cfun
->machine
->use_shadow_register_set_p
=
9147 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9148 cfun
->machine
->keep_interrupts_masked_p
=
9149 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9150 cfun
->machine
->use_debug_exception_return_p
=
9151 mips_use_debug_exception_return_p (TREE_TYPE
9152 (current_function_decl
));
9156 frame
= &cfun
->machine
->frame
;
9157 memset (frame
, 0, sizeof (*frame
));
9158 size
= get_frame_size ();
9160 cfun
->machine
->global_pointer
= mips_global_pointer ();
9162 /* The first two blocks contain the outgoing argument area and the $gp save
9163 slot. This area isn't needed in leaf functions, but if the
9164 target-independent frame size is nonzero, we have already committed to
9165 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9166 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && current_function_is_leaf
)
9168 /* The MIPS 3.0 linker does not like functions that dynamically
9169 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9170 looks like we are trying to create a second frame pointer to the
9171 function, so allocate some stack space to make it happy. */
9172 if (cfun
->calls_alloca
)
9173 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9175 frame
->args_size
= 0;
9176 frame
->cprestore_size
= 0;
9180 frame
->args_size
= crtl
->outgoing_args_size
;
9181 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9183 offset
= frame
->args_size
+ frame
->cprestore_size
;
9185 /* Move above the local variables. */
9186 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9187 offset
+= frame
->var_size
;
9189 /* Find out which GPRs we need to save. */
9190 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9191 if (mips_save_reg_p (regno
))
9194 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9197 /* If this function calls eh_return, we must also save and restore the
9198 EH data registers. */
9199 if (crtl
->calls_eh_return
)
9200 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9203 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9206 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9207 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9208 save all later registers too. */
9209 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9211 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9212 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9213 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9214 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9217 /* Move above the GPR save area. */
9218 if (frame
->num_gp
> 0)
9220 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9221 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9224 /* Find out which FPRs we need to save. This loop must iterate over
9225 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9226 if (TARGET_HARD_FLOAT
)
9227 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9228 if (mips_save_reg_p (regno
))
9230 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9231 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9234 /* Move above the FPR save area. */
9235 if (frame
->num_fp
> 0)
9237 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9238 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9241 /* Add in space for the interrupt context information. */
9242 if (cfun
->machine
->interrupt_handler_p
)
9245 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9248 frame
->acc_mask
|= (1 << 0);
9251 /* Check accumulators 1, 2, 3. */
9252 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
9253 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
9256 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
9259 /* All interrupt context functions need space to preserve STATUS. */
9260 frame
->num_cop0_regs
++;
9262 /* If we don't keep interrupts masked, we need to save EPC. */
9263 if (!cfun
->machine
->keep_interrupts_masked_p
)
9264 frame
->num_cop0_regs
++;
9267 /* Move above the accumulator save area. */
9268 if (frame
->num_acc
> 0)
9270 /* Each accumulator needs 2 words. */
9271 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
9272 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
9275 /* Move above the COP0 register save area. */
9276 if (frame
->num_cop0_regs
> 0)
9278 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
9279 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
9282 /* Move above the callee-allocated varargs save area. */
9283 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
9284 frame
->arg_pointer_offset
= offset
;
9286 /* Move above the callee-allocated area for pretend stack arguments. */
9287 offset
+= crtl
->args
.pretend_args_size
;
9288 frame
->total_size
= offset
;
9290 /* Work out the offsets of the save areas from the top of the frame. */
9291 if (frame
->gp_sp_offset
> 0)
9292 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
9293 if (frame
->fp_sp_offset
> 0)
9294 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
9295 if (frame
->acc_sp_offset
> 0)
9296 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
9297 if (frame
->num_cop0_regs
> 0)
9298 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
9300 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9301 arguments. This tends to increase the chances of using unextended
9302 instructions for local variables and incoming arguments. */
9304 frame
->hard_frame_pointer_offset
= frame
->args_size
;
9307 /* Return the style of GP load sequence that is being used for the
9308 current function. */
9310 enum mips_loadgp_style
9311 mips_current_loadgp_style (void)
9313 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
9319 if (TARGET_ABSOLUTE_ABICALLS
)
9320 return LOADGP_ABSOLUTE
;
9322 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
9325 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9328 mips_frame_pointer_required (void)
9330 /* If the function contains dynamic stack allocations, we need to
9331 use the frame pointer to access the static parts of the frame. */
9332 if (cfun
->calls_alloca
)
9335 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9336 reload may be unable to compute the address of a local variable,
9337 since there is no way to add a large constant to the stack pointer
9338 without using a second temporary register. */
9341 mips_compute_frame_info ();
9342 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
9349 /* Make sure that we're not trying to eliminate to the wrong hard frame
9353 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
9355 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
9358 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9359 or argument pointer. TO is either the stack pointer or hard frame
9363 mips_initial_elimination_offset (int from
, int to
)
9365 HOST_WIDE_INT offset
;
9367 mips_compute_frame_info ();
9369 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9372 case FRAME_POINTER_REGNUM
:
9373 if (FRAME_GROWS_DOWNWARD
)
9374 offset
= (cfun
->machine
->frame
.args_size
9375 + cfun
->machine
->frame
.cprestore_size
9376 + cfun
->machine
->frame
.var_size
);
9381 case ARG_POINTER_REGNUM
:
9382 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
9389 if (to
== HARD_FRAME_POINTER_REGNUM
)
9390 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9395 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9398 mips_extra_live_on_entry (bitmap regs
)
9402 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9403 the global pointer. */
9404 if (!TARGET_ABSOLUTE_ABICALLS
)
9405 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
9407 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9408 the global pointer. */
9410 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
9412 /* See the comment above load_call<mode> for details. */
9413 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
9417 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9421 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
9426 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
9429 /* Emit code to change the current function's return address to
9430 ADDRESS. SCRATCH is available as a scratch register, if needed.
9431 ADDRESS and SCRATCH are both word-mode GPRs. */
9434 mips_set_return_address (rtx address
, rtx scratch
)
9438 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
9439 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
9440 cfun
->machine
->frame
.gp_sp_offset
);
9441 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
9444 /* Return true if the current function has a cprestore slot. */
9447 mips_cfun_has_cprestore_slot_p (void)
9449 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
9450 && cfun
->machine
->frame
.cprestore_size
> 0);
9453 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9454 cprestore slot. LOAD_P is true if the caller wants to load from
9455 the cprestore slot; it is false if the caller wants to store to
9459 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
9462 const struct mips_frame_info
*frame
;
9464 frame
= &cfun
->machine
->frame
;
9465 /* .cprestore always uses the stack pointer instead of the frame pointer.
9466 We have a free choice for direct stores for non-MIPS16 functions,
9467 and for MIPS16 functions whose cprestore slot is in range of the
9468 stack pointer. Using the stack pointer would sometimes give more
9469 (early) scheduling freedom, but using the frame pointer would
9470 sometimes give more (late) scheduling freedom. It's hard to
9471 predict which applies to a given function, so let's keep things
9474 Loads must always use the frame pointer in functions that call
9475 alloca, and there's little benefit to using the stack pointer
9477 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
9479 *base
= hard_frame_pointer_rtx
;
9480 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
9484 *base
= stack_pointer_rtx
;
9485 *offset
= frame
->args_size
;
9489 /* Return true if X is the load or store address of the cprestore slot;
9490 LOAD_P says which. */
9493 mips_cprestore_address_p (rtx x
, bool load_p
)
9495 rtx given_base
, required_base
;
9496 HOST_WIDE_INT given_offset
, required_offset
;
9498 mips_split_plus (x
, &given_base
, &given_offset
);
9499 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
9500 return given_base
== required_base
&& given_offset
== required_offset
;
9503 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9504 going to load from it, false if we are going to store to it.
9505 Use TEMP as a temporary register if need be. */
9508 mips_cprestore_slot (rtx temp
, bool load_p
)
9511 HOST_WIDE_INT offset
;
9513 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
9514 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
9517 /* Emit instructions to save global pointer value GP into cprestore
9518 slot MEM. OFFSET is the offset that MEM applies to the base register.
9520 MEM may not be a legitimate address. If it isn't, TEMP is a
9521 temporary register that can be used, otherwise it is a SCRATCH. */
9524 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
9526 if (TARGET_CPRESTORE_DIRECTIVE
)
9528 gcc_assert (gp
== pic_offset_table_rtx
);
9529 emit_insn (gen_cprestore (mem
, offset
));
9532 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
9535 /* Restore $gp from its save slot, using TEMP as a temporary base register
9536 if need be. This function is for o32 and o64 abicalls only.
9538 See mips_must_initialize_gp_p for details about how we manage the
9542 mips_restore_gp_from_cprestore_slot (rtx temp
)
9544 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
9546 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
9548 emit_note (NOTE_INSN_DELETED
);
9554 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
9555 mips_emit_move (pic_offset_table_rtx
, temp
);
9558 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
9559 if (!TARGET_EXPLICIT_RELOCS
)
9560 emit_insn (gen_blockage ());
9563 /* A function to save or store a register. The first argument is the
9564 register and the second is the stack slot. */
9565 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
9567 /* Use FN to save or restore register REGNO. MODE is the register's
9568 mode and OFFSET is the offset of its save slot from the current
9572 mips_save_restore_reg (enum machine_mode mode
, int regno
,
9573 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
9577 mem
= gen_frame_mem (mode
, plus_constant (stack_pointer_rtx
, offset
));
9578 fn (gen_rtx_REG (mode
, regno
), mem
);
9581 /* Call FN for each accumlator that is saved by the current function.
9582 SP_OFFSET is the offset of the current stack pointer from the start
9586 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
9588 HOST_WIDE_INT offset
;
9591 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
9592 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
9594 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
9595 offset
-= UNITS_PER_WORD
;
9596 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
9597 offset
-= UNITS_PER_WORD
;
9600 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
9601 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
9602 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
9604 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
9605 offset
-= UNITS_PER_WORD
;
9609 /* Call FN for each register that is saved by the current function.
9610 SP_OFFSET is the offset of the current stack pointer from the start
9614 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
9615 mips_save_restore_fn fn
)
9617 enum machine_mode fpr_mode
;
9618 HOST_WIDE_INT offset
;
9621 /* Save registers starting from high to low. The debuggers prefer at least
9622 the return register be stored at func+4, and also it allows us not to
9623 need a nop in the epilogue if at least one register is reloaded in
9624 addition to return address. */
9625 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
9626 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
9627 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
9629 /* Record the ra offset for use by mips_function_profiler. */
9630 if (regno
== RETURN_ADDR_REGNUM
)
9631 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
9632 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
9633 offset
-= UNITS_PER_WORD
;
9636 /* This loop must iterate over the same space as its companion in
9637 mips_compute_frame_info. */
9638 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
9639 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
9640 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
9641 regno
>= FP_REG_FIRST
;
9642 regno
-= MAX_FPRS_PER_FMT
)
9643 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
9645 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
9646 offset
-= GET_MODE_SIZE (fpr_mode
);
9650 /* Return true if a move between register REGNO and its save slot (MEM)
9651 can be done in a single move. LOAD_P is true if we are loading
9652 from the slot, false if we are storing to it. */
9655 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
9657 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9658 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
9661 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
9662 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
9665 /* Emit a move from SRC to DEST, given that one of them is a register
9666 save slot and that the other is a register. TEMP is a temporary
9667 GPR of the same mode that is available if need be. */
9670 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
9677 regno
= REGNO (src
);
9682 regno
= REGNO (dest
);
9686 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
9688 /* We don't yet know whether we'll need this instruction or not.
9689 Postpone the decision by emitting a ghost move. This move
9690 is specifically not frame-related; only the split version is. */
9692 emit_insn (gen_move_gpdi (dest
, src
));
9694 emit_insn (gen_move_gpsi (dest
, src
));
9698 if (regno
== HI_REGNUM
)
9702 mips_emit_move (temp
, src
);
9704 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
9705 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
9707 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
9708 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
9713 emit_insn (gen_mfhidi_ti (temp
,
9714 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
9716 emit_insn (gen_mfhisi_di (temp
,
9717 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
9718 mips_emit_move (dest
, temp
);
9721 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
9722 mips_emit_move (dest
, src
);
9725 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
9726 mips_emit_move (temp
, src
);
9727 mips_emit_move (dest
, temp
);
9730 mips_set_frame_expr (mips_frame_set (dest
, src
));
9733 /* If we're generating n32 or n64 abicalls, and the current function
9734 does not use $28 as its global pointer, emit a cplocal directive.
9735 Use pic_offset_table_rtx as the argument to the directive. */
9738 mips_output_cplocal (void)
9740 if (!TARGET_EXPLICIT_RELOCS
9741 && mips_must_initialize_gp_p ()
9742 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
9743 output_asm_insn (".cplocal %+", 0);
9746 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9749 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
9753 #ifdef SDB_DEBUGGING_INFO
9754 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
9755 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
9758 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9759 floating-point arguments. */
9761 && TARGET_HARD_FLOAT_ABI
9762 && crtl
->args
.info
.fp_code
!= 0)
9763 mips16_build_function_stub ();
9765 /* Get the function name the same way that toplev.c does before calling
9766 assemble_start_function. This is needed so that the name used here
9767 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9768 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9769 mips_start_function_definition (fnname
, TARGET_MIPS16
);
9771 /* Output MIPS-specific frame information. */
9772 if (!flag_inhibit_size_directive
)
9774 const struct mips_frame_info
*frame
;
9776 frame
= &cfun
->machine
->frame
;
9778 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9780 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
9781 "# vars= " HOST_WIDE_INT_PRINT_DEC
9783 ", args= " HOST_WIDE_INT_PRINT_DEC
9784 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
9785 reg_names
[frame_pointer_needed
9786 ? HARD_FRAME_POINTER_REGNUM
9787 : STACK_POINTER_REGNUM
],
9788 (frame_pointer_needed
9789 ? frame
->total_size
- frame
->hard_frame_pointer_offset
9790 : frame
->total_size
),
9791 reg_names
[RETURN_ADDR_REGNUM
],
9793 frame
->num_gp
, frame
->num_fp
,
9795 frame
->cprestore_size
);
9797 /* .mask MASK, OFFSET. */
9798 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
9799 frame
->mask
, frame
->gp_save_offset
);
9801 /* .fmask MASK, OFFSET. */
9802 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
9803 frame
->fmask
, frame
->fp_save_offset
);
9806 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9807 Also emit the ".set noreorder; .set nomacro" sequence for functions
9809 if (mips_must_initialize_gp_p ()
9810 && mips_current_loadgp_style () == LOADGP_OLDABI
)
9814 /* This is a fixed-form sequence. The position of the
9815 first two instructions is important because of the
9816 way _gp_disp is defined. */
9817 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9818 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9819 output_asm_insn ("sll\t$2,16", 0);
9820 output_asm_insn ("addu\t$2,$3", 0);
9824 /* .cpload must be in a .set noreorder but not a
9825 .set nomacro block. */
9826 mips_push_asm_switch (&mips_noreorder
);
9827 output_asm_insn (".cpload\t%^", 0);
9828 if (!cfun
->machine
->all_noreorder_p
)
9829 mips_pop_asm_switch (&mips_noreorder
);
9831 mips_push_asm_switch (&mips_nomacro
);
9834 else if (cfun
->machine
->all_noreorder_p
)
9836 mips_push_asm_switch (&mips_noreorder
);
9837 mips_push_asm_switch (&mips_nomacro
);
9840 /* Tell the assembler which register we're using as the global
9841 pointer. This is needed for thunks, since they can use either
9842 explicit relocs or assembler macros. */
9843 mips_output_cplocal ();
9846 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9849 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9850 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
9854 /* Reinstate the normal $gp. */
9855 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
9856 mips_output_cplocal ();
9858 if (cfun
->machine
->all_noreorder_p
)
9860 mips_pop_asm_switch (&mips_nomacro
);
9861 mips_pop_asm_switch (&mips_noreorder
);
9864 /* Get the function name the same way that toplev.c does before calling
9865 assemble_start_function. This is needed so that the name used here
9866 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9867 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9868 mips_end_function_definition (fnname
);
9871 /* Save register REG to MEM. Make the instruction frame-related. */
9874 mips_save_reg (rtx reg
, rtx mem
)
9876 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
9880 if (mips_split_64bit_move_p (mem
, reg
))
9881 mips_split_doubleword_move (mem
, reg
);
9883 mips_emit_move (mem
, reg
);
9885 x1
= mips_frame_set (mips_subword (mem
, false),
9886 mips_subword (reg
, false));
9887 x2
= mips_frame_set (mips_subword (mem
, true),
9888 mips_subword (reg
, true));
9889 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
9892 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
9895 /* The __gnu_local_gp symbol. */
9897 static GTY(()) rtx mips_gnu_local_gp
;
9899 /* If we're generating n32 or n64 abicalls, emit instructions
9900 to set up the global pointer. */
9903 mips_emit_loadgp (void)
9905 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
9907 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
9908 switch (mips_current_loadgp_style ())
9910 case LOADGP_ABSOLUTE
:
9911 if (mips_gnu_local_gp
== NULL
)
9913 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
9914 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
9916 emit_insn (Pmode
== SImode
9917 ? gen_loadgp_absolute_si (pic_reg
, mips_gnu_local_gp
)
9918 : gen_loadgp_absolute_di (pic_reg
, mips_gnu_local_gp
));
9922 /* Added by mips_output_function_prologue. */
9926 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
9927 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
9928 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
9929 emit_insn (Pmode
== SImode
9930 ? gen_loadgp_newabi_si (pic_reg
, offset
, incoming_address
)
9931 : gen_loadgp_newabi_di (pic_reg
, offset
, incoming_address
));
9935 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
9936 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
9937 emit_insn (Pmode
== SImode
9938 ? gen_loadgp_rtp_si (pic_reg
, base
, index
)
9939 : gen_loadgp_rtp_di (pic_reg
, base
, index
));
9947 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx
, pic_reg
));
9949 /* Emit a blockage if there are implicit uses of the GP register.
9950 This includes profiled functions, because FUNCTION_PROFILE uses
9952 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
9953 emit_insn (gen_loadgp_blockage ());
9956 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9959 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
9961 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
9964 /* Expand the "prologue" pattern. */
9967 mips_expand_prologue (void)
9969 const struct mips_frame_info
*frame
;
9974 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
9976 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
9977 or implicitly. If so, we can commit to using a global pointer
9978 straight away, otherwise we need to defer the decision. */
9979 if (mips_cfun_has_inflexible_gp_ref_p ()
9980 || mips_cfun_has_flexible_gp_ref_p ())
9982 cfun
->machine
->must_initialize_gp_p
= true;
9983 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
9986 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
9989 frame
= &cfun
->machine
->frame
;
9990 size
= frame
->total_size
;
9992 if (flag_stack_usage_info
)
9993 current_function_static_stack_size
= size
;
9995 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9996 bytes beforehand; this is enough to cover the register save area
9997 without going out of range. */
9998 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
9999 || frame
->num_cop0_regs
> 0)
10001 HOST_WIDE_INT step1
;
10003 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10004 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10006 HOST_WIDE_INT offset
;
10007 unsigned int mask
, regno
;
10009 /* Try to merge argument stores into the save instruction. */
10010 nargs
= mips16e_collect_argument_saves ();
10012 /* Build the save instruction. */
10013 mask
= frame
->mask
;
10014 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
10016 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10019 /* Check if we need to save other registers. */
10020 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10021 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10023 offset
-= UNITS_PER_WORD
;
10024 mips_save_restore_reg (word_mode
, regno
,
10025 offset
, mips_save_reg
);
10030 if (cfun
->machine
->interrupt_handler_p
)
10032 HOST_WIDE_INT offset
;
10035 /* If this interrupt is using a shadow register set, we need to
10036 get the stack pointer from the previous register set. */
10037 if (cfun
->machine
->use_shadow_register_set_p
)
10038 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
10039 stack_pointer_rtx
));
10041 if (!cfun
->machine
->keep_interrupts_masked_p
)
10043 /* Move from COP0 Cause to K0. */
10044 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
10045 gen_rtx_REG (SImode
,
10046 COP0_CAUSE_REG_NUM
)));
10047 /* Move from COP0 EPC to K1. */
10048 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10049 gen_rtx_REG (SImode
,
10050 COP0_EPC_REG_NUM
)));
10053 /* Allocate the first part of the frame. */
10054 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
10056 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10059 /* Start at the uppermost location for saving. */
10060 offset
= frame
->cop0_sp_offset
- size
;
10061 if (!cfun
->machine
->keep_interrupts_masked_p
)
10063 /* Push EPC into its stack slot. */
10064 mem
= gen_frame_mem (word_mode
,
10065 plus_constant (stack_pointer_rtx
,
10067 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10068 offset
-= UNITS_PER_WORD
;
10071 /* Move from COP0 Status to K1. */
10072 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10073 gen_rtx_REG (SImode
,
10074 COP0_STATUS_REG_NUM
)));
10076 /* Right justify the RIPL in k0. */
10077 if (!cfun
->machine
->keep_interrupts_masked_p
)
10078 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
10079 gen_rtx_REG (SImode
, K0_REG_NUM
),
10080 GEN_INT (CAUSE_IPL
)));
10082 /* Push Status into its stack slot. */
10083 mem
= gen_frame_mem (word_mode
,
10084 plus_constant (stack_pointer_rtx
, offset
));
10085 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10086 offset
-= UNITS_PER_WORD
;
10088 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10089 if (!cfun
->machine
->keep_interrupts_masked_p
)
10090 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10093 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10095 if (!cfun
->machine
->keep_interrupts_masked_p
)
10096 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10097 IE is already the correct value, so we don't have to do
10098 anything explicit. */
10099 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10102 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10104 /* Disable interrupts by clearing the KSU, ERL, EXL,
10106 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10109 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10113 insn
= gen_add3_insn (stack_pointer_rtx
,
10116 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10119 mips_for_each_saved_acc (size
, mips_save_reg
);
10120 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
10124 /* Allocate the rest of the frame. */
10127 if (SMALL_OPERAND (-size
))
10128 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
10130 GEN_INT (-size
)))) = 1;
10133 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
10136 /* There are no instructions to add or subtract registers
10137 from the stack pointer, so use the frame pointer as a
10138 temporary. We should always be using a frame pointer
10139 in this case anyway. */
10140 gcc_assert (frame_pointer_needed
);
10141 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10142 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
10143 hard_frame_pointer_rtx
,
10144 MIPS_PROLOGUE_TEMP (Pmode
)));
10145 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
10148 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
10150 MIPS_PROLOGUE_TEMP (Pmode
)));
10152 /* Describe the combined effect of the previous instructions. */
10153 mips_set_frame_expr
10154 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10155 plus_constant (stack_pointer_rtx
, -size
)));
10159 /* Set up the frame pointer, if we're using one. */
10160 if (frame_pointer_needed
)
10162 HOST_WIDE_INT offset
;
10164 offset
= frame
->hard_frame_pointer_offset
;
10167 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10168 RTX_FRAME_RELATED_P (insn
) = 1;
10170 else if (SMALL_OPERAND (offset
))
10172 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
10173 stack_pointer_rtx
, GEN_INT (offset
));
10174 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10178 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
10179 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10180 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
10181 hard_frame_pointer_rtx
,
10182 MIPS_PROLOGUE_TEMP (Pmode
)));
10183 mips_set_frame_expr
10184 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
10185 plus_constant (stack_pointer_rtx
, offset
)));
10189 mips_emit_loadgp ();
10191 /* Initialize the $gp save slot. */
10192 if (mips_cfun_has_cprestore_slot_p ())
10194 rtx base
, mem
, gp
, temp
;
10195 HOST_WIDE_INT offset
;
10197 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
10198 mem
= gen_frame_mem (Pmode
, plus_constant (base
, offset
));
10199 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10200 temp
= (SMALL_OPERAND (offset
)
10201 ? gen_rtx_SCRATCH (Pmode
)
10202 : MIPS_PROLOGUE_TEMP (Pmode
));
10203 emit_insn (gen_potential_cprestore (mem
, GEN_INT (offset
), gp
, temp
));
10205 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
10206 mem
= gen_frame_mem (Pmode
, plus_constant (base
, offset
));
10207 emit_insn (gen_use_cprestore (mem
));
10210 /* We need to search back to the last use of K0 or K1. */
10211 if (cfun
->machine
->interrupt_handler_p
)
10213 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
10215 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
10217 /* Emit a move from K1 to COP0 Status after insn. */
10218 gcc_assert (insn
!= NULL_RTX
);
10219 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10220 gen_rtx_REG (SImode
, K1_REG_NUM
)),
10224 /* If we are profiling, make sure no instructions are scheduled before
10225 the call to mcount. */
10227 emit_insn (gen_blockage ());
10230 /* Emit instructions to restore register REG from slot MEM. */
10233 mips_restore_reg (rtx reg
, rtx mem
)
10235 /* There's no MIPS16 instruction to load $31 directly. Load into
10236 $7 instead and adjust the return insn appropriately. */
10237 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
10238 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
10240 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
10243 /* Emit any instructions needed before a return. */
10246 mips_expand_before_return (void)
10248 /* When using a call-clobbered gp, we start out with unified call
10249 insns that include instructions to restore the gp. We then split
10250 these unified calls after reload. These split calls explicitly
10251 clobber gp, so there is no need to define
10252 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10254 For consistency, we should also insert an explicit clobber of $28
10255 before return insns, so that the post-reload optimizers know that
10256 the register is not live on exit. */
10257 if (TARGET_CALL_CLOBBERED_GP
)
10258 emit_clobber (pic_offset_table_rtx
);
10261 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10265 mips_expand_epilogue (bool sibcall_p
)
10267 const struct mips_frame_info
*frame
;
10268 HOST_WIDE_INT step1
, step2
;
10269 rtx base
, target
, insn
;
10271 if (!sibcall_p
&& mips_can_use_return_insn ())
10273 emit_jump_insn (gen_return ());
10277 /* In MIPS16 mode, if the return value should go into a floating-point
10278 register, we need to call a helper routine to copy it over. */
10279 if (mips16_cfun_returns_in_fpr_p ())
10280 mips16_copy_fpr_return_value ();
10282 /* Split the frame into two. STEP1 is the amount of stack we should
10283 deallocate before restoring the registers. STEP2 is the amount we
10284 should deallocate afterwards.
10286 Start off by assuming that no registers need to be restored. */
10287 frame
= &cfun
->machine
->frame
;
10288 step1
= frame
->total_size
;
10291 /* Work out which register holds the frame address. */
10292 if (!frame_pointer_needed
)
10293 base
= stack_pointer_rtx
;
10296 base
= hard_frame_pointer_rtx
;
10297 step1
-= frame
->hard_frame_pointer_offset
;
10300 /* If we need to restore registers, deallocate as much stack as
10301 possible in the second step without going out of range. */
10302 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
10303 || frame
->num_cop0_regs
> 0)
10305 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
10309 /* Set TARGET to BASE + STEP1. */
10315 /* Get an rtx for STEP1 that we can add to BASE. */
10316 adjust
= GEN_INT (step1
);
10317 if (!SMALL_OPERAND (step1
))
10319 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
10320 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
10323 /* Normal mode code can copy the result straight into $sp. */
10324 if (!TARGET_MIPS16
)
10325 target
= stack_pointer_rtx
;
10327 emit_insn (gen_add3_insn (target
, base
, adjust
));
10330 /* Copy TARGET into the stack pointer. */
10331 if (target
!= stack_pointer_rtx
)
10332 mips_emit_move (stack_pointer_rtx
, target
);
10334 /* If we're using addressing macros, $gp is implicitly used by all
10335 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10337 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
10338 emit_insn (gen_blockage ());
10340 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
10342 unsigned int regno
, mask
;
10343 HOST_WIDE_INT offset
;
10346 /* Generate the restore instruction. */
10347 mask
= frame
->mask
;
10348 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
10350 /* Restore any other registers manually. */
10351 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10352 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10354 offset
-= UNITS_PER_WORD
;
10355 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
10358 /* Restore the remaining registers and deallocate the final bit
10360 emit_insn (restore
);
10364 /* Restore the registers. */
10365 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
10366 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
10369 if (cfun
->machine
->interrupt_handler_p
)
10371 HOST_WIDE_INT offset
;
10374 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
10375 if (!cfun
->machine
->keep_interrupts_masked_p
)
10377 /* Restore the original EPC. */
10378 mem
= gen_frame_mem (word_mode
,
10379 plus_constant (stack_pointer_rtx
, offset
));
10380 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10381 offset
-= UNITS_PER_WORD
;
10383 /* Move to COP0 EPC. */
10384 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
10385 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10388 /* Restore the original Status. */
10389 mem
= gen_frame_mem (word_mode
,
10390 plus_constant (stack_pointer_rtx
, offset
));
10391 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10392 offset
-= UNITS_PER_WORD
;
10394 /* If we don't use shoadow register set, we need to update SP. */
10395 if (!cfun
->machine
->use_shadow_register_set_p
&& step2
> 0)
10396 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10400 /* Move to COP0 Status. */
10401 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10402 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10406 /* Deallocate the final bit of the frame. */
10408 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10414 /* Add in the __builtin_eh_return stack adjustment. We need to
10415 use a temporary in MIPS16 code. */
10416 if (crtl
->calls_eh_return
)
10420 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
10421 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
10422 MIPS_EPILOGUE_TEMP (Pmode
),
10423 EH_RETURN_STACKADJ_RTX
));
10424 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
10427 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10429 EH_RETURN_STACKADJ_RTX
));
10434 mips_expand_before_return ();
10435 if (cfun
->machine
->interrupt_handler_p
)
10437 /* Interrupt handlers generate eret or deret. */
10438 if (cfun
->machine
->use_debug_exception_return_p
)
10439 emit_jump_insn (gen_mips_deret ());
10441 emit_jump_insn (gen_mips_eret ());
10445 unsigned int regno
;
10447 /* When generating MIPS16 code, the normal
10448 mips_for_each_saved_gpr_and_fpr path will restore the return
10449 address into $7 rather than $31. */
10451 && !GENERATE_MIPS16E_SAVE_RESTORE
10452 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
10453 regno
= GP_REG_FIRST
+ 7;
10455 regno
= RETURN_ADDR_REGNUM
;
10456 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, regno
)));
10460 /* Search from the beginning to the first use of K0 or K1. */
10461 if (cfun
->machine
->interrupt_handler_p
10462 && !cfun
->machine
->keep_interrupts_masked_p
)
10464 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
10466 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
10468 gcc_assert (insn
!= NULL_RTX
);
10469 /* Insert disable interrupts before the first use of K0 or K1. */
10470 emit_insn_before (gen_mips_di (), insn
);
10471 emit_insn_before (gen_mips_ehb (), insn
);
10475 /* Return nonzero if this function is known to have a null epilogue.
10476 This allows the optimizer to omit jumps to jumps if no stack
10480 mips_can_use_return_insn (void)
10482 /* Interrupt handlers need to go through the epilogue. */
10483 if (cfun
->machine
->interrupt_handler_p
)
10486 if (!reload_completed
)
10492 /* In MIPS16 mode, a function that returns a floating-point value
10493 needs to arrange to copy the return value into the floating-point
10495 if (mips16_cfun_returns_in_fpr_p ())
10498 return cfun
->machine
->frame
.total_size
== 0;
10501 /* Return true if register REGNO can store a value of mode MODE.
10502 The result of this function is cached in mips_hard_regno_mode_ok. */
10505 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
10508 enum mode_class mclass
;
10510 if (mode
== CCV2mode
)
10511 return (ISA_HAS_8CC
10512 && ST_REG_P (regno
)
10513 && (regno
- ST_REG_FIRST
) % 2 == 0);
10515 if (mode
== CCV4mode
)
10516 return (ISA_HAS_8CC
10517 && ST_REG_P (regno
)
10518 && (regno
- ST_REG_FIRST
) % 4 == 0);
10520 if (mode
== CCmode
)
10523 return regno
== FPSW_REGNUM
;
10525 return (ST_REG_P (regno
)
10526 || GP_REG_P (regno
)
10527 || FP_REG_P (regno
));
10530 size
= GET_MODE_SIZE (mode
);
10531 mclass
= GET_MODE_CLASS (mode
);
10533 if (GP_REG_P (regno
))
10534 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
10536 if (FP_REG_P (regno
)
10537 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
10538 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
10540 /* Allow TFmode for CCmode reloads. */
10541 if (mode
== TFmode
&& ISA_HAS_8CC
)
10544 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10545 if (TARGET_LOONGSON_VECTORS
10546 && (mode
== V2SImode
10547 || mode
== V4HImode
10548 || mode
== V8QImode
10549 || mode
== DImode
))
10552 if (mclass
== MODE_FLOAT
10553 || mclass
== MODE_COMPLEX_FLOAT
10554 || mclass
== MODE_VECTOR_FLOAT
)
10555 return size
<= UNITS_PER_FPVALUE
;
10557 /* Allow integer modes that fit into a single register. We need
10558 to put integers into FPRs when using instructions like CVT
10559 and TRUNC. There's no point allowing sizes smaller than a word,
10560 because the FPU has no appropriate load/store instructions. */
10561 if (mclass
== MODE_INT
)
10562 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
10565 if (ACC_REG_P (regno
)
10566 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
10568 if (MD_REG_P (regno
))
10570 /* After a multiplication or division, clobbering HI makes
10571 the value of LO unpredictable, and vice versa. This means
10572 that, for all interesting cases, HI and LO are effectively
10575 We model this by requiring that any value that uses HI
10577 if (size
<= UNITS_PER_WORD
* 2)
10578 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
10582 /* DSP accumulators do not have the same restrictions as
10583 HI and LO, so we can treat them as normal doubleword
10585 if (size
<= UNITS_PER_WORD
)
10588 if (size
<= UNITS_PER_WORD
* 2
10589 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
10594 if (ALL_COP_REG_P (regno
))
10595 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
10597 if (regno
== GOT_VERSION_REGNUM
)
10598 return mode
== SImode
;
10603 /* Implement HARD_REGNO_NREGS. */
10606 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
10608 if (ST_REG_P (regno
))
10609 /* The size of FP status registers is always 4, because they only hold
10610 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10611 return (GET_MODE_SIZE (mode
) + 3) / 4;
10613 if (FP_REG_P (regno
))
10614 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
10616 /* All other registers are word-sized. */
10617 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
10620 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10621 in mips_hard_regno_nregs. */
10624 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
10630 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
10631 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
10633 size
= MIN (size
, 4);
10634 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
10636 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
10638 size
= MIN (size
, UNITS_PER_FPREG
);
10639 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
10641 if (!hard_reg_set_empty_p (left
))
10642 size
= MIN (size
, UNITS_PER_WORD
);
10643 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
10646 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10649 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED
,
10650 enum machine_mode to ATTRIBUTE_UNUSED
,
10651 enum reg_class rclass
)
10653 /* There are several problems with changing the modes of values in
10654 floating-point registers:
10656 - When a multi-word value is stored in paired floating-point
10657 registers, the first register always holds the low word. We
10658 therefore can't allow FPRs to change between single-word and
10659 multi-word modes on big-endian targets.
10661 - GCC assumes that each word of a multiword register can be
10662 accessed individually using SUBREGs. This is not true for
10663 floating-point registers if they are bigger than a word.
10665 - Loading a 32-bit value into a 64-bit floating-point register
10666 will not sign-extend the value, despite what LOAD_EXTEND_OP
10667 says. We can't allow FPRs to change from SImode to a wider
10668 mode on 64-bit targets.
10670 - If the FPU has already interpreted a value in one format, we
10671 must not ask it to treat the value as having a different
10674 We therefore disallow all mode changes involving FPRs. */
10675 return reg_classes_intersect_p (FP_REGS
, rclass
);
10678 /* Implement target hook small_register_classes_for_mode_p. */
10681 mips_small_register_classes_for_mode_p (enum machine_mode mode
10684 return TARGET_MIPS16
;
10687 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10690 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
10695 return TARGET_HARD_FLOAT
;
10698 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
10701 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
10708 /* Implement MODES_TIEABLE_P. */
10711 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
10713 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10714 prefer to put one of them in FPRs. */
10715 return (mode1
== mode2
10716 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
10717 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
10720 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
10723 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
10725 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
10728 if (reg_class_subset_p (FP_REGS
, rclass
)
10729 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
10732 if (reg_class_subset_p (GR_REGS
, rclass
))
10735 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
10741 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10742 Return a "canonical" class to represent it in later calculations. */
10745 mips_canonicalize_move_class (reg_class_t rclass
)
10747 /* All moves involving accumulator registers have the same cost. */
10748 if (reg_class_subset_p (rclass
, ACC_REGS
))
10751 /* Likewise promote subclasses of general registers to the most
10752 interesting containing class. */
10753 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
10755 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
10756 rclass
= GENERAL_REGS
;
10761 /* Return the cost of moving a value of mode MODE from a register of
10762 class FROM to a GPR. Return 0 for classes that are unions of other
10763 classes handled by this function. */
10766 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
10772 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10776 /* MFLO and MFHI. */
10784 /* LUI followed by MOVF. */
10790 /* This choice of value is historical. */
10798 /* Return the cost of moving a value of mode MODE from a GPR to a
10799 register of class TO. Return 0 for classes that are unions of
10800 other classes handled by this function. */
10803 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
10808 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10812 /* MTLO and MTHI. */
10820 /* A secondary reload through an FPR scratch. */
10821 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
10822 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
10827 /* This choice of value is historical. */
10835 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10836 maximum of the move costs for subclasses; regclass will work out
10837 the maximum for us. */
10840 mips_register_move_cost (enum machine_mode mode
,
10841 reg_class_t from
, reg_class_t to
)
10846 from
= mips_canonicalize_move_class (from
);
10847 to
= mips_canonicalize_move_class (to
);
10849 /* Handle moves that can be done without using general-purpose registers. */
10850 if (from
== FP_REGS
)
10852 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
10856 /* The sequence generated by mips_expand_fcc_reload. */
10860 /* Handle cases in which only one class deviates from the ideal. */
10861 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
10863 return mips_move_from_gpr_cost (mode
, to
);
10865 return mips_move_to_gpr_cost (mode
, from
);
10867 /* Handles cases that require a GPR temporary. */
10868 cost1
= mips_move_to_gpr_cost (mode
, from
);
10871 cost2
= mips_move_from_gpr_cost (mode
, to
);
10873 return cost1
+ cost2
;
10879 /* Implement TARGET_MEMORY_MOVE_COST. */
10882 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
10884 return (mips_cost
->memory_latency
10885 + memory_move_secondary_cost (mode
, rclass
, in
));
10888 /* Return the register class required for a secondary register when
10889 copying between one of the registers in RCLASS and value X, which
10890 has mode MODE. X is the source of the move if IN_P, otherwise it
10891 is the destination. Return NO_REGS if no secondary register is
10895 mips_secondary_reload_class (enum reg_class rclass
,
10896 enum machine_mode mode
, rtx x
, bool in_p
)
10900 /* If X is a constant that cannot be loaded into $25, it must be loaded
10901 into some other GPR. No other register class allows a direct move. */
10902 if (mips_dangerous_for_la25_p (x
))
10903 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
10905 regno
= true_regnum (x
);
10908 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10909 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
10915 /* Copying from accumulator registers to anywhere other than a general
10916 register requires a temporary general register. */
10917 if (reg_class_subset_p (rclass
, ACC_REGS
))
10918 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
10919 if (ACC_REG_P (regno
))
10920 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
10922 /* We can only copy a value to a condition code register from a
10923 floating-point register, and even then we require a scratch
10924 floating-point register. We can only copy a value out of a
10925 condition-code register into a general register. */
10926 if (reg_class_subset_p (rclass
, ST_REGS
))
10930 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
10932 if (ST_REG_P (regno
))
10936 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
10939 if (reg_class_subset_p (rclass
, FP_REGS
))
10942 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
10943 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10944 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10947 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
10948 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10951 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
10952 /* We can force the constant to memory and use lwc1
10953 and ldc1. As above, we will use pairs of lwc1s if
10954 ldc1 is not supported. */
10957 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
10958 /* In this case we can use mov.fmt. */
10961 /* Otherwise, we need to reload through an integer register. */
10964 if (FP_REG_P (regno
))
10965 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
10970 /* Implement TARGET_MODE_REP_EXTENDED. */
10973 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
10975 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
10976 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
10977 return SIGN_EXTEND
;
10982 /* Implement TARGET_VALID_POINTER_MODE. */
10985 mips_valid_pointer_mode (enum machine_mode mode
)
10987 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
10990 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10993 mips_vector_mode_supported_p (enum machine_mode mode
)
10998 return TARGET_PAIRED_SINGLE_FLOAT
;
11013 return TARGET_LOONGSON_VECTORS
;
11020 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11023 mips_scalar_mode_supported_p (enum machine_mode mode
)
11025 if (ALL_FIXED_POINT_MODE_P (mode
)
11026 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
11029 return default_scalar_mode_supported_p (mode
);
11032 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11034 static enum machine_mode
11035 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
11037 if (TARGET_PAIRED_SINGLE_FLOAT
11043 /* Implement TARGET_INIT_LIBFUNCS. */
11046 mips_init_libfuncs (void)
11048 if (TARGET_FIX_VR4120
)
11050 /* Register the special divsi3 and modsi3 functions needed to work
11051 around VR4120 division errata. */
11052 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
11053 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
11056 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
11058 /* Register the MIPS16 -mhard-float stubs. */
11059 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
11060 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
11061 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
11062 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
11064 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
11065 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
11066 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
11067 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
11068 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
11069 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
11070 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
11072 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
11073 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
11074 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
11076 if (TARGET_DOUBLE_FLOAT
)
11078 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
11079 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
11080 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
11081 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
11083 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
11084 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
11085 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
11086 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
11087 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
11088 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
11089 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
11091 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
11092 "__mips16_extendsfdf2");
11093 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
11094 "__mips16_truncdfsf2");
11095 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
11096 "__mips16_fix_truncdfsi");
11097 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
11098 "__mips16_floatsidf");
11099 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
11100 "__mips16_floatunsidf");
11104 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11105 on an external non-MIPS16 routine to implement __sync_synchronize. */
11107 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
11110 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11113 mips_process_load_label (rtx target
)
11115 rtx base
, gp
, intop
;
11116 HOST_WIDE_INT offset
;
11118 mips_multi_start ();
11122 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
11123 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11127 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
11128 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11132 gp
= pic_offset_table_rtx
;
11133 if (mips_cfun_has_cprestore_slot_p ())
11135 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
11136 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11137 if (!SMALL_OPERAND (offset
))
11139 intop
= GEN_INT (CONST_HIGH_PART (offset
));
11140 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
11141 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
11144 offset
= CONST_LOW_PART (offset
);
11146 intop
= GEN_INT (offset
);
11147 if (ISA_HAS_LOAD_DELAY
)
11148 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
11150 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
11152 if (ISA_HAS_LOAD_DELAY
)
11153 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
11155 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
11156 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
11161 /* Return the number of instructions needed to load a label into $AT. */
11163 static unsigned int
11164 mips_load_label_num_insns (void)
11166 if (cfun
->machine
->load_label_num_insns
== 0)
11168 mips_process_load_label (pc_rtx
);
11169 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
11171 return cfun
->machine
->load_label_num_insns
;
11174 /* Emit an asm sequence to start a noat block and load the address
11175 of a label into $1. */
11178 mips_output_load_label (rtx target
)
11180 mips_push_asm_switch (&mips_noat
);
11181 if (TARGET_EXPLICIT_RELOCS
)
11183 mips_process_load_label (target
);
11184 mips_multi_write ();
11188 if (Pmode
== DImode
)
11189 output_asm_insn ("dla\t%@,%0", &target
);
11191 output_asm_insn ("la\t%@,%0", &target
);
11195 /* Return the length of INSN. LENGTH is the initial length computed by
11196 attributes in the machine-description file. */
11199 mips_adjust_insn_length (rtx insn
, int length
)
11201 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11202 of a PIC long-branch sequence. Substitute the correct value. */
11203 if (length
== MAX_PIC_BRANCH_LENGTH
11204 && INSN_CODE (insn
) >= 0
11205 && get_attr_type (insn
) == TYPE_BRANCH
)
11207 /* Add the branch-over instruction and its delay slot, if this
11208 is a conditional branch. */
11209 length
= simplejump_p (insn
) ? 0 : 8;
11211 /* Load the label into $AT and jump to it. Ignore the delay
11212 slot of the jump. */
11213 length
+= 4 * mips_load_label_num_insns() + 4;
11216 /* A unconditional jump has an unfilled delay slot if it is not part
11217 of a sequence. A conditional jump normally has a delay slot, but
11218 does not on MIPS16. */
11219 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
11222 /* See how many nops might be needed to avoid hardware hazards. */
11223 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
11224 switch (get_attr_hazard (insn
))
11238 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11239 the .md file length attributes are 4-based for both modes.
11240 Adjust the MIPS16 ones here. */
11247 /* Return the assembly code for INSN, which has the operands given by
11248 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11249 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11250 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11251 version of BRANCH_IF_TRUE. */
11254 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
11255 const char *branch_if_true
,
11256 const char *branch_if_false
)
11258 unsigned int length
;
11259 rtx taken
, not_taken
;
11261 gcc_assert (LABEL_P (operands
[0]));
11263 length
= get_attr_length (insn
);
11266 /* Just a simple conditional branch. */
11267 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
11268 return branch_if_true
;
11271 /* Generate a reversed branch around a direct jump. This fallback does
11272 not use branch-likely instructions. */
11273 mips_branch_likely
= false;
11274 not_taken
= gen_label_rtx ();
11275 taken
= operands
[0];
11277 /* Generate the reversed branch to NOT_TAKEN. */
11278 operands
[0] = not_taken
;
11279 output_asm_insn (branch_if_false
, operands
);
11281 /* If INSN has a delay slot, we must provide delay slots for both the
11282 branch to NOT_TAKEN and the conditional jump. We must also ensure
11283 that INSN's delay slot is executed in the appropriate cases. */
11284 if (final_sequence
)
11286 /* This first delay slot will always be executed, so use INSN's
11287 delay slot if is not annulled. */
11288 if (!INSN_ANNULLED_BRANCH_P (insn
))
11290 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11291 asm_out_file
, optimize
, 1, NULL
);
11292 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11295 output_asm_insn ("nop", 0);
11296 fprintf (asm_out_file
, "\n");
11299 /* Output the unconditional branch to TAKEN. */
11300 if (TARGET_ABSOLUTE_JUMPS
)
11301 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
11304 mips_output_load_label (taken
);
11305 output_asm_insn ("jr\t%@%]%/", 0);
11308 /* Now deal with its delay slot; see above. */
11309 if (final_sequence
)
11311 /* This delay slot will only be executed if the branch is taken.
11312 Use INSN's delay slot if is annulled. */
11313 if (INSN_ANNULLED_BRANCH_P (insn
))
11315 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11316 asm_out_file
, optimize
, 1, NULL
);
11317 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11320 output_asm_insn ("nop", 0);
11321 fprintf (asm_out_file
, "\n");
11324 /* Output NOT_TAKEN. */
11325 targetm
.asm_out
.internal_label (asm_out_file
, "L",
11326 CODE_LABEL_NUMBER (not_taken
));
11330 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11331 if some ordering condition is true. The condition is given by
11332 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11333 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11334 its second is always zero. */
11337 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
11339 const char *branch
[2];
11341 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11342 Make BRANCH[0] branch on the inverse condition. */
11343 switch (GET_CODE (operands
[1]))
11345 /* These cases are equivalent to comparisons against zero. */
11347 inverted_p
= !inverted_p
;
11348 /* Fall through. */
11350 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
11351 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
11354 /* These cases are always true or always false. */
11356 inverted_p
= !inverted_p
;
11357 /* Fall through. */
11359 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
11360 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
11364 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
11365 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
11368 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
11371 /* Start a block of code that needs access to the LL, SC and SYNC
11375 mips_start_ll_sc_sync_block (void)
11377 if (!ISA_HAS_LL_SC
)
11379 output_asm_insn (".set\tpush", 0);
11380 output_asm_insn (".set\tmips2", 0);
11384 /* End a block started by mips_start_ll_sc_sync_block. */
11387 mips_end_ll_sc_sync_block (void)
11389 if (!ISA_HAS_LL_SC
)
11390 output_asm_insn (".set\tpop", 0);
11393 /* Output and/or return the asm template for a sync instruction. */
11396 mips_output_sync (void)
11398 mips_start_ll_sc_sync_block ();
11399 output_asm_insn ("sync", 0);
11400 mips_end_ll_sc_sync_block ();
11404 /* Return the asm template associated with sync_insn1 value TYPE.
11405 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11407 static const char *
11408 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
11412 case SYNC_INSN1_MOVE
:
11413 return "move\t%0,%z2";
11414 case SYNC_INSN1_LI
:
11415 return "li\t%0,%2";
11416 case SYNC_INSN1_ADDU
:
11417 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11418 case SYNC_INSN1_ADDIU
:
11419 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11420 case SYNC_INSN1_SUBU
:
11421 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11422 case SYNC_INSN1_AND
:
11423 return "and\t%0,%1,%z2";
11424 case SYNC_INSN1_ANDI
:
11425 return "andi\t%0,%1,%2";
11426 case SYNC_INSN1_OR
:
11427 return "or\t%0,%1,%z2";
11428 case SYNC_INSN1_ORI
:
11429 return "ori\t%0,%1,%2";
11430 case SYNC_INSN1_XOR
:
11431 return "xor\t%0,%1,%z2";
11432 case SYNC_INSN1_XORI
:
11433 return "xori\t%0,%1,%2";
11435 gcc_unreachable ();
11438 /* Return the asm template associated with sync_insn2 value TYPE. */
11440 static const char *
11441 mips_sync_insn2_template (enum attr_sync_insn2 type
)
11445 case SYNC_INSN2_NOP
:
11446 gcc_unreachable ();
11447 case SYNC_INSN2_AND
:
11448 return "and\t%0,%1,%z2";
11449 case SYNC_INSN2_XOR
:
11450 return "xor\t%0,%1,%z2";
11451 case SYNC_INSN2_NOT
:
11452 return "nor\t%0,%1,%.";
11454 gcc_unreachable ();
11457 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11458 the value of the one of the sync_* attributes. Return the operand
11459 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11460 have the associated attribute. */
11463 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
11466 default_value
= operands
[index
- 1];
11467 return default_value
;
11470 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11471 sequence for it. */
11474 mips_process_sync_loop (rtx insn
, rtx
*operands
)
11476 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
11477 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
;
11478 unsigned int tmp3_insn
;
11479 enum attr_sync_insn1 insn1
;
11480 enum attr_sync_insn2 insn2
;
11483 /* Read an operand from the sync_WHAT attribute and store it in
11484 variable WHAT. DEFAULT is the default value if no attribute
11486 #define READ_OPERAND(WHAT, DEFAULT) \
11487 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11490 /* Read the memory. */
11491 READ_OPERAND (mem
, 0);
11493 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
11495 /* Read the other attributes. */
11496 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
11497 READ_OPERAND (oldval
, at
);
11498 READ_OPERAND (newval
, at
);
11499 READ_OPERAND (inclusive_mask
, 0);
11500 READ_OPERAND (exclusive_mask
, 0);
11501 READ_OPERAND (required_oldval
, 0);
11502 READ_OPERAND (insn1_op2
, 0);
11503 insn1
= get_attr_sync_insn1 (insn
);
11504 insn2
= get_attr_sync_insn2 (insn
);
11506 mips_multi_start ();
11508 /* Output the release side of the memory barrier. */
11509 if (get_attr_sync_release_barrier (insn
) == SYNC_RELEASE_BARRIER_YES
)
11511 if (required_oldval
== 0 && TARGET_OCTEON
)
11513 /* Octeon doesn't reorder reads, so a full barrier can be
11514 created by using SYNCW to order writes combined with the
11515 write from the following SC. When the SC successfully
11516 completes, we know that all preceding writes are also
11517 committed to the coherent memory system. It is possible
11518 for a single SYNCW to fail, but a pair of them will never
11519 fail, so we use two. */
11520 mips_multi_add_insn ("syncw", NULL
);
11521 mips_multi_add_insn ("syncw", NULL
);
11524 mips_multi_add_insn ("sync", NULL
);
11527 /* Output the branch-back label. */
11528 mips_multi_add_label ("1:");
11530 /* OLDVAL = *MEM. */
11531 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
11532 oldval
, mem
, NULL
);
11534 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11535 if (required_oldval
)
11537 if (inclusive_mask
== 0)
11541 gcc_assert (oldval
!= at
);
11542 mips_multi_add_insn ("and\t%0,%1,%2",
11543 at
, oldval
, inclusive_mask
, NULL
);
11546 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
11549 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11550 if (exclusive_mask
== 0)
11554 gcc_assert (oldval
!= at
);
11555 mips_multi_add_insn ("and\t%0,%1,%z2",
11556 at
, oldval
, exclusive_mask
, NULL
);
11560 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11562 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11563 at least one instruction in that case. */
11564 if (insn1
== SYNC_INSN1_MOVE
11565 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
11569 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
11570 newval
, oldval
, insn1_op2
, NULL
);
11574 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11575 if (insn2
== SYNC_INSN2_NOP
)
11579 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
11580 newval
, tmp2
, inclusive_mask
, NULL
);
11583 tmp3_insn
= mips_multi_last_index ();
11585 /* $AT = $TMP1 | $TMP3. */
11586 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
11588 mips_multi_set_operand (tmp3_insn
, 0, at
);
11593 gcc_assert (tmp1
!= tmp3
);
11594 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
11597 /* if (!commit (*MEM = $AT)) goto 1.
11599 This will sometimes be a delayed branch; see the write code below
11601 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
11602 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
11604 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11605 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
11607 mips_multi_copy_insn (tmp3_insn
);
11608 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
11611 mips_multi_add_insn ("nop", NULL
);
11613 /* Output the acquire side of the memory barrier. */
11614 if (TARGET_SYNC_AFTER_SC
)
11615 mips_multi_add_insn ("sync", NULL
);
11617 /* Output the exit label, if needed. */
11618 if (required_oldval
)
11619 mips_multi_add_label ("2:");
11621 #undef READ_OPERAND
11624 /* Output and/or return the asm template for sync loop INSN, which has
11625 the operands given by OPERANDS. */
11628 mips_output_sync_loop (rtx insn
, rtx
*operands
)
11630 mips_process_sync_loop (insn
, operands
);
11632 /* Use branch-likely instructions to work around the LL/SC R10000
11634 mips_branch_likely
= TARGET_FIX_R10000
;
11636 mips_push_asm_switch (&mips_noreorder
);
11637 mips_push_asm_switch (&mips_nomacro
);
11638 mips_push_asm_switch (&mips_noat
);
11639 mips_start_ll_sc_sync_block ();
11641 mips_multi_write ();
11643 mips_end_ll_sc_sync_block ();
11644 mips_pop_asm_switch (&mips_noat
);
11645 mips_pop_asm_switch (&mips_nomacro
);
11646 mips_pop_asm_switch (&mips_noreorder
);
11651 /* Return the number of individual instructions in sync loop INSN,
11652 which has the operands given by OPERANDS. */
11655 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
11657 mips_process_sync_loop (insn
, operands
);
11658 return mips_multi_num_insns
;
11661 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11662 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11664 When working around R4000 and R4400 errata, we need to make sure that
11665 the division is not immediately followed by a shift[1][2]. We also
11666 need to stop the division from being put into a branch delay slot[3].
11667 The easiest way to avoid both problems is to add a nop after the
11668 division. When a divide-by-zero check is needed, this nop can be
11669 used to fill the branch delay slot.
11671 [1] If a double-word or a variable shift executes immediately
11672 after starting an integer division, the shift may give an
11673 incorrect result. See quotations of errata #16 and #28 from
11674 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11675 in mips.md for details.
11677 [2] A similar bug to [1] exists for all revisions of the
11678 R4000 and the R4400 when run in an MC configuration.
11679 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11681 "19. In this following sequence:
11683 ddiv (or ddivu or div or divu)
11684 dsll32 (or dsrl32, dsra32)
11686 if an MPT stall occurs, while the divide is slipping the cpu
11687 pipeline, then the following double shift would end up with an
11690 Workaround: The compiler needs to avoid generating any
11691 sequence with divide followed by extended double shift."
11693 This erratum is also present in "MIPS R4400MC Errata, Processor
11694 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11695 & 3.0" as errata #10 and #4, respectively.
11697 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11698 (also valid for MIPS R4000MC processors):
11700 "52. R4000SC: This bug does not apply for the R4000PC.
11702 There are two flavors of this bug:
11704 1) If the instruction just after divide takes an RF exception
11705 (tlb-refill, tlb-invalid) and gets an instruction cache
11706 miss (both primary and secondary) and the line which is
11707 currently in secondary cache at this index had the first
11708 data word, where the bits 5..2 are set, then R4000 would
11709 get a wrong result for the div.
11714 ------------------- # end-of page. -tlb-refill
11719 ------------------- # end-of page. -tlb-invalid
11722 2) If the divide is in the taken branch delay slot, where the
11723 target takes RF exception and gets an I-cache miss for the
11724 exception vector or where I-cache miss occurs for the
11725 target address, under the above mentioned scenarios, the
11726 div would get wrong results.
11729 j r2 # to next page mapped or unmapped
11730 div r8,r9 # this bug would be there as long
11731 # as there is an ICache miss and
11732 nop # the "data pattern" is present
11735 beq r0, r0, NextPage # to Next page
11739 This bug is present for div, divu, ddiv, and ddivu
11742 Workaround: For item 1), OS could make sure that the next page
11743 after the divide instruction is also mapped. For item 2), the
11744 compiler could make sure that the divide instruction is not in
11745 the branch delay slot."
11747 These processors have PRId values of 0x00004220 and 0x00004300 for
11748 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11751 mips_output_division (const char *division
, rtx
*operands
)
11756 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
11758 output_asm_insn (s
, operands
);
11761 if (TARGET_CHECK_ZERO_DIV
)
11765 output_asm_insn (s
, operands
);
11766 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
11768 else if (GENERATE_DIVIDE_TRAPS
)
11770 /* Avoid long replay penalty on load miss by putting the trap before
11773 output_asm_insn ("teq\t%2,%.,7", operands
);
11776 output_asm_insn (s
, operands
);
11777 s
= "teq\t%2,%.,7";
11782 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
11783 output_asm_insn (s
, operands
);
11784 s
= "break\t7%)\n1:";
11790 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11791 instruction and if OUT_INSN assigns to the accumulator operand. */
11794 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
11798 x
= single_set (in_insn
);
11804 if (GET_CODE (x
) == PLUS
11805 && GET_CODE (XEXP (x
, 0)) == MULT
11806 && reg_set_p (XEXP (x
, 1), out_insn
))
11809 if (GET_CODE (x
) == MINUS
11810 && GET_CODE (XEXP (x
, 1)) == MULT
11811 && reg_set_p (XEXP (x
, 0), out_insn
))
11817 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11818 data rather than the address. We need this because the cprestore
11819 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11820 which causes the default routine to abort. We just return false
11824 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
11826 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
11829 return !store_data_bypass_p (out_insn
, in_insn
);
11833 /* Variables and flags used in scheduler hooks when tuning for
11837 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11840 /* If true, then next ALU1/2 instruction will go to ALU1. */
11843 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11846 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11847 int alu1_core_unit_code
;
11848 int alu2_core_unit_code
;
11849 int falu1_core_unit_code
;
11850 int falu2_core_unit_code
;
11852 /* True if current cycle has a multi instruction.
11853 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11854 bool cycle_has_multi_p
;
11856 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11857 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11859 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11860 instruction to go ALU1. */
11861 rtx alu1_turn_enabled_insn
;
11862 rtx alu2_turn_enabled_insn
;
11863 rtx falu1_turn_enabled_insn
;
11864 rtx falu2_turn_enabled_insn
;
11867 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11868 dependencies have no cost, except on the 20Kc where output-dependence
11869 is treated like input-dependence. */
11872 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
11873 rtx dep ATTRIBUTE_UNUSED
, int cost
)
11875 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
11878 if (REG_NOTE_KIND (link
) != 0)
11883 /* Return the number of instructions that can be issued per cycle. */
11886 mips_issue_rate (void)
11890 case PROCESSOR_74KC
:
11891 case PROCESSOR_74KF2_1
:
11892 case PROCESSOR_74KF1_1
:
11893 case PROCESSOR_74KF3_2
:
11894 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11895 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11896 but in reality only a maximum of 3 insns can be issued as
11897 floating-point loads and stores also require a slot in the
11899 case PROCESSOR_R10000
:
11900 /* All R10K Processors are quad-issue (being the first MIPS
11901 processors to support this feature). */
11904 case PROCESSOR_20KC
:
11905 case PROCESSOR_R4130
:
11906 case PROCESSOR_R5400
:
11907 case PROCESSOR_R5500
:
11908 case PROCESSOR_R7000
:
11909 case PROCESSOR_R9000
:
11910 case PROCESSOR_OCTEON
:
11913 case PROCESSOR_SB1
:
11914 case PROCESSOR_SB1A
:
11915 /* This is actually 4, but we get better performance if we claim 3.
11916 This is partly because of unwanted speculative code motion with the
11917 larger number, and partly because in most common cases we can't
11918 reach the theoretical max of 4. */
11921 case PROCESSOR_LOONGSON_2E
:
11922 case PROCESSOR_LOONGSON_2F
:
11923 case PROCESSOR_LOONGSON_3A
:
11931 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11934 mips_ls2_init_dfa_post_cycle_insn (void)
11937 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11938 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
11942 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11943 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
11947 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11948 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
11952 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11953 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
11956 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
11957 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
11958 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
11959 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
11962 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11963 Init data used in mips_dfa_post_advance_cycle. */
11966 mips_init_dfa_post_cycle_insn (void)
11968 if (TUNE_LOONGSON_2EF
)
11969 mips_ls2_init_dfa_post_cycle_insn ();
11972 /* Initialize STATE when scheduling for Loongson 2E/2F.
11973 Support round-robin dispatch scheme by enabling only one of
11974 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
11978 mips_ls2_dfa_post_advance_cycle (state_t state
)
11980 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
11982 /* Though there are no non-pipelined ALU1 insns,
11983 we can get an instruction of type 'multi' before reload. */
11984 gcc_assert (mips_ls2
.cycle_has_multi_p
);
11985 mips_ls2
.alu1_turn_p
= false;
11988 mips_ls2
.cycle_has_multi_p
= false;
11990 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
11991 /* We have a non-pipelined alu instruction in the core,
11992 adjust round-robin counter. */
11993 mips_ls2
.alu1_turn_p
= true;
11995 if (mips_ls2
.alu1_turn_p
)
11997 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
11998 gcc_unreachable ();
12002 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
12003 gcc_unreachable ();
12006 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
12008 /* There are no non-pipelined FALU1 insns. */
12009 gcc_unreachable ();
12010 mips_ls2
.falu1_turn_p
= false;
12013 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
12014 /* We have a non-pipelined falu instruction in the core,
12015 adjust round-robin counter. */
12016 mips_ls2
.falu1_turn_p
= true;
12018 if (mips_ls2
.falu1_turn_p
)
12020 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
12021 gcc_unreachable ();
12025 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
12026 gcc_unreachable ();
12030 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12031 This hook is being called at the start of each cycle. */
12034 mips_dfa_post_advance_cycle (void)
12036 if (TUNE_LOONGSON_2EF
)
12037 mips_ls2_dfa_post_advance_cycle (curr_state
);
12040 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12041 be as wide as the scheduling freedom in the DFA. */
12044 mips_multipass_dfa_lookahead (void)
12046 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12050 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
12059 /* Remove the instruction at index LOWER from ready queue READY and
12060 reinsert it in front of the instruction at index HIGHER. LOWER must
12064 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
12069 new_head
= ready
[lower
];
12070 for (i
= lower
; i
< higher
; i
++)
12071 ready
[i
] = ready
[i
+ 1];
12072 ready
[i
] = new_head
;
12075 /* If the priority of the instruction at POS2 in the ready queue READY
12076 is within LIMIT units of that of the instruction at POS1, swap the
12077 instructions if POS2 is not already less than POS1. */
12080 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
12083 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
12087 temp
= ready
[pos1
];
12088 ready
[pos1
] = ready
[pos2
];
12089 ready
[pos2
] = temp
;
12093 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12094 that may clobber hi or lo. */
12095 static rtx mips_macc_chains_last_hilo
;
12097 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12098 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12101 mips_macc_chains_record (rtx insn
)
12103 if (get_attr_may_clobber_hilo (insn
))
12104 mips_macc_chains_last_hilo
= insn
;
12107 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12108 has NREADY elements, looking for a multiply-add or multiply-subtract
12109 instruction that is cumulative with mips_macc_chains_last_hilo.
12110 If there is one, promote it ahead of anything else that might
12111 clobber hi or lo. */
12114 mips_macc_chains_reorder (rtx
*ready
, int nready
)
12118 if (mips_macc_chains_last_hilo
!= 0)
12119 for (i
= nready
- 1; i
>= 0; i
--)
12120 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
12122 for (j
= nready
- 1; j
> i
; j
--)
12123 if (recog_memoized (ready
[j
]) >= 0
12124 && get_attr_may_clobber_hilo (ready
[j
]))
12126 mips_promote_ready (ready
, i
, j
);
12133 /* The last instruction to be scheduled. */
12134 static rtx vr4130_last_insn
;
12136 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12137 points to an rtx that is initially an instruction. Nullify the rtx
12138 if the instruction uses the value of register X. */
12141 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
12146 insn_ptr
= (rtx
*) data
;
12149 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
12153 /* Return true if there is true register dependence between vr4130_last_insn
12157 vr4130_true_reg_dependence_p (rtx insn
)
12159 note_stores (PATTERN (vr4130_last_insn
),
12160 vr4130_true_reg_dependence_p_1
, &insn
);
12164 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12165 the ready queue and that INSN2 is the instruction after it, return
12166 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12167 in which INSN1 and INSN2 can probably issue in parallel, but for
12168 which (INSN2, INSN1) should be less sensitive to instruction
12169 alignment than (INSN1, INSN2). See 4130.md for more details. */
12172 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
12174 sd_iterator_def sd_it
;
12177 /* Check for the following case:
12179 1) there is some other instruction X with an anti dependence on INSN1;
12180 2) X has a higher priority than INSN2; and
12181 3) X is an arithmetic instruction (and thus has no unit restrictions).
12183 If INSN1 is the last instruction blocking X, it would better to
12184 choose (INSN1, X) over (INSN2, INSN1). */
12185 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
12186 if (DEP_TYPE (dep
) == REG_DEP_ANTI
12187 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
12188 && recog_memoized (DEP_CON (dep
)) >= 0
12189 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
12192 if (vr4130_last_insn
!= 0
12193 && recog_memoized (insn1
) >= 0
12194 && recog_memoized (insn2
) >= 0)
12196 /* See whether INSN1 and INSN2 use different execution units,
12197 or if they are both ALU-type instructions. If so, they can
12198 probably execute in parallel. */
12199 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
12200 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
12201 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
12203 /* If only one of the instructions has a dependence on
12204 vr4130_last_insn, prefer to schedule the other one first. */
12205 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
12206 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
12207 if (dep1_p
!= dep2_p
)
12210 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12211 is not an ALU-type instruction and if INSN1 uses the same
12212 execution unit. (Note that if this condition holds, we already
12213 know that INSN2 uses a different execution unit.) */
12214 if (class1
!= VR4130_CLASS_ALU
12215 && recog_memoized (vr4130_last_insn
) >= 0
12216 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
12223 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12224 queue with at least two instructions. Swap the first two if
12225 vr4130_swap_insns_p says that it could be worthwhile. */
12228 vr4130_reorder (rtx
*ready
, int nready
)
12230 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
12231 mips_promote_ready (ready
, nready
- 2, nready
- 1);
12234 /* Record whether last 74k AGEN instruction was a load or store. */
12235 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12237 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12238 resets to TYPE_UNKNOWN state. */
12241 mips_74k_agen_init (rtx insn
)
12243 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
12244 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12247 enum attr_type type
= get_attr_type (insn
);
12248 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
12249 mips_last_74k_agen_insn
= type
;
12253 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12254 loads to be grouped together, and multiple stores to be grouped
12255 together. Swap things around in the ready queue to make this happen. */
12258 mips_74k_agen_reorder (rtx
*ready
, int nready
)
12261 int store_pos
, load_pos
;
12266 for (i
= nready
- 1; i
>= 0; i
--)
12268 rtx insn
= ready
[i
];
12269 if (USEFUL_INSN_P (insn
))
12270 switch (get_attr_type (insn
))
12273 if (store_pos
== -1)
12278 if (load_pos
== -1)
12287 if (load_pos
== -1 || store_pos
== -1)
12290 switch (mips_last_74k_agen_insn
)
12293 /* Prefer to schedule loads since they have a higher latency. */
12295 /* Swap loads to the front of the queue. */
12296 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
12299 /* Swap stores to the front of the queue. */
12300 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
12307 /* Implement TARGET_SCHED_INIT. */
12310 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12311 int max_ready ATTRIBUTE_UNUSED
)
12313 mips_macc_chains_last_hilo
= 0;
12314 vr4130_last_insn
= 0;
12315 mips_74k_agen_init (NULL_RTX
);
12317 /* When scheduling for Loongson2, branch instructions go to ALU1,
12318 therefore basic block is most likely to start with round-robin counter
12319 pointed to ALU2. */
12320 mips_ls2
.alu1_turn_p
= false;
12321 mips_ls2
.falu1_turn_p
= true;
12324 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12327 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12328 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12330 if (!reload_completed
12331 && TUNE_MACC_CHAINS
12333 mips_macc_chains_reorder (ready
, *nreadyp
);
12335 if (reload_completed
12337 && !TARGET_VR4130_ALIGN
12339 vr4130_reorder (ready
, *nreadyp
);
12342 mips_74k_agen_reorder (ready
, *nreadyp
);
12345 /* Implement TARGET_SCHED_REORDER. */
12348 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12349 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12351 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
12352 return mips_issue_rate ();
12355 /* Implement TARGET_SCHED_REORDER2. */
12358 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12359 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12361 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
12362 return cached_can_issue_more
;
12365 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12368 mips_ls2_variable_issue (rtx insn
)
12370 if (mips_ls2
.alu1_turn_p
)
12372 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
12373 mips_ls2
.alu1_turn_p
= false;
12377 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
12378 mips_ls2
.alu1_turn_p
= true;
12381 if (mips_ls2
.falu1_turn_p
)
12383 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
12384 mips_ls2
.falu1_turn_p
= false;
12388 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
12389 mips_ls2
.falu1_turn_p
= true;
12392 if (recog_memoized (insn
) >= 0)
12393 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
12396 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12399 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12400 rtx insn
, int more
)
12402 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12403 if (USEFUL_INSN_P (insn
))
12405 if (get_attr_type (insn
) != TYPE_GHOST
)
12407 if (!reload_completed
&& TUNE_MACC_CHAINS
)
12408 mips_macc_chains_record (insn
);
12409 vr4130_last_insn
= insn
;
12411 mips_74k_agen_init (insn
);
12412 else if (TUNE_LOONGSON_2EF
)
12413 mips_ls2_variable_issue (insn
);
12416 /* Instructions of type 'multi' should all be split before
12417 the second scheduling pass. */
12418 gcc_assert (!reload_completed
12419 || recog_memoized (insn
) < 0
12420 || get_attr_type (insn
) != TYPE_MULTI
);
12422 cached_can_issue_more
= more
;
12426 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12427 return the first operand of the associated PREF or PREFX insn. */
12430 mips_prefetch_cookie (rtx write
, rtx locality
)
12432 /* store_streamed / load_streamed. */
12433 if (INTVAL (locality
) <= 0)
12434 return GEN_INT (INTVAL (write
) + 4);
12436 /* store / load. */
12437 if (INTVAL (locality
) <= 2)
12440 /* store_retained / load_retained. */
12441 return GEN_INT (INTVAL (write
) + 6);
12444 /* Flags that indicate when a built-in function is available.
12446 BUILTIN_AVAIL_NON_MIPS16
12447 The function is available on the current target, but only
12448 in non-MIPS16 mode. */
12449 #define BUILTIN_AVAIL_NON_MIPS16 1
12451 /* Declare an availability predicate for built-in functions that
12452 require non-MIPS16 mode and also require COND to be true.
12453 NAME is the main part of the predicate's name. */
12454 #define AVAIL_NON_MIPS16(NAME, COND) \
12455 static unsigned int \
12456 mips_builtin_avail_##NAME (void) \
12458 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12461 /* This structure describes a single built-in function. */
12462 struct mips_builtin_description
{
12463 /* The code of the main .md file instruction. See mips_builtin_type
12464 for more information. */
12465 enum insn_code icode
;
12467 /* The floating-point comparison code to use with ICODE, if any. */
12468 enum mips_fp_condition cond
;
12470 /* The name of the built-in function. */
12473 /* Specifies how the function should be expanded. */
12474 enum mips_builtin_type builtin_type
;
12476 /* The function's prototype. */
12477 enum mips_function_type function_type
;
12479 /* Whether the function is available. */
12480 unsigned int (*avail
) (void);
12483 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
12484 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
12485 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
12486 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
12487 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
12488 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
12489 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
12490 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
12491 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
12493 /* Construct a mips_builtin_description from the given arguments.
12495 INSN is the name of the associated instruction pattern, without the
12496 leading CODE_FOR_mips_.
12498 CODE is the floating-point condition code associated with the
12499 function. It can be 'f' if the field is not applicable.
12501 NAME is the name of the function itself, without the leading
12504 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12506 AVAIL is the name of the availability predicate, without the leading
12507 mips_builtin_avail_. */
12508 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12509 FUNCTION_TYPE, AVAIL) \
12510 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12511 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12512 mips_builtin_avail_ ## AVAIL }
12514 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12515 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12516 are as for MIPS_BUILTIN. */
12517 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12518 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12520 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12521 are subject to mips_builtin_avail_<AVAIL>. */
12522 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12523 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12524 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12525 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12526 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12528 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12529 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12530 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12531 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12532 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12533 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12535 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12536 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12538 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12539 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12541 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12542 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12545 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12546 are subject to mips_builtin_avail_mips3d. */
12547 #define CMP_4S_BUILTINS(INSN, COND) \
12548 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12549 MIPS_BUILTIN_CMP_ANY, \
12550 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12551 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12552 MIPS_BUILTIN_CMP_ALL, \
12553 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12555 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12556 instruction requires mips_builtin_avail_<AVAIL>. */
12557 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12558 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12559 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12561 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12562 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12565 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12566 #define CMP_BUILTINS(COND) \
12567 MOVTF_BUILTINS (c, COND, paired_single), \
12568 MOVTF_BUILTINS (cabs, COND, mips3d), \
12569 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12570 CMP_PS_BUILTINS (c, COND, paired_single), \
12571 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12572 CMP_4S_BUILTINS (c, COND), \
12573 CMP_4S_BUILTINS (cabs, COND)
12575 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12576 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12577 and AVAIL are as for MIPS_BUILTIN. */
12578 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12579 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12580 FUNCTION_TYPE, AVAIL)
12582 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12583 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12584 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12585 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12586 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12588 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12589 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12590 builtin_description field. */
12591 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12592 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12593 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12594 FUNCTION_TYPE, mips_builtin_avail_loongson }
12596 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12597 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12598 builtin_description field. */
12599 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12600 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12602 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12603 We use functions of this form when the same insn can be usefully applied
12604 to more than one datatype. */
12605 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12606 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12608 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12609 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12610 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12611 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12612 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12613 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12614 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
12615 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
12617 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12618 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12619 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12620 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12621 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12622 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12623 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12624 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12625 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12626 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12627 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12628 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12629 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12630 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12631 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12632 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12633 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12634 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
12635 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
12636 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
12637 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
12638 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
12639 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
12640 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12641 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12642 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12643 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12644 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12645 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12646 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12647 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12648 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12649 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12650 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12651 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12652 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12654 static const struct mips_builtin_description mips_builtins
[] = {
12655 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12656 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12657 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12658 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12659 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
12660 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
12661 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
12662 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
12664 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
12665 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12666 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12667 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12668 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12670 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
12671 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
12672 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12673 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
12674 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
12675 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12677 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
12678 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
12679 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12680 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
12681 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
12682 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12684 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
12686 /* Built-in functions for the SB-1 processor. */
12687 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
12689 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12690 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12691 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12692 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12693 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12694 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12695 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12696 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12697 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12698 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12699 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12700 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12701 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12702 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12703 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
12704 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
12705 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
12706 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
12707 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
12708 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
12709 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
12710 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
12711 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
12712 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12713 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12714 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12715 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12716 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12717 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12718 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12719 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12720 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
12721 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12722 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12723 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12724 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
12725 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12726 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12727 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12728 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
12729 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
12730 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12731 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
12732 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
12733 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
12734 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12735 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
12736 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
12737 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12738 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12739 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12740 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12741 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12742 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12743 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12744 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12745 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12746 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12747 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12748 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12749 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
12750 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
12751 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12752 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12753 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12754 BPOSGE_BUILTIN (32, dsp
),
12756 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12757 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
12758 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12759 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12760 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12761 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12762 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12763 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12764 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12765 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12766 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12767 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12768 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12769 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12770 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12771 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12772 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
12773 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
12774 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
12775 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12776 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
12777 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
12778 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
12779 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12780 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12781 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12782 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12783 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12784 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12785 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12786 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12787 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12788 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12789 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12790 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12792 /* Built-in functions for the DSP ASE (32-bit only). */
12793 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12794 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12795 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12796 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12797 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12798 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12799 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12800 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12801 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12802 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12803 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12804 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12805 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12806 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12807 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12808 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12809 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12810 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12811 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12812 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
12813 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
12814 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12815 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
12816 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12817 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
12818 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
12819 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
12821 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12822 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12823 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12824 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12825 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12826 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12827 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12828 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12829 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12830 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12832 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12833 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
12834 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
12835 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
12836 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12837 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12838 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12839 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12840 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12841 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12842 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
12843 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
12844 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12845 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12846 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12847 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12848 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
12849 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12850 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12851 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12852 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
12853 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12854 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12855 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12856 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12857 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12858 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12859 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12860 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12861 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12862 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12863 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12864 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12865 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12866 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12867 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12868 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12869 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12870 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
12871 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
12872 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12873 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12874 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12875 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12876 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12877 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12878 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12879 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12880 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
12881 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12882 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12883 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12884 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12885 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
12886 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
12887 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12888 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12889 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12890 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
12891 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12892 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
12893 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
12894 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI
),
12895 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI
),
12896 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
12897 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
12898 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
12899 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
12900 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
12901 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
12902 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
12903 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
12904 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
12905 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
12906 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
12907 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
12908 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12909 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12910 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12911 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12912 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12913 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12914 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
12915 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
12916 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12917 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12918 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12919 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12920 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12921 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12922 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12923 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12924 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12925 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12926 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12927 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12928 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12929 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12930 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12931 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12933 /* Sundry other built-in functions. */
12934 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
12937 /* Index I is the function declaration for mips_builtins[I], or null if the
12938 function isn't defined on this target. */
12939 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
12941 /* MODE is a vector mode whose elements have type TYPE. Return the type
12942 of the vector itself. */
12945 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
12947 static tree types
[2 * (int) MAX_MACHINE_MODE
];
12950 mode_index
= (int) mode
;
12952 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
12953 mode_index
+= MAX_MACHINE_MODE
;
12955 if (types
[mode_index
] == NULL_TREE
)
12956 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
12957 return types
[mode_index
];
12960 /* Return a type for 'const volatile void *'. */
12963 mips_build_cvpointer_type (void)
12967 if (cache
== NULL_TREE
)
12968 cache
= build_pointer_type (build_qualified_type
12970 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
12974 /* Source-level argument types. */
12975 #define MIPS_ATYPE_VOID void_type_node
12976 #define MIPS_ATYPE_INT integer_type_node
12977 #define MIPS_ATYPE_POINTER ptr_type_node
12978 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12980 /* Standard mode-based argument types. */
12981 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12982 #define MIPS_ATYPE_SI intSI_type_node
12983 #define MIPS_ATYPE_USI unsigned_intSI_type_node
12984 #define MIPS_ATYPE_DI intDI_type_node
12985 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
12986 #define MIPS_ATYPE_SF float_type_node
12987 #define MIPS_ATYPE_DF double_type_node
12989 /* Vector argument types. */
12990 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
12991 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
12992 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
12993 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
12994 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
12995 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
12996 #define MIPS_ATYPE_UV2SI \
12997 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
12998 #define MIPS_ATYPE_UV4HI \
12999 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13000 #define MIPS_ATYPE_UV8QI \
13001 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13003 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13004 their associated MIPS_ATYPEs. */
13005 #define MIPS_FTYPE_ATYPES1(A, B) \
13006 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13008 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13009 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13011 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13012 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13014 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13015 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13018 /* Return the function type associated with function prototype TYPE. */
13021 mips_build_function_type (enum mips_function_type type
)
13023 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
13025 if (types
[(int) type
] == NULL_TREE
)
13028 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13029 case MIPS_FTYPE_NAME##NUM ARGS: \
13030 types[(int) type] \
13031 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13034 #include "config/mips/mips-ftypes.def"
13035 #undef DEF_MIPS_FTYPE
13037 gcc_unreachable ();
13040 return types
[(int) type
];
13043 /* Implement TARGET_INIT_BUILTINS. */
13046 mips_init_builtins (void)
13048 const struct mips_builtin_description
*d
;
13051 /* Iterate through all of the bdesc arrays, initializing all of the
13052 builtin functions. */
13053 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
13055 d
= &mips_builtins
[i
];
13057 mips_builtin_decls
[i
]
13058 = add_builtin_function (d
->name
,
13059 mips_build_function_type (d
->function_type
),
13060 i
, BUILT_IN_MD
, NULL
, NULL
);
13064 /* Implement TARGET_BUILTIN_DECL. */
13067 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
13069 if (code
>= ARRAY_SIZE (mips_builtins
))
13070 return error_mark_node
;
13071 return mips_builtin_decls
[code
];
13074 /* Take argument ARGNO from EXP's argument list and convert it into
13075 an expand operand. Store the operand in *OP. */
13078 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
13079 unsigned int argno
)
13084 arg
= CALL_EXPR_ARG (exp
, argno
);
13085 value
= expand_normal (arg
);
13086 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
13089 /* Expand instruction ICODE as part of a built-in function sequence.
13090 Use the first NOPS elements of OPS as the instruction's operands.
13091 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13092 instruction has no target.
13094 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13097 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
13098 struct expand_operand
*ops
, bool has_target_p
)
13100 if (!maybe_expand_insn (icode
, nops
, ops
))
13102 error ("invalid argument to built-in function");
13103 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
13105 return has_target_p
? ops
[0].value
: const0_rtx
;
13108 /* Expand a floating-point comparison for built-in function call EXP.
13109 The first NARGS arguments are the values to be compared. ICODE is
13110 the .md pattern that does the comparison and COND is the condition
13111 that is being tested. Return an rtx for the result. */
13114 mips_expand_builtin_compare_1 (enum insn_code icode
,
13115 enum mips_fp_condition cond
,
13116 tree exp
, int nargs
)
13118 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
13121 /* The instruction should have a target operand, an operand for each
13122 argument, and an operand for COND. */
13123 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
13126 create_output_operand (&ops
[opno
++], NULL_RTX
,
13127 insn_data
[(int) icode
].operand
[0].mode
);
13128 for (argno
= 0; argno
< nargs
; argno
++)
13129 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
13130 create_integer_operand (&ops
[opno
++], (int) cond
);
13131 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
13134 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13135 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13136 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13137 suggests a good place to put the result. */
13140 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
13143 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
13146 /* Map any target to operand 0. */
13149 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
13151 /* Map the arguments to the other operands. */
13152 gcc_assert (opno
+ call_expr_nargs (exp
)
13153 == insn_data
[icode
].n_generator_args
);
13154 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
13155 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
13157 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
13160 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13161 function; TYPE says which. EXP is the CALL_EXPR that calls the
13162 function, ICODE is the instruction that should be used to compare
13163 the first two arguments, and COND is the condition it should test.
13164 TARGET, if nonnull, suggests a good place to put the result. */
13167 mips_expand_builtin_movtf (enum mips_builtin_type type
,
13168 enum insn_code icode
, enum mips_fp_condition cond
,
13169 rtx target
, tree exp
)
13171 struct expand_operand ops
[4];
13174 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
13175 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
13176 if (type
== MIPS_BUILTIN_MOVT
)
13178 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
13179 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
13183 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
13184 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
13186 create_fixed_operand (&ops
[3], cmp_result
);
13187 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
13191 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13192 into TARGET otherwise. Return TARGET. */
13195 mips_builtin_branch_and_move (rtx condition
, rtx target
,
13196 rtx value_if_true
, rtx value_if_false
)
13198 rtx true_label
, done_label
;
13200 true_label
= gen_label_rtx ();
13201 done_label
= gen_label_rtx ();
13203 /* First assume that CONDITION is false. */
13204 mips_emit_move (target
, value_if_false
);
13206 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13207 emit_jump_insn (gen_condjump (condition
, true_label
));
13208 emit_jump_insn (gen_jump (done_label
));
13211 /* Fix TARGET if CONDITION is true. */
13212 emit_label (true_label
);
13213 mips_emit_move (target
, value_if_true
);
13215 emit_label (done_label
);
13219 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13220 the CALL_EXPR that calls the function, ICODE is the code of the
13221 comparison instruction, and COND is the condition it should test.
13222 TARGET, if nonnull, suggests a good place to put the boolean result. */
13225 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
13226 enum insn_code icode
, enum mips_fp_condition cond
,
13227 rtx target
, tree exp
)
13229 rtx offset
, condition
, cmp_result
;
13231 if (target
== 0 || GET_MODE (target
) != SImode
)
13232 target
= gen_reg_rtx (SImode
);
13233 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
13234 call_expr_nargs (exp
));
13236 /* If the comparison sets more than one register, we define the result
13237 to be 0 if all registers are false and -1 if all registers are true.
13238 The value of the complete result is indeterminate otherwise. */
13239 switch (builtin_type
)
13241 case MIPS_BUILTIN_CMP_ALL
:
13242 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
13243 return mips_builtin_branch_and_move (condition
, target
,
13244 const0_rtx
, const1_rtx
);
13246 case MIPS_BUILTIN_CMP_UPPER
:
13247 case MIPS_BUILTIN_CMP_LOWER
:
13248 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
13249 condition
= gen_single_cc (cmp_result
, offset
);
13250 return mips_builtin_branch_and_move (condition
, target
,
13251 const1_rtx
, const0_rtx
);
13254 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
13255 return mips_builtin_branch_and_move (condition
, target
,
13256 const1_rtx
, const0_rtx
);
13260 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13261 if nonnull, suggests a good place to put the boolean result. */
13264 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
13266 rtx condition
, cmp_result
;
13269 if (target
== 0 || GET_MODE (target
) != SImode
)
13270 target
= gen_reg_rtx (SImode
);
13272 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
13274 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
13279 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
13280 return mips_builtin_branch_and_move (condition
, target
,
13281 const1_rtx
, const0_rtx
);
13284 /* Implement TARGET_EXPAND_BUILTIN. */
13287 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13288 enum machine_mode mode
, int ignore
)
13291 unsigned int fcode
, avail
;
13292 const struct mips_builtin_description
*d
;
13294 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13295 fcode
= DECL_FUNCTION_CODE (fndecl
);
13296 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
13297 d
= &mips_builtins
[fcode
];
13298 avail
= d
->avail ();
13299 gcc_assert (avail
!= 0);
13302 error ("built-in function %qE not supported for MIPS16",
13303 DECL_NAME (fndecl
));
13304 return ignore
? const0_rtx
: CONST0_RTX (mode
);
13306 switch (d
->builtin_type
)
13308 case MIPS_BUILTIN_DIRECT
:
13309 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
13311 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
13312 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
13314 case MIPS_BUILTIN_MOVT
:
13315 case MIPS_BUILTIN_MOVF
:
13316 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
13317 d
->cond
, target
, exp
);
13319 case MIPS_BUILTIN_CMP_ANY
:
13320 case MIPS_BUILTIN_CMP_ALL
:
13321 case MIPS_BUILTIN_CMP_UPPER
:
13322 case MIPS_BUILTIN_CMP_LOWER
:
13323 case MIPS_BUILTIN_CMP_SINGLE
:
13324 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
13325 d
->cond
, target
, exp
);
13327 case MIPS_BUILTIN_BPOSGE32
:
13328 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
13330 gcc_unreachable ();
13333 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13334 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13335 struct mips16_constant
{
13336 struct mips16_constant
*next
;
13339 enum machine_mode mode
;
13342 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13343 first constant, HIGHEST_ADDRESS is the highest address that the first
13344 byte of the pool can have, and INSN_ADDRESS is the current instruction
13346 struct mips16_constant_pool
{
13347 struct mips16_constant
*first
;
13348 int highest_address
;
13352 /* Add constant VALUE to POOL and return its label. MODE is the
13353 value's mode (used for CONST_INTs, etc.). */
13356 mips16_add_constant (struct mips16_constant_pool
*pool
,
13357 rtx value
, enum machine_mode mode
)
13359 struct mips16_constant
**p
, *c
;
13360 bool first_of_size_p
;
13362 /* See whether the constant is already in the pool. If so, return the
13363 existing label, otherwise leave P pointing to the place where the
13364 constant should be added.
13366 Keep the pool sorted in increasing order of mode size so that we can
13367 reduce the number of alignments needed. */
13368 first_of_size_p
= true;
13369 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
13371 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
13372 return (*p
)->label
;
13373 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
13375 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
13376 first_of_size_p
= false;
13379 /* In the worst case, the constant needed by the earliest instruction
13380 will end up at the end of the pool. The entire pool must then be
13381 accessible from that instruction.
13383 When adding the first constant, set the pool's highest address to
13384 the address of the first out-of-range byte. Adjust this address
13385 downwards each time a new constant is added. */
13386 if (pool
->first
== 0)
13387 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13388 of the instruction with the lowest two bits clear. The base PC
13389 value for LDPC has the lowest three bits clear. Assume the worst
13390 case here; namely that the PC-relative instruction occupies the
13391 last 2 bytes in an aligned word. */
13392 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
13393 pool
->highest_address
-= GET_MODE_SIZE (mode
);
13394 if (first_of_size_p
)
13395 /* Take into account the worst possible padding due to alignment. */
13396 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
13398 /* Create a new entry. */
13399 c
= XNEW (struct mips16_constant
);
13402 c
->label
= gen_label_rtx ();
13409 /* Output constant VALUE after instruction INSN and return the last
13410 instruction emitted. MODE is the mode of the constant. */
13413 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
13415 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
13417 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
13418 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
13421 if (SCALAR_FLOAT_MODE_P (mode
))
13422 return emit_insn_after (gen_consttable_float (value
), insn
);
13424 if (VECTOR_MODE_P (mode
))
13428 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
13429 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
13430 CONST_VECTOR_ELT (value
, i
), insn
);
13434 gcc_unreachable ();
13437 /* Dump out the constants in CONSTANTS after INSN. */
13440 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
13442 struct mips16_constant
*c
, *next
;
13446 for (c
= constants
; c
!= NULL
; c
= next
)
13448 /* If necessary, increase the alignment of PC. */
13449 if (align
< GET_MODE_SIZE (c
->mode
))
13451 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
13452 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
13454 align
= GET_MODE_SIZE (c
->mode
);
13456 insn
= emit_label_after (c
->label
, insn
);
13457 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
13463 emit_barrier_after (insn
);
13466 /* Return the length of instruction INSN. */
13469 mips16_insn_length (rtx insn
)
13473 rtx body
= PATTERN (insn
);
13474 if (GET_CODE (body
) == ADDR_VEC
)
13475 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
13476 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
13477 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
13479 return get_attr_length (insn
);
13482 /* If *X is a symbolic constant that refers to the constant pool, add
13483 the constant to POOL and rewrite *X to use the constant's label. */
13486 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
13488 rtx base
, offset
, label
;
13490 split_const (*x
, &base
, &offset
);
13491 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
13493 label
= mips16_add_constant (pool
, get_pool_constant (base
),
13494 get_pool_mode (base
));
13495 base
= gen_rtx_LABEL_REF (Pmode
, label
);
13496 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
13500 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13501 INSN is the instruction we're rewriting and POOL points to the current
13503 struct mips16_rewrite_pool_refs_info
{
13505 struct mips16_constant_pool
*pool
;
13508 /* Rewrite *X so that constant pool references refer to the constant's
13509 label instead. DATA points to a mips16_rewrite_pool_refs_info
13513 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
13515 struct mips16_rewrite_pool_refs_info
*info
=
13516 (struct mips16_rewrite_pool_refs_info
*) data
;
13518 if (force_to_mem_operand (*x
, Pmode
))
13520 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
13521 validate_change (info
->insn
, x
, mem
, false);
13526 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
13530 if (TARGET_MIPS16_TEXT_LOADS
)
13531 mips16_rewrite_pool_constant (info
->pool
, x
);
13533 return GET_CODE (*x
) == CONST
? -1 : 0;
13536 /* Return whether CFG is used in mips_reorg. */
13539 mips_cfg_in_reorg (void)
13541 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
13542 || TARGET_RELAX_PIC_CALLS
);
13545 /* Build MIPS16 constant pools. */
13548 mips16_lay_out_constants (void)
13550 struct mips16_constant_pool pool
;
13551 struct mips16_rewrite_pool_refs_info info
;
13554 if (!TARGET_MIPS16_PCREL_LOADS
)
13557 if (mips_cfg_in_reorg ())
13558 split_all_insns ();
13560 split_all_insns_noflow ();
13562 memset (&pool
, 0, sizeof (pool
));
13563 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13565 /* Rewrite constant pool references in INSN. */
13566 if (USEFUL_INSN_P (insn
))
13570 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
13573 pool
.insn_address
+= mips16_insn_length (insn
);
13575 if (pool
.first
!= NULL
)
13577 /* If there are no natural barriers between the first user of
13578 the pool and the highest acceptable address, we'll need to
13579 create a new instruction to jump around the constant pool.
13580 In the worst case, this instruction will be 4 bytes long.
13582 If it's too late to do this transformation after INSN,
13583 do it immediately before INSN. */
13584 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
13588 label
= gen_label_rtx ();
13590 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
13591 JUMP_LABEL (jump
) = label
;
13592 LABEL_NUSES (label
) = 1;
13593 barrier
= emit_barrier_after (jump
);
13595 emit_label_after (label
, barrier
);
13596 pool
.insn_address
+= 4;
13599 /* See whether the constant pool is now out of range of the first
13600 user. If so, output the constants after the previous barrier.
13601 Note that any instructions between BARRIER and INSN (inclusive)
13602 will use negative offsets to refer to the pool. */
13603 if (pool
.insn_address
> pool
.highest_address
)
13605 mips16_emit_constants (pool
.first
, barrier
);
13609 else if (BARRIER_P (insn
))
13613 mips16_emit_constants (pool
.first
, get_last_insn ());
13616 /* Return true if it is worth r10k_simplify_address's while replacing
13617 an address with X. We are looking for constants, and for addresses
13618 at a known offset from the incoming stack pointer. */
13621 r10k_simplified_address_p (rtx x
)
13623 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
13625 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
13628 /* X is an expression that appears in INSN. Try to use the UD chains
13629 to simplify it, returning the simplified form on success and the
13630 original form otherwise. Replace the incoming value of $sp with
13631 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13634 r10k_simplify_address (rtx x
, rtx insn
)
13636 rtx newx
, op0
, op1
, set
, def_insn
, note
;
13638 struct df_link
*defs
;
13643 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13644 if (op0
!= XEXP (x
, 0))
13645 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
13646 op0
, GET_MODE (XEXP (x
, 0)));
13648 else if (BINARY_P (x
))
13650 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13651 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
13652 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
13653 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
13655 else if (GET_CODE (x
) == LO_SUM
)
13657 /* LO_SUMs can be offset from HIGHs, if we know they won't
13658 overflow. See mips_classify_address for the rationale behind
13660 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13661 if (GET_CODE (op0
) == HIGH
)
13662 newx
= XEXP (x
, 1);
13664 else if (REG_P (x
))
13666 /* Uses are recorded by regno_reg_rtx, not X itself. */
13667 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
13669 defs
= DF_REF_CHAIN (use
);
13671 /* Require a single definition. */
13672 if (defs
&& defs
->next
== NULL
)
13675 if (DF_REF_IS_ARTIFICIAL (def
))
13677 /* Replace the incoming value of $sp with
13678 virtual_incoming_args_rtx. */
13679 if (x
== stack_pointer_rtx
13680 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
13681 newx
= virtual_incoming_args_rtx
;
13683 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
13686 /* Make sure that DEF_INSN is a single set of REG. */
13687 def_insn
= DF_REF_INSN (def
);
13688 if (NONJUMP_INSN_P (def_insn
))
13690 set
= single_set (def_insn
);
13691 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
13693 /* Prefer to use notes, since the def-use chains
13694 are often shorter. */
13695 note
= find_reg_equal_equiv_note (def_insn
);
13697 newx
= XEXP (note
, 0);
13699 newx
= SET_SRC (set
);
13700 newx
= r10k_simplify_address (newx
, def_insn
);
13706 if (newx
&& r10k_simplified_address_p (newx
))
13711 /* Return true if ADDRESS is known to be an uncached address
13712 on R10K systems. */
13715 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
13717 unsigned HOST_WIDE_INT upper
;
13719 /* Check for KSEG1. */
13720 if (address
+ 0x60000000 < 0x20000000)
13723 /* Check for uncached XKPHYS addresses. */
13724 if (Pmode
== DImode
)
13726 upper
= (address
>> 40) & 0xf9ffff;
13727 if (upper
== 0x900000 || upper
== 0xb80000)
13733 /* Return true if we can prove that an access to address X in instruction
13734 INSN would be safe from R10K speculation. This X is a general
13735 expression; it might not be a legitimate address. */
13738 r10k_safe_address_p (rtx x
, rtx insn
)
13741 HOST_WIDE_INT offset_val
;
13743 x
= r10k_simplify_address (x
, insn
);
13745 /* Check for references to the stack frame. It doesn't really matter
13746 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13747 allows us to assume that accesses to any part of the eventual frame
13748 is safe from speculation at any point in the function. */
13749 mips_split_plus (x
, &base
, &offset_val
);
13750 if (base
== virtual_incoming_args_rtx
13751 && offset_val
>= -cfun
->machine
->frame
.total_size
13752 && offset_val
< cfun
->machine
->frame
.args_size
)
13755 /* Check for uncached addresses. */
13756 if (CONST_INT_P (x
))
13757 return r10k_uncached_address_p (INTVAL (x
));
13759 /* Check for accesses to a static object. */
13760 split_const (x
, &base
, &offset
);
13761 return offset_within_block_p (base
, INTVAL (offset
));
13764 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13765 an in-range access to an automatic variable, or to an object with
13766 a link-time-constant address. */
13769 r10k_safe_mem_expr_p (tree expr
, HOST_WIDE_INT offset
)
13771 if (offset
< 0 || offset
>= int_size_in_bytes (TREE_TYPE (expr
)))
13774 while (TREE_CODE (expr
) == COMPONENT_REF
)
13776 expr
= TREE_OPERAND (expr
, 0);
13777 if (expr
== NULL_TREE
)
13781 return DECL_P (expr
);
13784 /* A for_each_rtx callback for which DATA points to the instruction
13785 containing *X. Stop the search if we find a MEM that is not safe
13786 from R10K speculation. */
13789 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
13798 && MEM_OFFSET_KNOWN_P (mem
)
13799 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
13802 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
13808 /* A note_stores callback for which DATA points to an instruction pointer.
13809 If *DATA is nonnull, make it null if it X contains a MEM that is not
13810 safe from R10K speculation. */
13813 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13818 insn_ptr
= (rtx
*) data
;
13819 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
13820 *insn_ptr
= NULL_RTX
;
13823 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13824 Return nonzero if the call is not to a declared function. */
13827 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13836 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
13842 /* Return true if instruction INSN needs to be protected by an R10K
13846 r10k_needs_protection_p (rtx insn
)
13849 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
13851 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
13853 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
13854 return insn
== NULL_RTX
;
13857 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
13860 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13861 edge is unconditional. */
13864 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
13869 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
13870 if (!single_succ_p (e
->src
)
13871 || !TEST_BIT (protected_bbs
, e
->src
->index
)
13872 || (e
->flags
& EDGE_COMPLEX
) != 0)
13877 /* Implement -mr10k-cache-barrier= for the current function. */
13880 r10k_insert_cache_barriers (void)
13882 int *rev_post_order
;
13885 sbitmap protected_bbs
;
13886 rtx insn
, end
, unprotected_region
;
13890 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
13894 /* Calculate dominators. */
13895 calculate_dominance_info (CDI_DOMINATORS
);
13897 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
13898 X is protected by a cache barrier. */
13899 protected_bbs
= sbitmap_alloc (last_basic_block
);
13900 sbitmap_zero (protected_bbs
);
13902 /* Iterate over the basic blocks in reverse post-order. */
13903 rev_post_order
= XNEWVEC (int, last_basic_block
);
13904 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
13905 for (i
= 0; i
< n
; i
++)
13907 bb
= BASIC_BLOCK (rev_post_order
[i
]);
13909 /* If this block is only reached by unconditional edges, and if the
13910 source of every edge is protected, the beginning of the block is
13912 if (r10k_protected_bb_p (bb
, protected_bbs
))
13913 unprotected_region
= NULL_RTX
;
13915 unprotected_region
= pc_rtx
;
13916 end
= NEXT_INSN (BB_END (bb
));
13918 /* UNPROTECTED_REGION is:
13920 - null if we are processing a protected region,
13921 - pc_rtx if we are processing an unprotected region but have
13922 not yet found the first instruction in it
13923 - the first instruction in an unprotected region otherwise. */
13924 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
13926 if (unprotected_region
&& USEFUL_INSN_P (insn
))
13928 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
13929 /* This CACHE instruction protects the following code. */
13930 unprotected_region
= NULL_RTX
;
13933 /* See if INSN is the first instruction in this
13934 unprotected region. */
13935 if (unprotected_region
== pc_rtx
)
13936 unprotected_region
= insn
;
13938 /* See if INSN needs to be protected. If so,
13939 we must insert a cache barrier somewhere between
13940 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13941 clear which position is better performance-wise,
13942 but as a tie-breaker, we assume that it is better
13943 to allow delay slots to be back-filled where
13944 possible, and that it is better not to insert
13945 barriers in the middle of already-scheduled code.
13946 We therefore insert the barrier at the beginning
13948 if (r10k_needs_protection_p (insn
))
13950 emit_insn_before (gen_r10k_cache_barrier (),
13951 unprotected_region
);
13952 unprotected_region
= NULL_RTX
;
13958 /* The called function is not required to protect the exit path.
13959 The code that follows a call is therefore unprotected. */
13960 unprotected_region
= pc_rtx
;
13963 /* Record whether the end of this block is protected. */
13964 if (unprotected_region
== NULL_RTX
)
13965 SET_BIT (protected_bbs
, bb
->index
);
13967 XDELETEVEC (rev_post_order
);
13969 sbitmap_free (protected_bbs
);
13971 free_dominance_info (CDI_DOMINATORS
);
13974 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
13975 otherwise. If INSN has two call rtx, then store the second one in
13979 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
13984 if (!CALL_P (insn
))
13987 x
= PATTERN (insn
);
13988 if (GET_CODE (x
) == PARALLEL
)
13990 /* Calls returning complex values have two CALL rtx. Look for the second
13991 one here, and return it via the SECOND_CALL arg. */
13992 x2
= XVECEXP (x
, 0, 1);
13993 if (GET_CODE (x2
) == SET
)
13995 if (GET_CODE (x2
) == CALL
)
13998 x
= XVECEXP (x
, 0, 0);
14000 if (GET_CODE (x
) == SET
)
14002 gcc_assert (GET_CODE (x
) == CALL
);
14007 /* REG is set in DEF. See if the definition is one of the ways we load a
14008 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14009 If it is, return the symbol reference of the function, otherwise return
14012 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14013 the values of source registers, otherwise treat such registers as
14014 having an unknown value. */
14017 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
14021 if (DF_REF_IS_ARTIFICIAL (def
))
14024 def_insn
= DF_REF_INSN (def
);
14025 set
= single_set (def_insn
);
14026 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
14028 rtx note
, src
, symbol
;
14030 /* First, look at REG_EQUAL/EQUIV notes. */
14031 note
= find_reg_equal_equiv_note (def_insn
);
14032 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
14033 return XEXP (note
, 0);
14035 /* For %call16 references we don't have REG_EQUAL. */
14036 src
= SET_SRC (set
);
14037 symbol
= mips_strip_unspec_call (src
);
14040 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14044 /* Follow at most one simple register copy. Such copies are
14045 interesting in cases like:
14049 locally_binding_fn (...);
14054 locally_binding_fn (...);
14056 locally_binding_fn (...);
14058 where the load of locally_binding_fn can legitimately be
14059 hoisted or shared. However, we do not expect to see complex
14060 chains of copies, so a full worklist solution to the problem
14061 would probably be overkill. */
14062 if (recurse_p
&& REG_P (src
))
14063 return mips_find_pic_call_symbol (def_insn
, src
, false);
14069 /* Find the definition of the use of REG in INSN. See if the definition
14070 is one of the ways we load a register with a symbol address for a
14071 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14072 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14073 mips_pic_call_symbol_from_set. */
14076 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
14079 struct df_link
*defs
;
14082 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
14085 defs
= DF_REF_CHAIN (use
);
14088 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
14092 /* If we have more than one definition, they need to be identical. */
14093 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
14097 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
14098 if (!rtx_equal_p (symbol
, other
))
14105 /* Replace the args_size operand of the call expression CALL with the
14106 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14109 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
14113 args_size
= XEXP (call
, 1);
14114 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
14115 gen_rtvec (2, args_size
, symbol
),
14119 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14120 if instead of the arg_size argument it contains the call attributes. If
14121 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14122 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14126 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
14128 rtx args_size
, symbol
;
14130 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
14133 args_size
= operands
[args_size_opno
];
14134 if (GET_CODE (args_size
) != UNSPEC
)
14136 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
14138 symbol
= XVECEXP (args_size
, 0, 1);
14139 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14141 operands
[args_size_opno
] = symbol
;
14145 /* Use DF to annotate PIC indirect calls with the function symbol they
14149 mips_annotate_pic_calls (void)
14155 FOR_BB_INSNS (bb
, insn
)
14157 rtx call
, reg
, symbol
, second_call
;
14160 call
= mips_call_expr_from_insn (insn
, &second_call
);
14163 gcc_assert (MEM_P (XEXP (call
, 0)));
14164 reg
= XEXP (XEXP (call
, 0), 0);
14168 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
14171 mips_annotate_pic_call_expr (call
, symbol
);
14173 mips_annotate_pic_call_expr (second_call
, symbol
);
14178 /* A temporary variable used by for_each_rtx callbacks, etc. */
14179 static rtx mips_sim_insn
;
14181 /* A structure representing the state of the processor pipeline.
14182 Used by the mips_sim_* family of functions. */
14184 /* The maximum number of instructions that can be issued in a cycle.
14185 (Caches mips_issue_rate.) */
14186 unsigned int issue_rate
;
14188 /* The current simulation time. */
14191 /* How many more instructions can be issued in the current cycle. */
14192 unsigned int insns_left
;
14194 /* LAST_SET[X].INSN is the last instruction to set register X.
14195 LAST_SET[X].TIME is the time at which that instruction was issued.
14196 INSN is null if no instruction has yet set register X. */
14200 } last_set
[FIRST_PSEUDO_REGISTER
];
14202 /* The pipeline's current DFA state. */
14206 /* Reset STATE to the initial simulation state. */
14209 mips_sim_reset (struct mips_sim
*state
)
14212 state
->insns_left
= state
->issue_rate
;
14213 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
14214 state_reset (state
->dfa_state
);
14217 /* Initialize STATE before its first use. DFA_STATE points to an
14218 allocated but uninitialized DFA state. */
14221 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
14223 state
->issue_rate
= mips_issue_rate ();
14224 state
->dfa_state
= dfa_state
;
14225 mips_sim_reset (state
);
14228 /* Advance STATE by one clock cycle. */
14231 mips_sim_next_cycle (struct mips_sim
*state
)
14234 state
->insns_left
= state
->issue_rate
;
14235 state_transition (state
->dfa_state
, 0);
14238 /* Advance simulation state STATE until instruction INSN can read
14242 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
14244 unsigned int regno
, end_regno
;
14246 end_regno
= END_REGNO (reg
);
14247 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
14248 if (state
->last_set
[regno
].insn
!= 0)
14252 t
= (state
->last_set
[regno
].time
14253 + insn_latency (state
->last_set
[regno
].insn
, insn
));
14254 while (state
->time
< t
)
14255 mips_sim_next_cycle (state
);
14259 /* A for_each_rtx callback. If *X is a register, advance simulation state
14260 DATA until mips_sim_insn can read the register's value. */
14263 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
14266 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
14270 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14273 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
14275 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
14278 /* Advance simulation state STATE until all of INSN's register
14279 dependencies are satisfied. */
14282 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
14284 mips_sim_insn
= insn
;
14285 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
14288 /* Advance simulation state STATE until the units required by
14289 instruction INSN are available. */
14292 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
14296 tmp_state
= alloca (state_size ());
14297 while (state
->insns_left
== 0
14298 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
14299 state_transition (tmp_state
, insn
) >= 0))
14300 mips_sim_next_cycle (state
);
14303 /* Advance simulation state STATE until INSN is ready to issue. */
14306 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
14308 mips_sim_wait_regs (state
, insn
);
14309 mips_sim_wait_units (state
, insn
);
14312 /* mips_sim_insn has just set X. Update the LAST_SET array
14313 in simulation state DATA. */
14316 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
14318 struct mips_sim
*state
;
14320 state
= (struct mips_sim
*) data
;
14323 unsigned int regno
, end_regno
;
14325 end_regno
= END_REGNO (x
);
14326 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
14328 state
->last_set
[regno
].insn
= mips_sim_insn
;
14329 state
->last_set
[regno
].time
= state
->time
;
14334 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14335 can issue immediately (i.e., that mips_sim_wait_insn has already
14339 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
14341 state_transition (state
->dfa_state
, insn
);
14342 state
->insns_left
--;
14344 mips_sim_insn
= insn
;
14345 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
14348 /* Simulate issuing a NOP in state STATE. */
14351 mips_sim_issue_nop (struct mips_sim
*state
)
14353 if (state
->insns_left
== 0)
14354 mips_sim_next_cycle (state
);
14355 state
->insns_left
--;
14358 /* Update simulation state STATE so that it's ready to accept the instruction
14359 after INSN. INSN should be part of the main rtl chain, not a member of a
14363 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
14365 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14367 mips_sim_issue_nop (state
);
14369 switch (GET_CODE (SEQ_BEGIN (insn
)))
14373 /* We can't predict the processor state after a call or label. */
14374 mips_sim_reset (state
);
14378 /* The delay slots of branch likely instructions are only executed
14379 when the branch is taken. Therefore, if the caller has simulated
14380 the delay slot instruction, STATE does not really reflect the state
14381 of the pipeline for the instruction after the delay slot. Also,
14382 branch likely instructions tend to incur a penalty when not taken,
14383 so there will probably be an extra delay between the branch and
14384 the instruction after the delay slot. */
14385 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
14386 mips_sim_reset (state
);
14394 /* The VR4130 pipeline issues aligned pairs of instructions together,
14395 but it stalls the second instruction if it depends on the first.
14396 In order to cut down the amount of logic required, this dependence
14397 check is not based on a full instruction decode. Instead, any non-SPECIAL
14398 instruction is assumed to modify the register specified by bits 20-16
14399 (which is usually the "rt" field).
14401 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14402 input, so we can end up with a false dependence between the branch
14403 and its delay slot. If this situation occurs in instruction INSN,
14404 try to avoid it by swapping rs and rt. */
14407 vr4130_avoid_branch_rt_conflict (rtx insn
)
14411 first
= SEQ_BEGIN (insn
);
14412 second
= SEQ_END (insn
);
14414 && NONJUMP_INSN_P (second
)
14415 && GET_CODE (PATTERN (first
)) == SET
14416 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
14417 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
14419 /* Check for the right kind of condition. */
14420 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
14421 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
14422 && REG_P (XEXP (cond
, 0))
14423 && REG_P (XEXP (cond
, 1))
14424 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
14425 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
14427 /* SECOND mentions the rt register but not the rs register. */
14428 rtx tmp
= XEXP (cond
, 0);
14429 XEXP (cond
, 0) = XEXP (cond
, 1);
14430 XEXP (cond
, 1) = tmp
;
14435 /* Implement -mvr4130-align. Go through each basic block and simulate the
14436 processor pipeline. If we find that a pair of instructions could execute
14437 in parallel, and the first of those instructions is not 8-byte aligned,
14438 insert a nop to make it aligned. */
14441 vr4130_align_insns (void)
14443 struct mips_sim state
;
14444 rtx insn
, subinsn
, last
, last2
, next
;
14449 /* LAST is the last instruction before INSN to have a nonzero length.
14450 LAST2 is the last such instruction before LAST. */
14454 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14457 mips_sim_init (&state
, alloca (state_size ()));
14458 for (insn
= get_insns (); insn
!= 0; insn
= next
)
14460 unsigned int length
;
14462 next
= NEXT_INSN (insn
);
14464 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14465 This isn't really related to the alignment pass, but we do it on
14466 the fly to avoid a separate instruction walk. */
14467 vr4130_avoid_branch_rt_conflict (insn
);
14469 if (USEFUL_INSN_P (insn
))
14470 FOR_EACH_SUBINSN (subinsn
, insn
)
14472 mips_sim_wait_insn (&state
, subinsn
);
14474 /* If we want this instruction to issue in parallel with the
14475 previous one, make sure that the previous instruction is
14476 aligned. There are several reasons why this isn't worthwhile
14477 when the second instruction is a call:
14479 - Calls are less likely to be performance critical,
14480 - There's a good chance that the delay slot can execute
14481 in parallel with the call.
14482 - The return address would then be unaligned.
14484 In general, if we're going to insert a nop between instructions
14485 X and Y, it's better to insert it immediately after X. That
14486 way, if the nop makes Y aligned, it will also align any labels
14487 between X and Y. */
14488 if (state
.insns_left
!= state
.issue_rate
14489 && !CALL_P (subinsn
))
14491 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
14493 /* SUBINSN is the first instruction in INSN and INSN is
14494 aligned. We want to align the previous instruction
14495 instead, so insert a nop between LAST2 and LAST.
14497 Note that LAST could be either a single instruction
14498 or a branch with a delay slot. In the latter case,
14499 LAST, like INSN, is already aligned, but the delay
14500 slot must have some extra delay that stops it from
14501 issuing at the same time as the branch. We therefore
14502 insert a nop before the branch in order to align its
14504 emit_insn_after (gen_nop (), last2
);
14507 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
14509 /* SUBINSN is the delay slot of INSN, but INSN is
14510 currently unaligned. Insert a nop between
14511 LAST and INSN to align it. */
14512 emit_insn_after (gen_nop (), last
);
14516 mips_sim_issue_insn (&state
, subinsn
);
14518 mips_sim_finish_insn (&state
, insn
);
14520 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14521 length
= get_attr_length (insn
);
14524 /* If the instruction is an asm statement or multi-instruction
14525 mips.md patern, the length is only an estimate. Insert an
14526 8 byte alignment after it so that the following instructions
14527 can be handled correctly. */
14528 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
14529 && (recog_memoized (insn
) < 0 || length
>= 8))
14531 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
14532 next
= NEXT_INSN (next
);
14533 mips_sim_next_cycle (&state
);
14536 else if (length
& 4)
14537 aligned_p
= !aligned_p
;
14542 /* See whether INSN is an aligned label. */
14543 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
14549 /* This structure records that the current function has a LO_SUM
14550 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14551 the largest offset applied to BASE by all such LO_SUMs. */
14552 struct mips_lo_sum_offset
{
14554 HOST_WIDE_INT offset
;
14557 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14560 mips_hash_base (rtx base
)
14562 int do_not_record_p
;
14564 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
14567 /* Hash-table callbacks for mips_lo_sum_offsets. */
14570 mips_lo_sum_offset_hash (const void *entry
)
14572 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
14576 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
14578 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
14579 (const_rtx
) value
);
14582 /* Look up symbolic constant X in HTAB, which is a hash table of
14583 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14584 paired with a recorded LO_SUM, otherwise record X in the table. */
14587 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
14591 struct mips_lo_sum_offset
*entry
;
14593 /* Split X into a base and offset. */
14594 split_const (x
, &base
, &offset
);
14595 if (UNSPEC_ADDRESS_P (base
))
14596 base
= UNSPEC_ADDRESS (base
);
14598 /* Look up the base in the hash table. */
14599 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
14603 entry
= (struct mips_lo_sum_offset
*) *slot
;
14604 if (option
== INSERT
)
14608 entry
= XNEW (struct mips_lo_sum_offset
);
14609 entry
->base
= base
;
14610 entry
->offset
= INTVAL (offset
);
14615 if (INTVAL (offset
) > entry
->offset
)
14616 entry
->offset
= INTVAL (offset
);
14619 return INTVAL (offset
) <= entry
->offset
;
14622 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14623 Record every LO_SUM in *LOC. */
14626 mips_record_lo_sum (rtx
*loc
, void *data
)
14628 if (GET_CODE (*loc
) == LO_SUM
)
14629 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
14633 /* Return true if INSN is a SET of an orphaned high-part relocation.
14634 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14635 LO_SUMs in the current function. */
14638 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
14640 enum mips_symbol_type type
;
14643 set
= single_set (insn
);
14646 /* Check for %his. */
14648 if (GET_CODE (x
) == HIGH
14649 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
14650 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
14652 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14653 if (GET_CODE (x
) == UNSPEC
14654 && XINT (x
, 1) == UNSPEC_LOAD_GOT
14655 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
14656 SYMBOL_CONTEXT_LEA
, &type
)
14657 && type
== SYMBOL_GOTOFF_PAGE
)
14658 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
14663 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14664 INSN and a previous instruction, avoid it by inserting nops after
14667 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14668 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14669 before using the value of that register. *HILO_DELAY counts the
14670 number of instructions since the last hilo hazard (that is,
14671 the number of instructions since the last MFLO or MFHI).
14673 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14674 for the next instruction.
14676 LO_REG is an rtx for the LO register, used in dependence checking. */
14679 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
14680 rtx
*delayed_reg
, rtx lo_reg
)
14685 pattern
= PATTERN (insn
);
14687 /* Do not put the whole function in .set noreorder if it contains
14688 an asm statement. We don't know whether there will be hazards
14689 between the asm statement and the gcc-generated code. */
14690 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
14691 cfun
->machine
->all_noreorder_p
= false;
14693 /* Ignore zero-length instructions (barriers and the like). */
14694 ninsns
= get_attr_length (insn
) / 4;
14698 /* Work out how many nops are needed. Note that we only care about
14699 registers that are explicitly mentioned in the instruction's pattern.
14700 It doesn't matter that calls use the argument registers or that they
14701 clobber hi and lo. */
14702 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
14703 nops
= 2 - *hilo_delay
;
14704 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
14709 /* Insert the nops between this instruction and the previous one.
14710 Each new nop takes us further from the last hilo hazard. */
14711 *hilo_delay
+= nops
;
14713 emit_insn_after (gen_hazard_nop (), after
);
14715 /* Set up the state for the next instruction. */
14716 *hilo_delay
+= ninsns
;
14718 if (INSN_CODE (insn
) >= 0)
14719 switch (get_attr_hazard (insn
))
14729 set
= single_set (insn
);
14731 *delayed_reg
= SET_DEST (set
);
14736 /* Go through the instruction stream and insert nops where necessary.
14737 Also delete any high-part relocations whose partnering low parts
14738 are now all dead. See if the whole function can then be put into
14739 .set noreorder and .set nomacro. */
14742 mips_reorg_process_insns (void)
14744 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
14748 /* Force all instructions to be split into their final form. */
14749 split_all_insns_noflow ();
14751 /* Recalculate instruction lengths without taking nops into account. */
14752 cfun
->machine
->ignore_hazard_length_p
= true;
14753 shorten_branches (get_insns ());
14755 cfun
->machine
->all_noreorder_p
= true;
14757 /* We don't track MIPS16 PC-relative offsets closely enough to make
14758 a good job of "set .noreorder" code in MIPS16 mode. */
14760 cfun
->machine
->all_noreorder_p
= false;
14762 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14763 if (!TARGET_EXPLICIT_RELOCS
)
14764 cfun
->machine
->all_noreorder_p
= false;
14766 /* Profiled functions can't be all noreorder because the profiler
14767 support uses assembler macros. */
14769 cfun
->machine
->all_noreorder_p
= false;
14771 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
14772 because we rely on the assembler to work around some errata. */
14773 if (TARGET_FIX_VR4120
|| TARGET_FIX_24K
)
14774 cfun
->machine
->all_noreorder_p
= false;
14776 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14777 MFHI instructions. Note that we avoid using MFLO and MFHI if
14778 the VR4130 MACC and DMACC instructions are available instead;
14779 see the *mfhilo_{si,di}_macc patterns. */
14780 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
14781 cfun
->machine
->all_noreorder_p
= false;
14783 htab
= htab_create (37, mips_lo_sum_offset_hash
,
14784 mips_lo_sum_offset_eq
, free
);
14786 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14787 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
14788 FOR_EACH_SUBINSN (subinsn
, insn
)
14789 if (USEFUL_INSN_P (subinsn
))
14790 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
14795 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
14797 /* Make a second pass over the instructions. Delete orphaned
14798 high-part relocations or turn them into NOPs. Avoid hazards
14799 by inserting NOPs. */
14800 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
14802 next_insn
= NEXT_INSN (insn
);
14803 if (USEFUL_INSN_P (insn
))
14805 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
14807 /* If we find an orphaned high-part relocation in a delay
14808 slot, it's easier to turn that instruction into a NOP than
14809 to delete it. The delay slot will be a NOP either way. */
14810 FOR_EACH_SUBINSN (subinsn
, insn
)
14811 if (INSN_P (subinsn
))
14813 if (mips_orphaned_high_part_p (htab
, subinsn
))
14815 PATTERN (subinsn
) = gen_nop ();
14816 INSN_CODE (subinsn
) = CODE_FOR_nop
;
14818 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
14819 &delayed_reg
, lo_reg
);
14825 /* INSN is a single instruction. Delete it if it's an
14826 orphaned high-part relocation. */
14827 if (mips_orphaned_high_part_p (htab
, insn
))
14828 delete_insn (insn
);
14829 /* Also delete cache barriers if the last instruction
14830 was an annulled branch. INSN will not be speculatively
14832 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
14834 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
14835 delete_insn (insn
);
14838 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
14839 &delayed_reg
, lo_reg
);
14846 htab_delete (htab
);
14849 /* If we are using a GOT, but have not decided to use a global pointer yet,
14850 see whether we need one to implement long branches. Convert the ghost
14851 global-pointer instructions into real ones if so. */
14854 mips_expand_ghost_gp_insns (void)
14859 /* Quick exit if we already know that we will or won't need a
14861 if (!TARGET_USE_GOT
14862 || cfun
->machine
->global_pointer
== INVALID_REGNUM
14863 || mips_must_initialize_gp_p ())
14866 shorten_branches (get_insns ());
14868 /* Look for a branch that is longer than normal. The normal length for
14869 non-MIPS16 branches is 8, because the length includes the delay slot.
14870 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14871 but they have no delay slot. */
14872 normal_length
= (TARGET_MIPS16
? 4 : 8);
14873 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14875 && USEFUL_INSN_P (insn
)
14876 && get_attr_length (insn
) > normal_length
)
14879 if (insn
== NULL_RTX
)
14882 /* We've now established that we need $gp. */
14883 cfun
->machine
->must_initialize_gp_p
= true;
14884 split_all_insns_noflow ();
14889 /* Subroutine of mips_reorg to manage passes that require DF. */
14892 mips_df_reorg (void)
14894 /* Create def-use chains. */
14895 df_set_flags (DF_EQ_NOTES
);
14896 df_chain_add_problem (DF_UD_CHAIN
);
14899 if (TARGET_RELAX_PIC_CALLS
)
14900 mips_annotate_pic_calls ();
14902 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
14903 r10k_insert_cache_barriers ();
14905 df_finish_pass (false);
14908 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
14913 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
14914 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
14915 to date if the CFG is available. */
14916 if (mips_cfg_in_reorg ())
14917 compute_bb_for_insn ();
14918 mips16_lay_out_constants ();
14919 if (mips_cfg_in_reorg ())
14922 free_bb_for_insn ();
14925 if (optimize
> 0 && flag_delayed_branch
)
14926 dbr_schedule (get_insns ());
14927 mips_reorg_process_insns ();
14929 && TARGET_EXPLICIT_RELOCS
14931 && TARGET_VR4130_ALIGN
)
14932 vr4130_align_insns ();
14933 if (mips_expand_ghost_gp_insns ())
14934 /* The expansion could invalidate some of the VR4130 alignment
14935 optimizations, but this should be an extremely rare case anyhow. */
14936 mips_reorg_process_insns ();
14939 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
14940 in order to avoid duplicating too much logic from elsewhere. */
14943 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
14944 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
14947 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
14948 bool use_sibcall_p
;
14950 /* Pretend to be a post-reload pass while generating rtl. */
14951 reload_completed
= 1;
14953 /* Mark the end of the (empty) prologue. */
14954 emit_note (NOTE_INSN_PROLOGUE_END
);
14956 /* Determine if we can use a sibcall to call FUNCTION directly. */
14957 fnaddr
= XEXP (DECL_RTL (function
), 0);
14958 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
14959 && const_call_insn_operand (fnaddr
, Pmode
));
14961 /* Determine if we need to load FNADDR from the GOT. */
14963 && (mips_got_symbol_type_p
14964 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
14966 /* Pick a global pointer. Use a call-clobbered register if
14967 TARGET_CALL_SAVED_GP. */
14968 cfun
->machine
->global_pointer
14969 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
14970 cfun
->machine
->must_initialize_gp_p
= true;
14971 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
14973 /* Set up the global pointer for n32 or n64 abicalls. */
14974 mips_emit_loadgp ();
14977 /* We need two temporary registers in some cases. */
14978 temp1
= gen_rtx_REG (Pmode
, 2);
14979 temp2
= gen_rtx_REG (Pmode
, 3);
14981 /* Find out which register contains the "this" pointer. */
14982 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
14983 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
14985 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
14987 /* Add DELTA to THIS_RTX. */
14990 rtx offset
= GEN_INT (delta
);
14991 if (!SMALL_OPERAND (delta
))
14993 mips_emit_move (temp1
, offset
);
14996 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
14999 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15000 if (vcall_offset
!= 0)
15004 /* Set TEMP1 to *THIS_RTX. */
15005 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
15007 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15008 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
15010 /* Load the offset and add it to THIS_RTX. */
15011 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
15012 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
15015 /* Jump to the target function. Use a sibcall if direct jumps are
15016 allowed, otherwise load the address into a register first. */
15019 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
15020 SIBLING_CALL_P (insn
) = 1;
15024 /* This is messy. GAS treats "la $25,foo" as part of a call
15025 sequence and may allow a global "foo" to be lazily bound.
15026 The general move patterns therefore reject this combination.
15028 In this context, lazy binding would actually be OK
15029 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15030 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15031 We must therefore load the address via a temporary
15032 register if mips_dangerous_for_la25_p.
15034 If we jump to the temporary register rather than $25,
15035 the assembler can use the move insn to fill the jump's
15038 We can use the same technique for MIPS16 code, where $25
15039 is not a valid JR register. */
15040 if (TARGET_USE_PIC_FN_ADDR_REG
15042 && !mips_dangerous_for_la25_p (fnaddr
))
15043 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
15044 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
15046 if (TARGET_USE_PIC_FN_ADDR_REG
15047 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
15048 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
15049 emit_jump_insn (gen_indirect_jump (temp1
));
15052 /* Run just enough of rest_of_compilation. This sequence was
15053 "borrowed" from alpha.c. */
15054 insn
= get_insns ();
15055 insn_locators_alloc ();
15056 split_all_insns_noflow ();
15057 mips16_lay_out_constants ();
15058 shorten_branches (insn
);
15059 final_start_function (insn
, file
, 1);
15060 final (insn
, file
, 1);
15061 final_end_function ();
15063 /* Clean up the vars set above. Note that final_end_function resets
15064 the global pointer for us. */
15065 reload_completed
= 0;
15068 /* The last argument passed to mips_set_mips16_mode, or negative if the
15069 function hasn't been called yet.
15071 There are two copies of this information. One is saved and restored
15072 by the PCH process while the other is specific to this compiler
15073 invocation. The information calculated by mips_set_mips16_mode
15074 is invalid unless the two variables are the same. */
15075 static int was_mips16_p
= -1;
15076 static GTY(()) int was_mips16_pch_p
= -1;
15078 /* Set up the target-dependent global state so that it matches the
15079 current function's ISA mode. */
15082 mips_set_mips16_mode (int mips16_p
)
15084 if (mips16_p
== was_mips16_p
15085 && mips16_p
== was_mips16_pch_p
)
15088 /* Restore base settings of various flags. */
15089 target_flags
= mips_base_target_flags
;
15090 flag_schedule_insns
= mips_base_schedule_insns
;
15091 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
15092 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
15093 align_loops
= mips_base_align_loops
;
15094 align_jumps
= mips_base_align_jumps
;
15095 align_functions
= mips_base_align_functions
;
15099 /* Switch to MIPS16 mode. */
15100 target_flags
|= MASK_MIPS16
;
15102 /* Don't run the scheduler before reload, since it tends to
15103 increase register pressure. */
15104 flag_schedule_insns
= 0;
15106 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15107 the whole function to be in a single section. */
15108 flag_reorder_blocks_and_partition
= 0;
15110 /* Don't move loop invariants, because it tends to increase
15111 register pressure. It also introduces an extra move in cases
15112 where the constant is the first operand in a two-operand binary
15113 instruction, or when it forms a register argument to a functon
15115 flag_move_loop_invariants
= 0;
15117 target_flags
|= MASK_EXPLICIT_RELOCS
;
15119 /* Experiments suggest we get the best overall section-anchor
15120 results from using the range of an unextended LW or SW. Code
15121 that makes heavy use of byte or short accesses can do better
15122 with ranges of 0...31 and 0...63 respectively, but most code is
15123 sensitive to the range of LW and SW instead. */
15124 targetm
.min_anchor_offset
= 0;
15125 targetm
.max_anchor_offset
= 127;
15127 targetm
.const_anchor
= 0;
15129 /* MIPS16 has no BAL instruction. */
15130 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
15132 if (flag_pic
&& !TARGET_OLDABI
)
15133 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15136 sorry ("MIPS16 -mxgot code");
15138 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
15139 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15143 /* Switch to normal (non-MIPS16) mode. */
15144 target_flags
&= ~MASK_MIPS16
;
15146 /* Provide default values for align_* for 64-bit targets. */
15149 if (align_loops
== 0)
15151 if (align_jumps
== 0)
15153 if (align_functions
== 0)
15154 align_functions
= 8;
15157 targetm
.min_anchor_offset
= -32768;
15158 targetm
.max_anchor_offset
= 32767;
15160 targetm
.const_anchor
= 0x8000;
15163 /* (Re)initialize MIPS target internals for new ISA. */
15164 mips_init_relocs ();
15168 if (!mips16_globals
)
15169 mips16_globals
= save_target_globals ();
15171 restore_target_globals (mips16_globals
);
15174 restore_target_globals (&default_target_globals
);
15176 was_mips16_p
= mips16_p
;
15177 was_mips16_pch_p
= mips16_p
;
15180 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15181 function should use the MIPS16 ISA and switch modes accordingly. */
15184 mips_set_current_function (tree fndecl
)
15186 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
15189 /* Allocate a chunk of memory for per-function machine-dependent data. */
15191 static struct machine_function
*
15192 mips_init_machine_status (void)
15194 return ggc_alloc_cleared_machine_function ();
15197 /* Return the processor associated with the given ISA level, or null
15198 if the ISA isn't valid. */
15200 static const struct mips_cpu_info
*
15201 mips_cpu_info_from_isa (int isa
)
15205 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15206 if (mips_cpu_info_table
[i
].isa
== isa
)
15207 return mips_cpu_info_table
+ i
;
15212 /* Return a mips_cpu_info entry determined by an option valued
15215 static const struct mips_cpu_info
*
15216 mips_cpu_info_from_opt (int opt
)
15220 case MIPS_ARCH_OPTION_FROM_ABI
:
15221 /* 'from-abi' selects the most compatible architecture for the
15222 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
15223 ABIs. For the EABIs, we have to decide whether we're using
15224 the 32-bit or 64-bit version. */
15225 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
15226 : ABI_NEEDS_64BIT_REGS
? 3
15227 : (TARGET_64BIT
? 3 : 1));
15229 case MIPS_ARCH_OPTION_NATIVE
:
15230 gcc_unreachable ();
15233 return &mips_cpu_info_table
[opt
];
15237 /* Return a default mips_cpu_info entry, given that no -march= option
15238 was explicitly specified. */
15240 static const struct mips_cpu_info
*
15241 mips_default_arch (void)
15243 #if defined (MIPS_CPU_STRING_DEFAULT)
15245 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15246 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
15247 return mips_cpu_info_table
+ i
;
15248 gcc_unreachable ();
15249 #elif defined (MIPS_ISA_DEFAULT)
15250 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
15252 /* 'from-abi' makes a good default: you get whatever the ABI
15254 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
15258 /* Set up globals to generate code for the ISA or processor
15259 described by INFO. */
15262 mips_set_architecture (const struct mips_cpu_info
*info
)
15266 mips_arch_info
= info
;
15267 mips_arch
= info
->cpu
;
15268 mips_isa
= info
->isa
;
15272 /* Likewise for tuning. */
15275 mips_set_tune (const struct mips_cpu_info
*info
)
15279 mips_tune_info
= info
;
15280 mips_tune
= info
->cpu
;
15284 /* Implement TARGET_OPTION_OVERRIDE. */
15287 mips_option_override (void)
15289 int i
, start
, regno
, mode
;
15291 if (global_options_set
.x_mips_isa_option
)
15292 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
15294 /* Process flags as though we were generating non-MIPS16 code. */
15295 mips_base_mips16
= TARGET_MIPS16
;
15296 target_flags
&= ~MASK_MIPS16
;
15298 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15299 SUBTARGET_OVERRIDE_OPTIONS
;
15302 /* -mno-float overrides -mhard-float and -msoft-float. */
15303 if (TARGET_NO_FLOAT
)
15305 target_flags
|= MASK_SOFT_FLOAT_ABI
;
15306 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
15309 if (TARGET_FLIP_MIPS16
)
15310 TARGET_INTERLINK_MIPS16
= 1;
15312 /* Set the small data limit. */
15313 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
15315 : MIPS_DEFAULT_GVALUE
);
15317 /* The following code determines the architecture and register size.
15318 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15319 The GAS and GCC code should be kept in sync as much as possible. */
15321 if (global_options_set
.x_mips_arch_option
)
15322 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
15324 if (mips_isa_option_info
!= 0)
15326 if (mips_arch_info
== 0)
15327 mips_set_architecture (mips_isa_option_info
);
15328 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
15329 error ("%<-%s%> conflicts with the other architecture options, "
15330 "which specify a %s processor",
15331 mips_isa_option_info
->name
,
15332 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
15335 if (mips_arch_info
== 0)
15336 mips_set_architecture (mips_default_arch ());
15338 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
15339 error ("%<-march=%s%> is not compatible with the selected ABI",
15340 mips_arch_info
->name
);
15342 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15343 if (global_options_set
.x_mips_tune_option
)
15344 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
15346 if (mips_tune_info
== 0)
15347 mips_set_tune (mips_arch_info
);
15349 if ((target_flags_explicit
& MASK_64BIT
) != 0)
15351 /* The user specified the size of the integer registers. Make sure
15352 it agrees with the ABI and ISA. */
15353 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
15354 error ("%<-mgp64%> used with a 32-bit processor");
15355 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
15356 error ("%<-mgp32%> used with a 64-bit ABI");
15357 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
15358 error ("%<-mgp64%> used with a 32-bit ABI");
15362 /* Infer the integer register size from the ABI and processor.
15363 Restrict ourselves to 32-bit registers if that's all the
15364 processor has, or if the ABI cannot handle 64-bit registers. */
15365 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
15366 target_flags
&= ~MASK_64BIT
;
15368 target_flags
|= MASK_64BIT
;
15371 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
15373 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
15374 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15375 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
15376 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15377 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
15379 if (!ISA_HAS_MXHC1
)
15380 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15381 " the target supports the mfhc1 and mthc1 instructions");
15382 else if (mips_abi
!= ABI_32
)
15383 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15389 /* -msingle-float selects 32-bit float registers. Otherwise the
15390 float registers should be the same size as the integer ones. */
15391 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
15392 target_flags
|= MASK_FLOAT64
;
15394 target_flags
&= ~MASK_FLOAT64
;
15397 /* End of code shared with GAS. */
15399 /* If no -mlong* option was given, infer it from the other options. */
15400 if ((target_flags_explicit
& MASK_LONG64
) == 0)
15402 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
15403 target_flags
|= MASK_LONG64
;
15405 target_flags
&= ~MASK_LONG64
;
15408 if (!TARGET_OLDABI
)
15409 flag_pcc_struct_return
= 0;
15411 /* Decide which rtx_costs structure to use. */
15413 mips_cost
= &mips_rtx_cost_optimize_size
;
15415 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
15417 /* If the user hasn't specified a branch cost, use the processor's
15419 if (mips_branch_cost
== 0)
15420 mips_branch_cost
= mips_cost
->branch_cost
;
15422 /* If neither -mbranch-likely nor -mno-branch-likely was given
15423 on the command line, set MASK_BRANCHLIKELY based on the target
15424 architecture and tuning flags. Annulled delay slots are a
15425 size win, so we only consider the processor-specific tuning
15426 for !optimize_size. */
15427 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
15429 if (ISA_HAS_BRANCHLIKELY
15431 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
15432 target_flags
|= MASK_BRANCHLIKELY
;
15434 target_flags
&= ~MASK_BRANCHLIKELY
;
15436 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
15437 warning (0, "the %qs architecture does not support branch-likely"
15438 " instructions", mips_arch_info
->name
);
15440 /* The effect of -mabicalls isn't defined for the EABI. */
15441 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
15443 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15444 target_flags
&= ~MASK_ABICALLS
;
15447 if (TARGET_ABICALLS_PIC2
)
15448 /* We need to set flag_pic for executables as well as DSOs
15449 because we may reference symbols that are not defined in
15450 the final executable. (MIPS does not use things like
15451 copy relocs, for example.)
15453 There is a body of code that uses __PIC__ to distinguish
15454 between -mabicalls and -mno-abicalls code. The non-__PIC__
15455 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15456 long as any indirect jumps use $25. */
15459 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15460 faster code, but at the expense of more nops. Enable it at -O3 and
15462 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
15463 target_flags
|= MASK_VR4130_ALIGN
;
15465 /* Prefer a call to memcpy over inline code when optimizing for size,
15466 though see MOVE_RATIO in mips.h. */
15467 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
15468 target_flags
|= MASK_MEMCPY
;
15470 /* If we have a nonzero small-data limit, check that the -mgpopt
15471 setting is consistent with the other target flags. */
15472 if (mips_small_data_threshold
> 0)
15476 if (!TARGET_EXPLICIT_RELOCS
)
15477 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15479 TARGET_LOCAL_SDATA
= false;
15480 TARGET_EXTERN_SDATA
= false;
15484 if (TARGET_VXWORKS_RTP
)
15485 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15487 if (TARGET_ABICALLS
)
15488 warning (0, "cannot use small-data accesses for %qs",
15493 #ifdef MIPS_TFMODE_FORMAT
15494 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
15497 /* Make sure that the user didn't turn off paired single support when
15498 MIPS-3D support is requested. */
15500 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
15501 && !TARGET_PAIRED_SINGLE_FLOAT
)
15502 error ("%<-mips3d%> requires %<-mpaired-single%>");
15504 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15506 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
15508 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15509 and TARGET_HARD_FLOAT_ABI are both true. */
15510 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
15511 error ("%qs must be used with %qs",
15512 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
15513 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
15515 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15517 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
15518 warning (0, "the %qs architecture does not support paired-single"
15519 " instructions", mips_arch_info
->name
);
15521 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
15522 && !TARGET_CACHE_BUILTIN
)
15524 error ("%qs requires a target that provides the %qs instruction",
15525 "-mr10k-cache-barrier", "cache");
15526 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
15529 /* If TARGET_DSPR2, enable MASK_DSP. */
15531 target_flags
|= MASK_DSP
;
15533 /* .eh_frame addresses should be the same width as a C pointer.
15534 Most MIPS ABIs support only one pointer size, so the assembler
15535 will usually know exactly how big an .eh_frame address is.
15537 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15538 originally defined to use 64-bit pointers (i.e. it is LP64), and
15539 this is still the default mode. However, we also support an n32-like
15540 ILP32 mode, which is selected by -mlong32. The problem is that the
15541 assembler has traditionally not had an -mlong option, so it has
15542 traditionally not known whether we're using the ILP32 or LP64 form.
15544 As it happens, gas versions up to and including 2.19 use _32-bit_
15545 addresses for EABI64 .cfi_* directives. This is wrong for the
15546 default LP64 mode, so we can't use the directives by default.
15547 Moreover, since gas's current behavior is at odds with gcc's
15548 default behavior, it seems unwise to rely on future versions
15549 of gas behaving the same way. We therefore avoid using .cfi
15550 directives for -mlong32 as well. */
15551 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
15552 flag_dwarf2_cfi_asm
= 0;
15554 /* .cfi_* directives generate a read-only section, so fall back on
15555 manual .eh_frame creation if we need the section to be writable. */
15556 if (TARGET_WRITABLE_EH_FRAME
)
15557 flag_dwarf2_cfi_asm
= 0;
15559 mips_init_print_operand_punct ();
15561 /* Set up array to map GCC register number to debug register number.
15562 Ignore the special purpose register numbers. */
15564 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
15566 mips_dbx_regno
[i
] = INVALID_REGNUM
;
15567 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
15568 mips_dwarf_regno
[i
] = i
;
15570 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
15573 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
15574 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
15575 mips_dbx_regno
[i
] = i
+ start
;
15577 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
15578 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
15579 mips_dbx_regno
[i
] = i
+ start
;
15581 /* Accumulator debug registers use big-endian ordering. */
15582 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
15583 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
15584 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
15585 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
15586 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
15588 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
15589 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
15592 /* Set up mips_hard_regno_mode_ok. */
15593 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
15594 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
15595 mips_hard_regno_mode_ok
[mode
][regno
]
15596 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
15598 /* Function to allocate machine-dependent function status. */
15599 init_machine_status
= &mips_init_machine_status
;
15601 /* Default to working around R4000 errata only if the processor
15602 was selected explicitly. */
15603 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
15604 && strcmp (mips_arch_info
->name
, "r4000") == 0)
15605 target_flags
|= MASK_FIX_R4000
;
15607 /* Default to working around R4400 errata only if the processor
15608 was selected explicitly. */
15609 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
15610 && strcmp (mips_arch_info
->name
, "r4400") == 0)
15611 target_flags
|= MASK_FIX_R4400
;
15613 /* Default to working around R10000 errata only if the processor
15614 was selected explicitly. */
15615 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
15616 && strcmp (mips_arch_info
->name
, "r10000") == 0)
15617 target_flags
|= MASK_FIX_R10000
;
15619 /* Make sure that branch-likely instructions available when using
15620 -mfix-r10000. The instructions are not available if either:
15622 1. -mno-branch-likely was passed.
15623 2. The selected ISA does not support branch-likely and
15624 the command line does not include -mbranch-likely. */
15625 if (TARGET_FIX_R10000
15626 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
15627 ? !ISA_HAS_BRANCHLIKELY
15628 : !TARGET_BRANCHLIKELY
))
15629 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15631 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
15633 warning (0, "the %qs architecture does not support the synci "
15634 "instruction", mips_arch_info
->name
);
15635 target_flags
&= ~MASK_SYNCI
;
15638 /* Only optimize PIC indirect calls if they are actually required. */
15639 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
15640 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
15642 /* Save base state of options. */
15643 mips_base_target_flags
= target_flags
;
15644 mips_base_schedule_insns
= flag_schedule_insns
;
15645 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
15646 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
15647 mips_base_align_loops
= align_loops
;
15648 mips_base_align_jumps
= align_jumps
;
15649 mips_base_align_functions
= align_functions
;
15651 /* Now select the ISA mode.
15653 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15654 MIPS16 mode afterwards if need be. */
15655 mips_set_mips16_mode (false);
15658 /* Swap the register information for registers I and I + 1, which
15659 currently have the wrong endianness. Note that the registers'
15660 fixedness and call-clobberedness might have been set on the
15664 mips_swap_registers (unsigned int i
)
15669 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15670 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15672 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
15673 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
15674 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
15675 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
15681 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
15684 mips_conditional_register_usage (void)
15689 /* These DSP control register fields are global. */
15690 global_regs
[CCDSP_PO_REGNUM
] = 1;
15691 global_regs
[CCDSP_SC_REGNUM
] = 1;
15697 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
15698 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15700 if (!TARGET_HARD_FLOAT
)
15704 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
15705 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15706 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
15707 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15709 else if (! ISA_HAS_8CC
)
15713 /* We only have a single condition-code register. We implement
15714 this by fixing all the condition-code registers and generating
15715 RTL that refers directly to ST_REG_FIRST. */
15716 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
15717 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15719 /* In MIPS16 mode, we permit the $t temporary registers to be used
15720 for reload. We prohibit the unused $s registers, since they
15721 are call-saved, and saving them via a MIPS16 register would
15722 probably waste more time than just reloading the value. */
15725 fixed_regs
[18] = call_used_regs
[18] = 1;
15726 fixed_regs
[19] = call_used_regs
[19] = 1;
15727 fixed_regs
[20] = call_used_regs
[20] = 1;
15728 fixed_regs
[21] = call_used_regs
[21] = 1;
15729 fixed_regs
[22] = call_used_regs
[22] = 1;
15730 fixed_regs
[23] = call_used_regs
[23] = 1;
15731 fixed_regs
[26] = call_used_regs
[26] = 1;
15732 fixed_regs
[27] = call_used_regs
[27] = 1;
15733 fixed_regs
[30] = call_used_regs
[30] = 1;
15735 /* $f20-$f23 are call-clobbered for n64. */
15736 if (mips_abi
== ABI_64
)
15739 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
15740 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
15742 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15744 if (mips_abi
== ABI_N32
)
15747 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
15748 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
15750 /* Make sure that double-register accumulator values are correctly
15751 ordered for the current endianness. */
15752 if (TARGET_LITTLE_ENDIAN
)
15754 unsigned int regno
;
15756 mips_swap_registers (MD_REG_FIRST
);
15757 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
15758 mips_swap_registers (regno
);
15762 /* Initialize vector TARGET to VALS. */
15765 mips_expand_vector_init (rtx target
, rtx vals
)
15767 enum machine_mode mode
;
15768 enum machine_mode inner
;
15769 unsigned int i
, n_elts
;
15772 mode
= GET_MODE (target
);
15773 inner
= GET_MODE_INNER (mode
);
15774 n_elts
= GET_MODE_NUNITS (mode
);
15776 gcc_assert (VECTOR_MODE_P (mode
));
15778 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
15779 for (i
= 0; i
< n_elts
; i
++)
15780 emit_move_insn (adjust_address_nv (mem
, inner
, i
* GET_MODE_SIZE (inner
)),
15781 XVECEXP (vals
, 0, i
));
15783 emit_move_insn (target
, mem
);
15786 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15787 other registers for instructions for which it is possible. This
15788 encourages the compiler to use CMP in cases where an XOR would
15789 require some register shuffling. */
15792 mips_order_regs_for_local_alloc (void)
15796 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
15797 reg_alloc_order
[i
] = i
;
15801 /* It really doesn't matter where we put register 0, since it is
15802 a fixed register anyhow. */
15803 reg_alloc_order
[0] = 24;
15804 reg_alloc_order
[24] = 0;
15808 /* Implement EH_USES. */
15811 mips_eh_uses (unsigned int regno
)
15813 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
15815 /* We need to force certain registers to be live in order to handle
15816 PIC long branches correctly. See mips_must_initialize_gp_p for
15818 if (mips_cfun_has_cprestore_slot_p ())
15820 if (regno
== CPRESTORE_SLOT_REGNUM
)
15825 if (cfun
->machine
->global_pointer
== regno
)
15833 /* Implement EPILOGUE_USES. */
15836 mips_epilogue_uses (unsigned int regno
)
15838 /* Say that the epilogue uses the return address register. Note that
15839 in the case of sibcalls, the values "used by the epilogue" are
15840 considered live at the start of the called function. */
15841 if (regno
== RETURN_ADDR_REGNUM
)
15844 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
15845 See the comment above load_call<mode> for details. */
15846 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
15849 /* An interrupt handler must preserve some registers that are
15850 ordinarily call-clobbered. */
15851 if (cfun
->machine
->interrupt_handler_p
15852 && mips_interrupt_extra_call_saved_reg_p (regno
))
15858 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
15861 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
15863 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
15866 /* Return true if INSN needs to be wrapped in ".set noat".
15867 INSN has NOPERANDS operands, stored in OPVEC. */
15870 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
15874 if (recog_memoized (insn
) >= 0)
15875 for (i
= 0; i
< noperands
; i
++)
15876 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
15881 /* Implement FINAL_PRESCAN_INSN. */
15884 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
15886 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
15887 mips_push_asm_switch (&mips_noat
);
15890 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
15893 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
15894 rtx
*opvec
, int noperands
)
15896 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
15897 mips_pop_asm_switch (&mips_noat
);
15900 /* Return the function that is used to expand the <u>mulsidi3 pattern.
15901 EXT_CODE is the code of the extension used. Return NULL if widening
15902 multiplication shouldn't be used. */
15905 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
15909 signed_p
= ext_code
== SIGN_EXTEND
;
15912 /* Don't use widening multiplication with MULT when we have DMUL. Even
15913 with the extension of its input operands DMUL is faster. Note that
15914 the extension is not needed for signed multiplication. In order to
15915 ensure that we always remove the redundant sign-extension in this
15916 case we still expand mulsidi3 for DMUL. */
15918 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
15919 if (TARGET_FIX_R4000
)
15921 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
15925 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
15926 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
15927 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
15931 /* Return the size in bytes of the trampoline code, padded to
15932 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
15933 function address immediately follow. */
15936 mips_trampoline_code_size (void)
15938 if (TARGET_USE_PIC_FN_ADDR_REG
)
15940 else if (ptr_mode
== DImode
)
15942 else if (ISA_HAS_LOAD_DELAY
)
15948 /* Implement TARGET_TRAMPOLINE_INIT. */
15951 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
15953 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
15956 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
15958 /* Work out the offsets of the pointers from the start of the
15959 trampoline code. */
15960 end_addr_offset
= mips_trampoline_code_size ();
15961 static_chain_offset
= end_addr_offset
;
15962 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
15964 /* Get pointers to the beginning and end of the code block. */
15965 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
15966 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
15968 #define OP(X) gen_int_mode (X, SImode)
15970 /* Build up the code in TRAMPOLINE. */
15972 if (TARGET_USE_PIC_FN_ADDR_REG
)
15974 /* $25 contains the address of the trampoline. Emit code of the form:
15976 l[wd] $1, target_function_offset($25)
15977 l[wd] $static_chain, static_chain_offset($25)
15980 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
15981 target_function_offset
,
15982 PIC_FUNCTION_ADDR_REGNUM
));
15983 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
15984 static_chain_offset
,
15985 PIC_FUNCTION_ADDR_REGNUM
));
15986 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
15987 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
15989 else if (ptr_mode
== DImode
)
15991 /* It's too cumbersome to create the full 64-bit address, so let's
15997 1: l[wd] $25, target_function_offset - 12($31)
15998 l[wd] $static_chain, static_chain_offset - 12($31)
16002 where 12 is the offset of "1:" from the start of the code block. */
16003 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
16004 trampoline
[i
++] = OP (MIPS_BAL (1));
16005 trampoline
[i
++] = OP (MIPS_NOP
);
16006 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16007 target_function_offset
- 12,
16008 RETURN_ADDR_REGNUM
));
16009 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16010 static_chain_offset
- 12,
16011 RETURN_ADDR_REGNUM
));
16012 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16013 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
16017 /* If the target has load delays, emit:
16019 lui $1, %hi(end_addr)
16020 lw $25, %lo(end_addr + ...)($1)
16021 lw $static_chain, %lo(end_addr + ...)($1)
16027 lui $1, %hi(end_addr)
16028 lw $25, %lo(end_addr + ...)($1)
16030 lw $static_chain, %lo(end_addr + ...)($1). */
16032 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16033 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16034 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
16035 NULL
, false, OPTAB_WIDEN
);
16036 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
16037 NULL
, false, OPTAB_WIDEN
);
16038 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
16040 /* Emit the LUI. */
16041 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
16042 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
16043 NULL
, false, OPTAB_WIDEN
);
16045 /* Emit the load of the target function. */
16046 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16047 target_function_offset
- end_addr_offset
,
16049 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16050 NULL
, false, OPTAB_WIDEN
);
16052 /* Emit the JR here, if we can. */
16053 if (!ISA_HAS_LOAD_DELAY
)
16054 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16056 /* Emit the load of the static chain register. */
16057 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16058 static_chain_offset
- end_addr_offset
,
16060 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16061 NULL
, false, OPTAB_WIDEN
);
16063 /* Emit the JR, if we couldn't above. */
16064 if (ISA_HAS_LOAD_DELAY
)
16066 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16067 trampoline
[i
++] = OP (MIPS_NOP
);
16073 /* Copy the trampoline code. Leave any padding uninitialized. */
16074 for (j
= 0; j
< i
; j
++)
16076 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
16077 mips_emit_move (mem
, trampoline
[j
]);
16080 /* Set up the static chain pointer field. */
16081 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
16082 mips_emit_move (mem
, chain_value
);
16084 /* Set up the target function field. */
16085 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
16086 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
16088 /* Flush the code part of the trampoline. */
16089 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
16090 emit_insn (gen_clear_cache (addr
, end_addr
));
16093 /* Implement FUNCTION_PROFILER. */
16095 void mips_function_profiler (FILE *file
)
16098 sorry ("mips16 function profiling");
16099 if (TARGET_LONG_CALLS
)
16101 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16102 if (Pmode
== DImode
)
16103 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
16105 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
16107 mips_push_asm_switch (&mips_noat
);
16108 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
16109 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
16110 /* _mcount treats $2 as the static chain register. */
16111 if (cfun
->static_chain_decl
!= NULL
)
16112 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
16113 reg_names
[STATIC_CHAIN_REGNUM
]);
16114 if (TARGET_MCOUNT_RA_ADDRESS
)
16116 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16117 ra save location. */
16118 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
16119 /* ra not saved, pass zero. */
16120 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
16122 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
16123 Pmode
== DImode
? "dla" : "la", reg_names
[12],
16124 cfun
->machine
->frame
.ra_fp_offset
,
16125 reg_names
[STACK_POINTER_REGNUM
]);
16127 if (!TARGET_NEWABI
)
16129 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16130 TARGET_64BIT
? "dsubu" : "subu",
16131 reg_names
[STACK_POINTER_REGNUM
],
16132 reg_names
[STACK_POINTER_REGNUM
],
16133 Pmode
== DImode
? 16 : 8);
16135 if (TARGET_LONG_CALLS
)
16136 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
16138 fprintf (file
, "\tjal\t_mcount\n");
16139 mips_pop_asm_switch (&mips_noat
);
16140 /* _mcount treats $2 as the static chain register. */
16141 if (cfun
->static_chain_decl
!= NULL
)
16142 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
16146 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16147 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16148 when TARGET_LOONGSON_VECTORS is true. */
16150 static unsigned HOST_WIDE_INT
16151 mips_shift_truncation_mask (enum machine_mode mode
)
16153 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
16156 return GET_MODE_BITSIZE (mode
) - 1;
16160 /* Initialize the GCC target structure. */
16161 #undef TARGET_ASM_ALIGNED_HI_OP
16162 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16163 #undef TARGET_ASM_ALIGNED_SI_OP
16164 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16165 #undef TARGET_ASM_ALIGNED_DI_OP
16166 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16168 #undef TARGET_OPTION_OVERRIDE
16169 #define TARGET_OPTION_OVERRIDE mips_option_override
16171 #undef TARGET_LEGITIMIZE_ADDRESS
16172 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16174 #undef TARGET_ASM_FUNCTION_PROLOGUE
16175 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16176 #undef TARGET_ASM_FUNCTION_EPILOGUE
16177 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16178 #undef TARGET_ASM_SELECT_RTX_SECTION
16179 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16180 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16181 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16183 #undef TARGET_SCHED_INIT
16184 #define TARGET_SCHED_INIT mips_sched_init
16185 #undef TARGET_SCHED_REORDER
16186 #define TARGET_SCHED_REORDER mips_sched_reorder
16187 #undef TARGET_SCHED_REORDER2
16188 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
16189 #undef TARGET_SCHED_VARIABLE_ISSUE
16190 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16191 #undef TARGET_SCHED_ADJUST_COST
16192 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16193 #undef TARGET_SCHED_ISSUE_RATE
16194 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16195 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16196 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16197 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16198 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16199 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16200 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16201 mips_multipass_dfa_lookahead
16202 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16203 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16204 mips_small_register_classes_for_mode_p
16206 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16207 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16209 #undef TARGET_INSERT_ATTRIBUTES
16210 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16211 #undef TARGET_MERGE_DECL_ATTRIBUTES
16212 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16213 #undef TARGET_SET_CURRENT_FUNCTION
16214 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16216 #undef TARGET_VALID_POINTER_MODE
16217 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16218 #undef TARGET_REGISTER_MOVE_COST
16219 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16220 #undef TARGET_MEMORY_MOVE_COST
16221 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16222 #undef TARGET_RTX_COSTS
16223 #define TARGET_RTX_COSTS mips_rtx_costs
16224 #undef TARGET_ADDRESS_COST
16225 #define TARGET_ADDRESS_COST mips_address_cost
16227 #undef TARGET_IN_SMALL_DATA_P
16228 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16230 #undef TARGET_MACHINE_DEPENDENT_REORG
16231 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16233 #undef TARGET_PREFERRED_RELOAD_CLASS
16234 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
16236 #undef TARGET_ASM_FILE_START
16237 #define TARGET_ASM_FILE_START mips_file_start
16238 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16239 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16241 #undef TARGET_INIT_LIBFUNCS
16242 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16244 #undef TARGET_BUILD_BUILTIN_VA_LIST
16245 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16246 #undef TARGET_EXPAND_BUILTIN_VA_START
16247 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16248 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16249 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16251 #undef TARGET_PROMOTE_FUNCTION_MODE
16252 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16253 #undef TARGET_PROMOTE_PROTOTYPES
16254 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16256 #undef TARGET_FUNCTION_VALUE
16257 #define TARGET_FUNCTION_VALUE mips_function_value
16258 #undef TARGET_LIBCALL_VALUE
16259 #define TARGET_LIBCALL_VALUE mips_libcall_value
16260 #undef TARGET_FUNCTION_VALUE_REGNO_P
16261 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
16262 #undef TARGET_RETURN_IN_MEMORY
16263 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16264 #undef TARGET_RETURN_IN_MSB
16265 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16267 #undef TARGET_ASM_OUTPUT_MI_THUNK
16268 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16269 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16270 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16272 #undef TARGET_PRINT_OPERAND
16273 #define TARGET_PRINT_OPERAND mips_print_operand
16274 #undef TARGET_PRINT_OPERAND_ADDRESS
16275 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16276 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16277 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16279 #undef TARGET_SETUP_INCOMING_VARARGS
16280 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16281 #undef TARGET_STRICT_ARGUMENT_NAMING
16282 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16283 #undef TARGET_MUST_PASS_IN_STACK
16284 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16285 #undef TARGET_PASS_BY_REFERENCE
16286 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16287 #undef TARGET_CALLEE_COPIES
16288 #define TARGET_CALLEE_COPIES mips_callee_copies
16289 #undef TARGET_ARG_PARTIAL_BYTES
16290 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16291 #undef TARGET_FUNCTION_ARG
16292 #define TARGET_FUNCTION_ARG mips_function_arg
16293 #undef TARGET_FUNCTION_ARG_ADVANCE
16294 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16295 #undef TARGET_FUNCTION_ARG_BOUNDARY
16296 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
16298 #undef TARGET_MODE_REP_EXTENDED
16299 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16301 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16302 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16304 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16305 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16307 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16308 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
16310 #undef TARGET_INIT_BUILTINS
16311 #define TARGET_INIT_BUILTINS mips_init_builtins
16312 #undef TARGET_BUILTIN_DECL
16313 #define TARGET_BUILTIN_DECL mips_builtin_decl
16314 #undef TARGET_EXPAND_BUILTIN
16315 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16317 #undef TARGET_HAVE_TLS
16318 #define TARGET_HAVE_TLS HAVE_AS_TLS
16320 #undef TARGET_CANNOT_FORCE_CONST_MEM
16321 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16323 #undef TARGET_LEGITIMATE_CONSTANT_P
16324 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
16326 #undef TARGET_ENCODE_SECTION_INFO
16327 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16329 #undef TARGET_ATTRIBUTE_TABLE
16330 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16331 /* All our function attributes are related to how out-of-line copies should
16332 be compiled or called. They don't in themselves prevent inlining. */
16333 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16334 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16336 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16337 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16339 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16340 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16341 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16342 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16344 #undef TARGET_COMP_TYPE_ATTRIBUTES
16345 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16347 #ifdef HAVE_AS_DTPRELWORD
16348 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16349 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16351 #undef TARGET_DWARF_REGISTER_SPAN
16352 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16354 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16355 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16357 #undef TARGET_LEGITIMATE_ADDRESS_P
16358 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16360 #undef TARGET_FRAME_POINTER_REQUIRED
16361 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16363 #undef TARGET_CAN_ELIMINATE
16364 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16366 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16367 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
16369 #undef TARGET_TRAMPOLINE_INIT
16370 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16372 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16373 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16375 #undef TARGET_SHIFT_TRUNCATION_MASK
16376 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
16378 struct gcc_target targetm
= TARGET_INITIALIZER
;
16380 #include "gt-mips.h"