1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
40 #include "fold-const.h"
42 #include "stringpool.h"
43 #include "stor-layout.h"
52 #include "insn-codes.h"
60 #include "common/common-target.h"
61 #include "langhooks.h"
66 #include "cfgcleanup.h"
67 #include "sched-int.h"
68 #include "internal-fn.h"
69 #include "gimple-fold.h"
72 #include "diagnostic.h"
73 #include "target-globals.h"
75 #include "tree-pass.h"
81 /* This file should be included last. */
82 #include "target-def.h"
84 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
85 #define UNSPEC_ADDRESS_P(X) \
86 (GET_CODE (X) == UNSPEC \
87 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
88 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
90 /* Extract the symbol or label from UNSPEC wrapper X. */
91 #define UNSPEC_ADDRESS(X) \
94 /* Extract the symbol type from UNSPEC wrapper X. */
95 #define UNSPEC_ADDRESS_TYPE(X) \
96 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
98 /* The maximum distance between the top of the stack frame and the
99 value $sp has when we save and restore registers.
101 The value for normal-mode code must be a SMALL_OPERAND and must
102 preserve the maximum stack alignment. We therefore use a value
103 of 0x7ff0 in this case.
105 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
106 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
108 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
109 up to 0x7f8 bytes and can usually save or restore all the registers
110 that we need to save or restore. (Note that we can only use these
111 instructions for o32, for which the stack alignment is 8 bytes.)
113 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
114 RESTORE are not available. We can then use unextended instructions
115 to save and restore registers, and to allocate and deallocate the top
116 part of the frame. */
117 #define MIPS_MAX_FIRST_STACK_STEP \
118 (!TARGET_COMPRESSION ? 0x7ff0 \
119 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
120 : TARGET_64BIT ? 0x100 : 0x400)
122 /* True if INSN is a mips.md pattern or asm statement. */
123 /* ??? This test exists through the compiler, perhaps it should be
125 #define USEFUL_INSN_P(INSN) \
126 (NONDEBUG_INSN_P (INSN) \
127 && GET_CODE (PATTERN (INSN)) != USE \
128 && GET_CODE (PATTERN (INSN)) != CLOBBER)
130 /* If INSN is a delayed branch sequence, return the first instruction
131 in the sequence, otherwise return INSN itself. */
132 #define SEQ_BEGIN(INSN) \
133 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
134 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
137 /* Likewise for the last instruction in a delayed branch sequence. */
138 #define SEQ_END(INSN) \
139 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
140 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
142 XVECLEN (PATTERN (INSN), 0) - 1)) \
145 /* Execute the following loop body with SUBINSN set to each instruction
146 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
147 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
148 for ((SUBINSN) = SEQ_BEGIN (INSN); \
149 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
150 (SUBINSN) = NEXT_INSN (SUBINSN))
152 /* True if bit BIT is set in VALUE. */
153 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
155 /* Return the opcode for a ptr_mode load of the form:
157 l[wd] DEST, OFFSET(BASE). */
158 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
159 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
164 /* Return the opcode to move register SRC into register DEST. */
165 #define MIPS_MOVE(DEST, SRC) \
166 ((TARGET_64BIT ? 0x2d : 0x21) \
170 /* Return the opcode for:
173 #define MIPS_LUI(DEST, VALUE) \
174 ((0xf << 26) | ((DEST) << 16) | (VALUE))
176 /* Return the opcode to jump to register DEST. When the JR opcode is not
177 available use JALR $0, DEST. */
178 #define MIPS_JR(DEST) \
179 (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9))
181 /* Return the opcode for:
183 bal . + (1 + OFFSET) * 4. */
184 #define MIPS_BAL(OFFSET) \
185 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
187 /* Return the usual opcode for a nop. */
190 /* Classifies an address.
193 A natural register + offset address. The register satisfies
194 mips_valid_base_register_p and the offset is a const_arith_operand.
197 A LO_SUM rtx. The first operand is a valid base register and
198 the second operand is a symbolic address.
201 A signed 16-bit constant address.
204 A constant symbolic address. */
205 enum mips_address_type
{
212 /* Macros to create an enumeration identifier for a function prototype. */
213 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
214 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
215 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
216 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
218 /* Classifies the prototype of a built-in function. */
219 enum mips_function_type
{
220 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
221 #include "config/mips/mips-ftypes.def"
222 #undef DEF_MIPS_FTYPE
226 /* Specifies how a built-in function should be converted into rtl. */
227 enum mips_builtin_type
{
228 /* The function corresponds directly to an .md pattern. The return
229 value is mapped to operand 0 and the arguments are mapped to
230 operands 1 and above. */
233 /* The function corresponds directly to an .md pattern. There is no return
234 value and the arguments are mapped to operands 0 and above. */
235 MIPS_BUILTIN_DIRECT_NO_TARGET
,
237 /* The function corresponds to a comparison instruction followed by
238 a mips_cond_move_tf_ps pattern. The first two arguments are the
239 values to compare and the second two arguments are the vector
240 operands for the movt.ps or movf.ps instruction (in assembly order). */
244 /* The function corresponds to a V2SF comparison instruction. Operand 0
245 of this instruction is the result of the comparison, which has mode
246 CCV2 or CCV4. The function arguments are mapped to operands 1 and
247 above. The function's return value is an SImode boolean that is
248 true under the following conditions:
250 MIPS_BUILTIN_CMP_ANY: one of the registers is true
251 MIPS_BUILTIN_CMP_ALL: all of the registers are true
252 MIPS_BUILTIN_CMP_LOWER: the first register is true
253 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
254 MIPS_BUILTIN_CMP_ANY
,
255 MIPS_BUILTIN_CMP_ALL
,
256 MIPS_BUILTIN_CMP_UPPER
,
257 MIPS_BUILTIN_CMP_LOWER
,
259 /* As above, but the instruction only sets a single $fcc register. */
260 MIPS_BUILTIN_CMP_SINGLE
,
262 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
263 MIPS_BUILTIN_BPOSGE32
266 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
267 #define MIPS_FP_CONDITIONS(MACRO) \
285 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
286 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
287 enum mips_fp_condition
{
288 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
290 #undef DECLARE_MIPS_COND
292 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
293 #define STRINGIFY(X) #X
294 static const char *const mips_fp_conditions
[] = {
295 MIPS_FP_CONDITIONS (STRINGIFY
)
299 /* A class used to control a comdat-style stub that we output in each
300 translation unit that needs it. */
301 class mips_one_only_stub
{
303 virtual ~mips_one_only_stub () {}
305 /* Return the name of the stub. */
306 virtual const char *get_name () = 0;
308 /* Output the body of the function to asm_out_file. */
309 virtual void output_body () = 0;
312 /* Tuning information that is automatically derived from other sources
313 (such as the scheduler). */
315 /* The architecture and tuning settings that this structure describes. */
319 /* True if this structure describes MIPS16 settings. */
322 /* True if the structure has been initialized. */
325 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
326 when optimizing for speed. */
327 bool fast_mult_zero_zero_p
;
330 /* Information about a function's frame layout. */
331 struct GTY(()) mips_frame_info
{
332 /* The size of the frame in bytes. */
333 HOST_WIDE_INT total_size
;
335 /* The number of bytes allocated to variables. */
336 HOST_WIDE_INT var_size
;
338 /* The number of bytes allocated to outgoing function arguments. */
339 HOST_WIDE_INT args_size
;
341 /* The number of bytes allocated to the .cprestore slot, or 0 if there
343 HOST_WIDE_INT cprestore_size
;
345 /* Bit X is set if the function saves or restores GPR X. */
348 /* Likewise FPR X. */
351 /* Likewise doubleword accumulator X ($acX). */
352 unsigned int acc_mask
;
354 /* The number of GPRs, FPRs, doubleword accumulators and COP0
358 unsigned int num_acc
;
359 unsigned int num_cop0_regs
;
361 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
362 save slots from the top of the frame, or zero if no such slots are
364 HOST_WIDE_INT gp_save_offset
;
365 HOST_WIDE_INT fp_save_offset
;
366 HOST_WIDE_INT acc_save_offset
;
367 HOST_WIDE_INT cop0_save_offset
;
369 /* Likewise, but giving offsets from the bottom of the frame. */
370 HOST_WIDE_INT gp_sp_offset
;
371 HOST_WIDE_INT fp_sp_offset
;
372 HOST_WIDE_INT acc_sp_offset
;
373 HOST_WIDE_INT cop0_sp_offset
;
375 /* Similar, but the value passed to _mcount. */
376 HOST_WIDE_INT ra_fp_offset
;
378 /* The offset of arg_pointer_rtx from the bottom of the frame. */
379 HOST_WIDE_INT arg_pointer_offset
;
381 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
382 HOST_WIDE_INT hard_frame_pointer_offset
;
385 struct GTY(()) machine_function
{
386 /* The next floating-point condition-code register to allocate
387 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
388 unsigned int next_fcc
;
390 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
391 rtx mips16_gp_pseudo_rtx
;
393 /* The number of extra stack bytes taken up by register varargs.
394 This area is allocated by the callee at the very top of the frame. */
397 /* The current frame information, calculated by mips_compute_frame_info. */
398 struct mips_frame_info frame
;
400 /* The register to use as the function's global pointer, or INVALID_REGNUM
401 if the function doesn't need one. */
402 unsigned int global_pointer
;
404 /* How many instructions it takes to load a label into $AT, or 0 if
405 this property hasn't yet been calculated. */
406 unsigned int load_label_num_insns
;
408 /* True if mips_adjust_insn_length should ignore an instruction's
410 bool ignore_hazard_length_p
;
412 /* True if the whole function is suitable for .set noreorder and
414 bool all_noreorder_p
;
416 /* True if the function has "inflexible" and "flexible" references
417 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
418 and mips_cfun_has_flexible_gp_ref_p for details. */
419 bool has_inflexible_gp_insn_p
;
420 bool has_flexible_gp_insn_p
;
422 /* True if the function's prologue must load the global pointer
423 value into pic_offset_table_rtx and store the same value in
424 the function's cprestore slot (if any). Even if this value
425 is currently false, we may decide to set it to true later;
426 see mips_must_initialize_gp_p () for details. */
427 bool must_initialize_gp_p
;
429 /* True if the current function must restore $gp after any potential
430 clobber. This value is only meaningful during the first post-epilogue
431 split_insns pass; see mips_must_initialize_gp_p () for details. */
432 bool must_restore_gp_when_clobbered_p
;
434 /* True if this is an interrupt handler. */
435 bool interrupt_handler_p
;
437 /* True if this is an interrupt handler that uses shadow registers. */
438 bool use_shadow_register_set_p
;
440 /* True if this is an interrupt handler that should keep interrupts
442 bool keep_interrupts_masked_p
;
444 /* True if this is an interrupt handler that should use DERET
446 bool use_debug_exception_return_p
;
449 /* Information about a single argument. */
450 struct mips_arg_info
{
451 /* True if the argument is passed in a floating-point register, or
452 would have been if we hadn't run out of registers. */
455 /* The number of words passed in registers, rounded up. */
456 unsigned int reg_words
;
458 /* For EABI, the offset of the first register from GP_ARG_FIRST or
459 FP_ARG_FIRST. For other ABIs, the offset of the first register from
460 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
461 comment for details).
463 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
465 unsigned int reg_offset
;
467 /* The number of words that must be passed on the stack, rounded up. */
468 unsigned int stack_words
;
470 /* The offset from the start of the stack overflow area of the argument's
471 first stack word. Only meaningful when STACK_WORDS is nonzero. */
472 unsigned int stack_offset
;
475 /* Information about an address described by mips_address_type.
481 REG is the base register and OFFSET is the constant offset.
484 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
485 is the type of symbol it references.
488 SYMBOL_TYPE is the type of symbol that the address references. */
489 struct mips_address_info
{
490 enum mips_address_type type
;
493 enum mips_symbol_type symbol_type
;
496 /* One stage in a constant building sequence. These sequences have
500 A = A CODE[1] VALUE[1]
501 A = A CODE[2] VALUE[2]
504 where A is an accumulator, each CODE[i] is a binary rtl operation
505 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
506 struct mips_integer_op
{
508 unsigned HOST_WIDE_INT value
;
511 /* The largest number of operations needed to load an integer constant.
512 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
513 When the lowest bit is clear, we can try, but reject a sequence with
514 an extra SLL at the end. */
515 #define MIPS_MAX_INTEGER_OPS 7
517 /* Information about a MIPS16e SAVE or RESTORE instruction. */
518 struct mips16e_save_restore_info
{
519 /* The number of argument registers saved by a SAVE instruction.
520 0 for RESTORE instructions. */
523 /* Bit X is set if the instruction saves or restores GPR X. */
526 /* The total number of bytes to allocate. */
530 /* Costs of various operations on the different architectures. */
532 struct mips_rtx_cost_data
534 unsigned short fp_add
;
535 unsigned short fp_mult_sf
;
536 unsigned short fp_mult_df
;
537 unsigned short fp_div_sf
;
538 unsigned short fp_div_df
;
539 unsigned short int_mult_si
;
540 unsigned short int_mult_di
;
541 unsigned short int_div_si
;
542 unsigned short int_div_di
;
543 unsigned short branch_cost
;
544 unsigned short memory_latency
;
547 /* Global variables for machine-dependent things. */
549 /* The -G setting, or the configuration's default small-data limit if
550 no -G option is given. */
551 static unsigned int mips_small_data_threshold
;
553 /* The number of file directives written by mips_output_filename. */
554 int num_source_filenames
;
556 /* The name that appeared in the last .file directive written by
557 mips_output_filename, or "" if mips_output_filename hasn't
558 written anything yet. */
559 const char *current_function_file
= "";
561 /* Arrays that map GCC register numbers to debugger register numbers. */
562 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
563 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
565 /* Information about the current function's epilogue, used only while
568 /* A list of queued REG_CFA_RESTORE notes. */
571 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
573 HOST_WIDE_INT cfa_offset
;
575 /* The offset of the CFA from the stack pointer while restoring
577 HOST_WIDE_INT cfa_restore_sp_offset
;
580 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
581 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
582 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
583 struct mips_asm_switch mips_noat
= { "at", 0 };
585 /* True if we're writing out a branch-likely instruction rather than a
587 static bool mips_branch_likely
;
589 /* The current instruction-set architecture. */
590 enum processor mips_arch
;
591 const struct mips_cpu_info
*mips_arch_info
;
593 /* The processor that we should tune the code for. */
594 enum processor mips_tune
;
595 const struct mips_cpu_info
*mips_tune_info
;
597 /* The ISA level associated with mips_arch. */
600 /* The ISA revision level. This is 0 for MIPS I to V and N for
604 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
605 static const struct mips_cpu_info
*mips_isa_option_info
;
607 /* Which cost information to use. */
608 static const struct mips_rtx_cost_data
*mips_cost
;
610 /* The ambient target flags, excluding MASK_MIPS16. */
611 static int mips_base_target_flags
;
613 /* The default compression mode. */
614 unsigned int mips_base_compression_flags
;
616 /* The ambient values of other global variables. */
617 static int mips_base_schedule_insns
; /* flag_schedule_insns */
618 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
619 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
620 static int mips_base_align_loops
; /* align_loops */
621 static int mips_base_align_jumps
; /* align_jumps */
622 static int mips_base_align_functions
; /* align_functions */
624 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
625 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
627 /* Index C is true if character C is a valid PRINT_OPERAND punctation
629 static bool mips_print_operand_punct
[256];
631 static GTY (()) int mips_output_filename_first_time
= 1;
633 /* mips_split_p[X] is true if symbols of type X can be split by
634 mips_split_symbol. */
635 bool mips_split_p
[NUM_SYMBOL_TYPES
];
637 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
638 can be split by mips_split_symbol. */
639 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
641 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
642 forced into a PC-relative constant pool. */
643 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
645 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
646 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
647 if they are matched by a special .md file pattern. */
648 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
650 /* Likewise for HIGHs. */
651 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
653 /* Target state for MIPS16. */
654 struct target_globals
*mips16_globals
;
656 /* Target state for MICROMIPS. */
657 struct target_globals
*micromips_globals
;
659 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
660 and returned from mips_sched_reorder2. */
661 static int cached_can_issue_more
;
663 /* The stubs for various MIPS16 support functions, if used. */
664 static mips_one_only_stub
*mips16_rdhwr_stub
;
665 static mips_one_only_stub
*mips16_get_fcsr_stub
;
666 static mips_one_only_stub
*mips16_set_fcsr_stub
;
668 /* Index R is the smallest register class that contains register R. */
669 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
670 LEA_REGS
, LEA_REGS
, M16_STORE_REGS
, V1_REG
,
671 M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
,
672 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
673 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
674 M16_REGS
, M16_STORE_REGS
, LEA_REGS
, LEA_REGS
,
675 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
676 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
677 LEA_REGS
, M16_SP_REGS
, LEA_REGS
, LEA_REGS
,
679 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
680 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
681 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
682 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
683 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
684 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
685 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
686 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
687 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
688 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
689 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
690 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
691 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
692 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
693 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
694 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
695 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
696 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
697 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
698 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
699 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
700 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
701 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
702 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
703 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
704 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
705 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
706 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
707 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
708 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
709 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
710 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
711 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
712 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
713 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
714 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
715 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
716 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
717 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
720 /* The value of TARGET_ATTRIBUTE_TABLE. */
721 static const struct attribute_spec mips_attribute_table
[] = {
722 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
724 { "long_call", 0, 0, false, true, true, NULL
, false },
725 { "far", 0, 0, false, true, true, NULL
, false },
726 { "near", 0, 0, false, true, true, NULL
, false },
727 /* We would really like to treat "mips16" and "nomips16" as type
728 attributes, but GCC doesn't provide the hooks we need to support
729 the right conversion rules. As declaration attributes, they affect
730 code generation but don't carry other semantics. */
731 { "mips16", 0, 0, true, false, false, NULL
, false },
732 { "nomips16", 0, 0, true, false, false, NULL
, false },
733 { "micromips", 0, 0, true, false, false, NULL
, false },
734 { "nomicromips", 0, 0, true, false, false, NULL
, false },
735 { "nocompression", 0, 0, true, false, false, NULL
, false },
736 /* Allow functions to be specified as interrupt handlers */
737 { "interrupt", 0, 0, false, true, true, NULL
, false },
738 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
739 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
740 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
741 { NULL
, 0, 0, false, false, false, NULL
, false }
744 /* A table describing all the processors GCC knows about; see
745 mips-cpus.def for details. */
746 static const struct mips_cpu_info mips_cpu_info_table
[] = {
747 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
748 { NAME, CPU, ISA, FLAGS },
749 #include "mips-cpus.def"
753 /* Default costs. If these are used for a processor we should look
754 up the actual costs. */
755 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
756 COSTS_N_INSNS (7), /* fp_mult_sf */ \
757 COSTS_N_INSNS (8), /* fp_mult_df */ \
758 COSTS_N_INSNS (23), /* fp_div_sf */ \
759 COSTS_N_INSNS (36), /* fp_div_df */ \
760 COSTS_N_INSNS (10), /* int_mult_si */ \
761 COSTS_N_INSNS (10), /* int_mult_di */ \
762 COSTS_N_INSNS (69), /* int_div_si */ \
763 COSTS_N_INSNS (69), /* int_div_di */ \
764 2, /* branch_cost */ \
765 4 /* memory_latency */
767 /* Floating-point costs for processors without an FPU. Just assume that
768 all floating-point libcalls are very expensive. */
769 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
770 COSTS_N_INSNS (256), /* fp_mult_sf */ \
771 COSTS_N_INSNS (256), /* fp_mult_df */ \
772 COSTS_N_INSNS (256), /* fp_div_sf */ \
773 COSTS_N_INSNS (256) /* fp_div_df */
775 /* Costs to use when optimizing for size. */
776 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
777 COSTS_N_INSNS (1), /* fp_add */
778 COSTS_N_INSNS (1), /* fp_mult_sf */
779 COSTS_N_INSNS (1), /* fp_mult_df */
780 COSTS_N_INSNS (1), /* fp_div_sf */
781 COSTS_N_INSNS (1), /* fp_div_df */
782 COSTS_N_INSNS (1), /* int_mult_si */
783 COSTS_N_INSNS (1), /* int_mult_di */
784 COSTS_N_INSNS (1), /* int_div_si */
785 COSTS_N_INSNS (1), /* int_div_di */
787 4 /* memory_latency */
790 /* Costs to use when optimizing for speed, indexed by processor. */
791 static const struct mips_rtx_cost_data
792 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
794 COSTS_N_INSNS (2), /* fp_add */
795 COSTS_N_INSNS (4), /* fp_mult_sf */
796 COSTS_N_INSNS (5), /* fp_mult_df */
797 COSTS_N_INSNS (12), /* fp_div_sf */
798 COSTS_N_INSNS (19), /* fp_div_df */
799 COSTS_N_INSNS (12), /* int_mult_si */
800 COSTS_N_INSNS (12), /* int_mult_di */
801 COSTS_N_INSNS (35), /* int_div_si */
802 COSTS_N_INSNS (35), /* int_div_di */
804 4 /* memory_latency */
808 COSTS_N_INSNS (6), /* int_mult_si */
809 COSTS_N_INSNS (6), /* int_mult_di */
810 COSTS_N_INSNS (36), /* int_div_si */
811 COSTS_N_INSNS (36), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (36), /* int_mult_si */
818 COSTS_N_INSNS (36), /* int_mult_di */
819 COSTS_N_INSNS (37), /* int_div_si */
820 COSTS_N_INSNS (37), /* int_div_di */
822 4 /* memory_latency */
826 COSTS_N_INSNS (4), /* int_mult_si */
827 COSTS_N_INSNS (11), /* int_mult_di */
828 COSTS_N_INSNS (36), /* int_div_si */
829 COSTS_N_INSNS (68), /* int_div_di */
831 4 /* memory_latency */
834 COSTS_N_INSNS (4), /* fp_add */
835 COSTS_N_INSNS (4), /* fp_mult_sf */
836 COSTS_N_INSNS (5), /* fp_mult_df */
837 COSTS_N_INSNS (17), /* fp_div_sf */
838 COSTS_N_INSNS (32), /* fp_div_df */
839 COSTS_N_INSNS (4), /* int_mult_si */
840 COSTS_N_INSNS (11), /* int_mult_di */
841 COSTS_N_INSNS (36), /* int_div_si */
842 COSTS_N_INSNS (68), /* int_div_di */
844 4 /* memory_latency */
847 COSTS_N_INSNS (4), /* fp_add */
848 COSTS_N_INSNS (4), /* fp_mult_sf */
849 COSTS_N_INSNS (5), /* fp_mult_df */
850 COSTS_N_INSNS (17), /* fp_div_sf */
851 COSTS_N_INSNS (32), /* fp_div_df */
852 COSTS_N_INSNS (4), /* int_mult_si */
853 COSTS_N_INSNS (7), /* int_mult_di */
854 COSTS_N_INSNS (42), /* int_div_si */
855 COSTS_N_INSNS (72), /* int_div_di */
857 4 /* memory_latency */
861 COSTS_N_INSNS (5), /* int_mult_si */
862 COSTS_N_INSNS (5), /* int_mult_di */
863 COSTS_N_INSNS (41), /* int_div_si */
864 COSTS_N_INSNS (41), /* int_div_di */
866 4 /* memory_latency */
869 COSTS_N_INSNS (8), /* fp_add */
870 COSTS_N_INSNS (8), /* fp_mult_sf */
871 COSTS_N_INSNS (10), /* fp_mult_df */
872 COSTS_N_INSNS (34), /* fp_div_sf */
873 COSTS_N_INSNS (64), /* fp_div_df */
874 COSTS_N_INSNS (5), /* int_mult_si */
875 COSTS_N_INSNS (5), /* int_mult_di */
876 COSTS_N_INSNS (41), /* int_div_si */
877 COSTS_N_INSNS (41), /* int_div_di */
879 4 /* memory_latency */
882 COSTS_N_INSNS (4), /* fp_add */
883 COSTS_N_INSNS (4), /* fp_mult_sf */
884 COSTS_N_INSNS (5), /* fp_mult_df */
885 COSTS_N_INSNS (17), /* fp_div_sf */
886 COSTS_N_INSNS (32), /* fp_div_df */
887 COSTS_N_INSNS (5), /* int_mult_si */
888 COSTS_N_INSNS (5), /* int_mult_di */
889 COSTS_N_INSNS (41), /* int_div_si */
890 COSTS_N_INSNS (41), /* int_div_di */
892 4 /* memory_latency */
896 COSTS_N_INSNS (5), /* int_mult_si */
897 COSTS_N_INSNS (5), /* int_mult_di */
898 COSTS_N_INSNS (41), /* int_div_si */
899 COSTS_N_INSNS (41), /* int_div_di */
901 4 /* memory_latency */
904 COSTS_N_INSNS (8), /* fp_add */
905 COSTS_N_INSNS (8), /* fp_mult_sf */
906 COSTS_N_INSNS (10), /* fp_mult_df */
907 COSTS_N_INSNS (34), /* fp_div_sf */
908 COSTS_N_INSNS (64), /* fp_div_df */
909 COSTS_N_INSNS (5), /* int_mult_si */
910 COSTS_N_INSNS (5), /* int_mult_di */
911 COSTS_N_INSNS (41), /* int_div_si */
912 COSTS_N_INSNS (41), /* int_div_di */
914 4 /* memory_latency */
917 COSTS_N_INSNS (4), /* fp_add */
918 COSTS_N_INSNS (4), /* fp_mult_sf */
919 COSTS_N_INSNS (5), /* fp_mult_df */
920 COSTS_N_INSNS (17), /* fp_div_sf */
921 COSTS_N_INSNS (32), /* fp_div_df */
922 COSTS_N_INSNS (5), /* int_mult_si */
923 COSTS_N_INSNS (5), /* int_mult_di */
924 COSTS_N_INSNS (41), /* int_div_si */
925 COSTS_N_INSNS (41), /* int_div_di */
927 4 /* memory_latency */
930 COSTS_N_INSNS (6), /* fp_add */
931 COSTS_N_INSNS (6), /* fp_mult_sf */
932 COSTS_N_INSNS (7), /* fp_mult_df */
933 COSTS_N_INSNS (25), /* fp_div_sf */
934 COSTS_N_INSNS (48), /* fp_div_df */
935 COSTS_N_INSNS (5), /* int_mult_si */
936 COSTS_N_INSNS (5), /* int_mult_di */
937 COSTS_N_INSNS (41), /* int_div_si */
938 COSTS_N_INSNS (41), /* int_div_di */
940 4 /* memory_latency */
957 COSTS_N_INSNS (5), /* int_mult_si */
958 COSTS_N_INSNS (5), /* int_mult_di */
959 COSTS_N_INSNS (72), /* int_div_si */
960 COSTS_N_INSNS (72), /* int_div_di */
962 4 /* memory_latency */
967 COSTS_N_INSNS (6), /* int_mult_si */
968 COSTS_N_INSNS (6), /* int_mult_di */
969 COSTS_N_INSNS (18), /* int_div_si */
970 COSTS_N_INSNS (35), /* int_div_di */
972 4 /* memory_latency */
976 COSTS_N_INSNS (6), /* fp_add */
977 COSTS_N_INSNS (6), /* fp_mult_sf */
978 COSTS_N_INSNS (7), /* fp_mult_df */
979 COSTS_N_INSNS (25), /* fp_div_sf */
980 COSTS_N_INSNS (48), /* fp_div_df */
981 COSTS_N_INSNS (6), /* int_mult_si */
982 COSTS_N_INSNS (6), /* int_mult_di */
983 COSTS_N_INSNS (18), /* int_div_si */
984 COSTS_N_INSNS (35), /* int_div_di */
986 4 /* memory_latency */
989 COSTS_N_INSNS (2), /* fp_add */
990 COSTS_N_INSNS (4), /* fp_mult_sf */
991 COSTS_N_INSNS (5), /* fp_mult_df */
992 COSTS_N_INSNS (12), /* fp_div_sf */
993 COSTS_N_INSNS (19), /* fp_div_df */
994 COSTS_N_INSNS (2), /* int_mult_si */
995 COSTS_N_INSNS (2), /* int_mult_di */
996 COSTS_N_INSNS (35), /* int_div_si */
997 COSTS_N_INSNS (35), /* int_div_di */
999 4 /* memory_latency */
1002 COSTS_N_INSNS (3), /* fp_add */
1003 COSTS_N_INSNS (5), /* fp_mult_sf */
1004 COSTS_N_INSNS (6), /* fp_mult_df */
1005 COSTS_N_INSNS (15), /* fp_div_sf */
1006 COSTS_N_INSNS (16), /* fp_div_df */
1007 COSTS_N_INSNS (17), /* int_mult_si */
1008 COSTS_N_INSNS (17), /* int_mult_di */
1009 COSTS_N_INSNS (38), /* int_div_si */
1010 COSTS_N_INSNS (38), /* int_div_di */
1011 2, /* branch_cost */
1012 6 /* memory_latency */
1015 COSTS_N_INSNS (6), /* fp_add */
1016 COSTS_N_INSNS (7), /* fp_mult_sf */
1017 COSTS_N_INSNS (8), /* fp_mult_df */
1018 COSTS_N_INSNS (23), /* fp_div_sf */
1019 COSTS_N_INSNS (36), /* fp_div_df */
1020 COSTS_N_INSNS (10), /* int_mult_si */
1021 COSTS_N_INSNS (10), /* int_mult_di */
1022 COSTS_N_INSNS (69), /* int_div_si */
1023 COSTS_N_INSNS (69), /* int_div_di */
1024 2, /* branch_cost */
1025 6 /* memory_latency */
1037 /* The only costs that appear to be updated here are
1038 integer multiplication. */
1040 COSTS_N_INSNS (4), /* int_mult_si */
1041 COSTS_N_INSNS (6), /* int_mult_di */
1042 COSTS_N_INSNS (69), /* int_div_si */
1043 COSTS_N_INSNS (69), /* int_div_di */
1044 1, /* branch_cost */
1045 4 /* memory_latency */
1060 COSTS_N_INSNS (6), /* fp_add */
1061 COSTS_N_INSNS (4), /* fp_mult_sf */
1062 COSTS_N_INSNS (5), /* fp_mult_df */
1063 COSTS_N_INSNS (23), /* fp_div_sf */
1064 COSTS_N_INSNS (36), /* fp_div_df */
1065 COSTS_N_INSNS (5), /* int_mult_si */
1066 COSTS_N_INSNS (5), /* int_mult_di */
1067 COSTS_N_INSNS (36), /* int_div_si */
1068 COSTS_N_INSNS (36), /* int_div_di */
1069 1, /* branch_cost */
1070 4 /* memory_latency */
1073 COSTS_N_INSNS (6), /* fp_add */
1074 COSTS_N_INSNS (5), /* fp_mult_sf */
1075 COSTS_N_INSNS (6), /* fp_mult_df */
1076 COSTS_N_INSNS (30), /* fp_div_sf */
1077 COSTS_N_INSNS (59), /* fp_div_df */
1078 COSTS_N_INSNS (3), /* int_mult_si */
1079 COSTS_N_INSNS (4), /* int_mult_di */
1080 COSTS_N_INSNS (42), /* int_div_si */
1081 COSTS_N_INSNS (74), /* int_div_di */
1082 1, /* branch_cost */
1083 4 /* memory_latency */
1086 COSTS_N_INSNS (6), /* fp_add */
1087 COSTS_N_INSNS (5), /* fp_mult_sf */
1088 COSTS_N_INSNS (6), /* fp_mult_df */
1089 COSTS_N_INSNS (30), /* fp_div_sf */
1090 COSTS_N_INSNS (59), /* fp_div_df */
1091 COSTS_N_INSNS (5), /* int_mult_si */
1092 COSTS_N_INSNS (9), /* int_mult_di */
1093 COSTS_N_INSNS (42), /* int_div_si */
1094 COSTS_N_INSNS (74), /* int_div_di */
1095 1, /* branch_cost */
1096 4 /* memory_latency */
1099 COSTS_N_INSNS (4), /* fp_add */
1100 COSTS_N_INSNS (4), /* fp_mult_sf */
1101 COSTS_N_INSNS (256), /* fp_mult_df */
1102 COSTS_N_INSNS (8), /* fp_div_sf */
1103 COSTS_N_INSNS (256), /* fp_div_df */
1104 COSTS_N_INSNS (4), /* int_mult_si */
1105 COSTS_N_INSNS (256), /* int_mult_di */
1106 COSTS_N_INSNS (37), /* int_div_si */
1107 COSTS_N_INSNS (256), /* int_div_di */
1108 1, /* branch_cost */
1109 4 /* memory_latency */
1112 /* The only costs that are changed here are
1113 integer multiplication. */
1114 COSTS_N_INSNS (6), /* fp_add */
1115 COSTS_N_INSNS (7), /* fp_mult_sf */
1116 COSTS_N_INSNS (8), /* fp_mult_df */
1117 COSTS_N_INSNS (23), /* fp_div_sf */
1118 COSTS_N_INSNS (36), /* fp_div_df */
1119 COSTS_N_INSNS (5), /* int_mult_si */
1120 COSTS_N_INSNS (9), /* int_mult_di */
1121 COSTS_N_INSNS (69), /* int_div_si */
1122 COSTS_N_INSNS (69), /* int_div_di */
1123 1, /* branch_cost */
1124 4 /* memory_latency */
1130 /* The only costs that are changed here are
1131 integer multiplication. */
1132 COSTS_N_INSNS (6), /* fp_add */
1133 COSTS_N_INSNS (7), /* fp_mult_sf */
1134 COSTS_N_INSNS (8), /* fp_mult_df */
1135 COSTS_N_INSNS (23), /* fp_div_sf */
1136 COSTS_N_INSNS (36), /* fp_div_df */
1137 COSTS_N_INSNS (3), /* int_mult_si */
1138 COSTS_N_INSNS (8), /* int_mult_di */
1139 COSTS_N_INSNS (69), /* int_div_si */
1140 COSTS_N_INSNS (69), /* int_div_di */
1141 1, /* branch_cost */
1142 4 /* memory_latency */
1145 COSTS_N_INSNS (2), /* fp_add */
1146 COSTS_N_INSNS (2), /* fp_mult_sf */
1147 COSTS_N_INSNS (2), /* fp_mult_df */
1148 COSTS_N_INSNS (12), /* fp_div_sf */
1149 COSTS_N_INSNS (19), /* fp_div_df */
1150 COSTS_N_INSNS (5), /* int_mult_si */
1151 COSTS_N_INSNS (9), /* int_mult_di */
1152 COSTS_N_INSNS (34), /* int_div_si */
1153 COSTS_N_INSNS (66), /* int_div_di */
1154 1, /* branch_cost */
1155 4 /* memory_latency */
1158 /* These costs are the same as the SB-1A below. */
1159 COSTS_N_INSNS (4), /* fp_add */
1160 COSTS_N_INSNS (4), /* fp_mult_sf */
1161 COSTS_N_INSNS (4), /* fp_mult_df */
1162 COSTS_N_INSNS (24), /* fp_div_sf */
1163 COSTS_N_INSNS (32), /* fp_div_df */
1164 COSTS_N_INSNS (3), /* int_mult_si */
1165 COSTS_N_INSNS (4), /* int_mult_di */
1166 COSTS_N_INSNS (36), /* int_div_si */
1167 COSTS_N_INSNS (68), /* int_div_di */
1168 1, /* branch_cost */
1169 4 /* memory_latency */
1172 /* These costs are the same as the SB-1 above. */
1173 COSTS_N_INSNS (4), /* fp_add */
1174 COSTS_N_INSNS (4), /* fp_mult_sf */
1175 COSTS_N_INSNS (4), /* fp_mult_df */
1176 COSTS_N_INSNS (24), /* fp_div_sf */
1177 COSTS_N_INSNS (32), /* fp_div_df */
1178 COSTS_N_INSNS (3), /* int_mult_si */
1179 COSTS_N_INSNS (4), /* int_mult_di */
1180 COSTS_N_INSNS (36), /* int_div_si */
1181 COSTS_N_INSNS (68), /* int_div_di */
1182 1, /* branch_cost */
1183 4 /* memory_latency */
1190 COSTS_N_INSNS (8), /* int_mult_si */
1191 COSTS_N_INSNS (8), /* int_mult_di */
1192 COSTS_N_INSNS (72), /* int_div_si */
1193 COSTS_N_INSNS (72), /* int_div_di */
1194 1, /* branch_cost */
1195 4 /* memory_latency */
1198 /* These costs are the same as 5KF above. */
1199 COSTS_N_INSNS (4), /* fp_add */
1200 COSTS_N_INSNS (4), /* fp_mult_sf */
1201 COSTS_N_INSNS (5), /* fp_mult_df */
1202 COSTS_N_INSNS (17), /* fp_div_sf */
1203 COSTS_N_INSNS (32), /* fp_div_df */
1204 COSTS_N_INSNS (4), /* int_mult_si */
1205 COSTS_N_INSNS (11), /* int_mult_di */
1206 COSTS_N_INSNS (36), /* int_div_si */
1207 COSTS_N_INSNS (68), /* int_div_di */
1208 1, /* branch_cost */
1209 4 /* memory_latency */
1212 COSTS_N_INSNS (4), /* fp_add */
1213 COSTS_N_INSNS (5), /* fp_mult_sf */
1214 COSTS_N_INSNS (5), /* fp_mult_df */
1215 COSTS_N_INSNS (17), /* fp_div_sf */
1216 COSTS_N_INSNS (17), /* fp_div_df */
1217 COSTS_N_INSNS (5), /* int_mult_si */
1218 COSTS_N_INSNS (5), /* int_mult_di */
1219 COSTS_N_INSNS (8), /* int_div_si */
1220 COSTS_N_INSNS (8), /* int_div_di */
1221 2, /* branch_cost */
1222 4 /* memory_latency */
1225 COSTS_N_INSNS (4), /* fp_add */
1226 COSTS_N_INSNS (4), /* fp_mult_sf */
1227 COSTS_N_INSNS (5), /* fp_mult_df */
1228 COSTS_N_INSNS (17), /* fp_div_sf */
1229 COSTS_N_INSNS (32), /* fp_div_df */
1230 COSTS_N_INSNS (5), /* int_mult_si */
1231 COSTS_N_INSNS (5), /* int_mult_di */
1232 COSTS_N_INSNS (41), /* int_div_si */
1233 COSTS_N_INSNS (41), /* int_div_di */
1234 1, /* branch_cost */
1235 4 /* memory_latency */
1238 COSTS_N_INSNS (4), /* fp_add */
1239 COSTS_N_INSNS (4), /* fp_mult_sf */
1240 COSTS_N_INSNS (5), /* fp_mult_df */
1241 COSTS_N_INSNS (17), /* fp_div_sf */
1242 COSTS_N_INSNS (32), /* fp_div_df */
1243 COSTS_N_INSNS (5), /* int_mult_si */
1244 COSTS_N_INSNS (5), /* int_mult_di */
1245 COSTS_N_INSNS (41), /* int_div_si */
1246 COSTS_N_INSNS (41), /* int_div_di */
1247 1, /* branch_cost */
1248 4 /* memory_latency */
1252 static rtx
mips_find_pic_call_symbol (rtx_insn
*, rtx
, bool);
1253 static int mips_register_move_cost (machine_mode
, reg_class_t
,
1255 static unsigned int mips_function_arg_boundary (machine_mode
, const_tree
);
1256 static machine_mode
mips_get_reg_raw_mode (int regno
);
1258 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1259 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1260 static GTY (()) hash_map
<nofree_string_hash
, bool> *mflip_mips16_htab
;
1262 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1263 mode, false if it should next add an attribute for the opposite mode. */
1264 static GTY(()) bool mips16_flipper
;
1266 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1267 for -mflip-mips16. Return true if it should use "mips16" and false if
1268 it should use "nomips16". */
1271 mflip_mips16_use_mips16_p (tree decl
)
1274 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1276 /* Use the opposite of the command-line setting for anonymous decls. */
1277 if (!DECL_NAME (decl
))
1278 return !base_is_mips16
;
1280 if (!mflip_mips16_htab
)
1281 mflip_mips16_htab
= hash_map
<nofree_string_hash
, bool>::create_ggc (37);
1283 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1286 bool *slot
= &mflip_mips16_htab
->get_or_insert (name
, &existed
);
1289 mips16_flipper
= !mips16_flipper
;
1290 *slot
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1295 /* Predicates to test for presence of "near" and "far"/"long_call"
1296 attributes on the given TYPE. */
1299 mips_near_type_p (const_tree type
)
1301 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1305 mips_far_type_p (const_tree type
)
1307 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1308 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1312 /* Check if the interrupt attribute is set for a function. */
1315 mips_interrupt_type_p (tree type
)
1317 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1320 /* Check if the attribute to use shadow register set is set for a function. */
1323 mips_use_shadow_register_set_p (tree type
)
1325 return lookup_attribute ("use_shadow_register_set",
1326 TYPE_ATTRIBUTES (type
)) != NULL
;
1329 /* Check if the attribute to keep interrupts masked is set for a function. */
1332 mips_keep_interrupts_masked_p (tree type
)
1334 return lookup_attribute ("keep_interrupts_masked",
1335 TYPE_ATTRIBUTES (type
)) != NULL
;
1338 /* Check if the attribute to use debug exception return is set for
1342 mips_use_debug_exception_return_p (tree type
)
1344 return lookup_attribute ("use_debug_exception_return",
1345 TYPE_ATTRIBUTES (type
)) != NULL
;
1348 /* Return the set of compression modes that are explicitly required
1349 by the attributes in ATTRIBUTES. */
1352 mips_get_compress_on_flags (tree attributes
)
1354 unsigned int flags
= 0;
1356 if (lookup_attribute ("mips16", attributes
) != NULL
)
1357 flags
|= MASK_MIPS16
;
1359 if (lookup_attribute ("micromips", attributes
) != NULL
)
1360 flags
|= MASK_MICROMIPS
;
1365 /* Return the set of compression modes that are explicitly forbidden
1366 by the attributes in ATTRIBUTES. */
1369 mips_get_compress_off_flags (tree attributes
)
1371 unsigned int flags
= 0;
1373 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1374 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1376 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1377 flags
|= MASK_MIPS16
;
1379 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1380 flags
|= MASK_MICROMIPS
;
1385 /* Return the compression mode that should be used for function DECL.
1386 Return the ambient setting if DECL is null. */
1389 mips_get_compress_mode (tree decl
)
1391 unsigned int flags
, force_on
;
1393 flags
= mips_base_compression_flags
;
1396 /* Nested functions must use the same frame pointer as their
1397 parent and must therefore use the same ISA mode. */
1398 tree parent
= decl_function_context (decl
);
1401 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1404 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1409 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1413 mips_get_compress_on_name (unsigned int flags
)
1415 if (flags
== MASK_MIPS16
)
1420 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1424 mips_get_compress_off_name (unsigned int flags
)
1426 if (flags
== MASK_MIPS16
)
1428 if (flags
== MASK_MICROMIPS
)
1429 return "nomicromips";
1430 return "nocompression";
1433 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1436 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1438 /* Disallow mixed near/far attributes. */
1439 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1441 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1446 /* Implement TARGET_INSERT_ATTRIBUTES. */
1449 mips_insert_attributes (tree decl
, tree
*attributes
)
1452 unsigned int compression_flags
, nocompression_flags
;
1454 /* Check for "mips16" and "nomips16" attributes. */
1455 compression_flags
= mips_get_compress_on_flags (*attributes
);
1456 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1458 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1460 if (nocompression_flags
)
1461 error ("%qs attribute only applies to functions",
1462 mips_get_compress_off_name (nocompression_flags
));
1464 if (compression_flags
)
1465 error ("%qs attribute only applies to functions",
1466 mips_get_compress_on_name (nocompression_flags
));
1470 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1471 nocompression_flags
|=
1472 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1474 if (compression_flags
&& nocompression_flags
)
1475 error ("%qE cannot have both %qs and %qs attributes",
1476 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1477 mips_get_compress_off_name (nocompression_flags
));
1479 if (compression_flags
& MASK_MIPS16
1480 && compression_flags
& MASK_MICROMIPS
)
1481 error ("%qE cannot have both %qs and %qs attributes",
1482 DECL_NAME (decl
), "mips16", "micromips");
1484 if (TARGET_FLIP_MIPS16
1485 && !DECL_ARTIFICIAL (decl
)
1486 && compression_flags
== 0
1487 && nocompression_flags
== 0)
1489 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1490 "mips16" attribute, arbitrarily pick one. We must pick the same
1491 setting for duplicate declarations of a function. */
1492 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1493 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1494 name
= "nomicromips";
1495 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1500 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1503 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1507 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1508 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1510 error ("%qE redeclared with conflicting %qs attributes",
1511 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1513 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1514 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1516 error ("%qE redeclared with conflicting %qs attributes",
1517 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1519 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1520 DECL_ATTRIBUTES (newdecl
));
1523 /* Implement TARGET_CAN_INLINE_P. */
1526 mips_can_inline_p (tree caller
, tree callee
)
1528 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1530 return default_target_can_inline_p (caller
, callee
);
1533 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1534 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1537 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1539 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1541 *base_ptr
= XEXP (x
, 0);
1542 *offset_ptr
= INTVAL (XEXP (x
, 1));
1551 static unsigned int mips_build_integer (struct mips_integer_op
*,
1552 unsigned HOST_WIDE_INT
);
1554 /* A subroutine of mips_build_integer, with the same interface.
1555 Assume that the final action in the sequence should be a left shift. */
1558 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1560 unsigned int i
, shift
;
1562 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1563 since signed numbers are easier to load than unsigned ones. */
1565 while ((value
& 1) == 0)
1566 value
/= 2, shift
++;
1568 i
= mips_build_integer (codes
, value
);
1569 codes
[i
].code
= ASHIFT
;
1570 codes
[i
].value
= shift
;
1574 /* As for mips_build_shift, but assume that the final action will be
1575 an IOR or PLUS operation. */
1578 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1580 unsigned HOST_WIDE_INT high
;
1583 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1584 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1586 /* The constant is too complex to load with a simple LUI/ORI pair,
1587 so we want to give the recursive call as many trailing zeros as
1588 possible. In this case, we know bit 16 is set and that the
1589 low 16 bits form a negative number. If we subtract that number
1590 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1591 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1592 codes
[i
].code
= PLUS
;
1593 codes
[i
].value
= CONST_LOW_PART (value
);
1597 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1598 bits gives a value with at least 17 trailing zeros. */
1599 i
= mips_build_integer (codes
, high
);
1600 codes
[i
].code
= IOR
;
1601 codes
[i
].value
= value
& 0xffff;
1606 /* Fill CODES with a sequence of rtl operations to load VALUE.
1607 Return the number of operations needed. */
1610 mips_build_integer (struct mips_integer_op
*codes
,
1611 unsigned HOST_WIDE_INT value
)
1613 if (SMALL_OPERAND (value
)
1614 || SMALL_OPERAND_UNSIGNED (value
)
1615 || LUI_OPERAND (value
))
1617 /* The value can be loaded with a single instruction. */
1618 codes
[0].code
= UNKNOWN
;
1619 codes
[0].value
= value
;
1622 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1624 /* Either the constant is a simple LUI/ORI combination or its
1625 lowest bit is set. We don't want to shift in this case. */
1626 return mips_build_lower (codes
, value
);
1628 else if ((value
& 0xffff) == 0)
1630 /* The constant will need at least three actions. The lowest
1631 16 bits are clear, so the final action will be a shift. */
1632 return mips_build_shift (codes
, value
);
1636 /* The final action could be a shift, add or inclusive OR.
1637 Rather than use a complex condition to select the best
1638 approach, try both mips_build_shift and mips_build_lower
1639 and pick the one that gives the shortest sequence.
1640 Note that this case is only used once per constant. */
1641 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1642 unsigned int cost
, alt_cost
;
1644 cost
= mips_build_shift (codes
, value
);
1645 alt_cost
= mips_build_lower (alt_codes
, value
);
1646 if (alt_cost
< cost
)
1648 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1655 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1658 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1660 return mips_const_insns (x
) > 0;
1663 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1666 mips16_stub_function (const char *name
)
1670 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1671 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1675 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1676 support function. */
1679 mips16_stub_call_address (mips_one_only_stub
*stub
)
1681 rtx fn
= mips16_stub_function (stub
->get_name ());
1682 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1683 if (!call_insn_operand (fn
, VOIDmode
))
1684 fn
= force_reg (Pmode
, fn
);
1688 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1690 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1692 virtual const char *get_name ();
1693 virtual void output_body ();
1697 mips16_rdhwr_one_only_stub::get_name ()
1699 return "__mips16_rdhwr";
1703 mips16_rdhwr_one_only_stub::output_body ()
1705 fprintf (asm_out_file
,
1707 "\t.set\tmips32r2\n"
1708 "\t.set\tnoreorder\n"
1714 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1715 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1717 virtual const char *get_name ();
1718 virtual void output_body ();
1722 mips16_get_fcsr_one_only_stub::get_name ()
1724 return "__mips16_get_fcsr";
1728 mips16_get_fcsr_one_only_stub::output_body ()
1730 fprintf (asm_out_file
,
1732 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1735 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1736 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1738 virtual const char *get_name ();
1739 virtual void output_body ();
1743 mips16_set_fcsr_one_only_stub::get_name ()
1745 return "__mips16_set_fcsr";
1749 mips16_set_fcsr_one_only_stub::output_body ()
1751 fprintf (asm_out_file
,
1753 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1756 /* Return true if symbols of type TYPE require a GOT access. */
1759 mips_got_symbol_type_p (enum mips_symbol_type type
)
1763 case SYMBOL_GOT_PAGE_OFST
:
1764 case SYMBOL_GOT_DISP
:
1772 /* Return true if X is a thread-local symbol. */
1775 mips_tls_symbol_p (rtx x
)
1777 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1780 /* Return true if SYMBOL_REF X is associated with a global symbol
1781 (in the STB_GLOBAL sense). */
1784 mips_global_symbol_p (const_rtx x
)
1786 const_tree decl
= SYMBOL_REF_DECL (x
);
1789 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1791 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1792 or weak symbols. Relocations in the object file will be against
1793 the target symbol, so it's that symbol's binding that matters here. */
1794 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1797 /* Return true if function X is a libgcc MIPS16 stub function. */
1800 mips16_stub_function_p (const_rtx x
)
1802 return (GET_CODE (x
) == SYMBOL_REF
1803 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1806 /* Return true if function X is a locally-defined and locally-binding
1810 mips16_local_function_p (const_rtx x
)
1812 return (GET_CODE (x
) == SYMBOL_REF
1813 && SYMBOL_REF_LOCAL_P (x
)
1814 && !SYMBOL_REF_EXTERNAL_P (x
)
1815 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1818 /* Return true if SYMBOL_REF X binds locally. */
1821 mips_symbol_binds_local_p (const_rtx x
)
1823 return (SYMBOL_REF_DECL (x
)
1824 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1825 : SYMBOL_REF_LOCAL_P (x
));
1828 /* Return true if rtx constants of mode MODE should be put into a small
1832 mips_rtx_constant_in_small_data_p (machine_mode mode
)
1834 return (!TARGET_EMBEDDED_DATA
1835 && TARGET_LOCAL_SDATA
1836 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1839 /* Return true if X should not be moved directly into register $25.
1840 We need this because many versions of GAS will treat "la $25,foo" as
1841 part of a call sequence and so allow a global "foo" to be lazily bound. */
1844 mips_dangerous_for_la25_p (rtx x
)
1846 return (!TARGET_EXPLICIT_RELOCS
1848 && GET_CODE (x
) == SYMBOL_REF
1849 && mips_global_symbol_p (x
));
1852 /* Return true if calls to X might need $25 to be valid on entry. */
1855 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1857 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1860 /* MIPS16 stub functions are guaranteed not to use $25. */
1861 if (mips16_stub_function_p (x
))
1864 if (GET_CODE (x
) == SYMBOL_REF
)
1866 /* If PLTs and copy relocations are available, the static linker
1867 will make sure that $25 is valid on entry to the target function. */
1868 if (TARGET_ABICALLS_PIC0
)
1871 /* Locally-defined functions use absolute accesses to set up
1872 the global pointer. */
1873 if (TARGET_ABSOLUTE_ABICALLS
1874 && mips_symbol_binds_local_p (x
)
1875 && !SYMBOL_REF_EXTERNAL_P (x
))
1882 /* Return the method that should be used to access SYMBOL_REF or
1883 LABEL_REF X in context CONTEXT. */
1885 static enum mips_symbol_type
1886 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1889 return SYMBOL_GOT_DISP
;
1891 if (GET_CODE (x
) == LABEL_REF
)
1893 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1894 code and if we know that the label is in the current function's
1895 text section. LABEL_REFs are used for jump tables as well as
1896 text labels, so we must check whether jump tables live in the
1898 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1899 && !LABEL_REF_NONLOCAL_P (x
))
1900 return SYMBOL_PC_RELATIVE
;
1902 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1903 return SYMBOL_GOT_PAGE_OFST
;
1905 return SYMBOL_ABSOLUTE
;
1908 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1910 if (SYMBOL_REF_TLS_MODEL (x
))
1913 if (CONSTANT_POOL_ADDRESS_P (x
))
1915 if (TARGET_MIPS16_TEXT_LOADS
)
1916 return SYMBOL_PC_RELATIVE
;
1918 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1919 return SYMBOL_PC_RELATIVE
;
1921 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1922 return SYMBOL_GP_RELATIVE
;
1925 /* Do not use small-data accesses for weak symbols; they may end up
1927 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1928 return SYMBOL_GP_RELATIVE
;
1930 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1932 if (TARGET_ABICALLS_PIC2
1933 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1935 /* There are three cases to consider:
1937 - o32 PIC (either with or without explicit relocs)
1938 - n32/n64 PIC without explicit relocs
1939 - n32/n64 PIC with explicit relocs
1941 In the first case, both local and global accesses will use an
1942 R_MIPS_GOT16 relocation. We must correctly predict which of
1943 the two semantics (local or global) the assembler and linker
1944 will apply. The choice depends on the symbol's binding rather
1945 than its visibility.
1947 In the second case, the assembler will not use R_MIPS_GOT16
1948 relocations, but it chooses between local and global accesses
1949 in the same way as for o32 PIC.
1951 In the third case we have more freedom since both forms of
1952 access will work for any kind of symbol. However, there seems
1953 little point in doing things differently. */
1954 if (mips_global_symbol_p (x
))
1955 return SYMBOL_GOT_DISP
;
1957 return SYMBOL_GOT_PAGE_OFST
;
1960 return SYMBOL_ABSOLUTE
;
1963 /* Classify the base of symbolic expression X, given that X appears in
1966 static enum mips_symbol_type
1967 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1971 split_const (x
, &x
, &offset
);
1972 if (UNSPEC_ADDRESS_P (x
))
1973 return UNSPEC_ADDRESS_TYPE (x
);
1975 return mips_classify_symbol (x
, context
);
1978 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1979 is the alignment in bytes of SYMBOL_REF X. */
1982 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1984 HOST_WIDE_INT align
;
1986 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1987 return IN_RANGE (offset
, 0, align
- 1);
1990 /* Return true if X is a symbolic constant that can be used in context
1991 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1994 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1995 enum mips_symbol_type
*symbol_type
)
1999 split_const (x
, &x
, &offset
);
2000 if (UNSPEC_ADDRESS_P (x
))
2002 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
2003 x
= UNSPEC_ADDRESS (x
);
2005 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
2007 *symbol_type
= mips_classify_symbol (x
, context
);
2008 if (*symbol_type
== SYMBOL_TLS
)
2014 if (offset
== const0_rtx
)
2017 /* Check whether a nonzero offset is valid for the underlying
2019 switch (*symbol_type
)
2021 case SYMBOL_ABSOLUTE
:
2022 case SYMBOL_64_HIGH
:
2025 /* If the target has 64-bit pointers and the object file only
2026 supports 32-bit symbols, the values of those symbols will be
2027 sign-extended. In this case we can't allow an arbitrary offset
2028 in case the 32-bit value X + OFFSET has a different sign from X. */
2029 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
2030 return offset_within_block_p (x
, INTVAL (offset
));
2032 /* In other cases the relocations can handle any offset. */
2035 case SYMBOL_PC_RELATIVE
:
2036 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2037 In this case, we no longer have access to the underlying constant,
2038 but the original symbol-based access was known to be valid. */
2039 if (GET_CODE (x
) == LABEL_REF
)
2044 case SYMBOL_GP_RELATIVE
:
2045 /* Make sure that the offset refers to something within the
2046 same object block. This should guarantee that the final
2047 PC- or GP-relative offset is within the 16-bit limit. */
2048 return offset_within_block_p (x
, INTVAL (offset
));
2050 case SYMBOL_GOT_PAGE_OFST
:
2051 case SYMBOL_GOTOFF_PAGE
:
2052 /* If the symbol is global, the GOT entry will contain the symbol's
2053 address, and we will apply a 16-bit offset after loading it.
2054 If the symbol is local, the linker should provide enough local
2055 GOT entries for a 16-bit offset, but larger offsets may lead
2057 return SMALL_INT (offset
);
2061 /* There is no carry between the HI and LO REL relocations, so the
2062 offset is only valid if we know it won't lead to such a carry. */
2063 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2065 case SYMBOL_GOT_DISP
:
2066 case SYMBOL_GOTOFF_DISP
:
2067 case SYMBOL_GOTOFF_CALL
:
2068 case SYMBOL_GOTOFF_LOADGP
:
2071 case SYMBOL_GOTTPREL
:
2079 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2080 single instruction. We rely on the fact that, in the worst case,
2081 all instructions involved in a MIPS16 address calculation are usually
2085 mips_symbol_insns_1 (enum mips_symbol_type type
, machine_mode mode
)
2087 if (mips_use_pcrel_pool_p
[(int) type
])
2089 if (mode
== MAX_MACHINE_MODE
)
2090 /* LEAs will be converted into constant-pool references by
2092 type
= SYMBOL_PC_RELATIVE
;
2094 /* The constant must be loaded and then dereferenced. */
2100 case SYMBOL_ABSOLUTE
:
2101 /* When using 64-bit symbols, we need 5 preparatory instructions,
2104 lui $at,%highest(symbol)
2105 daddiu $at,$at,%higher(symbol)
2107 daddiu $at,$at,%hi(symbol)
2110 The final address is then $at + %lo(symbol). With 32-bit
2111 symbols we just need a preparatory LUI for normal mode and
2112 a preparatory LI and SLL for MIPS16. */
2113 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2115 case SYMBOL_GP_RELATIVE
:
2116 /* Treat GP-relative accesses as taking a single instruction on
2117 MIPS16 too; the copy of $gp can often be shared. */
2120 case SYMBOL_PC_RELATIVE
:
2121 /* PC-relative constants can be only be used with ADDIUPC,
2122 DADDIUPC, LWPC and LDPC. */
2123 if (mode
== MAX_MACHINE_MODE
2124 || GET_MODE_SIZE (mode
) == 4
2125 || GET_MODE_SIZE (mode
) == 8)
2128 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2131 case SYMBOL_GOT_DISP
:
2132 /* The constant will have to be loaded from the GOT before it
2133 is used in an address. */
2134 if (mode
!= MAX_MACHINE_MODE
)
2139 case SYMBOL_GOT_PAGE_OFST
:
2140 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2141 local/global classification is accurate. The worst cases are:
2143 (1) For local symbols when generating o32 or o64 code. The assembler
2149 ...and the final address will be $at + %lo(symbol).
2151 (2) For global symbols when -mxgot. The assembler will use:
2153 lui $at,%got_hi(symbol)
2156 ...and the final address will be $at + %got_lo(symbol). */
2159 case SYMBOL_GOTOFF_PAGE
:
2160 case SYMBOL_GOTOFF_DISP
:
2161 case SYMBOL_GOTOFF_CALL
:
2162 case SYMBOL_GOTOFF_LOADGP
:
2163 case SYMBOL_64_HIGH
:
2169 case SYMBOL_GOTTPREL
:
2172 /* A 16-bit constant formed by a single relocation, or a 32-bit
2173 constant formed from a high 16-bit relocation and a low 16-bit
2174 relocation. Use mips_split_p to determine which. 32-bit
2175 constants need an "lui; addiu" sequence for normal mode and
2176 an "li; sll; addiu" sequence for MIPS16 mode. */
2177 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2180 /* We don't treat a bare TLS symbol as a constant. */
2186 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2187 to load symbols of type TYPE into a register. Return 0 if the given
2188 type of symbol cannot be used as an immediate operand.
2190 Otherwise, return the number of instructions needed to load or store
2191 values of mode MODE to or from addresses of type TYPE. Return 0 if
2192 the given type of symbol is not valid in addresses.
2194 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2197 mips_symbol_insns (enum mips_symbol_type type
, machine_mode mode
)
2199 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2202 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2205 mips_cannot_force_const_mem (machine_mode mode
, rtx x
)
2207 enum mips_symbol_type type
;
2210 /* There is no assembler syntax for expressing an address-sized
2212 if (GET_CODE (x
) == HIGH
)
2215 /* As an optimization, reject constants that mips_legitimize_move
2218 Suppose we have a multi-instruction sequence that loads constant C
2219 into register R. If R does not get allocated a hard register, and
2220 R is used in an operand that allows both registers and memory
2221 references, reload will consider forcing C into memory and using
2222 one of the instruction's memory alternatives. Returning false
2223 here will force it to use an input reload instead. */
2224 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2227 split_const (x
, &base
, &offset
);
2228 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2230 /* See whether we explicitly want these symbols in the pool. */
2231 if (mips_use_pcrel_pool_p
[(int) type
])
2234 /* The same optimization as for CONST_INT. */
2235 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2238 /* If MIPS16 constant pools live in the text section, they should
2239 not refer to anything that might need run-time relocation. */
2240 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2244 /* TLS symbols must be computed by mips_legitimize_move. */
2245 if (tls_referenced_p (x
))
2251 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2252 constants when we're using a per-function constant pool. */
2255 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED
,
2256 const_rtx x ATTRIBUTE_UNUSED
)
2258 return !TARGET_MIPS16_PCREL_LOADS
;
2261 /* Return true if register REGNO is a valid base register for mode MODE.
2262 STRICT_P is true if REG_OK_STRICT is in effect. */
2265 mips_regno_mode_ok_for_base_p (int regno
, machine_mode mode
,
2268 if (!HARD_REGISTER_NUM_P (regno
))
2272 regno
= reg_renumber
[regno
];
2275 /* These fake registers will be eliminated to either the stack or
2276 hard frame pointer, both of which are usually valid base registers.
2277 Reload deals with the cases where the eliminated form isn't valid. */
2278 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2281 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2282 values, nothing smaller. */
2283 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2284 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2286 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2289 /* Return true if X is a valid base register for mode MODE.
2290 STRICT_P is true if REG_OK_STRICT is in effect. */
2293 mips_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
2295 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2299 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2302 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2303 can address a value of mode MODE. */
2306 mips_valid_offset_p (rtx x
, machine_mode mode
)
2308 /* Check that X is a signed 16-bit number. */
2309 if (!const_arith_operand (x
, Pmode
))
2312 /* We may need to split multiword moves, so make sure that every word
2314 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2315 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2321 /* Return true if a LO_SUM can address a value of mode MODE when the
2322 LO_SUM symbol has type SYMBOL_TYPE. */
2325 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, machine_mode mode
)
2327 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2329 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2332 /* Check that there is a known low-part relocation. */
2333 if (mips_lo_relocs
[symbol_type
] == NULL
)
2336 /* We may need to split multiword moves, so make sure that each word
2337 can be accessed without inducing a carry. This is mainly needed
2338 for o64, which has historically only guaranteed 64-bit alignment
2339 for 128-bit types. */
2340 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2341 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2347 /* Return true if X is a valid address for machine mode MODE. If it is,
2348 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2352 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2353 machine_mode mode
, bool strict_p
)
2355 switch (GET_CODE (x
))
2359 info
->type
= ADDRESS_REG
;
2361 info
->offset
= const0_rtx
;
2362 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2365 info
->type
= ADDRESS_REG
;
2366 info
->reg
= XEXP (x
, 0);
2367 info
->offset
= XEXP (x
, 1);
2368 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2369 && mips_valid_offset_p (info
->offset
, mode
));
2372 info
->type
= ADDRESS_LO_SUM
;
2373 info
->reg
= XEXP (x
, 0);
2374 info
->offset
= XEXP (x
, 1);
2375 /* We have to trust the creator of the LO_SUM to do something vaguely
2376 sane. Target-independent code that creates a LO_SUM should also
2377 create and verify the matching HIGH. Target-independent code that
2378 adds an offset to a LO_SUM must prove that the offset will not
2379 induce a carry. Failure to do either of these things would be
2380 a bug, and we are not required to check for it here. The MIPS
2381 backend itself should only create LO_SUMs for valid symbolic
2382 constants, with the high part being either a HIGH or a copy
2385 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2386 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2387 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2390 /* Small-integer addresses don't occur very often, but they
2391 are legitimate if $0 is a valid base register. */
2392 info
->type
= ADDRESS_CONST_INT
;
2393 return !TARGET_MIPS16
&& SMALL_INT (x
);
2398 info
->type
= ADDRESS_SYMBOLIC
;
2399 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2401 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2402 && !mips_split_p
[info
->symbol_type
]);
2409 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2412 mips_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2414 struct mips_address_info addr
;
2416 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2419 /* Return true if X is a legitimate $sp-based address for mode MODE. */
2422 mips_stack_address_p (rtx x
, machine_mode mode
)
2424 struct mips_address_info addr
;
2426 return (mips_classify_address (&addr
, x
, mode
, false)
2427 && addr
.type
== ADDRESS_REG
2428 && addr
.reg
== stack_pointer_rtx
);
2431 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2432 address instruction. Note that such addresses are not considered
2433 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2434 is so restricted. */
2437 mips_lwxs_address_p (rtx addr
)
2440 && GET_CODE (addr
) == PLUS
2441 && REG_P (XEXP (addr
, 1)))
2443 rtx offset
= XEXP (addr
, 0);
2444 if (GET_CODE (offset
) == MULT
2445 && REG_P (XEXP (offset
, 0))
2446 && CONST_INT_P (XEXP (offset
, 1))
2447 && INTVAL (XEXP (offset
, 1)) == 4)
2453 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2454 indexed address instruction. Note that such addresses are
2455 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2456 sense, because their use is so restricted. */
2459 mips_lx_address_p (rtx addr
, machine_mode mode
)
2461 if (GET_CODE (addr
) != PLUS
2462 || !REG_P (XEXP (addr
, 0))
2463 || !REG_P (XEXP (addr
, 1)))
2465 if (ISA_HAS_LBX
&& mode
== QImode
)
2467 if (ISA_HAS_LHX
&& mode
== HImode
)
2469 if (ISA_HAS_LWX
&& mode
== SImode
)
2471 if (ISA_HAS_LDX
&& mode
== DImode
)
2476 /* Return true if a value at OFFSET bytes from base register BASE can be
2477 accessed using an unextended MIPS16 instruction. MODE is the mode of
2480 Usually the offset in an unextended instruction is a 5-bit field.
2481 The offset is unsigned and shifted left once for LH and SH, twice
2482 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2483 an 8-bit immediate field that's shifted left twice. */
2486 mips16_unextended_reference_p (machine_mode mode
, rtx base
,
2487 unsigned HOST_WIDE_INT offset
)
2489 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2491 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2492 return offset
< 256U * GET_MODE_SIZE (mode
);
2493 return offset
< 32U * GET_MODE_SIZE (mode
);
2498 /* Return the number of instructions needed to load or store a value
2499 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2500 length of one instruction. Return 0 if X isn't valid for MODE.
2501 Assume that multiword moves may need to be split into word moves
2502 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2506 mips_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
2508 struct mips_address_info addr
;
2511 /* BLKmode is used for single unaligned loads and stores and should
2512 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2513 meaningless, so we have to single it out as a special case one way
2515 if (mode
!= BLKmode
&& might_split_p
)
2516 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2520 if (mips_classify_address (&addr
, x
, mode
, false))
2525 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2526 UINTVAL (addr
.offset
)))
2530 case ADDRESS_LO_SUM
:
2531 return TARGET_MIPS16
? factor
* 2 : factor
;
2533 case ADDRESS_CONST_INT
:
2536 case ADDRESS_SYMBOLIC
:
2537 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2542 /* Return true if X fits within an unsigned field of BITS bits that is
2543 shifted left SHIFT bits before being used. */
2546 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2548 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2551 /* Return true if X fits within a signed field of BITS bits that is
2552 shifted left SHIFT bits before being used. */
2555 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2557 x
+= 1 << (bits
+ shift
- 1);
2558 return mips_unsigned_immediate_p (x
, bits
, shift
);
2561 /* Return true if X is legitimate for accessing values of mode MODE,
2562 if it is based on a MIPS16 register, and if the offset satisfies
2563 OFFSET_PREDICATE. */
2566 m16_based_address_p (rtx x
, machine_mode mode
,
2567 insn_operand_predicate_fn offset_predicate
)
2569 struct mips_address_info addr
;
2571 return (mips_classify_address (&addr
, x
, mode
, false)
2572 && addr
.type
== ADDRESS_REG
2573 && M16_REG_P (REGNO (addr
.reg
))
2574 && offset_predicate (addr
.offset
, mode
));
2577 /* Return true if X is a legitimate address that conforms to the requirements
2578 for a microMIPS LWSP or SWSP insn. */
2581 lwsp_swsp_address_p (rtx x
, machine_mode mode
)
2583 struct mips_address_info addr
;
2585 return (mips_classify_address (&addr
, x
, mode
, false)
2586 && addr
.type
== ADDRESS_REG
2587 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2588 && uw5_operand (addr
.offset
, mode
));
2591 /* Return true if X is a legitimate address with a 12-bit offset.
2592 MODE is the mode of the value being accessed. */
2595 umips_12bit_offset_address_p (rtx x
, machine_mode mode
)
2597 struct mips_address_info addr
;
2599 return (mips_classify_address (&addr
, x
, mode
, false)
2600 && addr
.type
== ADDRESS_REG
2601 && CONST_INT_P (addr
.offset
)
2602 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2605 /* Return true if X is a legitimate address with a 9-bit offset.
2606 MODE is the mode of the value being accessed. */
2609 mips_9bit_offset_address_p (rtx x
, machine_mode mode
)
2611 struct mips_address_info addr
;
2613 return (mips_classify_address (&addr
, x
, mode
, false)
2614 && addr
.type
== ADDRESS_REG
2615 && CONST_INT_P (addr
.offset
)
2616 && MIPS_9BIT_OFFSET_P (INTVAL (addr
.offset
)));
2619 /* Return the number of instructions needed to load constant X,
2620 assuming that BASE_INSN_LENGTH is the length of one instruction.
2621 Return 0 if X isn't a valid constant. */
2624 mips_const_insns (rtx x
)
2626 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2627 enum mips_symbol_type symbol_type
;
2630 switch (GET_CODE (x
))
2633 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2635 || !mips_split_p
[symbol_type
])
2638 /* This is simply an LUI for normal mode. It is an extended
2639 LI followed by an extended SLL for MIPS16. */
2640 return TARGET_MIPS16
? 4 : 1;
2644 /* Unsigned 8-bit constants can be loaded using an unextended
2645 LI instruction. Unsigned 16-bit constants can be loaded
2646 using an extended LI. Negative constants must be loaded
2647 using LI and then negated. */
2648 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2649 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2650 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2651 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2654 return mips_build_integer (codes
, INTVAL (x
));
2658 /* Allow zeros for normal mode, where we can use $0. */
2659 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2665 /* See if we can refer to X directly. */
2666 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2667 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2669 /* Otherwise try splitting the constant into a base and offset.
2670 If the offset is a 16-bit value, we can load the base address
2671 into a register and then use (D)ADDIU to add in the offset.
2672 If the offset is larger, we can load the base and offset
2673 into separate registers and add them together with (D)ADDU.
2674 However, the latter is only possible before reload; during
2675 and after reload, we must have the option of forcing the
2676 constant into the pool instead. */
2677 split_const (x
, &x
, &offset
);
2680 int n
= mips_const_insns (x
);
2683 if (SMALL_INT (offset
))
2685 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2686 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2693 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2701 /* X is a doubleword constant that can be handled by splitting it into
2702 two words and loading each word separately. Return the number of
2703 instructions required to do this, assuming that BASE_INSN_LENGTH
2704 is the length of one instruction. */
2707 mips_split_const_insns (rtx x
)
2709 unsigned int low
, high
;
2711 low
= mips_const_insns (mips_subword (x
, false));
2712 high
= mips_const_insns (mips_subword (x
, true));
2713 gcc_assert (low
> 0 && high
> 0);
2717 /* Return the number of instructions needed to implement INSN,
2718 given that it loads from or stores to MEM. Assume that
2719 BASE_INSN_LENGTH is the length of one instruction. */
2722 mips_load_store_insns (rtx mem
, rtx_insn
*insn
)
2728 gcc_assert (MEM_P (mem
));
2729 mode
= GET_MODE (mem
);
2731 /* Try to prove that INSN does not need to be split. */
2732 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2735 set
= single_set (insn
);
2736 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2737 might_split_p
= false;
2740 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2743 /* Return the number of instructions needed for an integer division,
2744 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2747 mips_idiv_insns (void)
2752 if (TARGET_CHECK_ZERO_DIV
)
2754 if (GENERATE_DIVIDE_TRAPS
)
2760 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2765 /* Emit a move from SRC to DEST. Assume that the move expanders can
2766 handle all moves if !can_create_pseudo_p (). The distinction is
2767 important because, unlike emit_move_insn, the move expanders know
2768 how to force Pmode objects into the constant pool even when the
2769 constant pool address is not itself legitimate. */
2772 mips_emit_move (rtx dest
, rtx src
)
2774 return (can_create_pseudo_p ()
2775 ? emit_move_insn (dest
, src
)
2776 : emit_move_insn_1 (dest
, src
));
2779 /* Emit a move from SRC to DEST, splitting compound moves into individual
2780 instructions. SPLIT_TYPE is the type of split to perform. */
2783 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2785 if (mips_split_move_p (dest
, src
, split_type
))
2786 mips_split_move (dest
, src
, split_type
);
2788 mips_emit_move (dest
, src
);
2791 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2794 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2796 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2799 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2800 Return that new register. */
2803 mips_force_unary (machine_mode mode
, enum rtx_code code
, rtx op0
)
2807 reg
= gen_reg_rtx (mode
);
2808 mips_emit_unary (code
, reg
, op0
);
2812 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2815 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2817 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (code
, GET_MODE (target
),
2821 /* Compute (CODE OP0 OP1) and store the result in a new register
2822 of mode MODE. Return that new register. */
2825 mips_force_binary (machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2829 reg
= gen_reg_rtx (mode
);
2830 mips_emit_binary (code
, reg
, op0
, op1
);
2834 /* Copy VALUE to a register and return that register. If new pseudos
2835 are allowed, copy it into a new register, otherwise use DEST. */
2838 mips_force_temporary (rtx dest
, rtx value
)
2840 if (can_create_pseudo_p ())
2841 return force_reg (Pmode
, value
);
2844 mips_emit_move (dest
, value
);
2849 /* Emit a call sequence with call pattern PATTERN and return the call
2850 instruction itself (which is not necessarily the last instruction
2851 emitted). ORIG_ADDR is the original, unlegitimized address,
2852 ADDR is the legitimized form, and LAZY_P is true if the call
2853 address is lazily-bound. */
2856 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2861 insn
= emit_call_insn (pattern
);
2863 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2865 /* MIPS16 JALRs only take MIPS16 registers. If the target
2866 function requires $25 to be valid on entry, we must copy it
2867 there separately. The move instruction can be put in the
2868 call's delay slot. */
2869 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2870 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2871 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2875 /* Lazy-binding stubs require $gp to be valid on entry. */
2876 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2880 /* See the comment above load_call<mode> for details. */
2881 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2882 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2883 emit_insn (gen_update_got_version ());
2887 && TARGET_EXPLICIT_RELOCS
2888 && TARGET_CALL_CLOBBERED_GP
)
2890 rtx post_call_tmp_reg
= gen_rtx_REG (word_mode
, POST_CALL_TMP_REG
);
2891 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn
), post_call_tmp_reg
);
2897 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2898 then add CONST_INT OFFSET to the result. */
2901 mips_unspec_address_offset (rtx base
, rtx offset
,
2902 enum mips_symbol_type symbol_type
)
2904 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2905 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2906 if (offset
!= const0_rtx
)
2907 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2908 return gen_rtx_CONST (Pmode
, base
);
2911 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2912 type SYMBOL_TYPE. */
2915 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2919 split_const (address
, &base
, &offset
);
2920 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2923 /* If OP is an UNSPEC address, return the address to which it refers,
2924 otherwise return OP itself. */
2927 mips_strip_unspec_address (rtx op
)
2931 split_const (op
, &base
, &offset
);
2932 if (UNSPEC_ADDRESS_P (base
))
2933 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2937 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2938 high part to BASE and return the result. Just return BASE otherwise.
2939 TEMP is as for mips_force_temporary.
2941 The returned expression can be used as the first operand to a LO_SUM. */
2944 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2945 enum mips_symbol_type symbol_type
)
2947 if (mips_split_p
[symbol_type
])
2949 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2950 addr
= mips_force_temporary (temp
, addr
);
2951 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2956 /* Return an instruction that copies $gp into register REG. We want
2957 GCC to treat the register's value as constant, so that its value
2958 can be rematerialized on demand. */
2961 gen_load_const_gp (rtx reg
)
2963 return PMODE_INSN (gen_load_const_gp
, (reg
));
2966 /* Return a pseudo register that contains the value of $gp throughout
2967 the current function. Such registers are needed by MIPS16 functions,
2968 for which $gp itself is not a valid base register or addition operand. */
2971 mips16_gp_pseudo_reg (void)
2973 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2977 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2979 push_topmost_sequence ();
2981 scan
= get_insns ();
2982 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2983 scan
= NEXT_INSN (scan
);
2985 rtx set
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2986 rtx_insn
*insn
= emit_insn_after (set
, scan
);
2987 INSN_LOCATION (insn
) = 0;
2989 pop_topmost_sequence ();
2992 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2995 /* Return a base register that holds pic_offset_table_rtx.
2996 TEMP, if nonnull, is a scratch Pmode base register. */
2999 mips_pic_base_register (rtx temp
)
3002 return pic_offset_table_rtx
;
3004 if (currently_expanding_to_rtl
)
3005 return mips16_gp_pseudo_reg ();
3007 if (can_create_pseudo_p ())
3008 temp
= gen_reg_rtx (Pmode
);
3011 /* The first post-reload split exposes all references to $gp
3012 (both uses and definitions). All references must remain
3013 explicit after that point.
3015 It is safe to introduce uses of $gp at any time, so for
3016 simplicity, we do that before the split too. */
3017 mips_emit_move (temp
, pic_offset_table_rtx
);
3019 emit_insn (gen_load_const_gp (temp
));
3023 /* Return the RHS of a load_call<mode> insn. */
3026 mips_unspec_call (rtx reg
, rtx symbol
)
3030 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
3031 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
3034 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3035 reference. Return NULL_RTX otherwise. */
3038 mips_strip_unspec_call (rtx src
)
3040 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
3041 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
3045 /* Create and return a GOT reference of type TYPE for address ADDR.
3046 TEMP, if nonnull, is a scratch Pmode base register. */
3049 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3051 rtx base
, high
, lo_sum_symbol
;
3053 base
= mips_pic_base_register (temp
);
3055 /* If we used the temporary register to load $gp, we can't use
3056 it for the high part as well. */
3057 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3060 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3061 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3063 if (type
== SYMBOL_GOTOFF_CALL
)
3064 return mips_unspec_call (high
, lo_sum_symbol
);
3066 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3069 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3070 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3071 constant in that context and can be split into high and low parts.
3072 If so, and if LOW_OUT is nonnull, emit the high part and store the
3073 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3075 TEMP is as for mips_force_temporary and is used to load the high
3076 part into a register.
3078 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3079 a legitimize SET_SRC for an .md pattern, otherwise the low part
3080 is guaranteed to be a legitimate address for mode MODE. */
3083 mips_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
3085 enum mips_symbol_context context
;
3086 enum mips_symbol_type symbol_type
;
3089 context
= (mode
== MAX_MACHINE_MODE
3090 ? SYMBOL_CONTEXT_LEA
3091 : SYMBOL_CONTEXT_MEM
);
3092 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3094 addr
= XEXP (addr
, 0);
3095 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3096 && mips_symbol_insns (symbol_type
, mode
) > 0
3097 && mips_split_hi_p
[symbol_type
])
3100 switch (symbol_type
)
3102 case SYMBOL_GOT_PAGE_OFST
:
3103 /* The high part of a page/ofst pair is loaded from the GOT. */
3104 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3115 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3116 && mips_symbol_insns (symbol_type
, mode
) > 0
3117 && mips_split_p
[symbol_type
])
3120 switch (symbol_type
)
3122 case SYMBOL_GOT_DISP
:
3123 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3124 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3127 case SYMBOL_GP_RELATIVE
:
3128 high
= mips_pic_base_register (temp
);
3129 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3133 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3134 high
= mips_force_temporary (temp
, high
);
3135 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3144 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3145 mips_force_temporary; it is only needed when OFFSET is not a
3149 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3151 if (!SMALL_OPERAND (offset
))
3157 /* Load the full offset into a register so that we can use
3158 an unextended instruction for the address itself. */
3159 high
= GEN_INT (offset
);
3164 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3165 The addition inside the macro CONST_HIGH_PART may cause an
3166 overflow, so we need to force a sign-extension check. */
3167 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3168 offset
= CONST_LOW_PART (offset
);
3170 high
= mips_force_temporary (temp
, high
);
3171 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3173 return plus_constant (Pmode
, reg
, offset
);
3176 /* The __tls_get_attr symbol. */
3177 static GTY(()) rtx mips_tls_symbol
;
3179 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3180 the TLS symbol we are referencing and TYPE is the symbol type to use
3181 (either global dynamic or local dynamic). V0 is an RTX for the
3182 return value location. */
3185 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3189 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3191 if (!mips_tls_symbol
)
3192 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3194 loc
= mips_unspec_address (sym
, type
);
3198 emit_insn (gen_rtx_SET (a0
, gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
,
3200 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3201 const0_rtx
, NULL_RTX
, false);
3202 RTL_CONST_CALL_P (insn
) = 1;
3203 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3204 insn
= get_insns ();
3211 /* Return a pseudo register that contains the current thread pointer. */
3214 mips_expand_thread_pointer (rtx tp
)
3220 if (!mips16_rdhwr_stub
)
3221 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3222 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3223 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3226 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3233 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3236 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3237 its address. The return value will be both a valid address and a valid
3238 SET_SRC (either a REG or a LO_SUM). */
3241 mips_legitimize_tls_address (rtx loc
)
3243 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3244 enum tls_model model
;
3246 model
= SYMBOL_REF_TLS_MODEL (loc
);
3247 /* Only TARGET_ABICALLS code can have more than one module; other
3248 code must be be static and should not use a GOT. All TLS models
3249 reduce to local exec in this situation. */
3250 if (!TARGET_ABICALLS
)
3251 model
= TLS_MODEL_LOCAL_EXEC
;
3255 case TLS_MODEL_GLOBAL_DYNAMIC
:
3256 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3257 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3258 dest
= gen_reg_rtx (Pmode
);
3259 emit_libcall_block (insn
, dest
, v0
, loc
);
3262 case TLS_MODEL_LOCAL_DYNAMIC
:
3263 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3264 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3265 tmp1
= gen_reg_rtx (Pmode
);
3267 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3268 share the LDM result with other LD model accesses. */
3269 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3271 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3273 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3274 if (mips_split_p
[SYMBOL_DTPREL
])
3276 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3277 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3280 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3281 0, 0, OPTAB_DIRECT
);
3284 case TLS_MODEL_INITIAL_EXEC
:
3285 tp
= mips_get_tp ();
3286 tmp1
= gen_reg_rtx (Pmode
);
3287 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3288 if (Pmode
== DImode
)
3289 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3291 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3292 dest
= gen_reg_rtx (Pmode
);
3293 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3296 case TLS_MODEL_LOCAL_EXEC
:
3297 tmp1
= mips_get_tp ();
3298 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3299 if (mips_split_p
[SYMBOL_TPREL
])
3301 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3302 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3305 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3306 0, 0, OPTAB_DIRECT
);
3315 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3319 mips16_expand_get_fcsr (rtx target
)
3321 if (!mips16_get_fcsr_stub
)
3322 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3323 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3324 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3325 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3328 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3331 mips16_expand_set_fcsr (rtx newval
)
3333 if (!mips16_set_fcsr_stub
)
3334 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3335 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3336 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3337 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3340 /* If X is not a valid address for mode MODE, force it into a register. */
3343 mips_force_address (rtx x
, machine_mode mode
)
3345 if (!mips_legitimate_address_p (mode
, x
, false))
3346 x
= force_reg (Pmode
, x
);
3350 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3351 be legitimized in a way that the generic machinery might not expect,
3352 return a new address, otherwise return NULL. MODE is the mode of
3353 the memory being accessed. */
3356 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3360 HOST_WIDE_INT offset
;
3362 if (mips_tls_symbol_p (x
))
3363 return mips_legitimize_tls_address (x
);
3365 /* See if the address can split into a high part and a LO_SUM. */
3366 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3367 return mips_force_address (addr
, mode
);
3369 /* Handle BASE + OFFSET using mips_add_offset. */
3370 mips_split_plus (x
, &base
, &offset
);
3373 if (!mips_valid_base_register_p (base
, mode
, false))
3374 base
= copy_to_mode_reg (Pmode
, base
);
3375 addr
= mips_add_offset (NULL
, base
, offset
);
3376 return mips_force_address (addr
, mode
);
3382 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3385 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3387 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3389 unsigned int i
, num_ops
;
3392 mode
= GET_MODE (dest
);
3393 num_ops
= mips_build_integer (codes
, value
);
3395 /* Apply each binary operation to X. Invariant: X is a legitimate
3396 source operand for a SET pattern. */
3397 x
= GEN_INT (codes
[0].value
);
3398 for (i
= 1; i
< num_ops
; i
++)
3400 if (!can_create_pseudo_p ())
3402 emit_insn (gen_rtx_SET (temp
, x
));
3406 x
= force_reg (mode
, x
);
3407 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3410 emit_insn (gen_rtx_SET (dest
, x
));
3413 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3414 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3418 mips_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
3422 /* Split moves of big integers into smaller pieces. */
3423 if (splittable_const_int_operand (src
, mode
))
3425 mips_move_integer (dest
, dest
, INTVAL (src
));
3429 /* Split moves of symbolic constants into high/low pairs. */
3430 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3432 emit_insn (gen_rtx_SET (dest
, src
));
3436 /* Generate the appropriate access sequences for TLS symbols. */
3437 if (mips_tls_symbol_p (src
))
3439 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3443 /* If we have (const (plus symbol offset)), and that expression cannot
3444 be forced into memory, load the symbol first and add in the offset.
3445 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3446 forced into memory, as it usually produces better code. */
3447 split_const (src
, &base
, &offset
);
3448 if (offset
!= const0_rtx
3449 && (targetm
.cannot_force_const_mem (mode
, src
)
3450 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3452 base
= mips_force_temporary (dest
, base
);
3453 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3457 src
= force_const_mem (mode
, src
);
3459 /* When using explicit relocs, constant pool references are sometimes
3460 not legitimate addresses. */
3461 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3462 mips_emit_move (dest
, src
);
3465 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3466 sequence that is valid. */
3469 mips_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
3471 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3473 mips_emit_move (dest
, force_reg (mode
, src
));
3477 /* We need to deal with constants that would be legitimate
3478 immediate_operands but aren't legitimate move_operands. */
3479 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3481 mips_legitimize_const_move (mode
, dest
, src
);
3482 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3488 /* Return true if value X in context CONTEXT is a small-data address
3489 that can be rewritten as a LO_SUM. */
3492 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3494 enum mips_symbol_type symbol_type
;
3496 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3497 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3498 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3499 && symbol_type
== SYMBOL_GP_RELATIVE
);
3502 /* Return true if OP refers to small data symbols directly, not through
3503 a LO_SUM. CONTEXT is the context in which X appears. */
3506 mips_small_data_pattern_1 (rtx x
, enum mips_symbol_context context
)
3508 subrtx_var_iterator::array_type array
;
3509 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
3513 /* Ignore things like "g" constraints in asms. We make no particular
3514 guarantee about which symbolic constants are acceptable as asm operands
3515 versus which must be forced into a GPR. */
3516 if (GET_CODE (x
) == LO_SUM
|| GET_CODE (x
) == ASM_OPERANDS
)
3517 iter
.skip_subrtxes ();
3520 if (mips_small_data_pattern_1 (XEXP (x
, 0), SYMBOL_CONTEXT_MEM
))
3522 iter
.skip_subrtxes ();
3524 else if (mips_rewrite_small_data_p (x
, context
))
3530 /* Return true if OP refers to small data symbols directly, not through
3534 mips_small_data_pattern_p (rtx op
)
3536 return mips_small_data_pattern_1 (op
, SYMBOL_CONTEXT_LEA
);
3539 /* Rewrite *LOC so that it refers to small data using explicit
3540 relocations. CONTEXT is the context in which *LOC appears. */
3543 mips_rewrite_small_data_1 (rtx
*loc
, enum mips_symbol_context context
)
3545 subrtx_ptr_iterator::array_type array
;
3546 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3551 mips_rewrite_small_data_1 (&XEXP (*loc
, 0), SYMBOL_CONTEXT_MEM
);
3552 iter
.skip_subrtxes ();
3554 else if (mips_rewrite_small_data_p (*loc
, context
))
3556 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3557 iter
.skip_subrtxes ();
3559 else if (GET_CODE (*loc
) == LO_SUM
)
3560 iter
.skip_subrtxes ();
3564 /* Rewrite instruction pattern PATTERN so that it refers to small data
3565 using explicit relocations. */
3568 mips_rewrite_small_data (rtx pattern
)
3570 pattern
= copy_insn (pattern
);
3571 mips_rewrite_small_data_1 (&pattern
, SYMBOL_CONTEXT_LEA
);
3575 /* The cost of loading values from the constant pool. It should be
3576 larger than the cost of any constant we want to synthesize inline. */
3577 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3579 /* Return the cost of X when used as an operand to the MIPS16 instruction
3580 that implements CODE. Return -1 if there is no such instruction, or if
3581 X is not a valid immediate operand for it. */
3584 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3591 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3592 other shifts are extended. The shift patterns truncate the shift
3593 count to the right size, so there are no out-of-range values. */
3594 if (IN_RANGE (x
, 1, 8))
3596 return COSTS_N_INSNS (1);
3599 if (IN_RANGE (x
, -128, 127))
3601 if (SMALL_OPERAND (x
))
3602 return COSTS_N_INSNS (1);
3606 /* Like LE, but reject the always-true case. */
3610 /* We add 1 to the immediate and use SLT. */
3613 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3616 if (IN_RANGE (x
, 0, 255))
3618 if (SMALL_OPERAND_UNSIGNED (x
))
3619 return COSTS_N_INSNS (1);
3624 /* Equality comparisons with 0 are cheap. */
3634 /* Return true if there is a non-MIPS16 instruction that implements CODE
3635 and if that instruction accepts X as an immediate operand. */
3638 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3645 /* All shift counts are truncated to a valid constant. */
3650 /* Likewise rotates, if the target supports rotates at all. */
3656 /* These instructions take 16-bit unsigned immediates. */
3657 return SMALL_OPERAND_UNSIGNED (x
);
3662 /* These instructions take 16-bit signed immediates. */
3663 return SMALL_OPERAND (x
);
3669 /* The "immediate" forms of these instructions are really
3670 implemented as comparisons with register 0. */
3675 /* Likewise, meaning that the only valid immediate operand is 1. */
3679 /* We add 1 to the immediate and use SLT. */
3680 return SMALL_OPERAND (x
+ 1);
3683 /* Likewise SLTU, but reject the always-true case. */
3684 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3688 /* The bit position and size are immediate operands. */
3689 return ISA_HAS_EXT_INS
;
3692 /* By default assume that $0 can be used for 0. */
3697 /* Return the cost of binary operation X, given that the instruction
3698 sequence for a word-sized or smaller operation has cost SINGLE_COST
3699 and that the sequence of a double-word operation has cost DOUBLE_COST.
3700 If SPEED is true, optimize for speed otherwise optimize for size. */
3703 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3707 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3712 + set_src_cost (XEXP (x
, 0), GET_MODE (x
), speed
)
3713 + rtx_cost (XEXP (x
, 1), GET_MODE (x
), GET_CODE (x
), 1, speed
));
3716 /* Return the cost of floating-point multiplications of mode MODE. */
3719 mips_fp_mult_cost (machine_mode mode
)
3721 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3724 /* Return the cost of floating-point divisions of mode MODE. */
3727 mips_fp_div_cost (machine_mode mode
)
3729 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3732 /* Return the cost of sign-extending OP to mode MODE, not including the
3733 cost of OP itself. */
3736 mips_sign_extend_cost (machine_mode mode
, rtx op
)
3739 /* Extended loads are as cheap as unextended ones. */
3742 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3743 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3746 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3747 /* We can use SEB or SEH. */
3748 return COSTS_N_INSNS (1);
3750 /* We need to use a shift left and a shift right. */
3751 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3754 /* Return the cost of zero-extending OP to mode MODE, not including the
3755 cost of OP itself. */
3758 mips_zero_extend_cost (machine_mode mode
, rtx op
)
3761 /* Extended loads are as cheap as unextended ones. */
3764 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3765 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3766 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3768 if (GENERATE_MIPS16E
)
3769 /* We can use ZEB or ZEH. */
3770 return COSTS_N_INSNS (1);
3773 /* We need to load 0xff or 0xffff into a register and use AND. */
3774 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3776 /* We can use ANDI. */
3777 return COSTS_N_INSNS (1);
3780 /* Return the cost of moving between two registers of mode MODE,
3781 assuming that the move will be in pieces of at most UNITS bytes. */
3784 mips_set_reg_reg_piece_cost (machine_mode mode
, unsigned int units
)
3786 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3789 /* Return the cost of moving between two registers of mode MODE. */
3792 mips_set_reg_reg_cost (machine_mode mode
)
3794 switch (GET_MODE_CLASS (mode
))
3797 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3800 case MODE_COMPLEX_FLOAT
:
3801 case MODE_VECTOR_FLOAT
:
3802 if (TARGET_HARD_FLOAT
)
3803 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3807 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3811 /* Implement TARGET_RTX_COSTS. */
3814 mips_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
3815 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
3817 int code
= GET_CODE (x
);
3818 bool float_mode_p
= FLOAT_MODE_P (mode
);
3822 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3823 appear in the instruction stream, and the cost of a comparison is
3824 really the cost of the branch or scc condition. At the time of
3825 writing, GCC only uses an explicit outer COMPARE code when optabs
3826 is testing whether a constant is expensive enough to force into a
3827 register. We want optabs to pass such constants through the MIPS
3828 expanders instead, so make all constants very cheap here. */
3829 if (outer_code
== COMPARE
)
3831 gcc_assert (CONSTANT_P (x
));
3839 /* Treat *clear_upper32-style ANDs as having zero cost in the
3840 second operand. The cost is entirely in the first operand.
3842 ??? This is needed because we would otherwise try to CSE
3843 the constant operand. Although that's the right thing for
3844 instructions that continue to be a register operation throughout
3845 compilation, it is disastrous for instructions that could
3846 later be converted into a memory operation. */
3848 && outer_code
== AND
3849 && UINTVAL (x
) == 0xffffffff)
3857 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3866 /* When not optimizing for size, we care more about the cost
3867 of hot code, and hot code is often in a loop. If a constant
3868 operand needs to be forced into a register, we will often be
3869 able to hoist the constant load out of the loop, so the load
3870 should not contribute to the cost. */
3871 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3883 if (force_to_mem_operand (x
, VOIDmode
))
3885 *total
= COSTS_N_INSNS (1);
3888 cost
= mips_const_insns (x
);
3891 /* If the constant is likely to be stored in a GPR, SETs of
3892 single-insn constants are as cheap as register sets; we
3893 never want to CSE them.
3895 Don't reduce the cost of storing a floating-point zero in
3896 FPRs. If we have a zero in an FPR for other reasons, we
3897 can get better cfg-cleanup and delayed-branch results by
3898 using it consistently, rather than using $0 sometimes and
3899 an FPR at other times. Also, moves between floating-point
3900 registers are sometimes cheaper than (D)MTC1 $0. */
3902 && outer_code
== SET
3903 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3905 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3906 want to CSE the constant itself. It is usually better to
3907 have N copies of the last operation in the sequence and one
3908 shared copy of the other operations. (Note that this is
3909 not true for MIPS16 code, where the final operation in the
3910 sequence is often an extended instruction.)
3912 Also, if we have a CONST_INT, we don't know whether it is
3913 for a word or doubleword operation, so we cannot rely on
3914 the result of mips_build_integer. */
3915 else if (!TARGET_MIPS16
3916 && (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
))
3918 *total
= COSTS_N_INSNS (cost
);
3921 /* The value will need to be fetched from the constant pool. */
3922 *total
= CONSTANT_POOL_COST
;
3926 /* If the address is legitimate, return the number of
3927 instructions it needs. */
3929 cost
= mips_address_insns (addr
, mode
, true);
3932 *total
= COSTS_N_INSNS (cost
+ 1);
3935 /* Check for a scaled indexed address. */
3936 if (mips_lwxs_address_p (addr
)
3937 || mips_lx_address_p (addr
, mode
))
3939 *total
= COSTS_N_INSNS (2);
3942 /* Otherwise use the default handling. */
3946 *total
= COSTS_N_INSNS (6);
3950 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3954 /* Check for a *clear_upper32 pattern and treat it like a zero
3955 extension. See the pattern's comment for details. */
3958 && CONST_INT_P (XEXP (x
, 1))
3959 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3961 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3962 + set_src_cost (XEXP (x
, 0), mode
, speed
));
3965 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3967 rtx op
= XEXP (x
, 0);
3968 if (GET_CODE (op
) == ASHIFT
3969 && CONST_INT_P (XEXP (op
, 1))
3970 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3972 *total
= COSTS_N_INSNS (1);
3973 *total
+= set_src_cost (XEXP (op
, 0), mode
, speed
);
3977 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3978 a single instruction. */
3980 && GET_CODE (XEXP (x
, 0)) == NOT
3981 && GET_CODE (XEXP (x
, 1)) == NOT
)
3983 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
3984 *total
= (COSTS_N_INSNS (cost
)
3985 + set_src_cost (XEXP (XEXP (x
, 0), 0), mode
, speed
)
3986 + set_src_cost (XEXP (XEXP (x
, 1), 0), mode
, speed
));
3994 /* Double-word operations use two single-word operations. */
3995 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
4004 if (CONSTANT_P (XEXP (x
, 1)))
4005 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4008 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
4014 *total
= mips_cost
->fp_add
;
4016 *total
= COSTS_N_INSNS (4);
4020 /* Low-part immediates need an extended MIPS16 instruction. */
4021 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
4022 + set_src_cost (XEXP (x
, 0), mode
, speed
));
4037 /* Branch comparisons have VOIDmode, so use the first operand's
4039 mode
= GET_MODE (XEXP (x
, 0));
4040 if (FLOAT_MODE_P (mode
))
4042 *total
= mips_cost
->fp_add
;
4045 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4050 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
&& !HONOR_SIGNED_ZEROS (mode
))
4052 /* See if we can use NMADD or NMSUB via the *nmadd4<mode>_fastmath
4053 or *nmsub4<mode>_fastmath patterns. These patterns check for
4054 HONOR_SIGNED_ZEROS so we check here too. */
4055 rtx op0
= XEXP (x
, 0);
4056 rtx op1
= XEXP (x
, 1);
4057 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4059 *total
= (mips_fp_mult_cost (mode
)
4060 + set_src_cost (XEXP (XEXP (op0
, 0), 0), mode
, speed
)
4061 + set_src_cost (XEXP (op0
, 1), mode
, speed
)
4062 + set_src_cost (op1
, mode
, speed
));
4065 if (GET_CODE (op1
) == MULT
)
4067 *total
= (mips_fp_mult_cost (mode
)
4068 + set_src_cost (op0
, mode
, speed
)
4069 + set_src_cost (XEXP (op1
, 0), mode
, speed
)
4070 + set_src_cost (XEXP (op1
, 1), mode
, speed
));
4079 /* If this is part of a MADD or MSUB, treat the PLUS as
4081 if (ISA_HAS_UNFUSED_MADD4
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4084 *total
= mips_cost
->fp_add
;
4088 /* If it's an add + mult (which is equivalent to shift left) and
4089 it's immediate operand satisfies const_immlsa_operand predicate. */
4090 if (((ISA_HAS_LSA
&& mode
== SImode
)
4091 || (ISA_HAS_DLSA
&& mode
== DImode
))
4092 && GET_CODE (XEXP (x
, 0)) == MULT
)
4094 rtx op2
= XEXP (XEXP (x
, 0), 1);
4095 if (const_immlsa_operand (op2
, mode
))
4097 *total
= (COSTS_N_INSNS (1)
4098 + set_src_cost (XEXP (XEXP (x
, 0), 0), mode
, speed
)
4099 + set_src_cost (XEXP (x
, 1), mode
, speed
));
4104 /* Double-word operations require three single-word operations and
4105 an SLTU. The MIPS16 version then needs to move the result of
4106 the SLTU from $24 to a MIPS16 register. */
4107 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4108 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4113 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
)
4115 /* See if we can use NMADD or NMSUB via the *nmadd4<mode> or
4116 *nmsub4<mode> patterns. */
4117 rtx op
= XEXP (x
, 0);
4118 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4119 && GET_CODE (XEXP (op
, 0)) == MULT
)
4121 *total
= (mips_fp_mult_cost (mode
)
4122 + set_src_cost (XEXP (XEXP (op
, 0), 0), mode
, speed
)
4123 + set_src_cost (XEXP (XEXP (op
, 0), 1), mode
, speed
)
4124 + set_src_cost (XEXP (op
, 1), mode
, speed
));
4130 *total
= mips_cost
->fp_add
;
4132 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4136 *total
= mips_fp_mult_cost (mode
);
4141 *total
= mips_fp_mult_cost (mode
);
4142 else if (mode
== DImode
&& !TARGET_64BIT
)
4143 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4144 where the mulsidi3 always includes an MFHI and an MFLO. */
4146 ? mips_cost
->int_mult_si
* 3 + 6
4147 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4149 *total
= COSTS_N_INSNS ((ISA_HAS_MUL3
|| ISA_HAS_R6MUL
) ? 1 : 2) + 1;
4150 else if (mode
== DImode
)
4151 *total
= mips_cost
->int_mult_di
;
4153 *total
= mips_cost
->int_mult_si
;
4157 /* Check for a reciprocal. */
4159 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4160 && flag_unsafe_math_optimizations
4161 && XEXP (x
, 0) == CONST1_RTX (mode
))
4163 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4164 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4165 division as being free. */
4166 *total
= set_src_cost (XEXP (x
, 1), mode
, speed
);
4168 *total
= (mips_fp_div_cost (mode
)
4169 + set_src_cost (XEXP (x
, 1), mode
, speed
));
4178 *total
= mips_fp_div_cost (mode
);
4187 /* It is our responsibility to make division by a power of 2
4188 as cheap as 2 register additions if we want the division
4189 expanders to be used for such operations; see the setting
4190 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4191 should always produce shorter code than using
4192 expand_sdiv2_pow2. */
4194 && CONST_INT_P (XEXP (x
, 1))
4195 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4197 *total
= COSTS_N_INSNS (2);
4198 *total
+= set_src_cost (XEXP (x
, 0), mode
, speed
);
4201 *total
= COSTS_N_INSNS (mips_idiv_insns ());
4203 else if (mode
== DImode
)
4204 *total
= mips_cost
->int_div_di
;
4206 *total
= mips_cost
->int_div_si
;
4210 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4214 if (outer_code
== SET
4216 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4217 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4218 && GET_MODE (XEXP (x
, 0)) == QImode
4219 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4221 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
, speed
);
4224 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4227 /* Costings for highpart multiplies. Matching patterns of the form:
4229 (lshiftrt:DI (mult:DI (sign_extend:DI (...)
4230 (sign_extend:DI (...))
4234 && (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4235 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
4236 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4237 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) == 32
4238 && GET_MODE (XEXP (x
, 0)) == DImode
)
4240 && INTVAL (XEXP (XEXP (x
, 0), 1)) == 64
4241 && GET_MODE (XEXP (x
, 0)) == TImode
))
4242 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4243 && ((GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
4244 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SIGN_EXTEND
)
4245 || (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4246 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4250 *total
= COSTS_N_INSNS (1) + 1;
4251 else if (mode
== DImode
)
4252 *total
= mips_cost
->int_mult_di
;
4254 *total
= mips_cost
->int_mult_si
;
4256 /* Sign extension is free, zero extension costs for DImode when
4257 on a 64bit core / when DMUL is present. */
4258 for (int i
= 0; i
< 2; ++i
)
4260 rtx op
= XEXP (XEXP (XEXP (x
, 0), 0), i
);
4262 && GET_CODE (op
) == ZERO_EXTEND
4263 && GET_MODE (op
) == DImode
)
4264 *total
+= rtx_cost (op
, DImode
, MULT
, i
, speed
);
4266 *total
+= rtx_cost (XEXP (op
, 0), VOIDmode
, GET_CODE (op
),
4275 case UNSIGNED_FLOAT
:
4278 case FLOAT_TRUNCATE
:
4279 *total
= mips_cost
->fp_add
;
4283 if (register_operand (SET_DEST (x
), VOIDmode
)
4284 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4286 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4296 /* Implement TARGET_ADDRESS_COST. */
4299 mips_address_cost (rtx addr
, machine_mode mode
,
4300 addr_space_t as ATTRIBUTE_UNUSED
,
4301 bool speed ATTRIBUTE_UNUSED
)
4303 return mips_address_insns (addr
, mode
, false);
4306 /* Information about a single instruction in a multi-instruction
4308 struct mips_multi_member
{
4309 /* True if this is a label, false if it is code. */
4312 /* The output_asm_insn format of the instruction. */
4315 /* The operands to the instruction. */
4316 rtx operands
[MAX_RECOG_OPERANDS
];
4318 typedef struct mips_multi_member mips_multi_member
;
4320 /* The instructions that make up the current multi-insn sequence. */
4321 static vec
<mips_multi_member
> mips_multi_members
;
4323 /* How many instructions (as opposed to labels) are in the current
4324 multi-insn sequence. */
4325 static unsigned int mips_multi_num_insns
;
4327 /* Start a new multi-insn sequence. */
4330 mips_multi_start (void)
4332 mips_multi_members
.truncate (0);
4333 mips_multi_num_insns
= 0;
4336 /* Add a new, uninitialized member to the current multi-insn sequence. */
4338 static struct mips_multi_member
*
4339 mips_multi_add (void)
4341 mips_multi_member empty
;
4342 return mips_multi_members
.safe_push (empty
);
4345 /* Add a normal insn with the given asm format to the current multi-insn
4346 sequence. The other arguments are a null-terminated list of operands. */
4349 mips_multi_add_insn (const char *format
, ...)
4351 struct mips_multi_member
*member
;
4356 member
= mips_multi_add ();
4357 member
->is_label_p
= false;
4358 member
->format
= format
;
4359 va_start (ap
, format
);
4361 while ((op
= va_arg (ap
, rtx
)))
4362 member
->operands
[i
++] = op
;
4364 mips_multi_num_insns
++;
4367 /* Add the given label definition to the current multi-insn sequence.
4368 The definition should include the colon. */
4371 mips_multi_add_label (const char *label
)
4373 struct mips_multi_member
*member
;
4375 member
= mips_multi_add ();
4376 member
->is_label_p
= true;
4377 member
->format
= label
;
4380 /* Return the index of the last member of the current multi-insn sequence. */
4383 mips_multi_last_index (void)
4385 return mips_multi_members
.length () - 1;
4388 /* Add a copy of an existing instruction to the current multi-insn
4389 sequence. I is the index of the instruction that should be copied. */
4392 mips_multi_copy_insn (unsigned int i
)
4394 struct mips_multi_member
*member
;
4396 member
= mips_multi_add ();
4397 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4398 gcc_assert (!member
->is_label_p
);
4401 /* Change the operand of an existing instruction in the current
4402 multi-insn sequence. I is the index of the instruction,
4403 OP is the index of the operand, and X is the new value. */
4406 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4408 mips_multi_members
[i
].operands
[op
] = x
;
4411 /* Write out the asm code for the current multi-insn sequence. */
4414 mips_multi_write (void)
4416 struct mips_multi_member
*member
;
4419 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4420 if (member
->is_label_p
)
4421 fprintf (asm_out_file
, "%s\n", member
->format
);
4423 output_asm_insn (member
->format
, member
->operands
);
4426 /* Return one word of double-word value OP, taking into account the fixed
4427 endianness of certain registers. HIGH_P is true to select the high part,
4428 false to select the low part. */
4431 mips_subword (rtx op
, bool high_p
)
4433 unsigned int byte
, offset
;
4436 mode
= GET_MODE (op
);
4437 if (mode
== VOIDmode
)
4438 mode
= TARGET_64BIT
? TImode
: DImode
;
4440 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4441 byte
= UNITS_PER_WORD
;
4445 if (FP_REG_RTX_P (op
))
4447 /* Paired FPRs are always ordered little-endian. */
4448 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4449 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4453 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4455 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4458 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4459 SPLIT_TYPE is the condition under which moves should be split. */
4462 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4464 return ((split_type
!= SPLIT_FOR_SPEED
4465 || mips_tuning_info
.fast_mult_zero_zero_p
)
4466 && src
== const0_rtx
4468 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4469 && (ISA_HAS_DSP_MULT
4470 ? ACC_REG_P (REGNO (dest
))
4471 : MD_REG_P (REGNO (dest
))));
4474 /* Return true if a move from SRC to DEST should be split into two.
4475 SPLIT_TYPE describes the split condition. */
4478 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4480 /* Check whether the move can be done using some variant of MULT $0,$0. */
4481 if (mips_mult_move_p (dest
, src
, split_type
))
4484 /* FPR-to-FPR moves can be done in a single instruction, if they're
4486 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4487 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4490 /* Check for floating-point loads and stores. */
4491 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4493 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4495 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4499 /* Otherwise split all multiword moves. */
4500 return size
> UNITS_PER_WORD
;
4503 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4504 SPLIT_TYPE describes the split condition. */
4507 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4511 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4512 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4514 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4515 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4516 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4517 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4518 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4519 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4520 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4521 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4522 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4523 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4524 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4525 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4526 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4527 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4531 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4533 low_dest
= mips_subword (dest
, false);
4534 mips_emit_move (low_dest
, mips_subword (src
, false));
4536 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4538 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4540 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4542 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4544 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4546 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4550 /* The operation can be split into two normal moves. Decide in
4551 which order to do them. */
4552 low_dest
= mips_subword (dest
, false);
4553 if (REG_P (low_dest
)
4554 && reg_overlap_mentioned_p (low_dest
, src
))
4556 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4557 mips_emit_move (low_dest
, mips_subword (src
, false));
4561 mips_emit_move (low_dest
, mips_subword (src
, false));
4562 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4567 /* Return the split type for instruction INSN. */
4569 static enum mips_split_type
4570 mips_insn_split_type (rtx insn
)
4572 basic_block bb
= BLOCK_FOR_INSN (insn
);
4575 if (optimize_bb_for_speed_p (bb
))
4576 return SPLIT_FOR_SPEED
;
4578 return SPLIT_FOR_SIZE
;
4580 /* Once CFG information has been removed, we should trust the optimization
4581 decisions made by previous passes and only split where necessary. */
4582 return SPLIT_IF_NECESSARY
;
4585 /* Return true if a move from SRC to DEST in INSN should be split. */
4588 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4590 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4593 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4597 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4599 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4602 /* Return the appropriate instructions to move SRC into DEST. Assume
4603 that SRC is operand 1 and DEST is operand 0. */
4606 mips_output_move (rtx dest
, rtx src
)
4608 enum rtx_code dest_code
, src_code
;
4610 enum mips_symbol_type symbol_type
;
4613 dest_code
= GET_CODE (dest
);
4614 src_code
= GET_CODE (src
);
4615 mode
= GET_MODE (dest
);
4616 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4618 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4621 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4622 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4624 if (dest_code
== REG
)
4626 if (GP_REG_P (REGNO (dest
)))
4627 return "move\t%0,%z1";
4629 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4631 if (ISA_HAS_DSP_MULT
)
4632 return "mult\t%q0,%.,%.";
4634 return "mult\t%.,%.";
4637 /* Moves to HI are handled by special .md insns. */
4638 if (REGNO (dest
) == LO_REGNUM
)
4641 if (DSP_ACC_REG_P (REGNO (dest
)))
4643 static char retval
[] = "mt__\t%z1,%q0";
4645 retval
[2] = reg_names
[REGNO (dest
)][4];
4646 retval
[3] = reg_names
[REGNO (dest
)][5];
4650 if (FP_REG_P (REGNO (dest
)))
4651 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4653 if (ALL_COP_REG_P (REGNO (dest
)))
4655 static char retval
[] = "dmtc_\t%z1,%0";
4657 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4658 return dbl_p
? retval
: retval
+ 1;
4661 if (dest_code
== MEM
)
4662 switch (GET_MODE_SIZE (mode
))
4664 case 1: return "sb\t%z1,%0";
4665 case 2: return "sh\t%z1,%0";
4666 case 4: return "sw\t%z1,%0";
4667 case 8: return "sd\t%z1,%0";
4670 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4672 if (src_code
== REG
)
4674 /* Moves from HI are handled by special .md insns. */
4675 if (REGNO (src
) == LO_REGNUM
)
4677 /* When generating VR4120 or VR4130 code, we use MACC and
4678 DMACC instead of MFLO. This avoids both the normal
4679 MIPS III HI/LO hazards and the errata related to
4682 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4686 if (DSP_ACC_REG_P (REGNO (src
)))
4688 static char retval
[] = "mf__\t%0,%q1";
4690 retval
[2] = reg_names
[REGNO (src
)][4];
4691 retval
[3] = reg_names
[REGNO (src
)][5];
4695 if (FP_REG_P (REGNO (src
)))
4696 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4698 if (ALL_COP_REG_P (REGNO (src
)))
4700 static char retval
[] = "dmfc_\t%0,%1";
4702 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4703 return dbl_p
? retval
: retval
+ 1;
4707 if (src_code
== MEM
)
4708 switch (GET_MODE_SIZE (mode
))
4710 case 1: return "lbu\t%0,%1";
4711 case 2: return "lhu\t%0,%1";
4712 case 4: return "lw\t%0,%1";
4713 case 8: return "ld\t%0,%1";
4716 if (src_code
== CONST_INT
)
4718 /* Don't use the X format for the operand itself, because that
4719 will give out-of-range numbers for 64-bit hosts and 32-bit
4722 return "li\t%0,%1\t\t\t# %X1";
4724 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4727 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4731 if (src_code
== HIGH
)
4732 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4734 if (CONST_GP_P (src
))
4735 return "move\t%0,%1";
4737 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4738 && mips_lo_relocs
[symbol_type
] != 0)
4740 /* A signed 16-bit constant formed by applying a relocation
4741 operator to a symbolic address. */
4742 gcc_assert (!mips_split_p
[symbol_type
]);
4743 return "li\t%0,%R1";
4746 if (symbolic_operand (src
, VOIDmode
))
4748 gcc_assert (TARGET_MIPS16
4749 ? TARGET_MIPS16_TEXT_LOADS
4750 : !TARGET_EXPLICIT_RELOCS
);
4751 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4754 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4756 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4758 if (GET_MODE (dest
) == V2SFmode
)
4759 return "mov.ps\t%0,%1";
4761 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4764 if (dest_code
== MEM
)
4765 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4767 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4769 if (src_code
== MEM
)
4770 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4772 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4774 static char retval
[] = "l_c_\t%0,%1";
4776 retval
[1] = (dbl_p
? 'd' : 'w');
4777 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4780 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4782 static char retval
[] = "s_c_\t%1,%0";
4784 retval
[1] = (dbl_p
? 'd' : 'w');
4785 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4791 /* Return true if CMP1 is a suitable second operand for integer ordering
4792 test CODE. See also the *sCC patterns in mips.md. */
4795 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4801 return reg_or_0_operand (cmp1
, VOIDmode
);
4805 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4809 return arith_operand (cmp1
, VOIDmode
);
4812 return sle_operand (cmp1
, VOIDmode
);
4815 return sleu_operand (cmp1
, VOIDmode
);
4822 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4823 integer ordering test *CODE, or if an equivalent combination can
4824 be formed by adjusting *CODE and *CMP1. When returning true, update
4825 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4829 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4832 HOST_WIDE_INT plus_one
;
4834 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4837 if (CONST_INT_P (*cmp1
))
4841 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4842 if (INTVAL (*cmp1
) < plus_one
)
4845 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4851 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4855 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4866 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4867 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4868 is nonnull, it's OK to set TARGET to the inverse of the result and
4869 flip *INVERT_PTR instead. */
4872 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4873 rtx target
, rtx cmp0
, rtx cmp1
)
4877 /* First see if there is a MIPS instruction that can do this operation.
4878 If not, try doing the same for the inverse operation. If that also
4879 fails, force CMP1 into a register and try again. */
4880 mode
= GET_MODE (cmp0
);
4881 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4882 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4885 enum rtx_code inv_code
= reverse_condition (code
);
4886 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4888 cmp1
= force_reg (mode
, cmp1
);
4889 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4891 else if (invert_ptr
== 0)
4895 inv_target
= mips_force_binary (GET_MODE (target
),
4896 inv_code
, cmp0
, cmp1
);
4897 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4901 *invert_ptr
= !*invert_ptr
;
4902 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4907 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4908 The register will have the same mode as CMP0. */
4911 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4913 if (cmp1
== const0_rtx
)
4916 if (uns_arith_operand (cmp1
, VOIDmode
))
4917 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4918 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4920 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4921 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4924 /* Convert *CODE into a code that can be used in a floating-point
4925 scc instruction (C.cond.fmt). Return true if the values of
4926 the condition code registers will be inverted, with 0 indicating
4927 that the condition holds. */
4930 mips_reversed_fp_cond (enum rtx_code
*code
)
4937 *code
= reverse_condition_maybe_unordered (*code
);
4945 /* Allocate a floating-point condition-code register of mode MODE.
4947 These condition code registers are used for certain kinds
4948 of compound operation, such as compare and branches, vconds,
4949 and built-in functions. At expand time, their use is entirely
4950 controlled by MIPS-specific code and is entirely internal
4951 to these compound operations.
4953 We could (and did in the past) expose condition-code values
4954 as pseudo registers and leave the register allocator to pick
4955 appropriate registers. The problem is that it is not practically
4956 possible for the rtl optimizers to guarantee that no spills will
4957 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4958 therefore need spill and reload sequences to handle the worst case.
4960 Although such sequences do exist, they are very expensive and are
4961 not something we'd want to use. This is especially true of CCV2 and
4962 CCV4, where all the shuffling would greatly outweigh whatever benefit
4963 the vectorization itself provides.
4965 The main benefit of having more than one condition-code register
4966 is to allow the pipelining of operations, especially those involving
4967 comparisons and conditional moves. We don't really expect the
4968 registers to be live for long periods, and certainly never want
4969 them to be live across calls.
4971 Also, there should be no penalty attached to using all the available
4972 registers. They are simply bits in the same underlying FPU control
4975 We therefore expose the hardware registers from the outset and use
4976 a simple round-robin allocation scheme. */
4979 mips_allocate_fcc (machine_mode mode
)
4981 unsigned int regno
, count
;
4983 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4987 else if (mode
== CCV2mode
)
4989 else if (mode
== CCV4mode
)
4994 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4995 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4996 cfun
->machine
->next_fcc
= 0;
4997 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4998 cfun
->machine
->next_fcc
+= count
;
4999 return gen_rtx_REG (mode
, regno
);
5002 /* Convert a comparison into something that can be used in a branch or
5003 conditional move. On entry, *OP0 and *OP1 are the values being
5004 compared and *CODE is the code used to compare them.
5006 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
5007 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
5008 otherwise any standard branch condition can be used. The standard branch
5011 - EQ or NE between two registers.
5012 - any comparison between a register and zero. */
5015 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
5020 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
5022 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
5024 else if (*code
== EQ
|| *code
== NE
)
5028 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
5032 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5036 /* The comparison needs a separate scc instruction. Store the
5037 result of the scc in *OP0 and compare it against zero. */
5038 bool invert
= false;
5039 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
5040 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
5041 *code
= (invert
? EQ
: NE
);
5045 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
5047 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
5048 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
5054 enum rtx_code cmp_code
;
5056 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt
5057 comparison to set a register. The branch or conditional move will
5058 then compare that register against zero.
5060 Set CMP_CODE to the code of the comparison instruction and
5061 *CODE to the code that the branch or move should use. */
5065 /* All FP conditions can be implemented directly with CMP.cond.fmt
5066 or by reversing the operands. */
5068 *op0
= gen_reg_rtx (CCFmode
);
5072 /* Three FP conditions cannot be implemented by reversing the
5073 operands for C.cond.fmt, instead a reversed condition code is
5074 required and a test for false. */
5075 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
5077 *op0
= mips_allocate_fcc (CCmode
);
5079 *op0
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
5083 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
5087 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
5088 and OPERAND[3]. Store the result in OPERANDS[0].
5090 On 64-bit targets, the mode of the comparison and target will always be
5091 SImode, thus possibly narrower than that of the comparison's operands. */
5094 mips_expand_scc (rtx operands
[])
5096 rtx target
= operands
[0];
5097 enum rtx_code code
= GET_CODE (operands
[1]);
5098 rtx op0
= operands
[2];
5099 rtx op1
= operands
[3];
5101 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
5103 if (code
== EQ
|| code
== NE
)
5106 && reg_imm10_operand (op1
, GET_MODE (op1
)))
5107 mips_emit_binary (code
, target
, op0
, op1
);
5110 rtx zie
= mips_zero_if_equal (op0
, op1
);
5111 mips_emit_binary (code
, target
, zie
, const0_rtx
);
5115 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
5118 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5119 CODE and jump to OPERANDS[3] if the condition holds. */
5122 mips_expand_conditional_branch (rtx
*operands
)
5124 enum rtx_code code
= GET_CODE (operands
[0]);
5125 rtx op0
= operands
[1];
5126 rtx op1
= operands
[2];
5129 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5130 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5131 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5136 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5137 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5140 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5141 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5146 reversed_p
= mips_reversed_fp_cond (&cond
);
5147 cmp_result
= mips_allocate_fcc (CCV2mode
);
5148 emit_insn (gen_scc_ps (cmp_result
,
5149 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5151 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5154 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5158 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5159 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5162 mips_expand_conditional_move (rtx
*operands
)
5165 enum rtx_code code
= GET_CODE (operands
[1]);
5166 rtx op0
= XEXP (operands
[1], 0);
5167 rtx op1
= XEXP (operands
[1], 1);
5169 mips_emit_compare (&code
, &op0
, &op1
, true);
5170 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5172 /* There is no direct support for general conditional GP move involving
5173 two registers using SEL. */
5175 && INTEGRAL_MODE_P (GET_MODE (operands
[2]))
5176 && register_operand (operands
[2], VOIDmode
)
5177 && register_operand (operands
[3], VOIDmode
))
5179 machine_mode mode
= GET_MODE (operands
[0]);
5180 rtx temp
= gen_reg_rtx (mode
);
5181 rtx temp2
= gen_reg_rtx (mode
);
5183 emit_insn (gen_rtx_SET (temp
,
5184 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5185 operands
[2], const0_rtx
)));
5187 /* Flip the test for the second operand. */
5188 cond
= gen_rtx_fmt_ee ((code
== EQ
) ? NE
: EQ
, GET_MODE (op0
), op0
, op1
);
5190 emit_insn (gen_rtx_SET (temp2
,
5191 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5192 operands
[3], const0_rtx
)));
5194 /* Merge the two results, at least one is guaranteed to be zero. */
5195 emit_insn (gen_rtx_SET (operands
[0], gen_rtx_IOR (mode
, temp
, temp2
)));
5199 if (FLOAT_MODE_P (GET_MODE (operands
[2])) && !ISA_HAS_SEL
)
5201 operands
[2] = force_reg (GET_MODE (operands
[0]), operands
[2]);
5202 operands
[3] = force_reg (GET_MODE (operands
[0]), operands
[3]);
5205 emit_insn (gen_rtx_SET (operands
[0],
5206 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5207 operands
[2], operands
[3])));
5211 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5214 mips_expand_conditional_trap (rtx comparison
)
5220 /* MIPS conditional trap instructions don't have GT or LE flavors,
5221 so we must swap the operands and convert to LT and GE respectively. */
5222 code
= GET_CODE (comparison
);
5229 code
= swap_condition (code
);
5230 op0
= XEXP (comparison
, 1);
5231 op1
= XEXP (comparison
, 0);
5235 op0
= XEXP (comparison
, 0);
5236 op1
= XEXP (comparison
, 1);
5240 mode
= GET_MODE (XEXP (comparison
, 0));
5241 op0
= force_reg (mode
, op0
);
5242 if (!(ISA_HAS_COND_TRAPI
5243 ? arith_operand (op1
, mode
)
5244 : reg_or_0_operand (op1
, mode
)))
5245 op1
= force_reg (mode
, op1
);
5247 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5248 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5252 /* Initialize *CUM for a call to a function of type FNTYPE. */
5255 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5257 memset (cum
, 0, sizeof (*cum
));
5258 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5259 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5262 /* Fill INFO with information about a single argument. CUM is the
5263 cumulative state for earlier arguments. MODE is the mode of this
5264 argument and TYPE is its type (if known). NAMED is true if this
5265 is a named (fixed) argument rather than a variable one. */
5268 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5269 machine_mode mode
, const_tree type
, bool named
)
5271 bool doubleword_aligned_p
;
5272 unsigned int num_bytes
, num_words
, max_regs
;
5274 /* Work out the size of the argument. */
5275 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5276 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5278 /* Decide whether it should go in a floating-point register, assuming
5279 one is free. Later code checks for availability.
5281 The checks against UNITS_PER_FPVALUE handle the soft-float and
5282 single-float cases. */
5286 /* The EABI conventions have traditionally been defined in terms
5287 of TYPE_MODE, regardless of the actual type. */
5288 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5289 || mode
== V2SFmode
)
5290 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5295 /* Only leading floating-point scalars are passed in
5296 floating-point registers. We also handle vector floats the same
5297 say, which is OK because they are not covered by the standard ABI. */
5298 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5299 info
->fpr_p
= (!cum
->gp_reg_found
5300 && cum
->arg_number
< 2
5302 || SCALAR_FLOAT_TYPE_P (type
)
5303 || VECTOR_FLOAT_TYPE_P (type
))
5304 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5305 || mode
== V2SFmode
)
5306 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5311 /* Scalar, complex and vector floating-point types are passed in
5312 floating-point registers, as long as this is a named rather
5313 than a variable argument. */
5314 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5315 info
->fpr_p
= (named
5316 && (type
== 0 || FLOAT_TYPE_P (type
))
5317 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5318 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5319 || mode
== V2SFmode
)
5320 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5322 /* ??? According to the ABI documentation, the real and imaginary
5323 parts of complex floats should be passed in individual registers.
5324 The real and imaginary parts of stack arguments are supposed
5325 to be contiguous and there should be an extra word of padding
5328 This has two problems. First, it makes it impossible to use a
5329 single "void *" va_list type, since register and stack arguments
5330 are passed differently. (At the time of writing, MIPSpro cannot
5331 handle complex float varargs correctly.) Second, it's unclear
5332 what should happen when there is only one register free.
5334 For now, we assume that named complex floats should go into FPRs
5335 if there are two FPRs free, otherwise they should be passed in the
5336 same way as a struct containing two floats. */
5338 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5339 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5341 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5342 info
->fpr_p
= false;
5352 /* See whether the argument has doubleword alignment. */
5353 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5356 /* Set REG_OFFSET to the register count we're interested in.
5357 The EABI allocates the floating-point registers separately,
5358 but the other ABIs allocate them like integer registers. */
5359 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5363 /* Advance to an even register if the argument is doubleword-aligned. */
5364 if (doubleword_aligned_p
)
5365 info
->reg_offset
+= info
->reg_offset
& 1;
5367 /* Work out the offset of a stack argument. */
5368 info
->stack_offset
= cum
->stack_words
;
5369 if (doubleword_aligned_p
)
5370 info
->stack_offset
+= info
->stack_offset
& 1;
5372 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5374 /* Partition the argument between registers and stack. */
5375 info
->reg_words
= MIN (num_words
, max_regs
);
5376 info
->stack_words
= num_words
- info
->reg_words
;
5379 /* INFO describes a register argument that has the normal format for the
5380 argument's mode. Return the register it uses, assuming that FPRs are
5381 available if HARD_FLOAT_P. */
5384 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5386 if (!info
->fpr_p
|| !hard_float_p
)
5387 return GP_ARG_FIRST
+ info
->reg_offset
;
5388 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5389 /* In o32, the second argument is always passed in $f14
5390 for TARGET_DOUBLE_FLOAT, regardless of whether the
5391 first argument was a word or doubleword. */
5392 return FP_ARG_FIRST
+ 2;
5394 return FP_ARG_FIRST
+ info
->reg_offset
;
5397 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5400 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5402 return !TARGET_OLDABI
;
5405 /* Implement TARGET_FUNCTION_ARG. */
5408 mips_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
5409 const_tree type
, bool named
)
5411 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5412 struct mips_arg_info info
;
5414 /* We will be called with a mode of VOIDmode after the last argument
5415 has been seen. Whatever we return will be passed to the call expander.
5416 If we need a MIPS16 fp_code, return a REG with the code stored as
5418 if (mode
== VOIDmode
)
5420 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5421 return gen_rtx_REG ((machine_mode
) cum
->fp_code
, 0);
5426 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5428 /* Return straight away if the whole argument is passed on the stack. */
5429 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5432 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5433 contains a double in its entirety, then that 64-bit chunk is passed
5434 in a floating-point register. */
5436 && TARGET_HARD_FLOAT
5439 && TREE_CODE (type
) == RECORD_TYPE
5440 && TYPE_SIZE_UNIT (type
)
5441 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5445 /* First check to see if there is any such field. */
5446 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5447 if (TREE_CODE (field
) == FIELD_DECL
5448 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5449 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5450 && tree_fits_shwi_p (bit_position (field
))
5451 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5456 /* Now handle the special case by returning a PARALLEL
5457 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5458 chunks are passed in registers. */
5460 HOST_WIDE_INT bitpos
;
5463 /* assign_parms checks the mode of ENTRY_PARM, so we must
5464 use the actual mode here. */
5465 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5468 field
= TYPE_FIELDS (type
);
5469 for (i
= 0; i
< info
.reg_words
; i
++)
5473 for (; field
; field
= DECL_CHAIN (field
))
5474 if (TREE_CODE (field
) == FIELD_DECL
5475 && int_bit_position (field
) >= bitpos
)
5479 && int_bit_position (field
) == bitpos
5480 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5481 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5482 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5484 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5487 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5488 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5490 bitpos
+= BITS_PER_WORD
;
5496 /* Handle the n32/n64 conventions for passing complex floating-point
5497 arguments in FPR pairs. The real part goes in the lower register
5498 and the imaginary part goes in the upper register. */
5501 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5507 inner
= GET_MODE_INNER (mode
);
5508 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5509 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5511 /* Real part in registers, imaginary part on stack. */
5512 gcc_assert (info
.stack_words
== info
.reg_words
);
5513 return gen_rtx_REG (inner
, regno
);
5517 gcc_assert (info
.stack_words
== 0);
5518 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5519 gen_rtx_REG (inner
, regno
),
5521 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5523 regno
+ info
.reg_words
/ 2),
5524 GEN_INT (GET_MODE_SIZE (inner
)));
5525 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5529 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5532 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5535 mips_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
5536 const_tree type
, bool named
)
5538 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5539 struct mips_arg_info info
;
5541 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5544 cum
->gp_reg_found
= true;
5546 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5547 an explanation of what this code does. It assumes that we're using
5548 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5550 if (cum
->arg_number
< 2 && info
.fpr_p
)
5551 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5553 /* Advance the register count. This has the effect of setting
5554 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5555 argument required us to skip the final GPR and pass the whole
5556 argument on the stack. */
5557 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5558 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5559 else if (info
.reg_words
> 0)
5560 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5562 /* Advance the stack word count. */
5563 if (info
.stack_words
> 0)
5564 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5569 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5572 mips_arg_partial_bytes (cumulative_args_t cum
,
5573 machine_mode mode
, tree type
, bool named
)
5575 struct mips_arg_info info
;
5577 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5578 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5581 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5582 least PARM_BOUNDARY bits of alignment, but will be given anything up
5583 to STACK_BOUNDARY bits if the type requires it. */
5586 mips_function_arg_boundary (machine_mode mode
, const_tree type
)
5588 unsigned int alignment
;
5590 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5591 if (alignment
< PARM_BOUNDARY
)
5592 alignment
= PARM_BOUNDARY
;
5593 if (alignment
> STACK_BOUNDARY
)
5594 alignment
= STACK_BOUNDARY
;
5598 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
5601 mips_get_reg_raw_mode (int regno
)
5603 if (TARGET_FLOATXX
&& FP_REG_P (regno
))
5605 return default_get_reg_raw_mode (regno
);
5608 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5609 upward rather than downward. In other words, return true if the
5610 first byte of the stack slot has useful data, false if the last
5614 mips_pad_arg_upward (machine_mode mode
, const_tree type
)
5616 /* On little-endian targets, the first byte of every stack argument
5617 is passed in the first byte of the stack slot. */
5618 if (!BYTES_BIG_ENDIAN
)
5621 /* Otherwise, integral types are padded downward: the last byte of a
5622 stack argument is passed in the last byte of the stack slot. */
5624 ? (INTEGRAL_TYPE_P (type
)
5625 || POINTER_TYPE_P (type
)
5626 || FIXED_POINT_TYPE_P (type
))
5627 : (SCALAR_INT_MODE_P (mode
)
5628 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5631 /* Big-endian o64 pads floating-point arguments downward. */
5632 if (mips_abi
== ABI_O64
)
5633 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5636 /* Other types are padded upward for o32, o64, n32 and n64. */
5637 if (mips_abi
!= ABI_EABI
)
5640 /* Arguments smaller than a stack slot are padded downward. */
5641 if (mode
!= BLKmode
)
5642 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5644 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5647 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5648 if the least significant byte of the register has useful data. Return
5649 the opposite if the most significant byte does. */
5652 mips_pad_reg_upward (machine_mode mode
, tree type
)
5654 /* No shifting is required for floating-point arguments. */
5655 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5656 return !BYTES_BIG_ENDIAN
;
5658 /* Otherwise, apply the same padding to register arguments as we do
5659 to stack arguments. */
5660 return mips_pad_arg_upward (mode
, type
);
5663 /* Return nonzero when an argument must be passed by reference. */
5666 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5667 machine_mode mode
, const_tree type
,
5668 bool named ATTRIBUTE_UNUSED
)
5670 if (mips_abi
== ABI_EABI
)
5674 /* ??? How should SCmode be handled? */
5675 if (mode
== DImode
|| mode
== DFmode
5676 || mode
== DQmode
|| mode
== UDQmode
5677 || mode
== DAmode
|| mode
== UDAmode
)
5680 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5681 return size
== -1 || size
> UNITS_PER_WORD
;
5685 /* If we have a variable-sized parameter, we have no choice. */
5686 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5690 /* Implement TARGET_CALLEE_COPIES. */
5693 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5694 machine_mode mode ATTRIBUTE_UNUSED
,
5695 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5697 return mips_abi
== ABI_EABI
&& named
;
5700 /* See whether VALTYPE is a record whose fields should be returned in
5701 floating-point registers. If so, return the number of fields and
5702 list them in FIELDS (which should have two elements). Return 0
5705 For n32 & n64, a structure with one or two fields is returned in
5706 floating-point registers as long as every field has a floating-point
5710 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5718 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5722 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5724 if (TREE_CODE (field
) != FIELD_DECL
)
5727 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5733 fields
[i
++] = field
;
5738 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5739 a value in the most significant part of $2/$3 if:
5741 - the target is big-endian;
5743 - the value has a structure or union type (we generalize this to
5744 cover aggregates from other languages too); and
5746 - the structure is not returned in floating-point registers. */
5749 mips_return_in_msb (const_tree valtype
)
5753 return (TARGET_NEWABI
5754 && TARGET_BIG_ENDIAN
5755 && AGGREGATE_TYPE_P (valtype
)
5756 && mips_fpr_return_fields (valtype
, fields
) == 0);
5759 /* Return true if the function return value MODE will get returned in a
5760 floating-point register. */
5763 mips_return_mode_in_fpr_p (machine_mode mode
)
5765 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5766 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5768 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5769 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5772 /* Return the representation of an FPR return register when the
5773 value being returned in FP_RETURN has mode VALUE_MODE and the
5774 return type itself has mode TYPE_MODE. On NewABI targets,
5775 the two modes may be different for structures like:
5777 struct __attribute__((packed)) foo { float f; }
5779 where we return the SFmode value of "f" in FP_RETURN, but where
5780 the structure itself has mode BLKmode. */
5783 mips_return_fpr_single (machine_mode type_mode
,
5784 machine_mode value_mode
)
5788 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5789 if (type_mode
!= value_mode
)
5791 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5792 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5797 /* Return a composite value in a pair of floating-point registers.
5798 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5799 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5802 For n32 & n64, $f0 always holds the first value and $f2 the second.
5803 Otherwise the values are packed together as closely as possible. */
5806 mips_return_fpr_pair (machine_mode mode
,
5807 machine_mode mode1
, HOST_WIDE_INT offset1
,
5808 machine_mode mode2
, HOST_WIDE_INT offset2
)
5812 inc
= (TARGET_NEWABI
|| mips_abi
== ABI_32
? 2 : MAX_FPRS_PER_FMT
);
5813 return gen_rtx_PARALLEL
5816 gen_rtx_EXPR_LIST (VOIDmode
,
5817 gen_rtx_REG (mode1
, FP_RETURN
),
5819 gen_rtx_EXPR_LIST (VOIDmode
,
5820 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5821 GEN_INT (offset2
))));
5825 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5826 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5827 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5830 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5839 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5840 func
= fn_decl_or_type
;
5844 mode
= TYPE_MODE (valtype
);
5845 unsigned_p
= TYPE_UNSIGNED (valtype
);
5847 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5848 return values, promote the mode here too. */
5849 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5851 /* Handle structures whose fields are returned in $f0/$f2. */
5852 switch (mips_fpr_return_fields (valtype
, fields
))
5855 return mips_return_fpr_single (mode
,
5856 TYPE_MODE (TREE_TYPE (fields
[0])));
5859 return mips_return_fpr_pair (mode
,
5860 TYPE_MODE (TREE_TYPE (fields
[0])),
5861 int_byte_position (fields
[0]),
5862 TYPE_MODE (TREE_TYPE (fields
[1])),
5863 int_byte_position (fields
[1]));
5866 /* If a value is passed in the most significant part of a register, see
5867 whether we have to round the mode up to a whole number of words. */
5868 if (mips_return_in_msb (valtype
))
5870 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5871 if (size
% UNITS_PER_WORD
!= 0)
5873 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5874 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5878 /* For EABI, the class of return register depends entirely on MODE.
5879 For example, "struct { some_type x; }" and "union { some_type x; }"
5880 are returned in the same way as a bare "some_type" would be.
5881 Other ABIs only use FPRs for scalar, complex or vector types. */
5882 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5883 return gen_rtx_REG (mode
, GP_RETURN
);
5888 /* Handle long doubles for n32 & n64. */
5890 return mips_return_fpr_pair (mode
,
5892 DImode
, GET_MODE_SIZE (mode
) / 2);
5894 if (mips_return_mode_in_fpr_p (mode
))
5896 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5897 return mips_return_fpr_pair (mode
,
5898 GET_MODE_INNER (mode
), 0,
5899 GET_MODE_INNER (mode
),
5900 GET_MODE_SIZE (mode
) / 2);
5902 return gen_rtx_REG (mode
, FP_RETURN
);
5906 return gen_rtx_REG (mode
, GP_RETURN
);
5909 /* Implement TARGET_FUNCTION_VALUE. */
5912 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5913 bool outgoing ATTRIBUTE_UNUSED
)
5915 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5918 /* Implement TARGET_LIBCALL_VALUE. */
5921 mips_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5923 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5926 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5928 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
5931 mips_function_value_regno_p (const unsigned int regno
)
5933 /* Most types only require one GPR or one FPR for return values but for
5934 hard-float two FPRs can be used for _Complex types (for all ABIs)
5935 and long doubles (for n64). */
5936 if (regno
== GP_RETURN
5937 || regno
== FP_RETURN
5938 || (FP_RETURN
!= GP_RETURN
5939 && regno
== FP_RETURN
+ 2))
5942 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
5943 This does not apply to o32 FPXX as floating-point function argument and
5944 return registers are described as 64-bit even though floating-point
5945 registers are primarily described as 32-bit internally.
5946 See: mips_get_reg_raw_mode. */
5947 if ((mips_abi
== ABI_32
&& TARGET_FLOAT32
)
5948 && FP_RETURN
!= GP_RETURN
5949 && (regno
== FP_RETURN
+ 1
5950 || regno
== FP_RETURN
+ 3))
5956 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5957 all BLKmode objects are returned in memory. Under the n32, n64
5958 and embedded ABIs, small structures are returned in a register.
5959 Objects with varying size must still be returned in memory, of
5963 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5965 return (TARGET_OLDABI
5966 ? TYPE_MODE (type
) == BLKmode
5967 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5970 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5973 mips_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
5974 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5977 CUMULATIVE_ARGS local_cum
;
5978 int gp_saved
, fp_saved
;
5980 /* The caller has advanced CUM up to, but not beyond, the last named
5981 argument. Advance a local copy of CUM past the last "real" named
5982 argument, to find out how many registers are left over. */
5983 local_cum
= *get_cumulative_args (cum
);
5984 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5987 /* Found out how many registers we need to save. */
5988 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5989 fp_saved
= (EABI_FLOAT_VARARGS_P
5990 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5999 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
6000 REG_PARM_STACK_SPACE (cfun
->decl
)
6001 - gp_saved
* UNITS_PER_WORD
);
6002 mem
= gen_frame_mem (BLKmode
, ptr
);
6003 set_mem_alias_set (mem
, get_varargs_alias_set ());
6005 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
6010 /* We can't use move_block_from_reg, because it will use
6015 /* Set OFF to the offset from virtual_incoming_args_rtx of
6016 the first float register. The FP save area lies below
6017 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
6018 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
6019 off
-= fp_saved
* UNITS_PER_FPREG
;
6021 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6023 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
6024 i
+= MAX_FPRS_PER_FMT
)
6028 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
6029 mem
= gen_frame_mem (mode
, ptr
);
6030 set_mem_alias_set (mem
, get_varargs_alias_set ());
6031 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
6032 off
+= UNITS_PER_HWFPVALUE
;
6036 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
6037 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
6038 + fp_saved
* UNITS_PER_FPREG
);
6041 /* Implement TARGET_BUILTIN_VA_LIST. */
6044 mips_build_builtin_va_list (void)
6046 if (EABI_FLOAT_VARARGS_P
)
6048 /* We keep 3 pointers, and two offsets.
6050 Two pointers are to the overflow area, which starts at the CFA.
6051 One of these is constant, for addressing into the GPR save area
6052 below it. The other is advanced up the stack through the
6055 The third pointer is to the bottom of the GPR save area.
6056 Since the FPR save area is just below it, we can address
6057 FPR slots off this pointer.
6059 We also keep two one-byte offsets, which are to be subtracted
6060 from the constant pointers to yield addresses in the GPR and
6061 FPR save areas. These are downcounted as float or non-float
6062 arguments are used, and when they get to zero, the argument
6063 must be obtained from the overflow region. */
6064 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
6067 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
6069 f_ovfl
= build_decl (BUILTINS_LOCATION
,
6070 FIELD_DECL
, get_identifier ("__overflow_argptr"),
6072 f_gtop
= build_decl (BUILTINS_LOCATION
,
6073 FIELD_DECL
, get_identifier ("__gpr_top"),
6075 f_ftop
= build_decl (BUILTINS_LOCATION
,
6076 FIELD_DECL
, get_identifier ("__fpr_top"),
6078 f_goff
= build_decl (BUILTINS_LOCATION
,
6079 FIELD_DECL
, get_identifier ("__gpr_offset"),
6080 unsigned_char_type_node
);
6081 f_foff
= build_decl (BUILTINS_LOCATION
,
6082 FIELD_DECL
, get_identifier ("__fpr_offset"),
6083 unsigned_char_type_node
);
6084 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
6085 warn on every user file. */
6086 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
6087 array
= build_array_type (unsigned_char_type_node
,
6088 build_index_type (index
));
6089 f_res
= build_decl (BUILTINS_LOCATION
,
6090 FIELD_DECL
, get_identifier ("__reserved"), array
);
6092 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
6093 DECL_FIELD_CONTEXT (f_gtop
) = record
;
6094 DECL_FIELD_CONTEXT (f_ftop
) = record
;
6095 DECL_FIELD_CONTEXT (f_goff
) = record
;
6096 DECL_FIELD_CONTEXT (f_foff
) = record
;
6097 DECL_FIELD_CONTEXT (f_res
) = record
;
6099 TYPE_FIELDS (record
) = f_ovfl
;
6100 DECL_CHAIN (f_ovfl
) = f_gtop
;
6101 DECL_CHAIN (f_gtop
) = f_ftop
;
6102 DECL_CHAIN (f_ftop
) = f_goff
;
6103 DECL_CHAIN (f_goff
) = f_foff
;
6104 DECL_CHAIN (f_foff
) = f_res
;
6106 layout_type (record
);
6110 /* Otherwise, we use 'void *'. */
6111 return ptr_type_node
;
6114 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6117 mips_va_start (tree valist
, rtx nextarg
)
6119 if (EABI_FLOAT_VARARGS_P
)
6121 const CUMULATIVE_ARGS
*cum
;
6122 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6123 tree ovfl
, gtop
, ftop
, goff
, foff
;
6125 int gpr_save_area_size
;
6126 int fpr_save_area_size
;
6129 cum
= &crtl
->args
.info
;
6131 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
6133 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
6135 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6136 f_gtop
= DECL_CHAIN (f_ovfl
);
6137 f_ftop
= DECL_CHAIN (f_gtop
);
6138 f_goff
= DECL_CHAIN (f_ftop
);
6139 f_foff
= DECL_CHAIN (f_goff
);
6141 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6143 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
6145 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
6147 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
6149 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
6152 /* Emit code to initialize OVFL, which points to the next varargs
6153 stack argument. CUM->STACK_WORDS gives the number of stack
6154 words used by named arguments. */
6155 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
6156 if (cum
->stack_words
> 0)
6157 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
6158 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
6159 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6161 /* Emit code to initialize GTOP, the top of the GPR save area. */
6162 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
6163 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
6164 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6166 /* Emit code to initialize FTOP, the top of the FPR save area.
6167 This address is gpr_save_area_bytes below GTOP, rounded
6168 down to the next fp-aligned boundary. */
6169 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
6170 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
6171 fpr_offset
&= -UNITS_PER_FPVALUE
;
6173 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
6174 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
6175 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6177 /* Emit code to initialize GOFF, the offset from GTOP of the
6178 next GPR argument. */
6179 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
6180 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
6181 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6183 /* Likewise emit code to initialize FOFF, the offset from FTOP
6184 of the next FPR argument. */
6185 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
6186 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
6187 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6191 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6192 std_expand_builtin_va_start (valist
, nextarg
);
6196 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6200 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6203 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6204 unsigned HOST_WIDE_INT align
, boundary
;
6207 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6209 type
= build_pointer_type (type
);
6211 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6212 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6214 /* When we align parameter on stack for caller, if the parameter
6215 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6216 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6217 here with caller. */
6218 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6219 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6221 boundary
/= BITS_PER_UNIT
;
6223 /* Hoist the valist value into a temporary for the moment. */
6224 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6226 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6227 requires greater alignment, we must perform dynamic alignment. */
6228 if (boundary
> align
)
6230 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6231 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6232 gimplify_and_add (t
, pre_p
);
6234 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6235 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6237 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6238 gimplify_and_add (t
, pre_p
);
6243 /* If the actual alignment is less than the alignment of the type,
6244 adjust the type accordingly so that we don't assume strict alignment
6245 when dereferencing the pointer. */
6246 boundary
*= BITS_PER_UNIT
;
6247 if (boundary
< TYPE_ALIGN (type
))
6249 type
= build_variant_type_copy (type
);
6250 TYPE_ALIGN (type
) = boundary
;
6253 /* Compute the rounded size of the type. */
6254 type_size
= size_in_bytes (type
);
6255 rounded_size
= round_up (type_size
, align
);
6257 /* Reduce rounded_size so it's sharable with the postqueue. */
6258 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6262 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6264 /* Small args are padded downward. */
6265 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6266 rounded_size
, size_int (align
));
6267 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6268 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6269 addr
= fold_build_pointer_plus (addr
, t
);
6272 /* Compute new value for AP. */
6273 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6274 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6275 gimplify_and_add (t
, pre_p
);
6277 addr
= fold_convert (build_pointer_type (type
), addr
);
6280 addr
= build_va_arg_indirect_ref (addr
);
6282 return build_va_arg_indirect_ref (addr
);
6285 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6288 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6294 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6296 type
= build_pointer_type (type
);
6298 if (!EABI_FLOAT_VARARGS_P
)
6299 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6302 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6303 tree ovfl
, top
, off
, align
;
6304 HOST_WIDE_INT size
, rsize
, osize
;
6307 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6308 f_gtop
= DECL_CHAIN (f_ovfl
);
6309 f_ftop
= DECL_CHAIN (f_gtop
);
6310 f_goff
= DECL_CHAIN (f_ftop
);
6311 f_foff
= DECL_CHAIN (f_goff
);
6315 TOP be the top of the GPR or FPR save area;
6316 OFF be the offset from TOP of the next register;
6317 ADDR_RTX be the address of the argument;
6318 SIZE be the number of bytes in the argument type;
6319 RSIZE be the number of bytes used to store the argument
6320 when it's in the register save area; and
6321 OSIZE be the number of bytes used to store it when it's
6322 in the stack overflow area.
6324 The code we want is:
6326 1: off &= -rsize; // round down
6329 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6334 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6335 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6339 [1] and [9] can sometimes be optimized away. */
6341 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6343 size
= int_size_in_bytes (type
);
6345 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6346 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6348 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6349 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6350 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6351 unshare_expr (valist
), f_foff
, NULL_TREE
);
6353 /* When va_start saves FPR arguments to the stack, each slot
6354 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6355 argument's precision. */
6356 rsize
= UNITS_PER_HWFPVALUE
;
6358 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6359 (= PARM_BOUNDARY bits). This can be different from RSIZE
6362 (1) On 32-bit targets when TYPE is a structure such as:
6364 struct s { float f; };
6366 Such structures are passed in paired FPRs, so RSIZE
6367 will be 8 bytes. However, the structure only takes
6368 up 4 bytes of memory, so OSIZE will only be 4.
6370 (2) In combinations such as -mgp64 -msingle-float
6371 -fshort-double. Doubles passed in registers will then take
6372 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6373 stack take up UNITS_PER_WORD bytes. */
6374 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6378 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6379 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6380 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6381 unshare_expr (valist
), f_goff
, NULL_TREE
);
6382 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6383 if (rsize
> UNITS_PER_WORD
)
6385 /* [1] Emit code for: off &= -rsize. */
6386 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6387 build_int_cst (TREE_TYPE (off
), -rsize
));
6388 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6393 /* [2] Emit code to branch if off == 0. */
6394 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6395 build_int_cst (TREE_TYPE (off
), 0));
6396 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6398 /* [5] Emit code for: off -= rsize. We do this as a form of
6399 post-decrement not available to C. */
6400 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6401 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6403 /* [4] Emit code for:
6404 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6405 t
= fold_convert (sizetype
, t
);
6406 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6407 t
= fold_build_pointer_plus (top
, t
);
6408 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6409 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6410 COND_EXPR_THEN (addr
) = t
;
6412 if (osize
> UNITS_PER_WORD
)
6414 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6415 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6416 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6417 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6418 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6419 unshare_expr (ovfl
), t
);
6424 /* [10, 11] Emit code for:
6425 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6427 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6428 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6429 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6430 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6432 /* String [9] and [10, 11] together. */
6434 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6435 COND_EXPR_ELSE (addr
) = t
;
6437 addr
= fold_convert (build_pointer_type (type
), addr
);
6438 addr
= build_va_arg_indirect_ref (addr
);
6442 addr
= build_va_arg_indirect_ref (addr
);
6447 /* Declare a unique, locally-binding function called NAME, then start
6451 mips_start_unique_function (const char *name
)
6455 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6456 get_identifier (name
),
6457 build_function_type_list (void_type_node
, NULL_TREE
));
6458 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6459 NULL_TREE
, void_type_node
);
6460 TREE_PUBLIC (decl
) = 1;
6461 TREE_STATIC (decl
) = 1;
6463 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
6465 targetm
.asm_out
.unique_section (decl
, 0);
6466 switch_to_section (get_named_section (decl
, NULL
, 0));
6468 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6469 fputs ("\t.hidden\t", asm_out_file
);
6470 assemble_name (asm_out_file
, name
);
6471 putc ('\n', asm_out_file
);
6474 /* Start a definition of function NAME. MIPS16_P indicates whether the
6475 function contains MIPS16 code. */
6478 mips_start_function_definition (const char *name
, bool mips16_p
)
6481 fprintf (asm_out_file
, "\t.set\tmips16\n");
6483 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6485 if (TARGET_MICROMIPS
)
6486 fprintf (asm_out_file
, "\t.set\tmicromips\n");
6487 #ifdef HAVE_GAS_MICROMIPS
6489 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
6492 if (!flag_inhibit_size_directive
)
6494 fputs ("\t.ent\t", asm_out_file
);
6495 assemble_name (asm_out_file
, name
);
6496 fputs ("\n", asm_out_file
);
6499 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6501 /* Start the definition proper. */
6502 assemble_name (asm_out_file
, name
);
6503 fputs (":\n", asm_out_file
);
6506 /* End a function definition started by mips_start_function_definition. */
6509 mips_end_function_definition (const char *name
)
6511 if (!flag_inhibit_size_directive
)
6513 fputs ("\t.end\t", asm_out_file
);
6514 assemble_name (asm_out_file
, name
);
6515 fputs ("\n", asm_out_file
);
6519 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6520 then free *STUB_PTR. */
6523 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
6525 mips_one_only_stub
*stub
= *stub_ptr
;
6529 const char *name
= stub
->get_name ();
6530 mips_start_unique_function (name
);
6531 mips_start_function_definition (name
, false);
6532 stub
->output_body ();
6533 mips_end_function_definition (name
);
6538 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6541 mips_ok_for_lazy_binding_p (rtx x
)
6543 return (TARGET_USE_GOT
6544 && GET_CODE (x
) == SYMBOL_REF
6545 && !SYMBOL_REF_BIND_NOW_P (x
)
6546 && !mips_symbol_binds_local_p (x
));
6549 /* Load function address ADDR into register DEST. TYPE is as for
6550 mips_expand_call. Return true if we used an explicit lazy-binding
6554 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6556 /* If we're generating PIC, and this call is to a global function,
6557 try to allow its address to be resolved lazily. This isn't
6558 possible for sibcalls when $gp is call-saved because the value
6559 of $gp on entry to the stub would be our caller's gp, not ours. */
6560 if (TARGET_EXPLICIT_RELOCS
6561 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6562 && mips_ok_for_lazy_binding_p (addr
))
6564 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6565 emit_insn (gen_rtx_SET (dest
, addr
));
6570 mips_emit_move (dest
, addr
);
6575 /* Each locally-defined hard-float MIPS16 function has a local symbol
6576 associated with it. This hash table maps the function symbol (FUNC)
6577 to the local symbol (LOCAL). */
6578 static GTY (()) hash_map
<nofree_string_hash
, rtx
> *mips16_local_aliases
;
6580 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6581 Return a local alias for it, creating a new one if necessary. */
6584 mips16_local_alias (rtx func
)
6586 /* Create the hash table if this is the first call. */
6587 if (mips16_local_aliases
== NULL
)
6588 mips16_local_aliases
= hash_map
<nofree_string_hash
, rtx
>::create_ggc (37);
6590 /* Look up the function symbol, creating a new entry if need be. */
6592 const char *func_name
= XSTR (func
, 0);
6593 rtx
*slot
= &mips16_local_aliases
->get_or_insert (func_name
, &existed
);
6594 gcc_assert (slot
!= NULL
);
6600 /* Create a new SYMBOL_REF for the local symbol. The choice of
6601 __fn_local_* is based on the __fn_stub_* names that we've
6602 traditionally used for the non-MIPS16 stub. */
6603 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6604 const char *local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6605 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6606 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6608 /* Create a new structure to represent the mapping. */
6614 /* A chained list of functions for which mips16_build_call_stub has already
6615 generated a stub. NAME is the name of the function and FP_RET_P is true
6616 if the function returns a value in floating-point registers. */
6617 struct mips16_stub
{
6618 struct mips16_stub
*next
;
6622 static struct mips16_stub
*mips16_stubs
;
6624 /* Return the two-character string that identifies floating-point
6625 return mode MODE in the name of a MIPS16 function stub. */
6628 mips16_call_stub_mode_suffix (machine_mode mode
)
6632 else if (mode
== DFmode
)
6634 else if (mode
== SCmode
)
6636 else if (mode
== DCmode
)
6638 else if (mode
== V2SFmode
)
6640 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
);
6647 /* Write instructions to move a 32-bit value between general register
6648 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6649 from GPREG to FPREG and 'f' to move in the opposite direction. */
6652 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6654 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6655 reg_names
[gpreg
], reg_names
[fpreg
]);
6658 /* Likewise for 64-bit values. */
6661 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6664 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6665 reg_names
[gpreg
], reg_names
[fpreg
]);
6666 else if (ISA_HAS_MXHC1
)
6668 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6669 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6670 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6671 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6673 else if (TARGET_FLOATXX
&& direction
== 't')
6675 /* Use the argument save area to move via memory. */
6676 fprintf (asm_out_file
, "\tsw\t%s,0($sp)\n", reg_names
[gpreg
]);
6677 fprintf (asm_out_file
, "\tsw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
6678 fprintf (asm_out_file
, "\tldc1\t%s,0($sp)\n", reg_names
[fpreg
]);
6680 else if (TARGET_FLOATXX
&& direction
== 'f')
6682 /* Use the argument save area to move via memory. */
6683 fprintf (asm_out_file
, "\tsdc1\t%s,0($sp)\n", reg_names
[fpreg
]);
6684 fprintf (asm_out_file
, "\tlw\t%s,0($sp)\n", reg_names
[gpreg
]);
6685 fprintf (asm_out_file
, "\tlw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
6689 /* Move the least-significant word. */
6690 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6691 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6692 /* ...then the most significant word. */
6693 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6694 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6698 /* Write out code to move floating-point arguments into or out of
6699 general registers. FP_CODE is the code describing which arguments
6700 are present (see the comment above the definition of CUMULATIVE_ARGS
6701 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6704 mips_output_args_xfer (int fp_code
, char direction
)
6706 unsigned int gparg
, fparg
, f
;
6707 CUMULATIVE_ARGS cum
;
6709 /* This code only works for o32 and o64. */
6710 gcc_assert (TARGET_OLDABI
);
6712 mips_init_cumulative_args (&cum
, NULL
);
6714 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6717 struct mips_arg_info info
;
6721 else if ((f
& 3) == 2)
6726 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6727 gparg
= mips_arg_regno (&info
, false);
6728 fparg
= mips_arg_regno (&info
, true);
6731 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6733 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6735 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6739 /* Write a MIPS16 stub for the current function. This stub is used
6740 for functions which take arguments in the floating-point registers.
6741 It is normal-mode code that moves the floating-point arguments
6742 into the general registers and then jumps to the MIPS16 code. */
6745 mips16_build_function_stub (void)
6747 const char *fnname
, *alias_name
, *separator
;
6748 char *secname
, *stubname
;
6753 /* Create the name of the stub, and its unique section. */
6754 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6755 alias
= mips16_local_alias (symbol
);
6757 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6758 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6759 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6760 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6762 /* Build a decl for the stub. */
6763 stubdecl
= build_decl (BUILTINS_LOCATION
,
6764 FUNCTION_DECL
, get_identifier (stubname
),
6765 build_function_type_list (void_type_node
, NULL_TREE
));
6766 set_decl_section_name (stubdecl
, secname
);
6767 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6768 RESULT_DECL
, NULL_TREE
, void_type_node
);
6770 /* Output a comment. */
6771 fprintf (asm_out_file
, "\t# Stub function for %s (",
6772 current_function_name ());
6774 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6776 fprintf (asm_out_file
, "%s%s", separator
,
6777 (f
& 3) == 1 ? "float" : "double");
6780 fprintf (asm_out_file
, ")\n");
6782 /* Start the function definition. */
6783 assemble_start_function (stubdecl
, stubname
);
6784 mips_start_function_definition (stubname
, false);
6786 /* If generating pic2 code, either set up the global pointer or
6788 if (TARGET_ABICALLS_PIC2
)
6790 if (TARGET_ABSOLUTE_ABICALLS
)
6791 fprintf (asm_out_file
, "\t.option\tpic0\n");
6794 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6795 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6796 target function is. Use a local GOT access when loading the
6797 symbol, to cut down on the number of unnecessary GOT entries
6798 for stubs that aren't needed. */
6799 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6804 /* Load the address of the MIPS16 function into $25. Do this first so
6805 that targets with coprocessor interlocks can use an MFC1 to fill the
6807 output_asm_insn ("la\t%^,%0", &symbol
);
6809 /* Move the arguments from floating-point registers to general registers. */
6810 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6812 /* Jump to the MIPS16 function. */
6813 output_asm_insn ("jr\t%^", NULL
);
6815 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6816 fprintf (asm_out_file
, "\t.option\tpic2\n");
6818 mips_end_function_definition (stubname
);
6820 /* If the linker needs to create a dynamic symbol for the target
6821 function, it will associate the symbol with the stub (which,
6822 unlike the target function, follows the proper calling conventions).
6823 It is therefore useful to have a local alias for the target function,
6824 so that it can still be identified as MIPS16 code. As an optimization,
6825 this symbol can also be used for indirect MIPS16 references from
6826 within this file. */
6827 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6829 switch_to_section (function_section (current_function_decl
));
6832 /* The current function is a MIPS16 function that returns a value in an FPR.
6833 Copy the return value from its soft-float to its hard-float location.
6834 libgcc2 has special non-MIPS16 helper functions for each case. */
6837 mips16_copy_fpr_return_value (void)
6839 rtx fn
, insn
, retval
;
6841 machine_mode return_mode
;
6844 return_type
= DECL_RESULT (current_function_decl
);
6845 return_mode
= DECL_MODE (return_type
);
6847 name
= ACONCAT (("__mips16_ret_",
6848 mips16_call_stub_mode_suffix (return_mode
),
6850 fn
= mips16_stub_function (name
);
6852 /* The function takes arguments in $2 (and possibly $3), so calls
6853 to it cannot be lazily bound. */
6854 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6856 /* Model the call as something that takes the GPR return value as
6857 argument and returns an "updated" value. */
6858 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6859 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6860 const0_rtx
, NULL_RTX
, false);
6861 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6864 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6865 RETVAL is the location of the return value, or null if this is
6866 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6867 arguments and FP_CODE is the code built by mips_function_arg;
6868 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6870 There are three alternatives:
6872 - If a stub was needed, emit the call and return the call insn itself.
6874 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6875 to the new target and return null.
6877 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6880 A stub is needed for calls to functions that, in normal mode,
6881 receive arguments in FPRs or return values in FPRs. The stub
6882 copies the arguments from their soft-float positions to their
6883 hard-float positions, calls the real function, then copies the
6884 return value from its hard-float position to its soft-float
6887 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6888 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6889 automatically redirects the JAL to the stub, otherwise the JAL
6890 continues to call FN directly. */
6893 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6897 struct mips16_stub
*l
;
6901 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6902 we were invoked with the -msoft-float option. */
6903 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6906 /* Figure out whether the value might come back in a floating-point
6908 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6910 /* We don't need to do anything if there were no floating-point
6911 arguments and the value will not be returned in a floating-point
6913 if (fp_code
== 0 && !fp_ret_p
)
6916 /* We don't need to do anything if this is a call to a special
6917 MIPS16 support function. */
6919 if (mips16_stub_function_p (fn
))
6922 /* If we're calling a locally-defined MIPS16 function, we know that
6923 it will return values in both the "soft-float" and "hard-float"
6924 registers. There is no need to use a stub to move the latter
6926 if (fp_code
== 0 && mips16_local_function_p (fn
))
6929 /* This code will only work for o32 and o64 abis. The other ABI's
6930 require more sophisticated support. */
6931 gcc_assert (TARGET_OLDABI
);
6933 /* If we're calling via a function pointer, use one of the magic
6934 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6935 Each stub expects the function address to arrive in register $2. */
6936 if (GET_CODE (fn
) != SYMBOL_REF
6937 || !call_insn_operand (fn
, VOIDmode
))
6944 /* If this is a locally-defined and locally-binding function,
6945 avoid the stub by calling the local alias directly. */
6946 if (mips16_local_function_p (fn
))
6948 *fn_ptr
= mips16_local_alias (fn
);
6952 /* Create a SYMBOL_REF for the libgcc.a function. */
6954 sprintf (buf
, "__mips16_call_stub_%s_%d",
6955 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6958 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6959 stub_fn
= mips16_stub_function (buf
);
6961 /* The function uses $2 as an argument, so calls to it
6962 cannot be lazily bound. */
6963 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6965 /* Load the target function into $2. */
6966 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6967 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6969 /* Emit the call. */
6970 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6971 args_size
, NULL_RTX
, lazy_p
);
6973 /* Tell GCC that this call does indeed use the value of $2. */
6974 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6976 /* If we are handling a floating-point return value, we need to
6977 save $18 in the function prologue. Putting a note on the
6978 call will mean that df_regs_ever_live_p ($18) will be true if the
6979 call is not eliminated, and we can check that in the prologue
6982 CALL_INSN_FUNCTION_USAGE (insn
) =
6983 gen_rtx_EXPR_LIST (VOIDmode
,
6984 gen_rtx_CLOBBER (VOIDmode
,
6985 gen_rtx_REG (word_mode
, 18)),
6986 CALL_INSN_FUNCTION_USAGE (insn
));
6991 /* We know the function we are going to call. If we have already
6992 built a stub, we don't need to do anything further. */
6993 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6994 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6995 if (strcmp (l
->name
, fnname
) == 0)
7000 const char *separator
;
7001 char *secname
, *stubname
;
7002 tree stubid
, stubdecl
;
7005 /* If the function does not return in FPRs, the special stub
7009 If the function does return in FPRs, the stub section is named
7010 .mips16.call.fp.FNNAME
7012 Build a decl for the stub. */
7013 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
7015 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
7017 stubid
= get_identifier (stubname
);
7018 stubdecl
= build_decl (BUILTINS_LOCATION
,
7019 FUNCTION_DECL
, stubid
,
7020 build_function_type_list (void_type_node
,
7022 set_decl_section_name (stubdecl
, secname
);
7023 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7024 RESULT_DECL
, NULL_TREE
,
7027 /* Output a comment. */
7028 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
7030 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
7034 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7036 fprintf (asm_out_file
, "%s%s", separator
,
7037 (f
& 3) == 1 ? "float" : "double");
7040 fprintf (asm_out_file
, ")\n");
7042 /* Start the function definition. */
7043 assemble_start_function (stubdecl
, stubname
);
7044 mips_start_function_definition (stubname
, false);
7048 fprintf (asm_out_file
, "\t.cfi_startproc\n");
7050 /* Create a fake CFA 4 bytes below the stack pointer.
7051 This works around unwinders (like libgcc's) that expect
7052 the CFA for non-signal frames to be unique. */
7053 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
7055 /* "Save" $sp in itself so we don't use the fake CFA.
7056 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
7057 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
7059 /* Save the return address in $18. The stub's caller knows
7060 that $18 might be clobbered, even though $18 is usually
7061 a call-saved register.
7063 Do it early on in case the last move to a floating-point
7064 register can be scheduled into the delay slot of the
7065 call we are about to make. */
7066 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
7067 reg_names
[GP_REG_FIRST
+ 18],
7068 reg_names
[RETURN_ADDR_REGNUM
]);
7072 /* Load the address of the MIPS16 function into $25. Do this
7073 first so that targets with coprocessor interlocks can use
7074 an MFC1 to fill the delay slot. */
7075 if (TARGET_EXPLICIT_RELOCS
)
7077 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
7078 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
7081 output_asm_insn ("la\t%^,%0", &fn
);
7084 /* Move the arguments from general registers to floating-point
7086 mips_output_args_xfer (fp_code
, 't');
7090 /* Now call the non-MIPS16 function. */
7091 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
7092 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
7094 /* Move the result from floating-point registers to
7095 general registers. */
7096 switch (GET_MODE (retval
))
7099 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
7103 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
7104 TARGET_LITTLE_ENDIAN
7107 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
7109 /* On 64-bit targets, complex floats are returned in
7110 a single GPR, such that "sd" on a suitably-aligned
7111 target would store the value correctly. */
7112 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7113 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7114 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7115 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7116 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
7117 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
7118 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
7119 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7120 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7121 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
7122 reg_names
[GP_RETURN
],
7123 reg_names
[GP_RETURN
],
7124 reg_names
[GP_RETURN
+ 1]);
7129 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7133 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
7138 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7139 || GET_MODE (retval
) != V2SFmode
);
7140 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7146 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
7147 fprintf (asm_out_file
, "\t.cfi_endproc\n");
7151 /* Jump to the previously-loaded address. */
7152 output_asm_insn ("jr\t%^", NULL
);
7155 #ifdef ASM_DECLARE_FUNCTION_SIZE
7156 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
7159 mips_end_function_definition (stubname
);
7161 /* Record this stub. */
7162 l
= XNEW (struct mips16_stub
);
7163 l
->name
= xstrdup (fnname
);
7164 l
->fp_ret_p
= fp_ret_p
;
7165 l
->next
= mips16_stubs
;
7169 /* If we expect a floating-point return value, but we've built a
7170 stub which does not expect one, then we're in trouble. We can't
7171 use the existing stub, because it won't handle the floating-point
7172 value. We can't build a new stub, because the linker won't know
7173 which stub to use for the various calls in this object file.
7174 Fortunately, this case is illegal, since it means that a function
7175 was declared in two different ways in a single compilation. */
7176 if (fp_ret_p
&& !l
->fp_ret_p
)
7177 error ("cannot handle inconsistent calls to %qs", fnname
);
7179 if (retval
== NULL_RTX
)
7180 pattern
= gen_call_internal_direct (fn
, args_size
);
7182 pattern
= gen_call_value_internal_direct (retval
, fn
, args_size
);
7183 insn
= mips_emit_call_insn (pattern
, fn
, fn
, false);
7185 /* If we are calling a stub which handles a floating-point return
7186 value, we need to arrange to save $18 in the prologue. We do this
7187 by marking the function call as using the register. The prologue
7188 will later see that it is used, and emit code to save it. */
7190 CALL_INSN_FUNCTION_USAGE (insn
) =
7191 gen_rtx_EXPR_LIST (VOIDmode
,
7192 gen_rtx_CLOBBER (VOIDmode
,
7193 gen_rtx_REG (word_mode
, 18)),
7194 CALL_INSN_FUNCTION_USAGE (insn
));
7199 /* Expand a call of type TYPE. RESULT is where the result will go (null
7200 for "call"s and "sibcall"s), ADDR is the address of the function,
7201 ARGS_SIZE is the size of the arguments and AUX is the value passed
7202 to us by mips_function_arg. LAZY_P is true if this call already
7203 involves a lazily-bound function address (such as when calling
7204 functions through a MIPS16 hard-float stub).
7206 Return the call itself. */
7209 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7210 rtx args_size
, rtx aux
, bool lazy_p
)
7212 rtx orig_addr
, pattern
;
7216 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7217 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7220 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7225 if (!call_insn_operand (addr
, VOIDmode
))
7227 if (type
== MIPS_CALL_EPILOGUE
)
7228 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7230 addr
= gen_reg_rtx (Pmode
);
7231 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7236 rtx (*fn
) (rtx
, rtx
);
7238 if (type
== MIPS_CALL_SIBCALL
)
7239 fn
= gen_sibcall_internal
;
7241 fn
= gen_call_internal
;
7243 pattern
= fn (addr
, args_size
);
7245 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7247 /* Handle return values created by mips_return_fpr_pair. */
7248 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7251 if (type
== MIPS_CALL_SIBCALL
)
7252 fn
= gen_sibcall_value_multiple_internal
;
7254 fn
= gen_call_value_multiple_internal
;
7256 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7257 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7258 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7262 rtx (*fn
) (rtx
, rtx
, rtx
);
7264 if (type
== MIPS_CALL_SIBCALL
)
7265 fn
= gen_sibcall_value_internal
;
7267 fn
= gen_call_value_internal
;
7269 /* Handle return values created by mips_return_fpr_single. */
7270 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7271 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7272 pattern
= fn (result
, addr
, args_size
);
7275 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7278 /* Split call instruction INSN into a $gp-clobbering call and
7279 (where necessary) an instruction to restore $gp from its save slot.
7280 CALL_PATTERN is the pattern of the new call. */
7283 mips_split_call (rtx insn
, rtx call_pattern
)
7285 emit_call_insn (call_pattern
);
7286 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7287 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
,
7288 POST_CALL_TMP_REG
));
7291 /* Return true if a call to DECL may need to use JALX. */
7294 mips_call_may_need_jalx_p (tree decl
)
7296 /* If the current translation unit would use a different mode for DECL,
7297 assume that the call needs JALX. */
7298 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7301 /* mips_get_compress_mode is always accurate for locally-binding
7302 functions in the current translation unit. */
7303 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7306 /* When -minterlink-compressed is in effect, assume that functions
7307 could use a different encoding mode unless an attribute explicitly
7308 tells us otherwise. */
7309 if (TARGET_INTERLINK_COMPRESSED
)
7311 if (!TARGET_COMPRESSION
7312 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7314 if (TARGET_COMPRESSION
7315 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7322 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7325 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7327 if (!TARGET_SIBCALLS
)
7330 /* Interrupt handlers need special epilogue code and therefore can't
7332 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7335 /* Direct Js are only possible to functions that use the same ISA encoding.
7336 There is no JX counterpoart of JALX. */
7338 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7339 && mips_call_may_need_jalx_p (decl
))
7342 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7343 require $gp to be valid on entry, so sibcalls can only use stubs
7344 if $gp is call-clobbered. */
7346 && TARGET_CALL_SAVED_GP
7347 && !TARGET_ABICALLS_PIC0
7348 && !targetm
.binds_local_p (decl
))
7355 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7358 mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
7360 enum by_pieces_operation op
,
7363 if (op
== STORE_BY_PIECES
)
7364 return mips_store_by_pieces_p (size
, align
);
7365 if (op
== MOVE_BY_PIECES
&& HAVE_movmemsi
)
7367 /* movmemsi is meant to generate code that is at least as good as
7368 move_by_pieces. However, movmemsi effectively uses a by-pieces
7369 implementation both for moves smaller than a word and for
7370 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7371 bytes. We should allow the tree-level optimisers to do such
7372 moves by pieces, as it often exposes other optimization
7373 opportunities. We might as well continue to use movmemsi at
7374 the rtl level though, as it produces better code when
7375 scheduling is disabled (such as at -O). */
7376 if (currently_expanding_to_rtl
)
7378 if (align
< BITS_PER_WORD
)
7379 return size
< UNITS_PER_WORD
;
7380 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7383 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
7386 /* Implement a handler for STORE_BY_PIECES operations
7387 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7390 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7392 /* Storing by pieces involves moving constants into registers
7393 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7394 We need to decide whether it is cheaper to load the address of
7395 constant data into a register and use a block move instead. */
7397 /* If the data is only byte aligned, then:
7399 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7400 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7403 (a2) A block move of 4 bytes from aligned source data can use an
7404 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7405 4 SBs that we would generate when storing by pieces. */
7406 if (align
<= BITS_PER_UNIT
)
7409 /* If the data is 2-byte aligned, then:
7411 (b1) A block move of less than 4 bytes would use a combination of LBs,
7412 LHs, SBs and SHs. We get better code by using single-instruction
7413 LIs, SBs and SHs instead.
7415 (b2) A block move of 4 bytes from aligned source data would again use
7416 an LW/SWL/SWR sequence. In most cases, loading the address of
7417 the source data would require at least one extra instruction.
7418 It is often more efficient to use 2 single-instruction LIs and
7421 (b3) A block move of up to 3 additional bytes would be like (b1).
7423 (b4) A block move of 8 bytes from aligned source data can use two
7424 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7425 sequences are better than the 4 LIs and 4 SHs that we'd generate
7426 when storing by pieces.
7428 The reasoning for higher alignments is similar:
7430 (c1) A block move of less than 4 bytes would be the same as (b1).
7432 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7433 loading the address of the source data would typically require
7434 at least one extra instruction. It is generally better to use
7437 (c3) A block move of up to 3 additional bytes would be like (b1).
7439 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7440 LD/SD sequence, and in these cases we've traditionally preferred
7441 the memory copy over the more bulky constant moves. */
7445 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7446 Assume that the areas do not overlap. */
7449 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7451 HOST_WIDE_INT offset
, delta
;
7452 unsigned HOST_WIDE_INT bits
;
7457 /* Work out how many bits to move at a time. If both operands have
7458 half-word alignment, it is usually better to move in half words.
7459 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7460 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7461 Otherwise move word-sized chunks. */
7462 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7463 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7464 bits
= BITS_PER_WORD
/ 2;
7466 bits
= BITS_PER_WORD
;
7468 mode
= mode_for_size (bits
, MODE_INT
, 0);
7469 delta
= bits
/ BITS_PER_UNIT
;
7471 /* Allocate a buffer for the temporary registers. */
7472 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7474 /* Load as many BITS-sized chunks as possible. Use a normal load if
7475 the source has enough alignment, otherwise use left/right pairs. */
7476 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7478 regs
[i
] = gen_reg_rtx (mode
);
7479 if (MEM_ALIGN (src
) >= bits
)
7480 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7483 rtx part
= adjust_address (src
, BLKmode
, offset
);
7484 set_mem_size (part
, delta
);
7485 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7490 /* Copy the chunks to the destination. */
7491 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7492 if (MEM_ALIGN (dest
) >= bits
)
7493 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7496 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7497 set_mem_size (part
, delta
);
7498 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7502 /* Mop up any left-over bytes. */
7503 if (offset
< length
)
7505 src
= adjust_address (src
, BLKmode
, offset
);
7506 dest
= adjust_address (dest
, BLKmode
, offset
);
7507 move_by_pieces (dest
, src
, length
- offset
,
7508 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7512 /* Helper function for doing a loop-based block operation on memory
7513 reference MEM. Each iteration of the loop will operate on LENGTH
7516 Create a new base register for use within the loop and point it to
7517 the start of MEM. Create a new memory reference that uses this
7518 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7521 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7522 rtx
*loop_reg
, rtx
*loop_mem
)
7524 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7526 /* Although the new mem does not refer to a known location,
7527 it does keep up to LENGTH bytes of alignment. */
7528 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7529 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7532 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7533 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7534 the memory regions do not overlap. */
7537 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7538 HOST_WIDE_INT bytes_per_iter
)
7540 rtx_code_label
*label
;
7541 rtx src_reg
, dest_reg
, final_src
, test
;
7542 HOST_WIDE_INT leftover
;
7544 leftover
= length
% bytes_per_iter
;
7547 /* Create registers and memory references for use within the loop. */
7548 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7549 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7551 /* Calculate the value that SRC_REG should have after the last iteration
7553 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7556 /* Emit the start of the loop. */
7557 label
= gen_label_rtx ();
7560 /* Emit the loop body. */
7561 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7563 /* Move on to the next block. */
7564 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7565 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7567 /* Emit the loop condition. */
7568 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7569 if (Pmode
== DImode
)
7570 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7572 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7574 /* Mop up any left-over bytes. */
7576 mips_block_move_straight (dest
, src
, leftover
);
7579 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7580 memory reference SRC to memory reference DEST. */
7583 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7585 /* Disable entirely for R6 initially. */
7586 if (!ISA_HAS_LWL_LWR
)
7589 if (CONST_INT_P (length
))
7591 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7593 mips_block_move_straight (dest
, src
, INTVAL (length
));
7598 mips_block_move_loop (dest
, src
, INTVAL (length
),
7599 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7606 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7609 mips_expand_synci_loop (rtx begin
, rtx end
)
7611 rtx inc
, cmp_result
, mask
, length
;
7612 rtx_code_label
*label
, *end_label
;
7614 /* Create end_label. */
7615 end_label
= gen_label_rtx ();
7617 /* Check if begin equals end. */
7618 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7619 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7621 /* Load INC with the cache line size (rdhwr INC,$1). */
7622 inc
= gen_reg_rtx (Pmode
);
7623 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7625 /* Check if inc is 0. */
7626 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7627 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7629 /* Calculate mask. */
7630 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7632 /* Mask out begin by mask. */
7633 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7635 /* Calculate length. */
7636 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7638 /* Loop back to here. */
7639 label
= gen_label_rtx ();
7642 emit_insn (gen_synci (begin
));
7644 /* Update length. */
7645 mips_emit_binary (MINUS
, length
, length
, inc
);
7648 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7650 /* Check if length is greater than 0. */
7651 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7652 emit_jump_insn (gen_condjump (cmp_result
, label
));
7654 emit_label (end_label
);
7657 /* Expand a QI or HI mode atomic memory operation.
7659 GENERATOR contains a pointer to the gen_* function that generates
7660 the SI mode underlying atomic operation using masks that we
7663 RESULT is the return register for the operation. Its value is NULL
7666 MEM is the location of the atomic access.
7668 OLDVAL is the first operand for the operation.
7670 NEWVAL is the optional second operand for the operation. Its value
7671 is NULL if unused. */
7674 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7675 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7677 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7678 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7682 mode
= GET_MODE (mem
);
7684 /* Compute the address of the containing SImode value. */
7685 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7686 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7687 force_reg (Pmode
, GEN_INT (-4)));
7689 /* Create a memory reference for it. */
7690 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7691 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7692 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7694 /* Work out the byte offset of the QImode or HImode value,
7695 counting from the least significant byte. */
7696 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7697 if (TARGET_BIG_ENDIAN
)
7698 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7700 /* Multiply by eight to convert the shift value from bytes to bits. */
7701 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7703 /* Make the final shift an SImode value, so that it can be used in
7704 SImode operations. */
7705 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7707 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7708 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7709 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7710 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7712 /* Compute the equivalent exclusive mask. */
7713 inverted_mask
= gen_reg_rtx (SImode
);
7714 emit_insn (gen_rtx_SET (inverted_mask
, gen_rtx_NOT (SImode
, mask
)));
7716 /* Shift the old value into place. */
7717 if (oldval
!= const0_rtx
)
7719 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7720 oldval
= force_reg (SImode
, oldval
);
7721 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7724 /* Do the same for the new value. */
7725 if (newval
&& newval
!= const0_rtx
)
7727 newval
= convert_modes (SImode
, mode
, newval
, true);
7728 newval
= force_reg (SImode
, newval
);
7729 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7732 /* Do the SImode atomic access. */
7734 res
= gen_reg_rtx (SImode
);
7736 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7738 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7740 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7746 /* Shift and convert the result. */
7747 mips_emit_binary (AND
, res
, res
, mask
);
7748 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7749 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7753 /* Return true if it is possible to use left/right accesses for a
7754 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7755 When returning true, update *LEFT and *RIGHT as follows:
7757 *LEFT is a QImode reference to the first byte if big endian or
7758 the last byte if little endian. This address can be used in the
7759 left-side instructions (LWL, SWL, LDL, SDL).
7761 *RIGHT is a QImode reference to the opposite end of the field and
7762 can be used in the patterning right-side instruction. */
7765 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7766 rtx
*left
, rtx
*right
)
7770 /* Check that the size is valid. */
7771 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7774 /* We can only access byte-aligned values. Since we are always passed
7775 a reference to the first byte of the field, it is not necessary to
7776 do anything with BITPOS after this check. */
7777 if (bitpos
% BITS_PER_UNIT
!= 0)
7780 /* Reject aligned bitfields: we want to use a normal load or store
7781 instead of a left/right pair. */
7782 if (MEM_ALIGN (op
) >= width
)
7785 /* Get references to both ends of the field. */
7786 first
= adjust_address (op
, QImode
, 0);
7787 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7789 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7790 correspond to the MSB and RIGHT to the LSB. */
7791 if (TARGET_BIG_ENDIAN
)
7792 *left
= first
, *right
= last
;
7794 *left
= last
, *right
= first
;
7799 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7800 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7801 the operation is the equivalent of:
7803 (set DEST (*_extract SRC WIDTH BITPOS))
7805 Return true on success. */
7808 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7809 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7811 rtx left
, right
, temp
;
7812 rtx dest1
= NULL_RTX
;
7814 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7815 be a DImode, create a new temp and emit a zero extend at the end. */
7816 if (GET_MODE (dest
) == DImode
7818 && GET_MODE_BITSIZE (SImode
) == width
)
7821 dest
= gen_reg_rtx (SImode
);
7824 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
7827 temp
= gen_reg_rtx (GET_MODE (dest
));
7828 if (GET_MODE (dest
) == DImode
)
7830 emit_insn (gen_mov_ldl (temp
, src
, left
));
7831 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7835 emit_insn (gen_mov_lwl (temp
, src
, left
));
7836 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7839 /* If we were loading 32bits and the original register was DI then
7840 sign/zero extend into the orignal dest. */
7844 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7846 emit_insn (gen_extendsidi2 (dest1
, dest
));
7851 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7852 BITPOS and SRC are the operands passed to the expander; the operation
7853 is the equivalent of:
7855 (set (zero_extract DEST WIDTH BITPOS) SRC)
7857 Return true on success. */
7860 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7861 HOST_WIDE_INT bitpos
)
7866 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
7869 mode
= mode_for_size (width
, MODE_INT
, 0);
7870 src
= gen_lowpart (mode
, src
);
7873 emit_insn (gen_mov_sdl (dest
, src
, left
));
7874 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7878 emit_insn (gen_mov_swl (dest
, src
, left
));
7879 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7884 /* Return true if X is a MEM with the same size as MODE. */
7887 mips_mem_fits_mode_p (machine_mode mode
, rtx x
)
7890 && MEM_SIZE_KNOWN_P (x
)
7891 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7894 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7895 source of an "ext" instruction or the destination of an "ins"
7896 instruction. OP must be a register operand and the following
7897 conditions must hold:
7899 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7900 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7901 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7903 Also reject lengths equal to a word as they are better handled
7904 by the move patterns. */
7907 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7909 if (!ISA_HAS_EXT_INS
7910 || !register_operand (op
, VOIDmode
)
7911 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7914 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7917 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7923 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7924 operation if MAXLEN is the maxium length of consecutive bits that
7925 can make up MASK. MODE is the mode of the operation. See
7926 mask_low_and_shift_len for the actual definition. */
7929 mask_low_and_shift_p (machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7931 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7934 /* Return true iff OP1 and OP2 are valid operands together for the
7935 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7936 see the table in the comment before the pattern. */
7939 and_operands_ok (machine_mode mode
, rtx op1
, rtx op2
)
7941 return (memory_operand (op1
, mode
)
7942 ? and_load_operand (op2
, mode
)
7943 : and_reg_operand (op2
, mode
));
7946 /* The canonical form of a mask-low-and-shift-left operation is
7947 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7948 cleared. Thus we need to shift MASK to the right before checking if it
7949 is a valid mask value. MODE is the mode of the operation. If true
7950 return the length of the mask, otherwise return -1. */
7953 mask_low_and_shift_len (machine_mode mode
, rtx mask
, rtx shift
)
7955 HOST_WIDE_INT shval
;
7957 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7958 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7961 /* Return true if -msplit-addresses is selected and should be honored.
7963 -msplit-addresses is a half-way house between explicit relocations
7964 and the traditional assembler macros. It can split absolute 32-bit
7965 symbolic constants into a high/lo_sum pair but uses macros for other
7968 Like explicit relocation support for REL targets, it relies
7969 on GNU extensions in the assembler and the linker.
7971 Although this code should work for -O0, it has traditionally
7972 been treated as an optimization. */
7975 mips_split_addresses_p (void)
7977 return (TARGET_SPLIT_ADDRESSES
7981 && !ABI_HAS_64BIT_SYMBOLS
);
7984 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7987 mips_init_relocs (void)
7989 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7990 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7991 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7992 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7993 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7995 if (TARGET_MIPS16_PCREL_LOADS
)
7996 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7999 if (ABI_HAS_64BIT_SYMBOLS
)
8001 if (TARGET_EXPLICIT_RELOCS
)
8003 mips_split_p
[SYMBOL_64_HIGH
] = true;
8004 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
8005 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
8007 mips_split_p
[SYMBOL_64_MID
] = true;
8008 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
8009 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
8011 mips_split_p
[SYMBOL_64_LOW
] = true;
8012 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
8013 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
8015 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8016 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8021 if (TARGET_EXPLICIT_RELOCS
8022 || mips_split_addresses_p ()
8025 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8026 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
8027 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8034 /* The high part is provided by a pseudo copy of $gp. */
8035 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
8036 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
8038 else if (TARGET_EXPLICIT_RELOCS
)
8039 /* Small data constants are kept whole until after reload,
8040 then lowered by mips_rewrite_small_data. */
8041 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
8043 if (TARGET_EXPLICIT_RELOCS
)
8045 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8048 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
8049 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
8053 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
8054 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
8057 /* Expose the use of $28 as soon as possible. */
8058 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8062 /* The HIGH and LO_SUM are matched by special .md patterns. */
8063 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8065 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
8066 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
8067 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
8069 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
8070 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
8071 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
8076 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
8078 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
8079 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
8081 /* Expose the use of $28 as soon as possible. */
8082 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8088 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
8089 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
8090 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
8093 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
8094 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
8096 if (TARGET_MIPS16_PCREL_LOADS
)
8098 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
8099 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
8103 mips_split_p
[SYMBOL_DTPREL
] = true;
8104 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
8105 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
8107 mips_split_p
[SYMBOL_TPREL
] = true;
8108 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
8109 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
8112 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
8113 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
8116 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8117 in context CONTEXT. RELOCS is the array of relocations to use. */
8120 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
8121 const char **relocs
)
8123 enum mips_symbol_type symbol_type
;
8126 symbol_type
= mips_classify_symbolic_expression (op
, context
);
8127 gcc_assert (relocs
[symbol_type
]);
8129 fputs (relocs
[symbol_type
], file
);
8130 output_addr_const (file
, mips_strip_unspec_address (op
));
8131 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
8136 /* Start a new block with the given asm switch enabled. If we need
8137 to print a directive, emit PREFIX before it and SUFFIX after it. */
8140 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8141 const char *prefix
, const char *suffix
)
8143 if (asm_switch
->nesting_level
== 0)
8144 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
8145 asm_switch
->nesting_level
++;
8148 /* Likewise, but end a block. */
8151 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8152 const char *prefix
, const char *suffix
)
8154 gcc_assert (asm_switch
->nesting_level
);
8155 asm_switch
->nesting_level
--;
8156 if (asm_switch
->nesting_level
== 0)
8157 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
8160 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8161 that either print a complete line or print nothing. */
8164 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
8166 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
8170 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
8172 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
8175 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8176 The punctuation characters are:
8178 '(' Start a nested ".set noreorder" block.
8179 ')' End a nested ".set noreorder" block.
8180 '[' Start a nested ".set noat" block.
8181 ']' End a nested ".set noat" block.
8182 '<' Start a nested ".set nomacro" block.
8183 '>' End a nested ".set nomacro" block.
8184 '*' Behave like %(%< if generating a delayed-branch sequence.
8185 '#' Print a nop if in a ".set noreorder" block.
8186 '/' Like '#', but do nothing within a delayed-branch sequence.
8187 '?' Print "l" if mips_branch_likely is true
8188 '~' Print a nop if mips_branch_likely is true
8189 '.' Print the name of the register with a hard-wired zero (zero or $0).
8190 '@' Print the name of the assembler temporary register (at or $1).
8191 '^' Print the name of the pic call-through register (t9 or $25).
8192 '+' Print the name of the gp register (usually gp or $28).
8193 '$' Print the name of the stack pointer register (sp or $29).
8194 ':' Print "c" to use the compact version if the delay slot is a nop.
8195 '!' Print "s" to use the short version if the delay slot contains a
8198 See also mips_init_print_operand_pucnt. */
8201 mips_print_operand_punctuation (FILE *file
, int ch
)
8206 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8210 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8214 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8218 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8222 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8226 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8230 if (final_sequence
!= 0)
8232 mips_print_operand_punctuation (file
, '(');
8233 mips_print_operand_punctuation (file
, '<');
8238 if (mips_noreorder
.nesting_level
> 0)
8239 fputs ("\n\tnop", file
);
8243 /* Print an extra newline so that the delayed insn is separated
8244 from the following ones. This looks neater and is consistent
8245 with non-nop delayed sequences. */
8246 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8247 fputs ("\n\tnop\n", file
);
8251 if (mips_branch_likely
)
8256 if (mips_branch_likely
)
8257 fputs ("\n\tnop", file
);
8261 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8265 fputs (reg_names
[AT_REGNUM
], file
);
8269 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8273 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8277 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8281 /* When final_sequence is 0, the delay slot will be a nop. We can
8282 use the compact version for microMIPS. */
8283 if (final_sequence
== 0)
8288 /* If the delay slot instruction is short, then use the
8290 if (final_sequence
== 0
8291 || get_attr_length (final_sequence
->insn (1)) == 2)
8301 /* Initialize mips_print_operand_punct. */
8304 mips_init_print_operand_punct (void)
8308 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8309 mips_print_operand_punct
[(unsigned char) *p
] = true;
8312 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8313 associated with condition CODE. Print the condition part of the
8317 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8331 /* Conveniently, the MIPS names for these conditions are the same
8332 as their RTL equivalents. */
8333 fputs (GET_RTX_NAME (code
), file
);
8337 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8342 /* Likewise floating-point branches. */
8345 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8351 fputs ("c1eqz", file
);
8353 fputs ("c1f", file
);
8358 fputs ("c1nez", file
);
8360 fputs ("c1t", file
);
8364 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8369 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8372 mips_print_operand_punct_valid_p (unsigned char code
)
8374 return mips_print_operand_punct
[code
];
8377 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8379 'X' Print CONST_INT OP in hexadecimal format.
8380 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8381 'd' Print CONST_INT OP in decimal.
8382 'm' Print one less than CONST_INT OP in decimal.
8383 'h' Print the high-part relocation associated with OP, after stripping
8385 'R' Print the low-part relocation associated with OP.
8386 'C' Print the integer branch condition for comparison OP.
8387 'N' Print the inverse of the integer branch condition for comparison OP.
8388 'F' Print the FPU branch condition for comparison OP.
8389 'W' Print the inverse of the FPU branch condition for comparison OP.
8390 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8391 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8392 't' Like 'T', but with the EQ/NE cases reversed
8393 'Y' Print mips_fp_conditions[INTVAL (OP)]
8394 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8395 'q' Print a DSP accumulator register.
8396 'D' Print the second part of a double-word register or memory operand.
8397 'L' Print the low-order register in a double-word register operand.
8398 'M' Print high-order register in a double-word register operand.
8399 'z' Print $0 if OP is zero, otherwise print OP normally.
8400 'b' Print the address of a memory operand, without offset. */
8403 mips_print_operand (FILE *file
, rtx op
, int letter
)
8407 if (mips_print_operand_punct_valid_p (letter
))
8409 mips_print_operand_punctuation (file
, letter
);
8414 code
= GET_CODE (op
);
8419 if (CONST_INT_P (op
))
8420 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8422 output_operand_lossage ("invalid use of '%%%c'", letter
);
8426 if (CONST_INT_P (op
))
8427 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8429 output_operand_lossage ("invalid use of '%%%c'", letter
);
8433 if (CONST_INT_P (op
))
8434 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8436 output_operand_lossage ("invalid use of '%%%c'", letter
);
8440 if (CONST_INT_P (op
))
8441 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8443 output_operand_lossage ("invalid use of '%%%c'", letter
);
8449 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8453 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8457 mips_print_int_branch_condition (file
, code
, letter
);
8461 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8465 mips_print_float_branch_condition (file
, code
, letter
);
8469 mips_print_float_branch_condition (file
, reverse_condition (code
),
8476 int truth
= (code
== NE
) == (letter
== 'T');
8477 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
8482 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8483 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8485 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8490 if (ISA_HAS_8CC
|| ISA_HAS_CCF
)
8492 mips_print_operand (file
, op
, 0);
8498 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8499 fprintf (file
, "$ac0");
8500 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8501 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8503 output_operand_lossage ("invalid use of '%%%c'", letter
);
8511 unsigned int regno
= REGNO (op
);
8512 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8513 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8516 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8517 output_operand_lossage ("invalid use of '%%%c'", letter
);
8518 /* We need to print $0 .. $31 for COP0 registers. */
8519 if (COP0_REG_P (regno
))
8520 fprintf (file
, "$%s", ®_names
[regno
][4]);
8522 fprintf (file
, "%s", reg_names
[regno
]);
8528 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8529 else if (letter
== 'b')
8531 gcc_assert (REG_P (XEXP (op
, 0)));
8532 mips_print_operand (file
, XEXP (op
, 0), 0);
8534 else if (letter
&& letter
!= 'z')
8535 output_operand_lossage ("invalid use of '%%%c'", letter
);
8537 output_address (XEXP (op
, 0));
8541 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8542 fputs (reg_names
[GP_REG_FIRST
], file
);
8543 else if (letter
&& letter
!= 'z')
8544 output_operand_lossage ("invalid use of '%%%c'", letter
);
8545 else if (CONST_GP_P (op
))
8546 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8548 output_addr_const (file
, mips_strip_unspec_address (op
));
8554 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8557 mips_print_operand_address (FILE *file
, rtx x
)
8559 struct mips_address_info addr
;
8561 if (mips_classify_address (&addr
, x
, word_mode
, true))
8565 mips_print_operand (file
, addr
.offset
, 0);
8566 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8569 case ADDRESS_LO_SUM
:
8570 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8572 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8575 case ADDRESS_CONST_INT
:
8576 output_addr_const (file
, x
);
8577 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8580 case ADDRESS_SYMBOLIC
:
8581 output_addr_const (file
, mips_strip_unspec_address (x
));
8587 /* Implement TARGET_ENCODE_SECTION_INFO. */
8590 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8592 default_encode_section_info (decl
, rtl
, first
);
8594 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8596 rtx symbol
= XEXP (rtl
, 0);
8597 tree type
= TREE_TYPE (decl
);
8599 /* Encode whether the symbol is short or long. */
8600 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8601 || mips_far_type_p (type
))
8602 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8606 /* Implement TARGET_SELECT_RTX_SECTION. */
8609 mips_select_rtx_section (machine_mode mode
, rtx x
,
8610 unsigned HOST_WIDE_INT align
)
8612 /* ??? Consider using mergeable small data sections. */
8613 if (mips_rtx_constant_in_small_data_p (mode
))
8614 return get_named_section (NULL
, ".sdata", 0);
8616 return default_elf_select_rtx_section (mode
, x
, align
);
8619 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8621 The complication here is that, with the combination TARGET_ABICALLS
8622 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8623 absolute addresses, and should therefore not be included in the
8624 read-only part of a DSO. Handle such cases by selecting a normal
8625 data section instead of a read-only one. The logic apes that in
8626 default_function_rodata_section. */
8629 mips_function_rodata_section (tree decl
)
8631 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8632 return default_function_rodata_section (decl
);
8634 if (decl
&& DECL_SECTION_NAME (decl
))
8636 const char *name
= DECL_SECTION_NAME (decl
);
8637 if (DECL_COMDAT_GROUP (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8639 char *rname
= ASTRDUP (name
);
8641 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8643 else if (flag_function_sections
8644 && flag_data_sections
8645 && strncmp (name
, ".text.", 6) == 0)
8647 char *rname
= ASTRDUP (name
);
8648 memcpy (rname
+ 1, "data", 4);
8649 return get_section (rname
, SECTION_WRITE
, decl
);
8652 return data_section
;
8655 /* Implement TARGET_IN_SMALL_DATA_P. */
8658 mips_in_small_data_p (const_tree decl
)
8660 unsigned HOST_WIDE_INT size
;
8662 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8665 /* We don't yet generate small-data references for -mabicalls
8666 or VxWorks RTP code. See the related -G handling in
8667 mips_option_override. */
8668 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8671 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8675 /* Reject anything that isn't in a known small-data section. */
8676 name
= DECL_SECTION_NAME (decl
);
8677 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8680 /* If a symbol is defined externally, the assembler will use the
8681 usual -G rules when deciding how to implement macros. */
8682 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8685 else if (TARGET_EMBEDDED_DATA
)
8687 /* Don't put constants into the small data section: we want them
8688 to be in ROM rather than RAM. */
8689 if (TREE_CODE (decl
) != VAR_DECL
)
8692 if (TREE_READONLY (decl
)
8693 && !TREE_SIDE_EFFECTS (decl
)
8694 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8698 /* Enforce -mlocal-sdata. */
8699 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8702 /* Enforce -mextern-sdata. */
8703 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8705 if (DECL_EXTERNAL (decl
))
8707 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8711 /* We have traditionally not treated zero-sized objects as small data,
8712 so this is now effectively part of the ABI. */
8713 size
= int_size_in_bytes (TREE_TYPE (decl
));
8714 return size
> 0 && size
<= mips_small_data_threshold
;
8717 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8718 anchors for small data: the GP register acts as an anchor in that
8719 case. We also don't want to use them for PC-relative accesses,
8720 where the PC acts as an anchor. */
8723 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8725 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8727 case SYMBOL_PC_RELATIVE
:
8728 case SYMBOL_GP_RELATIVE
:
8732 return default_use_anchors_for_symbol_p (symbol
);
8736 /* The MIPS debug format wants all automatic variables and arguments
8737 to be in terms of the virtual frame pointer (stack pointer before
8738 any adjustment in the function), while the MIPS 3.0 linker wants
8739 the frame pointer to be the stack pointer after the initial
8740 adjustment. So, we do the adjustment here. The arg pointer (which
8741 is eliminated) points to the virtual frame pointer, while the frame
8742 pointer (which may be eliminated) points to the stack pointer after
8743 the initial adjustments. */
8746 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8748 rtx offset2
= const0_rtx
;
8749 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8752 offset
= INTVAL (offset2
);
8754 if (reg
== stack_pointer_rtx
8755 || reg
== frame_pointer_rtx
8756 || reg
== hard_frame_pointer_rtx
)
8758 offset
-= cfun
->machine
->frame
.total_size
;
8759 if (reg
== hard_frame_pointer_rtx
)
8760 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8766 /* Implement ASM_OUTPUT_EXTERNAL. */
8769 mips_output_external (FILE *file
, tree decl
, const char *name
)
8771 default_elf_asm_output_external (file
, decl
, name
);
8773 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8774 set in order to avoid putting out names that are never really
8776 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8778 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8780 /* When using assembler macros, emit .extern directives for
8781 all small-data externs so that the assembler knows how
8784 In most cases it would be safe (though pointless) to emit
8785 .externs for other symbols too. One exception is when an
8786 object is within the -G limit but declared by the user to
8787 be in a section other than .sbss or .sdata. */
8788 fputs ("\t.extern\t", file
);
8789 assemble_name (file
, name
);
8790 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8791 int_size_in_bytes (TREE_TYPE (decl
)));
8796 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8799 mips_output_filename (FILE *stream
, const char *name
)
8801 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8803 if (write_symbols
== DWARF2_DEBUG
)
8805 else if (mips_output_filename_first_time
)
8807 mips_output_filename_first_time
= 0;
8808 num_source_filenames
+= 1;
8809 current_function_file
= name
;
8810 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8811 output_quoted_string (stream
, name
);
8812 putc ('\n', stream
);
8814 /* If we are emitting stabs, let dbxout.c handle this (except for
8815 the mips_output_filename_first_time case). */
8816 else if (write_symbols
== DBX_DEBUG
)
8818 else if (name
!= current_function_file
8819 && strcmp (name
, current_function_file
) != 0)
8821 num_source_filenames
+= 1;
8822 current_function_file
= name
;
8823 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8824 output_quoted_string (stream
, name
);
8825 putc ('\n', stream
);
8829 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8831 static void ATTRIBUTE_UNUSED
8832 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8837 fputs ("\t.dtprelword\t", file
);
8841 fputs ("\t.dtpreldword\t", file
);
8847 output_addr_const (file
, x
);
8848 fputs ("+0x8000", file
);
8851 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8854 mips_dwarf_register_span (rtx reg
)
8859 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
8860 ensures that double-precision registers are treated as if they were
8861 64-bit physical registers. The code will run correctly with 32-bit or
8862 64-bit registers which means that dwarf information cannot be precise
8863 for all scenarios. We choose to state that the 64-bit values are stored
8864 in a single 64-bit 'piece'. This slightly unusual construct can then be
8865 interpreted as either a pair of registers if the registers are 32-bit or
8866 a single 64-bit register depending on hardware. */
8867 mode
= GET_MODE (reg
);
8868 if (FP_REG_P (REGNO (reg
))
8870 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8872 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, reg
));
8874 /* By default, GCC maps increasing register numbers to increasing
8875 memory locations, but paired FPRs are always little-endian,
8876 regardless of the prevailing endianness. */
8877 else if (FP_REG_P (REGNO (reg
))
8878 && TARGET_BIG_ENDIAN
8879 && MAX_FPRS_PER_FMT
> 1
8880 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8882 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8883 high
= mips_subword (reg
, true);
8884 low
= mips_subword (reg
, false);
8885 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8891 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
8894 mips_dwarf_frame_reg_mode (int regno
)
8896 machine_mode mode
= default_dwarf_frame_reg_mode (regno
);
8898 if (FP_REG_P (regno
) && mips_abi
== ABI_32
&& TARGET_FLOAT64
)
8904 /* DSP ALU can bypass data with no delays for the following pairs. */
8905 enum insn_code dspalu_bypass_table
[][2] =
8907 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8908 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8909 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8910 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8911 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8912 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8913 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8914 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8918 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8921 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8922 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8923 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8925 for (i
= 0; i
< num_bypass
; i
++)
8927 if (out_icode
== dspalu_bypass_table
[i
][0]
8928 && in_icode
== dspalu_bypass_table
[i
][1])
8934 /* Implement ASM_OUTPUT_ASCII. */
8937 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8943 fprintf (stream
, "\t.ascii\t\"");
8944 for (i
= 0; i
< len
; i
++)
8948 c
= (unsigned char) string
[i
];
8951 if (c
== '\\' || c
== '\"')
8953 putc ('\\', stream
);
8961 fprintf (stream
, "\\%03o", c
);
8965 if (cur_pos
> 72 && i
+1 < len
)
8968 fprintf (stream
, "\"\n\t.ascii\t\"");
8971 fprintf (stream
, "\"\n");
8974 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8975 Update *ADDR with the operand that should be printed. */
8978 mips_output_tls_reloc_directive (rtx
*addr
)
8980 enum mips_symbol_type type
;
8982 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8983 *addr
= mips_strip_unspec_address (*addr
);
8987 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8990 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8997 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8998 macros, mark the symbol as written so that mips_asm_output_external
8999 won't emit an .extern for it. STREAM is the output file, NAME is the
9000 name of the symbol, INIT_STRING is the string that should be written
9001 before the symbol and FINAL_STRING is the string that should be
9002 written after it. FINAL_STRING is a printf format that consumes the
9003 remaining arguments. */
9006 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
9007 const char *final_string
, ...)
9011 fputs (init_string
, stream
);
9012 assemble_name (stream
, name
);
9013 va_start (ap
, final_string
);
9014 vfprintf (stream
, final_string
, ap
);
9017 if (!TARGET_EXPLICIT_RELOCS
)
9019 tree name_tree
= get_identifier (name
);
9020 TREE_ASM_WRITTEN (name_tree
) = 1;
9024 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
9025 NAME is the name of the object and ALIGN is the required alignment
9026 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
9027 alignment argument. */
9030 mips_declare_common_object (FILE *stream
, const char *name
,
9031 const char *init_string
,
9032 unsigned HOST_WIDE_INT size
,
9033 unsigned int align
, bool takes_alignment_p
)
9035 if (!takes_alignment_p
)
9037 size
+= (align
/ BITS_PER_UNIT
) - 1;
9038 size
-= size
% (align
/ BITS_PER_UNIT
);
9039 mips_declare_object (stream
, name
, init_string
,
9040 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
9043 mips_declare_object (stream
, name
, init_string
,
9044 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
9045 size
, align
/ BITS_PER_UNIT
);
9048 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
9049 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
9052 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
9053 unsigned HOST_WIDE_INT size
,
9056 /* If the target wants uninitialized const declarations in
9057 .rdata then don't put them in .comm. */
9058 if (TARGET_EMBEDDED_DATA
9059 && TARGET_UNINIT_CONST_IN_RODATA
9060 && TREE_CODE (decl
) == VAR_DECL
9061 && TREE_READONLY (decl
)
9062 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
9064 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
9065 targetm
.asm_out
.globalize_label (stream
, name
);
9067 switch_to_section (readonly_data_section
);
9068 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
9069 mips_declare_object (stream
, name
, "",
9070 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
9074 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
9078 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
9079 extern int size_directive_output
;
9081 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
9082 definitions except that it uses mips_declare_object to emit the label. */
9085 mips_declare_object_name (FILE *stream
, const char *name
,
9086 tree decl ATTRIBUTE_UNUSED
)
9088 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9089 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
9092 size_directive_output
= 0;
9093 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
9097 size_directive_output
= 1;
9098 size
= int_size_in_bytes (TREE_TYPE (decl
));
9099 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9102 mips_declare_object (stream
, name
, "", ":\n");
9105 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
9108 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
9112 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
9113 if (!flag_inhibit_size_directive
9114 && DECL_SIZE (decl
) != 0
9117 && DECL_INITIAL (decl
) == error_mark_node
9118 && !size_directive_output
)
9122 size_directive_output
= 1;
9123 size
= int_size_in_bytes (TREE_TYPE (decl
));
9124 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9129 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9130 with the current ABI. */
9133 mips_mdebug_abi_name (void)
9146 return TARGET_64BIT
? "eabi64" : "eabi32";
9152 /* Implement TARGET_ASM_FILE_START. */
9155 mips_file_start (void)
9157 default_file_start ();
9159 /* Generate a special section to describe the ABI switches used to
9160 produce the resultant binary. */
9162 /* Record the ABI itself. Modern versions of binutils encode
9163 this information in the ELF header flags, but GDB needs the
9164 information in order to correctly debug binaries produced by
9165 older binutils. See the function mips_gdbarch_init in
9167 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
9168 mips_mdebug_abi_name ());
9170 /* There is no ELF header flag to distinguish long32 forms of the
9171 EABI from long64 forms. Emit a special section to help tools
9172 such as GDB. Do the same for o64, which is sometimes used with
9174 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
9175 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
9176 "\t.previous\n", TARGET_LONG64
? 64 : 32);
9178 /* Record the NaN encoding. */
9179 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
9180 fprintf (asm_out_file
, "\t.nan\t%s\n",
9181 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
9183 #ifdef HAVE_AS_DOT_MODULE
9184 /* Record the FP ABI. See below for comments. */
9185 if (TARGET_NO_FLOAT
)
9186 #ifdef HAVE_AS_GNU_ATTRIBUTE
9187 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file
);
9191 else if (!TARGET_HARD_FLOAT_ABI
)
9192 fputs ("\t.module\tsoftfloat\n", asm_out_file
);
9193 else if (!TARGET_DOUBLE_FLOAT
)
9194 fputs ("\t.module\tsinglefloat\n", asm_out_file
);
9195 else if (TARGET_FLOATXX
)
9196 fputs ("\t.module\tfp=xx\n", asm_out_file
);
9197 else if (TARGET_FLOAT64
)
9198 fputs ("\t.module\tfp=64\n", asm_out_file
);
9200 fputs ("\t.module\tfp=32\n", asm_out_file
);
9202 if (TARGET_ODD_SPREG
)
9203 fputs ("\t.module\toddspreg\n", asm_out_file
);
9205 fputs ("\t.module\tnooddspreg\n", asm_out_file
);
9208 #ifdef HAVE_AS_GNU_ATTRIBUTE
9212 /* No floating-point operations, -mno-float. */
9213 if (TARGET_NO_FLOAT
)
9215 /* Soft-float code, -msoft-float. */
9216 else if (!TARGET_HARD_FLOAT_ABI
)
9218 /* Single-float code, -msingle-float. */
9219 else if (!TARGET_DOUBLE_FLOAT
)
9221 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9223 This case used 12 callee-saved double-precision registers
9224 and is deprecated. */
9225 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9226 else if (TARGET_FLOATXX
)
9228 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9229 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
&& TARGET_ODD_SPREG
)
9231 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9232 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9234 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9238 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
9243 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9244 if (TARGET_ABICALLS
)
9246 fprintf (asm_out_file
, "\t.abicalls\n");
9247 if (TARGET_ABICALLS_PIC0
)
9248 fprintf (asm_out_file
, "\t.option\tpic0\n");
9251 if (flag_verbose_asm
)
9252 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9254 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
9257 /* Implement TARGET_ASM_CODE_END. */
9260 mips_code_end (void)
9262 mips_finish_stub (&mips16_rdhwr_stub
);
9263 mips_finish_stub (&mips16_get_fcsr_stub
);
9264 mips_finish_stub (&mips16_set_fcsr_stub
);
9267 /* Make the last instruction frame-related and note that it performs
9268 the operation described by FRAME_PATTERN. */
9271 mips_set_frame_expr (rtx frame_pattern
)
9275 insn
= get_last_insn ();
9276 RTX_FRAME_RELATED_P (insn
) = 1;
9277 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9282 /* Return a frame-related rtx that stores REG at MEM.
9283 REG must be a single register. */
9286 mips_frame_set (rtx mem
, rtx reg
)
9290 set
= gen_rtx_SET (mem
, reg
);
9291 RTX_FRAME_RELATED_P (set
) = 1;
9296 /* Record that the epilogue has restored call-saved register REG. */
9299 mips_add_cfa_restore (rtx reg
)
9301 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
9302 mips_epilogue
.cfa_restores
);
9305 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9306 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9307 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9308 static const unsigned char mips16e_s2_s8_regs
[] = {
9309 30, 23, 22, 21, 20, 19, 18
9311 static const unsigned char mips16e_a0_a3_regs
[] = {
9315 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9316 ordered from the uppermost in memory to the lowest in memory. */
9317 static const unsigned char mips16e_save_restore_regs
[] = {
9318 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9321 /* Return the index of the lowest X in the range [0, SIZE) for which
9322 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9325 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
9330 for (i
= 0; i
< size
; i
++)
9331 if (BITSET_P (mask
, regs
[i
]))
9337 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9338 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9339 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9340 is true for all indexes (X, SIZE). */
9343 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
9344 unsigned int size
, unsigned int *num_regs_ptr
)
9348 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
9349 for (i
++; i
< size
; i
++)
9350 if (!BITSET_P (*mask_ptr
, regs
[i
]))
9353 *mask_ptr
|= 1 << regs
[i
];
9357 /* Return a simplified form of X using the register values in REG_VALUES.
9358 REG_VALUES[R] is the last value assigned to hard register R, or null
9359 if R has not been modified.
9361 This function is rather limited, but is good enough for our purposes. */
9364 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
9366 x
= avoid_constant_pool_reference (x
);
9370 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9371 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
9372 x0
, GET_MODE (XEXP (x
, 0)));
9375 if (ARITHMETIC_P (x
))
9377 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
9378 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
9379 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
9383 && reg_values
[REGNO (x
)]
9384 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
9385 return reg_values
[REGNO (x
)];
9390 /* Return true if (set DEST SRC) stores an argument register into its
9391 caller-allocated save slot, storing the number of that argument
9392 register in *REGNO_PTR if so. REG_VALUES is as for
9393 mips16e_collect_propagate_value. */
9396 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
9397 unsigned int *regno_ptr
)
9399 unsigned int argno
, regno
;
9400 HOST_WIDE_INT offset
, required_offset
;
9403 /* Check that this is a word-mode store. */
9404 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
9407 /* Check that the register being saved is an unmodified argument
9409 regno
= REGNO (src
);
9410 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
9412 argno
= regno
- GP_ARG_FIRST
;
9414 /* Check whether the address is an appropriate stack-pointer or
9415 frame-pointer access. */
9416 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
9417 mips_split_plus (addr
, &base
, &offset
);
9418 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
9419 if (base
== hard_frame_pointer_rtx
)
9420 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9421 else if (base
!= stack_pointer_rtx
)
9423 if (offset
!= required_offset
)
9430 /* A subroutine of mips_expand_prologue, called only when generating
9431 MIPS16e SAVE instructions. Search the start of the function for any
9432 instructions that save argument registers into their caller-allocated
9433 save slots. Delete such instructions and return a value N such that
9434 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9435 instructions redundant. */
9438 mips16e_collect_argument_saves (void)
9440 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
9441 rtx_insn
*insn
, *next
;
9443 unsigned int nargs
, regno
;
9445 push_topmost_sequence ();
9447 memset (reg_values
, 0, sizeof (reg_values
));
9448 for (insn
= get_insns (); insn
; insn
= next
)
9450 next
= NEXT_INSN (insn
);
9451 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9457 set
= PATTERN (insn
);
9458 if (GET_CODE (set
) != SET
)
9461 dest
= SET_DEST (set
);
9462 src
= SET_SRC (set
);
9463 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9465 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9468 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9471 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9472 reg_values
[REGNO (dest
)]
9473 = mips16e_collect_propagate_value (src
, reg_values
);
9477 pop_topmost_sequence ();
9482 /* Return a move between register REGNO and memory location SP + OFFSET.
9483 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9484 Make the move a load if RESTORE_P, otherwise make it a store. */
9487 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9488 HOST_WIDE_INT offset
, unsigned int regno
)
9492 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9494 reg
= gen_rtx_REG (SImode
, regno
);
9497 mips_add_cfa_restore (reg
);
9498 return gen_rtx_SET (reg
, mem
);
9501 return gen_rtx_SET (mem
, reg
);
9502 return mips_frame_set (mem
, reg
);
9505 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9506 The instruction must:
9508 - Allocate or deallocate SIZE bytes in total; SIZE is known
9511 - Save or restore as many registers in *MASK_PTR as possible.
9512 The instruction saves the first registers at the top of the
9513 allocated area, with the other registers below it.
9515 - Save NARGS argument registers above the allocated area.
9517 (NARGS is always zero if RESTORE_P.)
9519 The SAVE and RESTORE instructions cannot save and restore all general
9520 registers, so there may be some registers left over for the caller to
9521 handle. Destructively modify *MASK_PTR so that it contains the registers
9522 that still need to be saved or restored. The caller can save these
9523 registers in the memory immediately below *OFFSET_PTR, which is a
9524 byte offset from the bottom of the allocated stack area. */
9527 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9528 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9532 HOST_WIDE_INT offset
, top_offset
;
9533 unsigned int i
, regno
;
9536 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9538 /* Calculate the number of elements in the PARALLEL. We need one element
9539 for the stack adjustment, one for each argument register save, and one
9540 for each additional register move. */
9542 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9543 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9546 /* Create the final PARALLEL. */
9547 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9550 /* Add the stack pointer adjustment. */
9551 set
= gen_rtx_SET (stack_pointer_rtx
,
9552 plus_constant (Pmode
, stack_pointer_rtx
,
9553 restore_p
? size
: -size
));
9554 RTX_FRAME_RELATED_P (set
) = 1;
9555 XVECEXP (pattern
, 0, n
++) = set
;
9557 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9558 top_offset
= restore_p
? size
: 0;
9560 /* Save the arguments. */
9561 for (i
= 0; i
< nargs
; i
++)
9563 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9564 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9566 XVECEXP (pattern
, 0, n
++) = set
;
9569 /* Then fill in the other register moves. */
9570 offset
= top_offset
;
9571 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9573 regno
= mips16e_save_restore_regs
[i
];
9574 if (BITSET_P (*mask_ptr
, regno
))
9576 offset
-= UNITS_PER_WORD
;
9577 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9578 XVECEXP (pattern
, 0, n
++) = set
;
9579 *mask_ptr
&= ~(1 << regno
);
9583 /* Tell the caller what offset it should use for the remaining registers. */
9584 *offset_ptr
= size
+ (offset
- top_offset
);
9586 gcc_assert (n
== XVECLEN (pattern
, 0));
9591 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9592 pointer. Return true if PATTERN matches the kind of instruction
9593 generated by mips16e_build_save_restore. If INFO is nonnull,
9594 initialize it when returning true. */
9597 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9598 struct mips16e_save_restore_info
*info
)
9600 unsigned int i
, nargs
, mask
, extra
;
9601 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9602 rtx set
, reg
, mem
, base
;
9605 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9608 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9609 top_offset
= adjust
> 0 ? adjust
: 0;
9611 /* Interpret all other members of the PARALLEL. */
9612 save_offset
= top_offset
- UNITS_PER_WORD
;
9616 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9618 /* Check that we have a SET. */
9619 set
= XVECEXP (pattern
, 0, n
);
9620 if (GET_CODE (set
) != SET
)
9623 /* Check that the SET is a load (if restoring) or a store
9625 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9629 /* Check that the address is the sum of the stack pointer and a
9630 possibly-zero constant offset. */
9631 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9632 if (base
!= stack_pointer_rtx
)
9635 /* Check that SET's other operand is a register. */
9636 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9640 /* Check for argument saves. */
9641 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9642 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9644 else if (offset
== save_offset
)
9646 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9647 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9650 mask
|= 1 << REGNO (reg
);
9651 save_offset
-= UNITS_PER_WORD
;
9657 /* Check that the restrictions on register ranges are met. */
9659 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9660 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9661 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9662 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9666 /* Make sure that the topmost argument register is not saved twice.
9667 The checks above ensure that the same is then true for the other
9668 argument registers. */
9669 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9672 /* Pass back information, if requested. */
9675 info
->nargs
= nargs
;
9677 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9683 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9684 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9685 the null terminator. */
9688 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9689 unsigned int max_reg
)
9691 if (min_reg
!= max_reg
)
9692 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9694 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9698 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9699 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9702 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9704 static char buffer
[300];
9706 struct mips16e_save_restore_info info
;
9707 unsigned int i
, end
;
9710 /* Parse the pattern. */
9711 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9714 /* Add the mnemonic. */
9715 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9718 /* Save the arguments. */
9720 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9721 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9722 else if (info
.nargs
== 1)
9723 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9725 /* Emit the amount of stack space to allocate or deallocate. */
9726 s
+= sprintf (s
, "%d", (int) info
.size
);
9728 /* Save or restore $16. */
9729 if (BITSET_P (info
.mask
, 16))
9730 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9732 /* Save or restore $17. */
9733 if (BITSET_P (info
.mask
, 17))
9734 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9736 /* Save or restore registers in the range $s2...$s8, which
9737 mips16e_s2_s8_regs lists in decreasing order. Note that this
9738 is a software register range; the hardware registers are not
9739 numbered consecutively. */
9740 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9741 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9743 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9744 mips16e_s2_s8_regs
[i
]);
9746 /* Save or restore registers in the range $a0...$a3. */
9747 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9748 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9750 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9751 mips16e_a0_a3_regs
[end
- 1]);
9753 /* Save or restore $31. */
9754 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9755 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9760 /* Return true if the current function returns its value in a floating-point
9761 register in MIPS16 mode. */
9764 mips16_cfun_returns_in_fpr_p (void)
9766 tree return_type
= DECL_RESULT (current_function_decl
);
9767 return (TARGET_MIPS16
9768 && TARGET_HARD_FLOAT_ABI
9769 && !aggregate_value_p (return_type
, current_function_decl
)
9770 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9773 /* Return true if predicate PRED is true for at least one instruction.
9774 Cache the result in *CACHE, and assume that the result is true
9775 if *CACHE is already true. */
9778 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx_insn
*))
9780 rtx_insn
*insn
, *subinsn
;
9784 push_topmost_sequence ();
9785 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9786 FOR_EACH_SUBINSN (subinsn
, insn
)
9787 if (USEFUL_INSN_P (subinsn
) && pred (subinsn
))
9792 pop_topmost_sequence ();
9797 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9798 See mips_cfun_has_inflexible_gp_ref_p for details. */
9801 mips_insn_has_inflexible_gp_ref_p (rtx_insn
*insn
)
9803 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9804 indicate that the target could be a traditional MIPS
9805 lazily-binding stub. */
9806 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9809 /* Return true if the current function refers to the global pointer
9810 in a way that forces $28 to be valid. This means that we can't
9811 change the choice of global pointer, even for NewABI code.
9813 One example of this (and one which needs several checks) is that
9814 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9815 (This restriction does not apply to PLTs.) */
9818 mips_cfun_has_inflexible_gp_ref_p (void)
9820 /* If the function has a nonlocal goto, $28 must hold the correct
9821 global pointer for the target function. That is, the target
9822 of the goto implicitly uses $28. */
9823 if (crtl
->has_nonlocal_goto
)
9826 if (TARGET_ABICALLS_PIC2
)
9828 /* Symbolic accesses implicitly use the global pointer unless
9829 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9830 might go to traditional MIPS lazy-binding stubs. */
9831 if (!TARGET_EXPLICIT_RELOCS
)
9834 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9835 can be lazily-bound. */
9839 /* MIPS16 functions that return in FPRs need to call an
9840 external libgcc routine. This call is only made explict
9841 during mips_expand_epilogue, and it too might be lazily bound. */
9842 if (mips16_cfun_returns_in_fpr_p ())
9846 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9847 mips_insn_has_inflexible_gp_ref_p
);
9850 /* Return true if INSN refers to the global pointer in a "flexible" way.
9851 See mips_cfun_has_flexible_gp_ref_p for details. */
9854 mips_insn_has_flexible_gp_ref_p (rtx_insn
*insn
)
9856 return (get_attr_got (insn
) != GOT_UNSET
9857 || mips_small_data_pattern_p (PATTERN (insn
))
9858 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9861 /* Return true if the current function references the global pointer,
9862 but if those references do not inherently require the global pointer
9863 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9866 mips_cfun_has_flexible_gp_ref_p (void)
9868 /* Reload can sometimes introduce constant pool references
9869 into a function that otherwise didn't need them. For example,
9870 suppose we have an instruction like:
9872 (set (reg:DF R1) (float:DF (reg:SI R2)))
9874 If R2 turns out to be a constant such as 1, the instruction may
9875 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9876 the option of using this constant if R2 doesn't get allocated
9879 In cases like these, reload will have added the constant to the
9880 pool but no instruction will yet refer to it. */
9881 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9884 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9885 mips_insn_has_flexible_gp_ref_p
);
9888 /* Return the register that should be used as the global pointer
9889 within this function. Return INVALID_REGNUM if the function
9890 doesn't need a global pointer. */
9893 mips_global_pointer (void)
9897 /* $gp is always available unless we're using a GOT. */
9898 if (!TARGET_USE_GOT
)
9899 return GLOBAL_POINTER_REGNUM
;
9901 /* If there are inflexible references to $gp, we must use the
9902 standard register. */
9903 if (mips_cfun_has_inflexible_gp_ref_p ())
9904 return GLOBAL_POINTER_REGNUM
;
9906 /* If there are no current references to $gp, then the only uses
9907 we can introduce later are those involved in long branches. */
9908 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9909 return INVALID_REGNUM
;
9911 /* If the global pointer is call-saved, try to use a call-clobbered
9913 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9914 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9915 if (!df_regs_ever_live_p (regno
)
9916 && call_really_used_regs
[regno
]
9917 && !fixed_regs
[regno
]
9918 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9921 return GLOBAL_POINTER_REGNUM
;
9924 /* Return true if the current function's prologue must load the global
9925 pointer value into pic_offset_table_rtx and store the same value in
9926 the function's cprestore slot (if any).
9928 One problem we have to deal with is that, when emitting GOT-based
9929 position independent code, long-branch sequences will need to load
9930 the address of the branch target from the GOT. We don't know until
9931 the very end of compilation whether (and where) the function needs
9932 long branches, so we must ensure that _any_ branch can access the
9933 global pointer in some form. However, we do not want to pessimize
9934 the usual case in which all branches are short.
9936 We handle this as follows:
9938 (1) During reload, we set cfun->machine->global_pointer to
9939 INVALID_REGNUM if we _know_ that the current function
9940 doesn't need a global pointer. This is only valid if
9941 long branches don't need the GOT.
9943 Otherwise, we assume that we might need a global pointer
9944 and pick an appropriate register.
9946 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9947 we ensure that the global pointer is available at every
9948 block boundary bar entry and exit. We do this in one of two ways:
9950 - If the function has a cprestore slot, we ensure that this
9951 slot is valid at every branch. However, as explained in
9952 point (6) below, there is no guarantee that pic_offset_table_rtx
9953 itself is valid if new uses of the global pointer are introduced
9954 after the first post-epilogue split.
9956 We guarantee that the cprestore slot is valid by loading it
9957 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9958 this register live at every block boundary bar function entry
9959 and exit. It is then invalid to move the load (and thus the
9960 preceding store) across a block boundary.
9962 - If the function has no cprestore slot, we guarantee that
9963 pic_offset_table_rtx itself is valid at every branch.
9965 See mips_eh_uses for the handling of the register liveness.
9967 (3) During prologue and epilogue generation, we emit "ghost"
9968 placeholder instructions to manipulate the global pointer.
9970 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9971 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9972 that the function needs a global pointer. (There is no need to set
9973 them earlier than this, and doing it as late as possible leads to
9974 fewer false positives.)
9976 (5) If cfun->machine->must_initialize_gp_p is true during a
9977 split_insns pass, we split the ghost instructions into real
9978 instructions. These split instructions can then be optimized in
9979 the usual way. Otherwise, we keep the ghost instructions intact,
9980 and optimize for the case where they aren't needed. We still
9981 have the option of splitting them later, if we need to introduce
9982 new uses of the global pointer.
9984 For example, the scheduler ignores a ghost instruction that
9985 stores $28 to the stack, but it handles the split form of
9986 the ghost instruction as an ordinary store.
9988 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9989 is true during the first post-epilogue split_insns pass, we split
9990 calls and restore_gp patterns into instructions that explicitly
9991 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9992 we split these patterns into instructions that _don't_ load from
9995 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9996 time of the split, then any instructions that exist at that time
9997 can make free use of pic_offset_table_rtx. However, if we want
9998 to introduce new uses of the global pointer after the split,
9999 we must explicitly load the value from the cprestore slot, since
10000 pic_offset_table_rtx itself might not be valid at a given point
10003 The idea is that we want to be able to delete redundant
10004 loads from the cprestore slot in the usual case where no
10005 long branches are needed.
10007 (7) If cfun->machine->must_initialize_gp_p is still false at the end
10008 of md_reorg, we decide whether the global pointer is needed for
10009 long branches. If so, we set cfun->machine->must_initialize_gp_p
10010 to true and split the ghost instructions into real instructions
10013 Note that the ghost instructions must have a zero length for three reasons:
10015 - Giving the length of the underlying $gp sequence might cause
10016 us to use long branches in cases where they aren't really needed.
10018 - They would perturb things like alignment calculations.
10020 - More importantly, the hazard detection in md_reorg relies on
10021 empty instructions having a zero length.
10023 If we find a long branch and split the ghost instructions at the
10024 end of md_reorg, the split could introduce more long branches.
10025 That isn't a problem though, because we still do the split before
10026 the final shorten_branches pass.
10028 This is extremely ugly, but it seems like the best compromise between
10029 correctness and efficiency. */
10032 mips_must_initialize_gp_p (void)
10034 return cfun
->machine
->must_initialize_gp_p
;
10037 /* Return true if REGNO is a register that is ordinarily call-clobbered
10038 but must nevertheless be preserved by an interrupt handler. */
10041 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
10043 if ((ISA_HAS_HILO
|| TARGET_DSP
)
10044 && MD_REG_P (regno
))
10047 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
10050 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
10052 /* $0 is hard-wired. */
10053 if (regno
== GP_REG_FIRST
)
10056 /* The interrupt handler can treat kernel registers as
10057 scratch registers. */
10058 if (KERNEL_REG_P (regno
))
10061 /* The function will return the stack pointer to its original value
10063 if (regno
== STACK_POINTER_REGNUM
)
10066 /* Otherwise, return true for registers that aren't ordinarily
10068 return call_really_used_regs
[regno
];
10074 /* Return true if the current function should treat register REGNO
10078 mips_cfun_call_saved_reg_p (unsigned int regno
)
10080 /* If the user makes an ordinarily-call-saved register global,
10081 that register is no longer call-saved. */
10082 if (global_regs
[regno
])
10085 /* Interrupt handlers need to save extra registers. */
10086 if (cfun
->machine
->interrupt_handler_p
10087 && mips_interrupt_extra_call_saved_reg_p (regno
))
10090 /* call_insns preserve $28 unless they explicitly say otherwise,
10091 so call_really_used_regs[] treats $28 as call-saved. However,
10092 we want the ABI property rather than the default call_insn
10094 return (regno
== GLOBAL_POINTER_REGNUM
10095 ? TARGET_CALL_SAVED_GP
10096 : !call_really_used_regs
[regno
]);
10099 /* Return true if the function body might clobber register REGNO.
10100 We know that REGNO is call-saved. */
10103 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
10105 /* Some functions should be treated as clobbering all call-saved
10107 if (crtl
->saves_all_registers
)
10110 /* DF handles cases where a register is explicitly referenced in
10111 the rtl. Incoming values are passed in call-clobbered registers,
10112 so we can assume that any live call-saved register is set within
10114 if (df_regs_ever_live_p (regno
))
10117 /* Check for registers that are clobbered by FUNCTION_PROFILER.
10118 These clobbers are not explicit in the rtl. */
10119 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
10122 /* If we're using a call-saved global pointer, the function's
10123 prologue will need to set it up. */
10124 if (cfun
->machine
->global_pointer
== regno
)
10127 /* The function's prologue will need to set the frame pointer if
10128 frame_pointer_needed. */
10129 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
10132 /* If a MIPS16 function returns a value in FPRs, its epilogue
10133 will need to call an external libgcc routine. This yet-to-be
10134 generated call_insn will clobber $31. */
10135 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
10138 /* If REGNO is ordinarily call-clobbered, we must assume that any
10139 called function could modify it. */
10140 if (cfun
->machine
->interrupt_handler_p
10142 && mips_interrupt_extra_call_saved_reg_p (regno
))
10148 /* Return true if the current function must save register REGNO. */
10151 mips_save_reg_p (unsigned int regno
)
10153 if (mips_cfun_call_saved_reg_p (regno
))
10155 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
10158 /* Save both registers in an FPR pair if either one is used. This is
10159 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10160 register to be used without the even register. */
10161 if (FP_REG_P (regno
)
10162 && MAX_FPRS_PER_FMT
== 2
10163 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
10167 /* We need to save the incoming return address if __builtin_eh_return
10168 is being used to set a different return address. */
10169 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
10175 /* Populate the current function's mips_frame_info structure.
10177 MIPS stack frames look like:
10179 +-------------------------------+
10181 | incoming stack arguments |
10183 +-------------------------------+
10185 | caller-allocated save area |
10186 A | for register arguments |
10188 +-------------------------------+ <-- incoming stack pointer
10190 | callee-allocated save area |
10191 B | for arguments that are |
10192 | split between registers and |
10195 +-------------------------------+ <-- arg_pointer_rtx
10197 C | callee-allocated save area |
10198 | for register varargs |
10200 +-------------------------------+ <-- frame_pointer_rtx
10201 | | + cop0_sp_offset
10202 | COP0 reg save area | + UNITS_PER_WORD
10204 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10205 | | + UNITS_PER_WORD
10206 | accumulator save area |
10208 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10209 | | + UNITS_PER_HWFPVALUE
10212 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10213 | | + UNITS_PER_WORD
10216 +-------------------------------+ <-- frame_pointer_rtx with
10217 | | \ -fstack-protector
10218 | local variables | | var_size
10220 +-------------------------------+
10222 | $gp save area | | cprestore_size
10224 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10226 | outgoing stack arguments | |
10228 +-------------------------------+ | args_size
10230 | caller-allocated save area | |
10231 | for register arguments | |
10233 +-------------------------------+ <-- stack_pointer_rtx
10234 frame_pointer_rtx without
10236 hard_frame_pointer_rtx for
10239 At least two of A, B and C will be empty.
10241 Dynamic stack allocations such as alloca insert data at point P.
10242 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10243 hard_frame_pointer_rtx unchanged. */
10246 mips_compute_frame_info (void)
10248 struct mips_frame_info
*frame
;
10249 HOST_WIDE_INT offset
, size
;
10250 unsigned int regno
, i
;
10252 /* Set this function's interrupt properties. */
10253 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
10255 if (mips_isa_rev
< 2)
10256 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10257 else if (TARGET_HARD_FLOAT
)
10258 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10259 else if (TARGET_MIPS16
)
10260 error ("interrupt handlers cannot be MIPS16 functions");
10263 cfun
->machine
->interrupt_handler_p
= true;
10264 cfun
->machine
->use_shadow_register_set_p
=
10265 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
10266 cfun
->machine
->keep_interrupts_masked_p
=
10267 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10268 cfun
->machine
->use_debug_exception_return_p
=
10269 mips_use_debug_exception_return_p (TREE_TYPE
10270 (current_function_decl
));
10274 frame
= &cfun
->machine
->frame
;
10275 memset (frame
, 0, sizeof (*frame
));
10276 size
= get_frame_size ();
10278 cfun
->machine
->global_pointer
= mips_global_pointer ();
10280 /* The first two blocks contain the outgoing argument area and the $gp save
10281 slot. This area isn't needed in leaf functions, but if the
10282 target-independent frame size is nonzero, we have already committed to
10283 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10284 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
10286 /* The MIPS 3.0 linker does not like functions that dynamically
10287 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10288 looks like we are trying to create a second frame pointer to the
10289 function, so allocate some stack space to make it happy. */
10290 if (cfun
->calls_alloca
)
10291 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
10293 frame
->args_size
= 0;
10294 frame
->cprestore_size
= 0;
10298 frame
->args_size
= crtl
->outgoing_args_size
;
10299 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
10301 offset
= frame
->args_size
+ frame
->cprestore_size
;
10303 /* Move above the local variables. */
10304 frame
->var_size
= MIPS_STACK_ALIGN (size
);
10305 offset
+= frame
->var_size
;
10307 /* Find out which GPRs we need to save. */
10308 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10309 if (mips_save_reg_p (regno
))
10312 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
10315 /* If this function calls eh_return, we must also save and restore the
10316 EH data registers. */
10317 if (crtl
->calls_eh_return
)
10318 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
10321 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
10324 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10325 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10326 save all later registers too. */
10327 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10329 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
10330 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
10331 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
10332 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
10335 /* Move above the GPR save area. */
10336 if (frame
->num_gp
> 0)
10338 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
10339 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
10342 /* Find out which FPRs we need to save. This loop must iterate over
10343 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10344 if (TARGET_HARD_FLOAT
)
10345 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
10346 if (mips_save_reg_p (regno
))
10348 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
10349 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
10352 /* Move above the FPR save area. */
10353 if (frame
->num_fp
> 0)
10355 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
10356 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
10359 /* Add in space for the interrupt context information. */
10360 if (cfun
->machine
->interrupt_handler_p
)
10363 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
10366 frame
->acc_mask
|= (1 << 0);
10369 /* Check accumulators 1, 2, 3. */
10370 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
10371 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
10374 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
10377 /* All interrupt context functions need space to preserve STATUS. */
10378 frame
->num_cop0_regs
++;
10380 /* If we don't keep interrupts masked, we need to save EPC. */
10381 if (!cfun
->machine
->keep_interrupts_masked_p
)
10382 frame
->num_cop0_regs
++;
10385 /* Move above the accumulator save area. */
10386 if (frame
->num_acc
> 0)
10388 /* Each accumulator needs 2 words. */
10389 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
10390 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
10393 /* Move above the COP0 register save area. */
10394 if (frame
->num_cop0_regs
> 0)
10396 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
10397 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
10400 /* Move above the callee-allocated varargs save area. */
10401 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
10402 frame
->arg_pointer_offset
= offset
;
10404 /* Move above the callee-allocated area for pretend stack arguments. */
10405 offset
+= crtl
->args
.pretend_args_size
;
10406 frame
->total_size
= offset
;
10408 /* Work out the offsets of the save areas from the top of the frame. */
10409 if (frame
->gp_sp_offset
> 0)
10410 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
10411 if (frame
->fp_sp_offset
> 0)
10412 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
10413 if (frame
->acc_sp_offset
> 0)
10414 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
10415 if (frame
->num_cop0_regs
> 0)
10416 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
10418 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10419 arguments. This tends to increase the chances of using unextended
10420 instructions for local variables and incoming arguments. */
10422 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10425 /* Return the style of GP load sequence that is being used for the
10426 current function. */
10428 enum mips_loadgp_style
10429 mips_current_loadgp_style (void)
10431 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
10432 return LOADGP_NONE
;
10434 if (TARGET_RTP_PIC
)
10437 if (TARGET_ABSOLUTE_ABICALLS
)
10438 return LOADGP_ABSOLUTE
;
10440 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
10443 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10446 mips_frame_pointer_required (void)
10448 /* If the function contains dynamic stack allocations, we need to
10449 use the frame pointer to access the static parts of the frame. */
10450 if (cfun
->calls_alloca
)
10453 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10454 reload may be unable to compute the address of a local variable,
10455 since there is no way to add a large constant to the stack pointer
10456 without using a second temporary register. */
10459 mips_compute_frame_info ();
10460 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10467 /* Make sure that we're not trying to eliminate to the wrong hard frame
10471 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10473 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10476 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10477 or argument pointer. TO is either the stack pointer or hard frame
10481 mips_initial_elimination_offset (int from
, int to
)
10483 HOST_WIDE_INT offset
;
10485 mips_compute_frame_info ();
10487 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10490 case FRAME_POINTER_REGNUM
:
10491 if (FRAME_GROWS_DOWNWARD
)
10492 offset
= (cfun
->machine
->frame
.args_size
10493 + cfun
->machine
->frame
.cprestore_size
10494 + cfun
->machine
->frame
.var_size
);
10499 case ARG_POINTER_REGNUM
:
10500 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10504 gcc_unreachable ();
10507 if (to
== HARD_FRAME_POINTER_REGNUM
)
10508 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10513 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10516 mips_extra_live_on_entry (bitmap regs
)
10518 if (TARGET_USE_GOT
)
10520 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10521 the global pointer. */
10522 if (!TARGET_ABSOLUTE_ABICALLS
)
10523 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10525 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10526 the global pointer. */
10528 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10530 /* See the comment above load_call<mode> for details. */
10531 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10535 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10539 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10544 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10547 /* Emit code to change the current function's return address to
10548 ADDRESS. SCRATCH is available as a scratch register, if needed.
10549 ADDRESS and SCRATCH are both word-mode GPRs. */
10552 mips_set_return_address (rtx address
, rtx scratch
)
10556 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10557 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10558 cfun
->machine
->frame
.gp_sp_offset
);
10559 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10562 /* Return true if the current function has a cprestore slot. */
10565 mips_cfun_has_cprestore_slot_p (void)
10567 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10568 && cfun
->machine
->frame
.cprestore_size
> 0);
10571 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10572 cprestore slot. LOAD_P is true if the caller wants to load from
10573 the cprestore slot; it is false if the caller wants to store to
10577 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10580 const struct mips_frame_info
*frame
;
10582 frame
= &cfun
->machine
->frame
;
10583 /* .cprestore always uses the stack pointer instead of the frame pointer.
10584 We have a free choice for direct stores for non-MIPS16 functions,
10585 and for MIPS16 functions whose cprestore slot is in range of the
10586 stack pointer. Using the stack pointer would sometimes give more
10587 (early) scheduling freedom, but using the frame pointer would
10588 sometimes give more (late) scheduling freedom. It's hard to
10589 predict which applies to a given function, so let's keep things
10592 Loads must always use the frame pointer in functions that call
10593 alloca, and there's little benefit to using the stack pointer
10595 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10597 *base
= hard_frame_pointer_rtx
;
10598 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10602 *base
= stack_pointer_rtx
;
10603 *offset
= frame
->args_size
;
10607 /* Return true if X is the load or store address of the cprestore slot;
10608 LOAD_P says which. */
10611 mips_cprestore_address_p (rtx x
, bool load_p
)
10613 rtx given_base
, required_base
;
10614 HOST_WIDE_INT given_offset
, required_offset
;
10616 mips_split_plus (x
, &given_base
, &given_offset
);
10617 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10618 return given_base
== required_base
&& given_offset
== required_offset
;
10621 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10622 going to load from it, false if we are going to store to it.
10623 Use TEMP as a temporary register if need be. */
10626 mips_cprestore_slot (rtx temp
, bool load_p
)
10629 HOST_WIDE_INT offset
;
10631 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10632 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10635 /* Emit instructions to save global pointer value GP into cprestore
10636 slot MEM. OFFSET is the offset that MEM applies to the base register.
10638 MEM may not be a legitimate address. If it isn't, TEMP is a
10639 temporary register that can be used, otherwise it is a SCRATCH. */
10642 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10644 if (TARGET_CPRESTORE_DIRECTIVE
)
10646 gcc_assert (gp
== pic_offset_table_rtx
);
10647 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10650 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10653 /* Restore $gp from its save slot, using TEMP as a temporary base register
10654 if need be. This function is for o32 and o64 abicalls only.
10656 See mips_must_initialize_gp_p for details about how we manage the
10660 mips_restore_gp_from_cprestore_slot (rtx temp
)
10662 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10664 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10666 emit_note (NOTE_INSN_DELETED
);
10672 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10673 mips_emit_move (pic_offset_table_rtx
, temp
);
10676 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10677 if (!TARGET_EXPLICIT_RELOCS
)
10678 emit_insn (gen_blockage ());
10681 /* A function to save or store a register. The first argument is the
10682 register and the second is the stack slot. */
10683 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10685 /* Use FN to save or restore register REGNO. MODE is the register's
10686 mode and OFFSET is the offset of its save slot from the current
10690 mips_save_restore_reg (machine_mode mode
, int regno
,
10691 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10695 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10697 fn (gen_rtx_REG (mode
, regno
), mem
);
10700 /* Call FN for each accumlator that is saved by the current function.
10701 SP_OFFSET is the offset of the current stack pointer from the start
10705 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10707 HOST_WIDE_INT offset
;
10710 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10711 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10713 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10714 offset
-= UNITS_PER_WORD
;
10715 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10716 offset
-= UNITS_PER_WORD
;
10719 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10720 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10721 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10723 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10724 offset
-= UNITS_PER_WORD
;
10728 /* Save register REG to MEM. Make the instruction frame-related. */
10731 mips_save_reg (rtx reg
, rtx mem
)
10733 if (GET_MODE (reg
) == DFmode
10734 && (!TARGET_FLOAT64
10735 || mips_abi
== ABI_32
))
10739 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10741 x1
= mips_frame_set (mips_subword (mem
, false),
10742 mips_subword (reg
, false));
10743 x2
= mips_frame_set (mips_subword (mem
, true),
10744 mips_subword (reg
, true));
10745 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10748 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10751 /* Capture the register combinations that are allowed in a SWM or LWM
10752 instruction. The entries are ordered by number of registers set in
10753 the mask. We also ignore the single register encodings because a
10754 normal SW/LW is preferred. */
10756 static const unsigned int umips_swm_mask
[17] = {
10757 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10758 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10759 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10760 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10764 static const unsigned int umips_swm_encoding
[17] = {
10765 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10768 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10769 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10770 stack pointer of the topmost save slot.
10772 Remove from *MASK all registers that were handled using LWM and SWM.
10773 Update *OFFSET so that it points to the first unused save slot. */
10776 umips_build_save_restore (mips_save_restore_fn fn
,
10777 unsigned *mask
, HOST_WIDE_INT
*offset
)
10781 rtx pattern
, set
, reg
, mem
;
10782 HOST_WIDE_INT this_offset
;
10785 /* Try matching $16 to $31 (s0 to ra). */
10786 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
10787 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
10790 if (i
== ARRAY_SIZE (umips_swm_mask
))
10793 /* Get the offset of the lowest save slot. */
10794 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
10795 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
10797 /* LWM/SWM can only support offsets from -2048 to 2047. */
10798 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
10801 /* Create the final PARALLEL. */
10802 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
10803 this_base
= stack_pointer_rtx
;
10805 /* For registers $16-$23 and $30. */
10806 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
10808 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10809 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10810 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
10811 *mask
&= ~(1 << regno
);
10812 reg
= gen_rtx_REG (SImode
, regno
);
10813 if (fn
== mips_save_reg
)
10814 set
= mips_frame_set (mem
, reg
);
10817 set
= gen_rtx_SET (reg
, mem
);
10818 mips_add_cfa_restore (reg
);
10820 XVECEXP (pattern
, 0, j
) = set
;
10823 /* For register $31. */
10824 if (umips_swm_encoding
[i
] >> 4)
10826 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
10827 *mask
&= ~(1 << 31);
10828 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
10829 reg
= gen_rtx_REG (SImode
, 31);
10830 if (fn
== mips_save_reg
)
10831 set
= mips_frame_set (mem
, reg
);
10834 set
= gen_rtx_SET (reg
, mem
);
10835 mips_add_cfa_restore (reg
);
10837 XVECEXP (pattern
, 0, j
) = set
;
10840 pattern
= emit_insn (pattern
);
10841 if (fn
== mips_save_reg
)
10842 RTX_FRAME_RELATED_P (pattern
) = 1;
10844 /* Adjust the last offset. */
10845 *offset
-= UNITS_PER_WORD
* nregs
;
10850 /* Call FN for each register that is saved by the current function.
10851 SP_OFFSET is the offset of the current stack pointer from the start
10855 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10856 mips_save_restore_fn fn
)
10858 machine_mode fpr_mode
;
10860 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
10861 HOST_WIDE_INT offset
;
10864 /* Save registers starting from high to low. The debuggers prefer at least
10865 the return register be stored at func+4, and also it allows us not to
10866 need a nop in the epilogue if at least one register is reloaded in
10867 addition to return address. */
10868 offset
= frame
->gp_sp_offset
- sp_offset
;
10869 mask
= frame
->mask
;
10871 if (TARGET_MICROMIPS
)
10872 umips_build_save_restore (fn
, &mask
, &offset
);
10874 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10875 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10877 /* Record the ra offset for use by mips_function_profiler. */
10878 if (regno
== RETURN_ADDR_REGNUM
)
10879 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10880 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10881 offset
-= UNITS_PER_WORD
;
10884 /* This loop must iterate over the same space as its companion in
10885 mips_compute_frame_info. */
10886 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10887 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10888 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10889 regno
>= FP_REG_FIRST
;
10890 regno
-= MAX_FPRS_PER_FMT
)
10891 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10893 if (!TARGET_FLOAT64
&& TARGET_DOUBLE_FLOAT
10894 && (fixed_regs
[regno
] || fixed_regs
[regno
+ 1]))
10896 if (fixed_regs
[regno
])
10897 mips_save_restore_reg (SFmode
, regno
+ 1, offset
, fn
);
10899 mips_save_restore_reg (SFmode
, regno
, offset
, fn
);
10902 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10903 offset
-= GET_MODE_SIZE (fpr_mode
);
10907 /* Return true if a move between register REGNO and its save slot (MEM)
10908 can be done in a single move. LOAD_P is true if we are loading
10909 from the slot, false if we are storing to it. */
10912 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10914 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10915 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10918 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10919 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10922 /* Emit a move from SRC to DEST, given that one of them is a register
10923 save slot and that the other is a register. TEMP is a temporary
10924 GPR of the same mode that is available if need be. */
10927 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10929 unsigned int regno
;
10934 regno
= REGNO (src
);
10939 regno
= REGNO (dest
);
10943 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10945 /* We don't yet know whether we'll need this instruction or not.
10946 Postpone the decision by emitting a ghost move. This move
10947 is specifically not frame-related; only the split version is. */
10949 emit_insn (gen_move_gpdi (dest
, src
));
10951 emit_insn (gen_move_gpsi (dest
, src
));
10955 if (regno
== HI_REGNUM
)
10959 mips_emit_move (temp
, src
);
10961 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10962 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10964 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10965 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10970 emit_insn (gen_mfhidi_ti (temp
,
10971 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10973 emit_insn (gen_mfhisi_di (temp
,
10974 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10975 mips_emit_move (dest
, temp
);
10978 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10979 mips_emit_move (dest
, src
);
10982 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10983 mips_emit_move (temp
, src
);
10984 mips_emit_move (dest
, temp
);
10987 mips_set_frame_expr (mips_frame_set (dest
, src
));
10990 /* If we're generating n32 or n64 abicalls, and the current function
10991 does not use $28 as its global pointer, emit a cplocal directive.
10992 Use pic_offset_table_rtx as the argument to the directive. */
10995 mips_output_cplocal (void)
10997 if (!TARGET_EXPLICIT_RELOCS
10998 && mips_must_initialize_gp_p ()
10999 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
11000 output_asm_insn (".cplocal %+", 0);
11003 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
11006 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
11008 const char *fnname
;
11010 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
11011 floating-point arguments. */
11013 && TARGET_HARD_FLOAT_ABI
11014 && crtl
->args
.info
.fp_code
!= 0)
11015 mips16_build_function_stub ();
11017 /* Get the function name the same way that toplev.c does before calling
11018 assemble_start_function. This is needed so that the name used here
11019 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11020 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11021 mips_start_function_definition (fnname
, TARGET_MIPS16
);
11023 /* Output MIPS-specific frame information. */
11024 if (!flag_inhibit_size_directive
)
11026 const struct mips_frame_info
*frame
;
11028 frame
= &cfun
->machine
->frame
;
11030 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
11032 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
11033 "# vars= " HOST_WIDE_INT_PRINT_DEC
11035 ", args= " HOST_WIDE_INT_PRINT_DEC
11036 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
11037 reg_names
[frame_pointer_needed
11038 ? HARD_FRAME_POINTER_REGNUM
11039 : STACK_POINTER_REGNUM
],
11040 (frame_pointer_needed
11041 ? frame
->total_size
- frame
->hard_frame_pointer_offset
11042 : frame
->total_size
),
11043 reg_names
[RETURN_ADDR_REGNUM
],
11045 frame
->num_gp
, frame
->num_fp
,
11047 frame
->cprestore_size
);
11049 /* .mask MASK, OFFSET. */
11050 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11051 frame
->mask
, frame
->gp_save_offset
);
11053 /* .fmask MASK, OFFSET. */
11054 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11055 frame
->fmask
, frame
->fp_save_offset
);
11058 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
11059 Also emit the ".set noreorder; .set nomacro" sequence for functions
11061 if (mips_must_initialize_gp_p ()
11062 && mips_current_loadgp_style () == LOADGP_OLDABI
)
11066 /* This is a fixed-form sequence. The position of the
11067 first two instructions is important because of the
11068 way _gp_disp is defined. */
11069 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
11070 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
11071 output_asm_insn ("sll\t$2,16", 0);
11072 output_asm_insn ("addu\t$2,$3", 0);
11076 /* .cpload must be in a .set noreorder but not a
11077 .set nomacro block. */
11078 mips_push_asm_switch (&mips_noreorder
);
11079 output_asm_insn (".cpload\t%^", 0);
11080 if (!cfun
->machine
->all_noreorder_p
)
11081 mips_pop_asm_switch (&mips_noreorder
);
11083 mips_push_asm_switch (&mips_nomacro
);
11086 else if (cfun
->machine
->all_noreorder_p
)
11088 mips_push_asm_switch (&mips_noreorder
);
11089 mips_push_asm_switch (&mips_nomacro
);
11092 /* Tell the assembler which register we're using as the global
11093 pointer. This is needed for thunks, since they can use either
11094 explicit relocs or assembler macros. */
11095 mips_output_cplocal ();
11098 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
11101 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
11102 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
11104 const char *fnname
;
11106 /* Reinstate the normal $gp. */
11107 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
11108 mips_output_cplocal ();
11110 if (cfun
->machine
->all_noreorder_p
)
11112 mips_pop_asm_switch (&mips_nomacro
);
11113 mips_pop_asm_switch (&mips_noreorder
);
11116 /* Get the function name the same way that toplev.c does before calling
11117 assemble_start_function. This is needed so that the name used here
11118 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11119 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11120 mips_end_function_definition (fnname
);
11123 /* Emit an optimisation barrier for accesses to the current frame. */
11126 mips_frame_barrier (void)
11128 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
11132 /* The __gnu_local_gp symbol. */
11134 static GTY(()) rtx mips_gnu_local_gp
;
11136 /* If we're generating n32 or n64 abicalls, emit instructions
11137 to set up the global pointer. */
11140 mips_emit_loadgp (void)
11142 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
11144 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11145 switch (mips_current_loadgp_style ())
11147 case LOADGP_ABSOLUTE
:
11148 if (mips_gnu_local_gp
== NULL
)
11150 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
11151 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
11153 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
11154 (pic_reg
, mips_gnu_local_gp
)));
11157 case LOADGP_OLDABI
:
11158 /* Added by mips_output_function_prologue. */
11161 case LOADGP_NEWABI
:
11162 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
11163 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
11164 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11165 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
11166 (pic_reg
, offset
, incoming_address
)));
11170 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
11171 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
11172 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
11180 emit_insn (PMODE_INSN (gen_copygp_mips16
,
11181 (pic_offset_table_rtx
, pic_reg
)));
11183 /* Emit a blockage if there are implicit uses of the GP register.
11184 This includes profiled functions, because FUNCTION_PROFILE uses
11186 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
11187 emit_insn (gen_loadgp_blockage ());
11190 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11192 #if PROBE_INTERVAL > 32768
11193 #error Cannot use indexed addressing mode for stack probing
11196 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11197 inclusive. These are offsets from the current stack pointer. */
11200 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
11203 sorry ("-fstack-check=specific not implemented for MIPS16");
11205 /* See if we have a constant small number of probes to generate. If so,
11206 that's the easy case. */
11207 if (first
+ size
<= 32768)
11211 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11212 it exceeds SIZE. If only one probe is needed, this will not
11213 generate any code. Then probe at FIRST + SIZE. */
11214 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
11215 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11218 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11222 /* Otherwise, do the same as above, but in a loop. Note that we must be
11223 extra careful with variables wrapping around because we might be at
11224 the very top (or the very bottom) of the address space and we have
11225 to be able to handle this case properly; in particular, we use an
11226 equality test for the loop condition. */
11229 HOST_WIDE_INT rounded_size
;
11230 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
11231 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
11233 /* Sanity check for the addressing mode we're going to use. */
11234 gcc_assert (first
<= 32768);
11237 /* Step 1: round SIZE to the previous multiple of the interval. */
11239 rounded_size
= size
& -PROBE_INTERVAL
;
11242 /* Step 2: compute initial and final value of the loop counter. */
11244 /* TEST_ADDR = SP + FIRST. */
11245 emit_insn (gen_rtx_SET (r3
, plus_constant (Pmode
, stack_pointer_rtx
,
11248 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11249 if (rounded_size
> 32768)
11251 emit_move_insn (r12
, GEN_INT (rounded_size
));
11252 emit_insn (gen_rtx_SET (r12
, gen_rtx_MINUS (Pmode
, r3
, r12
)));
11255 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, r3
,
11259 /* Step 3: the loop
11261 while (TEST_ADDR != LAST_ADDR)
11263 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11267 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11268 until it is equal to ROUNDED_SIZE. */
11270 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
11273 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11274 that SIZE is equal to ROUNDED_SIZE. */
11276 if (size
!= rounded_size
)
11277 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
11280 /* Make sure nothing is scheduled before we are done. */
11281 emit_insn (gen_blockage ());
11284 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11285 absolute addresses. */
11288 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
11290 static int labelno
= 0;
11291 char loop_lab
[32], end_lab
[32], tmp
[64];
11294 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
11295 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
11297 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
11299 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11302 strcpy (tmp
, "%(%<beq\t%0,%1,");
11303 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
11305 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11306 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
11307 if (TARGET_64BIT
&& TARGET_LONG64
)
11308 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
11310 output_asm_insn ("addiu\t%0,%0,%1", xops
);
11312 /* Probe at TEST_ADDR and branch. */
11313 fprintf (asm_out_file
, "\tb\t");
11314 assemble_name_raw (asm_out_file
, loop_lab
);
11315 fputc ('\n', asm_out_file
);
11317 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
11319 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
11321 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
11326 /* Return true if X contains a kernel register. */
11329 mips_refers_to_kernel_reg_p (const_rtx x
)
11331 subrtx_iterator::array_type array
;
11332 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
11333 if (REG_P (*iter
) && KERNEL_REG_P (REGNO (*iter
)))
11338 /* Expand the "prologue" pattern. */
11341 mips_expand_prologue (void)
11343 const struct mips_frame_info
*frame
;
11344 HOST_WIDE_INT size
;
11345 unsigned int nargs
;
11347 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
11349 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11350 or implicitly. If so, we can commit to using a global pointer
11351 straight away, otherwise we need to defer the decision. */
11352 if (mips_cfun_has_inflexible_gp_ref_p ()
11353 || mips_cfun_has_flexible_gp_ref_p ())
11355 cfun
->machine
->must_initialize_gp_p
= true;
11356 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
11359 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11362 frame
= &cfun
->machine
->frame
;
11363 size
= frame
->total_size
;
11365 if (flag_stack_usage_info
)
11366 current_function_static_stack_size
= size
;
11368 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
11370 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
11372 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
11373 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
,
11374 size
- STACK_CHECK_PROTECT
);
11377 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
11380 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11381 bytes beforehand; this is enough to cover the register save area
11382 without going out of range. */
11383 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
11384 || frame
->num_cop0_regs
> 0)
11386 HOST_WIDE_INT step1
;
11388 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
11389 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11391 HOST_WIDE_INT offset
;
11392 unsigned int mask
, regno
;
11394 /* Try to merge argument stores into the save instruction. */
11395 nargs
= mips16e_collect_argument_saves ();
11397 /* Build the save instruction. */
11398 mask
= frame
->mask
;
11399 rtx insn
= mips16e_build_save_restore (false, &mask
, &offset
,
11401 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11402 mips_frame_barrier ();
11405 /* Check if we need to save other registers. */
11406 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11407 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11409 offset
-= UNITS_PER_WORD
;
11410 mips_save_restore_reg (word_mode
, regno
,
11411 offset
, mips_save_reg
);
11416 if (cfun
->machine
->interrupt_handler_p
)
11418 HOST_WIDE_INT offset
;
11421 /* If this interrupt is using a shadow register set, we need to
11422 get the stack pointer from the previous register set. */
11423 if (cfun
->machine
->use_shadow_register_set_p
)
11424 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
11425 stack_pointer_rtx
));
11427 if (!cfun
->machine
->keep_interrupts_masked_p
)
11429 /* Move from COP0 Cause to K0. */
11430 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
11431 gen_rtx_REG (SImode
,
11432 COP0_CAUSE_REG_NUM
)));
11433 /* Move from COP0 EPC to K1. */
11434 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11435 gen_rtx_REG (SImode
,
11436 COP0_EPC_REG_NUM
)));
11439 /* Allocate the first part of the frame. */
11440 rtx insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
11442 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11443 mips_frame_barrier ();
11446 /* Start at the uppermost location for saving. */
11447 offset
= frame
->cop0_sp_offset
- size
;
11448 if (!cfun
->machine
->keep_interrupts_masked_p
)
11450 /* Push EPC into its stack slot. */
11451 mem
= gen_frame_mem (word_mode
,
11452 plus_constant (Pmode
, stack_pointer_rtx
,
11454 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11455 offset
-= UNITS_PER_WORD
;
11458 /* Move from COP0 Status to K1. */
11459 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
11460 gen_rtx_REG (SImode
,
11461 COP0_STATUS_REG_NUM
)));
11463 /* Right justify the RIPL in k0. */
11464 if (!cfun
->machine
->keep_interrupts_masked_p
)
11465 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
11466 gen_rtx_REG (SImode
, K0_REG_NUM
),
11467 GEN_INT (CAUSE_IPL
)));
11469 /* Push Status into its stack slot. */
11470 mem
= gen_frame_mem (word_mode
,
11471 plus_constant (Pmode
, stack_pointer_rtx
,
11473 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
11474 offset
-= UNITS_PER_WORD
;
11476 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11477 if (!cfun
->machine
->keep_interrupts_masked_p
)
11478 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11481 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11483 if (!cfun
->machine
->keep_interrupts_masked_p
)
11484 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11485 IE is already the correct value, so we don't have to do
11486 anything explicit. */
11487 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11490 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11492 /* Disable interrupts by clearing the KSU, ERL, EXL,
11494 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
11497 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
11501 rtx insn
= gen_add3_insn (stack_pointer_rtx
,
11504 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11505 mips_frame_barrier ();
11508 mips_for_each_saved_acc (size
, mips_save_reg
);
11509 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
11513 /* Allocate the rest of the frame. */
11516 if (SMALL_OPERAND (-size
))
11517 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
11519 GEN_INT (-size
)))) = 1;
11522 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
11525 /* There are no instructions to add or subtract registers
11526 from the stack pointer, so use the frame pointer as a
11527 temporary. We should always be using a frame pointer
11528 in this case anyway. */
11529 gcc_assert (frame_pointer_needed
);
11530 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11531 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
11532 hard_frame_pointer_rtx
,
11533 MIPS_PROLOGUE_TEMP (Pmode
)));
11534 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
11537 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
11539 MIPS_PROLOGUE_TEMP (Pmode
)));
11541 /* Describe the combined effect of the previous instructions. */
11542 mips_set_frame_expr
11543 (gen_rtx_SET (stack_pointer_rtx
,
11544 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
11546 mips_frame_barrier ();
11549 /* Set up the frame pointer, if we're using one. */
11550 if (frame_pointer_needed
)
11552 HOST_WIDE_INT offset
;
11554 offset
= frame
->hard_frame_pointer_offset
;
11557 rtx insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11558 RTX_FRAME_RELATED_P (insn
) = 1;
11560 else if (SMALL_OPERAND (offset
))
11562 rtx insn
= gen_add3_insn (hard_frame_pointer_rtx
,
11563 stack_pointer_rtx
, GEN_INT (offset
));
11564 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
11568 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
11569 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
11570 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
11571 hard_frame_pointer_rtx
,
11572 MIPS_PROLOGUE_TEMP (Pmode
)));
11573 mips_set_frame_expr
11574 (gen_rtx_SET (hard_frame_pointer_rtx
,
11575 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
11579 mips_emit_loadgp ();
11581 /* Initialize the $gp save slot. */
11582 if (mips_cfun_has_cprestore_slot_p ())
11584 rtx base
, mem
, gp
, temp
;
11585 HOST_WIDE_INT offset
;
11587 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11588 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11589 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11590 temp
= (SMALL_OPERAND (offset
)
11591 ? gen_rtx_SCRATCH (Pmode
)
11592 : MIPS_PROLOGUE_TEMP (Pmode
));
11593 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11594 (mem
, GEN_INT (offset
), gp
, temp
)));
11596 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11597 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11598 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11601 /* We need to search back to the last use of K0 or K1. */
11602 if (cfun
->machine
->interrupt_handler_p
)
11605 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11607 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
11609 /* Emit a move from K1 to COP0 Status after insn. */
11610 gcc_assert (insn
!= NULL_RTX
);
11611 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11612 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11616 /* If we are profiling, make sure no instructions are scheduled before
11617 the call to mcount. */
11619 emit_insn (gen_blockage ());
11622 /* Attach all pending register saves to the previous instruction.
11623 Return that instruction. */
11626 mips_epilogue_emit_cfa_restores (void)
11630 insn
= get_last_insn ();
11631 gcc_assert (insn
&& !REG_NOTES (insn
));
11632 if (mips_epilogue
.cfa_restores
)
11634 RTX_FRAME_RELATED_P (insn
) = 1;
11635 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11636 mips_epilogue
.cfa_restores
= 0;
11641 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11642 now at REG + OFFSET. */
11645 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11649 insn
= mips_epilogue_emit_cfa_restores ();
11650 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11652 RTX_FRAME_RELATED_P (insn
) = 1;
11653 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11654 plus_constant (Pmode
, reg
, offset
),
11656 mips_epilogue
.cfa_reg
= reg
;
11657 mips_epilogue
.cfa_offset
= offset
;
11661 /* Emit instructions to restore register REG from slot MEM. Also update
11662 the cfa_restores list. */
11665 mips_restore_reg (rtx reg
, rtx mem
)
11667 /* There's no MIPS16 instruction to load $31 directly. Load into
11668 $7 instead and adjust the return insn appropriately. */
11669 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11670 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11671 else if (GET_MODE (reg
) == DFmode
11672 && (!TARGET_FLOAT64
11673 || mips_abi
== ABI_32
))
11675 mips_add_cfa_restore (mips_subword (reg
, true));
11676 mips_add_cfa_restore (mips_subword (reg
, false));
11679 mips_add_cfa_restore (reg
);
11681 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11682 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11683 /* The CFA is currently defined in terms of the register whose
11684 value we have just restored. Redefine the CFA in terms of
11685 the stack pointer. */
11686 mips_epilogue_set_cfa (stack_pointer_rtx
,
11687 mips_epilogue
.cfa_restore_sp_offset
);
11690 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11691 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11692 BASE, if not the stack pointer, is available as a temporary. */
11695 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11697 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11700 mips_frame_barrier ();
11701 if (offset
== const0_rtx
)
11703 emit_move_insn (stack_pointer_rtx
, base
);
11704 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11706 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11708 emit_insn (gen_add3_insn (base
, base
, offset
));
11709 mips_epilogue_set_cfa (base
, new_frame_size
);
11710 emit_move_insn (stack_pointer_rtx
, base
);
11714 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11715 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11719 /* Emit any instructions needed before a return. */
11722 mips_expand_before_return (void)
11724 /* When using a call-clobbered gp, we start out with unified call
11725 insns that include instructions to restore the gp. We then split
11726 these unified calls after reload. These split calls explicitly
11727 clobber gp, so there is no need to define
11728 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11730 For consistency, we should also insert an explicit clobber of $28
11731 before return insns, so that the post-reload optimizers know that
11732 the register is not live on exit. */
11733 if (TARGET_CALL_CLOBBERED_GP
)
11734 emit_clobber (pic_offset_table_rtx
);
11737 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11741 mips_expand_epilogue (bool sibcall_p
)
11743 const struct mips_frame_info
*frame
;
11744 HOST_WIDE_INT step1
, step2
;
11747 bool use_jraddiusp_p
= false;
11749 if (!sibcall_p
&& mips_can_use_return_insn ())
11751 emit_jump_insn (gen_return ());
11755 /* In MIPS16 mode, if the return value should go into a floating-point
11756 register, we need to call a helper routine to copy it over. */
11757 if (mips16_cfun_returns_in_fpr_p ())
11758 mips16_copy_fpr_return_value ();
11760 /* Split the frame into two. STEP1 is the amount of stack we should
11761 deallocate before restoring the registers. STEP2 is the amount we
11762 should deallocate afterwards.
11764 Start off by assuming that no registers need to be restored. */
11765 frame
= &cfun
->machine
->frame
;
11766 step1
= frame
->total_size
;
11769 /* Work out which register holds the frame address. */
11770 if (!frame_pointer_needed
)
11771 base
= stack_pointer_rtx
;
11774 base
= hard_frame_pointer_rtx
;
11775 step1
-= frame
->hard_frame_pointer_offset
;
11777 mips_epilogue
.cfa_reg
= base
;
11778 mips_epilogue
.cfa_offset
= step1
;
11779 mips_epilogue
.cfa_restores
= NULL_RTX
;
11781 /* If we need to restore registers, deallocate as much stack as
11782 possible in the second step without going out of range. */
11783 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11784 || frame
->num_cop0_regs
> 0)
11786 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11790 /* Get an rtx for STEP1 that we can add to BASE. */
11791 adjust
= GEN_INT (step1
);
11792 if (!SMALL_OPERAND (step1
))
11794 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11795 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11797 mips_deallocate_stack (base
, adjust
, step2
);
11799 /* If we're using addressing macros, $gp is implicitly used by all
11800 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11802 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11803 emit_insn (gen_blockage ());
11805 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11806 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11808 unsigned int regno
, mask
;
11809 HOST_WIDE_INT offset
;
11812 /* Generate the restore instruction. */
11813 mask
= frame
->mask
;
11814 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11816 /* Restore any other registers manually. */
11817 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11818 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11820 offset
-= UNITS_PER_WORD
;
11821 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11824 /* Restore the remaining registers and deallocate the final bit
11826 mips_frame_barrier ();
11827 emit_insn (restore
);
11828 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11832 /* Restore the registers. */
11833 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11834 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11837 if (cfun
->machine
->interrupt_handler_p
)
11839 HOST_WIDE_INT offset
;
11842 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11843 if (!cfun
->machine
->keep_interrupts_masked_p
)
11845 /* Restore the original EPC. */
11846 mem
= gen_frame_mem (word_mode
,
11847 plus_constant (Pmode
, stack_pointer_rtx
,
11849 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11850 offset
-= UNITS_PER_WORD
;
11852 /* Move to COP0 EPC. */
11853 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11854 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11857 /* Restore the original Status. */
11858 mem
= gen_frame_mem (word_mode
,
11859 plus_constant (Pmode
, stack_pointer_rtx
,
11861 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11862 offset
-= UNITS_PER_WORD
;
11864 /* If we don't use shadow register set, we need to update SP. */
11865 if (!cfun
->machine
->use_shadow_register_set_p
)
11866 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11868 /* The choice of position is somewhat arbitrary in this case. */
11869 mips_epilogue_emit_cfa_restores ();
11871 /* Move to COP0 Status. */
11872 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11873 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11875 else if (TARGET_MICROMIPS
11876 && !crtl
->calls_eh_return
11879 && mips_unsigned_immediate_p (step2
, 5, 2))
11880 use_jraddiusp_p
= true;
11882 /* Deallocate the final bit of the frame. */
11883 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11886 if (!use_jraddiusp_p
)
11887 gcc_assert (!mips_epilogue
.cfa_restores
);
11889 /* Add in the __builtin_eh_return stack adjustment. We need to
11890 use a temporary in MIPS16 code. */
11891 if (crtl
->calls_eh_return
)
11895 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11896 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11897 MIPS_EPILOGUE_TEMP (Pmode
),
11898 EH_RETURN_STACKADJ_RTX
));
11899 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11902 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11904 EH_RETURN_STACKADJ_RTX
));
11909 mips_expand_before_return ();
11910 if (cfun
->machine
->interrupt_handler_p
)
11912 /* Interrupt handlers generate eret or deret. */
11913 if (cfun
->machine
->use_debug_exception_return_p
)
11914 emit_jump_insn (gen_mips_deret ());
11916 emit_jump_insn (gen_mips_eret ());
11922 /* When generating MIPS16 code, the normal
11923 mips_for_each_saved_gpr_and_fpr path will restore the return
11924 address into $7 rather than $31. */
11926 && !GENERATE_MIPS16E_SAVE_RESTORE
11927 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11929 /* simple_returns cannot rely on values that are only available
11930 on paths through the epilogue (because return paths that do
11931 not pass through the epilogue may nevertheless reuse a
11932 simple_return that occurs at the end of the epilogue).
11933 Use a normal return here instead. */
11934 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11935 pat
= gen_return_internal (reg
);
11937 else if (use_jraddiusp_p
)
11938 pat
= gen_jraddiusp (GEN_INT (step2
));
11941 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11942 pat
= gen_simple_return_internal (reg
);
11944 emit_jump_insn (pat
);
11945 if (use_jraddiusp_p
)
11946 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
11950 /* Search from the beginning to the first use of K0 or K1. */
11951 if (cfun
->machine
->interrupt_handler_p
11952 && !cfun
->machine
->keep_interrupts_masked_p
)
11954 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11956 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
11958 gcc_assert (insn
!= NULL_RTX
);
11959 /* Insert disable interrupts before the first use of K0 or K1. */
11960 emit_insn_before (gen_mips_di (), insn
);
11961 emit_insn_before (gen_mips_ehb (), insn
);
11965 /* Return nonzero if this function is known to have a null epilogue.
11966 This allows the optimizer to omit jumps to jumps if no stack
11970 mips_can_use_return_insn (void)
11972 /* Interrupt handlers need to go through the epilogue. */
11973 if (cfun
->machine
->interrupt_handler_p
)
11976 if (!reload_completed
)
11982 /* In MIPS16 mode, a function that returns a floating-point value
11983 needs to arrange to copy the return value into the floating-point
11985 if (mips16_cfun_returns_in_fpr_p ())
11988 return cfun
->machine
->frame
.total_size
== 0;
11991 /* Return true if register REGNO can store a value of mode MODE.
11992 The result of this function is cached in mips_hard_regno_mode_ok. */
11995 mips_hard_regno_mode_ok_p (unsigned int regno
, machine_mode mode
)
11998 enum mode_class mclass
;
12000 if (mode
== CCV2mode
)
12001 return (ISA_HAS_8CC
12002 && ST_REG_P (regno
)
12003 && (regno
- ST_REG_FIRST
) % 2 == 0);
12005 if (mode
== CCV4mode
)
12006 return (ISA_HAS_8CC
12007 && ST_REG_P (regno
)
12008 && (regno
- ST_REG_FIRST
) % 4 == 0);
12010 if (mode
== CCmode
)
12011 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
12013 size
= GET_MODE_SIZE (mode
);
12014 mclass
= GET_MODE_CLASS (mode
);
12016 if (GP_REG_P (regno
) && mode
!= CCFmode
)
12017 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
12019 if (FP_REG_P (regno
)
12020 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
12021 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
12023 /* Deny use of odd-numbered registers for 32-bit data for
12024 the o32 FP64A ABI. */
12025 if (TARGET_O32_FP64A_ABI
&& size
<= 4 && (regno
& 1) != 0)
12028 /* The FPXX ABI requires double-precision values to be placed in
12029 even-numbered registers. Disallow odd-numbered registers with
12030 CCFmode because CCFmode double-precision compares will write a
12031 64-bit value to a register. */
12032 if (mode
== CCFmode
)
12033 return !(TARGET_FLOATXX
&& (regno
& 1) != 0);
12035 /* Allow 64-bit vector modes for Loongson-2E/2F. */
12036 if (TARGET_LOONGSON_VECTORS
12037 && (mode
== V2SImode
12038 || mode
== V4HImode
12039 || mode
== V8QImode
12040 || mode
== DImode
))
12043 if (mclass
== MODE_FLOAT
12044 || mclass
== MODE_COMPLEX_FLOAT
12045 || mclass
== MODE_VECTOR_FLOAT
)
12046 return size
<= UNITS_PER_FPVALUE
;
12048 /* Allow integer modes that fit into a single register. We need
12049 to put integers into FPRs when using instructions like CVT
12050 and TRUNC. There's no point allowing sizes smaller than a word,
12051 because the FPU has no appropriate load/store instructions. */
12052 if (mclass
== MODE_INT
)
12053 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
12056 /* Don't allow vector modes in accumulators. */
12057 if (ACC_REG_P (regno
)
12058 && !VECTOR_MODE_P (mode
)
12059 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
12061 if (MD_REG_P (regno
))
12063 /* After a multiplication or division, clobbering HI makes
12064 the value of LO unpredictable, and vice versa. This means
12065 that, for all interesting cases, HI and LO are effectively
12068 We model this by requiring that any value that uses HI
12070 if (size
<= UNITS_PER_WORD
* 2)
12071 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
12075 /* DSP accumulators do not have the same restrictions as
12076 HI and LO, so we can treat them as normal doubleword
12078 if (size
<= UNITS_PER_WORD
)
12081 if (size
<= UNITS_PER_WORD
* 2
12082 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
12087 if (ALL_COP_REG_P (regno
))
12088 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
12090 if (regno
== GOT_VERSION_REGNUM
)
12091 return mode
== SImode
;
12096 /* Implement HARD_REGNO_NREGS. */
12099 mips_hard_regno_nregs (int regno
, machine_mode mode
)
12101 if (ST_REG_P (regno
))
12102 /* The size of FP status registers is always 4, because they only hold
12103 CCmode values, and CCmode is always considered to be 4 bytes wide. */
12104 return (GET_MODE_SIZE (mode
) + 3) / 4;
12106 if (FP_REG_P (regno
))
12107 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
12109 /* All other registers are word-sized. */
12110 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
12113 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
12114 in mips_hard_regno_nregs. */
12117 mips_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
12123 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
12124 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
12126 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
12127 size
= MIN (size
, 4);
12128 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
12130 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
12132 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
12133 size
= MIN (size
, UNITS_PER_FPREG
);
12134 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
12136 if (!hard_reg_set_empty_p (left
))
12137 size
= MIN (size
, UNITS_PER_WORD
);
12138 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
12141 /* Implement CANNOT_CHANGE_MODE_CLASS. */
12144 mips_cannot_change_mode_class (machine_mode from
,
12146 enum reg_class rclass
)
12148 /* Allow conversions between different Loongson integer vectors,
12149 and between those vectors and DImode. */
12150 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
12151 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
12154 /* Otherwise, there are several problems with changing the modes of
12155 values in floating-point registers:
12157 - When a multi-word value is stored in paired floating-point
12158 registers, the first register always holds the low word. We
12159 therefore can't allow FPRs to change between single-word and
12160 multi-word modes on big-endian targets.
12162 - GCC assumes that each word of a multiword register can be
12163 accessed individually using SUBREGs. This is not true for
12164 floating-point registers if they are bigger than a word.
12166 - Loading a 32-bit value into a 64-bit floating-point register
12167 will not sign-extend the value, despite what LOAD_EXTEND_OP
12168 says. We can't allow FPRs to change from SImode to a wider
12169 mode on 64-bit targets.
12171 - If the FPU has already interpreted a value in one format, we
12172 must not ask it to treat the value as having a different
12175 We therefore disallow all mode changes involving FPRs. */
12177 return reg_classes_intersect_p (FP_REGS
, rclass
);
12180 /* Implement target hook small_register_classes_for_mode_p. */
12183 mips_small_register_classes_for_mode_p (machine_mode mode
12186 return TARGET_MIPS16
;
12189 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
12192 mips_mode_ok_for_mov_fmt_p (machine_mode mode
)
12198 return TARGET_HARD_FLOAT
;
12201 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
12204 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
12211 /* Implement MODES_TIEABLE_P. */
12214 mips_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
12216 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
12217 prefer to put one of them in FPRs. */
12218 return (mode1
== mode2
12219 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
12220 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
12223 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
12226 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
12228 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
12231 if (reg_class_subset_p (FP_REGS
, rclass
)
12232 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
12235 if (reg_class_subset_p (GR_REGS
, rclass
))
12238 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
12244 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
12245 Return a "canonical" class to represent it in later calculations. */
12248 mips_canonicalize_move_class (reg_class_t rclass
)
12250 /* All moves involving accumulator registers have the same cost. */
12251 if (reg_class_subset_p (rclass
, ACC_REGS
))
12254 /* Likewise promote subclasses of general registers to the most
12255 interesting containing class. */
12256 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
12258 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
12259 rclass
= GENERAL_REGS
;
12264 /* Return the cost of moving a value from a register of class FROM to a GPR.
12265 Return 0 for classes that are unions of other classes handled by this
12269 mips_move_to_gpr_cost (reg_class_t from
)
12275 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12279 /* MFLO and MFHI. */
12289 /* This choice of value is historical. */
12297 /* Return the cost of moving a value from a GPR to a register of class TO.
12298 Return 0 for classes that are unions of other classes handled by this
12302 mips_move_from_gpr_cost (reg_class_t to
)
12308 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12312 /* MTLO and MTHI. */
12322 /* This choice of value is historical. */
12330 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12331 maximum of the move costs for subclasses; regclass will work out
12332 the maximum for us. */
12335 mips_register_move_cost (machine_mode mode
,
12336 reg_class_t from
, reg_class_t to
)
12341 from
= mips_canonicalize_move_class (from
);
12342 to
= mips_canonicalize_move_class (to
);
12344 /* Handle moves that can be done without using general-purpose registers. */
12345 if (from
== FP_REGS
)
12347 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
12352 /* Handle cases in which only one class deviates from the ideal. */
12353 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
12355 return mips_move_from_gpr_cost (to
);
12357 return mips_move_to_gpr_cost (from
);
12359 /* Handles cases that require a GPR temporary. */
12360 cost1
= mips_move_to_gpr_cost (from
);
12363 cost2
= mips_move_from_gpr_cost (to
);
12365 return cost1
+ cost2
;
12371 /* Implement TARGET_REGISTER_PRIORITY. */
12374 mips_register_priority (int hard_regno
)
12376 /* Treat MIPS16 registers with higher priority than other regs. */
12378 && TEST_HARD_REG_BIT (reg_class_contents
[M16_REGS
], hard_regno
))
12383 /* Implement TARGET_MEMORY_MOVE_COST. */
12386 mips_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
12388 return (mips_cost
->memory_latency
12389 + memory_move_secondary_cost (mode
, rclass
, in
));
12392 /* Implement SECONDARY_MEMORY_NEEDED. */
12395 mips_secondary_memory_needed (enum reg_class class1
, enum reg_class class2
,
12398 /* Ignore spilled pseudos. */
12399 if (lra_in_progress
&& (class1
== NO_REGS
|| class2
== NO_REGS
))
12402 if (((class1
== FP_REGS
) != (class2
== FP_REGS
))
12403 && ((TARGET_FLOATXX
&& !ISA_HAS_MXHC1
)
12404 || TARGET_O32_FP64A_ABI
)
12405 && GET_MODE_SIZE (mode
) >= 8)
12411 /* Return the register class required for a secondary register when
12412 copying between one of the registers in RCLASS and value X, which
12413 has mode MODE. X is the source of the move if IN_P, otherwise it
12414 is the destination. Return NO_REGS if no secondary register is
12418 mips_secondary_reload_class (enum reg_class rclass
,
12419 machine_mode mode
, rtx x
, bool)
12423 /* If X is a constant that cannot be loaded into $25, it must be loaded
12424 into some other GPR. No other register class allows a direct move. */
12425 if (mips_dangerous_for_la25_p (x
))
12426 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
12428 regno
= true_regnum (x
);
12431 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12432 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
12438 /* Copying from accumulator registers to anywhere other than a general
12439 register requires a temporary general register. */
12440 if (reg_class_subset_p (rclass
, ACC_REGS
))
12441 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
12442 if (ACC_REG_P (regno
))
12443 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12445 if (reg_class_subset_p (rclass
, FP_REGS
))
12449 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)))
12450 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12451 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12454 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
12455 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12458 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
12459 /* We can force the constant to memory and use lwc1
12460 and ldc1. As above, we will use pairs of lwc1s if
12461 ldc1 is not supported. */
12464 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
12465 /* In this case we can use mov.fmt. */
12468 /* Otherwise, we need to reload through an integer register. */
12471 if (FP_REG_P (regno
))
12472 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
12477 /* Implement TARGET_MODE_REP_EXTENDED. */
12480 mips_mode_rep_extended (machine_mode mode
, machine_mode mode_rep
)
12482 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12483 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
12484 return SIGN_EXTEND
;
12489 /* Implement TARGET_VALID_POINTER_MODE. */
12492 mips_valid_pointer_mode (machine_mode mode
)
12494 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
12497 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12500 mips_vector_mode_supported_p (machine_mode mode
)
12505 return TARGET_PAIRED_SINGLE_FLOAT
;
12520 return TARGET_LOONGSON_VECTORS
;
12527 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12530 mips_scalar_mode_supported_p (machine_mode mode
)
12532 if (ALL_FIXED_POINT_MODE_P (mode
)
12533 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
12536 return default_scalar_mode_supported_p (mode
);
12539 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12541 static machine_mode
12542 mips_preferred_simd_mode (machine_mode mode ATTRIBUTE_UNUSED
)
12544 if (TARGET_PAIRED_SINGLE_FLOAT
12550 /* Implement TARGET_INIT_LIBFUNCS. */
12553 mips_init_libfuncs (void)
12555 if (TARGET_FIX_VR4120
)
12557 /* Register the special divsi3 and modsi3 functions needed to work
12558 around VR4120 division errata. */
12559 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
12560 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
12563 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
12565 /* Register the MIPS16 -mhard-float stubs. */
12566 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
12567 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
12568 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
12569 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
12571 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
12572 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
12573 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
12574 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
12575 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
12576 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
12577 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
12579 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
12580 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
12581 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
12583 if (TARGET_DOUBLE_FLOAT
)
12585 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
12586 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
12587 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
12588 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
12590 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
12591 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
12592 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
12593 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
12594 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
12595 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
12596 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
12598 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
12599 "__mips16_extendsfdf2");
12600 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
12601 "__mips16_truncdfsf2");
12602 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
12603 "__mips16_fix_truncdfsi");
12604 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
12605 "__mips16_floatsidf");
12606 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
12607 "__mips16_floatunsidf");
12611 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12612 on an external non-MIPS16 routine to implement __sync_synchronize.
12613 Similarly for the rest of the ll/sc libfuncs. */
12616 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
12617 init_sync_libfuncs (UNITS_PER_WORD
);
12621 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12624 mips_process_load_label (rtx target
)
12626 rtx base
, gp
, intop
;
12627 HOST_WIDE_INT offset
;
12629 mips_multi_start ();
12633 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12634 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12638 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12639 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12643 gp
= pic_offset_table_rtx
;
12644 if (mips_cfun_has_cprestore_slot_p ())
12646 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12647 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12648 if (!SMALL_OPERAND (offset
))
12650 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12651 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12652 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12655 offset
= CONST_LOW_PART (offset
);
12657 intop
= GEN_INT (offset
);
12658 if (ISA_HAS_LOAD_DELAY
)
12659 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12661 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12663 if (ISA_HAS_LOAD_DELAY
)
12664 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12666 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12667 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12672 /* Return the number of instructions needed to load a label into $AT. */
12674 static unsigned int
12675 mips_load_label_num_insns (void)
12677 if (cfun
->machine
->load_label_num_insns
== 0)
12679 mips_process_load_label (pc_rtx
);
12680 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12682 return cfun
->machine
->load_label_num_insns
;
12685 /* Emit an asm sequence to start a noat block and load the address
12686 of a label into $1. */
12689 mips_output_load_label (rtx target
)
12691 mips_push_asm_switch (&mips_noat
);
12692 if (TARGET_EXPLICIT_RELOCS
)
12694 mips_process_load_label (target
);
12695 mips_multi_write ();
12699 if (Pmode
== DImode
)
12700 output_asm_insn ("dla\t%@,%0", &target
);
12702 output_asm_insn ("la\t%@,%0", &target
);
12706 /* Return the length of INSN. LENGTH is the initial length computed by
12707 attributes in the machine-description file. */
12710 mips_adjust_insn_length (rtx_insn
*insn
, int length
)
12712 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12713 of a PIC long-branch sequence. Substitute the correct value. */
12714 if (length
== MAX_PIC_BRANCH_LENGTH
12716 && INSN_CODE (insn
) >= 0
12717 && get_attr_type (insn
) == TYPE_BRANCH
)
12719 /* Add the branch-over instruction and its delay slot, if this
12720 is a conditional branch. */
12721 length
= simplejump_p (insn
) ? 0 : 8;
12723 /* Add the size of a load into $AT. */
12724 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
12726 /* Add the length of an indirect jump, ignoring the delay slot. */
12727 length
+= TARGET_COMPRESSION
? 2 : 4;
12730 /* A unconditional jump has an unfilled delay slot if it is not part
12731 of a sequence. A conditional jump normally has a delay slot, but
12732 does not on MIPS16. */
12733 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12734 length
+= TARGET_MIPS16
? 2 : 4;
12736 /* See how many nops might be needed to avoid hardware hazards. */
12737 if (!cfun
->machine
->ignore_hazard_length_p
12739 && INSN_CODE (insn
) >= 0)
12740 switch (get_attr_hazard (insn
))
12746 length
+= NOP_INSN_LENGTH
;
12750 length
+= NOP_INSN_LENGTH
* 2;
12757 /* Return the assembly code for INSN, which has the operands given by
12758 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12759 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12760 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12761 version of BRANCH_IF_TRUE. */
12764 mips_output_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
12765 const char *branch_if_true
,
12766 const char *branch_if_false
)
12768 unsigned int length
;
12771 gcc_assert (LABEL_P (operands
[0]));
12773 length
= get_attr_length (insn
);
12776 /* Just a simple conditional branch. */
12777 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12778 return branch_if_true
;
12781 /* Generate a reversed branch around a direct jump. This fallback does
12782 not use branch-likely instructions. */
12783 mips_branch_likely
= false;
12784 rtx_code_label
*not_taken
= gen_label_rtx ();
12785 taken
= operands
[0];
12787 /* Generate the reversed branch to NOT_TAKEN. */
12788 operands
[0] = not_taken
;
12789 output_asm_insn (branch_if_false
, operands
);
12791 /* If INSN has a delay slot, we must provide delay slots for both the
12792 branch to NOT_TAKEN and the conditional jump. We must also ensure
12793 that INSN's delay slot is executed in the appropriate cases. */
12794 if (final_sequence
)
12796 /* This first delay slot will always be executed, so use INSN's
12797 delay slot if is not annulled. */
12798 if (!INSN_ANNULLED_BRANCH_P (insn
))
12800 final_scan_insn (final_sequence
->insn (1),
12801 asm_out_file
, optimize
, 1, NULL
);
12802 final_sequence
->insn (1)->set_deleted ();
12805 output_asm_insn ("nop", 0);
12806 fprintf (asm_out_file
, "\n");
12809 /* Output the unconditional branch to TAKEN. */
12810 if (TARGET_ABSOLUTE_JUMPS
)
12811 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12814 mips_output_load_label (taken
);
12815 output_asm_insn ("jr\t%@%]%/", 0);
12818 /* Now deal with its delay slot; see above. */
12819 if (final_sequence
)
12821 /* This delay slot will only be executed if the branch is taken.
12822 Use INSN's delay slot if is annulled. */
12823 if (INSN_ANNULLED_BRANCH_P (insn
))
12825 final_scan_insn (final_sequence
->insn (1),
12826 asm_out_file
, optimize
, 1, NULL
);
12827 final_sequence
->insn (1)->set_deleted ();
12830 output_asm_insn ("nop", 0);
12831 fprintf (asm_out_file
, "\n");
12834 /* Output NOT_TAKEN. */
12835 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12836 CODE_LABEL_NUMBER (not_taken
));
12840 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12841 if some ordering condition is true. The condition is given by
12842 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12843 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12844 its second is always zero. */
12847 mips_output_order_conditional_branch (rtx_insn
*insn
, rtx
*operands
, bool inverted_p
)
12849 const char *branch
[2];
12851 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12852 Make BRANCH[0] branch on the inverse condition. */
12853 switch (GET_CODE (operands
[1]))
12855 /* These cases are equivalent to comparisons against zero. */
12857 inverted_p
= !inverted_p
;
12858 /* Fall through. */
12860 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12861 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12864 /* These cases are always true or always false. */
12866 inverted_p
= !inverted_p
;
12867 /* Fall through. */
12869 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12870 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12874 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12875 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12878 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12881 /* Start a block of code that needs access to the LL, SC and SYNC
12885 mips_start_ll_sc_sync_block (void)
12887 if (!ISA_HAS_LL_SC
)
12889 output_asm_insn (".set\tpush", 0);
12891 output_asm_insn (".set\tmips3", 0);
12893 output_asm_insn (".set\tmips2", 0);
12897 /* End a block started by mips_start_ll_sc_sync_block. */
12900 mips_end_ll_sc_sync_block (void)
12902 if (!ISA_HAS_LL_SC
)
12903 output_asm_insn (".set\tpop", 0);
12906 /* Output and/or return the asm template for a sync instruction. */
12909 mips_output_sync (void)
12911 mips_start_ll_sc_sync_block ();
12912 output_asm_insn ("sync", 0);
12913 mips_end_ll_sc_sync_block ();
12917 /* Return the asm template associated with sync_insn1 value TYPE.
12918 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12920 static const char *
12921 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12925 case SYNC_INSN1_MOVE
:
12926 return "move\t%0,%z2";
12927 case SYNC_INSN1_LI
:
12928 return "li\t%0,%2";
12929 case SYNC_INSN1_ADDU
:
12930 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12931 case SYNC_INSN1_ADDIU
:
12932 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12933 case SYNC_INSN1_SUBU
:
12934 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12935 case SYNC_INSN1_AND
:
12936 return "and\t%0,%1,%z2";
12937 case SYNC_INSN1_ANDI
:
12938 return "andi\t%0,%1,%2";
12939 case SYNC_INSN1_OR
:
12940 return "or\t%0,%1,%z2";
12941 case SYNC_INSN1_ORI
:
12942 return "ori\t%0,%1,%2";
12943 case SYNC_INSN1_XOR
:
12944 return "xor\t%0,%1,%z2";
12945 case SYNC_INSN1_XORI
:
12946 return "xori\t%0,%1,%2";
12948 gcc_unreachable ();
12951 /* Return the asm template associated with sync_insn2 value TYPE. */
12953 static const char *
12954 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12958 case SYNC_INSN2_NOP
:
12959 gcc_unreachable ();
12960 case SYNC_INSN2_AND
:
12961 return "and\t%0,%1,%z2";
12962 case SYNC_INSN2_XOR
:
12963 return "xor\t%0,%1,%z2";
12964 case SYNC_INSN2_NOT
:
12965 return "nor\t%0,%1,%.";
12967 gcc_unreachable ();
12970 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12971 the value of the one of the sync_* attributes. Return the operand
12972 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12973 have the associated attribute. */
12976 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12979 default_value
= operands
[index
- 1];
12980 return default_value
;
12983 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12984 sequence for it. */
12987 mips_process_sync_loop (rtx_insn
*insn
, rtx
*operands
)
12989 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12990 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12991 unsigned int tmp3_insn
;
12992 enum attr_sync_insn1 insn1
;
12993 enum attr_sync_insn2 insn2
;
12996 enum memmodel model
;
12998 /* Read an operand from the sync_WHAT attribute and store it in
12999 variable WHAT. DEFAULT is the default value if no attribute
13001 #define READ_OPERAND(WHAT, DEFAULT) \
13002 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
13005 /* Read the memory. */
13006 READ_OPERAND (mem
, 0);
13008 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
13010 /* Read the other attributes. */
13011 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
13012 READ_OPERAND (oldval
, at
);
13013 READ_OPERAND (cmp
, 0);
13014 READ_OPERAND (newval
, at
);
13015 READ_OPERAND (inclusive_mask
, 0);
13016 READ_OPERAND (exclusive_mask
, 0);
13017 READ_OPERAND (required_oldval
, 0);
13018 READ_OPERAND (insn1_op2
, 0);
13019 insn1
= get_attr_sync_insn1 (insn
);
13020 insn2
= get_attr_sync_insn2 (insn
);
13022 /* Don't bother setting CMP result that is never used. */
13023 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
13026 memmodel_attr
= get_attr_sync_memmodel (insn
);
13027 switch (memmodel_attr
)
13030 model
= MEMMODEL_ACQ_REL
;
13033 model
= MEMMODEL_ACQUIRE
;
13036 model
= memmodel_from_int (INTVAL (operands
[memmodel_attr
]));
13039 mips_multi_start ();
13041 /* Output the release side of the memory barrier. */
13042 if (need_atomic_barrier_p (model
, true))
13044 if (required_oldval
== 0 && TARGET_OCTEON
)
13046 /* Octeon doesn't reorder reads, so a full barrier can be
13047 created by using SYNCW to order writes combined with the
13048 write from the following SC. When the SC successfully
13049 completes, we know that all preceding writes are also
13050 committed to the coherent memory system. It is possible
13051 for a single SYNCW to fail, but a pair of them will never
13052 fail, so we use two. */
13053 mips_multi_add_insn ("syncw", NULL
);
13054 mips_multi_add_insn ("syncw", NULL
);
13057 mips_multi_add_insn ("sync", NULL
);
13060 /* Output the branch-back label. */
13061 mips_multi_add_label ("1:");
13063 /* OLDVAL = *MEM. */
13064 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
13065 oldval
, mem
, NULL
);
13067 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
13068 if (required_oldval
)
13070 if (inclusive_mask
== 0)
13074 gcc_assert (oldval
!= at
);
13075 mips_multi_add_insn ("and\t%0,%1,%2",
13076 at
, oldval
, inclusive_mask
, NULL
);
13079 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
13081 /* CMP = 0 [delay slot]. */
13083 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
13086 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
13087 if (exclusive_mask
== 0)
13091 gcc_assert (oldval
!= at
);
13092 mips_multi_add_insn ("and\t%0,%1,%z2",
13093 at
, oldval
, exclusive_mask
, NULL
);
13097 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
13099 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
13100 at least one instruction in that case. */
13101 if (insn1
== SYNC_INSN1_MOVE
13102 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
13106 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
13107 newval
, oldval
, insn1_op2
, NULL
);
13111 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
13112 if (insn2
== SYNC_INSN2_NOP
)
13116 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
13117 newval
, tmp2
, inclusive_mask
, NULL
);
13120 tmp3_insn
= mips_multi_last_index ();
13122 /* $AT = $TMP1 | $TMP3. */
13123 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
13125 mips_multi_set_operand (tmp3_insn
, 0, at
);
13130 gcc_assert (tmp1
!= tmp3
);
13131 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
13134 /* if (!commit (*MEM = $AT)) goto 1.
13136 This will sometimes be a delayed branch; see the write code below
13138 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
13140 /* When using branch likely (-mfix-r10000), the delay slot instruction
13141 will be annulled on false. The normal delay slot instructions
13142 calculate the overall result of the atomic operation and must not
13143 be annulled. To ensure this behaviour unconditionally use a NOP
13144 in the delay slot for the branch likely case. */
13146 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at
, NULL
);
13148 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
13149 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
13151 mips_multi_copy_insn (tmp3_insn
);
13152 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
13154 else if (!(required_oldval
&& cmp
) && !mips_branch_likely
)
13155 mips_multi_add_insn ("nop", NULL
);
13157 /* CMP = 1 -- either standalone or in a delay slot. */
13158 if (required_oldval
&& cmp
)
13159 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
13161 /* Output the acquire side of the memory barrier. */
13162 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
13163 mips_multi_add_insn ("sync", NULL
);
13165 /* Output the exit label, if needed. */
13166 if (required_oldval
)
13167 mips_multi_add_label ("2:");
13169 #undef READ_OPERAND
13172 /* Output and/or return the asm template for sync loop INSN, which has
13173 the operands given by OPERANDS. */
13176 mips_output_sync_loop (rtx_insn
*insn
, rtx
*operands
)
13178 /* Use branch-likely instructions to work around the LL/SC R10000
13180 mips_branch_likely
= TARGET_FIX_R10000
;
13182 mips_process_sync_loop (insn
, operands
);
13184 mips_push_asm_switch (&mips_noreorder
);
13185 mips_push_asm_switch (&mips_nomacro
);
13186 mips_push_asm_switch (&mips_noat
);
13187 mips_start_ll_sc_sync_block ();
13189 mips_multi_write ();
13191 mips_end_ll_sc_sync_block ();
13192 mips_pop_asm_switch (&mips_noat
);
13193 mips_pop_asm_switch (&mips_nomacro
);
13194 mips_pop_asm_switch (&mips_noreorder
);
13199 /* Return the number of individual instructions in sync loop INSN,
13200 which has the operands given by OPERANDS. */
13203 mips_sync_loop_insns (rtx_insn
*insn
, rtx
*operands
)
13205 /* Use branch-likely instructions to work around the LL/SC R10000
13207 mips_branch_likely
= TARGET_FIX_R10000
;
13208 mips_process_sync_loop (insn
, operands
);
13209 return mips_multi_num_insns
;
13212 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
13213 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
13215 When working around R4000 and R4400 errata, we need to make sure that
13216 the division is not immediately followed by a shift[1][2]. We also
13217 need to stop the division from being put into a branch delay slot[3].
13218 The easiest way to avoid both problems is to add a nop after the
13219 division. When a divide-by-zero check is needed, this nop can be
13220 used to fill the branch delay slot.
13222 [1] If a double-word or a variable shift executes immediately
13223 after starting an integer division, the shift may give an
13224 incorrect result. See quotations of errata #16 and #28 from
13225 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13226 in mips.md for details.
13228 [2] A similar bug to [1] exists for all revisions of the
13229 R4000 and the R4400 when run in an MC configuration.
13230 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
13232 "19. In this following sequence:
13234 ddiv (or ddivu or div or divu)
13235 dsll32 (or dsrl32, dsra32)
13237 if an MPT stall occurs, while the divide is slipping the cpu
13238 pipeline, then the following double shift would end up with an
13241 Workaround: The compiler needs to avoid generating any
13242 sequence with divide followed by extended double shift."
13244 This erratum is also present in "MIPS R4400MC Errata, Processor
13245 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
13246 & 3.0" as errata #10 and #4, respectively.
13248 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
13249 (also valid for MIPS R4000MC processors):
13251 "52. R4000SC: This bug does not apply for the R4000PC.
13253 There are two flavors of this bug:
13255 1) If the instruction just after divide takes an RF exception
13256 (tlb-refill, tlb-invalid) and gets an instruction cache
13257 miss (both primary and secondary) and the line which is
13258 currently in secondary cache at this index had the first
13259 data word, where the bits 5..2 are set, then R4000 would
13260 get a wrong result for the div.
13265 ------------------- # end-of page. -tlb-refill
13270 ------------------- # end-of page. -tlb-invalid
13273 2) If the divide is in the taken branch delay slot, where the
13274 target takes RF exception and gets an I-cache miss for the
13275 exception vector or where I-cache miss occurs for the
13276 target address, under the above mentioned scenarios, the
13277 div would get wrong results.
13280 j r2 # to next page mapped or unmapped
13281 div r8,r9 # this bug would be there as long
13282 # as there is an ICache miss and
13283 nop # the "data pattern" is present
13286 beq r0, r0, NextPage # to Next page
13290 This bug is present for div, divu, ddiv, and ddivu
13293 Workaround: For item 1), OS could make sure that the next page
13294 after the divide instruction is also mapped. For item 2), the
13295 compiler could make sure that the divide instruction is not in
13296 the branch delay slot."
13298 These processors have PRId values of 0x00004220 and 0x00004300 for
13299 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
13302 mips_output_division (const char *division
, rtx
*operands
)
13307 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
13309 output_asm_insn (s
, operands
);
13312 if (TARGET_CHECK_ZERO_DIV
)
13316 output_asm_insn (s
, operands
);
13317 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
13319 else if (GENERATE_DIVIDE_TRAPS
)
13321 /* Avoid long replay penalty on load miss by putting the trap before
13324 output_asm_insn ("teq\t%2,%.,7", operands
);
13327 output_asm_insn (s
, operands
);
13328 s
= "teq\t%2,%.,7";
13333 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
13334 output_asm_insn (s
, operands
);
13335 s
= "break\t7%)\n1:";
13341 /* Return true if destination of IN_INSN is used as add source in
13342 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13343 madd.s dst, x, y, z
13344 madd.s a, dst, b, c */
13347 mips_fmadd_bypass (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13349 int dst_reg
, src_reg
;
13351 gcc_assert (get_attr_type (in_insn
) == TYPE_FMADD
);
13352 gcc_assert (get_attr_type (out_insn
) == TYPE_FMADD
);
13354 extract_insn (in_insn
);
13355 dst_reg
= REG_P (recog_data
.operand
[0]);
13357 extract_insn (out_insn
);
13358 src_reg
= REG_P (recog_data
.operand
[1]);
13360 if (dst_reg
== src_reg
)
13366 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13367 instruction and if OUT_INSN assigns to the accumulator operand. */
13370 mips_linked_madd_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13372 enum attr_accum_in accum_in
;
13373 int accum_in_opnum
;
13376 if (recog_memoized (in_insn
) < 0)
13379 accum_in
= get_attr_accum_in (in_insn
);
13380 if (accum_in
== ACCUM_IN_NONE
)
13383 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
13385 extract_insn (in_insn
);
13386 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
13387 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
13389 return reg_set_p (accum_in_op
, out_insn
);
13392 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13393 data rather than the address. We need this because the cprestore
13394 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13395 which causes the default routine to abort. We just return false
13399 mips_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
13401 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
13404 return !store_data_bypass_p (out_insn
, in_insn
);
13408 /* Variables and flags used in scheduler hooks when tuning for
13412 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13415 /* If true, then next ALU1/2 instruction will go to ALU1. */
13418 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13421 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13422 int alu1_core_unit_code
;
13423 int alu2_core_unit_code
;
13424 int falu1_core_unit_code
;
13425 int falu2_core_unit_code
;
13427 /* True if current cycle has a multi instruction.
13428 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13429 bool cycle_has_multi_p
;
13431 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13432 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13434 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13435 instruction to go ALU1. */
13436 rtx_insn
*alu1_turn_enabled_insn
;
13437 rtx_insn
*alu2_turn_enabled_insn
;
13438 rtx_insn
*falu1_turn_enabled_insn
;
13439 rtx_insn
*falu2_turn_enabled_insn
;
13442 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13443 dependencies have no cost, except on the 20Kc where output-dependence
13444 is treated like input-dependence. */
13447 mips_adjust_cost (rtx_insn
*insn ATTRIBUTE_UNUSED
, rtx link
,
13448 rtx_insn
*dep ATTRIBUTE_UNUSED
, int cost
)
13450 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
13453 if (REG_NOTE_KIND (link
) != 0)
13458 /* Return the number of instructions that can be issued per cycle. */
13461 mips_issue_rate (void)
13465 case PROCESSOR_74KC
:
13466 case PROCESSOR_74KF2_1
:
13467 case PROCESSOR_74KF1_1
:
13468 case PROCESSOR_74KF3_2
:
13469 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13470 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13471 but in reality only a maximum of 3 insns can be issued as
13472 floating-point loads and stores also require a slot in the
13474 case PROCESSOR_R10000
:
13475 /* All R10K Processors are quad-issue (being the first MIPS
13476 processors to support this feature). */
13479 case PROCESSOR_20KC
:
13480 case PROCESSOR_R4130
:
13481 case PROCESSOR_R5400
:
13482 case PROCESSOR_R5500
:
13483 case PROCESSOR_R5900
:
13484 case PROCESSOR_R7000
:
13485 case PROCESSOR_R9000
:
13486 case PROCESSOR_OCTEON
:
13487 case PROCESSOR_OCTEON2
:
13488 case PROCESSOR_OCTEON3
:
13491 case PROCESSOR_SB1
:
13492 case PROCESSOR_SB1A
:
13493 /* This is actually 4, but we get better performance if we claim 3.
13494 This is partly because of unwanted speculative code motion with the
13495 larger number, and partly because in most common cases we can't
13496 reach the theoretical max of 4. */
13499 case PROCESSOR_LOONGSON_2E
:
13500 case PROCESSOR_LOONGSON_2F
:
13501 case PROCESSOR_LOONGSON_3A
:
13502 case PROCESSOR_P5600
:
13505 case PROCESSOR_XLP
:
13506 return (reload_completed
? 4 : 3);
13513 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13516 mips_ls2_init_dfa_post_cycle_insn (void)
13519 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13520 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
13524 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13525 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
13529 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13530 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
13534 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13535 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
13538 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
13539 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
13540 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
13541 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
13544 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13545 Init data used in mips_dfa_post_advance_cycle. */
13548 mips_init_dfa_post_cycle_insn (void)
13550 if (TUNE_LOONGSON_2EF
)
13551 mips_ls2_init_dfa_post_cycle_insn ();
13554 /* Initialize STATE when scheduling for Loongson 2E/2F.
13555 Support round-robin dispatch scheme by enabling only one of
13556 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13560 mips_ls2_dfa_post_advance_cycle (state_t state
)
13562 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
13564 /* Though there are no non-pipelined ALU1 insns,
13565 we can get an instruction of type 'multi' before reload. */
13566 gcc_assert (mips_ls2
.cycle_has_multi_p
);
13567 mips_ls2
.alu1_turn_p
= false;
13570 mips_ls2
.cycle_has_multi_p
= false;
13572 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
13573 /* We have a non-pipelined alu instruction in the core,
13574 adjust round-robin counter. */
13575 mips_ls2
.alu1_turn_p
= true;
13577 if (mips_ls2
.alu1_turn_p
)
13579 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
13580 gcc_unreachable ();
13584 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
13585 gcc_unreachable ();
13588 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
13590 /* There are no non-pipelined FALU1 insns. */
13591 gcc_unreachable ();
13592 mips_ls2
.falu1_turn_p
= false;
13595 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
13596 /* We have a non-pipelined falu instruction in the core,
13597 adjust round-robin counter. */
13598 mips_ls2
.falu1_turn_p
= true;
13600 if (mips_ls2
.falu1_turn_p
)
13602 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
13603 gcc_unreachable ();
13607 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
13608 gcc_unreachable ();
13612 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13613 This hook is being called at the start of each cycle. */
13616 mips_dfa_post_advance_cycle (void)
13618 if (TUNE_LOONGSON_2EF
)
13619 mips_ls2_dfa_post_advance_cycle (curr_state
);
13622 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13623 be as wide as the scheduling freedom in the DFA. */
13626 mips_multipass_dfa_lookahead (void)
13628 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13632 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
13644 /* Remove the instruction at index LOWER from ready queue READY and
13645 reinsert it in front of the instruction at index HIGHER. LOWER must
13649 mips_promote_ready (rtx_insn
**ready
, int lower
, int higher
)
13651 rtx_insn
*new_head
;
13654 new_head
= ready
[lower
];
13655 for (i
= lower
; i
< higher
; i
++)
13656 ready
[i
] = ready
[i
+ 1];
13657 ready
[i
] = new_head
;
13660 /* If the priority of the instruction at POS2 in the ready queue READY
13661 is within LIMIT units of that of the instruction at POS1, swap the
13662 instructions if POS2 is not already less than POS1. */
13665 mips_maybe_swap_ready (rtx_insn
**ready
, int pos1
, int pos2
, int limit
)
13668 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13672 temp
= ready
[pos1
];
13673 ready
[pos1
] = ready
[pos2
];
13674 ready
[pos2
] = temp
;
13678 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13679 that may clobber hi or lo. */
13680 static rtx_insn
*mips_macc_chains_last_hilo
;
13682 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13683 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13686 mips_macc_chains_record (rtx_insn
*insn
)
13688 if (get_attr_may_clobber_hilo (insn
))
13689 mips_macc_chains_last_hilo
= insn
;
13692 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13693 has NREADY elements, looking for a multiply-add or multiply-subtract
13694 instruction that is cumulative with mips_macc_chains_last_hilo.
13695 If there is one, promote it ahead of anything else that might
13696 clobber hi or lo. */
13699 mips_macc_chains_reorder (rtx_insn
**ready
, int nready
)
13703 if (mips_macc_chains_last_hilo
!= 0)
13704 for (i
= nready
- 1; i
>= 0; i
--)
13705 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13707 for (j
= nready
- 1; j
> i
; j
--)
13708 if (recog_memoized (ready
[j
]) >= 0
13709 && get_attr_may_clobber_hilo (ready
[j
]))
13711 mips_promote_ready (ready
, i
, j
);
13718 /* The last instruction to be scheduled. */
13719 static rtx_insn
*vr4130_last_insn
;
13721 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13722 points to an rtx that is initially an instruction. Nullify the rtx
13723 if the instruction uses the value of register X. */
13726 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13731 insn_ptr
= (rtx
*) data
;
13734 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13738 /* Return true if there is true register dependence between vr4130_last_insn
13742 vr4130_true_reg_dependence_p (rtx insn
)
13744 note_stores (PATTERN (vr4130_last_insn
),
13745 vr4130_true_reg_dependence_p_1
, &insn
);
13749 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13750 the ready queue and that INSN2 is the instruction after it, return
13751 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13752 in which INSN1 and INSN2 can probably issue in parallel, but for
13753 which (INSN2, INSN1) should be less sensitive to instruction
13754 alignment than (INSN1, INSN2). See 4130.md for more details. */
13757 vr4130_swap_insns_p (rtx_insn
*insn1
, rtx_insn
*insn2
)
13759 sd_iterator_def sd_it
;
13762 /* Check for the following case:
13764 1) there is some other instruction X with an anti dependence on INSN1;
13765 2) X has a higher priority than INSN2; and
13766 3) X is an arithmetic instruction (and thus has no unit restrictions).
13768 If INSN1 is the last instruction blocking X, it would better to
13769 choose (INSN1, X) over (INSN2, INSN1). */
13770 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13771 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13772 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13773 && recog_memoized (DEP_CON (dep
)) >= 0
13774 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13777 if (vr4130_last_insn
!= 0
13778 && recog_memoized (insn1
) >= 0
13779 && recog_memoized (insn2
) >= 0)
13781 /* See whether INSN1 and INSN2 use different execution units,
13782 or if they are both ALU-type instructions. If so, they can
13783 probably execute in parallel. */
13784 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13785 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13786 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13788 /* If only one of the instructions has a dependence on
13789 vr4130_last_insn, prefer to schedule the other one first. */
13790 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13791 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13792 if (dep1_p
!= dep2_p
)
13795 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13796 is not an ALU-type instruction and if INSN1 uses the same
13797 execution unit. (Note that if this condition holds, we already
13798 know that INSN2 uses a different execution unit.) */
13799 if (class1
!= VR4130_CLASS_ALU
13800 && recog_memoized (vr4130_last_insn
) >= 0
13801 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13808 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13809 queue with at least two instructions. Swap the first two if
13810 vr4130_swap_insns_p says that it could be worthwhile. */
13813 vr4130_reorder (rtx_insn
**ready
, int nready
)
13815 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13816 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13819 /* Record whether last 74k AGEN instruction was a load or store. */
13820 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13822 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13823 resets to TYPE_UNKNOWN state. */
13826 mips_74k_agen_init (rtx_insn
*insn
)
13828 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13829 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13832 enum attr_type type
= get_attr_type (insn
);
13833 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13834 mips_last_74k_agen_insn
= type
;
13838 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13839 loads to be grouped together, and multiple stores to be grouped
13840 together. Swap things around in the ready queue to make this happen. */
13843 mips_74k_agen_reorder (rtx_insn
**ready
, int nready
)
13846 int store_pos
, load_pos
;
13851 for (i
= nready
- 1; i
>= 0; i
--)
13853 rtx_insn
*insn
= ready
[i
];
13854 if (USEFUL_INSN_P (insn
))
13855 switch (get_attr_type (insn
))
13858 if (store_pos
== -1)
13863 if (load_pos
== -1)
13872 if (load_pos
== -1 || store_pos
== -1)
13875 switch (mips_last_74k_agen_insn
)
13878 /* Prefer to schedule loads since they have a higher latency. */
13880 /* Swap loads to the front of the queue. */
13881 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13884 /* Swap stores to the front of the queue. */
13885 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13892 /* Implement TARGET_SCHED_INIT. */
13895 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13896 int max_ready ATTRIBUTE_UNUSED
)
13898 mips_macc_chains_last_hilo
= 0;
13899 vr4130_last_insn
= 0;
13900 mips_74k_agen_init (NULL
);
13902 /* When scheduling for Loongson2, branch instructions go to ALU1,
13903 therefore basic block is most likely to start with round-robin counter
13904 pointed to ALU2. */
13905 mips_ls2
.alu1_turn_p
= false;
13906 mips_ls2
.falu1_turn_p
= true;
13909 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13912 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13913 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13915 if (!reload_completed
13916 && TUNE_MACC_CHAINS
13918 mips_macc_chains_reorder (ready
, *nreadyp
);
13920 if (reload_completed
13922 && !TARGET_VR4130_ALIGN
13924 vr4130_reorder (ready
, *nreadyp
);
13927 mips_74k_agen_reorder (ready
, *nreadyp
);
13930 /* Implement TARGET_SCHED_REORDER. */
13933 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13934 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13936 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13937 return mips_issue_rate ();
13940 /* Implement TARGET_SCHED_REORDER2. */
13943 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13944 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13946 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13947 return cached_can_issue_more
;
13950 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13953 mips_ls2_variable_issue (rtx_insn
*insn
)
13955 if (mips_ls2
.alu1_turn_p
)
13957 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13958 mips_ls2
.alu1_turn_p
= false;
13962 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13963 mips_ls2
.alu1_turn_p
= true;
13966 if (mips_ls2
.falu1_turn_p
)
13968 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13969 mips_ls2
.falu1_turn_p
= false;
13973 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13974 mips_ls2
.falu1_turn_p
= true;
13977 if (recog_memoized (insn
) >= 0)
13978 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13981 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13984 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13985 rtx_insn
*insn
, int more
)
13987 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13988 if (USEFUL_INSN_P (insn
))
13990 if (get_attr_type (insn
) != TYPE_GHOST
)
13992 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13993 mips_macc_chains_record (insn
);
13994 vr4130_last_insn
= insn
;
13996 mips_74k_agen_init (insn
);
13997 else if (TUNE_LOONGSON_2EF
)
13998 mips_ls2_variable_issue (insn
);
14001 /* Instructions of type 'multi' should all be split before
14002 the second scheduling pass. */
14003 gcc_assert (!reload_completed
14004 || recog_memoized (insn
) < 0
14005 || get_attr_type (insn
) != TYPE_MULTI
);
14007 cached_can_issue_more
= more
;
14011 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
14012 return the first operand of the associated PREF or PREFX insn. */
14015 mips_prefetch_cookie (rtx write
, rtx locality
)
14017 /* store_streamed / load_streamed. */
14018 if (INTVAL (locality
) <= 0)
14019 return GEN_INT (INTVAL (write
) + 4);
14021 /* store / load. */
14022 if (INTVAL (locality
) <= 2)
14025 /* store_retained / load_retained. */
14026 return GEN_INT (INTVAL (write
) + 6);
14029 /* Flags that indicate when a built-in function is available.
14031 BUILTIN_AVAIL_NON_MIPS16
14032 The function is available on the current target if !TARGET_MIPS16.
14034 BUILTIN_AVAIL_MIPS16
14035 The function is available on the current target if TARGET_MIPS16. */
14036 #define BUILTIN_AVAIL_NON_MIPS16 1
14037 #define BUILTIN_AVAIL_MIPS16 2
14039 /* Declare an availability predicate for built-in functions that
14040 require non-MIPS16 mode and also require COND to be true.
14041 NAME is the main part of the predicate's name. */
14042 #define AVAIL_NON_MIPS16(NAME, COND) \
14043 static unsigned int \
14044 mips_builtin_avail_##NAME (void) \
14046 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
14049 /* Declare an availability predicate for built-in functions that
14050 support both MIPS16 and non-MIPS16 code and also require COND
14051 to be true. NAME is the main part of the predicate's name. */
14052 #define AVAIL_ALL(NAME, COND) \
14053 static unsigned int \
14054 mips_builtin_avail_##NAME (void) \
14056 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
14059 /* This structure describes a single built-in function. */
14060 struct mips_builtin_description
{
14061 /* The code of the main .md file instruction. See mips_builtin_type
14062 for more information. */
14063 enum insn_code icode
;
14065 /* The floating-point comparison code to use with ICODE, if any. */
14066 enum mips_fp_condition cond
;
14068 /* The name of the built-in function. */
14071 /* Specifies how the function should be expanded. */
14072 enum mips_builtin_type builtin_type
;
14074 /* The function's prototype. */
14075 enum mips_function_type function_type
;
14077 /* Whether the function is available. */
14078 unsigned int (*avail
) (void);
14081 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
14082 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
14083 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
14084 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
14085 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
14086 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
14087 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
14088 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
14089 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
14090 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
14091 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
14093 /* Construct a mips_builtin_description from the given arguments.
14095 INSN is the name of the associated instruction pattern, without the
14096 leading CODE_FOR_mips_.
14098 CODE is the floating-point condition code associated with the
14099 function. It can be 'f' if the field is not applicable.
14101 NAME is the name of the function itself, without the leading
14104 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
14106 AVAIL is the name of the availability predicate, without the leading
14107 mips_builtin_avail_. */
14108 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
14109 FUNCTION_TYPE, AVAIL) \
14110 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
14111 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
14112 mips_builtin_avail_ ## AVAIL }
14114 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
14115 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
14116 are as for MIPS_BUILTIN. */
14117 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14118 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
14120 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
14121 are subject to mips_builtin_avail_<AVAIL>. */
14122 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
14123 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
14124 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
14125 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
14126 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
14128 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
14129 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
14130 while the any and all forms are subject to mips_builtin_avail_mips3d. */
14131 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
14132 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
14133 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
14135 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
14136 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
14138 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
14139 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
14141 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
14142 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
14145 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
14146 are subject to mips_builtin_avail_mips3d. */
14147 #define CMP_4S_BUILTINS(INSN, COND) \
14148 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
14149 MIPS_BUILTIN_CMP_ANY, \
14150 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
14151 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
14152 MIPS_BUILTIN_CMP_ALL, \
14153 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
14155 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
14156 instruction requires mips_builtin_avail_<AVAIL>. */
14157 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
14158 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
14159 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14161 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
14162 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
14165 /* Define all the built-in functions related to C.cond.fmt condition COND. */
14166 #define CMP_BUILTINS(COND) \
14167 MOVTF_BUILTINS (c, COND, paired_single), \
14168 MOVTF_BUILTINS (cabs, COND, mips3d), \
14169 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
14170 CMP_PS_BUILTINS (c, COND, paired_single), \
14171 CMP_PS_BUILTINS (cabs, COND, mips3d), \
14172 CMP_4S_BUILTINS (c, COND), \
14173 CMP_4S_BUILTINS (cabs, COND)
14175 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
14176 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
14177 and AVAIL are as for MIPS_BUILTIN. */
14178 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
14179 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
14180 FUNCTION_TYPE, AVAIL)
14182 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
14183 branch instruction. AVAIL is as for MIPS_BUILTIN. */
14184 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
14185 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
14186 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
14188 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
14189 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14190 builtin_description field. */
14191 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
14192 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
14193 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
14194 FUNCTION_TYPE, mips_builtin_avail_loongson }
14196 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
14197 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
14198 builtin_description field. */
14199 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
14200 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
14202 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
14203 We use functions of this form when the same insn can be usefully applied
14204 to more than one datatype. */
14205 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
14206 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
14208 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
14209 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
14210 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
14211 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
14212 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
14213 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
14214 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
14215 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
14217 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
14218 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
14219 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
14220 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
14221 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
14222 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
14223 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
14224 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
14225 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
14226 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
14227 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
14228 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
14229 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
14230 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
14231 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
14232 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
14233 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
14234 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
14235 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
14236 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
14237 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
14238 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
14239 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
14240 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
14241 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
14242 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
14243 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
14244 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
14245 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
14246 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
14248 static const struct mips_builtin_description mips_builtins
[] = {
14249 #define MIPS_GET_FCSR 0
14250 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
14251 #define MIPS_SET_FCSR 1
14252 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
14254 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14255 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14256 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14257 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
14258 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
14259 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
14260 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
14261 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
14263 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
14264 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14265 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14266 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14267 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14269 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
14270 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
14271 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14272 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
14273 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
14274 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14276 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
14277 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
14278 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
14279 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
14280 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
14281 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
14283 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
14285 /* Built-in functions for the SB-1 processor. */
14286 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
14288 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
14289 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14290 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14291 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14292 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14293 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14294 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14295 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14296 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14297 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14298 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14299 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14300 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14301 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14302 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
14303 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
14304 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
14305 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14306 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
14307 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
14308 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
14309 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
14310 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
14311 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14312 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14313 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14314 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14315 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14316 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14317 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14318 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
14319 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14320 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14321 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14322 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14323 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
14324 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14325 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
14326 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14327 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14328 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
14329 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14330 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14331 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
14332 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
14333 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
14334 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
14335 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
14336 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14337 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14338 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
14339 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14340 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14341 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
14342 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14343 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14344 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
14345 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
14346 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14347 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
14348 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
14349 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
14350 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14351 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14352 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
14353 BPOSGE_BUILTIN (32, dsp
),
14355 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14356 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
14357 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14358 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14359 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14360 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14361 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14362 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14363 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14364 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14365 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
14366 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14367 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14368 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14369 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14370 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14371 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
14372 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14373 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
14374 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
14375 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14376 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
14377 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
14378 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14379 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14380 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14381 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
14382 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14383 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14384 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14385 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14386 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14387 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
14388 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14389 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
14391 /* Built-in functions for the DSP ASE (32-bit only). */
14392 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14393 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14394 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14395 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
14396 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14397 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14398 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14399 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14400 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14401 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14402 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14403 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14404 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
14405 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14406 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14407 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14408 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14409 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14410 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
14411 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14412 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
14413 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14414 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14415 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
14416 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
14417 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
14418 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
14420 /* Built-in functions for the DSP ASE (64-bit only). */
14421 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
14423 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14424 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14425 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14426 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14427 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14428 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14429 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14430 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14431 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14432 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
14434 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14435 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
14436 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
14437 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
14438 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14439 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14440 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14441 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14442 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14443 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14444 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14445 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
14446 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14447 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14448 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14449 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14450 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
14451 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14452 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14453 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14454 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
14455 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14456 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14457 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14458 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14459 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14460 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14461 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14462 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14463 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14464 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14465 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14466 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14467 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14468 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14469 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14470 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14471 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14472 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
14473 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
14474 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14475 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14476 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14477 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14478 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14479 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14480 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14481 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14482 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
14483 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14484 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14485 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14486 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14487 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
14488 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
14489 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14490 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14491 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14492 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
14493 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14494 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
14495 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
14496 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14497 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14498 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14499 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14500 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14501 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14502 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14503 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14504 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14505 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14506 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
14507 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
14508 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
14509 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
14510 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14511 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14512 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14513 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14514 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14515 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14516 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
14517 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
14518 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14519 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14520 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14521 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14522 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14523 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14524 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14525 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14526 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14527 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14528 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
14529 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
14530 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
14531 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
14532 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
14533 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
14535 /* Sundry other built-in functions. */
14536 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
14539 /* Index I is the function declaration for mips_builtins[I], or null if the
14540 function isn't defined on this target. */
14541 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
14543 /* MODE is a vector mode whose elements have type TYPE. Return the type
14544 of the vector itself. */
14547 mips_builtin_vector_type (tree type
, machine_mode mode
)
14549 static tree types
[2 * (int) MAX_MACHINE_MODE
];
14552 mode_index
= (int) mode
;
14554 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
14555 mode_index
+= MAX_MACHINE_MODE
;
14557 if (types
[mode_index
] == NULL_TREE
)
14558 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
14559 return types
[mode_index
];
14562 /* Return a type for 'const volatile void *'. */
14565 mips_build_cvpointer_type (void)
14569 if (cache
== NULL_TREE
)
14570 cache
= build_pointer_type (build_qualified_type
14572 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
14576 /* Source-level argument types. */
14577 #define MIPS_ATYPE_VOID void_type_node
14578 #define MIPS_ATYPE_INT integer_type_node
14579 #define MIPS_ATYPE_POINTER ptr_type_node
14580 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14582 /* Standard mode-based argument types. */
14583 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14584 #define MIPS_ATYPE_SI intSI_type_node
14585 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14586 #define MIPS_ATYPE_DI intDI_type_node
14587 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14588 #define MIPS_ATYPE_SF float_type_node
14589 #define MIPS_ATYPE_DF double_type_node
14591 /* Vector argument types. */
14592 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14593 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14594 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14595 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14596 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14597 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14598 #define MIPS_ATYPE_UV2SI \
14599 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14600 #define MIPS_ATYPE_UV4HI \
14601 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14602 #define MIPS_ATYPE_UV8QI \
14603 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14605 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14606 their associated MIPS_ATYPEs. */
14607 #define MIPS_FTYPE_ATYPES1(A, B) \
14608 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14610 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14611 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14613 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14614 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14616 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14617 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14620 /* Return the function type associated with function prototype TYPE. */
14623 mips_build_function_type (enum mips_function_type type
)
14625 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
14627 if (types
[(int) type
] == NULL_TREE
)
14630 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14631 case MIPS_FTYPE_NAME##NUM ARGS: \
14632 types[(int) type] \
14633 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14636 #include "config/mips/mips-ftypes.def"
14637 #undef DEF_MIPS_FTYPE
14639 gcc_unreachable ();
14642 return types
[(int) type
];
14645 /* Implement TARGET_INIT_BUILTINS. */
14648 mips_init_builtins (void)
14650 const struct mips_builtin_description
*d
;
14653 /* Iterate through all of the bdesc arrays, initializing all of the
14654 builtin functions. */
14655 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
14657 d
= &mips_builtins
[i
];
14659 mips_builtin_decls
[i
]
14660 = add_builtin_function (d
->name
,
14661 mips_build_function_type (d
->function_type
),
14662 i
, BUILT_IN_MD
, NULL
, NULL
);
14666 /* Implement TARGET_BUILTIN_DECL. */
14669 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
14671 if (code
>= ARRAY_SIZE (mips_builtins
))
14672 return error_mark_node
;
14673 return mips_builtin_decls
[code
];
14676 /* Take argument ARGNO from EXP's argument list and convert it into
14677 an expand operand. Store the operand in *OP. */
14680 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14681 unsigned int argno
)
14686 arg
= CALL_EXPR_ARG (exp
, argno
);
14687 value
= expand_normal (arg
);
14688 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14691 /* Expand instruction ICODE as part of a built-in function sequence.
14692 Use the first NOPS elements of OPS as the instruction's operands.
14693 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14694 instruction has no target.
14696 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14699 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14700 struct expand_operand
*ops
, bool has_target_p
)
14702 if (!maybe_expand_insn (icode
, nops
, ops
))
14704 error ("invalid argument to built-in function");
14705 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14707 return has_target_p
? ops
[0].value
: const0_rtx
;
14710 /* Expand a floating-point comparison for built-in function call EXP.
14711 The first NARGS arguments are the values to be compared. ICODE is
14712 the .md pattern that does the comparison and COND is the condition
14713 that is being tested. Return an rtx for the result. */
14716 mips_expand_builtin_compare_1 (enum insn_code icode
,
14717 enum mips_fp_condition cond
,
14718 tree exp
, int nargs
)
14720 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14724 /* The instruction should have a target operand, an operand for each
14725 argument, and an operand for COND. */
14726 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14728 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14730 create_fixed_operand (&ops
[opno
++], output
);
14731 for (argno
= 0; argno
< nargs
; argno
++)
14732 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14733 create_integer_operand (&ops
[opno
++], (int) cond
);
14734 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14737 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14738 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14739 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14740 suggests a good place to put the result. */
14743 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14746 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14749 /* Map any target to operand 0. */
14752 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14754 /* Map the arguments to the other operands. */
14755 gcc_assert (opno
+ call_expr_nargs (exp
)
14756 == insn_data
[icode
].n_generator_args
);
14757 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14758 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14760 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14763 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14764 function; TYPE says which. EXP is the CALL_EXPR that calls the
14765 function, ICODE is the instruction that should be used to compare
14766 the first two arguments, and COND is the condition it should test.
14767 TARGET, if nonnull, suggests a good place to put the result. */
14770 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14771 enum insn_code icode
, enum mips_fp_condition cond
,
14772 rtx target
, tree exp
)
14774 struct expand_operand ops
[4];
14777 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14778 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14779 if (type
== MIPS_BUILTIN_MOVT
)
14781 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14782 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14786 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14787 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14789 create_fixed_operand (&ops
[3], cmp_result
);
14790 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14794 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14795 into TARGET otherwise. Return TARGET. */
14798 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14799 rtx value_if_true
, rtx value_if_false
)
14801 rtx_code_label
*true_label
, *done_label
;
14803 true_label
= gen_label_rtx ();
14804 done_label
= gen_label_rtx ();
14806 /* First assume that CONDITION is false. */
14807 mips_emit_move (target
, value_if_false
);
14809 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14810 emit_jump_insn (gen_condjump (condition
, true_label
));
14811 emit_jump_insn (gen_jump (done_label
));
14814 /* Fix TARGET if CONDITION is true. */
14815 emit_label (true_label
);
14816 mips_emit_move (target
, value_if_true
);
14818 emit_label (done_label
);
14822 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14823 the CALL_EXPR that calls the function, ICODE is the code of the
14824 comparison instruction, and COND is the condition it should test.
14825 TARGET, if nonnull, suggests a good place to put the boolean result. */
14828 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14829 enum insn_code icode
, enum mips_fp_condition cond
,
14830 rtx target
, tree exp
)
14832 rtx offset
, condition
, cmp_result
;
14834 if (target
== 0 || GET_MODE (target
) != SImode
)
14835 target
= gen_reg_rtx (SImode
);
14836 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14837 call_expr_nargs (exp
));
14839 /* If the comparison sets more than one register, we define the result
14840 to be 0 if all registers are false and -1 if all registers are true.
14841 The value of the complete result is indeterminate otherwise. */
14842 switch (builtin_type
)
14844 case MIPS_BUILTIN_CMP_ALL
:
14845 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14846 return mips_builtin_branch_and_move (condition
, target
,
14847 const0_rtx
, const1_rtx
);
14849 case MIPS_BUILTIN_CMP_UPPER
:
14850 case MIPS_BUILTIN_CMP_LOWER
:
14851 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14852 condition
= gen_single_cc (cmp_result
, offset
);
14853 return mips_builtin_branch_and_move (condition
, target
,
14854 const1_rtx
, const0_rtx
);
14857 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14858 return mips_builtin_branch_and_move (condition
, target
,
14859 const1_rtx
, const0_rtx
);
14863 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14864 if nonnull, suggests a good place to put the boolean result. */
14867 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14869 rtx condition
, cmp_result
;
14872 if (target
== 0 || GET_MODE (target
) != SImode
)
14873 target
= gen_reg_rtx (SImode
);
14875 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14877 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14882 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14883 return mips_builtin_branch_and_move (condition
, target
,
14884 const1_rtx
, const0_rtx
);
14887 /* Implement TARGET_EXPAND_BUILTIN. */
14890 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14891 machine_mode mode
, int ignore
)
14894 unsigned int fcode
, avail
;
14895 const struct mips_builtin_description
*d
;
14897 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14898 fcode
= DECL_FUNCTION_CODE (fndecl
);
14899 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14900 d
= &mips_builtins
[fcode
];
14901 avail
= d
->avail ();
14902 gcc_assert (avail
!= 0);
14903 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
14905 error ("built-in function %qE not supported for MIPS16",
14906 DECL_NAME (fndecl
));
14907 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14909 switch (d
->builtin_type
)
14911 case MIPS_BUILTIN_DIRECT
:
14912 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14914 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14915 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14917 case MIPS_BUILTIN_MOVT
:
14918 case MIPS_BUILTIN_MOVF
:
14919 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14920 d
->cond
, target
, exp
);
14922 case MIPS_BUILTIN_CMP_ANY
:
14923 case MIPS_BUILTIN_CMP_ALL
:
14924 case MIPS_BUILTIN_CMP_UPPER
:
14925 case MIPS_BUILTIN_CMP_LOWER
:
14926 case MIPS_BUILTIN_CMP_SINGLE
:
14927 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14928 d
->cond
, target
, exp
);
14930 case MIPS_BUILTIN_BPOSGE32
:
14931 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14933 gcc_unreachable ();
14936 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14937 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14938 struct mips16_constant
{
14939 struct mips16_constant
*next
;
14941 rtx_code_label
*label
;
14945 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14946 first constant, HIGHEST_ADDRESS is the highest address that the first
14947 byte of the pool can have, and INSN_ADDRESS is the current instruction
14949 struct mips16_constant_pool
{
14950 struct mips16_constant
*first
;
14951 int highest_address
;
14955 /* Add constant VALUE to POOL and return its label. MODE is the
14956 value's mode (used for CONST_INTs, etc.). */
14958 static rtx_code_label
*
14959 mips16_add_constant (struct mips16_constant_pool
*pool
,
14960 rtx value
, machine_mode mode
)
14962 struct mips16_constant
**p
, *c
;
14963 bool first_of_size_p
;
14965 /* See whether the constant is already in the pool. If so, return the
14966 existing label, otherwise leave P pointing to the place where the
14967 constant should be added.
14969 Keep the pool sorted in increasing order of mode size so that we can
14970 reduce the number of alignments needed. */
14971 first_of_size_p
= true;
14972 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14974 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14975 return (*p
)->label
;
14976 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14978 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14979 first_of_size_p
= false;
14982 /* In the worst case, the constant needed by the earliest instruction
14983 will end up at the end of the pool. The entire pool must then be
14984 accessible from that instruction.
14986 When adding the first constant, set the pool's highest address to
14987 the address of the first out-of-range byte. Adjust this address
14988 downwards each time a new constant is added. */
14989 if (pool
->first
== 0)
14990 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14991 of the instruction with the lowest two bits clear. The base PC
14992 value for LDPC has the lowest three bits clear. Assume the worst
14993 case here; namely that the PC-relative instruction occupies the
14994 last 2 bytes in an aligned word. */
14995 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14996 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14997 if (first_of_size_p
)
14998 /* Take into account the worst possible padding due to alignment. */
14999 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
15001 /* Create a new entry. */
15002 c
= XNEW (struct mips16_constant
);
15005 c
->label
= gen_label_rtx ();
15012 /* Output constant VALUE after instruction INSN and return the last
15013 instruction emitted. MODE is the mode of the constant. */
15016 mips16_emit_constants_1 (machine_mode mode
, rtx value
, rtx_insn
*insn
)
15018 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
15020 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
15021 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
15024 if (SCALAR_FLOAT_MODE_P (mode
))
15025 return emit_insn_after (gen_consttable_float (value
), insn
);
15027 if (VECTOR_MODE_P (mode
))
15031 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
15032 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
15033 CONST_VECTOR_ELT (value
, i
), insn
);
15037 gcc_unreachable ();
15040 /* Dump out the constants in CONSTANTS after INSN. */
15043 mips16_emit_constants (struct mips16_constant
*constants
, rtx_insn
*insn
)
15045 struct mips16_constant
*c
, *next
;
15049 for (c
= constants
; c
!= NULL
; c
= next
)
15051 /* If necessary, increase the alignment of PC. */
15052 if (align
< GET_MODE_SIZE (c
->mode
))
15054 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
15055 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
15057 align
= GET_MODE_SIZE (c
->mode
);
15059 insn
= emit_label_after (c
->label
, insn
);
15060 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
15066 emit_barrier_after (insn
);
15069 /* Return the length of instruction INSN. */
15072 mips16_insn_length (rtx_insn
*insn
)
15074 if (JUMP_TABLE_DATA_P (insn
))
15076 rtx body
= PATTERN (insn
);
15077 if (GET_CODE (body
) == ADDR_VEC
)
15078 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
15079 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
15080 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
15082 gcc_unreachable ();
15084 return get_attr_length (insn
);
15087 /* If *X is a symbolic constant that refers to the constant pool, add
15088 the constant to POOL and rewrite *X to use the constant's label. */
15091 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
15094 rtx_code_label
*label
;
15096 split_const (*x
, &base
, &offset
);
15097 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
15099 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
15100 get_pool_mode (base
));
15101 base
= gen_rtx_LABEL_REF (Pmode
, label
);
15102 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
15106 /* Rewrite INSN so that constant pool references refer to the constant's
15110 mips16_rewrite_pool_refs (rtx_insn
*insn
, struct mips16_constant_pool
*pool
)
15112 subrtx_ptr_iterator::array_type array
;
15113 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), ALL
)
15117 if (force_to_mem_operand (*loc
, Pmode
))
15119 rtx mem
= force_const_mem (GET_MODE (*loc
), *loc
);
15120 validate_change (insn
, loc
, mem
, false);
15125 mips16_rewrite_pool_constant (pool
, &XEXP (*loc
, 0));
15126 iter
.skip_subrtxes ();
15130 if (TARGET_MIPS16_TEXT_LOADS
)
15131 mips16_rewrite_pool_constant (pool
, loc
);
15132 if (GET_CODE (*loc
) == CONST
15133 /* Don't rewrite the __mips16_rdwr symbol. */
15134 || (GET_CODE (*loc
) == UNSPEC
15135 && XINT (*loc
, 1) == UNSPEC_TLS_GET_TP
))
15136 iter
.skip_subrtxes ();
15141 /* Return whether CFG is used in mips_reorg. */
15144 mips_cfg_in_reorg (void)
15146 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
15147 || TARGET_RELAX_PIC_CALLS
);
15150 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
15151 otherwise assume that they are already split. */
15154 mips16_lay_out_constants (bool split_p
)
15156 struct mips16_constant_pool pool
;
15157 rtx_insn
*insn
, *barrier
;
15159 if (!TARGET_MIPS16_PCREL_LOADS
)
15164 if (mips_cfg_in_reorg ())
15165 split_all_insns ();
15167 split_all_insns_noflow ();
15170 memset (&pool
, 0, sizeof (pool
));
15171 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15173 /* Rewrite constant pool references in INSN. */
15174 if (USEFUL_INSN_P (insn
))
15175 mips16_rewrite_pool_refs (insn
, &pool
);
15177 pool
.insn_address
+= mips16_insn_length (insn
);
15179 if (pool
.first
!= NULL
)
15181 /* If there are no natural barriers between the first user of
15182 the pool and the highest acceptable address, we'll need to
15183 create a new instruction to jump around the constant pool.
15184 In the worst case, this instruction will be 4 bytes long.
15186 If it's too late to do this transformation after INSN,
15187 do it immediately before INSN. */
15188 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
15190 rtx_code_label
*label
;
15193 label
= gen_label_rtx ();
15195 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
15196 JUMP_LABEL (jump
) = label
;
15197 LABEL_NUSES (label
) = 1;
15198 barrier
= emit_barrier_after (jump
);
15200 emit_label_after (label
, barrier
);
15201 pool
.insn_address
+= 4;
15204 /* See whether the constant pool is now out of range of the first
15205 user. If so, output the constants after the previous barrier.
15206 Note that any instructions between BARRIER and INSN (inclusive)
15207 will use negative offsets to refer to the pool. */
15208 if (pool
.insn_address
> pool
.highest_address
)
15210 mips16_emit_constants (pool
.first
, barrier
);
15214 else if (BARRIER_P (insn
))
15218 mips16_emit_constants (pool
.first
, get_last_insn ());
15221 /* Return true if it is worth r10k_simplify_address's while replacing
15222 an address with X. We are looking for constants, and for addresses
15223 at a known offset from the incoming stack pointer. */
15226 r10k_simplified_address_p (rtx x
)
15228 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
15230 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
15233 /* X is an expression that appears in INSN. Try to use the UD chains
15234 to simplify it, returning the simplified form on success and the
15235 original form otherwise. Replace the incoming value of $sp with
15236 virtual_incoming_args_rtx (which should never occur in X otherwise). */
15239 r10k_simplify_address (rtx x
, rtx_insn
*insn
)
15241 rtx newx
, op0
, op1
, set
, note
;
15242 rtx_insn
*def_insn
;
15244 struct df_link
*defs
;
15249 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15250 if (op0
!= XEXP (x
, 0))
15251 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
15252 op0
, GET_MODE (XEXP (x
, 0)));
15254 else if (BINARY_P (x
))
15256 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15257 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
15258 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
15259 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
15261 else if (GET_CODE (x
) == LO_SUM
)
15263 /* LO_SUMs can be offset from HIGHs, if we know they won't
15264 overflow. See mips_classify_address for the rationale behind
15266 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
15267 if (GET_CODE (op0
) == HIGH
)
15268 newx
= XEXP (x
, 1);
15270 else if (REG_P (x
))
15272 /* Uses are recorded by regno_reg_rtx, not X itself. */
15273 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
15275 defs
= DF_REF_CHAIN (use
);
15277 /* Require a single definition. */
15278 if (defs
&& defs
->next
== NULL
)
15281 if (DF_REF_IS_ARTIFICIAL (def
))
15283 /* Replace the incoming value of $sp with
15284 virtual_incoming_args_rtx. */
15285 if (x
== stack_pointer_rtx
15286 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
15287 newx
= virtual_incoming_args_rtx
;
15289 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
15292 /* Make sure that DEF_INSN is a single set of REG. */
15293 def_insn
= DF_REF_INSN (def
);
15294 if (NONJUMP_INSN_P (def_insn
))
15296 set
= single_set (def_insn
);
15297 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
15299 /* Prefer to use notes, since the def-use chains
15300 are often shorter. */
15301 note
= find_reg_equal_equiv_note (def_insn
);
15303 newx
= XEXP (note
, 0);
15305 newx
= SET_SRC (set
);
15306 newx
= r10k_simplify_address (newx
, def_insn
);
15312 if (newx
&& r10k_simplified_address_p (newx
))
15317 /* Return true if ADDRESS is known to be an uncached address
15318 on R10K systems. */
15321 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
15323 unsigned HOST_WIDE_INT upper
;
15325 /* Check for KSEG1. */
15326 if (address
+ 0x60000000 < 0x20000000)
15329 /* Check for uncached XKPHYS addresses. */
15330 if (Pmode
== DImode
)
15332 upper
= (address
>> 40) & 0xf9ffff;
15333 if (upper
== 0x900000 || upper
== 0xb80000)
15339 /* Return true if we can prove that an access to address X in instruction
15340 INSN would be safe from R10K speculation. This X is a general
15341 expression; it might not be a legitimate address. */
15344 r10k_safe_address_p (rtx x
, rtx_insn
*insn
)
15347 HOST_WIDE_INT offset_val
;
15349 x
= r10k_simplify_address (x
, insn
);
15351 /* Check for references to the stack frame. It doesn't really matter
15352 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15353 allows us to assume that accesses to any part of the eventual frame
15354 is safe from speculation at any point in the function. */
15355 mips_split_plus (x
, &base
, &offset_val
);
15356 if (base
== virtual_incoming_args_rtx
15357 && offset_val
>= -cfun
->machine
->frame
.total_size
15358 && offset_val
< cfun
->machine
->frame
.args_size
)
15361 /* Check for uncached addresses. */
15362 if (CONST_INT_P (x
))
15363 return r10k_uncached_address_p (INTVAL (x
));
15365 /* Check for accesses to a static object. */
15366 split_const (x
, &base
, &offset
);
15367 return offset_within_block_p (base
, INTVAL (offset
));
15370 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15371 an in-range access to an automatic variable, or to an object with
15372 a link-time-constant address. */
15375 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
15377 HOST_WIDE_INT bitoffset
, bitsize
;
15378 tree inner
, var_offset
;
15380 int unsigned_p
, volatile_p
;
15382 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
15383 &unsigned_p
, &volatile_p
, false);
15384 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
15387 offset
+= bitoffset
/ BITS_PER_UNIT
;
15388 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
15391 /* Return true if X contains a MEM that is not safe from R10K speculation.
15392 INSN is the instruction that contains X. */
15395 r10k_needs_protection_p_1 (rtx x
, rtx_insn
*insn
)
15397 subrtx_var_iterator::array_type array
;
15398 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
15403 if ((MEM_EXPR (mem
)
15404 && MEM_OFFSET_KNOWN_P (mem
)
15405 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
15406 || r10k_safe_address_p (XEXP (mem
, 0), insn
))
15407 iter
.skip_subrtxes ();
15415 /* A note_stores callback for which DATA points to an instruction pointer.
15416 If *DATA is nonnull, make it null if it X contains a MEM that is not
15417 safe from R10K speculation. */
15420 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
15423 rtx_insn
**insn_ptr
;
15425 insn_ptr
= (rtx_insn
**) data
;
15426 if (*insn_ptr
&& r10k_needs_protection_p_1 (x
, *insn_ptr
))
15430 /* X is the pattern of a call instruction. Return true if the call is
15431 not to a declared function. */
15434 r10k_needs_protection_p_call (const_rtx x
)
15436 subrtx_iterator::array_type array
;
15437 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
15439 const_rtx mem
= *iter
;
15442 const_rtx addr
= XEXP (mem
, 0);
15443 if (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_DECL (addr
))
15444 iter
.skip_subrtxes ();
15452 /* Return true if instruction INSN needs to be protected by an R10K
15456 r10k_needs_protection_p (rtx_insn
*insn
)
15459 return r10k_needs_protection_p_call (PATTERN (insn
));
15461 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
15463 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
15464 return insn
== NULL_RTX
;
15467 return r10k_needs_protection_p_1 (PATTERN (insn
), insn
);
15470 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15471 edge is unconditional. */
15474 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
15479 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
15480 if (!single_succ_p (e
->src
)
15481 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
15482 || (e
->flags
& EDGE_COMPLEX
) != 0)
15487 /* Implement -mr10k-cache-barrier= for the current function. */
15490 r10k_insert_cache_barriers (void)
15492 int *rev_post_order
;
15495 sbitmap protected_bbs
;
15496 rtx_insn
*insn
, *end
;
15497 rtx unprotected_region
;
15501 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15505 /* Calculate dominators. */
15506 calculate_dominance_info (CDI_DOMINATORS
);
15508 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15509 X is protected by a cache barrier. */
15510 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
15511 bitmap_clear (protected_bbs
);
15513 /* Iterate over the basic blocks in reverse post-order. */
15514 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
15515 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
15516 for (i
= 0; i
< n
; i
++)
15518 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
15520 /* If this block is only reached by unconditional edges, and if the
15521 source of every edge is protected, the beginning of the block is
15523 if (r10k_protected_bb_p (bb
, protected_bbs
))
15524 unprotected_region
= NULL_RTX
;
15526 unprotected_region
= pc_rtx
;
15527 end
= NEXT_INSN (BB_END (bb
));
15529 /* UNPROTECTED_REGION is:
15531 - null if we are processing a protected region,
15532 - pc_rtx if we are processing an unprotected region but have
15533 not yet found the first instruction in it
15534 - the first instruction in an unprotected region otherwise. */
15535 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
15537 if (unprotected_region
&& USEFUL_INSN_P (insn
))
15539 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
15540 /* This CACHE instruction protects the following code. */
15541 unprotected_region
= NULL_RTX
;
15544 /* See if INSN is the first instruction in this
15545 unprotected region. */
15546 if (unprotected_region
== pc_rtx
)
15547 unprotected_region
= insn
;
15549 /* See if INSN needs to be protected. If so,
15550 we must insert a cache barrier somewhere between
15551 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15552 clear which position is better performance-wise,
15553 but as a tie-breaker, we assume that it is better
15554 to allow delay slots to be back-filled where
15555 possible, and that it is better not to insert
15556 barriers in the middle of already-scheduled code.
15557 We therefore insert the barrier at the beginning
15559 if (r10k_needs_protection_p (insn
))
15561 emit_insn_before (gen_r10k_cache_barrier (),
15562 unprotected_region
);
15563 unprotected_region
= NULL_RTX
;
15569 /* The called function is not required to protect the exit path.
15570 The code that follows a call is therefore unprotected. */
15571 unprotected_region
= pc_rtx
;
15574 /* Record whether the end of this block is protected. */
15575 if (unprotected_region
== NULL_RTX
)
15576 bitmap_set_bit (protected_bbs
, bb
->index
);
15578 XDELETEVEC (rev_post_order
);
15580 sbitmap_free (protected_bbs
);
15582 free_dominance_info (CDI_DOMINATORS
);
15585 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15586 otherwise. If INSN has two call rtx, then store the second one in
15590 mips_call_expr_from_insn (rtx_insn
*insn
, rtx
*second_call
)
15595 if (!CALL_P (insn
))
15598 x
= PATTERN (insn
);
15599 if (GET_CODE (x
) == PARALLEL
)
15601 /* Calls returning complex values have two CALL rtx. Look for the second
15602 one here, and return it via the SECOND_CALL arg. */
15603 x2
= XVECEXP (x
, 0, 1);
15604 if (GET_CODE (x2
) == SET
)
15606 if (GET_CODE (x2
) == CALL
)
15609 x
= XVECEXP (x
, 0, 0);
15611 if (GET_CODE (x
) == SET
)
15613 gcc_assert (GET_CODE (x
) == CALL
);
15618 /* REG is set in DEF. See if the definition is one of the ways we load a
15619 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15620 If it is, return the symbol reference of the function, otherwise return
15623 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15624 the values of source registers, otherwise treat such registers as
15625 having an unknown value. */
15628 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
15630 rtx_insn
*def_insn
;
15633 if (DF_REF_IS_ARTIFICIAL (def
))
15636 def_insn
= DF_REF_INSN (def
);
15637 set
= single_set (def_insn
);
15638 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
15640 rtx note
, src
, symbol
;
15642 /* First see whether the source is a plain symbol. This is used
15643 when calling symbols that are not lazily bound. */
15644 src
= SET_SRC (set
);
15645 if (GET_CODE (src
) == SYMBOL_REF
)
15648 /* Handle %call16 references. */
15649 symbol
= mips_strip_unspec_call (src
);
15652 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15656 /* If we have something more complicated, look for a
15657 REG_EQUAL or REG_EQUIV note. */
15658 note
= find_reg_equal_equiv_note (def_insn
);
15659 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
15660 return XEXP (note
, 0);
15662 /* Follow at most one simple register copy. Such copies are
15663 interesting in cases like:
15667 locally_binding_fn (...);
15672 locally_binding_fn (...);
15674 locally_binding_fn (...);
15676 where the load of locally_binding_fn can legitimately be
15677 hoisted or shared. However, we do not expect to see complex
15678 chains of copies, so a full worklist solution to the problem
15679 would probably be overkill. */
15680 if (recurse_p
&& REG_P (src
))
15681 return mips_find_pic_call_symbol (def_insn
, src
, false);
15687 /* Find the definition of the use of REG in INSN. See if the definition
15688 is one of the ways we load a register with a symbol address for a
15689 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15690 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15691 mips_pic_call_symbol_from_set. */
15694 mips_find_pic_call_symbol (rtx_insn
*insn
, rtx reg
, bool recurse_p
)
15697 struct df_link
*defs
;
15700 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15703 defs
= DF_REF_CHAIN (use
);
15706 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15710 /* If we have more than one definition, they need to be identical. */
15711 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15715 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15716 if (!rtx_equal_p (symbol
, other
))
15723 /* Replace the args_size operand of the call expression CALL with the
15724 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15727 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15731 args_size
= XEXP (call
, 1);
15732 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15733 gen_rtvec (2, args_size
, symbol
),
15737 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15738 if instead of the arg_size argument it contains the call attributes. If
15739 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15740 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15744 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15746 rtx args_size
, symbol
;
15748 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15751 args_size
= operands
[args_size_opno
];
15752 if (GET_CODE (args_size
) != UNSPEC
)
15754 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15756 symbol
= XVECEXP (args_size
, 0, 1);
15757 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15759 operands
[args_size_opno
] = symbol
;
15763 /* Use DF to annotate PIC indirect calls with the function symbol they
15767 mips_annotate_pic_calls (void)
15772 FOR_EACH_BB_FN (bb
, cfun
)
15773 FOR_BB_INSNS (bb
, insn
)
15775 rtx call
, reg
, symbol
, second_call
;
15778 call
= mips_call_expr_from_insn (insn
, &second_call
);
15781 gcc_assert (MEM_P (XEXP (call
, 0)));
15782 reg
= XEXP (XEXP (call
, 0), 0);
15786 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15789 mips_annotate_pic_call_expr (call
, symbol
);
15791 mips_annotate_pic_call_expr (second_call
, symbol
);
15796 /* A temporary variable used by note_uses callbacks, etc. */
15797 static rtx_insn
*mips_sim_insn
;
15799 /* A structure representing the state of the processor pipeline.
15800 Used by the mips_sim_* family of functions. */
15802 /* The maximum number of instructions that can be issued in a cycle.
15803 (Caches mips_issue_rate.) */
15804 unsigned int issue_rate
;
15806 /* The current simulation time. */
15809 /* How many more instructions can be issued in the current cycle. */
15810 unsigned int insns_left
;
15812 /* LAST_SET[X].INSN is the last instruction to set register X.
15813 LAST_SET[X].TIME is the time at which that instruction was issued.
15814 INSN is null if no instruction has yet set register X. */
15818 } last_set
[FIRST_PSEUDO_REGISTER
];
15820 /* The pipeline's current DFA state. */
15824 /* Reset STATE to the initial simulation state. */
15827 mips_sim_reset (struct mips_sim
*state
)
15829 curr_state
= state
->dfa_state
;
15832 state
->insns_left
= state
->issue_rate
;
15833 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15834 state_reset (curr_state
);
15836 targetm
.sched
.init (0, false, 0);
15837 advance_state (curr_state
);
15840 /* Initialize STATE before its first use. DFA_STATE points to an
15841 allocated but uninitialized DFA state. */
15844 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15846 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15847 targetm
.sched
.init_dfa_pre_cycle_insn ();
15849 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15850 targetm
.sched
.init_dfa_post_cycle_insn ();
15852 state
->issue_rate
= mips_issue_rate ();
15853 state
->dfa_state
= dfa_state
;
15854 mips_sim_reset (state
);
15857 /* Advance STATE by one clock cycle. */
15860 mips_sim_next_cycle (struct mips_sim
*state
)
15862 curr_state
= state
->dfa_state
;
15865 state
->insns_left
= state
->issue_rate
;
15866 advance_state (curr_state
);
15869 /* Advance simulation state STATE until instruction INSN can read
15873 mips_sim_wait_reg (struct mips_sim
*state
, rtx_insn
*insn
, rtx reg
)
15875 unsigned int regno
, end_regno
;
15877 end_regno
= END_REGNO (reg
);
15878 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15879 if (state
->last_set
[regno
].insn
!= 0)
15883 t
= (state
->last_set
[regno
].time
15884 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15885 while (state
->time
< t
)
15886 mips_sim_next_cycle (state
);
15890 /* A note_uses callback. For each register in *X, advance simulation
15891 state DATA until mips_sim_insn can read the register's value. */
15894 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15896 subrtx_var_iterator::array_type array
;
15897 FOR_EACH_SUBRTX_VAR (iter
, array
, *x
, NONCONST
)
15899 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *iter
);
15902 /* Advance simulation state STATE until all of INSN's register
15903 dependencies are satisfied. */
15906 mips_sim_wait_regs (struct mips_sim
*state
, rtx_insn
*insn
)
15908 mips_sim_insn
= insn
;
15909 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15912 /* Advance simulation state STATE until the units required by
15913 instruction INSN are available. */
15916 mips_sim_wait_units (struct mips_sim
*state
, rtx_insn
*insn
)
15920 tmp_state
= alloca (state_size ());
15921 while (state
->insns_left
== 0
15922 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15923 state_transition (tmp_state
, insn
) >= 0))
15924 mips_sim_next_cycle (state
);
15927 /* Advance simulation state STATE until INSN is ready to issue. */
15930 mips_sim_wait_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15932 mips_sim_wait_regs (state
, insn
);
15933 mips_sim_wait_units (state
, insn
);
15936 /* mips_sim_insn has just set X. Update the LAST_SET array
15937 in simulation state DATA. */
15940 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15942 struct mips_sim
*state
;
15944 state
= (struct mips_sim
*) data
;
15947 unsigned int regno
, end_regno
;
15949 end_regno
= END_REGNO (x
);
15950 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15952 state
->last_set
[regno
].insn
= mips_sim_insn
;
15953 state
->last_set
[regno
].time
= state
->time
;
15958 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15959 can issue immediately (i.e., that mips_sim_wait_insn has already
15963 mips_sim_issue_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15965 curr_state
= state
->dfa_state
;
15967 state_transition (curr_state
, insn
);
15968 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15969 state
->insns_left
);
15971 mips_sim_insn
= insn
;
15972 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15975 /* Simulate issuing a NOP in state STATE. */
15978 mips_sim_issue_nop (struct mips_sim
*state
)
15980 if (state
->insns_left
== 0)
15981 mips_sim_next_cycle (state
);
15982 state
->insns_left
--;
15985 /* Update simulation state STATE so that it's ready to accept the instruction
15986 after INSN. INSN should be part of the main rtl chain, not a member of a
15990 mips_sim_finish_insn (struct mips_sim
*state
, rtx_insn
*insn
)
15992 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15994 mips_sim_issue_nop (state
);
15996 switch (GET_CODE (SEQ_BEGIN (insn
)))
16000 /* We can't predict the processor state after a call or label. */
16001 mips_sim_reset (state
);
16005 /* The delay slots of branch likely instructions are only executed
16006 when the branch is taken. Therefore, if the caller has simulated
16007 the delay slot instruction, STATE does not really reflect the state
16008 of the pipeline for the instruction after the delay slot. Also,
16009 branch likely instructions tend to incur a penalty when not taken,
16010 so there will probably be an extra delay between the branch and
16011 the instruction after the delay slot. */
16012 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
16013 mips_sim_reset (state
);
16021 /* Use simulator state STATE to calculate the execution time of
16022 instruction sequence SEQ. */
16024 static unsigned int
16025 mips_seq_time (struct mips_sim
*state
, rtx_insn
*seq
)
16027 mips_sim_reset (state
);
16028 for (rtx_insn
*insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
16030 mips_sim_wait_insn (state
, insn
);
16031 mips_sim_issue_insn (state
, insn
);
16033 return state
->time
;
16036 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
16037 setting SETTING, using STATE to simulate instruction sequences. */
16039 static unsigned int
16040 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
16042 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
16045 machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
16046 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
16047 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
16049 /* If the target provides mulsidi3_32bit then that's the most likely
16050 consumer of the result. Test for bypasses. */
16051 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
16053 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
16054 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
16057 unsigned int time
= mips_seq_time (state
, get_insns ());
16062 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
16063 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
16064 Prefer MULT -- which is shorter -- in the event of a tie. */
16067 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
16069 if (TARGET_MIPS16
|| !ISA_HAS_HILO
)
16070 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO
16071 registers then there is no reason to zero them, arbitrarily choose to
16072 say that "MULT $0,$0" would be faster. */
16073 mips_tuning_info
.fast_mult_zero_zero_p
= true;
16076 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
16077 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
16078 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
16082 /* Set up costs based on the current architecture and tuning settings. */
16085 mips_set_tuning_info (void)
16087 if (mips_tuning_info
.initialized_p
16088 && mips_tuning_info
.arch
== mips_arch
16089 && mips_tuning_info
.tune
== mips_tune
16090 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
16093 mips_tuning_info
.arch
= mips_arch
;
16094 mips_tuning_info
.tune
= mips_tune
;
16095 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
16096 mips_tuning_info
.initialized_p
= true;
16100 struct mips_sim state
;
16101 mips_sim_init (&state
, alloca (state_size ()));
16103 mips_set_fast_mult_zero_zero_p (&state
);
16108 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
16111 mips_expand_to_rtl_hook (void)
16113 /* We need to call this at a point where we can safely create sequences
16114 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
16115 need to call it at a point where the DFA infrastructure is not
16116 already in use, so we can't just call it lazily on demand.
16118 At present, mips_tuning_info is only needed during post-expand
16119 RTL passes such as split_insns, so this hook should be early enough.
16120 We may need to move the call elsewhere if mips_tuning_info starts
16121 to be used for other things (such as rtx_costs, or expanders that
16122 could be called during gimple optimization). */
16123 mips_set_tuning_info ();
16126 /* The VR4130 pipeline issues aligned pairs of instructions together,
16127 but it stalls the second instruction if it depends on the first.
16128 In order to cut down the amount of logic required, this dependence
16129 check is not based on a full instruction decode. Instead, any non-SPECIAL
16130 instruction is assumed to modify the register specified by bits 20-16
16131 (which is usually the "rt" field).
16133 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
16134 input, so we can end up with a false dependence between the branch
16135 and its delay slot. If this situation occurs in instruction INSN,
16136 try to avoid it by swapping rs and rt. */
16139 vr4130_avoid_branch_rt_conflict (rtx_insn
*insn
)
16141 rtx_insn
*first
, *second
;
16143 first
= SEQ_BEGIN (insn
);
16144 second
= SEQ_END (insn
);
16146 && NONJUMP_INSN_P (second
)
16147 && GET_CODE (PATTERN (first
)) == SET
16148 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
16149 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
16151 /* Check for the right kind of condition. */
16152 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
16153 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
16154 && REG_P (XEXP (cond
, 0))
16155 && REG_P (XEXP (cond
, 1))
16156 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
16157 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
16159 /* SECOND mentions the rt register but not the rs register. */
16160 rtx tmp
= XEXP (cond
, 0);
16161 XEXP (cond
, 0) = XEXP (cond
, 1);
16162 XEXP (cond
, 1) = tmp
;
16167 /* Implement -mvr4130-align. Go through each basic block and simulate the
16168 processor pipeline. If we find that a pair of instructions could execute
16169 in parallel, and the first of those instructions is not 8-byte aligned,
16170 insert a nop to make it aligned. */
16173 vr4130_align_insns (void)
16175 struct mips_sim state
;
16176 rtx_insn
*insn
, *subinsn
, *last
, *last2
, *next
;
16181 /* LAST is the last instruction before INSN to have a nonzero length.
16182 LAST2 is the last such instruction before LAST. */
16186 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
16189 mips_sim_init (&state
, alloca (state_size ()));
16190 for (insn
= get_insns (); insn
!= 0; insn
= next
)
16192 unsigned int length
;
16194 next
= NEXT_INSN (insn
);
16196 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
16197 This isn't really related to the alignment pass, but we do it on
16198 the fly to avoid a separate instruction walk. */
16199 vr4130_avoid_branch_rt_conflict (insn
);
16201 length
= get_attr_length (insn
);
16202 if (length
> 0 && USEFUL_INSN_P (insn
))
16203 FOR_EACH_SUBINSN (subinsn
, insn
)
16205 mips_sim_wait_insn (&state
, subinsn
);
16207 /* If we want this instruction to issue in parallel with the
16208 previous one, make sure that the previous instruction is
16209 aligned. There are several reasons why this isn't worthwhile
16210 when the second instruction is a call:
16212 - Calls are less likely to be performance critical,
16213 - There's a good chance that the delay slot can execute
16214 in parallel with the call.
16215 - The return address would then be unaligned.
16217 In general, if we're going to insert a nop between instructions
16218 X and Y, it's better to insert it immediately after X. That
16219 way, if the nop makes Y aligned, it will also align any labels
16220 between X and Y. */
16221 if (state
.insns_left
!= state
.issue_rate
16222 && !CALL_P (subinsn
))
16224 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
16226 /* SUBINSN is the first instruction in INSN and INSN is
16227 aligned. We want to align the previous instruction
16228 instead, so insert a nop between LAST2 and LAST.
16230 Note that LAST could be either a single instruction
16231 or a branch with a delay slot. In the latter case,
16232 LAST, like INSN, is already aligned, but the delay
16233 slot must have some extra delay that stops it from
16234 issuing at the same time as the branch. We therefore
16235 insert a nop before the branch in order to align its
16237 gcc_assert (last2
);
16238 emit_insn_after (gen_nop (), last2
);
16241 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
16243 /* SUBINSN is the delay slot of INSN, but INSN is
16244 currently unaligned. Insert a nop between
16245 LAST and INSN to align it. */
16247 emit_insn_after (gen_nop (), last
);
16251 mips_sim_issue_insn (&state
, subinsn
);
16253 mips_sim_finish_insn (&state
, insn
);
16255 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
16256 length
= get_attr_length (insn
);
16259 /* If the instruction is an asm statement or multi-instruction
16260 mips.md patern, the length is only an estimate. Insert an
16261 8 byte alignment after it so that the following instructions
16262 can be handled correctly. */
16263 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
16264 && (recog_memoized (insn
) < 0 || length
>= 8))
16266 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
16267 next
= NEXT_INSN (next
);
16268 mips_sim_next_cycle (&state
);
16271 else if (length
& 4)
16272 aligned_p
= !aligned_p
;
16277 /* See whether INSN is an aligned label. */
16278 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
16284 /* This structure records that the current function has a LO_SUM
16285 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
16286 the largest offset applied to BASE by all such LO_SUMs. */
16287 struct mips_lo_sum_offset
{
16289 HOST_WIDE_INT offset
;
16292 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
16295 mips_hash_base (rtx base
)
16297 int do_not_record_p
;
16299 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
16302 /* Hashtable helpers. */
16304 struct mips_lo_sum_offset_hasher
: free_ptr_hash
<mips_lo_sum_offset
>
16306 typedef rtx_def
*compare_type
;
16307 static inline hashval_t
hash (const mips_lo_sum_offset
*);
16308 static inline bool equal (const mips_lo_sum_offset
*, const rtx_def
*);
16311 /* Hash-table callbacks for mips_lo_sum_offsets. */
16314 mips_lo_sum_offset_hasher::hash (const mips_lo_sum_offset
*entry
)
16316 return mips_hash_base (entry
->base
);
16320 mips_lo_sum_offset_hasher::equal (const mips_lo_sum_offset
*entry
,
16321 const rtx_def
*value
)
16323 return rtx_equal_p (entry
->base
, value
);
16326 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
16328 /* Look up symbolic constant X in HTAB, which is a hash table of
16329 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16330 paired with a recorded LO_SUM, otherwise record X in the table. */
16333 mips_lo_sum_offset_lookup (mips_offset_table
*htab
, rtx x
,
16334 enum insert_option option
)
16337 mips_lo_sum_offset
**slot
;
16338 struct mips_lo_sum_offset
*entry
;
16340 /* Split X into a base and offset. */
16341 split_const (x
, &base
, &offset
);
16342 if (UNSPEC_ADDRESS_P (base
))
16343 base
= UNSPEC_ADDRESS (base
);
16345 /* Look up the base in the hash table. */
16346 slot
= htab
->find_slot_with_hash (base
, mips_hash_base (base
), option
);
16350 entry
= (struct mips_lo_sum_offset
*) *slot
;
16351 if (option
== INSERT
)
16355 entry
= XNEW (struct mips_lo_sum_offset
);
16356 entry
->base
= base
;
16357 entry
->offset
= INTVAL (offset
);
16362 if (INTVAL (offset
) > entry
->offset
)
16363 entry
->offset
= INTVAL (offset
);
16366 return INTVAL (offset
) <= entry
->offset
;
16369 /* Search X for LO_SUMs and record them in HTAB. */
16372 mips_record_lo_sums (const_rtx x
, mips_offset_table
*htab
)
16374 subrtx_iterator::array_type array
;
16375 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
16376 if (GET_CODE (*iter
) == LO_SUM
)
16377 mips_lo_sum_offset_lookup (htab
, XEXP (*iter
, 1), INSERT
);
16380 /* Return true if INSN is a SET of an orphaned high-part relocation.
16381 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16382 LO_SUMs in the current function. */
16385 mips_orphaned_high_part_p (mips_offset_table
*htab
, rtx_insn
*insn
)
16387 enum mips_symbol_type type
;
16390 set
= single_set (insn
);
16393 /* Check for %his. */
16395 if (GET_CODE (x
) == HIGH
16396 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
16397 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
16399 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16400 if (GET_CODE (x
) == UNSPEC
16401 && XINT (x
, 1) == UNSPEC_LOAD_GOT
16402 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
16403 SYMBOL_CONTEXT_LEA
, &type
)
16404 && type
== SYMBOL_GOTOFF_PAGE
)
16405 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
16410 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16411 INSN and a previous instruction, avoid it by inserting nops after
16414 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16415 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16416 before using the value of that register. *HILO_DELAY counts the
16417 number of instructions since the last hilo hazard (that is,
16418 the number of instructions since the last MFLO or MFHI).
16420 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16421 for the next instruction.
16423 LO_REG is an rtx for the LO register, used in dependence checking. */
16426 mips_avoid_hazard (rtx_insn
*after
, rtx_insn
*insn
, int *hilo_delay
,
16427 rtx
*delayed_reg
, rtx lo_reg
)
16432 pattern
= PATTERN (insn
);
16434 /* Do not put the whole function in .set noreorder if it contains
16435 an asm statement. We don't know whether there will be hazards
16436 between the asm statement and the gcc-generated code. */
16437 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
16438 cfun
->machine
->all_noreorder_p
= false;
16440 /* Ignore zero-length instructions (barriers and the like). */
16441 ninsns
= get_attr_length (insn
) / 4;
16445 /* Work out how many nops are needed. Note that we only care about
16446 registers that are explicitly mentioned in the instruction's pattern.
16447 It doesn't matter that calls use the argument registers or that they
16448 clobber hi and lo. */
16449 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
16450 nops
= 2 - *hilo_delay
;
16451 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
16456 /* Insert the nops between this instruction and the previous one.
16457 Each new nop takes us further from the last hilo hazard. */
16458 *hilo_delay
+= nops
;
16460 emit_insn_after (gen_hazard_nop (), after
);
16462 /* Set up the state for the next instruction. */
16463 *hilo_delay
+= ninsns
;
16465 if (INSN_CODE (insn
) >= 0)
16466 switch (get_attr_hazard (insn
))
16476 set
= single_set (insn
);
16478 *delayed_reg
= SET_DEST (set
);
16483 /* Go through the instruction stream and insert nops where necessary.
16484 Also delete any high-part relocations whose partnering low parts
16485 are now all dead. See if the whole function can then be put into
16486 .set noreorder and .set nomacro. */
16489 mips_reorg_process_insns (void)
16491 rtx_insn
*insn
, *last_insn
, *subinsn
, *next_insn
;
16492 rtx lo_reg
, delayed_reg
;
16495 /* Force all instructions to be split into their final form. */
16496 split_all_insns_noflow ();
16498 /* Recalculate instruction lengths without taking nops into account. */
16499 cfun
->machine
->ignore_hazard_length_p
= true;
16500 shorten_branches (get_insns ());
16502 cfun
->machine
->all_noreorder_p
= true;
16504 /* We don't track MIPS16 PC-relative offsets closely enough to make
16505 a good job of "set .noreorder" code in MIPS16 mode. */
16507 cfun
->machine
->all_noreorder_p
= false;
16509 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16510 if (!TARGET_EXPLICIT_RELOCS
)
16511 cfun
->machine
->all_noreorder_p
= false;
16513 /* Profiled functions can't be all noreorder because the profiler
16514 support uses assembler macros. */
16516 cfun
->machine
->all_noreorder_p
= false;
16518 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16519 all noreorder because we rely on the assembler to work around some
16520 errata. The R5900 too has several bugs. */
16521 if (TARGET_FIX_VR4120
16522 || TARGET_FIX_RM7000
16524 || TARGET_MIPS5900
)
16525 cfun
->machine
->all_noreorder_p
= false;
16527 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16528 MFHI instructions. Note that we avoid using MFLO and MFHI if
16529 the VR4130 MACC and DMACC instructions are available instead;
16530 see the *mfhilo_{si,di}_macc patterns. */
16531 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
16532 cfun
->machine
->all_noreorder_p
= false;
16534 mips_offset_table
htab (37);
16536 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16537 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
16538 FOR_EACH_SUBINSN (subinsn
, insn
)
16539 if (USEFUL_INSN_P (subinsn
))
16541 rtx body
= PATTERN (insn
);
16542 int noperands
= asm_noperands (body
);
16543 if (noperands
>= 0)
16545 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
16546 bool *used
= XALLOCAVEC (bool, noperands
);
16547 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
16549 get_referenced_operands (string
, used
, noperands
);
16550 for (int i
= 0; i
< noperands
; ++i
)
16552 mips_record_lo_sums (ops
[i
], &htab
);
16555 mips_record_lo_sums (PATTERN (subinsn
), &htab
);
16561 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
16563 /* Make a second pass over the instructions. Delete orphaned
16564 high-part relocations or turn them into NOPs. Avoid hazards
16565 by inserting NOPs. */
16566 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
16568 next_insn
= NEXT_INSN (insn
);
16569 if (USEFUL_INSN_P (insn
))
16571 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
16573 /* If we find an orphaned high-part relocation in a delay
16574 slot, it's easier to turn that instruction into a NOP than
16575 to delete it. The delay slot will be a NOP either way. */
16576 FOR_EACH_SUBINSN (subinsn
, insn
)
16577 if (INSN_P (subinsn
))
16579 if (mips_orphaned_high_part_p (&htab
, subinsn
))
16581 PATTERN (subinsn
) = gen_nop ();
16582 INSN_CODE (subinsn
) = CODE_FOR_nop
;
16584 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
16585 &delayed_reg
, lo_reg
);
16591 /* INSN is a single instruction. Delete it if it's an
16592 orphaned high-part relocation. */
16593 if (mips_orphaned_high_part_p (&htab
, insn
))
16594 delete_insn (insn
);
16595 /* Also delete cache barriers if the last instruction
16596 was an annulled branch. INSN will not be speculatively
16598 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
16600 && JUMP_P (SEQ_BEGIN (last_insn
))
16601 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
16602 delete_insn (insn
);
16605 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
16606 &delayed_reg
, lo_reg
);
16614 /* Return true if the function has a long branch instruction. */
16617 mips_has_long_branch_p (void)
16619 rtx_insn
*insn
, *subinsn
;
16622 /* We need up-to-date instruction lengths. */
16623 shorten_branches (get_insns ());
16625 /* Look for a branch that is longer than normal. The normal length for
16626 non-MIPS16 branches is 8, because the length includes the delay slot.
16627 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16628 but they have no delay slot. */
16629 normal_length
= (TARGET_MIPS16
? 4 : 8);
16630 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16631 FOR_EACH_SUBINSN (subinsn
, insn
)
16632 if (JUMP_P (subinsn
)
16633 && get_attr_length (subinsn
) > normal_length
16634 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
16640 /* If we are using a GOT, but have not decided to use a global pointer yet,
16641 see whether we need one to implement long branches. Convert the ghost
16642 global-pointer instructions into real ones if so. */
16645 mips_expand_ghost_gp_insns (void)
16647 /* Quick exit if we already know that we will or won't need a
16649 if (!TARGET_USE_GOT
16650 || cfun
->machine
->global_pointer
== INVALID_REGNUM
16651 || mips_must_initialize_gp_p ())
16654 /* Run a full check for long branches. */
16655 if (!mips_has_long_branch_p ())
16658 /* We've now established that we need $gp. */
16659 cfun
->machine
->must_initialize_gp_p
= true;
16660 split_all_insns_noflow ();
16665 /* Subroutine of mips_reorg to manage passes that require DF. */
16668 mips_df_reorg (void)
16670 /* Create def-use chains. */
16671 df_set_flags (DF_EQ_NOTES
);
16672 df_chain_add_problem (DF_UD_CHAIN
);
16675 if (TARGET_RELAX_PIC_CALLS
)
16676 mips_annotate_pic_calls ();
16678 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
16679 r10k_insert_cache_barriers ();
16681 df_finish_pass (false);
16684 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16685 called very late in mips_reorg, but the caller is required to run
16686 mips16_lay_out_constants on the result. */
16689 mips16_load_branch_target (rtx dest
, rtx src
)
16691 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
16695 if (mips_cfun_has_cprestore_slot_p ())
16696 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
16698 mips_emit_move (dest
, pic_offset_table_rtx
);
16699 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
16700 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
16701 emit_insn (gen_rtx_SET (dest
,
16702 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
16703 emit_insn (gen_rtx_SET (dest
, gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16707 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16708 mips_emit_move (dest
, src
);
16712 /* If we're compiling a MIPS16 function, look for and split any long branches.
16713 This must be called after all other instruction modifications in
16717 mips16_split_long_branches (void)
16719 bool something_changed
;
16721 if (!TARGET_MIPS16
)
16724 /* Loop until the alignments for all targets are sufficient. */
16728 rtx_jump_insn
*jump_insn
;
16730 shorten_branches (get_insns ());
16731 something_changed
= false;
16732 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16733 if ((jump_insn
= dyn_cast
<rtx_jump_insn
*> (insn
))
16734 && get_attr_length (jump_insn
) > 4
16735 && (any_condjump_p (jump_insn
) || any_uncondjump_p (jump_insn
)))
16737 rtx old_label
, temp
, saved_temp
;
16738 rtx_code_label
*new_label
;
16740 rtx_insn
*jump
, *jump_sequence
;
16744 /* Free up a MIPS16 register by saving it in $1. */
16745 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16746 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16747 emit_move_insn (saved_temp
, temp
);
16749 /* Load the branch target into TEMP. */
16750 old_label
= JUMP_LABEL (jump_insn
);
16751 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16752 mips16_load_branch_target (temp
, target
);
16754 /* Jump to the target and restore the register's
16756 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16757 (temp
, temp
, saved_temp
)));
16758 JUMP_LABEL (jump
) = old_label
;
16759 LABEL_NUSES (old_label
)++;
16761 /* Rewrite any symbolic references that are supposed to use
16762 a PC-relative constant pool. */
16763 mips16_lay_out_constants (false);
16765 if (simplejump_p (jump_insn
))
16766 /* We're going to replace INSN with a longer form. */
16770 /* Create a branch-around label for the original
16772 new_label
= gen_label_rtx ();
16773 emit_label (new_label
);
16776 jump_sequence
= get_insns ();
16779 emit_insn_after (jump_sequence
, jump_insn
);
16781 invert_jump (jump_insn
, new_label
, false);
16783 delete_insn (jump_insn
);
16784 something_changed
= true;
16787 while (something_changed
);
16790 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16795 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16796 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16797 to date if the CFG is available. */
16798 if (mips_cfg_in_reorg ())
16799 compute_bb_for_insn ();
16800 mips16_lay_out_constants (true);
16801 if (mips_cfg_in_reorg ())
16804 free_bb_for_insn ();
16808 /* We use a machine specific pass to do a second machine dependent reorg
16809 pass after delay branch scheduling. */
16811 static unsigned int
16812 mips_machine_reorg2 (void)
16814 mips_reorg_process_insns ();
16816 && TARGET_EXPLICIT_RELOCS
16818 && TARGET_VR4130_ALIGN
)
16819 vr4130_align_insns ();
16820 if (mips_expand_ghost_gp_insns ())
16821 /* The expansion could invalidate some of the VR4130 alignment
16822 optimizations, but this should be an extremely rare case anyhow. */
16823 mips_reorg_process_insns ();
16824 mips16_split_long_branches ();
16830 const pass_data pass_data_mips_machine_reorg2
=
16832 RTL_PASS
, /* type */
16833 "mach2", /* name */
16834 OPTGROUP_NONE
, /* optinfo_flags */
16835 TV_MACH_DEP
, /* tv_id */
16836 0, /* properties_required */
16837 0, /* properties_provided */
16838 0, /* properties_destroyed */
16839 0, /* todo_flags_start */
16840 0, /* todo_flags_finish */
16843 class pass_mips_machine_reorg2
: public rtl_opt_pass
16846 pass_mips_machine_reorg2(gcc::context
*ctxt
)
16847 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
16850 /* opt_pass methods: */
16851 virtual unsigned int execute (function
*) { return mips_machine_reorg2 (); }
16853 }; // class pass_mips_machine_reorg2
16855 } // anon namespace
16858 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
16860 return new pass_mips_machine_reorg2 (ctxt
);
16864 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16865 in order to avoid duplicating too much logic from elsewhere. */
16868 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16869 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16872 rtx this_rtx
, temp1
, temp2
, fnaddr
;
16874 bool use_sibcall_p
;
16876 /* Pretend to be a post-reload pass while generating rtl. */
16877 reload_completed
= 1;
16879 /* Mark the end of the (empty) prologue. */
16880 emit_note (NOTE_INSN_PROLOGUE_END
);
16882 /* Determine if we can use a sibcall to call FUNCTION directly. */
16883 fnaddr
= XEXP (DECL_RTL (function
), 0);
16884 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16885 && const_call_insn_operand (fnaddr
, Pmode
));
16887 /* Determine if we need to load FNADDR from the GOT. */
16889 && (mips_got_symbol_type_p
16890 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16892 /* Pick a global pointer. Use a call-clobbered register if
16893 TARGET_CALL_SAVED_GP. */
16894 cfun
->machine
->global_pointer
16895 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16896 cfun
->machine
->must_initialize_gp_p
= true;
16897 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16899 /* Set up the global pointer for n32 or n64 abicalls. */
16900 mips_emit_loadgp ();
16903 /* We need two temporary registers in some cases. */
16904 temp1
= gen_rtx_REG (Pmode
, 2);
16905 temp2
= gen_rtx_REG (Pmode
, 3);
16907 /* Find out which register contains the "this" pointer. */
16908 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16909 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16911 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16913 /* Add DELTA to THIS_RTX. */
16916 rtx offset
= GEN_INT (delta
);
16917 if (!SMALL_OPERAND (delta
))
16919 mips_emit_move (temp1
, offset
);
16922 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16925 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16926 if (vcall_offset
!= 0)
16930 /* Set TEMP1 to *THIS_RTX. */
16931 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16933 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16934 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16936 /* Load the offset and add it to THIS_RTX. */
16937 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16938 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16941 /* Jump to the target function. Use a sibcall if direct jumps are
16942 allowed, otherwise load the address into a register first. */
16945 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16946 SIBLING_CALL_P (insn
) = 1;
16950 /* This is messy. GAS treats "la $25,foo" as part of a call
16951 sequence and may allow a global "foo" to be lazily bound.
16952 The general move patterns therefore reject this combination.
16954 In this context, lazy binding would actually be OK
16955 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16956 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16957 We must therefore load the address via a temporary
16958 register if mips_dangerous_for_la25_p.
16960 If we jump to the temporary register rather than $25,
16961 the assembler can use the move insn to fill the jump's
16964 We can use the same technique for MIPS16 code, where $25
16965 is not a valid JR register. */
16966 if (TARGET_USE_PIC_FN_ADDR_REG
16968 && !mips_dangerous_for_la25_p (fnaddr
))
16969 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16970 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16972 if (TARGET_USE_PIC_FN_ADDR_REG
16973 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16974 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16975 emit_jump_insn (gen_indirect_jump (temp1
));
16978 /* Run just enough of rest_of_compilation. This sequence was
16979 "borrowed" from alpha.c. */
16980 insn
= get_insns ();
16981 split_all_insns_noflow ();
16982 mips16_lay_out_constants (true);
16983 shorten_branches (insn
);
16984 final_start_function (insn
, file
, 1);
16985 final (insn
, file
, 1);
16986 final_end_function ();
16988 /* Clean up the vars set above. Note that final_end_function resets
16989 the global pointer for us. */
16990 reload_completed
= 0;
16994 /* The last argument passed to mips_set_compression_mode,
16995 or negative if the function hasn't been called yet. */
16996 static unsigned int old_compression_mode
= -1;
16998 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16999 which is either MASK_MIPS16 or MASK_MICROMIPS. */
17002 mips_set_compression_mode (unsigned int compression_mode
)
17005 if (compression_mode
== old_compression_mode
)
17008 /* Restore base settings of various flags. */
17009 target_flags
= mips_base_target_flags
;
17010 flag_schedule_insns
= mips_base_schedule_insns
;
17011 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
17012 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
17013 align_loops
= mips_base_align_loops
;
17014 align_jumps
= mips_base_align_jumps
;
17015 align_functions
= mips_base_align_functions
;
17016 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
17017 target_flags
|= compression_mode
;
17019 if (compression_mode
& MASK_MIPS16
)
17021 /* Switch to MIPS16 mode. */
17022 target_flags
|= MASK_MIPS16
;
17024 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
17025 target_flags
&= ~MASK_SYNCI
;
17027 /* Don't run the scheduler before reload, since it tends to
17028 increase register pressure. */
17029 flag_schedule_insns
= 0;
17031 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
17032 the whole function to be in a single section. */
17033 flag_reorder_blocks_and_partition
= 0;
17035 /* Don't move loop invariants, because it tends to increase
17036 register pressure. It also introduces an extra move in cases
17037 where the constant is the first operand in a two-operand binary
17038 instruction, or when it forms a register argument to a functon
17040 flag_move_loop_invariants
= 0;
17042 target_flags
|= MASK_EXPLICIT_RELOCS
;
17044 /* Experiments suggest we get the best overall section-anchor
17045 results from using the range of an unextended LW or SW. Code
17046 that makes heavy use of byte or short accesses can do better
17047 with ranges of 0...31 and 0...63 respectively, but most code is
17048 sensitive to the range of LW and SW instead. */
17049 targetm
.min_anchor_offset
= 0;
17050 targetm
.max_anchor_offset
= 127;
17052 targetm
.const_anchor
= 0;
17054 /* MIPS16 has no BAL instruction. */
17055 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17057 /* The R4000 errata don't apply to any known MIPS16 cores.
17058 It's simpler to make the R4000 fixes and MIPS16 mode
17059 mutually exclusive. */
17060 target_flags
&= ~MASK_FIX_R4000
;
17062 if (flag_pic
&& !TARGET_OLDABI
)
17063 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
17066 sorry ("MIPS16 -mxgot code");
17068 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
17069 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
17073 /* Switch to microMIPS or the standard encoding. */
17075 if (TARGET_MICROMIPS
)
17076 /* Avoid branch likely. */
17077 target_flags
&= ~MASK_BRANCHLIKELY
;
17079 /* Provide default values for align_* for 64-bit targets. */
17082 if (align_loops
== 0)
17084 if (align_jumps
== 0)
17086 if (align_functions
== 0)
17087 align_functions
= 8;
17090 targetm
.min_anchor_offset
= -32768;
17091 targetm
.max_anchor_offset
= 32767;
17093 targetm
.const_anchor
= 0x8000;
17096 /* (Re)initialize MIPS target internals for new ISA. */
17097 mips_init_relocs ();
17099 if (compression_mode
& MASK_MIPS16
)
17101 if (!mips16_globals
)
17102 mips16_globals
= save_target_globals_default_opts ();
17104 restore_target_globals (mips16_globals
);
17106 else if (compression_mode
& MASK_MICROMIPS
)
17108 if (!micromips_globals
)
17109 micromips_globals
= save_target_globals_default_opts ();
17111 restore_target_globals (micromips_globals
);
17114 restore_target_globals (&default_target_globals
);
17116 old_compression_mode
= compression_mode
;
17119 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
17120 function should use the MIPS16 or microMIPS ISA and switch modes
17124 mips_set_current_function (tree fndecl
)
17126 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
17129 /* Allocate a chunk of memory for per-function machine-dependent data. */
17131 static struct machine_function
*
17132 mips_init_machine_status (void)
17134 return ggc_cleared_alloc
<machine_function
> ();
17137 /* Return the processor associated with the given ISA level, or null
17138 if the ISA isn't valid. */
17140 static const struct mips_cpu_info
*
17141 mips_cpu_info_from_isa (int isa
)
17145 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
17146 if (mips_cpu_info_table
[i
].isa
== isa
)
17147 return mips_cpu_info_table
+ i
;
17152 /* Return a mips_cpu_info entry determined by an option valued
17155 static const struct mips_cpu_info
*
17156 mips_cpu_info_from_opt (int opt
)
17160 case MIPS_ARCH_OPTION_FROM_ABI
:
17161 /* 'from-abi' selects the most compatible architecture for the
17162 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
17163 ABIs. For the EABIs, we have to decide whether we're using
17164 the 32-bit or 64-bit version. */
17165 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
17166 : ABI_NEEDS_64BIT_REGS
? 3
17167 : (TARGET_64BIT
? 3 : 1));
17169 case MIPS_ARCH_OPTION_NATIVE
:
17170 gcc_unreachable ();
17173 return &mips_cpu_info_table
[opt
];
17177 /* Return a default mips_cpu_info entry, given that no -march= option
17178 was explicitly specified. */
17180 static const struct mips_cpu_info
*
17181 mips_default_arch (void)
17183 #if defined (MIPS_CPU_STRING_DEFAULT)
17185 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
17186 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
17187 return mips_cpu_info_table
+ i
;
17188 gcc_unreachable ();
17189 #elif defined (MIPS_ISA_DEFAULT)
17190 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
17192 /* 'from-abi' makes a good default: you get whatever the ABI
17194 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
17198 /* Set up globals to generate code for the ISA or processor
17199 described by INFO. */
17202 mips_set_architecture (const struct mips_cpu_info
*info
)
17206 mips_arch_info
= info
;
17207 mips_arch
= info
->cpu
;
17208 mips_isa
= info
->isa
;
17212 mips_isa_rev
= (mips_isa
& 31) + 1;
17216 /* Likewise for tuning. */
17219 mips_set_tune (const struct mips_cpu_info
*info
)
17223 mips_tune_info
= info
;
17224 mips_tune
= info
->cpu
;
17228 /* Implement TARGET_OPTION_OVERRIDE. */
17231 mips_option_override (void)
17233 int i
, start
, regno
, mode
;
17235 if (global_options_set
.x_mips_isa_option
)
17236 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
17238 #ifdef SUBTARGET_OVERRIDE_OPTIONS
17239 SUBTARGET_OVERRIDE_OPTIONS
;
17242 /* MIPS16 and microMIPS cannot coexist. */
17243 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
17244 error ("unsupported combination: %s", "-mips16 -mmicromips");
17246 /* Save the base compression state and process flags as though we
17247 were generating uncompressed code. */
17248 mips_base_compression_flags
= TARGET_COMPRESSION
;
17249 target_flags
&= ~TARGET_COMPRESSION
;
17251 /* -mno-float overrides -mhard-float and -msoft-float. */
17252 if (TARGET_NO_FLOAT
)
17254 target_flags
|= MASK_SOFT_FLOAT_ABI
;
17255 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
17258 if (TARGET_FLIP_MIPS16
)
17259 TARGET_INTERLINK_COMPRESSED
= 1;
17261 /* Set the small data limit. */
17262 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
17264 : MIPS_DEFAULT_GVALUE
);
17266 /* The following code determines the architecture and register size.
17267 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
17268 The GAS and GCC code should be kept in sync as much as possible. */
17270 if (global_options_set
.x_mips_arch_option
)
17271 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
17273 if (mips_isa_option_info
!= 0)
17275 if (mips_arch_info
== 0)
17276 mips_set_architecture (mips_isa_option_info
);
17277 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
17278 error ("%<-%s%> conflicts with the other architecture options, "
17279 "which specify a %s processor",
17280 mips_isa_option_info
->name
,
17281 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
17284 if (mips_arch_info
== 0)
17285 mips_set_architecture (mips_default_arch ());
17287 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
17288 error ("%<-march=%s%> is not compatible with the selected ABI",
17289 mips_arch_info
->name
);
17291 /* Optimize for mips_arch, unless -mtune selects a different processor. */
17292 if (global_options_set
.x_mips_tune_option
)
17293 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
17295 if (mips_tune_info
== 0)
17296 mips_set_tune (mips_arch_info
);
17298 if ((target_flags_explicit
& MASK_64BIT
) != 0)
17300 /* The user specified the size of the integer registers. Make sure
17301 it agrees with the ABI and ISA. */
17302 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
17303 error ("%<-mgp64%> used with a 32-bit processor");
17304 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
17305 error ("%<-mgp32%> used with a 64-bit ABI");
17306 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
17307 error ("%<-mgp64%> used with a 32-bit ABI");
17311 /* Infer the integer register size from the ABI and processor.
17312 Restrict ourselves to 32-bit registers if that's all the
17313 processor has, or if the ABI cannot handle 64-bit registers. */
17314 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
17315 target_flags
&= ~MASK_64BIT
;
17317 target_flags
|= MASK_64BIT
;
17320 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
17322 if (mips_isa_rev
>= 6 && !TARGET_FLOAT64
)
17323 error ("the %qs architecture does not support %<-mfp32%>",
17324 mips_arch_info
->name
);
17325 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
17326 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17327 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
17328 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17329 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
17331 if (!ISA_HAS_MXHC1
)
17332 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17333 " the target supports the mfhc1 and mthc1 instructions");
17334 else if (mips_abi
!= ABI_32
)
17335 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17341 /* -msingle-float selects 32-bit float registers. On r6 and later,
17342 -mdouble-float selects 64-bit float registers, since the old paired
17343 register model is not supported. In other cases the float registers
17344 should be the same size as the integer ones. */
17345 if (mips_isa_rev
>= 6 && TARGET_DOUBLE_FLOAT
&& !TARGET_FLOATXX
)
17346 target_flags
|= MASK_FLOAT64
;
17347 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
17348 target_flags
|= MASK_FLOAT64
;
17350 target_flags
&= ~MASK_FLOAT64
;
17353 if (mips_abi
!= ABI_32
&& TARGET_FLOATXX
)
17354 error ("%<-mfpxx%> can only be used with the o32 ABI");
17355 else if (TARGET_FLOAT64
&& TARGET_FLOATXX
)
17356 error ("unsupported combination: %s", "-mfp64 -mfpxx");
17357 else if (ISA_MIPS1
&& !TARGET_FLOAT32
)
17358 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info
->name
);
17359 else if (TARGET_FLOATXX
&& !mips_lra_flag
)
17360 error ("%<-mfpxx%> requires %<-mlra%>");
17362 /* End of code shared with GAS. */
17364 /* The R5900 FPU only supports single precision. */
17365 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
17366 error ("unsupported combination: %s",
17367 "-march=r5900 -mhard-float -mdouble-float");
17369 /* If a -mlong* option was given, check that it matches the ABI,
17370 otherwise infer the -mlong* setting from the other options. */
17371 if ((target_flags_explicit
& MASK_LONG64
) != 0)
17375 if (mips_abi
== ABI_N32
)
17376 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17377 else if (mips_abi
== ABI_32
)
17378 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17379 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
17380 /* We have traditionally allowed non-abicalls code to use
17381 an LP64 form of o64. However, it would take a bit more
17382 effort to support the combination of 32-bit GOT entries
17383 and 64-bit pointers, so we treat the abicalls case as
17385 error ("the combination of %qs and %qs is incompatible with %qs",
17386 "-mabi=o64", "-mabicalls", "-mlong64");
17390 if (mips_abi
== ABI_64
)
17391 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17396 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
17397 target_flags
|= MASK_LONG64
;
17399 target_flags
&= ~MASK_LONG64
;
17402 if (!TARGET_OLDABI
)
17403 flag_pcc_struct_return
= 0;
17405 /* Decide which rtx_costs structure to use. */
17407 mips_cost
= &mips_rtx_cost_optimize_size
;
17409 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
17411 /* If the user hasn't specified a branch cost, use the processor's
17413 if (mips_branch_cost
== 0)
17414 mips_branch_cost
= mips_cost
->branch_cost
;
17416 /* If neither -mbranch-likely nor -mno-branch-likely was given
17417 on the command line, set MASK_BRANCHLIKELY based on the target
17418 architecture and tuning flags. Annulled delay slots are a
17419 size win, so we only consider the processor-specific tuning
17420 for !optimize_size. */
17421 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
17423 if (ISA_HAS_BRANCHLIKELY
17425 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
17426 target_flags
|= MASK_BRANCHLIKELY
;
17428 target_flags
&= ~MASK_BRANCHLIKELY
;
17430 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
17431 warning (0, "the %qs architecture does not support branch-likely"
17432 " instructions", mips_arch_info
->name
);
17434 /* If the user hasn't specified -mimadd or -mno-imadd set
17435 MASK_IMADD based on the target architecture and tuning
17437 if ((target_flags_explicit
& MASK_IMADD
) == 0)
17439 if (ISA_HAS_MADD_MSUB
&&
17440 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
17441 target_flags
|= MASK_IMADD
;
17443 target_flags
&= ~MASK_IMADD
;
17445 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
17446 warning (0, "the %qs architecture does not support madd or msub"
17447 " instructions", mips_arch_info
->name
);
17449 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
17450 line, set MASK_ODD_SPREG based on the ISA and ABI. */
17451 if ((target_flags_explicit
& MASK_ODD_SPREG
) == 0)
17453 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
17454 if (!ISA_HAS_ODD_SPREG
|| TARGET_FLOATXX
)
17455 target_flags
&= ~MASK_ODD_SPREG
;
17457 target_flags
|= MASK_ODD_SPREG
;
17459 else if (TARGET_ODD_SPREG
&& !ISA_HAS_ODD_SPREG
)
17460 warning (0, "the %qs architecture does not support odd single-precision"
17461 " registers", mips_arch_info
->name
);
17463 if (!TARGET_ODD_SPREG
&& TARGET_64BIT
)
17465 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
17466 /* Allow compilation to continue further even though invalid output
17467 will be produced. */
17468 target_flags
|= MASK_ODD_SPREG
;
17471 /* The effect of -mabicalls isn't defined for the EABI. */
17472 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
17474 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17475 target_flags
&= ~MASK_ABICALLS
;
17478 /* PIC requires -mabicalls. */
17481 if (mips_abi
== ABI_EABI
)
17482 error ("cannot generate position-independent code for %qs",
17484 else if (!TARGET_ABICALLS
)
17485 error ("position-independent code requires %qs", "-mabicalls");
17488 if (TARGET_ABICALLS_PIC2
)
17489 /* We need to set flag_pic for executables as well as DSOs
17490 because we may reference symbols that are not defined in
17491 the final executable. (MIPS does not use things like
17492 copy relocs, for example.)
17494 There is a body of code that uses __PIC__ to distinguish
17495 between -mabicalls and -mno-abicalls code. The non-__PIC__
17496 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17497 long as any indirect jumps use $25. */
17500 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17501 faster code, but at the expense of more nops. Enable it at -O3 and
17503 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
17504 target_flags
|= MASK_VR4130_ALIGN
;
17506 /* Prefer a call to memcpy over inline code when optimizing for size,
17507 though see MOVE_RATIO in mips.h. */
17508 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
17509 target_flags
|= MASK_MEMCPY
;
17511 /* If we have a nonzero small-data limit, check that the -mgpopt
17512 setting is consistent with the other target flags. */
17513 if (mips_small_data_threshold
> 0)
17517 if (!TARGET_EXPLICIT_RELOCS
)
17518 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17520 TARGET_LOCAL_SDATA
= false;
17521 TARGET_EXTERN_SDATA
= false;
17525 if (TARGET_VXWORKS_RTP
)
17526 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17528 if (TARGET_ABICALLS
)
17529 warning (0, "cannot use small-data accesses for %qs",
17534 /* Set NaN and ABS defaults. */
17535 if (mips_nan
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
17536 mips_nan
= MIPS_IEEE_754_2008
;
17537 if (mips_abs
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
17538 mips_abs
= MIPS_IEEE_754_2008
;
17540 /* Check for IEEE 754 legacy/2008 support. */
17541 if ((mips_nan
== MIPS_IEEE_754_LEGACY
17542 || mips_abs
== MIPS_IEEE_754_LEGACY
)
17543 && !ISA_HAS_IEEE_754_LEGACY
)
17544 warning (0, "the %qs architecture does not support %<-m%s=legacy%>",
17545 mips_arch_info
->name
,
17546 mips_nan
== MIPS_IEEE_754_LEGACY
? "nan" : "abs");
17548 if ((mips_nan
== MIPS_IEEE_754_2008
17549 || mips_abs
== MIPS_IEEE_754_2008
)
17550 && !ISA_HAS_IEEE_754_2008
)
17551 warning (0, "the %qs architecture does not support %<-m%s=2008%>",
17552 mips_arch_info
->name
,
17553 mips_nan
== MIPS_IEEE_754_2008
? "nan" : "abs");
17555 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17556 for all its floating point. */
17557 if (mips_nan
!= MIPS_IEEE_754_2008
)
17559 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
17560 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
17561 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
17564 /* Make sure that the user didn't turn off paired single support when
17565 MIPS-3D support is requested. */
17567 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
17568 && !TARGET_PAIRED_SINGLE_FLOAT
)
17569 error ("%<-mips3d%> requires %<-mpaired-single%>");
17571 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17573 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
17575 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17576 and TARGET_HARD_FLOAT_ABI are both true. */
17577 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
17579 error ("%qs must be used with %qs",
17580 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
17581 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
17582 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17586 /* Make sure that -mpaired-single is only used on ISAs that support it.
17587 We must disable it otherwise since it relies on other ISA properties
17588 like ISA_HAS_8CC having their normal values. */
17589 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
17591 error ("the %qs architecture does not support paired-single"
17592 " instructions", mips_arch_info
->name
);
17593 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
17597 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17598 && !TARGET_CACHE_BUILTIN
)
17600 error ("%qs requires a target that provides the %qs instruction",
17601 "-mr10k-cache-barrier", "cache");
17602 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
17605 /* If TARGET_DSPR2, enable TARGET_DSP. */
17609 if (TARGET_DSP
&& mips_isa_rev
>= 6)
17611 error ("the %qs architecture does not support DSP instructions",
17612 mips_arch_info
->name
);
17613 TARGET_DSP
= false;
17614 TARGET_DSPR2
= false;
17617 /* .eh_frame addresses should be the same width as a C pointer.
17618 Most MIPS ABIs support only one pointer size, so the assembler
17619 will usually know exactly how big an .eh_frame address is.
17621 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17622 originally defined to use 64-bit pointers (i.e. it is LP64), and
17623 this is still the default mode. However, we also support an n32-like
17624 ILP32 mode, which is selected by -mlong32. The problem is that the
17625 assembler has traditionally not had an -mlong option, so it has
17626 traditionally not known whether we're using the ILP32 or LP64 form.
17628 As it happens, gas versions up to and including 2.19 use _32-bit_
17629 addresses for EABI64 .cfi_* directives. This is wrong for the
17630 default LP64 mode, so we can't use the directives by default.
17631 Moreover, since gas's current behavior is at odds with gcc's
17632 default behavior, it seems unwise to rely on future versions
17633 of gas behaving the same way. We therefore avoid using .cfi
17634 directives for -mlong32 as well. */
17635 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
17636 flag_dwarf2_cfi_asm
= 0;
17638 /* .cfi_* directives generate a read-only section, so fall back on
17639 manual .eh_frame creation if we need the section to be writable. */
17640 if (TARGET_WRITABLE_EH_FRAME
)
17641 flag_dwarf2_cfi_asm
= 0;
17643 mips_init_print_operand_punct ();
17645 /* Set up array to map GCC register number to debug register number.
17646 Ignore the special purpose register numbers. */
17648 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
17650 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
17651 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
17652 mips_dwarf_regno
[i
] = i
;
17654 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
17657 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
17658 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
17659 mips_dbx_regno
[i
] = i
+ start
;
17661 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
17662 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
17663 mips_dbx_regno
[i
] = i
+ start
;
17665 /* Accumulator debug registers use big-endian ordering. */
17666 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
17667 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
17668 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
17669 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
17670 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
17672 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
17673 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
17676 /* Set up mips_hard_regno_mode_ok. */
17677 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
17678 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
17679 mips_hard_regno_mode_ok
[mode
][regno
]
17680 = mips_hard_regno_mode_ok_p (regno
, (machine_mode
) mode
);
17682 /* Function to allocate machine-dependent function status. */
17683 init_machine_status
= &mips_init_machine_status
;
17685 /* Default to working around R4000 errata only if the processor
17686 was selected explicitly. */
17687 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
17688 && strcmp (mips_arch_info
->name
, "r4000") == 0)
17689 target_flags
|= MASK_FIX_R4000
;
17691 /* Default to working around R4400 errata only if the processor
17692 was selected explicitly. */
17693 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
17694 && strcmp (mips_arch_info
->name
, "r4400") == 0)
17695 target_flags
|= MASK_FIX_R4400
;
17697 /* Default to working around R10000 errata only if the processor
17698 was selected explicitly. */
17699 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
17700 && strcmp (mips_arch_info
->name
, "r10000") == 0)
17701 target_flags
|= MASK_FIX_R10000
;
17703 /* Make sure that branch-likely instructions available when using
17704 -mfix-r10000. The instructions are not available if either:
17706 1. -mno-branch-likely was passed.
17707 2. The selected ISA does not support branch-likely and
17708 the command line does not include -mbranch-likely. */
17709 if (TARGET_FIX_R10000
17710 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
17711 ? !ISA_HAS_BRANCHLIKELY
17712 : !TARGET_BRANCHLIKELY
))
17713 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17715 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
17717 warning (0, "the %qs architecture does not support the synci "
17718 "instruction", mips_arch_info
->name
);
17719 target_flags
&= ~MASK_SYNCI
;
17722 /* Only optimize PIC indirect calls if they are actually required. */
17723 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
17724 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
17726 /* Save base state of options. */
17727 mips_base_target_flags
= target_flags
;
17728 mips_base_schedule_insns
= flag_schedule_insns
;
17729 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
17730 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
17731 mips_base_align_loops
= align_loops
;
17732 mips_base_align_jumps
= align_jumps
;
17733 mips_base_align_functions
= align_functions
;
17735 /* Now select the ISA mode.
17737 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17738 later if required. */
17739 mips_set_compression_mode (0);
17741 /* We register a second machine specific reorg pass after delay slot
17742 filling. Registering the pass must be done at start up. It's
17743 convenient to do it here. */
17744 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
17745 struct register_pass_info insert_pass_mips_machine_reorg2
=
17747 new_pass
, /* pass */
17748 "dbr", /* reference_pass_name */
17749 1, /* ref_pass_instance_number */
17750 PASS_POS_INSERT_AFTER
/* po_op */
17752 register_pass (&insert_pass_mips_machine_reorg2
);
17754 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
17755 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
17758 /* Swap the register information for registers I and I + 1, which
17759 currently have the wrong endianness. Note that the registers'
17760 fixedness and call-clobberedness might have been set on the
17764 mips_swap_registers (unsigned int i
)
17769 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17770 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17772 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
17773 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
17774 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
17775 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
17781 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17784 mips_conditional_register_usage (void)
17789 /* These DSP control register fields are global. */
17790 global_regs
[CCDSP_PO_REGNUM
] = 1;
17791 global_regs
[CCDSP_SC_REGNUM
] = 1;
17794 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17795 reg_class_contents
[(int) DSP_ACC_REGS
]);
17798 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17799 reg_class_contents
[(int) MD_REGS
]);
17801 if (!TARGET_HARD_FLOAT
)
17803 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17804 reg_class_contents
[(int) FP_REGS
]);
17805 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17806 reg_class_contents
[(int) ST_REGS
]);
17808 else if (!ISA_HAS_8CC
)
17810 /* We only have a single condition-code register. We implement
17811 this by fixing all the condition-code registers and generating
17812 RTL that refers directly to ST_REG_FIRST. */
17813 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
17814 reg_class_contents
[(int) ST_REGS
]);
17816 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
17817 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
17821 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17822 are call-saved, and saving them via a MIPS16 register would
17823 probably waste more time than just reloading the value.
17825 We permit the $t temporary registers when optimizing for speed
17826 but not when optimizing for space because using them results in
17827 code that is larger (but faster) then not using them. We do
17828 allow $24 (t8) because it is used in CMP and CMPI instructions
17829 and $25 (t9) because it is used as the function call address in
17832 fixed_regs
[18] = call_used_regs
[18] = 1;
17833 fixed_regs
[19] = call_used_regs
[19] = 1;
17834 fixed_regs
[20] = call_used_regs
[20] = 1;
17835 fixed_regs
[21] = call_used_regs
[21] = 1;
17836 fixed_regs
[22] = call_used_regs
[22] = 1;
17837 fixed_regs
[23] = call_used_regs
[23] = 1;
17838 fixed_regs
[26] = call_used_regs
[26] = 1;
17839 fixed_regs
[27] = call_used_regs
[27] = 1;
17840 fixed_regs
[30] = call_used_regs
[30] = 1;
17843 fixed_regs
[8] = call_used_regs
[8] = 1;
17844 fixed_regs
[9] = call_used_regs
[9] = 1;
17845 fixed_regs
[10] = call_used_regs
[10] = 1;
17846 fixed_regs
[11] = call_used_regs
[11] = 1;
17847 fixed_regs
[12] = call_used_regs
[12] = 1;
17848 fixed_regs
[13] = call_used_regs
[13] = 1;
17849 fixed_regs
[14] = call_used_regs
[14] = 1;
17850 fixed_regs
[15] = call_used_regs
[15] = 1;
17853 /* Do not allow HI and LO to be treated as register operands.
17854 There are no MTHI or MTLO instructions (or any real need
17855 for them) and one-way registers cannot easily be reloaded. */
17856 AND_COMPL_HARD_REG_SET (operand_reg_set
,
17857 reg_class_contents
[(int) MD_REGS
]);
17859 /* $f20-$f23 are call-clobbered for n64. */
17860 if (mips_abi
== ABI_64
)
17863 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
17864 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17866 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17867 for n32 and o32 FP64. */
17868 if (mips_abi
== ABI_N32
17869 || (mips_abi
== ABI_32
17870 && TARGET_FLOAT64
))
17873 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
17874 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
17876 /* Make sure that double-register accumulator values are correctly
17877 ordered for the current endianness. */
17878 if (TARGET_LITTLE_ENDIAN
)
17880 unsigned int regno
;
17882 mips_swap_registers (MD_REG_FIRST
);
17883 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
17884 mips_swap_registers (regno
);
17888 /* Implement EH_USES. */
17891 mips_eh_uses (unsigned int regno
)
17893 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17895 /* We need to force certain registers to be live in order to handle
17896 PIC long branches correctly. See mips_must_initialize_gp_p for
17898 if (mips_cfun_has_cprestore_slot_p ())
17900 if (regno
== CPRESTORE_SLOT_REGNUM
)
17905 if (cfun
->machine
->global_pointer
== regno
)
17913 /* Implement EPILOGUE_USES. */
17916 mips_epilogue_uses (unsigned int regno
)
17918 /* Say that the epilogue uses the return address register. Note that
17919 in the case of sibcalls, the values "used by the epilogue" are
17920 considered live at the start of the called function. */
17921 if (regno
== RETURN_ADDR_REGNUM
)
17924 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17925 See the comment above load_call<mode> for details. */
17926 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17929 /* An interrupt handler must preserve some registers that are
17930 ordinarily call-clobbered. */
17931 if (cfun
->machine
->interrupt_handler_p
17932 && mips_interrupt_extra_call_saved_reg_p (regno
))
17938 /* Return true if INSN needs to be wrapped in ".set noat".
17939 INSN has NOPERANDS operands, stored in OPVEC. */
17942 mips_need_noat_wrapper_p (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
17944 if (recog_memoized (insn
) >= 0)
17946 subrtx_iterator::array_type array
;
17947 for (int i
= 0; i
< noperands
; i
++)
17948 FOR_EACH_SUBRTX (iter
, array
, opvec
[i
], NONCONST
)
17949 if (REG_P (*iter
) && REGNO (*iter
) == AT_REGNUM
)
17955 /* Implement FINAL_PRESCAN_INSN. */
17958 mips_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
17960 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17961 mips_push_asm_switch (&mips_noat
);
17964 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17967 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx_insn
*insn
,
17968 rtx
*opvec
, int noperands
)
17970 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17971 mips_pop_asm_switch (&mips_noat
);
17974 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17975 EXT_CODE is the code of the extension used. Return NULL if widening
17976 multiplication shouldn't be used. */
17979 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17983 signed_p
= ext_code
== SIGN_EXTEND
;
17986 /* Don't use widening multiplication with MULT when we have DMUL. Even
17987 with the extension of its input operands DMUL is faster. Note that
17988 the extension is not needed for signed multiplication. In order to
17989 ensure that we always remove the redundant sign-extension in this
17990 case we still expand mulsidi3 for DMUL. */
17991 if (ISA_HAS_R6DMUL
)
17992 return signed_p
? gen_mulsidi3_64bit_r6dmul
: NULL
;
17994 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17997 ? gen_mulsidi3_64bit_mips16
17998 : gen_umulsidi3_64bit_mips16
);
17999 if (TARGET_FIX_R4000
)
18001 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
18006 return (signed_p
? gen_mulsidi3_32bit_r6
: gen_umulsidi3_32bit_r6
);
18009 ? gen_mulsidi3_32bit_mips16
18010 : gen_umulsidi3_32bit_mips16
);
18011 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
18012 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
18013 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
18017 /* Return true if PATTERN matches the kind of instruction generated by
18018 umips_build_save_restore. SAVE_P is true for store. */
18021 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
18025 HOST_WIDE_INT first_offset
= 0;
18026 rtx first_base
= 0;
18027 unsigned int regmask
= 0;
18029 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
18031 rtx set
, reg
, mem
, this_base
;
18032 HOST_WIDE_INT this_offset
;
18034 /* Check that we have a SET. */
18035 set
= XVECEXP (pattern
, 0, n
);
18036 if (GET_CODE (set
) != SET
)
18039 /* Check that the SET is a load (if restoring) or a store
18041 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
18042 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
18045 /* Check that the address is the sum of base and a possibly-zero
18046 constant offset. Determine if the offset is in range. */
18047 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
18048 if (!REG_P (this_base
))
18053 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
18055 first_base
= this_base
;
18056 first_offset
= this_offset
;
18060 /* Check that the save slots are consecutive. */
18061 if (REGNO (this_base
) != REGNO (first_base
)
18062 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
18066 /* Check that SET's other operand is a register. */
18067 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
18071 regmask
|= 1 << REGNO (reg
);
18074 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
18075 if (regmask
== umips_swm_mask
[i
])
18081 /* Return the assembly instruction for microMIPS LWM or SWM.
18082 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
18085 umips_output_save_restore (bool save_p
, rtx pattern
)
18087 static char buffer
[300];
18090 HOST_WIDE_INT offset
;
18091 rtx base
, mem
, set
, last_set
, last_reg
;
18093 /* Parse the pattern. */
18094 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
18096 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
18098 n
= XVECLEN (pattern
, 0);
18100 set
= XVECEXP (pattern
, 0, 0);
18101 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
18102 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
18104 last_set
= XVECEXP (pattern
, 0, n
- 1);
18105 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
18107 if (REGNO (last_reg
) == 31)
18110 gcc_assert (n
<= 9);
18114 s
+= sprintf (s
, "%s,", reg_names
[16]);
18116 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
18118 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
18121 if (REGNO (last_reg
) == 31)
18122 s
+= sprintf (s
, "%s,", reg_names
[31]);
18124 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
18128 /* Return true if MEM1 and MEM2 use the same base register, and the
18129 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
18130 register into (from) which the contents of MEM1 will be loaded
18131 (stored), depending on the value of LOAD_P.
18132 SWAP_P is true when the 1st and 2nd instructions are swapped. */
18135 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
18136 rtx first_reg
, rtx mem1
, rtx mem2
)
18139 HOST_WIDE_INT offset1
, offset2
;
18141 if (!MEM_P (mem1
) || !MEM_P (mem2
))
18144 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
18145 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
18147 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
18150 /* Avoid invalid load pair instructions. */
18151 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
18154 /* We must avoid this case for anti-dependence.
18157 first_reg is $2, but the base is $3. */
18160 && REGNO (first_reg
) + 1 == REGNO (base1
))
18163 if (offset2
!= offset1
+ 4)
18166 if (!UMIPS_12BIT_OFFSET_P (offset1
))
18173 mips_load_store_bonding_p (rtx
*operands
, machine_mode mode
, bool load_p
)
18175 rtx reg1
, reg2
, mem1
, mem2
, base1
, base2
;
18176 enum reg_class rc1
, rc2
;
18177 HOST_WIDE_INT offset1
, offset2
;
18181 reg1
= operands
[0];
18182 reg2
= operands
[2];
18183 mem1
= operands
[1];
18184 mem2
= operands
[3];
18188 reg1
= operands
[1];
18189 reg2
= operands
[3];
18190 mem1
= operands
[0];
18191 mem2
= operands
[2];
18194 if (mips_address_insns (XEXP (mem1
, 0), mode
, false) == 0
18195 || mips_address_insns (XEXP (mem2
, 0), mode
, false) == 0)
18198 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
18199 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
18201 /* Base regs do not match. */
18202 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
18205 /* Either of the loads is clobbering base register. It is legitimate to bond
18206 loads if second load clobbers base register. However, hardware does not
18207 support such bonding. */
18209 && (REGNO (reg1
) == REGNO (base1
)
18210 || (REGNO (reg2
) == REGNO (base1
))))
18213 /* Loading in same registers. */
18215 && REGNO (reg1
) == REGNO (reg2
))
18218 /* The loads/stores are not of same type. */
18219 rc1
= REGNO_REG_CLASS (REGNO (reg1
));
18220 rc2
= REGNO_REG_CLASS (REGNO (reg2
));
18222 && !reg_class_subset_p (rc1
, rc2
)
18223 && !reg_class_subset_p (rc2
, rc1
))
18226 if (abs (offset1
- offset2
) != GET_MODE_SIZE (mode
))
18232 /* OPERANDS describes the operands to a pair of SETs, in the order
18233 dest1, src1, dest2, src2. Return true if the operands can be used
18234 in an LWP or SWP instruction; LOAD_P says which. */
18237 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
18239 rtx reg1
, reg2
, mem1
, mem2
;
18243 reg1
= operands
[0];
18244 reg2
= operands
[2];
18245 mem1
= operands
[1];
18246 mem2
= operands
[3];
18250 reg1
= operands
[1];
18251 reg2
= operands
[3];
18252 mem1
= operands
[0];
18253 mem2
= operands
[2];
18256 if (REGNO (reg2
) == REGNO (reg1
) + 1)
18257 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
18259 if (REGNO (reg1
) == REGNO (reg2
) + 1)
18260 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
18265 /* Return the assembly instruction for a microMIPS LWP or SWP in which
18266 the first register is REG and the first memory slot is MEM.
18267 LOAD_P is true for LWP. */
18270 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
18272 rtx ops
[] = {reg
, mem
};
18275 output_asm_insn ("lwp\t%0,%1", ops
);
18277 output_asm_insn ("swp\t%0,%1", ops
);
18280 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
18281 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
18284 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
18286 rtx reg1
, reg2
, mem1
, mem2
;
18289 reg1
= operands
[0];
18290 reg2
= operands
[2];
18291 mem1
= operands
[1];
18292 mem2
= operands
[3];
18296 reg1
= operands
[1];
18297 reg2
= operands
[3];
18298 mem1
= operands
[0];
18299 mem2
= operands
[2];
18302 if (REGNO (reg2
) == REGNO (reg1
) + 1)
18304 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
18308 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
18309 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
18312 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
18315 umips_movep_target_p (rtx reg1
, rtx reg2
)
18317 int regno1
, regno2
, pair
;
18319 static const int match
[8] = {
18320 0x00000060, /* 5, 6 */
18321 0x000000a0, /* 5, 7 */
18322 0x000000c0, /* 6, 7 */
18323 0x00200010, /* 4, 21 */
18324 0x00400010, /* 4, 22 */
18325 0x00000030, /* 4, 5 */
18326 0x00000050, /* 4, 6 */
18327 0x00000090 /* 4, 7 */
18330 if (!REG_P (reg1
) || !REG_P (reg2
))
18333 regno1
= REGNO (reg1
);
18334 regno2
= REGNO (reg2
);
18336 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
18339 pair
= (1 << regno1
) | (1 << regno2
);
18341 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
18342 if (pair
== match
[i
])
18348 /* Return the size in bytes of the trampoline code, padded to
18349 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
18350 function address immediately follow. */
18353 mips_trampoline_code_size (void)
18355 if (TARGET_USE_PIC_FN_ADDR_REG
)
18357 else if (ptr_mode
== DImode
)
18359 else if (ISA_HAS_LOAD_DELAY
)
18365 /* Implement TARGET_TRAMPOLINE_INIT. */
18368 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
18370 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
18373 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
18375 /* Work out the offsets of the pointers from the start of the
18376 trampoline code. */
18377 end_addr_offset
= mips_trampoline_code_size ();
18378 static_chain_offset
= end_addr_offset
;
18379 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
18381 /* Get pointers to the beginning and end of the code block. */
18382 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
18383 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
18385 #define OP(X) gen_int_mode (X, SImode)
18387 /* Build up the code in TRAMPOLINE. */
18389 if (TARGET_USE_PIC_FN_ADDR_REG
)
18391 /* $25 contains the address of the trampoline. Emit code of the form:
18393 l[wd] $1, target_function_offset($25)
18394 l[wd] $static_chain, static_chain_offset($25)
18397 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
18398 target_function_offset
,
18399 PIC_FUNCTION_ADDR_REGNUM
));
18400 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18401 static_chain_offset
,
18402 PIC_FUNCTION_ADDR_REGNUM
));
18403 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
18404 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
18406 else if (ptr_mode
== DImode
)
18408 /* It's too cumbersome to create the full 64-bit address, so let's
18414 1: l[wd] $25, target_function_offset - 12($31)
18415 l[wd] $static_chain, static_chain_offset - 12($31)
18419 where 12 is the offset of "1:" from the start of the code block. */
18420 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
18421 trampoline
[i
++] = OP (MIPS_BAL (1));
18422 trampoline
[i
++] = OP (MIPS_NOP
);
18423 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18424 target_function_offset
- 12,
18425 RETURN_ADDR_REGNUM
));
18426 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18427 static_chain_offset
- 12,
18428 RETURN_ADDR_REGNUM
));
18429 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18430 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
18434 /* If the target has load delays, emit:
18436 lui $1, %hi(end_addr)
18437 lw $25, %lo(end_addr + ...)($1)
18438 lw $static_chain, %lo(end_addr + ...)($1)
18444 lui $1, %hi(end_addr)
18445 lw $25, %lo(end_addr + ...)($1)
18447 lw $static_chain, %lo(end_addr + ...)($1). */
18449 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18450 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18451 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
18452 NULL
, false, OPTAB_WIDEN
);
18453 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
18454 NULL
, false, OPTAB_WIDEN
);
18455 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
18457 /* Emit the LUI. */
18458 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
18459 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
18460 NULL
, false, OPTAB_WIDEN
);
18462 /* Emit the load of the target function. */
18463 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
18464 target_function_offset
- end_addr_offset
,
18466 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18467 NULL
, false, OPTAB_WIDEN
);
18469 /* Emit the JR here, if we can. */
18470 if (!ISA_HAS_LOAD_DELAY
)
18471 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18473 /* Emit the load of the static chain register. */
18474 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
18475 static_chain_offset
- end_addr_offset
,
18477 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
18478 NULL
, false, OPTAB_WIDEN
);
18480 /* Emit the JR, if we couldn't above. */
18481 if (ISA_HAS_LOAD_DELAY
)
18483 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
18484 trampoline
[i
++] = OP (MIPS_NOP
);
18490 /* Copy the trampoline code. Leave any padding uninitialized. */
18491 for (j
= 0; j
< i
; j
++)
18493 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
18494 mips_emit_move (mem
, trampoline
[j
]);
18497 /* Set up the static chain pointer field. */
18498 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
18499 mips_emit_move (mem
, chain_value
);
18501 /* Set up the target function field. */
18502 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
18503 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
18505 /* Flush the code part of the trampoline. */
18506 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
18507 emit_insn (gen_clear_cache (addr
, end_addr
));
18510 /* Implement FUNCTION_PROFILER. */
18512 void mips_function_profiler (FILE *file
)
18515 sorry ("mips16 function profiling");
18516 if (TARGET_LONG_CALLS
)
18518 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18519 if (Pmode
== DImode
)
18520 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
18522 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
18524 mips_push_asm_switch (&mips_noat
);
18525 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
18526 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
18527 /* _mcount treats $2 as the static chain register. */
18528 if (cfun
->static_chain_decl
!= NULL
)
18529 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
18530 reg_names
[STATIC_CHAIN_REGNUM
]);
18531 if (TARGET_MCOUNT_RA_ADDRESS
)
18533 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18534 ra save location. */
18535 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
18536 /* ra not saved, pass zero. */
18537 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
18539 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
18540 Pmode
== DImode
? "dla" : "la", reg_names
[12],
18541 cfun
->machine
->frame
.ra_fp_offset
,
18542 reg_names
[STACK_POINTER_REGNUM
]);
18544 if (!TARGET_NEWABI
)
18546 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18547 TARGET_64BIT
? "dsubu" : "subu",
18548 reg_names
[STACK_POINTER_REGNUM
],
18549 reg_names
[STACK_POINTER_REGNUM
],
18550 Pmode
== DImode
? 16 : 8);
18552 if (TARGET_LONG_CALLS
)
18553 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
18555 fprintf (file
, "\tjal\t_mcount\n");
18556 mips_pop_asm_switch (&mips_noat
);
18557 /* _mcount treats $2 as the static chain register. */
18558 if (cfun
->static_chain_decl
!= NULL
)
18559 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
18563 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18564 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18565 when TARGET_LOONGSON_VECTORS is true. */
18567 static unsigned HOST_WIDE_INT
18568 mips_shift_truncation_mask (machine_mode mode
)
18570 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
18573 return GET_MODE_BITSIZE (mode
) - 1;
18576 /* Implement TARGET_PREPARE_PCH_SAVE. */
18579 mips_prepare_pch_save (void)
18581 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18582 setting should be irrelevant. The question then is: which setting
18583 makes most sense at load time?
18585 The PCH is loaded before the first token is read. We should never
18586 have switched into MIPS16 mode by that point, and thus should not
18587 have populated mips16_globals. Nor can we load the entire contents
18588 of mips16_globals from the PCH file, because mips16_globals contains
18589 a combination of GGC and non-GGC data.
18591 There is therefore no point in trying save the GGC part of
18592 mips16_globals to the PCH file, or to preserve MIPS16ness across
18593 the PCH save and load. The loading compiler would not have access
18594 to the non-GGC parts of mips16_globals (either from the PCH file,
18595 or from a copy that the loading compiler generated itself) and would
18596 have to call target_reinit anyway.
18598 It therefore seems best to switch back to non-MIPS16 mode at
18599 save time, and to ensure that mips16_globals remains null after
18601 mips_set_compression_mode (0);
18602 mips16_globals
= 0;
18605 /* Generate or test for an insn that supports a constant permutation. */
18607 #define MAX_VECT_LEN 8
18609 struct expand_vec_perm_d
18611 rtx target
, op0
, op1
;
18612 unsigned char perm
[MAX_VECT_LEN
];
18613 machine_mode vmode
;
18614 unsigned char nelt
;
18619 /* Construct (set target (vec_select op0 (parallel perm))) and
18620 return true if that's a valid instruction in the active ISA. */
18623 mips_expand_vselect (rtx target
, rtx op0
,
18624 const unsigned char *perm
, unsigned nelt
)
18626 rtx rperm
[MAX_VECT_LEN
], x
;
18630 for (i
= 0; i
< nelt
; ++i
)
18631 rperm
[i
] = GEN_INT (perm
[i
]);
18633 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
18634 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
18635 x
= gen_rtx_SET (target
, x
);
18637 insn
= emit_insn (x
);
18638 if (recog_memoized (insn
) < 0)
18640 remove_insn (insn
);
18646 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18649 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
18650 const unsigned char *perm
, unsigned nelt
)
18652 machine_mode v2mode
;
18655 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
18656 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
18657 return mips_expand_vselect (target
, x
, perm
, nelt
);
18660 /* Recognize patterns for even-odd extraction. */
18663 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
18665 unsigned i
, odd
, nelt
= d
->nelt
;
18666 rtx t0
, t1
, t2
, t3
;
18668 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18670 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18677 for (i
= 1; i
< nelt
; ++i
)
18678 if (d
->perm
[i
] != i
* 2 + odd
)
18684 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18685 t0
= gen_reg_rtx (d
->vmode
);
18686 t1
= gen_reg_rtx (d
->vmode
);
18690 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
18691 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
18693 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
18695 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
18699 t2
= gen_reg_rtx (d
->vmode
);
18700 t3
= gen_reg_rtx (d
->vmode
);
18701 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
18702 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
18703 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
18704 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
18706 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
18708 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
18712 gcc_unreachable ();
18717 /* Recognize patterns for the Loongson PSHUFH instruction. */
18720 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
18725 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18727 if (d
->vmode
!= V4HImode
)
18732 /* Convert the selector into the packed 8-bit form for pshufh. */
18733 /* Recall that loongson is little-endian only. No big-endian
18734 adjustment required. */
18735 for (i
= mask
= 0; i
< 4; i
++)
18736 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
18737 rmask
= force_reg (SImode
, GEN_INT (mask
));
18739 if (d
->one_vector_p
)
18740 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
18743 rtx t0
, t1
, x
, merge
, rmerge
[4];
18745 t0
= gen_reg_rtx (V4HImode
);
18746 t1
= gen_reg_rtx (V4HImode
);
18747 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
18748 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
18750 for (i
= 0; i
< 4; ++i
)
18751 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
18752 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
18753 merge
= force_reg (V4HImode
, merge
);
18755 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
18756 emit_insn (gen_rtx_SET (t1
, x
));
18758 x
= gen_rtx_NOT (V4HImode
, merge
);
18759 x
= gen_rtx_AND (V4HImode
, x
, t0
);
18760 emit_insn (gen_rtx_SET (t0
, x
));
18762 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
18763 emit_insn (gen_rtx_SET (d
->target
, x
));
18769 /* Recognize broadcast patterns for the Loongson. */
18772 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
18777 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
18779 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18780 if (d
->vmode
!= V8QImode
)
18782 if (!d
->one_vector_p
)
18786 for (i
= 1; i
< 8; ++i
)
18787 if (d
->perm
[i
] != elt
)
18793 /* With one interleave we put two of the desired element adjacent. */
18794 t0
= gen_reg_rtx (V8QImode
);
18796 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
18798 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
18800 /* Shuffle that one HImode element into all locations. */
18803 t1
= gen_reg_rtx (V4HImode
);
18804 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
18805 force_reg (SImode
, GEN_INT (elt
))));
18807 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
18812 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
18814 unsigned int i
, nelt
= d
->nelt
;
18815 unsigned char perm2
[MAX_VECT_LEN
];
18817 if (d
->one_vector_p
)
18819 /* Try interleave with alternating operands. */
18820 memcpy (perm2
, d
->perm
, sizeof(perm2
));
18821 for (i
= 1; i
< nelt
; i
+= 2)
18823 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
18828 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
18832 /* Try again with swapped operands. */
18833 for (i
= 0; i
< nelt
; ++i
)
18834 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
18835 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
18839 if (mips_expand_vpc_loongson_even_odd (d
))
18841 if (mips_expand_vpc_loongson_pshufh (d
))
18843 if (mips_expand_vpc_loongson_bcast (d
))
18848 /* Expand a vec_perm_const pattern. */
18851 mips_expand_vec_perm_const (rtx operands
[4])
18853 struct expand_vec_perm_d d
;
18854 int i
, nelt
, which
;
18855 unsigned char orig_perm
[MAX_VECT_LEN
];
18859 d
.target
= operands
[0];
18860 d
.op0
= operands
[1];
18861 d
.op1
= operands
[2];
18864 d
.vmode
= GET_MODE (d
.target
);
18865 gcc_assert (VECTOR_MODE_P (d
.vmode
));
18866 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18867 d
.testing_p
= false;
18869 for (i
= which
= 0; i
< nelt
; ++i
)
18871 rtx e
= XVECEXP (sel
, 0, i
);
18872 int ei
= INTVAL (e
) & (2 * nelt
- 1);
18873 which
|= (ei
< nelt
? 1 : 2);
18876 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18884 d
.one_vector_p
= false;
18885 if (!rtx_equal_p (d
.op0
, d
.op1
))
18890 for (i
= 0; i
< nelt
; ++i
)
18891 d
.perm
[i
] &= nelt
- 1;
18893 d
.one_vector_p
= true;
18898 d
.one_vector_p
= true;
18902 ok
= mips_expand_vec_perm_const_1 (&d
);
18904 /* If we were given a two-vector permutation which just happened to
18905 have both input vectors equal, we folded this into a one-vector
18906 permutation. There are several loongson patterns that are matched
18907 via direct vec_select+vec_concat expansion, but we do not have
18908 support in mips_expand_vec_perm_const_1 to guess the adjustment
18909 that should be made for a single operand. Just try again with
18910 the original permutation. */
18911 if (!ok
&& which
== 3)
18913 d
.op0
= operands
[1];
18914 d
.op1
= operands
[2];
18915 d
.one_vector_p
= false;
18916 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
18917 ok
= mips_expand_vec_perm_const_1 (&d
);
18923 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18926 mips_vectorize_vec_perm_const_ok (machine_mode vmode
,
18927 const unsigned char *sel
)
18929 struct expand_vec_perm_d d
;
18930 unsigned int i
, nelt
, which
;
18934 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
18935 d
.testing_p
= true;
18936 memcpy (d
.perm
, sel
, nelt
);
18938 /* Categorize the set of elements in the selector. */
18939 for (i
= which
= 0; i
< nelt
; ++i
)
18941 unsigned char e
= d
.perm
[i
];
18942 gcc_assert (e
< 2 * nelt
);
18943 which
|= (e
< nelt
? 1 : 2);
18946 /* For all elements from second vector, fold the elements to first. */
18948 for (i
= 0; i
< nelt
; ++i
)
18951 /* Check whether the mask can be applied to the vector type. */
18952 d
.one_vector_p
= (which
!= 3);
18954 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
18955 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
18956 if (!d
.one_vector_p
)
18957 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
18960 ret
= mips_expand_vec_perm_const_1 (&d
);
18966 /* Expand an integral vector unpack operation. */
18969 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
18971 machine_mode imode
= GET_MODE (operands
[1]);
18972 rtx (*unpack
) (rtx
, rtx
, rtx
);
18973 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
18974 rtx tmp
, dest
, zero
;
18980 unpack
= gen_loongson_punpckhbh
;
18982 unpack
= gen_loongson_punpcklbh
;
18983 cmpgt
= gen_loongson_pcmpgtb
;
18987 unpack
= gen_loongson_punpckhhw
;
18989 unpack
= gen_loongson_punpcklhw
;
18990 cmpgt
= gen_loongson_pcmpgth
;
18993 gcc_unreachable ();
18996 zero
= force_reg (imode
, CONST0_RTX (imode
));
19001 tmp
= gen_reg_rtx (imode
);
19002 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
19005 dest
= gen_reg_rtx (imode
);
19006 emit_insn (unpack (dest
, operands
[1], tmp
));
19008 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
19011 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
19014 mips_constant_elt_p (rtx x
)
19016 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
19019 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
19022 mips_expand_vi_broadcast (machine_mode vmode
, rtx target
, rtx elt
)
19024 struct expand_vec_perm_d d
;
19028 if (elt
!= const0_rtx
)
19029 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
19031 elt
= gen_lowpart (DImode
, elt
);
19033 t1
= gen_reg_rtx (vmode
);
19037 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
19040 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
19043 gcc_unreachable ();
19046 memset (&d
, 0, sizeof (d
));
19051 d
.nelt
= GET_MODE_NUNITS (vmode
);
19052 d
.one_vector_p
= true;
19054 ok
= mips_expand_vec_perm_const_1 (&d
);
19058 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
19059 elements of VALS with zeros, copy the constant vector to TARGET. */
19062 mips_expand_vi_constant (machine_mode vmode
, unsigned nelt
,
19063 rtx target
, rtx vals
)
19065 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
19068 for (i
= 0; i
< nelt
; ++i
)
19070 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
19071 RTVEC_ELT (vec
, i
) = const0_rtx
;
19074 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
19078 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
19081 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
19083 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
19085 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
19086 GEN_INT (one_var
)));
19089 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
19092 mips_expand_vi_general (machine_mode vmode
, machine_mode imode
,
19093 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
19095 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
19096 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
19099 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
19101 for (i
= 0; i
< nelt
; ++i
)
19103 rtx x
= XVECEXP (vals
, 0, i
);
19104 if (!mips_constant_elt_p (x
))
19105 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
19108 emit_move_insn (target
, mem
);
19111 /* Expand a vector initialization. */
19114 mips_expand_vector_init (rtx target
, rtx vals
)
19116 machine_mode vmode
= GET_MODE (target
);
19117 machine_mode imode
= GET_MODE_INNER (vmode
);
19118 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
19119 unsigned nvar
= 0, one_var
= -1u;
19120 bool all_same
= true;
19123 for (i
= 0; i
< nelt
; ++i
)
19125 x
= XVECEXP (vals
, 0, i
);
19126 if (!mips_constant_elt_p (x
))
19127 nvar
++, one_var
= i
;
19128 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
19132 /* Load constants from the pool, or whatever's handy. */
19135 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
19139 /* For two-part initialization, always use CONCAT. */
19142 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
19143 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
19144 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
19145 emit_insn (gen_rtx_SET (target
, x
));
19149 /* Loongson is the only cpu with vectors with more elements. */
19150 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
19152 /* If all values are identical, broadcast the value. */
19155 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
19159 /* If we've only got one non-variable V4HImode, use PINSRH. */
19160 if (nvar
== 1 && vmode
== V4HImode
)
19162 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
19166 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
19169 /* Expand a vector reduction. */
19172 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
19174 machine_mode vmode
= GET_MODE (in
);
19175 unsigned char perm2
[2];
19176 rtx last
, next
, fold
, x
;
19180 fold
= gen_reg_rtx (vmode
);
19184 /* Use PUL/PLU to produce { L, H } op { H, L }.
19185 By reversing the pair order, rather than a pure interleave high,
19186 we avoid erroneous exceptional conditions that we might otherwise
19187 produce from the computation of H op H. */
19190 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
19195 /* Use interleave to produce { H, L } op { H, H }. */
19196 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
19200 /* Perform the first reduction with interleave,
19201 and subsequent reductions with shifts. */
19202 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
19204 next
= gen_reg_rtx (vmode
);
19205 emit_insn (gen (next
, last
, fold
));
19208 fold
= gen_reg_rtx (vmode
);
19209 x
= force_reg (SImode
, GEN_INT (16));
19210 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
19214 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
19216 next
= gen_reg_rtx (vmode
);
19217 emit_insn (gen (next
, last
, fold
));
19220 fold
= gen_reg_rtx (vmode
);
19221 x
= force_reg (SImode
, GEN_INT (16));
19222 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
19224 next
= gen_reg_rtx (vmode
);
19225 emit_insn (gen (next
, last
, fold
));
19228 fold
= gen_reg_rtx (vmode
);
19229 x
= force_reg (SImode
, GEN_INT (8));
19230 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
19234 gcc_unreachable ();
19237 emit_insn (gen (target
, last
, fold
));
19240 /* Expand a vector minimum/maximum. */
19243 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
19244 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
19246 machine_mode vmode
= GET_MODE (target
);
19249 tc
= gen_reg_rtx (vmode
);
19250 t0
= gen_reg_rtx (vmode
);
19251 t1
= gen_reg_rtx (vmode
);
19254 emit_insn (cmp (tc
, op0
, op1
));
19256 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
19257 emit_insn (gen_rtx_SET (t0
, x
));
19259 x
= gen_rtx_NOT (vmode
, tc
);
19260 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
19261 emit_insn (gen_rtx_SET (t1
, x
));
19263 x
= gen_rtx_IOR (vmode
, t0
, t1
);
19264 emit_insn (gen_rtx_SET (target
, x
));
19267 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
19270 mips_hard_regno_caller_save_mode (unsigned int regno
,
19271 unsigned int nregs
,
19274 /* For performance, avoid saving/restoring upper parts of a register
19275 by returning MODE as save mode when the mode is known. */
19276 if (mode
== VOIDmode
)
19277 return choose_hard_reg_mode (regno
, nregs
, false);
19282 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
19285 mips_case_values_threshold (void)
19287 /* In MIPS16 mode using a larger case threshold generates smaller code. */
19288 if (TARGET_MIPS16
&& optimize_size
)
19291 return default_case_values_threshold ();
19294 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
19297 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
19299 if (!TARGET_HARD_FLOAT_ABI
)
19301 tree exceptions_var
= create_tmp_var (MIPS_ATYPE_USI
);
19302 tree fcsr_orig_var
= create_tmp_var (MIPS_ATYPE_USI
);
19303 tree fcsr_mod_var
= create_tmp_var (MIPS_ATYPE_USI
);
19304 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
19305 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
19306 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
19307 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19308 fcsr_orig_var
, get_fcsr_hold_call
);
19309 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
19310 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
19311 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19312 fcsr_mod_var
, hold_mod_val
);
19313 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
19314 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
19315 hold_assign_orig
, hold_assign_mod
);
19316 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
19317 set_fcsr_hold_call
);
19319 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
19321 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
19322 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
19323 exceptions_var
, get_fcsr_update_call
);
19324 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
19325 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
19326 set_fcsr_update_call
);
19327 tree atomic_feraiseexcept
19328 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
19329 tree int_exceptions_var
= fold_convert (integer_type_node
,
19331 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
19332 1, int_exceptions_var
);
19333 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
19334 atomic_feraiseexcept_call
);
19337 /* Implement TARGET_SPILL_CLASS. */
19340 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED
,
19341 machine_mode mode ATTRIBUTE_UNUSED
)
19348 /* Implement TARGET_LRA_P. */
19353 return mips_lra_flag
;
19356 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
19359 mips_ira_change_pseudo_allocno_class (int regno
, reg_class_t allocno_class
)
19361 /* LRA will allocate an FPR for an integer mode pseudo instead of spilling
19362 to memory if an FPR is present in the allocno class. It is rare that
19363 we actually need to place an integer mode value in an FPR so where
19364 possible limit the allocation to GR_REGS. This will slightly pessimize
19365 code that involves integer to/from float conversions as these will have
19366 to reload into FPRs in LRA. Such reloads are sometimes eliminated and
19367 sometimes only partially eliminated. We choose to take this penalty
19368 in order to eliminate usage of FPRs in code that does not use floating
19371 This change has a similar effect to increasing the cost of FPR->GPR
19372 register moves for integer modes so that they are higher than the cost
19373 of memory but changing the allocno class is more reliable.
19375 This is also similar to forbidding integer mode values in FPRs entirely
19376 but this would lead to an inconsistency in the integer to/from float
19377 instructions that say integer mode values must be placed in FPRs. */
19378 if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno
)) && allocno_class
== ALL_REGS
)
19380 return allocno_class
;
19383 /* Initialize the GCC target structure. */
19384 #undef TARGET_ASM_ALIGNED_HI_OP
19385 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
19386 #undef TARGET_ASM_ALIGNED_SI_OP
19387 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
19388 #undef TARGET_ASM_ALIGNED_DI_OP
19389 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
19391 #undef TARGET_OPTION_OVERRIDE
19392 #define TARGET_OPTION_OVERRIDE mips_option_override
19394 #undef TARGET_LEGITIMIZE_ADDRESS
19395 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
19397 #undef TARGET_ASM_FUNCTION_PROLOGUE
19398 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
19399 #undef TARGET_ASM_FUNCTION_EPILOGUE
19400 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
19401 #undef TARGET_ASM_SELECT_RTX_SECTION
19402 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
19403 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
19404 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
19406 #undef TARGET_SCHED_INIT
19407 #define TARGET_SCHED_INIT mips_sched_init
19408 #undef TARGET_SCHED_REORDER
19409 #define TARGET_SCHED_REORDER mips_sched_reorder
19410 #undef TARGET_SCHED_REORDER2
19411 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
19412 #undef TARGET_SCHED_VARIABLE_ISSUE
19413 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
19414 #undef TARGET_SCHED_ADJUST_COST
19415 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
19416 #undef TARGET_SCHED_ISSUE_RATE
19417 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
19418 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
19419 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
19420 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
19421 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
19422 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
19423 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
19424 mips_multipass_dfa_lookahead
19425 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
19426 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
19427 mips_small_register_classes_for_mode_p
19429 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
19430 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
19432 #undef TARGET_INSERT_ATTRIBUTES
19433 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
19434 #undef TARGET_MERGE_DECL_ATTRIBUTES
19435 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
19436 #undef TARGET_CAN_INLINE_P
19437 #define TARGET_CAN_INLINE_P mips_can_inline_p
19438 #undef TARGET_SET_CURRENT_FUNCTION
19439 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
19441 #undef TARGET_VALID_POINTER_MODE
19442 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
19443 #undef TARGET_REGISTER_MOVE_COST
19444 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
19445 #undef TARGET_REGISTER_PRIORITY
19446 #define TARGET_REGISTER_PRIORITY mips_register_priority
19447 #undef TARGET_MEMORY_MOVE_COST
19448 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
19449 #undef TARGET_RTX_COSTS
19450 #define TARGET_RTX_COSTS mips_rtx_costs
19451 #undef TARGET_ADDRESS_COST
19452 #define TARGET_ADDRESS_COST mips_address_cost
19454 #undef TARGET_IN_SMALL_DATA_P
19455 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
19457 #undef TARGET_MACHINE_DEPENDENT_REORG
19458 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
19460 #undef TARGET_PREFERRED_RELOAD_CLASS
19461 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
19463 #undef TARGET_EXPAND_TO_RTL_HOOK
19464 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
19465 #undef TARGET_ASM_FILE_START
19466 #define TARGET_ASM_FILE_START mips_file_start
19467 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
19468 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
19469 #undef TARGET_ASM_CODE_END
19470 #define TARGET_ASM_CODE_END mips_code_end
19472 #undef TARGET_INIT_LIBFUNCS
19473 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
19475 #undef TARGET_BUILD_BUILTIN_VA_LIST
19476 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
19477 #undef TARGET_EXPAND_BUILTIN_VA_START
19478 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
19479 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
19480 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
19482 #undef TARGET_PROMOTE_FUNCTION_MODE
19483 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
19484 #undef TARGET_PROMOTE_PROTOTYPES
19485 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
19487 #undef TARGET_FUNCTION_VALUE
19488 #define TARGET_FUNCTION_VALUE mips_function_value
19489 #undef TARGET_LIBCALL_VALUE
19490 #define TARGET_LIBCALL_VALUE mips_libcall_value
19491 #undef TARGET_FUNCTION_VALUE_REGNO_P
19492 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19493 #undef TARGET_RETURN_IN_MEMORY
19494 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19495 #undef TARGET_RETURN_IN_MSB
19496 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19498 #undef TARGET_ASM_OUTPUT_MI_THUNK
19499 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19500 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19501 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19503 #undef TARGET_PRINT_OPERAND
19504 #define TARGET_PRINT_OPERAND mips_print_operand
19505 #undef TARGET_PRINT_OPERAND_ADDRESS
19506 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19507 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19508 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19510 #undef TARGET_SETUP_INCOMING_VARARGS
19511 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19512 #undef TARGET_STRICT_ARGUMENT_NAMING
19513 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19514 #undef TARGET_MUST_PASS_IN_STACK
19515 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19516 #undef TARGET_PASS_BY_REFERENCE
19517 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19518 #undef TARGET_CALLEE_COPIES
19519 #define TARGET_CALLEE_COPIES mips_callee_copies
19520 #undef TARGET_ARG_PARTIAL_BYTES
19521 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19522 #undef TARGET_FUNCTION_ARG
19523 #define TARGET_FUNCTION_ARG mips_function_arg
19524 #undef TARGET_FUNCTION_ARG_ADVANCE
19525 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19526 #undef TARGET_FUNCTION_ARG_BOUNDARY
19527 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19528 #undef TARGET_GET_RAW_RESULT_MODE
19529 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
19530 #undef TARGET_GET_RAW_ARG_MODE
19531 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
19533 #undef TARGET_MODE_REP_EXTENDED
19534 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19536 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19537 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19539 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19540 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19542 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19543 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19545 #undef TARGET_INIT_BUILTINS
19546 #define TARGET_INIT_BUILTINS mips_init_builtins
19547 #undef TARGET_BUILTIN_DECL
19548 #define TARGET_BUILTIN_DECL mips_builtin_decl
19549 #undef TARGET_EXPAND_BUILTIN
19550 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19552 #undef TARGET_HAVE_TLS
19553 #define TARGET_HAVE_TLS HAVE_AS_TLS
19555 #undef TARGET_CANNOT_FORCE_CONST_MEM
19556 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19558 #undef TARGET_LEGITIMATE_CONSTANT_P
19559 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19561 #undef TARGET_ENCODE_SECTION_INFO
19562 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19564 #undef TARGET_ATTRIBUTE_TABLE
19565 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19566 /* All our function attributes are related to how out-of-line copies should
19567 be compiled or called. They don't in themselves prevent inlining. */
19568 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19569 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19571 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19572 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19574 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19575 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19576 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19577 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19579 #undef TARGET_COMP_TYPE_ATTRIBUTES
19580 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19582 #ifdef HAVE_AS_DTPRELWORD
19583 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19584 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19586 #undef TARGET_DWARF_REGISTER_SPAN
19587 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19588 #undef TARGET_DWARF_FRAME_REG_MODE
19589 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
19591 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19592 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19594 #undef TARGET_LEGITIMATE_ADDRESS_P
19595 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19597 #undef TARGET_FRAME_POINTER_REQUIRED
19598 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19600 #undef TARGET_CAN_ELIMINATE
19601 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19603 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19604 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19606 #undef TARGET_TRAMPOLINE_INIT
19607 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19609 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19610 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19612 #undef TARGET_SHIFT_TRUNCATION_MASK
19613 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19615 #undef TARGET_PREPARE_PCH_SAVE
19616 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19618 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19619 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19621 #undef TARGET_CASE_VALUES_THRESHOLD
19622 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19624 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19625 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19627 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19628 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19630 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
19631 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
19632 mips_use_by_pieces_infrastructure_p
19634 #undef TARGET_SPILL_CLASS
19635 #define TARGET_SPILL_CLASS mips_spill_class
19636 #undef TARGET_LRA_P
19637 #define TARGET_LRA_P mips_lra_p
19638 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
19639 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
19641 struct gcc_target targetm
= TARGET_INITIALIZER
;
19643 #include "gt-mips.h"