1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "common/common-target.h"
54 #include "langhooks.h"
55 #include "sched-int.h"
58 #include "diagnostic.h"
59 #include "target-globals.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (NONDEBUG_INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Return the opcode for a ptr_mode load of the form:
130 l[wd] DEST, OFFSET(BASE). */
131 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
132 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
137 /* Return the opcode to move register SRC into register DEST. */
138 #define MIPS_MOVE(DEST, SRC) \
139 ((TARGET_64BIT ? 0x2d : 0x21) \
143 /* Return the opcode for:
146 #define MIPS_LUI(DEST, VALUE) \
147 ((0xf << 26) | ((DEST) << 16) | (VALUE))
149 /* Return the opcode to jump to register DEST. */
150 #define MIPS_JR(DEST) \
151 (((DEST) << 21) | 0x8)
153 /* Return the opcode for:
155 bal . + (1 + OFFSET) * 4. */
156 #define MIPS_BAL(OFFSET) \
157 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
159 /* Return the usual opcode for a nop. */
162 /* Classifies an address.
165 A natural register + offset address. The register satisfies
166 mips_valid_base_register_p and the offset is a const_arith_operand.
169 A LO_SUM rtx. The first operand is a valid base register and
170 the second operand is a symbolic address.
173 A signed 16-bit constant address.
176 A constant symbolic address. */
177 enum mips_address_type
{
184 /* Macros to create an enumeration identifier for a function prototype. */
185 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
186 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
187 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
188 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
190 /* Classifies the prototype of a built-in function. */
191 enum mips_function_type
{
192 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
193 #include "config/mips/mips-ftypes.def"
194 #undef DEF_MIPS_FTYPE
198 /* Specifies how a built-in function should be converted into rtl. */
199 enum mips_builtin_type
{
200 /* The function corresponds directly to an .md pattern. The return
201 value is mapped to operand 0 and the arguments are mapped to
202 operands 1 and above. */
205 /* The function corresponds directly to an .md pattern. There is no return
206 value and the arguments are mapped to operands 0 and above. */
207 MIPS_BUILTIN_DIRECT_NO_TARGET
,
209 /* The function corresponds to a comparison instruction followed by
210 a mips_cond_move_tf_ps pattern. The first two arguments are the
211 values to compare and the second two arguments are the vector
212 operands for the movt.ps or movf.ps instruction (in assembly order). */
216 /* The function corresponds to a V2SF comparison instruction. Operand 0
217 of this instruction is the result of the comparison, which has mode
218 CCV2 or CCV4. The function arguments are mapped to operands 1 and
219 above. The function's return value is an SImode boolean that is
220 true under the following conditions:
222 MIPS_BUILTIN_CMP_ANY: one of the registers is true
223 MIPS_BUILTIN_CMP_ALL: all of the registers are true
224 MIPS_BUILTIN_CMP_LOWER: the first register is true
225 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
226 MIPS_BUILTIN_CMP_ANY
,
227 MIPS_BUILTIN_CMP_ALL
,
228 MIPS_BUILTIN_CMP_UPPER
,
229 MIPS_BUILTIN_CMP_LOWER
,
231 /* As above, but the instruction only sets a single $fcc register. */
232 MIPS_BUILTIN_CMP_SINGLE
,
234 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
235 MIPS_BUILTIN_BPOSGE32
238 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
239 #define MIPS_FP_CONDITIONS(MACRO) \
257 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
258 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
259 enum mips_fp_condition
{
260 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
263 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
264 #define STRINGIFY(X) #X
265 static const char *const mips_fp_conditions
[] = {
266 MIPS_FP_CONDITIONS (STRINGIFY
)
269 /* Tuning information that is automatically derived from other sources
270 (such as the scheduler). */
272 /* The architecture and tuning settings that this structure describes. */
276 /* True if this structure describes MIPS16 settings. */
279 /* True if the structure has been initialized. */
282 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
283 when optimizing for speed. */
284 bool fast_mult_zero_zero_p
;
287 /* Information about a function's frame layout. */
288 struct GTY(()) mips_frame_info
{
289 /* The size of the frame in bytes. */
290 HOST_WIDE_INT total_size
;
292 /* The number of bytes allocated to variables. */
293 HOST_WIDE_INT var_size
;
295 /* The number of bytes allocated to outgoing function arguments. */
296 HOST_WIDE_INT args_size
;
298 /* The number of bytes allocated to the .cprestore slot, or 0 if there
300 HOST_WIDE_INT cprestore_size
;
302 /* Bit X is set if the function saves or restores GPR X. */
305 /* Likewise FPR X. */
308 /* Likewise doubleword accumulator X ($acX). */
309 unsigned int acc_mask
;
311 /* The number of GPRs, FPRs, doubleword accumulators and COP0
315 unsigned int num_acc
;
316 unsigned int num_cop0_regs
;
318 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
319 save slots from the top of the frame, or zero if no such slots are
321 HOST_WIDE_INT gp_save_offset
;
322 HOST_WIDE_INT fp_save_offset
;
323 HOST_WIDE_INT acc_save_offset
;
324 HOST_WIDE_INT cop0_save_offset
;
326 /* Likewise, but giving offsets from the bottom of the frame. */
327 HOST_WIDE_INT gp_sp_offset
;
328 HOST_WIDE_INT fp_sp_offset
;
329 HOST_WIDE_INT acc_sp_offset
;
330 HOST_WIDE_INT cop0_sp_offset
;
332 /* Similar, but the value passed to _mcount. */
333 HOST_WIDE_INT ra_fp_offset
;
335 /* The offset of arg_pointer_rtx from the bottom of the frame. */
336 HOST_WIDE_INT arg_pointer_offset
;
338 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
339 HOST_WIDE_INT hard_frame_pointer_offset
;
342 struct GTY(()) machine_function
{
343 /* The next floating-point condition-code register to allocate
344 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
345 unsigned int next_fcc
;
347 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
348 rtx mips16_gp_pseudo_rtx
;
350 /* The number of extra stack bytes taken up by register varargs.
351 This area is allocated by the callee at the very top of the frame. */
354 /* The current frame information, calculated by mips_compute_frame_info. */
355 struct mips_frame_info frame
;
357 /* The register to use as the function's global pointer, or INVALID_REGNUM
358 if the function doesn't need one. */
359 unsigned int global_pointer
;
361 /* How many instructions it takes to load a label into $AT, or 0 if
362 this property hasn't yet been calculated. */
363 unsigned int load_label_num_insns
;
365 /* True if mips_adjust_insn_length should ignore an instruction's
367 bool ignore_hazard_length_p
;
369 /* True if the whole function is suitable for .set noreorder and
371 bool all_noreorder_p
;
373 /* True if the function has "inflexible" and "flexible" references
374 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
375 and mips_cfun_has_flexible_gp_ref_p for details. */
376 bool has_inflexible_gp_insn_p
;
377 bool has_flexible_gp_insn_p
;
379 /* True if the function's prologue must load the global pointer
380 value into pic_offset_table_rtx and store the same value in
381 the function's cprestore slot (if any). Even if this value
382 is currently false, we may decide to set it to true later;
383 see mips_must_initialize_gp_p () for details. */
384 bool must_initialize_gp_p
;
386 /* True if the current function must restore $gp after any potential
387 clobber. This value is only meaningful during the first post-epilogue
388 split_insns pass; see mips_must_initialize_gp_p () for details. */
389 bool must_restore_gp_when_clobbered_p
;
391 /* True if this is an interrupt handler. */
392 bool interrupt_handler_p
;
394 /* True if this is an interrupt handler that uses shadow registers. */
395 bool use_shadow_register_set_p
;
397 /* True if this is an interrupt handler that should keep interrupts
399 bool keep_interrupts_masked_p
;
401 /* True if this is an interrupt handler that should use DERET
403 bool use_debug_exception_return_p
;
406 /* Information about a single argument. */
407 struct mips_arg_info
{
408 /* True if the argument is passed in a floating-point register, or
409 would have been if we hadn't run out of registers. */
412 /* The number of words passed in registers, rounded up. */
413 unsigned int reg_words
;
415 /* For EABI, the offset of the first register from GP_ARG_FIRST or
416 FP_ARG_FIRST. For other ABIs, the offset of the first register from
417 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
418 comment for details).
420 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
422 unsigned int reg_offset
;
424 /* The number of words that must be passed on the stack, rounded up. */
425 unsigned int stack_words
;
427 /* The offset from the start of the stack overflow area of the argument's
428 first stack word. Only meaningful when STACK_WORDS is nonzero. */
429 unsigned int stack_offset
;
432 /* Information about an address described by mips_address_type.
438 REG is the base register and OFFSET is the constant offset.
441 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
442 is the type of symbol it references.
445 SYMBOL_TYPE is the type of symbol that the address references. */
446 struct mips_address_info
{
447 enum mips_address_type type
;
450 enum mips_symbol_type symbol_type
;
453 /* One stage in a constant building sequence. These sequences have
457 A = A CODE[1] VALUE[1]
458 A = A CODE[2] VALUE[2]
461 where A is an accumulator, each CODE[i] is a binary rtl operation
462 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
463 struct mips_integer_op
{
465 unsigned HOST_WIDE_INT value
;
468 /* The largest number of operations needed to load an integer constant.
469 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
470 When the lowest bit is clear, we can try, but reject a sequence with
471 an extra SLL at the end. */
472 #define MIPS_MAX_INTEGER_OPS 7
474 /* Information about a MIPS16e SAVE or RESTORE instruction. */
475 struct mips16e_save_restore_info
{
476 /* The number of argument registers saved by a SAVE instruction.
477 0 for RESTORE instructions. */
480 /* Bit X is set if the instruction saves or restores GPR X. */
483 /* The total number of bytes to allocate. */
487 /* Costs of various operations on the different architectures. */
489 struct mips_rtx_cost_data
491 unsigned short fp_add
;
492 unsigned short fp_mult_sf
;
493 unsigned short fp_mult_df
;
494 unsigned short fp_div_sf
;
495 unsigned short fp_div_df
;
496 unsigned short int_mult_si
;
497 unsigned short int_mult_di
;
498 unsigned short int_div_si
;
499 unsigned short int_div_di
;
500 unsigned short branch_cost
;
501 unsigned short memory_latency
;
504 /* Global variables for machine-dependent things. */
506 /* The -G setting, or the configuration's default small-data limit if
507 no -G option is given. */
508 static unsigned int mips_small_data_threshold
;
510 /* The number of file directives written by mips_output_filename. */
511 int num_source_filenames
;
513 /* The name that appeared in the last .file directive written by
514 mips_output_filename, or "" if mips_output_filename hasn't
515 written anything yet. */
516 const char *current_function_file
= "";
518 /* Arrays that map GCC register numbers to debugger register numbers. */
519 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
520 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
522 /* Information about the current function's epilogue, used only while
525 /* A list of queued REG_CFA_RESTORE notes. */
528 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
530 HOST_WIDE_INT cfa_offset
;
532 /* The offset of the CFA from the stack pointer while restoring
534 HOST_WIDE_INT cfa_restore_sp_offset
;
537 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
538 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
539 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
540 struct mips_asm_switch mips_noat
= { "at", 0 };
542 /* True if we're writing out a branch-likely instruction rather than a
544 static bool mips_branch_likely
;
546 /* The current instruction-set architecture. */
547 enum processor mips_arch
;
548 const struct mips_cpu_info
*mips_arch_info
;
550 /* The processor that we should tune the code for. */
551 enum processor mips_tune
;
552 const struct mips_cpu_info
*mips_tune_info
;
554 /* The ISA level associated with mips_arch. */
557 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
558 static const struct mips_cpu_info
*mips_isa_option_info
;
560 /* Which cost information to use. */
561 static const struct mips_rtx_cost_data
*mips_cost
;
563 /* The ambient target flags, excluding MASK_MIPS16. */
564 static int mips_base_target_flags
;
566 /* True if MIPS16 is the default mode. */
567 bool mips_base_mips16
;
569 /* The ambient values of other global variables. */
570 static int mips_base_schedule_insns
; /* flag_schedule_insns */
571 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
572 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
573 static int mips_base_align_loops
; /* align_loops */
574 static int mips_base_align_jumps
; /* align_jumps */
575 static int mips_base_align_functions
; /* align_functions */
577 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
578 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
580 /* Index C is true if character C is a valid PRINT_OPERAND punctation
582 static bool mips_print_operand_punct
[256];
584 static GTY (()) int mips_output_filename_first_time
= 1;
586 /* mips_split_p[X] is true if symbols of type X can be split by
587 mips_split_symbol. */
588 bool mips_split_p
[NUM_SYMBOL_TYPES
];
590 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
591 can be split by mips_split_symbol. */
592 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
594 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
595 forced into a PC-relative constant pool. */
596 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
598 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
599 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
600 if they are matched by a special .md file pattern. */
601 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
603 /* Likewise for HIGHs. */
604 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
606 /* Target state for MIPS16. */
607 struct target_globals
*mips16_globals
;
609 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
610 and returned from mips_sched_reorder2. */
611 static int cached_can_issue_more
;
613 /* True if the output uses __mips16_rdhwr. */
614 static bool mips_need_mips16_rdhwr_p
;
616 /* Index R is the smallest register class that contains register R. */
617 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
618 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
619 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
620 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
621 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
622 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
623 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
624 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
625 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
626 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
627 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
628 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
629 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
630 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
631 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
632 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
633 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
634 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
635 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
636 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
637 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
638 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
639 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
640 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
641 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
642 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
643 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
644 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
645 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
646 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
647 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
648 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
649 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
650 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
651 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
652 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
653 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
654 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
655 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
656 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
657 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
658 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
659 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
660 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
661 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
662 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
663 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
664 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
667 /* The value of TARGET_ATTRIBUTE_TABLE. */
668 static const struct attribute_spec mips_attribute_table
[] = {
669 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
671 { "long_call", 0, 0, false, true, true, NULL
, false },
672 { "far", 0, 0, false, true, true, NULL
, false },
673 { "near", 0, 0, false, true, true, NULL
, false },
674 /* We would really like to treat "mips16" and "nomips16" as type
675 attributes, but GCC doesn't provide the hooks we need to support
676 the right conversion rules. As declaration attributes, they affect
677 code generation but don't carry other semantics. */
678 { "mips16", 0, 0, true, false, false, NULL
, false },
679 { "nomips16", 0, 0, true, false, false, NULL
, false },
680 /* Allow functions to be specified as interrupt handlers */
681 { "interrupt", 0, 0, false, true, true, NULL
, false },
682 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
683 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
684 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
685 { NULL
, 0, 0, false, false, false, NULL
, false }
688 /* A table describing all the processors GCC knows about; see
689 mips-cpus.def for details. */
690 static const struct mips_cpu_info mips_cpu_info_table
[] = {
691 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
692 { NAME, CPU, ISA, FLAGS },
693 #include "mips-cpus.def"
697 /* Default costs. If these are used for a processor we should look
698 up the actual costs. */
699 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
700 COSTS_N_INSNS (7), /* fp_mult_sf */ \
701 COSTS_N_INSNS (8), /* fp_mult_df */ \
702 COSTS_N_INSNS (23), /* fp_div_sf */ \
703 COSTS_N_INSNS (36), /* fp_div_df */ \
704 COSTS_N_INSNS (10), /* int_mult_si */ \
705 COSTS_N_INSNS (10), /* int_mult_di */ \
706 COSTS_N_INSNS (69), /* int_div_si */ \
707 COSTS_N_INSNS (69), /* int_div_di */ \
708 2, /* branch_cost */ \
709 4 /* memory_latency */
711 /* Floating-point costs for processors without an FPU. Just assume that
712 all floating-point libcalls are very expensive. */
713 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
714 COSTS_N_INSNS (256), /* fp_mult_sf */ \
715 COSTS_N_INSNS (256), /* fp_mult_df */ \
716 COSTS_N_INSNS (256), /* fp_div_sf */ \
717 COSTS_N_INSNS (256) /* fp_div_df */
719 /* Costs to use when optimizing for size. */
720 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
721 COSTS_N_INSNS (1), /* fp_add */
722 COSTS_N_INSNS (1), /* fp_mult_sf */
723 COSTS_N_INSNS (1), /* fp_mult_df */
724 COSTS_N_INSNS (1), /* fp_div_sf */
725 COSTS_N_INSNS (1), /* fp_div_df */
726 COSTS_N_INSNS (1), /* int_mult_si */
727 COSTS_N_INSNS (1), /* int_mult_di */
728 COSTS_N_INSNS (1), /* int_div_si */
729 COSTS_N_INSNS (1), /* int_div_di */
731 4 /* memory_latency */
734 /* Costs to use when optimizing for speed, indexed by processor. */
735 static const struct mips_rtx_cost_data
736 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
738 COSTS_N_INSNS (2), /* fp_add */
739 COSTS_N_INSNS (4), /* fp_mult_sf */
740 COSTS_N_INSNS (5), /* fp_mult_df */
741 COSTS_N_INSNS (12), /* fp_div_sf */
742 COSTS_N_INSNS (19), /* fp_div_df */
743 COSTS_N_INSNS (12), /* int_mult_si */
744 COSTS_N_INSNS (12), /* int_mult_di */
745 COSTS_N_INSNS (35), /* int_div_si */
746 COSTS_N_INSNS (35), /* int_div_di */
748 4 /* memory_latency */
752 COSTS_N_INSNS (6), /* int_mult_si */
753 COSTS_N_INSNS (6), /* int_mult_di */
754 COSTS_N_INSNS (36), /* int_div_si */
755 COSTS_N_INSNS (36), /* int_div_di */
757 4 /* memory_latency */
761 COSTS_N_INSNS (36), /* int_mult_si */
762 COSTS_N_INSNS (36), /* int_mult_di */
763 COSTS_N_INSNS (37), /* int_div_si */
764 COSTS_N_INSNS (37), /* int_div_di */
766 4 /* memory_latency */
770 COSTS_N_INSNS (4), /* int_mult_si */
771 COSTS_N_INSNS (11), /* int_mult_di */
772 COSTS_N_INSNS (36), /* int_div_si */
773 COSTS_N_INSNS (68), /* int_div_di */
775 4 /* memory_latency */
778 COSTS_N_INSNS (4), /* fp_add */
779 COSTS_N_INSNS (4), /* fp_mult_sf */
780 COSTS_N_INSNS (5), /* fp_mult_df */
781 COSTS_N_INSNS (17), /* fp_div_sf */
782 COSTS_N_INSNS (32), /* fp_div_df */
783 COSTS_N_INSNS (4), /* int_mult_si */
784 COSTS_N_INSNS (11), /* int_mult_di */
785 COSTS_N_INSNS (36), /* int_div_si */
786 COSTS_N_INSNS (68), /* int_div_di */
788 4 /* memory_latency */
791 COSTS_N_INSNS (4), /* fp_add */
792 COSTS_N_INSNS (4), /* fp_mult_sf */
793 COSTS_N_INSNS (5), /* fp_mult_df */
794 COSTS_N_INSNS (17), /* fp_div_sf */
795 COSTS_N_INSNS (32), /* fp_div_df */
796 COSTS_N_INSNS (4), /* int_mult_si */
797 COSTS_N_INSNS (7), /* int_mult_di */
798 COSTS_N_INSNS (42), /* int_div_si */
799 COSTS_N_INSNS (72), /* int_div_di */
801 4 /* memory_latency */
805 COSTS_N_INSNS (5), /* int_mult_si */
806 COSTS_N_INSNS (5), /* int_mult_di */
807 COSTS_N_INSNS (41), /* int_div_si */
808 COSTS_N_INSNS (41), /* int_div_di */
810 4 /* memory_latency */
813 COSTS_N_INSNS (8), /* fp_add */
814 COSTS_N_INSNS (8), /* fp_mult_sf */
815 COSTS_N_INSNS (10), /* fp_mult_df */
816 COSTS_N_INSNS (34), /* fp_div_sf */
817 COSTS_N_INSNS (64), /* fp_div_df */
818 COSTS_N_INSNS (5), /* int_mult_si */
819 COSTS_N_INSNS (5), /* int_mult_di */
820 COSTS_N_INSNS (41), /* int_div_si */
821 COSTS_N_INSNS (41), /* int_div_di */
823 4 /* memory_latency */
826 COSTS_N_INSNS (4), /* fp_add */
827 COSTS_N_INSNS (4), /* fp_mult_sf */
828 COSTS_N_INSNS (5), /* fp_mult_df */
829 COSTS_N_INSNS (17), /* fp_div_sf */
830 COSTS_N_INSNS (32), /* fp_div_df */
831 COSTS_N_INSNS (5), /* int_mult_si */
832 COSTS_N_INSNS (5), /* int_mult_di */
833 COSTS_N_INSNS (41), /* int_div_si */
834 COSTS_N_INSNS (41), /* int_div_di */
836 4 /* memory_latency */
840 COSTS_N_INSNS (5), /* int_mult_si */
841 COSTS_N_INSNS (5), /* int_mult_di */
842 COSTS_N_INSNS (41), /* int_div_si */
843 COSTS_N_INSNS (41), /* int_div_di */
845 4 /* memory_latency */
848 COSTS_N_INSNS (8), /* fp_add */
849 COSTS_N_INSNS (8), /* fp_mult_sf */
850 COSTS_N_INSNS (10), /* fp_mult_df */
851 COSTS_N_INSNS (34), /* fp_div_sf */
852 COSTS_N_INSNS (64), /* fp_div_df */
853 COSTS_N_INSNS (5), /* int_mult_si */
854 COSTS_N_INSNS (5), /* int_mult_di */
855 COSTS_N_INSNS (41), /* int_div_si */
856 COSTS_N_INSNS (41), /* int_div_di */
858 4 /* memory_latency */
861 COSTS_N_INSNS (4), /* fp_add */
862 COSTS_N_INSNS (4), /* fp_mult_sf */
863 COSTS_N_INSNS (5), /* fp_mult_df */
864 COSTS_N_INSNS (17), /* fp_div_sf */
865 COSTS_N_INSNS (32), /* fp_div_df */
866 COSTS_N_INSNS (5), /* int_mult_si */
867 COSTS_N_INSNS (5), /* int_mult_di */
868 COSTS_N_INSNS (41), /* int_div_si */
869 COSTS_N_INSNS (41), /* int_div_di */
871 4 /* memory_latency */
874 COSTS_N_INSNS (6), /* fp_add */
875 COSTS_N_INSNS (6), /* fp_mult_sf */
876 COSTS_N_INSNS (7), /* fp_mult_df */
877 COSTS_N_INSNS (25), /* fp_div_sf */
878 COSTS_N_INSNS (48), /* fp_div_df */
879 COSTS_N_INSNS (5), /* int_mult_si */
880 COSTS_N_INSNS (5), /* int_mult_di */
881 COSTS_N_INSNS (41), /* int_div_si */
882 COSTS_N_INSNS (41), /* int_div_di */
884 4 /* memory_latency */
901 COSTS_N_INSNS (5), /* int_mult_si */
902 COSTS_N_INSNS (5), /* int_mult_di */
903 COSTS_N_INSNS (72), /* int_div_si */
904 COSTS_N_INSNS (72), /* int_div_di */
906 4 /* memory_latency */
911 COSTS_N_INSNS (6), /* int_mult_si */
912 COSTS_N_INSNS (6), /* int_mult_di */
913 COSTS_N_INSNS (18), /* int_div_si */
914 COSTS_N_INSNS (35), /* int_div_di */
916 4 /* memory_latency */
919 COSTS_N_INSNS (2), /* fp_add */
920 COSTS_N_INSNS (4), /* fp_mult_sf */
921 COSTS_N_INSNS (5), /* fp_mult_df */
922 COSTS_N_INSNS (12), /* fp_div_sf */
923 COSTS_N_INSNS (19), /* fp_div_df */
924 COSTS_N_INSNS (2), /* int_mult_si */
925 COSTS_N_INSNS (2), /* int_mult_di */
926 COSTS_N_INSNS (35), /* int_div_si */
927 COSTS_N_INSNS (35), /* int_div_di */
929 4 /* memory_latency */
932 COSTS_N_INSNS (3), /* fp_add */
933 COSTS_N_INSNS (5), /* fp_mult_sf */
934 COSTS_N_INSNS (6), /* fp_mult_df */
935 COSTS_N_INSNS (15), /* fp_div_sf */
936 COSTS_N_INSNS (16), /* fp_div_df */
937 COSTS_N_INSNS (17), /* int_mult_si */
938 COSTS_N_INSNS (17), /* int_mult_di */
939 COSTS_N_INSNS (38), /* int_div_si */
940 COSTS_N_INSNS (38), /* int_div_di */
942 6 /* memory_latency */
945 COSTS_N_INSNS (6), /* fp_add */
946 COSTS_N_INSNS (7), /* fp_mult_sf */
947 COSTS_N_INSNS (8), /* fp_mult_df */
948 COSTS_N_INSNS (23), /* fp_div_sf */
949 COSTS_N_INSNS (36), /* fp_div_df */
950 COSTS_N_INSNS (10), /* int_mult_si */
951 COSTS_N_INSNS (10), /* int_mult_di */
952 COSTS_N_INSNS (69), /* int_div_si */
953 COSTS_N_INSNS (69), /* int_div_di */
955 6 /* memory_latency */
967 /* The only costs that appear to be updated here are
968 integer multiplication. */
970 COSTS_N_INSNS (4), /* int_mult_si */
971 COSTS_N_INSNS (6), /* int_mult_di */
972 COSTS_N_INSNS (69), /* int_div_si */
973 COSTS_N_INSNS (69), /* int_div_di */
975 4 /* memory_latency */
990 COSTS_N_INSNS (6), /* fp_add */
991 COSTS_N_INSNS (4), /* fp_mult_sf */
992 COSTS_N_INSNS (5), /* fp_mult_df */
993 COSTS_N_INSNS (23), /* fp_div_sf */
994 COSTS_N_INSNS (36), /* fp_div_df */
995 COSTS_N_INSNS (5), /* int_mult_si */
996 COSTS_N_INSNS (5), /* int_mult_di */
997 COSTS_N_INSNS (36), /* int_div_si */
998 COSTS_N_INSNS (36), /* int_div_di */
1000 4 /* memory_latency */
1003 COSTS_N_INSNS (6), /* fp_add */
1004 COSTS_N_INSNS (5), /* fp_mult_sf */
1005 COSTS_N_INSNS (6), /* fp_mult_df */
1006 COSTS_N_INSNS (30), /* fp_div_sf */
1007 COSTS_N_INSNS (59), /* fp_div_df */
1008 COSTS_N_INSNS (3), /* int_mult_si */
1009 COSTS_N_INSNS (4), /* int_mult_di */
1010 COSTS_N_INSNS (42), /* int_div_si */
1011 COSTS_N_INSNS (74), /* int_div_di */
1012 1, /* branch_cost */
1013 4 /* memory_latency */
1016 COSTS_N_INSNS (6), /* fp_add */
1017 COSTS_N_INSNS (5), /* fp_mult_sf */
1018 COSTS_N_INSNS (6), /* fp_mult_df */
1019 COSTS_N_INSNS (30), /* fp_div_sf */
1020 COSTS_N_INSNS (59), /* fp_div_df */
1021 COSTS_N_INSNS (5), /* int_mult_si */
1022 COSTS_N_INSNS (9), /* int_mult_di */
1023 COSTS_N_INSNS (42), /* int_div_si */
1024 COSTS_N_INSNS (74), /* int_div_di */
1025 1, /* branch_cost */
1026 4 /* memory_latency */
1029 /* The only costs that are changed here are
1030 integer multiplication. */
1031 COSTS_N_INSNS (6), /* fp_add */
1032 COSTS_N_INSNS (7), /* fp_mult_sf */
1033 COSTS_N_INSNS (8), /* fp_mult_df */
1034 COSTS_N_INSNS (23), /* fp_div_sf */
1035 COSTS_N_INSNS (36), /* fp_div_df */
1036 COSTS_N_INSNS (5), /* int_mult_si */
1037 COSTS_N_INSNS (9), /* int_mult_di */
1038 COSTS_N_INSNS (69), /* int_div_si */
1039 COSTS_N_INSNS (69), /* int_div_di */
1040 1, /* branch_cost */
1041 4 /* memory_latency */
1047 /* The only costs that are changed here are
1048 integer multiplication. */
1049 COSTS_N_INSNS (6), /* fp_add */
1050 COSTS_N_INSNS (7), /* fp_mult_sf */
1051 COSTS_N_INSNS (8), /* fp_mult_df */
1052 COSTS_N_INSNS (23), /* fp_div_sf */
1053 COSTS_N_INSNS (36), /* fp_div_df */
1054 COSTS_N_INSNS (3), /* int_mult_si */
1055 COSTS_N_INSNS (8), /* int_mult_di */
1056 COSTS_N_INSNS (69), /* int_div_si */
1057 COSTS_N_INSNS (69), /* int_div_di */
1058 1, /* branch_cost */
1059 4 /* memory_latency */
1062 COSTS_N_INSNS (2), /* fp_add */
1063 COSTS_N_INSNS (2), /* fp_mult_sf */
1064 COSTS_N_INSNS (2), /* fp_mult_df */
1065 COSTS_N_INSNS (12), /* fp_div_sf */
1066 COSTS_N_INSNS (19), /* fp_div_df */
1067 COSTS_N_INSNS (5), /* int_mult_si */
1068 COSTS_N_INSNS (9), /* int_mult_di */
1069 COSTS_N_INSNS (34), /* int_div_si */
1070 COSTS_N_INSNS (66), /* int_div_di */
1071 1, /* branch_cost */
1072 4 /* memory_latency */
1075 /* These costs are the same as the SB-1A below. */
1076 COSTS_N_INSNS (4), /* fp_add */
1077 COSTS_N_INSNS (4), /* fp_mult_sf */
1078 COSTS_N_INSNS (4), /* fp_mult_df */
1079 COSTS_N_INSNS (24), /* fp_div_sf */
1080 COSTS_N_INSNS (32), /* fp_div_df */
1081 COSTS_N_INSNS (3), /* int_mult_si */
1082 COSTS_N_INSNS (4), /* int_mult_di */
1083 COSTS_N_INSNS (36), /* int_div_si */
1084 COSTS_N_INSNS (68), /* int_div_di */
1085 1, /* branch_cost */
1086 4 /* memory_latency */
1089 /* These costs are the same as the SB-1 above. */
1090 COSTS_N_INSNS (4), /* fp_add */
1091 COSTS_N_INSNS (4), /* fp_mult_sf */
1092 COSTS_N_INSNS (4), /* fp_mult_df */
1093 COSTS_N_INSNS (24), /* fp_div_sf */
1094 COSTS_N_INSNS (32), /* fp_div_df */
1095 COSTS_N_INSNS (3), /* int_mult_si */
1096 COSTS_N_INSNS (4), /* int_mult_di */
1097 COSTS_N_INSNS (36), /* int_div_si */
1098 COSTS_N_INSNS (68), /* int_div_di */
1099 1, /* branch_cost */
1100 4 /* memory_latency */
1107 COSTS_N_INSNS (8), /* int_mult_si */
1108 COSTS_N_INSNS (8), /* int_mult_di */
1109 COSTS_N_INSNS (72), /* int_div_si */
1110 COSTS_N_INSNS (72), /* int_div_di */
1111 1, /* branch_cost */
1112 4 /* memory_latency */
1115 /* These costs are the same as 5KF above. */
1116 COSTS_N_INSNS (4), /* fp_add */
1117 COSTS_N_INSNS (4), /* fp_mult_sf */
1118 COSTS_N_INSNS (5), /* fp_mult_df */
1119 COSTS_N_INSNS (17), /* fp_div_sf */
1120 COSTS_N_INSNS (32), /* fp_div_df */
1121 COSTS_N_INSNS (4), /* int_mult_si */
1122 COSTS_N_INSNS (11), /* int_mult_di */
1123 COSTS_N_INSNS (36), /* int_div_si */
1124 COSTS_N_INSNS (68), /* int_div_di */
1125 1, /* branch_cost */
1126 4 /* memory_latency */
1130 static rtx
mips_find_pic_call_symbol (rtx
, rtx
, bool);
1131 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1133 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1135 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1136 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1137 struct GTY (()) mflip_mips16_entry
{
1141 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1143 /* Hash table callbacks for mflip_mips16_htab. */
1146 mflip_mips16_htab_hash (const void *entry
)
1148 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1152 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1154 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1155 (const char *) name
) == 0;
1158 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1159 mode, false if it should next add an attribute for the opposite mode. */
1160 static GTY(()) bool mips16_flipper
;
1162 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1163 for -mflip-mips16. Return true if it should use "mips16" and false if
1164 it should use "nomips16". */
1167 mflip_mips16_use_mips16_p (tree decl
)
1169 struct mflip_mips16_entry
*entry
;
1174 /* Use the opposite of the command-line setting for anonymous decls. */
1175 if (!DECL_NAME (decl
))
1176 return !mips_base_mips16
;
1178 if (!mflip_mips16_htab
)
1179 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1180 mflip_mips16_htab_eq
, NULL
);
1182 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1183 hash
= htab_hash_string (name
);
1184 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1185 entry
= (struct mflip_mips16_entry
*) *slot
;
1188 mips16_flipper
= !mips16_flipper
;
1189 entry
= ggc_alloc_mflip_mips16_entry ();
1191 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1194 return entry
->mips16_p
;
1197 /* Predicates to test for presence of "near" and "far"/"long_call"
1198 attributes on the given TYPE. */
1201 mips_near_type_p (const_tree type
)
1203 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1207 mips_far_type_p (const_tree type
)
1209 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1210 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1213 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1216 mips_mips16_decl_p (const_tree decl
)
1218 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1222 mips_nomips16_decl_p (const_tree decl
)
1224 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1227 /* Check if the interrupt attribute is set for a function. */
1230 mips_interrupt_type_p (tree type
)
1232 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1235 /* Check if the attribute to use shadow register set is set for a function. */
1238 mips_use_shadow_register_set_p (tree type
)
1240 return lookup_attribute ("use_shadow_register_set",
1241 TYPE_ATTRIBUTES (type
)) != NULL
;
1244 /* Check if the attribute to keep interrupts masked is set for a function. */
1247 mips_keep_interrupts_masked_p (tree type
)
1249 return lookup_attribute ("keep_interrupts_masked",
1250 TYPE_ATTRIBUTES (type
)) != NULL
;
1253 /* Check if the attribute to use debug exception return is set for
1257 mips_use_debug_exception_return_p (tree type
)
1259 return lookup_attribute ("use_debug_exception_return",
1260 TYPE_ATTRIBUTES (type
)) != NULL
;
1263 /* Return true if function DECL is a MIPS16 function. Return the ambient
1264 setting if DECL is null. */
1267 mips_use_mips16_mode_p (tree decl
)
1271 /* Nested functions must use the same frame pointer as their
1272 parent and must therefore use the same ISA mode. */
1273 tree parent
= decl_function_context (decl
);
1276 if (mips_mips16_decl_p (decl
))
1278 if (mips_nomips16_decl_p (decl
))
1281 return mips_base_mips16
;
1284 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1287 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1289 /* Disallow mixed near/far attributes. */
1290 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1292 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1297 /* Implement TARGET_INSERT_ATTRIBUTES. */
1300 mips_insert_attributes (tree decl
, tree
*attributes
)
1303 bool mips16_p
, nomips16_p
;
1305 /* Check for "mips16" and "nomips16" attributes. */
1306 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1307 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1308 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1311 error ("%qs attribute only applies to functions", "mips16");
1313 error ("%qs attribute only applies to functions", "nomips16");
1317 mips16_p
|= mips_mips16_decl_p (decl
);
1318 nomips16_p
|= mips_nomips16_decl_p (decl
);
1319 if (mips16_p
|| nomips16_p
)
1321 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1322 if (mips16_p
&& nomips16_p
)
1323 error ("%qE cannot have both %<mips16%> and "
1324 "%<nomips16%> attributes",
1327 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1329 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1330 "mips16" attribute, arbitrarily pick one. We must pick the same
1331 setting for duplicate declarations of a function. */
1332 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1333 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1338 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1341 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1343 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1344 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1345 error ("%qE redeclared with conflicting %qs attributes",
1346 DECL_NAME (newdecl
), "mips16");
1347 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1348 error ("%qE redeclared with conflicting %qs attributes",
1349 DECL_NAME (newdecl
), "nomips16");
1351 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1352 DECL_ATTRIBUTES (newdecl
));
1355 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1356 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1359 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1361 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1363 *base_ptr
= XEXP (x
, 0);
1364 *offset_ptr
= INTVAL (XEXP (x
, 1));
1373 static unsigned int mips_build_integer (struct mips_integer_op
*,
1374 unsigned HOST_WIDE_INT
);
1376 /* A subroutine of mips_build_integer, with the same interface.
1377 Assume that the final action in the sequence should be a left shift. */
1380 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1382 unsigned int i
, shift
;
1384 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1385 since signed numbers are easier to load than unsigned ones. */
1387 while ((value
& 1) == 0)
1388 value
/= 2, shift
++;
1390 i
= mips_build_integer (codes
, value
);
1391 codes
[i
].code
= ASHIFT
;
1392 codes
[i
].value
= shift
;
1396 /* As for mips_build_shift, but assume that the final action will be
1397 an IOR or PLUS operation. */
1400 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1402 unsigned HOST_WIDE_INT high
;
1405 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1406 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1408 /* The constant is too complex to load with a simple LUI/ORI pair,
1409 so we want to give the recursive call as many trailing zeros as
1410 possible. In this case, we know bit 16 is set and that the
1411 low 16 bits form a negative number. If we subtract that number
1412 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1413 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1414 codes
[i
].code
= PLUS
;
1415 codes
[i
].value
= CONST_LOW_PART (value
);
1419 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1420 bits gives a value with at least 17 trailing zeros. */
1421 i
= mips_build_integer (codes
, high
);
1422 codes
[i
].code
= IOR
;
1423 codes
[i
].value
= value
& 0xffff;
1428 /* Fill CODES with a sequence of rtl operations to load VALUE.
1429 Return the number of operations needed. */
1432 mips_build_integer (struct mips_integer_op
*codes
,
1433 unsigned HOST_WIDE_INT value
)
1435 if (SMALL_OPERAND (value
)
1436 || SMALL_OPERAND_UNSIGNED (value
)
1437 || LUI_OPERAND (value
))
1439 /* The value can be loaded with a single instruction. */
1440 codes
[0].code
= UNKNOWN
;
1441 codes
[0].value
= value
;
1444 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1446 /* Either the constant is a simple LUI/ORI combination or its
1447 lowest bit is set. We don't want to shift in this case. */
1448 return mips_build_lower (codes
, value
);
1450 else if ((value
& 0xffff) == 0)
1452 /* The constant will need at least three actions. The lowest
1453 16 bits are clear, so the final action will be a shift. */
1454 return mips_build_shift (codes
, value
);
1458 /* The final action could be a shift, add or inclusive OR.
1459 Rather than use a complex condition to select the best
1460 approach, try both mips_build_shift and mips_build_lower
1461 and pick the one that gives the shortest sequence.
1462 Note that this case is only used once per constant. */
1463 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1464 unsigned int cost
, alt_cost
;
1466 cost
= mips_build_shift (codes
, value
);
1467 alt_cost
= mips_build_lower (alt_codes
, value
);
1468 if (alt_cost
< cost
)
1470 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1477 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1480 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1482 return mips_const_insns (x
) > 0;
1485 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1488 mips16_stub_function (const char *name
)
1492 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1493 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1497 /* Return true if symbols of type TYPE require a GOT access. */
1500 mips_got_symbol_type_p (enum mips_symbol_type type
)
1504 case SYMBOL_GOT_PAGE_OFST
:
1505 case SYMBOL_GOT_DISP
:
1513 /* Return true if X is a thread-local symbol. */
1516 mips_tls_symbol_p (rtx x
)
1518 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1521 /* Return true if SYMBOL_REF X is associated with a global symbol
1522 (in the STB_GLOBAL sense). */
1525 mips_global_symbol_p (const_rtx x
)
1527 const_tree decl
= SYMBOL_REF_DECL (x
);
1530 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1532 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1533 or weak symbols. Relocations in the object file will be against
1534 the target symbol, so it's that symbol's binding that matters here. */
1535 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1538 /* Return true if function X is a libgcc MIPS16 stub function. */
1541 mips16_stub_function_p (const_rtx x
)
1543 return (GET_CODE (x
) == SYMBOL_REF
1544 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1547 /* Return true if function X is a locally-defined and locally-binding
1551 mips16_local_function_p (const_rtx x
)
1553 return (GET_CODE (x
) == SYMBOL_REF
1554 && SYMBOL_REF_LOCAL_P (x
)
1555 && !SYMBOL_REF_EXTERNAL_P (x
)
1556 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x
)));
1559 /* Return true if SYMBOL_REF X binds locally. */
1562 mips_symbol_binds_local_p (const_rtx x
)
1564 return (SYMBOL_REF_DECL (x
)
1565 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1566 : SYMBOL_REF_LOCAL_P (x
));
1569 /* Return true if rtx constants of mode MODE should be put into a small
1573 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1575 return (!TARGET_EMBEDDED_DATA
1576 && TARGET_LOCAL_SDATA
1577 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1580 /* Return true if X should not be moved directly into register $25.
1581 We need this because many versions of GAS will treat "la $25,foo" as
1582 part of a call sequence and so allow a global "foo" to be lazily bound. */
1585 mips_dangerous_for_la25_p (rtx x
)
1587 return (!TARGET_EXPLICIT_RELOCS
1589 && GET_CODE (x
) == SYMBOL_REF
1590 && mips_global_symbol_p (x
));
1593 /* Return true if calls to X might need $25 to be valid on entry. */
1596 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1598 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1601 /* MIPS16 stub functions are guaranteed not to use $25. */
1602 if (mips16_stub_function_p (x
))
1605 if (GET_CODE (x
) == SYMBOL_REF
)
1607 /* If PLTs and copy relocations are available, the static linker
1608 will make sure that $25 is valid on entry to the target function. */
1609 if (TARGET_ABICALLS_PIC0
)
1612 /* Locally-defined functions use absolute accesses to set up
1613 the global pointer. */
1614 if (TARGET_ABSOLUTE_ABICALLS
1615 && mips_symbol_binds_local_p (x
)
1616 && !SYMBOL_REF_EXTERNAL_P (x
))
1623 /* Return the method that should be used to access SYMBOL_REF or
1624 LABEL_REF X in context CONTEXT. */
1626 static enum mips_symbol_type
1627 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1630 return SYMBOL_GOT_DISP
;
1632 if (GET_CODE (x
) == LABEL_REF
)
1634 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1635 code and if we know that the label is in the current function's
1636 text section. LABEL_REFs are used for jump tables as well as
1637 text labels, so we must check whether jump tables live in the
1639 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1640 && !LABEL_REF_NONLOCAL_P (x
))
1641 return SYMBOL_PC_RELATIVE
;
1643 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1644 return SYMBOL_GOT_PAGE_OFST
;
1646 return SYMBOL_ABSOLUTE
;
1649 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1651 if (SYMBOL_REF_TLS_MODEL (x
))
1654 if (CONSTANT_POOL_ADDRESS_P (x
))
1656 if (TARGET_MIPS16_TEXT_LOADS
)
1657 return SYMBOL_PC_RELATIVE
;
1659 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1660 return SYMBOL_PC_RELATIVE
;
1662 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1663 return SYMBOL_GP_RELATIVE
;
1666 /* Do not use small-data accesses for weak symbols; they may end up
1668 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1669 return SYMBOL_GP_RELATIVE
;
1671 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1673 if (TARGET_ABICALLS_PIC2
1674 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1676 /* There are three cases to consider:
1678 - o32 PIC (either with or without explicit relocs)
1679 - n32/n64 PIC without explicit relocs
1680 - n32/n64 PIC with explicit relocs
1682 In the first case, both local and global accesses will use an
1683 R_MIPS_GOT16 relocation. We must correctly predict which of
1684 the two semantics (local or global) the assembler and linker
1685 will apply. The choice depends on the symbol's binding rather
1686 than its visibility.
1688 In the second case, the assembler will not use R_MIPS_GOT16
1689 relocations, but it chooses between local and global accesses
1690 in the same way as for o32 PIC.
1692 In the third case we have more freedom since both forms of
1693 access will work for any kind of symbol. However, there seems
1694 little point in doing things differently. */
1695 if (mips_global_symbol_p (x
))
1696 return SYMBOL_GOT_DISP
;
1698 return SYMBOL_GOT_PAGE_OFST
;
1701 return SYMBOL_ABSOLUTE
;
1704 /* Classify the base of symbolic expression X, given that X appears in
1707 static enum mips_symbol_type
1708 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1712 split_const (x
, &x
, &offset
);
1713 if (UNSPEC_ADDRESS_P (x
))
1714 return UNSPEC_ADDRESS_TYPE (x
);
1716 return mips_classify_symbol (x
, context
);
1719 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1720 is the alignment in bytes of SYMBOL_REF X. */
1723 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1725 HOST_WIDE_INT align
;
1727 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1728 return IN_RANGE (offset
, 0, align
- 1);
1731 /* Return true if X is a symbolic constant that can be used in context
1732 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1735 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1736 enum mips_symbol_type
*symbol_type
)
1740 split_const (x
, &x
, &offset
);
1741 if (UNSPEC_ADDRESS_P (x
))
1743 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1744 x
= UNSPEC_ADDRESS (x
);
1746 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1748 *symbol_type
= mips_classify_symbol (x
, context
);
1749 if (*symbol_type
== SYMBOL_TLS
)
1755 if (offset
== const0_rtx
)
1758 /* Check whether a nonzero offset is valid for the underlying
1760 switch (*symbol_type
)
1762 case SYMBOL_ABSOLUTE
:
1763 case SYMBOL_64_HIGH
:
1766 /* If the target has 64-bit pointers and the object file only
1767 supports 32-bit symbols, the values of those symbols will be
1768 sign-extended. In this case we can't allow an arbitrary offset
1769 in case the 32-bit value X + OFFSET has a different sign from X. */
1770 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1771 return offset_within_block_p (x
, INTVAL (offset
));
1773 /* In other cases the relocations can handle any offset. */
1776 case SYMBOL_PC_RELATIVE
:
1777 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1778 In this case, we no longer have access to the underlying constant,
1779 but the original symbol-based access was known to be valid. */
1780 if (GET_CODE (x
) == LABEL_REF
)
1785 case SYMBOL_GP_RELATIVE
:
1786 /* Make sure that the offset refers to something within the
1787 same object block. This should guarantee that the final
1788 PC- or GP-relative offset is within the 16-bit limit. */
1789 return offset_within_block_p (x
, INTVAL (offset
));
1791 case SYMBOL_GOT_PAGE_OFST
:
1792 case SYMBOL_GOTOFF_PAGE
:
1793 /* If the symbol is global, the GOT entry will contain the symbol's
1794 address, and we will apply a 16-bit offset after loading it.
1795 If the symbol is local, the linker should provide enough local
1796 GOT entries for a 16-bit offset, but larger offsets may lead
1798 return SMALL_INT (offset
);
1802 /* There is no carry between the HI and LO REL relocations, so the
1803 offset is only valid if we know it won't lead to such a carry. */
1804 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1806 case SYMBOL_GOT_DISP
:
1807 case SYMBOL_GOTOFF_DISP
:
1808 case SYMBOL_GOTOFF_CALL
:
1809 case SYMBOL_GOTOFF_LOADGP
:
1812 case SYMBOL_GOTTPREL
:
1820 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1821 single instruction. We rely on the fact that, in the worst case,
1822 all instructions involved in a MIPS16 address calculation are usually
1826 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1828 if (mips_use_pcrel_pool_p
[(int) type
])
1830 if (mode
== MAX_MACHINE_MODE
)
1831 /* LEAs will be converted into constant-pool references by
1833 type
= SYMBOL_PC_RELATIVE
;
1835 /* The constant must be loaded and then dereferenced. */
1841 case SYMBOL_ABSOLUTE
:
1842 /* When using 64-bit symbols, we need 5 preparatory instructions,
1845 lui $at,%highest(symbol)
1846 daddiu $at,$at,%higher(symbol)
1848 daddiu $at,$at,%hi(symbol)
1851 The final address is then $at + %lo(symbol). With 32-bit
1852 symbols we just need a preparatory LUI for normal mode and
1853 a preparatory LI and SLL for MIPS16. */
1854 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1856 case SYMBOL_GP_RELATIVE
:
1857 /* Treat GP-relative accesses as taking a single instruction on
1858 MIPS16 too; the copy of $gp can often be shared. */
1861 case SYMBOL_PC_RELATIVE
:
1862 /* PC-relative constants can be only be used with ADDIUPC,
1863 DADDIUPC, LWPC and LDPC. */
1864 if (mode
== MAX_MACHINE_MODE
1865 || GET_MODE_SIZE (mode
) == 4
1866 || GET_MODE_SIZE (mode
) == 8)
1869 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1872 case SYMBOL_GOT_DISP
:
1873 /* The constant will have to be loaded from the GOT before it
1874 is used in an address. */
1875 if (mode
!= MAX_MACHINE_MODE
)
1880 case SYMBOL_GOT_PAGE_OFST
:
1881 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1882 local/global classification is accurate. The worst cases are:
1884 (1) For local symbols when generating o32 or o64 code. The assembler
1890 ...and the final address will be $at + %lo(symbol).
1892 (2) For global symbols when -mxgot. The assembler will use:
1894 lui $at,%got_hi(symbol)
1897 ...and the final address will be $at + %got_lo(symbol). */
1900 case SYMBOL_GOTOFF_PAGE
:
1901 case SYMBOL_GOTOFF_DISP
:
1902 case SYMBOL_GOTOFF_CALL
:
1903 case SYMBOL_GOTOFF_LOADGP
:
1904 case SYMBOL_64_HIGH
:
1910 case SYMBOL_GOTTPREL
:
1913 /* A 16-bit constant formed by a single relocation, or a 32-bit
1914 constant formed from a high 16-bit relocation and a low 16-bit
1915 relocation. Use mips_split_p to determine which. 32-bit
1916 constants need an "lui; addiu" sequence for normal mode and
1917 an "li; sll; addiu" sequence for MIPS16 mode. */
1918 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1921 /* We don't treat a bare TLS symbol as a constant. */
1927 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1928 to load symbols of type TYPE into a register. Return 0 if the given
1929 type of symbol cannot be used as an immediate operand.
1931 Otherwise, return the number of instructions needed to load or store
1932 values of mode MODE to or from addresses of type TYPE. Return 0 if
1933 the given type of symbol is not valid in addresses.
1935 In both cases, treat extended MIPS16 instructions as two instructions. */
1938 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1940 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1943 /* A for_each_rtx callback. Stop the search if *X references a
1944 thread-local symbol. */
1947 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1949 return mips_tls_symbol_p (*x
);
1952 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1955 mips_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
1957 enum mips_symbol_type type
;
1960 /* There is no assembler syntax for expressing an address-sized
1962 if (GET_CODE (x
) == HIGH
)
1965 /* As an optimization, reject constants that mips_legitimize_move
1968 Suppose we have a multi-instruction sequence that loads constant C
1969 into register R. If R does not get allocated a hard register, and
1970 R is used in an operand that allows both registers and memory
1971 references, reload will consider forcing C into memory and using
1972 one of the instruction's memory alternatives. Returning false
1973 here will force it to use an input reload instead. */
1974 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
1977 split_const (x
, &base
, &offset
);
1978 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
1980 /* See whether we explicitly want these symbols in the pool. */
1981 if (mips_use_pcrel_pool_p
[(int) type
])
1984 /* The same optimization as for CONST_INT. */
1985 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
1988 /* If MIPS16 constant pools live in the text section, they should
1989 not refer to anything that might need run-time relocation. */
1990 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
1994 /* TLS symbols must be computed by mips_legitimize_move. */
1995 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2001 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2002 constants when we're using a per-function constant pool. */
2005 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2006 const_rtx x ATTRIBUTE_UNUSED
)
2008 return !TARGET_MIPS16_PCREL_LOADS
;
2011 /* Return true if register REGNO is a valid base register for mode MODE.
2012 STRICT_P is true if REG_OK_STRICT is in effect. */
2015 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2018 if (!HARD_REGISTER_NUM_P (regno
))
2022 regno
= reg_renumber
[regno
];
2025 /* These fake registers will be eliminated to either the stack or
2026 hard frame pointer, both of which are usually valid base registers.
2027 Reload deals with the cases where the eliminated form isn't valid. */
2028 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2031 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2032 values, nothing smaller. There are two problems here:
2034 (a) Instantiating virtual registers can introduce new uses of the
2035 stack pointer. If these virtual registers are valid addresses,
2036 the stack pointer should be too.
2038 (b) Most uses of the stack pointer are not made explicit until
2039 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2040 We don't know until that stage whether we'll be eliminating to the
2041 stack pointer (which needs the restriction) or the hard frame
2042 pointer (which doesn't).
2044 All in all, it seems more consistent to only enforce this restriction
2045 during and after reload. */
2046 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2047 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2049 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2052 /* Return true if X is a valid base register for mode MODE.
2053 STRICT_P is true if REG_OK_STRICT is in effect. */
2056 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2058 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2062 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2065 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2066 can address a value of mode MODE. */
2069 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2071 /* Check that X is a signed 16-bit number. */
2072 if (!const_arith_operand (x
, Pmode
))
2075 /* We may need to split multiword moves, so make sure that every word
2077 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2078 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2084 /* Return true if a LO_SUM can address a value of mode MODE when the
2085 LO_SUM symbol has type SYMBOL_TYPE. */
2088 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2090 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2092 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2095 /* Check that there is a known low-part relocation. */
2096 if (mips_lo_relocs
[symbol_type
] == NULL
)
2099 /* We may need to split multiword moves, so make sure that each word
2100 can be accessed without inducing a carry. This is mainly needed
2101 for o64, which has historically only guaranteed 64-bit alignment
2102 for 128-bit types. */
2103 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2104 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2110 /* Return true if X is a valid address for machine mode MODE. If it is,
2111 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2115 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2116 enum machine_mode mode
, bool strict_p
)
2118 switch (GET_CODE (x
))
2122 info
->type
= ADDRESS_REG
;
2124 info
->offset
= const0_rtx
;
2125 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2128 info
->type
= ADDRESS_REG
;
2129 info
->reg
= XEXP (x
, 0);
2130 info
->offset
= XEXP (x
, 1);
2131 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2132 && mips_valid_offset_p (info
->offset
, mode
));
2135 info
->type
= ADDRESS_LO_SUM
;
2136 info
->reg
= XEXP (x
, 0);
2137 info
->offset
= XEXP (x
, 1);
2138 /* We have to trust the creator of the LO_SUM to do something vaguely
2139 sane. Target-independent code that creates a LO_SUM should also
2140 create and verify the matching HIGH. Target-independent code that
2141 adds an offset to a LO_SUM must prove that the offset will not
2142 induce a carry. Failure to do either of these things would be
2143 a bug, and we are not required to check for it here. The MIPS
2144 backend itself should only create LO_SUMs for valid symbolic
2145 constants, with the high part being either a HIGH or a copy
2148 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2149 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2150 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2153 /* Small-integer addresses don't occur very often, but they
2154 are legitimate if $0 is a valid base register. */
2155 info
->type
= ADDRESS_CONST_INT
;
2156 return !TARGET_MIPS16
&& SMALL_INT (x
);
2161 info
->type
= ADDRESS_SYMBOLIC
;
2162 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2164 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2165 && !mips_split_p
[info
->symbol_type
]);
2172 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2175 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2177 struct mips_address_info addr
;
2179 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2182 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2185 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2187 struct mips_address_info addr
;
2189 return (mips_classify_address (&addr
, x
, mode
, false)
2190 && addr
.type
== ADDRESS_REG
2191 && addr
.reg
== stack_pointer_rtx
);
2194 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2195 address instruction. Note that such addresses are not considered
2196 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2197 is so restricted. */
2200 mips_lwxs_address_p (rtx addr
)
2203 && GET_CODE (addr
) == PLUS
2204 && REG_P (XEXP (addr
, 1)))
2206 rtx offset
= XEXP (addr
, 0);
2207 if (GET_CODE (offset
) == MULT
2208 && REG_P (XEXP (offset
, 0))
2209 && CONST_INT_P (XEXP (offset
, 1))
2210 && INTVAL (XEXP (offset
, 1)) == 4)
2216 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2217 indexed address instruction. Note that such addresses are
2218 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2219 sense, because their use is so restricted. */
2222 mips_lx_address_p (rtx addr
, enum machine_mode mode
)
2224 if (GET_CODE (addr
) != PLUS
2225 || !REG_P (XEXP (addr
, 0))
2226 || !REG_P (XEXP (addr
, 1)))
2228 if (ISA_HAS_LBX
&& mode
== QImode
)
2230 if (ISA_HAS_LHX
&& mode
== HImode
)
2232 if (ISA_HAS_LWX
&& mode
== SImode
)
2234 if (ISA_HAS_LDX
&& mode
== DImode
)
2239 /* Return true if a value at OFFSET bytes from base register BASE can be
2240 accessed using an unextended MIPS16 instruction. MODE is the mode of
2243 Usually the offset in an unextended instruction is a 5-bit field.
2244 The offset is unsigned and shifted left once for LH and SH, twice
2245 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2246 an 8-bit immediate field that's shifted left twice. */
2249 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2250 unsigned HOST_WIDE_INT offset
)
2252 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2254 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2255 return offset
< 256U * GET_MODE_SIZE (mode
);
2256 return offset
< 32U * GET_MODE_SIZE (mode
);
2261 /* Return the number of instructions needed to load or store a value
2262 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2263 Assume that multiword moves may need to be split into word moves
2264 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2267 For MIPS16 code, count extended instructions as two instructions. */
2270 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2272 struct mips_address_info addr
;
2275 /* BLKmode is used for single unaligned loads and stores and should
2276 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2277 meaningless, so we have to single it out as a special case one way
2279 if (mode
!= BLKmode
&& might_split_p
)
2280 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2284 if (mips_classify_address (&addr
, x
, mode
, false))
2289 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2290 UINTVAL (addr
.offset
)))
2294 case ADDRESS_LO_SUM
:
2295 return TARGET_MIPS16
? factor
* 2 : factor
;
2297 case ADDRESS_CONST_INT
:
2300 case ADDRESS_SYMBOLIC
:
2301 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2306 /* Return the number of instructions needed to load constant X.
2307 Return 0 if X isn't a valid constant. */
2310 mips_const_insns (rtx x
)
2312 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2313 enum mips_symbol_type symbol_type
;
2316 switch (GET_CODE (x
))
2319 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2321 || !mips_split_p
[symbol_type
])
2324 /* This is simply an LUI for normal mode. It is an extended
2325 LI followed by an extended SLL for MIPS16. */
2326 return TARGET_MIPS16
? 4 : 1;
2330 /* Unsigned 8-bit constants can be loaded using an unextended
2331 LI instruction. Unsigned 16-bit constants can be loaded
2332 using an extended LI. Negative constants must be loaded
2333 using LI and then negated. */
2334 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2335 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2336 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2337 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2340 return mips_build_integer (codes
, INTVAL (x
));
2344 /* Allow zeros for normal mode, where we can use $0. */
2345 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2351 /* See if we can refer to X directly. */
2352 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2353 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2355 /* Otherwise try splitting the constant into a base and offset.
2356 If the offset is a 16-bit value, we can load the base address
2357 into a register and then use (D)ADDIU to add in the offset.
2358 If the offset is larger, we can load the base and offset
2359 into separate registers and add them together with (D)ADDU.
2360 However, the latter is only possible before reload; during
2361 and after reload, we must have the option of forcing the
2362 constant into the pool instead. */
2363 split_const (x
, &x
, &offset
);
2366 int n
= mips_const_insns (x
);
2369 if (SMALL_INT (offset
))
2371 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2372 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2379 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2387 /* X is a doubleword constant that can be handled by splitting it into
2388 two words and loading each word separately. Return the number of
2389 instructions required to do this. */
2392 mips_split_const_insns (rtx x
)
2394 unsigned int low
, high
;
2396 low
= mips_const_insns (mips_subword (x
, false));
2397 high
= mips_const_insns (mips_subword (x
, true));
2398 gcc_assert (low
> 0 && high
> 0);
2402 /* Return the number of instructions needed to implement INSN,
2403 given that it loads from or stores to MEM. Count extended
2404 MIPS16 instructions as two instructions. */
2407 mips_load_store_insns (rtx mem
, rtx insn
)
2409 enum machine_mode mode
;
2413 gcc_assert (MEM_P (mem
));
2414 mode
= GET_MODE (mem
);
2416 /* Try to prove that INSN does not need to be split. */
2417 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2420 set
= single_set (insn
);
2421 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2422 might_split_p
= false;
2425 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2428 /* Return the number of instructions needed for an integer division. */
2431 mips_idiv_insns (void)
2436 if (TARGET_CHECK_ZERO_DIV
)
2438 if (GENERATE_DIVIDE_TRAPS
)
2444 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2449 /* Emit a move from SRC to DEST. Assume that the move expanders can
2450 handle all moves if !can_create_pseudo_p (). The distinction is
2451 important because, unlike emit_move_insn, the move expanders know
2452 how to force Pmode objects into the constant pool even when the
2453 constant pool address is not itself legitimate. */
2456 mips_emit_move (rtx dest
, rtx src
)
2458 return (can_create_pseudo_p ()
2459 ? emit_move_insn (dest
, src
)
2460 : emit_move_insn_1 (dest
, src
));
2463 /* Emit a move from SRC to DEST, splitting compound moves into individual
2464 instructions. SPLIT_TYPE is the type of split to perform. */
2467 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
2469 if (mips_split_move_p (dest
, src
, split_type
))
2470 mips_split_move (dest
, src
, split_type
);
2472 mips_emit_move (dest
, src
);
2475 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2478 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2480 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2481 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2484 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2485 Return that new register. */
2488 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2492 reg
= gen_reg_rtx (mode
);
2493 mips_emit_unary (code
, reg
, op0
);
2497 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2500 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2502 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2503 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2506 /* Compute (CODE OP0 OP1) and store the result in a new register
2507 of mode MODE. Return that new register. */
2510 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2514 reg
= gen_reg_rtx (mode
);
2515 mips_emit_binary (code
, reg
, op0
, op1
);
2519 /* Copy VALUE to a register and return that register. If new pseudos
2520 are allowed, copy it into a new register, otherwise use DEST. */
2523 mips_force_temporary (rtx dest
, rtx value
)
2525 if (can_create_pseudo_p ())
2526 return force_reg (Pmode
, value
);
2529 mips_emit_move (dest
, value
);
2534 /* Emit a call sequence with call pattern PATTERN and return the call
2535 instruction itself (which is not necessarily the last instruction
2536 emitted). ORIG_ADDR is the original, unlegitimized address,
2537 ADDR is the legitimized form, and LAZY_P is true if the call
2538 address is lazily-bound. */
2541 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2545 insn
= emit_call_insn (pattern
);
2547 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2549 /* MIPS16 JALRs only take MIPS16 registers. If the target
2550 function requires $25 to be valid on entry, we must copy it
2551 there separately. The move instruction can be put in the
2552 call's delay slot. */
2553 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2554 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2555 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2559 /* Lazy-binding stubs require $gp to be valid on entry. */
2560 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2564 /* See the comment above load_call<mode> for details. */
2565 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2566 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2567 emit_insn (gen_update_got_version ());
2572 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2573 then add CONST_INT OFFSET to the result. */
2576 mips_unspec_address_offset (rtx base
, rtx offset
,
2577 enum mips_symbol_type symbol_type
)
2579 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2580 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2581 if (offset
!= const0_rtx
)
2582 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2583 return gen_rtx_CONST (Pmode
, base
);
2586 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2587 type SYMBOL_TYPE. */
2590 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2594 split_const (address
, &base
, &offset
);
2595 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2598 /* If OP is an UNSPEC address, return the address to which it refers,
2599 otherwise return OP itself. */
2602 mips_strip_unspec_address (rtx op
)
2606 split_const (op
, &base
, &offset
);
2607 if (UNSPEC_ADDRESS_P (base
))
2608 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
2612 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2613 high part to BASE and return the result. Just return BASE otherwise.
2614 TEMP is as for mips_force_temporary.
2616 The returned expression can be used as the first operand to a LO_SUM. */
2619 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2620 enum mips_symbol_type symbol_type
)
2622 if (mips_split_p
[symbol_type
])
2624 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2625 addr
= mips_force_temporary (temp
, addr
);
2626 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2631 /* Return an instruction that copies $gp into register REG. We want
2632 GCC to treat the register's value as constant, so that its value
2633 can be rematerialized on demand. */
2636 gen_load_const_gp (rtx reg
)
2638 return PMODE_INSN (gen_load_const_gp
, (reg
));
2641 /* Return a pseudo register that contains the value of $gp throughout
2642 the current function. Such registers are needed by MIPS16 functions,
2643 for which $gp itself is not a valid base register or addition operand. */
2646 mips16_gp_pseudo_reg (void)
2648 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2652 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2654 push_topmost_sequence ();
2656 scan
= get_insns ();
2657 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2658 scan
= NEXT_INSN (scan
);
2660 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2661 insn
= emit_insn_after (insn
, scan
);
2662 INSN_LOCATION (insn
) = 0;
2664 pop_topmost_sequence ();
2667 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2670 /* Return a base register that holds pic_offset_table_rtx.
2671 TEMP, if nonnull, is a scratch Pmode base register. */
2674 mips_pic_base_register (rtx temp
)
2677 return pic_offset_table_rtx
;
2679 if (currently_expanding_to_rtl
)
2680 return mips16_gp_pseudo_reg ();
2682 if (can_create_pseudo_p ())
2683 temp
= gen_reg_rtx (Pmode
);
2686 /* The first post-reload split exposes all references to $gp
2687 (both uses and definitions). All references must remain
2688 explicit after that point.
2690 It is safe to introduce uses of $gp at any time, so for
2691 simplicity, we do that before the split too. */
2692 mips_emit_move (temp
, pic_offset_table_rtx
);
2694 emit_insn (gen_load_const_gp (temp
));
2698 /* Return the RHS of a load_call<mode> insn. */
2701 mips_unspec_call (rtx reg
, rtx symbol
)
2705 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2706 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2709 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2710 reference. Return NULL_RTX otherwise. */
2713 mips_strip_unspec_call (rtx src
)
2715 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2716 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2720 /* Create and return a GOT reference of type TYPE for address ADDR.
2721 TEMP, if nonnull, is a scratch Pmode base register. */
2724 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2726 rtx base
, high
, lo_sum_symbol
;
2728 base
= mips_pic_base_register (temp
);
2730 /* If we used the temporary register to load $gp, we can't use
2731 it for the high part as well. */
2732 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2735 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2736 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2738 if (type
== SYMBOL_GOTOFF_CALL
)
2739 return mips_unspec_call (high
, lo_sum_symbol
);
2741 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
2744 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2745 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2746 constant in that context and can be split into high and low parts.
2747 If so, and if LOW_OUT is nonnull, emit the high part and store the
2748 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2750 TEMP is as for mips_force_temporary and is used to load the high
2751 part into a register.
2753 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2754 a legitimize SET_SRC for an .md pattern, otherwise the low part
2755 is guaranteed to be a legitimate address for mode MODE. */
2758 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2760 enum mips_symbol_context context
;
2761 enum mips_symbol_type symbol_type
;
2764 context
= (mode
== MAX_MACHINE_MODE
2765 ? SYMBOL_CONTEXT_LEA
2766 : SYMBOL_CONTEXT_MEM
);
2767 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2769 addr
= XEXP (addr
, 0);
2770 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2771 && mips_symbol_insns (symbol_type
, mode
) > 0
2772 && mips_split_hi_p
[symbol_type
])
2775 switch (symbol_type
)
2777 case SYMBOL_GOT_PAGE_OFST
:
2778 /* The high part of a page/ofst pair is loaded from the GOT. */
2779 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2790 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2791 && mips_symbol_insns (symbol_type
, mode
) > 0
2792 && mips_split_p
[symbol_type
])
2795 switch (symbol_type
)
2797 case SYMBOL_GOT_DISP
:
2798 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2799 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2802 case SYMBOL_GP_RELATIVE
:
2803 high
= mips_pic_base_register (temp
);
2804 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2808 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2809 high
= mips_force_temporary (temp
, high
);
2810 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2819 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2820 mips_force_temporary; it is only needed when OFFSET is not a
2824 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2826 if (!SMALL_OPERAND (offset
))
2832 /* Load the full offset into a register so that we can use
2833 an unextended instruction for the address itself. */
2834 high
= GEN_INT (offset
);
2839 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2840 The addition inside the macro CONST_HIGH_PART may cause an
2841 overflow, so we need to force a sign-extension check. */
2842 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
2843 offset
= CONST_LOW_PART (offset
);
2845 high
= mips_force_temporary (temp
, high
);
2846 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2848 return plus_constant (Pmode
, reg
, offset
);
2851 /* The __tls_get_attr symbol. */
2852 static GTY(()) rtx mips_tls_symbol
;
2854 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2855 the TLS symbol we are referencing and TYPE is the symbol type to use
2856 (either global dynamic or local dynamic). V0 is an RTX for the
2857 return value location. */
2860 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2864 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2866 if (!mips_tls_symbol
)
2867 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2869 loc
= mips_unspec_address (sym
, type
);
2873 emit_insn (gen_rtx_SET (Pmode
, a0
,
2874 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2875 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
2876 const0_rtx
, NULL_RTX
, false);
2877 RTL_CONST_CALL_P (insn
) = 1;
2878 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2879 insn
= get_insns ();
2886 /* Return a pseudo register that contains the current thread pointer. */
2889 mips_expand_thread_pointer (rtx tp
)
2895 mips_need_mips16_rdhwr_p
= true;
2896 fn
= mips16_stub_function ("__mips16_rdhwr");
2897 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
2898 if (!call_insn_operand (fn
, VOIDmode
))
2899 fn
= force_reg (Pmode
, fn
);
2900 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
2903 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
2910 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
2913 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2914 its address. The return value will be both a valid address and a valid
2915 SET_SRC (either a REG or a LO_SUM). */
2918 mips_legitimize_tls_address (rtx loc
)
2920 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
2921 enum tls_model model
;
2923 model
= SYMBOL_REF_TLS_MODEL (loc
);
2924 /* Only TARGET_ABICALLS code can have more than one module; other
2925 code must be be static and should not use a GOT. All TLS models
2926 reduce to local exec in this situation. */
2927 if (!TARGET_ABICALLS
)
2928 model
= TLS_MODEL_LOCAL_EXEC
;
2932 case TLS_MODEL_GLOBAL_DYNAMIC
:
2933 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2934 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2935 dest
= gen_reg_rtx (Pmode
);
2936 emit_libcall_block (insn
, dest
, v0
, loc
);
2939 case TLS_MODEL_LOCAL_DYNAMIC
:
2940 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2941 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2942 tmp1
= gen_reg_rtx (Pmode
);
2944 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2945 share the LDM result with other LD model accesses. */
2946 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2948 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2950 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
2951 if (mips_split_p
[SYMBOL_DTPREL
])
2953 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2954 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
2957 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
2958 0, 0, OPTAB_DIRECT
);
2961 case TLS_MODEL_INITIAL_EXEC
:
2962 tp
= mips_get_tp ();
2963 tmp1
= gen_reg_rtx (Pmode
);
2964 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2965 if (Pmode
== DImode
)
2966 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2968 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2969 dest
= gen_reg_rtx (Pmode
);
2970 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
2973 case TLS_MODEL_LOCAL_EXEC
:
2974 tmp1
= mips_get_tp ();
2975 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
2976 if (mips_split_p
[SYMBOL_TPREL
])
2978 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
2979 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
2982 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
2983 0, 0, OPTAB_DIRECT
);
2992 /* If X is not a valid address for mode MODE, force it into a register. */
2995 mips_force_address (rtx x
, enum machine_mode mode
)
2997 if (!mips_legitimate_address_p (mode
, x
, false))
2998 x
= force_reg (Pmode
, x
);
3002 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3003 be legitimized in a way that the generic machinery might not expect,
3004 return a new address, otherwise return NULL. MODE is the mode of
3005 the memory being accessed. */
3008 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3009 enum machine_mode mode
)
3012 HOST_WIDE_INT offset
;
3014 if (mips_tls_symbol_p (x
))
3015 return mips_legitimize_tls_address (x
);
3017 /* See if the address can split into a high part and a LO_SUM. */
3018 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3019 return mips_force_address (addr
, mode
);
3021 /* Handle BASE + OFFSET using mips_add_offset. */
3022 mips_split_plus (x
, &base
, &offset
);
3025 if (!mips_valid_base_register_p (base
, mode
, false))
3026 base
= copy_to_mode_reg (Pmode
, base
);
3027 addr
= mips_add_offset (NULL
, base
, offset
);
3028 return mips_force_address (addr
, mode
);
3034 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3037 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3039 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3040 enum machine_mode mode
;
3041 unsigned int i
, num_ops
;
3044 mode
= GET_MODE (dest
);
3045 num_ops
= mips_build_integer (codes
, value
);
3047 /* Apply each binary operation to X. Invariant: X is a legitimate
3048 source operand for a SET pattern. */
3049 x
= GEN_INT (codes
[0].value
);
3050 for (i
= 1; i
< num_ops
; i
++)
3052 if (!can_create_pseudo_p ())
3054 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3058 x
= force_reg (mode
, x
);
3059 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3062 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3065 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3066 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3070 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3074 /* Split moves of big integers into smaller pieces. */
3075 if (splittable_const_int_operand (src
, mode
))
3077 mips_move_integer (dest
, dest
, INTVAL (src
));
3081 /* Split moves of symbolic constants into high/low pairs. */
3082 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3084 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3088 /* Generate the appropriate access sequences for TLS symbols. */
3089 if (mips_tls_symbol_p (src
))
3091 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3095 /* If we have (const (plus symbol offset)), and that expression cannot
3096 be forced into memory, load the symbol first and add in the offset.
3097 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3098 forced into memory, as it usually produces better code. */
3099 split_const (src
, &base
, &offset
);
3100 if (offset
!= const0_rtx
3101 && (targetm
.cannot_force_const_mem (mode
, src
)
3102 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3104 base
= mips_force_temporary (dest
, base
);
3105 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3109 src
= force_const_mem (mode
, src
);
3111 /* When using explicit relocs, constant pool references are sometimes
3112 not legitimate addresses. */
3113 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3114 mips_emit_move (dest
, src
);
3117 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3118 sequence that is valid. */
3121 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3123 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3125 mips_emit_move (dest
, force_reg (mode
, src
));
3129 /* We need to deal with constants that would be legitimate
3130 immediate_operands but aren't legitimate move_operands. */
3131 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3133 mips_legitimize_const_move (mode
, dest
, src
);
3134 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3140 /* Return true if value X in context CONTEXT is a small-data address
3141 that can be rewritten as a LO_SUM. */
3144 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3146 enum mips_symbol_type symbol_type
;
3148 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3149 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3150 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3151 && symbol_type
== SYMBOL_GP_RELATIVE
);
3154 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3155 containing MEM, or null if none. */
3158 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3160 enum mips_symbol_context context
;
3162 /* Ignore things like "g" constraints in asms. We make no particular
3163 guarantee about which symbolic constants are acceptable as asm operands
3164 versus which must be forced into a GPR. */
3165 if (GET_CODE (*loc
) == LO_SUM
|| GET_CODE (*loc
) == ASM_OPERANDS
)
3170 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3175 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3176 return mips_rewrite_small_data_p (*loc
, context
);
3179 /* Return true if OP refers to small data symbols directly, not through
3183 mips_small_data_pattern_p (rtx op
)
3185 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3188 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3189 DATA is the containing MEM, or null if none. */
3192 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3194 enum mips_symbol_context context
;
3198 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3202 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3203 if (mips_rewrite_small_data_p (*loc
, context
))
3204 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3206 if (GET_CODE (*loc
) == LO_SUM
)
3212 /* Rewrite instruction pattern PATTERN so that it refers to small data
3213 using explicit relocations. */
3216 mips_rewrite_small_data (rtx pattern
)
3218 pattern
= copy_insn (pattern
);
3219 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3223 /* We need a lot of little routines to check the range of MIPS16 immediate
3227 m16_check_op (rtx op
, int low
, int high
, int mask
)
3229 return (CONST_INT_P (op
)
3230 && IN_RANGE (INTVAL (op
), low
, high
)
3231 && (INTVAL (op
) & mask
) == 0);
3235 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3237 return m16_check_op (op
, 0x1, 0x8, 0);
3241 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3243 return m16_check_op (op
, -0x8, 0x7, 0);
3247 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3249 return m16_check_op (op
, -0x7, 0x8, 0);
3253 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3255 return m16_check_op (op
, -0x10, 0xf, 0);
3259 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3261 return m16_check_op (op
, -0xf, 0x10, 0);
3265 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3267 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
3271 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3273 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
3277 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3279 return m16_check_op (op
, -0x80, 0x7f, 0);
3283 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3285 return m16_check_op (op
, -0x7f, 0x80, 0);
3289 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3291 return m16_check_op (op
, 0x0, 0xff, 0);
3295 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3297 return m16_check_op (op
, -0xff, 0x0, 0);
3301 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3303 return m16_check_op (op
, -0x1, 0xfe, 0);
3307 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3309 return m16_check_op (op
, 0x0, 0xff << 2, 3);
3313 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3315 return m16_check_op (op
, -0xff << 2, 0x0, 3);
3319 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3321 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
3325 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3327 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
3330 /* The cost of loading values from the constant pool. It should be
3331 larger than the cost of any constant we want to synthesize inline. */
3332 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3334 /* Return the cost of X when used as an operand to the MIPS16 instruction
3335 that implements CODE. Return -1 if there is no such instruction, or if
3336 X is not a valid immediate operand for it. */
3339 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3346 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3347 other shifts are extended. The shift patterns truncate the shift
3348 count to the right size, so there are no out-of-range values. */
3349 if (IN_RANGE (x
, 1, 8))
3351 return COSTS_N_INSNS (1);
3354 if (IN_RANGE (x
, -128, 127))
3356 if (SMALL_OPERAND (x
))
3357 return COSTS_N_INSNS (1);
3361 /* Like LE, but reject the always-true case. */
3365 /* We add 1 to the immediate and use SLT. */
3368 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3371 if (IN_RANGE (x
, 0, 255))
3373 if (SMALL_OPERAND_UNSIGNED (x
))
3374 return COSTS_N_INSNS (1);
3379 /* Equality comparisons with 0 are cheap. */
3389 /* Return true if there is a non-MIPS16 instruction that implements CODE
3390 and if that instruction accepts X as an immediate operand. */
3393 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3400 /* All shift counts are truncated to a valid constant. */
3405 /* Likewise rotates, if the target supports rotates at all. */
3411 /* These instructions take 16-bit unsigned immediates. */
3412 return SMALL_OPERAND_UNSIGNED (x
);
3417 /* These instructions take 16-bit signed immediates. */
3418 return SMALL_OPERAND (x
);
3424 /* The "immediate" forms of these instructions are really
3425 implemented as comparisons with register 0. */
3430 /* Likewise, meaning that the only valid immediate operand is 1. */
3434 /* We add 1 to the immediate and use SLT. */
3435 return SMALL_OPERAND (x
+ 1);
3438 /* Likewise SLTU, but reject the always-true case. */
3439 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3443 /* The bit position and size are immediate operands. */
3444 return ISA_HAS_EXT_INS
;
3447 /* By default assume that $0 can be used for 0. */
3452 /* Return the cost of binary operation X, given that the instruction
3453 sequence for a word-sized or smaller operation has cost SINGLE_COST
3454 and that the sequence of a double-word operation has cost DOUBLE_COST.
3455 If SPEED is true, optimize for speed otherwise optimize for size. */
3458 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3462 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3467 + set_src_cost (XEXP (x
, 0), speed
)
3468 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), 1, speed
));
3471 /* Return the cost of floating-point multiplications of mode MODE. */
3474 mips_fp_mult_cost (enum machine_mode mode
)
3476 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3479 /* Return the cost of floating-point divisions of mode MODE. */
3482 mips_fp_div_cost (enum machine_mode mode
)
3484 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3487 /* Return the cost of sign-extending OP to mode MODE, not including the
3488 cost of OP itself. */
3491 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3494 /* Extended loads are as cheap as unextended ones. */
3497 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3498 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3501 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3502 /* We can use SEB or SEH. */
3503 return COSTS_N_INSNS (1);
3505 /* We need to use a shift left and a shift right. */
3506 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3509 /* Return the cost of zero-extending OP to mode MODE, not including the
3510 cost of OP itself. */
3513 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3516 /* Extended loads are as cheap as unextended ones. */
3519 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3520 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3521 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3523 if (GENERATE_MIPS16E
)
3524 /* We can use ZEB or ZEH. */
3525 return COSTS_N_INSNS (1);
3528 /* We need to load 0xff or 0xffff into a register and use AND. */
3529 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3531 /* We can use ANDI. */
3532 return COSTS_N_INSNS (1);
3535 /* Return the cost of moving between two registers of mode MODE,
3536 assuming that the move will be in pieces of at most UNITS bytes. */
3539 mips_set_reg_reg_piece_cost (enum machine_mode mode
, unsigned int units
)
3541 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
3544 /* Return the cost of moving between two registers of mode MODE. */
3547 mips_set_reg_reg_cost (enum machine_mode mode
)
3549 switch (GET_MODE_CLASS (mode
))
3552 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
3555 case MODE_COMPLEX_FLOAT
:
3556 case MODE_VECTOR_FLOAT
:
3557 if (TARGET_HARD_FLOAT
)
3558 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
3562 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
3566 /* Return the cost of an operand X that can be trucated for free.
3567 SPEED says whether we're optimizing for size or speed. */
3570 mips_truncated_op_cost (rtx x
, bool speed
)
3572 if (GET_CODE (x
) == TRUNCATE
)
3574 return set_src_cost (x
, speed
);
3577 /* Implement TARGET_RTX_COSTS. */
3580 mips_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
3581 int *total
, bool speed
)
3583 enum machine_mode mode
= GET_MODE (x
);
3584 bool float_mode_p
= FLOAT_MODE_P (mode
);
3588 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3589 appear in the instruction stream, and the cost of a comparison is
3590 really the cost of the branch or scc condition. At the time of
3591 writing, GCC only uses an explicit outer COMPARE code when optabs
3592 is testing whether a constant is expensive enough to force into a
3593 register. We want optabs to pass such constants through the MIPS
3594 expanders instead, so make all constants very cheap here. */
3595 if (outer_code
== COMPARE
)
3597 gcc_assert (CONSTANT_P (x
));
3605 /* Treat *clear_upper32-style ANDs as having zero cost in the
3606 second operand. The cost is entirely in the first operand.
3608 ??? This is needed because we would otherwise try to CSE
3609 the constant operand. Although that's the right thing for
3610 instructions that continue to be a register operation throughout
3611 compilation, it is disastrous for instructions that could
3612 later be converted into a memory operation. */
3614 && outer_code
== AND
3615 && UINTVAL (x
) == 0xffffffff)
3623 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3632 /* When not optimizing for size, we care more about the cost
3633 of hot code, and hot code is often in a loop. If a constant
3634 operand needs to be forced into a register, we will often be
3635 able to hoist the constant load out of the loop, so the load
3636 should not contribute to the cost. */
3637 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3649 if (force_to_mem_operand (x
, VOIDmode
))
3651 *total
= COSTS_N_INSNS (1);
3654 cost
= mips_const_insns (x
);
3657 /* If the constant is likely to be stored in a GPR, SETs of
3658 single-insn constants are as cheap as register sets; we
3659 never want to CSE them.
3661 Don't reduce the cost of storing a floating-point zero in
3662 FPRs. If we have a zero in an FPR for other reasons, we
3663 can get better cfg-cleanup and delayed-branch results by
3664 using it consistently, rather than using $0 sometimes and
3665 an FPR at other times. Also, moves between floating-point
3666 registers are sometimes cheaper than (D)MTC1 $0. */
3668 && outer_code
== SET
3669 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3671 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3672 want to CSE the constant itself. It is usually better to
3673 have N copies of the last operation in the sequence and one
3674 shared copy of the other operations. (Note that this is
3675 not true for MIPS16 code, where the final operation in the
3676 sequence is often an extended instruction.)
3678 Also, if we have a CONST_INT, we don't know whether it is
3679 for a word or doubleword operation, so we cannot rely on
3680 the result of mips_build_integer. */
3681 else if (!TARGET_MIPS16
3682 && (outer_code
== SET
|| mode
== VOIDmode
))
3684 *total
= COSTS_N_INSNS (cost
);
3687 /* The value will need to be fetched from the constant pool. */
3688 *total
= CONSTANT_POOL_COST
;
3692 /* If the address is legitimate, return the number of
3693 instructions it needs. */
3695 cost
= mips_address_insns (addr
, mode
, true);
3698 *total
= COSTS_N_INSNS (cost
+ 1);
3701 /* Check for a scaled indexed address. */
3702 if (mips_lwxs_address_p (addr
)
3703 || mips_lx_address_p (addr
, mode
))
3705 *total
= COSTS_N_INSNS (2);
3708 /* Otherwise use the default handling. */
3712 *total
= COSTS_N_INSNS (6);
3716 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3720 /* Check for a *clear_upper32 pattern and treat it like a zero
3721 extension. See the pattern's comment for details. */
3724 && CONST_INT_P (XEXP (x
, 1))
3725 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3727 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3728 + set_src_cost (XEXP (x
, 0), speed
));
3731 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
3733 rtx op
= XEXP (x
, 0);
3734 if (GET_CODE (op
) == ASHIFT
3735 && CONST_INT_P (XEXP (op
, 1))
3736 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
3738 *total
= COSTS_N_INSNS (1) + set_src_cost (XEXP (op
, 0), speed
);
3747 /* Double-word operations use two single-word operations. */
3748 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3757 if (CONSTANT_P (XEXP (x
, 1)))
3758 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3761 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3767 *total
= mips_cost
->fp_add
;
3769 *total
= COSTS_N_INSNS (4);
3773 /* Low-part immediates need an extended MIPS16 instruction. */
3774 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3775 + set_src_cost (XEXP (x
, 0), speed
));
3790 /* Branch comparisons have VOIDmode, so use the first operand's
3792 mode
= GET_MODE (XEXP (x
, 0));
3793 if (FLOAT_MODE_P (mode
))
3795 *total
= mips_cost
->fp_add
;
3798 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3804 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3805 && TARGET_FUSED_MADD
3806 && !HONOR_NANS (mode
)
3807 && !HONOR_SIGNED_ZEROS (mode
))
3809 /* See if we can use NMADD or NMSUB. See mips.md for the
3810 associated patterns. */
3811 rtx op0
= XEXP (x
, 0);
3812 rtx op1
= XEXP (x
, 1);
3813 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3815 *total
= (mips_fp_mult_cost (mode
)
3816 + set_src_cost (XEXP (XEXP (op0
, 0), 0), speed
)
3817 + set_src_cost (XEXP (op0
, 1), speed
)
3818 + set_src_cost (op1
, speed
));
3821 if (GET_CODE (op1
) == MULT
)
3823 *total
= (mips_fp_mult_cost (mode
)
3824 + set_src_cost (op0
, speed
)
3825 + set_src_cost (XEXP (op1
, 0), speed
)
3826 + set_src_cost (XEXP (op1
, 1), speed
));
3835 /* If this is part of a MADD or MSUB, treat the PLUS as
3838 && TARGET_FUSED_MADD
3839 && GET_CODE (XEXP (x
, 0)) == MULT
)
3842 *total
= mips_cost
->fp_add
;
3846 /* Double-word operations require three single-word operations and
3847 an SLTU. The MIPS16 version then needs to move the result of
3848 the SLTU from $24 to a MIPS16 register. */
3849 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3850 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3856 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3857 && TARGET_FUSED_MADD
3858 && !HONOR_NANS (mode
)
3859 && HONOR_SIGNED_ZEROS (mode
))
3861 /* See if we can use NMADD or NMSUB. See mips.md for the
3862 associated patterns. */
3863 rtx op
= XEXP (x
, 0);
3864 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3865 && GET_CODE (XEXP (op
, 0)) == MULT
)
3867 *total
= (mips_fp_mult_cost (mode
)
3868 + set_src_cost (XEXP (XEXP (op
, 0), 0), speed
)
3869 + set_src_cost (XEXP (XEXP (op
, 0), 1), speed
)
3870 + set_src_cost (XEXP (op
, 1), speed
));
3876 *total
= mips_cost
->fp_add
;
3878 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3883 *total
= mips_fp_mult_cost (mode
);
3884 else if (mode
== DImode
&& !TARGET_64BIT
)
3885 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3886 where the mulsidi3 always includes an MFHI and an MFLO. */
3888 ? mips_cost
->int_mult_si
* 3 + 6
3889 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3891 *total
= COSTS_N_INSNS (ISA_HAS_MUL3
? 1 : 2);
3892 else if (mode
== DImode
)
3893 *total
= mips_cost
->int_mult_di
;
3895 *total
= mips_cost
->int_mult_si
;
3899 /* Check for a reciprocal. */
3902 && flag_unsafe_math_optimizations
3903 && XEXP (x
, 0) == CONST1_RTX (mode
))
3905 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3906 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3907 division as being free. */
3908 *total
= set_src_cost (XEXP (x
, 1), speed
);
3910 *total
= (mips_fp_div_cost (mode
)
3911 + set_src_cost (XEXP (x
, 1), speed
));
3920 *total
= mips_fp_div_cost (mode
);
3929 /* It is our responsibility to make division by a power of 2
3930 as cheap as 2 register additions if we want the division
3931 expanders to be used for such operations; see the setting
3932 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3933 should always produce shorter code than using
3934 expand_sdiv2_pow2. */
3936 && CONST_INT_P (XEXP (x
, 1))
3937 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3939 *total
= COSTS_N_INSNS (2) + set_src_cost (XEXP (x
, 0), speed
);
3942 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3944 else if (mode
== DImode
)
3945 *total
= mips_cost
->int_div_di
;
3947 *total
= mips_cost
->int_div_si
;
3951 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3955 if (outer_code
== SET
3957 && GET_MODE (XEXP (x
, 0)) == QImode
3958 && GET_CODE (XEXP (x
, 0)) == PLUS
)
3960 rtx plus
= XEXP (x
, 0);
3961 *total
= (COSTS_N_INSNS (1)
3962 + mips_truncated_op_cost (XEXP (plus
, 0), speed
)
3963 + mips_truncated_op_cost (XEXP (plus
, 1), speed
));
3966 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3970 case UNSIGNED_FLOAT
:
3973 case FLOAT_TRUNCATE
:
3974 *total
= mips_cost
->fp_add
;
3978 if (register_operand (SET_DEST (x
), VOIDmode
)
3979 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
3981 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
3991 /* Implement TARGET_ADDRESS_COST. */
3994 mips_address_cost (rtx addr
, enum machine_mode mode
,
3995 addr_space_t as ATTRIBUTE_UNUSED
,
3996 bool speed ATTRIBUTE_UNUSED
)
3998 return mips_address_insns (addr
, mode
, false);
4001 /* Information about a single instruction in a multi-instruction
4003 struct mips_multi_member
{
4004 /* True if this is a label, false if it is code. */
4007 /* The output_asm_insn format of the instruction. */
4010 /* The operands to the instruction. */
4011 rtx operands
[MAX_RECOG_OPERANDS
];
4013 typedef struct mips_multi_member mips_multi_member
;
4015 /* Vector definitions for the above. */
4016 DEF_VEC_O(mips_multi_member
);
4017 DEF_VEC_ALLOC_O(mips_multi_member
, heap
);
4019 /* The instructions that make up the current multi-insn sequence. */
4020 static VEC (mips_multi_member
, heap
) *mips_multi_members
;
4022 /* How many instructions (as opposed to labels) are in the current
4023 multi-insn sequence. */
4024 static unsigned int mips_multi_num_insns
;
4026 /* Start a new multi-insn sequence. */
4029 mips_multi_start (void)
4031 VEC_truncate (mips_multi_member
, mips_multi_members
, 0);
4032 mips_multi_num_insns
= 0;
4035 /* Add a new, uninitialized member to the current multi-insn sequence. */
4037 static struct mips_multi_member
*
4038 mips_multi_add (void)
4040 mips_multi_member empty
;
4041 return VEC_safe_push (mips_multi_member
, heap
, mips_multi_members
, empty
);
4044 /* Add a normal insn with the given asm format to the current multi-insn
4045 sequence. The other arguments are a null-terminated list of operands. */
4048 mips_multi_add_insn (const char *format
, ...)
4050 struct mips_multi_member
*member
;
4055 member
= mips_multi_add ();
4056 member
->is_label_p
= false;
4057 member
->format
= format
;
4058 va_start (ap
, format
);
4060 while ((op
= va_arg (ap
, rtx
)))
4061 member
->operands
[i
++] = op
;
4063 mips_multi_num_insns
++;
4066 /* Add the given label definition to the current multi-insn sequence.
4067 The definition should include the colon. */
4070 mips_multi_add_label (const char *label
)
4072 struct mips_multi_member
*member
;
4074 member
= mips_multi_add ();
4075 member
->is_label_p
= true;
4076 member
->format
= label
;
4079 /* Return the index of the last member of the current multi-insn sequence. */
4082 mips_multi_last_index (void)
4084 return VEC_length (mips_multi_member
, mips_multi_members
) - 1;
4087 /* Add a copy of an existing instruction to the current multi-insn
4088 sequence. I is the index of the instruction that should be copied. */
4091 mips_multi_copy_insn (unsigned int i
)
4093 struct mips_multi_member
*member
;
4095 member
= mips_multi_add ();
4096 memcpy (member
, &VEC_index (mips_multi_member
, mips_multi_members
, i
),
4098 gcc_assert (!member
->is_label_p
);
4101 /* Change the operand of an existing instruction in the current
4102 multi-insn sequence. I is the index of the instruction,
4103 OP is the index of the operand, and X is the new value. */
4106 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4108 VEC_index (mips_multi_member
, mips_multi_members
, i
).operands
[op
] = x
;
4111 /* Write out the asm code for the current multi-insn sequence. */
4114 mips_multi_write (void)
4116 struct mips_multi_member
*member
;
4119 FOR_EACH_VEC_ELT (mips_multi_member
, mips_multi_members
, i
, member
)
4120 if (member
->is_label_p
)
4121 fprintf (asm_out_file
, "%s\n", member
->format
);
4123 output_asm_insn (member
->format
, member
->operands
);
4126 /* Return one word of double-word value OP, taking into account the fixed
4127 endianness of certain registers. HIGH_P is true to select the high part,
4128 false to select the low part. */
4131 mips_subword (rtx op
, bool high_p
)
4133 unsigned int byte
, offset
;
4134 enum machine_mode mode
;
4136 mode
= GET_MODE (op
);
4137 if (mode
== VOIDmode
)
4138 mode
= TARGET_64BIT
? TImode
: DImode
;
4140 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4141 byte
= UNITS_PER_WORD
;
4145 if (FP_REG_RTX_P (op
))
4147 /* Paired FPRs are always ordered little-endian. */
4148 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4149 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4153 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4155 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4158 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4159 SPLIT_TYPE is the condition under which moves should be split. */
4162 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4164 return ((split_type
!= SPLIT_FOR_SPEED
4165 || mips_tuning_info
.fast_mult_zero_zero_p
)
4166 && src
== const0_rtx
4168 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4169 && (ISA_HAS_DSP_MULT
4170 ? ACC_REG_P (REGNO (dest
))
4171 : MD_REG_P (REGNO (dest
))));
4174 /* Return true if a move from SRC to DEST should be split into two.
4175 SPLIT_TYPE describes the split condition. */
4178 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4180 /* Check whether the move can be done using some variant of MULT $0,$0. */
4181 if (mips_mult_move_p (dest
, src
, split_type
))
4184 /* FPR-to-FPR moves can be done in a single instruction, if they're
4186 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4187 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4190 /* Check for floating-point loads and stores. */
4191 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4193 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4195 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4199 /* Otherwise split all multiword moves. */
4200 return size
> UNITS_PER_WORD
;
4203 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4204 SPLIT_TYPE describes the split condition. */
4207 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4211 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4212 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4214 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4215 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4216 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4217 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4218 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4219 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4220 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4221 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4222 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4223 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4224 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4225 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4226 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4227 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4231 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4233 low_dest
= mips_subword (dest
, false);
4234 mips_emit_move (low_dest
, mips_subword (src
, false));
4236 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4238 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4240 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4242 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4244 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4246 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4250 /* The operation can be split into two normal moves. Decide in
4251 which order to do them. */
4252 low_dest
= mips_subword (dest
, false);
4253 if (REG_P (low_dest
)
4254 && reg_overlap_mentioned_p (low_dest
, src
))
4256 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4257 mips_emit_move (low_dest
, mips_subword (src
, false));
4261 mips_emit_move (low_dest
, mips_subword (src
, false));
4262 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4267 /* Return the split type for instruction INSN. */
4269 static enum mips_split_type
4270 mips_insn_split_type (rtx insn
)
4272 basic_block bb
= BLOCK_FOR_INSN (insn
);
4275 if (optimize_bb_for_speed_p (bb
))
4276 return SPLIT_FOR_SPEED
;
4278 return SPLIT_FOR_SIZE
;
4280 /* Once CFG information has been removed, we should trust the optimization
4281 decisions made by previous passes and only split where necessary. */
4282 return SPLIT_IF_NECESSARY
;
4285 /* Return true if a move from SRC to DEST in INSN should be split. */
4288 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
4290 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
4293 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4297 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
4299 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
4302 /* Return the appropriate instructions to move SRC into DEST. Assume
4303 that SRC is operand 1 and DEST is operand 0. */
4306 mips_output_move (rtx dest
, rtx src
)
4308 enum rtx_code dest_code
, src_code
;
4309 enum machine_mode mode
;
4310 enum mips_symbol_type symbol_type
;
4313 dest_code
= GET_CODE (dest
);
4314 src_code
= GET_CODE (src
);
4315 mode
= GET_MODE (dest
);
4316 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4318 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4321 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4322 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4324 if (dest_code
== REG
)
4326 if (GP_REG_P (REGNO (dest
)))
4327 return "move\t%0,%z1";
4329 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
4331 if (ISA_HAS_DSP_MULT
)
4332 return "mult\t%q0,%.,%.";
4334 return "mult\t%.,%.";
4337 /* Moves to HI are handled by special .md insns. */
4338 if (REGNO (dest
) == LO_REGNUM
)
4341 if (DSP_ACC_REG_P (REGNO (dest
)))
4343 static char retval
[] = "mt__\t%z1,%q0";
4345 retval
[2] = reg_names
[REGNO (dest
)][4];
4346 retval
[3] = reg_names
[REGNO (dest
)][5];
4350 if (FP_REG_P (REGNO (dest
)))
4351 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4353 if (ALL_COP_REG_P (REGNO (dest
)))
4355 static char retval
[] = "dmtc_\t%z1,%0";
4357 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4358 return dbl_p
? retval
: retval
+ 1;
4361 if (dest_code
== MEM
)
4362 switch (GET_MODE_SIZE (mode
))
4364 case 1: return "sb\t%z1,%0";
4365 case 2: return "sh\t%z1,%0";
4366 case 4: return "sw\t%z1,%0";
4367 case 8: return "sd\t%z1,%0";
4370 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4372 if (src_code
== REG
)
4374 /* Moves from HI are handled by special .md insns. */
4375 if (REGNO (src
) == LO_REGNUM
)
4377 /* When generating VR4120 or VR4130 code, we use MACC and
4378 DMACC instead of MFLO. This avoids both the normal
4379 MIPS III HI/LO hazards and the errata related to
4382 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4386 if (DSP_ACC_REG_P (REGNO (src
)))
4388 static char retval
[] = "mf__\t%0,%q1";
4390 retval
[2] = reg_names
[REGNO (src
)][4];
4391 retval
[3] = reg_names
[REGNO (src
)][5];
4395 if (FP_REG_P (REGNO (src
)))
4396 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4398 if (ALL_COP_REG_P (REGNO (src
)))
4400 static char retval
[] = "dmfc_\t%0,%1";
4402 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4403 return dbl_p
? retval
: retval
+ 1;
4407 if (src_code
== MEM
)
4408 switch (GET_MODE_SIZE (mode
))
4410 case 1: return "lbu\t%0,%1";
4411 case 2: return "lhu\t%0,%1";
4412 case 4: return "lw\t%0,%1";
4413 case 8: return "ld\t%0,%1";
4416 if (src_code
== CONST_INT
)
4418 /* Don't use the X format for the operand itself, because that
4419 will give out-of-range numbers for 64-bit hosts and 32-bit
4422 return "li\t%0,%1\t\t\t# %X1";
4424 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4427 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4431 if (src_code
== HIGH
)
4432 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4434 if (CONST_GP_P (src
))
4435 return "move\t%0,%1";
4437 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4438 && mips_lo_relocs
[symbol_type
] != 0)
4440 /* A signed 16-bit constant formed by applying a relocation
4441 operator to a symbolic address. */
4442 gcc_assert (!mips_split_p
[symbol_type
]);
4443 return "li\t%0,%R1";
4446 if (symbolic_operand (src
, VOIDmode
))
4448 gcc_assert (TARGET_MIPS16
4449 ? TARGET_MIPS16_TEXT_LOADS
4450 : !TARGET_EXPLICIT_RELOCS
);
4451 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4454 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4456 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4458 if (GET_MODE (dest
) == V2SFmode
)
4459 return "mov.ps\t%0,%1";
4461 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4464 if (dest_code
== MEM
)
4465 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4467 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4469 if (src_code
== MEM
)
4470 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4472 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4474 static char retval
[] = "l_c_\t%0,%1";
4476 retval
[1] = (dbl_p
? 'd' : 'w');
4477 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4480 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4482 static char retval
[] = "s_c_\t%1,%0";
4484 retval
[1] = (dbl_p
? 'd' : 'w');
4485 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4491 /* Return true if CMP1 is a suitable second operand for integer ordering
4492 test CODE. See also the *sCC patterns in mips.md. */
4495 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4501 return reg_or_0_operand (cmp1
, VOIDmode
);
4505 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4509 return arith_operand (cmp1
, VOIDmode
);
4512 return sle_operand (cmp1
, VOIDmode
);
4515 return sleu_operand (cmp1
, VOIDmode
);
4522 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4523 integer ordering test *CODE, or if an equivalent combination can
4524 be formed by adjusting *CODE and *CMP1. When returning true, update
4525 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4529 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4530 enum machine_mode mode
)
4532 HOST_WIDE_INT plus_one
;
4534 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4537 if (CONST_INT_P (*cmp1
))
4541 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4542 if (INTVAL (*cmp1
) < plus_one
)
4545 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4551 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4555 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4566 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4567 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4568 is nonnull, it's OK to set TARGET to the inverse of the result and
4569 flip *INVERT_PTR instead. */
4572 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4573 rtx target
, rtx cmp0
, rtx cmp1
)
4575 enum machine_mode mode
;
4577 /* First see if there is a MIPS instruction that can do this operation.
4578 If not, try doing the same for the inverse operation. If that also
4579 fails, force CMP1 into a register and try again. */
4580 mode
= GET_MODE (cmp0
);
4581 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4582 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4585 enum rtx_code inv_code
= reverse_condition (code
);
4586 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4588 cmp1
= force_reg (mode
, cmp1
);
4589 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4591 else if (invert_ptr
== 0)
4595 inv_target
= mips_force_binary (GET_MODE (target
),
4596 inv_code
, cmp0
, cmp1
);
4597 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4601 *invert_ptr
= !*invert_ptr
;
4602 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4607 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4608 The register will have the same mode as CMP0. */
4611 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4613 if (cmp1
== const0_rtx
)
4616 if (uns_arith_operand (cmp1
, VOIDmode
))
4617 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4618 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4620 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4621 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4624 /* Convert *CODE into a code that can be used in a floating-point
4625 scc instruction (C.cond.fmt). Return true if the values of
4626 the condition code registers will be inverted, with 0 indicating
4627 that the condition holds. */
4630 mips_reversed_fp_cond (enum rtx_code
*code
)
4637 *code
= reverse_condition_maybe_unordered (*code
);
4645 /* Allocate a floating-point condition-code register of mode MODE.
4647 These condition code registers are used for certain kinds
4648 of compound operation, such as compare and branches, vconds,
4649 and built-in functions. At expand time, their use is entirely
4650 controlled by MIPS-specific code and is entirely internal
4651 to these compound operations.
4653 We could (and did in the past) expose condition-code values
4654 as pseudo registers and leave the register allocator to pick
4655 appropriate registers. The problem is that it is not practically
4656 possible for the rtl optimizers to guarantee that no spills will
4657 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4658 therefore need spill and reload sequences to handle the worst case.
4660 Although such sequences do exist, they are very expensive and are
4661 not something we'd want to use. This is especially true of CCV2 and
4662 CCV4, where all the shuffling would greatly outweigh whatever benefit
4663 the vectorization itself provides.
4665 The main benefit of having more than one condition-code register
4666 is to allow the pipelining of operations, especially those involving
4667 comparisons and conditional moves. We don't really expect the
4668 registers to be live for long periods, and certainly never want
4669 them to be live across calls.
4671 Also, there should be no penalty attached to using all the available
4672 registers. They are simply bits in the same underlying FPU control
4675 We therefore expose the hardware registers from the outset and use
4676 a simple round-robin allocation scheme. */
4679 mips_allocate_fcc (enum machine_mode mode
)
4681 unsigned int regno
, count
;
4683 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
4687 else if (mode
== CCV2mode
)
4689 else if (mode
== CCV4mode
)
4694 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
4695 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
4696 cfun
->machine
->next_fcc
= 0;
4697 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
4698 cfun
->machine
->next_fcc
+= count
;
4699 return gen_rtx_REG (mode
, regno
);
4702 /* Convert a comparison into something that can be used in a branch or
4703 conditional move. On entry, *OP0 and *OP1 are the values being
4704 compared and *CODE is the code used to compare them.
4706 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4707 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4708 otherwise any standard branch condition can be used. The standard branch
4711 - EQ or NE between two registers.
4712 - any comparison between a register and zero. */
4715 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4720 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4722 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4724 else if (*code
== EQ
|| *code
== NE
)
4728 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4732 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4736 /* The comparison needs a separate scc instruction. Store the
4737 result of the scc in *OP0 and compare it against zero. */
4738 bool invert
= false;
4739 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4740 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4741 *code
= (invert
? EQ
: NE
);
4745 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4747 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4748 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4754 enum rtx_code cmp_code
;
4756 /* Floating-point tests use a separate C.cond.fmt comparison to
4757 set a condition code register. The branch or conditional move
4758 will then compare that register against zero.
4760 Set CMP_CODE to the code of the comparison instruction and
4761 *CODE to the code that the branch or move should use. */
4763 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4765 ? mips_allocate_fcc (CCmode
)
4766 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4768 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4772 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4773 and OPERAND[3]. Store the result in OPERANDS[0].
4775 On 64-bit targets, the mode of the comparison and target will always be
4776 SImode, thus possibly narrower than that of the comparison's operands. */
4779 mips_expand_scc (rtx operands
[])
4781 rtx target
= operands
[0];
4782 enum rtx_code code
= GET_CODE (operands
[1]);
4783 rtx op0
= operands
[2];
4784 rtx op1
= operands
[3];
4786 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4788 if (code
== EQ
|| code
== NE
)
4791 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4792 mips_emit_binary (code
, target
, op0
, op1
);
4795 rtx zie
= mips_zero_if_equal (op0
, op1
);
4796 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4800 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4803 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4804 CODE and jump to OPERANDS[3] if the condition holds. */
4807 mips_expand_conditional_branch (rtx
*operands
)
4809 enum rtx_code code
= GET_CODE (operands
[0]);
4810 rtx op0
= operands
[1];
4811 rtx op1
= operands
[2];
4814 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4815 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4816 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4821 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4822 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4825 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4826 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4831 reversed_p
= mips_reversed_fp_cond (&cond
);
4832 cmp_result
= mips_allocate_fcc (CCV2mode
);
4833 emit_insn (gen_scc_ps (cmp_result
,
4834 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4836 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4839 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4843 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4844 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4847 mips_expand_conditional_move (rtx
*operands
)
4850 enum rtx_code code
= GET_CODE (operands
[1]);
4851 rtx op0
= XEXP (operands
[1], 0);
4852 rtx op1
= XEXP (operands
[1], 1);
4854 mips_emit_compare (&code
, &op0
, &op1
, true);
4855 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4856 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4857 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4858 operands
[2], operands
[3])));
4861 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4864 mips_expand_conditional_trap (rtx comparison
)
4867 enum machine_mode mode
;
4870 /* MIPS conditional trap instructions don't have GT or LE flavors,
4871 so we must swap the operands and convert to LT and GE respectively. */
4872 code
= GET_CODE (comparison
);
4879 code
= swap_condition (code
);
4880 op0
= XEXP (comparison
, 1);
4881 op1
= XEXP (comparison
, 0);
4885 op0
= XEXP (comparison
, 0);
4886 op1
= XEXP (comparison
, 1);
4890 mode
= GET_MODE (XEXP (comparison
, 0));
4891 op0
= force_reg (mode
, op0
);
4892 if (!arith_operand (op1
, mode
))
4893 op1
= force_reg (mode
, op1
);
4895 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4896 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4900 /* Initialize *CUM for a call to a function of type FNTYPE. */
4903 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4905 memset (cum
, 0, sizeof (*cum
));
4906 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4907 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4910 /* Fill INFO with information about a single argument. CUM is the
4911 cumulative state for earlier arguments. MODE is the mode of this
4912 argument and TYPE is its type (if known). NAMED is true if this
4913 is a named (fixed) argument rather than a variable one. */
4916 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4917 enum machine_mode mode
, const_tree type
, bool named
)
4919 bool doubleword_aligned_p
;
4920 unsigned int num_bytes
, num_words
, max_regs
;
4922 /* Work out the size of the argument. */
4923 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4924 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4926 /* Decide whether it should go in a floating-point register, assuming
4927 one is free. Later code checks for availability.
4929 The checks against UNITS_PER_FPVALUE handle the soft-float and
4930 single-float cases. */
4934 /* The EABI conventions have traditionally been defined in terms
4935 of TYPE_MODE, regardless of the actual type. */
4936 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4937 || mode
== V2SFmode
)
4938 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4943 /* Only leading floating-point scalars are passed in
4944 floating-point registers. We also handle vector floats the same
4945 say, which is OK because they are not covered by the standard ABI. */
4946 info
->fpr_p
= (!cum
->gp_reg_found
4947 && cum
->arg_number
< 2
4949 || SCALAR_FLOAT_TYPE_P (type
)
4950 || VECTOR_FLOAT_TYPE_P (type
))
4951 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4952 || mode
== V2SFmode
)
4953 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4958 /* Scalar, complex and vector floating-point types are passed in
4959 floating-point registers, as long as this is a named rather
4960 than a variable argument. */
4961 info
->fpr_p
= (named
4962 && (type
== 0 || FLOAT_TYPE_P (type
))
4963 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4964 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4965 || mode
== V2SFmode
)
4966 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4968 /* ??? According to the ABI documentation, the real and imaginary
4969 parts of complex floats should be passed in individual registers.
4970 The real and imaginary parts of stack arguments are supposed
4971 to be contiguous and there should be an extra word of padding
4974 This has two problems. First, it makes it impossible to use a
4975 single "void *" va_list type, since register and stack arguments
4976 are passed differently. (At the time of writing, MIPSpro cannot
4977 handle complex float varargs correctly.) Second, it's unclear
4978 what should happen when there is only one register free.
4980 For now, we assume that named complex floats should go into FPRs
4981 if there are two FPRs free, otherwise they should be passed in the
4982 same way as a struct containing two floats. */
4984 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4985 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4987 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4988 info
->fpr_p
= false;
4998 /* See whether the argument has doubleword alignment. */
4999 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5002 /* Set REG_OFFSET to the register count we're interested in.
5003 The EABI allocates the floating-point registers separately,
5004 but the other ABIs allocate them like integer registers. */
5005 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5009 /* Advance to an even register if the argument is doubleword-aligned. */
5010 if (doubleword_aligned_p
)
5011 info
->reg_offset
+= info
->reg_offset
& 1;
5013 /* Work out the offset of a stack argument. */
5014 info
->stack_offset
= cum
->stack_words
;
5015 if (doubleword_aligned_p
)
5016 info
->stack_offset
+= info
->stack_offset
& 1;
5018 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5020 /* Partition the argument between registers and stack. */
5021 info
->reg_words
= MIN (num_words
, max_regs
);
5022 info
->stack_words
= num_words
- info
->reg_words
;
5025 /* INFO describes a register argument that has the normal format for the
5026 argument's mode. Return the register it uses, assuming that FPRs are
5027 available if HARD_FLOAT_P. */
5030 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5032 if (!info
->fpr_p
|| !hard_float_p
)
5033 return GP_ARG_FIRST
+ info
->reg_offset
;
5034 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5035 /* In o32, the second argument is always passed in $f14
5036 for TARGET_DOUBLE_FLOAT, regardless of whether the
5037 first argument was a word or doubleword. */
5038 return FP_ARG_FIRST
+ 2;
5040 return FP_ARG_FIRST
+ info
->reg_offset
;
5043 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5046 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5048 return !TARGET_OLDABI
;
5051 /* Implement TARGET_FUNCTION_ARG. */
5054 mips_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
5055 const_tree type
, bool named
)
5057 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5058 struct mips_arg_info info
;
5060 /* We will be called with a mode of VOIDmode after the last argument
5061 has been seen. Whatever we return will be passed to the call expander.
5062 If we need a MIPS16 fp_code, return a REG with the code stored as
5064 if (mode
== VOIDmode
)
5066 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5067 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
5072 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5074 /* Return straight away if the whole argument is passed on the stack. */
5075 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5078 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5079 contains a double in its entirety, then that 64-bit chunk is passed
5080 in a floating-point register. */
5082 && TARGET_HARD_FLOAT
5085 && TREE_CODE (type
) == RECORD_TYPE
5086 && TYPE_SIZE_UNIT (type
)
5087 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
5091 /* First check to see if there is any such field. */
5092 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5093 if (TREE_CODE (field
) == FIELD_DECL
5094 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5095 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5096 && host_integerp (bit_position (field
), 0)
5097 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5102 /* Now handle the special case by returning a PARALLEL
5103 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5104 chunks are passed in registers. */
5106 HOST_WIDE_INT bitpos
;
5109 /* assign_parms checks the mode of ENTRY_PARM, so we must
5110 use the actual mode here. */
5111 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5114 field
= TYPE_FIELDS (type
);
5115 for (i
= 0; i
< info
.reg_words
; i
++)
5119 for (; field
; field
= DECL_CHAIN (field
))
5120 if (TREE_CODE (field
) == FIELD_DECL
5121 && int_bit_position (field
) >= bitpos
)
5125 && int_bit_position (field
) == bitpos
5126 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5127 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5128 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5130 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
5133 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
5134 GEN_INT (bitpos
/ BITS_PER_UNIT
));
5136 bitpos
+= BITS_PER_WORD
;
5142 /* Handle the n32/n64 conventions for passing complex floating-point
5143 arguments in FPR pairs. The real part goes in the lower register
5144 and the imaginary part goes in the upper register. */
5147 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5150 enum machine_mode inner
;
5153 inner
= GET_MODE_INNER (mode
);
5154 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
5155 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
5157 /* Real part in registers, imaginary part on stack. */
5158 gcc_assert (info
.stack_words
== info
.reg_words
);
5159 return gen_rtx_REG (inner
, regno
);
5163 gcc_assert (info
.stack_words
== 0);
5164 real
= gen_rtx_EXPR_LIST (VOIDmode
,
5165 gen_rtx_REG (inner
, regno
),
5167 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
5169 regno
+ info
.reg_words
/ 2),
5170 GEN_INT (GET_MODE_SIZE (inner
)));
5171 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
5175 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
5178 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5181 mips_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
5182 const_tree type
, bool named
)
5184 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5185 struct mips_arg_info info
;
5187 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5190 cum
->gp_reg_found
= true;
5192 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5193 an explanation of what this code does. It assumes that we're using
5194 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5196 if (cum
->arg_number
< 2 && info
.fpr_p
)
5197 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
5199 /* Advance the register count. This has the effect of setting
5200 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5201 argument required us to skip the final GPR and pass the whole
5202 argument on the stack. */
5203 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
5204 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
5205 else if (info
.reg_words
> 0)
5206 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
5208 /* Advance the stack word count. */
5209 if (info
.stack_words
> 0)
5210 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5215 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5218 mips_arg_partial_bytes (cumulative_args_t cum
,
5219 enum machine_mode mode
, tree type
, bool named
)
5221 struct mips_arg_info info
;
5223 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
5224 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5227 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5228 least PARM_BOUNDARY bits of alignment, but will be given anything up
5229 to STACK_BOUNDARY bits if the type requires it. */
5232 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5234 unsigned int alignment
;
5236 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5237 if (alignment
< PARM_BOUNDARY
)
5238 alignment
= PARM_BOUNDARY
;
5239 if (alignment
> STACK_BOUNDARY
)
5240 alignment
= STACK_BOUNDARY
;
5244 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5245 upward rather than downward. In other words, return true if the
5246 first byte of the stack slot has useful data, false if the last
5250 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5252 /* On little-endian targets, the first byte of every stack argument
5253 is passed in the first byte of the stack slot. */
5254 if (!BYTES_BIG_ENDIAN
)
5257 /* Otherwise, integral types are padded downward: the last byte of a
5258 stack argument is passed in the last byte of the stack slot. */
5260 ? (INTEGRAL_TYPE_P (type
)
5261 || POINTER_TYPE_P (type
)
5262 || FIXED_POINT_TYPE_P (type
))
5263 : (SCALAR_INT_MODE_P (mode
)
5264 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5267 /* Big-endian o64 pads floating-point arguments downward. */
5268 if (mips_abi
== ABI_O64
)
5269 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5272 /* Other types are padded upward for o32, o64, n32 and n64. */
5273 if (mips_abi
!= ABI_EABI
)
5276 /* Arguments smaller than a stack slot are padded downward. */
5277 if (mode
!= BLKmode
)
5278 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5280 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5283 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5284 if the least significant byte of the register has useful data. Return
5285 the opposite if the most significant byte does. */
5288 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5290 /* No shifting is required for floating-point arguments. */
5291 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5292 return !BYTES_BIG_ENDIAN
;
5294 /* Otherwise, apply the same padding to register arguments as we do
5295 to stack arguments. */
5296 return mips_pad_arg_upward (mode
, type
);
5299 /* Return nonzero when an argument must be passed by reference. */
5302 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5303 enum machine_mode mode
, const_tree type
,
5304 bool named ATTRIBUTE_UNUSED
)
5306 if (mips_abi
== ABI_EABI
)
5310 /* ??? How should SCmode be handled? */
5311 if (mode
== DImode
|| mode
== DFmode
5312 || mode
== DQmode
|| mode
== UDQmode
5313 || mode
== DAmode
|| mode
== UDAmode
)
5316 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5317 return size
== -1 || size
> UNITS_PER_WORD
;
5321 /* If we have a variable-sized parameter, we have no choice. */
5322 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5326 /* Implement TARGET_CALLEE_COPIES. */
5329 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
5330 enum machine_mode mode ATTRIBUTE_UNUSED
,
5331 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5333 return mips_abi
== ABI_EABI
&& named
;
5336 /* See whether VALTYPE is a record whose fields should be returned in
5337 floating-point registers. If so, return the number of fields and
5338 list them in FIELDS (which should have two elements). Return 0
5341 For n32 & n64, a structure with one or two fields is returned in
5342 floating-point registers as long as every field has a floating-point
5346 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5354 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5358 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5360 if (TREE_CODE (field
) != FIELD_DECL
)
5363 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5369 fields
[i
++] = field
;
5374 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5375 a value in the most significant part of $2/$3 if:
5377 - the target is big-endian;
5379 - the value has a structure or union type (we generalize this to
5380 cover aggregates from other languages too); and
5382 - the structure is not returned in floating-point registers. */
5385 mips_return_in_msb (const_tree valtype
)
5389 return (TARGET_NEWABI
5390 && TARGET_BIG_ENDIAN
5391 && AGGREGATE_TYPE_P (valtype
)
5392 && mips_fpr_return_fields (valtype
, fields
) == 0);
5395 /* Return true if the function return value MODE will get returned in a
5396 floating-point register. */
5399 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5401 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5403 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5404 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5407 /* Return the representation of an FPR return register when the
5408 value being returned in FP_RETURN has mode VALUE_MODE and the
5409 return type itself has mode TYPE_MODE. On NewABI targets,
5410 the two modes may be different for structures like:
5412 struct __attribute__((packed)) foo { float f; }
5414 where we return the SFmode value of "f" in FP_RETURN, but where
5415 the structure itself has mode BLKmode. */
5418 mips_return_fpr_single (enum machine_mode type_mode
,
5419 enum machine_mode value_mode
)
5423 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5424 if (type_mode
!= value_mode
)
5426 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5427 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5432 /* Return a composite value in a pair of floating-point registers.
5433 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5434 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5437 For n32 & n64, $f0 always holds the first value and $f2 the second.
5438 Otherwise the values are packed together as closely as possible. */
5441 mips_return_fpr_pair (enum machine_mode mode
,
5442 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5443 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5447 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5448 return gen_rtx_PARALLEL
5451 gen_rtx_EXPR_LIST (VOIDmode
,
5452 gen_rtx_REG (mode1
, FP_RETURN
),
5454 gen_rtx_EXPR_LIST (VOIDmode
,
5455 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5456 GEN_INT (offset2
))));
5460 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5461 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5462 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5465 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
5466 enum machine_mode mode
)
5474 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
5475 func
= fn_decl_or_type
;
5479 mode
= TYPE_MODE (valtype
);
5480 unsigned_p
= TYPE_UNSIGNED (valtype
);
5482 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5483 return values, promote the mode here too. */
5484 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5486 /* Handle structures whose fields are returned in $f0/$f2. */
5487 switch (mips_fpr_return_fields (valtype
, fields
))
5490 return mips_return_fpr_single (mode
,
5491 TYPE_MODE (TREE_TYPE (fields
[0])));
5494 return mips_return_fpr_pair (mode
,
5495 TYPE_MODE (TREE_TYPE (fields
[0])),
5496 int_byte_position (fields
[0]),
5497 TYPE_MODE (TREE_TYPE (fields
[1])),
5498 int_byte_position (fields
[1]));
5501 /* If a value is passed in the most significant part of a register, see
5502 whether we have to round the mode up to a whole number of words. */
5503 if (mips_return_in_msb (valtype
))
5505 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5506 if (size
% UNITS_PER_WORD
!= 0)
5508 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5509 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5513 /* For EABI, the class of return register depends entirely on MODE.
5514 For example, "struct { some_type x; }" and "union { some_type x; }"
5515 are returned in the same way as a bare "some_type" would be.
5516 Other ABIs only use FPRs for scalar, complex or vector types. */
5517 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5518 return gen_rtx_REG (mode
, GP_RETURN
);
5523 /* Handle long doubles for n32 & n64. */
5525 return mips_return_fpr_pair (mode
,
5527 DImode
, GET_MODE_SIZE (mode
) / 2);
5529 if (mips_return_mode_in_fpr_p (mode
))
5531 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5532 return mips_return_fpr_pair (mode
,
5533 GET_MODE_INNER (mode
), 0,
5534 GET_MODE_INNER (mode
),
5535 GET_MODE_SIZE (mode
) / 2);
5537 return gen_rtx_REG (mode
, FP_RETURN
);
5541 return gen_rtx_REG (mode
, GP_RETURN
);
5544 /* Implement TARGET_FUNCTION_VALUE. */
5547 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
5548 bool outgoing ATTRIBUTE_UNUSED
)
5550 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
5553 /* Implement TARGET_LIBCALL_VALUE. */
5556 mips_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
5558 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
5561 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5563 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5564 Currently, R2 and F0 are only implemented here (C has no complex type). */
5567 mips_function_value_regno_p (const unsigned int regno
)
5569 if (regno
== GP_RETURN
5570 || regno
== FP_RETURN
5571 || (LONG_DOUBLE_TYPE_SIZE
== 128
5572 && FP_RETURN
!= GP_RETURN
5573 && regno
== FP_RETURN
+ 2))
5579 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5580 all BLKmode objects are returned in memory. Under the n32, n64
5581 and embedded ABIs, small structures are returned in a register.
5582 Objects with varying size must still be returned in memory, of
5586 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5588 return (TARGET_OLDABI
5589 ? TYPE_MODE (type
) == BLKmode
5590 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5593 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5596 mips_setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
5597 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5600 CUMULATIVE_ARGS local_cum
;
5601 int gp_saved
, fp_saved
;
5603 /* The caller has advanced CUM up to, but not beyond, the last named
5604 argument. Advance a local copy of CUM past the last "real" named
5605 argument, to find out how many registers are left over. */
5606 local_cum
= *get_cumulative_args (cum
);
5607 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
5610 /* Found out how many registers we need to save. */
5611 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5612 fp_saved
= (EABI_FLOAT_VARARGS_P
5613 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5622 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
5623 REG_PARM_STACK_SPACE (cfun
->decl
)
5624 - gp_saved
* UNITS_PER_WORD
);
5625 mem
= gen_frame_mem (BLKmode
, ptr
);
5626 set_mem_alias_set (mem
, get_varargs_alias_set ());
5628 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5633 /* We can't use move_block_from_reg, because it will use
5635 enum machine_mode mode
;
5638 /* Set OFF to the offset from virtual_incoming_args_rtx of
5639 the first float register. The FP save area lies below
5640 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5641 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5642 off
-= fp_saved
* UNITS_PER_FPREG
;
5644 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5646 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5647 i
+= MAX_FPRS_PER_FMT
)
5651 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
5652 mem
= gen_frame_mem (mode
, ptr
);
5653 set_mem_alias_set (mem
, get_varargs_alias_set ());
5654 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5655 off
+= UNITS_PER_HWFPVALUE
;
5659 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5660 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5661 + fp_saved
* UNITS_PER_FPREG
);
5664 /* Implement TARGET_BUILTIN_VA_LIST. */
5667 mips_build_builtin_va_list (void)
5669 if (EABI_FLOAT_VARARGS_P
)
5671 /* We keep 3 pointers, and two offsets.
5673 Two pointers are to the overflow area, which starts at the CFA.
5674 One of these is constant, for addressing into the GPR save area
5675 below it. The other is advanced up the stack through the
5678 The third pointer is to the bottom of the GPR save area.
5679 Since the FPR save area is just below it, we can address
5680 FPR slots off this pointer.
5682 We also keep two one-byte offsets, which are to be subtracted
5683 from the constant pointers to yield addresses in the GPR and
5684 FPR save areas. These are downcounted as float or non-float
5685 arguments are used, and when they get to zero, the argument
5686 must be obtained from the overflow region. */
5687 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5690 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5692 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5693 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5695 f_gtop
= build_decl (BUILTINS_LOCATION
,
5696 FIELD_DECL
, get_identifier ("__gpr_top"),
5698 f_ftop
= build_decl (BUILTINS_LOCATION
,
5699 FIELD_DECL
, get_identifier ("__fpr_top"),
5701 f_goff
= build_decl (BUILTINS_LOCATION
,
5702 FIELD_DECL
, get_identifier ("__gpr_offset"),
5703 unsigned_char_type_node
);
5704 f_foff
= build_decl (BUILTINS_LOCATION
,
5705 FIELD_DECL
, get_identifier ("__fpr_offset"),
5706 unsigned_char_type_node
);
5707 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5708 warn on every user file. */
5709 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5710 array
= build_array_type (unsigned_char_type_node
,
5711 build_index_type (index
));
5712 f_res
= build_decl (BUILTINS_LOCATION
,
5713 FIELD_DECL
, get_identifier ("__reserved"), array
);
5715 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5716 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5717 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5718 DECL_FIELD_CONTEXT (f_goff
) = record
;
5719 DECL_FIELD_CONTEXT (f_foff
) = record
;
5720 DECL_FIELD_CONTEXT (f_res
) = record
;
5722 TYPE_FIELDS (record
) = f_ovfl
;
5723 DECL_CHAIN (f_ovfl
) = f_gtop
;
5724 DECL_CHAIN (f_gtop
) = f_ftop
;
5725 DECL_CHAIN (f_ftop
) = f_goff
;
5726 DECL_CHAIN (f_goff
) = f_foff
;
5727 DECL_CHAIN (f_foff
) = f_res
;
5729 layout_type (record
);
5733 /* Otherwise, we use 'void *'. */
5734 return ptr_type_node
;
5737 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5740 mips_va_start (tree valist
, rtx nextarg
)
5742 if (EABI_FLOAT_VARARGS_P
)
5744 const CUMULATIVE_ARGS
*cum
;
5745 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5746 tree ovfl
, gtop
, ftop
, goff
, foff
;
5748 int gpr_save_area_size
;
5749 int fpr_save_area_size
;
5752 cum
= &crtl
->args
.info
;
5754 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5756 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5758 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5759 f_gtop
= DECL_CHAIN (f_ovfl
);
5760 f_ftop
= DECL_CHAIN (f_gtop
);
5761 f_goff
= DECL_CHAIN (f_ftop
);
5762 f_foff
= DECL_CHAIN (f_goff
);
5764 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5766 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5768 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5770 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5772 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5775 /* Emit code to initialize OVFL, which points to the next varargs
5776 stack argument. CUM->STACK_WORDS gives the number of stack
5777 words used by named arguments. */
5778 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5779 if (cum
->stack_words
> 0)
5780 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
5781 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5782 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5784 /* Emit code to initialize GTOP, the top of the GPR save area. */
5785 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5786 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5787 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5789 /* Emit code to initialize FTOP, the top of the FPR save area.
5790 This address is gpr_save_area_bytes below GTOP, rounded
5791 down to the next fp-aligned boundary. */
5792 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5793 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5794 fpr_offset
&= -UNITS_PER_FPVALUE
;
5796 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
5797 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5798 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5800 /* Emit code to initialize GOFF, the offset from GTOP of the
5801 next GPR argument. */
5802 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5803 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5804 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5806 /* Likewise emit code to initialize FOFF, the offset from FTOP
5807 of the next FPR argument. */
5808 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5809 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5810 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5814 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
5815 std_expand_builtin_va_start (valist
, nextarg
);
5819 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5823 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5826 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
5827 unsigned HOST_WIDE_INT align
, boundary
;
5830 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
5832 type
= build_pointer_type (type
);
5834 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
5835 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
5837 /* When we align parameter on stack for caller, if the parameter
5838 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5839 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5840 here with caller. */
5841 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
5842 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
5844 boundary
/= BITS_PER_UNIT
;
5846 /* Hoist the valist value into a temporary for the moment. */
5847 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
5849 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5850 requires greater alignment, we must perform dynamic alignment. */
5851 if (boundary
> align
)
5853 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5854 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
5855 gimplify_and_add (t
, pre_p
);
5857 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
5858 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
5860 build_int_cst (TREE_TYPE (valist
), -boundary
)));
5861 gimplify_and_add (t
, pre_p
);
5866 /* If the actual alignment is less than the alignment of the type,
5867 adjust the type accordingly so that we don't assume strict alignment
5868 when dereferencing the pointer. */
5869 boundary
*= BITS_PER_UNIT
;
5870 if (boundary
< TYPE_ALIGN (type
))
5872 type
= build_variant_type_copy (type
);
5873 TYPE_ALIGN (type
) = boundary
;
5876 /* Compute the rounded size of the type. */
5877 type_size
= size_in_bytes (type
);
5878 rounded_size
= round_up (type_size
, align
);
5880 /* Reduce rounded_size so it's sharable with the postqueue. */
5881 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
5885 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
5887 /* Small args are padded downward. */
5888 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
5889 rounded_size
, size_int (align
));
5890 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
5891 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
5892 addr
= fold_build_pointer_plus (addr
, t
);
5895 /* Compute new value for AP. */
5896 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
5897 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
5898 gimplify_and_add (t
, pre_p
);
5900 addr
= fold_convert (build_pointer_type (type
), addr
);
5903 addr
= build_va_arg_indirect_ref (addr
);
5905 return build_va_arg_indirect_ref (addr
);
5908 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5911 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5917 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5919 type
= build_pointer_type (type
);
5921 if (!EABI_FLOAT_VARARGS_P
)
5922 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5925 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5926 tree ovfl
, top
, off
, align
;
5927 HOST_WIDE_INT size
, rsize
, osize
;
5930 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5931 f_gtop
= DECL_CHAIN (f_ovfl
);
5932 f_ftop
= DECL_CHAIN (f_gtop
);
5933 f_goff
= DECL_CHAIN (f_ftop
);
5934 f_foff
= DECL_CHAIN (f_goff
);
5938 TOP be the top of the GPR or FPR save area;
5939 OFF be the offset from TOP of the next register;
5940 ADDR_RTX be the address of the argument;
5941 SIZE be the number of bytes in the argument type;
5942 RSIZE be the number of bytes used to store the argument
5943 when it's in the register save area; and
5944 OSIZE be the number of bytes used to store it when it's
5945 in the stack overflow area.
5947 The code we want is:
5949 1: off &= -rsize; // round down
5952 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5957 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5958 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5962 [1] and [9] can sometimes be optimized away. */
5964 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5966 size
= int_size_in_bytes (type
);
5968 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
5969 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
5971 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
5972 unshare_expr (valist
), f_ftop
, NULL_TREE
);
5973 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
5974 unshare_expr (valist
), f_foff
, NULL_TREE
);
5976 /* When va_start saves FPR arguments to the stack, each slot
5977 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5978 argument's precision. */
5979 rsize
= UNITS_PER_HWFPVALUE
;
5981 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5982 (= PARM_BOUNDARY bits). This can be different from RSIZE
5985 (1) On 32-bit targets when TYPE is a structure such as:
5987 struct s { float f; };
5989 Such structures are passed in paired FPRs, so RSIZE
5990 will be 8 bytes. However, the structure only takes
5991 up 4 bytes of memory, so OSIZE will only be 4.
5993 (2) In combinations such as -mgp64 -msingle-float
5994 -fshort-double. Doubles passed in registers will then take
5995 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5996 stack take up UNITS_PER_WORD bytes. */
5997 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6001 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6002 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6003 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6004 unshare_expr (valist
), f_goff
, NULL_TREE
);
6005 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
6006 if (rsize
> UNITS_PER_WORD
)
6008 /* [1] Emit code for: off &= -rsize. */
6009 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6010 build_int_cst (TREE_TYPE (off
), -rsize
));
6011 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6016 /* [2] Emit code to branch if off == 0. */
6017 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6018 build_int_cst (TREE_TYPE (off
), 0));
6019 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6021 /* [5] Emit code for: off -= rsize. We do this as a form of
6022 post-decrement not available to C. */
6023 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6024 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6026 /* [4] Emit code for:
6027 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6028 t
= fold_convert (sizetype
, t
);
6029 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6030 t
= fold_build_pointer_plus (top
, t
);
6031 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6032 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6033 COND_EXPR_THEN (addr
) = t
;
6035 if (osize
> UNITS_PER_WORD
)
6037 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6038 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6039 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6040 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6041 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6042 unshare_expr (ovfl
), t
);
6047 /* [10, 11] Emit code for:
6048 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6050 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6051 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6052 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6053 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6055 /* String [9] and [10, 11] together. */
6057 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6058 COND_EXPR_ELSE (addr
) = t
;
6060 addr
= fold_convert (build_pointer_type (type
), addr
);
6061 addr
= build_va_arg_indirect_ref (addr
);
6065 addr
= build_va_arg_indirect_ref (addr
);
6070 /* Declare a unique, locally-binding function called NAME, then start
6074 mips_start_unique_function (const char *name
)
6078 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6079 get_identifier (name
),
6080 build_function_type_list (void_type_node
, NULL_TREE
));
6081 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6082 NULL_TREE
, void_type_node
);
6083 TREE_PUBLIC (decl
) = 1;
6084 TREE_STATIC (decl
) = 1;
6086 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
6088 targetm
.asm_out
.unique_section (decl
, 0);
6089 switch_to_section (get_named_section (decl
, NULL
, 0));
6091 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6092 fputs ("\t.hidden\t", asm_out_file
);
6093 assemble_name (asm_out_file
, name
);
6094 putc ('\n', asm_out_file
);
6097 /* Start a definition of function NAME. MIPS16_P indicates whether the
6098 function contains MIPS16 code. */
6101 mips_start_function_definition (const char *name
, bool mips16_p
)
6104 fprintf (asm_out_file
, "\t.set\tmips16\n");
6106 fprintf (asm_out_file
, "\t.set\tnomips16\n");
6108 if (!flag_inhibit_size_directive
)
6110 fputs ("\t.ent\t", asm_out_file
);
6111 assemble_name (asm_out_file
, name
);
6112 fputs ("\n", asm_out_file
);
6115 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
6117 /* Start the definition proper. */
6118 assemble_name (asm_out_file
, name
);
6119 fputs (":\n", asm_out_file
);
6122 /* End a function definition started by mips_start_function_definition. */
6125 mips_end_function_definition (const char *name
)
6127 if (!flag_inhibit_size_directive
)
6129 fputs ("\t.end\t", asm_out_file
);
6130 assemble_name (asm_out_file
, name
);
6131 fputs ("\n", asm_out_file
);
6135 /* Output a definition of the __mips16_rdhwr function. */
6138 mips_output_mips16_rdhwr (void)
6142 name
= "__mips16_rdhwr";
6143 mips_start_unique_function (name
);
6144 mips_start_function_definition (name
, false);
6145 fprintf (asm_out_file
,
6147 "\t.set\tmips32r2\n"
6148 "\t.set\tnoreorder\n"
6152 mips_end_function_definition (name
);
6155 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6158 mips_ok_for_lazy_binding_p (rtx x
)
6160 return (TARGET_USE_GOT
6161 && GET_CODE (x
) == SYMBOL_REF
6162 && !SYMBOL_REF_BIND_NOW_P (x
)
6163 && !mips_symbol_binds_local_p (x
));
6166 /* Load function address ADDR into register DEST. TYPE is as for
6167 mips_expand_call. Return true if we used an explicit lazy-binding
6171 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
6173 /* If we're generating PIC, and this call is to a global function,
6174 try to allow its address to be resolved lazily. This isn't
6175 possible for sibcalls when $gp is call-saved because the value
6176 of $gp on entry to the stub would be our caller's gp, not ours. */
6177 if (TARGET_EXPLICIT_RELOCS
6178 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
6179 && mips_ok_for_lazy_binding_p (addr
))
6181 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
6182 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
6187 mips_emit_move (dest
, addr
);
6192 /* Each locally-defined hard-float MIPS16 function has a local symbol
6193 associated with it. This hash table maps the function symbol (FUNC)
6194 to the local symbol (LOCAL). */
6195 struct GTY(()) mips16_local_alias
{
6199 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
6201 /* Hash table callbacks for mips16_local_aliases. */
6204 mips16_local_aliases_hash (const void *entry
)
6206 const struct mips16_local_alias
*alias
;
6208 alias
= (const struct mips16_local_alias
*) entry
;
6209 return htab_hash_string (XSTR (alias
->func
, 0));
6213 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
6215 const struct mips16_local_alias
*alias1
, *alias2
;
6217 alias1
= (const struct mips16_local_alias
*) entry1
;
6218 alias2
= (const struct mips16_local_alias
*) entry2
;
6219 return rtx_equal_p (alias1
->func
, alias2
->func
);
6222 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6223 Return a local alias for it, creating a new one if necessary. */
6226 mips16_local_alias (rtx func
)
6228 struct mips16_local_alias
*alias
, tmp_alias
;
6231 /* Create the hash table if this is the first call. */
6232 if (mips16_local_aliases
== NULL
)
6233 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
6234 mips16_local_aliases_eq
, NULL
);
6236 /* Look up the function symbol, creating a new entry if need be. */
6237 tmp_alias
.func
= func
;
6238 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
6239 gcc_assert (slot
!= NULL
);
6241 alias
= (struct mips16_local_alias
*) *slot
;
6244 const char *func_name
, *local_name
;
6247 /* Create a new SYMBOL_REF for the local symbol. The choice of
6248 __fn_local_* is based on the __fn_stub_* names that we've
6249 traditionally used for the non-MIPS16 stub. */
6250 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
6251 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
6252 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
6253 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
6255 /* Create a new structure to represent the mapping. */
6256 alias
= ggc_alloc_mips16_local_alias ();
6258 alias
->local
= local
;
6261 return alias
->local
;
6264 /* A chained list of functions for which mips16_build_call_stub has already
6265 generated a stub. NAME is the name of the function and FP_RET_P is true
6266 if the function returns a value in floating-point registers. */
6267 struct mips16_stub
{
6268 struct mips16_stub
*next
;
6272 static struct mips16_stub
*mips16_stubs
;
6274 /* Return the two-character string that identifies floating-point
6275 return mode MODE in the name of a MIPS16 function stub. */
6278 mips16_call_stub_mode_suffix (enum machine_mode mode
)
6282 else if (mode
== DFmode
)
6284 else if (mode
== SCmode
)
6286 else if (mode
== DCmode
)
6288 else if (mode
== V2SFmode
)
6294 /* Write instructions to move a 32-bit value between general register
6295 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6296 from GPREG to FPREG and 'f' to move in the opposite direction. */
6299 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6301 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6302 reg_names
[gpreg
], reg_names
[fpreg
]);
6305 /* Likewise for 64-bit values. */
6308 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
6311 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
6312 reg_names
[gpreg
], reg_names
[fpreg
]);
6313 else if (TARGET_FLOAT64
)
6315 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6316 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6317 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
6318 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
6322 /* Move the least-significant word. */
6323 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6324 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
6325 /* ...then the most significant word. */
6326 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
6327 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
6331 /* Write out code to move floating-point arguments into or out of
6332 general registers. FP_CODE is the code describing which arguments
6333 are present (see the comment above the definition of CUMULATIVE_ARGS
6334 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6337 mips_output_args_xfer (int fp_code
, char direction
)
6339 unsigned int gparg
, fparg
, f
;
6340 CUMULATIVE_ARGS cum
;
6342 /* This code only works for o32 and o64. */
6343 gcc_assert (TARGET_OLDABI
);
6345 mips_init_cumulative_args (&cum
, NULL
);
6347 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6349 enum machine_mode mode
;
6350 struct mips_arg_info info
;
6354 else if ((f
& 3) == 2)
6359 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
6360 gparg
= mips_arg_regno (&info
, false);
6361 fparg
= mips_arg_regno (&info
, true);
6364 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6366 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6368 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
6372 /* Write a MIPS16 stub for the current function. This stub is used
6373 for functions which take arguments in the floating-point registers.
6374 It is normal-mode code that moves the floating-point arguments
6375 into the general registers and then jumps to the MIPS16 code. */
6378 mips16_build_function_stub (void)
6380 const char *fnname
, *alias_name
, *separator
;
6381 char *secname
, *stubname
;
6386 /* Create the name of the stub, and its unique section. */
6387 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6388 alias
= mips16_local_alias (symbol
);
6390 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6391 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6392 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6393 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6395 /* Build a decl for the stub. */
6396 stubdecl
= build_decl (BUILTINS_LOCATION
,
6397 FUNCTION_DECL
, get_identifier (stubname
),
6398 build_function_type_list (void_type_node
, NULL_TREE
));
6399 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6400 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6401 RESULT_DECL
, NULL_TREE
, void_type_node
);
6403 /* Output a comment. */
6404 fprintf (asm_out_file
, "\t# Stub function for %s (",
6405 current_function_name ());
6407 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6409 fprintf (asm_out_file
, "%s%s", separator
,
6410 (f
& 3) == 1 ? "float" : "double");
6413 fprintf (asm_out_file
, ")\n");
6415 /* Start the function definition. */
6416 assemble_start_function (stubdecl
, stubname
);
6417 mips_start_function_definition (stubname
, false);
6419 /* If generating pic2 code, either set up the global pointer or
6421 if (TARGET_ABICALLS_PIC2
)
6423 if (TARGET_ABSOLUTE_ABICALLS
)
6424 fprintf (asm_out_file
, "\t.option\tpic0\n");
6427 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6428 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6429 target function is. Use a local GOT access when loading the
6430 symbol, to cut down on the number of unnecessary GOT entries
6431 for stubs that aren't needed. */
6432 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6437 /* Load the address of the MIPS16 function into $25. Do this first so
6438 that targets with coprocessor interlocks can use an MFC1 to fill the
6440 output_asm_insn ("la\t%^,%0", &symbol
);
6442 /* Move the arguments from floating-point registers to general registers. */
6443 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6445 /* Jump to the MIPS16 function. */
6446 output_asm_insn ("jr\t%^", NULL
);
6448 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6449 fprintf (asm_out_file
, "\t.option\tpic2\n");
6451 mips_end_function_definition (stubname
);
6453 /* If the linker needs to create a dynamic symbol for the target
6454 function, it will associate the symbol with the stub (which,
6455 unlike the target function, follows the proper calling conventions).
6456 It is therefore useful to have a local alias for the target function,
6457 so that it can still be identified as MIPS16 code. As an optimization,
6458 this symbol can also be used for indirect MIPS16 references from
6459 within this file. */
6460 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6462 switch_to_section (function_section (current_function_decl
));
6465 /* The current function is a MIPS16 function that returns a value in an FPR.
6466 Copy the return value from its soft-float to its hard-float location.
6467 libgcc2 has special non-MIPS16 helper functions for each case. */
6470 mips16_copy_fpr_return_value (void)
6472 rtx fn
, insn
, retval
;
6474 enum machine_mode return_mode
;
6477 return_type
= DECL_RESULT (current_function_decl
);
6478 return_mode
= DECL_MODE (return_type
);
6480 name
= ACONCAT (("__mips16_ret_",
6481 mips16_call_stub_mode_suffix (return_mode
),
6483 fn
= mips16_stub_function (name
);
6485 /* The function takes arguments in $2 (and possibly $3), so calls
6486 to it cannot be lazily bound. */
6487 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6489 /* Model the call as something that takes the GPR return value as
6490 argument and returns an "updated" value. */
6491 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6492 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6493 const0_rtx
, NULL_RTX
, false);
6494 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6497 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6498 RETVAL is the location of the return value, or null if this is
6499 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6500 arguments and FP_CODE is the code built by mips_function_arg;
6501 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6503 There are three alternatives:
6505 - If a stub was needed, emit the call and return the call insn itself.
6507 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6508 to the new target and return null.
6510 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6513 A stub is needed for calls to functions that, in normal mode,
6514 receive arguments in FPRs or return values in FPRs. The stub
6515 copies the arguments from their soft-float positions to their
6516 hard-float positions, calls the real function, then copies the
6517 return value from its hard-float position to its soft-float
6520 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6521 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6522 automatically redirects the JAL to the stub, otherwise the JAL
6523 continues to call FN directly. */
6526 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6530 struct mips16_stub
*l
;
6533 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6534 we were invoked with the -msoft-float option. */
6535 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6538 /* Figure out whether the value might come back in a floating-point
6540 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6542 /* We don't need to do anything if there were no floating-point
6543 arguments and the value will not be returned in a floating-point
6545 if (fp_code
== 0 && !fp_ret_p
)
6548 /* We don't need to do anything if this is a call to a special
6549 MIPS16 support function. */
6551 if (mips16_stub_function_p (fn
))
6554 /* If we're calling a locally-defined MIPS16 function, we know that
6555 it will return values in both the "soft-float" and "hard-float"
6556 registers. There is no need to use a stub to move the latter
6558 if (fp_code
== 0 && mips16_local_function_p (fn
))
6561 /* This code will only work for o32 and o64 abis. The other ABI's
6562 require more sophisticated support. */
6563 gcc_assert (TARGET_OLDABI
);
6565 /* If we're calling via a function pointer, use one of the magic
6566 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6567 Each stub expects the function address to arrive in register $2. */
6568 if (GET_CODE (fn
) != SYMBOL_REF
6569 || !call_insn_operand (fn
, VOIDmode
))
6572 rtx stub_fn
, insn
, addr
;
6575 /* If this is a locally-defined and locally-binding function,
6576 avoid the stub by calling the local alias directly. */
6577 if (mips16_local_function_p (fn
))
6579 *fn_ptr
= mips16_local_alias (fn
);
6583 /* Create a SYMBOL_REF for the libgcc.a function. */
6585 sprintf (buf
, "__mips16_call_stub_%s_%d",
6586 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6589 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6590 stub_fn
= mips16_stub_function (buf
);
6592 /* The function uses $2 as an argument, so calls to it
6593 cannot be lazily bound. */
6594 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6596 /* Load the target function into $2. */
6597 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6598 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6600 /* Emit the call. */
6601 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6602 args_size
, NULL_RTX
, lazy_p
);
6604 /* Tell GCC that this call does indeed use the value of $2. */
6605 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6607 /* If we are handling a floating-point return value, we need to
6608 save $18 in the function prologue. Putting a note on the
6609 call will mean that df_regs_ever_live_p ($18) will be true if the
6610 call is not eliminated, and we can check that in the prologue
6613 CALL_INSN_FUNCTION_USAGE (insn
) =
6614 gen_rtx_EXPR_LIST (VOIDmode
,
6615 gen_rtx_CLOBBER (VOIDmode
,
6616 gen_rtx_REG (word_mode
, 18)),
6617 CALL_INSN_FUNCTION_USAGE (insn
));
6622 /* We know the function we are going to call. If we have already
6623 built a stub, we don't need to do anything further. */
6624 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6625 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6626 if (strcmp (l
->name
, fnname
) == 0)
6631 const char *separator
;
6632 char *secname
, *stubname
;
6633 tree stubid
, stubdecl
;
6636 /* If the function does not return in FPRs, the special stub
6640 If the function does return in FPRs, the stub section is named
6641 .mips16.call.fp.FNNAME
6643 Build a decl for the stub. */
6644 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6646 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6648 stubid
= get_identifier (stubname
);
6649 stubdecl
= build_decl (BUILTINS_LOCATION
,
6650 FUNCTION_DECL
, stubid
,
6651 build_function_type_list (void_type_node
,
6653 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6654 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6655 RESULT_DECL
, NULL_TREE
,
6658 /* Output a comment. */
6659 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6661 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6665 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6667 fprintf (asm_out_file
, "%s%s", separator
,
6668 (f
& 3) == 1 ? "float" : "double");
6671 fprintf (asm_out_file
, ")\n");
6673 /* Start the function definition. */
6674 assemble_start_function (stubdecl
, stubname
);
6675 mips_start_function_definition (stubname
, false);
6679 fprintf (asm_out_file
, "\t.cfi_startproc\n");
6681 /* Create a fake CFA 4 bytes below the stack pointer.
6682 This works around unwinders (like libgcc's) that expect
6683 the CFA for non-signal frames to be unique. */
6684 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
6686 /* "Save" $sp in itself so we don't use the fake CFA.
6687 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6688 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
6692 /* Load the address of the MIPS16 function into $25. Do this
6693 first so that targets with coprocessor interlocks can use
6694 an MFC1 to fill the delay slot. */
6695 if (TARGET_EXPLICIT_RELOCS
)
6697 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6698 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6701 output_asm_insn ("la\t%^,%0", &fn
);
6704 /* Move the arguments from general registers to floating-point
6706 mips_output_args_xfer (fp_code
, 't');
6710 /* Save the return address in $18 and call the non-MIPS16 function.
6711 The stub's caller knows that $18 might be clobbered, even though
6712 $18 is usually a call-saved register. */
6713 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6714 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6715 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6716 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
6718 /* Move the result from floating-point registers to
6719 general registers. */
6720 switch (GET_MODE (retval
))
6723 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6725 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6727 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6728 TARGET_LITTLE_ENDIAN
6729 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6731 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6733 /* On 64-bit targets, complex floats are returned in
6734 a single GPR, such that "sd" on a suitably-aligned
6735 target would store the value correctly. */
6736 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6737 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6738 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6739 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6740 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6741 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6742 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6743 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6744 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6745 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6746 reg_names
[GP_RETURN
],
6747 reg_names
[GP_RETURN
],
6748 reg_names
[GP_RETURN
+ 1]);
6753 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6757 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6758 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6762 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6768 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6769 fprintf (asm_out_file
, "\t.cfi_endproc\n");
6773 /* Jump to the previously-loaded address. */
6774 output_asm_insn ("jr\t%^", NULL
);
6777 #ifdef ASM_DECLARE_FUNCTION_SIZE
6778 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6781 mips_end_function_definition (stubname
);
6783 /* Record this stub. */
6784 l
= XNEW (struct mips16_stub
);
6785 l
->name
= xstrdup (fnname
);
6786 l
->fp_ret_p
= fp_ret_p
;
6787 l
->next
= mips16_stubs
;
6791 /* If we expect a floating-point return value, but we've built a
6792 stub which does not expect one, then we're in trouble. We can't
6793 use the existing stub, because it won't handle the floating-point
6794 value. We can't build a new stub, because the linker won't know
6795 which stub to use for the various calls in this object file.
6796 Fortunately, this case is illegal, since it means that a function
6797 was declared in two different ways in a single compilation. */
6798 if (fp_ret_p
&& !l
->fp_ret_p
)
6799 error ("cannot handle inconsistent calls to %qs", fnname
);
6801 if (retval
== NULL_RTX
)
6802 insn
= gen_call_internal_direct (fn
, args_size
);
6804 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6805 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6807 /* If we are calling a stub which handles a floating-point return
6808 value, we need to arrange to save $18 in the prologue. We do this
6809 by marking the function call as using the register. The prologue
6810 will later see that it is used, and emit code to save it. */
6812 CALL_INSN_FUNCTION_USAGE (insn
) =
6813 gen_rtx_EXPR_LIST (VOIDmode
,
6814 gen_rtx_CLOBBER (VOIDmode
,
6815 gen_rtx_REG (word_mode
, 18)),
6816 CALL_INSN_FUNCTION_USAGE (insn
));
6821 /* Expand a call of type TYPE. RESULT is where the result will go (null
6822 for "call"s and "sibcall"s), ADDR is the address of the function,
6823 ARGS_SIZE is the size of the arguments and AUX is the value passed
6824 to us by mips_function_arg. LAZY_P is true if this call already
6825 involves a lazily-bound function address (such as when calling
6826 functions through a MIPS16 hard-float stub).
6828 Return the call itself. */
6831 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6832 rtx args_size
, rtx aux
, bool lazy_p
)
6834 rtx orig_addr
, pattern
, insn
;
6837 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6838 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6841 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6846 if (!call_insn_operand (addr
, VOIDmode
))
6848 if (type
== MIPS_CALL_EPILOGUE
)
6849 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6851 addr
= gen_reg_rtx (Pmode
);
6852 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6857 rtx (*fn
) (rtx
, rtx
);
6859 if (type
== MIPS_CALL_SIBCALL
)
6860 fn
= gen_sibcall_internal
;
6862 fn
= gen_call_internal
;
6864 pattern
= fn (addr
, args_size
);
6866 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6868 /* Handle return values created by mips_return_fpr_pair. */
6869 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6872 if (type
== MIPS_CALL_SIBCALL
)
6873 fn
= gen_sibcall_value_multiple_internal
;
6875 fn
= gen_call_value_multiple_internal
;
6877 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6878 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6879 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6883 rtx (*fn
) (rtx
, rtx
, rtx
);
6885 if (type
== MIPS_CALL_SIBCALL
)
6886 fn
= gen_sibcall_value_internal
;
6888 fn
= gen_call_value_internal
;
6890 /* Handle return values created by mips_return_fpr_single. */
6891 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6892 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6893 pattern
= fn (result
, addr
, args_size
);
6896 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6899 /* Split call instruction INSN into a $gp-clobbering call and
6900 (where necessary) an instruction to restore $gp from its save slot.
6901 CALL_PATTERN is the pattern of the new call. */
6904 mips_split_call (rtx insn
, rtx call_pattern
)
6906 emit_call_insn (call_pattern
);
6907 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6908 /* Pick a temporary register that is suitable for both MIPS16 and
6909 non-MIPS16 code. $4 and $5 are used for returning complex double
6910 values in soft-float code, so $6 is the first suitable candidate. */
6911 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6914 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6917 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
6919 if (!TARGET_SIBCALLS
)
6922 /* Interrupt handlers need special epilogue code and therefore can't
6924 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
6927 /* We can't do a sibcall if the called function is a MIPS16 function
6928 because there is no direct "jx" instruction equivalent to "jalx" to
6929 switch the ISA mode. We only care about cases where the sibling
6930 and normal calls would both be direct. */
6932 && mips_use_mips16_mode_p (decl
)
6933 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6936 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6937 functions could be MIPS16 ones unless an attribute explicitly tells
6939 if (TARGET_INTERLINK_MIPS16
6941 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
6942 && !mips_nomips16_decl_p (decl
)
6943 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6950 /* Emit code to move general operand SRC into condition-code
6951 register DEST given that SCRATCH is a scratch TFmode FPR.
6958 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6961 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
6965 /* Change the source to SFmode. */
6967 src
= adjust_address (src
, SFmode
, 0);
6968 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
6969 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
6971 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
6972 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
6974 mips_emit_move (copy_rtx (fp1
), src
);
6975 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
6976 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
6979 /* Implement MOVE_BY_PIECES_P. */
6982 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
6986 /* movmemsi is meant to generate code that is at least as good as
6987 move_by_pieces. However, movmemsi effectively uses a by-pieces
6988 implementation both for moves smaller than a word and for
6989 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6990 bytes. We should allow the tree-level optimisers to do such
6991 moves by pieces, as it often exposes other optimization
6992 opportunities. We might as well continue to use movmemsi at
6993 the rtl level though, as it produces better code when
6994 scheduling is disabled (such as at -O). */
6995 if (currently_expanding_to_rtl
)
6997 if (align
< BITS_PER_WORD
)
6998 return size
< UNITS_PER_WORD
;
6999 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7001 /* The default value. If this becomes a target hook, we should
7002 call the default definition instead. */
7003 return (move_by_pieces_ninsns (size
, align
, MOVE_MAX_PIECES
+ 1)
7004 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7007 /* Implement STORE_BY_PIECES_P. */
7010 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7012 /* Storing by pieces involves moving constants into registers
7013 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7014 We need to decide whether it is cheaper to load the address of
7015 constant data into a register and use a block move instead. */
7017 /* If the data is only byte aligned, then:
7019 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7020 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7023 (a2) A block move of 4 bytes from aligned source data can use an
7024 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7025 4 SBs that we would generate when storing by pieces. */
7026 if (align
<= BITS_PER_UNIT
)
7029 /* If the data is 2-byte aligned, then:
7031 (b1) A block move of less than 4 bytes would use a combination of LBs,
7032 LHs, SBs and SHs. We get better code by using single-instruction
7033 LIs, SBs and SHs instead.
7035 (b2) A block move of 4 bytes from aligned source data would again use
7036 an LW/SWL/SWR sequence. In most cases, loading the address of
7037 the source data would require at least one extra instruction.
7038 It is often more efficient to use 2 single-instruction LIs and
7041 (b3) A block move of up to 3 additional bytes would be like (b1).
7043 (b4) A block move of 8 bytes from aligned source data can use two
7044 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7045 sequences are better than the 4 LIs and 4 SHs that we'd generate
7046 when storing by pieces.
7048 The reasoning for higher alignments is similar:
7050 (c1) A block move of less than 4 bytes would be the same as (b1).
7052 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7053 loading the address of the source data would typically require
7054 at least one extra instruction. It is generally better to use
7057 (c3) A block move of up to 3 additional bytes would be like (b1).
7059 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7060 LD/SD sequence, and in these cases we've traditionally preferred
7061 the memory copy over the more bulky constant moves. */
7065 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7066 Assume that the areas do not overlap. */
7069 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7071 HOST_WIDE_INT offset
, delta
;
7072 unsigned HOST_WIDE_INT bits
;
7074 enum machine_mode mode
;
7077 /* Work out how many bits to move at a time. If both operands have
7078 half-word alignment, it is usually better to move in half words.
7079 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7080 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7081 Otherwise move word-sized chunks. */
7082 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7083 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7084 bits
= BITS_PER_WORD
/ 2;
7086 bits
= BITS_PER_WORD
;
7088 mode
= mode_for_size (bits
, MODE_INT
, 0);
7089 delta
= bits
/ BITS_PER_UNIT
;
7091 /* Allocate a buffer for the temporary registers. */
7092 regs
= XALLOCAVEC (rtx
, length
/ delta
);
7094 /* Load as many BITS-sized chunks as possible. Use a normal load if
7095 the source has enough alignment, otherwise use left/right pairs. */
7096 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7098 regs
[i
] = gen_reg_rtx (mode
);
7099 if (MEM_ALIGN (src
) >= bits
)
7100 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
7103 rtx part
= adjust_address (src
, BLKmode
, offset
);
7104 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
7109 /* Copy the chunks to the destination. */
7110 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
7111 if (MEM_ALIGN (dest
) >= bits
)
7112 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
7115 rtx part
= adjust_address (dest
, BLKmode
, offset
);
7116 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
7120 /* Mop up any left-over bytes. */
7121 if (offset
< length
)
7123 src
= adjust_address (src
, BLKmode
, offset
);
7124 dest
= adjust_address (dest
, BLKmode
, offset
);
7125 move_by_pieces (dest
, src
, length
- offset
,
7126 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
7130 /* Helper function for doing a loop-based block operation on memory
7131 reference MEM. Each iteration of the loop will operate on LENGTH
7134 Create a new base register for use within the loop and point it to
7135 the start of MEM. Create a new memory reference that uses this
7136 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7139 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
7140 rtx
*loop_reg
, rtx
*loop_mem
)
7142 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
7144 /* Although the new mem does not refer to a known location,
7145 it does keep up to LENGTH bytes of alignment. */
7146 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
7147 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
7150 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7151 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7152 the memory regions do not overlap. */
7155 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
7156 HOST_WIDE_INT bytes_per_iter
)
7158 rtx label
, src_reg
, dest_reg
, final_src
, test
;
7159 HOST_WIDE_INT leftover
;
7161 leftover
= length
% bytes_per_iter
;
7164 /* Create registers and memory references for use within the loop. */
7165 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
7166 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
7168 /* Calculate the value that SRC_REG should have after the last iteration
7170 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
7173 /* Emit the start of the loop. */
7174 label
= gen_label_rtx ();
7177 /* Emit the loop body. */
7178 mips_block_move_straight (dest
, src
, bytes_per_iter
);
7180 /* Move on to the next block. */
7181 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
7182 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
7184 /* Emit the loop condition. */
7185 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
7186 if (Pmode
== DImode
)
7187 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
7189 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
7191 /* Mop up any left-over bytes. */
7193 mips_block_move_straight (dest
, src
, leftover
);
7196 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7197 memory reference SRC to memory reference DEST. */
7200 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
7202 if (CONST_INT_P (length
))
7204 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
7206 mips_block_move_straight (dest
, src
, INTVAL (length
));
7211 mips_block_move_loop (dest
, src
, INTVAL (length
),
7212 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
7219 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7222 mips_expand_synci_loop (rtx begin
, rtx end
)
7224 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
7226 /* Create end_label. */
7227 end_label
= gen_label_rtx ();
7229 /* Check if begin equals end. */
7230 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
7231 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7233 /* Load INC with the cache line size (rdhwr INC,$1). */
7234 inc
= gen_reg_rtx (Pmode
);
7235 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
7237 /* Check if inc is 0. */
7238 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
7239 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
7241 /* Calculate mask. */
7242 mask
= mips_force_unary (Pmode
, NEG
, inc
);
7244 /* Mask out begin by mask. */
7245 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
7247 /* Calculate length. */
7248 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
7250 /* Loop back to here. */
7251 label
= gen_label_rtx ();
7254 emit_insn (gen_synci (begin
));
7256 /* Update length. */
7257 mips_emit_binary (MINUS
, length
, length
, inc
);
7260 mips_emit_binary (PLUS
, begin
, begin
, inc
);
7262 /* Check if length is greater than 0. */
7263 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
7264 emit_jump_insn (gen_condjump (cmp_result
, label
));
7266 emit_label (end_label
);
7269 /* Expand a QI or HI mode atomic memory operation.
7271 GENERATOR contains a pointer to the gen_* function that generates
7272 the SI mode underlying atomic operation using masks that we
7275 RESULT is the return register for the operation. Its value is NULL
7278 MEM is the location of the atomic access.
7280 OLDVAL is the first operand for the operation.
7282 NEWVAL is the optional second operand for the operation. Its value
7283 is NULL if unused. */
7286 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
7287 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
7289 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
7290 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
7292 enum machine_mode mode
;
7294 mode
= GET_MODE (mem
);
7296 /* Compute the address of the containing SImode value. */
7297 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
7298 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
7299 force_reg (Pmode
, GEN_INT (-4)));
7301 /* Create a memory reference for it. */
7302 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
7303 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
7304 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
7306 /* Work out the byte offset of the QImode or HImode value,
7307 counting from the least significant byte. */
7308 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
7309 if (TARGET_BIG_ENDIAN
)
7310 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
7312 /* Multiply by eight to convert the shift value from bytes to bits. */
7313 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
7315 /* Make the final shift an SImode value, so that it can be used in
7316 SImode operations. */
7317 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
7319 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7320 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
7321 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
7322 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
7324 /* Compute the equivalent exclusive mask. */
7325 inverted_mask
= gen_reg_rtx (SImode
);
7326 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
7327 gen_rtx_NOT (SImode
, mask
)));
7329 /* Shift the old value into place. */
7330 if (oldval
!= const0_rtx
)
7332 oldval
= convert_modes (SImode
, mode
, oldval
, true);
7333 oldval
= force_reg (SImode
, oldval
);
7334 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
7337 /* Do the same for the new value. */
7338 if (newval
&& newval
!= const0_rtx
)
7340 newval
= convert_modes (SImode
, mode
, newval
, true);
7341 newval
= force_reg (SImode
, newval
);
7342 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
7345 /* Do the SImode atomic access. */
7347 res
= gen_reg_rtx (SImode
);
7349 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
7351 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
7353 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
7359 /* Shift and convert the result. */
7360 mips_emit_binary (AND
, res
, res
, mask
);
7361 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
7362 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
7366 /* Return true if it is possible to use left/right accesses for a
7367 bitfield of WIDTH bits starting BITPOS bits into *OP. When
7368 returning true, update *OP, *LEFT and *RIGHT as follows:
7370 *OP is a BLKmode reference to the whole field.
7372 *LEFT is a QImode reference to the first byte if big endian or
7373 the last byte if little endian. This address can be used in the
7374 left-side instructions (LWL, SWL, LDL, SDL).
7376 *RIGHT is a QImode reference to the opposite end of the field and
7377 can be used in the patterning right-side instruction. */
7380 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
7381 rtx
*left
, rtx
*right
)
7385 /* Check that the operand really is a MEM. Not all the extv and
7386 extzv predicates are checked. */
7390 /* Check that the size is valid. */
7391 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
7394 /* We can only access byte-aligned values. Since we are always passed
7395 a reference to the first byte of the field, it is not necessary to
7396 do anything with BITPOS after this check. */
7397 if (bitpos
% BITS_PER_UNIT
!= 0)
7400 /* Reject aligned bitfields: we want to use a normal load or store
7401 instead of a left/right pair. */
7402 if (MEM_ALIGN (*op
) >= width
)
7405 /* Create a copy of *OP that refers to the whole field. This also has
7406 the effect of legitimizing *OP's address for BLKmode, possibly
7408 *op
= copy_rtx (adjust_address (*op
, BLKmode
, 0));
7409 set_mem_size (*op
, width
/ BITS_PER_UNIT
);
7411 /* Get references to both ends of the field. We deliberately don't
7412 use the original QImode *OP for FIRST since the new BLKmode one
7413 might have a simpler address. */
7414 first
= adjust_address (*op
, QImode
, 0);
7415 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
7417 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7418 correspond to the MSB and RIGHT to the LSB. */
7419 if (TARGET_BIG_ENDIAN
)
7420 *left
= first
, *right
= last
;
7422 *left
= last
, *right
= first
;
7427 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7428 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7429 the operation is the equivalent of:
7431 (set DEST (*_extract SRC WIDTH BITPOS))
7433 Return true on success. */
7436 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7437 HOST_WIDE_INT bitpos
, bool unsigned_p
)
7439 rtx left
, right
, temp
;
7440 rtx dest1
= NULL_RTX
;
7442 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7443 be a paradoxical word_mode subreg. This is the only case in which
7444 we allow the destination to be larger than the source. */
7445 if (GET_CODE (dest
) == SUBREG
7446 && GET_MODE (dest
) == DImode
7447 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
7448 dest
= SUBREG_REG (dest
);
7450 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7451 be a DImode, create a new temp and emit a zero extend at the end. */
7452 if (GET_MODE (dest
) == DImode
7454 && GET_MODE_BITSIZE (SImode
) == width
)
7457 dest
= gen_reg_rtx (SImode
);
7460 /* After the above adjustment, the destination must be the same
7461 width as the source. */
7462 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
7465 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
7468 temp
= gen_reg_rtx (GET_MODE (dest
));
7469 if (GET_MODE (dest
) == DImode
)
7471 emit_insn (gen_mov_ldl (temp
, src
, left
));
7472 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
7476 emit_insn (gen_mov_lwl (temp
, src
, left
));
7477 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7480 /* If we were loading 32bits and the original register was DI then
7481 sign/zero extend into the orignal dest. */
7485 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
7487 emit_insn (gen_extendsidi2 (dest1
, dest
));
7492 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7493 BITPOS and SRC are the operands passed to the expander; the operation
7494 is the equivalent of:
7496 (set (zero_extract DEST WIDTH BITPOS) SRC)
7498 Return true on success. */
7501 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7502 HOST_WIDE_INT bitpos
)
7505 enum machine_mode mode
;
7507 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
7510 mode
= mode_for_size (width
, MODE_INT
, 0);
7511 src
= gen_lowpart (mode
, src
);
7514 emit_insn (gen_mov_sdl (dest
, src
, left
));
7515 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7519 emit_insn (gen_mov_swl (dest
, src
, left
));
7520 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7525 /* Return true if X is a MEM with the same size as MODE. */
7528 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7531 && MEM_SIZE_KNOWN_P (x
)
7532 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
7535 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7536 source of an "ext" instruction or the destination of an "ins"
7537 instruction. OP must be a register operand and the following
7538 conditions must hold:
7540 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7541 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7542 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7544 Also reject lengths equal to a word as they are better handled
7545 by the move patterns. */
7548 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7550 if (!ISA_HAS_EXT_INS
7551 || !register_operand (op
, VOIDmode
)
7552 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7555 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7558 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7564 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7565 operation if MAXLEN is the maxium length of consecutive bits that
7566 can make up MASK. MODE is the mode of the operation. See
7567 mask_low_and_shift_len for the actual definition. */
7570 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7572 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7575 /* Return true iff OP1 and OP2 are valid operands together for the
7576 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7577 see the table in the comment before the pattern. */
7580 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7582 return (memory_operand (op1
, mode
)
7583 ? and_load_operand (op2
, mode
)
7584 : and_reg_operand (op2
, mode
));
7587 /* The canonical form of a mask-low-and-shift-left operation is
7588 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7589 cleared. Thus we need to shift MASK to the right before checking if it
7590 is a valid mask value. MODE is the mode of the operation. If true
7591 return the length of the mask, otherwise return -1. */
7594 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7596 HOST_WIDE_INT shval
;
7598 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7599 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7602 /* Return true if -msplit-addresses is selected and should be honored.
7604 -msplit-addresses is a half-way house between explicit relocations
7605 and the traditional assembler macros. It can split absolute 32-bit
7606 symbolic constants into a high/lo_sum pair but uses macros for other
7609 Like explicit relocation support for REL targets, it relies
7610 on GNU extensions in the assembler and the linker.
7612 Although this code should work for -O0, it has traditionally
7613 been treated as an optimization. */
7616 mips_split_addresses_p (void)
7618 return (TARGET_SPLIT_ADDRESSES
7622 && !ABI_HAS_64BIT_SYMBOLS
);
7625 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7628 mips_init_relocs (void)
7630 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7631 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7632 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
7633 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7634 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7636 if (TARGET_MIPS16_PCREL_LOADS
)
7637 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
7640 if (ABI_HAS_64BIT_SYMBOLS
)
7642 if (TARGET_EXPLICIT_RELOCS
)
7644 mips_split_p
[SYMBOL_64_HIGH
] = true;
7645 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7646 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7648 mips_split_p
[SYMBOL_64_MID
] = true;
7649 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7650 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7652 mips_split_p
[SYMBOL_64_LOW
] = true;
7653 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7654 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7656 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7657 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7662 if (TARGET_EXPLICIT_RELOCS
7663 || mips_split_addresses_p ()
7666 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7667 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7668 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7675 /* The high part is provided by a pseudo copy of $gp. */
7676 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7677 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7679 else if (TARGET_EXPLICIT_RELOCS
)
7680 /* Small data constants are kept whole until after reload,
7681 then lowered by mips_rewrite_small_data. */
7682 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7684 if (TARGET_EXPLICIT_RELOCS
)
7686 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7689 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7690 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7694 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7695 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7698 /* Expose the use of $28 as soon as possible. */
7699 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7703 /* The HIGH and LO_SUM are matched by special .md patterns. */
7704 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7706 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7707 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7708 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7710 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7711 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7712 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7717 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7719 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7720 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7722 /* Expose the use of $28 as soon as possible. */
7723 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7729 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7730 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7731 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7734 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7735 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7737 if (TARGET_MIPS16_PCREL_LOADS
)
7739 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
7740 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
7744 mips_split_p
[SYMBOL_DTPREL
] = true;
7745 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7746 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7748 mips_split_p
[SYMBOL_TPREL
] = true;
7749 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7750 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7753 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7754 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7757 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7758 in context CONTEXT. RELOCS is the array of relocations to use. */
7761 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7762 const char **relocs
)
7764 enum mips_symbol_type symbol_type
;
7767 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7768 gcc_assert (relocs
[symbol_type
]);
7770 fputs (relocs
[symbol_type
], file
);
7771 output_addr_const (file
, mips_strip_unspec_address (op
));
7772 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7777 /* Start a new block with the given asm switch enabled. If we need
7778 to print a directive, emit PREFIX before it and SUFFIX after it. */
7781 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7782 const char *prefix
, const char *suffix
)
7784 if (asm_switch
->nesting_level
== 0)
7785 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7786 asm_switch
->nesting_level
++;
7789 /* Likewise, but end a block. */
7792 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7793 const char *prefix
, const char *suffix
)
7795 gcc_assert (asm_switch
->nesting_level
);
7796 asm_switch
->nesting_level
--;
7797 if (asm_switch
->nesting_level
== 0)
7798 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7801 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7802 that either print a complete line or print nothing. */
7805 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7807 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7811 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7813 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7816 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7817 The punctuation characters are:
7819 '(' Start a nested ".set noreorder" block.
7820 ')' End a nested ".set noreorder" block.
7821 '[' Start a nested ".set noat" block.
7822 ']' End a nested ".set noat" block.
7823 '<' Start a nested ".set nomacro" block.
7824 '>' End a nested ".set nomacro" block.
7825 '*' Behave like %(%< if generating a delayed-branch sequence.
7826 '#' Print a nop if in a ".set noreorder" block.
7827 '/' Like '#', but do nothing within a delayed-branch sequence.
7828 '?' Print "l" if mips_branch_likely is true
7829 '~' Print a nop if mips_branch_likely is true
7830 '.' Print the name of the register with a hard-wired zero (zero or $0).
7831 '@' Print the name of the assembler temporary register (at or $1).
7832 '^' Print the name of the pic call-through register (t9 or $25).
7833 '+' Print the name of the gp register (usually gp or $28).
7834 '$' Print the name of the stack pointer register (sp or $29).
7836 See also mips_init_print_operand_pucnt. */
7839 mips_print_operand_punctuation (FILE *file
, int ch
)
7844 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7848 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7852 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7856 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7860 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7864 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7868 if (final_sequence
!= 0)
7870 mips_print_operand_punctuation (file
, '(');
7871 mips_print_operand_punctuation (file
, '<');
7876 if (mips_noreorder
.nesting_level
> 0)
7877 fputs ("\n\tnop", file
);
7881 /* Print an extra newline so that the delayed insn is separated
7882 from the following ones. This looks neater and is consistent
7883 with non-nop delayed sequences. */
7884 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7885 fputs ("\n\tnop\n", file
);
7889 if (mips_branch_likely
)
7894 if (mips_branch_likely
)
7895 fputs ("\n\tnop", file
);
7899 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7903 fputs (reg_names
[AT_REGNUM
], file
);
7907 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7911 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7915 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7924 /* Initialize mips_print_operand_punct. */
7927 mips_init_print_operand_punct (void)
7931 for (p
= "()[]<>*#/?~.@^+$"; *p
; p
++)
7932 mips_print_operand_punct
[(unsigned char) *p
] = true;
7935 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7936 associated with condition CODE. Print the condition part of the
7940 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7954 /* Conveniently, the MIPS names for these conditions are the same
7955 as their RTL equivalents. */
7956 fputs (GET_RTX_NAME (code
), file
);
7960 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7965 /* Likewise floating-point branches. */
7968 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7973 fputs ("c1f", file
);
7977 fputs ("c1t", file
);
7981 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7986 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7989 mips_print_operand_punct_valid_p (unsigned char code
)
7991 return mips_print_operand_punct
[code
];
7994 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7996 'X' Print CONST_INT OP in hexadecimal format.
7997 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7998 'd' Print CONST_INT OP in decimal.
7999 'm' Print one less than CONST_INT OP in decimal.
8000 'h' Print the high-part relocation associated with OP, after stripping
8002 'R' Print the low-part relocation associated with OP.
8003 'C' Print the integer branch condition for comparison OP.
8004 'N' Print the inverse of the integer branch condition for comparison OP.
8005 'F' Print the FPU branch condition for comparison OP.
8006 'W' Print the inverse of the FPU branch condition for comparison OP.
8007 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8008 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8009 't' Like 'T', but with the EQ/NE cases reversed
8010 'Y' Print mips_fp_conditions[INTVAL (OP)]
8011 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8012 'q' Print a DSP accumulator register.
8013 'D' Print the second part of a double-word register or memory operand.
8014 'L' Print the low-order register in a double-word register operand.
8015 'M' Print high-order register in a double-word register operand.
8016 'z' Print $0 if OP is zero, otherwise print OP normally.
8017 'b' Print the address of a memory operand, without offset. */
8020 mips_print_operand (FILE *file
, rtx op
, int letter
)
8024 if (mips_print_operand_punct_valid_p (letter
))
8026 mips_print_operand_punctuation (file
, letter
);
8031 code
= GET_CODE (op
);
8036 if (CONST_INT_P (op
))
8037 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8039 output_operand_lossage ("invalid use of '%%%c'", letter
);
8043 if (CONST_INT_P (op
))
8044 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8046 output_operand_lossage ("invalid use of '%%%c'", letter
);
8050 if (CONST_INT_P (op
))
8051 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8053 output_operand_lossage ("invalid use of '%%%c'", letter
);
8057 if (CONST_INT_P (op
))
8058 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
8060 output_operand_lossage ("invalid use of '%%%c'", letter
);
8066 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
8070 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
8074 mips_print_int_branch_condition (file
, code
, letter
);
8078 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
8082 mips_print_float_branch_condition (file
, code
, letter
);
8086 mips_print_float_branch_condition (file
, reverse_condition (code
),
8093 int truth
= (code
== NE
) == (letter
== 'T');
8094 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
8099 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
8100 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
8102 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8109 mips_print_operand (file
, op
, 0);
8115 if (code
== REG
&& MD_REG_P (REGNO (op
)))
8116 fprintf (file
, "$ac0");
8117 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
8118 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
8120 output_operand_lossage ("invalid use of '%%%c'", letter
);
8128 unsigned int regno
= REGNO (op
);
8129 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
8130 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
8133 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
8134 output_operand_lossage ("invalid use of '%%%c'", letter
);
8135 /* We need to print $0 .. $31 for COP0 registers. */
8136 if (COP0_REG_P (regno
))
8137 fprintf (file
, "$%s", ®_names
[regno
][4]);
8139 fprintf (file
, "%s", reg_names
[regno
]);
8145 output_address (plus_constant (Pmode
, XEXP (op
, 0), 4));
8146 else if (letter
== 'b')
8148 gcc_assert (REG_P (XEXP (op
, 0)));
8149 mips_print_operand (file
, XEXP (op
, 0), 0);
8151 else if (letter
&& letter
!= 'z')
8152 output_operand_lossage ("invalid use of '%%%c'", letter
);
8154 output_address (XEXP (op
, 0));
8158 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
8159 fputs (reg_names
[GP_REG_FIRST
], file
);
8160 else if (letter
&& letter
!= 'z')
8161 output_operand_lossage ("invalid use of '%%%c'", letter
);
8162 else if (CONST_GP_P (op
))
8163 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
8165 output_addr_const (file
, mips_strip_unspec_address (op
));
8171 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8174 mips_print_operand_address (FILE *file
, rtx x
)
8176 struct mips_address_info addr
;
8178 if (mips_classify_address (&addr
, x
, word_mode
, true))
8182 mips_print_operand (file
, addr
.offset
, 0);
8183 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8186 case ADDRESS_LO_SUM
:
8187 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
8189 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
8192 case ADDRESS_CONST_INT
:
8193 output_addr_const (file
, x
);
8194 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
8197 case ADDRESS_SYMBOLIC
:
8198 output_addr_const (file
, mips_strip_unspec_address (x
));
8204 /* Implement TARGET_ENCODE_SECTION_INFO. */
8207 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
8209 default_encode_section_info (decl
, rtl
, first
);
8211 if (TREE_CODE (decl
) == FUNCTION_DECL
)
8213 rtx symbol
= XEXP (rtl
, 0);
8214 tree type
= TREE_TYPE (decl
);
8216 /* Encode whether the symbol is short or long. */
8217 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
8218 || mips_far_type_p (type
))
8219 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
8223 /* Implement TARGET_SELECT_RTX_SECTION. */
8226 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
8227 unsigned HOST_WIDE_INT align
)
8229 /* ??? Consider using mergeable small data sections. */
8230 if (mips_rtx_constant_in_small_data_p (mode
))
8231 return get_named_section (NULL
, ".sdata", 0);
8233 return default_elf_select_rtx_section (mode
, x
, align
);
8236 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8238 The complication here is that, with the combination TARGET_ABICALLS
8239 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8240 absolute addresses, and should therefore not be included in the
8241 read-only part of a DSO. Handle such cases by selecting a normal
8242 data section instead of a read-only one. The logic apes that in
8243 default_function_rodata_section. */
8246 mips_function_rodata_section (tree decl
)
8248 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
8249 return default_function_rodata_section (decl
);
8251 if (decl
&& DECL_SECTION_NAME (decl
))
8253 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8254 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
8256 char *rname
= ASTRDUP (name
);
8258 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
8260 else if (flag_function_sections
8261 && flag_data_sections
8262 && strncmp (name
, ".text.", 6) == 0)
8264 char *rname
= ASTRDUP (name
);
8265 memcpy (rname
+ 1, "data", 4);
8266 return get_section (rname
, SECTION_WRITE
, decl
);
8269 return data_section
;
8272 /* Implement TARGET_IN_SMALL_DATA_P. */
8275 mips_in_small_data_p (const_tree decl
)
8277 unsigned HOST_WIDE_INT size
;
8279 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
8282 /* We don't yet generate small-data references for -mabicalls
8283 or VxWorks RTP code. See the related -G handling in
8284 mips_option_override. */
8285 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
8288 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
8292 /* Reject anything that isn't in a known small-data section. */
8293 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
8294 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
8297 /* If a symbol is defined externally, the assembler will use the
8298 usual -G rules when deciding how to implement macros. */
8299 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
8302 else if (TARGET_EMBEDDED_DATA
)
8304 /* Don't put constants into the small data section: we want them
8305 to be in ROM rather than RAM. */
8306 if (TREE_CODE (decl
) != VAR_DECL
)
8309 if (TREE_READONLY (decl
)
8310 && !TREE_SIDE_EFFECTS (decl
)
8311 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
8315 /* Enforce -mlocal-sdata. */
8316 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
8319 /* Enforce -mextern-sdata. */
8320 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
8322 if (DECL_EXTERNAL (decl
))
8324 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
8328 /* We have traditionally not treated zero-sized objects as small data,
8329 so this is now effectively part of the ABI. */
8330 size
= int_size_in_bytes (TREE_TYPE (decl
));
8331 return size
> 0 && size
<= mips_small_data_threshold
;
8334 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8335 anchors for small data: the GP register acts as an anchor in that
8336 case. We also don't want to use them for PC-relative accesses,
8337 where the PC acts as an anchor. */
8340 mips_use_anchors_for_symbol_p (const_rtx symbol
)
8342 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
8344 case SYMBOL_PC_RELATIVE
:
8345 case SYMBOL_GP_RELATIVE
:
8349 return default_use_anchors_for_symbol_p (symbol
);
8353 /* The MIPS debug format wants all automatic variables and arguments
8354 to be in terms of the virtual frame pointer (stack pointer before
8355 any adjustment in the function), while the MIPS 3.0 linker wants
8356 the frame pointer to be the stack pointer after the initial
8357 adjustment. So, we do the adjustment here. The arg pointer (which
8358 is eliminated) points to the virtual frame pointer, while the frame
8359 pointer (which may be eliminated) points to the stack pointer after
8360 the initial adjustments. */
8363 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
8365 rtx offset2
= const0_rtx
;
8366 rtx reg
= eliminate_constant_term (addr
, &offset2
);
8369 offset
= INTVAL (offset2
);
8371 if (reg
== stack_pointer_rtx
8372 || reg
== frame_pointer_rtx
8373 || reg
== hard_frame_pointer_rtx
)
8375 offset
-= cfun
->machine
->frame
.total_size
;
8376 if (reg
== hard_frame_pointer_rtx
)
8377 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8383 /* Implement ASM_OUTPUT_EXTERNAL. */
8386 mips_output_external (FILE *file
, tree decl
, const char *name
)
8388 default_elf_asm_output_external (file
, decl
, name
);
8390 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8391 set in order to avoid putting out names that are never really
8393 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
8395 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
8397 /* When using assembler macros, emit .extern directives for
8398 all small-data externs so that the assembler knows how
8401 In most cases it would be safe (though pointless) to emit
8402 .externs for other symbols too. One exception is when an
8403 object is within the -G limit but declared by the user to
8404 be in a section other than .sbss or .sdata. */
8405 fputs ("\t.extern\t", file
);
8406 assemble_name (file
, name
);
8407 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
8408 int_size_in_bytes (TREE_TYPE (decl
)));
8413 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8416 mips_output_filename (FILE *stream
, const char *name
)
8418 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8420 if (write_symbols
== DWARF2_DEBUG
)
8422 else if (mips_output_filename_first_time
)
8424 mips_output_filename_first_time
= 0;
8425 num_source_filenames
+= 1;
8426 current_function_file
= name
;
8427 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8428 output_quoted_string (stream
, name
);
8429 putc ('\n', stream
);
8431 /* If we are emitting stabs, let dbxout.c handle this (except for
8432 the mips_output_filename_first_time case). */
8433 else if (write_symbols
== DBX_DEBUG
)
8435 else if (name
!= current_function_file
8436 && strcmp (name
, current_function_file
) != 0)
8438 num_source_filenames
+= 1;
8439 current_function_file
= name
;
8440 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
8441 output_quoted_string (stream
, name
);
8442 putc ('\n', stream
);
8446 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8448 static void ATTRIBUTE_UNUSED
8449 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8454 fputs ("\t.dtprelword\t", file
);
8458 fputs ("\t.dtpreldword\t", file
);
8464 output_addr_const (file
, x
);
8465 fputs ("+0x8000", file
);
8468 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8471 mips_dwarf_register_span (rtx reg
)
8474 enum machine_mode mode
;
8476 /* By default, GCC maps increasing register numbers to increasing
8477 memory locations, but paired FPRs are always little-endian,
8478 regardless of the prevailing endianness. */
8479 mode
= GET_MODE (reg
);
8480 if (FP_REG_P (REGNO (reg
))
8481 && TARGET_BIG_ENDIAN
8482 && MAX_FPRS_PER_FMT
> 1
8483 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
8485 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
8486 high
= mips_subword (reg
, true);
8487 low
= mips_subword (reg
, false);
8488 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
8494 /* DSP ALU can bypass data with no delays for the following pairs. */
8495 enum insn_code dspalu_bypass_table
[][2] =
8497 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
8498 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
8499 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
8500 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
8501 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
8502 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
8503 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
8504 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
8508 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
8511 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
8512 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
8513 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
8515 for (i
= 0; i
< num_bypass
; i
++)
8517 if (out_icode
== dspalu_bypass_table
[i
][0]
8518 && in_icode
== dspalu_bypass_table
[i
][1])
8524 /* Implement ASM_OUTPUT_ASCII. */
8527 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8533 fprintf (stream
, "\t.ascii\t\"");
8534 for (i
= 0; i
< len
; i
++)
8538 c
= (unsigned char) string
[i
];
8541 if (c
== '\\' || c
== '\"')
8543 putc ('\\', stream
);
8551 fprintf (stream
, "\\%03o", c
);
8555 if (cur_pos
> 72 && i
+1 < len
)
8558 fprintf (stream
, "\"\n\t.ascii\t\"");
8561 fprintf (stream
, "\"\n");
8564 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8565 Update *ADDR with the operand that should be printed. */
8568 mips_output_tls_reloc_directive (rtx
*addr
)
8570 enum mips_symbol_type type
;
8572 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
8573 *addr
= mips_strip_unspec_address (*addr
);
8577 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
8580 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
8587 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8588 macros, mark the symbol as written so that mips_asm_output_external
8589 won't emit an .extern for it. STREAM is the output file, NAME is the
8590 name of the symbol, INIT_STRING is the string that should be written
8591 before the symbol and FINAL_STRING is the string that should be
8592 written after it. FINAL_STRING is a printf format that consumes the
8593 remaining arguments. */
8596 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8597 const char *final_string
, ...)
8601 fputs (init_string
, stream
);
8602 assemble_name (stream
, name
);
8603 va_start (ap
, final_string
);
8604 vfprintf (stream
, final_string
, ap
);
8607 if (!TARGET_EXPLICIT_RELOCS
)
8609 tree name_tree
= get_identifier (name
);
8610 TREE_ASM_WRITTEN (name_tree
) = 1;
8614 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8615 NAME is the name of the object and ALIGN is the required alignment
8616 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8617 alignment argument. */
8620 mips_declare_common_object (FILE *stream
, const char *name
,
8621 const char *init_string
,
8622 unsigned HOST_WIDE_INT size
,
8623 unsigned int align
, bool takes_alignment_p
)
8625 if (!takes_alignment_p
)
8627 size
+= (align
/ BITS_PER_UNIT
) - 1;
8628 size
-= size
% (align
/ BITS_PER_UNIT
);
8629 mips_declare_object (stream
, name
, init_string
,
8630 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8633 mips_declare_object (stream
, name
, init_string
,
8634 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8635 size
, align
/ BITS_PER_UNIT
);
8638 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8639 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8642 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8643 unsigned HOST_WIDE_INT size
,
8646 /* If the target wants uninitialized const declarations in
8647 .rdata then don't put them in .comm. */
8648 if (TARGET_EMBEDDED_DATA
8649 && TARGET_UNINIT_CONST_IN_RODATA
8650 && TREE_CODE (decl
) == VAR_DECL
8651 && TREE_READONLY (decl
)
8652 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8654 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8655 targetm
.asm_out
.globalize_label (stream
, name
);
8657 switch_to_section (readonly_data_section
);
8658 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8659 mips_declare_object (stream
, name
, "",
8660 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8664 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8668 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8669 extern int size_directive_output
;
8671 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8672 definitions except that it uses mips_declare_object to emit the label. */
8675 mips_declare_object_name (FILE *stream
, const char *name
,
8676 tree decl ATTRIBUTE_UNUSED
)
8678 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8679 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8682 size_directive_output
= 0;
8683 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8687 size_directive_output
= 1;
8688 size
= int_size_in_bytes (TREE_TYPE (decl
));
8689 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8692 mips_declare_object (stream
, name
, "", ":\n");
8695 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8698 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8702 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8703 if (!flag_inhibit_size_directive
8704 && DECL_SIZE (decl
) != 0
8707 && DECL_INITIAL (decl
) == error_mark_node
8708 && !size_directive_output
)
8712 size_directive_output
= 1;
8713 size
= int_size_in_bytes (TREE_TYPE (decl
));
8714 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8719 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8720 with the current ABI. */
8723 mips_mdebug_abi_name (void)
8736 return TARGET_64BIT
? "eabi64" : "eabi32";
8742 /* Implement TARGET_ASM_FILE_START. */
8745 mips_file_start (void)
8747 default_file_start ();
8749 /* Generate a special section to describe the ABI switches used to
8750 produce the resultant binary. */
8752 /* Record the ABI itself. Modern versions of binutils encode
8753 this information in the ELF header flags, but GDB needs the
8754 information in order to correctly debug binaries produced by
8755 older binutils. See the function mips_gdbarch_init in
8757 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8758 mips_mdebug_abi_name ());
8760 /* There is no ELF header flag to distinguish long32 forms of the
8761 EABI from long64 forms. Emit a special section to help tools
8762 such as GDB. Do the same for o64, which is sometimes used with
8764 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8765 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8766 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8768 #ifdef HAVE_AS_GNU_ATTRIBUTE
8772 /* No floating-point operations, -mno-float. */
8773 if (TARGET_NO_FLOAT
)
8775 /* Soft-float code, -msoft-float. */
8776 else if (!TARGET_HARD_FLOAT_ABI
)
8778 /* Single-float code, -msingle-float. */
8779 else if (!TARGET_DOUBLE_FLOAT
)
8781 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8782 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8784 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8788 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8792 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8793 if (TARGET_ABICALLS
)
8795 fprintf (asm_out_file
, "\t.abicalls\n");
8796 if (TARGET_ABICALLS_PIC0
)
8797 fprintf (asm_out_file
, "\t.option\tpic0\n");
8800 if (flag_verbose_asm
)
8801 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8803 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8806 /* Implement TARGET_ASM_CODE_END. */
8809 mips_code_end (void)
8811 if (mips_need_mips16_rdhwr_p
)
8812 mips_output_mips16_rdhwr ();
8815 /* Make the last instruction frame-related and note that it performs
8816 the operation described by FRAME_PATTERN. */
8819 mips_set_frame_expr (rtx frame_pattern
)
8823 insn
= get_last_insn ();
8824 RTX_FRAME_RELATED_P (insn
) = 1;
8825 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8830 /* Return a frame-related rtx that stores REG at MEM.
8831 REG must be a single register. */
8834 mips_frame_set (rtx mem
, rtx reg
)
8838 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8839 RTX_FRAME_RELATED_P (set
) = 1;
8844 /* Record that the epilogue has restored call-saved register REG. */
8847 mips_add_cfa_restore (rtx reg
)
8849 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
8850 mips_epilogue
.cfa_restores
);
8853 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8854 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8855 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8856 static const unsigned char mips16e_s2_s8_regs
[] = {
8857 30, 23, 22, 21, 20, 19, 18
8859 static const unsigned char mips16e_a0_a3_regs
[] = {
8863 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8864 ordered from the uppermost in memory to the lowest in memory. */
8865 static const unsigned char mips16e_save_restore_regs
[] = {
8866 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8869 /* Return the index of the lowest X in the range [0, SIZE) for which
8870 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8873 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8878 for (i
= 0; i
< size
; i
++)
8879 if (BITSET_P (mask
, regs
[i
]))
8885 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8886 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8887 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8888 is true for all indexes (X, SIZE). */
8891 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8892 unsigned int size
, unsigned int *num_regs_ptr
)
8896 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8897 for (i
++; i
< size
; i
++)
8898 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8901 *mask_ptr
|= 1 << regs
[i
];
8905 /* Return a simplified form of X using the register values in REG_VALUES.
8906 REG_VALUES[R] is the last value assigned to hard register R, or null
8907 if R has not been modified.
8909 This function is rather limited, but is good enough for our purposes. */
8912 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8914 x
= avoid_constant_pool_reference (x
);
8918 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8919 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
8920 x0
, GET_MODE (XEXP (x
, 0)));
8923 if (ARITHMETIC_P (x
))
8925 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8926 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
8927 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
8931 && reg_values
[REGNO (x
)]
8932 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
8933 return reg_values
[REGNO (x
)];
8938 /* Return true if (set DEST SRC) stores an argument register into its
8939 caller-allocated save slot, storing the number of that argument
8940 register in *REGNO_PTR if so. REG_VALUES is as for
8941 mips16e_collect_propagate_value. */
8944 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
8945 unsigned int *regno_ptr
)
8947 unsigned int argno
, regno
;
8948 HOST_WIDE_INT offset
, required_offset
;
8951 /* Check that this is a word-mode store. */
8952 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
8955 /* Check that the register being saved is an unmodified argument
8957 regno
= REGNO (src
);
8958 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
8960 argno
= regno
- GP_ARG_FIRST
;
8962 /* Check whether the address is an appropriate stack-pointer or
8963 frame-pointer access. */
8964 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
8965 mips_split_plus (addr
, &base
, &offset
);
8966 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
8967 if (base
== hard_frame_pointer_rtx
)
8968 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8969 else if (base
!= stack_pointer_rtx
)
8971 if (offset
!= required_offset
)
8978 /* A subroutine of mips_expand_prologue, called only when generating
8979 MIPS16e SAVE instructions. Search the start of the function for any
8980 instructions that save argument registers into their caller-allocated
8981 save slots. Delete such instructions and return a value N such that
8982 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8983 instructions redundant. */
8986 mips16e_collect_argument_saves (void)
8988 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
8989 rtx insn
, next
, set
, dest
, src
;
8990 unsigned int nargs
, regno
;
8992 push_topmost_sequence ();
8994 memset (reg_values
, 0, sizeof (reg_values
));
8995 for (insn
= get_insns (); insn
; insn
= next
)
8997 next
= NEXT_INSN (insn
);
8998 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
9004 set
= PATTERN (insn
);
9005 if (GET_CODE (set
) != SET
)
9008 dest
= SET_DEST (set
);
9009 src
= SET_SRC (set
);
9010 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
9012 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
9015 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
9018 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
9019 reg_values
[REGNO (dest
)]
9020 = mips16e_collect_propagate_value (src
, reg_values
);
9024 pop_topmost_sequence ();
9029 /* Return a move between register REGNO and memory location SP + OFFSET.
9030 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9031 Make the move a load if RESTORE_P, otherwise make it a store. */
9034 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
9035 HOST_WIDE_INT offset
, unsigned int regno
)
9039 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
9041 reg
= gen_rtx_REG (SImode
, regno
);
9044 mips_add_cfa_restore (reg
);
9045 return gen_rtx_SET (VOIDmode
, reg
, mem
);
9048 return gen_rtx_SET (VOIDmode
, mem
, reg
);
9049 return mips_frame_set (mem
, reg
);
9052 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9053 The instruction must:
9055 - Allocate or deallocate SIZE bytes in total; SIZE is known
9058 - Save or restore as many registers in *MASK_PTR as possible.
9059 The instruction saves the first registers at the top of the
9060 allocated area, with the other registers below it.
9062 - Save NARGS argument registers above the allocated area.
9064 (NARGS is always zero if RESTORE_P.)
9066 The SAVE and RESTORE instructions cannot save and restore all general
9067 registers, so there may be some registers left over for the caller to
9068 handle. Destructively modify *MASK_PTR so that it contains the registers
9069 that still need to be saved or restored. The caller can save these
9070 registers in the memory immediately below *OFFSET_PTR, which is a
9071 byte offset from the bottom of the allocated stack area. */
9074 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
9075 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
9079 HOST_WIDE_INT offset
, top_offset
;
9080 unsigned int i
, regno
;
9083 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
9085 /* Calculate the number of elements in the PARALLEL. We need one element
9086 for the stack adjustment, one for each argument register save, and one
9087 for each additional register move. */
9089 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9090 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
9093 /* Create the final PARALLEL. */
9094 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
9097 /* Add the stack pointer adjustment. */
9098 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
9099 plus_constant (Pmode
, stack_pointer_rtx
,
9100 restore_p
? size
: -size
));
9101 RTX_FRAME_RELATED_P (set
) = 1;
9102 XVECEXP (pattern
, 0, n
++) = set
;
9104 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9105 top_offset
= restore_p
? size
: 0;
9107 /* Save the arguments. */
9108 for (i
= 0; i
< nargs
; i
++)
9110 offset
= top_offset
+ i
* UNITS_PER_WORD
;
9111 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
9113 XVECEXP (pattern
, 0, n
++) = set
;
9116 /* Then fill in the other register moves. */
9117 offset
= top_offset
;
9118 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
9120 regno
= mips16e_save_restore_regs
[i
];
9121 if (BITSET_P (*mask_ptr
, regno
))
9123 offset
-= UNITS_PER_WORD
;
9124 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
9125 XVECEXP (pattern
, 0, n
++) = set
;
9126 *mask_ptr
&= ~(1 << regno
);
9130 /* Tell the caller what offset it should use for the remaining registers. */
9131 *offset_ptr
= size
+ (offset
- top_offset
);
9133 gcc_assert (n
== XVECLEN (pattern
, 0));
9138 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9139 pointer. Return true if PATTERN matches the kind of instruction
9140 generated by mips16e_build_save_restore. If INFO is nonnull,
9141 initialize it when returning true. */
9144 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
9145 struct mips16e_save_restore_info
*info
)
9147 unsigned int i
, nargs
, mask
, extra
;
9148 HOST_WIDE_INT top_offset
, save_offset
, offset
;
9149 rtx set
, reg
, mem
, base
;
9152 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
9155 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9156 top_offset
= adjust
> 0 ? adjust
: 0;
9158 /* Interpret all other members of the PARALLEL. */
9159 save_offset
= top_offset
- UNITS_PER_WORD
;
9163 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
9165 /* Check that we have a SET. */
9166 set
= XVECEXP (pattern
, 0, n
);
9167 if (GET_CODE (set
) != SET
)
9170 /* Check that the SET is a load (if restoring) or a store
9172 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
9176 /* Check that the address is the sum of the stack pointer and a
9177 possibly-zero constant offset. */
9178 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
9179 if (base
!= stack_pointer_rtx
)
9182 /* Check that SET's other operand is a register. */
9183 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
9187 /* Check for argument saves. */
9188 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
9189 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
9191 else if (offset
== save_offset
)
9193 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
9194 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
9197 mask
|= 1 << REGNO (reg
);
9198 save_offset
-= UNITS_PER_WORD
;
9204 /* Check that the restrictions on register ranges are met. */
9206 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
9207 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
9208 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
9209 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
9213 /* Make sure that the topmost argument register is not saved twice.
9214 The checks above ensure that the same is then true for the other
9215 argument registers. */
9216 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
9219 /* Pass back information, if requested. */
9222 info
->nargs
= nargs
;
9224 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
9230 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9231 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9232 the null terminator. */
9235 mips16e_add_register_range (char *s
, unsigned int min_reg
,
9236 unsigned int max_reg
)
9238 if (min_reg
!= max_reg
)
9239 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
9241 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
9245 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9246 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9249 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
9251 static char buffer
[300];
9253 struct mips16e_save_restore_info info
;
9254 unsigned int i
, end
;
9257 /* Parse the pattern. */
9258 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
9261 /* Add the mnemonic. */
9262 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
9265 /* Save the arguments. */
9267 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
9268 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
9269 else if (info
.nargs
== 1)
9270 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
9272 /* Emit the amount of stack space to allocate or deallocate. */
9273 s
+= sprintf (s
, "%d", (int) info
.size
);
9275 /* Save or restore $16. */
9276 if (BITSET_P (info
.mask
, 16))
9277 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
9279 /* Save or restore $17. */
9280 if (BITSET_P (info
.mask
, 17))
9281 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
9283 /* Save or restore registers in the range $s2...$s8, which
9284 mips16e_s2_s8_regs lists in decreasing order. Note that this
9285 is a software register range; the hardware registers are not
9286 numbered consecutively. */
9287 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
9288 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
9290 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
9291 mips16e_s2_s8_regs
[i
]);
9293 /* Save or restore registers in the range $a0...$a3. */
9294 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
9295 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
9297 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
9298 mips16e_a0_a3_regs
[end
- 1]);
9300 /* Save or restore $31. */
9301 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
9302 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
9307 /* Return true if the current function returns its value in a floating-point
9308 register in MIPS16 mode. */
9311 mips16_cfun_returns_in_fpr_p (void)
9313 tree return_type
= DECL_RESULT (current_function_decl
);
9314 return (TARGET_MIPS16
9315 && TARGET_HARD_FLOAT_ABI
9316 && !aggregate_value_p (return_type
, current_function_decl
)
9317 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
9320 /* Return true if predicate PRED is true for at least one instruction.
9321 Cache the result in *CACHE, and assume that the result is true
9322 if *CACHE is already true. */
9325 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
9331 push_topmost_sequence ();
9332 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9333 if (USEFUL_INSN_P (insn
) && pred (insn
))
9338 pop_topmost_sequence ();
9343 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9344 See mips_cfun_has_inflexible_gp_ref_p for details. */
9347 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
9349 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9350 indicate that the target could be a traditional MIPS
9351 lazily-binding stub. */
9352 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
9355 /* Return true if the current function refers to the global pointer
9356 in a way that forces $28 to be valid. This means that we can't
9357 change the choice of global pointer, even for NewABI code.
9359 One example of this (and one which needs several checks) is that
9360 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9361 (This restriction does not apply to PLTs.) */
9364 mips_cfun_has_inflexible_gp_ref_p (void)
9366 /* If the function has a nonlocal goto, $28 must hold the correct
9367 global pointer for the target function. That is, the target
9368 of the goto implicitly uses $28. */
9369 if (crtl
->has_nonlocal_goto
)
9372 if (TARGET_ABICALLS_PIC2
)
9374 /* Symbolic accesses implicitly use the global pointer unless
9375 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9376 might go to traditional MIPS lazy-binding stubs. */
9377 if (!TARGET_EXPLICIT_RELOCS
)
9380 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9381 can be lazily-bound. */
9385 /* MIPS16 functions that return in FPRs need to call an
9386 external libgcc routine. This call is only made explict
9387 during mips_expand_epilogue, and it too might be lazily bound. */
9388 if (mips16_cfun_returns_in_fpr_p ())
9392 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
9393 mips_insn_has_inflexible_gp_ref_p
);
9396 /* Return true if INSN refers to the global pointer in a "flexible" way.
9397 See mips_cfun_has_flexible_gp_ref_p for details. */
9400 mips_insn_has_flexible_gp_ref_p (rtx insn
)
9402 return (get_attr_got (insn
) != GOT_UNSET
9403 || mips_small_data_pattern_p (PATTERN (insn
))
9404 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
9407 /* Return true if the current function references the global pointer,
9408 but if those references do not inherently require the global pointer
9409 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9412 mips_cfun_has_flexible_gp_ref_p (void)
9414 /* Reload can sometimes introduce constant pool references
9415 into a function that otherwise didn't need them. For example,
9416 suppose we have an instruction like:
9418 (set (reg:DF R1) (float:DF (reg:SI R2)))
9420 If R2 turns out to be a constant such as 1, the instruction may
9421 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9422 the option of using this constant if R2 doesn't get allocated
9425 In cases like these, reload will have added the constant to the
9426 pool but no instruction will yet refer to it. */
9427 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
9430 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
9431 mips_insn_has_flexible_gp_ref_p
);
9434 /* Return the register that should be used as the global pointer
9435 within this function. Return INVALID_REGNUM if the function
9436 doesn't need a global pointer. */
9439 mips_global_pointer (void)
9443 /* $gp is always available unless we're using a GOT. */
9444 if (!TARGET_USE_GOT
)
9445 return GLOBAL_POINTER_REGNUM
;
9447 /* If there are inflexible references to $gp, we must use the
9448 standard register. */
9449 if (mips_cfun_has_inflexible_gp_ref_p ())
9450 return GLOBAL_POINTER_REGNUM
;
9452 /* If there are no current references to $gp, then the only uses
9453 we can introduce later are those involved in long branches. */
9454 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
9455 return INVALID_REGNUM
;
9457 /* If the global pointer is call-saved, try to use a call-clobbered
9459 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
9460 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9461 if (!df_regs_ever_live_p (regno
)
9462 && call_really_used_regs
[regno
]
9463 && !fixed_regs
[regno
]
9464 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
9467 return GLOBAL_POINTER_REGNUM
;
9470 /* Return true if the current function's prologue must load the global
9471 pointer value into pic_offset_table_rtx and store the same value in
9472 the function's cprestore slot (if any).
9474 One problem we have to deal with is that, when emitting GOT-based
9475 position independent code, long-branch sequences will need to load
9476 the address of the branch target from the GOT. We don't know until
9477 the very end of compilation whether (and where) the function needs
9478 long branches, so we must ensure that _any_ branch can access the
9479 global pointer in some form. However, we do not want to pessimize
9480 the usual case in which all branches are short.
9482 We handle this as follows:
9484 (1) During reload, we set cfun->machine->global_pointer to
9485 INVALID_REGNUM if we _know_ that the current function
9486 doesn't need a global pointer. This is only valid if
9487 long branches don't need the GOT.
9489 Otherwise, we assume that we might need a global pointer
9490 and pick an appropriate register.
9492 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9493 we ensure that the global pointer is available at every
9494 block boundary bar entry and exit. We do this in one of two ways:
9496 - If the function has a cprestore slot, we ensure that this
9497 slot is valid at every branch. However, as explained in
9498 point (6) below, there is no guarantee that pic_offset_table_rtx
9499 itself is valid if new uses of the global pointer are introduced
9500 after the first post-epilogue split.
9502 We guarantee that the cprestore slot is valid by loading it
9503 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9504 this register live at every block boundary bar function entry
9505 and exit. It is then invalid to move the load (and thus the
9506 preceding store) across a block boundary.
9508 - If the function has no cprestore slot, we guarantee that
9509 pic_offset_table_rtx itself is valid at every branch.
9511 See mips_eh_uses for the handling of the register liveness.
9513 (3) During prologue and epilogue generation, we emit "ghost"
9514 placeholder instructions to manipulate the global pointer.
9516 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9517 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9518 that the function needs a global pointer. (There is no need to set
9519 them earlier than this, and doing it as late as possible leads to
9520 fewer false positives.)
9522 (5) If cfun->machine->must_initialize_gp_p is true during a
9523 split_insns pass, we split the ghost instructions into real
9524 instructions. These split instructions can then be optimized in
9525 the usual way. Otherwise, we keep the ghost instructions intact,
9526 and optimize for the case where they aren't needed. We still
9527 have the option of splitting them later, if we need to introduce
9528 new uses of the global pointer.
9530 For example, the scheduler ignores a ghost instruction that
9531 stores $28 to the stack, but it handles the split form of
9532 the ghost instruction as an ordinary store.
9534 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9535 is true during the first post-epilogue split_insns pass, we split
9536 calls and restore_gp patterns into instructions that explicitly
9537 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9538 we split these patterns into instructions that _don't_ load from
9541 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9542 time of the split, then any instructions that exist at that time
9543 can make free use of pic_offset_table_rtx. However, if we want
9544 to introduce new uses of the global pointer after the split,
9545 we must explicitly load the value from the cprestore slot, since
9546 pic_offset_table_rtx itself might not be valid at a given point
9549 The idea is that we want to be able to delete redundant
9550 loads from the cprestore slot in the usual case where no
9551 long branches are needed.
9553 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9554 of md_reorg, we decide whether the global pointer is needed for
9555 long branches. If so, we set cfun->machine->must_initialize_gp_p
9556 to true and split the ghost instructions into real instructions
9559 Note that the ghost instructions must have a zero length for three reasons:
9561 - Giving the length of the underlying $gp sequence might cause
9562 us to use long branches in cases where they aren't really needed.
9564 - They would perturb things like alignment calculations.
9566 - More importantly, the hazard detection in md_reorg relies on
9567 empty instructions having a zero length.
9569 If we find a long branch and split the ghost instructions at the
9570 end of md_reorg, the split could introduce more long branches.
9571 That isn't a problem though, because we still do the split before
9572 the final shorten_branches pass.
9574 This is extremely ugly, but it seems like the best compromise between
9575 correctness and efficiency. */
9578 mips_must_initialize_gp_p (void)
9580 return cfun
->machine
->must_initialize_gp_p
;
9583 /* Return true if REGNO is a register that is ordinarily call-clobbered
9584 but must nevertheless be preserved by an interrupt handler. */
9587 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9589 if (MD_REG_P (regno
))
9592 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9595 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9597 /* $0 is hard-wired. */
9598 if (regno
== GP_REG_FIRST
)
9601 /* The interrupt handler can treat kernel registers as
9602 scratch registers. */
9603 if (KERNEL_REG_P (regno
))
9606 /* The function will return the stack pointer to its original value
9608 if (regno
== STACK_POINTER_REGNUM
)
9611 /* Otherwise, return true for registers that aren't ordinarily
9613 return call_really_used_regs
[regno
];
9619 /* Return true if the current function should treat register REGNO
9623 mips_cfun_call_saved_reg_p (unsigned int regno
)
9625 /* If the user makes an ordinarily-call-saved register global,
9626 that register is no longer call-saved. */
9627 if (global_regs
[regno
])
9630 /* Interrupt handlers need to save extra registers. */
9631 if (cfun
->machine
->interrupt_handler_p
9632 && mips_interrupt_extra_call_saved_reg_p (regno
))
9635 /* call_insns preserve $28 unless they explicitly say otherwise,
9636 so call_really_used_regs[] treats $28 as call-saved. However,
9637 we want the ABI property rather than the default call_insn
9639 return (regno
== GLOBAL_POINTER_REGNUM
9640 ? TARGET_CALL_SAVED_GP
9641 : !call_really_used_regs
[regno
]);
9644 /* Return true if the function body might clobber register REGNO.
9645 We know that REGNO is call-saved. */
9648 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9650 /* Some functions should be treated as clobbering all call-saved
9652 if (crtl
->saves_all_registers
)
9655 /* DF handles cases where a register is explicitly referenced in
9656 the rtl. Incoming values are passed in call-clobbered registers,
9657 so we can assume that any live call-saved register is set within
9659 if (df_regs_ever_live_p (regno
))
9662 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9663 These clobbers are not explicit in the rtl. */
9664 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9667 /* If we're using a call-saved global pointer, the function's
9668 prologue will need to set it up. */
9669 if (cfun
->machine
->global_pointer
== regno
)
9672 /* The function's prologue will need to set the frame pointer if
9673 frame_pointer_needed. */
9674 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9677 /* If a MIPS16 function returns a value in FPRs, its epilogue
9678 will need to call an external libgcc routine. This yet-to-be
9679 generated call_insn will clobber $31. */
9680 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9683 /* If REGNO is ordinarily call-clobbered, we must assume that any
9684 called function could modify it. */
9685 if (cfun
->machine
->interrupt_handler_p
9687 && mips_interrupt_extra_call_saved_reg_p (regno
))
9693 /* Return true if the current function must save register REGNO. */
9696 mips_save_reg_p (unsigned int regno
)
9698 if (mips_cfun_call_saved_reg_p (regno
))
9700 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9703 /* Save both registers in an FPR pair if either one is used. This is
9704 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9705 register to be used without the even register. */
9706 if (FP_REG_P (regno
)
9707 && MAX_FPRS_PER_FMT
== 2
9708 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9712 /* We need to save the incoming return address if __builtin_eh_return
9713 is being used to set a different return address. */
9714 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9720 /* Populate the current function's mips_frame_info structure.
9722 MIPS stack frames look like:
9724 +-------------------------------+
9726 | incoming stack arguments |
9728 +-------------------------------+
9730 | caller-allocated save area |
9731 A | for register arguments |
9733 +-------------------------------+ <-- incoming stack pointer
9735 | callee-allocated save area |
9736 B | for arguments that are |
9737 | split between registers and |
9740 +-------------------------------+ <-- arg_pointer_rtx
9742 C | callee-allocated save area |
9743 | for register varargs |
9745 +-------------------------------+ <-- frame_pointer_rtx
9746 | | + cop0_sp_offset
9747 | COP0 reg save area | + UNITS_PER_WORD
9749 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9750 | | + UNITS_PER_WORD
9751 | accumulator save area |
9753 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9754 | | + UNITS_PER_HWFPVALUE
9757 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9758 | | + UNITS_PER_WORD
9761 +-------------------------------+ <-- frame_pointer_rtx with
9762 | | \ -fstack-protector
9763 | local variables | | var_size
9765 +-------------------------------+
9767 | $gp save area | | cprestore_size
9769 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9771 | outgoing stack arguments | |
9773 +-------------------------------+ | args_size
9775 | caller-allocated save area | |
9776 | for register arguments | |
9778 +-------------------------------+ <-- stack_pointer_rtx
9779 frame_pointer_rtx without
9781 hard_frame_pointer_rtx for
9784 At least two of A, B and C will be empty.
9786 Dynamic stack allocations such as alloca insert data at point P.
9787 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9788 hard_frame_pointer_rtx unchanged. */
9791 mips_compute_frame_info (void)
9793 struct mips_frame_info
*frame
;
9794 HOST_WIDE_INT offset
, size
;
9795 unsigned int regno
, i
;
9797 /* Set this function's interrupt properties. */
9798 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9801 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9802 else if (TARGET_HARD_FLOAT
)
9803 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9804 else if (TARGET_MIPS16
)
9805 error ("interrupt handlers cannot be MIPS16 functions");
9808 cfun
->machine
->interrupt_handler_p
= true;
9809 cfun
->machine
->use_shadow_register_set_p
=
9810 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9811 cfun
->machine
->keep_interrupts_masked_p
=
9812 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9813 cfun
->machine
->use_debug_exception_return_p
=
9814 mips_use_debug_exception_return_p (TREE_TYPE
9815 (current_function_decl
));
9819 frame
= &cfun
->machine
->frame
;
9820 memset (frame
, 0, sizeof (*frame
));
9821 size
= get_frame_size ();
9823 cfun
->machine
->global_pointer
= mips_global_pointer ();
9825 /* The first two blocks contain the outgoing argument area and the $gp save
9826 slot. This area isn't needed in leaf functions, but if the
9827 target-independent frame size is nonzero, we have already committed to
9828 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9829 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && crtl
->is_leaf
)
9831 /* The MIPS 3.0 linker does not like functions that dynamically
9832 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9833 looks like we are trying to create a second frame pointer to the
9834 function, so allocate some stack space to make it happy. */
9835 if (cfun
->calls_alloca
)
9836 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9838 frame
->args_size
= 0;
9839 frame
->cprestore_size
= 0;
9843 frame
->args_size
= crtl
->outgoing_args_size
;
9844 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9846 offset
= frame
->args_size
+ frame
->cprestore_size
;
9848 /* Move above the local variables. */
9849 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9850 offset
+= frame
->var_size
;
9852 /* Find out which GPRs we need to save. */
9853 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9854 if (mips_save_reg_p (regno
))
9857 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9860 /* If this function calls eh_return, we must also save and restore the
9861 EH data registers. */
9862 if (crtl
->calls_eh_return
)
9863 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9866 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9869 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9870 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9871 save all later registers too. */
9872 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9874 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9875 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9876 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9877 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9880 /* Move above the GPR save area. */
9881 if (frame
->num_gp
> 0)
9883 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9884 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9887 /* Find out which FPRs we need to save. This loop must iterate over
9888 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9889 if (TARGET_HARD_FLOAT
)
9890 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9891 if (mips_save_reg_p (regno
))
9893 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9894 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9897 /* Move above the FPR save area. */
9898 if (frame
->num_fp
> 0)
9900 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9901 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9904 /* Add in space for the interrupt context information. */
9905 if (cfun
->machine
->interrupt_handler_p
)
9908 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9911 frame
->acc_mask
|= (1 << 0);
9914 /* Check accumulators 1, 2, 3. */
9915 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
9916 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
9919 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
9922 /* All interrupt context functions need space to preserve STATUS. */
9923 frame
->num_cop0_regs
++;
9925 /* If we don't keep interrupts masked, we need to save EPC. */
9926 if (!cfun
->machine
->keep_interrupts_masked_p
)
9927 frame
->num_cop0_regs
++;
9930 /* Move above the accumulator save area. */
9931 if (frame
->num_acc
> 0)
9933 /* Each accumulator needs 2 words. */
9934 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
9935 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
9938 /* Move above the COP0 register save area. */
9939 if (frame
->num_cop0_regs
> 0)
9941 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
9942 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
9945 /* Move above the callee-allocated varargs save area. */
9946 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
9947 frame
->arg_pointer_offset
= offset
;
9949 /* Move above the callee-allocated area for pretend stack arguments. */
9950 offset
+= crtl
->args
.pretend_args_size
;
9951 frame
->total_size
= offset
;
9953 /* Work out the offsets of the save areas from the top of the frame. */
9954 if (frame
->gp_sp_offset
> 0)
9955 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
9956 if (frame
->fp_sp_offset
> 0)
9957 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
9958 if (frame
->acc_sp_offset
> 0)
9959 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
9960 if (frame
->num_cop0_regs
> 0)
9961 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
9963 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9964 arguments. This tends to increase the chances of using unextended
9965 instructions for local variables and incoming arguments. */
9967 frame
->hard_frame_pointer_offset
= frame
->args_size
;
9970 /* Return the style of GP load sequence that is being used for the
9971 current function. */
9973 enum mips_loadgp_style
9974 mips_current_loadgp_style (void)
9976 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
9982 if (TARGET_ABSOLUTE_ABICALLS
)
9983 return LOADGP_ABSOLUTE
;
9985 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
9988 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9991 mips_frame_pointer_required (void)
9993 /* If the function contains dynamic stack allocations, we need to
9994 use the frame pointer to access the static parts of the frame. */
9995 if (cfun
->calls_alloca
)
9998 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9999 reload may be unable to compute the address of a local variable,
10000 since there is no way to add a large constant to the stack pointer
10001 without using a second temporary register. */
10004 mips_compute_frame_info ();
10005 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
10012 /* Make sure that we're not trying to eliminate to the wrong hard frame
10016 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
10018 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
10021 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10022 or argument pointer. TO is either the stack pointer or hard frame
10026 mips_initial_elimination_offset (int from
, int to
)
10028 HOST_WIDE_INT offset
;
10030 mips_compute_frame_info ();
10032 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10035 case FRAME_POINTER_REGNUM
:
10036 if (FRAME_GROWS_DOWNWARD
)
10037 offset
= (cfun
->machine
->frame
.args_size
10038 + cfun
->machine
->frame
.cprestore_size
10039 + cfun
->machine
->frame
.var_size
);
10044 case ARG_POINTER_REGNUM
:
10045 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
10049 gcc_unreachable ();
10052 if (to
== HARD_FRAME_POINTER_REGNUM
)
10053 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10058 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10061 mips_extra_live_on_entry (bitmap regs
)
10063 if (TARGET_USE_GOT
)
10065 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10066 the global pointer. */
10067 if (!TARGET_ABSOLUTE_ABICALLS
)
10068 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
10070 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10071 the global pointer. */
10073 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
10075 /* See the comment above load_call<mode> for details. */
10076 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
10080 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10084 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
10089 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
10092 /* Emit code to change the current function's return address to
10093 ADDRESS. SCRATCH is available as a scratch register, if needed.
10094 ADDRESS and SCRATCH are both word-mode GPRs. */
10097 mips_set_return_address (rtx address
, rtx scratch
)
10101 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
10102 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
10103 cfun
->machine
->frame
.gp_sp_offset
);
10104 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
10107 /* Return true if the current function has a cprestore slot. */
10110 mips_cfun_has_cprestore_slot_p (void)
10112 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
10113 && cfun
->machine
->frame
.cprestore_size
> 0);
10116 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10117 cprestore slot. LOAD_P is true if the caller wants to load from
10118 the cprestore slot; it is false if the caller wants to store to
10122 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
10125 const struct mips_frame_info
*frame
;
10127 frame
= &cfun
->machine
->frame
;
10128 /* .cprestore always uses the stack pointer instead of the frame pointer.
10129 We have a free choice for direct stores for non-MIPS16 functions,
10130 and for MIPS16 functions whose cprestore slot is in range of the
10131 stack pointer. Using the stack pointer would sometimes give more
10132 (early) scheduling freedom, but using the frame pointer would
10133 sometimes give more (late) scheduling freedom. It's hard to
10134 predict which applies to a given function, so let's keep things
10137 Loads must always use the frame pointer in functions that call
10138 alloca, and there's little benefit to using the stack pointer
10140 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
10142 *base
= hard_frame_pointer_rtx
;
10143 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
10147 *base
= stack_pointer_rtx
;
10148 *offset
= frame
->args_size
;
10152 /* Return true if X is the load or store address of the cprestore slot;
10153 LOAD_P says which. */
10156 mips_cprestore_address_p (rtx x
, bool load_p
)
10158 rtx given_base
, required_base
;
10159 HOST_WIDE_INT given_offset
, required_offset
;
10161 mips_split_plus (x
, &given_base
, &given_offset
);
10162 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
10163 return given_base
== required_base
&& given_offset
== required_offset
;
10166 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10167 going to load from it, false if we are going to store to it.
10168 Use TEMP as a temporary register if need be. */
10171 mips_cprestore_slot (rtx temp
, bool load_p
)
10174 HOST_WIDE_INT offset
;
10176 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
10177 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
10180 /* Emit instructions to save global pointer value GP into cprestore
10181 slot MEM. OFFSET is the offset that MEM applies to the base register.
10183 MEM may not be a legitimate address. If it isn't, TEMP is a
10184 temporary register that can be used, otherwise it is a SCRATCH. */
10187 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
10189 if (TARGET_CPRESTORE_DIRECTIVE
)
10191 gcc_assert (gp
== pic_offset_table_rtx
);
10192 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
10195 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
10198 /* Restore $gp from its save slot, using TEMP as a temporary base register
10199 if need be. This function is for o32 and o64 abicalls only.
10201 See mips_must_initialize_gp_p for details about how we manage the
10205 mips_restore_gp_from_cprestore_slot (rtx temp
)
10207 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
10209 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
10211 emit_note (NOTE_INSN_DELETED
);
10217 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
10218 mips_emit_move (pic_offset_table_rtx
, temp
);
10221 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
10222 if (!TARGET_EXPLICIT_RELOCS
)
10223 emit_insn (gen_blockage ());
10226 /* A function to save or store a register. The first argument is the
10227 register and the second is the stack slot. */
10228 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
10230 /* Use FN to save or restore register REGNO. MODE is the register's
10231 mode and OFFSET is the offset of its save slot from the current
10235 mips_save_restore_reg (enum machine_mode mode
, int regno
,
10236 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
10240 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
10242 fn (gen_rtx_REG (mode
, regno
), mem
);
10245 /* Call FN for each accumlator that is saved by the current function.
10246 SP_OFFSET is the offset of the current stack pointer from the start
10250 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
10252 HOST_WIDE_INT offset
;
10255 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
10256 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
10258 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
10259 offset
-= UNITS_PER_WORD
;
10260 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
10261 offset
-= UNITS_PER_WORD
;
10264 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
10265 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
10266 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
10268 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10269 offset
-= UNITS_PER_WORD
;
10273 /* Call FN for each register that is saved by the current function.
10274 SP_OFFSET is the offset of the current stack pointer from the start
10278 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
10279 mips_save_restore_fn fn
)
10281 enum machine_mode fpr_mode
;
10282 HOST_WIDE_INT offset
;
10285 /* Save registers starting from high to low. The debuggers prefer at least
10286 the return register be stored at func+4, and also it allows us not to
10287 need a nop in the epilogue if at least one register is reloaded in
10288 addition to return address. */
10289 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
10290 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
10291 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
10293 /* Record the ra offset for use by mips_function_profiler. */
10294 if (regno
== RETURN_ADDR_REGNUM
)
10295 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
10296 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
10297 offset
-= UNITS_PER_WORD
;
10300 /* This loop must iterate over the same space as its companion in
10301 mips_compute_frame_info. */
10302 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
10303 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
10304 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
10305 regno
>= FP_REG_FIRST
;
10306 regno
-= MAX_FPRS_PER_FMT
)
10307 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
10309 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
10310 offset
-= GET_MODE_SIZE (fpr_mode
);
10314 /* Return true if a move between register REGNO and its save slot (MEM)
10315 can be done in a single move. LOAD_P is true if we are loading
10316 from the slot, false if we are storing to it. */
10319 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
10321 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10322 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
10325 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
10326 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
10329 /* Emit a move from SRC to DEST, given that one of them is a register
10330 save slot and that the other is a register. TEMP is a temporary
10331 GPR of the same mode that is available if need be. */
10334 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
10336 unsigned int regno
;
10341 regno
= REGNO (src
);
10346 regno
= REGNO (dest
);
10350 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
10352 /* We don't yet know whether we'll need this instruction or not.
10353 Postpone the decision by emitting a ghost move. This move
10354 is specifically not frame-related; only the split version is. */
10356 emit_insn (gen_move_gpdi (dest
, src
));
10358 emit_insn (gen_move_gpsi (dest
, src
));
10362 if (regno
== HI_REGNUM
)
10366 mips_emit_move (temp
, src
);
10368 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
10369 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
10371 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
10372 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
10377 emit_insn (gen_mfhidi_ti (temp
,
10378 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
10380 emit_insn (gen_mfhisi_di (temp
,
10381 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
10382 mips_emit_move (dest
, temp
);
10385 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
10386 mips_emit_move (dest
, src
);
10389 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
10390 mips_emit_move (temp
, src
);
10391 mips_emit_move (dest
, temp
);
10394 mips_set_frame_expr (mips_frame_set (dest
, src
));
10397 /* If we're generating n32 or n64 abicalls, and the current function
10398 does not use $28 as its global pointer, emit a cplocal directive.
10399 Use pic_offset_table_rtx as the argument to the directive. */
10402 mips_output_cplocal (void)
10404 if (!TARGET_EXPLICIT_RELOCS
10405 && mips_must_initialize_gp_p ()
10406 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
10407 output_asm_insn (".cplocal %+", 0);
10410 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10413 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10415 const char *fnname
;
10417 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10418 floating-point arguments. */
10420 && TARGET_HARD_FLOAT_ABI
10421 && crtl
->args
.info
.fp_code
!= 0)
10422 mips16_build_function_stub ();
10424 /* Get the function name the same way that toplev.c does before calling
10425 assemble_start_function. This is needed so that the name used here
10426 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10427 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10428 mips_start_function_definition (fnname
, TARGET_MIPS16
);
10430 /* Output MIPS-specific frame information. */
10431 if (!flag_inhibit_size_directive
)
10433 const struct mips_frame_info
*frame
;
10435 frame
= &cfun
->machine
->frame
;
10437 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10439 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
10440 "# vars= " HOST_WIDE_INT_PRINT_DEC
10442 ", args= " HOST_WIDE_INT_PRINT_DEC
10443 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
10444 reg_names
[frame_pointer_needed
10445 ? HARD_FRAME_POINTER_REGNUM
10446 : STACK_POINTER_REGNUM
],
10447 (frame_pointer_needed
10448 ? frame
->total_size
- frame
->hard_frame_pointer_offset
10449 : frame
->total_size
),
10450 reg_names
[RETURN_ADDR_REGNUM
],
10452 frame
->num_gp
, frame
->num_fp
,
10454 frame
->cprestore_size
);
10456 /* .mask MASK, OFFSET. */
10457 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10458 frame
->mask
, frame
->gp_save_offset
);
10460 /* .fmask MASK, OFFSET. */
10461 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
10462 frame
->fmask
, frame
->fp_save_offset
);
10465 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10466 Also emit the ".set noreorder; .set nomacro" sequence for functions
10468 if (mips_must_initialize_gp_p ()
10469 && mips_current_loadgp_style () == LOADGP_OLDABI
)
10473 /* This is a fixed-form sequence. The position of the
10474 first two instructions is important because of the
10475 way _gp_disp is defined. */
10476 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10477 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10478 output_asm_insn ("sll\t$2,16", 0);
10479 output_asm_insn ("addu\t$2,$3", 0);
10483 /* .cpload must be in a .set noreorder but not a
10484 .set nomacro block. */
10485 mips_push_asm_switch (&mips_noreorder
);
10486 output_asm_insn (".cpload\t%^", 0);
10487 if (!cfun
->machine
->all_noreorder_p
)
10488 mips_pop_asm_switch (&mips_noreorder
);
10490 mips_push_asm_switch (&mips_nomacro
);
10493 else if (cfun
->machine
->all_noreorder_p
)
10495 mips_push_asm_switch (&mips_noreorder
);
10496 mips_push_asm_switch (&mips_nomacro
);
10499 /* Tell the assembler which register we're using as the global
10500 pointer. This is needed for thunks, since they can use either
10501 explicit relocs or assembler macros. */
10502 mips_output_cplocal ();
10505 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10508 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
10509 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
10511 const char *fnname
;
10513 /* Reinstate the normal $gp. */
10514 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
10515 mips_output_cplocal ();
10517 if (cfun
->machine
->all_noreorder_p
)
10519 mips_pop_asm_switch (&mips_nomacro
);
10520 mips_pop_asm_switch (&mips_noreorder
);
10523 /* Get the function name the same way that toplev.c does before calling
10524 assemble_start_function. This is needed so that the name used here
10525 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10526 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10527 mips_end_function_definition (fnname
);
10530 /* Emit an optimisation barrier for accesses to the current frame. */
10533 mips_frame_barrier (void)
10535 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
10538 /* Save register REG to MEM. Make the instruction frame-related. */
10541 mips_save_reg (rtx reg
, rtx mem
)
10543 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
10547 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
10549 x1
= mips_frame_set (mips_subword (mem
, false),
10550 mips_subword (reg
, false));
10551 x2
= mips_frame_set (mips_subword (mem
, true),
10552 mips_subword (reg
, true));
10553 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
10556 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
10559 /* The __gnu_local_gp symbol. */
10561 static GTY(()) rtx mips_gnu_local_gp
;
10563 /* If we're generating n32 or n64 abicalls, emit instructions
10564 to set up the global pointer. */
10567 mips_emit_loadgp (void)
10569 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
10571 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10572 switch (mips_current_loadgp_style ())
10574 case LOADGP_ABSOLUTE
:
10575 if (mips_gnu_local_gp
== NULL
)
10577 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10578 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10580 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
10581 (pic_reg
, mips_gnu_local_gp
)));
10584 case LOADGP_OLDABI
:
10585 /* Added by mips_output_function_prologue. */
10588 case LOADGP_NEWABI
:
10589 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10590 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10591 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10592 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
10593 (pic_reg
, offset
, incoming_address
)));
10597 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10598 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10599 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
10607 emit_insn (PMODE_INSN (gen_copygp_mips16
,
10608 (pic_offset_table_rtx
, pic_reg
)));
10610 /* Emit a blockage if there are implicit uses of the GP register.
10611 This includes profiled functions, because FUNCTION_PROFILE uses
10613 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10614 emit_insn (gen_loadgp_blockage ());
10617 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10619 #if PROBE_INTERVAL > 32768
10620 #error Cannot use indexed addressing mode for stack probing
10623 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10624 inclusive. These are offsets from the current stack pointer. */
10627 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
10630 sorry ("-fstack-check=specific not implemented for MIPS16");
10632 /* See if we have a constant small number of probes to generate. If so,
10633 that's the easy case. */
10634 if (first
+ size
<= 32768)
10638 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10639 it exceeds SIZE. If only one probe is needed, this will not
10640 generate any code. Then probe at FIRST + SIZE. */
10641 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
10642 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10645 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
10649 /* Otherwise, do the same as above, but in a loop. Note that we must be
10650 extra careful with variables wrapping around because we might be at
10651 the very top (or the very bottom) of the address space and we have
10652 to be able to handle this case properly; in particular, we use an
10653 equality test for the loop condition. */
10656 HOST_WIDE_INT rounded_size
;
10657 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
10658 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
10660 /* Sanity check for the addressing mode we're going to use. */
10661 gcc_assert (first
<= 32768);
10664 /* Step 1: round SIZE to the previous multiple of the interval. */
10666 rounded_size
= size
& -PROBE_INTERVAL
;
10669 /* Step 2: compute initial and final value of the loop counter. */
10671 /* TEST_ADDR = SP + FIRST. */
10672 emit_insn (gen_rtx_SET (VOIDmode
, r3
,
10673 plus_constant (Pmode
, stack_pointer_rtx
,
10676 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10677 if (rounded_size
> 32768)
10679 emit_move_insn (r12
, GEN_INT (rounded_size
));
10680 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10681 gen_rtx_MINUS (Pmode
, r3
, r12
)));
10684 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
10685 plus_constant (Pmode
, r3
, -rounded_size
)));
10688 /* Step 3: the loop
10690 while (TEST_ADDR != LAST_ADDR)
10692 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10696 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10697 until it is equal to ROUNDED_SIZE. */
10699 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
10702 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10703 that SIZE is equal to ROUNDED_SIZE. */
10705 if (size
!= rounded_size
)
10706 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
10709 /* Make sure nothing is scheduled before we are done. */
10710 emit_insn (gen_blockage ());
10713 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
10714 absolute addresses. */
10717 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
10719 static int labelno
= 0;
10720 char loop_lab
[32], end_lab
[32], tmp
[64];
10723 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
10724 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
10726 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
10728 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10731 strcpy (tmp
, "%(%<beq\t%0,%1,");
10732 output_asm_insn (strcat (tmp
, &end_lab
[1]), xops
);
10734 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10735 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
10736 if (TARGET_64BIT
&& TARGET_LONG64
)
10737 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
10739 output_asm_insn ("addiu\t%0,%0,%1", xops
);
10741 /* Probe at TEST_ADDR and branch. */
10742 fprintf (asm_out_file
, "\tb\t");
10743 assemble_name_raw (asm_out_file
, loop_lab
);
10744 fputc ('\n', asm_out_file
);
10746 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
10748 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
10750 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
10755 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10758 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10760 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10763 /* Expand the "prologue" pattern. */
10766 mips_expand_prologue (void)
10768 const struct mips_frame_info
*frame
;
10769 HOST_WIDE_INT size
;
10770 unsigned int nargs
;
10773 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10775 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10776 or implicitly. If so, we can commit to using a global pointer
10777 straight away, otherwise we need to defer the decision. */
10778 if (mips_cfun_has_inflexible_gp_ref_p ()
10779 || mips_cfun_has_flexible_gp_ref_p ())
10781 cfun
->machine
->must_initialize_gp_p
= true;
10782 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10785 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10788 frame
= &cfun
->machine
->frame
;
10789 size
= frame
->total_size
;
10791 if (flag_stack_usage_info
)
10792 current_function_static_stack_size
= size
;
10794 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
&& size
)
10795 mips_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
10797 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10798 bytes beforehand; this is enough to cover the register save area
10799 without going out of range. */
10800 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
10801 || frame
->num_cop0_regs
> 0)
10803 HOST_WIDE_INT step1
;
10805 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10806 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10808 HOST_WIDE_INT offset
;
10809 unsigned int mask
, regno
;
10811 /* Try to merge argument stores into the save instruction. */
10812 nargs
= mips16e_collect_argument_saves ();
10814 /* Build the save instruction. */
10815 mask
= frame
->mask
;
10816 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
10818 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10819 mips_frame_barrier ();
10822 /* Check if we need to save other registers. */
10823 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10824 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10826 offset
-= UNITS_PER_WORD
;
10827 mips_save_restore_reg (word_mode
, regno
,
10828 offset
, mips_save_reg
);
10833 if (cfun
->machine
->interrupt_handler_p
)
10835 HOST_WIDE_INT offset
;
10838 /* If this interrupt is using a shadow register set, we need to
10839 get the stack pointer from the previous register set. */
10840 if (cfun
->machine
->use_shadow_register_set_p
)
10841 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
10842 stack_pointer_rtx
));
10844 if (!cfun
->machine
->keep_interrupts_masked_p
)
10846 /* Move from COP0 Cause to K0. */
10847 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
10848 gen_rtx_REG (SImode
,
10849 COP0_CAUSE_REG_NUM
)));
10850 /* Move from COP0 EPC to K1. */
10851 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10852 gen_rtx_REG (SImode
,
10853 COP0_EPC_REG_NUM
)));
10856 /* Allocate the first part of the frame. */
10857 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
10859 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10860 mips_frame_barrier ();
10863 /* Start at the uppermost location for saving. */
10864 offset
= frame
->cop0_sp_offset
- size
;
10865 if (!cfun
->machine
->keep_interrupts_masked_p
)
10867 /* Push EPC into its stack slot. */
10868 mem
= gen_frame_mem (word_mode
,
10869 plus_constant (Pmode
, stack_pointer_rtx
,
10871 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10872 offset
-= UNITS_PER_WORD
;
10875 /* Move from COP0 Status to K1. */
10876 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10877 gen_rtx_REG (SImode
,
10878 COP0_STATUS_REG_NUM
)));
10880 /* Right justify the RIPL in k0. */
10881 if (!cfun
->machine
->keep_interrupts_masked_p
)
10882 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
10883 gen_rtx_REG (SImode
, K0_REG_NUM
),
10884 GEN_INT (CAUSE_IPL
)));
10886 /* Push Status into its stack slot. */
10887 mem
= gen_frame_mem (word_mode
,
10888 plus_constant (Pmode
, stack_pointer_rtx
,
10890 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10891 offset
-= UNITS_PER_WORD
;
10893 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10894 if (!cfun
->machine
->keep_interrupts_masked_p
)
10895 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10898 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10900 if (!cfun
->machine
->keep_interrupts_masked_p
)
10901 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10902 IE is already the correct value, so we don't have to do
10903 anything explicit. */
10904 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10907 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10909 /* Disable interrupts by clearing the KSU, ERL, EXL,
10911 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10914 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10918 insn
= gen_add3_insn (stack_pointer_rtx
,
10921 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10922 mips_frame_barrier ();
10925 mips_for_each_saved_acc (size
, mips_save_reg
);
10926 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
10930 /* Allocate the rest of the frame. */
10933 if (SMALL_OPERAND (-size
))
10934 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
10936 GEN_INT (-size
)))) = 1;
10939 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
10942 /* There are no instructions to add or subtract registers
10943 from the stack pointer, so use the frame pointer as a
10944 temporary. We should always be using a frame pointer
10945 in this case anyway. */
10946 gcc_assert (frame_pointer_needed
);
10947 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10948 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
10949 hard_frame_pointer_rtx
,
10950 MIPS_PROLOGUE_TEMP (Pmode
)));
10951 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
10954 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
10956 MIPS_PROLOGUE_TEMP (Pmode
)));
10958 /* Describe the combined effect of the previous instructions. */
10959 mips_set_frame_expr
10960 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10961 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
10963 mips_frame_barrier ();
10966 /* Set up the frame pointer, if we're using one. */
10967 if (frame_pointer_needed
)
10969 HOST_WIDE_INT offset
;
10971 offset
= frame
->hard_frame_pointer_offset
;
10974 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10975 RTX_FRAME_RELATED_P (insn
) = 1;
10977 else if (SMALL_OPERAND (offset
))
10979 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
10980 stack_pointer_rtx
, GEN_INT (offset
));
10981 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10985 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
10986 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10987 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
10988 hard_frame_pointer_rtx
,
10989 MIPS_PROLOGUE_TEMP (Pmode
)));
10990 mips_set_frame_expr
10991 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
10992 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
10996 mips_emit_loadgp ();
10998 /* Initialize the $gp save slot. */
10999 if (mips_cfun_has_cprestore_slot_p ())
11001 rtx base
, mem
, gp
, temp
;
11002 HOST_WIDE_INT offset
;
11004 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
11005 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11006 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11007 temp
= (SMALL_OPERAND (offset
)
11008 ? gen_rtx_SCRATCH (Pmode
)
11009 : MIPS_PROLOGUE_TEMP (Pmode
));
11010 emit_insn (PMODE_INSN (gen_potential_cprestore
,
11011 (mem
, GEN_INT (offset
), gp
, temp
)));
11013 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11014 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
11015 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
11018 /* We need to search back to the last use of K0 or K1. */
11019 if (cfun
->machine
->interrupt_handler_p
)
11021 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
11023 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
11025 /* Emit a move from K1 to COP0 Status after insn. */
11026 gcc_assert (insn
!= NULL_RTX
);
11027 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11028 gen_rtx_REG (SImode
, K1_REG_NUM
)),
11032 /* If we are profiling, make sure no instructions are scheduled before
11033 the call to mcount. */
11035 emit_insn (gen_blockage ());
11038 /* Attach all pending register saves to the previous instruction.
11039 Return that instruction. */
11042 mips_epilogue_emit_cfa_restores (void)
11046 insn
= get_last_insn ();
11047 gcc_assert (insn
&& !REG_NOTES (insn
));
11048 if (mips_epilogue
.cfa_restores
)
11050 RTX_FRAME_RELATED_P (insn
) = 1;
11051 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
11052 mips_epilogue
.cfa_restores
= 0;
11057 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11058 now at REG + OFFSET. */
11061 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
11065 insn
= mips_epilogue_emit_cfa_restores ();
11066 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
11068 RTX_FRAME_RELATED_P (insn
) = 1;
11069 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
11070 plus_constant (Pmode
, reg
, offset
),
11072 mips_epilogue
.cfa_reg
= reg
;
11073 mips_epilogue
.cfa_offset
= offset
;
11077 /* Emit instructions to restore register REG from slot MEM. Also update
11078 the cfa_restores list. */
11081 mips_restore_reg (rtx reg
, rtx mem
)
11083 /* There's no MIPS16 instruction to load $31 directly. Load into
11084 $7 instead and adjust the return insn appropriately. */
11085 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
11086 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
11087 else if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
11089 mips_add_cfa_restore (mips_subword (reg
, true));
11090 mips_add_cfa_restore (mips_subword (reg
, false));
11093 mips_add_cfa_restore (reg
);
11095 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
11096 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
11097 /* The CFA is currently defined in terms of the register whose
11098 value we have just restored. Redefine the CFA in terms of
11099 the stack pointer. */
11100 mips_epilogue_set_cfa (stack_pointer_rtx
,
11101 mips_epilogue
.cfa_restore_sp_offset
);
11104 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11105 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11106 BASE, if not the stack pointer, is available as a temporary. */
11109 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
11111 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
11114 mips_frame_barrier ();
11115 if (offset
== const0_rtx
)
11117 emit_move_insn (stack_pointer_rtx
, base
);
11118 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11120 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
11122 emit_insn (gen_add3_insn (base
, base
, offset
));
11123 mips_epilogue_set_cfa (base
, new_frame_size
);
11124 emit_move_insn (stack_pointer_rtx
, base
);
11128 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
11129 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
11133 /* Emit any instructions needed before a return. */
11136 mips_expand_before_return (void)
11138 /* When using a call-clobbered gp, we start out with unified call
11139 insns that include instructions to restore the gp. We then split
11140 these unified calls after reload. These split calls explicitly
11141 clobber gp, so there is no need to define
11142 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11144 For consistency, we should also insert an explicit clobber of $28
11145 before return insns, so that the post-reload optimizers know that
11146 the register is not live on exit. */
11147 if (TARGET_CALL_CLOBBERED_GP
)
11148 emit_clobber (pic_offset_table_rtx
);
11151 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11155 mips_expand_epilogue (bool sibcall_p
)
11157 const struct mips_frame_info
*frame
;
11158 HOST_WIDE_INT step1
, step2
;
11159 rtx base
, adjust
, insn
;
11161 if (!sibcall_p
&& mips_can_use_return_insn ())
11163 emit_jump_insn (gen_return ());
11167 /* In MIPS16 mode, if the return value should go into a floating-point
11168 register, we need to call a helper routine to copy it over. */
11169 if (mips16_cfun_returns_in_fpr_p ())
11170 mips16_copy_fpr_return_value ();
11172 /* Split the frame into two. STEP1 is the amount of stack we should
11173 deallocate before restoring the registers. STEP2 is the amount we
11174 should deallocate afterwards.
11176 Start off by assuming that no registers need to be restored. */
11177 frame
= &cfun
->machine
->frame
;
11178 step1
= frame
->total_size
;
11181 /* Work out which register holds the frame address. */
11182 if (!frame_pointer_needed
)
11183 base
= stack_pointer_rtx
;
11186 base
= hard_frame_pointer_rtx
;
11187 step1
-= frame
->hard_frame_pointer_offset
;
11189 mips_epilogue
.cfa_reg
= base
;
11190 mips_epilogue
.cfa_offset
= step1
;
11191 mips_epilogue
.cfa_restores
= NULL_RTX
;
11193 /* If we need to restore registers, deallocate as much stack as
11194 possible in the second step without going out of range. */
11195 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
11196 || frame
->num_cop0_regs
> 0)
11198 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
11202 /* Get an rtx for STEP1 that we can add to BASE. */
11203 adjust
= GEN_INT (step1
);
11204 if (!SMALL_OPERAND (step1
))
11206 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
11207 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
11209 mips_deallocate_stack (base
, adjust
, step2
);
11211 /* If we're using addressing macros, $gp is implicitly used by all
11212 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11214 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
11215 emit_insn (gen_blockage ());
11217 mips_epilogue
.cfa_restore_sp_offset
= step2
;
11218 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
11220 unsigned int regno
, mask
;
11221 HOST_WIDE_INT offset
;
11224 /* Generate the restore instruction. */
11225 mask
= frame
->mask
;
11226 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
11228 /* Restore any other registers manually. */
11229 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
11230 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11232 offset
-= UNITS_PER_WORD
;
11233 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
11236 /* Restore the remaining registers and deallocate the final bit
11238 mips_frame_barrier ();
11239 emit_insn (restore
);
11240 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
11244 /* Restore the registers. */
11245 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
11246 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
11249 if (cfun
->machine
->interrupt_handler_p
)
11251 HOST_WIDE_INT offset
;
11254 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
11255 if (!cfun
->machine
->keep_interrupts_masked_p
)
11257 /* Restore the original EPC. */
11258 mem
= gen_frame_mem (word_mode
,
11259 plus_constant (Pmode
, stack_pointer_rtx
,
11261 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11262 offset
-= UNITS_PER_WORD
;
11264 /* Move to COP0 EPC. */
11265 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
11266 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11269 /* Restore the original Status. */
11270 mem
= gen_frame_mem (word_mode
,
11271 plus_constant (Pmode
, stack_pointer_rtx
,
11273 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
11274 offset
-= UNITS_PER_WORD
;
11276 /* If we don't use shoadow register set, we need to update SP. */
11277 if (!cfun
->machine
->use_shadow_register_set_p
)
11278 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11280 /* The choice of position is somewhat arbitrary in this case. */
11281 mips_epilogue_emit_cfa_restores ();
11283 /* Move to COP0 Status. */
11284 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
11285 gen_rtx_REG (SImode
, K0_REG_NUM
)));
11288 /* Deallocate the final bit of the frame. */
11289 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
11291 gcc_assert (!mips_epilogue
.cfa_restores
);
11293 /* Add in the __builtin_eh_return stack adjustment. We need to
11294 use a temporary in MIPS16 code. */
11295 if (crtl
->calls_eh_return
)
11299 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
11300 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
11301 MIPS_EPILOGUE_TEMP (Pmode
),
11302 EH_RETURN_STACKADJ_RTX
));
11303 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
11306 emit_insn (gen_add3_insn (stack_pointer_rtx
,
11308 EH_RETURN_STACKADJ_RTX
));
11313 mips_expand_before_return ();
11314 if (cfun
->machine
->interrupt_handler_p
)
11316 /* Interrupt handlers generate eret or deret. */
11317 if (cfun
->machine
->use_debug_exception_return_p
)
11318 emit_jump_insn (gen_mips_deret ());
11320 emit_jump_insn (gen_mips_eret ());
11326 /* When generating MIPS16 code, the normal
11327 mips_for_each_saved_gpr_and_fpr path will restore the return
11328 address into $7 rather than $31. */
11330 && !GENERATE_MIPS16E_SAVE_RESTORE
11331 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
11333 /* simple_returns cannot rely on values that are only available
11334 on paths through the epilogue (because return paths that do
11335 not pass through the epilogue may nevertheless reuse a
11336 simple_return that occurs at the end of the epilogue).
11337 Use a normal return here instead. */
11338 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
11339 pat
= gen_return_internal (reg
);
11343 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
11344 pat
= gen_simple_return_internal (reg
);
11346 emit_jump_insn (pat
);
11350 /* Search from the beginning to the first use of K0 or K1. */
11351 if (cfun
->machine
->interrupt_handler_p
11352 && !cfun
->machine
->keep_interrupts_masked_p
)
11354 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
11356 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
11358 gcc_assert (insn
!= NULL_RTX
);
11359 /* Insert disable interrupts before the first use of K0 or K1. */
11360 emit_insn_before (gen_mips_di (), insn
);
11361 emit_insn_before (gen_mips_ehb (), insn
);
11365 /* Return nonzero if this function is known to have a null epilogue.
11366 This allows the optimizer to omit jumps to jumps if no stack
11370 mips_can_use_return_insn (void)
11372 /* Interrupt handlers need to go through the epilogue. */
11373 if (cfun
->machine
->interrupt_handler_p
)
11376 if (!reload_completed
)
11382 /* In MIPS16 mode, a function that returns a floating-point value
11383 needs to arrange to copy the return value into the floating-point
11385 if (mips16_cfun_returns_in_fpr_p ())
11388 return cfun
->machine
->frame
.total_size
== 0;
11391 /* Return true if register REGNO can store a value of mode MODE.
11392 The result of this function is cached in mips_hard_regno_mode_ok. */
11395 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
11398 enum mode_class mclass
;
11400 if (mode
== CCV2mode
)
11401 return (ISA_HAS_8CC
11402 && ST_REG_P (regno
)
11403 && (regno
- ST_REG_FIRST
) % 2 == 0);
11405 if (mode
== CCV4mode
)
11406 return (ISA_HAS_8CC
11407 && ST_REG_P (regno
)
11408 && (regno
- ST_REG_FIRST
) % 4 == 0);
11410 if (mode
== CCmode
)
11411 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
11413 size
= GET_MODE_SIZE (mode
);
11414 mclass
= GET_MODE_CLASS (mode
);
11416 if (GP_REG_P (regno
))
11417 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
11419 if (FP_REG_P (regno
)
11420 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
11421 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
11423 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11424 if (TARGET_LOONGSON_VECTORS
11425 && (mode
== V2SImode
11426 || mode
== V4HImode
11427 || mode
== V8QImode
11428 || mode
== DImode
))
11431 if (mclass
== MODE_FLOAT
11432 || mclass
== MODE_COMPLEX_FLOAT
11433 || mclass
== MODE_VECTOR_FLOAT
)
11434 return size
<= UNITS_PER_FPVALUE
;
11436 /* Allow integer modes that fit into a single register. We need
11437 to put integers into FPRs when using instructions like CVT
11438 and TRUNC. There's no point allowing sizes smaller than a word,
11439 because the FPU has no appropriate load/store instructions. */
11440 if (mclass
== MODE_INT
)
11441 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
11444 if (ACC_REG_P (regno
)
11445 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
11447 if (MD_REG_P (regno
))
11449 /* After a multiplication or division, clobbering HI makes
11450 the value of LO unpredictable, and vice versa. This means
11451 that, for all interesting cases, HI and LO are effectively
11454 We model this by requiring that any value that uses HI
11456 if (size
<= UNITS_PER_WORD
* 2)
11457 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
11461 /* DSP accumulators do not have the same restrictions as
11462 HI and LO, so we can treat them as normal doubleword
11464 if (size
<= UNITS_PER_WORD
)
11467 if (size
<= UNITS_PER_WORD
* 2
11468 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
11473 if (ALL_COP_REG_P (regno
))
11474 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
11476 if (regno
== GOT_VERSION_REGNUM
)
11477 return mode
== SImode
;
11482 /* Implement HARD_REGNO_NREGS. */
11485 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
11487 if (ST_REG_P (regno
))
11488 /* The size of FP status registers is always 4, because they only hold
11489 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11490 return (GET_MODE_SIZE (mode
) + 3) / 4;
11492 if (FP_REG_P (regno
))
11493 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
11495 /* All other registers are word-sized. */
11496 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
11499 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11500 in mips_hard_regno_nregs. */
11503 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
11509 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
11510 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
11512 if (HARD_REGNO_MODE_OK (ST_REG_FIRST
, mode
))
11513 size
= MIN (size
, 4);
11514 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
11516 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
11518 if (HARD_REGNO_MODE_OK (FP_REG_FIRST
, mode
))
11519 size
= MIN (size
, UNITS_PER_FPREG
);
11520 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
11522 if (!hard_reg_set_empty_p (left
))
11523 size
= MIN (size
, UNITS_PER_WORD
);
11524 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
11527 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11530 mips_cannot_change_mode_class (enum machine_mode from
,
11531 enum machine_mode to
,
11532 enum reg_class rclass
)
11534 /* Allow conversions between different Loongson integer vectors,
11535 and between those vectors and DImode. */
11536 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
11537 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
11540 /* Otherwise, there are several problems with changing the modes of
11541 values in floating-point registers:
11543 - When a multi-word value is stored in paired floating-point
11544 registers, the first register always holds the low word. We
11545 therefore can't allow FPRs to change between single-word and
11546 multi-word modes on big-endian targets.
11548 - GCC assumes that each word of a multiword register can be
11549 accessed individually using SUBREGs. This is not true for
11550 floating-point registers if they are bigger than a word.
11552 - Loading a 32-bit value into a 64-bit floating-point register
11553 will not sign-extend the value, despite what LOAD_EXTEND_OP
11554 says. We can't allow FPRs to change from SImode to a wider
11555 mode on 64-bit targets.
11557 - If the FPU has already interpreted a value in one format, we
11558 must not ask it to treat the value as having a different
11561 We therefore disallow all mode changes involving FPRs. */
11563 return reg_classes_intersect_p (FP_REGS
, rclass
);
11566 /* Implement target hook small_register_classes_for_mode_p. */
11569 mips_small_register_classes_for_mode_p (enum machine_mode mode
11572 return TARGET_MIPS16
;
11575 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11578 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
11583 return TARGET_HARD_FLOAT
;
11586 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
11589 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
11596 /* Implement MODES_TIEABLE_P. */
11599 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
11601 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11602 prefer to put one of them in FPRs. */
11603 return (mode1
== mode2
11604 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
11605 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
11608 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11611 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
11613 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
11616 if (reg_class_subset_p (FP_REGS
, rclass
)
11617 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
11620 if (reg_class_subset_p (GR_REGS
, rclass
))
11623 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
11629 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11630 Return a "canonical" class to represent it in later calculations. */
11633 mips_canonicalize_move_class (reg_class_t rclass
)
11635 /* All moves involving accumulator registers have the same cost. */
11636 if (reg_class_subset_p (rclass
, ACC_REGS
))
11639 /* Likewise promote subclasses of general registers to the most
11640 interesting containing class. */
11641 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
11643 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
11644 rclass
= GENERAL_REGS
;
11649 /* Return the cost of moving a value of mode MODE from a register of
11650 class FROM to a GPR. Return 0 for classes that are unions of other
11651 classes handled by this function. */
11654 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11660 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11664 /* MFLO and MFHI. */
11672 /* LUI followed by MOVF. */
11678 /* This choice of value is historical. */
11686 /* Return the cost of moving a value of mode MODE from a GPR to a
11687 register of class TO. Return 0 for classes that are unions of
11688 other classes handled by this function. */
11691 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
11696 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11700 /* MTLO and MTHI. */
11708 /* A secondary reload through an FPR scratch. */
11709 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
11710 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
11715 /* This choice of value is historical. */
11723 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11724 maximum of the move costs for subclasses; regclass will work out
11725 the maximum for us. */
11728 mips_register_move_cost (enum machine_mode mode
,
11729 reg_class_t from
, reg_class_t to
)
11734 from
= mips_canonicalize_move_class (from
);
11735 to
= mips_canonicalize_move_class (to
);
11737 /* Handle moves that can be done without using general-purpose registers. */
11738 if (from
== FP_REGS
)
11740 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
11744 /* The sequence generated by mips_expand_fcc_reload. */
11748 /* Handle cases in which only one class deviates from the ideal. */
11749 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
11751 return mips_move_from_gpr_cost (mode
, to
);
11753 return mips_move_to_gpr_cost (mode
, from
);
11755 /* Handles cases that require a GPR temporary. */
11756 cost1
= mips_move_to_gpr_cost (mode
, from
);
11759 cost2
= mips_move_from_gpr_cost (mode
, to
);
11761 return cost1
+ cost2
;
11767 /* Implement TARGET_MEMORY_MOVE_COST. */
11770 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
11772 return (mips_cost
->memory_latency
11773 + memory_move_secondary_cost (mode
, rclass
, in
));
11776 /* Return the register class required for a secondary register when
11777 copying between one of the registers in RCLASS and value X, which
11778 has mode MODE. X is the source of the move if IN_P, otherwise it
11779 is the destination. Return NO_REGS if no secondary register is
11783 mips_secondary_reload_class (enum reg_class rclass
,
11784 enum machine_mode mode
, rtx x
, bool in_p
)
11788 /* If X is a constant that cannot be loaded into $25, it must be loaded
11789 into some other GPR. No other register class allows a direct move. */
11790 if (mips_dangerous_for_la25_p (x
))
11791 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
11793 regno
= true_regnum (x
);
11796 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11797 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
11803 /* Copying from accumulator registers to anywhere other than a general
11804 register requires a temporary general register. */
11805 if (reg_class_subset_p (rclass
, ACC_REGS
))
11806 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11807 if (ACC_REG_P (regno
))
11808 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11810 /* We can only copy a value to a condition code register from a
11811 floating-point register, and even then we require a scratch
11812 floating-point register. We can only copy a value out of a
11813 condition-code register into a general register. */
11814 if (reg_class_subset_p (rclass
, ST_REGS
))
11818 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11820 if (ST_REG_P (regno
))
11824 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11827 if (reg_class_subset_p (rclass
, FP_REGS
))
11830 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
11831 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11832 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11835 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
11836 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11839 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
11840 /* We can force the constant to memory and use lwc1
11841 and ldc1. As above, we will use pairs of lwc1s if
11842 ldc1 is not supported. */
11845 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
11846 /* In this case we can use mov.fmt. */
11849 /* Otherwise, we need to reload through an integer register. */
11852 if (FP_REG_P (regno
))
11853 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11858 /* Implement TARGET_MODE_REP_EXTENDED. */
11861 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
11863 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11864 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
11865 return SIGN_EXTEND
;
11870 /* Implement TARGET_VALID_POINTER_MODE. */
11873 mips_valid_pointer_mode (enum machine_mode mode
)
11875 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
11878 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11881 mips_vector_mode_supported_p (enum machine_mode mode
)
11886 return TARGET_PAIRED_SINGLE_FLOAT
;
11901 return TARGET_LOONGSON_VECTORS
;
11908 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11911 mips_scalar_mode_supported_p (enum machine_mode mode
)
11913 if (ALL_FIXED_POINT_MODE_P (mode
)
11914 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
11917 return default_scalar_mode_supported_p (mode
);
11920 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11922 static enum machine_mode
11923 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
11925 if (TARGET_PAIRED_SINGLE_FLOAT
11931 /* Implement TARGET_INIT_LIBFUNCS. */
11934 mips_init_libfuncs (void)
11936 if (TARGET_FIX_VR4120
)
11938 /* Register the special divsi3 and modsi3 functions needed to work
11939 around VR4120 division errata. */
11940 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
11941 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
11944 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
11946 /* Register the MIPS16 -mhard-float stubs. */
11947 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
11948 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
11949 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
11950 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
11952 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
11953 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
11954 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
11955 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
11956 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
11957 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
11958 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
11960 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
11961 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
11962 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
11964 if (TARGET_DOUBLE_FLOAT
)
11966 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
11967 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
11968 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
11969 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
11971 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
11972 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
11973 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
11974 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
11975 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
11976 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
11977 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
11979 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
11980 "__mips16_extendsfdf2");
11981 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
11982 "__mips16_truncdfsf2");
11983 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
11984 "__mips16_fix_truncdfsi");
11985 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
11986 "__mips16_floatsidf");
11987 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
11988 "__mips16_floatunsidf");
11992 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11993 on an external non-MIPS16 routine to implement __sync_synchronize.
11994 Similarly for the rest of the ll/sc libfuncs. */
11997 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
11998 init_sync_libfuncs (UNITS_PER_WORD
);
12002 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12005 mips_process_load_label (rtx target
)
12007 rtx base
, gp
, intop
;
12008 HOST_WIDE_INT offset
;
12010 mips_multi_start ();
12014 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
12015 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12019 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
12020 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
12024 gp
= pic_offset_table_rtx
;
12025 if (mips_cfun_has_cprestore_slot_p ())
12027 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
12028 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12029 if (!SMALL_OPERAND (offset
))
12031 intop
= GEN_INT (CONST_HIGH_PART (offset
));
12032 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
12033 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
12036 offset
= CONST_LOW_PART (offset
);
12038 intop
= GEN_INT (offset
);
12039 if (ISA_HAS_LOAD_DELAY
)
12040 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
12042 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
12044 if (ISA_HAS_LOAD_DELAY
)
12045 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
12047 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
12048 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
12053 /* Return the number of instructions needed to load a label into $AT. */
12055 static unsigned int
12056 mips_load_label_num_insns (void)
12058 if (cfun
->machine
->load_label_num_insns
== 0)
12060 mips_process_load_label (pc_rtx
);
12061 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
12063 return cfun
->machine
->load_label_num_insns
;
12066 /* Emit an asm sequence to start a noat block and load the address
12067 of a label into $1. */
12070 mips_output_load_label (rtx target
)
12072 mips_push_asm_switch (&mips_noat
);
12073 if (TARGET_EXPLICIT_RELOCS
)
12075 mips_process_load_label (target
);
12076 mips_multi_write ();
12080 if (Pmode
== DImode
)
12081 output_asm_insn ("dla\t%@,%0", &target
);
12083 output_asm_insn ("la\t%@,%0", &target
);
12087 /* Return the length of INSN. LENGTH is the initial length computed by
12088 attributes in the machine-description file. */
12091 mips_adjust_insn_length (rtx insn
, int length
)
12093 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12094 of a PIC long-branch sequence. Substitute the correct value. */
12095 if (length
== MAX_PIC_BRANCH_LENGTH
12096 && INSN_CODE (insn
) >= 0
12097 && get_attr_type (insn
) == TYPE_BRANCH
)
12099 /* Add the branch-over instruction and its delay slot, if this
12100 is a conditional branch. */
12101 length
= simplejump_p (insn
) ? 0 : 8;
12103 /* Load the label into $AT and jump to it. Ignore the delay
12104 slot of the jump. */
12105 length
+= 4 * mips_load_label_num_insns() + 4;
12108 /* A unconditional jump has an unfilled delay slot if it is not part
12109 of a sequence. A conditional jump normally has a delay slot, but
12110 does not on MIPS16. */
12111 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
12114 /* See how many nops might be needed to avoid hardware hazards. */
12115 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
12116 switch (get_attr_hazard (insn
))
12130 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
12131 the .md file length attributes are 4-based for both modes.
12132 Adjust the MIPS16 ones here. */
12139 /* Return the assembly code for INSN, which has the operands given by
12140 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12141 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12142 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12143 version of BRANCH_IF_TRUE. */
12146 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
12147 const char *branch_if_true
,
12148 const char *branch_if_false
)
12150 unsigned int length
;
12151 rtx taken
, not_taken
;
12153 gcc_assert (LABEL_P (operands
[0]));
12155 length
= get_attr_length (insn
);
12158 /* Just a simple conditional branch. */
12159 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
12160 return branch_if_true
;
12163 /* Generate a reversed branch around a direct jump. This fallback does
12164 not use branch-likely instructions. */
12165 mips_branch_likely
= false;
12166 not_taken
= gen_label_rtx ();
12167 taken
= operands
[0];
12169 /* Generate the reversed branch to NOT_TAKEN. */
12170 operands
[0] = not_taken
;
12171 output_asm_insn (branch_if_false
, operands
);
12173 /* If INSN has a delay slot, we must provide delay slots for both the
12174 branch to NOT_TAKEN and the conditional jump. We must also ensure
12175 that INSN's delay slot is executed in the appropriate cases. */
12176 if (final_sequence
)
12178 /* This first delay slot will always be executed, so use INSN's
12179 delay slot if is not annulled. */
12180 if (!INSN_ANNULLED_BRANCH_P (insn
))
12182 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12183 asm_out_file
, optimize
, 1, NULL
);
12184 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12187 output_asm_insn ("nop", 0);
12188 fprintf (asm_out_file
, "\n");
12191 /* Output the unconditional branch to TAKEN. */
12192 if (TARGET_ABSOLUTE_JUMPS
)
12193 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
12196 mips_output_load_label (taken
);
12197 output_asm_insn ("jr\t%@%]%/", 0);
12200 /* Now deal with its delay slot; see above. */
12201 if (final_sequence
)
12203 /* This delay slot will only be executed if the branch is taken.
12204 Use INSN's delay slot if is annulled. */
12205 if (INSN_ANNULLED_BRANCH_P (insn
))
12207 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
12208 asm_out_file
, optimize
, 1, NULL
);
12209 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
12212 output_asm_insn ("nop", 0);
12213 fprintf (asm_out_file
, "\n");
12216 /* Output NOT_TAKEN. */
12217 targetm
.asm_out
.internal_label (asm_out_file
, "L",
12218 CODE_LABEL_NUMBER (not_taken
));
12222 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12223 if some ordering condition is true. The condition is given by
12224 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12225 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12226 its second is always zero. */
12229 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
12231 const char *branch
[2];
12233 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12234 Make BRANCH[0] branch on the inverse condition. */
12235 switch (GET_CODE (operands
[1]))
12237 /* These cases are equivalent to comparisons against zero. */
12239 inverted_p
= !inverted_p
;
12240 /* Fall through. */
12242 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
12243 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
12246 /* These cases are always true or always false. */
12248 inverted_p
= !inverted_p
;
12249 /* Fall through. */
12251 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
12252 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
12256 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
12257 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
12260 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
12263 /* Start a block of code that needs access to the LL, SC and SYNC
12267 mips_start_ll_sc_sync_block (void)
12269 if (!ISA_HAS_LL_SC
)
12271 output_asm_insn (".set\tpush", 0);
12272 output_asm_insn (".set\tmips2", 0);
12276 /* End a block started by mips_start_ll_sc_sync_block. */
12279 mips_end_ll_sc_sync_block (void)
12281 if (!ISA_HAS_LL_SC
)
12282 output_asm_insn (".set\tpop", 0);
12285 /* Output and/or return the asm template for a sync instruction. */
12288 mips_output_sync (void)
12290 mips_start_ll_sc_sync_block ();
12291 output_asm_insn ("sync", 0);
12292 mips_end_ll_sc_sync_block ();
12296 /* Return the asm template associated with sync_insn1 value TYPE.
12297 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12299 static const char *
12300 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
12304 case SYNC_INSN1_MOVE
:
12305 return "move\t%0,%z2";
12306 case SYNC_INSN1_LI
:
12307 return "li\t%0,%2";
12308 case SYNC_INSN1_ADDU
:
12309 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12310 case SYNC_INSN1_ADDIU
:
12311 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12312 case SYNC_INSN1_SUBU
:
12313 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12314 case SYNC_INSN1_AND
:
12315 return "and\t%0,%1,%z2";
12316 case SYNC_INSN1_ANDI
:
12317 return "andi\t%0,%1,%2";
12318 case SYNC_INSN1_OR
:
12319 return "or\t%0,%1,%z2";
12320 case SYNC_INSN1_ORI
:
12321 return "ori\t%0,%1,%2";
12322 case SYNC_INSN1_XOR
:
12323 return "xor\t%0,%1,%z2";
12324 case SYNC_INSN1_XORI
:
12325 return "xori\t%0,%1,%2";
12327 gcc_unreachable ();
12330 /* Return the asm template associated with sync_insn2 value TYPE. */
12332 static const char *
12333 mips_sync_insn2_template (enum attr_sync_insn2 type
)
12337 case SYNC_INSN2_NOP
:
12338 gcc_unreachable ();
12339 case SYNC_INSN2_AND
:
12340 return "and\t%0,%1,%z2";
12341 case SYNC_INSN2_XOR
:
12342 return "xor\t%0,%1,%z2";
12343 case SYNC_INSN2_NOT
:
12344 return "nor\t%0,%1,%.";
12346 gcc_unreachable ();
12349 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12350 the value of the one of the sync_* attributes. Return the operand
12351 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12352 have the associated attribute. */
12355 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
12358 default_value
= operands
[index
- 1];
12359 return default_value
;
12362 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12363 sequence for it. */
12366 mips_process_sync_loop (rtx insn
, rtx
*operands
)
12368 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
12369 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
12370 unsigned int tmp3_insn
;
12371 enum attr_sync_insn1 insn1
;
12372 enum attr_sync_insn2 insn2
;
12375 enum memmodel model
;
12377 /* Read an operand from the sync_WHAT attribute and store it in
12378 variable WHAT. DEFAULT is the default value if no attribute
12380 #define READ_OPERAND(WHAT, DEFAULT) \
12381 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12384 /* Read the memory. */
12385 READ_OPERAND (mem
, 0);
12387 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
12389 /* Read the other attributes. */
12390 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
12391 READ_OPERAND (oldval
, at
);
12392 READ_OPERAND (cmp
, 0);
12393 READ_OPERAND (newval
, at
);
12394 READ_OPERAND (inclusive_mask
, 0);
12395 READ_OPERAND (exclusive_mask
, 0);
12396 READ_OPERAND (required_oldval
, 0);
12397 READ_OPERAND (insn1_op2
, 0);
12398 insn1
= get_attr_sync_insn1 (insn
);
12399 insn2
= get_attr_sync_insn2 (insn
);
12401 /* Don't bother setting CMP result that is never used. */
12402 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
12405 memmodel_attr
= get_attr_sync_memmodel (insn
);
12406 switch (memmodel_attr
)
12409 model
= MEMMODEL_ACQ_REL
;
12412 model
= MEMMODEL_ACQUIRE
;
12415 model
= (enum memmodel
) INTVAL (operands
[memmodel_attr
]);
12418 mips_multi_start ();
12420 /* Output the release side of the memory barrier. */
12421 if (need_atomic_barrier_p (model
, true))
12423 if (required_oldval
== 0 && TARGET_OCTEON
)
12425 /* Octeon doesn't reorder reads, so a full barrier can be
12426 created by using SYNCW to order writes combined with the
12427 write from the following SC. When the SC successfully
12428 completes, we know that all preceding writes are also
12429 committed to the coherent memory system. It is possible
12430 for a single SYNCW to fail, but a pair of them will never
12431 fail, so we use two. */
12432 mips_multi_add_insn ("syncw", NULL
);
12433 mips_multi_add_insn ("syncw", NULL
);
12436 mips_multi_add_insn ("sync", NULL
);
12439 /* Output the branch-back label. */
12440 mips_multi_add_label ("1:");
12442 /* OLDVAL = *MEM. */
12443 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
12444 oldval
, mem
, NULL
);
12446 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12447 if (required_oldval
)
12449 if (inclusive_mask
== 0)
12453 gcc_assert (oldval
!= at
);
12454 mips_multi_add_insn ("and\t%0,%1,%2",
12455 at
, oldval
, inclusive_mask
, NULL
);
12458 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
12460 /* CMP = 0 [delay slot]. */
12462 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
12465 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12466 if (exclusive_mask
== 0)
12470 gcc_assert (oldval
!= at
);
12471 mips_multi_add_insn ("and\t%0,%1,%z2",
12472 at
, oldval
, exclusive_mask
, NULL
);
12476 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12478 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12479 at least one instruction in that case. */
12480 if (insn1
== SYNC_INSN1_MOVE
12481 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
12485 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
12486 newval
, oldval
, insn1_op2
, NULL
);
12490 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12491 if (insn2
== SYNC_INSN2_NOP
)
12495 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
12496 newval
, tmp2
, inclusive_mask
, NULL
);
12499 tmp3_insn
= mips_multi_last_index ();
12501 /* $AT = $TMP1 | $TMP3. */
12502 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
12504 mips_multi_set_operand (tmp3_insn
, 0, at
);
12509 gcc_assert (tmp1
!= tmp3
);
12510 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
12513 /* if (!commit (*MEM = $AT)) goto 1.
12515 This will sometimes be a delayed branch; see the write code below
12517 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
12518 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
12520 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12521 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
12523 mips_multi_copy_insn (tmp3_insn
);
12524 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
12526 else if (!(required_oldval
&& cmp
))
12527 mips_multi_add_insn ("nop", NULL
);
12529 /* CMP = 1 -- either standalone or in a delay slot. */
12530 if (required_oldval
&& cmp
)
12531 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
12533 /* Output the acquire side of the memory barrier. */
12534 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
12535 mips_multi_add_insn ("sync", NULL
);
12537 /* Output the exit label, if needed. */
12538 if (required_oldval
)
12539 mips_multi_add_label ("2:");
12541 #undef READ_OPERAND
12544 /* Output and/or return the asm template for sync loop INSN, which has
12545 the operands given by OPERANDS. */
12548 mips_output_sync_loop (rtx insn
, rtx
*operands
)
12550 mips_process_sync_loop (insn
, operands
);
12552 /* Use branch-likely instructions to work around the LL/SC R10000
12554 mips_branch_likely
= TARGET_FIX_R10000
;
12556 mips_push_asm_switch (&mips_noreorder
);
12557 mips_push_asm_switch (&mips_nomacro
);
12558 mips_push_asm_switch (&mips_noat
);
12559 mips_start_ll_sc_sync_block ();
12561 mips_multi_write ();
12563 mips_end_ll_sc_sync_block ();
12564 mips_pop_asm_switch (&mips_noat
);
12565 mips_pop_asm_switch (&mips_nomacro
);
12566 mips_pop_asm_switch (&mips_noreorder
);
12571 /* Return the number of individual instructions in sync loop INSN,
12572 which has the operands given by OPERANDS. */
12575 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
12577 mips_process_sync_loop (insn
, operands
);
12578 return mips_multi_num_insns
;
12581 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12582 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12584 When working around R4000 and R4400 errata, we need to make sure that
12585 the division is not immediately followed by a shift[1][2]. We also
12586 need to stop the division from being put into a branch delay slot[3].
12587 The easiest way to avoid both problems is to add a nop after the
12588 division. When a divide-by-zero check is needed, this nop can be
12589 used to fill the branch delay slot.
12591 [1] If a double-word or a variable shift executes immediately
12592 after starting an integer division, the shift may give an
12593 incorrect result. See quotations of errata #16 and #28 from
12594 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12595 in mips.md for details.
12597 [2] A similar bug to [1] exists for all revisions of the
12598 R4000 and the R4400 when run in an MC configuration.
12599 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12601 "19. In this following sequence:
12603 ddiv (or ddivu or div or divu)
12604 dsll32 (or dsrl32, dsra32)
12606 if an MPT stall occurs, while the divide is slipping the cpu
12607 pipeline, then the following double shift would end up with an
12610 Workaround: The compiler needs to avoid generating any
12611 sequence with divide followed by extended double shift."
12613 This erratum is also present in "MIPS R4400MC Errata, Processor
12614 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12615 & 3.0" as errata #10 and #4, respectively.
12617 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12618 (also valid for MIPS R4000MC processors):
12620 "52. R4000SC: This bug does not apply for the R4000PC.
12622 There are two flavors of this bug:
12624 1) If the instruction just after divide takes an RF exception
12625 (tlb-refill, tlb-invalid) and gets an instruction cache
12626 miss (both primary and secondary) and the line which is
12627 currently in secondary cache at this index had the first
12628 data word, where the bits 5..2 are set, then R4000 would
12629 get a wrong result for the div.
12634 ------------------- # end-of page. -tlb-refill
12639 ------------------- # end-of page. -tlb-invalid
12642 2) If the divide is in the taken branch delay slot, where the
12643 target takes RF exception and gets an I-cache miss for the
12644 exception vector or where I-cache miss occurs for the
12645 target address, under the above mentioned scenarios, the
12646 div would get wrong results.
12649 j r2 # to next page mapped or unmapped
12650 div r8,r9 # this bug would be there as long
12651 # as there is an ICache miss and
12652 nop # the "data pattern" is present
12655 beq r0, r0, NextPage # to Next page
12659 This bug is present for div, divu, ddiv, and ddivu
12662 Workaround: For item 1), OS could make sure that the next page
12663 after the divide instruction is also mapped. For item 2), the
12664 compiler could make sure that the divide instruction is not in
12665 the branch delay slot."
12667 These processors have PRId values of 0x00004220 and 0x00004300 for
12668 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12671 mips_output_division (const char *division
, rtx
*operands
)
12676 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
12678 output_asm_insn (s
, operands
);
12681 if (TARGET_CHECK_ZERO_DIV
)
12685 output_asm_insn (s
, operands
);
12686 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
12688 else if (GENERATE_DIVIDE_TRAPS
)
12690 /* Avoid long replay penalty on load miss by putting the trap before
12693 output_asm_insn ("teq\t%2,%.,7", operands
);
12696 output_asm_insn (s
, operands
);
12697 s
= "teq\t%2,%.,7";
12702 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
12703 output_asm_insn (s
, operands
);
12704 s
= "break\t7%)\n1:";
12710 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12711 instruction and if OUT_INSN assigns to the accumulator operand. */
12714 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
12716 enum attr_accum_in accum_in
;
12717 int accum_in_opnum
;
12720 if (recog_memoized (in_insn
) < 0)
12723 accum_in
= get_attr_accum_in (in_insn
);
12724 if (accum_in
== ACCUM_IN_NONE
)
12727 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
12729 extract_insn (in_insn
);
12730 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
12731 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
12733 return reg_set_p (accum_in_op
, out_insn
);
12736 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12737 data rather than the address. We need this because the cprestore
12738 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12739 which causes the default routine to abort. We just return false
12743 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
12745 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
12748 return !store_data_bypass_p (out_insn
, in_insn
);
12752 /* Variables and flags used in scheduler hooks when tuning for
12756 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12759 /* If true, then next ALU1/2 instruction will go to ALU1. */
12762 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12765 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12766 int alu1_core_unit_code
;
12767 int alu2_core_unit_code
;
12768 int falu1_core_unit_code
;
12769 int falu2_core_unit_code
;
12771 /* True if current cycle has a multi instruction.
12772 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12773 bool cycle_has_multi_p
;
12775 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12776 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12778 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12779 instruction to go ALU1. */
12780 rtx alu1_turn_enabled_insn
;
12781 rtx alu2_turn_enabled_insn
;
12782 rtx falu1_turn_enabled_insn
;
12783 rtx falu2_turn_enabled_insn
;
12786 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12787 dependencies have no cost, except on the 20Kc where output-dependence
12788 is treated like input-dependence. */
12791 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
12792 rtx dep ATTRIBUTE_UNUSED
, int cost
)
12794 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
12797 if (REG_NOTE_KIND (link
) != 0)
12802 /* Return the number of instructions that can be issued per cycle. */
12805 mips_issue_rate (void)
12809 case PROCESSOR_74KC
:
12810 case PROCESSOR_74KF2_1
:
12811 case PROCESSOR_74KF1_1
:
12812 case PROCESSOR_74KF3_2
:
12813 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12814 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12815 but in reality only a maximum of 3 insns can be issued as
12816 floating-point loads and stores also require a slot in the
12818 case PROCESSOR_R10000
:
12819 /* All R10K Processors are quad-issue (being the first MIPS
12820 processors to support this feature). */
12823 case PROCESSOR_20KC
:
12824 case PROCESSOR_R4130
:
12825 case PROCESSOR_R5400
:
12826 case PROCESSOR_R5500
:
12827 case PROCESSOR_R7000
:
12828 case PROCESSOR_R9000
:
12829 case PROCESSOR_OCTEON
:
12830 case PROCESSOR_OCTEON2
:
12833 case PROCESSOR_SB1
:
12834 case PROCESSOR_SB1A
:
12835 /* This is actually 4, but we get better performance if we claim 3.
12836 This is partly because of unwanted speculative code motion with the
12837 larger number, and partly because in most common cases we can't
12838 reach the theoretical max of 4. */
12841 case PROCESSOR_LOONGSON_2E
:
12842 case PROCESSOR_LOONGSON_2F
:
12843 case PROCESSOR_LOONGSON_3A
:
12846 case PROCESSOR_XLP
:
12847 return (reload_completed
? 4 : 3);
12854 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12857 mips_ls2_init_dfa_post_cycle_insn (void)
12860 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12861 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
12865 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12866 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
12870 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12871 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
12875 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12876 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
12879 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
12880 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
12881 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
12882 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
12885 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12886 Init data used in mips_dfa_post_advance_cycle. */
12889 mips_init_dfa_post_cycle_insn (void)
12891 if (TUNE_LOONGSON_2EF
)
12892 mips_ls2_init_dfa_post_cycle_insn ();
12895 /* Initialize STATE when scheduling for Loongson 2E/2F.
12896 Support round-robin dispatch scheme by enabling only one of
12897 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12901 mips_ls2_dfa_post_advance_cycle (state_t state
)
12903 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
12905 /* Though there are no non-pipelined ALU1 insns,
12906 we can get an instruction of type 'multi' before reload. */
12907 gcc_assert (mips_ls2
.cycle_has_multi_p
);
12908 mips_ls2
.alu1_turn_p
= false;
12911 mips_ls2
.cycle_has_multi_p
= false;
12913 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
12914 /* We have a non-pipelined alu instruction in the core,
12915 adjust round-robin counter. */
12916 mips_ls2
.alu1_turn_p
= true;
12918 if (mips_ls2
.alu1_turn_p
)
12920 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
12921 gcc_unreachable ();
12925 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
12926 gcc_unreachable ();
12929 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
12931 /* There are no non-pipelined FALU1 insns. */
12932 gcc_unreachable ();
12933 mips_ls2
.falu1_turn_p
= false;
12936 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
12937 /* We have a non-pipelined falu instruction in the core,
12938 adjust round-robin counter. */
12939 mips_ls2
.falu1_turn_p
= true;
12941 if (mips_ls2
.falu1_turn_p
)
12943 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
12944 gcc_unreachable ();
12948 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
12949 gcc_unreachable ();
12953 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12954 This hook is being called at the start of each cycle. */
12957 mips_dfa_post_advance_cycle (void)
12959 if (TUNE_LOONGSON_2EF
)
12960 mips_ls2_dfa_post_advance_cycle (curr_state
);
12963 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12964 be as wide as the scheduling freedom in the DFA. */
12967 mips_multipass_dfa_lookahead (void)
12969 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12973 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
12982 /* Remove the instruction at index LOWER from ready queue READY and
12983 reinsert it in front of the instruction at index HIGHER. LOWER must
12987 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
12992 new_head
= ready
[lower
];
12993 for (i
= lower
; i
< higher
; i
++)
12994 ready
[i
] = ready
[i
+ 1];
12995 ready
[i
] = new_head
;
12998 /* If the priority of the instruction at POS2 in the ready queue READY
12999 is within LIMIT units of that of the instruction at POS1, swap the
13000 instructions if POS2 is not already less than POS1. */
13003 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
13006 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
13010 temp
= ready
[pos1
];
13011 ready
[pos1
] = ready
[pos2
];
13012 ready
[pos2
] = temp
;
13016 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13017 that may clobber hi or lo. */
13018 static rtx mips_macc_chains_last_hilo
;
13020 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13021 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13024 mips_macc_chains_record (rtx insn
)
13026 if (get_attr_may_clobber_hilo (insn
))
13027 mips_macc_chains_last_hilo
= insn
;
13030 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13031 has NREADY elements, looking for a multiply-add or multiply-subtract
13032 instruction that is cumulative with mips_macc_chains_last_hilo.
13033 If there is one, promote it ahead of anything else that might
13034 clobber hi or lo. */
13037 mips_macc_chains_reorder (rtx
*ready
, int nready
)
13041 if (mips_macc_chains_last_hilo
!= 0)
13042 for (i
= nready
- 1; i
>= 0; i
--)
13043 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
13045 for (j
= nready
- 1; j
> i
; j
--)
13046 if (recog_memoized (ready
[j
]) >= 0
13047 && get_attr_may_clobber_hilo (ready
[j
]))
13049 mips_promote_ready (ready
, i
, j
);
13056 /* The last instruction to be scheduled. */
13057 static rtx vr4130_last_insn
;
13059 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13060 points to an rtx that is initially an instruction. Nullify the rtx
13061 if the instruction uses the value of register X. */
13064 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13069 insn_ptr
= (rtx
*) data
;
13072 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
13076 /* Return true if there is true register dependence between vr4130_last_insn
13080 vr4130_true_reg_dependence_p (rtx insn
)
13082 note_stores (PATTERN (vr4130_last_insn
),
13083 vr4130_true_reg_dependence_p_1
, &insn
);
13087 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13088 the ready queue and that INSN2 is the instruction after it, return
13089 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13090 in which INSN1 and INSN2 can probably issue in parallel, but for
13091 which (INSN2, INSN1) should be less sensitive to instruction
13092 alignment than (INSN1, INSN2). See 4130.md for more details. */
13095 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
13097 sd_iterator_def sd_it
;
13100 /* Check for the following case:
13102 1) there is some other instruction X with an anti dependence on INSN1;
13103 2) X has a higher priority than INSN2; and
13104 3) X is an arithmetic instruction (and thus has no unit restrictions).
13106 If INSN1 is the last instruction blocking X, it would better to
13107 choose (INSN1, X) over (INSN2, INSN1). */
13108 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
13109 if (DEP_TYPE (dep
) == REG_DEP_ANTI
13110 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
13111 && recog_memoized (DEP_CON (dep
)) >= 0
13112 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
13115 if (vr4130_last_insn
!= 0
13116 && recog_memoized (insn1
) >= 0
13117 && recog_memoized (insn2
) >= 0)
13119 /* See whether INSN1 and INSN2 use different execution units,
13120 or if they are both ALU-type instructions. If so, they can
13121 probably execute in parallel. */
13122 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
13123 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
13124 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
13126 /* If only one of the instructions has a dependence on
13127 vr4130_last_insn, prefer to schedule the other one first. */
13128 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
13129 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
13130 if (dep1_p
!= dep2_p
)
13133 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13134 is not an ALU-type instruction and if INSN1 uses the same
13135 execution unit. (Note that if this condition holds, we already
13136 know that INSN2 uses a different execution unit.) */
13137 if (class1
!= VR4130_CLASS_ALU
13138 && recog_memoized (vr4130_last_insn
) >= 0
13139 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
13146 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13147 queue with at least two instructions. Swap the first two if
13148 vr4130_swap_insns_p says that it could be worthwhile. */
13151 vr4130_reorder (rtx
*ready
, int nready
)
13153 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
13154 mips_promote_ready (ready
, nready
- 2, nready
- 1);
13157 /* Record whether last 74k AGEN instruction was a load or store. */
13158 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13160 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13161 resets to TYPE_UNKNOWN state. */
13164 mips_74k_agen_init (rtx insn
)
13166 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
13167 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
13170 enum attr_type type
= get_attr_type (insn
);
13171 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
13172 mips_last_74k_agen_insn
= type
;
13176 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13177 loads to be grouped together, and multiple stores to be grouped
13178 together. Swap things around in the ready queue to make this happen. */
13181 mips_74k_agen_reorder (rtx
*ready
, int nready
)
13184 int store_pos
, load_pos
;
13189 for (i
= nready
- 1; i
>= 0; i
--)
13191 rtx insn
= ready
[i
];
13192 if (USEFUL_INSN_P (insn
))
13193 switch (get_attr_type (insn
))
13196 if (store_pos
== -1)
13201 if (load_pos
== -1)
13210 if (load_pos
== -1 || store_pos
== -1)
13213 switch (mips_last_74k_agen_insn
)
13216 /* Prefer to schedule loads since they have a higher latency. */
13218 /* Swap loads to the front of the queue. */
13219 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
13222 /* Swap stores to the front of the queue. */
13223 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
13230 /* Implement TARGET_SCHED_INIT. */
13233 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13234 int max_ready ATTRIBUTE_UNUSED
)
13236 mips_macc_chains_last_hilo
= 0;
13237 vr4130_last_insn
= 0;
13238 mips_74k_agen_init (NULL_RTX
);
13240 /* When scheduling for Loongson2, branch instructions go to ALU1,
13241 therefore basic block is most likely to start with round-robin counter
13242 pointed to ALU2. */
13243 mips_ls2
.alu1_turn_p
= false;
13244 mips_ls2
.falu1_turn_p
= true;
13247 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13250 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13251 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13253 if (!reload_completed
13254 && TUNE_MACC_CHAINS
13256 mips_macc_chains_reorder (ready
, *nreadyp
);
13258 if (reload_completed
13260 && !TARGET_VR4130_ALIGN
13262 vr4130_reorder (ready
, *nreadyp
);
13265 mips_74k_agen_reorder (ready
, *nreadyp
);
13268 /* Implement TARGET_SCHED_REORDER. */
13271 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13272 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13274 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13275 return mips_issue_rate ();
13278 /* Implement TARGET_SCHED_REORDER2. */
13281 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13282 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
13284 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
13285 return cached_can_issue_more
;
13288 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13291 mips_ls2_variable_issue (rtx insn
)
13293 if (mips_ls2
.alu1_turn_p
)
13295 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
13296 mips_ls2
.alu1_turn_p
= false;
13300 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
13301 mips_ls2
.alu1_turn_p
= true;
13304 if (mips_ls2
.falu1_turn_p
)
13306 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
13307 mips_ls2
.falu1_turn_p
= false;
13311 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
13312 mips_ls2
.falu1_turn_p
= true;
13315 if (recog_memoized (insn
) >= 0)
13316 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
13319 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13322 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
13323 rtx insn
, int more
)
13325 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13326 if (USEFUL_INSN_P (insn
))
13328 if (get_attr_type (insn
) != TYPE_GHOST
)
13330 if (!reload_completed
&& TUNE_MACC_CHAINS
)
13331 mips_macc_chains_record (insn
);
13332 vr4130_last_insn
= insn
;
13334 mips_74k_agen_init (insn
);
13335 else if (TUNE_LOONGSON_2EF
)
13336 mips_ls2_variable_issue (insn
);
13339 /* Instructions of type 'multi' should all be split before
13340 the second scheduling pass. */
13341 gcc_assert (!reload_completed
13342 || recog_memoized (insn
) < 0
13343 || get_attr_type (insn
) != TYPE_MULTI
);
13345 cached_can_issue_more
= more
;
13349 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13350 return the first operand of the associated PREF or PREFX insn. */
13353 mips_prefetch_cookie (rtx write
, rtx locality
)
13355 /* store_streamed / load_streamed. */
13356 if (INTVAL (locality
) <= 0)
13357 return GEN_INT (INTVAL (write
) + 4);
13359 /* store / load. */
13360 if (INTVAL (locality
) <= 2)
13363 /* store_retained / load_retained. */
13364 return GEN_INT (INTVAL (write
) + 6);
13367 /* Flags that indicate when a built-in function is available.
13369 BUILTIN_AVAIL_NON_MIPS16
13370 The function is available on the current target, but only
13371 in non-MIPS16 mode. */
13372 #define BUILTIN_AVAIL_NON_MIPS16 1
13374 /* Declare an availability predicate for built-in functions that
13375 require non-MIPS16 mode and also require COND to be true.
13376 NAME is the main part of the predicate's name. */
13377 #define AVAIL_NON_MIPS16(NAME, COND) \
13378 static unsigned int \
13379 mips_builtin_avail_##NAME (void) \
13381 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13384 /* This structure describes a single built-in function. */
13385 struct mips_builtin_description
{
13386 /* The code of the main .md file instruction. See mips_builtin_type
13387 for more information. */
13388 enum insn_code icode
;
13390 /* The floating-point comparison code to use with ICODE, if any. */
13391 enum mips_fp_condition cond
;
13393 /* The name of the built-in function. */
13396 /* Specifies how the function should be expanded. */
13397 enum mips_builtin_type builtin_type
;
13399 /* The function's prototype. */
13400 enum mips_function_type function_type
;
13402 /* Whether the function is available. */
13403 unsigned int (*avail
) (void);
13406 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
13407 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
13408 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
13409 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
13410 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
13411 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
13412 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
13413 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
13414 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
13415 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
13417 /* Construct a mips_builtin_description from the given arguments.
13419 INSN is the name of the associated instruction pattern, without the
13420 leading CODE_FOR_mips_.
13422 CODE is the floating-point condition code associated with the
13423 function. It can be 'f' if the field is not applicable.
13425 NAME is the name of the function itself, without the leading
13428 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13430 AVAIL is the name of the availability predicate, without the leading
13431 mips_builtin_avail_. */
13432 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13433 FUNCTION_TYPE, AVAIL) \
13434 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13435 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13436 mips_builtin_avail_ ## AVAIL }
13438 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13439 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13440 are as for MIPS_BUILTIN. */
13441 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13442 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13444 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13445 are subject to mips_builtin_avail_<AVAIL>. */
13446 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13447 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13448 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13449 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13450 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13452 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13453 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13454 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13455 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13456 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13457 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13459 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13460 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13462 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13463 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13465 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13466 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13469 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13470 are subject to mips_builtin_avail_mips3d. */
13471 #define CMP_4S_BUILTINS(INSN, COND) \
13472 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13473 MIPS_BUILTIN_CMP_ANY, \
13474 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13475 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13476 MIPS_BUILTIN_CMP_ALL, \
13477 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13479 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13480 instruction requires mips_builtin_avail_<AVAIL>. */
13481 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13482 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13483 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13485 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13486 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13489 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13490 #define CMP_BUILTINS(COND) \
13491 MOVTF_BUILTINS (c, COND, paired_single), \
13492 MOVTF_BUILTINS (cabs, COND, mips3d), \
13493 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13494 CMP_PS_BUILTINS (c, COND, paired_single), \
13495 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13496 CMP_4S_BUILTINS (c, COND), \
13497 CMP_4S_BUILTINS (cabs, COND)
13499 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13500 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13501 and AVAIL are as for MIPS_BUILTIN. */
13502 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13503 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13504 FUNCTION_TYPE, AVAIL)
13506 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13507 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13508 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13509 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13510 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13512 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13513 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13514 builtin_description field. */
13515 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13516 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13517 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13518 FUNCTION_TYPE, mips_builtin_avail_loongson }
13520 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13521 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13522 builtin_description field. */
13523 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13524 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13526 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13527 We use functions of this form when the same insn can be usefully applied
13528 to more than one datatype. */
13529 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13530 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13532 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13533 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13534 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13535 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13536 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13537 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13538 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13539 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13541 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13542 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13543 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13544 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13545 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13546 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13547 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13548 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13549 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13550 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13551 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13552 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13553 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13554 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13555 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13556 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13557 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13558 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13559 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13560 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13561 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13562 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13563 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13564 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13565 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13566 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13567 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13568 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13569 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13570 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13572 static const struct mips_builtin_description mips_builtins
[] = {
13573 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13574 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13575 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13576 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
13577 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
13578 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13579 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
13580 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
13582 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
13583 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13584 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13585 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13586 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13588 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13589 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13590 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13591 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13592 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13593 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13595 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
13596 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
13597 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
13598 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
13599 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
13600 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
13602 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
13604 /* Built-in functions for the SB-1 processor. */
13605 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
13607 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13608 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13609 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13610 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13611 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13612 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13613 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13614 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13615 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13616 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13617 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13618 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13619 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13620 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13621 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
13622 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
13623 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
13624 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13625 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13626 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
13627 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
13628 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
13629 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
13630 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13631 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13632 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13633 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13634 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13635 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13636 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13637 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
13638 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13639 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13640 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13641 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13642 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
13643 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13644 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
13645 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13646 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13647 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
13648 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13649 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13650 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
13651 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
13652 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
13653 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
13654 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
13655 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13656 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13657 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
13658 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13659 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13660 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
13661 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13662 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13663 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
13664 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
13665 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13666 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
13667 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
13668 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
13669 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13670 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13671 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
13672 BPOSGE_BUILTIN (32, dsp
),
13674 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13675 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
13676 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13677 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13678 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13679 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13680 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13681 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13682 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13683 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13684 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
13685 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13686 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13687 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13688 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13689 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13690 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
13691 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13692 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
13693 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
13694 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13695 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
13696 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
13697 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13698 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13699 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13700 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
13701 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13702 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13703 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13704 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13705 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13706 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
13707 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13708 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
13710 /* Built-in functions for the DSP ASE (32-bit only). */
13711 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13712 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13713 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13714 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
13715 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13716 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13717 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13718 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13719 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13720 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13721 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13722 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13723 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
13724 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13725 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13726 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13727 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13728 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13729 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
13730 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13731 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
13732 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13733 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13734 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
13735 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
13736 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
13737 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
13739 /* Built-in functions for the DSP ASE (64-bit only). */
13740 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
13742 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13743 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13744 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13745 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13746 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13747 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13748 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13749 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13750 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13751 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
13753 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13754 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
13755 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
13756 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
13757 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13758 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13759 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13760 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13761 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13762 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13763 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13764 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
13765 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13766 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13767 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13768 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13769 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
13770 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13771 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13772 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13773 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
13774 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13775 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13776 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13777 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13778 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13779 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13780 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13781 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13782 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13783 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13784 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13785 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13786 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13787 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13788 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13789 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13790 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13791 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
13792 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
13793 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13794 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13795 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13796 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13797 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13798 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13799 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13800 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13801 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
13802 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13803 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13804 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13805 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13806 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
13807 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
13808 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13809 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13810 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13811 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
13812 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13813 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
13814 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
13815 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13816 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13817 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13818 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13819 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13820 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13821 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13822 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13823 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13824 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13825 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13826 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13827 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13828 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13829 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13830 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13831 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13832 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13833 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13834 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13835 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13836 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
13837 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13838 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13839 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13840 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13841 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13842 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13843 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13844 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13845 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13846 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13847 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13848 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13849 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13850 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13851 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13852 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13854 /* Sundry other built-in functions. */
13855 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
13858 /* Index I is the function declaration for mips_builtins[I], or null if the
13859 function isn't defined on this target. */
13860 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
13862 /* MODE is a vector mode whose elements have type TYPE. Return the type
13863 of the vector itself. */
13866 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
13868 static tree types
[2 * (int) MAX_MACHINE_MODE
];
13871 mode_index
= (int) mode
;
13873 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
13874 mode_index
+= MAX_MACHINE_MODE
;
13876 if (types
[mode_index
] == NULL_TREE
)
13877 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
13878 return types
[mode_index
];
13881 /* Return a type for 'const volatile void *'. */
13884 mips_build_cvpointer_type (void)
13888 if (cache
== NULL_TREE
)
13889 cache
= build_pointer_type (build_qualified_type
13891 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
13895 /* Source-level argument types. */
13896 #define MIPS_ATYPE_VOID void_type_node
13897 #define MIPS_ATYPE_INT integer_type_node
13898 #define MIPS_ATYPE_POINTER ptr_type_node
13899 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13901 /* Standard mode-based argument types. */
13902 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13903 #define MIPS_ATYPE_SI intSI_type_node
13904 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13905 #define MIPS_ATYPE_DI intDI_type_node
13906 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13907 #define MIPS_ATYPE_SF float_type_node
13908 #define MIPS_ATYPE_DF double_type_node
13910 /* Vector argument types. */
13911 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13912 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13913 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13914 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13915 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13916 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13917 #define MIPS_ATYPE_UV2SI \
13918 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13919 #define MIPS_ATYPE_UV4HI \
13920 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13921 #define MIPS_ATYPE_UV8QI \
13922 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13924 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13925 their associated MIPS_ATYPEs. */
13926 #define MIPS_FTYPE_ATYPES1(A, B) \
13927 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13929 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13930 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13932 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13933 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13935 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13936 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13939 /* Return the function type associated with function prototype TYPE. */
13942 mips_build_function_type (enum mips_function_type type
)
13944 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
13946 if (types
[(int) type
] == NULL_TREE
)
13949 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13950 case MIPS_FTYPE_NAME##NUM ARGS: \
13951 types[(int) type] \
13952 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13955 #include "config/mips/mips-ftypes.def"
13956 #undef DEF_MIPS_FTYPE
13958 gcc_unreachable ();
13961 return types
[(int) type
];
13964 /* Implement TARGET_INIT_BUILTINS. */
13967 mips_init_builtins (void)
13969 const struct mips_builtin_description
*d
;
13972 /* Iterate through all of the bdesc arrays, initializing all of the
13973 builtin functions. */
13974 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
13976 d
= &mips_builtins
[i
];
13978 mips_builtin_decls
[i
]
13979 = add_builtin_function (d
->name
,
13980 mips_build_function_type (d
->function_type
),
13981 i
, BUILT_IN_MD
, NULL
, NULL
);
13985 /* Implement TARGET_BUILTIN_DECL. */
13988 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
13990 if (code
>= ARRAY_SIZE (mips_builtins
))
13991 return error_mark_node
;
13992 return mips_builtin_decls
[code
];
13995 /* Take argument ARGNO from EXP's argument list and convert it into
13996 an expand operand. Store the operand in *OP. */
13999 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
14000 unsigned int argno
)
14005 arg
= CALL_EXPR_ARG (exp
, argno
);
14006 value
= expand_normal (arg
);
14007 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
14010 /* Expand instruction ICODE as part of a built-in function sequence.
14011 Use the first NOPS elements of OPS as the instruction's operands.
14012 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14013 instruction has no target.
14015 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14018 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
14019 struct expand_operand
*ops
, bool has_target_p
)
14021 if (!maybe_expand_insn (icode
, nops
, ops
))
14023 error ("invalid argument to built-in function");
14024 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
14026 return has_target_p
? ops
[0].value
: const0_rtx
;
14029 /* Expand a floating-point comparison for built-in function call EXP.
14030 The first NARGS arguments are the values to be compared. ICODE is
14031 the .md pattern that does the comparison and COND is the condition
14032 that is being tested. Return an rtx for the result. */
14035 mips_expand_builtin_compare_1 (enum insn_code icode
,
14036 enum mips_fp_condition cond
,
14037 tree exp
, int nargs
)
14039 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14043 /* The instruction should have a target operand, an operand for each
14044 argument, and an operand for COND. */
14045 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
14047 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
14049 create_fixed_operand (&ops
[opno
++], output
);
14050 for (argno
= 0; argno
< nargs
; argno
++)
14051 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14052 create_integer_operand (&ops
[opno
++], (int) cond
);
14053 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
14056 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14057 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14058 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14059 suggests a good place to put the result. */
14062 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
14065 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
14068 /* Map any target to operand 0. */
14071 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
14073 /* Map the arguments to the other operands. */
14074 gcc_assert (opno
+ call_expr_nargs (exp
)
14075 == insn_data
[icode
].n_generator_args
);
14076 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
14077 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
14079 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
14082 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14083 function; TYPE says which. EXP is the CALL_EXPR that calls the
14084 function, ICODE is the instruction that should be used to compare
14085 the first two arguments, and COND is the condition it should test.
14086 TARGET, if nonnull, suggests a good place to put the result. */
14089 mips_expand_builtin_movtf (enum mips_builtin_type type
,
14090 enum insn_code icode
, enum mips_fp_condition cond
,
14091 rtx target
, tree exp
)
14093 struct expand_operand ops
[4];
14096 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
14097 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
14098 if (type
== MIPS_BUILTIN_MOVT
)
14100 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
14101 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
14105 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
14106 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
14108 create_fixed_operand (&ops
[3], cmp_result
);
14109 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
14113 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14114 into TARGET otherwise. Return TARGET. */
14117 mips_builtin_branch_and_move (rtx condition
, rtx target
,
14118 rtx value_if_true
, rtx value_if_false
)
14120 rtx true_label
, done_label
;
14122 true_label
= gen_label_rtx ();
14123 done_label
= gen_label_rtx ();
14125 /* First assume that CONDITION is false. */
14126 mips_emit_move (target
, value_if_false
);
14128 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14129 emit_jump_insn (gen_condjump (condition
, true_label
));
14130 emit_jump_insn (gen_jump (done_label
));
14133 /* Fix TARGET if CONDITION is true. */
14134 emit_label (true_label
);
14135 mips_emit_move (target
, value_if_true
);
14137 emit_label (done_label
);
14141 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14142 the CALL_EXPR that calls the function, ICODE is the code of the
14143 comparison instruction, and COND is the condition it should test.
14144 TARGET, if nonnull, suggests a good place to put the boolean result. */
14147 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
14148 enum insn_code icode
, enum mips_fp_condition cond
,
14149 rtx target
, tree exp
)
14151 rtx offset
, condition
, cmp_result
;
14153 if (target
== 0 || GET_MODE (target
) != SImode
)
14154 target
= gen_reg_rtx (SImode
);
14155 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
14156 call_expr_nargs (exp
));
14158 /* If the comparison sets more than one register, we define the result
14159 to be 0 if all registers are false and -1 if all registers are true.
14160 The value of the complete result is indeterminate otherwise. */
14161 switch (builtin_type
)
14163 case MIPS_BUILTIN_CMP_ALL
:
14164 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
14165 return mips_builtin_branch_and_move (condition
, target
,
14166 const0_rtx
, const1_rtx
);
14168 case MIPS_BUILTIN_CMP_UPPER
:
14169 case MIPS_BUILTIN_CMP_LOWER
:
14170 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
14171 condition
= gen_single_cc (cmp_result
, offset
);
14172 return mips_builtin_branch_and_move (condition
, target
,
14173 const1_rtx
, const0_rtx
);
14176 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
14177 return mips_builtin_branch_and_move (condition
, target
,
14178 const1_rtx
, const0_rtx
);
14182 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14183 if nonnull, suggests a good place to put the boolean result. */
14186 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
14188 rtx condition
, cmp_result
;
14191 if (target
== 0 || GET_MODE (target
) != SImode
)
14192 target
= gen_reg_rtx (SImode
);
14194 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
14196 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
14201 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
14202 return mips_builtin_branch_and_move (condition
, target
,
14203 const1_rtx
, const0_rtx
);
14206 /* Implement TARGET_EXPAND_BUILTIN. */
14209 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
14210 enum machine_mode mode
, int ignore
)
14213 unsigned int fcode
, avail
;
14214 const struct mips_builtin_description
*d
;
14216 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14217 fcode
= DECL_FUNCTION_CODE (fndecl
);
14218 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
14219 d
= &mips_builtins
[fcode
];
14220 avail
= d
->avail ();
14221 gcc_assert (avail
!= 0);
14224 error ("built-in function %qE not supported for MIPS16",
14225 DECL_NAME (fndecl
));
14226 return ignore
? const0_rtx
: CONST0_RTX (mode
);
14228 switch (d
->builtin_type
)
14230 case MIPS_BUILTIN_DIRECT
:
14231 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
14233 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
14234 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
14236 case MIPS_BUILTIN_MOVT
:
14237 case MIPS_BUILTIN_MOVF
:
14238 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
14239 d
->cond
, target
, exp
);
14241 case MIPS_BUILTIN_CMP_ANY
:
14242 case MIPS_BUILTIN_CMP_ALL
:
14243 case MIPS_BUILTIN_CMP_UPPER
:
14244 case MIPS_BUILTIN_CMP_LOWER
:
14245 case MIPS_BUILTIN_CMP_SINGLE
:
14246 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
14247 d
->cond
, target
, exp
);
14249 case MIPS_BUILTIN_BPOSGE32
:
14250 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
14252 gcc_unreachable ();
14255 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14256 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14257 struct mips16_constant
{
14258 struct mips16_constant
*next
;
14261 enum machine_mode mode
;
14264 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14265 first constant, HIGHEST_ADDRESS is the highest address that the first
14266 byte of the pool can have, and INSN_ADDRESS is the current instruction
14268 struct mips16_constant_pool
{
14269 struct mips16_constant
*first
;
14270 int highest_address
;
14274 /* Add constant VALUE to POOL and return its label. MODE is the
14275 value's mode (used for CONST_INTs, etc.). */
14278 mips16_add_constant (struct mips16_constant_pool
*pool
,
14279 rtx value
, enum machine_mode mode
)
14281 struct mips16_constant
**p
, *c
;
14282 bool first_of_size_p
;
14284 /* See whether the constant is already in the pool. If so, return the
14285 existing label, otherwise leave P pointing to the place where the
14286 constant should be added.
14288 Keep the pool sorted in increasing order of mode size so that we can
14289 reduce the number of alignments needed. */
14290 first_of_size_p
= true;
14291 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
14293 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
14294 return (*p
)->label
;
14295 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
14297 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
14298 first_of_size_p
= false;
14301 /* In the worst case, the constant needed by the earliest instruction
14302 will end up at the end of the pool. The entire pool must then be
14303 accessible from that instruction.
14305 When adding the first constant, set the pool's highest address to
14306 the address of the first out-of-range byte. Adjust this address
14307 downwards each time a new constant is added. */
14308 if (pool
->first
== 0)
14309 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14310 of the instruction with the lowest two bits clear. The base PC
14311 value for LDPC has the lowest three bits clear. Assume the worst
14312 case here; namely that the PC-relative instruction occupies the
14313 last 2 bytes in an aligned word. */
14314 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
14315 pool
->highest_address
-= GET_MODE_SIZE (mode
);
14316 if (first_of_size_p
)
14317 /* Take into account the worst possible padding due to alignment. */
14318 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
14320 /* Create a new entry. */
14321 c
= XNEW (struct mips16_constant
);
14324 c
->label
= gen_label_rtx ();
14331 /* Output constant VALUE after instruction INSN and return the last
14332 instruction emitted. MODE is the mode of the constant. */
14335 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
14337 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
14339 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
14340 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
14343 if (SCALAR_FLOAT_MODE_P (mode
))
14344 return emit_insn_after (gen_consttable_float (value
), insn
);
14346 if (VECTOR_MODE_P (mode
))
14350 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
14351 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
14352 CONST_VECTOR_ELT (value
, i
), insn
);
14356 gcc_unreachable ();
14359 /* Dump out the constants in CONSTANTS after INSN. */
14362 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
14364 struct mips16_constant
*c
, *next
;
14368 for (c
= constants
; c
!= NULL
; c
= next
)
14370 /* If necessary, increase the alignment of PC. */
14371 if (align
< GET_MODE_SIZE (c
->mode
))
14373 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
14374 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
14376 align
= GET_MODE_SIZE (c
->mode
);
14378 insn
= emit_label_after (c
->label
, insn
);
14379 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
14385 emit_barrier_after (insn
);
14388 /* Return the length of instruction INSN. */
14391 mips16_insn_length (rtx insn
)
14395 rtx body
= PATTERN (insn
);
14396 if (GET_CODE (body
) == ADDR_VEC
)
14397 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
14398 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
14399 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
14401 return get_attr_length (insn
);
14404 /* If *X is a symbolic constant that refers to the constant pool, add
14405 the constant to POOL and rewrite *X to use the constant's label. */
14408 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
14410 rtx base
, offset
, label
;
14412 split_const (*x
, &base
, &offset
);
14413 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
14415 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
14416 get_pool_mode (base
));
14417 base
= gen_rtx_LABEL_REF (Pmode
, label
);
14418 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
14422 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14423 INSN is the instruction we're rewriting and POOL points to the current
14425 struct mips16_rewrite_pool_refs_info
{
14427 struct mips16_constant_pool
*pool
;
14430 /* Rewrite *X so that constant pool references refer to the constant's
14431 label instead. DATA points to a mips16_rewrite_pool_refs_info
14435 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
14437 struct mips16_rewrite_pool_refs_info
*info
=
14438 (struct mips16_rewrite_pool_refs_info
*) data
;
14440 if (force_to_mem_operand (*x
, Pmode
))
14442 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
14443 validate_change (info
->insn
, x
, mem
, false);
14448 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
14452 /* Don't rewrite the __mips16_rdwr symbol. */
14453 if (GET_CODE (*x
) == UNSPEC
&& XINT (*x
, 1) == UNSPEC_TLS_GET_TP
)
14456 if (TARGET_MIPS16_TEXT_LOADS
)
14457 mips16_rewrite_pool_constant (info
->pool
, x
);
14459 return GET_CODE (*x
) == CONST
? -1 : 0;
14462 /* Return whether CFG is used in mips_reorg. */
14465 mips_cfg_in_reorg (void)
14467 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
14468 || TARGET_RELAX_PIC_CALLS
);
14471 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14472 otherwise assume that they are already split. */
14475 mips16_lay_out_constants (bool split_p
)
14477 struct mips16_constant_pool pool
;
14478 struct mips16_rewrite_pool_refs_info info
;
14481 if (!TARGET_MIPS16_PCREL_LOADS
)
14486 if (mips_cfg_in_reorg ())
14487 split_all_insns ();
14489 split_all_insns_noflow ();
14492 memset (&pool
, 0, sizeof (pool
));
14493 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
14495 /* Rewrite constant pool references in INSN. */
14496 if (USEFUL_INSN_P (insn
))
14500 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
14503 pool
.insn_address
+= mips16_insn_length (insn
);
14505 if (pool
.first
!= NULL
)
14507 /* If there are no natural barriers between the first user of
14508 the pool and the highest acceptable address, we'll need to
14509 create a new instruction to jump around the constant pool.
14510 In the worst case, this instruction will be 4 bytes long.
14512 If it's too late to do this transformation after INSN,
14513 do it immediately before INSN. */
14514 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
14518 label
= gen_label_rtx ();
14520 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
14521 JUMP_LABEL (jump
) = label
;
14522 LABEL_NUSES (label
) = 1;
14523 barrier
= emit_barrier_after (jump
);
14525 emit_label_after (label
, barrier
);
14526 pool
.insn_address
+= 4;
14529 /* See whether the constant pool is now out of range of the first
14530 user. If so, output the constants after the previous barrier.
14531 Note that any instructions between BARRIER and INSN (inclusive)
14532 will use negative offsets to refer to the pool. */
14533 if (pool
.insn_address
> pool
.highest_address
)
14535 mips16_emit_constants (pool
.first
, barrier
);
14539 else if (BARRIER_P (insn
))
14543 mips16_emit_constants (pool
.first
, get_last_insn ());
14546 /* Return true if it is worth r10k_simplify_address's while replacing
14547 an address with X. We are looking for constants, and for addresses
14548 at a known offset from the incoming stack pointer. */
14551 r10k_simplified_address_p (rtx x
)
14553 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
14555 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
14558 /* X is an expression that appears in INSN. Try to use the UD chains
14559 to simplify it, returning the simplified form on success and the
14560 original form otherwise. Replace the incoming value of $sp with
14561 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14564 r10k_simplify_address (rtx x
, rtx insn
)
14566 rtx newx
, op0
, op1
, set
, def_insn
, note
;
14568 struct df_link
*defs
;
14573 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14574 if (op0
!= XEXP (x
, 0))
14575 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
14576 op0
, GET_MODE (XEXP (x
, 0)));
14578 else if (BINARY_P (x
))
14580 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14581 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
14582 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
14583 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
14585 else if (GET_CODE (x
) == LO_SUM
)
14587 /* LO_SUMs can be offset from HIGHs, if we know they won't
14588 overflow. See mips_classify_address for the rationale behind
14590 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
14591 if (GET_CODE (op0
) == HIGH
)
14592 newx
= XEXP (x
, 1);
14594 else if (REG_P (x
))
14596 /* Uses are recorded by regno_reg_rtx, not X itself. */
14597 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
14599 defs
= DF_REF_CHAIN (use
);
14601 /* Require a single definition. */
14602 if (defs
&& defs
->next
== NULL
)
14605 if (DF_REF_IS_ARTIFICIAL (def
))
14607 /* Replace the incoming value of $sp with
14608 virtual_incoming_args_rtx. */
14609 if (x
== stack_pointer_rtx
14610 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
14611 newx
= virtual_incoming_args_rtx
;
14613 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
14616 /* Make sure that DEF_INSN is a single set of REG. */
14617 def_insn
= DF_REF_INSN (def
);
14618 if (NONJUMP_INSN_P (def_insn
))
14620 set
= single_set (def_insn
);
14621 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
14623 /* Prefer to use notes, since the def-use chains
14624 are often shorter. */
14625 note
= find_reg_equal_equiv_note (def_insn
);
14627 newx
= XEXP (note
, 0);
14629 newx
= SET_SRC (set
);
14630 newx
= r10k_simplify_address (newx
, def_insn
);
14636 if (newx
&& r10k_simplified_address_p (newx
))
14641 /* Return true if ADDRESS is known to be an uncached address
14642 on R10K systems. */
14645 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
14647 unsigned HOST_WIDE_INT upper
;
14649 /* Check for KSEG1. */
14650 if (address
+ 0x60000000 < 0x20000000)
14653 /* Check for uncached XKPHYS addresses. */
14654 if (Pmode
== DImode
)
14656 upper
= (address
>> 40) & 0xf9ffff;
14657 if (upper
== 0x900000 || upper
== 0xb80000)
14663 /* Return true if we can prove that an access to address X in instruction
14664 INSN would be safe from R10K speculation. This X is a general
14665 expression; it might not be a legitimate address. */
14668 r10k_safe_address_p (rtx x
, rtx insn
)
14671 HOST_WIDE_INT offset_val
;
14673 x
= r10k_simplify_address (x
, insn
);
14675 /* Check for references to the stack frame. It doesn't really matter
14676 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14677 allows us to assume that accesses to any part of the eventual frame
14678 is safe from speculation at any point in the function. */
14679 mips_split_plus (x
, &base
, &offset_val
);
14680 if (base
== virtual_incoming_args_rtx
14681 && offset_val
>= -cfun
->machine
->frame
.total_size
14682 && offset_val
< cfun
->machine
->frame
.args_size
)
14685 /* Check for uncached addresses. */
14686 if (CONST_INT_P (x
))
14687 return r10k_uncached_address_p (INTVAL (x
));
14689 /* Check for accesses to a static object. */
14690 split_const (x
, &base
, &offset
);
14691 return offset_within_block_p (base
, INTVAL (offset
));
14694 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14695 an in-range access to an automatic variable, or to an object with
14696 a link-time-constant address. */
14699 r10k_safe_mem_expr_p (tree expr
, HOST_WIDE_INT offset
)
14701 HOST_WIDE_INT bitoffset
, bitsize
;
14702 tree inner
, var_offset
;
14703 enum machine_mode mode
;
14704 int unsigned_p
, volatile_p
;
14706 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
14707 &unsigned_p
, &volatile_p
, false);
14708 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
14711 offset
+= bitoffset
/ BITS_PER_UNIT
;
14712 return offset
>= 0 && offset
< tree_low_cst (DECL_SIZE_UNIT (inner
), 1);
14715 /* A for_each_rtx callback for which DATA points to the instruction
14716 containing *X. Stop the search if we find a MEM that is not safe
14717 from R10K speculation. */
14720 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
14729 && MEM_OFFSET_KNOWN_P (mem
)
14730 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
14733 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
14739 /* A note_stores callback for which DATA points to an instruction pointer.
14740 If *DATA is nonnull, make it null if it X contains a MEM that is not
14741 safe from R10K speculation. */
14744 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14749 insn_ptr
= (rtx
*) data
;
14750 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
14751 *insn_ptr
= NULL_RTX
;
14754 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14755 Return nonzero if the call is not to a declared function. */
14758 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
14767 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
14773 /* Return true if instruction INSN needs to be protected by an R10K
14777 r10k_needs_protection_p (rtx insn
)
14780 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
14782 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
14784 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
14785 return insn
== NULL_RTX
;
14788 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
14791 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14792 edge is unconditional. */
14795 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
14800 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14801 if (!single_succ_p (e
->src
)
14802 || !TEST_BIT (protected_bbs
, e
->src
->index
)
14803 || (e
->flags
& EDGE_COMPLEX
) != 0)
14808 /* Implement -mr10k-cache-barrier= for the current function. */
14811 r10k_insert_cache_barriers (void)
14813 int *rev_post_order
;
14816 sbitmap protected_bbs
;
14817 rtx insn
, end
, unprotected_region
;
14821 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14825 /* Calculate dominators. */
14826 calculate_dominance_info (CDI_DOMINATORS
);
14828 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14829 X is protected by a cache barrier. */
14830 protected_bbs
= sbitmap_alloc (last_basic_block
);
14831 bitmap_clear (protected_bbs
);
14833 /* Iterate over the basic blocks in reverse post-order. */
14834 rev_post_order
= XNEWVEC (int, last_basic_block
);
14835 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
14836 for (i
= 0; i
< n
; i
++)
14838 bb
= BASIC_BLOCK (rev_post_order
[i
]);
14840 /* If this block is only reached by unconditional edges, and if the
14841 source of every edge is protected, the beginning of the block is
14843 if (r10k_protected_bb_p (bb
, protected_bbs
))
14844 unprotected_region
= NULL_RTX
;
14846 unprotected_region
= pc_rtx
;
14847 end
= NEXT_INSN (BB_END (bb
));
14849 /* UNPROTECTED_REGION is:
14851 - null if we are processing a protected region,
14852 - pc_rtx if we are processing an unprotected region but have
14853 not yet found the first instruction in it
14854 - the first instruction in an unprotected region otherwise. */
14855 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
14857 if (unprotected_region
&& USEFUL_INSN_P (insn
))
14859 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
14860 /* This CACHE instruction protects the following code. */
14861 unprotected_region
= NULL_RTX
;
14864 /* See if INSN is the first instruction in this
14865 unprotected region. */
14866 if (unprotected_region
== pc_rtx
)
14867 unprotected_region
= insn
;
14869 /* See if INSN needs to be protected. If so,
14870 we must insert a cache barrier somewhere between
14871 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14872 clear which position is better performance-wise,
14873 but as a tie-breaker, we assume that it is better
14874 to allow delay slots to be back-filled where
14875 possible, and that it is better not to insert
14876 barriers in the middle of already-scheduled code.
14877 We therefore insert the barrier at the beginning
14879 if (r10k_needs_protection_p (insn
))
14881 emit_insn_before (gen_r10k_cache_barrier (),
14882 unprotected_region
);
14883 unprotected_region
= NULL_RTX
;
14889 /* The called function is not required to protect the exit path.
14890 The code that follows a call is therefore unprotected. */
14891 unprotected_region
= pc_rtx
;
14894 /* Record whether the end of this block is protected. */
14895 if (unprotected_region
== NULL_RTX
)
14896 SET_BIT (protected_bbs
, bb
->index
);
14898 XDELETEVEC (rev_post_order
);
14900 sbitmap_free (protected_bbs
);
14902 free_dominance_info (CDI_DOMINATORS
);
14905 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14906 otherwise. If INSN has two call rtx, then store the second one in
14910 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
14915 if (!CALL_P (insn
))
14918 x
= PATTERN (insn
);
14919 if (GET_CODE (x
) == PARALLEL
)
14921 /* Calls returning complex values have two CALL rtx. Look for the second
14922 one here, and return it via the SECOND_CALL arg. */
14923 x2
= XVECEXP (x
, 0, 1);
14924 if (GET_CODE (x2
) == SET
)
14926 if (GET_CODE (x2
) == CALL
)
14929 x
= XVECEXP (x
, 0, 0);
14931 if (GET_CODE (x
) == SET
)
14933 gcc_assert (GET_CODE (x
) == CALL
);
14938 /* REG is set in DEF. See if the definition is one of the ways we load a
14939 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14940 If it is, return the symbol reference of the function, otherwise return
14943 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14944 the values of source registers, otherwise treat such registers as
14945 having an unknown value. */
14948 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
14952 if (DF_REF_IS_ARTIFICIAL (def
))
14955 def_insn
= DF_REF_INSN (def
);
14956 set
= single_set (def_insn
);
14957 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
14959 rtx note
, src
, symbol
;
14961 /* First see whether the source is a plain symbol. This is used
14962 when calling symbols that are not lazily bound. */
14963 src
= SET_SRC (set
);
14964 if (GET_CODE (src
) == SYMBOL_REF
)
14967 /* Handle %call16 references. */
14968 symbol
= mips_strip_unspec_call (src
);
14971 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14975 /* If we have something more complicated, look for a
14976 REG_EQUAL or REG_EQUIV note. */
14977 note
= find_reg_equal_equiv_note (def_insn
);
14978 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
14979 return XEXP (note
, 0);
14981 /* Follow at most one simple register copy. Such copies are
14982 interesting in cases like:
14986 locally_binding_fn (...);
14991 locally_binding_fn (...);
14993 locally_binding_fn (...);
14995 where the load of locally_binding_fn can legitimately be
14996 hoisted or shared. However, we do not expect to see complex
14997 chains of copies, so a full worklist solution to the problem
14998 would probably be overkill. */
14999 if (recurse_p
&& REG_P (src
))
15000 return mips_find_pic_call_symbol (def_insn
, src
, false);
15006 /* Find the definition of the use of REG in INSN. See if the definition
15007 is one of the ways we load a register with a symbol address for a
15008 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15009 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15010 mips_pic_call_symbol_from_set. */
15013 mips_find_pic_call_symbol (rtx insn
, rtx reg
, bool recurse_p
)
15016 struct df_link
*defs
;
15019 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
15022 defs
= DF_REF_CHAIN (use
);
15025 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15029 /* If we have more than one definition, they need to be identical. */
15030 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
15034 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
15035 if (!rtx_equal_p (symbol
, other
))
15042 /* Replace the args_size operand of the call expression CALL with the
15043 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15046 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
15050 args_size
= XEXP (call
, 1);
15051 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
15052 gen_rtvec (2, args_size
, symbol
),
15056 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15057 if instead of the arg_size argument it contains the call attributes. If
15058 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15059 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15063 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
15065 rtx args_size
, symbol
;
15067 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
15070 args_size
= operands
[args_size_opno
];
15071 if (GET_CODE (args_size
) != UNSPEC
)
15073 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
15075 symbol
= XVECEXP (args_size
, 0, 1);
15076 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
15078 operands
[args_size_opno
] = symbol
;
15082 /* Use DF to annotate PIC indirect calls with the function symbol they
15086 mips_annotate_pic_calls (void)
15092 FOR_BB_INSNS (bb
, insn
)
15094 rtx call
, reg
, symbol
, second_call
;
15097 call
= mips_call_expr_from_insn (insn
, &second_call
);
15100 gcc_assert (MEM_P (XEXP (call
, 0)));
15101 reg
= XEXP (XEXP (call
, 0), 0);
15105 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
15108 mips_annotate_pic_call_expr (call
, symbol
);
15110 mips_annotate_pic_call_expr (second_call
, symbol
);
15115 /* A temporary variable used by for_each_rtx callbacks, etc. */
15116 static rtx mips_sim_insn
;
15118 /* A structure representing the state of the processor pipeline.
15119 Used by the mips_sim_* family of functions. */
15121 /* The maximum number of instructions that can be issued in a cycle.
15122 (Caches mips_issue_rate.) */
15123 unsigned int issue_rate
;
15125 /* The current simulation time. */
15128 /* How many more instructions can be issued in the current cycle. */
15129 unsigned int insns_left
;
15131 /* LAST_SET[X].INSN is the last instruction to set register X.
15132 LAST_SET[X].TIME is the time at which that instruction was issued.
15133 INSN is null if no instruction has yet set register X. */
15137 } last_set
[FIRST_PSEUDO_REGISTER
];
15139 /* The pipeline's current DFA state. */
15143 /* Reset STATE to the initial simulation state. */
15146 mips_sim_reset (struct mips_sim
*state
)
15148 curr_state
= state
->dfa_state
;
15151 state
->insns_left
= state
->issue_rate
;
15152 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
15153 state_reset (curr_state
);
15155 targetm
.sched
.init (0, false, 0);
15156 advance_state (curr_state
);
15159 /* Initialize STATE before its first use. DFA_STATE points to an
15160 allocated but uninitialized DFA state. */
15163 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
15165 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
15166 targetm
.sched
.init_dfa_pre_cycle_insn ();
15168 if (targetm
.sched
.init_dfa_post_cycle_insn
)
15169 targetm
.sched
.init_dfa_post_cycle_insn ();
15171 state
->issue_rate
= mips_issue_rate ();
15172 state
->dfa_state
= dfa_state
;
15173 mips_sim_reset (state
);
15176 /* Advance STATE by one clock cycle. */
15179 mips_sim_next_cycle (struct mips_sim
*state
)
15181 curr_state
= state
->dfa_state
;
15184 state
->insns_left
= state
->issue_rate
;
15185 advance_state (curr_state
);
15188 /* Advance simulation state STATE until instruction INSN can read
15192 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
15194 unsigned int regno
, end_regno
;
15196 end_regno
= END_REGNO (reg
);
15197 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
15198 if (state
->last_set
[regno
].insn
!= 0)
15202 t
= (state
->last_set
[regno
].time
15203 + insn_latency (state
->last_set
[regno
].insn
, insn
));
15204 while (state
->time
< t
)
15205 mips_sim_next_cycle (state
);
15209 /* A for_each_rtx callback. If *X is a register, advance simulation state
15210 DATA until mips_sim_insn can read the register's value. */
15213 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
15216 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
15220 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15223 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
15225 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
15228 /* Advance simulation state STATE until all of INSN's register
15229 dependencies are satisfied. */
15232 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
15234 mips_sim_insn
= insn
;
15235 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
15238 /* Advance simulation state STATE until the units required by
15239 instruction INSN are available. */
15242 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
15246 tmp_state
= alloca (state_size ());
15247 while (state
->insns_left
== 0
15248 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
15249 state_transition (tmp_state
, insn
) >= 0))
15250 mips_sim_next_cycle (state
);
15253 /* Advance simulation state STATE until INSN is ready to issue. */
15256 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
15258 mips_sim_wait_regs (state
, insn
);
15259 mips_sim_wait_units (state
, insn
);
15262 /* mips_sim_insn has just set X. Update the LAST_SET array
15263 in simulation state DATA. */
15266 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
15268 struct mips_sim
*state
;
15270 state
= (struct mips_sim
*) data
;
15273 unsigned int regno
, end_regno
;
15275 end_regno
= END_REGNO (x
);
15276 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
15278 state
->last_set
[regno
].insn
= mips_sim_insn
;
15279 state
->last_set
[regno
].time
= state
->time
;
15284 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15285 can issue immediately (i.e., that mips_sim_wait_insn has already
15289 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
15291 curr_state
= state
->dfa_state
;
15293 state_transition (curr_state
, insn
);
15294 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
15295 state
->insns_left
);
15297 mips_sim_insn
= insn
;
15298 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
15301 /* Simulate issuing a NOP in state STATE. */
15304 mips_sim_issue_nop (struct mips_sim
*state
)
15306 if (state
->insns_left
== 0)
15307 mips_sim_next_cycle (state
);
15308 state
->insns_left
--;
15311 /* Update simulation state STATE so that it's ready to accept the instruction
15312 after INSN. INSN should be part of the main rtl chain, not a member of a
15316 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
15318 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15320 mips_sim_issue_nop (state
);
15322 switch (GET_CODE (SEQ_BEGIN (insn
)))
15326 /* We can't predict the processor state after a call or label. */
15327 mips_sim_reset (state
);
15331 /* The delay slots of branch likely instructions are only executed
15332 when the branch is taken. Therefore, if the caller has simulated
15333 the delay slot instruction, STATE does not really reflect the state
15334 of the pipeline for the instruction after the delay slot. Also,
15335 branch likely instructions tend to incur a penalty when not taken,
15336 so there will probably be an extra delay between the branch and
15337 the instruction after the delay slot. */
15338 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
15339 mips_sim_reset (state
);
15347 /* Use simulator state STATE to calculate the execution time of
15348 instruction sequence SEQ. */
15350 static unsigned int
15351 mips_seq_time (struct mips_sim
*state
, rtx seq
)
15353 mips_sim_reset (state
);
15354 for (rtx insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
15356 mips_sim_wait_insn (state
, insn
);
15357 mips_sim_issue_insn (state
, insn
);
15359 return state
->time
;
15362 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15363 setting SETTING, using STATE to simulate instruction sequences. */
15365 static unsigned int
15366 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
15368 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
15371 enum machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
15372 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
15373 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
15375 /* If the target provides mulsidi3_32bit then that's the most likely
15376 consumer of the result. Test for bypasses. */
15377 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
15379 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
15380 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
15383 unsigned int time
= mips_seq_time (state
, get_insns ());
15388 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15389 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15390 Prefer MULT -- which is shorter -- in the event of a tie. */
15393 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
15396 /* No MTLO or MTHI available. */
15397 mips_tuning_info
.fast_mult_zero_zero_p
= true;
15400 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
15401 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
15402 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
15406 /* Set up costs based on the current architecture and tuning settings. */
15409 mips_set_tuning_info (void)
15411 if (mips_tuning_info
.initialized_p
15412 && mips_tuning_info
.arch
== mips_arch
15413 && mips_tuning_info
.tune
== mips_tune
15414 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
15417 mips_tuning_info
.arch
= mips_arch
;
15418 mips_tuning_info
.tune
= mips_tune
;
15419 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
15420 mips_tuning_info
.initialized_p
= true;
15424 struct mips_sim state
;
15425 mips_sim_init (&state
, alloca (state_size ()));
15427 mips_set_fast_mult_zero_zero_p (&state
);
15432 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15435 mips_expand_to_rtl_hook (void)
15437 /* We need to call this at a point where we can safely create sequences
15438 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15439 need to call it at a point where the DFA infrastructure is not
15440 already in use, so we can't just call it lazily on demand.
15442 At present, mips_tuning_info is only needed during post-expand
15443 RTL passes such as split_insns, so this hook should be early enough.
15444 We may need to move the call elsewhere if mips_tuning_info starts
15445 to be used for other things (such as rtx_costs, or expanders that
15446 could be called during gimple optimization). */
15447 mips_set_tuning_info ();
15450 /* The VR4130 pipeline issues aligned pairs of instructions together,
15451 but it stalls the second instruction if it depends on the first.
15452 In order to cut down the amount of logic required, this dependence
15453 check is not based on a full instruction decode. Instead, any non-SPECIAL
15454 instruction is assumed to modify the register specified by bits 20-16
15455 (which is usually the "rt" field).
15457 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15458 input, so we can end up with a false dependence between the branch
15459 and its delay slot. If this situation occurs in instruction INSN,
15460 try to avoid it by swapping rs and rt. */
15463 vr4130_avoid_branch_rt_conflict (rtx insn
)
15467 first
= SEQ_BEGIN (insn
);
15468 second
= SEQ_END (insn
);
15470 && NONJUMP_INSN_P (second
)
15471 && GET_CODE (PATTERN (first
)) == SET
15472 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
15473 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
15475 /* Check for the right kind of condition. */
15476 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
15477 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
15478 && REG_P (XEXP (cond
, 0))
15479 && REG_P (XEXP (cond
, 1))
15480 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
15481 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
15483 /* SECOND mentions the rt register but not the rs register. */
15484 rtx tmp
= XEXP (cond
, 0);
15485 XEXP (cond
, 0) = XEXP (cond
, 1);
15486 XEXP (cond
, 1) = tmp
;
15491 /* Implement -mvr4130-align. Go through each basic block and simulate the
15492 processor pipeline. If we find that a pair of instructions could execute
15493 in parallel, and the first of those instructions is not 8-byte aligned,
15494 insert a nop to make it aligned. */
15497 vr4130_align_insns (void)
15499 struct mips_sim state
;
15500 rtx insn
, subinsn
, last
, last2
, next
;
15505 /* LAST is the last instruction before INSN to have a nonzero length.
15506 LAST2 is the last such instruction before LAST. */
15510 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15513 mips_sim_init (&state
, alloca (state_size ()));
15514 for (insn
= get_insns (); insn
!= 0; insn
= next
)
15516 unsigned int length
;
15518 next
= NEXT_INSN (insn
);
15520 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15521 This isn't really related to the alignment pass, but we do it on
15522 the fly to avoid a separate instruction walk. */
15523 vr4130_avoid_branch_rt_conflict (insn
);
15525 length
= get_attr_length (insn
);
15526 if (length
> 0 && USEFUL_INSN_P (insn
))
15527 FOR_EACH_SUBINSN (subinsn
, insn
)
15529 mips_sim_wait_insn (&state
, subinsn
);
15531 /* If we want this instruction to issue in parallel with the
15532 previous one, make sure that the previous instruction is
15533 aligned. There are several reasons why this isn't worthwhile
15534 when the second instruction is a call:
15536 - Calls are less likely to be performance critical,
15537 - There's a good chance that the delay slot can execute
15538 in parallel with the call.
15539 - The return address would then be unaligned.
15541 In general, if we're going to insert a nop between instructions
15542 X and Y, it's better to insert it immediately after X. That
15543 way, if the nop makes Y aligned, it will also align any labels
15544 between X and Y. */
15545 if (state
.insns_left
!= state
.issue_rate
15546 && !CALL_P (subinsn
))
15548 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
15550 /* SUBINSN is the first instruction in INSN and INSN is
15551 aligned. We want to align the previous instruction
15552 instead, so insert a nop between LAST2 and LAST.
15554 Note that LAST could be either a single instruction
15555 or a branch with a delay slot. In the latter case,
15556 LAST, like INSN, is already aligned, but the delay
15557 slot must have some extra delay that stops it from
15558 issuing at the same time as the branch. We therefore
15559 insert a nop before the branch in order to align its
15561 gcc_assert (last2
);
15562 emit_insn_after (gen_nop (), last2
);
15565 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
15567 /* SUBINSN is the delay slot of INSN, but INSN is
15568 currently unaligned. Insert a nop between
15569 LAST and INSN to align it. */
15571 emit_insn_after (gen_nop (), last
);
15575 mips_sim_issue_insn (&state
, subinsn
);
15577 mips_sim_finish_insn (&state
, insn
);
15579 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15580 length
= get_attr_length (insn
);
15583 /* If the instruction is an asm statement or multi-instruction
15584 mips.md patern, the length is only an estimate. Insert an
15585 8 byte alignment after it so that the following instructions
15586 can be handled correctly. */
15587 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
15588 && (recog_memoized (insn
) < 0 || length
>= 8))
15590 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
15591 next
= NEXT_INSN (next
);
15592 mips_sim_next_cycle (&state
);
15595 else if (length
& 4)
15596 aligned_p
= !aligned_p
;
15601 /* See whether INSN is an aligned label. */
15602 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
15608 /* This structure records that the current function has a LO_SUM
15609 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15610 the largest offset applied to BASE by all such LO_SUMs. */
15611 struct mips_lo_sum_offset
{
15613 HOST_WIDE_INT offset
;
15616 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15619 mips_hash_base (rtx base
)
15621 int do_not_record_p
;
15623 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
15626 /* Hash-table callbacks for mips_lo_sum_offsets. */
15629 mips_lo_sum_offset_hash (const void *entry
)
15631 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
15635 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
15637 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
15638 (const_rtx
) value
);
15641 /* Look up symbolic constant X in HTAB, which is a hash table of
15642 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15643 paired with a recorded LO_SUM, otherwise record X in the table. */
15646 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
15650 struct mips_lo_sum_offset
*entry
;
15652 /* Split X into a base and offset. */
15653 split_const (x
, &base
, &offset
);
15654 if (UNSPEC_ADDRESS_P (base
))
15655 base
= UNSPEC_ADDRESS (base
);
15657 /* Look up the base in the hash table. */
15658 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
15662 entry
= (struct mips_lo_sum_offset
*) *slot
;
15663 if (option
== INSERT
)
15667 entry
= XNEW (struct mips_lo_sum_offset
);
15668 entry
->base
= base
;
15669 entry
->offset
= INTVAL (offset
);
15674 if (INTVAL (offset
) > entry
->offset
)
15675 entry
->offset
= INTVAL (offset
);
15678 return INTVAL (offset
) <= entry
->offset
;
15681 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15682 Record every LO_SUM in *LOC. */
15685 mips_record_lo_sum (rtx
*loc
, void *data
)
15687 if (GET_CODE (*loc
) == LO_SUM
)
15688 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
15692 /* Return true if INSN is a SET of an orphaned high-part relocation.
15693 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15694 LO_SUMs in the current function. */
15697 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
15699 enum mips_symbol_type type
;
15702 set
= single_set (insn
);
15705 /* Check for %his. */
15707 if (GET_CODE (x
) == HIGH
15708 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
15709 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
15711 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15712 if (GET_CODE (x
) == UNSPEC
15713 && XINT (x
, 1) == UNSPEC_LOAD_GOT
15714 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
15715 SYMBOL_CONTEXT_LEA
, &type
)
15716 && type
== SYMBOL_GOTOFF_PAGE
)
15717 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
15722 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15723 INSN and a previous instruction, avoid it by inserting nops after
15726 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15727 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15728 before using the value of that register. *HILO_DELAY counts the
15729 number of instructions since the last hilo hazard (that is,
15730 the number of instructions since the last MFLO or MFHI).
15732 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15733 for the next instruction.
15735 LO_REG is an rtx for the LO register, used in dependence checking. */
15738 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
15739 rtx
*delayed_reg
, rtx lo_reg
)
15744 pattern
= PATTERN (insn
);
15746 /* Do not put the whole function in .set noreorder if it contains
15747 an asm statement. We don't know whether there will be hazards
15748 between the asm statement and the gcc-generated code. */
15749 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
15750 cfun
->machine
->all_noreorder_p
= false;
15752 /* Ignore zero-length instructions (barriers and the like). */
15753 ninsns
= get_attr_length (insn
) / 4;
15757 /* Work out how many nops are needed. Note that we only care about
15758 registers that are explicitly mentioned in the instruction's pattern.
15759 It doesn't matter that calls use the argument registers or that they
15760 clobber hi and lo. */
15761 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
15762 nops
= 2 - *hilo_delay
;
15763 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
15768 /* Insert the nops between this instruction and the previous one.
15769 Each new nop takes us further from the last hilo hazard. */
15770 *hilo_delay
+= nops
;
15772 emit_insn_after (gen_hazard_nop (), after
);
15774 /* Set up the state for the next instruction. */
15775 *hilo_delay
+= ninsns
;
15777 if (INSN_CODE (insn
) >= 0)
15778 switch (get_attr_hazard (insn
))
15788 set
= single_set (insn
);
15790 *delayed_reg
= SET_DEST (set
);
15795 /* Go through the instruction stream and insert nops where necessary.
15796 Also delete any high-part relocations whose partnering low parts
15797 are now all dead. See if the whole function can then be put into
15798 .set noreorder and .set nomacro. */
15801 mips_reorg_process_insns (void)
15803 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
15807 /* Force all instructions to be split into their final form. */
15808 split_all_insns_noflow ();
15810 /* Recalculate instruction lengths without taking nops into account. */
15811 cfun
->machine
->ignore_hazard_length_p
= true;
15812 shorten_branches (get_insns ());
15814 cfun
->machine
->all_noreorder_p
= true;
15816 /* We don't track MIPS16 PC-relative offsets closely enough to make
15817 a good job of "set .noreorder" code in MIPS16 mode. */
15819 cfun
->machine
->all_noreorder_p
= false;
15821 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15822 if (!TARGET_EXPLICIT_RELOCS
)
15823 cfun
->machine
->all_noreorder_p
= false;
15825 /* Profiled functions can't be all noreorder because the profiler
15826 support uses assembler macros. */
15828 cfun
->machine
->all_noreorder_p
= false;
15830 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15831 because we rely on the assembler to work around some errata. */
15832 if (TARGET_FIX_VR4120
|| TARGET_FIX_24K
)
15833 cfun
->machine
->all_noreorder_p
= false;
15835 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15836 MFHI instructions. Note that we avoid using MFLO and MFHI if
15837 the VR4130 MACC and DMACC instructions are available instead;
15838 see the *mfhilo_{si,di}_macc patterns. */
15839 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
15840 cfun
->machine
->all_noreorder_p
= false;
15842 htab
= htab_create (37, mips_lo_sum_offset_hash
,
15843 mips_lo_sum_offset_eq
, free
);
15845 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15846 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
15847 FOR_EACH_SUBINSN (subinsn
, insn
)
15848 if (USEFUL_INSN_P (subinsn
))
15849 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
15854 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
15856 /* Make a second pass over the instructions. Delete orphaned
15857 high-part relocations or turn them into NOPs. Avoid hazards
15858 by inserting NOPs. */
15859 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
15861 next_insn
= NEXT_INSN (insn
);
15862 if (USEFUL_INSN_P (insn
))
15864 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
15866 /* If we find an orphaned high-part relocation in a delay
15867 slot, it's easier to turn that instruction into a NOP than
15868 to delete it. The delay slot will be a NOP either way. */
15869 FOR_EACH_SUBINSN (subinsn
, insn
)
15870 if (INSN_P (subinsn
))
15872 if (mips_orphaned_high_part_p (htab
, subinsn
))
15874 PATTERN (subinsn
) = gen_nop ();
15875 INSN_CODE (subinsn
) = CODE_FOR_nop
;
15877 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
15878 &delayed_reg
, lo_reg
);
15884 /* INSN is a single instruction. Delete it if it's an
15885 orphaned high-part relocation. */
15886 if (mips_orphaned_high_part_p (htab
, insn
))
15887 delete_insn (insn
);
15888 /* Also delete cache barriers if the last instruction
15889 was an annulled branch. INSN will not be speculatively
15891 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
15893 && JUMP_P (SEQ_BEGIN (last_insn
))
15894 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
15895 delete_insn (insn
);
15898 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
15899 &delayed_reg
, lo_reg
);
15906 htab_delete (htab
);
15909 /* Return true if the function has a long branch instruction. */
15912 mips_has_long_branch_p (void)
15917 /* We need up-to-date instruction lengths. */
15918 shorten_branches (get_insns ());
15920 /* Look for a branch that is longer than normal. The normal length for
15921 non-MIPS16 branches is 8, because the length includes the delay slot.
15922 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15923 but they have no delay slot. */
15924 normal_length
= (TARGET_MIPS16
? 4 : 8);
15925 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15926 FOR_EACH_SUBINSN (subinsn
, insn
)
15927 if (JUMP_P (subinsn
)
15928 && USEFUL_INSN_P (subinsn
)
15929 && get_attr_length (subinsn
) > normal_length
15930 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
15936 /* If we are using a GOT, but have not decided to use a global pointer yet,
15937 see whether we need one to implement long branches. Convert the ghost
15938 global-pointer instructions into real ones if so. */
15941 mips_expand_ghost_gp_insns (void)
15943 /* Quick exit if we already know that we will or won't need a
15945 if (!TARGET_USE_GOT
15946 || cfun
->machine
->global_pointer
== INVALID_REGNUM
15947 || mips_must_initialize_gp_p ())
15950 /* Run a full check for long branches. */
15951 if (!mips_has_long_branch_p ())
15954 /* We've now established that we need $gp. */
15955 cfun
->machine
->must_initialize_gp_p
= true;
15956 split_all_insns_noflow ();
15961 /* Subroutine of mips_reorg to manage passes that require DF. */
15964 mips_df_reorg (void)
15966 /* Create def-use chains. */
15967 df_set_flags (DF_EQ_NOTES
);
15968 df_chain_add_problem (DF_UD_CHAIN
);
15971 if (TARGET_RELAX_PIC_CALLS
)
15972 mips_annotate_pic_calls ();
15974 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
15975 r10k_insert_cache_barriers ();
15977 df_finish_pass (false);
15980 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
15981 called very late in mips_reorg, but the caller is required to run
15982 mips16_lay_out_constants on the result. */
15985 mips16_load_branch_target (rtx dest
, rtx src
)
15987 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
15991 if (mips_cfun_has_cprestore_slot_p ())
15992 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
15994 mips_emit_move (dest
, pic_offset_table_rtx
);
15995 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
15996 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
15997 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
15998 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
15999 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
16000 gen_rtx_LO_SUM (Pmode
, dest
, low
)));
16004 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
16005 mips_emit_move (dest
, src
);
16009 /* If we're compiling a MIPS16 function, look for and split any long branches.
16010 This must be called after all other instruction modifications in
16014 mips16_split_long_branches (void)
16016 bool something_changed
;
16018 if (!TARGET_MIPS16
)
16021 /* Loop until the alignments for all targets are sufficient. */
16026 shorten_branches (get_insns ());
16027 something_changed
= false;
16028 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
16030 && USEFUL_INSN_P (insn
)
16031 && get_attr_length (insn
) > 8
16032 && (any_condjump_p (insn
) || any_uncondjump_p (insn
)))
16034 rtx old_label
, new_label
, temp
, saved_temp
;
16035 rtx target
, jump
, jump_sequence
;
16039 /* Free up a MIPS16 register by saving it in $1. */
16040 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
16041 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
16042 emit_move_insn (saved_temp
, temp
);
16044 /* Load the branch target into TEMP. */
16045 old_label
= JUMP_LABEL (insn
);
16046 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
16047 mips16_load_branch_target (temp
, target
);
16049 /* Jump to the target and restore the register's
16051 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
16052 (temp
, temp
, saved_temp
)));
16053 JUMP_LABEL (jump
) = old_label
;
16054 LABEL_NUSES (old_label
)++;
16056 /* Rewrite any symbolic references that are supposed to use
16057 a PC-relative constant pool. */
16058 mips16_lay_out_constants (false);
16060 if (simplejump_p (insn
))
16061 /* We're going to replace INSN with a longer form. */
16062 new_label
= NULL_RTX
;
16065 /* Create a branch-around label for the original
16067 new_label
= gen_label_rtx ();
16068 emit_label (new_label
);
16071 jump_sequence
= get_insns ();
16074 emit_insn_after (jump_sequence
, insn
);
16076 invert_jump (insn
, new_label
, false);
16078 delete_insn (insn
);
16079 something_changed
= true;
16082 while (something_changed
);
16085 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16090 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16091 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16092 to date if the CFG is available. */
16093 if (mips_cfg_in_reorg ())
16094 compute_bb_for_insn ();
16095 mips16_lay_out_constants (true);
16096 if (mips_cfg_in_reorg ())
16099 free_bb_for_insn ();
16102 if (optimize
> 0 && flag_delayed_branch
)
16104 cleanup_barriers ();
16105 dbr_schedule (get_insns ());
16107 mips_reorg_process_insns ();
16109 && TARGET_EXPLICIT_RELOCS
16111 && TARGET_VR4130_ALIGN
)
16112 vr4130_align_insns ();
16113 if (mips_expand_ghost_gp_insns ())
16114 /* The expansion could invalidate some of the VR4130 alignment
16115 optimizations, but this should be an extremely rare case anyhow. */
16116 mips_reorg_process_insns ();
16117 mips16_split_long_branches ();
16120 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16121 in order to avoid duplicating too much logic from elsewhere. */
16124 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
16125 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
16128 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
16129 bool use_sibcall_p
;
16131 /* Pretend to be a post-reload pass while generating rtl. */
16132 reload_completed
= 1;
16134 /* Mark the end of the (empty) prologue. */
16135 emit_note (NOTE_INSN_PROLOGUE_END
);
16137 /* Determine if we can use a sibcall to call FUNCTION directly. */
16138 fnaddr
= XEXP (DECL_RTL (function
), 0);
16139 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
16140 && const_call_insn_operand (fnaddr
, Pmode
));
16142 /* Determine if we need to load FNADDR from the GOT. */
16144 && (mips_got_symbol_type_p
16145 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
16147 /* Pick a global pointer. Use a call-clobbered register if
16148 TARGET_CALL_SAVED_GP. */
16149 cfun
->machine
->global_pointer
16150 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
16151 cfun
->machine
->must_initialize_gp_p
= true;
16152 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
16154 /* Set up the global pointer for n32 or n64 abicalls. */
16155 mips_emit_loadgp ();
16158 /* We need two temporary registers in some cases. */
16159 temp1
= gen_rtx_REG (Pmode
, 2);
16160 temp2
= gen_rtx_REG (Pmode
, 3);
16162 /* Find out which register contains the "this" pointer. */
16163 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
16164 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
16166 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
16168 /* Add DELTA to THIS_RTX. */
16171 rtx offset
= GEN_INT (delta
);
16172 if (!SMALL_OPERAND (delta
))
16174 mips_emit_move (temp1
, offset
);
16177 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
16180 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16181 if (vcall_offset
!= 0)
16185 /* Set TEMP1 to *THIS_RTX. */
16186 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
16188 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16189 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
16191 /* Load the offset and add it to THIS_RTX. */
16192 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
16193 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
16196 /* Jump to the target function. Use a sibcall if direct jumps are
16197 allowed, otherwise load the address into a register first. */
16200 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
16201 SIBLING_CALL_P (insn
) = 1;
16205 /* This is messy. GAS treats "la $25,foo" as part of a call
16206 sequence and may allow a global "foo" to be lazily bound.
16207 The general move patterns therefore reject this combination.
16209 In this context, lazy binding would actually be OK
16210 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16211 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16212 We must therefore load the address via a temporary
16213 register if mips_dangerous_for_la25_p.
16215 If we jump to the temporary register rather than $25,
16216 the assembler can use the move insn to fill the jump's
16219 We can use the same technique for MIPS16 code, where $25
16220 is not a valid JR register. */
16221 if (TARGET_USE_PIC_FN_ADDR_REG
16223 && !mips_dangerous_for_la25_p (fnaddr
))
16224 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
16225 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
16227 if (TARGET_USE_PIC_FN_ADDR_REG
16228 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
16229 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
16230 emit_jump_insn (gen_indirect_jump (temp1
));
16233 /* Run just enough of rest_of_compilation. This sequence was
16234 "borrowed" from alpha.c. */
16235 insn
= get_insns ();
16236 split_all_insns_noflow ();
16237 mips16_lay_out_constants (true);
16238 shorten_branches (insn
);
16239 final_start_function (insn
, file
, 1);
16240 final (insn
, file
, 1);
16241 final_end_function ();
16243 /* Clean up the vars set above. Note that final_end_function resets
16244 the global pointer for us. */
16245 reload_completed
= 0;
16248 /* The last argument passed to mips_set_mips16_mode, or negative if the
16249 function hasn't been called yet. */
16250 static int was_mips16_p
= -1;
16252 /* Set up the target-dependent global state so that it matches the
16253 current function's ISA mode. */
16256 mips_set_mips16_mode (int mips16_p
)
16258 if (mips16_p
== was_mips16_p
)
16261 /* Restore base settings of various flags. */
16262 target_flags
= mips_base_target_flags
;
16263 flag_schedule_insns
= mips_base_schedule_insns
;
16264 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
16265 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
16266 align_loops
= mips_base_align_loops
;
16267 align_jumps
= mips_base_align_jumps
;
16268 align_functions
= mips_base_align_functions
;
16272 /* Switch to MIPS16 mode. */
16273 target_flags
|= MASK_MIPS16
;
16275 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16276 target_flags
&= ~MASK_SYNCI
;
16278 /* Don't run the scheduler before reload, since it tends to
16279 increase register pressure. */
16280 flag_schedule_insns
= 0;
16282 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16283 the whole function to be in a single section. */
16284 flag_reorder_blocks_and_partition
= 0;
16286 /* Don't move loop invariants, because it tends to increase
16287 register pressure. It also introduces an extra move in cases
16288 where the constant is the first operand in a two-operand binary
16289 instruction, or when it forms a register argument to a functon
16291 flag_move_loop_invariants
= 0;
16293 target_flags
|= MASK_EXPLICIT_RELOCS
;
16295 /* Experiments suggest we get the best overall section-anchor
16296 results from using the range of an unextended LW or SW. Code
16297 that makes heavy use of byte or short accesses can do better
16298 with ranges of 0...31 and 0...63 respectively, but most code is
16299 sensitive to the range of LW and SW instead. */
16300 targetm
.min_anchor_offset
= 0;
16301 targetm
.max_anchor_offset
= 127;
16303 targetm
.const_anchor
= 0;
16305 /* MIPS16 has no BAL instruction. */
16306 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16308 /* The R4000 errata don't apply to any known MIPS16 cores.
16309 It's simpler to make the R4000 fixes and MIPS16 mode
16310 mutually exclusive. */
16311 target_flags
&= ~MASK_FIX_R4000
;
16313 if (flag_pic
&& !TARGET_OLDABI
)
16314 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16317 sorry ("MIPS16 -mxgot code");
16319 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
16320 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16324 /* Switch to normal (non-MIPS16) mode. */
16325 target_flags
&= ~MASK_MIPS16
;
16327 /* Provide default values for align_* for 64-bit targets. */
16330 if (align_loops
== 0)
16332 if (align_jumps
== 0)
16334 if (align_functions
== 0)
16335 align_functions
= 8;
16338 targetm
.min_anchor_offset
= -32768;
16339 targetm
.max_anchor_offset
= 32767;
16341 targetm
.const_anchor
= 0x8000;
16344 /* (Re)initialize MIPS target internals for new ISA. */
16345 mips_init_relocs ();
16349 if (!mips16_globals
)
16350 mips16_globals
= save_target_globals ();
16352 restore_target_globals (mips16_globals
);
16355 restore_target_globals (&default_target_globals
);
16357 was_mips16_p
= mips16_p
;
16360 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16361 function should use the MIPS16 ISA and switch modes accordingly. */
16364 mips_set_current_function (tree fndecl
)
16366 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
16369 /* Allocate a chunk of memory for per-function machine-dependent data. */
16371 static struct machine_function
*
16372 mips_init_machine_status (void)
16374 return ggc_alloc_cleared_machine_function ();
16377 /* Return the processor associated with the given ISA level, or null
16378 if the ISA isn't valid. */
16380 static const struct mips_cpu_info
*
16381 mips_cpu_info_from_isa (int isa
)
16385 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16386 if (mips_cpu_info_table
[i
].isa
== isa
)
16387 return mips_cpu_info_table
+ i
;
16392 /* Return a mips_cpu_info entry determined by an option valued
16395 static const struct mips_cpu_info
*
16396 mips_cpu_info_from_opt (int opt
)
16400 case MIPS_ARCH_OPTION_FROM_ABI
:
16401 /* 'from-abi' selects the most compatible architecture for the
16402 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16403 ABIs. For the EABIs, we have to decide whether we're using
16404 the 32-bit or 64-bit version. */
16405 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
16406 : ABI_NEEDS_64BIT_REGS
? 3
16407 : (TARGET_64BIT
? 3 : 1));
16409 case MIPS_ARCH_OPTION_NATIVE
:
16410 gcc_unreachable ();
16413 return &mips_cpu_info_table
[opt
];
16417 /* Return a default mips_cpu_info entry, given that no -march= option
16418 was explicitly specified. */
16420 static const struct mips_cpu_info
*
16421 mips_default_arch (void)
16423 #if defined (MIPS_CPU_STRING_DEFAULT)
16425 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
16426 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
16427 return mips_cpu_info_table
+ i
;
16428 gcc_unreachable ();
16429 #elif defined (MIPS_ISA_DEFAULT)
16430 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
16432 /* 'from-abi' makes a good default: you get whatever the ABI
16434 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
16438 /* Set up globals to generate code for the ISA or processor
16439 described by INFO. */
16442 mips_set_architecture (const struct mips_cpu_info
*info
)
16446 mips_arch_info
= info
;
16447 mips_arch
= info
->cpu
;
16448 mips_isa
= info
->isa
;
16452 /* Likewise for tuning. */
16455 mips_set_tune (const struct mips_cpu_info
*info
)
16459 mips_tune_info
= info
;
16460 mips_tune
= info
->cpu
;
16464 /* Implement TARGET_OPTION_OVERRIDE. */
16467 mips_option_override (void)
16469 int i
, start
, regno
, mode
;
16471 if (global_options_set
.x_mips_isa_option
)
16472 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
16474 /* Process flags as though we were generating non-MIPS16 code. */
16475 mips_base_mips16
= TARGET_MIPS16
;
16476 target_flags
&= ~MASK_MIPS16
;
16478 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16479 SUBTARGET_OVERRIDE_OPTIONS
;
16482 /* -mno-float overrides -mhard-float and -msoft-float. */
16483 if (TARGET_NO_FLOAT
)
16485 target_flags
|= MASK_SOFT_FLOAT_ABI
;
16486 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
16489 if (TARGET_FLIP_MIPS16
)
16490 TARGET_INTERLINK_MIPS16
= 1;
16492 /* Set the small data limit. */
16493 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
16495 : MIPS_DEFAULT_GVALUE
);
16497 /* The following code determines the architecture and register size.
16498 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16499 The GAS and GCC code should be kept in sync as much as possible. */
16501 if (global_options_set
.x_mips_arch_option
)
16502 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
16504 if (mips_isa_option_info
!= 0)
16506 if (mips_arch_info
== 0)
16507 mips_set_architecture (mips_isa_option_info
);
16508 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
16509 error ("%<-%s%> conflicts with the other architecture options, "
16510 "which specify a %s processor",
16511 mips_isa_option_info
->name
,
16512 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
16515 if (mips_arch_info
== 0)
16516 mips_set_architecture (mips_default_arch ());
16518 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
16519 error ("%<-march=%s%> is not compatible with the selected ABI",
16520 mips_arch_info
->name
);
16522 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16523 if (global_options_set
.x_mips_tune_option
)
16524 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
16526 if (mips_tune_info
== 0)
16527 mips_set_tune (mips_arch_info
);
16529 if ((target_flags_explicit
& MASK_64BIT
) != 0)
16531 /* The user specified the size of the integer registers. Make sure
16532 it agrees with the ABI and ISA. */
16533 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
16534 error ("%<-mgp64%> used with a 32-bit processor");
16535 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
16536 error ("%<-mgp32%> used with a 64-bit ABI");
16537 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
16538 error ("%<-mgp64%> used with a 32-bit ABI");
16542 /* Infer the integer register size from the ABI and processor.
16543 Restrict ourselves to 32-bit registers if that's all the
16544 processor has, or if the ABI cannot handle 64-bit registers. */
16545 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
16546 target_flags
&= ~MASK_64BIT
;
16548 target_flags
|= MASK_64BIT
;
16551 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
16553 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
16554 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16555 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
16556 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16557 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
16559 if (!ISA_HAS_MXHC1
)
16560 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16561 " the target supports the mfhc1 and mthc1 instructions");
16562 else if (mips_abi
!= ABI_32
)
16563 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16569 /* -msingle-float selects 32-bit float registers. Otherwise the
16570 float registers should be the same size as the integer ones. */
16571 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
16572 target_flags
|= MASK_FLOAT64
;
16574 target_flags
&= ~MASK_FLOAT64
;
16577 /* End of code shared with GAS. */
16579 /* If a -mlong* option was given, check that it matches the ABI,
16580 otherwise infer the -mlong* setting from the other options. */
16581 if ((target_flags_explicit
& MASK_LONG64
) != 0)
16585 if (mips_abi
== ABI_N32
)
16586 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16587 else if (mips_abi
== ABI_32
)
16588 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16589 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
16590 /* We have traditionally allowed non-abicalls code to use
16591 an LP64 form of o64. However, it would take a bit more
16592 effort to support the combination of 32-bit GOT entries
16593 and 64-bit pointers, so we treat the abicalls case as
16595 error ("the combination of %qs and %qs is incompatible with %qs",
16596 "-mabi=o64", "-mabicalls", "-mlong64");
16600 if (mips_abi
== ABI_64
)
16601 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16606 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
16607 target_flags
|= MASK_LONG64
;
16609 target_flags
&= ~MASK_LONG64
;
16612 if (!TARGET_OLDABI
)
16613 flag_pcc_struct_return
= 0;
16615 /* Decide which rtx_costs structure to use. */
16617 mips_cost
= &mips_rtx_cost_optimize_size
;
16619 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
16621 /* If the user hasn't specified a branch cost, use the processor's
16623 if (mips_branch_cost
== 0)
16624 mips_branch_cost
= mips_cost
->branch_cost
;
16626 /* If neither -mbranch-likely nor -mno-branch-likely was given
16627 on the command line, set MASK_BRANCHLIKELY based on the target
16628 architecture and tuning flags. Annulled delay slots are a
16629 size win, so we only consider the processor-specific tuning
16630 for !optimize_size. */
16631 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
16633 if (ISA_HAS_BRANCHLIKELY
16635 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
16636 target_flags
|= MASK_BRANCHLIKELY
;
16638 target_flags
&= ~MASK_BRANCHLIKELY
;
16640 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
16641 warning (0, "the %qs architecture does not support branch-likely"
16642 " instructions", mips_arch_info
->name
);
16644 /* The effect of -mabicalls isn't defined for the EABI. */
16645 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
16647 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16648 target_flags
&= ~MASK_ABICALLS
;
16651 /* PIC requires -mabicalls. */
16654 if (mips_abi
== ABI_EABI
)
16655 error ("cannot generate position-independent code for %qs",
16657 else if (!TARGET_ABICALLS
)
16658 error ("position-independent code requires %qs", "-mabicalls");
16661 if (TARGET_ABICALLS_PIC2
)
16662 /* We need to set flag_pic for executables as well as DSOs
16663 because we may reference symbols that are not defined in
16664 the final executable. (MIPS does not use things like
16665 copy relocs, for example.)
16667 There is a body of code that uses __PIC__ to distinguish
16668 between -mabicalls and -mno-abicalls code. The non-__PIC__
16669 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16670 long as any indirect jumps use $25. */
16673 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16674 faster code, but at the expense of more nops. Enable it at -O3 and
16676 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
16677 target_flags
|= MASK_VR4130_ALIGN
;
16679 /* Prefer a call to memcpy over inline code when optimizing for size,
16680 though see MOVE_RATIO in mips.h. */
16681 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
16682 target_flags
|= MASK_MEMCPY
;
16684 /* If we have a nonzero small-data limit, check that the -mgpopt
16685 setting is consistent with the other target flags. */
16686 if (mips_small_data_threshold
> 0)
16690 if (!TARGET_EXPLICIT_RELOCS
)
16691 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16693 TARGET_LOCAL_SDATA
= false;
16694 TARGET_EXTERN_SDATA
= false;
16698 if (TARGET_VXWORKS_RTP
)
16699 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16701 if (TARGET_ABICALLS
)
16702 warning (0, "cannot use small-data accesses for %qs",
16707 /* Make sure that the user didn't turn off paired single support when
16708 MIPS-3D support is requested. */
16710 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
16711 && !TARGET_PAIRED_SINGLE_FLOAT
)
16712 error ("%<-mips3d%> requires %<-mpaired-single%>");
16714 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16716 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
16718 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16719 and TARGET_HARD_FLOAT_ABI are both true. */
16720 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
16721 error ("%qs must be used with %qs",
16722 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
16723 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
16725 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16727 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
16728 warning (0, "the %qs architecture does not support paired-single"
16729 " instructions", mips_arch_info
->name
);
16731 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
16732 && !TARGET_CACHE_BUILTIN
)
16734 error ("%qs requires a target that provides the %qs instruction",
16735 "-mr10k-cache-barrier", "cache");
16736 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
16739 /* If TARGET_DSPR2, enable MASK_DSP. */
16741 target_flags
|= MASK_DSP
;
16743 /* .eh_frame addresses should be the same width as a C pointer.
16744 Most MIPS ABIs support only one pointer size, so the assembler
16745 will usually know exactly how big an .eh_frame address is.
16747 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16748 originally defined to use 64-bit pointers (i.e. it is LP64), and
16749 this is still the default mode. However, we also support an n32-like
16750 ILP32 mode, which is selected by -mlong32. The problem is that the
16751 assembler has traditionally not had an -mlong option, so it has
16752 traditionally not known whether we're using the ILP32 or LP64 form.
16754 As it happens, gas versions up to and including 2.19 use _32-bit_
16755 addresses for EABI64 .cfi_* directives. This is wrong for the
16756 default LP64 mode, so we can't use the directives by default.
16757 Moreover, since gas's current behavior is at odds with gcc's
16758 default behavior, it seems unwise to rely on future versions
16759 of gas behaving the same way. We therefore avoid using .cfi
16760 directives for -mlong32 as well. */
16761 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
16762 flag_dwarf2_cfi_asm
= 0;
16764 /* .cfi_* directives generate a read-only section, so fall back on
16765 manual .eh_frame creation if we need the section to be writable. */
16766 if (TARGET_WRITABLE_EH_FRAME
)
16767 flag_dwarf2_cfi_asm
= 0;
16769 mips_init_print_operand_punct ();
16771 /* Set up array to map GCC register number to debug register number.
16772 Ignore the special purpose register numbers. */
16774 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
16776 mips_dbx_regno
[i
] = INVALID_REGNUM
;
16777 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
16778 mips_dwarf_regno
[i
] = i
;
16780 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
16783 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
16784 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
16785 mips_dbx_regno
[i
] = i
+ start
;
16787 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
16788 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
16789 mips_dbx_regno
[i
] = i
+ start
;
16791 /* Accumulator debug registers use big-endian ordering. */
16792 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
16793 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
16794 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
16795 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
16796 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
16798 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
16799 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
16802 /* Set up mips_hard_regno_mode_ok. */
16803 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
16804 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
16805 mips_hard_regno_mode_ok
[mode
][regno
]
16806 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
16808 /* Function to allocate machine-dependent function status. */
16809 init_machine_status
= &mips_init_machine_status
;
16811 /* Default to working around R4000 errata only if the processor
16812 was selected explicitly. */
16813 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
16814 && strcmp (mips_arch_info
->name
, "r4000") == 0)
16815 target_flags
|= MASK_FIX_R4000
;
16817 /* Default to working around R4400 errata only if the processor
16818 was selected explicitly. */
16819 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
16820 && strcmp (mips_arch_info
->name
, "r4400") == 0)
16821 target_flags
|= MASK_FIX_R4400
;
16823 /* Default to working around R10000 errata only if the processor
16824 was selected explicitly. */
16825 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
16826 && strcmp (mips_arch_info
->name
, "r10000") == 0)
16827 target_flags
|= MASK_FIX_R10000
;
16829 /* Make sure that branch-likely instructions available when using
16830 -mfix-r10000. The instructions are not available if either:
16832 1. -mno-branch-likely was passed.
16833 2. The selected ISA does not support branch-likely and
16834 the command line does not include -mbranch-likely. */
16835 if (TARGET_FIX_R10000
16836 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
16837 ? !ISA_HAS_BRANCHLIKELY
16838 : !TARGET_BRANCHLIKELY
))
16839 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16841 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
16843 warning (0, "the %qs architecture does not support the synci "
16844 "instruction", mips_arch_info
->name
);
16845 target_flags
&= ~MASK_SYNCI
;
16848 /* Only optimize PIC indirect calls if they are actually required. */
16849 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
16850 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
16852 /* Save base state of options. */
16853 mips_base_target_flags
= target_flags
;
16854 mips_base_schedule_insns
= flag_schedule_insns
;
16855 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
16856 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
16857 mips_base_align_loops
= align_loops
;
16858 mips_base_align_jumps
= align_jumps
;
16859 mips_base_align_functions
= align_functions
;
16861 /* Now select the ISA mode.
16863 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16864 MIPS16 mode afterwards if need be. */
16865 mips_set_mips16_mode (false);
16868 /* Swap the register information for registers I and I + 1, which
16869 currently have the wrong endianness. Note that the registers'
16870 fixedness and call-clobberedness might have been set on the
16874 mips_swap_registers (unsigned int i
)
16879 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16880 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16882 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
16883 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
16884 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
16885 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
16891 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16894 mips_conditional_register_usage (void)
16899 /* These DSP control register fields are global. */
16900 global_regs
[CCDSP_PO_REGNUM
] = 1;
16901 global_regs
[CCDSP_SC_REGNUM
] = 1;
16904 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16905 reg_class_contents
[(int) DSP_ACC_REGS
]);
16907 if (!TARGET_HARD_FLOAT
)
16909 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16910 reg_class_contents
[(int) FP_REGS
]);
16911 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16912 reg_class_contents
[(int) ST_REGS
]);
16914 else if (!ISA_HAS_8CC
)
16916 /* We only have a single condition-code register. We implement
16917 this by fixing all the condition-code registers and generating
16918 RTL that refers directly to ST_REG_FIRST. */
16919 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
16920 reg_class_contents
[(int) ST_REGS
]);
16921 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
16922 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
16926 /* In MIPS16 mode, we permit the $t temporary registers to be used
16927 for reload. We prohibit the unused $s registers, since they
16928 are call-saved, and saving them via a MIPS16 register would
16929 probably waste more time than just reloading the value. */
16930 fixed_regs
[18] = call_used_regs
[18] = 1;
16931 fixed_regs
[19] = call_used_regs
[19] = 1;
16932 fixed_regs
[20] = call_used_regs
[20] = 1;
16933 fixed_regs
[21] = call_used_regs
[21] = 1;
16934 fixed_regs
[22] = call_used_regs
[22] = 1;
16935 fixed_regs
[23] = call_used_regs
[23] = 1;
16936 fixed_regs
[26] = call_used_regs
[26] = 1;
16937 fixed_regs
[27] = call_used_regs
[27] = 1;
16938 fixed_regs
[30] = call_used_regs
[30] = 1;
16940 /* Do not allow HI and LO to be treated as register operands.
16941 There are no MTHI or MTLO instructions (or any real need
16942 for them) and one-way registers cannot easily be reloaded. */
16943 AND_COMPL_HARD_REG_SET (operand_reg_set
,
16944 reg_class_contents
[(int) MD_REGS
]);
16946 /* $f20-$f23 are call-clobbered for n64. */
16947 if (mips_abi
== ABI_64
)
16950 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
16951 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
16953 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16955 if (mips_abi
== ABI_N32
)
16958 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
16959 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
16961 /* Make sure that double-register accumulator values are correctly
16962 ordered for the current endianness. */
16963 if (TARGET_LITTLE_ENDIAN
)
16965 unsigned int regno
;
16967 mips_swap_registers (MD_REG_FIRST
);
16968 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
16969 mips_swap_registers (regno
);
16973 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16974 other registers for instructions for which it is possible. This
16975 encourages the compiler to use CMP in cases where an XOR would
16976 require some register shuffling. */
16979 mips_order_regs_for_local_alloc (void)
16983 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
16984 reg_alloc_order
[i
] = i
;
16988 /* It really doesn't matter where we put register 0, since it is
16989 a fixed register anyhow. */
16990 reg_alloc_order
[0] = 24;
16991 reg_alloc_order
[24] = 0;
16995 /* Implement EH_USES. */
16998 mips_eh_uses (unsigned int regno
)
17000 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
17002 /* We need to force certain registers to be live in order to handle
17003 PIC long branches correctly. See mips_must_initialize_gp_p for
17005 if (mips_cfun_has_cprestore_slot_p ())
17007 if (regno
== CPRESTORE_SLOT_REGNUM
)
17012 if (cfun
->machine
->global_pointer
== regno
)
17020 /* Implement EPILOGUE_USES. */
17023 mips_epilogue_uses (unsigned int regno
)
17025 /* Say that the epilogue uses the return address register. Note that
17026 in the case of sibcalls, the values "used by the epilogue" are
17027 considered live at the start of the called function. */
17028 if (regno
== RETURN_ADDR_REGNUM
)
17031 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17032 See the comment above load_call<mode> for details. */
17033 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
17036 /* An interrupt handler must preserve some registers that are
17037 ordinarily call-clobbered. */
17038 if (cfun
->machine
->interrupt_handler_p
17039 && mips_interrupt_extra_call_saved_reg_p (regno
))
17045 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17048 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
17050 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
17053 /* Return true if INSN needs to be wrapped in ".set noat".
17054 INSN has NOPERANDS operands, stored in OPVEC. */
17057 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
17061 if (recog_memoized (insn
) >= 0)
17062 for (i
= 0; i
< noperands
; i
++)
17063 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
17068 /* Implement FINAL_PRESCAN_INSN. */
17071 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
17073 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17074 mips_push_asm_switch (&mips_noat
);
17077 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17080 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
17081 rtx
*opvec
, int noperands
)
17083 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
17084 mips_pop_asm_switch (&mips_noat
);
17087 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17088 EXT_CODE is the code of the extension used. Return NULL if widening
17089 multiplication shouldn't be used. */
17092 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
17096 signed_p
= ext_code
== SIGN_EXTEND
;
17099 /* Don't use widening multiplication with MULT when we have DMUL. Even
17100 with the extension of its input operands DMUL is faster. Note that
17101 the extension is not needed for signed multiplication. In order to
17102 ensure that we always remove the redundant sign-extension in this
17103 case we still expand mulsidi3 for DMUL. */
17105 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
17108 ? gen_mulsidi3_64bit_mips16
17109 : gen_umulsidi3_64bit_mips16
);
17110 if (TARGET_FIX_R4000
)
17112 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
17118 ? gen_mulsidi3_32bit_mips16
17119 : gen_umulsidi3_32bit_mips16
);
17120 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
17121 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
17122 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
17126 /* Return the size in bytes of the trampoline code, padded to
17127 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17128 function address immediately follow. */
17131 mips_trampoline_code_size (void)
17133 if (TARGET_USE_PIC_FN_ADDR_REG
)
17135 else if (ptr_mode
== DImode
)
17137 else if (ISA_HAS_LOAD_DELAY
)
17143 /* Implement TARGET_TRAMPOLINE_INIT. */
17146 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
17148 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
17151 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
17153 /* Work out the offsets of the pointers from the start of the
17154 trampoline code. */
17155 end_addr_offset
= mips_trampoline_code_size ();
17156 static_chain_offset
= end_addr_offset
;
17157 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
17159 /* Get pointers to the beginning and end of the code block. */
17160 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
17161 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
17163 #define OP(X) gen_int_mode (X, SImode)
17165 /* Build up the code in TRAMPOLINE. */
17167 if (TARGET_USE_PIC_FN_ADDR_REG
)
17169 /* $25 contains the address of the trampoline. Emit code of the form:
17171 l[wd] $1, target_function_offset($25)
17172 l[wd] $static_chain, static_chain_offset($25)
17175 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
17176 target_function_offset
,
17177 PIC_FUNCTION_ADDR_REGNUM
));
17178 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17179 static_chain_offset
,
17180 PIC_FUNCTION_ADDR_REGNUM
));
17181 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
17182 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
17184 else if (ptr_mode
== DImode
)
17186 /* It's too cumbersome to create the full 64-bit address, so let's
17192 1: l[wd] $25, target_function_offset - 12($31)
17193 l[wd] $static_chain, static_chain_offset - 12($31)
17197 where 12 is the offset of "1:" from the start of the code block. */
17198 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
17199 trampoline
[i
++] = OP (MIPS_BAL (1));
17200 trampoline
[i
++] = OP (MIPS_NOP
);
17201 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17202 target_function_offset
- 12,
17203 RETURN_ADDR_REGNUM
));
17204 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17205 static_chain_offset
- 12,
17206 RETURN_ADDR_REGNUM
));
17207 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17208 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
17212 /* If the target has load delays, emit:
17214 lui $1, %hi(end_addr)
17215 lw $25, %lo(end_addr + ...)($1)
17216 lw $static_chain, %lo(end_addr + ...)($1)
17222 lui $1, %hi(end_addr)
17223 lw $25, %lo(end_addr + ...)($1)
17225 lw $static_chain, %lo(end_addr + ...)($1). */
17227 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17228 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17229 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
17230 NULL
, false, OPTAB_WIDEN
);
17231 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
17232 NULL
, false, OPTAB_WIDEN
);
17233 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
17235 /* Emit the LUI. */
17236 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
17237 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
17238 NULL
, false, OPTAB_WIDEN
);
17240 /* Emit the load of the target function. */
17241 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
17242 target_function_offset
- end_addr_offset
,
17244 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17245 NULL
, false, OPTAB_WIDEN
);
17247 /* Emit the JR here, if we can. */
17248 if (!ISA_HAS_LOAD_DELAY
)
17249 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17251 /* Emit the load of the static chain register. */
17252 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
17253 static_chain_offset
- end_addr_offset
,
17255 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
17256 NULL
, false, OPTAB_WIDEN
);
17258 /* Emit the JR, if we couldn't above. */
17259 if (ISA_HAS_LOAD_DELAY
)
17261 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
17262 trampoline
[i
++] = OP (MIPS_NOP
);
17268 /* Copy the trampoline code. Leave any padding uninitialized. */
17269 for (j
= 0; j
< i
; j
++)
17271 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
17272 mips_emit_move (mem
, trampoline
[j
]);
17275 /* Set up the static chain pointer field. */
17276 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
17277 mips_emit_move (mem
, chain_value
);
17279 /* Set up the target function field. */
17280 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
17281 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
17283 /* Flush the code part of the trampoline. */
17284 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
17285 emit_insn (gen_clear_cache (addr
, end_addr
));
17288 /* Implement FUNCTION_PROFILER. */
17290 void mips_function_profiler (FILE *file
)
17293 sorry ("mips16 function profiling");
17294 if (TARGET_LONG_CALLS
)
17296 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17297 if (Pmode
== DImode
)
17298 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
17300 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
17302 mips_push_asm_switch (&mips_noat
);
17303 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
17304 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
17305 /* _mcount treats $2 as the static chain register. */
17306 if (cfun
->static_chain_decl
!= NULL
)
17307 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
17308 reg_names
[STATIC_CHAIN_REGNUM
]);
17309 if (TARGET_MCOUNT_RA_ADDRESS
)
17311 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17312 ra save location. */
17313 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
17314 /* ra not saved, pass zero. */
17315 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
17317 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
17318 Pmode
== DImode
? "dla" : "la", reg_names
[12],
17319 cfun
->machine
->frame
.ra_fp_offset
,
17320 reg_names
[STACK_POINTER_REGNUM
]);
17322 if (!TARGET_NEWABI
)
17324 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17325 TARGET_64BIT
? "dsubu" : "subu",
17326 reg_names
[STACK_POINTER_REGNUM
],
17327 reg_names
[STACK_POINTER_REGNUM
],
17328 Pmode
== DImode
? 16 : 8);
17330 if (TARGET_LONG_CALLS
)
17331 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
17333 fprintf (file
, "\tjal\t_mcount\n");
17334 mips_pop_asm_switch (&mips_noat
);
17335 /* _mcount treats $2 as the static chain register. */
17336 if (cfun
->static_chain_decl
!= NULL
)
17337 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
17341 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17342 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17343 when TARGET_LOONGSON_VECTORS is true. */
17345 static unsigned HOST_WIDE_INT
17346 mips_shift_truncation_mask (enum machine_mode mode
)
17348 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
17351 return GET_MODE_BITSIZE (mode
) - 1;
17354 /* Implement TARGET_PREPARE_PCH_SAVE. */
17357 mips_prepare_pch_save (void)
17359 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17360 setting should be irrelevant. The question then is: which setting
17361 makes most sense at load time?
17363 The PCH is loaded before the first token is read. We should never
17364 have switched into MIPS16 mode by that point, and thus should not
17365 have populated mips16_globals. Nor can we load the entire contents
17366 of mips16_globals from the PCH file, because mips16_globals contains
17367 a combination of GGC and non-GGC data.
17369 There is therefore no point in trying save the GGC part of
17370 mips16_globals to the PCH file, or to preserve MIPS16ness across
17371 the PCH save and load. The loading compiler would not have access
17372 to the non-GGC parts of mips16_globals (either from the PCH file,
17373 or from a copy that the loading compiler generated itself) and would
17374 have to call target_reinit anyway.
17376 It therefore seems best to switch back to non-MIPS16 mode at
17377 save time, and to ensure that mips16_globals remains null after
17379 mips_set_mips16_mode (false);
17380 mips16_globals
= 0;
17383 /* Generate or test for an insn that supports a constant permutation. */
17385 #define MAX_VECT_LEN 8
17387 struct expand_vec_perm_d
17389 rtx target
, op0
, op1
;
17390 unsigned char perm
[MAX_VECT_LEN
];
17391 enum machine_mode vmode
;
17392 unsigned char nelt
;
17397 /* Construct (set target (vec_select op0 (parallel perm))) and
17398 return true if that's a valid instruction in the active ISA. */
17401 mips_expand_vselect (rtx target
, rtx op0
,
17402 const unsigned char *perm
, unsigned nelt
)
17404 rtx rperm
[MAX_VECT_LEN
], x
;
17407 for (i
= 0; i
< nelt
; ++i
)
17408 rperm
[i
] = GEN_INT (perm
[i
]);
17410 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
17411 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
17412 x
= gen_rtx_SET (VOIDmode
, target
, x
);
17415 if (recog_memoized (x
) < 0)
17423 /* Similar, but generate a vec_concat from op0 and op1 as well. */
17426 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
17427 const unsigned char *perm
, unsigned nelt
)
17429 enum machine_mode v2mode
;
17432 v2mode
= GET_MODE_2XWIDER_MODE (GET_MODE (op0
));
17433 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
17434 return mips_expand_vselect (target
, x
, perm
, nelt
);
17437 /* Recognize patterns for even-odd extraction. */
17440 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
17442 unsigned i
, odd
, nelt
= d
->nelt
;
17443 rtx t0
, t1
, t2
, t3
;
17445 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17447 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
17454 for (i
= 1; i
< nelt
; ++i
)
17455 if (d
->perm
[i
] != i
* 2 + odd
)
17461 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
17462 t0
= gen_reg_rtx (d
->vmode
);
17463 t1
= gen_reg_rtx (d
->vmode
);
17467 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
17468 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
17470 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
17472 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
17476 t2
= gen_reg_rtx (d
->vmode
);
17477 t3
= gen_reg_rtx (d
->vmode
);
17478 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
17479 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
17480 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
17481 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
17483 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
17485 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
17489 gcc_unreachable ();
17494 /* Recognize patterns for the Loongson PSHUFH instruction. */
17497 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
17502 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17504 if (d
->vmode
!= V4HImode
)
17509 /* Convert the selector into the packed 8-bit form for pshufh. */
17510 /* Recall that loongson is little-endian only. No big-endian
17511 adjustment required. */
17512 for (i
= mask
= 0; i
< 4; i
++)
17513 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
17514 rmask
= force_reg (SImode
, GEN_INT (mask
));
17516 if (d
->one_vector_p
)
17517 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
17520 rtx t0
, t1
, x
, merge
, rmerge
[4];
17522 t0
= gen_reg_rtx (V4HImode
);
17523 t1
= gen_reg_rtx (V4HImode
);
17524 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
17525 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
17527 for (i
= 0; i
< 4; ++i
)
17528 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
17529 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
17530 merge
= force_reg (V4HImode
, merge
);
17532 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
17533 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
17535 x
= gen_rtx_NOT (V4HImode
, merge
);
17536 x
= gen_rtx_AND (V4HImode
, x
, t0
);
17537 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
17539 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
17540 emit_insn (gen_rtx_SET (VOIDmode
, d
->target
, x
));
17546 /* Recognize broadcast patterns for the Loongson. */
17549 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
17554 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
17556 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
17557 if (d
->vmode
!= V8QImode
)
17559 if (!d
->one_vector_p
)
17563 for (i
= 1; i
< 8; ++i
)
17564 if (d
->perm
[i
] != elt
)
17570 /* With one interleave we put two of the desired element adjacent. */
17571 t0
= gen_reg_rtx (V8QImode
);
17573 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
17575 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
17577 /* Shuffle that one HImode element into all locations. */
17580 t1
= gen_reg_rtx (V4HImode
);
17581 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
17582 force_reg (SImode
, GEN_INT (elt
))));
17584 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
17589 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
17591 unsigned int i
, nelt
= d
->nelt
;
17592 unsigned char perm2
[MAX_VECT_LEN
];
17594 if (d
->one_vector_p
)
17596 /* Try interleave with alternating operands. */
17597 memcpy (perm2
, d
->perm
, sizeof(perm2
));
17598 for (i
= 1; i
< nelt
; i
+= 2)
17600 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
17605 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
17609 /* Try again with swapped operands. */
17610 for (i
= 0; i
< nelt
; ++i
)
17611 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
17612 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
17616 if (mips_expand_vpc_loongson_even_odd (d
))
17618 if (mips_expand_vpc_loongson_pshufh (d
))
17620 if (mips_expand_vpc_loongson_bcast (d
))
17625 /* Expand a vec_perm_const pattern. */
17628 mips_expand_vec_perm_const (rtx operands
[4])
17630 struct expand_vec_perm_d d
;
17631 int i
, nelt
, which
;
17632 unsigned char orig_perm
[MAX_VECT_LEN
];
17636 d
.target
= operands
[0];
17637 d
.op0
= operands
[1];
17638 d
.op1
= operands
[2];
17641 d
.vmode
= GET_MODE (d
.target
);
17642 gcc_assert (VECTOR_MODE_P (d
.vmode
));
17643 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
17644 d
.testing_p
= false;
17646 for (i
= which
= 0; i
< nelt
; ++i
)
17648 rtx e
= XVECEXP (sel
, 0, i
);
17649 int ei
= INTVAL (e
) & (2 * nelt
- 1);
17650 which
|= (ei
< nelt
? 1 : 2);
17653 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
17661 d
.one_vector_p
= false;
17662 if (!rtx_equal_p (d
.op0
, d
.op1
))
17667 for (i
= 0; i
< nelt
; ++i
)
17668 d
.perm
[i
] &= nelt
- 1;
17670 d
.one_vector_p
= true;
17675 d
.one_vector_p
= true;
17679 ok
= mips_expand_vec_perm_const_1 (&d
);
17681 /* If we were given a two-vector permutation which just happened to
17682 have both input vectors equal, we folded this into a one-vector
17683 permutation. There are several loongson patterns that are matched
17684 via direct vec_select+vec_concat expansion, but we do not have
17685 support in mips_expand_vec_perm_const_1 to guess the adjustment
17686 that should be made for a single operand. Just try again with
17687 the original permutation. */
17688 if (!ok
&& which
== 3)
17690 d
.op0
= operands
[1];
17691 d
.op1
= operands
[2];
17692 d
.one_vector_p
= false;
17693 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
17694 ok
= mips_expand_vec_perm_const_1 (&d
);
17700 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
17703 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
17704 const unsigned char *sel
)
17706 struct expand_vec_perm_d d
;
17707 unsigned int i
, nelt
, which
;
17711 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
17712 d
.testing_p
= true;
17713 memcpy (d
.perm
, sel
, nelt
);
17715 /* Categorize the set of elements in the selector. */
17716 for (i
= which
= 0; i
< nelt
; ++i
)
17718 unsigned char e
= d
.perm
[i
];
17719 gcc_assert (e
< 2 * nelt
);
17720 which
|= (e
< nelt
? 1 : 2);
17723 /* For all elements from second vector, fold the elements to first. */
17725 for (i
= 0; i
< nelt
; ++i
)
17728 /* Check whether the mask can be applied to the vector type. */
17729 d
.one_vector_p
= (which
!= 3);
17731 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
17732 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
17733 if (!d
.one_vector_p
)
17734 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
17737 ret
= mips_expand_vec_perm_const_1 (&d
);
17743 /* Expand an integral vector unpack operation. */
17746 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
17748 enum machine_mode imode
= GET_MODE (operands
[1]);
17749 rtx (*unpack
) (rtx
, rtx
, rtx
);
17750 rtx (*cmpgt
) (rtx
, rtx
, rtx
);
17751 rtx tmp
, dest
, zero
;
17757 unpack
= gen_loongson_punpckhbh
;
17759 unpack
= gen_loongson_punpcklbh
;
17760 cmpgt
= gen_loongson_pcmpgtb
;
17764 unpack
= gen_loongson_punpckhhw
;
17766 unpack
= gen_loongson_punpcklhw
;
17767 cmpgt
= gen_loongson_pcmpgth
;
17770 gcc_unreachable ();
17773 zero
= force_reg (imode
, CONST0_RTX (imode
));
17778 tmp
= gen_reg_rtx (imode
);
17779 emit_insn (cmpgt (tmp
, zero
, operands
[1]));
17782 dest
= gen_reg_rtx (imode
);
17783 emit_insn (unpack (dest
, operands
[1], tmp
));
17785 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
17788 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17791 mips_constant_elt_p (rtx x
)
17793 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
17796 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17799 mips_expand_vi_broadcast (enum machine_mode vmode
, rtx target
, rtx elt
)
17801 struct expand_vec_perm_d d
;
17805 if (elt
!= const0_rtx
)
17806 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
17808 elt
= gen_lowpart (DImode
, elt
);
17810 t1
= gen_reg_rtx (vmode
);
17814 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
17817 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
17820 gcc_unreachable ();
17823 memset (&d
, 0, sizeof (d
));
17828 d
.nelt
= GET_MODE_NUNITS (vmode
);
17829 d
.one_vector_p
= true;
17831 ok
= mips_expand_vec_perm_const_1 (&d
);
17835 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17836 elements of VALS with zeros, copy the constant vector to TARGET. */
17839 mips_expand_vi_constant (enum machine_mode vmode
, unsigned nelt
,
17840 rtx target
, rtx vals
)
17842 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
17845 for (i
= 0; i
< nelt
; ++i
)
17847 if (!mips_constant_elt_p (RTVEC_ELT (vec
, i
)))
17848 RTVEC_ELT (vec
, i
) = const0_rtx
;
17851 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
17855 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17858 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
17860 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
17862 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
17863 GEN_INT (one_var
)));
17866 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17869 mips_expand_vi_general (enum machine_mode vmode
, enum machine_mode imode
,
17870 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
17872 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
17873 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
17876 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
17878 for (i
= 0; i
< nelt
; ++i
)
17880 rtx x
= XVECEXP (vals
, 0, i
);
17881 if (!mips_constant_elt_p (x
))
17882 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
17885 emit_move_insn (target
, mem
);
17888 /* Expand a vector initialization. */
17891 mips_expand_vector_init (rtx target
, rtx vals
)
17893 enum machine_mode vmode
= GET_MODE (target
);
17894 enum machine_mode imode
= GET_MODE_INNER (vmode
);
17895 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
17896 unsigned nvar
= 0, one_var
= -1u;
17897 bool all_same
= true;
17900 for (i
= 0; i
< nelt
; ++i
)
17902 x
= XVECEXP (vals
, 0, i
);
17903 if (!mips_constant_elt_p (x
))
17904 nvar
++, one_var
= i
;
17905 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
17909 /* Load constants from the pool, or whatever's handy. */
17912 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
17916 /* For two-part initialization, always use CONCAT. */
17919 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
17920 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
17921 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
17922 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
17926 /* Loongson is the only cpu with vectors with more elements. */
17927 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
17929 /* If all values are identical, broadcast the value. */
17932 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
17936 /* If we've only got one non-variable V4HImode, use PINSRH. */
17937 if (nvar
== 1 && vmode
== V4HImode
)
17939 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
17943 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
17946 /* Expand a vector reduction. */
17949 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
17951 enum machine_mode vmode
= GET_MODE (in
);
17952 unsigned char perm2
[2];
17953 rtx last
, next
, fold
, x
;
17957 fold
= gen_reg_rtx (vmode
);
17961 /* Use PUL/PLU to produce { L, H } op { H, L }.
17962 By reversing the pair order, rather than a pure interleave high,
17963 we avoid erroneous exceptional conditions that we might otherwise
17964 produce from the computation of H op H. */
17967 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
17972 /* Use interleave to produce { H, L } op { H, H }. */
17973 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
17977 /* Perform the first reduction with interleave,
17978 and subsequent reductions with shifts. */
17979 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
17981 next
= gen_reg_rtx (vmode
);
17982 emit_insn (gen (next
, last
, fold
));
17985 fold
= gen_reg_rtx (vmode
);
17986 x
= force_reg (SImode
, GEN_INT (16));
17987 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
17991 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
17993 next
= gen_reg_rtx (vmode
);
17994 emit_insn (gen (next
, last
, fold
));
17997 fold
= gen_reg_rtx (vmode
);
17998 x
= force_reg (SImode
, GEN_INT (16));
17999 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18001 next
= gen_reg_rtx (vmode
);
18002 emit_insn (gen (next
, last
, fold
));
18005 fold
= gen_reg_rtx (vmode
);
18006 x
= force_reg (SImode
, GEN_INT (8));
18007 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
18011 gcc_unreachable ();
18014 emit_insn (gen (target
, last
, fold
));
18017 /* Expand a vector minimum/maximum. */
18020 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
18021 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
18023 enum machine_mode vmode
= GET_MODE (target
);
18026 tc
= gen_reg_rtx (vmode
);
18027 t0
= gen_reg_rtx (vmode
);
18028 t1
= gen_reg_rtx (vmode
);
18031 emit_insn (cmp (tc
, op0
, op1
));
18033 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
18034 emit_insn (gen_rtx_SET (VOIDmode
, t0
, x
));
18036 x
= gen_rtx_NOT (vmode
, tc
);
18037 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
18038 emit_insn (gen_rtx_SET (VOIDmode
, t1
, x
));
18040 x
= gen_rtx_IOR (vmode
, t0
, t1
);
18041 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
18044 /* Initialize the GCC target structure. */
18045 #undef TARGET_ASM_ALIGNED_HI_OP
18046 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18047 #undef TARGET_ASM_ALIGNED_SI_OP
18048 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18049 #undef TARGET_ASM_ALIGNED_DI_OP
18050 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18052 #undef TARGET_OPTION_OVERRIDE
18053 #define TARGET_OPTION_OVERRIDE mips_option_override
18055 #undef TARGET_LEGITIMIZE_ADDRESS
18056 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18058 #undef TARGET_ASM_FUNCTION_PROLOGUE
18059 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18060 #undef TARGET_ASM_FUNCTION_EPILOGUE
18061 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18062 #undef TARGET_ASM_SELECT_RTX_SECTION
18063 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18064 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18065 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18067 #undef TARGET_SCHED_INIT
18068 #define TARGET_SCHED_INIT mips_sched_init
18069 #undef TARGET_SCHED_REORDER
18070 #define TARGET_SCHED_REORDER mips_sched_reorder
18071 #undef TARGET_SCHED_REORDER2
18072 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18073 #undef TARGET_SCHED_VARIABLE_ISSUE
18074 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18075 #undef TARGET_SCHED_ADJUST_COST
18076 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18077 #undef TARGET_SCHED_ISSUE_RATE
18078 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18079 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18080 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18081 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18082 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18083 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18084 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18085 mips_multipass_dfa_lookahead
18086 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18087 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18088 mips_small_register_classes_for_mode_p
18090 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18091 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18093 #undef TARGET_INSERT_ATTRIBUTES
18094 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18095 #undef TARGET_MERGE_DECL_ATTRIBUTES
18096 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18097 #undef TARGET_SET_CURRENT_FUNCTION
18098 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18100 #undef TARGET_VALID_POINTER_MODE
18101 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18102 #undef TARGET_REGISTER_MOVE_COST
18103 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18104 #undef TARGET_MEMORY_MOVE_COST
18105 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18106 #undef TARGET_RTX_COSTS
18107 #define TARGET_RTX_COSTS mips_rtx_costs
18108 #undef TARGET_ADDRESS_COST
18109 #define TARGET_ADDRESS_COST mips_address_cost
18111 #undef TARGET_IN_SMALL_DATA_P
18112 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18114 #undef TARGET_MACHINE_DEPENDENT_REORG
18115 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18117 #undef TARGET_PREFERRED_RELOAD_CLASS
18118 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18120 #undef TARGET_EXPAND_TO_RTL_HOOK
18121 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18122 #undef TARGET_ASM_FILE_START
18123 #define TARGET_ASM_FILE_START mips_file_start
18124 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18125 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18126 #undef TARGET_ASM_CODE_END
18127 #define TARGET_ASM_CODE_END mips_code_end
18129 #undef TARGET_INIT_LIBFUNCS
18130 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18132 #undef TARGET_BUILD_BUILTIN_VA_LIST
18133 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18134 #undef TARGET_EXPAND_BUILTIN_VA_START
18135 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18136 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18137 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18139 #undef TARGET_PROMOTE_FUNCTION_MODE
18140 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18141 #undef TARGET_PROMOTE_PROTOTYPES
18142 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18144 #undef TARGET_FUNCTION_VALUE
18145 #define TARGET_FUNCTION_VALUE mips_function_value
18146 #undef TARGET_LIBCALL_VALUE
18147 #define TARGET_LIBCALL_VALUE mips_libcall_value
18148 #undef TARGET_FUNCTION_VALUE_REGNO_P
18149 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18150 #undef TARGET_RETURN_IN_MEMORY
18151 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18152 #undef TARGET_RETURN_IN_MSB
18153 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18155 #undef TARGET_ASM_OUTPUT_MI_THUNK
18156 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18157 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18158 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18160 #undef TARGET_PRINT_OPERAND
18161 #define TARGET_PRINT_OPERAND mips_print_operand
18162 #undef TARGET_PRINT_OPERAND_ADDRESS
18163 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18164 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18165 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18167 #undef TARGET_SETUP_INCOMING_VARARGS
18168 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18169 #undef TARGET_STRICT_ARGUMENT_NAMING
18170 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18171 #undef TARGET_MUST_PASS_IN_STACK
18172 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18173 #undef TARGET_PASS_BY_REFERENCE
18174 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18175 #undef TARGET_CALLEE_COPIES
18176 #define TARGET_CALLEE_COPIES mips_callee_copies
18177 #undef TARGET_ARG_PARTIAL_BYTES
18178 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18179 #undef TARGET_FUNCTION_ARG
18180 #define TARGET_FUNCTION_ARG mips_function_arg
18181 #undef TARGET_FUNCTION_ARG_ADVANCE
18182 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18183 #undef TARGET_FUNCTION_ARG_BOUNDARY
18184 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18186 #undef TARGET_MODE_REP_EXTENDED
18187 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18189 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18190 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18192 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18193 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18195 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18196 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18198 #undef TARGET_INIT_BUILTINS
18199 #define TARGET_INIT_BUILTINS mips_init_builtins
18200 #undef TARGET_BUILTIN_DECL
18201 #define TARGET_BUILTIN_DECL mips_builtin_decl
18202 #undef TARGET_EXPAND_BUILTIN
18203 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18205 #undef TARGET_HAVE_TLS
18206 #define TARGET_HAVE_TLS HAVE_AS_TLS
18208 #undef TARGET_CANNOT_FORCE_CONST_MEM
18209 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18211 #undef TARGET_LEGITIMATE_CONSTANT_P
18212 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18214 #undef TARGET_ENCODE_SECTION_INFO
18215 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18217 #undef TARGET_ATTRIBUTE_TABLE
18218 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18219 /* All our function attributes are related to how out-of-line copies should
18220 be compiled or called. They don't in themselves prevent inlining. */
18221 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18222 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18224 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18225 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18227 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18228 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18229 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18230 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18232 #undef TARGET_COMP_TYPE_ATTRIBUTES
18233 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18235 #ifdef HAVE_AS_DTPRELWORD
18236 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18237 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18239 #undef TARGET_DWARF_REGISTER_SPAN
18240 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18242 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18243 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18245 #undef TARGET_LEGITIMATE_ADDRESS_P
18246 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18248 #undef TARGET_FRAME_POINTER_REQUIRED
18249 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18251 #undef TARGET_CAN_ELIMINATE
18252 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18254 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18255 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18257 #undef TARGET_TRAMPOLINE_INIT
18258 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18260 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18261 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18263 #undef TARGET_SHIFT_TRUNCATION_MASK
18264 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18266 #undef TARGET_PREPARE_PCH_SAVE
18267 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18269 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18270 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18272 struct gcc_target targetm
= TARGET_INITIALIZER
;
18274 #include "gt-mips.h"