1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
36 #include "stringpool.h"
43 #include "diagnostic.h"
44 #include "insn-attr.h"
47 #include "fold-const.h"
49 #include "stor-layout.h"
55 #include "common/common-target.h"
56 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "target-globals.h"
62 #include "tree-pass.h"
67 /* This file should be included last. */
68 #include "target-def.h"
70 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
71 #define UNSPEC_ADDRESS_P(X) \
72 (GET_CODE (X) == UNSPEC \
73 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
74 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
76 /* Extract the symbol or label from UNSPEC wrapper X. */
77 #define UNSPEC_ADDRESS(X) \
80 /* Extract the symbol type from UNSPEC wrapper X. */
81 #define UNSPEC_ADDRESS_TYPE(X) \
82 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
84 /* The maximum distance between the top of the stack frame and the
85 value $sp has when we save and restore registers.
87 The value for normal-mode code must be a SMALL_OPERAND and must
88 preserve the maximum stack alignment. We therefore use a value
89 of 0x7ff0 in this case.
91 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
92 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
94 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
95 up to 0x7f8 bytes and can usually save or restore all the registers
96 that we need to save or restore. (Note that we can only use these
97 instructions for o32, for which the stack alignment is 8 bytes.)
99 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
100 RESTORE are not available. We can then use unextended instructions
101 to save and restore registers, and to allocate and deallocate the top
102 part of the frame. */
103 #define MIPS_MAX_FIRST_STACK_STEP \
104 (!TARGET_COMPRESSION ? 0x7ff0 \
105 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
106 : TARGET_64BIT ? 0x100 : 0x400)
108 /* True if INSN is a mips.md pattern or asm statement. */
109 /* ??? This test exists through the compiler, perhaps it should be
111 #define USEFUL_INSN_P(INSN) \
112 (NONDEBUG_INSN_P (INSN) \
113 && GET_CODE (PATTERN (INSN)) != USE \
114 && GET_CODE (PATTERN (INSN)) != CLOBBER)
116 /* If INSN is a delayed branch sequence, return the first instruction
117 in the sequence, otherwise return INSN itself. */
118 #define SEQ_BEGIN(INSN) \
119 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
120 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), 0, 0)) \
123 /* Likewise for the last instruction in a delayed branch sequence. */
124 #define SEQ_END(INSN) \
125 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
126 ? as_a <rtx_insn *> (XVECEXP (PATTERN (INSN), \
128 XVECLEN (PATTERN (INSN), 0) - 1)) \
131 /* Execute the following loop body with SUBINSN set to each instruction
132 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
133 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
134 for ((SUBINSN) = SEQ_BEGIN (INSN); \
135 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
136 (SUBINSN) = NEXT_INSN (SUBINSN))
138 /* True if bit BIT is set in VALUE. */
139 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
141 /* Return the opcode for a ptr_mode load of the form:
143 l[wd] DEST, OFFSET(BASE). */
144 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
145 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
150 /* Return the opcode to move register SRC into register DEST. */
151 #define MIPS_MOVE(DEST, SRC) \
152 ((TARGET_64BIT ? 0x2d : 0x21) \
156 /* Return the opcode for:
159 #define MIPS_LUI(DEST, VALUE) \
160 ((0xf << 26) | ((DEST) << 16) | (VALUE))
162 /* Return the opcode to jump to register DEST. When the JR opcode is not
163 available use JALR $0, DEST. */
164 #define MIPS_JR(DEST) \
165 (TARGET_CB_ALWAYS ? ((0x1b << 27) | ((DEST) << 16)) \
166 : (((DEST) << 21) | (ISA_HAS_JR ? 0x8 : 0x9)))
168 /* Return the opcode for:
170 bal . + (1 + OFFSET) * 4. */
171 #define MIPS_BAL(OFFSET) \
172 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
174 /* Return the usual opcode for a nop. */
177 /* Classifies an address.
180 A natural register + offset address. The register satisfies
181 mips_valid_base_register_p and the offset is a const_arith_operand.
184 A LO_SUM rtx. The first operand is a valid base register and
185 the second operand is a symbolic address.
188 A signed 16-bit constant address.
191 A constant symbolic address. */
192 enum mips_address_type
{
199 /* Macros to create an enumeration identifier for a function prototype. */
200 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
201 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
202 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
203 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
205 /* Classifies the prototype of a built-in function. */
206 enum mips_function_type
{
207 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
208 #include "config/mips/mips-ftypes.def"
209 #undef DEF_MIPS_FTYPE
213 /* Specifies how a built-in function should be converted into rtl. */
214 enum mips_builtin_type
{
215 /* The function corresponds directly to an .md pattern. The return
216 value is mapped to operand 0 and the arguments are mapped to
217 operands 1 and above. */
220 /* The function corresponds directly to an .md pattern. There is no return
221 value and the arguments are mapped to operands 0 and above. */
222 MIPS_BUILTIN_DIRECT_NO_TARGET
,
224 /* The function corresponds to a comparison instruction followed by
225 a mips_cond_move_tf_ps pattern. The first two arguments are the
226 values to compare and the second two arguments are the vector
227 operands for the movt.ps or movf.ps instruction (in assembly order). */
231 /* The function corresponds to a V2SF comparison instruction. Operand 0
232 of this instruction is the result of the comparison, which has mode
233 CCV2 or CCV4. The function arguments are mapped to operands 1 and
234 above. The function's return value is an SImode boolean that is
235 true under the following conditions:
237 MIPS_BUILTIN_CMP_ANY: one of the registers is true
238 MIPS_BUILTIN_CMP_ALL: all of the registers are true
239 MIPS_BUILTIN_CMP_LOWER: the first register is true
240 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
241 MIPS_BUILTIN_CMP_ANY
,
242 MIPS_BUILTIN_CMP_ALL
,
243 MIPS_BUILTIN_CMP_UPPER
,
244 MIPS_BUILTIN_CMP_LOWER
,
246 /* As above, but the instruction only sets a single $fcc register. */
247 MIPS_BUILTIN_CMP_SINGLE
,
249 /* The function corresponds to an MSA conditional branch instruction
250 combined with a compare instruction. */
251 MIPS_BUILTIN_MSA_TEST_BRANCH
,
253 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
254 MIPS_BUILTIN_BPOSGE32
257 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
258 #define MIPS_FP_CONDITIONS(MACRO) \
276 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
277 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
278 enum mips_fp_condition
{
279 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
281 #undef DECLARE_MIPS_COND
283 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
284 #define STRINGIFY(X) #X
285 static const char *const mips_fp_conditions
[] = {
286 MIPS_FP_CONDITIONS (STRINGIFY
)
290 /* A class used to control a comdat-style stub that we output in each
291 translation unit that needs it. */
292 class mips_one_only_stub
{
294 virtual ~mips_one_only_stub () {}
296 /* Return the name of the stub. */
297 virtual const char *get_name () = 0;
299 /* Output the body of the function to asm_out_file. */
300 virtual void output_body () = 0;
303 /* Tuning information that is automatically derived from other sources
304 (such as the scheduler). */
306 /* The architecture and tuning settings that this structure describes. */
310 /* True if this structure describes MIPS16 settings. */
313 /* True if the structure has been initialized. */
316 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
317 when optimizing for speed. */
318 bool fast_mult_zero_zero_p
;
321 /* Information about a single argument. */
322 struct mips_arg_info
{
323 /* True if the argument is passed in a floating-point register, or
324 would have been if we hadn't run out of registers. */
327 /* The number of words passed in registers, rounded up. */
328 unsigned int reg_words
;
330 /* For EABI, the offset of the first register from GP_ARG_FIRST or
331 FP_ARG_FIRST. For other ABIs, the offset of the first register from
332 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
333 comment for details).
335 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
337 unsigned int reg_offset
;
339 /* The number of words that must be passed on the stack, rounded up. */
340 unsigned int stack_words
;
342 /* The offset from the start of the stack overflow area of the argument's
343 first stack word. Only meaningful when STACK_WORDS is nonzero. */
344 unsigned int stack_offset
;
347 /* Information about an address described by mips_address_type.
353 REG is the base register and OFFSET is the constant offset.
356 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
357 is the type of symbol it references.
360 SYMBOL_TYPE is the type of symbol that the address references. */
361 struct mips_address_info
{
362 enum mips_address_type type
;
365 enum mips_symbol_type symbol_type
;
368 /* One stage in a constant building sequence. These sequences have
372 A = A CODE[1] VALUE[1]
373 A = A CODE[2] VALUE[2]
376 where A is an accumulator, each CODE[i] is a binary rtl operation
377 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
378 struct mips_integer_op
{
380 unsigned HOST_WIDE_INT value
;
383 /* The largest number of operations needed to load an integer constant.
384 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
385 When the lowest bit is clear, we can try, but reject a sequence with
386 an extra SLL at the end. */
387 #define MIPS_MAX_INTEGER_OPS 7
389 /* Information about a MIPS16e SAVE or RESTORE instruction. */
390 struct mips16e_save_restore_info
{
391 /* The number of argument registers saved by a SAVE instruction.
392 0 for RESTORE instructions. */
395 /* Bit X is set if the instruction saves or restores GPR X. */
398 /* The total number of bytes to allocate. */
402 /* Costs of various operations on the different architectures. */
404 struct mips_rtx_cost_data
406 unsigned short fp_add
;
407 unsigned short fp_mult_sf
;
408 unsigned short fp_mult_df
;
409 unsigned short fp_div_sf
;
410 unsigned short fp_div_df
;
411 unsigned short int_mult_si
;
412 unsigned short int_mult_di
;
413 unsigned short int_div_si
;
414 unsigned short int_div_di
;
415 unsigned short branch_cost
;
416 unsigned short memory_latency
;
419 /* Global variables for machine-dependent things. */
421 /* The -G setting, or the configuration's default small-data limit if
422 no -G option is given. */
423 static unsigned int mips_small_data_threshold
;
425 /* The number of file directives written by mips_output_filename. */
426 int num_source_filenames
;
428 /* The name that appeared in the last .file directive written by
429 mips_output_filename, or "" if mips_output_filename hasn't
430 written anything yet. */
431 const char *current_function_file
= "";
433 /* Arrays that map GCC register numbers to debugger register numbers. */
434 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
435 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
437 /* Information about the current function's epilogue, used only while
440 /* A list of queued REG_CFA_RESTORE notes. */
443 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
445 HOST_WIDE_INT cfa_offset
;
447 /* The offset of the CFA from the stack pointer while restoring
449 HOST_WIDE_INT cfa_restore_sp_offset
;
452 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
453 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
454 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
455 struct mips_asm_switch mips_noat
= { "at", 0 };
457 /* True if we're writing out a branch-likely instruction rather than a
459 static bool mips_branch_likely
;
461 /* The current instruction-set architecture. */
462 enum processor mips_arch
;
463 const struct mips_cpu_info
*mips_arch_info
;
465 /* The processor that we should tune the code for. */
466 enum processor mips_tune
;
467 const struct mips_cpu_info
*mips_tune_info
;
469 /* The ISA level associated with mips_arch. */
472 /* The ISA revision level. This is 0 for MIPS I to V and N for
476 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
477 static const struct mips_cpu_info
*mips_isa_option_info
;
479 /* Which cost information to use. */
480 static const struct mips_rtx_cost_data
*mips_cost
;
482 /* The ambient target flags, excluding MASK_MIPS16. */
483 static int mips_base_target_flags
;
485 /* The default compression mode. */
486 unsigned int mips_base_compression_flags
;
488 /* The ambient values of other global variables. */
489 static int mips_base_schedule_insns
; /* flag_schedule_insns */
490 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
491 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
492 static int mips_base_align_loops
; /* align_loops */
493 static int mips_base_align_jumps
; /* align_jumps */
494 static int mips_base_align_functions
; /* align_functions */
496 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
497 static bool mips_hard_regno_mode_ok_p
[MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
499 /* Index C is true if character C is a valid PRINT_OPERAND punctation
501 static bool mips_print_operand_punct
[256];
503 static GTY (()) int mips_output_filename_first_time
= 1;
505 /* mips_split_p[X] is true if symbols of type X can be split by
506 mips_split_symbol. */
507 bool mips_split_p
[NUM_SYMBOL_TYPES
];
509 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
510 can be split by mips_split_symbol. */
511 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
513 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
514 forced into a PC-relative constant pool. */
515 bool mips_use_pcrel_pool_p
[NUM_SYMBOL_TYPES
];
517 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
518 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
519 if they are matched by a special .md file pattern. */
520 const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
522 /* Likewise for HIGHs. */
523 const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
525 /* Target state for MIPS16. */
526 struct target_globals
*mips16_globals
;
528 /* Target state for MICROMIPS. */
529 struct target_globals
*micromips_globals
;
531 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
532 and returned from mips_sched_reorder2. */
533 static int cached_can_issue_more
;
535 /* The stubs for various MIPS16 support functions, if used. */
536 static mips_one_only_stub
*mips16_rdhwr_stub
;
537 static mips_one_only_stub
*mips16_get_fcsr_stub
;
538 static mips_one_only_stub
*mips16_set_fcsr_stub
;
540 /* Index R is the smallest register class that contains register R. */
541 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
542 LEA_REGS
, LEA_REGS
, M16_STORE_REGS
, V1_REG
,
543 M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
, M16_STORE_REGS
,
544 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
545 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
546 M16_REGS
, M16_STORE_REGS
, LEA_REGS
, LEA_REGS
,
547 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
548 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
549 LEA_REGS
, M16_SP_REGS
, LEA_REGS
, LEA_REGS
,
551 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
552 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
553 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
554 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
555 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
556 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
557 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
558 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
559 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
560 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
561 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
562 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
563 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
564 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
565 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
566 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
567 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
568 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
569 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
570 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
571 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
572 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
573 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
574 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
575 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
576 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
577 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
578 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
579 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
580 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
581 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
582 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
583 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
584 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
585 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
586 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
587 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
588 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
589 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
592 static tree
mips_handle_interrupt_attr (tree
*, tree
, tree
, int, bool *);
593 static tree
mips_handle_use_shadow_register_set_attr (tree
*, tree
, tree
, int,
596 /* The value of TARGET_ATTRIBUTE_TABLE. */
597 static const struct attribute_spec mips_attribute_table
[] = {
598 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
599 affects_type_identity, handler, exclude } */
600 { "long_call", 0, 0, false, true, true, false, NULL
, NULL
},
601 { "short_call", 0, 0, false, true, true, false, NULL
, NULL
},
602 { "far", 0, 0, false, true, true, false, NULL
, NULL
},
603 { "near", 0, 0, false, true, true, false, NULL
, NULL
},
604 /* We would really like to treat "mips16" and "nomips16" as type
605 attributes, but GCC doesn't provide the hooks we need to support
606 the right conversion rules. As declaration attributes, they affect
607 code generation but don't carry other semantics. */
608 { "mips16", 0, 0, true, false, false, false, NULL
, NULL
},
609 { "nomips16", 0, 0, true, false, false, false, NULL
, NULL
},
610 { "micromips", 0, 0, true, false, false, false, NULL
, NULL
},
611 { "nomicromips", 0, 0, true, false, false, false, NULL
, NULL
},
612 { "nocompression", 0, 0, true, false, false, false, NULL
, NULL
},
613 /* Allow functions to be specified as interrupt handlers */
614 { "interrupt", 0, 1, false, true, true, false, mips_handle_interrupt_attr
,
616 { "use_shadow_register_set", 0, 1, false, true, true, false,
617 mips_handle_use_shadow_register_set_attr
, NULL
},
618 { "keep_interrupts_masked", 0, 0, false, true, true, false, NULL
, NULL
},
619 { "use_debug_exception_return", 0, 0, false, true, true, false, NULL
, NULL
},
620 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
623 /* A table describing all the processors GCC knows about; see
624 mips-cpus.def for details. */
625 static const struct mips_cpu_info mips_cpu_info_table
[] = {
626 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
627 { NAME, CPU, ISA, FLAGS },
628 #include "mips-cpus.def"
632 /* Default costs. If these are used for a processor we should look
633 up the actual costs. */
634 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
635 COSTS_N_INSNS (7), /* fp_mult_sf */ \
636 COSTS_N_INSNS (8), /* fp_mult_df */ \
637 COSTS_N_INSNS (23), /* fp_div_sf */ \
638 COSTS_N_INSNS (36), /* fp_div_df */ \
639 COSTS_N_INSNS (10), /* int_mult_si */ \
640 COSTS_N_INSNS (10), /* int_mult_di */ \
641 COSTS_N_INSNS (69), /* int_div_si */ \
642 COSTS_N_INSNS (69), /* int_div_di */ \
643 2, /* branch_cost */ \
644 4 /* memory_latency */
646 /* Floating-point costs for processors without an FPU. Just assume that
647 all floating-point libcalls are very expensive. */
648 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
649 COSTS_N_INSNS (256), /* fp_mult_sf */ \
650 COSTS_N_INSNS (256), /* fp_mult_df */ \
651 COSTS_N_INSNS (256), /* fp_div_sf */ \
652 COSTS_N_INSNS (256) /* fp_div_df */
654 /* Costs to use when optimizing for size. */
655 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
656 COSTS_N_INSNS (1), /* fp_add */
657 COSTS_N_INSNS (1), /* fp_mult_sf */
658 COSTS_N_INSNS (1), /* fp_mult_df */
659 COSTS_N_INSNS (1), /* fp_div_sf */
660 COSTS_N_INSNS (1), /* fp_div_df */
661 COSTS_N_INSNS (1), /* int_mult_si */
662 COSTS_N_INSNS (1), /* int_mult_di */
663 COSTS_N_INSNS (1), /* int_div_si */
664 COSTS_N_INSNS (1), /* int_div_di */
666 4 /* memory_latency */
669 /* Costs to use when optimizing for speed, indexed by processor. */
670 static const struct mips_rtx_cost_data
671 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
673 COSTS_N_INSNS (2), /* fp_add */
674 COSTS_N_INSNS (4), /* fp_mult_sf */
675 COSTS_N_INSNS (5), /* fp_mult_df */
676 COSTS_N_INSNS (12), /* fp_div_sf */
677 COSTS_N_INSNS (19), /* fp_div_df */
678 COSTS_N_INSNS (12), /* int_mult_si */
679 COSTS_N_INSNS (12), /* int_mult_di */
680 COSTS_N_INSNS (35), /* int_div_si */
681 COSTS_N_INSNS (35), /* int_div_di */
683 4 /* memory_latency */
687 COSTS_N_INSNS (6), /* int_mult_si */
688 COSTS_N_INSNS (6), /* int_mult_di */
689 COSTS_N_INSNS (36), /* int_div_si */
690 COSTS_N_INSNS (36), /* int_div_di */
692 4 /* memory_latency */
696 COSTS_N_INSNS (36), /* int_mult_si */
697 COSTS_N_INSNS (36), /* int_mult_di */
698 COSTS_N_INSNS (37), /* int_div_si */
699 COSTS_N_INSNS (37), /* int_div_di */
701 4 /* memory_latency */
705 COSTS_N_INSNS (4), /* int_mult_si */
706 COSTS_N_INSNS (11), /* int_mult_di */
707 COSTS_N_INSNS (36), /* int_div_si */
708 COSTS_N_INSNS (68), /* int_div_di */
710 4 /* memory_latency */
713 COSTS_N_INSNS (4), /* fp_add */
714 COSTS_N_INSNS (4), /* fp_mult_sf */
715 COSTS_N_INSNS (5), /* fp_mult_df */
716 COSTS_N_INSNS (17), /* fp_div_sf */
717 COSTS_N_INSNS (32), /* fp_div_df */
718 COSTS_N_INSNS (4), /* int_mult_si */
719 COSTS_N_INSNS (11), /* int_mult_di */
720 COSTS_N_INSNS (36), /* int_div_si */
721 COSTS_N_INSNS (68), /* int_div_di */
723 4 /* memory_latency */
726 COSTS_N_INSNS (4), /* fp_add */
727 COSTS_N_INSNS (4), /* fp_mult_sf */
728 COSTS_N_INSNS (5), /* fp_mult_df */
729 COSTS_N_INSNS (17), /* fp_div_sf */
730 COSTS_N_INSNS (32), /* fp_div_df */
731 COSTS_N_INSNS (4), /* int_mult_si */
732 COSTS_N_INSNS (7), /* int_mult_di */
733 COSTS_N_INSNS (42), /* int_div_si */
734 COSTS_N_INSNS (72), /* int_div_di */
736 4 /* memory_latency */
740 COSTS_N_INSNS (5), /* int_mult_si */
741 COSTS_N_INSNS (5), /* int_mult_di */
742 COSTS_N_INSNS (41), /* int_div_si */
743 COSTS_N_INSNS (41), /* int_div_di */
745 4 /* memory_latency */
748 COSTS_N_INSNS (8), /* fp_add */
749 COSTS_N_INSNS (8), /* fp_mult_sf */
750 COSTS_N_INSNS (10), /* fp_mult_df */
751 COSTS_N_INSNS (34), /* fp_div_sf */
752 COSTS_N_INSNS (64), /* fp_div_df */
753 COSTS_N_INSNS (5), /* int_mult_si */
754 COSTS_N_INSNS (5), /* int_mult_di */
755 COSTS_N_INSNS (41), /* int_div_si */
756 COSTS_N_INSNS (41), /* int_div_di */
758 4 /* memory_latency */
761 COSTS_N_INSNS (4), /* fp_add */
762 COSTS_N_INSNS (4), /* fp_mult_sf */
763 COSTS_N_INSNS (5), /* fp_mult_df */
764 COSTS_N_INSNS (17), /* fp_div_sf */
765 COSTS_N_INSNS (32), /* fp_div_df */
766 COSTS_N_INSNS (5), /* int_mult_si */
767 COSTS_N_INSNS (5), /* int_mult_di */
768 COSTS_N_INSNS (41), /* int_div_si */
769 COSTS_N_INSNS (41), /* int_div_di */
771 4 /* memory_latency */
775 COSTS_N_INSNS (5), /* int_mult_si */
776 COSTS_N_INSNS (5), /* int_mult_di */
777 COSTS_N_INSNS (41), /* int_div_si */
778 COSTS_N_INSNS (41), /* int_div_di */
780 4 /* memory_latency */
783 COSTS_N_INSNS (8), /* fp_add */
784 COSTS_N_INSNS (8), /* fp_mult_sf */
785 COSTS_N_INSNS (10), /* fp_mult_df */
786 COSTS_N_INSNS (34), /* fp_div_sf */
787 COSTS_N_INSNS (64), /* fp_div_df */
788 COSTS_N_INSNS (5), /* int_mult_si */
789 COSTS_N_INSNS (5), /* int_mult_di */
790 COSTS_N_INSNS (41), /* int_div_si */
791 COSTS_N_INSNS (41), /* int_div_di */
793 4 /* memory_latency */
796 COSTS_N_INSNS (4), /* fp_add */
797 COSTS_N_INSNS (4), /* fp_mult_sf */
798 COSTS_N_INSNS (5), /* fp_mult_df */
799 COSTS_N_INSNS (17), /* fp_div_sf */
800 COSTS_N_INSNS (32), /* fp_div_df */
801 COSTS_N_INSNS (5), /* int_mult_si */
802 COSTS_N_INSNS (5), /* int_mult_di */
803 COSTS_N_INSNS (41), /* int_div_si */
804 COSTS_N_INSNS (41), /* int_div_di */
806 4 /* memory_latency */
809 COSTS_N_INSNS (6), /* fp_add */
810 COSTS_N_INSNS (6), /* fp_mult_sf */
811 COSTS_N_INSNS (7), /* fp_mult_df */
812 COSTS_N_INSNS (25), /* fp_div_sf */
813 COSTS_N_INSNS (48), /* fp_div_df */
814 COSTS_N_INSNS (5), /* int_mult_si */
815 COSTS_N_INSNS (5), /* int_mult_di */
816 COSTS_N_INSNS (41), /* int_div_si */
817 COSTS_N_INSNS (41), /* int_div_di */
819 4 /* memory_latency */
836 COSTS_N_INSNS (5), /* int_mult_si */
837 COSTS_N_INSNS (5), /* int_mult_di */
838 COSTS_N_INSNS (72), /* int_div_si */
839 COSTS_N_INSNS (72), /* int_div_di */
841 4 /* memory_latency */
846 COSTS_N_INSNS (6), /* int_mult_si */
847 COSTS_N_INSNS (6), /* int_mult_di */
848 COSTS_N_INSNS (18), /* int_div_si */
849 COSTS_N_INSNS (35), /* int_div_di */
851 4 /* memory_latency */
855 COSTS_N_INSNS (6), /* fp_add */
856 COSTS_N_INSNS (6), /* fp_mult_sf */
857 COSTS_N_INSNS (7), /* fp_mult_df */
858 COSTS_N_INSNS (25), /* fp_div_sf */
859 COSTS_N_INSNS (48), /* fp_div_df */
860 COSTS_N_INSNS (6), /* int_mult_si */
861 COSTS_N_INSNS (6), /* int_mult_di */
862 COSTS_N_INSNS (18), /* int_div_si */
863 COSTS_N_INSNS (35), /* int_div_di */
865 4 /* memory_latency */
868 COSTS_N_INSNS (2), /* fp_add */
869 COSTS_N_INSNS (4), /* fp_mult_sf */
870 COSTS_N_INSNS (5), /* fp_mult_df */
871 COSTS_N_INSNS (12), /* fp_div_sf */
872 COSTS_N_INSNS (19), /* fp_div_df */
873 COSTS_N_INSNS (2), /* int_mult_si */
874 COSTS_N_INSNS (2), /* int_mult_di */
875 COSTS_N_INSNS (35), /* int_div_si */
876 COSTS_N_INSNS (35), /* int_div_di */
878 4 /* memory_latency */
881 COSTS_N_INSNS (3), /* fp_add */
882 COSTS_N_INSNS (5), /* fp_mult_sf */
883 COSTS_N_INSNS (6), /* fp_mult_df */
884 COSTS_N_INSNS (15), /* fp_div_sf */
885 COSTS_N_INSNS (16), /* fp_div_df */
886 COSTS_N_INSNS (17), /* int_mult_si */
887 COSTS_N_INSNS (17), /* int_mult_di */
888 COSTS_N_INSNS (38), /* int_div_si */
889 COSTS_N_INSNS (38), /* int_div_di */
891 6 /* memory_latency */
894 COSTS_N_INSNS (6), /* fp_add */
895 COSTS_N_INSNS (7), /* fp_mult_sf */
896 COSTS_N_INSNS (8), /* fp_mult_df */
897 COSTS_N_INSNS (23), /* fp_div_sf */
898 COSTS_N_INSNS (36), /* fp_div_df */
899 COSTS_N_INSNS (10), /* int_mult_si */
900 COSTS_N_INSNS (10), /* int_mult_di */
901 COSTS_N_INSNS (69), /* int_div_si */
902 COSTS_N_INSNS (69), /* int_div_di */
904 6 /* memory_latency */
916 /* The only costs that appear to be updated here are
917 integer multiplication. */
919 COSTS_N_INSNS (4), /* int_mult_si */
920 COSTS_N_INSNS (6), /* int_mult_di */
921 COSTS_N_INSNS (69), /* int_div_si */
922 COSTS_N_INSNS (69), /* int_div_di */
924 4 /* memory_latency */
939 COSTS_N_INSNS (6), /* fp_add */
940 COSTS_N_INSNS (4), /* fp_mult_sf */
941 COSTS_N_INSNS (5), /* fp_mult_df */
942 COSTS_N_INSNS (23), /* fp_div_sf */
943 COSTS_N_INSNS (36), /* fp_div_df */
944 COSTS_N_INSNS (5), /* int_mult_si */
945 COSTS_N_INSNS (5), /* int_mult_di */
946 COSTS_N_INSNS (36), /* int_div_si */
947 COSTS_N_INSNS (36), /* int_div_di */
949 4 /* memory_latency */
952 COSTS_N_INSNS (6), /* fp_add */
953 COSTS_N_INSNS (5), /* fp_mult_sf */
954 COSTS_N_INSNS (6), /* fp_mult_df */
955 COSTS_N_INSNS (30), /* fp_div_sf */
956 COSTS_N_INSNS (59), /* fp_div_df */
957 COSTS_N_INSNS (3), /* int_mult_si */
958 COSTS_N_INSNS (4), /* int_mult_di */
959 COSTS_N_INSNS (42), /* int_div_si */
960 COSTS_N_INSNS (74), /* int_div_di */
962 4 /* memory_latency */
965 COSTS_N_INSNS (6), /* fp_add */
966 COSTS_N_INSNS (5), /* fp_mult_sf */
967 COSTS_N_INSNS (6), /* fp_mult_df */
968 COSTS_N_INSNS (30), /* fp_div_sf */
969 COSTS_N_INSNS (59), /* fp_div_df */
970 COSTS_N_INSNS (5), /* int_mult_si */
971 COSTS_N_INSNS (9), /* int_mult_di */
972 COSTS_N_INSNS (42), /* int_div_si */
973 COSTS_N_INSNS (74), /* int_div_di */
975 4 /* memory_latency */
978 COSTS_N_INSNS (4), /* fp_add */
979 COSTS_N_INSNS (4), /* fp_mult_sf */
980 COSTS_N_INSNS (256), /* fp_mult_df */
981 COSTS_N_INSNS (8), /* fp_div_sf */
982 COSTS_N_INSNS (256), /* fp_div_df */
983 COSTS_N_INSNS (4), /* int_mult_si */
984 COSTS_N_INSNS (256), /* int_mult_di */
985 COSTS_N_INSNS (37), /* int_div_si */
986 COSTS_N_INSNS (256), /* int_div_di */
988 4 /* memory_latency */
991 /* The only costs that are changed here are
992 integer multiplication. */
993 COSTS_N_INSNS (6), /* fp_add */
994 COSTS_N_INSNS (7), /* fp_mult_sf */
995 COSTS_N_INSNS (8), /* fp_mult_df */
996 COSTS_N_INSNS (23), /* fp_div_sf */
997 COSTS_N_INSNS (36), /* fp_div_df */
998 COSTS_N_INSNS (5), /* int_mult_si */
999 COSTS_N_INSNS (9), /* int_mult_di */
1000 COSTS_N_INSNS (69), /* int_div_si */
1001 COSTS_N_INSNS (69), /* int_div_di */
1002 1, /* branch_cost */
1003 4 /* memory_latency */
1009 /* The only costs that are changed here are
1010 integer multiplication. */
1011 COSTS_N_INSNS (6), /* fp_add */
1012 COSTS_N_INSNS (7), /* fp_mult_sf */
1013 COSTS_N_INSNS (8), /* fp_mult_df */
1014 COSTS_N_INSNS (23), /* fp_div_sf */
1015 COSTS_N_INSNS (36), /* fp_div_df */
1016 COSTS_N_INSNS (3), /* int_mult_si */
1017 COSTS_N_INSNS (8), /* int_mult_di */
1018 COSTS_N_INSNS (69), /* int_div_si */
1019 COSTS_N_INSNS (69), /* int_div_di */
1020 1, /* branch_cost */
1021 4 /* memory_latency */
1024 COSTS_N_INSNS (2), /* fp_add */
1025 COSTS_N_INSNS (2), /* fp_mult_sf */
1026 COSTS_N_INSNS (2), /* fp_mult_df */
1027 COSTS_N_INSNS (12), /* fp_div_sf */
1028 COSTS_N_INSNS (19), /* fp_div_df */
1029 COSTS_N_INSNS (5), /* int_mult_si */
1030 COSTS_N_INSNS (9), /* int_mult_di */
1031 COSTS_N_INSNS (34), /* int_div_si */
1032 COSTS_N_INSNS (66), /* int_div_di */
1033 1, /* branch_cost */
1034 4 /* memory_latency */
1037 /* These costs are the same as the SB-1A below. */
1038 COSTS_N_INSNS (4), /* fp_add */
1039 COSTS_N_INSNS (4), /* fp_mult_sf */
1040 COSTS_N_INSNS (4), /* fp_mult_df */
1041 COSTS_N_INSNS (24), /* fp_div_sf */
1042 COSTS_N_INSNS (32), /* fp_div_df */
1043 COSTS_N_INSNS (3), /* int_mult_si */
1044 COSTS_N_INSNS (4), /* int_mult_di */
1045 COSTS_N_INSNS (36), /* int_div_si */
1046 COSTS_N_INSNS (68), /* int_div_di */
1047 1, /* branch_cost */
1048 4 /* memory_latency */
1051 /* These costs are the same as the SB-1 above. */
1052 COSTS_N_INSNS (4), /* fp_add */
1053 COSTS_N_INSNS (4), /* fp_mult_sf */
1054 COSTS_N_INSNS (4), /* fp_mult_df */
1055 COSTS_N_INSNS (24), /* fp_div_sf */
1056 COSTS_N_INSNS (32), /* fp_div_df */
1057 COSTS_N_INSNS (3), /* int_mult_si */
1058 COSTS_N_INSNS (4), /* int_mult_di */
1059 COSTS_N_INSNS (36), /* int_div_si */
1060 COSTS_N_INSNS (68), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1069 COSTS_N_INSNS (8), /* int_mult_si */
1070 COSTS_N_INSNS (8), /* int_mult_di */
1071 COSTS_N_INSNS (72), /* int_div_si */
1072 COSTS_N_INSNS (72), /* int_div_di */
1073 1, /* branch_cost */
1074 4 /* memory_latency */
1077 /* These costs are the same as 5KF above. */
1078 COSTS_N_INSNS (4), /* fp_add */
1079 COSTS_N_INSNS (4), /* fp_mult_sf */
1080 COSTS_N_INSNS (5), /* fp_mult_df */
1081 COSTS_N_INSNS (17), /* fp_div_sf */
1082 COSTS_N_INSNS (32), /* fp_div_df */
1083 COSTS_N_INSNS (4), /* int_mult_si */
1084 COSTS_N_INSNS (11), /* int_mult_di */
1085 COSTS_N_INSNS (36), /* int_div_si */
1086 COSTS_N_INSNS (68), /* int_div_di */
1087 1, /* branch_cost */
1088 4 /* memory_latency */
1091 COSTS_N_INSNS (4), /* fp_add */
1092 COSTS_N_INSNS (5), /* fp_mult_sf */
1093 COSTS_N_INSNS (5), /* fp_mult_df */
1094 COSTS_N_INSNS (17), /* fp_div_sf */
1095 COSTS_N_INSNS (17), /* fp_div_df */
1096 COSTS_N_INSNS (5), /* int_mult_si */
1097 COSTS_N_INSNS (5), /* int_mult_di */
1098 COSTS_N_INSNS (8), /* int_div_si */
1099 COSTS_N_INSNS (8), /* int_div_di */
1100 2, /* branch_cost */
1101 4 /* memory_latency */
1104 COSTS_N_INSNS (4), /* fp_add */
1105 COSTS_N_INSNS (4), /* fp_mult_sf */
1106 COSTS_N_INSNS (5), /* fp_mult_df */
1107 COSTS_N_INSNS (17), /* fp_div_sf */
1108 COSTS_N_INSNS (32), /* fp_div_df */
1109 COSTS_N_INSNS (5), /* int_mult_si */
1110 COSTS_N_INSNS (5), /* int_mult_di */
1111 COSTS_N_INSNS (34), /* int_div_si */
1112 COSTS_N_INSNS (68), /* int_div_di */
1113 1, /* branch_cost */
1114 4 /* memory_latency */
1117 COSTS_N_INSNS (4), /* fp_add */
1118 COSTS_N_INSNS (5), /* fp_mult_sf */
1119 COSTS_N_INSNS (5), /* fp_mult_df */
1120 COSTS_N_INSNS (32), /* fp_div_sf */
1121 COSTS_N_INSNS (32), /* fp_div_df */
1122 COSTS_N_INSNS (5), /* int_mult_si */
1123 COSTS_N_INSNS (5), /* int_mult_di */
1124 COSTS_N_INSNS (36), /* int_div_si */
1125 COSTS_N_INSNS (36), /* int_div_di */
1126 2, /* branch_cost */
1127 4 /* memory_latency */
1131 static rtx
mips_find_pic_call_symbol (rtx_insn
*, rtx
, bool);
1132 static int mips_register_move_cost (machine_mode
, reg_class_t
,
1134 static unsigned int mips_function_arg_boundary (machine_mode
, const_tree
);
1135 static rtx
mips_gen_const_int_vector_shuffle (machine_mode
, int);
1137 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1138 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1139 static GTY (()) hash_map
<nofree_string_hash
, bool> *mflip_mips16_htab
;
1141 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1142 mode, false if it should next add an attribute for the opposite mode. */
1143 static GTY(()) bool mips16_flipper
;
1145 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1146 for -mflip-mips16. Return true if it should use "mips16" and false if
1147 it should use "nomips16". */
1150 mflip_mips16_use_mips16_p (tree decl
)
1153 bool base_is_mips16
= (mips_base_compression_flags
& MASK_MIPS16
) != 0;
1155 /* Use the opposite of the command-line setting for anonymous decls. */
1156 if (!DECL_NAME (decl
))
1157 return !base_is_mips16
;
1159 if (!mflip_mips16_htab
)
1160 mflip_mips16_htab
= hash_map
<nofree_string_hash
, bool>::create_ggc (37);
1162 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1165 bool *slot
= &mflip_mips16_htab
->get_or_insert (name
, &existed
);
1168 mips16_flipper
= !mips16_flipper
;
1169 *slot
= mips16_flipper
? !base_is_mips16
: base_is_mips16
;
1174 /* Predicates to test for presence of "near"/"short_call" and "far"/"long_call"
1175 attributes on the given TYPE. */
1178 mips_near_type_p (const_tree type
)
1180 return (lookup_attribute ("short_call", TYPE_ATTRIBUTES (type
)) != NULL
1181 || lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
);
1185 mips_far_type_p (const_tree type
)
1187 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1188 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1192 /* Check if the interrupt attribute is set for a function. */
1195 mips_interrupt_type_p (tree type
)
1197 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1200 /* Return the mask for the "interrupt" attribute. */
1202 static enum mips_int_mask
1203 mips_interrupt_mask (tree type
)
1205 tree attr
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
));
1209 /* For missing attributes or no arguments then return 'eic' as a safe
1212 return INT_MASK_EIC
;
1214 args
= TREE_VALUE (attr
);
1217 return INT_MASK_EIC
;
1219 cst
= TREE_VALUE (args
);
1221 if (strcmp (TREE_STRING_POINTER (cst
), "eic") == 0)
1222 return INT_MASK_EIC
;
1224 /* The validation code in mips_handle_interrupt_attr guarantees that the
1225 argument is now in the form:
1226 vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5). */
1227 str
= TREE_STRING_POINTER (cst
);
1229 gcc_assert (strlen (str
) == strlen ("vector=sw0"));
1232 return (enum mips_int_mask
) (INT_MASK_SW0
+ (str
[9] - '0'));
1234 return (enum mips_int_mask
) (INT_MASK_HW0
+ (str
[9] - '0'));
1237 /* Return the mips_shadow_set if the "use_shadow_register_set" attribute is
1238 set for a function. */
1240 static enum mips_shadow_set
1241 mips_use_shadow_register_set (tree type
)
1243 tree attr
= lookup_attribute ("use_shadow_register_set",
1244 TYPE_ATTRIBUTES (type
));
1247 /* The validation code in mips_handle_use_shadow_register_set_attr guarantees
1248 that if an argument is present then it means: Assume the shadow register
1249 set has a valid stack pointer in it. */
1251 return SHADOW_SET_NO
;
1253 args
= TREE_VALUE (attr
);
1256 return SHADOW_SET_YES
;
1258 return SHADOW_SET_INTSTACK
;
1261 /* Check if the attribute to keep interrupts masked is set for a function. */
1264 mips_keep_interrupts_masked_p (tree type
)
1266 return lookup_attribute ("keep_interrupts_masked",
1267 TYPE_ATTRIBUTES (type
)) != NULL
;
1270 /* Check if the attribute to use debug exception return is set for
1274 mips_use_debug_exception_return_p (tree type
)
1276 return lookup_attribute ("use_debug_exception_return",
1277 TYPE_ATTRIBUTES (type
)) != NULL
;
1280 /* Return the set of compression modes that are explicitly required
1281 by the attributes in ATTRIBUTES. */
1284 mips_get_compress_on_flags (tree attributes
)
1286 unsigned int flags
= 0;
1288 if (lookup_attribute ("mips16", attributes
) != NULL
)
1289 flags
|= MASK_MIPS16
;
1291 if (lookup_attribute ("micromips", attributes
) != NULL
)
1292 flags
|= MASK_MICROMIPS
;
1297 /* Return the set of compression modes that are explicitly forbidden
1298 by the attributes in ATTRIBUTES. */
1301 mips_get_compress_off_flags (tree attributes
)
1303 unsigned int flags
= 0;
1305 if (lookup_attribute ("nocompression", attributes
) != NULL
)
1306 flags
|= MASK_MIPS16
| MASK_MICROMIPS
;
1308 if (lookup_attribute ("nomips16", attributes
) != NULL
)
1309 flags
|= MASK_MIPS16
;
1311 if (lookup_attribute ("nomicromips", attributes
) != NULL
)
1312 flags
|= MASK_MICROMIPS
;
1317 /* Return the compression mode that should be used for function DECL.
1318 Return the ambient setting if DECL is null. */
1321 mips_get_compress_mode (tree decl
)
1323 unsigned int flags
, force_on
;
1325 flags
= mips_base_compression_flags
;
1328 /* Nested functions must use the same frame pointer as their
1329 parent and must therefore use the same ISA mode. */
1330 tree parent
= decl_function_context (decl
);
1333 force_on
= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1336 flags
&= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1341 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1345 mips_get_compress_on_name (unsigned int flags
)
1347 if (flags
== MASK_MIPS16
)
1352 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1356 mips_get_compress_off_name (unsigned int flags
)
1358 if (flags
== MASK_MIPS16
)
1360 if (flags
== MASK_MICROMIPS
)
1361 return "nomicromips";
1362 return "nocompression";
1365 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1368 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1370 /* Disallow mixed near/far attributes. */
1371 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1373 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1378 /* Implement TARGET_INSERT_ATTRIBUTES. */
1381 mips_insert_attributes (tree decl
, tree
*attributes
)
1384 unsigned int compression_flags
, nocompression_flags
;
1386 /* Check for "mips16" and "nomips16" attributes. */
1387 compression_flags
= mips_get_compress_on_flags (*attributes
);
1388 nocompression_flags
= mips_get_compress_off_flags (*attributes
);
1390 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1392 if (nocompression_flags
)
1393 error ("%qs attribute only applies to functions",
1394 mips_get_compress_off_name (nocompression_flags
));
1396 if (compression_flags
)
1397 error ("%qs attribute only applies to functions",
1398 mips_get_compress_on_name (nocompression_flags
));
1402 compression_flags
|= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
));
1403 nocompression_flags
|=
1404 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
));
1406 if (compression_flags
&& nocompression_flags
)
1407 error ("%qE cannot have both %qs and %qs attributes",
1408 DECL_NAME (decl
), mips_get_compress_on_name (compression_flags
),
1409 mips_get_compress_off_name (nocompression_flags
));
1411 if (compression_flags
& MASK_MIPS16
1412 && compression_flags
& MASK_MICROMIPS
)
1413 error ("%qE cannot have both %qs and %qs attributes",
1414 DECL_NAME (decl
), "mips16", "micromips");
1416 if (TARGET_FLIP_MIPS16
1417 && !DECL_ARTIFICIAL (decl
)
1418 && compression_flags
== 0
1419 && nocompression_flags
== 0)
1421 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1422 "mips16" attribute, arbitrarily pick one. We must pick the same
1423 setting for duplicate declarations of a function. */
1424 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1425 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1426 name
= "nomicromips";
1427 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1432 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1435 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1439 diff
= (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl
))
1440 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl
)));
1442 error ("%qE redeclared with conflicting %qs attributes",
1443 DECL_NAME (newdecl
), mips_get_compress_on_name (diff
));
1445 diff
= (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl
))
1446 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl
)));
1448 error ("%qE redeclared with conflicting %qs attributes",
1449 DECL_NAME (newdecl
), mips_get_compress_off_name (diff
));
1451 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1452 DECL_ATTRIBUTES (newdecl
));
1455 /* Implement TARGET_CAN_INLINE_P. */
1458 mips_can_inline_p (tree caller
, tree callee
)
1460 if (mips_get_compress_mode (callee
) != mips_get_compress_mode (caller
))
1462 return default_target_can_inline_p (caller
, callee
);
1465 /* Handle an "interrupt" attribute with an optional argument. */
1468 mips_handle_interrupt_attr (tree
*node ATTRIBUTE_UNUSED
, tree name
, tree args
,
1469 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1471 /* Check for an argument. */
1472 if (is_attribute_p ("interrupt", name
) && args
!= NULL
)
1476 cst
= TREE_VALUE (args
);
1477 if (TREE_CODE (cst
) != STRING_CST
)
1479 warning (OPT_Wattributes
,
1480 "%qE attribute requires a string argument",
1482 *no_add_attrs
= true;
1484 else if (strcmp (TREE_STRING_POINTER (cst
), "eic") != 0
1485 && strncmp (TREE_STRING_POINTER (cst
), "vector=", 7) != 0)
1487 warning (OPT_Wattributes
,
1488 "argument to %qE attribute is neither eic, nor "
1489 "vector=<line>", name
);
1490 *no_add_attrs
= true;
1492 else if (strncmp (TREE_STRING_POINTER (cst
), "vector=", 7) == 0)
1494 const char *arg
= TREE_STRING_POINTER (cst
) + 7;
1496 /* Acceptable names are: sw0,sw1,hw0,hw1,hw2,hw3,hw4,hw5. */
1497 if (strlen (arg
) != 3
1498 || (arg
[0] != 's' && arg
[0] != 'h')
1500 || (arg
[0] == 's' && arg
[2] != '0' && arg
[2] != '1')
1501 || (arg
[0] == 'h' && (arg
[2] < '0' || arg
[2] > '5')))
1503 warning (OPT_Wattributes
,
1504 "interrupt vector to %qE attribute is not "
1505 "vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5)",
1507 *no_add_attrs
= true;
1517 /* Handle a "use_shadow_register_set" attribute with an optional argument. */
1520 mips_handle_use_shadow_register_set_attr (tree
*node ATTRIBUTE_UNUSED
,
1521 tree name
, tree args
,
1522 int flags ATTRIBUTE_UNUSED
,
1525 /* Check for an argument. */
1526 if (is_attribute_p ("use_shadow_register_set", name
) && args
!= NULL
)
1530 cst
= TREE_VALUE (args
);
1531 if (TREE_CODE (cst
) != STRING_CST
)
1533 warning (OPT_Wattributes
,
1534 "%qE attribute requires a string argument",
1536 *no_add_attrs
= true;
1538 else if (strcmp (TREE_STRING_POINTER (cst
), "intstack") != 0)
1540 warning (OPT_Wattributes
,
1541 "argument to %qE attribute is not intstack", name
);
1542 *no_add_attrs
= true;
1551 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1552 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1555 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1557 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1559 *base_ptr
= XEXP (x
, 0);
1560 *offset_ptr
= INTVAL (XEXP (x
, 1));
1569 static unsigned int mips_build_integer (struct mips_integer_op
*,
1570 unsigned HOST_WIDE_INT
);
1572 /* A subroutine of mips_build_integer, with the same interface.
1573 Assume that the final action in the sequence should be a left shift. */
1576 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1578 unsigned int i
, shift
;
1580 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1581 since signed numbers are easier to load than unsigned ones. */
1583 while ((value
& 1) == 0)
1584 value
/= 2, shift
++;
1586 i
= mips_build_integer (codes
, value
);
1587 codes
[i
].code
= ASHIFT
;
1588 codes
[i
].value
= shift
;
1592 /* As for mips_build_shift, but assume that the final action will be
1593 an IOR or PLUS operation. */
1596 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1598 unsigned HOST_WIDE_INT high
;
1601 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1602 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1604 /* The constant is too complex to load with a simple LUI/ORI pair,
1605 so we want to give the recursive call as many trailing zeros as
1606 possible. In this case, we know bit 16 is set and that the
1607 low 16 bits form a negative number. If we subtract that number
1608 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1609 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1610 codes
[i
].code
= PLUS
;
1611 codes
[i
].value
= CONST_LOW_PART (value
);
1615 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1616 bits gives a value with at least 17 trailing zeros. */
1617 i
= mips_build_integer (codes
, high
);
1618 codes
[i
].code
= IOR
;
1619 codes
[i
].value
= value
& 0xffff;
1624 /* Fill CODES with a sequence of rtl operations to load VALUE.
1625 Return the number of operations needed. */
1628 mips_build_integer (struct mips_integer_op
*codes
,
1629 unsigned HOST_WIDE_INT value
)
1631 if (SMALL_OPERAND (value
)
1632 || SMALL_OPERAND_UNSIGNED (value
)
1633 || LUI_OPERAND (value
))
1635 /* The value can be loaded with a single instruction. */
1636 codes
[0].code
= UNKNOWN
;
1637 codes
[0].value
= value
;
1640 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1642 /* Either the constant is a simple LUI/ORI combination or its
1643 lowest bit is set. We don't want to shift in this case. */
1644 return mips_build_lower (codes
, value
);
1646 else if ((value
& 0xffff) == 0)
1648 /* The constant will need at least three actions. The lowest
1649 16 bits are clear, so the final action will be a shift. */
1650 return mips_build_shift (codes
, value
);
1654 /* The final action could be a shift, add or inclusive OR.
1655 Rather than use a complex condition to select the best
1656 approach, try both mips_build_shift and mips_build_lower
1657 and pick the one that gives the shortest sequence.
1658 Note that this case is only used once per constant. */
1659 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1660 unsigned int cost
, alt_cost
;
1662 cost
= mips_build_shift (codes
, value
);
1663 alt_cost
= mips_build_lower (alt_codes
, value
);
1664 if (alt_cost
< cost
)
1666 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1673 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1676 mips_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1678 return mips_const_insns (x
) > 0;
1681 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1684 mips16_stub_function (const char *name
)
1688 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
1689 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
1693 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1694 support function. */
1697 mips16_stub_call_address (mips_one_only_stub
*stub
)
1699 rtx fn
= mips16_stub_function (stub
->get_name ());
1700 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_LOCAL
;
1701 if (!call_insn_operand (fn
, VOIDmode
))
1702 fn
= force_reg (Pmode
, fn
);
1706 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1708 class mips16_rdhwr_one_only_stub
: public mips_one_only_stub
1710 virtual const char *get_name ();
1711 virtual void output_body ();
1715 mips16_rdhwr_one_only_stub::get_name ()
1717 return "__mips16_rdhwr";
1721 mips16_rdhwr_one_only_stub::output_body ()
1723 fprintf (asm_out_file
,
1725 "\t.set\tmips32r2\n"
1726 "\t.set\tnoreorder\n"
1732 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1733 class mips16_get_fcsr_one_only_stub
: public mips_one_only_stub
1735 virtual const char *get_name ();
1736 virtual void output_body ();
1740 mips16_get_fcsr_one_only_stub::get_name ()
1742 return "__mips16_get_fcsr";
1746 mips16_get_fcsr_one_only_stub::output_body ()
1748 fprintf (asm_out_file
,
1750 "\tj\t$31\n", reg_names
[GET_FCSR_REGNUM
]);
1753 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1754 class mips16_set_fcsr_one_only_stub
: public mips_one_only_stub
1756 virtual const char *get_name ();
1757 virtual void output_body ();
1761 mips16_set_fcsr_one_only_stub::get_name ()
1763 return "__mips16_set_fcsr";
1767 mips16_set_fcsr_one_only_stub::output_body ()
1769 fprintf (asm_out_file
,
1771 "\tj\t$31\n", reg_names
[SET_FCSR_REGNUM
]);
1774 /* Return true if symbols of type TYPE require a GOT access. */
1777 mips_got_symbol_type_p (enum mips_symbol_type type
)
1781 case SYMBOL_GOT_PAGE_OFST
:
1782 case SYMBOL_GOT_DISP
:
1790 /* Return true if X is a thread-local symbol. */
1793 mips_tls_symbol_p (rtx x
)
1795 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1798 /* Return true if SYMBOL_REF X is associated with a global symbol
1799 (in the STB_GLOBAL sense). */
1802 mips_global_symbol_p (const_rtx x
)
1804 const_tree decl
= SYMBOL_REF_DECL (x
);
1807 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1809 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1810 or weak symbols. Relocations in the object file will be against
1811 the target symbol, so it's that symbol's binding that matters here. */
1812 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1815 /* Return true if function X is a libgcc MIPS16 stub function. */
1818 mips16_stub_function_p (const_rtx x
)
1820 return (GET_CODE (x
) == SYMBOL_REF
1821 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1824 /* Return true if function X is a locally-defined and locally-binding
1828 mips16_local_function_p (const_rtx x
)
1830 return (GET_CODE (x
) == SYMBOL_REF
1831 && SYMBOL_REF_LOCAL_P (x
)
1832 && !SYMBOL_REF_EXTERNAL_P (x
)
1833 && (mips_get_compress_mode (SYMBOL_REF_DECL (x
)) & MASK_MIPS16
));
1836 /* Return true if SYMBOL_REF X binds locally. */
1839 mips_symbol_binds_local_p (const_rtx x
)
1841 return (SYMBOL_REF_DECL (x
)
1842 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1843 : SYMBOL_REF_LOCAL_P (x
));
1846 /* Return true if OP is a constant vector with the number of units in MODE,
1847 and each unit has the same bit set. */
1850 mips_const_vector_bitimm_set_p (rtx op
, machine_mode mode
)
1852 if (GET_CODE (op
) == CONST_VECTOR
&& op
!= CONST0_RTX (mode
))
1854 unsigned HOST_WIDE_INT val
= UINTVAL (CONST_VECTOR_ELT (op
, 0));
1855 int vlog2
= exact_log2 (val
& GET_MODE_MASK (GET_MODE_INNER (mode
)));
1859 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
1860 gcc_assert (vlog2
>= 0 && vlog2
<= GET_MODE_UNIT_BITSIZE (mode
) - 1);
1861 return mips_const_vector_same_val_p (op
, mode
);
1868 /* Return true if OP is a constant vector with the number of units in MODE,
1869 and each unit has the same bit clear. */
1872 mips_const_vector_bitimm_clr_p (rtx op
, machine_mode mode
)
1874 if (GET_CODE (op
) == CONST_VECTOR
&& op
!= CONSTM1_RTX (mode
))
1876 unsigned HOST_WIDE_INT val
= ~UINTVAL (CONST_VECTOR_ELT (op
, 0));
1877 int vlog2
= exact_log2 (val
& GET_MODE_MASK (GET_MODE_INNER (mode
)));
1881 gcc_assert (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
1882 gcc_assert (vlog2
>= 0 && vlog2
<= GET_MODE_UNIT_BITSIZE (mode
) - 1);
1883 return mips_const_vector_same_val_p (op
, mode
);
1890 /* Return true if OP is a constant vector with the number of units in MODE,
1891 and each unit has the same value. */
1894 mips_const_vector_same_val_p (rtx op
, machine_mode mode
)
1896 int i
, nunits
= GET_MODE_NUNITS (mode
);
1899 if (GET_CODE (op
) != CONST_VECTOR
|| GET_MODE (op
) != mode
)
1902 first
= CONST_VECTOR_ELT (op
, 0);
1903 for (i
= 1; i
< nunits
; i
++)
1904 if (!rtx_equal_p (first
, CONST_VECTOR_ELT (op
, i
)))
1910 /* Return true if OP is a constant vector with the number of units in MODE,
1911 and each unit has the same value as well as replicated bytes in the value.
1915 mips_const_vector_same_bytes_p (rtx op
, machine_mode mode
)
1918 HOST_WIDE_INT val
, first_byte
;
1921 if (!mips_const_vector_same_val_p (op
, mode
))
1924 first
= CONST_VECTOR_ELT (op
, 0);
1925 bytes
= GET_MODE_UNIT_SIZE (mode
);
1926 val
= INTVAL (first
);
1927 first_byte
= val
& 0xff;
1928 for (i
= 1; i
< bytes
; i
++)
1931 if ((val
& 0xff) != first_byte
)
1938 /* Return true if OP is a constant vector with the number of units in MODE,
1939 and each unit has the same integer value in the range [LOW, HIGH]. */
1942 mips_const_vector_same_int_p (rtx op
, machine_mode mode
, HOST_WIDE_INT low
,
1945 HOST_WIDE_INT value
;
1948 if (!mips_const_vector_same_val_p (op
, mode
))
1951 elem0
= CONST_VECTOR_ELT (op
, 0);
1952 if (!CONST_INT_P (elem0
))
1955 value
= INTVAL (elem0
);
1956 return (value
>= low
&& value
<= high
);
1959 /* Return true if OP is a constant vector with repeated 4-element sets
1963 mips_const_vector_shuffle_set_p (rtx op
, machine_mode mode
)
1965 int nunits
= GET_MODE_NUNITS (mode
);
1966 int nsets
= nunits
/ 4;
1970 /* Check if we have the same 4-element sets. */
1971 for (j
= 0; j
< nsets
; j
++, set
= 4 * j
)
1972 for (i
= 0; i
< 4; i
++)
1973 if ((INTVAL (XVECEXP (op
, 0, i
))
1974 != (INTVAL (XVECEXP (op
, 0, set
+ i
)) - set
))
1975 || !IN_RANGE (INTVAL (XVECEXP (op
, 0, set
+ i
)), 0, set
+ 3))
1980 /* Return true if rtx constants of mode MODE should be put into a small
1984 mips_rtx_constant_in_small_data_p (machine_mode mode
)
1986 return (!TARGET_EMBEDDED_DATA
1987 && TARGET_LOCAL_SDATA
1988 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1991 /* Return true if X should not be moved directly into register $25.
1992 We need this because many versions of GAS will treat "la $25,foo" as
1993 part of a call sequence and so allow a global "foo" to be lazily bound. */
1996 mips_dangerous_for_la25_p (rtx x
)
1998 return (!TARGET_EXPLICIT_RELOCS
2000 && GET_CODE (x
) == SYMBOL_REF
2001 && mips_global_symbol_p (x
));
2004 /* Return true if calls to X might need $25 to be valid on entry. */
2007 mips_use_pic_fn_addr_reg_p (const_rtx x
)
2009 if (!TARGET_USE_PIC_FN_ADDR_REG
)
2012 /* MIPS16 stub functions are guaranteed not to use $25. */
2013 if (mips16_stub_function_p (x
))
2016 if (GET_CODE (x
) == SYMBOL_REF
)
2018 /* If PLTs and copy relocations are available, the static linker
2019 will make sure that $25 is valid on entry to the target function. */
2020 if (TARGET_ABICALLS_PIC0
)
2023 /* Locally-defined functions use absolute accesses to set up
2024 the global pointer. */
2025 if (TARGET_ABSOLUTE_ABICALLS
2026 && mips_symbol_binds_local_p (x
)
2027 && !SYMBOL_REF_EXTERNAL_P (x
))
2034 /* Return the method that should be used to access SYMBOL_REF or
2035 LABEL_REF X in context CONTEXT. */
2037 static enum mips_symbol_type
2038 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
2041 return SYMBOL_GOT_DISP
;
2043 if (GET_CODE (x
) == LABEL_REF
)
2045 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
2046 code and if we know that the label is in the current function's
2047 text section. LABEL_REFs are used for jump tables as well as
2048 text labels, so we must check whether jump tables live in the
2050 if (TARGET_MIPS16_SHORT_JUMP_TABLES
2051 && !LABEL_REF_NONLOCAL_P (x
))
2052 return SYMBOL_PC_RELATIVE
;
2054 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
2055 return SYMBOL_GOT_PAGE_OFST
;
2057 return SYMBOL_ABSOLUTE
;
2060 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
2062 if (SYMBOL_REF_TLS_MODEL (x
))
2065 if (CONSTANT_POOL_ADDRESS_P (x
))
2067 if (TARGET_MIPS16_TEXT_LOADS
)
2068 return SYMBOL_PC_RELATIVE
;
2070 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
2071 return SYMBOL_PC_RELATIVE
;
2073 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
2074 return SYMBOL_GP_RELATIVE
;
2077 /* Do not use small-data accesses for weak symbols; they may end up
2079 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
2080 return SYMBOL_GP_RELATIVE
;
2082 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
2084 if (TARGET_ABICALLS_PIC2
2085 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
2087 /* There are three cases to consider:
2089 - o32 PIC (either with or without explicit relocs)
2090 - n32/n64 PIC without explicit relocs
2091 - n32/n64 PIC with explicit relocs
2093 In the first case, both local and global accesses will use an
2094 R_MIPS_GOT16 relocation. We must correctly predict which of
2095 the two semantics (local or global) the assembler and linker
2096 will apply. The choice depends on the symbol's binding rather
2097 than its visibility.
2099 In the second case, the assembler will not use R_MIPS_GOT16
2100 relocations, but it chooses between local and global accesses
2101 in the same way as for o32 PIC.
2103 In the third case we have more freedom since both forms of
2104 access will work for any kind of symbol. However, there seems
2105 little point in doing things differently. */
2106 if (mips_global_symbol_p (x
))
2107 return SYMBOL_GOT_DISP
;
2109 return SYMBOL_GOT_PAGE_OFST
;
2112 return SYMBOL_ABSOLUTE
;
2115 /* Classify the base of symbolic expression X, given that X appears in
2118 static enum mips_symbol_type
2119 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
2123 split_const (x
, &x
, &offset
);
2124 if (UNSPEC_ADDRESS_P (x
))
2125 return UNSPEC_ADDRESS_TYPE (x
);
2127 return mips_classify_symbol (x
, context
);
2130 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
2131 is the alignment in bytes of SYMBOL_REF X. */
2134 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
2136 HOST_WIDE_INT align
;
2138 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
2139 return IN_RANGE (offset
, 0, align
- 1);
2142 /* Return true if X is a symbolic constant that can be used in context
2143 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
2146 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
2147 enum mips_symbol_type
*symbol_type
)
2151 split_const (x
, &x
, &offset
);
2152 if (UNSPEC_ADDRESS_P (x
))
2154 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
2155 x
= UNSPEC_ADDRESS (x
);
2157 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
2159 *symbol_type
= mips_classify_symbol (x
, context
);
2160 if (*symbol_type
== SYMBOL_TLS
)
2166 if (offset
== const0_rtx
)
2169 /* Check whether a nonzero offset is valid for the underlying
2171 switch (*symbol_type
)
2173 case SYMBOL_ABSOLUTE
:
2174 case SYMBOL_64_HIGH
:
2177 /* If the target has 64-bit pointers and the object file only
2178 supports 32-bit symbols, the values of those symbols will be
2179 sign-extended. In this case we can't allow an arbitrary offset
2180 in case the 32-bit value X + OFFSET has a different sign from X. */
2181 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
2182 return offset_within_block_p (x
, INTVAL (offset
));
2184 /* In other cases the relocations can handle any offset. */
2187 case SYMBOL_PC_RELATIVE
:
2188 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2189 In this case, we no longer have access to the underlying constant,
2190 but the original symbol-based access was known to be valid. */
2191 if (GET_CODE (x
) == LABEL_REF
)
2196 case SYMBOL_GP_RELATIVE
:
2197 /* Make sure that the offset refers to something within the
2198 same object block. This should guarantee that the final
2199 PC- or GP-relative offset is within the 16-bit limit. */
2200 return offset_within_block_p (x
, INTVAL (offset
));
2202 case SYMBOL_GOT_PAGE_OFST
:
2203 case SYMBOL_GOTOFF_PAGE
:
2204 /* If the symbol is global, the GOT entry will contain the symbol's
2205 address, and we will apply a 16-bit offset after loading it.
2206 If the symbol is local, the linker should provide enough local
2207 GOT entries for a 16-bit offset, but larger offsets may lead
2209 return SMALL_INT (offset
);
2213 /* There is no carry between the HI and LO REL relocations, so the
2214 offset is only valid if we know it won't lead to such a carry. */
2215 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
2217 case SYMBOL_GOT_DISP
:
2218 case SYMBOL_GOTOFF_DISP
:
2219 case SYMBOL_GOTOFF_CALL
:
2220 case SYMBOL_GOTOFF_LOADGP
:
2223 case SYMBOL_GOTTPREL
:
2231 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2232 single instruction. We rely on the fact that, in the worst case,
2233 all instructions involved in a MIPS16 address calculation are usually
2237 mips_symbol_insns_1 (enum mips_symbol_type type
, machine_mode mode
)
2239 if (mips_use_pcrel_pool_p
[(int) type
])
2241 if (mode
== MAX_MACHINE_MODE
)
2242 /* LEAs will be converted into constant-pool references by
2244 type
= SYMBOL_PC_RELATIVE
;
2246 /* The constant must be loaded and then dereferenced. */
2252 case SYMBOL_ABSOLUTE
:
2253 /* When using 64-bit symbols, we need 5 preparatory instructions,
2256 lui $at,%highest(symbol)
2257 daddiu $at,$at,%higher(symbol)
2259 daddiu $at,$at,%hi(symbol)
2262 The final address is then $at + %lo(symbol). With 32-bit
2263 symbols we just need a preparatory LUI for normal mode and
2264 a preparatory LI and SLL for MIPS16. */
2265 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
2267 case SYMBOL_GP_RELATIVE
:
2268 /* Treat GP-relative accesses as taking a single instruction on
2269 MIPS16 too; the copy of $gp can often be shared. */
2272 case SYMBOL_PC_RELATIVE
:
2273 /* PC-relative constants can be only be used with ADDIUPC,
2274 DADDIUPC, LWPC and LDPC. */
2275 if (mode
== MAX_MACHINE_MODE
2276 || GET_MODE_SIZE (mode
) == 4
2277 || GET_MODE_SIZE (mode
) == 8)
2280 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2283 case SYMBOL_GOT_DISP
:
2284 /* The constant will have to be loaded from the GOT before it
2285 is used in an address. */
2286 if (mode
!= MAX_MACHINE_MODE
)
2291 case SYMBOL_GOT_PAGE_OFST
:
2292 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2293 local/global classification is accurate. The worst cases are:
2295 (1) For local symbols when generating o32 or o64 code. The assembler
2301 ...and the final address will be $at + %lo(symbol).
2303 (2) For global symbols when -mxgot. The assembler will use:
2305 lui $at,%got_hi(symbol)
2308 ...and the final address will be $at + %got_lo(symbol). */
2311 case SYMBOL_GOTOFF_PAGE
:
2312 case SYMBOL_GOTOFF_DISP
:
2313 case SYMBOL_GOTOFF_CALL
:
2314 case SYMBOL_GOTOFF_LOADGP
:
2315 case SYMBOL_64_HIGH
:
2321 case SYMBOL_GOTTPREL
:
2324 /* A 16-bit constant formed by a single relocation, or a 32-bit
2325 constant formed from a high 16-bit relocation and a low 16-bit
2326 relocation. Use mips_split_p to determine which. 32-bit
2327 constants need an "lui; addiu" sequence for normal mode and
2328 an "li; sll; addiu" sequence for MIPS16 mode. */
2329 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
2332 /* We don't treat a bare TLS symbol as a constant. */
2338 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2339 to load symbols of type TYPE into a register. Return 0 if the given
2340 type of symbol cannot be used as an immediate operand.
2342 Otherwise, return the number of instructions needed to load or store
2343 values of mode MODE to or from addresses of type TYPE. Return 0 if
2344 the given type of symbol is not valid in addresses.
2346 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2349 mips_symbol_insns (enum mips_symbol_type type
, machine_mode mode
)
2351 /* MSA LD.* and ST.* cannot support loading symbols via an immediate
2353 if (MSA_SUPPORTED_MODE_P (mode
))
2356 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
2359 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2362 mips_cannot_force_const_mem (machine_mode mode
, rtx x
)
2364 enum mips_symbol_type type
;
2367 /* There is no assembler syntax for expressing an address-sized
2369 if (GET_CODE (x
) == HIGH
)
2372 /* As an optimization, reject constants that mips_legitimize_move
2375 Suppose we have a multi-instruction sequence that loads constant C
2376 into register R. If R does not get allocated a hard register, and
2377 R is used in an operand that allows both registers and memory
2378 references, reload will consider forcing C into memory and using
2379 one of the instruction's memory alternatives. Returning false
2380 here will force it to use an input reload instead. */
2381 if (CONST_INT_P (x
) && mips_legitimate_constant_p (mode
, x
))
2384 split_const (x
, &base
, &offset
);
2385 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
))
2387 /* See whether we explicitly want these symbols in the pool. */
2388 if (mips_use_pcrel_pool_p
[(int) type
])
2391 /* The same optimization as for CONST_INT. */
2392 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2395 /* If MIPS16 constant pools live in the text section, they should
2396 not refer to anything that might need run-time relocation. */
2397 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2401 /* TLS symbols must be computed by mips_legitimize_move. */
2402 if (tls_referenced_p (x
))
2408 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2409 constants when we're using a per-function constant pool. */
2412 mips_use_blocks_for_constant_p (machine_mode mode ATTRIBUTE_UNUSED
,
2413 const_rtx x ATTRIBUTE_UNUSED
)
2415 return !TARGET_MIPS16_PCREL_LOADS
;
2418 /* Return true if register REGNO is a valid base register for mode MODE.
2419 STRICT_P is true if REG_OK_STRICT is in effect. */
2422 mips_regno_mode_ok_for_base_p (int regno
, machine_mode mode
,
2425 if (!HARD_REGISTER_NUM_P (regno
))
2429 regno
= reg_renumber
[regno
];
2432 /* These fake registers will be eliminated to either the stack or
2433 hard frame pointer, both of which are usually valid base registers.
2434 Reload deals with the cases where the eliminated form isn't valid. */
2435 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2438 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2439 values, nothing smaller. */
2440 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2441 return GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2443 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2446 /* Return true if X is a valid base register for mode MODE.
2447 STRICT_P is true if REG_OK_STRICT is in effect. */
2450 mips_valid_base_register_p (rtx x
, machine_mode mode
, bool strict_p
)
2452 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2456 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2459 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2460 can address a value of mode MODE. */
2463 mips_valid_offset_p (rtx x
, machine_mode mode
)
2465 /* Check that X is a signed 16-bit number. */
2466 if (!const_arith_operand (x
, Pmode
))
2469 /* We may need to split multiword moves, so make sure that every word
2471 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2472 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2475 /* MSA LD.* and ST.* supports 10-bit signed offsets. */
2476 if (MSA_SUPPORTED_MODE_P (mode
)
2477 && !mips_signed_immediate_p (INTVAL (x
), 10,
2478 mips_ldst_scaled_shift (mode
)))
2484 /* Return true if a LO_SUM can address a value of mode MODE when the
2485 LO_SUM symbol has type SYMBOL_TYPE. */
2488 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, machine_mode mode
)
2490 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2492 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2495 /* Check that there is a known low-part relocation. */
2496 if (mips_lo_relocs
[symbol_type
] == NULL
)
2499 /* We may need to split multiword moves, so make sure that each word
2500 can be accessed without inducing a carry. This is mainly needed
2501 for o64, which has historically only guaranteed 64-bit alignment
2502 for 128-bit types. */
2503 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2504 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2507 /* MSA LD.* and ST.* cannot support loading symbols via %lo($base). */
2508 if (MSA_SUPPORTED_MODE_P (mode
))
2514 /* Return true if X is a valid address for machine mode MODE. If it is,
2515 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2519 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2520 machine_mode mode
, bool strict_p
)
2522 switch (GET_CODE (x
))
2526 info
->type
= ADDRESS_REG
;
2528 info
->offset
= const0_rtx
;
2529 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2532 info
->type
= ADDRESS_REG
;
2533 info
->reg
= XEXP (x
, 0);
2534 info
->offset
= XEXP (x
, 1);
2535 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2536 && mips_valid_offset_p (info
->offset
, mode
));
2539 info
->type
= ADDRESS_LO_SUM
;
2540 info
->reg
= XEXP (x
, 0);
2541 info
->offset
= XEXP (x
, 1);
2542 /* We have to trust the creator of the LO_SUM to do something vaguely
2543 sane. Target-independent code that creates a LO_SUM should also
2544 create and verify the matching HIGH. Target-independent code that
2545 adds an offset to a LO_SUM must prove that the offset will not
2546 induce a carry. Failure to do either of these things would be
2547 a bug, and we are not required to check for it here. The MIPS
2548 backend itself should only create LO_SUMs for valid symbolic
2549 constants, with the high part being either a HIGH or a copy
2552 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2553 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2554 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2557 /* Small-integer addresses don't occur very often, but they
2558 are legitimate if $0 is a valid base register. */
2559 info
->type
= ADDRESS_CONST_INT
;
2560 return !TARGET_MIPS16
&& SMALL_INT (x
);
2565 info
->type
= ADDRESS_SYMBOLIC
;
2566 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2568 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2569 && !mips_split_p
[info
->symbol_type
]);
2576 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2579 mips_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2581 struct mips_address_info addr
;
2583 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2586 /* Return true if X is a legitimate $sp-based address for mode MODE. */
2589 mips_stack_address_p (rtx x
, machine_mode mode
)
2591 struct mips_address_info addr
;
2593 return (mips_classify_address (&addr
, x
, mode
, false)
2594 && addr
.type
== ADDRESS_REG
2595 && addr
.reg
== stack_pointer_rtx
);
2598 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2599 address instruction. Note that such addresses are not considered
2600 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2601 is so restricted. */
2604 mips_lwxs_address_p (rtx addr
)
2607 && GET_CODE (addr
) == PLUS
2608 && REG_P (XEXP (addr
, 1)))
2610 rtx offset
= XEXP (addr
, 0);
2611 if (GET_CODE (offset
) == MULT
2612 && REG_P (XEXP (offset
, 0))
2613 && CONST_INT_P (XEXP (offset
, 1))
2614 && INTVAL (XEXP (offset
, 1)) == 4)
2620 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2621 indexed address instruction. Note that such addresses are
2622 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2623 sense, because their use is so restricted. */
2626 mips_lx_address_p (rtx addr
, machine_mode mode
)
2628 if (GET_CODE (addr
) != PLUS
2629 || !REG_P (XEXP (addr
, 0))
2630 || !REG_P (XEXP (addr
, 1)))
2632 if (ISA_HAS_LBX
&& mode
== QImode
)
2634 if (ISA_HAS_LHX
&& mode
== HImode
)
2636 if (ISA_HAS_LWX
&& mode
== SImode
)
2638 if (ISA_HAS_LDX
&& mode
== DImode
)
2640 if (MSA_SUPPORTED_MODE_P (mode
))
2645 /* Return true if a value at OFFSET bytes from base register BASE can be
2646 accessed using an unextended MIPS16 instruction. MODE is the mode of
2649 Usually the offset in an unextended instruction is a 5-bit field.
2650 The offset is unsigned and shifted left once for LH and SH, twice
2651 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2652 an 8-bit immediate field that's shifted left twice. */
2655 mips16_unextended_reference_p (machine_mode mode
, rtx base
,
2656 unsigned HOST_WIDE_INT offset
)
2658 if (mode
!= BLKmode
&& offset
% GET_MODE_SIZE (mode
) == 0)
2660 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2661 return offset
< 256U * GET_MODE_SIZE (mode
);
2662 return offset
< 32U * GET_MODE_SIZE (mode
);
2667 /* Return the number of instructions needed to load or store a value
2668 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2669 length of one instruction. Return 0 if X isn't valid for MODE.
2670 Assume that multiword moves may need to be split into word moves
2671 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2675 mips_address_insns (rtx x
, machine_mode mode
, bool might_split_p
)
2677 struct mips_address_info addr
;
2679 bool msa_p
= (!might_split_p
&& MSA_SUPPORTED_MODE_P (mode
));
2681 /* BLKmode is used for single unaligned loads and stores and should
2682 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2683 meaningless, so we have to single it out as a special case one way
2685 if (mode
!= BLKmode
&& might_split_p
)
2686 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2690 if (mips_classify_address (&addr
, x
, mode
, false))
2696 /* MSA LD.* and ST.* supports 10-bit signed offsets. */
2697 if (mips_signed_immediate_p (INTVAL (addr
.offset
), 10,
2698 mips_ldst_scaled_shift (mode
)))
2704 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2705 UINTVAL (addr
.offset
)))
2709 case ADDRESS_LO_SUM
:
2710 return msa_p
? 0 : TARGET_MIPS16
? factor
* 2 : factor
;
2712 case ADDRESS_CONST_INT
:
2713 return msa_p
? 0 : factor
;
2715 case ADDRESS_SYMBOLIC
:
2716 return msa_p
? 0 : factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2721 /* Return true if X fits within an unsigned field of BITS bits that is
2722 shifted left SHIFT bits before being used. */
2725 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2727 return (x
& ((1 << shift
) - 1)) == 0 && x
< ((unsigned) 1 << (shift
+ bits
));
2730 /* Return true if X fits within a signed field of BITS bits that is
2731 shifted left SHIFT bits before being used. */
2734 mips_signed_immediate_p (unsigned HOST_WIDE_INT x
, int bits
, int shift
= 0)
2736 x
+= 1 << (bits
+ shift
- 1);
2737 return mips_unsigned_immediate_p (x
, bits
, shift
);
2740 /* Return the scale shift that applied to MSA LD/ST address offset. */
2743 mips_ldst_scaled_shift (machine_mode mode
)
2745 int shift
= exact_log2 (GET_MODE_UNIT_SIZE (mode
));
2747 if (shift
< 0 || shift
> 8)
2753 /* Return true if X is legitimate for accessing values of mode MODE,
2754 if it is based on a MIPS16 register, and if the offset satisfies
2755 OFFSET_PREDICATE. */
2758 m16_based_address_p (rtx x
, machine_mode mode
,
2759 insn_operand_predicate_fn offset_predicate
)
2761 struct mips_address_info addr
;
2763 return (mips_classify_address (&addr
, x
, mode
, false)
2764 && addr
.type
== ADDRESS_REG
2765 && M16_REG_P (REGNO (addr
.reg
))
2766 && offset_predicate (addr
.offset
, mode
));
2769 /* Return true if X is a legitimate address that conforms to the requirements
2770 for a microMIPS LWSP or SWSP insn. */
2773 lwsp_swsp_address_p (rtx x
, machine_mode mode
)
2775 struct mips_address_info addr
;
2777 return (mips_classify_address (&addr
, x
, mode
, false)
2778 && addr
.type
== ADDRESS_REG
2779 && REGNO (addr
.reg
) == STACK_POINTER_REGNUM
2780 && uw5_operand (addr
.offset
, mode
));
2783 /* Return true if X is a legitimate address with a 12-bit offset.
2784 MODE is the mode of the value being accessed. */
2787 umips_12bit_offset_address_p (rtx x
, machine_mode mode
)
2789 struct mips_address_info addr
;
2791 return (mips_classify_address (&addr
, x
, mode
, false)
2792 && addr
.type
== ADDRESS_REG
2793 && CONST_INT_P (addr
.offset
)
2794 && UMIPS_12BIT_OFFSET_P (INTVAL (addr
.offset
)));
2797 /* Return true if X is a legitimate address with a 9-bit offset.
2798 MODE is the mode of the value being accessed. */
2801 mips_9bit_offset_address_p (rtx x
, machine_mode mode
)
2803 struct mips_address_info addr
;
2805 return (mips_classify_address (&addr
, x
, mode
, false)
2806 && addr
.type
== ADDRESS_REG
2807 && CONST_INT_P (addr
.offset
)
2808 && MIPS_9BIT_OFFSET_P (INTVAL (addr
.offset
)));
2811 /* Return the number of instructions needed to load constant X,
2812 assuming that BASE_INSN_LENGTH is the length of one instruction.
2813 Return 0 if X isn't a valid constant. */
2816 mips_const_insns (rtx x
)
2818 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2819 enum mips_symbol_type symbol_type
;
2822 switch (GET_CODE (x
))
2825 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2827 || !mips_split_p
[symbol_type
])
2830 /* This is simply an LUI for normal mode. It is an extended
2831 LI followed by an extended SLL for MIPS16. */
2832 return TARGET_MIPS16
? 4 : 1;
2836 /* Unsigned 8-bit constants can be loaded using an unextended
2837 LI instruction. Unsigned 16-bit constants can be loaded
2838 using an extended LI. Negative constants must be loaded
2839 using LI and then negated. */
2840 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2841 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2842 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2843 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2846 return mips_build_integer (codes
, INTVAL (x
));
2850 && mips_const_vector_same_int_p (x
, GET_MODE (x
), -512, 511))
2854 /* Allow zeros for normal mode, where we can use $0. */
2855 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2861 /* See if we can refer to X directly. */
2862 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2863 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2865 /* Otherwise try splitting the constant into a base and offset.
2866 If the offset is a 16-bit value, we can load the base address
2867 into a register and then use (D)ADDIU to add in the offset.
2868 If the offset is larger, we can load the base and offset
2869 into separate registers and add them together with (D)ADDU.
2870 However, the latter is only possible before reload; during
2871 and after reload, we must have the option of forcing the
2872 constant into the pool instead. */
2873 split_const (x
, &x
, &offset
);
2876 int n
= mips_const_insns (x
);
2879 if (SMALL_INT (offset
))
2881 else if (!targetm
.cannot_force_const_mem (GET_MODE (x
), x
))
2882 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2889 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2897 /* X is a doubleword constant that can be handled by splitting it into
2898 two words and loading each word separately. Return the number of
2899 instructions required to do this, assuming that BASE_INSN_LENGTH
2900 is the length of one instruction. */
2903 mips_split_const_insns (rtx x
)
2905 unsigned int low
, high
;
2907 low
= mips_const_insns (mips_subword (x
, false));
2908 high
= mips_const_insns (mips_subword (x
, true));
2909 gcc_assert (low
> 0 && high
> 0);
2913 /* Return one word of 128-bit value OP, taking into account the fixed
2914 endianness of certain registers. BYTE selects from the byte address. */
2917 mips_subword_at_byte (rtx op
, unsigned int byte
)
2921 mode
= GET_MODE (op
);
2922 if (mode
== VOIDmode
)
2925 gcc_assert (!FP_REG_RTX_P (op
));
2928 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
2930 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
2933 /* Return the number of instructions needed to implement INSN,
2934 given that it loads from or stores to MEM. Assume that
2935 BASE_INSN_LENGTH is the length of one instruction. */
2938 mips_load_store_insns (rtx mem
, rtx_insn
*insn
)
2944 gcc_assert (MEM_P (mem
));
2945 mode
= GET_MODE (mem
);
2947 /* Try to prove that INSN does not need to be split. */
2948 might_split_p
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
;
2951 set
= single_set (insn
);
2952 if (set
&& !mips_split_move_insn_p (SET_DEST (set
), SET_SRC (set
), insn
))
2953 might_split_p
= false;
2956 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2959 /* Return the number of instructions needed for an integer division,
2960 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2963 mips_idiv_insns (machine_mode mode
)
2968 if (TARGET_CHECK_ZERO_DIV
)
2970 if (GENERATE_DIVIDE_TRAPS
&& !MSA_SUPPORTED_MODE_P (mode
))
2976 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2982 /* Emit a move from SRC to DEST. Assume that the move expanders can
2983 handle all moves if !can_create_pseudo_p (). The distinction is
2984 important because, unlike emit_move_insn, the move expanders know
2985 how to force Pmode objects into the constant pool even when the
2986 constant pool address is not itself legitimate. */
2989 mips_emit_move (rtx dest
, rtx src
)
2991 return (can_create_pseudo_p ()
2992 ? emit_move_insn (dest
, src
)
2993 : emit_move_insn_1 (dest
, src
));
2996 /* Emit a move from SRC to DEST, splitting compound moves into individual
2997 instructions. SPLIT_TYPE is the type of split to perform. */
3000 mips_emit_move_or_split (rtx dest
, rtx src
, enum mips_split_type split_type
)
3002 if (mips_split_move_p (dest
, src
, split_type
))
3003 mips_split_move (dest
, src
, split_type
);
3005 mips_emit_move (dest
, src
);
3008 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
3011 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
3013 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
3016 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
3017 Return that new register. */
3020 mips_force_unary (machine_mode mode
, enum rtx_code code
, rtx op0
)
3024 reg
= gen_reg_rtx (mode
);
3025 mips_emit_unary (code
, reg
, op0
);
3029 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3032 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
3034 emit_insn (gen_rtx_SET (target
, gen_rtx_fmt_ee (code
, GET_MODE (target
),
3038 /* Compute (CODE OP0 OP1) and store the result in a new register
3039 of mode MODE. Return that new register. */
3042 mips_force_binary (machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
3046 reg
= gen_reg_rtx (mode
);
3047 mips_emit_binary (code
, reg
, op0
, op1
);
3051 /* Copy VALUE to a register and return that register. If new pseudos
3052 are allowed, copy it into a new register, otherwise use DEST. */
3055 mips_force_temporary (rtx dest
, rtx value
)
3057 if (can_create_pseudo_p ())
3058 return force_reg (Pmode
, value
);
3061 mips_emit_move (dest
, value
);
3066 /* Emit a call sequence with call pattern PATTERN and return the call
3067 instruction itself (which is not necessarily the last instruction
3068 emitted). ORIG_ADDR is the original, unlegitimized address,
3069 ADDR is the legitimized form, and LAZY_P is true if the call
3070 address is lazily-bound. */
3073 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
3078 insn
= emit_call_insn (pattern
);
3080 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
3082 /* MIPS16 JALRs only take MIPS16 registers. If the target
3083 function requires $25 to be valid on entry, we must copy it
3084 there separately. The move instruction can be put in the
3085 call's delay slot. */
3086 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
3087 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
3088 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
3092 /* Lazy-binding stubs require $gp to be valid on entry. */
3093 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
3097 /* See the comment above load_call<mode> for details. */
3098 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
3099 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
3100 emit_insn (gen_update_got_version ());
3104 && TARGET_EXPLICIT_RELOCS
3105 && TARGET_CALL_CLOBBERED_GP
)
3107 rtx post_call_tmp_reg
= gen_rtx_REG (word_mode
, POST_CALL_TMP_REG
);
3108 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn
), post_call_tmp_reg
);
3114 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
3115 then add CONST_INT OFFSET to the result. */
3118 mips_unspec_address_offset (rtx base
, rtx offset
,
3119 enum mips_symbol_type symbol_type
)
3121 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
3122 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
3123 if (offset
!= const0_rtx
)
3124 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
3125 return gen_rtx_CONST (Pmode
, base
);
3128 /* Return an UNSPEC address with underlying address ADDRESS and symbol
3129 type SYMBOL_TYPE. */
3132 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
3136 split_const (address
, &base
, &offset
);
3137 return mips_unspec_address_offset (base
, offset
, symbol_type
);
3140 /* If OP is an UNSPEC address, return the address to which it refers,
3141 otherwise return OP itself. */
3144 mips_strip_unspec_address (rtx op
)
3148 split_const (op
, &base
, &offset
);
3149 if (UNSPEC_ADDRESS_P (base
))
3150 op
= plus_constant (Pmode
, UNSPEC_ADDRESS (base
), INTVAL (offset
));
3154 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
3155 high part to BASE and return the result. Just return BASE otherwise.
3156 TEMP is as for mips_force_temporary.
3158 The returned expression can be used as the first operand to a LO_SUM. */
3161 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
3162 enum mips_symbol_type symbol_type
)
3164 if (mips_split_p
[symbol_type
])
3166 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
3167 addr
= mips_force_temporary (temp
, addr
);
3168 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
3173 /* Return an instruction that copies $gp into register REG. We want
3174 GCC to treat the register's value as constant, so that its value
3175 can be rematerialized on demand. */
3178 gen_load_const_gp (rtx reg
)
3180 return PMODE_INSN (gen_load_const_gp
, (reg
));
3183 /* Return a pseudo register that contains the value of $gp throughout
3184 the current function. Such registers are needed by MIPS16 functions,
3185 for which $gp itself is not a valid base register or addition operand. */
3188 mips16_gp_pseudo_reg (void)
3190 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
3194 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
3196 push_topmost_sequence ();
3198 scan
= get_insns ();
3199 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
3200 scan
= NEXT_INSN (scan
);
3202 rtx set
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
3203 rtx_insn
*insn
= emit_insn_after (set
, scan
);
3204 INSN_LOCATION (insn
) = 0;
3206 pop_topmost_sequence ();
3209 return cfun
->machine
->mips16_gp_pseudo_rtx
;
3212 /* Return a base register that holds pic_offset_table_rtx.
3213 TEMP, if nonnull, is a scratch Pmode base register. */
3216 mips_pic_base_register (rtx temp
)
3219 return pic_offset_table_rtx
;
3221 if (currently_expanding_to_rtl
)
3222 return mips16_gp_pseudo_reg ();
3224 if (can_create_pseudo_p ())
3225 temp
= gen_reg_rtx (Pmode
);
3228 /* The first post-reload split exposes all references to $gp
3229 (both uses and definitions). All references must remain
3230 explicit after that point.
3232 It is safe to introduce uses of $gp at any time, so for
3233 simplicity, we do that before the split too. */
3234 mips_emit_move (temp
, pic_offset_table_rtx
);
3236 emit_insn (gen_load_const_gp (temp
));
3240 /* Return the RHS of a load_call<mode> insn. */
3243 mips_unspec_call (rtx reg
, rtx symbol
)
3247 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
3248 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
3251 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3252 reference. Return NULL_RTX otherwise. */
3255 mips_strip_unspec_call (rtx src
)
3257 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
3258 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
3262 /* Create and return a GOT reference of type TYPE for address ADDR.
3263 TEMP, if nonnull, is a scratch Pmode base register. */
3266 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
3268 rtx base
, high
, lo_sum_symbol
;
3270 base
= mips_pic_base_register (temp
);
3272 /* If we used the temporary register to load $gp, we can't use
3273 it for the high part as well. */
3274 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
3277 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
3278 lo_sum_symbol
= mips_unspec_address (addr
, type
);
3280 if (type
== SYMBOL_GOTOFF_CALL
)
3281 return mips_unspec_call (high
, lo_sum_symbol
);
3283 return PMODE_INSN (gen_unspec_got
, (high
, lo_sum_symbol
));
3286 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3287 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3288 constant in that context and can be split into high and low parts.
3289 If so, and if LOW_OUT is nonnull, emit the high part and store the
3290 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3292 TEMP is as for mips_force_temporary and is used to load the high
3293 part into a register.
3295 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3296 a legitimize SET_SRC for an .md pattern, otherwise the low part
3297 is guaranteed to be a legitimate address for mode MODE. */
3300 mips_split_symbol (rtx temp
, rtx addr
, machine_mode mode
, rtx
*low_out
)
3302 enum mips_symbol_context context
;
3303 enum mips_symbol_type symbol_type
;
3306 context
= (mode
== MAX_MACHINE_MODE
3307 ? SYMBOL_CONTEXT_LEA
3308 : SYMBOL_CONTEXT_MEM
);
3309 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
3311 addr
= XEXP (addr
, 0);
3312 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3313 && mips_symbol_insns (symbol_type
, mode
) > 0
3314 && mips_split_hi_p
[symbol_type
])
3317 switch (symbol_type
)
3319 case SYMBOL_GOT_PAGE_OFST
:
3320 /* The high part of a page/ofst pair is loaded from the GOT. */
3321 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
3332 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
3333 && mips_symbol_insns (symbol_type
, mode
) > 0
3334 && mips_split_p
[symbol_type
])
3337 switch (symbol_type
)
3339 case SYMBOL_GOT_DISP
:
3340 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3341 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
3344 case SYMBOL_GP_RELATIVE
:
3345 high
= mips_pic_base_register (temp
);
3346 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3350 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
3351 high
= mips_force_temporary (temp
, high
);
3352 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
3361 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3362 mips_force_temporary; it is only needed when OFFSET is not a
3366 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
3368 if (!SMALL_OPERAND (offset
))
3374 /* Load the full offset into a register so that we can use
3375 an unextended instruction for the address itself. */
3376 high
= GEN_INT (offset
);
3381 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3382 The addition inside the macro CONST_HIGH_PART may cause an
3383 overflow, so we need to force a sign-extension check. */
3384 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
3385 offset
= CONST_LOW_PART (offset
);
3387 high
= mips_force_temporary (temp
, high
);
3388 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
3390 return plus_constant (Pmode
, reg
, offset
);
3393 /* The __tls_get_attr symbol. */
3394 static GTY(()) rtx mips_tls_symbol
;
3396 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3397 the TLS symbol we are referencing and TYPE is the symbol type to use
3398 (either global dynamic or local dynamic). V0 is an RTX for the
3399 return value location. */
3402 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
3407 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
3409 if (!mips_tls_symbol
)
3410 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
3412 loc
= mips_unspec_address (sym
, type
);
3416 emit_insn (gen_rtx_SET (a0
, gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
,
3418 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
3419 const0_rtx
, NULL_RTX
, false);
3420 RTL_CONST_CALL_P (insn
) = 1;
3421 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
3422 insn
= get_insns ();
3429 /* Return a pseudo register that contains the current thread pointer. */
3432 mips_expand_thread_pointer (rtx tp
)
3438 if (!mips16_rdhwr_stub
)
3439 mips16_rdhwr_stub
= new mips16_rdhwr_one_only_stub ();
3440 fn
= mips16_stub_call_address (mips16_rdhwr_stub
);
3441 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16
, (tp
, fn
)));
3444 emit_insn (PMODE_INSN (gen_tls_get_tp
, (tp
)));
3451 return mips_expand_thread_pointer (gen_reg_rtx (Pmode
));
3454 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3455 its address. The return value will be both a valid address and a valid
3456 SET_SRC (either a REG or a LO_SUM). */
3459 mips_legitimize_tls_address (rtx loc
)
3461 rtx dest
, v0
, tp
, tmp1
, tmp2
, eqv
, offset
;
3462 enum tls_model model
;
3464 model
= SYMBOL_REF_TLS_MODEL (loc
);
3465 /* Only TARGET_ABICALLS code can have more than one module; other
3466 code must be static and should not use a GOT. All TLS models
3467 reduce to local exec in this situation. */
3468 if (!TARGET_ABICALLS
)
3469 model
= TLS_MODEL_LOCAL_EXEC
;
3473 case TLS_MODEL_GLOBAL_DYNAMIC
:
3475 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3476 rtx_insn
*insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
3477 dest
= gen_reg_rtx (Pmode
);
3478 emit_libcall_block (insn
, dest
, v0
, loc
);
3482 case TLS_MODEL_LOCAL_DYNAMIC
:
3484 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
3485 rtx_insn
*insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
3486 tmp1
= gen_reg_rtx (Pmode
);
3488 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3489 share the LDM result with other LD model accesses. */
3490 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
3492 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
3494 offset
= mips_unspec_address (loc
, SYMBOL_DTPREL
);
3495 if (mips_split_p
[SYMBOL_DTPREL
])
3497 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
3498 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3501 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3502 0, 0, OPTAB_DIRECT
);
3506 case TLS_MODEL_INITIAL_EXEC
:
3507 tp
= mips_get_tp ();
3508 tmp1
= gen_reg_rtx (Pmode
);
3509 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
3510 if (Pmode
== DImode
)
3511 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
3513 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
3514 dest
= gen_reg_rtx (Pmode
);
3515 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
3518 case TLS_MODEL_LOCAL_EXEC
:
3519 tmp1
= mips_get_tp ();
3520 offset
= mips_unspec_address (loc
, SYMBOL_TPREL
);
3521 if (mips_split_p
[SYMBOL_TPREL
])
3523 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_TPREL
);
3524 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
, offset
);
3527 dest
= expand_binop (Pmode
, add_optab
, tmp1
, offset
,
3528 0, 0, OPTAB_DIRECT
);
3537 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3541 mips16_expand_get_fcsr (rtx target
)
3543 if (!mips16_get_fcsr_stub
)
3544 mips16_get_fcsr_stub
= new mips16_get_fcsr_one_only_stub ();
3545 rtx fn
= mips16_stub_call_address (mips16_get_fcsr_stub
);
3546 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16
, (fn
)));
3547 emit_move_insn (target
, gen_rtx_REG (SImode
, GET_FCSR_REGNUM
));
3550 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3553 mips16_expand_set_fcsr (rtx newval
)
3555 if (!mips16_set_fcsr_stub
)
3556 mips16_set_fcsr_stub
= new mips16_set_fcsr_one_only_stub ();
3557 rtx fn
= mips16_stub_call_address (mips16_set_fcsr_stub
);
3558 emit_move_insn (gen_rtx_REG (SImode
, SET_FCSR_REGNUM
), newval
);
3559 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16
, (fn
)));
3562 /* If X is not a valid address for mode MODE, force it into a register. */
3565 mips_force_address (rtx x
, machine_mode mode
)
3567 if (!mips_legitimate_address_p (mode
, x
, false))
3568 x
= force_reg (Pmode
, x
);
3572 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3573 be legitimized in a way that the generic machinery might not expect,
3574 return a new address, otherwise return NULL. MODE is the mode of
3575 the memory being accessed. */
3578 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3582 HOST_WIDE_INT offset
;
3584 if (mips_tls_symbol_p (x
))
3585 return mips_legitimize_tls_address (x
);
3587 /* See if the address can split into a high part and a LO_SUM. */
3588 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3589 return mips_force_address (addr
, mode
);
3591 /* Handle BASE + OFFSET using mips_add_offset. */
3592 mips_split_plus (x
, &base
, &offset
);
3595 if (!mips_valid_base_register_p (base
, mode
, false))
3596 base
= copy_to_mode_reg (Pmode
, base
);
3597 addr
= mips_add_offset (NULL
, base
, offset
);
3598 return mips_force_address (addr
, mode
);
3604 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3607 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3609 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3611 unsigned int i
, num_ops
;
3614 mode
= GET_MODE (dest
);
3615 num_ops
= mips_build_integer (codes
, value
);
3617 /* Apply each binary operation to X. Invariant: X is a legitimate
3618 source operand for a SET pattern. */
3619 x
= GEN_INT (codes
[0].value
);
3620 for (i
= 1; i
< num_ops
; i
++)
3622 if (!can_create_pseudo_p ())
3624 emit_insn (gen_rtx_SET (temp
, x
));
3628 x
= force_reg (mode
, x
);
3629 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3632 emit_insn (gen_rtx_SET (dest
, x
));
3635 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3636 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3640 mips_legitimize_const_move (machine_mode mode
, rtx dest
, rtx src
)
3644 /* Split moves of big integers into smaller pieces. */
3645 if (splittable_const_int_operand (src
, mode
))
3647 mips_move_integer (dest
, dest
, INTVAL (src
));
3651 /* Split moves of symbolic constants into high/low pairs. */
3652 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3654 emit_insn (gen_rtx_SET (dest
, src
));
3658 /* Generate the appropriate access sequences for TLS symbols. */
3659 if (mips_tls_symbol_p (src
))
3661 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3665 /* If we have (const (plus symbol offset)), and that expression cannot
3666 be forced into memory, load the symbol first and add in the offset.
3667 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3668 forced into memory, as it usually produces better code. */
3669 split_const (src
, &base
, &offset
);
3670 if (offset
!= const0_rtx
3671 && (targetm
.cannot_force_const_mem (mode
, src
)
3672 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3674 base
= mips_force_temporary (dest
, base
);
3675 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3679 src
= force_const_mem (mode
, src
);
3681 /* When using explicit relocs, constant pool references are sometimes
3682 not legitimate addresses. */
3683 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3684 mips_emit_move (dest
, src
);
3687 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3688 sequence that is valid. */
3691 mips_legitimize_move (machine_mode mode
, rtx dest
, rtx src
)
3693 /* Both src and dest are non-registers; one special case is supported where
3694 the source is (const_int 0) and the store can source the zero register.
3695 MIPS16 and MSA are never able to source the zero register directly in
3696 memory operations. */
3697 if (!register_operand (dest
, mode
)
3698 && !register_operand (src
, mode
)
3699 && (TARGET_MIPS16
|| !const_0_operand (src
, mode
)
3700 || MSA_SUPPORTED_MODE_P (mode
)))
3702 mips_emit_move (dest
, force_reg (mode
, src
));
3706 /* We need to deal with constants that would be legitimate
3707 immediate_operands but aren't legitimate move_operands. */
3708 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3710 mips_legitimize_const_move (mode
, dest
, src
);
3711 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3717 /* Return true if value X in context CONTEXT is a small-data address
3718 that can be rewritten as a LO_SUM. */
3721 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3723 enum mips_symbol_type symbol_type
;
3725 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3726 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3727 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3728 && symbol_type
== SYMBOL_GP_RELATIVE
);
3731 /* Return true if OP refers to small data symbols directly, not through
3732 a LO_SUM. CONTEXT is the context in which X appears. */
3735 mips_small_data_pattern_1 (rtx x
, enum mips_symbol_context context
)
3737 subrtx_var_iterator::array_type array
;
3738 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
3742 /* Ignore things like "g" constraints in asms. We make no particular
3743 guarantee about which symbolic constants are acceptable as asm operands
3744 versus which must be forced into a GPR. */
3745 if (GET_CODE (x
) == LO_SUM
|| GET_CODE (x
) == ASM_OPERANDS
)
3746 iter
.skip_subrtxes ();
3749 if (mips_small_data_pattern_1 (XEXP (x
, 0), SYMBOL_CONTEXT_MEM
))
3751 iter
.skip_subrtxes ();
3753 else if (mips_rewrite_small_data_p (x
, context
))
3759 /* Return true if OP refers to small data symbols directly, not through
3763 mips_small_data_pattern_p (rtx op
)
3765 return mips_small_data_pattern_1 (op
, SYMBOL_CONTEXT_LEA
);
3768 /* Rewrite *LOC so that it refers to small data using explicit
3769 relocations. CONTEXT is the context in which *LOC appears. */
3772 mips_rewrite_small_data_1 (rtx
*loc
, enum mips_symbol_context context
)
3774 subrtx_ptr_iterator::array_type array
;
3775 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, ALL
)
3780 mips_rewrite_small_data_1 (&XEXP (*loc
, 0), SYMBOL_CONTEXT_MEM
);
3781 iter
.skip_subrtxes ();
3783 else if (mips_rewrite_small_data_p (*loc
, context
))
3785 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3786 iter
.skip_subrtxes ();
3788 else if (GET_CODE (*loc
) == LO_SUM
)
3789 iter
.skip_subrtxes ();
3793 /* Rewrite instruction pattern PATTERN so that it refers to small data
3794 using explicit relocations. */
3797 mips_rewrite_small_data (rtx pattern
)
3799 pattern
= copy_insn (pattern
);
3800 mips_rewrite_small_data_1 (&pattern
, SYMBOL_CONTEXT_LEA
);
3804 /* The cost of loading values from the constant pool. It should be
3805 larger than the cost of any constant we want to synthesize inline. */
3806 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3808 /* Return the cost of X when used as an operand to the MIPS16 instruction
3809 that implements CODE. Return -1 if there is no such instruction, or if
3810 X is not a valid immediate operand for it. */
3813 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3820 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3821 other shifts are extended. The shift patterns truncate the shift
3822 count to the right size, so there are no out-of-range values. */
3823 if (IN_RANGE (x
, 1, 8))
3825 return COSTS_N_INSNS (1);
3828 if (IN_RANGE (x
, -128, 127))
3830 if (SMALL_OPERAND (x
))
3831 return COSTS_N_INSNS (1);
3835 /* Like LE, but reject the always-true case. */
3840 /* We add 1 to the immediate and use SLT. */
3844 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3847 if (IN_RANGE (x
, 0, 255))
3849 if (SMALL_OPERAND_UNSIGNED (x
))
3850 return COSTS_N_INSNS (1);
3855 /* Equality comparisons with 0 are cheap. */
3865 /* Return true if there is a non-MIPS16 instruction that implements CODE
3866 and if that instruction accepts X as an immediate operand. */
3869 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3876 /* All shift counts are truncated to a valid constant. */
3881 /* Likewise rotates, if the target supports rotates at all. */
3887 /* These instructions take 16-bit unsigned immediates. */
3888 return SMALL_OPERAND_UNSIGNED (x
);
3893 /* These instructions take 16-bit signed immediates. */
3894 return SMALL_OPERAND (x
);
3900 /* The "immediate" forms of these instructions are really
3901 implemented as comparisons with register 0. */
3906 /* Likewise, meaning that the only valid immediate operand is 1. */
3910 /* We add 1 to the immediate and use SLT. */
3911 return SMALL_OPERAND (x
+ 1);
3914 /* Likewise SLTU, but reject the always-true case. */
3915 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3919 /* The bit position and size are immediate operands. */
3920 return ISA_HAS_EXT_INS
;
3923 /* By default assume that $0 can be used for 0. */
3928 /* Return the cost of binary operation X, given that the instruction
3929 sequence for a word-sized or smaller operation has cost SINGLE_COST
3930 and that the sequence of a double-word operation has cost DOUBLE_COST.
3931 If SPEED is true, optimize for speed otherwise optimize for size. */
3934 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3938 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3943 + set_src_cost (XEXP (x
, 0), GET_MODE (x
), speed
)
3944 + rtx_cost (XEXP (x
, 1), GET_MODE (x
), GET_CODE (x
), 1, speed
));
3947 /* Return the cost of floating-point multiplications of mode MODE. */
3950 mips_fp_mult_cost (machine_mode mode
)
3952 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3955 /* Return the cost of floating-point divisions of mode MODE. */
3958 mips_fp_div_cost (machine_mode mode
)
3960 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3963 /* Return the cost of sign-extending OP to mode MODE, not including the
3964 cost of OP itself. */
3967 mips_sign_extend_cost (machine_mode mode
, rtx op
)
3970 /* Extended loads are as cheap as unextended ones. */
3973 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3974 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3977 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3978 /* We can use SEB or SEH. */
3979 return COSTS_N_INSNS (1);
3981 /* We need to use a shift left and a shift right. */
3982 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3985 /* Return the cost of zero-extending OP to mode MODE, not including the
3986 cost of OP itself. */
3989 mips_zero_extend_cost (machine_mode mode
, rtx op
)
3992 /* Extended loads are as cheap as unextended ones. */
3995 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3996 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3997 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3999 if (GENERATE_MIPS16E
)
4000 /* We can use ZEB or ZEH. */
4001 return COSTS_N_INSNS (1);
4004 /* We need to load 0xff or 0xffff into a register and use AND. */
4005 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
4007 /* We can use ANDI. */
4008 return COSTS_N_INSNS (1);
4011 /* Return the cost of moving between two registers of mode MODE,
4012 assuming that the move will be in pieces of at most UNITS bytes. */
4015 mips_set_reg_reg_piece_cost (machine_mode mode
, unsigned int units
)
4017 return COSTS_N_INSNS ((GET_MODE_SIZE (mode
) + units
- 1) / units
);
4020 /* Return the cost of moving between two registers of mode MODE. */
4023 mips_set_reg_reg_cost (machine_mode mode
)
4025 switch (GET_MODE_CLASS (mode
))
4028 return mips_set_reg_reg_piece_cost (mode
, GET_MODE_SIZE (CCmode
));
4031 case MODE_COMPLEX_FLOAT
:
4032 case MODE_VECTOR_FLOAT
:
4033 if (TARGET_HARD_FLOAT
)
4034 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_HWFPVALUE
);
4038 return mips_set_reg_reg_piece_cost (mode
, UNITS_PER_WORD
);
4042 /* Implement TARGET_RTX_COSTS. */
4045 mips_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
4046 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
4048 int code
= GET_CODE (x
);
4049 bool float_mode_p
= FLOAT_MODE_P (mode
);
4053 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
4054 appear in the instruction stream, and the cost of a comparison is
4055 really the cost of the branch or scc condition. At the time of
4056 writing, GCC only uses an explicit outer COMPARE code when optabs
4057 is testing whether a constant is expensive enough to force into a
4058 register. We want optabs to pass such constants through the MIPS
4059 expanders instead, so make all constants very cheap here. */
4060 if (outer_code
== COMPARE
)
4062 gcc_assert (CONSTANT_P (x
));
4070 /* Treat *clear_upper32-style ANDs as having zero cost in the
4071 second operand. The cost is entirely in the first operand.
4073 ??? This is needed because we would otherwise try to CSE
4074 the constant operand. Although that's the right thing for
4075 instructions that continue to be a register operation throughout
4076 compilation, it is disastrous for instructions that could
4077 later be converted into a memory operation. */
4079 && outer_code
== AND
4080 && UINTVAL (x
) == 0xffffffff)
4088 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
4097 /* When not optimizing for size, we care more about the cost
4098 of hot code, and hot code is often in a loop. If a constant
4099 operand needs to be forced into a register, we will often be
4100 able to hoist the constant load out of the loop, so the load
4101 should not contribute to the cost. */
4102 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
4114 if (force_to_mem_operand (x
, VOIDmode
))
4116 *total
= COSTS_N_INSNS (1);
4119 cost
= mips_const_insns (x
);
4122 /* If the constant is likely to be stored in a GPR, SETs of
4123 single-insn constants are as cheap as register sets; we
4124 never want to CSE them.
4126 Don't reduce the cost of storing a floating-point zero in
4127 FPRs. If we have a zero in an FPR for other reasons, we
4128 can get better cfg-cleanup and delayed-branch results by
4129 using it consistently, rather than using $0 sometimes and
4130 an FPR at other times. Also, moves between floating-point
4131 registers are sometimes cheaper than (D)MTC1 $0. */
4133 && outer_code
== SET
4134 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
4136 /* When non-MIPS16 code loads a constant N>1 times, we rarely
4137 want to CSE the constant itself. It is usually better to
4138 have N copies of the last operation in the sequence and one
4139 shared copy of the other operations. (Note that this is
4140 not true for MIPS16 code, where the final operation in the
4141 sequence is often an extended instruction.)
4143 Also, if we have a CONST_INT, we don't know whether it is
4144 for a word or doubleword operation, so we cannot rely on
4145 the result of mips_build_integer. */
4146 else if (!TARGET_MIPS16
4147 && (outer_code
== SET
|| GET_MODE (x
) == VOIDmode
))
4149 *total
= COSTS_N_INSNS (cost
);
4152 /* The value will need to be fetched from the constant pool. */
4153 *total
= CONSTANT_POOL_COST
;
4157 /* If the address is legitimate, return the number of
4158 instructions it needs. */
4160 cost
= mips_address_insns (addr
, mode
, true);
4163 *total
= COSTS_N_INSNS (cost
+ 1);
4166 /* Check for a scaled indexed address. */
4167 if (mips_lwxs_address_p (addr
)
4168 || mips_lx_address_p (addr
, mode
))
4170 *total
= COSTS_N_INSNS (2);
4173 /* Otherwise use the default handling. */
4177 *total
= COSTS_N_INSNS (6);
4181 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
4185 /* Check for a *clear_upper32 pattern and treat it like a zero
4186 extension. See the pattern's comment for details. */
4189 && CONST_INT_P (XEXP (x
, 1))
4190 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
4192 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
4193 + set_src_cost (XEXP (x
, 0), mode
, speed
));
4196 if (ISA_HAS_CINS
&& CONST_INT_P (XEXP (x
, 1)))
4198 rtx op
= XEXP (x
, 0);
4199 if (GET_CODE (op
) == ASHIFT
4200 && CONST_INT_P (XEXP (op
, 1))
4201 && mask_low_and_shift_p (mode
, XEXP (x
, 1), XEXP (op
, 1), 32))
4203 *total
= COSTS_N_INSNS (1);
4204 *total
+= set_src_cost (XEXP (op
, 0), mode
, speed
);
4208 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
4209 a single instruction. */
4211 && GET_CODE (XEXP (x
, 0)) == NOT
4212 && GET_CODE (XEXP (x
, 1)) == NOT
)
4214 cost
= GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1;
4215 *total
= (COSTS_N_INSNS (cost
)
4216 + set_src_cost (XEXP (XEXP (x
, 0), 0), mode
, speed
)
4217 + set_src_cost (XEXP (XEXP (x
, 1), 0), mode
, speed
));
4225 /* Double-word operations use two single-word operations. */
4226 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
4235 if (CONSTANT_P (XEXP (x
, 1)))
4236 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4239 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
4245 *total
= mips_cost
->fp_add
;
4247 *total
= COSTS_N_INSNS (4);
4251 /* Low-part immediates need an extended MIPS16 instruction. */
4252 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
4253 + set_src_cost (XEXP (x
, 0), mode
, speed
));
4272 /* Branch comparisons have VOIDmode, so use the first operand's
4274 mode
= GET_MODE (XEXP (x
, 0));
4275 if (FLOAT_MODE_P (mode
))
4277 *total
= mips_cost
->fp_add
;
4280 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4285 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
&& !HONOR_SIGNED_ZEROS (mode
))
4287 /* See if we can use NMADD or NMSUB via the *nmadd4<mode>_fastmath
4288 or *nmsub4<mode>_fastmath patterns. These patterns check for
4289 HONOR_SIGNED_ZEROS so we check here too. */
4290 rtx op0
= XEXP (x
, 0);
4291 rtx op1
= XEXP (x
, 1);
4292 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
4294 *total
= (mips_fp_mult_cost (mode
)
4295 + set_src_cost (XEXP (XEXP (op0
, 0), 0), mode
, speed
)
4296 + set_src_cost (XEXP (op0
, 1), mode
, speed
)
4297 + set_src_cost (op1
, mode
, speed
));
4300 if (GET_CODE (op1
) == MULT
)
4302 *total
= (mips_fp_mult_cost (mode
)
4303 + set_src_cost (op0
, mode
, speed
)
4304 + set_src_cost (XEXP (op1
, 0), mode
, speed
)
4305 + set_src_cost (XEXP (op1
, 1), mode
, speed
));
4314 /* If this is part of a MADD or MSUB, treat the PLUS as
4316 if (ISA_HAS_UNFUSED_MADD4
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4319 *total
= mips_cost
->fp_add
;
4323 /* If it's an add + mult (which is equivalent to shift left) and
4324 it's immediate operand satisfies const_immlsa_operand predicate. */
4325 if (((ISA_HAS_LSA
&& mode
== SImode
)
4326 || (ISA_HAS_DLSA
&& mode
== DImode
))
4327 && GET_CODE (XEXP (x
, 0)) == MULT
)
4329 rtx op2
= XEXP (XEXP (x
, 0), 1);
4330 if (const_immlsa_operand (op2
, mode
))
4332 *total
= (COSTS_N_INSNS (1)
4333 + set_src_cost (XEXP (XEXP (x
, 0), 0), mode
, speed
)
4334 + set_src_cost (XEXP (x
, 1), mode
, speed
));
4339 /* Double-word operations require three single-word operations and
4340 an SLTU. The MIPS16 version then needs to move the result of
4341 the SLTU from $24 to a MIPS16 register. */
4342 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
4343 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
4348 if (float_mode_p
&& ISA_HAS_UNFUSED_MADD4
)
4350 /* See if we can use NMADD or NMSUB via the *nmadd4<mode> or
4351 *nmsub4<mode> patterns. */
4352 rtx op
= XEXP (x
, 0);
4353 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
4354 && GET_CODE (XEXP (op
, 0)) == MULT
)
4356 *total
= (mips_fp_mult_cost (mode
)
4357 + set_src_cost (XEXP (XEXP (op
, 0), 0), mode
, speed
)
4358 + set_src_cost (XEXP (XEXP (op
, 0), 1), mode
, speed
)
4359 + set_src_cost (XEXP (op
, 1), mode
, speed
));
4365 *total
= mips_cost
->fp_add
;
4367 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
4371 *total
= mips_fp_mult_cost (mode
);
4376 *total
= mips_fp_mult_cost (mode
);
4377 else if (mode
== DImode
&& !TARGET_64BIT
)
4378 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4379 where the mulsidi3 always includes an MFHI and an MFLO. */
4381 ? mips_cost
->int_mult_si
* 3 + 6
4382 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
4384 *total
= COSTS_N_INSNS ((ISA_HAS_MUL3
|| ISA_HAS_R6MUL
) ? 1 : 2) + 1;
4385 else if (mode
== DImode
)
4386 *total
= mips_cost
->int_mult_di
;
4388 *total
= mips_cost
->int_mult_si
;
4392 /* Check for a reciprocal. */
4394 && ISA_HAS_FP_RECIP_RSQRT (mode
)
4395 && flag_unsafe_math_optimizations
4396 && XEXP (x
, 0) == CONST1_RTX (mode
))
4398 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
4399 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4400 division as being free. */
4401 *total
= set_src_cost (XEXP (x
, 1), mode
, speed
);
4403 *total
= (mips_fp_div_cost (mode
)
4404 + set_src_cost (XEXP (x
, 1), mode
, speed
));
4413 *total
= mips_fp_div_cost (mode
);
4422 /* It is our responsibility to make division by a power of 2
4423 as cheap as 2 register additions if we want the division
4424 expanders to be used for such operations; see the setting
4425 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4426 should always produce shorter code than using
4427 expand_sdiv2_pow2. */
4429 && CONST_INT_P (XEXP (x
, 1))
4430 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
4432 *total
= COSTS_N_INSNS (2);
4433 *total
+= set_src_cost (XEXP (x
, 0), mode
, speed
);
4436 *total
= COSTS_N_INSNS (mips_idiv_insns (mode
));
4438 else if (mode
== DImode
)
4439 *total
= mips_cost
->int_div_di
;
4441 *total
= mips_cost
->int_div_si
;
4445 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
4449 if (outer_code
== SET
4451 && (GET_CODE (XEXP (x
, 0)) == TRUNCATE
4452 || GET_CODE (XEXP (x
, 0)) == SUBREG
)
4453 && GET_MODE (XEXP (x
, 0)) == QImode
4454 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
4456 *total
= set_src_cost (XEXP (XEXP (x
, 0), 0), VOIDmode
, speed
);
4459 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
4462 /* Costings for highpart multiplies. Matching patterns of the form:
4464 (lshiftrt:DI (mult:DI (sign_extend:DI (...)
4465 (sign_extend:DI (...))
4469 && (GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4470 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
)
4471 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4472 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) == 32
4473 && GET_MODE (XEXP (x
, 0)) == DImode
)
4475 && INTVAL (XEXP (XEXP (x
, 0), 1)) == 64
4476 && GET_MODE (XEXP (x
, 0)) == TImode
))
4477 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
4478 && ((GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
4479 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == SIGN_EXTEND
)
4480 || (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
4481 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4485 *total
= COSTS_N_INSNS (1) + 1;
4486 else if (mode
== DImode
)
4487 *total
= mips_cost
->int_mult_di
;
4489 *total
= mips_cost
->int_mult_si
;
4491 /* Sign extension is free, zero extension costs for DImode when
4492 on a 64bit core / when DMUL is present. */
4493 for (int i
= 0; i
< 2; ++i
)
4495 rtx op
= XEXP (XEXP (XEXP (x
, 0), 0), i
);
4497 && GET_CODE (op
) == ZERO_EXTEND
4498 && GET_MODE (op
) == DImode
)
4499 *total
+= rtx_cost (op
, DImode
, MULT
, i
, speed
);
4501 *total
+= rtx_cost (XEXP (op
, 0), VOIDmode
, GET_CODE (op
),
4510 case UNSIGNED_FLOAT
:
4513 case FLOAT_TRUNCATE
:
4514 *total
= mips_cost
->fp_add
;
4518 if (register_operand (SET_DEST (x
), VOIDmode
)
4519 && reg_or_0_operand (SET_SRC (x
), VOIDmode
))
4521 *total
= mips_set_reg_reg_cost (GET_MODE (SET_DEST (x
)));
4531 /* Implement TARGET_ADDRESS_COST. */
4534 mips_address_cost (rtx addr
, machine_mode mode
,
4535 addr_space_t as ATTRIBUTE_UNUSED
,
4536 bool speed ATTRIBUTE_UNUSED
)
4538 return mips_address_insns (addr
, mode
, false);
4541 /* Implement TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P. */
4544 mips_no_speculation_in_delay_slots_p ()
4546 return TARGET_CB_MAYBE
;
4549 /* Information about a single instruction in a multi-instruction
4551 struct mips_multi_member
{
4552 /* True if this is a label, false if it is code. */
4555 /* The output_asm_insn format of the instruction. */
4558 /* The operands to the instruction. */
4559 rtx operands
[MAX_RECOG_OPERANDS
];
4561 typedef struct mips_multi_member mips_multi_member
;
4563 /* The instructions that make up the current multi-insn sequence. */
4564 static vec
<mips_multi_member
> mips_multi_members
;
4566 /* How many instructions (as opposed to labels) are in the current
4567 multi-insn sequence. */
4568 static unsigned int mips_multi_num_insns
;
4570 /* Start a new multi-insn sequence. */
4573 mips_multi_start (void)
4575 mips_multi_members
.truncate (0);
4576 mips_multi_num_insns
= 0;
4579 /* Add a new, zero initialized member to the current multi-insn sequence. */
4581 static struct mips_multi_member
*
4582 mips_multi_add (void)
4584 mips_multi_member empty
;
4585 memset (&empty
, 0, sizeof (empty
));
4586 return mips_multi_members
.safe_push (empty
);
4589 /* Add a normal insn with the given asm format to the current multi-insn
4590 sequence. The other arguments are a null-terminated list of operands. */
4593 mips_multi_add_insn (const char *format
, ...)
4595 struct mips_multi_member
*member
;
4600 member
= mips_multi_add ();
4601 member
->is_label_p
= false;
4602 member
->format
= format
;
4603 va_start (ap
, format
);
4605 while ((op
= va_arg (ap
, rtx
)))
4606 member
->operands
[i
++] = op
;
4608 mips_multi_num_insns
++;
4611 /* Add the given label definition to the current multi-insn sequence.
4612 The definition should include the colon. */
4615 mips_multi_add_label (const char *label
)
4617 struct mips_multi_member
*member
;
4619 member
= mips_multi_add ();
4620 member
->is_label_p
= true;
4621 member
->format
= label
;
4624 /* Return the index of the last member of the current multi-insn sequence. */
4627 mips_multi_last_index (void)
4629 return mips_multi_members
.length () - 1;
4632 /* Add a copy of an existing instruction to the current multi-insn
4633 sequence. I is the index of the instruction that should be copied. */
4636 mips_multi_copy_insn (unsigned int i
)
4638 struct mips_multi_member
*member
;
4640 member
= mips_multi_add ();
4641 memcpy (member
, &mips_multi_members
[i
], sizeof (*member
));
4642 gcc_assert (!member
->is_label_p
);
4645 /* Change the operand of an existing instruction in the current
4646 multi-insn sequence. I is the index of the instruction,
4647 OP is the index of the operand, and X is the new value. */
4650 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4652 mips_multi_members
[i
].operands
[op
] = x
;
4655 /* Write out the asm code for the current multi-insn sequence. */
4658 mips_multi_write (void)
4660 struct mips_multi_member
*member
;
4663 FOR_EACH_VEC_ELT (mips_multi_members
, i
, member
)
4664 if (member
->is_label_p
)
4665 fprintf (asm_out_file
, "%s\n", member
->format
);
4667 output_asm_insn (member
->format
, member
->operands
);
4670 /* Return one word of double-word value OP, taking into account the fixed
4671 endianness of certain registers. HIGH_P is true to select the high part,
4672 false to select the low part. */
4675 mips_subword (rtx op
, bool high_p
)
4677 unsigned int byte
, offset
;
4680 mode
= GET_MODE (op
);
4681 if (mode
== VOIDmode
)
4682 mode
= TARGET_64BIT
? TImode
: DImode
;
4684 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4685 byte
= UNITS_PER_WORD
;
4689 if (FP_REG_RTX_P (op
))
4691 /* Paired FPRs are always ordered little-endian. */
4692 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4693 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4697 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4699 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4702 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4703 SPLIT_TYPE is the condition under which moves should be split. */
4706 mips_mult_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4708 return ((split_type
!= SPLIT_FOR_SPEED
4709 || mips_tuning_info
.fast_mult_zero_zero_p
)
4710 && src
== const0_rtx
4712 && GET_MODE_SIZE (GET_MODE (dest
)) == 2 * UNITS_PER_WORD
4713 && (ISA_HAS_DSP_MULT
4714 ? ACC_REG_P (REGNO (dest
))
4715 : MD_REG_P (REGNO (dest
))));
4718 /* Return true if a move from SRC to DEST should be split into two.
4719 SPLIT_TYPE describes the split condition. */
4722 mips_split_move_p (rtx dest
, rtx src
, enum mips_split_type split_type
)
4724 /* Check whether the move can be done using some variant of MULT $0,$0. */
4725 if (mips_mult_move_p (dest
, src
, split_type
))
4728 /* FPR-to-FPR moves can be done in a single instruction, if they're
4730 unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
4731 if (size
== 8 && FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4734 /* Check for floating-point loads and stores. */
4735 if (size
== 8 && ISA_HAS_LDC1_SDC1
)
4737 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4739 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4743 /* Check if MSA moves need splitting. */
4744 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest
)))
4745 return mips_split_128bit_move_p (dest
, src
);
4747 /* Otherwise split all multiword moves. */
4748 return size
> UNITS_PER_WORD
;
4751 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4752 SPLIT_TYPE describes the split condition. */
4755 mips_split_move (rtx dest
, rtx src
, enum mips_split_type split_type
)
4759 gcc_checking_assert (mips_split_move_p (dest
, src
, split_type
));
4760 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest
)))
4761 mips_split_128bit_move (dest
, src
);
4762 else if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4764 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4765 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4766 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4767 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4768 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4769 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4770 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4771 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4772 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4773 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4774 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4775 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4776 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4777 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4781 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4783 low_dest
= mips_subword (dest
, false);
4784 mips_emit_move (low_dest
, mips_subword (src
, false));
4786 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4788 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4790 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4792 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4794 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4796 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4800 /* The operation can be split into two normal moves. Decide in
4801 which order to do them. */
4802 low_dest
= mips_subword (dest
, false);
4803 if (REG_P (low_dest
)
4804 && reg_overlap_mentioned_p (low_dest
, src
))
4806 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4807 mips_emit_move (low_dest
, mips_subword (src
, false));
4811 mips_emit_move (low_dest
, mips_subword (src
, false));
4812 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4817 /* Return the split type for instruction INSN. */
4819 static enum mips_split_type
4820 mips_insn_split_type (rtx insn
)
4822 basic_block bb
= BLOCK_FOR_INSN (insn
);
4825 if (optimize_bb_for_speed_p (bb
))
4826 return SPLIT_FOR_SPEED
;
4828 return SPLIT_FOR_SIZE
;
4830 /* Once CFG information has been removed, we should trust the optimization
4831 decisions made by previous passes and only split where necessary. */
4832 return SPLIT_IF_NECESSARY
;
4835 /* Return true if a 128-bit move from SRC to DEST should be split. */
4838 mips_split_128bit_move_p (rtx dest
, rtx src
)
4840 /* MSA-to-MSA moves can be done in a single instruction. */
4841 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4844 /* Check for MSA loads and stores. */
4845 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4847 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4850 /* Check for MSA set to an immediate const vector with valid replicated
4852 if (FP_REG_RTX_P (dest
)
4853 && mips_const_vector_same_int_p (src
, GET_MODE (src
), -512, 511))
4856 /* Check for MSA load zero immediate. */
4857 if (FP_REG_RTX_P (dest
) && src
== CONST0_RTX (GET_MODE (src
)))
4863 /* Split a 128-bit move from SRC to DEST. */
4866 mips_split_128bit_move (rtx dest
, rtx src
)
4869 rtx low_dest
, low_src
, d
, s
;
4871 if (FP_REG_RTX_P (dest
))
4873 gcc_assert (!MEM_P (src
));
4875 rtx new_dest
= dest
;
4878 if (GET_MODE (dest
) != V4SImode
)
4879 new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
4883 if (GET_MODE (dest
) != V2DImode
)
4884 new_dest
= simplify_gen_subreg (V2DImode
, dest
, GET_MODE (dest
), 0);
4887 for (byte
= 0, index
= 0; byte
< GET_MODE_SIZE (TImode
);
4888 byte
+= UNITS_PER_WORD
, index
++)
4890 s
= mips_subword_at_byte (src
, byte
);
4892 emit_insn (gen_msa_insert_w (new_dest
, s
, new_dest
,
4893 GEN_INT (1 << index
)));
4895 emit_insn (gen_msa_insert_d (new_dest
, s
, new_dest
,
4896 GEN_INT (1 << index
)));
4899 else if (FP_REG_RTX_P (src
))
4901 gcc_assert (!MEM_P (dest
));
4906 if (GET_MODE (src
) != V4SImode
)
4907 new_src
= simplify_gen_subreg (V4SImode
, src
, GET_MODE (src
), 0);
4911 if (GET_MODE (src
) != V2DImode
)
4912 new_src
= simplify_gen_subreg (V2DImode
, src
, GET_MODE (src
), 0);
4915 for (byte
= 0, index
= 0; byte
< GET_MODE_SIZE (TImode
);
4916 byte
+= UNITS_PER_WORD
, index
++)
4918 d
= mips_subword_at_byte (dest
, byte
);
4920 emit_insn (gen_msa_copy_s_w (d
, new_src
, GEN_INT (index
)));
4922 emit_insn (gen_msa_copy_s_d (d
, new_src
, GEN_INT (index
)));
4927 low_dest
= mips_subword_at_byte (dest
, 0);
4928 low_src
= mips_subword_at_byte (src
, 0);
4929 gcc_assert (REG_P (low_dest
) && REG_P (low_src
));
4930 /* Make sure the source register is not written before reading. */
4931 if (REGNO (low_dest
) <= REGNO (low_src
))
4933 for (byte
= 0; byte
< GET_MODE_SIZE (TImode
);
4934 byte
+= UNITS_PER_WORD
)
4936 d
= mips_subword_at_byte (dest
, byte
);
4937 s
= mips_subword_at_byte (src
, byte
);
4938 mips_emit_move (d
, s
);
4943 for (byte
= GET_MODE_SIZE (TImode
) - UNITS_PER_WORD
; byte
>= 0;
4944 byte
-= UNITS_PER_WORD
)
4946 d
= mips_subword_at_byte (dest
, byte
);
4947 s
= mips_subword_at_byte (src
, byte
);
4948 mips_emit_move (d
, s
);
4954 /* Split a COPY_S.D with operands DEST, SRC and INDEX. GEN is a function
4955 used to generate subregs. */
4958 mips_split_msa_copy_d (rtx dest
, rtx src
, rtx index
,
4959 rtx (*gen_fn
)(rtx
, rtx
, rtx
))
4961 gcc_assert ((GET_MODE (src
) == V2DImode
&& GET_MODE (dest
) == DImode
)
4962 || (GET_MODE (src
) == V2DFmode
&& GET_MODE (dest
) == DFmode
));
4964 /* Note that low is always from the lower index, and high is always
4965 from the higher index. */
4966 rtx low
= mips_subword (dest
, false);
4967 rtx high
= mips_subword (dest
, true);
4968 rtx new_src
= simplify_gen_subreg (V4SImode
, src
, GET_MODE (src
), 0);
4970 emit_insn (gen_fn (low
, new_src
, GEN_INT (INTVAL (index
) * 2)));
4971 emit_insn (gen_fn (high
, new_src
, GEN_INT (INTVAL (index
) * 2 + 1)));
4974 /* Split a INSERT.D with operand DEST, SRC1.INDEX and SRC2. */
4977 mips_split_msa_insert_d (rtx dest
, rtx src1
, rtx index
, rtx src2
)
4980 gcc_assert (GET_MODE (dest
) == GET_MODE (src1
));
4981 gcc_assert ((GET_MODE (dest
) == V2DImode
4982 && (GET_MODE (src2
) == DImode
|| src2
== const0_rtx
))
4983 || (GET_MODE (dest
) == V2DFmode
&& GET_MODE (src2
) == DFmode
));
4985 /* Note that low is always from the lower index, and high is always
4986 from the higher index. */
4987 rtx low
= mips_subword (src2
, false);
4988 rtx high
= mips_subword (src2
, true);
4989 rtx new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
4990 rtx new_src1
= simplify_gen_subreg (V4SImode
, src1
, GET_MODE (src1
), 0);
4991 i
= exact_log2 (INTVAL (index
));
4992 gcc_assert (i
!= -1);
4994 emit_insn (gen_msa_insert_w (new_dest
, low
, new_src1
,
4995 GEN_INT (1 << (i
* 2))));
4996 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
,
4997 GEN_INT (1 << (i
* 2 + 1))));
5003 mips_split_msa_fill_d (rtx dest
, rtx src
)
5005 gcc_assert ((GET_MODE (dest
) == V2DImode
5006 && (GET_MODE (src
) == DImode
|| src
== const0_rtx
))
5007 || (GET_MODE (dest
) == V2DFmode
&& GET_MODE (src
) == DFmode
));
5009 /* Note that low is always from the lower index, and high is always
5010 from the higher index. */
5012 if (src
== const0_rtx
)
5019 low
= mips_subword (src
, false);
5020 high
= mips_subword (src
, true);
5022 rtx new_dest
= simplify_gen_subreg (V4SImode
, dest
, GET_MODE (dest
), 0);
5023 emit_insn (gen_msa_fill_w (new_dest
, low
));
5024 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
, GEN_INT (1 << 1)));
5025 emit_insn (gen_msa_insert_w (new_dest
, high
, new_dest
, GEN_INT (1 << 3)));
5028 /* Return true if a move from SRC to DEST in INSN should be split. */
5031 mips_split_move_insn_p (rtx dest
, rtx src
, rtx insn
)
5033 return mips_split_move_p (dest
, src
, mips_insn_split_type (insn
));
5036 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
5040 mips_split_move_insn (rtx dest
, rtx src
, rtx insn
)
5042 mips_split_move (dest
, src
, mips_insn_split_type (insn
));
5045 /* Return the appropriate instructions to move SRC into DEST. Assume
5046 that SRC is operand 1 and DEST is operand 0. */
5049 mips_output_move (rtx dest
, rtx src
)
5051 enum rtx_code dest_code
= GET_CODE (dest
);
5052 enum rtx_code src_code
= GET_CODE (src
);
5053 machine_mode mode
= GET_MODE (dest
);
5054 bool dbl_p
= (GET_MODE_SIZE (mode
) == 8);
5055 bool msa_p
= MSA_SUPPORTED_MODE_P (mode
);
5056 enum mips_symbol_type symbol_type
;
5058 if (mips_split_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
5062 && dest_code
== REG
&& FP_REG_P (REGNO (dest
))
5063 && src_code
== CONST_VECTOR
5064 && CONST_INT_P (CONST_VECTOR_ELT (src
, 0)))
5066 gcc_assert (mips_const_vector_same_int_p (src
, mode
, -512, 511));
5067 return "ldi.%v0\t%w0,%E1";
5070 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
5071 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
5073 if (dest_code
== REG
)
5075 if (GP_REG_P (REGNO (dest
)))
5076 return "move\t%0,%z1";
5078 if (mips_mult_move_p (dest
, src
, SPLIT_IF_NECESSARY
))
5080 if (ISA_HAS_DSP_MULT
)
5081 return "mult\t%q0,%.,%.";
5083 return "mult\t%.,%.";
5086 /* Moves to HI are handled by special .md insns. */
5087 if (REGNO (dest
) == LO_REGNUM
)
5090 if (DSP_ACC_REG_P (REGNO (dest
)))
5092 static char retval
[] = "mt__\t%z1,%q0";
5094 retval
[2] = reg_names
[REGNO (dest
)][4];
5095 retval
[3] = reg_names
[REGNO (dest
)][5];
5099 if (FP_REG_P (REGNO (dest
)))
5103 gcc_assert (src
== CONST0_RTX (GET_MODE (src
)));
5104 return "ldi.%v0\t%w0,0";
5107 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
5110 if (ALL_COP_REG_P (REGNO (dest
)))
5112 static char retval
[] = "dmtc_\t%z1,%0";
5114 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
5115 return dbl_p
? retval
: retval
+ 1;
5118 if (dest_code
== MEM
)
5119 switch (GET_MODE_SIZE (mode
))
5121 case 1: return "sb\t%z1,%0";
5122 case 2: return "sh\t%z1,%0";
5123 case 4: return "sw\t%z1,%0";
5124 case 8: return "sd\t%z1,%0";
5125 default: gcc_unreachable ();
5128 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
5130 if (src_code
== REG
)
5132 /* Moves from HI are handled by special .md insns. */
5133 if (REGNO (src
) == LO_REGNUM
)
5135 /* When generating VR4120 or VR4130 code, we use MACC and
5136 DMACC instead of MFLO. This avoids both the normal
5137 MIPS III HI/LO hazards and the errata related to
5140 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
5144 if (DSP_ACC_REG_P (REGNO (src
)))
5146 static char retval
[] = "mf__\t%0,%q1";
5148 retval
[2] = reg_names
[REGNO (src
)][4];
5149 retval
[3] = reg_names
[REGNO (src
)][5];
5153 if (FP_REG_P (REGNO (src
)))
5155 gcc_assert (!msa_p
);
5156 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
5159 if (ALL_COP_REG_P (REGNO (src
)))
5161 static char retval
[] = "dmfc_\t%0,%1";
5163 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
5164 return dbl_p
? retval
: retval
+ 1;
5168 if (src_code
== MEM
)
5169 switch (GET_MODE_SIZE (mode
))
5171 case 1: return "lbu\t%0,%1";
5172 case 2: return "lhu\t%0,%1";
5173 case 4: return "lw\t%0,%1";
5174 case 8: return "ld\t%0,%1";
5175 default: gcc_unreachable ();
5178 if (src_code
== CONST_INT
)
5180 /* Don't use the X format for the operand itself, because that
5181 will give out-of-range numbers for 64-bit hosts and 32-bit
5184 return "li\t%0,%1\t\t\t# %X1";
5186 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
5189 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
5193 if (src_code
== HIGH
)
5194 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
5196 if (CONST_GP_P (src
))
5197 return "move\t%0,%1";
5199 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
5200 && mips_lo_relocs
[symbol_type
] != 0)
5202 /* A signed 16-bit constant formed by applying a relocation
5203 operator to a symbolic address. */
5204 gcc_assert (!mips_split_p
[symbol_type
]);
5205 return "li\t%0,%R1";
5208 if (symbolic_operand (src
, VOIDmode
))
5210 gcc_assert (TARGET_MIPS16
5211 ? TARGET_MIPS16_TEXT_LOADS
5212 : !TARGET_EXPLICIT_RELOCS
);
5213 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
5216 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
5218 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
5220 if (GET_MODE (dest
) == V2SFmode
)
5221 return "mov.ps\t%0,%1";
5223 return "move.v\t%w0,%w1";
5225 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
5228 if (dest_code
== MEM
)
5231 return "st.%v1\t%w1,%0";
5233 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
5236 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
5238 if (src_code
== MEM
)
5241 return "ld.%v0\t%w0,%1";
5243 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
5246 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
5248 static char retval
[] = "l_c_\t%0,%1";
5250 retval
[1] = (dbl_p
? 'd' : 'w');
5251 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
5254 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
5256 static char retval
[] = "s_c_\t%1,%0";
5258 retval
[1] = (dbl_p
? 'd' : 'w');
5259 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
5265 /* Return true if CMP1 is a suitable second operand for integer ordering
5266 test CODE. See also the *sCC patterns in mips.md. */
5269 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
5275 return reg_or_0_operand (cmp1
, VOIDmode
);
5279 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
5283 return arith_operand (cmp1
, VOIDmode
);
5286 return sle_operand (cmp1
, VOIDmode
);
5289 return sleu_operand (cmp1
, VOIDmode
);
5296 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
5297 integer ordering test *CODE, or if an equivalent combination can
5298 be formed by adjusting *CODE and *CMP1. When returning true, update
5299 *CODE and *CMP1 with the chosen code and operand, otherwise leave
5303 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
5306 HOST_WIDE_INT plus_one
;
5308 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
5311 if (CONST_INT_P (*cmp1
))
5315 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
5316 if (INTVAL (*cmp1
) < plus_one
)
5319 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
5325 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
5329 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
5340 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
5341 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
5342 is nonnull, it's OK to set TARGET to the inverse of the result and
5343 flip *INVERT_PTR instead. */
5346 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
5347 rtx target
, rtx cmp0
, rtx cmp1
)
5351 /* First see if there is a MIPS instruction that can do this operation.
5352 If not, try doing the same for the inverse operation. If that also
5353 fails, force CMP1 into a register and try again. */
5354 mode
= GET_MODE (cmp0
);
5355 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
5356 mips_emit_binary (code
, target
, cmp0
, cmp1
);
5359 enum rtx_code inv_code
= reverse_condition (code
);
5360 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
5362 cmp1
= force_reg (mode
, cmp1
);
5363 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
5365 else if (invert_ptr
== 0)
5369 inv_target
= mips_force_binary (GET_MODE (target
),
5370 inv_code
, cmp0
, cmp1
);
5371 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
5375 *invert_ptr
= !*invert_ptr
;
5376 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
5381 /* Return a register that is zero iff CMP0 and CMP1 are equal.
5382 The register will have the same mode as CMP0. */
5385 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
5387 if (cmp1
== const0_rtx
)
5390 if (uns_arith_operand (cmp1
, VOIDmode
))
5391 return expand_binop (GET_MODE (cmp0
), xor_optab
,
5392 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
5394 return expand_binop (GET_MODE (cmp0
), sub_optab
,
5395 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
5398 /* Convert *CODE into a code that can be used in a floating-point
5399 scc instruction (C.cond.fmt). Return true if the values of
5400 the condition code registers will be inverted, with 0 indicating
5401 that the condition holds. */
5404 mips_reversed_fp_cond (enum rtx_code
*code
)
5411 *code
= reverse_condition_maybe_unordered (*code
);
5419 /* Allocate a floating-point condition-code register of mode MODE.
5421 These condition code registers are used for certain kinds
5422 of compound operation, such as compare and branches, vconds,
5423 and built-in functions. At expand time, their use is entirely
5424 controlled by MIPS-specific code and is entirely internal
5425 to these compound operations.
5427 We could (and did in the past) expose condition-code values
5428 as pseudo registers and leave the register allocator to pick
5429 appropriate registers. The problem is that it is not practically
5430 possible for the rtl optimizers to guarantee that no spills will
5431 be needed, even when AVOID_CCMODE_COPIES is defined. We would
5432 therefore need spill and reload sequences to handle the worst case.
5434 Although such sequences do exist, they are very expensive and are
5435 not something we'd want to use. This is especially true of CCV2 and
5436 CCV4, where all the shuffling would greatly outweigh whatever benefit
5437 the vectorization itself provides.
5439 The main benefit of having more than one condition-code register
5440 is to allow the pipelining of operations, especially those involving
5441 comparisons and conditional moves. We don't really expect the
5442 registers to be live for long periods, and certainly never want
5443 them to be live across calls.
5445 Also, there should be no penalty attached to using all the available
5446 registers. They are simply bits in the same underlying FPU control
5449 We therefore expose the hardware registers from the outset and use
5450 a simple round-robin allocation scheme. */
5453 mips_allocate_fcc (machine_mode mode
)
5455 unsigned int regno
, count
;
5457 gcc_assert (TARGET_HARD_FLOAT
&& ISA_HAS_8CC
);
5461 else if (mode
== CCV2mode
)
5463 else if (mode
== CCV4mode
)
5468 cfun
->machine
->next_fcc
+= -cfun
->machine
->next_fcc
& (count
- 1);
5469 if (cfun
->machine
->next_fcc
> ST_REG_LAST
- ST_REG_FIRST
)
5470 cfun
->machine
->next_fcc
= 0;
5471 regno
= ST_REG_FIRST
+ cfun
->machine
->next_fcc
;
5472 cfun
->machine
->next_fcc
+= count
;
5473 return gen_rtx_REG (mode
, regno
);
5476 /* Convert a comparison into something that can be used in a branch or
5477 conditional move. On entry, *OP0 and *OP1 are the values being
5478 compared and *CODE is the code used to compare them.
5480 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
5481 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
5482 otherwise any standard branch condition can be used. The standard branch
5485 - EQ or NE between two registers.
5486 - any comparison between a register and zero.
5487 - if compact branches are available then any condition is valid. */
5490 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
5495 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
5497 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
5499 else if (*code
== EQ
|| *code
== NE
)
5503 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
5507 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5509 else if (!need_eq_ne_p
&& TARGET_CB_MAYBE
)
5539 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
5549 /* The comparison needs a separate scc instruction. Store the
5550 result of the scc in *OP0 and compare it against zero. */
5551 bool invert
= false;
5552 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
5553 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
5554 *code
= (invert
? EQ
: NE
);
5558 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
5560 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
5561 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
5567 enum rtx_code cmp_code
;
5569 /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt
5570 comparison to set a register. The branch or conditional move will
5571 then compare that register against zero.
5573 Set CMP_CODE to the code of the comparison instruction and
5574 *CODE to the code that the branch or move should use. */
5578 /* All FP conditions can be implemented directly with CMP.cond.fmt
5579 or by reversing the operands. */
5581 *op0
= gen_reg_rtx (CCFmode
);
5585 /* Three FP conditions cannot be implemented by reversing the
5586 operands for C.cond.fmt, instead a reversed condition code is
5587 required and a test for false. */
5588 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
5590 *op0
= mips_allocate_fcc (CCmode
);
5592 *op0
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
5596 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
5600 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
5601 and OPERAND[3]. Store the result in OPERANDS[0].
5603 On 64-bit targets, the mode of the comparison and target will always be
5604 SImode, thus possibly narrower than that of the comparison's operands. */
5607 mips_expand_scc (rtx operands
[])
5609 rtx target
= operands
[0];
5610 enum rtx_code code
= GET_CODE (operands
[1]);
5611 rtx op0
= operands
[2];
5612 rtx op1
= operands
[3];
5614 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
5616 if (code
== EQ
|| code
== NE
)
5619 && reg_imm10_operand (op1
, GET_MODE (op1
)))
5620 mips_emit_binary (code
, target
, op0
, op1
);
5623 rtx zie
= mips_zero_if_equal (op0
, op1
);
5624 mips_emit_binary (code
, target
, zie
, const0_rtx
);
5628 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
5631 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5632 CODE and jump to OPERANDS[3] if the condition holds. */
5635 mips_expand_conditional_branch (rtx
*operands
)
5637 enum rtx_code code
= GET_CODE (operands
[0]);
5638 rtx op0
= operands
[1];
5639 rtx op1
= operands
[2];
5642 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
5643 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
5644 emit_jump_insn (gen_condjump (condition
, operands
[3]));
5649 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5650 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5653 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
5654 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
5659 reversed_p
= mips_reversed_fp_cond (&cond
);
5660 cmp_result
= mips_allocate_fcc (CCV2mode
);
5661 emit_insn (gen_scc_ps (cmp_result
,
5662 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
5664 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
5667 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
5671 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5672 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5675 mips_expand_conditional_move (rtx
*operands
)
5678 enum rtx_code code
= GET_CODE (operands
[1]);
5679 rtx op0
= XEXP (operands
[1], 0);
5680 rtx op1
= XEXP (operands
[1], 1);
5682 mips_emit_compare (&code
, &op0
, &op1
, true);
5683 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
5685 /* There is no direct support for general conditional GP move involving
5686 two registers using SEL. */
5688 && INTEGRAL_MODE_P (GET_MODE (operands
[2]))
5689 && register_operand (operands
[2], VOIDmode
)
5690 && register_operand (operands
[3], VOIDmode
))
5692 machine_mode mode
= GET_MODE (operands
[0]);
5693 rtx temp
= gen_reg_rtx (mode
);
5694 rtx temp2
= gen_reg_rtx (mode
);
5696 emit_insn (gen_rtx_SET (temp
,
5697 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5698 operands
[2], const0_rtx
)));
5700 /* Flip the test for the second operand. */
5701 cond
= gen_rtx_fmt_ee ((code
== EQ
) ? NE
: EQ
, GET_MODE (op0
), op0
, op1
);
5703 emit_insn (gen_rtx_SET (temp2
,
5704 gen_rtx_IF_THEN_ELSE (mode
, cond
,
5705 operands
[3], const0_rtx
)));
5707 /* Merge the two results, at least one is guaranteed to be zero. */
5708 emit_insn (gen_rtx_SET (operands
[0], gen_rtx_IOR (mode
, temp
, temp2
)));
5712 if (FLOAT_MODE_P (GET_MODE (operands
[2])) && !ISA_HAS_SEL
)
5714 operands
[2] = force_reg (GET_MODE (operands
[0]), operands
[2]);
5715 operands
[3] = force_reg (GET_MODE (operands
[0]), operands
[3]);
5718 emit_insn (gen_rtx_SET (operands
[0],
5719 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
5720 operands
[2], operands
[3])));
5724 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5727 mips_expand_conditional_trap (rtx comparison
)
5733 /* MIPS conditional trap instructions don't have GT or LE flavors,
5734 so we must swap the operands and convert to LT and GE respectively. */
5735 code
= GET_CODE (comparison
);
5742 code
= swap_condition (code
);
5743 op0
= XEXP (comparison
, 1);
5744 op1
= XEXP (comparison
, 0);
5748 op0
= XEXP (comparison
, 0);
5749 op1
= XEXP (comparison
, 1);
5753 mode
= GET_MODE (XEXP (comparison
, 0));
5754 op0
= force_reg (mode
, op0
);
5755 if (!(ISA_HAS_COND_TRAPI
5756 ? arith_operand (op1
, mode
)
5757 : reg_or_0_operand (op1
, mode
)))
5758 op1
= force_reg (mode
, op1
);
5760 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
5761 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
5765 /* Initialize *CUM for a call to a function of type FNTYPE. */
5768 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
5770 memset (cum
, 0, sizeof (*cum
));
5771 cum
->prototype
= (fntype
&& prototype_p (fntype
));
5772 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
5775 /* Fill INFO with information about a single argument. CUM is the
5776 cumulative state for earlier arguments. MODE is the mode of this
5777 argument and TYPE is its type (if known). NAMED is true if this
5778 is a named (fixed) argument rather than a variable one. */
5781 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
5782 machine_mode mode
, const_tree type
, bool named
)
5784 bool doubleword_aligned_p
;
5785 unsigned int num_bytes
, num_words
, max_regs
;
5787 /* Work out the size of the argument. */
5788 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5789 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
5791 /* Decide whether it should go in a floating-point register, assuming
5792 one is free. Later code checks for availability.
5794 The checks against UNITS_PER_FPVALUE handle the soft-float and
5795 single-float cases. */
5799 /* The EABI conventions have traditionally been defined in terms
5800 of TYPE_MODE, regardless of the actual type. */
5801 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5802 || mode
== V2SFmode
)
5803 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5808 /* Only leading floating-point scalars are passed in
5809 floating-point registers. We also handle vector floats the same
5810 say, which is OK because they are not covered by the standard ABI. */
5811 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5812 info
->fpr_p
= (!cum
->gp_reg_found
5813 && cum
->arg_number
< 2
5815 || SCALAR_FLOAT_TYPE_P (type
)
5816 || VECTOR_FLOAT_TYPE_P (type
))
5817 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5818 || mode
== V2SFmode
)
5819 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5824 /* Scalar, complex and vector floating-point types are passed in
5825 floating-point registers, as long as this is a named rather
5826 than a variable argument. */
5827 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
5828 info
->fpr_p
= (named
5829 && (type
== 0 || FLOAT_TYPE_P (type
))
5830 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
5831 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5832 || mode
== V2SFmode
)
5833 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
5835 /* ??? According to the ABI documentation, the real and imaginary
5836 parts of complex floats should be passed in individual registers.
5837 The real and imaginary parts of stack arguments are supposed
5838 to be contiguous and there should be an extra word of padding
5841 This has two problems. First, it makes it impossible to use a
5842 single "void *" va_list type, since register and stack arguments
5843 are passed differently. (At the time of writing, MIPSpro cannot
5844 handle complex float varargs correctly.) Second, it's unclear
5845 what should happen when there is only one register free.
5847 For now, we assume that named complex floats should go into FPRs
5848 if there are two FPRs free, otherwise they should be passed in the
5849 same way as a struct containing two floats. */
5851 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5852 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
5854 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
5855 info
->fpr_p
= false;
5865 /* See whether the argument has doubleword alignment. */
5866 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
5869 /* Set REG_OFFSET to the register count we're interested in.
5870 The EABI allocates the floating-point registers separately,
5871 but the other ABIs allocate them like integer registers. */
5872 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
5876 /* Advance to an even register if the argument is doubleword-aligned. */
5877 if (doubleword_aligned_p
)
5878 info
->reg_offset
+= info
->reg_offset
& 1;
5880 /* Work out the offset of a stack argument. */
5881 info
->stack_offset
= cum
->stack_words
;
5882 if (doubleword_aligned_p
)
5883 info
->stack_offset
+= info
->stack_offset
& 1;
5885 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
5887 /* Partition the argument between registers and stack. */
5888 info
->reg_words
= MIN (num_words
, max_regs
);
5889 info
->stack_words
= num_words
- info
->reg_words
;
5892 /* INFO describes a register argument that has the normal format for the
5893 argument's mode. Return the register it uses, assuming that FPRs are
5894 available if HARD_FLOAT_P. */
5897 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
5899 if (!info
->fpr_p
|| !hard_float_p
)
5900 return GP_ARG_FIRST
+ info
->reg_offset
;
5901 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
5902 /* In o32, the second argument is always passed in $f14
5903 for TARGET_DOUBLE_FLOAT, regardless of whether the
5904 first argument was a word or doubleword. */
5905 return FP_ARG_FIRST
+ 2;
5907 return FP_ARG_FIRST
+ info
->reg_offset
;
5910 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5913 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
5915 return !TARGET_OLDABI
;
5918 /* Implement TARGET_FUNCTION_ARG. */
5921 mips_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
5922 const_tree type
, bool named
)
5924 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
5925 struct mips_arg_info info
;
5927 /* We will be called with a mode of VOIDmode after the last argument
5928 has been seen. Whatever we return will be passed to the call expander.
5929 If we need a MIPS16 fp_code, return a REG with the code stored as
5931 if (mode
== VOIDmode
)
5933 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
5934 return gen_rtx_REG ((machine_mode
) cum
->fp_code
, 0);
5939 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5941 /* Return straight away if the whole argument is passed on the stack. */
5942 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
5945 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5946 contains a double in its entirety, then that 64-bit chunk is passed
5947 in a floating-point register. */
5949 && TARGET_HARD_FLOAT
5952 && TREE_CODE (type
) == RECORD_TYPE
5953 && TYPE_SIZE_UNIT (type
)
5954 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
5958 /* First check to see if there is any such field. */
5959 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
5960 if (TREE_CODE (field
) == FIELD_DECL
5961 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5962 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
5963 && tree_fits_shwi_p (bit_position (field
))
5964 && int_bit_position (field
) % BITS_PER_WORD
== 0)
5969 /* Now handle the special case by returning a PARALLEL
5970 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5971 chunks are passed in registers. */
5973 HOST_WIDE_INT bitpos
;
5976 /* assign_parms checks the mode of ENTRY_PARM, so we must
5977 use the actual mode here. */
5978 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
5981 field
= TYPE_FIELDS (type
);
5982 for (i
= 0; i
< info
.reg_words
; i
++)
5986 for (; field
; field
= DECL_CHAIN (field
))
5987 if (TREE_CODE (field
) == FIELD_DECL
5988 && int_bit_position (field
) >= bitpos
)
5992 && int_bit_position (field
) == bitpos
5993 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
5994 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
5995 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
5997 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
6000 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
6001 GEN_INT (bitpos
/ BITS_PER_UNIT
));
6003 bitpos
+= BITS_PER_WORD
;
6009 /* Handle the n32/n64 conventions for passing complex floating-point
6010 arguments in FPR pairs. The real part goes in the lower register
6011 and the imaginary part goes in the upper register. */
6014 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6020 inner
= GET_MODE_INNER (mode
);
6021 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
6022 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
6024 /* Real part in registers, imaginary part on stack. */
6025 gcc_assert (info
.stack_words
== info
.reg_words
);
6026 return gen_rtx_REG (inner
, regno
);
6030 gcc_assert (info
.stack_words
== 0);
6031 real
= gen_rtx_EXPR_LIST (VOIDmode
,
6032 gen_rtx_REG (inner
, regno
),
6034 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
6036 regno
+ info
.reg_words
/ 2),
6037 GEN_INT (GET_MODE_SIZE (inner
)));
6038 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
6042 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
6045 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
6048 mips_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
6049 const_tree type
, bool named
)
6051 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6052 struct mips_arg_info info
;
6054 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
6057 cum
->gp_reg_found
= true;
6059 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
6060 an explanation of what this code does. It assumes that we're using
6061 either the o32 or the o64 ABI, both of which pass at most 2 arguments
6063 if (cum
->arg_number
< 2 && info
.fpr_p
)
6064 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
6066 /* Advance the register count. This has the effect of setting
6067 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
6068 argument required us to skip the final GPR and pass the whole
6069 argument on the stack. */
6070 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
6071 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
6072 else if (info
.reg_words
> 0)
6073 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
6075 /* Advance the stack word count. */
6076 if (info
.stack_words
> 0)
6077 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
6082 /* Implement TARGET_ARG_PARTIAL_BYTES. */
6085 mips_arg_partial_bytes (cumulative_args_t cum
,
6086 machine_mode mode
, tree type
, bool named
)
6088 struct mips_arg_info info
;
6090 mips_get_arg_info (&info
, get_cumulative_args (cum
), mode
, type
, named
);
6091 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
6094 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
6095 least PARM_BOUNDARY bits of alignment, but will be given anything up
6096 to STACK_BOUNDARY bits if the type requires it. */
6099 mips_function_arg_boundary (machine_mode mode
, const_tree type
)
6101 unsigned int alignment
;
6103 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
6104 if (alignment
< PARM_BOUNDARY
)
6105 alignment
= PARM_BOUNDARY
;
6106 if (alignment
> STACK_BOUNDARY
)
6107 alignment
= STACK_BOUNDARY
;
6111 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
6113 static fixed_size_mode
6114 mips_get_reg_raw_mode (int regno
)
6116 if (TARGET_FLOATXX
&& FP_REG_P (regno
))
6118 return default_get_reg_raw_mode (regno
);
6121 /* Implement TARGET_FUNCTION_ARG_PADDING; return PAD_UPWARD if the first
6122 byte of the stack slot has useful data, PAD_DOWNWARD if the last byte
6125 static pad_direction
6126 mips_function_arg_padding (machine_mode mode
, const_tree type
)
6128 /* On little-endian targets, the first byte of every stack argument
6129 is passed in the first byte of the stack slot. */
6130 if (!BYTES_BIG_ENDIAN
)
6133 /* Otherwise, integral types are padded downward: the last byte of a
6134 stack argument is passed in the last byte of the stack slot. */
6136 ? (INTEGRAL_TYPE_P (type
)
6137 || POINTER_TYPE_P (type
)
6138 || FIXED_POINT_TYPE_P (type
))
6139 : (SCALAR_INT_MODE_P (mode
)
6140 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
6141 return PAD_DOWNWARD
;
6143 /* Big-endian o64 pads floating-point arguments downward. */
6144 if (mips_abi
== ABI_O64
)
6145 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6146 return PAD_DOWNWARD
;
6148 /* Other types are padded upward for o32, o64, n32 and n64. */
6149 if (mips_abi
!= ABI_EABI
)
6152 /* Arguments smaller than a stack slot are padded downward. */
6154 ? GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
6155 : int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
))
6158 return PAD_DOWNWARD
;
6161 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
6162 if the least significant byte of the register has useful data. Return
6163 the opposite if the most significant byte does. */
6166 mips_pad_reg_upward (machine_mode mode
, tree type
)
6168 /* No shifting is required for floating-point arguments. */
6169 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
6170 return !BYTES_BIG_ENDIAN
;
6172 /* Otherwise, apply the same padding to register arguments as we do
6173 to stack arguments. */
6174 return mips_function_arg_padding (mode
, type
) == PAD_UPWARD
;
6177 /* Return nonzero when an argument must be passed by reference. */
6180 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6181 machine_mode mode
, const_tree type
,
6182 bool named ATTRIBUTE_UNUSED
)
6184 if (mips_abi
== ABI_EABI
)
6188 /* ??? How should SCmode be handled? */
6189 if (mode
== DImode
|| mode
== DFmode
6190 || mode
== DQmode
|| mode
== UDQmode
6191 || mode
== DAmode
|| mode
== UDAmode
)
6194 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
6195 return size
== -1 || size
> UNITS_PER_WORD
;
6199 /* If we have a variable-sized parameter, we have no choice. */
6200 return targetm
.calls
.must_pass_in_stack (mode
, type
);
6204 /* Implement TARGET_CALLEE_COPIES. */
6207 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED
,
6208 machine_mode mode ATTRIBUTE_UNUSED
,
6209 const_tree type ATTRIBUTE_UNUSED
, bool named
)
6211 return mips_abi
== ABI_EABI
&& named
;
6214 /* See whether VALTYPE is a record whose fields should be returned in
6215 floating-point registers. If so, return the number of fields and
6216 list them in FIELDS (which should have two elements). Return 0
6219 For n32 & n64, a structure with one or two fields is returned in
6220 floating-point registers as long as every field has a floating-point
6224 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
6232 if (TREE_CODE (valtype
) != RECORD_TYPE
)
6236 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
6238 if (TREE_CODE (field
) != FIELD_DECL
)
6241 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
6247 fields
[i
++] = field
;
6252 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
6253 a value in the most significant part of $2/$3 if:
6255 - the target is big-endian;
6257 - the value has a structure or union type (we generalize this to
6258 cover aggregates from other languages too); and
6260 - the structure is not returned in floating-point registers. */
6263 mips_return_in_msb (const_tree valtype
)
6267 return (TARGET_NEWABI
6268 && TARGET_BIG_ENDIAN
6269 && AGGREGATE_TYPE_P (valtype
)
6270 && mips_fpr_return_fields (valtype
, fields
) == 0);
6273 /* Return true if the function return value MODE will get returned in a
6274 floating-point register. */
6277 mips_return_mode_in_fpr_p (machine_mode mode
)
6279 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
|| mode
!= V2SFmode
);
6280 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
6282 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6283 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
6286 /* Return the representation of an FPR return register when the
6287 value being returned in FP_RETURN has mode VALUE_MODE and the
6288 return type itself has mode TYPE_MODE. On NewABI targets,
6289 the two modes may be different for structures like:
6291 struct __attribute__((packed)) foo { float f; }
6293 where we return the SFmode value of "f" in FP_RETURN, but where
6294 the structure itself has mode BLKmode. */
6297 mips_return_fpr_single (machine_mode type_mode
,
6298 machine_mode value_mode
)
6302 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
6303 if (type_mode
!= value_mode
)
6305 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
6306 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
6311 /* Return a composite value in a pair of floating-point registers.
6312 MODE1 and OFFSET1 are the mode and byte offset for the first value,
6313 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
6316 For n32 & n64, $f0 always holds the first value and $f2 the second.
6317 Otherwise the values are packed together as closely as possible. */
6320 mips_return_fpr_pair (machine_mode mode
,
6321 machine_mode mode1
, HOST_WIDE_INT offset1
,
6322 machine_mode mode2
, HOST_WIDE_INT offset2
)
6326 inc
= (TARGET_NEWABI
|| mips_abi
== ABI_32
? 2 : MAX_FPRS_PER_FMT
);
6327 return gen_rtx_PARALLEL
6330 gen_rtx_EXPR_LIST (VOIDmode
,
6331 gen_rtx_REG (mode1
, FP_RETURN
),
6333 gen_rtx_EXPR_LIST (VOIDmode
,
6334 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
6335 GEN_INT (offset2
))));
6339 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
6340 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
6341 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
6344 mips_function_value_1 (const_tree valtype
, const_tree fn_decl_or_type
,
6353 if (fn_decl_or_type
&& DECL_P (fn_decl_or_type
))
6354 func
= fn_decl_or_type
;
6358 mode
= TYPE_MODE (valtype
);
6359 unsigned_p
= TYPE_UNSIGNED (valtype
);
6361 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
6362 return values, promote the mode here too. */
6363 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
6365 /* Handle structures whose fields are returned in $f0/$f2. */
6366 switch (mips_fpr_return_fields (valtype
, fields
))
6369 return mips_return_fpr_single (mode
,
6370 TYPE_MODE (TREE_TYPE (fields
[0])));
6373 return mips_return_fpr_pair (mode
,
6374 TYPE_MODE (TREE_TYPE (fields
[0])),
6375 int_byte_position (fields
[0]),
6376 TYPE_MODE (TREE_TYPE (fields
[1])),
6377 int_byte_position (fields
[1]));
6380 /* If a value is passed in the most significant part of a register, see
6381 whether we have to round the mode up to a whole number of words. */
6382 if (mips_return_in_msb (valtype
))
6384 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
6385 if (size
% UNITS_PER_WORD
!= 0)
6387 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
6388 mode
= int_mode_for_size (size
* BITS_PER_UNIT
, 0).require ();
6392 /* For EABI, the class of return register depends entirely on MODE.
6393 For example, "struct { some_type x; }" and "union { some_type x; }"
6394 are returned in the same way as a bare "some_type" would be.
6395 Other ABIs only use FPRs for scalar, complex or vector types. */
6396 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
6397 return gen_rtx_REG (mode
, GP_RETURN
);
6402 /* Handle long doubles for n32 & n64. */
6404 return mips_return_fpr_pair (mode
,
6406 DImode
, GET_MODE_SIZE (mode
) / 2);
6408 if (mips_return_mode_in_fpr_p (mode
))
6410 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6411 return mips_return_fpr_pair (mode
,
6412 GET_MODE_INNER (mode
), 0,
6413 GET_MODE_INNER (mode
),
6414 GET_MODE_SIZE (mode
) / 2);
6416 return gen_rtx_REG (mode
, FP_RETURN
);
6420 return gen_rtx_REG (mode
, GP_RETURN
);
6423 /* Implement TARGET_FUNCTION_VALUE. */
6426 mips_function_value (const_tree valtype
, const_tree fn_decl_or_type
,
6427 bool outgoing ATTRIBUTE_UNUSED
)
6429 return mips_function_value_1 (valtype
, fn_decl_or_type
, VOIDmode
);
6432 /* Implement TARGET_LIBCALL_VALUE. */
6435 mips_libcall_value (machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
6437 return mips_function_value_1 (NULL_TREE
, NULL_TREE
, mode
);
6440 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
6442 On the MIPS, R2 R3 and F0 F2 are the only register thus used. */
6445 mips_function_value_regno_p (const unsigned int regno
)
6447 /* Most types only require one GPR or one FPR for return values but for
6448 hard-float two FPRs can be used for _Complex types (for all ABIs)
6449 and long doubles (for n64). */
6450 if (regno
== GP_RETURN
6451 || regno
== FP_RETURN
6452 || (FP_RETURN
!= GP_RETURN
6453 && regno
== FP_RETURN
+ 2))
6456 /* For o32 FP32, _Complex double will be returned in four 32-bit registers.
6457 This does not apply to o32 FPXX as floating-point function argument and
6458 return registers are described as 64-bit even though floating-point
6459 registers are primarily described as 32-bit internally.
6460 See: mips_get_reg_raw_mode. */
6461 if ((mips_abi
== ABI_32
&& TARGET_FLOAT32
)
6462 && FP_RETURN
!= GP_RETURN
6463 && (regno
== FP_RETURN
+ 1
6464 || regno
== FP_RETURN
+ 3))
6470 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
6471 all BLKmode objects are returned in memory. Under the n32, n64
6472 and embedded ABIs, small structures are returned in a register.
6473 Objects with varying size must still be returned in memory, of
6477 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
6480 /* Ensure that any floating point vector types are returned via memory
6481 even if they are supported through a vector mode with some ASEs. */
6482 return (VECTOR_FLOAT_TYPE_P (type
)
6483 || TYPE_MODE (type
) == BLKmode
);
6485 return (!IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
6488 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
6491 mips_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
6492 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
6495 CUMULATIVE_ARGS local_cum
;
6496 int gp_saved
, fp_saved
;
6498 /* The caller has advanced CUM up to, but not beyond, the last named
6499 argument. Advance a local copy of CUM past the last "real" named
6500 argument, to find out how many registers are left over. */
6501 local_cum
= *get_cumulative_args (cum
);
6502 mips_function_arg_advance (pack_cumulative_args (&local_cum
), mode
, type
,
6505 /* Found out how many registers we need to save. */
6506 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
6507 fp_saved
= (EABI_FLOAT_VARARGS_P
6508 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
6517 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
,
6518 REG_PARM_STACK_SPACE (cfun
->decl
)
6519 - gp_saved
* UNITS_PER_WORD
);
6520 mem
= gen_frame_mem (BLKmode
, ptr
);
6521 set_mem_alias_set (mem
, get_varargs_alias_set ());
6523 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
6528 /* We can't use move_block_from_reg, because it will use
6533 /* Set OFF to the offset from virtual_incoming_args_rtx of
6534 the first float register. The FP save area lies below
6535 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
6536 off
= ROUND_DOWN (-gp_saved
* UNITS_PER_WORD
, UNITS_PER_FPVALUE
);
6537 off
-= fp_saved
* UNITS_PER_FPREG
;
6539 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
6541 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
6542 i
+= MAX_FPRS_PER_FMT
)
6546 ptr
= plus_constant (Pmode
, virtual_incoming_args_rtx
, off
);
6547 mem
= gen_frame_mem (mode
, ptr
);
6548 set_mem_alias_set (mem
, get_varargs_alias_set ());
6549 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
6550 off
+= UNITS_PER_HWFPVALUE
;
6554 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
6555 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
6556 + fp_saved
* UNITS_PER_FPREG
);
6559 /* Implement TARGET_BUILTIN_VA_LIST. */
6562 mips_build_builtin_va_list (void)
6564 if (EABI_FLOAT_VARARGS_P
)
6566 /* We keep 3 pointers, and two offsets.
6568 Two pointers are to the overflow area, which starts at the CFA.
6569 One of these is constant, for addressing into the GPR save area
6570 below it. The other is advanced up the stack through the
6573 The third pointer is to the bottom of the GPR save area.
6574 Since the FPR save area is just below it, we can address
6575 FPR slots off this pointer.
6577 We also keep two one-byte offsets, which are to be subtracted
6578 from the constant pointers to yield addresses in the GPR and
6579 FPR save areas. These are downcounted as float or non-float
6580 arguments are used, and when they get to zero, the argument
6581 must be obtained from the overflow region. */
6582 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
6585 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
6587 f_ovfl
= build_decl (BUILTINS_LOCATION
,
6588 FIELD_DECL
, get_identifier ("__overflow_argptr"),
6590 f_gtop
= build_decl (BUILTINS_LOCATION
,
6591 FIELD_DECL
, get_identifier ("__gpr_top"),
6593 f_ftop
= build_decl (BUILTINS_LOCATION
,
6594 FIELD_DECL
, get_identifier ("__fpr_top"),
6596 f_goff
= build_decl (BUILTINS_LOCATION
,
6597 FIELD_DECL
, get_identifier ("__gpr_offset"),
6598 unsigned_char_type_node
);
6599 f_foff
= build_decl (BUILTINS_LOCATION
,
6600 FIELD_DECL
, get_identifier ("__fpr_offset"),
6601 unsigned_char_type_node
);
6602 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
6603 warn on every user file. */
6604 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
6605 array
= build_array_type (unsigned_char_type_node
,
6606 build_index_type (index
));
6607 f_res
= build_decl (BUILTINS_LOCATION
,
6608 FIELD_DECL
, get_identifier ("__reserved"), array
);
6610 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
6611 DECL_FIELD_CONTEXT (f_gtop
) = record
;
6612 DECL_FIELD_CONTEXT (f_ftop
) = record
;
6613 DECL_FIELD_CONTEXT (f_goff
) = record
;
6614 DECL_FIELD_CONTEXT (f_foff
) = record
;
6615 DECL_FIELD_CONTEXT (f_res
) = record
;
6617 TYPE_FIELDS (record
) = f_ovfl
;
6618 DECL_CHAIN (f_ovfl
) = f_gtop
;
6619 DECL_CHAIN (f_gtop
) = f_ftop
;
6620 DECL_CHAIN (f_ftop
) = f_goff
;
6621 DECL_CHAIN (f_goff
) = f_foff
;
6622 DECL_CHAIN (f_foff
) = f_res
;
6624 layout_type (record
);
6628 /* Otherwise, we use 'void *'. */
6629 return ptr_type_node
;
6632 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6635 mips_va_start (tree valist
, rtx nextarg
)
6637 if (EABI_FLOAT_VARARGS_P
)
6639 const CUMULATIVE_ARGS
*cum
;
6640 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6641 tree ovfl
, gtop
, ftop
, goff
, foff
;
6643 int gpr_save_area_size
;
6644 int fpr_save_area_size
;
6647 cum
= &crtl
->args
.info
;
6649 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
6651 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
6653 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6654 f_gtop
= DECL_CHAIN (f_ovfl
);
6655 f_ftop
= DECL_CHAIN (f_gtop
);
6656 f_goff
= DECL_CHAIN (f_ftop
);
6657 f_foff
= DECL_CHAIN (f_goff
);
6659 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6661 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
6663 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
6665 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
6667 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
6670 /* Emit code to initialize OVFL, which points to the next varargs
6671 stack argument. CUM->STACK_WORDS gives the number of stack
6672 words used by named arguments. */
6673 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
6674 if (cum
->stack_words
> 0)
6675 t
= fold_build_pointer_plus_hwi (t
, cum
->stack_words
* UNITS_PER_WORD
);
6676 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
6677 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6679 /* Emit code to initialize GTOP, the top of the GPR save area. */
6680 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
6681 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
6682 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6684 /* Emit code to initialize FTOP, the top of the FPR save area.
6685 This address is gpr_save_area_bytes below GTOP, rounded
6686 down to the next fp-aligned boundary. */
6687 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
6688 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
6689 fpr_offset
&= -UNITS_PER_FPVALUE
;
6691 t
= fold_build_pointer_plus_hwi (t
, -fpr_offset
);
6692 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
6693 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6695 /* Emit code to initialize GOFF, the offset from GTOP of the
6696 next GPR argument. */
6697 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
6698 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
6699 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6701 /* Likewise emit code to initialize FOFF, the offset from FTOP
6702 of the next FPR argument. */
6703 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
6704 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
6705 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
6709 nextarg
= plus_constant (Pmode
, nextarg
, -cfun
->machine
->varargs_size
);
6710 std_expand_builtin_va_start (valist
, nextarg
);
6714 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6718 mips_std_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6721 tree addr
, t
, type_size
, rounded_size
, valist_tmp
;
6722 unsigned HOST_WIDE_INT align
, boundary
;
6725 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
6727 type
= build_pointer_type (type
);
6729 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
6730 boundary
= targetm
.calls
.function_arg_boundary (TYPE_MODE (type
), type
);
6732 /* When we align parameter on stack for caller, if the parameter
6733 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6734 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6735 here with caller. */
6736 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
6737 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
6739 boundary
/= BITS_PER_UNIT
;
6741 /* Hoist the valist value into a temporary for the moment. */
6742 valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
6744 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6745 requires greater alignment, we must perform dynamic alignment. */
6746 if (boundary
> align
)
6748 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6749 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
6750 gimplify_and_add (t
, pre_p
);
6752 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
6753 fold_build2 (BIT_AND_EXPR
, TREE_TYPE (valist
),
6755 build_int_cst (TREE_TYPE (valist
), -boundary
)));
6756 gimplify_and_add (t
, pre_p
);
6761 /* If the actual alignment is less than the alignment of the type,
6762 adjust the type accordingly so that we don't assume strict alignment
6763 when dereferencing the pointer. */
6764 boundary
*= BITS_PER_UNIT
;
6765 if (boundary
< TYPE_ALIGN (type
))
6767 type
= build_variant_type_copy (type
);
6768 SET_TYPE_ALIGN (type
, boundary
);
6771 /* Compute the rounded size of the type. */
6772 type_size
= size_in_bytes (type
);
6773 rounded_size
= round_up (type_size
, align
);
6775 /* Reduce rounded_size so it's sharable with the postqueue. */
6776 gimplify_expr (&rounded_size
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
6780 if (PAD_VARARGS_DOWN
&& !integer_zerop (rounded_size
))
6782 /* Small args are padded downward. */
6783 t
= fold_build2_loc (input_location
, GT_EXPR
, sizetype
,
6784 rounded_size
, size_int (align
));
6785 t
= fold_build3 (COND_EXPR
, sizetype
, t
, size_zero_node
,
6786 size_binop (MINUS_EXPR
, rounded_size
, type_size
));
6787 addr
= fold_build_pointer_plus (addr
, t
);
6790 /* Compute new value for AP. */
6791 t
= fold_build_pointer_plus (valist_tmp
, rounded_size
);
6792 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
6793 gimplify_and_add (t
, pre_p
);
6795 addr
= fold_convert (build_pointer_type (type
), addr
);
6798 addr
= build_va_arg_indirect_ref (addr
);
6800 return build_va_arg_indirect_ref (addr
);
6803 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6806 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
6812 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
6814 type
= build_pointer_type (type
);
6816 if (!EABI_FLOAT_VARARGS_P
)
6817 addr
= mips_std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
6820 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
6821 tree ovfl
, top
, off
, align
;
6822 HOST_WIDE_INT size
, rsize
, osize
;
6825 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
6826 f_gtop
= DECL_CHAIN (f_ovfl
);
6827 f_ftop
= DECL_CHAIN (f_gtop
);
6828 f_goff
= DECL_CHAIN (f_ftop
);
6829 f_foff
= DECL_CHAIN (f_goff
);
6833 TOP be the top of the GPR or FPR save area;
6834 OFF be the offset from TOP of the next register;
6835 ADDR_RTX be the address of the argument;
6836 SIZE be the number of bytes in the argument type;
6837 RSIZE be the number of bytes used to store the argument
6838 when it's in the register save area; and
6839 OSIZE be the number of bytes used to store it when it's
6840 in the stack overflow area.
6842 The code we want is:
6844 1: off &= -rsize; // round down
6847 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6852 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6853 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6857 [1] and [9] can sometimes be optimized away. */
6859 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
6861 size
= int_size_in_bytes (type
);
6863 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
6864 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
6866 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
6867 unshare_expr (valist
), f_ftop
, NULL_TREE
);
6868 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
6869 unshare_expr (valist
), f_foff
, NULL_TREE
);
6871 /* When va_start saves FPR arguments to the stack, each slot
6872 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6873 argument's precision. */
6874 rsize
= UNITS_PER_HWFPVALUE
;
6876 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6877 (= PARM_BOUNDARY bits). This can be different from RSIZE
6880 (1) On 32-bit targets when TYPE is a structure such as:
6882 struct s { float f; };
6884 Such structures are passed in paired FPRs, so RSIZE
6885 will be 8 bytes. However, the structure only takes
6886 up 4 bytes of memory, so OSIZE will only be 4.
6888 (2) In combinations such as -mgp64 -msingle-float
6889 -fshort-double. Doubles passed in registers will then take
6890 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6891 stack take up UNITS_PER_WORD bytes. */
6892 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
6896 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
6897 unshare_expr (valist
), f_gtop
, NULL_TREE
);
6898 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
6899 unshare_expr (valist
), f_goff
, NULL_TREE
);
6900 rsize
= ROUND_UP (size
, UNITS_PER_WORD
);
6901 if (rsize
> UNITS_PER_WORD
)
6903 /* [1] Emit code for: off &= -rsize. */
6904 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
6905 build_int_cst (TREE_TYPE (off
), -rsize
));
6906 gimplify_assign (unshare_expr (off
), t
, pre_p
);
6911 /* [2] Emit code to branch if off == 0. */
6912 t
= build2 (NE_EXPR
, boolean_type_node
, unshare_expr (off
),
6913 build_int_cst (TREE_TYPE (off
), 0));
6914 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
6916 /* [5] Emit code for: off -= rsize. We do this as a form of
6917 post-decrement not available to C. */
6918 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
6919 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
6921 /* [4] Emit code for:
6922 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6923 t
= fold_convert (sizetype
, t
);
6924 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
6925 t
= fold_build_pointer_plus (top
, t
);
6926 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
6927 t
= fold_build_pointer_plus_hwi (t
, rsize
- size
);
6928 COND_EXPR_THEN (addr
) = t
;
6930 if (osize
> UNITS_PER_WORD
)
6932 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6933 t
= fold_build_pointer_plus_hwi (unshare_expr (ovfl
), osize
- 1);
6934 u
= build_int_cst (TREE_TYPE (t
), -osize
);
6935 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
, u
);
6936 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
6937 unshare_expr (ovfl
), t
);
6942 /* [10, 11] Emit code for:
6943 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6945 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
6946 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
6947 if (BYTES_BIG_ENDIAN
&& osize
> size
)
6948 t
= fold_build_pointer_plus_hwi (t
, osize
- size
);
6950 /* String [9] and [10, 11] together. */
6952 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
6953 COND_EXPR_ELSE (addr
) = t
;
6955 addr
= fold_convert (build_pointer_type (type
), addr
);
6956 addr
= build_va_arg_indirect_ref (addr
);
6960 addr
= build_va_arg_indirect_ref (addr
);
6965 /* Declare a unique, locally-binding function called NAME, then start
6969 mips_start_unique_function (const char *name
)
6973 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
6974 get_identifier (name
),
6975 build_function_type_list (void_type_node
, NULL_TREE
));
6976 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
6977 NULL_TREE
, void_type_node
);
6978 TREE_PUBLIC (decl
) = 1;
6979 TREE_STATIC (decl
) = 1;
6981 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
6983 targetm
.asm_out
.unique_section (decl
, 0);
6984 switch_to_section (get_named_section (decl
, NULL
, 0));
6986 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
6987 fputs ("\t.hidden\t", asm_out_file
);
6988 assemble_name (asm_out_file
, name
);
6989 putc ('\n', asm_out_file
);
6992 /* Start a definition of function NAME. MIPS16_P indicates whether the
6993 function contains MIPS16 code. */
6996 mips_start_function_definition (const char *name
, bool mips16_p
)
6999 fprintf (asm_out_file
, "\t.set\tmips16\n");
7001 fprintf (asm_out_file
, "\t.set\tnomips16\n");
7003 if (TARGET_MICROMIPS
)
7004 fprintf (asm_out_file
, "\t.set\tmicromips\n");
7005 #ifdef HAVE_GAS_MICROMIPS
7007 fprintf (asm_out_file
, "\t.set\tnomicromips\n");
7010 if (!flag_inhibit_size_directive
)
7012 fputs ("\t.ent\t", asm_out_file
);
7013 assemble_name (asm_out_file
, name
);
7014 fputs ("\n", asm_out_file
);
7017 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
7019 /* Start the definition proper. */
7020 assemble_name (asm_out_file
, name
);
7021 fputs (":\n", asm_out_file
);
7024 /* End a function definition started by mips_start_function_definition. */
7027 mips_end_function_definition (const char *name
)
7029 if (!flag_inhibit_size_directive
)
7031 fputs ("\t.end\t", asm_out_file
);
7032 assemble_name (asm_out_file
, name
);
7033 fputs ("\n", asm_out_file
);
7037 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
7038 then free *STUB_PTR. */
7041 mips_finish_stub (mips_one_only_stub
**stub_ptr
)
7043 mips_one_only_stub
*stub
= *stub_ptr
;
7047 const char *name
= stub
->get_name ();
7048 mips_start_unique_function (name
);
7049 mips_start_function_definition (name
, false);
7050 stub
->output_body ();
7051 mips_end_function_definition (name
);
7056 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
7059 mips_ok_for_lazy_binding_p (rtx x
)
7061 return (TARGET_USE_GOT
7062 && GET_CODE (x
) == SYMBOL_REF
7063 && !SYMBOL_REF_BIND_NOW_P (x
)
7064 && !mips_symbol_binds_local_p (x
));
7067 /* Load function address ADDR into register DEST. TYPE is as for
7068 mips_expand_call. Return true if we used an explicit lazy-binding
7072 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
7074 /* If we're generating PIC, and this call is to a global function,
7075 try to allow its address to be resolved lazily. This isn't
7076 possible for sibcalls when $gp is call-saved because the value
7077 of $gp on entry to the stub would be our caller's gp, not ours. */
7078 if (TARGET_EXPLICIT_RELOCS
7079 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
7080 && mips_ok_for_lazy_binding_p (addr
))
7082 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
7083 emit_insn (gen_rtx_SET (dest
, addr
));
7088 mips_emit_move (dest
, addr
);
7093 /* Each locally-defined hard-float MIPS16 function has a local symbol
7094 associated with it. This hash table maps the function symbol (FUNC)
7095 to the local symbol (LOCAL). */
7096 static GTY (()) hash_map
<nofree_string_hash
, rtx
> *mips16_local_aliases
;
7098 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
7099 Return a local alias for it, creating a new one if necessary. */
7102 mips16_local_alias (rtx func
)
7104 /* Create the hash table if this is the first call. */
7105 if (mips16_local_aliases
== NULL
)
7106 mips16_local_aliases
= hash_map
<nofree_string_hash
, rtx
>::create_ggc (37);
7108 /* Look up the function symbol, creating a new entry if need be. */
7110 const char *func_name
= XSTR (func
, 0);
7111 rtx
*slot
= &mips16_local_aliases
->get_or_insert (func_name
, &existed
);
7112 gcc_assert (slot
!= NULL
);
7118 /* Create a new SYMBOL_REF for the local symbol. The choice of
7119 __fn_local_* is based on the __fn_stub_* names that we've
7120 traditionally used for the non-MIPS16 stub. */
7121 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
7122 const char *local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
7123 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
7124 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
7126 /* Create a new structure to represent the mapping. */
7132 /* A chained list of functions for which mips16_build_call_stub has already
7133 generated a stub. NAME is the name of the function and FP_RET_P is true
7134 if the function returns a value in floating-point registers. */
7135 struct mips16_stub
{
7136 struct mips16_stub
*next
;
7140 static struct mips16_stub
*mips16_stubs
;
7142 /* Return the two-character string that identifies floating-point
7143 return mode MODE in the name of a MIPS16 function stub. */
7146 mips16_call_stub_mode_suffix (machine_mode mode
)
7150 else if (mode
== DFmode
)
7152 else if (mode
== SCmode
)
7154 else if (mode
== DCmode
)
7156 else if (mode
== V2SFmode
)
7158 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
);
7165 /* Write instructions to move a 32-bit value between general register
7166 GPREG and floating-point register FPREG. DIRECTION is 't' to move
7167 from GPREG to FPREG and 'f' to move in the opposite direction. */
7170 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
7172 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7173 reg_names
[gpreg
], reg_names
[fpreg
]);
7176 /* Likewise for 64-bit values. */
7179 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
7182 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
7183 reg_names
[gpreg
], reg_names
[fpreg
]);
7184 else if (ISA_HAS_MXHC1
)
7186 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7187 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
7188 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
7189 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
7191 else if (TARGET_FLOATXX
&& direction
== 't')
7193 /* Use the argument save area to move via memory. */
7194 fprintf (asm_out_file
, "\tsw\t%s,0($sp)\n", reg_names
[gpreg
]);
7195 fprintf (asm_out_file
, "\tsw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
7196 fprintf (asm_out_file
, "\tldc1\t%s,0($sp)\n", reg_names
[fpreg
]);
7198 else if (TARGET_FLOATXX
&& direction
== 'f')
7200 /* Use the argument save area to move via memory. */
7201 fprintf (asm_out_file
, "\tsdc1\t%s,0($sp)\n", reg_names
[fpreg
]);
7202 fprintf (asm_out_file
, "\tlw\t%s,0($sp)\n", reg_names
[gpreg
]);
7203 fprintf (asm_out_file
, "\tlw\t%s,4($sp)\n", reg_names
[gpreg
+ 1]);
7207 /* Move the least-significant word. */
7208 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7209 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
7210 /* ...then the most significant word. */
7211 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
7212 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
7216 /* Write out code to move floating-point arguments into or out of
7217 general registers. FP_CODE is the code describing which arguments
7218 are present (see the comment above the definition of CUMULATIVE_ARGS
7219 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
7222 mips_output_args_xfer (int fp_code
, char direction
)
7224 unsigned int gparg
, fparg
, f
;
7225 CUMULATIVE_ARGS cum
;
7227 /* This code only works for o32 and o64. */
7228 gcc_assert (TARGET_OLDABI
);
7230 mips_init_cumulative_args (&cum
, NULL
);
7232 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7235 struct mips_arg_info info
;
7239 else if ((f
& 3) == 2)
7244 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
7245 gparg
= mips_arg_regno (&info
, false);
7246 fparg
= mips_arg_regno (&info
, true);
7249 mips_output_32bit_xfer (direction
, gparg
, fparg
);
7251 mips_output_64bit_xfer (direction
, gparg
, fparg
);
7253 mips_function_arg_advance (pack_cumulative_args (&cum
), mode
, NULL
, true);
7257 /* Write a MIPS16 stub for the current function. This stub is used
7258 for functions which take arguments in the floating-point registers.
7259 It is normal-mode code that moves the floating-point arguments
7260 into the general registers and then jumps to the MIPS16 code. */
7263 mips16_build_function_stub (void)
7265 const char *fnname
, *alias_name
, *separator
;
7266 char *secname
, *stubname
;
7271 /* Create the name of the stub, and its unique section. */
7272 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
7273 alias
= mips16_local_alias (symbol
);
7275 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
7276 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
7277 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
7278 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
7280 /* Build a decl for the stub. */
7281 stubdecl
= build_decl (BUILTINS_LOCATION
,
7282 FUNCTION_DECL
, get_identifier (stubname
),
7283 build_function_type_list (void_type_node
, NULL_TREE
));
7284 set_decl_section_name (stubdecl
, secname
);
7285 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7286 RESULT_DECL
, NULL_TREE
, void_type_node
);
7288 /* Output a comment. */
7289 fprintf (asm_out_file
, "\t# Stub function for %s (",
7290 current_function_name ());
7292 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
7294 fprintf (asm_out_file
, "%s%s", separator
,
7295 (f
& 3) == 1 ? "float" : "double");
7298 fprintf (asm_out_file
, ")\n");
7300 /* Start the function definition. */
7301 assemble_start_function (stubdecl
, stubname
);
7302 mips_start_function_definition (stubname
, false);
7304 /* If generating pic2 code, either set up the global pointer or
7306 if (TARGET_ABICALLS_PIC2
)
7308 if (TARGET_ABSOLUTE_ABICALLS
)
7309 fprintf (asm_out_file
, "\t.option\tpic0\n");
7312 output_asm_insn ("%(.cpload\t%^%)", NULL
);
7313 /* Emit an R_MIPS_NONE relocation to tell the linker what the
7314 target function is. Use a local GOT access when loading the
7315 symbol, to cut down on the number of unnecessary GOT entries
7316 for stubs that aren't needed. */
7317 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
7322 /* Load the address of the MIPS16 function into $25. Do this first so
7323 that targets with coprocessor interlocks can use an MFC1 to fill the
7325 output_asm_insn ("la\t%^,%0", &symbol
);
7327 /* Move the arguments from floating-point registers to general registers. */
7328 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
7330 /* Jump to the MIPS16 function. */
7331 output_asm_insn ("jr\t%^", NULL
);
7333 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
7334 fprintf (asm_out_file
, "\t.option\tpic2\n");
7336 mips_end_function_definition (stubname
);
7338 /* If the linker needs to create a dynamic symbol for the target
7339 function, it will associate the symbol with the stub (which,
7340 unlike the target function, follows the proper calling conventions).
7341 It is therefore useful to have a local alias for the target function,
7342 so that it can still be identified as MIPS16 code. As an optimization,
7343 this symbol can also be used for indirect MIPS16 references from
7344 within this file. */
7345 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
7347 switch_to_section (function_section (current_function_decl
));
7350 /* The current function is a MIPS16 function that returns a value in an FPR.
7351 Copy the return value from its soft-float to its hard-float location.
7352 libgcc2 has special non-MIPS16 helper functions for each case. */
7355 mips16_copy_fpr_return_value (void)
7357 rtx fn
, insn
, retval
;
7359 machine_mode return_mode
;
7362 return_type
= DECL_RESULT (current_function_decl
);
7363 return_mode
= DECL_MODE (return_type
);
7365 name
= ACONCAT (("__mips16_ret_",
7366 mips16_call_stub_mode_suffix (return_mode
),
7368 fn
= mips16_stub_function (name
);
7370 /* The function takes arguments in $2 (and possibly $3), so calls
7371 to it cannot be lazily bound. */
7372 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
7374 /* Model the call as something that takes the GPR return value as
7375 argument and returns an "updated" value. */
7376 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
7377 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
7378 const0_rtx
, NULL_RTX
, false);
7379 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
7382 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
7383 RETVAL is the location of the return value, or null if this is
7384 a "call" rather than a "call_value". ARGS_SIZE is the size of the
7385 arguments and FP_CODE is the code built by mips_function_arg;
7386 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
7388 There are three alternatives:
7390 - If a stub was needed, emit the call and return the call insn itself.
7392 - If we can avoid using a stub by redirecting the call, set *FN_PTR
7393 to the new target and return null.
7395 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
7398 A stub is needed for calls to functions that, in normal mode,
7399 receive arguments in FPRs or return values in FPRs. The stub
7400 copies the arguments from their soft-float positions to their
7401 hard-float positions, calls the real function, then copies the
7402 return value from its hard-float position to its soft-float
7405 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
7406 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
7407 automatically redirects the JAL to the stub, otherwise the JAL
7408 continues to call FN directly. */
7411 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
7415 struct mips16_stub
*l
;
7419 /* We don't need to do anything if we aren't in MIPS16 mode, or if
7420 we were invoked with the -msoft-float option. */
7421 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
7424 /* Figure out whether the value might come back in a floating-point
7426 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
7428 /* We don't need to do anything if there were no floating-point
7429 arguments and the value will not be returned in a floating-point
7431 if (fp_code
== 0 && !fp_ret_p
)
7434 /* We don't need to do anything if this is a call to a special
7435 MIPS16 support function. */
7437 if (mips16_stub_function_p (fn
))
7440 /* If we're calling a locally-defined MIPS16 function, we know that
7441 it will return values in both the "soft-float" and "hard-float"
7442 registers. There is no need to use a stub to move the latter
7444 if (fp_code
== 0 && mips16_local_function_p (fn
))
7447 /* This code will only work for o32 and o64 abis. The other ABI's
7448 require more sophisticated support. */
7449 gcc_assert (TARGET_OLDABI
);
7451 /* If we're calling via a function pointer, use one of the magic
7452 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
7453 Each stub expects the function address to arrive in register $2. */
7454 if (GET_CODE (fn
) != SYMBOL_REF
7455 || !call_insn_operand (fn
, VOIDmode
))
7462 /* If this is a locally-defined and locally-binding function,
7463 avoid the stub by calling the local alias directly. */
7464 if (mips16_local_function_p (fn
))
7466 *fn_ptr
= mips16_local_alias (fn
);
7470 /* Create a SYMBOL_REF for the libgcc.a function. */
7472 sprintf (buf
, "__mips16_call_stub_%s_%d",
7473 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
7476 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
7477 stub_fn
= mips16_stub_function (buf
);
7479 /* The function uses $2 as an argument, so calls to it
7480 cannot be lazily bound. */
7481 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
7483 /* Load the target function into $2. */
7484 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
7485 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
7487 /* Emit the call. */
7488 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
7489 args_size
, NULL_RTX
, lazy_p
);
7491 /* Tell GCC that this call does indeed use the value of $2. */
7492 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
7494 /* If we are handling a floating-point return value, we need to
7495 save $18 in the function prologue. Putting a note on the
7496 call will mean that df_regs_ever_live_p ($18) will be true if the
7497 call is not eliminated, and we can check that in the prologue
7500 CALL_INSN_FUNCTION_USAGE (insn
) =
7501 gen_rtx_EXPR_LIST (VOIDmode
,
7502 gen_rtx_CLOBBER (VOIDmode
,
7503 gen_rtx_REG (word_mode
, 18)),
7504 CALL_INSN_FUNCTION_USAGE (insn
));
7509 /* We know the function we are going to call. If we have already
7510 built a stub, we don't need to do anything further. */
7511 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
7512 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
7513 if (strcmp (l
->name
, fnname
) == 0)
7518 const char *separator
;
7519 char *secname
, *stubname
;
7520 tree stubid
, stubdecl
;
7523 /* If the function does not return in FPRs, the special stub
7527 If the function does return in FPRs, the stub section is named
7528 .mips16.call.fp.FNNAME
7530 Build a decl for the stub. */
7531 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
7533 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
7535 stubid
= get_identifier (stubname
);
7536 stubdecl
= build_decl (BUILTINS_LOCATION
,
7537 FUNCTION_DECL
, stubid
,
7538 build_function_type_list (void_type_node
,
7540 set_decl_section_name (stubdecl
, secname
);
7541 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
7542 RESULT_DECL
, NULL_TREE
,
7545 /* Output a comment. */
7546 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
7548 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
7552 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
7554 fprintf (asm_out_file
, "%s%s", separator
,
7555 (f
& 3) == 1 ? "float" : "double");
7558 fprintf (asm_out_file
, ")\n");
7560 /* Start the function definition. */
7561 assemble_start_function (stubdecl
, stubname
);
7562 mips_start_function_definition (stubname
, false);
7566 fprintf (asm_out_file
, "\t.cfi_startproc\n");
7568 /* Create a fake CFA 4 bytes below the stack pointer.
7569 This works around unwinders (like libgcc's) that expect
7570 the CFA for non-signal frames to be unique. */
7571 fprintf (asm_out_file
, "\t.cfi_def_cfa 29,-4\n");
7573 /* "Save" $sp in itself so we don't use the fake CFA.
7574 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
7575 fprintf (asm_out_file
, "\t.cfi_escape 0x16,29,1,0x6d\n");
7577 /* Save the return address in $18. The stub's caller knows
7578 that $18 might be clobbered, even though $18 is usually
7579 a call-saved register.
7581 Do it early on in case the last move to a floating-point
7582 register can be scheduled into the delay slot of the
7583 call we are about to make. */
7584 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
7585 reg_names
[GP_REG_FIRST
+ 18],
7586 reg_names
[RETURN_ADDR_REGNUM
]);
7590 /* Load the address of the MIPS16 function into $25. Do this
7591 first so that targets with coprocessor interlocks can use
7592 an MFC1 to fill the delay slot. */
7593 if (TARGET_EXPLICIT_RELOCS
)
7595 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
7596 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
7599 output_asm_insn ("la\t%^,%0", &fn
);
7602 /* Move the arguments from general registers to floating-point
7604 mips_output_args_xfer (fp_code
, 't');
7608 /* Now call the non-MIPS16 function. */
7609 output_asm_insn (mips_output_jump (&fn
, 0, -1, true), &fn
);
7610 fprintf (asm_out_file
, "\t.cfi_register 31,18\n");
7612 /* Move the result from floating-point registers to
7613 general registers. */
7614 switch (GET_MODE (retval
))
7617 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
7621 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
7622 TARGET_LITTLE_ENDIAN
7625 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
7627 /* On 64-bit targets, complex floats are returned in
7628 a single GPR, such that "sd" on a suitably-aligned
7629 target would store the value correctly. */
7630 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7631 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7632 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7633 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
7634 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
7635 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
7636 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
7637 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
7638 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
7639 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
7640 reg_names
[GP_RETURN
],
7641 reg_names
[GP_RETURN
],
7642 reg_names
[GP_RETURN
+ 1]);
7647 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7651 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
7656 gcc_assert (TARGET_PAIRED_SINGLE_FLOAT
7657 || GET_MODE (retval
) != V2SFmode
);
7658 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
7664 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
7665 fprintf (asm_out_file
, "\t.cfi_endproc\n");
7669 /* Jump to the previously-loaded address. */
7670 output_asm_insn ("jr\t%^", NULL
);
7673 #ifdef ASM_DECLARE_FUNCTION_SIZE
7674 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
7677 mips_end_function_definition (stubname
);
7679 /* Record this stub. */
7680 l
= XNEW (struct mips16_stub
);
7681 l
->name
= xstrdup (fnname
);
7682 l
->fp_ret_p
= fp_ret_p
;
7683 l
->next
= mips16_stubs
;
7687 /* If we expect a floating-point return value, but we've built a
7688 stub which does not expect one, then we're in trouble. We can't
7689 use the existing stub, because it won't handle the floating-point
7690 value. We can't build a new stub, because the linker won't know
7691 which stub to use for the various calls in this object file.
7692 Fortunately, this case is illegal, since it means that a function
7693 was declared in two different ways in a single compilation. */
7694 if (fp_ret_p
&& !l
->fp_ret_p
)
7695 error ("cannot handle inconsistent calls to %qs", fnname
);
7697 if (retval
== NULL_RTX
)
7698 pattern
= gen_call_internal_direct (fn
, args_size
);
7700 pattern
= gen_call_value_internal_direct (retval
, fn
, args_size
);
7701 insn
= mips_emit_call_insn (pattern
, fn
, fn
, false);
7703 /* If we are calling a stub which handles a floating-point return
7704 value, we need to arrange to save $18 in the prologue. We do this
7705 by marking the function call as using the register. The prologue
7706 will later see that it is used, and emit code to save it. */
7708 CALL_INSN_FUNCTION_USAGE (insn
) =
7709 gen_rtx_EXPR_LIST (VOIDmode
,
7710 gen_rtx_CLOBBER (VOIDmode
,
7711 gen_rtx_REG (word_mode
, 18)),
7712 CALL_INSN_FUNCTION_USAGE (insn
));
7717 /* Expand a call of type TYPE. RESULT is where the result will go (null
7718 for "call"s and "sibcall"s), ADDR is the address of the function,
7719 ARGS_SIZE is the size of the arguments and AUX is the value passed
7720 to us by mips_function_arg. LAZY_P is true if this call already
7721 involves a lazily-bound function address (such as when calling
7722 functions through a MIPS16 hard-float stub).
7724 Return the call itself. */
7727 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
7728 rtx args_size
, rtx aux
, bool lazy_p
)
7730 rtx orig_addr
, pattern
;
7734 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
7735 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
7738 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
7743 if (!call_insn_operand (addr
, VOIDmode
))
7745 if (type
== MIPS_CALL_EPILOGUE
)
7746 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
7748 addr
= gen_reg_rtx (Pmode
);
7749 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
7754 rtx (*fn
) (rtx
, rtx
);
7756 if (type
== MIPS_CALL_SIBCALL
)
7757 fn
= gen_sibcall_internal
;
7759 fn
= gen_call_internal
;
7761 pattern
= fn (addr
, args_size
);
7763 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
7765 /* Handle return values created by mips_return_fpr_pair. */
7766 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
7769 if (type
== MIPS_CALL_SIBCALL
)
7770 fn
= gen_sibcall_value_multiple_internal
;
7772 fn
= gen_call_value_multiple_internal
;
7774 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
7775 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
7776 pattern
= fn (reg1
, addr
, args_size
, reg2
);
7780 rtx (*fn
) (rtx
, rtx
, rtx
);
7782 if (type
== MIPS_CALL_SIBCALL
)
7783 fn
= gen_sibcall_value_internal
;
7785 fn
= gen_call_value_internal
;
7787 /* Handle return values created by mips_return_fpr_single. */
7788 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
7789 result
= XEXP (XVECEXP (result
, 0, 0), 0);
7790 pattern
= fn (result
, addr
, args_size
);
7793 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
7796 /* Split call instruction INSN into a $gp-clobbering call and
7797 (where necessary) an instruction to restore $gp from its save slot.
7798 CALL_PATTERN is the pattern of the new call. */
7801 mips_split_call (rtx insn
, rtx call_pattern
)
7803 emit_call_insn (call_pattern
);
7804 if (!find_reg_note (insn
, REG_NORETURN
, 0))
7805 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
,
7806 POST_CALL_TMP_REG
));
7809 /* Return true if a call to DECL may need to use JALX. */
7812 mips_call_may_need_jalx_p (tree decl
)
7814 /* If the current translation unit would use a different mode for DECL,
7815 assume that the call needs JALX. */
7816 if (mips_get_compress_mode (decl
) != TARGET_COMPRESSION
)
7819 /* mips_get_compress_mode is always accurate for locally-binding
7820 functions in the current translation unit. */
7821 if (!DECL_EXTERNAL (decl
) && targetm
.binds_local_p (decl
))
7824 /* When -minterlink-compressed is in effect, assume that functions
7825 could use a different encoding mode unless an attribute explicitly
7826 tells us otherwise. */
7827 if (TARGET_INTERLINK_COMPRESSED
)
7829 if (!TARGET_COMPRESSION
7830 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl
)) ==0)
7832 if (TARGET_COMPRESSION
7833 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl
)) == 0)
7840 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7843 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
7845 if (!TARGET_SIBCALLS
)
7848 /* Interrupt handlers need special epilogue code and therefore can't
7850 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
7853 /* Direct Js are only possible to functions that use the same ISA encoding.
7854 There is no JX counterpoart of JALX. */
7856 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
)
7857 && mips_call_may_need_jalx_p (decl
))
7860 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7861 require $gp to be valid on entry, so sibcalls can only use stubs
7862 if $gp is call-clobbered. */
7864 && TARGET_CALL_SAVED_GP
7865 && !TARGET_ABICALLS_PIC0
7866 && !targetm
.binds_local_p (decl
))
7873 /* Implement TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7876 mips_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size
,
7878 enum by_pieces_operation op
,
7881 if (op
== STORE_BY_PIECES
)
7882 return mips_store_by_pieces_p (size
, align
);
7883 if (op
== MOVE_BY_PIECES
&& HAVE_movmemsi
)
7885 /* movmemsi is meant to generate code that is at least as good as
7886 move_by_pieces. However, movmemsi effectively uses a by-pieces
7887 implementation both for moves smaller than a word and for
7888 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7889 bytes. We should allow the tree-level optimisers to do such
7890 moves by pieces, as it often exposes other optimization
7891 opportunities. We might as well continue to use movmemsi at
7892 the rtl level though, as it produces better code when
7893 scheduling is disabled (such as at -O). */
7894 if (currently_expanding_to_rtl
)
7896 if (align
< BITS_PER_WORD
)
7897 return size
< UNITS_PER_WORD
;
7898 return size
<= MIPS_MAX_MOVE_BYTES_STRAIGHT
;
7901 return default_use_by_pieces_infrastructure_p (size
, align
, op
, speed_p
);
7904 /* Implement a handler for STORE_BY_PIECES operations
7905 for TARGET_USE_MOVE_BY_PIECES_INFRASTRUCTURE_P. */
7908 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size
, unsigned int align
)
7910 /* Storing by pieces involves moving constants into registers
7911 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7912 We need to decide whether it is cheaper to load the address of
7913 constant data into a register and use a block move instead. */
7915 /* If the data is only byte aligned, then:
7917 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7918 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7921 (a2) A block move of 4 bytes from aligned source data can use an
7922 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7923 4 SBs that we would generate when storing by pieces. */
7924 if (align
<= BITS_PER_UNIT
)
7927 /* If the data is 2-byte aligned, then:
7929 (b1) A block move of less than 4 bytes would use a combination of LBs,
7930 LHs, SBs and SHs. We get better code by using single-instruction
7931 LIs, SBs and SHs instead.
7933 (b2) A block move of 4 bytes from aligned source data would again use
7934 an LW/SWL/SWR sequence. In most cases, loading the address of
7935 the source data would require at least one extra instruction.
7936 It is often more efficient to use 2 single-instruction LIs and
7939 (b3) A block move of up to 3 additional bytes would be like (b1).
7941 (b4) A block move of 8 bytes from aligned source data can use two
7942 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7943 sequences are better than the 4 LIs and 4 SHs that we'd generate
7944 when storing by pieces.
7946 The reasoning for higher alignments is similar:
7948 (c1) A block move of less than 4 bytes would be the same as (b1).
7950 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7951 loading the address of the source data would typically require
7952 at least one extra instruction. It is generally better to use
7955 (c3) A block move of up to 3 additional bytes would be like (b1).
7957 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7958 LD/SD sequence, and in these cases we've traditionally preferred
7959 the memory copy over the more bulky constant moves. */
7963 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7964 Assume that the areas do not overlap. */
7967 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
7969 HOST_WIDE_INT offset
, delta
;
7970 unsigned HOST_WIDE_INT bits
;
7975 /* Work out how many bits to move at a time. If both operands have
7976 half-word alignment, it is usually better to move in half words.
7977 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7978 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7979 Otherwise move word-sized chunks.
7981 For ISA_HAS_LWL_LWR we rely on the lwl/lwr & swl/swr load. Otherwise
7982 picking the minimum of alignment or BITS_PER_WORD gets us the
7983 desired size for bits. */
7985 if (!ISA_HAS_LWL_LWR
)
7986 bits
= MIN (BITS_PER_WORD
, MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)));
7989 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
7990 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
7991 bits
= BITS_PER_WORD
/ 2;
7993 bits
= BITS_PER_WORD
;
7996 mode
= int_mode_for_size (bits
, 0).require ();
7997 delta
= bits
/ BITS_PER_UNIT
;
7999 /* Allocate a buffer for the temporary registers. */
8000 regs
= XALLOCAVEC (rtx
, length
/ delta
);
8002 /* Load as many BITS-sized chunks as possible. Use a normal load if
8003 the source has enough alignment, otherwise use left/right pairs. */
8004 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
8006 regs
[i
] = gen_reg_rtx (mode
);
8007 if (MEM_ALIGN (src
) >= bits
)
8008 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
8011 rtx part
= adjust_address (src
, BLKmode
, offset
);
8012 set_mem_size (part
, delta
);
8013 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0, 0))
8018 /* Copy the chunks to the destination. */
8019 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
8020 if (MEM_ALIGN (dest
) >= bits
)
8021 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
8024 rtx part
= adjust_address (dest
, BLKmode
, offset
);
8025 set_mem_size (part
, delta
);
8026 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
8030 /* Mop up any left-over bytes. */
8031 if (offset
< length
)
8033 src
= adjust_address (src
, BLKmode
, offset
);
8034 dest
= adjust_address (dest
, BLKmode
, offset
);
8035 move_by_pieces (dest
, src
, length
- offset
,
8036 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
8040 /* Helper function for doing a loop-based block operation on memory
8041 reference MEM. Each iteration of the loop will operate on LENGTH
8044 Create a new base register for use within the loop and point it to
8045 the start of MEM. Create a new memory reference that uses this
8046 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
8049 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
8050 rtx
*loop_reg
, rtx
*loop_mem
)
8052 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
8054 /* Although the new mem does not refer to a known location,
8055 it does keep up to LENGTH bytes of alignment. */
8056 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
8057 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
8060 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
8061 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
8062 the memory regions do not overlap. */
8065 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
8066 HOST_WIDE_INT bytes_per_iter
)
8068 rtx_code_label
*label
;
8069 rtx src_reg
, dest_reg
, final_src
, test
;
8070 HOST_WIDE_INT leftover
;
8072 leftover
= length
% bytes_per_iter
;
8075 /* Create registers and memory references for use within the loop. */
8076 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
8077 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
8079 /* Calculate the value that SRC_REG should have after the last iteration
8081 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
8084 /* Emit the start of the loop. */
8085 label
= gen_label_rtx ();
8088 /* Emit the loop body. */
8089 mips_block_move_straight (dest
, src
, bytes_per_iter
);
8091 /* Move on to the next block. */
8092 mips_emit_move (src_reg
, plus_constant (Pmode
, src_reg
, bytes_per_iter
));
8093 mips_emit_move (dest_reg
, plus_constant (Pmode
, dest_reg
, bytes_per_iter
));
8095 /* Emit the loop condition. */
8096 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
8097 if (Pmode
== DImode
)
8098 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
8100 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
8102 /* Mop up any left-over bytes. */
8104 mips_block_move_straight (dest
, src
, leftover
);
8106 /* Temporary fix for PR79150. */
8107 emit_insn (gen_nop ());
8110 /* Expand a movmemsi instruction, which copies LENGTH bytes from
8111 memory reference SRC to memory reference DEST. */
8114 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
8116 if (!ISA_HAS_LWL_LWR
8117 && (MEM_ALIGN (src
) < MIPS_MIN_MOVE_MEM_ALIGN
8118 || MEM_ALIGN (dest
) < MIPS_MIN_MOVE_MEM_ALIGN
))
8121 if (CONST_INT_P (length
))
8123 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
8125 mips_block_move_straight (dest
, src
, INTVAL (length
));
8130 mips_block_move_loop (dest
, src
, INTVAL (length
),
8131 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
8138 /* Expand a loop of synci insns for the address range [BEGIN, END). */
8141 mips_expand_synci_loop (rtx begin
, rtx end
)
8143 rtx inc
, cmp_result
, mask
, length
;
8144 rtx_code_label
*label
, *end_label
;
8146 /* Create end_label. */
8147 end_label
= gen_label_rtx ();
8149 /* Check if begin equals end. */
8150 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
8151 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
8153 /* Load INC with the cache line size (rdhwr INC,$1). */
8154 inc
= gen_reg_rtx (Pmode
);
8155 emit_insn (PMODE_INSN (gen_rdhwr_synci_step
, (inc
)));
8157 /* Check if inc is 0. */
8158 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
8159 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
8161 /* Calculate mask. */
8162 mask
= mips_force_unary (Pmode
, NEG
, inc
);
8164 /* Mask out begin by mask. */
8165 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
8167 /* Calculate length. */
8168 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
8170 /* Loop back to here. */
8171 label
= gen_label_rtx ();
8174 emit_insn (gen_synci (begin
));
8176 /* Update length. */
8177 mips_emit_binary (MINUS
, length
, length
, inc
);
8180 mips_emit_binary (PLUS
, begin
, begin
, inc
);
8182 /* Check if length is greater than 0. */
8183 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
8184 emit_jump_insn (gen_condjump (cmp_result
, label
));
8186 emit_label (end_label
);
8189 /* Expand a QI or HI mode atomic memory operation.
8191 GENERATOR contains a pointer to the gen_* function that generates
8192 the SI mode underlying atomic operation using masks that we
8195 RESULT is the return register for the operation. Its value is NULL
8198 MEM is the location of the atomic access.
8200 OLDVAL is the first operand for the operation.
8202 NEWVAL is the optional second operand for the operation. Its value
8203 is NULL if unused. */
8206 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
8207 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
8209 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
8210 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
8214 mode
= GET_MODE (mem
);
8216 /* Compute the address of the containing SImode value. */
8217 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
8218 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
8219 force_reg (Pmode
, GEN_INT (-4)));
8221 /* Create a memory reference for it. */
8222 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
8223 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
8224 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
8226 /* Work out the byte offset of the QImode or HImode value,
8227 counting from the least significant byte. */
8228 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
8229 if (TARGET_BIG_ENDIAN
)
8230 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
8232 /* Multiply by eight to convert the shift value from bytes to bits. */
8233 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
8235 /* Make the final shift an SImode value, so that it can be used in
8236 SImode operations. */
8237 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
8239 /* Set MASK to an inclusive mask of the QImode or HImode value. */
8240 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
8241 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
8242 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
8244 /* Compute the equivalent exclusive mask. */
8245 inverted_mask
= gen_reg_rtx (SImode
);
8246 emit_insn (gen_rtx_SET (inverted_mask
, gen_rtx_NOT (SImode
, mask
)));
8248 /* Shift the old value into place. */
8249 if (oldval
!= const0_rtx
)
8251 oldval
= convert_modes (SImode
, mode
, oldval
, true);
8252 oldval
= force_reg (SImode
, oldval
);
8253 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
8256 /* Do the same for the new value. */
8257 if (newval
&& newval
!= const0_rtx
)
8259 newval
= convert_modes (SImode
, mode
, newval
, true);
8260 newval
= force_reg (SImode
, newval
);
8261 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
8264 /* Do the SImode atomic access. */
8266 res
= gen_reg_rtx (SImode
);
8268 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
8270 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
8272 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
8278 /* Shift and convert the result. */
8279 mips_emit_binary (AND
, res
, res
, mask
);
8280 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
8281 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
8285 /* Return true if it is possible to use left/right accesses for a
8286 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
8287 When returning true, update *LEFT and *RIGHT as follows:
8289 *LEFT is a QImode reference to the first byte if big endian or
8290 the last byte if little endian. This address can be used in the
8291 left-side instructions (LWL, SWL, LDL, SDL).
8293 *RIGHT is a QImode reference to the opposite end of the field and
8294 can be used in the patterning right-side instruction. */
8297 mips_get_unaligned_mem (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
8298 rtx
*left
, rtx
*right
)
8302 /* Check that the size is valid. */
8303 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
8306 /* We can only access byte-aligned values. Since we are always passed
8307 a reference to the first byte of the field, it is not necessary to
8308 do anything with BITPOS after this check. */
8309 if (bitpos
% BITS_PER_UNIT
!= 0)
8312 /* Reject aligned bitfields: we want to use a normal load or store
8313 instead of a left/right pair. */
8314 if (MEM_ALIGN (op
) >= width
)
8317 /* Get references to both ends of the field. */
8318 first
= adjust_address (op
, QImode
, 0);
8319 last
= adjust_address (op
, QImode
, width
/ BITS_PER_UNIT
- 1);
8321 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
8322 correspond to the MSB and RIGHT to the LSB. */
8323 if (TARGET_BIG_ENDIAN
)
8324 *left
= first
, *right
= last
;
8326 *left
= last
, *right
= first
;
8331 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
8332 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
8333 the operation is the equivalent of:
8335 (set DEST (*_extract SRC WIDTH BITPOS))
8337 Return true on success. */
8340 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
8341 HOST_WIDE_INT bitpos
, bool unsigned_p
)
8343 rtx left
, right
, temp
;
8344 rtx dest1
= NULL_RTX
;
8346 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
8347 be a DImode, create a new temp and emit a zero extend at the end. */
8348 if (GET_MODE (dest
) == DImode
8350 && GET_MODE_BITSIZE (SImode
) == width
)
8353 dest
= gen_reg_rtx (SImode
);
8356 if (!mips_get_unaligned_mem (src
, width
, bitpos
, &left
, &right
))
8359 temp
= gen_reg_rtx (GET_MODE (dest
));
8360 if (GET_MODE (dest
) == DImode
)
8362 emit_insn (gen_mov_ldl (temp
, src
, left
));
8363 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
8367 emit_insn (gen_mov_lwl (temp
, src
, left
));
8368 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
8371 /* If we were loading 32bits and the original register was DI then
8372 sign/zero extend into the orignal dest. */
8376 emit_insn (gen_zero_extendsidi2 (dest1
, dest
));
8378 emit_insn (gen_extendsidi2 (dest1
, dest
));
8383 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
8384 BITPOS and SRC are the operands passed to the expander; the operation
8385 is the equivalent of:
8387 (set (zero_extract DEST WIDTH BITPOS) SRC)
8389 Return true on success. */
8392 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
8393 HOST_WIDE_INT bitpos
)
8398 if (!mips_get_unaligned_mem (dest
, width
, bitpos
, &left
, &right
))
8401 mode
= int_mode_for_size (width
, 0).require ();
8402 src
= gen_lowpart (mode
, src
);
8405 emit_insn (gen_mov_sdl (dest
, src
, left
));
8406 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
8410 emit_insn (gen_mov_swl (dest
, src
, left
));
8411 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
8416 /* Return true if X is a MEM with the same size as MODE. */
8419 mips_mem_fits_mode_p (machine_mode mode
, rtx x
)
8422 && MEM_SIZE_KNOWN_P (x
)
8423 && MEM_SIZE (x
) == GET_MODE_SIZE (mode
));
8426 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
8427 source of an "ext" instruction or the destination of an "ins"
8428 instruction. OP must be a register operand and the following
8429 conditions must hold:
8431 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
8432 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
8433 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
8435 Also reject lengths equal to a word as they are better handled
8436 by the move patterns. */
8439 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
8441 if (!ISA_HAS_EXT_INS
8442 || !register_operand (op
, VOIDmode
)
8443 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
8446 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
8449 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
8455 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
8456 operation if MAXLEN is the maxium length of consecutive bits that
8457 can make up MASK. MODE is the mode of the operation. See
8458 mask_low_and_shift_len for the actual definition. */
8461 mask_low_and_shift_p (machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
8463 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
8466 /* Return true iff OP1 and OP2 are valid operands together for the
8467 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
8468 see the table in the comment before the pattern. */
8471 and_operands_ok (machine_mode mode
, rtx op1
, rtx op2
)
8474 if (memory_operand (op1
, mode
))
8476 if (TARGET_MIPS16
) {
8477 struct mips_address_info addr
;
8478 if (!mips_classify_address (&addr
, op1
, mode
, false))
8481 return and_load_operand (op2
, mode
);
8484 return and_reg_operand (op2
, mode
);
8487 /* The canonical form of a mask-low-and-shift-left operation is
8488 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
8489 cleared. Thus we need to shift MASK to the right before checking if it
8490 is a valid mask value. MODE is the mode of the operation. If true
8491 return the length of the mask, otherwise return -1. */
8494 mask_low_and_shift_len (machine_mode mode
, rtx mask
, rtx shift
)
8496 HOST_WIDE_INT shval
;
8498 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
8499 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
8502 /* Return true if -msplit-addresses is selected and should be honored.
8504 -msplit-addresses is a half-way house between explicit relocations
8505 and the traditional assembler macros. It can split absolute 32-bit
8506 symbolic constants into a high/lo_sum pair but uses macros for other
8509 Like explicit relocation support for REL targets, it relies
8510 on GNU extensions in the assembler and the linker.
8512 Although this code should work for -O0, it has traditionally
8513 been treated as an optimization. */
8516 mips_split_addresses_p (void)
8518 return (TARGET_SPLIT_ADDRESSES
8522 && !ABI_HAS_64BIT_SYMBOLS
);
8525 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
8528 mips_init_relocs (void)
8530 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
8531 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
8532 memset (mips_use_pcrel_pool_p
, '\0', sizeof (mips_use_pcrel_pool_p
));
8533 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
8534 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
8536 if (TARGET_MIPS16_PCREL_LOADS
)
8537 mips_use_pcrel_pool_p
[SYMBOL_ABSOLUTE
] = true;
8540 if (ABI_HAS_64BIT_SYMBOLS
)
8542 if (TARGET_EXPLICIT_RELOCS
)
8544 mips_split_p
[SYMBOL_64_HIGH
] = true;
8545 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
8546 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
8548 mips_split_p
[SYMBOL_64_MID
] = true;
8549 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
8550 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
8552 mips_split_p
[SYMBOL_64_LOW
] = true;
8553 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
8554 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
8556 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8557 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8562 if (TARGET_EXPLICIT_RELOCS
8563 || mips_split_addresses_p ()
8566 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
8567 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
8568 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
8575 /* The high part is provided by a pseudo copy of $gp. */
8576 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
8577 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
8579 else if (TARGET_EXPLICIT_RELOCS
)
8580 /* Small data constants are kept whole until after reload,
8581 then lowered by mips_rewrite_small_data. */
8582 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
8584 if (TARGET_EXPLICIT_RELOCS
)
8586 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8589 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
8590 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
8594 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
8595 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
8598 /* Expose the use of $28 as soon as possible. */
8599 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
8603 /* The HIGH and LO_SUM are matched by special .md patterns. */
8604 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8606 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
8607 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
8608 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
8610 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
8611 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
8612 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
8617 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
8619 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
8620 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
8622 /* Expose the use of $28 as soon as possible. */
8623 mips_split_p
[SYMBOL_GOT_DISP
] = true;
8629 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
8630 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
8631 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
8634 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
8635 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
8637 if (TARGET_MIPS16_PCREL_LOADS
)
8639 mips_use_pcrel_pool_p
[SYMBOL_DTPREL
] = true;
8640 mips_use_pcrel_pool_p
[SYMBOL_TPREL
] = true;
8644 mips_split_p
[SYMBOL_DTPREL
] = true;
8645 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
8646 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
8648 mips_split_p
[SYMBOL_TPREL
] = true;
8649 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
8650 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
8653 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
8654 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
8657 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
8658 in context CONTEXT. RELOCS is the array of relocations to use. */
8661 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
8662 const char **relocs
)
8664 enum mips_symbol_type symbol_type
;
8667 symbol_type
= mips_classify_symbolic_expression (op
, context
);
8668 gcc_assert (relocs
[symbol_type
]);
8670 fputs (relocs
[symbol_type
], file
);
8671 output_addr_const (file
, mips_strip_unspec_address (op
));
8672 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
8677 /* Start a new block with the given asm switch enabled. If we need
8678 to print a directive, emit PREFIX before it and SUFFIX after it. */
8681 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8682 const char *prefix
, const char *suffix
)
8684 if (asm_switch
->nesting_level
== 0)
8685 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
8686 asm_switch
->nesting_level
++;
8689 /* Likewise, but end a block. */
8692 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
8693 const char *prefix
, const char *suffix
)
8695 gcc_assert (asm_switch
->nesting_level
);
8696 asm_switch
->nesting_level
--;
8697 if (asm_switch
->nesting_level
== 0)
8698 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
8701 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
8702 that either print a complete line or print nothing. */
8705 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
8707 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
8711 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
8713 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
8716 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
8717 The punctuation characters are:
8719 '(' Start a nested ".set noreorder" block.
8720 ')' End a nested ".set noreorder" block.
8721 '[' Start a nested ".set noat" block.
8722 ']' End a nested ".set noat" block.
8723 '<' Start a nested ".set nomacro" block.
8724 '>' End a nested ".set nomacro" block.
8725 '*' Behave like %(%< if generating a delayed-branch sequence.
8726 '#' Print a nop if in a ".set noreorder" block.
8727 '/' Like '#', but do nothing within a delayed-branch sequence.
8728 '?' Print "l" if mips_branch_likely is true
8729 '~' Print a nop if mips_branch_likely is true
8730 '.' Print the name of the register with a hard-wired zero (zero or $0).
8731 '@' Print the name of the assembler temporary register (at or $1).
8732 '^' Print the name of the pic call-through register (t9 or $25).
8733 '+' Print the name of the gp register (usually gp or $28).
8734 '$' Print the name of the stack pointer register (sp or $29).
8735 ':' Print "c" to use the compact version if the delay slot is a nop.
8736 '!' Print "s" to use the short version if the delay slot contains a
8739 See also mips_init_print_operand_punct. */
8742 mips_print_operand_punctuation (FILE *file
, int ch
)
8747 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
8751 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
8755 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
8759 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
8763 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
8767 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
8771 if (final_sequence
!= 0)
8773 mips_print_operand_punctuation (file
, '(');
8774 mips_print_operand_punctuation (file
, '<');
8779 if (mips_noreorder
.nesting_level
> 0)
8780 fputs ("\n\tnop", file
);
8784 /* Print an extra newline so that the delayed insn is separated
8785 from the following ones. This looks neater and is consistent
8786 with non-nop delayed sequences. */
8787 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
8788 fputs ("\n\tnop\n", file
);
8792 if (mips_branch_likely
)
8797 if (mips_branch_likely
)
8798 fputs ("\n\tnop", file
);
8802 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
8806 fputs (reg_names
[AT_REGNUM
], file
);
8810 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
8814 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
8818 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
8822 /* When final_sequence is 0, the delay slot will be a nop. We can
8823 use the compact version where available. The %: formatter will
8824 only be present if a compact form of the branch is available. */
8825 if (final_sequence
== 0)
8830 /* If the delay slot instruction is short, then use the
8832 if (TARGET_MICROMIPS
&& !TARGET_INTERLINK_COMPRESSED
&& mips_isa_rev
<= 5
8833 && (final_sequence
== 0
8834 || get_attr_length (final_sequence
->insn (1)) == 2))
8844 /* Initialize mips_print_operand_punct. */
8847 mips_init_print_operand_punct (void)
8851 for (p
= "()[]<>*#/?~.@^+$:!"; *p
; p
++)
8852 mips_print_operand_punct
[(unsigned char) *p
] = true;
8855 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8856 associated with condition CODE. Print the condition part of the
8860 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8874 /* Conveniently, the MIPS names for these conditions are the same
8875 as their RTL equivalents. */
8876 fputs (GET_RTX_NAME (code
), file
);
8880 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8885 /* Likewise floating-point branches. */
8888 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
8894 fputs ("c1eqz", file
);
8896 fputs ("c1f", file
);
8901 fputs ("c1nez", file
);
8903 fputs ("c1t", file
);
8907 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
8912 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8915 mips_print_operand_punct_valid_p (unsigned char code
)
8917 return mips_print_operand_punct
[code
];
8920 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8922 'E' Print CONST_INT OP element 0 of a replicated CONST_VECTOR in decimal.
8923 'X' Print CONST_INT OP in hexadecimal format.
8924 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8925 'd' Print CONST_INT OP in decimal.
8926 'B' Print CONST_INT OP element 0 of a replicated CONST_VECTOR
8927 as an unsigned byte [0..255].
8928 'm' Print one less than CONST_INT OP in decimal.
8929 'y' Print exact log2 of CONST_INT OP in decimal.
8930 'h' Print the high-part relocation associated with OP, after stripping
8932 'R' Print the low-part relocation associated with OP.
8933 'C' Print the integer branch condition for comparison OP.
8934 'N' Print the inverse of the integer branch condition for comparison OP.
8935 'F' Print the FPU branch condition for comparison OP.
8936 'W' Print the inverse of the FPU branch condition for comparison OP.
8937 'w' Print a MSA register.
8938 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8939 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8940 't' Like 'T', but with the EQ/NE cases reversed
8941 'Y' Print mips_fp_conditions[INTVAL (OP)]
8942 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8943 'q' Print a DSP accumulator register.
8944 'D' Print the second part of a double-word register or memory operand.
8945 'L' Print the low-order register in a double-word register operand.
8946 'M' Print high-order register in a double-word register operand.
8947 'z' Print $0 if OP is zero, otherwise print OP normally.
8948 'b' Print the address of a memory operand, without offset.
8949 'v' Print the insn size suffix b, h, w or d for vector modes V16QI, V8HI,
8950 V4SI, V2SI, and w, d for vector modes V4SF, V2DF respectively.
8951 'V' Print exact log2 of CONST_INT OP element 0 of a replicated
8952 CONST_VECTOR in decimal. */
8955 mips_print_operand (FILE *file
, rtx op
, int letter
)
8959 if (mips_print_operand_punct_valid_p (letter
))
8961 mips_print_operand_punctuation (file
, letter
);
8966 code
= GET_CODE (op
);
8971 if (GET_CODE (op
) == CONST_VECTOR
)
8973 gcc_assert (mips_const_vector_same_val_p (op
, GET_MODE (op
)));
8974 op
= CONST_VECTOR_ELT (op
, 0);
8975 gcc_assert (CONST_INT_P (op
));
8976 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
8979 output_operand_lossage ("invalid use of '%%%c'", letter
);
8983 if (CONST_INT_P (op
))
8984 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
8986 output_operand_lossage ("invalid use of '%%%c'", letter
);
8990 if (CONST_INT_P (op
))
8991 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
8993 output_operand_lossage ("invalid use of '%%%c'", letter
);
8997 if (CONST_INT_P (op
))
8998 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
9000 output_operand_lossage ("invalid use of '%%%c'", letter
);
9004 if (GET_CODE (op
) == CONST_VECTOR
)
9006 gcc_assert (mips_const_vector_same_val_p (op
, GET_MODE (op
)));
9007 op
= CONST_VECTOR_ELT (op
, 0);
9008 gcc_assert (CONST_INT_P (op
));
9009 unsigned HOST_WIDE_INT val8
= UINTVAL (op
) & GET_MODE_MASK (QImode
);
9010 fprintf (file
, HOST_WIDE_INT_PRINT_UNSIGNED
, val8
);
9013 output_operand_lossage ("invalid use of '%%%c'", letter
);
9017 if (CONST_INT_P (op
))
9018 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
9020 output_operand_lossage ("invalid use of '%%%c'", letter
);
9024 if (CONST_INT_P (op
))
9026 int val
= exact_log2 (INTVAL (op
));
9028 fprintf (file
, "%d", val
);
9030 output_operand_lossage ("invalid use of '%%%c'", letter
);
9033 output_operand_lossage ("invalid use of '%%%c'", letter
);
9037 if (GET_CODE (op
) == CONST_VECTOR
)
9039 machine_mode mode
= GET_MODE_INNER (GET_MODE (op
));
9040 unsigned HOST_WIDE_INT val
= UINTVAL (CONST_VECTOR_ELT (op
, 0));
9041 int vlog2
= exact_log2 (val
& GET_MODE_MASK (mode
));
9043 fprintf (file
, "%d", vlog2
);
9045 output_operand_lossage ("invalid use of '%%%c'", letter
);
9048 output_operand_lossage ("invalid use of '%%%c'", letter
);
9054 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
9058 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
9062 mips_print_int_branch_condition (file
, code
, letter
);
9066 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
9070 mips_print_float_branch_condition (file
, code
, letter
);
9074 mips_print_float_branch_condition (file
, reverse_condition (code
),
9081 int truth
= (code
== NE
) == (letter
== 'T');
9082 fputc ("zfnt"[truth
* 2 + ST_REG_P (REGNO (XEXP (op
, 0)))], file
);
9087 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
9088 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
9090 output_operand_lossage ("'%%%c' is not a valid operand prefix",
9095 if (ISA_HAS_8CC
|| ISA_HAS_CCF
)
9097 mips_print_operand (file
, op
, 0);
9103 if (code
== REG
&& MD_REG_P (REGNO (op
)))
9104 fprintf (file
, "$ac0");
9105 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
9106 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
9108 output_operand_lossage ("invalid use of '%%%c'", letter
);
9112 if (code
== REG
&& MSA_REG_P (REGNO (op
)))
9113 fprintf (file
, "$w%s", ®_names
[REGNO (op
)][2]);
9115 output_operand_lossage ("invalid use of '%%%c'", letter
);
9119 switch (GET_MODE (op
))
9122 fprintf (file
, "b");
9125 fprintf (file
, "h");
9129 fprintf (file
, "w");
9133 fprintf (file
, "d");
9136 output_operand_lossage ("invalid use of '%%%c'", letter
);
9145 unsigned int regno
= REGNO (op
);
9146 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
9147 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
9150 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
9151 output_operand_lossage ("invalid use of '%%%c'", letter
);
9152 /* We need to print $0 .. $31 for COP0 registers. */
9153 if (COP0_REG_P (regno
))
9154 fprintf (file
, "$%s", ®_names
[regno
][4]);
9156 fprintf (file
, "%s", reg_names
[regno
]);
9162 output_address (GET_MODE (op
), plus_constant (Pmode
,
9164 else if (letter
== 'b')
9166 gcc_assert (REG_P (XEXP (op
, 0)));
9167 mips_print_operand (file
, XEXP (op
, 0), 0);
9169 else if (letter
&& letter
!= 'z')
9170 output_operand_lossage ("invalid use of '%%%c'", letter
);
9172 output_address (GET_MODE (op
), XEXP (op
, 0));
9176 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
9177 fputs (reg_names
[GP_REG_FIRST
], file
);
9178 else if (letter
&& letter
!= 'z')
9179 output_operand_lossage ("invalid use of '%%%c'", letter
);
9180 else if (CONST_GP_P (op
))
9181 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
9183 output_addr_const (file
, mips_strip_unspec_address (op
));
9189 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9192 mips_print_operand_address (FILE *file
, machine_mode
/*mode*/, rtx x
)
9194 struct mips_address_info addr
;
9196 if (mips_classify_address (&addr
, x
, word_mode
, true))
9200 mips_print_operand (file
, addr
.offset
, 0);
9201 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
9204 case ADDRESS_LO_SUM
:
9205 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
9207 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
9210 case ADDRESS_CONST_INT
:
9211 output_addr_const (file
, x
);
9212 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
9215 case ADDRESS_SYMBOLIC
:
9216 output_addr_const (file
, mips_strip_unspec_address (x
));
9222 /* Implement TARGET_ENCODE_SECTION_INFO. */
9225 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
9227 default_encode_section_info (decl
, rtl
, first
);
9229 if (TREE_CODE (decl
) == FUNCTION_DECL
)
9231 rtx symbol
= XEXP (rtl
, 0);
9232 tree type
= TREE_TYPE (decl
);
9234 /* Encode whether the symbol is short or long. */
9235 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
9236 || mips_far_type_p (type
))
9237 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
9241 /* Implement TARGET_SELECT_RTX_SECTION. */
9244 mips_select_rtx_section (machine_mode mode
, rtx x
,
9245 unsigned HOST_WIDE_INT align
)
9247 /* ??? Consider using mergeable small data sections. */
9248 if (mips_rtx_constant_in_small_data_p (mode
))
9249 return get_named_section (NULL
, ".sdata", 0);
9251 return default_elf_select_rtx_section (mode
, x
, align
);
9254 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
9256 The complication here is that, with the combination TARGET_ABICALLS
9257 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
9258 absolute addresses, and should therefore not be included in the
9259 read-only part of a DSO. Handle such cases by selecting a normal
9260 data section instead of a read-only one. The logic apes that in
9261 default_function_rodata_section. */
9264 mips_function_rodata_section (tree decl
)
9266 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
9267 return default_function_rodata_section (decl
);
9269 if (decl
&& DECL_SECTION_NAME (decl
))
9271 const char *name
= DECL_SECTION_NAME (decl
);
9272 if (DECL_COMDAT_GROUP (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
9274 char *rname
= ASTRDUP (name
);
9276 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
9278 else if (flag_function_sections
9279 && flag_data_sections
9280 && strncmp (name
, ".text.", 6) == 0)
9282 char *rname
= ASTRDUP (name
);
9283 memcpy (rname
+ 1, "data", 4);
9284 return get_section (rname
, SECTION_WRITE
, decl
);
9287 return data_section
;
9290 /* Implement TARGET_IN_SMALL_DATA_P. */
9293 mips_in_small_data_p (const_tree decl
)
9295 unsigned HOST_WIDE_INT size
;
9297 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
9300 /* We don't yet generate small-data references for -mabicalls
9301 or VxWorks RTP code. See the related -G handling in
9302 mips_option_override. */
9303 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
9306 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
9310 /* Reject anything that isn't in a known small-data section. */
9311 name
= DECL_SECTION_NAME (decl
);
9312 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
9315 /* If a symbol is defined externally, the assembler will use the
9316 usual -G rules when deciding how to implement macros. */
9317 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
9320 else if (TARGET_EMBEDDED_DATA
)
9322 /* Don't put constants into the small data section: we want them
9323 to be in ROM rather than RAM. */
9324 if (TREE_CODE (decl
) != VAR_DECL
)
9327 if (TREE_READONLY (decl
)
9328 && !TREE_SIDE_EFFECTS (decl
)
9329 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
9333 /* Enforce -mlocal-sdata. */
9334 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
9337 /* Enforce -mextern-sdata. */
9338 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
9340 if (DECL_EXTERNAL (decl
))
9342 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
9346 /* We have traditionally not treated zero-sized objects as small data,
9347 so this is now effectively part of the ABI. */
9348 size
= int_size_in_bytes (TREE_TYPE (decl
));
9349 return size
> 0 && size
<= mips_small_data_threshold
;
9352 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
9353 anchors for small data: the GP register acts as an anchor in that
9354 case. We also don't want to use them for PC-relative accesses,
9355 where the PC acts as an anchor. */
9358 mips_use_anchors_for_symbol_p (const_rtx symbol
)
9360 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
9362 case SYMBOL_PC_RELATIVE
:
9363 case SYMBOL_GP_RELATIVE
:
9367 return default_use_anchors_for_symbol_p (symbol
);
9371 /* The MIPS debug format wants all automatic variables and arguments
9372 to be in terms of the virtual frame pointer (stack pointer before
9373 any adjustment in the function), while the MIPS 3.0 linker wants
9374 the frame pointer to be the stack pointer after the initial
9375 adjustment. So, we do the adjustment here. The arg pointer (which
9376 is eliminated) points to the virtual frame pointer, while the frame
9377 pointer (which may be eliminated) points to the stack pointer after
9378 the initial adjustments. */
9381 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
9383 rtx offset2
= const0_rtx
;
9384 rtx reg
= eliminate_constant_term (addr
, &offset2
);
9387 offset
= INTVAL (offset2
);
9389 if (reg
== stack_pointer_rtx
9390 || reg
== frame_pointer_rtx
9391 || reg
== hard_frame_pointer_rtx
)
9393 offset
-= cfun
->machine
->frame
.total_size
;
9394 if (reg
== hard_frame_pointer_rtx
)
9395 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9401 /* Implement ASM_OUTPUT_EXTERNAL. */
9404 mips_output_external (FILE *file
, tree decl
, const char *name
)
9406 default_elf_asm_output_external (file
, decl
, name
);
9408 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
9409 set in order to avoid putting out names that are never really
9411 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
9413 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
9415 /* When using assembler macros, emit .extern directives for
9416 all small-data externs so that the assembler knows how
9419 In most cases it would be safe (though pointless) to emit
9420 .externs for other symbols too. One exception is when an
9421 object is within the -G limit but declared by the user to
9422 be in a section other than .sbss or .sdata. */
9423 fputs ("\t.extern\t", file
);
9424 assemble_name (file
, name
);
9425 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
9426 int_size_in_bytes (TREE_TYPE (decl
)));
9431 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
9434 mips_output_filename (FILE *stream
, const char *name
)
9436 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
9438 if (write_symbols
== DWARF2_DEBUG
)
9440 else if (mips_output_filename_first_time
)
9442 mips_output_filename_first_time
= 0;
9443 num_source_filenames
+= 1;
9444 current_function_file
= name
;
9445 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
9446 output_quoted_string (stream
, name
);
9447 putc ('\n', stream
);
9449 /* If we are emitting stabs, let dbxout.c handle this (except for
9450 the mips_output_filename_first_time case). */
9451 else if (write_symbols
== DBX_DEBUG
)
9453 else if (name
!= current_function_file
9454 && strcmp (name
, current_function_file
) != 0)
9456 num_source_filenames
+= 1;
9457 current_function_file
= name
;
9458 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
9459 output_quoted_string (stream
, name
);
9460 putc ('\n', stream
);
9464 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
9466 static void ATTRIBUTE_UNUSED
9467 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9472 fputs ("\t.dtprelword\t", file
);
9476 fputs ("\t.dtpreldword\t", file
);
9482 output_addr_const (file
, x
);
9483 fputs ("+0x8000", file
);
9486 /* Implement TARGET_DWARF_REGISTER_SPAN. */
9489 mips_dwarf_register_span (rtx reg
)
9494 /* TARGET_FLOATXX is implemented as 32-bit floating-point registers but
9495 ensures that double-precision registers are treated as if they were
9496 64-bit physical registers. The code will run correctly with 32-bit or
9497 64-bit registers which means that dwarf information cannot be precise
9498 for all scenarios. We choose to state that the 64-bit values are stored
9499 in a single 64-bit 'piece'. This slightly unusual construct can then be
9500 interpreted as either a pair of registers if the registers are 32-bit or
9501 a single 64-bit register depending on hardware. */
9502 mode
= GET_MODE (reg
);
9503 if (FP_REG_P (REGNO (reg
))
9505 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
9507 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (1, reg
));
9509 /* By default, GCC maps increasing register numbers to increasing
9510 memory locations, but paired FPRs are always little-endian,
9511 regardless of the prevailing endianness. */
9512 else if (FP_REG_P (REGNO (reg
))
9513 && TARGET_BIG_ENDIAN
9514 && MAX_FPRS_PER_FMT
> 1
9515 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
9517 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
9518 high
= mips_subword (reg
, true);
9519 low
= mips_subword (reg
, false);
9520 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
9526 /* Implement TARGET_DWARF_FRAME_REG_MODE. */
9529 mips_dwarf_frame_reg_mode (int regno
)
9531 machine_mode mode
= default_dwarf_frame_reg_mode (regno
);
9533 if (FP_REG_P (regno
) && mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9539 /* DSP ALU can bypass data with no delays for the following pairs. */
9540 enum insn_code dspalu_bypass_table
[][2] =
9542 {CODE_FOR_mips_addsc
, CODE_FOR_mips_addwc
},
9543 {CODE_FOR_mips_cmpu_eq_qb
, CODE_FOR_mips_pick_qb
},
9544 {CODE_FOR_mips_cmpu_lt_qb
, CODE_FOR_mips_pick_qb
},
9545 {CODE_FOR_mips_cmpu_le_qb
, CODE_FOR_mips_pick_qb
},
9546 {CODE_FOR_mips_cmp_eq_ph
, CODE_FOR_mips_pick_ph
},
9547 {CODE_FOR_mips_cmp_lt_ph
, CODE_FOR_mips_pick_ph
},
9548 {CODE_FOR_mips_cmp_le_ph
, CODE_FOR_mips_pick_ph
},
9549 {CODE_FOR_mips_wrdsp
, CODE_FOR_mips_insv
}
9553 mips_dspalu_bypass_p (rtx out_insn
, rtx in_insn
)
9556 int num_bypass
= ARRAY_SIZE (dspalu_bypass_table
);
9557 enum insn_code out_icode
= (enum insn_code
) INSN_CODE (out_insn
);
9558 enum insn_code in_icode
= (enum insn_code
) INSN_CODE (in_insn
);
9560 for (i
= 0; i
< num_bypass
; i
++)
9562 if (out_icode
== dspalu_bypass_table
[i
][0]
9563 && in_icode
== dspalu_bypass_table
[i
][1])
9569 /* Implement ASM_OUTPUT_ASCII. */
9572 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
9578 fprintf (stream
, "\t.ascii\t\"");
9579 for (i
= 0; i
< len
; i
++)
9583 c
= (unsigned char) string
[i
];
9586 if (c
== '\\' || c
== '\"')
9588 putc ('\\', stream
);
9596 fprintf (stream
, "\\%03o", c
);
9600 if (cur_pos
> 72 && i
+1 < len
)
9603 fprintf (stream
, "\"\n\t.ascii\t\"");
9606 fprintf (stream
, "\"\n");
9609 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
9610 Update *ADDR with the operand that should be printed. */
9613 mips_output_tls_reloc_directive (rtx
*addr
)
9615 enum mips_symbol_type type
;
9617 type
= mips_classify_symbolic_expression (*addr
, SYMBOL_CONTEXT_LEA
);
9618 *addr
= mips_strip_unspec_address (*addr
);
9622 return Pmode
== SImode
? ".dtprelword\t%0" : ".dtpreldword\t%0";
9625 return Pmode
== SImode
? ".tprelword\t%0" : ".tpreldword\t%0";
9632 /* Emit either a label, .comm, or .lcomm directive. When using assembler
9633 macros, mark the symbol as written so that mips_asm_output_external
9634 won't emit an .extern for it. STREAM is the output file, NAME is the
9635 name of the symbol, INIT_STRING is the string that should be written
9636 before the symbol and FINAL_STRING is the string that should be
9637 written after it. FINAL_STRING is a printf format that consumes the
9638 remaining arguments. */
9641 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
9642 const char *final_string
, ...)
9646 fputs (init_string
, stream
);
9647 assemble_name (stream
, name
);
9648 va_start (ap
, final_string
);
9649 vfprintf (stream
, final_string
, ap
);
9652 if (!TARGET_EXPLICIT_RELOCS
)
9654 tree name_tree
= get_identifier (name
);
9655 TREE_ASM_WRITTEN (name_tree
) = 1;
9659 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
9660 NAME is the name of the object and ALIGN is the required alignment
9661 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
9662 alignment argument. */
9665 mips_declare_common_object (FILE *stream
, const char *name
,
9666 const char *init_string
,
9667 unsigned HOST_WIDE_INT size
,
9668 unsigned int align
, bool takes_alignment_p
)
9670 if (!takes_alignment_p
)
9672 size
+= (align
/ BITS_PER_UNIT
) - 1;
9673 size
-= size
% (align
/ BITS_PER_UNIT
);
9674 mips_declare_object (stream
, name
, init_string
,
9675 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
9678 mips_declare_object (stream
, name
, init_string
,
9679 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
9680 size
, align
/ BITS_PER_UNIT
);
9683 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
9684 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
9687 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
9688 unsigned HOST_WIDE_INT size
,
9691 /* If the target wants uninitialized const declarations in
9692 .rdata then don't put them in .comm. */
9693 if (TARGET_EMBEDDED_DATA
9694 && TARGET_UNINIT_CONST_IN_RODATA
9695 && TREE_CODE (decl
) == VAR_DECL
9696 && TREE_READONLY (decl
)
9697 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
9699 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
9700 targetm
.asm_out
.globalize_label (stream
, name
);
9702 switch_to_section (readonly_data_section
);
9703 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
9704 mips_declare_object (stream
, name
, "",
9705 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
9709 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
9713 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
9714 extern int size_directive_output
;
9716 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
9717 definitions except that it uses mips_declare_object to emit the label. */
9720 mips_declare_object_name (FILE *stream
, const char *name
,
9721 tree decl ATTRIBUTE_UNUSED
)
9723 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9724 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
9727 size_directive_output
= 0;
9728 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
9732 size_directive_output
= 1;
9733 size
= int_size_in_bytes (TREE_TYPE (decl
));
9734 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9737 mips_declare_object (stream
, name
, "", ":\n");
9740 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
9743 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
9747 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
9748 if (!flag_inhibit_size_directive
9749 && DECL_SIZE (decl
) != 0
9752 && DECL_INITIAL (decl
) == error_mark_node
9753 && !size_directive_output
)
9757 size_directive_output
= 1;
9758 size
= int_size_in_bytes (TREE_TYPE (decl
));
9759 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
9764 /* Mark text contents as code or data, mainly for the purpose of correct
9765 disassembly. Emit a local symbol and set its type appropriately for
9766 that purpose. Also emit `.insn' if marking contents as code so that
9767 the ISA mode is recorded and any padding that follows is disassembled
9768 as correct instructions. */
9771 mips_set_text_contents_type (FILE *file ATTRIBUTE_UNUSED
,
9772 const char *prefix ATTRIBUTE_UNUSED
,
9773 unsigned long num ATTRIBUTE_UNUSED
,
9774 bool function_p ATTRIBUTE_UNUSED
)
9776 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9777 char buf
[(sizeof (num
) * 10) / 4 + 2];
9782 sprintf (buf
, "%lu", num
);
9783 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
9784 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
9785 sname
= ACONCAT ((prefix
, fnname
, "_", buf
, NULL
));
9787 ASM_OUTPUT_TYPE_DIRECTIVE (file
, sname
, function_p
? "function" : "object");
9788 assemble_name (file
, sname
);
9789 fputs (":\n", file
);
9791 fputs ("\t.insn\n", file
);
9795 /* Return the FOO in the name of the ".mdebug.FOO" section associated
9796 with the current ABI. */
9799 mips_mdebug_abi_name (void)
9812 return TARGET_64BIT
? "eabi64" : "eabi32";
9818 /* Implement TARGET_ASM_FILE_START. */
9821 mips_file_start (void)
9823 default_file_start ();
9825 /* Generate a special section to describe the ABI switches used to
9826 produce the resultant binary. */
9828 /* Record the ABI itself. Modern versions of binutils encode
9829 this information in the ELF header flags, but GDB needs the
9830 information in order to correctly debug binaries produced by
9831 older binutils. See the function mips_gdbarch_init in
9833 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
9834 mips_mdebug_abi_name ());
9836 /* There is no ELF header flag to distinguish long32 forms of the
9837 EABI from long64 forms. Emit a special section to help tools
9838 such as GDB. Do the same for o64, which is sometimes used with
9840 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
9841 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
9842 "\t.previous\n", TARGET_LONG64
? 64 : 32);
9844 /* Record the NaN encoding. */
9845 if (HAVE_AS_NAN
|| mips_nan
!= MIPS_IEEE_754_DEFAULT
)
9846 fprintf (asm_out_file
, "\t.nan\t%s\n",
9847 mips_nan
== MIPS_IEEE_754_2008
? "2008" : "legacy");
9849 #ifdef HAVE_AS_DOT_MODULE
9850 /* Record the FP ABI. See below for comments. */
9851 if (TARGET_NO_FLOAT
)
9852 #ifdef HAVE_AS_GNU_ATTRIBUTE
9853 fputs ("\t.gnu_attribute 4, 0\n", asm_out_file
);
9857 else if (!TARGET_HARD_FLOAT_ABI
)
9858 fputs ("\t.module\tsoftfloat\n", asm_out_file
);
9859 else if (!TARGET_DOUBLE_FLOAT
)
9860 fputs ("\t.module\tsinglefloat\n", asm_out_file
);
9861 else if (TARGET_FLOATXX
)
9862 fputs ("\t.module\tfp=xx\n", asm_out_file
);
9863 else if (TARGET_FLOAT64
)
9864 fputs ("\t.module\tfp=64\n", asm_out_file
);
9866 fputs ("\t.module\tfp=32\n", asm_out_file
);
9868 if (TARGET_ODD_SPREG
)
9869 fputs ("\t.module\toddspreg\n", asm_out_file
);
9871 fputs ("\t.module\tnooddspreg\n", asm_out_file
);
9874 #ifdef HAVE_AS_GNU_ATTRIBUTE
9878 /* No floating-point operations, -mno-float. */
9879 if (TARGET_NO_FLOAT
)
9881 /* Soft-float code, -msoft-float. */
9882 else if (!TARGET_HARD_FLOAT_ABI
)
9884 /* Single-float code, -msingle-float. */
9885 else if (!TARGET_DOUBLE_FLOAT
)
9887 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64.
9889 This case used 12 callee-saved double-precision registers
9890 and is deprecated. */
9891 /* 64-bit or 32-bit FP registers on a 32-bit target, -mfpxx. */
9892 else if (TARGET_FLOATXX
)
9894 /* 64-bit FP registers on a 32-bit target, -mfp64 -modd-spreg. */
9895 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
&& TARGET_ODD_SPREG
)
9897 /* 64-bit FP registers on a 32-bit target, -mfp64 -mno-odd-spreg. */
9898 else if (mips_abi
== ABI_32
&& TARGET_FLOAT64
)
9900 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
9904 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
9908 fprintf (asm_out_file
, "\t.gnu_attribute 8, 1\n");
9913 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
9914 if (TARGET_ABICALLS
)
9916 fprintf (asm_out_file
, "\t.abicalls\n");
9917 if (TARGET_ABICALLS_PIC0
)
9918 fprintf (asm_out_file
, "\t.option\tpic0\n");
9921 if (flag_verbose_asm
)
9922 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9924 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
9927 /* Implement TARGET_ASM_CODE_END. */
9930 mips_code_end (void)
9932 mips_finish_stub (&mips16_rdhwr_stub
);
9933 mips_finish_stub (&mips16_get_fcsr_stub
);
9934 mips_finish_stub (&mips16_set_fcsr_stub
);
9937 /* Make the last instruction frame-related and note that it performs
9938 the operation described by FRAME_PATTERN. */
9941 mips_set_frame_expr (rtx frame_pattern
)
9945 insn
= get_last_insn ();
9946 RTX_FRAME_RELATED_P (insn
) = 1;
9947 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
9952 /* Return a frame-related rtx that stores REG at MEM.
9953 REG must be a single register. */
9956 mips_frame_set (rtx mem
, rtx reg
)
9960 set
= gen_rtx_SET (mem
, reg
);
9961 RTX_FRAME_RELATED_P (set
) = 1;
9966 /* Record that the epilogue has restored call-saved register REG. */
9969 mips_add_cfa_restore (rtx reg
)
9971 mips_epilogue
.cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
9972 mips_epilogue
.cfa_restores
);
9975 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9976 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9977 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9978 static const unsigned char mips16e_s2_s8_regs
[] = {
9979 30, 23, 22, 21, 20, 19, 18
9981 static const unsigned char mips16e_a0_a3_regs
[] = {
9985 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9986 ordered from the uppermost in memory to the lowest in memory. */
9987 static const unsigned char mips16e_save_restore_regs
[] = {
9988 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9991 /* Return the index of the lowest X in the range [0, SIZE) for which
9992 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9995 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
10000 for (i
= 0; i
< size
; i
++)
10001 if (BITSET_P (mask
, regs
[i
]))
10007 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
10008 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
10009 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
10010 is true for all indexes (X, SIZE). */
10013 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
10014 unsigned int size
, unsigned int *num_regs_ptr
)
10018 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
10019 for (i
++; i
< size
; i
++)
10020 if (!BITSET_P (*mask_ptr
, regs
[i
]))
10022 *num_regs_ptr
+= 1;
10023 *mask_ptr
|= 1 << regs
[i
];
10027 /* Return a simplified form of X using the register values in REG_VALUES.
10028 REG_VALUES[R] is the last value assigned to hard register R, or null
10029 if R has not been modified.
10031 This function is rather limited, but is good enough for our purposes. */
10034 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
10036 x
= avoid_constant_pool_reference (x
);
10040 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
10041 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
10042 x0
, GET_MODE (XEXP (x
, 0)));
10045 if (ARITHMETIC_P (x
))
10047 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
10048 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
10049 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
10053 && reg_values
[REGNO (x
)]
10054 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
10055 return reg_values
[REGNO (x
)];
10060 /* Return true if (set DEST SRC) stores an argument register into its
10061 caller-allocated save slot, storing the number of that argument
10062 register in *REGNO_PTR if so. REG_VALUES is as for
10063 mips16e_collect_propagate_value. */
10066 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
10067 unsigned int *regno_ptr
)
10069 unsigned int argno
, regno
;
10070 HOST_WIDE_INT offset
, required_offset
;
10073 /* Check that this is a word-mode store. */
10074 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
10077 /* Check that the register being saved is an unmodified argument
10079 regno
= REGNO (src
);
10080 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
10082 argno
= regno
- GP_ARG_FIRST
;
10084 /* Check whether the address is an appropriate stack-pointer or
10085 frame-pointer access. */
10086 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
10087 mips_split_plus (addr
, &base
, &offset
);
10088 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
10089 if (base
== hard_frame_pointer_rtx
)
10090 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
10091 else if (base
!= stack_pointer_rtx
)
10093 if (offset
!= required_offset
)
10096 *regno_ptr
= regno
;
10100 /* A subroutine of mips_expand_prologue, called only when generating
10101 MIPS16e SAVE instructions. Search the start of the function for any
10102 instructions that save argument registers into their caller-allocated
10103 save slots. Delete such instructions and return a value N such that
10104 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
10105 instructions redundant. */
10107 static unsigned int
10108 mips16e_collect_argument_saves (void)
10110 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
10111 rtx_insn
*insn
, *next
;
10112 rtx set
, dest
, src
;
10113 unsigned int nargs
, regno
;
10115 push_topmost_sequence ();
10117 memset (reg_values
, 0, sizeof (reg_values
));
10118 for (insn
= get_insns (); insn
; insn
= next
)
10120 next
= NEXT_INSN (insn
);
10121 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
10124 if (!INSN_P (insn
))
10127 set
= PATTERN (insn
);
10128 if (GET_CODE (set
) != SET
)
10131 dest
= SET_DEST (set
);
10132 src
= SET_SRC (set
);
10133 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
10135 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
10137 delete_insn (insn
);
10138 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
10141 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
10142 reg_values
[REGNO (dest
)]
10143 = mips16e_collect_propagate_value (src
, reg_values
);
10147 pop_topmost_sequence ();
10152 /* Return a move between register REGNO and memory location SP + OFFSET.
10153 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
10154 Make the move a load if RESTORE_P, otherwise make it a store. */
10157 mips16e_save_restore_reg (bool restore_p
, bool reg_parm_p
,
10158 HOST_WIDE_INT offset
, unsigned int regno
)
10162 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, stack_pointer_rtx
,
10164 reg
= gen_rtx_REG (SImode
, regno
);
10167 mips_add_cfa_restore (reg
);
10168 return gen_rtx_SET (reg
, mem
);
10171 return gen_rtx_SET (mem
, reg
);
10172 return mips_frame_set (mem
, reg
);
10175 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
10176 The instruction must:
10178 - Allocate or deallocate SIZE bytes in total; SIZE is known
10181 - Save or restore as many registers in *MASK_PTR as possible.
10182 The instruction saves the first registers at the top of the
10183 allocated area, with the other registers below it.
10185 - Save NARGS argument registers above the allocated area.
10187 (NARGS is always zero if RESTORE_P.)
10189 The SAVE and RESTORE instructions cannot save and restore all general
10190 registers, so there may be some registers left over for the caller to
10191 handle. Destructively modify *MASK_PTR so that it contains the registers
10192 that still need to be saved or restored. The caller can save these
10193 registers in the memory immediately below *OFFSET_PTR, which is a
10194 byte offset from the bottom of the allocated stack area. */
10197 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
10198 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
10199 HOST_WIDE_INT size
)
10202 HOST_WIDE_INT offset
, top_offset
;
10203 unsigned int i
, regno
;
10206 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
10208 /* Calculate the number of elements in the PARALLEL. We need one element
10209 for the stack adjustment, one for each argument register save, and one
10210 for each additional register move. */
10212 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
10213 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
10216 /* Create the final PARALLEL. */
10217 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
10220 /* Add the stack pointer adjustment. */
10221 set
= gen_rtx_SET (stack_pointer_rtx
,
10222 plus_constant (Pmode
, stack_pointer_rtx
,
10223 restore_p
? size
: -size
));
10224 RTX_FRAME_RELATED_P (set
) = 1;
10225 XVECEXP (pattern
, 0, n
++) = set
;
10227 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
10228 top_offset
= restore_p
? size
: 0;
10230 /* Save the arguments. */
10231 for (i
= 0; i
< nargs
; i
++)
10233 offset
= top_offset
+ i
* UNITS_PER_WORD
;
10234 set
= mips16e_save_restore_reg (restore_p
, true, offset
,
10236 XVECEXP (pattern
, 0, n
++) = set
;
10239 /* Then fill in the other register moves. */
10240 offset
= top_offset
;
10241 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
10243 regno
= mips16e_save_restore_regs
[i
];
10244 if (BITSET_P (*mask_ptr
, regno
))
10246 offset
-= UNITS_PER_WORD
;
10247 set
= mips16e_save_restore_reg (restore_p
, false, offset
, regno
);
10248 XVECEXP (pattern
, 0, n
++) = set
;
10249 *mask_ptr
&= ~(1 << regno
);
10253 /* Tell the caller what offset it should use for the remaining registers. */
10254 *offset_ptr
= size
+ (offset
- top_offset
);
10256 gcc_assert (n
== XVECLEN (pattern
, 0));
10261 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
10262 pointer. Return true if PATTERN matches the kind of instruction
10263 generated by mips16e_build_save_restore. If INFO is nonnull,
10264 initialize it when returning true. */
10267 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
10268 struct mips16e_save_restore_info
*info
)
10270 unsigned int i
, nargs
, mask
, extra
;
10271 HOST_WIDE_INT top_offset
, save_offset
, offset
;
10272 rtx set
, reg
, mem
, base
;
10275 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
10278 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
10279 top_offset
= adjust
> 0 ? adjust
: 0;
10281 /* Interpret all other members of the PARALLEL. */
10282 save_offset
= top_offset
- UNITS_PER_WORD
;
10286 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
10288 /* Check that we have a SET. */
10289 set
= XVECEXP (pattern
, 0, n
);
10290 if (GET_CODE (set
) != SET
)
10293 /* Check that the SET is a load (if restoring) or a store
10295 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
10299 /* Check that the address is the sum of the stack pointer and a
10300 possibly-zero constant offset. */
10301 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
10302 if (base
!= stack_pointer_rtx
)
10305 /* Check that SET's other operand is a register. */
10306 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
10310 /* Check for argument saves. */
10311 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
10312 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
10314 else if (offset
== save_offset
)
10316 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
10317 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
10320 mask
|= 1 << REGNO (reg
);
10321 save_offset
-= UNITS_PER_WORD
;
10327 /* Check that the restrictions on register ranges are met. */
10329 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
10330 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
10331 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
10332 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
10336 /* Make sure that the topmost argument register is not saved twice.
10337 The checks above ensure that the same is then true for the other
10338 argument registers. */
10339 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
10342 /* Pass back information, if requested. */
10345 info
->nargs
= nargs
;
10347 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
10353 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
10354 for the register range [MIN_REG, MAX_REG]. Return a pointer to
10355 the null terminator. */
10358 mips16e_add_register_range (char *s
, unsigned int min_reg
,
10359 unsigned int max_reg
)
10361 if (min_reg
!= max_reg
)
10362 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
10364 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
10368 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
10369 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
10372 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
10374 static char buffer
[300];
10376 struct mips16e_save_restore_info info
;
10377 unsigned int i
, end
;
10380 /* Parse the pattern. */
10381 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
10382 gcc_unreachable ();
10384 /* Add the mnemonic. */
10385 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
10388 /* Save the arguments. */
10389 if (info
.nargs
> 1)
10390 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
10391 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
10392 else if (info
.nargs
== 1)
10393 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
10395 /* Emit the amount of stack space to allocate or deallocate. */
10396 s
+= sprintf (s
, "%d", (int) info
.size
);
10398 /* Save or restore $16. */
10399 if (BITSET_P (info
.mask
, 16))
10400 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
10402 /* Save or restore $17. */
10403 if (BITSET_P (info
.mask
, 17))
10404 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
10406 /* Save or restore registers in the range $s2...$s8, which
10407 mips16e_s2_s8_regs lists in decreasing order. Note that this
10408 is a software register range; the hardware registers are not
10409 numbered consecutively. */
10410 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
10411 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
10413 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
10414 mips16e_s2_s8_regs
[i
]);
10416 /* Save or restore registers in the range $a0...$a3. */
10417 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
10418 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
10420 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
10421 mips16e_a0_a3_regs
[end
- 1]);
10423 /* Save or restore $31. */
10424 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
10425 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
10430 /* Return true if the current function returns its value in a floating-point
10431 register in MIPS16 mode. */
10434 mips16_cfun_returns_in_fpr_p (void)
10436 tree return_type
= DECL_RESULT (current_function_decl
);
10437 return (TARGET_MIPS16
10438 && TARGET_HARD_FLOAT_ABI
10439 && !aggregate_value_p (return_type
, current_function_decl
)
10440 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
10443 /* Return true if predicate PRED is true for at least one instruction.
10444 Cache the result in *CACHE, and assume that the result is true
10445 if *CACHE is already true. */
10448 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx_insn
*))
10450 rtx_insn
*insn
, *subinsn
;
10454 push_topmost_sequence ();
10455 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
10456 FOR_EACH_SUBINSN (subinsn
, insn
)
10457 if (USEFUL_INSN_P (subinsn
) && pred (subinsn
))
10462 pop_topmost_sequence ();
10467 /* Return true if INSN refers to the global pointer in an "inflexible" way.
10468 See mips_cfun_has_inflexible_gp_ref_p for details. */
10471 mips_insn_has_inflexible_gp_ref_p (rtx_insn
*insn
)
10473 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
10474 indicate that the target could be a traditional MIPS
10475 lazily-binding stub. */
10476 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
10479 /* Return true if the current function refers to the global pointer
10480 in a way that forces $28 to be valid. This means that we can't
10481 change the choice of global pointer, even for NewABI code.
10483 One example of this (and one which needs several checks) is that
10484 $28 must be valid when calling traditional MIPS lazy-binding stubs.
10485 (This restriction does not apply to PLTs.) */
10488 mips_cfun_has_inflexible_gp_ref_p (void)
10490 /* If the function has a nonlocal goto, $28 must hold the correct
10491 global pointer for the target function. That is, the target
10492 of the goto implicitly uses $28. */
10493 if (crtl
->has_nonlocal_goto
)
10496 if (TARGET_ABICALLS_PIC2
)
10498 /* Symbolic accesses implicitly use the global pointer unless
10499 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
10500 might go to traditional MIPS lazy-binding stubs. */
10501 if (!TARGET_EXPLICIT_RELOCS
)
10504 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
10505 can be lazily-bound. */
10509 /* MIPS16 functions that return in FPRs need to call an
10510 external libgcc routine. This call is only made explict
10511 during mips_expand_epilogue, and it too might be lazily bound. */
10512 if (mips16_cfun_returns_in_fpr_p ())
10516 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
10517 mips_insn_has_inflexible_gp_ref_p
);
10520 /* Return true if INSN refers to the global pointer in a "flexible" way.
10521 See mips_cfun_has_flexible_gp_ref_p for details. */
10524 mips_insn_has_flexible_gp_ref_p (rtx_insn
*insn
)
10526 return (get_attr_got (insn
) != GOT_UNSET
10527 || mips_small_data_pattern_p (PATTERN (insn
))
10528 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
10531 /* Return true if the current function references the global pointer,
10532 but if those references do not inherently require the global pointer
10533 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
10536 mips_cfun_has_flexible_gp_ref_p (void)
10538 /* Reload can sometimes introduce constant pool references
10539 into a function that otherwise didn't need them. For example,
10540 suppose we have an instruction like:
10542 (set (reg:DF R1) (float:DF (reg:SI R2)))
10544 If R2 turns out to be a constant such as 1, the instruction may
10545 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
10546 the option of using this constant if R2 doesn't get allocated
10549 In cases like these, reload will have added the constant to the
10550 pool but no instruction will yet refer to it. */
10551 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
10554 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
10555 mips_insn_has_flexible_gp_ref_p
);
10558 /* Return the register that should be used as the global pointer
10559 within this function. Return INVALID_REGNUM if the function
10560 doesn't need a global pointer. */
10562 static unsigned int
10563 mips_global_pointer (void)
10565 unsigned int regno
;
10567 /* $gp is always available unless we're using a GOT. */
10568 if (!TARGET_USE_GOT
)
10569 return GLOBAL_POINTER_REGNUM
;
10571 /* If there are inflexible references to $gp, we must use the
10572 standard register. */
10573 if (mips_cfun_has_inflexible_gp_ref_p ())
10574 return GLOBAL_POINTER_REGNUM
;
10576 /* If there are no current references to $gp, then the only uses
10577 we can introduce later are those involved in long branches. */
10578 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
10579 return INVALID_REGNUM
;
10581 /* If the global pointer is call-saved, try to use a call-clobbered
10583 if (TARGET_CALL_SAVED_GP
&& crtl
->is_leaf
)
10584 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
10585 if (!df_regs_ever_live_p (regno
)
10586 && call_really_used_regs
[regno
]
10587 && !fixed_regs
[regno
]
10588 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
10591 return GLOBAL_POINTER_REGNUM
;
10594 /* Return true if the current function's prologue must load the global
10595 pointer value into pic_offset_table_rtx and store the same value in
10596 the function's cprestore slot (if any).
10598 One problem we have to deal with is that, when emitting GOT-based
10599 position independent code, long-branch sequences will need to load
10600 the address of the branch target from the GOT. We don't know until
10601 the very end of compilation whether (and where) the function needs
10602 long branches, so we must ensure that _any_ branch can access the
10603 global pointer in some form. However, we do not want to pessimize
10604 the usual case in which all branches are short.
10606 We handle this as follows:
10608 (1) During reload, we set cfun->machine->global_pointer to
10609 INVALID_REGNUM if we _know_ that the current function
10610 doesn't need a global pointer. This is only valid if
10611 long branches don't need the GOT.
10613 Otherwise, we assume that we might need a global pointer
10614 and pick an appropriate register.
10616 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
10617 we ensure that the global pointer is available at every
10618 block boundary bar entry and exit. We do this in one of two ways:
10620 - If the function has a cprestore slot, we ensure that this
10621 slot is valid at every branch. However, as explained in
10622 point (6) below, there is no guarantee that pic_offset_table_rtx
10623 itself is valid if new uses of the global pointer are introduced
10624 after the first post-epilogue split.
10626 We guarantee that the cprestore slot is valid by loading it
10627 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
10628 this register live at every block boundary bar function entry
10629 and exit. It is then invalid to move the load (and thus the
10630 preceding store) across a block boundary.
10632 - If the function has no cprestore slot, we guarantee that
10633 pic_offset_table_rtx itself is valid at every branch.
10635 See mips_eh_uses for the handling of the register liveness.
10637 (3) During prologue and epilogue generation, we emit "ghost"
10638 placeholder instructions to manipulate the global pointer.
10640 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
10641 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
10642 that the function needs a global pointer. (There is no need to set
10643 them earlier than this, and doing it as late as possible leads to
10644 fewer false positives.)
10646 (5) If cfun->machine->must_initialize_gp_p is true during a
10647 split_insns pass, we split the ghost instructions into real
10648 instructions. These split instructions can then be optimized in
10649 the usual way. Otherwise, we keep the ghost instructions intact,
10650 and optimize for the case where they aren't needed. We still
10651 have the option of splitting them later, if we need to introduce
10652 new uses of the global pointer.
10654 For example, the scheduler ignores a ghost instruction that
10655 stores $28 to the stack, but it handles the split form of
10656 the ghost instruction as an ordinary store.
10658 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
10659 is true during the first post-epilogue split_insns pass, we split
10660 calls and restore_gp patterns into instructions that explicitly
10661 load pic_offset_table_rtx from the cprestore slot. Otherwise,
10662 we split these patterns into instructions that _don't_ load from
10663 the cprestore slot.
10665 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
10666 time of the split, then any instructions that exist at that time
10667 can make free use of pic_offset_table_rtx. However, if we want
10668 to introduce new uses of the global pointer after the split,
10669 we must explicitly load the value from the cprestore slot, since
10670 pic_offset_table_rtx itself might not be valid at a given point
10673 The idea is that we want to be able to delete redundant
10674 loads from the cprestore slot in the usual case where no
10675 long branches are needed.
10677 (7) If cfun->machine->must_initialize_gp_p is still false at the end
10678 of md_reorg, we decide whether the global pointer is needed for
10679 long branches. If so, we set cfun->machine->must_initialize_gp_p
10680 to true and split the ghost instructions into real instructions
10683 Note that the ghost instructions must have a zero length for three reasons:
10685 - Giving the length of the underlying $gp sequence might cause
10686 us to use long branches in cases where they aren't really needed.
10688 - They would perturb things like alignment calculations.
10690 - More importantly, the hazard detection in md_reorg relies on
10691 empty instructions having a zero length.
10693 If we find a long branch and split the ghost instructions at the
10694 end of md_reorg, the split could introduce more long branches.
10695 That isn't a problem though, because we still do the split before
10696 the final shorten_branches pass.
10698 This is extremely ugly, but it seems like the best compromise between
10699 correctness and efficiency. */
10702 mips_must_initialize_gp_p (void)
10704 return cfun
->machine
->must_initialize_gp_p
;
10707 /* Return true if REGNO is a register that is ordinarily call-clobbered
10708 but must nevertheless be preserved by an interrupt handler. */
10711 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
10713 if ((ISA_HAS_HILO
|| TARGET_DSP
)
10714 && MD_REG_P (regno
))
10717 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
10720 if (GP_REG_P (regno
)
10721 && cfun
->machine
->use_shadow_register_set
== SHADOW_SET_NO
)
10723 /* $0 is hard-wired. */
10724 if (regno
== GP_REG_FIRST
)
10727 /* The interrupt handler can treat kernel registers as
10728 scratch registers. */
10729 if (KERNEL_REG_P (regno
))
10732 /* The function will return the stack pointer to its original value
10734 if (regno
== STACK_POINTER_REGNUM
)
10737 /* Otherwise, return true for registers that aren't ordinarily
10739 return call_really_used_regs
[regno
];
10745 /* Return true if the current function should treat register REGNO
10749 mips_cfun_call_saved_reg_p (unsigned int regno
)
10751 /* If the user makes an ordinarily-call-saved register global,
10752 that register is no longer call-saved. */
10753 if (global_regs
[regno
])
10756 /* Interrupt handlers need to save extra registers. */
10757 if (cfun
->machine
->interrupt_handler_p
10758 && mips_interrupt_extra_call_saved_reg_p (regno
))
10761 /* call_insns preserve $28 unless they explicitly say otherwise,
10762 so call_really_used_regs[] treats $28 as call-saved. However,
10763 we want the ABI property rather than the default call_insn
10765 return (regno
== GLOBAL_POINTER_REGNUM
10766 ? TARGET_CALL_SAVED_GP
10767 : !call_really_used_regs
[regno
]);
10770 /* Return true if the function body might clobber register REGNO.
10771 We know that REGNO is call-saved. */
10774 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
10776 /* Some functions should be treated as clobbering all call-saved
10778 if (crtl
->saves_all_registers
)
10781 /* DF handles cases where a register is explicitly referenced in
10782 the rtl. Incoming values are passed in call-clobbered registers,
10783 so we can assume that any live call-saved register is set within
10785 if (df_regs_ever_live_p (regno
))
10788 /* Check for registers that are clobbered by FUNCTION_PROFILER.
10789 These clobbers are not explicit in the rtl. */
10790 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
10793 /* If we're using a call-saved global pointer, the function's
10794 prologue will need to set it up. */
10795 if (cfun
->machine
->global_pointer
== regno
)
10798 /* The function's prologue will need to set the frame pointer if
10799 frame_pointer_needed. */
10800 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
10803 /* If a MIPS16 function returns a value in FPRs, its epilogue
10804 will need to call an external libgcc routine. This yet-to-be
10805 generated call_insn will clobber $31. */
10806 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
10809 /* If REGNO is ordinarily call-clobbered, we must assume that any
10810 called function could modify it. */
10811 if (cfun
->machine
->interrupt_handler_p
10813 && mips_interrupt_extra_call_saved_reg_p (regno
))
10819 /* Return true if the current function must save register REGNO. */
10822 mips_save_reg_p (unsigned int regno
)
10824 if (mips_cfun_call_saved_reg_p (regno
))
10826 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
10829 /* Save both registers in an FPR pair if either one is used. This is
10830 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
10831 register to be used without the even register. */
10832 if (FP_REG_P (regno
)
10833 && MAX_FPRS_PER_FMT
== 2
10834 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
10838 /* We need to save the incoming return address if __builtin_eh_return
10839 is being used to set a different return address. */
10840 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
10846 /* Populate the current function's mips_frame_info structure.
10848 MIPS stack frames look like:
10850 +-------------------------------+
10852 | incoming stack arguments |
10854 +-------------------------------+
10856 | caller-allocated save area |
10857 A | for register arguments |
10859 +-------------------------------+ <-- incoming stack pointer
10861 | callee-allocated save area |
10862 B | for arguments that are |
10863 | split between registers and |
10866 +-------------------------------+ <-- arg_pointer_rtx
10868 C | callee-allocated save area |
10869 | for register varargs |
10871 +-------------------------------+ <-- frame_pointer_rtx
10872 | | + cop0_sp_offset
10873 | COP0 reg save area | + UNITS_PER_WORD
10875 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
10876 | | + UNITS_PER_WORD
10877 | accumulator save area |
10879 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
10880 | | + UNITS_PER_HWFPVALUE
10883 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
10884 | | + UNITS_PER_WORD
10887 +-------------------------------+ <-- frame_pointer_rtx with
10888 | | \ -fstack-protector
10889 | local variables | | var_size
10891 +-------------------------------+
10893 | $gp save area | | cprestore_size
10895 P +-------------------------------+ <-- hard_frame_pointer_rtx for
10897 | outgoing stack arguments | |
10899 +-------------------------------+ | args_size
10901 | caller-allocated save area | |
10902 | for register arguments | |
10904 +-------------------------------+ <-- stack_pointer_rtx
10905 frame_pointer_rtx without
10907 hard_frame_pointer_rtx for
10910 At least two of A, B and C will be empty.
10912 Dynamic stack allocations such as alloca insert data at point P.
10913 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
10914 hard_frame_pointer_rtx unchanged. */
10917 mips_compute_frame_info (void)
10919 struct mips_frame_info
*frame
;
10920 HOST_WIDE_INT offset
, size
;
10921 unsigned int regno
, i
;
10923 /* Skip re-computing the frame info after reload completed. */
10924 if (reload_completed
)
10927 /* Set this function's interrupt properties. */
10928 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
10930 if (mips_isa_rev
< 2)
10931 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10932 else if (TARGET_MIPS16
)
10933 error ("interrupt handlers cannot be MIPS16 functions");
10936 cfun
->machine
->interrupt_handler_p
= true;
10937 cfun
->machine
->int_mask
=
10938 mips_interrupt_mask (TREE_TYPE (current_function_decl
));
10939 cfun
->machine
->use_shadow_register_set
=
10940 mips_use_shadow_register_set (TREE_TYPE (current_function_decl
));
10941 cfun
->machine
->keep_interrupts_masked_p
=
10942 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
10943 cfun
->machine
->use_debug_exception_return_p
=
10944 mips_use_debug_exception_return_p (TREE_TYPE
10945 (current_function_decl
));
10949 frame
= &cfun
->machine
->frame
;
10950 memset (frame
, 0, sizeof (*frame
));
10951 size
= get_frame_size ();
10953 /* The first two blocks contain the outgoing argument area and the $gp save
10954 slot. This area isn't needed in leaf functions. We can also skip it
10955 if we know that none of the called functions will use this space.
10957 But if the target-independent frame size is nonzero, we have already
10958 committed to allocating these in TARGET_STARTING_FRAME_OFFSET for
10959 !FRAME_GROWS_DOWNWARD. */
10961 if ((size
== 0 || FRAME_GROWS_DOWNWARD
)
10962 && (crtl
->is_leaf
|| (cfun
->machine
->optimize_call_stack
&& !flag_pic
)))
10964 /* The MIPS 3.0 linker does not like functions that dynamically
10965 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10966 looks like we are trying to create a second frame pointer to the
10967 function, so allocate some stack space to make it happy. */
10968 if (cfun
->calls_alloca
)
10969 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
10971 frame
->args_size
= 0;
10972 frame
->cprestore_size
= 0;
10976 frame
->args_size
= crtl
->outgoing_args_size
;
10977 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
10980 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10981 arguments. This tends to increase the chances of using unextended
10982 instructions for local variables and incoming arguments. */
10984 frame
->hard_frame_pointer_offset
= frame
->args_size
;
10986 /* PR 69129 / 69012: Beware of a possible race condition. mips_global_pointer
10987 might call mips_cfun_has_inflexible_gp_ref_p which in turn can call
10988 mips_find_gp_ref which will iterate over the current insn sequence.
10989 If any of these insns use the cprestore_save_slot_operand or
10990 cprestore_load_slot_operand predicates in order to be recognised then
10991 they will call mips_cprestore_address_p which calls
10992 mips_get_cprestore_base_and_offset which expects the frame information
10993 to be filled in... In fact mips_get_cprestore_base_and_offset only
10994 needs the args_size and hard_frame_pointer_offset fields to be filled
10995 in, which is why the global_pointer field is initialised here and not
10997 cfun
->machine
->global_pointer
= mips_global_pointer ();
10999 offset
= frame
->args_size
+ frame
->cprestore_size
;
11001 /* Move above the local variables. */
11002 frame
->var_size
= MIPS_STACK_ALIGN (size
);
11003 offset
+= frame
->var_size
;
11005 /* Find out which GPRs we need to save. */
11006 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
11007 if (mips_save_reg_p (regno
))
11010 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
11013 /* If this function calls eh_return, we must also save and restore the
11014 EH data registers. */
11015 if (crtl
->calls_eh_return
)
11016 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
11019 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
11022 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
11023 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
11024 save all later registers too. */
11025 if (GENERATE_MIPS16E_SAVE_RESTORE
)
11027 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
11028 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
11029 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
11030 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
11033 /* Move above the GPR save area. */
11034 if (frame
->num_gp
> 0)
11036 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
11037 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
11040 /* Find out which FPRs we need to save. This loop must iterate over
11041 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
11042 if (TARGET_HARD_FLOAT
)
11043 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
11044 if (mips_save_reg_p (regno
))
11046 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
11047 frame
->fmask
|= ~(~0U << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
11050 /* Move above the FPR save area. */
11051 if (frame
->num_fp
> 0)
11053 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
11054 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
11057 /* Add in space for the interrupt context information. */
11058 if (cfun
->machine
->interrupt_handler_p
)
11061 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
11064 frame
->acc_mask
|= (1 << 0);
11067 /* Check accumulators 1, 2, 3. */
11068 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
11069 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
11072 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
11075 /* All interrupt context functions need space to preserve STATUS. */
11076 frame
->num_cop0_regs
++;
11078 /* We need to save EPC regardless of whether interrupts remain masked
11079 as exceptions will corrupt EPC. */
11080 frame
->num_cop0_regs
++;
11083 /* Move above the accumulator save area. */
11084 if (frame
->num_acc
> 0)
11086 /* Each accumulator needs 2 words. */
11087 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
11088 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
11091 /* Move above the COP0 register save area. */
11092 if (frame
->num_cop0_regs
> 0)
11094 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
11095 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
11098 /* Determine if we can save the callee-saved registers in the frame
11099 header. Restrict this to functions where there is no other reason
11100 to allocate stack space so that we can eliminate the instructions
11101 that modify the stack pointer. */
11105 && flag_frame_header_optimization
11106 && !MAIN_NAME_P (DECL_NAME (current_function_decl
))
11107 && cfun
->machine
->varargs_size
== 0
11108 && crtl
->args
.pretend_args_size
== 0
11109 && frame
->var_size
== 0
11110 && frame
->num_acc
== 0
11111 && frame
->num_cop0_regs
== 0
11112 && frame
->num_fp
== 0
11113 && frame
->num_gp
> 0
11114 && frame
->num_gp
<= MAX_ARGS_IN_REGISTERS
11115 && !GENERATE_MIPS16E_SAVE_RESTORE
11116 && !cfun
->machine
->interrupt_handler_p
11117 && cfun
->machine
->does_not_use_frame_header
11118 && cfun
->machine
->optimize_call_stack
11119 && !cfun
->machine
->callers_may_not_allocate_frame
11120 && !mips_cfun_has_cprestore_slot_p ())
11123 frame
->gp_sp_offset
= REG_PARM_STACK_SPACE(cfun
) - UNITS_PER_WORD
;
11124 cfun
->machine
->use_frame_header_for_callee_saved_regs
= true;
11127 /* Move above the callee-allocated varargs save area. */
11128 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
11129 frame
->arg_pointer_offset
= offset
;
11131 /* Move above the callee-allocated area for pretend stack arguments. */
11132 offset
+= crtl
->args
.pretend_args_size
;
11133 frame
->total_size
= offset
;
11135 /* Work out the offsets of the save areas from the top of the frame. */
11136 if (frame
->gp_sp_offset
> 0)
11137 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
11138 if (frame
->fp_sp_offset
> 0)
11139 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
11140 if (frame
->acc_sp_offset
> 0)
11141 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
11142 if (frame
->num_cop0_regs
> 0)
11143 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
11146 /* Return the style of GP load sequence that is being used for the
11147 current function. */
11149 enum mips_loadgp_style
11150 mips_current_loadgp_style (void)
11152 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
11153 return LOADGP_NONE
;
11155 if (TARGET_RTP_PIC
)
11158 if (TARGET_ABSOLUTE_ABICALLS
)
11159 return LOADGP_ABSOLUTE
;
11161 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
11164 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11167 mips_frame_pointer_required (void)
11169 /* If the function contains dynamic stack allocations, we need to
11170 use the frame pointer to access the static parts of the frame. */
11171 if (cfun
->calls_alloca
)
11174 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
11175 reload may be unable to compute the address of a local variable,
11176 since there is no way to add a large constant to the stack pointer
11177 without using a second temporary register. */
11180 mips_compute_frame_info ();
11181 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
11188 /* Make sure that we're not trying to eliminate to the wrong hard frame
11192 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
11194 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
11197 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
11198 or argument pointer. TO is either the stack pointer or hard frame
11202 mips_initial_elimination_offset (int from
, int to
)
11204 HOST_WIDE_INT offset
;
11206 mips_compute_frame_info ();
11208 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
11211 case FRAME_POINTER_REGNUM
:
11212 if (FRAME_GROWS_DOWNWARD
)
11213 offset
= (cfun
->machine
->frame
.args_size
11214 + cfun
->machine
->frame
.cprestore_size
11215 + cfun
->machine
->frame
.var_size
);
11220 case ARG_POINTER_REGNUM
:
11221 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
11225 gcc_unreachable ();
11228 if (to
== HARD_FRAME_POINTER_REGNUM
)
11229 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
11234 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
11237 mips_extra_live_on_entry (bitmap regs
)
11239 if (TARGET_USE_GOT
)
11241 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
11242 the global pointer. */
11243 if (!TARGET_ABSOLUTE_ABICALLS
)
11244 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
11246 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
11247 the global pointer. */
11249 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
11251 /* See the comment above load_call<mode> for details. */
11252 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
11256 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
11260 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
11265 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
11268 /* Emit code to change the current function's return address to
11269 ADDRESS. SCRATCH is available as a scratch register, if needed.
11270 ADDRESS and SCRATCH are both word-mode GPRs. */
11273 mips_set_return_address (rtx address
, rtx scratch
)
11277 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
11278 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
11279 cfun
->machine
->frame
.gp_sp_offset
);
11280 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
11283 /* Return true if the current function has a cprestore slot. */
11286 mips_cfun_has_cprestore_slot_p (void)
11288 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
11289 && cfun
->machine
->frame
.cprestore_size
> 0);
11292 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
11293 cprestore slot. LOAD_P is true if the caller wants to load from
11294 the cprestore slot; it is false if the caller wants to store to
11298 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
11301 const struct mips_frame_info
*frame
;
11303 frame
= &cfun
->machine
->frame
;
11304 /* .cprestore always uses the stack pointer instead of the frame pointer.
11305 We have a free choice for direct stores for non-MIPS16 functions,
11306 and for MIPS16 functions whose cprestore slot is in range of the
11307 stack pointer. Using the stack pointer would sometimes give more
11308 (early) scheduling freedom, but using the frame pointer would
11309 sometimes give more (late) scheduling freedom. It's hard to
11310 predict which applies to a given function, so let's keep things
11313 Loads must always use the frame pointer in functions that call
11314 alloca, and there's little benefit to using the stack pointer
11316 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
11318 *base
= hard_frame_pointer_rtx
;
11319 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
11323 *base
= stack_pointer_rtx
;
11324 *offset
= frame
->args_size
;
11328 /* Return true if X is the load or store address of the cprestore slot;
11329 LOAD_P says which. */
11332 mips_cprestore_address_p (rtx x
, bool load_p
)
11334 rtx given_base
, required_base
;
11335 HOST_WIDE_INT given_offset
, required_offset
;
11337 mips_split_plus (x
, &given_base
, &given_offset
);
11338 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
11339 return given_base
== required_base
&& given_offset
== required_offset
;
11342 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
11343 going to load from it, false if we are going to store to it.
11344 Use TEMP as a temporary register if need be. */
11347 mips_cprestore_slot (rtx temp
, bool load_p
)
11350 HOST_WIDE_INT offset
;
11352 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
11353 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
11356 /* Emit instructions to save global pointer value GP into cprestore
11357 slot MEM. OFFSET is the offset that MEM applies to the base register.
11359 MEM may not be a legitimate address. If it isn't, TEMP is a
11360 temporary register that can be used, otherwise it is a SCRATCH. */
11363 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
11365 if (TARGET_CPRESTORE_DIRECTIVE
)
11367 gcc_assert (gp
== pic_offset_table_rtx
);
11368 emit_insn (PMODE_INSN (gen_cprestore
, (mem
, offset
)));
11371 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
11374 /* Restore $gp from its save slot, using TEMP as a temporary base register
11375 if need be. This function is for o32 and o64 abicalls only.
11377 See mips_must_initialize_gp_p for details about how we manage the
11381 mips_restore_gp_from_cprestore_slot (rtx temp
)
11383 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
11385 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
11387 emit_note (NOTE_INSN_DELETED
);
11393 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
11394 mips_emit_move (pic_offset_table_rtx
, temp
);
11397 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
11398 if (!TARGET_EXPLICIT_RELOCS
)
11399 emit_insn (gen_blockage ());
11402 /* A function to save or store a register. The first argument is the
11403 register and the second is the stack slot. */
11404 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
11406 /* Use FN to save or restore register REGNO. MODE is the register's
11407 mode and OFFSET is the offset of its save slot from the current
11411 mips_save_restore_reg (machine_mode mode
, int regno
,
11412 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
11416 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11418 fn (gen_rtx_REG (mode
, regno
), mem
);
11421 /* Call FN for each accumulator that is saved by the current function.
11422 SP_OFFSET is the offset of the current stack pointer from the start
11426 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
11428 HOST_WIDE_INT offset
;
11431 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
11432 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
11434 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
11435 offset
-= UNITS_PER_WORD
;
11436 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
11437 offset
-= UNITS_PER_WORD
;
11440 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
11441 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
11442 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
11444 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
11445 offset
-= UNITS_PER_WORD
;
11449 /* Save register REG to MEM. Make the instruction frame-related. */
11452 mips_save_reg (rtx reg
, rtx mem
)
11454 if (GET_MODE (reg
) == DFmode
11455 && (!TARGET_FLOAT64
11456 || mips_abi
== ABI_32
))
11460 mips_emit_move_or_split (mem
, reg
, SPLIT_IF_NECESSARY
);
11462 x1
= mips_frame_set (mips_subword (mem
, false),
11463 mips_subword (reg
, false));
11464 x2
= mips_frame_set (mips_subword (mem
, true),
11465 mips_subword (reg
, true));
11466 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
11469 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
11472 /* Capture the register combinations that are allowed in a SWM or LWM
11473 instruction. The entries are ordered by number of registers set in
11474 the mask. We also ignore the single register encodings because a
11475 normal SW/LW is preferred. */
11477 static const unsigned int umips_swm_mask
[17] = {
11478 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
11479 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
11480 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
11481 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
11485 static const unsigned int umips_swm_encoding
[17] = {
11486 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
11489 /* Try to use a microMIPS LWM or SWM instruction to save or restore
11490 as many GPRs in *MASK as possible. *OFFSET is the offset from the
11491 stack pointer of the topmost save slot.
11493 Remove from *MASK all registers that were handled using LWM and SWM.
11494 Update *OFFSET so that it points to the first unused save slot. */
11497 umips_build_save_restore (mips_save_restore_fn fn
,
11498 unsigned *mask
, HOST_WIDE_INT
*offset
)
11502 rtx pattern
, set
, reg
, mem
;
11503 HOST_WIDE_INT this_offset
;
11506 /* Try matching $16 to $31 (s0 to ra). */
11507 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
11508 if ((*mask
& 0xffff0000) == umips_swm_mask
[i
])
11511 if (i
== ARRAY_SIZE (umips_swm_mask
))
11514 /* Get the offset of the lowest save slot. */
11515 nregs
= (umips_swm_encoding
[i
] & 0xf) + (umips_swm_encoding
[i
] >> 4);
11516 this_offset
= *offset
- UNITS_PER_WORD
* (nregs
- 1);
11518 /* LWM/SWM can only support offsets from -2048 to 2047. */
11519 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
11522 /* Create the final PARALLEL. */
11523 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nregs
));
11524 this_base
= stack_pointer_rtx
;
11526 /* For registers $16-$23 and $30. */
11527 for (j
= 0; j
< (umips_swm_encoding
[i
] & 0xf); j
++)
11529 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
11530 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
11531 unsigned int regno
= (j
!= 8) ? 16 + j
: 30;
11532 *mask
&= ~(1 << regno
);
11533 reg
= gen_rtx_REG (SImode
, regno
);
11534 if (fn
== mips_save_reg
)
11535 set
= mips_frame_set (mem
, reg
);
11538 set
= gen_rtx_SET (reg
, mem
);
11539 mips_add_cfa_restore (reg
);
11541 XVECEXP (pattern
, 0, j
) = set
;
11544 /* For register $31. */
11545 if (umips_swm_encoding
[i
] >> 4)
11547 HOST_WIDE_INT offset
= this_offset
+ j
* UNITS_PER_WORD
;
11548 *mask
&= ~(1 << 31);
11549 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, this_base
, offset
));
11550 reg
= gen_rtx_REG (SImode
, 31);
11551 if (fn
== mips_save_reg
)
11552 set
= mips_frame_set (mem
, reg
);
11555 set
= gen_rtx_SET (reg
, mem
);
11556 mips_add_cfa_restore (reg
);
11558 XVECEXP (pattern
, 0, j
) = set
;
11561 pattern
= emit_insn (pattern
);
11562 if (fn
== mips_save_reg
)
11563 RTX_FRAME_RELATED_P (pattern
) = 1;
11565 /* Adjust the last offset. */
11566 *offset
-= UNITS_PER_WORD
* nregs
;
11571 /* Call FN for each register that is saved by the current function.
11572 SP_OFFSET is the offset of the current stack pointer from the start
11576 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
11577 mips_save_restore_fn fn
)
11579 machine_mode fpr_mode
;
11581 const struct mips_frame_info
*frame
= &cfun
->machine
->frame
;
11582 HOST_WIDE_INT offset
;
11585 /* Save registers starting from high to low. The debuggers prefer at least
11586 the return register be stored at func+4, and also it allows us not to
11587 need a nop in the epilogue if at least one register is reloaded in
11588 addition to return address. */
11589 offset
= frame
->gp_sp_offset
- sp_offset
;
11590 mask
= frame
->mask
;
11592 if (TARGET_MICROMIPS
)
11593 umips_build_save_restore (fn
, &mask
, &offset
);
11595 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
11596 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
11598 /* Record the ra offset for use by mips_function_profiler. */
11599 if (regno
== RETURN_ADDR_REGNUM
)
11600 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
11601 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
11602 offset
-= UNITS_PER_WORD
;
11605 /* This loop must iterate over the same space as its companion in
11606 mips_compute_frame_info. */
11607 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
11608 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
11609 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
11610 regno
>= FP_REG_FIRST
;
11611 regno
-= MAX_FPRS_PER_FMT
)
11612 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
11614 if (!TARGET_FLOAT64
&& TARGET_DOUBLE_FLOAT
11615 && (fixed_regs
[regno
] || fixed_regs
[regno
+ 1]))
11617 if (fixed_regs
[regno
])
11618 mips_save_restore_reg (SFmode
, regno
+ 1, offset
, fn
);
11620 mips_save_restore_reg (SFmode
, regno
, offset
, fn
);
11623 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
11624 offset
-= GET_MODE_SIZE (fpr_mode
);
11628 /* Return true if a move between register REGNO and its save slot (MEM)
11629 can be done in a single move. LOAD_P is true if we are loading
11630 from the slot, false if we are storing to it. */
11633 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
11635 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
11636 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
11639 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
11640 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
11643 /* Emit a move from SRC to DEST, given that one of them is a register
11644 save slot and that the other is a register. TEMP is a temporary
11645 GPR of the same mode that is available if need be. */
11648 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
11650 unsigned int regno
;
11655 regno
= REGNO (src
);
11660 regno
= REGNO (dest
);
11664 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
11666 /* We don't yet know whether we'll need this instruction or not.
11667 Postpone the decision by emitting a ghost move. This move
11668 is specifically not frame-related; only the split version is. */
11670 emit_insn (gen_move_gpdi (dest
, src
));
11672 emit_insn (gen_move_gpsi (dest
, src
));
11676 if (regno
== HI_REGNUM
)
11680 mips_emit_move (temp
, src
);
11682 emit_insn (gen_mthidi_ti (gen_rtx_REG (TImode
, MD_REG_FIRST
),
11683 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
11685 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
11686 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
11691 emit_insn (gen_mfhidi_ti (temp
,
11692 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
11694 emit_insn (gen_mfhisi_di (temp
,
11695 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
11696 mips_emit_move (dest
, temp
);
11699 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
11700 mips_emit_move (dest
, src
);
11703 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
11704 mips_emit_move (temp
, src
);
11705 mips_emit_move (dest
, temp
);
11708 mips_set_frame_expr (mips_frame_set (dest
, src
));
11711 /* If we're generating n32 or n64 abicalls, and the current function
11712 does not use $28 as its global pointer, emit a cplocal directive.
11713 Use pic_offset_table_rtx as the argument to the directive. */
11716 mips_output_cplocal (void)
11718 if (!TARGET_EXPLICIT_RELOCS
11719 && mips_must_initialize_gp_p ()
11720 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
11721 output_asm_insn (".cplocal %+", 0);
11724 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
11727 mips_output_function_prologue (FILE *file
)
11729 const char *fnname
;
11731 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
11732 floating-point arguments. */
11734 && TARGET_HARD_FLOAT_ABI
11735 && crtl
->args
.info
.fp_code
!= 0)
11736 mips16_build_function_stub ();
11738 /* Get the function name the same way that toplev.c does before calling
11739 assemble_start_function. This is needed so that the name used here
11740 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11741 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11742 mips_start_function_definition (fnname
, TARGET_MIPS16
);
11744 /* Output MIPS-specific frame information. */
11745 if (!flag_inhibit_size_directive
)
11747 const struct mips_frame_info
*frame
;
11749 frame
= &cfun
->machine
->frame
;
11751 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
11753 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
11754 "# vars= " HOST_WIDE_INT_PRINT_DEC
11756 ", args= " HOST_WIDE_INT_PRINT_DEC
11757 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
11758 reg_names
[frame_pointer_needed
11759 ? HARD_FRAME_POINTER_REGNUM
11760 : STACK_POINTER_REGNUM
],
11761 (frame_pointer_needed
11762 ? frame
->total_size
- frame
->hard_frame_pointer_offset
11763 : frame
->total_size
),
11764 reg_names
[RETURN_ADDR_REGNUM
],
11766 frame
->num_gp
, frame
->num_fp
,
11768 frame
->cprestore_size
);
11770 /* .mask MASK, OFFSET. */
11771 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11772 frame
->mask
, frame
->gp_save_offset
);
11774 /* .fmask MASK, OFFSET. */
11775 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
11776 frame
->fmask
, frame
->fp_save_offset
);
11779 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
11780 Also emit the ".set noreorder; .set nomacro" sequence for functions
11782 if (mips_must_initialize_gp_p ()
11783 && mips_current_loadgp_style () == LOADGP_OLDABI
)
11787 /* This is a fixed-form sequence. The position of the
11788 first two instructions is important because of the
11789 way _gp_disp is defined. */
11790 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
11791 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
11792 output_asm_insn ("sll\t$2,16", 0);
11793 output_asm_insn ("addu\t$2,$3", 0);
11797 /* .cpload must be in a .set noreorder but not a
11798 .set nomacro block. */
11799 mips_push_asm_switch (&mips_noreorder
);
11800 output_asm_insn (".cpload\t%^", 0);
11801 if (!cfun
->machine
->all_noreorder_p
)
11802 mips_pop_asm_switch (&mips_noreorder
);
11804 mips_push_asm_switch (&mips_nomacro
);
11807 else if (cfun
->machine
->all_noreorder_p
)
11809 mips_push_asm_switch (&mips_noreorder
);
11810 mips_push_asm_switch (&mips_nomacro
);
11813 /* Tell the assembler which register we're using as the global
11814 pointer. This is needed for thunks, since they can use either
11815 explicit relocs or assembler macros. */
11816 mips_output_cplocal ();
11819 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
11822 mips_output_function_epilogue (FILE *)
11824 const char *fnname
;
11826 /* Reinstate the normal $gp. */
11827 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
11828 mips_output_cplocal ();
11830 if (cfun
->machine
->all_noreorder_p
)
11832 mips_pop_asm_switch (&mips_nomacro
);
11833 mips_pop_asm_switch (&mips_noreorder
);
11836 /* Get the function name the same way that toplev.c does before calling
11837 assemble_start_function. This is needed so that the name used here
11838 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
11839 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
11840 mips_end_function_definition (fnname
);
11843 /* Emit an optimisation barrier for accesses to the current frame. */
11846 mips_frame_barrier (void)
11848 emit_clobber (gen_frame_mem (BLKmode
, stack_pointer_rtx
));
11852 /* The __gnu_local_gp symbol. */
11854 static GTY(()) rtx mips_gnu_local_gp
;
11856 /* If we're generating n32 or n64 abicalls, emit instructions
11857 to set up the global pointer. */
11860 mips_emit_loadgp (void)
11862 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
11864 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
11865 switch (mips_current_loadgp_style ())
11867 case LOADGP_ABSOLUTE
:
11868 if (mips_gnu_local_gp
== NULL
)
11870 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
11871 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
11873 emit_insn (PMODE_INSN (gen_loadgp_absolute
,
11874 (pic_reg
, mips_gnu_local_gp
)));
11877 case LOADGP_OLDABI
:
11878 /* Added by mips_output_function_prologue. */
11881 case LOADGP_NEWABI
:
11882 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
11883 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
11884 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11885 emit_insn (PMODE_INSN (gen_loadgp_newabi
,
11886 (pic_reg
, offset
, incoming_address
)));
11890 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
11891 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
11892 emit_insn (PMODE_INSN (gen_loadgp_rtp
, (pic_reg
, base
, index
)));
11900 emit_insn (PMODE_INSN (gen_copygp_mips16
,
11901 (pic_offset_table_rtx
, pic_reg
)));
11903 /* Emit a blockage if there are implicit uses of the GP register.
11904 This includes profiled functions, because FUNCTION_PROFILE uses
11906 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
11907 emit_insn (gen_loadgp_blockage ());
11910 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11912 #if PROBE_INTERVAL > 32768
11913 #error Cannot use indexed addressing mode for stack probing
11916 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11917 inclusive. These are offsets from the current stack pointer. */
11920 mips_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
11923 sorry ("-fstack-check=specific not implemented for MIPS16");
11925 /* See if we have a constant small number of probes to generate. If so,
11926 that's the easy case. */
11927 if (first
+ size
<= 32768)
11931 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11932 it exceeds SIZE. If only one probe is needed, this will not
11933 generate any code. Then probe at FIRST + SIZE. */
11934 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
11935 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11938 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
11942 /* Otherwise, do the same as above, but in a loop. Note that we must be
11943 extra careful with variables wrapping around because we might be at
11944 the very top (or the very bottom) of the address space and we have
11945 to be able to handle this case properly; in particular, we use an
11946 equality test for the loop condition. */
11949 HOST_WIDE_INT rounded_size
;
11950 rtx r3
= MIPS_PROLOGUE_TEMP (Pmode
);
11951 rtx r12
= MIPS_PROLOGUE_TEMP2 (Pmode
);
11953 /* Sanity check for the addressing mode we're going to use. */
11954 gcc_assert (first
<= 32768);
11957 /* Step 1: round SIZE to the previous multiple of the interval. */
11959 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
11962 /* Step 2: compute initial and final value of the loop counter. */
11964 /* TEST_ADDR = SP + FIRST. */
11965 emit_insn (gen_rtx_SET (r3
, plus_constant (Pmode
, stack_pointer_rtx
,
11968 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
11969 if (rounded_size
> 32768)
11971 emit_move_insn (r12
, GEN_INT (rounded_size
));
11972 emit_insn (gen_rtx_SET (r12
, gen_rtx_MINUS (Pmode
, r3
, r12
)));
11975 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, r3
,
11979 /* Step 3: the loop
11983 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11986 while (TEST_ADDR != LAST_ADDR)
11988 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11989 until it is equal to ROUNDED_SIZE. */
11991 emit_insn (PMODE_INSN (gen_probe_stack_range
, (r3
, r3
, r12
)));
11994 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11995 that SIZE is equal to ROUNDED_SIZE. */
11997 if (size
!= rounded_size
)
11998 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
12001 /* Make sure nothing is scheduled before we are done. */
12002 emit_insn (gen_blockage ());
12005 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
12006 absolute addresses. */
12009 mips_output_probe_stack_range (rtx reg1
, rtx reg2
)
12011 static int labelno
= 0;
12012 char loop_lab
[32], tmp
[64];
12015 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
12018 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
12020 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
12022 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
12023 if (TARGET_64BIT
&& TARGET_LONG64
)
12024 output_asm_insn ("daddiu\t%0,%0,%1", xops
);
12026 output_asm_insn ("addiu\t%0,%0,%1", xops
);
12028 /* Probe at TEST_ADDR, test if TEST_ADDR == LAST_ADDR and branch. */
12030 strcpy (tmp
, "%(%<bne\t%0,%1,");
12031 output_asm_insn (strcat (tmp
, &loop_lab
[1]), xops
);
12033 output_asm_insn ("sd\t$0,0(%0)%)", xops
);
12035 output_asm_insn ("sw\t$0,0(%0)%)", xops
);
12040 /* Return true if X contains a kernel register. */
12043 mips_refers_to_kernel_reg_p (const_rtx x
)
12045 subrtx_iterator::array_type array
;
12046 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
12047 if (REG_P (*iter
) && KERNEL_REG_P (REGNO (*iter
)))
12052 /* Expand the "prologue" pattern. */
12055 mips_expand_prologue (void)
12057 const struct mips_frame_info
*frame
;
12058 HOST_WIDE_INT size
;
12059 unsigned int nargs
;
12061 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
12063 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
12064 or implicitly. If so, we can commit to using a global pointer
12065 straight away, otherwise we need to defer the decision. */
12066 if (mips_cfun_has_inflexible_gp_ref_p ()
12067 || mips_cfun_has_flexible_gp_ref_p ())
12069 cfun
->machine
->must_initialize_gp_p
= true;
12070 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
12073 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
12076 frame
= &cfun
->machine
->frame
;
12077 size
= frame
->total_size
;
12079 if (flag_stack_usage_info
)
12080 current_function_static_stack_size
= size
;
12082 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
12083 || flag_stack_clash_protection
)
12085 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
12087 if (size
> PROBE_INTERVAL
&& size
> get_stack_check_protect ())
12088 mips_emit_probe_stack_range (get_stack_check_protect (),
12089 size
- get_stack_check_protect ());
12092 mips_emit_probe_stack_range (get_stack_check_protect (), size
);
12095 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
12096 bytes beforehand; this is enough to cover the register save area
12097 without going out of range. */
12098 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
12099 || frame
->num_cop0_regs
> 0)
12101 HOST_WIDE_INT step1
;
12103 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
12104 if (GENERATE_MIPS16E_SAVE_RESTORE
)
12106 HOST_WIDE_INT offset
;
12107 unsigned int mask
, regno
;
12109 /* Try to merge argument stores into the save instruction. */
12110 nargs
= mips16e_collect_argument_saves ();
12112 /* Build the save instruction. */
12113 mask
= frame
->mask
;
12114 rtx insn
= mips16e_build_save_restore (false, &mask
, &offset
,
12116 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12117 mips_frame_barrier ();
12120 /* Check if we need to save other registers. */
12121 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
12122 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
12124 offset
-= UNITS_PER_WORD
;
12125 mips_save_restore_reg (word_mode
, regno
,
12126 offset
, mips_save_reg
);
12131 if (cfun
->machine
->interrupt_handler_p
)
12133 HOST_WIDE_INT offset
;
12136 /* If this interrupt is using a shadow register set, we need to
12137 get the stack pointer from the previous register set. */
12138 if (cfun
->machine
->use_shadow_register_set
== SHADOW_SET_YES
)
12139 emit_insn (PMODE_INSN (gen_mips_rdpgpr
, (stack_pointer_rtx
,
12140 stack_pointer_rtx
)));
12142 if (!cfun
->machine
->keep_interrupts_masked_p
)
12144 if (cfun
->machine
->int_mask
== INT_MASK_EIC
)
12145 /* Move from COP0 Cause to K0. */
12146 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
12147 gen_rtx_REG (SImode
, COP0_CAUSE_REG_NUM
)));
12149 /* Move from COP0 EPC to K1. */
12150 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
12151 gen_rtx_REG (SImode
,
12152 COP0_EPC_REG_NUM
)));
12154 /* Allocate the first part of the frame. */
12155 rtx insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
12157 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12158 mips_frame_barrier ();
12161 /* Start at the uppermost location for saving. */
12162 offset
= frame
->cop0_sp_offset
- size
;
12164 /* Push EPC into its stack slot. */
12165 mem
= gen_frame_mem (word_mode
,
12166 plus_constant (Pmode
, stack_pointer_rtx
,
12168 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
12169 offset
-= UNITS_PER_WORD
;
12171 /* Move from COP0 Status to K1. */
12172 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
12173 gen_rtx_REG (SImode
,
12174 COP0_STATUS_REG_NUM
)));
12176 /* Right justify the RIPL in k0. */
12177 if (!cfun
->machine
->keep_interrupts_masked_p
12178 && cfun
->machine
->int_mask
== INT_MASK_EIC
)
12179 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
12180 gen_rtx_REG (SImode
, K0_REG_NUM
),
12181 GEN_INT (CAUSE_IPL
)));
12183 /* Push Status into its stack slot. */
12184 mem
= gen_frame_mem (word_mode
,
12185 plus_constant (Pmode
, stack_pointer_rtx
,
12187 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
12188 offset
-= UNITS_PER_WORD
;
12190 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
12191 if (!cfun
->machine
->keep_interrupts_masked_p
12192 && cfun
->machine
->int_mask
== INT_MASK_EIC
)
12193 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12196 gen_rtx_REG (SImode
, K0_REG_NUM
)));
12198 /* Clear all interrupt mask bits up to and including the
12199 handler's interrupt line. */
12200 if (!cfun
->machine
->keep_interrupts_masked_p
12201 && cfun
->machine
->int_mask
!= INT_MASK_EIC
)
12202 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12203 GEN_INT (cfun
->machine
->int_mask
+ 1),
12205 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12207 if (!cfun
->machine
->keep_interrupts_masked_p
)
12208 /* Enable interrupts by clearing the KSU ERL and EXL bits.
12209 IE is already the correct value, so we don't have to do
12210 anything explicit. */
12211 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12214 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12216 /* Disable interrupts by clearing the KSU, ERL, EXL,
12218 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12221 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12223 if (TARGET_HARD_FLOAT
)
12224 /* Disable COP1 for hard-float. This will lead to an exception
12225 if floating-point code is executed in an ISR. */
12226 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
12229 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
12235 rtx insn
= gen_add3_insn (stack_pointer_rtx
,
12238 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12239 mips_frame_barrier ();
12243 mips_for_each_saved_acc (size
, mips_save_reg
);
12244 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
12248 /* Allocate the rest of the frame. */
12251 if (SMALL_OPERAND (-size
))
12252 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
12254 GEN_INT (-size
)))) = 1;
12257 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
12260 /* There are no instructions to add or subtract registers
12261 from the stack pointer, so use the frame pointer as a
12262 temporary. We should always be using a frame pointer
12263 in this case anyway. */
12264 gcc_assert (frame_pointer_needed
);
12265 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12266 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
12267 hard_frame_pointer_rtx
,
12268 MIPS_PROLOGUE_TEMP (Pmode
)));
12269 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
12272 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
12274 MIPS_PROLOGUE_TEMP (Pmode
)));
12276 /* Describe the combined effect of the previous instructions. */
12277 mips_set_frame_expr
12278 (gen_rtx_SET (stack_pointer_rtx
,
12279 plus_constant (Pmode
, stack_pointer_rtx
, -size
)));
12281 mips_frame_barrier ();
12284 /* Set up the frame pointer, if we're using one. */
12285 if (frame_pointer_needed
)
12287 HOST_WIDE_INT offset
;
12289 offset
= frame
->hard_frame_pointer_offset
;
12292 rtx insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12293 RTX_FRAME_RELATED_P (insn
) = 1;
12295 else if (SMALL_OPERAND (offset
))
12297 rtx insn
= gen_add3_insn (hard_frame_pointer_rtx
,
12298 stack_pointer_rtx
, GEN_INT (offset
));
12299 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
12303 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
12304 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
12305 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
12306 hard_frame_pointer_rtx
,
12307 MIPS_PROLOGUE_TEMP (Pmode
)));
12308 mips_set_frame_expr
12309 (gen_rtx_SET (hard_frame_pointer_rtx
,
12310 plus_constant (Pmode
, stack_pointer_rtx
, offset
)));
12314 mips_emit_loadgp ();
12316 /* Initialize the $gp save slot. */
12317 if (mips_cfun_has_cprestore_slot_p ())
12319 rtx base
, mem
, gp
, temp
;
12320 HOST_WIDE_INT offset
;
12322 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
12323 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
12324 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
12325 temp
= (SMALL_OPERAND (offset
)
12326 ? gen_rtx_SCRATCH (Pmode
)
12327 : MIPS_PROLOGUE_TEMP (Pmode
));
12328 emit_insn (PMODE_INSN (gen_potential_cprestore
,
12329 (mem
, GEN_INT (offset
), gp
, temp
)));
12331 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
12332 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, base
, offset
));
12333 emit_insn (PMODE_INSN (gen_use_cprestore
, (mem
)));
12336 /* We need to search back to the last use of K0 or K1. */
12337 if (cfun
->machine
->interrupt_handler_p
)
12340 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
12342 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
12344 /* Emit a move from K1 to COP0 Status after insn. */
12345 gcc_assert (insn
!= NULL_RTX
);
12346 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
12347 gen_rtx_REG (SImode
, K1_REG_NUM
)),
12351 /* If we are profiling, make sure no instructions are scheduled before
12352 the call to mcount. */
12354 emit_insn (gen_blockage ());
12357 /* Attach all pending register saves to the previous instruction.
12358 Return that instruction. */
12361 mips_epilogue_emit_cfa_restores (void)
12365 insn
= get_last_insn ();
12366 if (mips_epilogue
.cfa_restores
)
12368 gcc_assert (insn
&& !REG_NOTES (insn
));
12369 RTX_FRAME_RELATED_P (insn
) = 1;
12370 REG_NOTES (insn
) = mips_epilogue
.cfa_restores
;
12371 mips_epilogue
.cfa_restores
= 0;
12376 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
12377 now at REG + OFFSET. */
12380 mips_epilogue_set_cfa (rtx reg
, HOST_WIDE_INT offset
)
12384 insn
= mips_epilogue_emit_cfa_restores ();
12385 if (reg
!= mips_epilogue
.cfa_reg
|| offset
!= mips_epilogue
.cfa_offset
)
12387 RTX_FRAME_RELATED_P (insn
) = 1;
12388 REG_NOTES (insn
) = alloc_reg_note (REG_CFA_DEF_CFA
,
12389 plus_constant (Pmode
, reg
, offset
),
12391 mips_epilogue
.cfa_reg
= reg
;
12392 mips_epilogue
.cfa_offset
= offset
;
12396 /* Emit instructions to restore register REG from slot MEM. Also update
12397 the cfa_restores list. */
12400 mips_restore_reg (rtx reg
, rtx mem
)
12402 /* There's no MIPS16 instruction to load $31 directly. Load into
12403 $7 instead and adjust the return insn appropriately. */
12404 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
12405 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
12406 else if (GET_MODE (reg
) == DFmode
12407 && (!TARGET_FLOAT64
12408 || mips_abi
== ABI_32
))
12410 mips_add_cfa_restore (mips_subword (reg
, true));
12411 mips_add_cfa_restore (mips_subword (reg
, false));
12414 mips_add_cfa_restore (reg
);
12416 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
12417 if (REGNO (reg
) == REGNO (mips_epilogue
.cfa_reg
))
12418 /* The CFA is currently defined in terms of the register whose
12419 value we have just restored. Redefine the CFA in terms of
12420 the stack pointer. */
12421 mips_epilogue_set_cfa (stack_pointer_rtx
,
12422 mips_epilogue
.cfa_restore_sp_offset
);
12425 /* Emit code to set the stack pointer to BASE + OFFSET, given that
12426 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
12427 BASE, if not the stack pointer, is available as a temporary. */
12430 mips_deallocate_stack (rtx base
, rtx offset
, HOST_WIDE_INT new_frame_size
)
12432 if (base
== stack_pointer_rtx
&& offset
== const0_rtx
)
12435 mips_frame_barrier ();
12436 if (offset
== const0_rtx
)
12438 emit_move_insn (stack_pointer_rtx
, base
);
12439 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
12441 else if (TARGET_MIPS16
&& base
!= stack_pointer_rtx
)
12443 emit_insn (gen_add3_insn (base
, base
, offset
));
12444 mips_epilogue_set_cfa (base
, new_frame_size
);
12445 emit_move_insn (stack_pointer_rtx
, base
);
12449 emit_insn (gen_add3_insn (stack_pointer_rtx
, base
, offset
));
12450 mips_epilogue_set_cfa (stack_pointer_rtx
, new_frame_size
);
12454 /* Emit any instructions needed before a return. */
12457 mips_expand_before_return (void)
12459 /* When using a call-clobbered gp, we start out with unified call
12460 insns that include instructions to restore the gp. We then split
12461 these unified calls after reload. These split calls explicitly
12462 clobber gp, so there is no need to define
12463 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
12465 For consistency, we should also insert an explicit clobber of $28
12466 before return insns, so that the post-reload optimizers know that
12467 the register is not live on exit. */
12468 if (TARGET_CALL_CLOBBERED_GP
)
12469 emit_clobber (pic_offset_table_rtx
);
12472 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
12476 mips_expand_epilogue (bool sibcall_p
)
12478 const struct mips_frame_info
*frame
;
12479 HOST_WIDE_INT step1
, step2
;
12482 bool use_jraddiusp_p
= false;
12484 if (!sibcall_p
&& mips_can_use_return_insn ())
12486 emit_jump_insn (gen_return ());
12490 /* In MIPS16 mode, if the return value should go into a floating-point
12491 register, we need to call a helper routine to copy it over. */
12492 if (mips16_cfun_returns_in_fpr_p ())
12493 mips16_copy_fpr_return_value ();
12495 /* Split the frame into two. STEP1 is the amount of stack we should
12496 deallocate before restoring the registers. STEP2 is the amount we
12497 should deallocate afterwards.
12499 Start off by assuming that no registers need to be restored. */
12500 frame
= &cfun
->machine
->frame
;
12501 step1
= frame
->total_size
;
12504 /* Work out which register holds the frame address. */
12505 if (!frame_pointer_needed
)
12506 base
= stack_pointer_rtx
;
12509 base
= hard_frame_pointer_rtx
;
12510 step1
-= frame
->hard_frame_pointer_offset
;
12512 mips_epilogue
.cfa_reg
= base
;
12513 mips_epilogue
.cfa_offset
= step1
;
12514 mips_epilogue
.cfa_restores
= NULL_RTX
;
12516 /* If we need to restore registers, deallocate as much stack as
12517 possible in the second step without going out of range. */
12518 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
12519 || frame
->num_cop0_regs
> 0)
12521 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
12525 /* Get an rtx for STEP1 that we can add to BASE. */
12526 adjust
= GEN_INT (step1
);
12527 if (!SMALL_OPERAND (step1
))
12529 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
12530 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
12532 mips_deallocate_stack (base
, adjust
, step2
);
12534 /* If we're using addressing macros, $gp is implicitly used by all
12535 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
12537 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
12538 emit_insn (gen_blockage ());
12540 mips_epilogue
.cfa_restore_sp_offset
= step2
;
12541 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
12543 unsigned int regno
, mask
;
12544 HOST_WIDE_INT offset
;
12547 /* Generate the restore instruction. */
12548 mask
= frame
->mask
;
12549 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
12551 /* Restore any other registers manually. */
12552 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
12553 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
12555 offset
-= UNITS_PER_WORD
;
12556 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
12559 /* Restore the remaining registers and deallocate the final bit
12561 mips_frame_barrier ();
12562 emit_insn (restore
);
12563 mips_epilogue_set_cfa (stack_pointer_rtx
, 0);
12567 /* Restore the registers. */
12568 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
12569 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
12572 if (cfun
->machine
->interrupt_handler_p
)
12574 HOST_WIDE_INT offset
;
12577 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
12579 /* Restore the original EPC. */
12580 mem
= gen_frame_mem (word_mode
,
12581 plus_constant (Pmode
, stack_pointer_rtx
,
12583 mips_emit_move (gen_rtx_REG (word_mode
, K1_REG_NUM
), mem
);
12584 offset
-= UNITS_PER_WORD
;
12586 /* Move to COP0 EPC. */
12587 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
12588 gen_rtx_REG (SImode
, K1_REG_NUM
)));
12590 /* Restore the original Status. */
12591 mem
= gen_frame_mem (word_mode
,
12592 plus_constant (Pmode
, stack_pointer_rtx
,
12594 mips_emit_move (gen_rtx_REG (word_mode
, K1_REG_NUM
), mem
);
12595 offset
-= UNITS_PER_WORD
;
12597 /* If we don't use shadow register set, we need to update SP. */
12598 if (cfun
->machine
->use_shadow_register_set
== SHADOW_SET_NO
)
12599 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
12601 /* The choice of position is somewhat arbitrary in this case. */
12602 mips_epilogue_emit_cfa_restores ();
12604 /* Move to COP0 Status. */
12605 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
12606 gen_rtx_REG (SImode
, K1_REG_NUM
)));
12608 else if (TARGET_MICROMIPS
12609 && !crtl
->calls_eh_return
12612 && mips_unsigned_immediate_p (step2
, 5, 2))
12613 use_jraddiusp_p
= true;
12615 /* Deallocate the final bit of the frame. */
12616 mips_deallocate_stack (stack_pointer_rtx
, GEN_INT (step2
), 0);
12619 if (cfun
->machine
->use_frame_header_for_callee_saved_regs
)
12620 mips_epilogue_emit_cfa_restores ();
12621 else if (!use_jraddiusp_p
)
12622 gcc_assert (!mips_epilogue
.cfa_restores
);
12624 /* Add in the __builtin_eh_return stack adjustment. We need to
12625 use a temporary in MIPS16 code. */
12626 if (crtl
->calls_eh_return
)
12630 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
12631 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
12632 MIPS_EPILOGUE_TEMP (Pmode
),
12633 EH_RETURN_STACKADJ_RTX
));
12634 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
12637 emit_insn (gen_add3_insn (stack_pointer_rtx
,
12639 EH_RETURN_STACKADJ_RTX
));
12644 mips_expand_before_return ();
12645 if (cfun
->machine
->interrupt_handler_p
)
12647 /* Interrupt handlers generate eret or deret. */
12648 if (cfun
->machine
->use_debug_exception_return_p
)
12649 emit_jump_insn (gen_mips_deret ());
12651 emit_jump_insn (gen_mips_eret ());
12657 /* When generating MIPS16 code, the normal
12658 mips_for_each_saved_gpr_and_fpr path will restore the return
12659 address into $7 rather than $31. */
12661 && !GENERATE_MIPS16E_SAVE_RESTORE
12662 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
12664 /* simple_returns cannot rely on values that are only available
12665 on paths through the epilogue (because return paths that do
12666 not pass through the epilogue may nevertheless reuse a
12667 simple_return that occurs at the end of the epilogue).
12668 Use a normal return here instead. */
12669 rtx reg
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 7);
12670 pat
= gen_return_internal (reg
);
12672 else if (use_jraddiusp_p
)
12673 pat
= gen_jraddiusp (GEN_INT (step2
));
12676 rtx reg
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
12677 pat
= gen_simple_return_internal (reg
);
12679 emit_jump_insn (pat
);
12680 if (use_jraddiusp_p
)
12681 mips_epilogue_set_cfa (stack_pointer_rtx
, step2
);
12685 /* Search from the beginning to the first use of K0 or K1. */
12686 if (cfun
->machine
->interrupt_handler_p
12687 && !cfun
->machine
->keep_interrupts_masked_p
)
12689 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
12691 && mips_refers_to_kernel_reg_p (PATTERN (insn
)))
12693 gcc_assert (insn
!= NULL_RTX
);
12694 /* Insert disable interrupts before the first use of K0 or K1. */
12695 emit_insn_before (gen_mips_di (), insn
);
12696 emit_insn_before (gen_mips_ehb (), insn
);
12700 /* Return nonzero if this function is known to have a null epilogue.
12701 This allows the optimizer to omit jumps to jumps if no stack
12705 mips_can_use_return_insn (void)
12707 /* Interrupt handlers need to go through the epilogue. */
12708 if (cfun
->machine
->interrupt_handler_p
)
12711 if (!reload_completed
)
12717 /* In MIPS16 mode, a function that returns a floating-point value
12718 needs to arrange to copy the return value into the floating-point
12720 if (mips16_cfun_returns_in_fpr_p ())
12723 return (cfun
->machine
->frame
.total_size
== 0
12724 && !cfun
->machine
->use_frame_header_for_callee_saved_regs
);
12727 /* Return true if register REGNO can store a value of mode MODE.
12728 The result of this function is cached in mips_hard_regno_mode_ok. */
12731 mips_hard_regno_mode_ok_uncached (unsigned int regno
, machine_mode mode
)
12734 enum mode_class mclass
;
12736 if (mode
== CCV2mode
)
12737 return (ISA_HAS_8CC
12738 && ST_REG_P (regno
)
12739 && (regno
- ST_REG_FIRST
) % 2 == 0);
12741 if (mode
== CCV4mode
)
12742 return (ISA_HAS_8CC
12743 && ST_REG_P (regno
)
12744 && (regno
- ST_REG_FIRST
) % 4 == 0);
12746 if (mode
== CCmode
)
12747 return ISA_HAS_8CC
? ST_REG_P (regno
) : regno
== FPSW_REGNUM
;
12749 size
= GET_MODE_SIZE (mode
);
12750 mclass
= GET_MODE_CLASS (mode
);
12752 if (GP_REG_P (regno
) && mode
!= CCFmode
&& !MSA_SUPPORTED_MODE_P (mode
))
12753 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
12755 /* For MSA, allow TImode and 128-bit vector modes in all FPR. */
12756 if (FP_REG_P (regno
) && MSA_SUPPORTED_MODE_P (mode
))
12759 if (FP_REG_P (regno
)
12760 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
12761 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
12763 /* Deny use of odd-numbered registers for 32-bit data for
12764 the o32 FP64A ABI. */
12765 if (TARGET_O32_FP64A_ABI
&& size
<= 4 && (regno
& 1) != 0)
12768 /* The FPXX ABI requires double-precision values to be placed in
12769 even-numbered registers. Disallow odd-numbered registers with
12770 CCFmode because CCFmode double-precision compares will write a
12771 64-bit value to a register. */
12772 if (mode
== CCFmode
)
12773 return !(TARGET_FLOATXX
&& (regno
& 1) != 0);
12775 /* Allow 64-bit vector modes for Loongson-2E/2F. */
12776 if (TARGET_LOONGSON_VECTORS
12777 && (mode
== V2SImode
12778 || mode
== V4HImode
12779 || mode
== V8QImode
12780 || mode
== DImode
))
12783 if (mclass
== MODE_FLOAT
12784 || mclass
== MODE_COMPLEX_FLOAT
12785 || mclass
== MODE_VECTOR_FLOAT
)
12786 return size
<= UNITS_PER_FPVALUE
;
12788 /* Allow integer modes that fit into a single register. We need
12789 to put integers into FPRs when using instructions like CVT
12790 and TRUNC. There's no point allowing sizes smaller than a word,
12791 because the FPU has no appropriate load/store instructions. */
12792 if (mclass
== MODE_INT
)
12793 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
12796 /* Don't allow vector modes in accumulators. */
12797 if (ACC_REG_P (regno
)
12798 && !VECTOR_MODE_P (mode
)
12799 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
12801 if (MD_REG_P (regno
))
12803 /* After a multiplication or division, clobbering HI makes
12804 the value of LO unpredictable, and vice versa. This means
12805 that, for all interesting cases, HI and LO are effectively
12808 We model this by requiring that any value that uses HI
12810 if (size
<= UNITS_PER_WORD
* 2)
12811 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
12815 /* DSP accumulators do not have the same restrictions as
12816 HI and LO, so we can treat them as normal doubleword
12818 if (size
<= UNITS_PER_WORD
)
12821 if (size
<= UNITS_PER_WORD
* 2
12822 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
12827 if (ALL_COP_REG_P (regno
))
12828 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
12830 if (regno
== GOT_VERSION_REGNUM
)
12831 return mode
== SImode
;
12836 /* Implement TARGET_HARD_REGNO_MODE_OK. */
12839 mips_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
12841 return mips_hard_regno_mode_ok_p
[mode
][regno
];
12844 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
12847 mips_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
12848 unsigned int new_reg
)
12850 /* Interrupt functions can only use registers that have already been
12851 saved by the prologue, even if they would normally be call-clobbered. */
12852 if (cfun
->machine
->interrupt_handler_p
&& !df_regs_ever_live_p (new_reg
))
12858 /* Return nonzero if register REGNO can be used as a scratch register
12862 mips_hard_regno_scratch_ok (unsigned int regno
)
12864 /* See mips_hard_regno_rename_ok. */
12865 if (cfun
->machine
->interrupt_handler_p
&& !df_regs_ever_live_p (regno
))
12871 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. Odd-numbered
12872 single-precision registers are not considered callee-saved for o32
12873 FPXX as they will be clobbered when run on an FR=1 FPU. MSA vector
12874 registers with MODE > 64 bits are part clobbered too. */
12877 mips_hard_regno_call_part_clobbered (unsigned int regno
, machine_mode mode
)
12880 && hard_regno_nregs (regno
, mode
) == 1
12881 && FP_REG_P (regno
)
12882 && (regno
& 1) != 0)
12885 if (ISA_HAS_MSA
&& FP_REG_P (regno
) && GET_MODE_SIZE (mode
) > 8)
12891 /* Implement TARGET_HARD_REGNO_NREGS. */
12893 static unsigned int
12894 mips_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
12896 if (ST_REG_P (regno
))
12897 /* The size of FP status registers is always 4, because they only hold
12898 CCmode values, and CCmode is always considered to be 4 bytes wide. */
12899 return (GET_MODE_SIZE (mode
) + 3) / 4;
12901 if (FP_REG_P (regno
))
12903 if (MSA_SUPPORTED_MODE_P (mode
))
12906 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
12909 /* All other registers are word-sized. */
12910 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
12913 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
12914 in mips_hard_regno_nregs. */
12917 mips_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
12923 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
12924 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
12926 if (mips_hard_regno_mode_ok (ST_REG_FIRST
, mode
))
12927 size
= MIN (size
, 4);
12929 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
12931 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
12933 if (mips_hard_regno_mode_ok (FP_REG_FIRST
, mode
))
12935 if (MSA_SUPPORTED_MODE_P (mode
))
12936 size
= MIN (size
, UNITS_PER_MSA_REG
);
12938 size
= MIN (size
, UNITS_PER_FPREG
);
12941 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
12943 if (!hard_reg_set_empty_p (left
))
12944 size
= MIN (size
, UNITS_PER_WORD
);
12945 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
12948 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
12951 mips_can_change_mode_class (machine_mode from
,
12952 machine_mode to
, reg_class_t rclass
)
12954 /* Allow conversions between different Loongson integer vectors,
12955 and between those vectors and DImode. */
12956 if (GET_MODE_SIZE (from
) == 8 && GET_MODE_SIZE (to
) == 8
12957 && INTEGRAL_MODE_P (from
) && INTEGRAL_MODE_P (to
))
12960 /* Allow conversions between different MSA vector modes. */
12961 if (MSA_SUPPORTED_MODE_P (from
) && MSA_SUPPORTED_MODE_P (to
))
12964 /* Otherwise, there are several problems with changing the modes of
12965 values in floating-point registers:
12967 - When a multi-word value is stored in paired floating-point
12968 registers, the first register always holds the low word. We
12969 therefore can't allow FPRs to change between single-word and
12970 multi-word modes on big-endian targets.
12972 - GCC assumes that each word of a multiword register can be
12973 accessed individually using SUBREGs. This is not true for
12974 floating-point registers if they are bigger than a word.
12976 - Loading a 32-bit value into a 64-bit floating-point register
12977 will not sign-extend the value, despite what LOAD_EXTEND_OP
12978 says. We can't allow FPRs to change from SImode to a wider
12979 mode on 64-bit targets.
12981 - If the FPU has already interpreted a value in one format, we
12982 must not ask it to treat the value as having a different
12985 We therefore disallow all mode changes involving FPRs. */
12987 return !reg_classes_intersect_p (FP_REGS
, rclass
);
12990 /* Implement target hook small_register_classes_for_mode_p. */
12993 mips_small_register_classes_for_mode_p (machine_mode mode
12996 return TARGET_MIPS16
;
12999 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction,
13000 or use the MSA's move.v instruction. */
13003 mips_mode_ok_for_mov_fmt_p (machine_mode mode
)
13009 return TARGET_HARD_FLOAT
;
13012 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
13015 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
13018 return MSA_SUPPORTED_MODE_P (mode
);
13022 /* Implement TARGET_MODES_TIEABLE_P. */
13025 mips_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
13027 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
13028 prefer to put one of them in FPRs. */
13029 return (mode1
== mode2
13030 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
13031 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
13034 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
13037 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
13039 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
13042 if (reg_class_subset_p (FP_REGS
, rclass
)
13043 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
13046 if (reg_class_subset_p (GR_REGS
, rclass
))
13049 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
13055 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
13056 Return a "canonical" class to represent it in later calculations. */
13059 mips_canonicalize_move_class (reg_class_t rclass
)
13061 /* All moves involving accumulator registers have the same cost. */
13062 if (reg_class_subset_p (rclass
, ACC_REGS
))
13065 /* Likewise promote subclasses of general registers to the most
13066 interesting containing class. */
13067 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
13069 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
13070 rclass
= GENERAL_REGS
;
13075 /* Return the cost of moving a value from a register of class FROM to a GPR.
13076 Return 0 for classes that are unions of other classes handled by this
13080 mips_move_to_gpr_cost (reg_class_t from
)
13086 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
13090 /* MFLO and MFHI. */
13100 /* This choice of value is historical. */
13108 /* Return the cost of moving a value from a GPR to a register of class TO.
13109 Return 0 for classes that are unions of other classes handled by this
13113 mips_move_from_gpr_cost (reg_class_t to
)
13119 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
13123 /* MTLO and MTHI. */
13133 /* This choice of value is historical. */
13141 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
13142 maximum of the move costs for subclasses; regclass will work out
13143 the maximum for us. */
13146 mips_register_move_cost (machine_mode mode
,
13147 reg_class_t from
, reg_class_t to
)
13152 from
= mips_canonicalize_move_class (from
);
13153 to
= mips_canonicalize_move_class (to
);
13155 /* Handle moves that can be done without using general-purpose registers. */
13156 if (from
== FP_REGS
)
13158 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
13163 /* Handle cases in which only one class deviates from the ideal. */
13164 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
13166 return mips_move_from_gpr_cost (to
);
13168 return mips_move_to_gpr_cost (from
);
13170 /* Handles cases that require a GPR temporary. */
13171 cost1
= mips_move_to_gpr_cost (from
);
13174 cost2
= mips_move_from_gpr_cost (to
);
13176 return cost1
+ cost2
;
13182 /* Implement TARGET_REGISTER_PRIORITY. */
13185 mips_register_priority (int hard_regno
)
13187 /* Treat MIPS16 registers with higher priority than other regs. */
13189 && TEST_HARD_REG_BIT (reg_class_contents
[M16_REGS
], hard_regno
))
13194 /* Implement TARGET_MEMORY_MOVE_COST. */
13197 mips_memory_move_cost (machine_mode mode
, reg_class_t rclass
, bool in
)
13199 return (mips_cost
->memory_latency
13200 + memory_move_secondary_cost (mode
, rclass
, in
));
13203 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
13205 When targeting the o32 FPXX ABI, all moves with a length of doubleword
13206 or greater must be performed by FR-mode-aware instructions.
13207 This can be achieved using MFHC1/MTHC1 when these instructions are
13208 available but otherwise moves must go via memory.
13209 For the o32 FP64A ABI, all odd-numbered moves with a length of
13210 doubleword or greater are required to use memory. Using MTC1/MFC1
13211 to access the lower-half of these registers would require a forbidden
13212 single-precision access. We require all double-word moves to use
13213 memory because adding even and odd floating-point registers classes
13214 would have a significant impact on the backend. */
13217 mips_secondary_memory_needed (machine_mode mode
, reg_class_t class1
,
13218 reg_class_t class2
)
13220 /* Ignore spilled pseudos. */
13221 if (lra_in_progress
&& (class1
== NO_REGS
|| class2
== NO_REGS
))
13224 if (((class1
== FP_REGS
) != (class2
== FP_REGS
))
13225 && ((TARGET_FLOATXX
&& !ISA_HAS_MXHC1
)
13226 || TARGET_O32_FP64A_ABI
)
13227 && GET_MODE_SIZE (mode
) >= 8)
13233 /* Return the register class required for a secondary register when
13234 copying between one of the registers in RCLASS and value X, which
13235 has mode MODE. X is the source of the move if IN_P, otherwise it
13236 is the destination. Return NO_REGS if no secondary register is
13240 mips_secondary_reload_class (enum reg_class rclass
,
13241 machine_mode mode
, rtx x
, bool)
13245 /* If X is a constant that cannot be loaded into $25, it must be loaded
13246 into some other GPR. No other register class allows a direct move. */
13247 if (mips_dangerous_for_la25_p (x
))
13248 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
13250 regno
= true_regnum (x
);
13253 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
13254 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
13260 /* Copying from accumulator registers to anywhere other than a general
13261 register requires a temporary general register. */
13262 if (reg_class_subset_p (rclass
, ACC_REGS
))
13263 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
13264 if (ACC_REG_P (regno
))
13265 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
13267 if (reg_class_subset_p (rclass
, FP_REGS
))
13271 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)))
13272 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
13273 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
13276 if (MEM_P (x
) && MSA_SUPPORTED_MODE_P (mode
))
13277 /* In this case we can use MSA LD.* and ST.*. */
13280 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
13281 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
13284 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (mode
, x
))
13285 /* We can force the constant to memory and use lwc1
13286 and ldc1. As above, we will use pairs of lwc1s if
13287 ldc1 is not supported. */
13290 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
13291 /* In this case we can use mov.fmt. */
13294 /* Otherwise, we need to reload through an integer register. */
13297 if (FP_REG_P (regno
))
13298 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
13303 /* Implement TARGET_MODE_REP_EXTENDED. */
13306 mips_mode_rep_extended (scalar_int_mode mode
, scalar_int_mode mode_rep
)
13308 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
13309 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
13310 return SIGN_EXTEND
;
13315 /* Implement TARGET_VALID_POINTER_MODE. */
13318 mips_valid_pointer_mode (scalar_int_mode mode
)
13320 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
13323 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
13326 mips_vector_mode_supported_p (machine_mode mode
)
13331 return TARGET_PAIRED_SINGLE_FLOAT
;
13346 return TARGET_LOONGSON_VECTORS
;
13349 return MSA_SUPPORTED_MODE_P (mode
);
13353 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
13356 mips_scalar_mode_supported_p (scalar_mode mode
)
13358 if (ALL_FIXED_POINT_MODE_P (mode
)
13359 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
13362 return default_scalar_mode_supported_p (mode
);
13365 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
13367 static machine_mode
13368 mips_preferred_simd_mode (scalar_mode mode
)
13370 if (TARGET_PAIRED_SINGLE_FLOAT
13400 /* Implement TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES. */
13402 static unsigned int
13403 mips_autovectorize_vector_sizes (void)
13405 return ISA_HAS_MSA
? 16 : 0;
13408 /* Implement TARGET_INIT_LIBFUNCS. */
13411 mips_init_libfuncs (void)
13413 if (TARGET_FIX_VR4120
)
13415 /* Register the special divsi3 and modsi3 functions needed to work
13416 around VR4120 division errata. */
13417 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
13418 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
13421 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
13423 /* Register the MIPS16 -mhard-float stubs. */
13424 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
13425 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
13426 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
13427 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
13429 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
13430 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
13431 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
13432 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
13433 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
13434 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
13435 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
13437 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
13438 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
13439 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
13441 if (TARGET_DOUBLE_FLOAT
)
13443 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
13444 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
13445 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
13446 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
13448 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
13449 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
13450 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
13451 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
13452 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
13453 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
13454 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
13456 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
13457 "__mips16_extendsfdf2");
13458 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
13459 "__mips16_truncdfsf2");
13460 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
13461 "__mips16_fix_truncdfsi");
13462 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
13463 "__mips16_floatsidf");
13464 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
13465 "__mips16_floatunsidf");
13469 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
13470 on an external non-MIPS16 routine to implement __sync_synchronize.
13471 Similarly for the rest of the ll/sc libfuncs. */
13474 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
13475 init_sync_libfuncs (UNITS_PER_WORD
);
13479 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
13482 mips_process_load_label (rtx target
)
13484 rtx base
, gp
, intop
;
13485 HOST_WIDE_INT offset
;
13487 mips_multi_start ();
13491 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
13492 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
13496 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
13497 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
13501 gp
= pic_offset_table_rtx
;
13502 if (mips_cfun_has_cprestore_slot_p ())
13504 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
13505 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
13506 if (!SMALL_OPERAND (offset
))
13508 intop
= GEN_INT (CONST_HIGH_PART (offset
));
13509 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
13510 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
13513 offset
= CONST_LOW_PART (offset
);
13515 intop
= GEN_INT (offset
);
13516 if (ISA_HAS_LOAD_DELAY
)
13517 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
13519 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
13521 if (ISA_HAS_LOAD_DELAY
)
13522 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
13524 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
13525 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
13530 /* Return the number of instructions needed to load a label into $AT. */
13532 static unsigned int
13533 mips_load_label_num_insns (void)
13535 if (cfun
->machine
->load_label_num_insns
== 0)
13537 mips_process_load_label (pc_rtx
);
13538 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
13540 return cfun
->machine
->load_label_num_insns
;
13543 /* Emit an asm sequence to start a noat block and load the address
13544 of a label into $1. */
13547 mips_output_load_label (rtx target
)
13549 mips_push_asm_switch (&mips_noat
);
13550 if (TARGET_EXPLICIT_RELOCS
)
13552 mips_process_load_label (target
);
13553 mips_multi_write ();
13557 if (Pmode
== DImode
)
13558 output_asm_insn ("dla\t%@,%0", &target
);
13560 output_asm_insn ("la\t%@,%0", &target
);
13564 /* Return the length of INSN. LENGTH is the initial length computed by
13565 attributes in the machine-description file. */
13568 mips_adjust_insn_length (rtx_insn
*insn
, int length
)
13570 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
13571 of a PIC long-branch sequence. Substitute the correct value. */
13572 if (length
== MAX_PIC_BRANCH_LENGTH
13574 && INSN_CODE (insn
) >= 0
13575 && get_attr_type (insn
) == TYPE_BRANCH
)
13577 /* Add the branch-over instruction and its delay slot, if this
13578 is a conditional branch. */
13579 length
= simplejump_p (insn
) ? 0 : 8;
13581 /* Add the size of a load into $AT. */
13582 length
+= BASE_INSN_LENGTH
* mips_load_label_num_insns ();
13584 /* Add the length of an indirect jump, ignoring the delay slot. */
13585 length
+= TARGET_COMPRESSION
? 2 : 4;
13588 /* A unconditional jump has an unfilled delay slot if it is not part
13589 of a sequence. A conditional jump normally has a delay slot, but
13590 does not on MIPS16. */
13591 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
13592 length
+= TARGET_MIPS16
? 2 : 4;
13594 /* See how many nops might be needed to avoid hardware hazards. */
13595 if (!cfun
->machine
->ignore_hazard_length_p
13597 && INSN_CODE (insn
) >= 0)
13598 switch (get_attr_hazard (insn
))
13604 case HAZARD_FORBIDDEN_SLOT
:
13605 length
+= NOP_INSN_LENGTH
;
13609 length
+= NOP_INSN_LENGTH
* 2;
13616 /* Return the asm template for a call. OPERANDS are the operands, TARGET_OPNO
13617 is the operand number of the target. SIZE_OPNO is the operand number of
13618 the argument size operand that can optionally hold the call attributes. If
13619 SIZE_OPNO is not -1 and the call is indirect, use the function symbol from
13620 the call attributes to attach a R_MIPS_JALR relocation to the call. LINK_P
13621 indicates whether the jump is a call and needs to set the link register.
13623 When generating GOT code without explicit relocation operators, all calls
13624 should use assembly macros. Otherwise, all indirect calls should use "jr"
13625 or "jalr"; we will arrange to restore $gp afterwards if necessary. Finally,
13626 we can only generate direct calls for -mabicalls by temporarily switching
13629 For microMIPS jal(r), we try to generate jal(r)s when a 16-bit
13630 instruction is in the delay slot of jal(r).
13632 Where compact branches are available, we try to use them if the delay slot
13633 has a NOP (or equivalently delay slots were not enabled for the instruction
13637 mips_output_jump (rtx
*operands
, int target_opno
, int size_opno
, bool link_p
)
13639 static char buffer
[300];
13641 bool reg_p
= REG_P (operands
[target_opno
]);
13643 const char *and_link
= link_p
? "al" : "";
13644 const char *reg
= reg_p
? "r" : "";
13645 const char *compact
= "";
13646 const char *nop
= "%/";
13647 const char *short_delay
= link_p
? "%!" : "";
13648 const char *insn_name
= TARGET_CB_NEVER
|| reg_p
? "j" : "b";
13650 /* Compact branches can only be described when the ISA has support for them
13651 as both the compact formatter '%:' and the delay slot NOP formatter '%/'
13652 work as a mutually exclusive pair. I.e. a NOP is never required if a
13653 compact form is available. */
13654 if (!final_sequence
13655 && (TARGET_CB_MAYBE
13656 || (ISA_HAS_JRC
&& !link_p
&& reg_p
)))
13662 if (TARGET_USE_GOT
&& !TARGET_EXPLICIT_RELOCS
)
13663 sprintf (s
, "%%*%s%s\t%%%d%%/", insn_name
, and_link
, target_opno
);
13666 if (!reg_p
&& TARGET_ABICALLS_PIC2
)
13667 s
+= sprintf (s
, ".option\tpic0\n\t");
13669 if (reg_p
&& mips_get_pic_call_symbol (operands
, size_opno
))
13670 s
+= sprintf (s
, "%%*.reloc\t1f,%s,%%%d\n1:\t",
13671 TARGET_MICROMIPS
? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
13674 s
+= sprintf (s
, "%%*");
13676 s
+= sprintf (s
, "%s%s%s%s%s\t%%%d%s",
13677 insn_name
, and_link
, reg
, compact
, short_delay
,
13680 if (!reg_p
&& TARGET_ABICALLS_PIC2
)
13681 s
+= sprintf (s
, "\n\t.option\tpic2");
13686 /* Return the assembly code for INSN, which has the operands given by
13687 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
13688 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
13689 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
13690 version of BRANCH_IF_TRUE. */
13693 mips_output_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
13694 const char *branch_if_true
,
13695 const char *branch_if_false
)
13697 unsigned int length
;
13700 gcc_assert (LABEL_P (operands
[0]));
13702 length
= get_attr_length (insn
);
13705 /* Just a simple conditional branch. */
13706 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
13707 return branch_if_true
;
13710 /* Generate a reversed branch around a direct jump. This fallback does
13711 not use branch-likely instructions. */
13712 mips_branch_likely
= false;
13713 rtx_code_label
*not_taken
= gen_label_rtx ();
13714 taken
= operands
[0];
13716 /* Generate the reversed branch to NOT_TAKEN. */
13717 operands
[0] = not_taken
;
13718 output_asm_insn (branch_if_false
, operands
);
13720 /* If INSN has a delay slot, we must provide delay slots for both the
13721 branch to NOT_TAKEN and the conditional jump. We must also ensure
13722 that INSN's delay slot is executed in the appropriate cases. */
13723 if (final_sequence
)
13725 /* This first delay slot will always be executed, so use INSN's
13726 delay slot if is not annulled. */
13727 if (!INSN_ANNULLED_BRANCH_P (insn
))
13729 final_scan_insn (final_sequence
->insn (1),
13730 asm_out_file
, optimize
, 1, NULL
);
13731 final_sequence
->insn (1)->set_deleted ();
13734 output_asm_insn ("nop", 0);
13735 fprintf (asm_out_file
, "\n");
13738 /* Output the unconditional branch to TAKEN. */
13739 if (TARGET_ABSOLUTE_JUMPS
&& TARGET_CB_MAYBE
)
13741 /* Add a hazard nop. */
13742 if (!final_sequence
)
13744 output_asm_insn ("nop\t\t# hazard nop", 0);
13745 fprintf (asm_out_file
, "\n");
13747 output_asm_insn (MIPS_ABSOLUTE_JUMP ("bc\t%0"), &taken
);
13749 else if (TARGET_ABSOLUTE_JUMPS
)
13750 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
13753 mips_output_load_label (taken
);
13754 if (TARGET_CB_MAYBE
)
13755 output_asm_insn ("jrc\t%@%]", 0);
13757 output_asm_insn ("jr\t%@%]%/", 0);
13760 /* Now deal with its delay slot; see above. */
13761 if (final_sequence
)
13763 /* This delay slot will only be executed if the branch is taken.
13764 Use INSN's delay slot if is annulled. */
13765 if (INSN_ANNULLED_BRANCH_P (insn
))
13767 final_scan_insn (final_sequence
->insn (1),
13768 asm_out_file
, optimize
, 1, NULL
);
13769 final_sequence
->insn (1)->set_deleted ();
13771 else if (TARGET_CB_NEVER
)
13772 output_asm_insn ("nop", 0);
13773 fprintf (asm_out_file
, "\n");
13776 /* Output NOT_TAKEN. */
13777 targetm
.asm_out
.internal_label (asm_out_file
, "L",
13778 CODE_LABEL_NUMBER (not_taken
));
13782 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13783 if some equality condition is true. The condition is given by
13784 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13785 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13786 OPERANDS[3] is the second operand and may be zero or a register. */
13789 mips_output_equal_conditional_branch (rtx_insn
* insn
, rtx
*operands
,
13792 const char *branch
[2];
13793 /* For a simple BNEZ or BEQZ microMIPSr3 branch. */
13794 if (TARGET_MICROMIPS
13795 && mips_isa_rev
<= 5
13796 && operands
[3] == const0_rtx
13797 && get_attr_length (insn
) <= 8)
13799 if (mips_cb
== MIPS_CB_OPTIMAL
)
13801 branch
[!inverted_p
] = "%*b%C1z%:\t%2,%0";
13802 branch
[inverted_p
] = "%*b%N1z%:\t%2,%0";
13806 branch
[!inverted_p
] = "%*b%C1z\t%2,%0%/";
13807 branch
[inverted_p
] = "%*b%N1z\t%2,%0%/";
13810 else if (TARGET_CB_MAYBE
)
13812 if (operands
[3] == const0_rtx
)
13814 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13815 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13817 else if (REGNO (operands
[2]) != REGNO (operands
[3]))
13819 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13820 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13824 /* This case is degenerate. It should not happen, but does. */
13825 if (GET_CODE (operands
[1]) == NE
)
13826 inverted_p
= !inverted_p
;
13828 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13829 branch
[inverted_p
] = "%*\t\t# branch never";
13834 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1", "%2,%z3,%0");
13835 branch
[inverted_p
] = MIPS_BRANCH ("b%N1", "%2,%z3,%0");
13838 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
13841 /* Return the assembly code for INSN, which branches to OPERANDS[0]
13842 if some ordering condition is true. The condition is given by
13843 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
13844 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
13845 OPERANDS[3] is the second operand and may be zero or a register. */
13848 mips_output_order_conditional_branch (rtx_insn
*insn
, rtx
*operands
,
13851 const char *branch
[2];
13853 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
13854 Make BRANCH[0] branch on the inverse condition. */
13855 if (operands
[3] != const0_rtx
)
13857 /* Handle degenerate cases that should not, but do, occur. */
13858 if (REGNO (operands
[2]) == REGNO (operands
[3]))
13860 switch (GET_CODE (operands
[1]))
13864 inverted_p
= !inverted_p
;
13865 /* Fall through. */
13868 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13869 branch
[inverted_p
] = "%*\t\t# branch never";
13872 gcc_unreachable ();
13877 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1", "%2,%3,%0");
13878 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1", "%2,%3,%0");
13883 switch (GET_CODE (operands
[1]))
13885 /* These cases are equivalent to comparisons against zero. */
13887 inverted_p
= !inverted_p
;
13888 /* Fall through. */
13890 if (TARGET_CB_MAYBE
)
13892 branch
[!inverted_p
] = MIPS_BRANCH_C ("bnez", "%2,%0");
13893 branch
[inverted_p
] = MIPS_BRANCH_C ("beqz", "%2,%0");
13897 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
13898 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
13902 /* These cases are always true or always false. */
13904 inverted_p
= !inverted_p
;
13905 /* Fall through. */
13907 if (TARGET_CB_MAYBE
)
13909 branch
[!inverted_p
] = MIPS_BRANCH_C ("b", "%0");
13910 branch
[inverted_p
] = "%*\t\t# branch never";
13914 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
13915 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
13920 if (TARGET_CB_MAYBE
)
13922 branch
[!inverted_p
] = MIPS_BRANCH_C ("b%C1z", "%2,%0");
13923 branch
[inverted_p
] = MIPS_BRANCH_C ("b%N1z", "%2,%0");
13927 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
13928 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
13933 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
13936 /* Start a block of code that needs access to the LL, SC and SYNC
13940 mips_start_ll_sc_sync_block (void)
13942 if (!ISA_HAS_LL_SC
)
13944 output_asm_insn (".set\tpush", 0);
13946 output_asm_insn (".set\tmips3", 0);
13948 output_asm_insn (".set\tmips2", 0);
13952 /* End a block started by mips_start_ll_sc_sync_block. */
13955 mips_end_ll_sc_sync_block (void)
13957 if (!ISA_HAS_LL_SC
)
13958 output_asm_insn (".set\tpop", 0);
13961 /* Output and/or return the asm template for a sync instruction. */
13964 mips_output_sync (void)
13966 mips_start_ll_sc_sync_block ();
13967 output_asm_insn ("sync", 0);
13968 mips_end_ll_sc_sync_block ();
13972 /* Return the asm template associated with sync_insn1 value TYPE.
13973 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
13975 static const char *
13976 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
13980 case SYNC_INSN1_MOVE
:
13981 return "move\t%0,%z2";
13982 case SYNC_INSN1_LI
:
13983 return "li\t%0,%2";
13984 case SYNC_INSN1_ADDU
:
13985 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
13986 case SYNC_INSN1_ADDIU
:
13987 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
13988 case SYNC_INSN1_SUBU
:
13989 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
13990 case SYNC_INSN1_AND
:
13991 return "and\t%0,%1,%z2";
13992 case SYNC_INSN1_ANDI
:
13993 return "andi\t%0,%1,%2";
13994 case SYNC_INSN1_OR
:
13995 return "or\t%0,%1,%z2";
13996 case SYNC_INSN1_ORI
:
13997 return "ori\t%0,%1,%2";
13998 case SYNC_INSN1_XOR
:
13999 return "xor\t%0,%1,%z2";
14000 case SYNC_INSN1_XORI
:
14001 return "xori\t%0,%1,%2";
14003 gcc_unreachable ();
14006 /* Return the asm template associated with sync_insn2 value TYPE. */
14008 static const char *
14009 mips_sync_insn2_template (enum attr_sync_insn2 type
)
14013 case SYNC_INSN2_NOP
:
14014 gcc_unreachable ();
14015 case SYNC_INSN2_AND
:
14016 return "and\t%0,%1,%z2";
14017 case SYNC_INSN2_XOR
:
14018 return "xor\t%0,%1,%z2";
14019 case SYNC_INSN2_NOT
:
14020 return "nor\t%0,%1,%.";
14022 gcc_unreachable ();
14025 /* OPERANDS are the operands to a sync loop instruction and INDEX is
14026 the value of the one of the sync_* attributes. Return the operand
14027 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
14028 have the associated attribute. */
14031 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
14034 default_value
= operands
[index
- 1];
14035 return default_value
;
14038 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
14039 sequence for it. */
14042 mips_process_sync_loop (rtx_insn
*insn
, rtx
*operands
)
14044 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
14045 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
, cmp
;
14046 unsigned int tmp3_insn
;
14047 enum attr_sync_insn1 insn1
;
14048 enum attr_sync_insn2 insn2
;
14051 enum memmodel model
;
14053 /* Read an operand from the sync_WHAT attribute and store it in
14054 variable WHAT. DEFAULT is the default value if no attribute
14056 #define READ_OPERAND(WHAT, DEFAULT) \
14057 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
14060 /* Read the memory. */
14061 READ_OPERAND (mem
, 0);
14063 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
14065 /* Read the other attributes. */
14066 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
14067 READ_OPERAND (oldval
, at
);
14068 READ_OPERAND (cmp
, 0);
14069 READ_OPERAND (newval
, at
);
14070 READ_OPERAND (inclusive_mask
, 0);
14071 READ_OPERAND (exclusive_mask
, 0);
14072 READ_OPERAND (required_oldval
, 0);
14073 READ_OPERAND (insn1_op2
, 0);
14074 insn1
= get_attr_sync_insn1 (insn
);
14075 insn2
= get_attr_sync_insn2 (insn
);
14077 /* Don't bother setting CMP result that is never used. */
14078 if (cmp
&& find_reg_note (insn
, REG_UNUSED
, cmp
))
14081 memmodel_attr
= get_attr_sync_memmodel (insn
);
14082 switch (memmodel_attr
)
14085 model
= MEMMODEL_ACQ_REL
;
14088 model
= MEMMODEL_ACQUIRE
;
14091 model
= memmodel_from_int (INTVAL (operands
[memmodel_attr
]));
14094 mips_multi_start ();
14096 /* Output the release side of the memory barrier. */
14097 if (need_atomic_barrier_p (model
, true))
14099 if (required_oldval
== 0 && TARGET_OCTEON
)
14101 /* Octeon doesn't reorder reads, so a full barrier can be
14102 created by using SYNCW to order writes combined with the
14103 write from the following SC. When the SC successfully
14104 completes, we know that all preceding writes are also
14105 committed to the coherent memory system. It is possible
14106 for a single SYNCW to fail, but a pair of them will never
14107 fail, so we use two. */
14108 mips_multi_add_insn ("syncw", NULL
);
14109 mips_multi_add_insn ("syncw", NULL
);
14112 mips_multi_add_insn ("sync", NULL
);
14115 /* Output the branch-back label. */
14116 mips_multi_add_label ("1:");
14118 /* OLDVAL = *MEM. */
14119 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
14120 oldval
, mem
, NULL
);
14122 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
14123 if (required_oldval
)
14125 if (inclusive_mask
== 0)
14129 gcc_assert (oldval
!= at
);
14130 mips_multi_add_insn ("and\t%0,%1,%2",
14131 at
, oldval
, inclusive_mask
, NULL
);
14134 if (TARGET_CB_NEVER
)
14135 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
14137 /* CMP = 0 [delay slot]. */
14139 mips_multi_add_insn ("li\t%0,0", cmp
, NULL
);
14141 if (TARGET_CB_MAYBE
&& required_oldval
== const0_rtx
)
14142 mips_multi_add_insn ("bnezc\t%0,2f", tmp1
, NULL
);
14143 else if (TARGET_CB_MAYBE
)
14144 mips_multi_add_insn ("bnec\t%0,%1,2f", tmp1
, required_oldval
, NULL
);
14148 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
14149 if (exclusive_mask
== 0)
14153 gcc_assert (oldval
!= at
);
14154 mips_multi_add_insn ("and\t%0,%1,%z2",
14155 at
, oldval
, exclusive_mask
, NULL
);
14159 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
14161 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
14162 at least one instruction in that case. */
14163 if (insn1
== SYNC_INSN1_MOVE
14164 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
14168 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
14169 newval
, oldval
, insn1_op2
, NULL
);
14173 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
14174 if (insn2
== SYNC_INSN2_NOP
)
14178 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
14179 newval
, tmp2
, inclusive_mask
, NULL
);
14182 tmp3_insn
= mips_multi_last_index ();
14184 /* $AT = $TMP1 | $TMP3. */
14185 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
14187 mips_multi_set_operand (tmp3_insn
, 0, at
);
14192 gcc_assert (tmp1
!= tmp3
);
14193 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
14196 /* if (!commit (*MEM = $AT)) goto 1.
14198 This will sometimes be a delayed branch; see the write code below
14200 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
14202 /* When using branch likely (-mfix-r10000), the delay slot instruction
14203 will be annulled on false. The normal delay slot instructions
14204 calculate the overall result of the atomic operation and must not
14205 be annulled. To ensure this behavior unconditionally use a NOP
14206 in the delay slot for the branch likely case. */
14208 if (TARGET_CB_MAYBE
)
14209 mips_multi_add_insn ("beqzc\t%0,1b", at
, NULL
);
14211 mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at
, NULL
);
14213 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
14214 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
14216 mips_multi_copy_insn (tmp3_insn
);
14217 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
14219 else if (!(required_oldval
&& cmp
) && !mips_branch_likely
)
14220 mips_multi_add_insn ("nop", NULL
);
14222 /* CMP = 1 -- either standalone or in a delay slot. */
14223 if (required_oldval
&& cmp
)
14224 mips_multi_add_insn ("li\t%0,1", cmp
, NULL
);
14226 /* Output the acquire side of the memory barrier. */
14227 if (TARGET_SYNC_AFTER_SC
&& need_atomic_barrier_p (model
, false))
14228 mips_multi_add_insn ("sync", NULL
);
14230 /* Output the exit label, if needed. */
14231 if (required_oldval
)
14232 mips_multi_add_label ("2:");
14234 #undef READ_OPERAND
14237 /* Output and/or return the asm template for sync loop INSN, which has
14238 the operands given by OPERANDS. */
14241 mips_output_sync_loop (rtx_insn
*insn
, rtx
*operands
)
14243 /* Use branch-likely instructions to work around the LL/SC R10000
14245 mips_branch_likely
= TARGET_FIX_R10000
;
14247 mips_process_sync_loop (insn
, operands
);
14249 mips_push_asm_switch (&mips_noreorder
);
14250 mips_push_asm_switch (&mips_nomacro
);
14251 mips_push_asm_switch (&mips_noat
);
14252 mips_start_ll_sc_sync_block ();
14254 mips_multi_write ();
14256 mips_end_ll_sc_sync_block ();
14257 mips_pop_asm_switch (&mips_noat
);
14258 mips_pop_asm_switch (&mips_nomacro
);
14259 mips_pop_asm_switch (&mips_noreorder
);
14264 /* Return the number of individual instructions in sync loop INSN,
14265 which has the operands given by OPERANDS. */
14268 mips_sync_loop_insns (rtx_insn
*insn
, rtx
*operands
)
14270 /* Use branch-likely instructions to work around the LL/SC R10000
14272 mips_branch_likely
= TARGET_FIX_R10000
;
14273 mips_process_sync_loop (insn
, operands
);
14274 return mips_multi_num_insns
;
14277 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
14278 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
14280 When working around R4000 and R4400 errata, we need to make sure that
14281 the division is not immediately followed by a shift[1][2]. We also
14282 need to stop the division from being put into a branch delay slot[3].
14283 The easiest way to avoid both problems is to add a nop after the
14284 division. When a divide-by-zero check is needed, this nop can be
14285 used to fill the branch delay slot.
14287 [1] If a double-word or a variable shift executes immediately
14288 after starting an integer division, the shift may give an
14289 incorrect result. See quotations of errata #16 and #28 from
14290 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
14291 in mips.md for details.
14293 [2] A similar bug to [1] exists for all revisions of the
14294 R4000 and the R4400 when run in an MC configuration.
14295 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
14297 "19. In this following sequence:
14299 ddiv (or ddivu or div or divu)
14300 dsll32 (or dsrl32, dsra32)
14302 if an MPT stall occurs, while the divide is slipping the cpu
14303 pipeline, then the following double shift would end up with an
14306 Workaround: The compiler needs to avoid generating any
14307 sequence with divide followed by extended double shift."
14309 This erratum is also present in "MIPS R4400MC Errata, Processor
14310 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
14311 & 3.0" as errata #10 and #4, respectively.
14313 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
14314 (also valid for MIPS R4000MC processors):
14316 "52. R4000SC: This bug does not apply for the R4000PC.
14318 There are two flavors of this bug:
14320 1) If the instruction just after divide takes an RF exception
14321 (tlb-refill, tlb-invalid) and gets an instruction cache
14322 miss (both primary and secondary) and the line which is
14323 currently in secondary cache at this index had the first
14324 data word, where the bits 5..2 are set, then R4000 would
14325 get a wrong result for the div.
14330 ------------------- # end-of page. -tlb-refill
14335 ------------------- # end-of page. -tlb-invalid
14338 2) If the divide is in the taken branch delay slot, where the
14339 target takes RF exception and gets an I-cache miss for the
14340 exception vector or where I-cache miss occurs for the
14341 target address, under the above mentioned scenarios, the
14342 div would get wrong results.
14345 j r2 # to next page mapped or unmapped
14346 div r8,r9 # this bug would be there as long
14347 # as there is an ICache miss and
14348 nop # the "data pattern" is present
14351 beq r0, r0, NextPage # to Next page
14355 This bug is present for div, divu, ddiv, and ddivu
14358 Workaround: For item 1), OS could make sure that the next page
14359 after the divide instruction is also mapped. For item 2), the
14360 compiler could make sure that the divide instruction is not in
14361 the branch delay slot."
14363 These processors have PRId values of 0x00004220 and 0x00004300 for
14364 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
14367 mips_output_division (const char *division
, rtx
*operands
)
14372 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
14374 output_asm_insn (s
, operands
);
14377 if (TARGET_CHECK_ZERO_DIV
)
14381 output_asm_insn (s
, operands
);
14382 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
14384 else if (GENERATE_DIVIDE_TRAPS
)
14386 /* Avoid long replay penalty on load miss by putting the trap before
14389 output_asm_insn ("teq\t%2,%.,7", operands
);
14392 output_asm_insn (s
, operands
);
14393 s
= "teq\t%2,%.,7";
14398 if (flag_delayed_branch
)
14400 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
14401 output_asm_insn (s
, operands
);
14402 s
= "break\t7%)\n1:";
14406 output_asm_insn (s
, operands
);
14407 s
= "bne\t%2,%.,1f\n\tnop\n\tbreak\t7\n1:";
14414 /* Return the assembly code for MSA DIV_{S,U}.DF or MOD_{S,U}.DF instructions,
14415 which has the operands given by OPERANDS. Add in a divide-by-zero check
14419 mips_msa_output_division (const char *division
, rtx
*operands
)
14424 if (TARGET_CHECK_ZERO_DIV
)
14426 output_asm_insn ("%(bnz.%v0\t%w2,1f", operands
);
14427 output_asm_insn (s
, operands
);
14428 s
= "break\t7%)\n1:";
14433 /* Return true if destination of IN_INSN is used as add source in
14434 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
14435 madd.s dst, x, y, z
14436 madd.s a, dst, b, c */
14439 mips_fmadd_bypass (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14441 int dst_reg
, src_reg
;
14443 gcc_assert (get_attr_type (in_insn
) == TYPE_FMADD
);
14444 gcc_assert (get_attr_type (out_insn
) == TYPE_FMADD
);
14446 extract_insn (in_insn
);
14447 dst_reg
= REG_P (recog_data
.operand
[0]);
14449 extract_insn (out_insn
);
14450 src_reg
= REG_P (recog_data
.operand
[1]);
14452 if (dst_reg
== src_reg
)
14458 /* Return true if IN_INSN is a multiply-add or multiply-subtract
14459 instruction and if OUT_INSN assigns to the accumulator operand. */
14462 mips_linked_madd_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14464 enum attr_accum_in accum_in
;
14465 int accum_in_opnum
;
14468 if (recog_memoized (in_insn
) < 0)
14471 accum_in
= get_attr_accum_in (in_insn
);
14472 if (accum_in
== ACCUM_IN_NONE
)
14475 accum_in_opnum
= accum_in
- ACCUM_IN_0
;
14477 extract_insn (in_insn
);
14478 gcc_assert (accum_in_opnum
< recog_data
.n_operands
);
14479 accum_in_op
= recog_data
.operand
[accum_in_opnum
];
14481 return reg_set_p (accum_in_op
, out_insn
);
14484 /* True if the dependency between OUT_INSN and IN_INSN is on the store
14485 data rather than the address. We need this because the cprestore
14486 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
14487 which causes the default routine to abort. We just return false
14491 mips_store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
14493 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
14496 return store_data_bypass_p (out_insn
, in_insn
);
14500 /* Variables and flags used in scheduler hooks when tuning for
14504 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
14507 /* If true, then next ALU1/2 instruction will go to ALU1. */
14510 /* If true, then next FALU1/2 unstruction will go to FALU1. */
14513 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
14514 int alu1_core_unit_code
;
14515 int alu2_core_unit_code
;
14516 int falu1_core_unit_code
;
14517 int falu2_core_unit_code
;
14519 /* True if current cycle has a multi instruction.
14520 This flag is used in mips_ls2_dfa_post_advance_cycle. */
14521 bool cycle_has_multi_p
;
14523 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
14524 These are used in mips_ls2_dfa_post_advance_cycle to initialize
14526 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
14527 instruction to go ALU1. */
14528 rtx_insn
*alu1_turn_enabled_insn
;
14529 rtx_insn
*alu2_turn_enabled_insn
;
14530 rtx_insn
*falu1_turn_enabled_insn
;
14531 rtx_insn
*falu2_turn_enabled_insn
;
14534 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
14535 dependencies have no cost, except on the 20Kc where output-dependence
14536 is treated like input-dependence. */
14539 mips_adjust_cost (rtx_insn
*, int dep_type
, rtx_insn
*, int cost
, unsigned int)
14541 if (dep_type
!= 0 && (dep_type
!= REG_DEP_OUTPUT
|| !TUNE_20KC
))
14546 /* Return the number of instructions that can be issued per cycle. */
14549 mips_issue_rate (void)
14553 case PROCESSOR_74KC
:
14554 case PROCESSOR_74KF2_1
:
14555 case PROCESSOR_74KF1_1
:
14556 case PROCESSOR_74KF3_2
:
14557 /* The 74k is not strictly quad-issue cpu, but can be seen as one
14558 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
14559 but in reality only a maximum of 3 insns can be issued as
14560 floating-point loads and stores also require a slot in the
14562 case PROCESSOR_R10000
:
14563 /* All R10K Processors are quad-issue (being the first MIPS
14564 processors to support this feature). */
14567 case PROCESSOR_20KC
:
14568 case PROCESSOR_R4130
:
14569 case PROCESSOR_R5400
:
14570 case PROCESSOR_R5500
:
14571 case PROCESSOR_R5900
:
14572 case PROCESSOR_R7000
:
14573 case PROCESSOR_R9000
:
14574 case PROCESSOR_OCTEON
:
14575 case PROCESSOR_OCTEON2
:
14576 case PROCESSOR_OCTEON3
:
14577 case PROCESSOR_I6400
:
14580 case PROCESSOR_SB1
:
14581 case PROCESSOR_SB1A
:
14582 /* This is actually 4, but we get better performance if we claim 3.
14583 This is partly because of unwanted speculative code motion with the
14584 larger number, and partly because in most common cases we can't
14585 reach the theoretical max of 4. */
14588 case PROCESSOR_LOONGSON_2E
:
14589 case PROCESSOR_LOONGSON_2F
:
14590 case PROCESSOR_LOONGSON_3A
:
14591 case PROCESSOR_P5600
:
14594 case PROCESSOR_XLP
:
14595 return (reload_completed
? 4 : 3);
14602 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
14605 mips_ls2_init_dfa_post_cycle_insn (void)
14608 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
14609 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
14613 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
14614 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
14618 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
14619 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
14623 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
14624 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
14627 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
14628 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
14629 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
14630 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
14633 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
14634 Init data used in mips_dfa_post_advance_cycle. */
14637 mips_init_dfa_post_cycle_insn (void)
14639 if (TUNE_LOONGSON_2EF
)
14640 mips_ls2_init_dfa_post_cycle_insn ();
14643 /* Initialize STATE when scheduling for Loongson 2E/2F.
14644 Support round-robin dispatch scheme by enabling only one of
14645 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
14649 mips_ls2_dfa_post_advance_cycle (state_t state
)
14651 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
14653 /* Though there are no non-pipelined ALU1 insns,
14654 we can get an instruction of type 'multi' before reload. */
14655 gcc_assert (mips_ls2
.cycle_has_multi_p
);
14656 mips_ls2
.alu1_turn_p
= false;
14659 mips_ls2
.cycle_has_multi_p
= false;
14661 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
14662 /* We have a non-pipelined alu instruction in the core,
14663 adjust round-robin counter. */
14664 mips_ls2
.alu1_turn_p
= true;
14666 if (mips_ls2
.alu1_turn_p
)
14668 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
14669 gcc_unreachable ();
14673 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
14674 gcc_unreachable ();
14677 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
14679 /* There are no non-pipelined FALU1 insns. */
14680 gcc_unreachable ();
14681 mips_ls2
.falu1_turn_p
= false;
14684 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
14685 /* We have a non-pipelined falu instruction in the core,
14686 adjust round-robin counter. */
14687 mips_ls2
.falu1_turn_p
= true;
14689 if (mips_ls2
.falu1_turn_p
)
14691 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
14692 gcc_unreachable ();
14696 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
14697 gcc_unreachable ();
14701 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
14702 This hook is being called at the start of each cycle. */
14705 mips_dfa_post_advance_cycle (void)
14707 if (TUNE_LOONGSON_2EF
)
14708 mips_ls2_dfa_post_advance_cycle (curr_state
);
14711 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
14712 be as wide as the scheduling freedom in the DFA. */
14715 mips_multipass_dfa_lookahead (void)
14717 /* Can schedule up to 4 of the 6 function units in any one cycle. */
14721 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
14727 if (TUNE_P5600
|| TUNE_I6400
)
14733 /* Remove the instruction at index LOWER from ready queue READY and
14734 reinsert it in front of the instruction at index HIGHER. LOWER must
14738 mips_promote_ready (rtx_insn
**ready
, int lower
, int higher
)
14740 rtx_insn
*new_head
;
14743 new_head
= ready
[lower
];
14744 for (i
= lower
; i
< higher
; i
++)
14745 ready
[i
] = ready
[i
+ 1];
14746 ready
[i
] = new_head
;
14749 /* If the priority of the instruction at POS2 in the ready queue READY
14750 is within LIMIT units of that of the instruction at POS1, swap the
14751 instructions if POS2 is not already less than POS1. */
14754 mips_maybe_swap_ready (rtx_insn
**ready
, int pos1
, int pos2
, int limit
)
14757 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
14761 temp
= ready
[pos1
];
14762 ready
[pos1
] = ready
[pos2
];
14763 ready
[pos2
] = temp
;
14767 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
14768 that may clobber hi or lo. */
14769 static rtx_insn
*mips_macc_chains_last_hilo
;
14771 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
14772 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
14775 mips_macc_chains_record (rtx_insn
*insn
)
14777 if (get_attr_may_clobber_hilo (insn
))
14778 mips_macc_chains_last_hilo
= insn
;
14781 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
14782 has NREADY elements, looking for a multiply-add or multiply-subtract
14783 instruction that is cumulative with mips_macc_chains_last_hilo.
14784 If there is one, promote it ahead of anything else that might
14785 clobber hi or lo. */
14788 mips_macc_chains_reorder (rtx_insn
**ready
, int nready
)
14792 if (mips_macc_chains_last_hilo
!= 0)
14793 for (i
= nready
- 1; i
>= 0; i
--)
14794 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
14796 for (j
= nready
- 1; j
> i
; j
--)
14797 if (recog_memoized (ready
[j
]) >= 0
14798 && get_attr_may_clobber_hilo (ready
[j
]))
14800 mips_promote_ready (ready
, i
, j
);
14807 /* The last instruction to be scheduled. */
14808 static rtx_insn
*vr4130_last_insn
;
14810 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
14811 points to an rtx that is initially an instruction. Nullify the rtx
14812 if the instruction uses the value of register X. */
14815 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
14820 insn_ptr
= (rtx
*) data
;
14823 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
14827 /* Return true if there is true register dependence between vr4130_last_insn
14831 vr4130_true_reg_dependence_p (rtx insn
)
14833 note_stores (PATTERN (vr4130_last_insn
),
14834 vr4130_true_reg_dependence_p_1
, &insn
);
14838 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
14839 the ready queue and that INSN2 is the instruction after it, return
14840 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
14841 in which INSN1 and INSN2 can probably issue in parallel, but for
14842 which (INSN2, INSN1) should be less sensitive to instruction
14843 alignment than (INSN1, INSN2). See 4130.md for more details. */
14846 vr4130_swap_insns_p (rtx_insn
*insn1
, rtx_insn
*insn2
)
14848 sd_iterator_def sd_it
;
14851 /* Check for the following case:
14853 1) there is some other instruction X with an anti dependence on INSN1;
14854 2) X has a higher priority than INSN2; and
14855 3) X is an arithmetic instruction (and thus has no unit restrictions).
14857 If INSN1 is the last instruction blocking X, it would better to
14858 choose (INSN1, X) over (INSN2, INSN1). */
14859 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
14860 if (DEP_TYPE (dep
) == REG_DEP_ANTI
14861 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
14862 && recog_memoized (DEP_CON (dep
)) >= 0
14863 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
14866 if (vr4130_last_insn
!= 0
14867 && recog_memoized (insn1
) >= 0
14868 && recog_memoized (insn2
) >= 0)
14870 /* See whether INSN1 and INSN2 use different execution units,
14871 or if they are both ALU-type instructions. If so, they can
14872 probably execute in parallel. */
14873 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
14874 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
14875 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
14877 /* If only one of the instructions has a dependence on
14878 vr4130_last_insn, prefer to schedule the other one first. */
14879 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
14880 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
14881 if (dep1_p
!= dep2_p
)
14884 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
14885 is not an ALU-type instruction and if INSN1 uses the same
14886 execution unit. (Note that if this condition holds, we already
14887 know that INSN2 uses a different execution unit.) */
14888 if (class1
!= VR4130_CLASS_ALU
14889 && recog_memoized (vr4130_last_insn
) >= 0
14890 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
14897 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
14898 queue with at least two instructions. Swap the first two if
14899 vr4130_swap_insns_p says that it could be worthwhile. */
14902 vr4130_reorder (rtx_insn
**ready
, int nready
)
14904 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
14905 mips_promote_ready (ready
, nready
- 2, nready
- 1);
14908 /* Record whether last 74k AGEN instruction was a load or store. */
14909 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
14911 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
14912 resets to TYPE_UNKNOWN state. */
14915 mips_74k_agen_init (rtx_insn
*insn
)
14917 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
14918 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
14921 enum attr_type type
= get_attr_type (insn
);
14922 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
14923 mips_last_74k_agen_insn
= type
;
14927 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
14928 loads to be grouped together, and multiple stores to be grouped
14929 together. Swap things around in the ready queue to make this happen. */
14932 mips_74k_agen_reorder (rtx_insn
**ready
, int nready
)
14935 int store_pos
, load_pos
;
14940 for (i
= nready
- 1; i
>= 0; i
--)
14942 rtx_insn
*insn
= ready
[i
];
14943 if (USEFUL_INSN_P (insn
))
14944 switch (get_attr_type (insn
))
14947 if (store_pos
== -1)
14952 if (load_pos
== -1)
14961 if (load_pos
== -1 || store_pos
== -1)
14964 switch (mips_last_74k_agen_insn
)
14967 /* Prefer to schedule loads since they have a higher latency. */
14969 /* Swap loads to the front of the queue. */
14970 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
14973 /* Swap stores to the front of the queue. */
14974 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
14981 /* Implement TARGET_SCHED_INIT. */
14984 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
14985 int max_ready ATTRIBUTE_UNUSED
)
14987 mips_macc_chains_last_hilo
= 0;
14988 vr4130_last_insn
= 0;
14989 mips_74k_agen_init (NULL
);
14991 /* When scheduling for Loongson2, branch instructions go to ALU1,
14992 therefore basic block is most likely to start with round-robin counter
14993 pointed to ALU2. */
14994 mips_ls2
.alu1_turn_p
= false;
14995 mips_ls2
.falu1_turn_p
= true;
14998 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
15001 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15002 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
15004 if (!reload_completed
15005 && TUNE_MACC_CHAINS
15007 mips_macc_chains_reorder (ready
, *nreadyp
);
15009 if (reload_completed
15011 && !TARGET_VR4130_ALIGN
15013 vr4130_reorder (ready
, *nreadyp
);
15016 mips_74k_agen_reorder (ready
, *nreadyp
);
15019 /* Implement TARGET_SCHED_REORDER. */
15022 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15023 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
15025 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
15026 return mips_issue_rate ();
15029 /* Implement TARGET_SCHED_REORDER2. */
15032 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15033 rtx_insn
**ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
15035 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
15036 return cached_can_issue_more
;
15039 /* Update round-robin counters for ALU1/2 and FALU1/2. */
15042 mips_ls2_variable_issue (rtx_insn
*insn
)
15044 if (mips_ls2
.alu1_turn_p
)
15046 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
15047 mips_ls2
.alu1_turn_p
= false;
15051 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
15052 mips_ls2
.alu1_turn_p
= true;
15055 if (mips_ls2
.falu1_turn_p
)
15057 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
15058 mips_ls2
.falu1_turn_p
= false;
15062 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
15063 mips_ls2
.falu1_turn_p
= true;
15066 if (recog_memoized (insn
) >= 0)
15067 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
15070 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
15073 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
15074 rtx_insn
*insn
, int more
)
15076 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
15077 if (USEFUL_INSN_P (insn
))
15079 if (get_attr_type (insn
) != TYPE_GHOST
)
15081 if (!reload_completed
&& TUNE_MACC_CHAINS
)
15082 mips_macc_chains_record (insn
);
15083 vr4130_last_insn
= insn
;
15085 mips_74k_agen_init (insn
);
15086 else if (TUNE_LOONGSON_2EF
)
15087 mips_ls2_variable_issue (insn
);
15090 /* Instructions of type 'multi' should all be split before
15091 the second scheduling pass. */
15092 gcc_assert (!reload_completed
15093 || recog_memoized (insn
) < 0
15094 || get_attr_type (insn
) != TYPE_MULTI
);
15096 cached_can_issue_more
= more
;
15100 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
15101 return the first operand of the associated PREF or PREFX insn. */
15104 mips_prefetch_cookie (rtx write
, rtx locality
)
15106 /* store_streamed / load_streamed. */
15107 if (INTVAL (locality
) <= 0)
15108 return GEN_INT (INTVAL (write
) + 4);
15110 /* store / load. */
15111 if (INTVAL (locality
) <= 2)
15114 /* store_retained / load_retained. */
15115 return GEN_INT (INTVAL (write
) + 6);
15118 /* Flags that indicate when a built-in function is available.
15120 BUILTIN_AVAIL_NON_MIPS16
15121 The function is available on the current target if !TARGET_MIPS16.
15123 BUILTIN_AVAIL_MIPS16
15124 The function is available on the current target if TARGET_MIPS16. */
15125 #define BUILTIN_AVAIL_NON_MIPS16 1
15126 #define BUILTIN_AVAIL_MIPS16 2
15128 /* Declare an availability predicate for built-in functions that
15129 require non-MIPS16 mode and also require COND to be true.
15130 NAME is the main part of the predicate's name. */
15131 #define AVAIL_NON_MIPS16(NAME, COND) \
15132 static unsigned int \
15133 mips_builtin_avail_##NAME (void) \
15135 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
15138 /* Declare an availability predicate for built-in functions that
15139 support both MIPS16 and non-MIPS16 code and also require COND
15140 to be true. NAME is the main part of the predicate's name. */
15141 #define AVAIL_ALL(NAME, COND) \
15142 static unsigned int \
15143 mips_builtin_avail_##NAME (void) \
15145 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
15148 /* This structure describes a single built-in function. */
15149 struct mips_builtin_description
{
15150 /* The code of the main .md file instruction. See mips_builtin_type
15151 for more information. */
15152 enum insn_code icode
;
15154 /* The floating-point comparison code to use with ICODE, if any. */
15155 enum mips_fp_condition cond
;
15157 /* The name of the built-in function. */
15160 /* Specifies how the function should be expanded. */
15161 enum mips_builtin_type builtin_type
;
15163 /* The function's prototype. */
15164 enum mips_function_type function_type
;
15166 /* Whether the function is available. */
15167 unsigned int (*avail
) (void);
15170 AVAIL_ALL (hard_float
, TARGET_HARD_FLOAT_ABI
)
15171 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
15172 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
15173 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
15174 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
15175 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
15176 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
15177 AVAIL_NON_MIPS16 (dsp_64
, TARGET_64BIT
&& TARGET_DSP
)
15178 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
15179 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
15180 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
15181 AVAIL_NON_MIPS16 (msa
, TARGET_MSA
)
15183 /* Construct a mips_builtin_description from the given arguments.
15185 INSN is the name of the associated instruction pattern, without the
15186 leading CODE_FOR_mips_.
15188 CODE is the floating-point condition code associated with the
15189 function. It can be 'f' if the field is not applicable.
15191 NAME is the name of the function itself, without the leading
15194 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
15196 AVAIL is the name of the availability predicate, without the leading
15197 mips_builtin_avail_. */
15198 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
15199 FUNCTION_TYPE, AVAIL) \
15200 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
15201 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
15202 mips_builtin_avail_ ## AVAIL }
15204 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
15205 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
15206 are as for MIPS_BUILTIN. */
15207 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15208 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
15210 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
15211 are subject to mips_builtin_avail_<AVAIL>. */
15212 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
15213 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
15214 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
15215 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
15216 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
15218 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
15219 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
15220 while the any and all forms are subject to mips_builtin_avail_mips3d. */
15221 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
15222 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
15223 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
15225 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
15226 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
15228 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
15229 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
15231 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
15232 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
15235 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
15236 are subject to mips_builtin_avail_mips3d. */
15237 #define CMP_4S_BUILTINS(INSN, COND) \
15238 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
15239 MIPS_BUILTIN_CMP_ANY, \
15240 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
15241 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
15242 MIPS_BUILTIN_CMP_ALL, \
15243 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
15245 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
15246 instruction requires mips_builtin_avail_<AVAIL>. */
15247 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
15248 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
15249 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15251 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
15252 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15255 /* Define all the built-in functions related to C.cond.fmt condition COND. */
15256 #define CMP_BUILTINS(COND) \
15257 MOVTF_BUILTINS (c, COND, paired_single), \
15258 MOVTF_BUILTINS (cabs, COND, mips3d), \
15259 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
15260 CMP_PS_BUILTINS (c, COND, paired_single), \
15261 CMP_PS_BUILTINS (cabs, COND, mips3d), \
15262 CMP_4S_BUILTINS (c, COND), \
15263 CMP_4S_BUILTINS (cabs, COND)
15265 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
15266 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
15267 and AVAIL are as for MIPS_BUILTIN. */
15268 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15269 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15270 FUNCTION_TYPE, AVAIL)
15272 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
15273 branch instruction. AVAIL is as for MIPS_BUILTIN. */
15274 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
15275 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
15276 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
15278 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
15279 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15280 builtin_description field. */
15281 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
15282 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
15283 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
15284 FUNCTION_TYPE, mips_builtin_avail_loongson }
15286 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
15287 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15288 builtin_description field. */
15289 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
15290 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
15292 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
15293 We use functions of this form when the same insn can be usefully applied
15294 to more than one datatype. */
15295 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
15296 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
15298 /* Define an MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15299 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15301 #define MSA_BUILTIN(INSN, FUNCTION_TYPE) \
15302 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15303 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15304 FUNCTION_TYPE, mips_builtin_avail_msa }
15306 /* Define a remapped MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15307 for instruction CODE_FOR_msa_<INSN2>. FUNCTION_TYPE is
15308 a builtin_description field. */
15309 #define MSA_BUILTIN_REMAP(INSN, INSN2, FUNCTION_TYPE) \
15310 { CODE_FOR_msa_ ## INSN2, MIPS_FP_COND_f, \
15311 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15312 FUNCTION_TYPE, mips_builtin_avail_msa }
15314 /* Define an MSA MIPS_BUILTIN_MSA_TEST_BRANCH function __builtin_msa_<INSN>
15315 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15317 #define MSA_BUILTIN_TEST_BRANCH(INSN, FUNCTION_TYPE) \
15318 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15319 "__builtin_msa_" #INSN, MIPS_BUILTIN_MSA_TEST_BRANCH, \
15320 FUNCTION_TYPE, mips_builtin_avail_msa }
15322 /* Define an MSA MIPS_BUILTIN_DIRECT_NO_TARGET function __builtin_msa_<INSN>
15323 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15325 #define MSA_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE) \
15326 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15327 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15328 FUNCTION_TYPE, mips_builtin_avail_msa }
15330 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
15331 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
15332 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
15333 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
15334 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
15335 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
15336 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
15337 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
15339 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
15340 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
15341 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
15342 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
15343 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
15344 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
15345 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
15346 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
15347 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
15348 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
15349 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
15350 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
15351 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
15352 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
15353 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
15354 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
15355 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
15356 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
15357 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
15358 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
15359 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
15360 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
15361 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
15362 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
15363 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
15364 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
15365 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
15366 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
15367 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
15368 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
15370 #define CODE_FOR_msa_adds_s_b CODE_FOR_ssaddv16qi3
15371 #define CODE_FOR_msa_adds_s_h CODE_FOR_ssaddv8hi3
15372 #define CODE_FOR_msa_adds_s_w CODE_FOR_ssaddv4si3
15373 #define CODE_FOR_msa_adds_s_d CODE_FOR_ssaddv2di3
15374 #define CODE_FOR_msa_adds_u_b CODE_FOR_usaddv16qi3
15375 #define CODE_FOR_msa_adds_u_h CODE_FOR_usaddv8hi3
15376 #define CODE_FOR_msa_adds_u_w CODE_FOR_usaddv4si3
15377 #define CODE_FOR_msa_adds_u_d CODE_FOR_usaddv2di3
15378 #define CODE_FOR_msa_addv_b CODE_FOR_addv16qi3
15379 #define CODE_FOR_msa_addv_h CODE_FOR_addv8hi3
15380 #define CODE_FOR_msa_addv_w CODE_FOR_addv4si3
15381 #define CODE_FOR_msa_addv_d CODE_FOR_addv2di3
15382 #define CODE_FOR_msa_addvi_b CODE_FOR_addv16qi3
15383 #define CODE_FOR_msa_addvi_h CODE_FOR_addv8hi3
15384 #define CODE_FOR_msa_addvi_w CODE_FOR_addv4si3
15385 #define CODE_FOR_msa_addvi_d CODE_FOR_addv2di3
15386 #define CODE_FOR_msa_and_v CODE_FOR_andv16qi3
15387 #define CODE_FOR_msa_andi_b CODE_FOR_andv16qi3
15388 #define CODE_FOR_msa_bmnz_v CODE_FOR_msa_bmnz_b
15389 #define CODE_FOR_msa_bmnzi_b CODE_FOR_msa_bmnz_b
15390 #define CODE_FOR_msa_bmz_v CODE_FOR_msa_bmz_b
15391 #define CODE_FOR_msa_bmzi_b CODE_FOR_msa_bmz_b
15392 #define CODE_FOR_msa_bnz_v CODE_FOR_msa_bnz_v_b
15393 #define CODE_FOR_msa_bz_v CODE_FOR_msa_bz_v_b
15394 #define CODE_FOR_msa_bsel_v CODE_FOR_msa_bsel_b
15395 #define CODE_FOR_msa_bseli_b CODE_FOR_msa_bsel_b
15396 #define CODE_FOR_msa_ceqi_b CODE_FOR_msa_ceq_b
15397 #define CODE_FOR_msa_ceqi_h CODE_FOR_msa_ceq_h
15398 #define CODE_FOR_msa_ceqi_w CODE_FOR_msa_ceq_w
15399 #define CODE_FOR_msa_ceqi_d CODE_FOR_msa_ceq_d
15400 #define CODE_FOR_msa_clti_s_b CODE_FOR_msa_clt_s_b
15401 #define CODE_FOR_msa_clti_s_h CODE_FOR_msa_clt_s_h
15402 #define CODE_FOR_msa_clti_s_w CODE_FOR_msa_clt_s_w
15403 #define CODE_FOR_msa_clti_s_d CODE_FOR_msa_clt_s_d
15404 #define CODE_FOR_msa_clti_u_b CODE_FOR_msa_clt_u_b
15405 #define CODE_FOR_msa_clti_u_h CODE_FOR_msa_clt_u_h
15406 #define CODE_FOR_msa_clti_u_w CODE_FOR_msa_clt_u_w
15407 #define CODE_FOR_msa_clti_u_d CODE_FOR_msa_clt_u_d
15408 #define CODE_FOR_msa_clei_s_b CODE_FOR_msa_cle_s_b
15409 #define CODE_FOR_msa_clei_s_h CODE_FOR_msa_cle_s_h
15410 #define CODE_FOR_msa_clei_s_w CODE_FOR_msa_cle_s_w
15411 #define CODE_FOR_msa_clei_s_d CODE_FOR_msa_cle_s_d
15412 #define CODE_FOR_msa_clei_u_b CODE_FOR_msa_cle_u_b
15413 #define CODE_FOR_msa_clei_u_h CODE_FOR_msa_cle_u_h
15414 #define CODE_FOR_msa_clei_u_w CODE_FOR_msa_cle_u_w
15415 #define CODE_FOR_msa_clei_u_d CODE_FOR_msa_cle_u_d
15416 #define CODE_FOR_msa_div_s_b CODE_FOR_divv16qi3
15417 #define CODE_FOR_msa_div_s_h CODE_FOR_divv8hi3
15418 #define CODE_FOR_msa_div_s_w CODE_FOR_divv4si3
15419 #define CODE_FOR_msa_div_s_d CODE_FOR_divv2di3
15420 #define CODE_FOR_msa_div_u_b CODE_FOR_udivv16qi3
15421 #define CODE_FOR_msa_div_u_h CODE_FOR_udivv8hi3
15422 #define CODE_FOR_msa_div_u_w CODE_FOR_udivv4si3
15423 #define CODE_FOR_msa_div_u_d CODE_FOR_udivv2di3
15424 #define CODE_FOR_msa_fadd_w CODE_FOR_addv4sf3
15425 #define CODE_FOR_msa_fadd_d CODE_FOR_addv2df3
15426 #define CODE_FOR_msa_fexdo_w CODE_FOR_vec_pack_trunc_v2df
15427 #define CODE_FOR_msa_ftrunc_s_w CODE_FOR_fix_truncv4sfv4si2
15428 #define CODE_FOR_msa_ftrunc_s_d CODE_FOR_fix_truncv2dfv2di2
15429 #define CODE_FOR_msa_ftrunc_u_w CODE_FOR_fixuns_truncv4sfv4si2
15430 #define CODE_FOR_msa_ftrunc_u_d CODE_FOR_fixuns_truncv2dfv2di2
15431 #define CODE_FOR_msa_ffint_s_w CODE_FOR_floatv4siv4sf2
15432 #define CODE_FOR_msa_ffint_s_d CODE_FOR_floatv2div2df2
15433 #define CODE_FOR_msa_ffint_u_w CODE_FOR_floatunsv4siv4sf2
15434 #define CODE_FOR_msa_ffint_u_d CODE_FOR_floatunsv2div2df2
15435 #define CODE_FOR_msa_fsub_w CODE_FOR_subv4sf3
15436 #define CODE_FOR_msa_fsub_d CODE_FOR_subv2df3
15437 #define CODE_FOR_msa_fmadd_w CODE_FOR_fmav4sf4
15438 #define CODE_FOR_msa_fmadd_d CODE_FOR_fmav2df4
15439 #define CODE_FOR_msa_fmsub_w CODE_FOR_fnmav4sf4
15440 #define CODE_FOR_msa_fmsub_d CODE_FOR_fnmav2df4
15441 #define CODE_FOR_msa_fmul_w CODE_FOR_mulv4sf3
15442 #define CODE_FOR_msa_fmul_d CODE_FOR_mulv2df3
15443 #define CODE_FOR_msa_fdiv_w CODE_FOR_divv4sf3
15444 #define CODE_FOR_msa_fdiv_d CODE_FOR_divv2df3
15445 #define CODE_FOR_msa_fmax_w CODE_FOR_smaxv4sf3
15446 #define CODE_FOR_msa_fmax_d CODE_FOR_smaxv2df3
15447 #define CODE_FOR_msa_fmin_w CODE_FOR_sminv4sf3
15448 #define CODE_FOR_msa_fmin_d CODE_FOR_sminv2df3
15449 #define CODE_FOR_msa_fsqrt_w CODE_FOR_sqrtv4sf2
15450 #define CODE_FOR_msa_fsqrt_d CODE_FOR_sqrtv2df2
15451 #define CODE_FOR_msa_max_s_b CODE_FOR_smaxv16qi3
15452 #define CODE_FOR_msa_max_s_h CODE_FOR_smaxv8hi3
15453 #define CODE_FOR_msa_max_s_w CODE_FOR_smaxv4si3
15454 #define CODE_FOR_msa_max_s_d CODE_FOR_smaxv2di3
15455 #define CODE_FOR_msa_maxi_s_b CODE_FOR_smaxv16qi3
15456 #define CODE_FOR_msa_maxi_s_h CODE_FOR_smaxv8hi3
15457 #define CODE_FOR_msa_maxi_s_w CODE_FOR_smaxv4si3
15458 #define CODE_FOR_msa_maxi_s_d CODE_FOR_smaxv2di3
15459 #define CODE_FOR_msa_max_u_b CODE_FOR_umaxv16qi3
15460 #define CODE_FOR_msa_max_u_h CODE_FOR_umaxv8hi3
15461 #define CODE_FOR_msa_max_u_w CODE_FOR_umaxv4si3
15462 #define CODE_FOR_msa_max_u_d CODE_FOR_umaxv2di3
15463 #define CODE_FOR_msa_maxi_u_b CODE_FOR_umaxv16qi3
15464 #define CODE_FOR_msa_maxi_u_h CODE_FOR_umaxv8hi3
15465 #define CODE_FOR_msa_maxi_u_w CODE_FOR_umaxv4si3
15466 #define CODE_FOR_msa_maxi_u_d CODE_FOR_umaxv2di3
15467 #define CODE_FOR_msa_min_s_b CODE_FOR_sminv16qi3
15468 #define CODE_FOR_msa_min_s_h CODE_FOR_sminv8hi3
15469 #define CODE_FOR_msa_min_s_w CODE_FOR_sminv4si3
15470 #define CODE_FOR_msa_min_s_d CODE_FOR_sminv2di3
15471 #define CODE_FOR_msa_mini_s_b CODE_FOR_sminv16qi3
15472 #define CODE_FOR_msa_mini_s_h CODE_FOR_sminv8hi3
15473 #define CODE_FOR_msa_mini_s_w CODE_FOR_sminv4si3
15474 #define CODE_FOR_msa_mini_s_d CODE_FOR_sminv2di3
15475 #define CODE_FOR_msa_min_u_b CODE_FOR_uminv16qi3
15476 #define CODE_FOR_msa_min_u_h CODE_FOR_uminv8hi3
15477 #define CODE_FOR_msa_min_u_w CODE_FOR_uminv4si3
15478 #define CODE_FOR_msa_min_u_d CODE_FOR_uminv2di3
15479 #define CODE_FOR_msa_mini_u_b CODE_FOR_uminv16qi3
15480 #define CODE_FOR_msa_mini_u_h CODE_FOR_uminv8hi3
15481 #define CODE_FOR_msa_mini_u_w CODE_FOR_uminv4si3
15482 #define CODE_FOR_msa_mini_u_d CODE_FOR_uminv2di3
15483 #define CODE_FOR_msa_mod_s_b CODE_FOR_modv16qi3
15484 #define CODE_FOR_msa_mod_s_h CODE_FOR_modv8hi3
15485 #define CODE_FOR_msa_mod_s_w CODE_FOR_modv4si3
15486 #define CODE_FOR_msa_mod_s_d CODE_FOR_modv2di3
15487 #define CODE_FOR_msa_mod_u_b CODE_FOR_umodv16qi3
15488 #define CODE_FOR_msa_mod_u_h CODE_FOR_umodv8hi3
15489 #define CODE_FOR_msa_mod_u_w CODE_FOR_umodv4si3
15490 #define CODE_FOR_msa_mod_u_d CODE_FOR_umodv2di3
15491 #define CODE_FOR_msa_mod_s_b CODE_FOR_modv16qi3
15492 #define CODE_FOR_msa_mod_s_h CODE_FOR_modv8hi3
15493 #define CODE_FOR_msa_mod_s_w CODE_FOR_modv4si3
15494 #define CODE_FOR_msa_mod_s_d CODE_FOR_modv2di3
15495 #define CODE_FOR_msa_mod_u_b CODE_FOR_umodv16qi3
15496 #define CODE_FOR_msa_mod_u_h CODE_FOR_umodv8hi3
15497 #define CODE_FOR_msa_mod_u_w CODE_FOR_umodv4si3
15498 #define CODE_FOR_msa_mod_u_d CODE_FOR_umodv2di3
15499 #define CODE_FOR_msa_mulv_b CODE_FOR_mulv16qi3
15500 #define CODE_FOR_msa_mulv_h CODE_FOR_mulv8hi3
15501 #define CODE_FOR_msa_mulv_w CODE_FOR_mulv4si3
15502 #define CODE_FOR_msa_mulv_d CODE_FOR_mulv2di3
15503 #define CODE_FOR_msa_nlzc_b CODE_FOR_clzv16qi2
15504 #define CODE_FOR_msa_nlzc_h CODE_FOR_clzv8hi2
15505 #define CODE_FOR_msa_nlzc_w CODE_FOR_clzv4si2
15506 #define CODE_FOR_msa_nlzc_d CODE_FOR_clzv2di2
15507 #define CODE_FOR_msa_nor_v CODE_FOR_msa_nor_b
15508 #define CODE_FOR_msa_or_v CODE_FOR_iorv16qi3
15509 #define CODE_FOR_msa_ori_b CODE_FOR_iorv16qi3
15510 #define CODE_FOR_msa_nori_b CODE_FOR_msa_nor_b
15511 #define CODE_FOR_msa_pcnt_b CODE_FOR_popcountv16qi2
15512 #define CODE_FOR_msa_pcnt_h CODE_FOR_popcountv8hi2
15513 #define CODE_FOR_msa_pcnt_w CODE_FOR_popcountv4si2
15514 #define CODE_FOR_msa_pcnt_d CODE_FOR_popcountv2di2
15515 #define CODE_FOR_msa_xor_v CODE_FOR_xorv16qi3
15516 #define CODE_FOR_msa_xori_b CODE_FOR_xorv16qi3
15517 #define CODE_FOR_msa_sll_b CODE_FOR_vashlv16qi3
15518 #define CODE_FOR_msa_sll_h CODE_FOR_vashlv8hi3
15519 #define CODE_FOR_msa_sll_w CODE_FOR_vashlv4si3
15520 #define CODE_FOR_msa_sll_d CODE_FOR_vashlv2di3
15521 #define CODE_FOR_msa_slli_b CODE_FOR_vashlv16qi3
15522 #define CODE_FOR_msa_slli_h CODE_FOR_vashlv8hi3
15523 #define CODE_FOR_msa_slli_w CODE_FOR_vashlv4si3
15524 #define CODE_FOR_msa_slli_d CODE_FOR_vashlv2di3
15525 #define CODE_FOR_msa_sra_b CODE_FOR_vashrv16qi3
15526 #define CODE_FOR_msa_sra_h CODE_FOR_vashrv8hi3
15527 #define CODE_FOR_msa_sra_w CODE_FOR_vashrv4si3
15528 #define CODE_FOR_msa_sra_d CODE_FOR_vashrv2di3
15529 #define CODE_FOR_msa_srai_b CODE_FOR_vashrv16qi3
15530 #define CODE_FOR_msa_srai_h CODE_FOR_vashrv8hi3
15531 #define CODE_FOR_msa_srai_w CODE_FOR_vashrv4si3
15532 #define CODE_FOR_msa_srai_d CODE_FOR_vashrv2di3
15533 #define CODE_FOR_msa_srl_b CODE_FOR_vlshrv16qi3
15534 #define CODE_FOR_msa_srl_h CODE_FOR_vlshrv8hi3
15535 #define CODE_FOR_msa_srl_w CODE_FOR_vlshrv4si3
15536 #define CODE_FOR_msa_srl_d CODE_FOR_vlshrv2di3
15537 #define CODE_FOR_msa_srli_b CODE_FOR_vlshrv16qi3
15538 #define CODE_FOR_msa_srli_h CODE_FOR_vlshrv8hi3
15539 #define CODE_FOR_msa_srli_w CODE_FOR_vlshrv4si3
15540 #define CODE_FOR_msa_srli_d CODE_FOR_vlshrv2di3
15541 #define CODE_FOR_msa_subv_b CODE_FOR_subv16qi3
15542 #define CODE_FOR_msa_subv_h CODE_FOR_subv8hi3
15543 #define CODE_FOR_msa_subv_w CODE_FOR_subv4si3
15544 #define CODE_FOR_msa_subv_d CODE_FOR_subv2di3
15545 #define CODE_FOR_msa_subvi_b CODE_FOR_subv16qi3
15546 #define CODE_FOR_msa_subvi_h CODE_FOR_subv8hi3
15547 #define CODE_FOR_msa_subvi_w CODE_FOR_subv4si3
15548 #define CODE_FOR_msa_subvi_d CODE_FOR_subv2di3
15550 #define CODE_FOR_msa_move_v CODE_FOR_movv16qi
15552 #define CODE_FOR_msa_vshf_b CODE_FOR_vec_permv16qi
15553 #define CODE_FOR_msa_vshf_h CODE_FOR_vec_permv8hi
15554 #define CODE_FOR_msa_vshf_w CODE_FOR_vec_permv4si
15555 #define CODE_FOR_msa_vshf_d CODE_FOR_vec_permv2di
15557 #define CODE_FOR_msa_ilvod_d CODE_FOR_msa_ilvl_d
15558 #define CODE_FOR_msa_ilvev_d CODE_FOR_msa_ilvr_d
15559 #define CODE_FOR_msa_pckod_d CODE_FOR_msa_ilvl_d
15560 #define CODE_FOR_msa_pckev_d CODE_FOR_msa_ilvr_d
15562 #define CODE_FOR_msa_ldi_b CODE_FOR_msa_ldiv16qi
15563 #define CODE_FOR_msa_ldi_h CODE_FOR_msa_ldiv8hi
15564 #define CODE_FOR_msa_ldi_w CODE_FOR_msa_ldiv4si
15565 #define CODE_FOR_msa_ldi_d CODE_FOR_msa_ldiv2di
15567 static const struct mips_builtin_description mips_builtins
[] = {
15568 #define MIPS_GET_FCSR 0
15569 DIRECT_BUILTIN (get_fcsr
, MIPS_USI_FTYPE_VOID
, hard_float
),
15570 #define MIPS_SET_FCSR 1
15571 DIRECT_NO_TARGET_BUILTIN (set_fcsr
, MIPS_VOID_FTYPE_USI
, hard_float
),
15573 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15574 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15575 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15576 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
15577 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
15578 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
15579 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
15580 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
15582 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
15583 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15584 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15585 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15586 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15588 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
15589 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
15590 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15591 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
15592 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
15593 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15595 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
15596 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
15597 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
15598 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
15599 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
15600 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
15602 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
15604 /* Built-in functions for the SB-1 processor. */
15605 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
15607 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
15608 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15609 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15610 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15611 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15612 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15613 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15614 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15615 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15616 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15617 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15618 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15619 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15620 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15621 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
15622 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
15623 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
15624 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
15625 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
15626 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
15627 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
15628 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
15629 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
15630 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15631 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15632 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15633 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15634 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15635 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15636 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15637 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
15638 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
15639 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15640 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15641 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15642 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
15643 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15644 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
15645 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15646 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
15647 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
15648 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15649 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
15650 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
15651 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
15652 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
15653 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
15654 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
15655 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15656 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15657 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
15658 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15659 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15660 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
15661 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15662 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15663 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
15664 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
15665 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15666 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
15667 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
15668 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
15669 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15670 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15671 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
15672 BPOSGE_BUILTIN (32, dsp
),
15674 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
15675 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
15676 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15677 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15678 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15679 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15680 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15681 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15682 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15683 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15684 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
15685 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15686 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15687 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15688 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15689 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15690 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
15691 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
15692 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
15693 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
15694 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
15695 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
15696 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
15697 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15698 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15699 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15700 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
15701 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15702 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15703 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15704 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15705 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15706 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
15707 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15708 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
15710 /* Built-in functions for the DSP ASE (32-bit only). */
15711 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15712 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15713 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15714 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
15715 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15716 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15717 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15718 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15719 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15720 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15721 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15722 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15723 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
15724 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15725 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15726 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15727 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15728 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15729 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
15730 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
15731 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
15732 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15733 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
15734 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
15735 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
15736 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
15737 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
15739 /* Built-in functions for the DSP ASE (64-bit only). */
15740 DIRECT_BUILTIN (ldx
, MIPS_DI_FTYPE_POINTER_SI
, dsp_64
),
15742 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
15743 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15744 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15745 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15746 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15747 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15748 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15749 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15750 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15751 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
15753 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
15754 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
15755 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
15756 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
15757 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15758 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15759 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15760 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15761 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15762 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15763 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
15764 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
15765 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15766 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15767 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15768 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15769 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
15770 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15771 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15772 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15773 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
15774 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15775 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15776 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15777 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15778 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15779 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15780 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15781 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15782 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15783 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15784 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15785 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15786 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15787 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15788 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15789 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15790 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15791 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
15792 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
15793 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15794 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15795 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15796 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15797 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15798 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15799 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15800 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15801 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
15802 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15803 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15804 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15805 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15806 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
15807 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
15808 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15809 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15810 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15811 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
15812 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15813 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
15814 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
15815 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15816 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15817 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15818 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15819 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15820 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15821 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15822 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15823 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15824 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15825 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
15826 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
15827 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
15828 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
15829 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15830 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15831 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15832 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15833 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15834 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15835 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
15836 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
15837 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15838 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15839 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15840 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15841 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15842 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15843 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15844 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15845 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15846 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15847 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
15848 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
15849 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
15850 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
15851 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
15852 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
15854 /* Sundry other built-in functions. */
15855 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
),
15857 /* Built-in functions for MSA. */
15858 MSA_BUILTIN (sll_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15859 MSA_BUILTIN (sll_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15860 MSA_BUILTIN (sll_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15861 MSA_BUILTIN (sll_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15862 MSA_BUILTIN (slli_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15863 MSA_BUILTIN (slli_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15864 MSA_BUILTIN (slli_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15865 MSA_BUILTIN (slli_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15866 MSA_BUILTIN (sra_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15867 MSA_BUILTIN (sra_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15868 MSA_BUILTIN (sra_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15869 MSA_BUILTIN (sra_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15870 MSA_BUILTIN (srai_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15871 MSA_BUILTIN (srai_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15872 MSA_BUILTIN (srai_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15873 MSA_BUILTIN (srai_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15874 MSA_BUILTIN (srar_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15875 MSA_BUILTIN (srar_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15876 MSA_BUILTIN (srar_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15877 MSA_BUILTIN (srar_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15878 MSA_BUILTIN (srari_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15879 MSA_BUILTIN (srari_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15880 MSA_BUILTIN (srari_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15881 MSA_BUILTIN (srari_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15882 MSA_BUILTIN (srl_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15883 MSA_BUILTIN (srl_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15884 MSA_BUILTIN (srl_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15885 MSA_BUILTIN (srl_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15886 MSA_BUILTIN (srli_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15887 MSA_BUILTIN (srli_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15888 MSA_BUILTIN (srli_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15889 MSA_BUILTIN (srli_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15890 MSA_BUILTIN (srlr_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15891 MSA_BUILTIN (srlr_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15892 MSA_BUILTIN (srlr_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15893 MSA_BUILTIN (srlr_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15894 MSA_BUILTIN (srlri_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15895 MSA_BUILTIN (srlri_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15896 MSA_BUILTIN (srlri_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15897 MSA_BUILTIN (srlri_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15898 MSA_BUILTIN (bclr_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15899 MSA_BUILTIN (bclr_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15900 MSA_BUILTIN (bclr_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15901 MSA_BUILTIN (bclr_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15902 MSA_BUILTIN (bclri_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15903 MSA_BUILTIN (bclri_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15904 MSA_BUILTIN (bclri_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15905 MSA_BUILTIN (bclri_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15906 MSA_BUILTIN (bset_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15907 MSA_BUILTIN (bset_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15908 MSA_BUILTIN (bset_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15909 MSA_BUILTIN (bset_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15910 MSA_BUILTIN (bseti_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15911 MSA_BUILTIN (bseti_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15912 MSA_BUILTIN (bseti_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15913 MSA_BUILTIN (bseti_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15914 MSA_BUILTIN (bneg_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15915 MSA_BUILTIN (bneg_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15916 MSA_BUILTIN (bneg_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15917 MSA_BUILTIN (bneg_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15918 MSA_BUILTIN (bnegi_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15919 MSA_BUILTIN (bnegi_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15920 MSA_BUILTIN (bnegi_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15921 MSA_BUILTIN (bnegi_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15922 MSA_BUILTIN (binsl_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
15923 MSA_BUILTIN (binsl_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI
),
15924 MSA_BUILTIN (binsl_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI
),
15925 MSA_BUILTIN (binsl_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI
),
15926 MSA_BUILTIN (binsli_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
15927 MSA_BUILTIN (binsli_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI
),
15928 MSA_BUILTIN (binsli_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI
),
15929 MSA_BUILTIN (binsli_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI
),
15930 MSA_BUILTIN (binsr_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
15931 MSA_BUILTIN (binsr_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI
),
15932 MSA_BUILTIN (binsr_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI
),
15933 MSA_BUILTIN (binsr_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI
),
15934 MSA_BUILTIN (binsri_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
15935 MSA_BUILTIN (binsri_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI
),
15936 MSA_BUILTIN (binsri_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI
),
15937 MSA_BUILTIN (binsri_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI
),
15938 MSA_BUILTIN (addv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15939 MSA_BUILTIN (addv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15940 MSA_BUILTIN (addv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15941 MSA_BUILTIN (addv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15942 MSA_BUILTIN (addvi_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15943 MSA_BUILTIN (addvi_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15944 MSA_BUILTIN (addvi_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15945 MSA_BUILTIN (addvi_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15946 MSA_BUILTIN (subv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15947 MSA_BUILTIN (subv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15948 MSA_BUILTIN (subv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15949 MSA_BUILTIN (subv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15950 MSA_BUILTIN (subvi_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
15951 MSA_BUILTIN (subvi_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
15952 MSA_BUILTIN (subvi_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
15953 MSA_BUILTIN (subvi_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
15954 MSA_BUILTIN (max_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15955 MSA_BUILTIN (max_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15956 MSA_BUILTIN (max_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15957 MSA_BUILTIN (max_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15958 MSA_BUILTIN (maxi_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
15959 MSA_BUILTIN (maxi_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
15960 MSA_BUILTIN (maxi_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
15961 MSA_BUILTIN (maxi_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
15962 MSA_BUILTIN (max_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15963 MSA_BUILTIN (max_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15964 MSA_BUILTIN (max_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15965 MSA_BUILTIN (max_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15966 MSA_BUILTIN (maxi_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15967 MSA_BUILTIN (maxi_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15968 MSA_BUILTIN (maxi_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15969 MSA_BUILTIN (maxi_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15970 MSA_BUILTIN (min_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15971 MSA_BUILTIN (min_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15972 MSA_BUILTIN (min_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15973 MSA_BUILTIN (min_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15974 MSA_BUILTIN (mini_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
15975 MSA_BUILTIN (mini_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
15976 MSA_BUILTIN (mini_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
15977 MSA_BUILTIN (mini_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
15978 MSA_BUILTIN (min_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
15979 MSA_BUILTIN (min_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
15980 MSA_BUILTIN (min_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
15981 MSA_BUILTIN (min_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
15982 MSA_BUILTIN (mini_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
15983 MSA_BUILTIN (mini_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
15984 MSA_BUILTIN (mini_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
15985 MSA_BUILTIN (mini_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
15986 MSA_BUILTIN (max_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15987 MSA_BUILTIN (max_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15988 MSA_BUILTIN (max_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15989 MSA_BUILTIN (max_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15990 MSA_BUILTIN (min_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15991 MSA_BUILTIN (min_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15992 MSA_BUILTIN (min_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15993 MSA_BUILTIN (min_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15994 MSA_BUILTIN (ceq_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
15995 MSA_BUILTIN (ceq_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
15996 MSA_BUILTIN (ceq_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
15997 MSA_BUILTIN (ceq_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
15998 MSA_BUILTIN (ceqi_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
15999 MSA_BUILTIN (ceqi_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
16000 MSA_BUILTIN (ceqi_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
16001 MSA_BUILTIN (ceqi_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
16002 MSA_BUILTIN (clt_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16003 MSA_BUILTIN (clt_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16004 MSA_BUILTIN (clt_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16005 MSA_BUILTIN (clt_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16006 MSA_BUILTIN (clti_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
16007 MSA_BUILTIN (clti_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
16008 MSA_BUILTIN (clti_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
16009 MSA_BUILTIN (clti_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
16010 MSA_BUILTIN (clt_u_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
16011 MSA_BUILTIN (clt_u_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
16012 MSA_BUILTIN (clt_u_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
16013 MSA_BUILTIN (clt_u_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
16014 MSA_BUILTIN (clti_u_b
, MIPS_V16QI_FTYPE_UV16QI_UQI
),
16015 MSA_BUILTIN (clti_u_h
, MIPS_V8HI_FTYPE_UV8HI_UQI
),
16016 MSA_BUILTIN (clti_u_w
, MIPS_V4SI_FTYPE_UV4SI_UQI
),
16017 MSA_BUILTIN (clti_u_d
, MIPS_V2DI_FTYPE_UV2DI_UQI
),
16018 MSA_BUILTIN (cle_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16019 MSA_BUILTIN (cle_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16020 MSA_BUILTIN (cle_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16021 MSA_BUILTIN (cle_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16022 MSA_BUILTIN (clei_s_b
, MIPS_V16QI_FTYPE_V16QI_QI
),
16023 MSA_BUILTIN (clei_s_h
, MIPS_V8HI_FTYPE_V8HI_QI
),
16024 MSA_BUILTIN (clei_s_w
, MIPS_V4SI_FTYPE_V4SI_QI
),
16025 MSA_BUILTIN (clei_s_d
, MIPS_V2DI_FTYPE_V2DI_QI
),
16026 MSA_BUILTIN (cle_u_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
16027 MSA_BUILTIN (cle_u_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
16028 MSA_BUILTIN (cle_u_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
16029 MSA_BUILTIN (cle_u_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
16030 MSA_BUILTIN (clei_u_b
, MIPS_V16QI_FTYPE_UV16QI_UQI
),
16031 MSA_BUILTIN (clei_u_h
, MIPS_V8HI_FTYPE_UV8HI_UQI
),
16032 MSA_BUILTIN (clei_u_w
, MIPS_V4SI_FTYPE_UV4SI_UQI
),
16033 MSA_BUILTIN (clei_u_d
, MIPS_V2DI_FTYPE_UV2DI_UQI
),
16034 MSA_BUILTIN (ld_b
, MIPS_V16QI_FTYPE_CVPOINTER_SI
),
16035 MSA_BUILTIN (ld_h
, MIPS_V8HI_FTYPE_CVPOINTER_SI
),
16036 MSA_BUILTIN (ld_w
, MIPS_V4SI_FTYPE_CVPOINTER_SI
),
16037 MSA_BUILTIN (ld_d
, MIPS_V2DI_FTYPE_CVPOINTER_SI
),
16038 MSA_NO_TARGET_BUILTIN (st_b
, MIPS_VOID_FTYPE_V16QI_CVPOINTER_SI
),
16039 MSA_NO_TARGET_BUILTIN (st_h
, MIPS_VOID_FTYPE_V8HI_CVPOINTER_SI
),
16040 MSA_NO_TARGET_BUILTIN (st_w
, MIPS_VOID_FTYPE_V4SI_CVPOINTER_SI
),
16041 MSA_NO_TARGET_BUILTIN (st_d
, MIPS_VOID_FTYPE_V2DI_CVPOINTER_SI
),
16042 MSA_BUILTIN (sat_s_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16043 MSA_BUILTIN (sat_s_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16044 MSA_BUILTIN (sat_s_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16045 MSA_BUILTIN (sat_s_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
16046 MSA_BUILTIN (sat_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16047 MSA_BUILTIN (sat_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UQI
),
16048 MSA_BUILTIN (sat_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UQI
),
16049 MSA_BUILTIN (sat_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UQI
),
16050 MSA_BUILTIN (add_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16051 MSA_BUILTIN (add_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16052 MSA_BUILTIN (add_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16053 MSA_BUILTIN (add_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16054 MSA_BUILTIN (adds_a_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16055 MSA_BUILTIN (adds_a_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16056 MSA_BUILTIN (adds_a_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16057 MSA_BUILTIN (adds_a_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16058 MSA_BUILTIN (adds_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16059 MSA_BUILTIN (adds_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16060 MSA_BUILTIN (adds_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16061 MSA_BUILTIN (adds_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16062 MSA_BUILTIN (adds_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16063 MSA_BUILTIN (adds_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16064 MSA_BUILTIN (adds_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16065 MSA_BUILTIN (adds_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16066 MSA_BUILTIN (ave_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16067 MSA_BUILTIN (ave_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16068 MSA_BUILTIN (ave_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16069 MSA_BUILTIN (ave_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16070 MSA_BUILTIN (ave_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16071 MSA_BUILTIN (ave_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16072 MSA_BUILTIN (ave_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16073 MSA_BUILTIN (ave_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16074 MSA_BUILTIN (aver_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16075 MSA_BUILTIN (aver_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16076 MSA_BUILTIN (aver_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16077 MSA_BUILTIN (aver_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16078 MSA_BUILTIN (aver_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16079 MSA_BUILTIN (aver_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16080 MSA_BUILTIN (aver_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16081 MSA_BUILTIN (aver_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16082 MSA_BUILTIN (subs_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16083 MSA_BUILTIN (subs_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16084 MSA_BUILTIN (subs_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16085 MSA_BUILTIN (subs_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16086 MSA_BUILTIN (subs_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16087 MSA_BUILTIN (subs_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16088 MSA_BUILTIN (subs_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16089 MSA_BUILTIN (subs_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16090 MSA_BUILTIN (subsuu_s_b
, MIPS_V16QI_FTYPE_UV16QI_UV16QI
),
16091 MSA_BUILTIN (subsuu_s_h
, MIPS_V8HI_FTYPE_UV8HI_UV8HI
),
16092 MSA_BUILTIN (subsuu_s_w
, MIPS_V4SI_FTYPE_UV4SI_UV4SI
),
16093 MSA_BUILTIN (subsuu_s_d
, MIPS_V2DI_FTYPE_UV2DI_UV2DI
),
16094 MSA_BUILTIN (subsus_u_b
, MIPS_UV16QI_FTYPE_UV16QI_V16QI
),
16095 MSA_BUILTIN (subsus_u_h
, MIPS_UV8HI_FTYPE_UV8HI_V8HI
),
16096 MSA_BUILTIN (subsus_u_w
, MIPS_UV4SI_FTYPE_UV4SI_V4SI
),
16097 MSA_BUILTIN (subsus_u_d
, MIPS_UV2DI_FTYPE_UV2DI_V2DI
),
16098 MSA_BUILTIN (asub_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16099 MSA_BUILTIN (asub_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16100 MSA_BUILTIN (asub_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16101 MSA_BUILTIN (asub_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16102 MSA_BUILTIN (asub_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16103 MSA_BUILTIN (asub_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16104 MSA_BUILTIN (asub_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16105 MSA_BUILTIN (asub_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16106 MSA_BUILTIN (mulv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16107 MSA_BUILTIN (mulv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16108 MSA_BUILTIN (mulv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16109 MSA_BUILTIN (mulv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16110 MSA_BUILTIN (maddv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16111 MSA_BUILTIN (maddv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16112 MSA_BUILTIN (maddv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16113 MSA_BUILTIN (maddv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16114 MSA_BUILTIN (msubv_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16115 MSA_BUILTIN (msubv_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16116 MSA_BUILTIN (msubv_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16117 MSA_BUILTIN (msubv_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16118 MSA_BUILTIN (div_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16119 MSA_BUILTIN (div_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16120 MSA_BUILTIN (div_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16121 MSA_BUILTIN (div_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16122 MSA_BUILTIN (div_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16123 MSA_BUILTIN (div_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16124 MSA_BUILTIN (div_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16125 MSA_BUILTIN (div_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16126 MSA_BUILTIN (hadd_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16127 MSA_BUILTIN (hadd_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16128 MSA_BUILTIN (hadd_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16129 MSA_BUILTIN (hadd_u_h
, MIPS_UV8HI_FTYPE_UV16QI_UV16QI
),
16130 MSA_BUILTIN (hadd_u_w
, MIPS_UV4SI_FTYPE_UV8HI_UV8HI
),
16131 MSA_BUILTIN (hadd_u_d
, MIPS_UV2DI_FTYPE_UV4SI_UV4SI
),
16132 MSA_BUILTIN (hsub_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16133 MSA_BUILTIN (hsub_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16134 MSA_BUILTIN (hsub_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16135 MSA_BUILTIN (hsub_u_h
, MIPS_V8HI_FTYPE_UV16QI_UV16QI
),
16136 MSA_BUILTIN (hsub_u_w
, MIPS_V4SI_FTYPE_UV8HI_UV8HI
),
16137 MSA_BUILTIN (hsub_u_d
, MIPS_V2DI_FTYPE_UV4SI_UV4SI
),
16138 MSA_BUILTIN (mod_s_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16139 MSA_BUILTIN (mod_s_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16140 MSA_BUILTIN (mod_s_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16141 MSA_BUILTIN (mod_s_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16142 MSA_BUILTIN (mod_u_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16143 MSA_BUILTIN (mod_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV8HI
),
16144 MSA_BUILTIN (mod_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV4SI
),
16145 MSA_BUILTIN (mod_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV2DI
),
16146 MSA_BUILTIN (dotp_s_h
, MIPS_V8HI_FTYPE_V16QI_V16QI
),
16147 MSA_BUILTIN (dotp_s_w
, MIPS_V4SI_FTYPE_V8HI_V8HI
),
16148 MSA_BUILTIN (dotp_s_d
, MIPS_V2DI_FTYPE_V4SI_V4SI
),
16149 MSA_BUILTIN (dotp_u_h
, MIPS_UV8HI_FTYPE_UV16QI_UV16QI
),
16150 MSA_BUILTIN (dotp_u_w
, MIPS_UV4SI_FTYPE_UV8HI_UV8HI
),
16151 MSA_BUILTIN (dotp_u_d
, MIPS_UV2DI_FTYPE_UV4SI_UV4SI
),
16152 MSA_BUILTIN (dpadd_s_h
, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI
),
16153 MSA_BUILTIN (dpadd_s_w
, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI
),
16154 MSA_BUILTIN (dpadd_s_d
, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI
),
16155 MSA_BUILTIN (dpadd_u_h
, MIPS_UV8HI_FTYPE_UV8HI_UV16QI_UV16QI
),
16156 MSA_BUILTIN (dpadd_u_w
, MIPS_UV4SI_FTYPE_UV4SI_UV8HI_UV8HI
),
16157 MSA_BUILTIN (dpadd_u_d
, MIPS_UV2DI_FTYPE_UV2DI_UV4SI_UV4SI
),
16158 MSA_BUILTIN (dpsub_s_h
, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI
),
16159 MSA_BUILTIN (dpsub_s_w
, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI
),
16160 MSA_BUILTIN (dpsub_s_d
, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI
),
16161 MSA_BUILTIN (dpsub_u_h
, MIPS_V8HI_FTYPE_V8HI_UV16QI_UV16QI
),
16162 MSA_BUILTIN (dpsub_u_w
, MIPS_V4SI_FTYPE_V4SI_UV8HI_UV8HI
),
16163 MSA_BUILTIN (dpsub_u_d
, MIPS_V2DI_FTYPE_V2DI_UV4SI_UV4SI
),
16164 MSA_BUILTIN (sld_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_SI
),
16165 MSA_BUILTIN (sld_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_SI
),
16166 MSA_BUILTIN (sld_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_SI
),
16167 MSA_BUILTIN (sld_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_SI
),
16168 MSA_BUILTIN (sldi_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_UQI
),
16169 MSA_BUILTIN (sldi_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_UQI
),
16170 MSA_BUILTIN (sldi_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_UQI
),
16171 MSA_BUILTIN (sldi_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_UQI
),
16172 MSA_BUILTIN (splat_b
, MIPS_V16QI_FTYPE_V16QI_SI
),
16173 MSA_BUILTIN (splat_h
, MIPS_V8HI_FTYPE_V8HI_SI
),
16174 MSA_BUILTIN (splat_w
, MIPS_V4SI_FTYPE_V4SI_SI
),
16175 MSA_BUILTIN (splat_d
, MIPS_V2DI_FTYPE_V2DI_SI
),
16176 MSA_BUILTIN (splati_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16177 MSA_BUILTIN (splati_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16178 MSA_BUILTIN (splati_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16179 MSA_BUILTIN (splati_d
, MIPS_V2DI_FTYPE_V2DI_UQI
),
16180 MSA_BUILTIN (pckev_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16181 MSA_BUILTIN (pckev_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16182 MSA_BUILTIN (pckev_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16183 MSA_BUILTIN (pckev_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16184 MSA_BUILTIN (pckod_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16185 MSA_BUILTIN (pckod_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16186 MSA_BUILTIN (pckod_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16187 MSA_BUILTIN (pckod_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16188 MSA_BUILTIN (ilvl_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16189 MSA_BUILTIN (ilvl_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16190 MSA_BUILTIN (ilvl_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16191 MSA_BUILTIN (ilvl_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16192 MSA_BUILTIN (ilvr_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16193 MSA_BUILTIN (ilvr_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16194 MSA_BUILTIN (ilvr_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16195 MSA_BUILTIN (ilvr_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16196 MSA_BUILTIN (ilvev_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16197 MSA_BUILTIN (ilvev_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16198 MSA_BUILTIN (ilvev_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16199 MSA_BUILTIN (ilvev_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16200 MSA_BUILTIN (ilvod_b
, MIPS_V16QI_FTYPE_V16QI_V16QI
),
16201 MSA_BUILTIN (ilvod_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16202 MSA_BUILTIN (ilvod_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16203 MSA_BUILTIN (ilvod_d
, MIPS_V2DI_FTYPE_V2DI_V2DI
),
16204 MSA_BUILTIN (vshf_b
, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI
),
16205 MSA_BUILTIN (vshf_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16206 MSA_BUILTIN (vshf_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16207 MSA_BUILTIN (vshf_d
, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI
),
16208 MSA_BUILTIN (and_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16209 MSA_BUILTIN (andi_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16210 MSA_BUILTIN (or_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16211 MSA_BUILTIN (ori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16212 MSA_BUILTIN (nor_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16213 MSA_BUILTIN (nori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16214 MSA_BUILTIN (xor_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI
),
16215 MSA_BUILTIN (xori_b
, MIPS_UV16QI_FTYPE_UV16QI_UQI
),
16216 MSA_BUILTIN (bmnz_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16217 MSA_BUILTIN (bmnzi_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16218 MSA_BUILTIN (bmz_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16219 MSA_BUILTIN (bmzi_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16220 MSA_BUILTIN (bsel_v
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI
),
16221 MSA_BUILTIN (bseli_b
, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI
),
16222 MSA_BUILTIN (shf_b
, MIPS_V16QI_FTYPE_V16QI_UQI
),
16223 MSA_BUILTIN (shf_h
, MIPS_V8HI_FTYPE_V8HI_UQI
),
16224 MSA_BUILTIN (shf_w
, MIPS_V4SI_FTYPE_V4SI_UQI
),
16225 MSA_BUILTIN_TEST_BRANCH (bnz_v
, MIPS_SI_FTYPE_UV16QI
),
16226 MSA_BUILTIN_TEST_BRANCH (bz_v
, MIPS_SI_FTYPE_UV16QI
),
16227 MSA_BUILTIN (fill_b
, MIPS_V16QI_FTYPE_SI
),
16228 MSA_BUILTIN (fill_h
, MIPS_V8HI_FTYPE_SI
),
16229 MSA_BUILTIN (fill_w
, MIPS_V4SI_FTYPE_SI
),
16230 MSA_BUILTIN (fill_d
, MIPS_V2DI_FTYPE_DI
),
16231 MSA_BUILTIN (pcnt_b
, MIPS_V16QI_FTYPE_V16QI
),
16232 MSA_BUILTIN (pcnt_h
, MIPS_V8HI_FTYPE_V8HI
),
16233 MSA_BUILTIN (pcnt_w
, MIPS_V4SI_FTYPE_V4SI
),
16234 MSA_BUILTIN (pcnt_d
, MIPS_V2DI_FTYPE_V2DI
),
16235 MSA_BUILTIN (nloc_b
, MIPS_V16QI_FTYPE_V16QI
),
16236 MSA_BUILTIN (nloc_h
, MIPS_V8HI_FTYPE_V8HI
),
16237 MSA_BUILTIN (nloc_w
, MIPS_V4SI_FTYPE_V4SI
),
16238 MSA_BUILTIN (nloc_d
, MIPS_V2DI_FTYPE_V2DI
),
16239 MSA_BUILTIN (nlzc_b
, MIPS_V16QI_FTYPE_V16QI
),
16240 MSA_BUILTIN (nlzc_h
, MIPS_V8HI_FTYPE_V8HI
),
16241 MSA_BUILTIN (nlzc_w
, MIPS_V4SI_FTYPE_V4SI
),
16242 MSA_BUILTIN (nlzc_d
, MIPS_V2DI_FTYPE_V2DI
),
16243 MSA_BUILTIN (copy_s_b
, MIPS_SI_FTYPE_V16QI_UQI
),
16244 MSA_BUILTIN (copy_s_h
, MIPS_SI_FTYPE_V8HI_UQI
),
16245 MSA_BUILTIN (copy_s_w
, MIPS_SI_FTYPE_V4SI_UQI
),
16246 MSA_BUILTIN (copy_s_d
, MIPS_DI_FTYPE_V2DI_UQI
),
16247 MSA_BUILTIN (copy_u_b
, MIPS_USI_FTYPE_V16QI_UQI
),
16248 MSA_BUILTIN (copy_u_h
, MIPS_USI_FTYPE_V8HI_UQI
),
16249 MSA_BUILTIN_REMAP (copy_u_w
, copy_s_w
, MIPS_USI_FTYPE_V4SI_UQI
),
16250 MSA_BUILTIN_REMAP (copy_u_d
, copy_s_d
, MIPS_UDI_FTYPE_V2DI_UQI
),
16251 MSA_BUILTIN (insert_b
, MIPS_V16QI_FTYPE_V16QI_UQI_SI
),
16252 MSA_BUILTIN (insert_h
, MIPS_V8HI_FTYPE_V8HI_UQI_SI
),
16253 MSA_BUILTIN (insert_w
, MIPS_V4SI_FTYPE_V4SI_UQI_SI
),
16254 MSA_BUILTIN (insert_d
, MIPS_V2DI_FTYPE_V2DI_UQI_DI
),
16255 MSA_BUILTIN (insve_b
, MIPS_V16QI_FTYPE_V16QI_UQI_V16QI
),
16256 MSA_BUILTIN (insve_h
, MIPS_V8HI_FTYPE_V8HI_UQI_V8HI
),
16257 MSA_BUILTIN (insve_w
, MIPS_V4SI_FTYPE_V4SI_UQI_V4SI
),
16258 MSA_BUILTIN (insve_d
, MIPS_V2DI_FTYPE_V2DI_UQI_V2DI
),
16259 MSA_BUILTIN_TEST_BRANCH (bnz_b
, MIPS_SI_FTYPE_UV16QI
),
16260 MSA_BUILTIN_TEST_BRANCH (bnz_h
, MIPS_SI_FTYPE_UV8HI
),
16261 MSA_BUILTIN_TEST_BRANCH (bnz_w
, MIPS_SI_FTYPE_UV4SI
),
16262 MSA_BUILTIN_TEST_BRANCH (bnz_d
, MIPS_SI_FTYPE_UV2DI
),
16263 MSA_BUILTIN_TEST_BRANCH (bz_b
, MIPS_SI_FTYPE_UV16QI
),
16264 MSA_BUILTIN_TEST_BRANCH (bz_h
, MIPS_SI_FTYPE_UV8HI
),
16265 MSA_BUILTIN_TEST_BRANCH (bz_w
, MIPS_SI_FTYPE_UV4SI
),
16266 MSA_BUILTIN_TEST_BRANCH (bz_d
, MIPS_SI_FTYPE_UV2DI
),
16267 MSA_BUILTIN (ldi_b
, MIPS_V16QI_FTYPE_HI
),
16268 MSA_BUILTIN (ldi_h
, MIPS_V8HI_FTYPE_HI
),
16269 MSA_BUILTIN (ldi_w
, MIPS_V4SI_FTYPE_HI
),
16270 MSA_BUILTIN (ldi_d
, MIPS_V2DI_FTYPE_HI
),
16271 MSA_BUILTIN (fcaf_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16272 MSA_BUILTIN (fcaf_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16273 MSA_BUILTIN (fcor_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16274 MSA_BUILTIN (fcor_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16275 MSA_BUILTIN (fcun_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16276 MSA_BUILTIN (fcun_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16277 MSA_BUILTIN (fcune_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16278 MSA_BUILTIN (fcune_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16279 MSA_BUILTIN (fcueq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16280 MSA_BUILTIN (fcueq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16281 MSA_BUILTIN (fceq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16282 MSA_BUILTIN (fceq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16283 MSA_BUILTIN (fcne_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16284 MSA_BUILTIN (fcne_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16285 MSA_BUILTIN (fclt_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16286 MSA_BUILTIN (fclt_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16287 MSA_BUILTIN (fcult_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16288 MSA_BUILTIN (fcult_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16289 MSA_BUILTIN (fcle_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16290 MSA_BUILTIN (fcle_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16291 MSA_BUILTIN (fcule_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16292 MSA_BUILTIN (fcule_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16293 MSA_BUILTIN (fsaf_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16294 MSA_BUILTIN (fsaf_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16295 MSA_BUILTIN (fsor_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16296 MSA_BUILTIN (fsor_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16297 MSA_BUILTIN (fsun_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16298 MSA_BUILTIN (fsun_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16299 MSA_BUILTIN (fsune_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16300 MSA_BUILTIN (fsune_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16301 MSA_BUILTIN (fsueq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16302 MSA_BUILTIN (fsueq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16303 MSA_BUILTIN (fseq_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16304 MSA_BUILTIN (fseq_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16305 MSA_BUILTIN (fsne_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16306 MSA_BUILTIN (fsne_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16307 MSA_BUILTIN (fslt_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16308 MSA_BUILTIN (fslt_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16309 MSA_BUILTIN (fsult_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16310 MSA_BUILTIN (fsult_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16311 MSA_BUILTIN (fsle_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16312 MSA_BUILTIN (fsle_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16313 MSA_BUILTIN (fsule_w
, MIPS_V4SI_FTYPE_V4SF_V4SF
),
16314 MSA_BUILTIN (fsule_d
, MIPS_V2DI_FTYPE_V2DF_V2DF
),
16315 MSA_BUILTIN (fadd_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16316 MSA_BUILTIN (fadd_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16317 MSA_BUILTIN (fsub_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16318 MSA_BUILTIN (fsub_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16319 MSA_BUILTIN (fmul_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16320 MSA_BUILTIN (fmul_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16321 MSA_BUILTIN (fdiv_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16322 MSA_BUILTIN (fdiv_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16323 MSA_BUILTIN (fmadd_w
, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF
),
16324 MSA_BUILTIN (fmadd_d
, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF
),
16325 MSA_BUILTIN (fmsub_w
, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF
),
16326 MSA_BUILTIN (fmsub_d
, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF
),
16327 MSA_BUILTIN (fexp2_w
, MIPS_V4SF_FTYPE_V4SF_V4SI
),
16328 MSA_BUILTIN (fexp2_d
, MIPS_V2DF_FTYPE_V2DF_V2DI
),
16329 MSA_BUILTIN (fexdo_h
, MIPS_V8HI_FTYPE_V4SF_V4SF
),
16330 MSA_BUILTIN (fexdo_w
, MIPS_V4SF_FTYPE_V2DF_V2DF
),
16331 MSA_BUILTIN (ftq_h
, MIPS_V8HI_FTYPE_V4SF_V4SF
),
16332 MSA_BUILTIN (ftq_w
, MIPS_V4SI_FTYPE_V2DF_V2DF
),
16333 MSA_BUILTIN (fmin_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16334 MSA_BUILTIN (fmin_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16335 MSA_BUILTIN (fmin_a_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16336 MSA_BUILTIN (fmin_a_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16337 MSA_BUILTIN (fmax_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16338 MSA_BUILTIN (fmax_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16339 MSA_BUILTIN (fmax_a_w
, MIPS_V4SF_FTYPE_V4SF_V4SF
),
16340 MSA_BUILTIN (fmax_a_d
, MIPS_V2DF_FTYPE_V2DF_V2DF
),
16341 MSA_BUILTIN (mul_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16342 MSA_BUILTIN (mul_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16343 MSA_BUILTIN (mulr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI
),
16344 MSA_BUILTIN (mulr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI
),
16345 MSA_BUILTIN (madd_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16346 MSA_BUILTIN (madd_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16347 MSA_BUILTIN (maddr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16348 MSA_BUILTIN (maddr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16349 MSA_BUILTIN (msub_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16350 MSA_BUILTIN (msub_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16351 MSA_BUILTIN (msubr_q_h
, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI
),
16352 MSA_BUILTIN (msubr_q_w
, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI
),
16353 MSA_BUILTIN (fclass_w
, MIPS_V4SI_FTYPE_V4SF
),
16354 MSA_BUILTIN (fclass_d
, MIPS_V2DI_FTYPE_V2DF
),
16355 MSA_BUILTIN (fsqrt_w
, MIPS_V4SF_FTYPE_V4SF
),
16356 MSA_BUILTIN (fsqrt_d
, MIPS_V2DF_FTYPE_V2DF
),
16357 MSA_BUILTIN (frcp_w
, MIPS_V4SF_FTYPE_V4SF
),
16358 MSA_BUILTIN (frcp_d
, MIPS_V2DF_FTYPE_V2DF
),
16359 MSA_BUILTIN (frint_w
, MIPS_V4SF_FTYPE_V4SF
),
16360 MSA_BUILTIN (frint_d
, MIPS_V2DF_FTYPE_V2DF
),
16361 MSA_BUILTIN (frsqrt_w
, MIPS_V4SF_FTYPE_V4SF
),
16362 MSA_BUILTIN (frsqrt_d
, MIPS_V2DF_FTYPE_V2DF
),
16363 MSA_BUILTIN (flog2_w
, MIPS_V4SF_FTYPE_V4SF
),
16364 MSA_BUILTIN (flog2_d
, MIPS_V2DF_FTYPE_V2DF
),
16365 MSA_BUILTIN (fexupl_w
, MIPS_V4SF_FTYPE_V8HI
),
16366 MSA_BUILTIN (fexupl_d
, MIPS_V2DF_FTYPE_V4SF
),
16367 MSA_BUILTIN (fexupr_w
, MIPS_V4SF_FTYPE_V8HI
),
16368 MSA_BUILTIN (fexupr_d
, MIPS_V2DF_FTYPE_V4SF
),
16369 MSA_BUILTIN (ffql_w
, MIPS_V4SF_FTYPE_V8HI
),
16370 MSA_BUILTIN (ffql_d
, MIPS_V2DF_FTYPE_V4SI
),
16371 MSA_BUILTIN (ffqr_w
, MIPS_V4SF_FTYPE_V8HI
),
16372 MSA_BUILTIN (ffqr_d
, MIPS_V2DF_FTYPE_V4SI
),
16373 MSA_BUILTIN (ftint_s_w
, MIPS_V4SI_FTYPE_V4SF
),
16374 MSA_BUILTIN (ftint_s_d
, MIPS_V2DI_FTYPE_V2DF
),
16375 MSA_BUILTIN (ftint_u_w
, MIPS_UV4SI_FTYPE_V4SF
),
16376 MSA_BUILTIN (ftint_u_d
, MIPS_UV2DI_FTYPE_V2DF
),
16377 MSA_BUILTIN (ftrunc_s_w
, MIPS_V4SI_FTYPE_V4SF
),
16378 MSA_BUILTIN (ftrunc_s_d
, MIPS_V2DI_FTYPE_V2DF
),
16379 MSA_BUILTIN (ftrunc_u_w
, MIPS_UV4SI_FTYPE_V4SF
),
16380 MSA_BUILTIN (ftrunc_u_d
, MIPS_UV2DI_FTYPE_V2DF
),
16381 MSA_BUILTIN (ffint_s_w
, MIPS_V4SF_FTYPE_V4SI
),
16382 MSA_BUILTIN (ffint_s_d
, MIPS_V2DF_FTYPE_V2DI
),
16383 MSA_BUILTIN (ffint_u_w
, MIPS_V4SF_FTYPE_UV4SI
),
16384 MSA_BUILTIN (ffint_u_d
, MIPS_V2DF_FTYPE_UV2DI
),
16385 MSA_NO_TARGET_BUILTIN (ctcmsa
, MIPS_VOID_FTYPE_UQI_SI
),
16386 MSA_BUILTIN (cfcmsa
, MIPS_SI_FTYPE_UQI
),
16387 MSA_BUILTIN (move_v
, MIPS_V16QI_FTYPE_V16QI
),
16390 /* Index I is the function declaration for mips_builtins[I], or null if the
16391 function isn't defined on this target. */
16392 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
16393 /* Get the index I of the function declaration for mips_builtin_decls[I]
16394 using the instruction code or return null if not defined for the target. */
16395 static GTY(()) int mips_get_builtin_decl_index
[NUM_INSN_CODES
];
16397 /* MODE is a vector mode whose elements have type TYPE. Return the type
16398 of the vector itself. */
16401 mips_builtin_vector_type (tree type
, machine_mode mode
)
16403 static tree types
[2 * (int) MAX_MACHINE_MODE
];
16406 mode_index
= (int) mode
;
16408 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
16409 mode_index
+= MAX_MACHINE_MODE
;
16411 if (types
[mode_index
] == NULL_TREE
)
16412 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
16413 return types
[mode_index
];
16416 /* Return a type for 'const volatile void *'. */
16419 mips_build_cvpointer_type (void)
16423 if (cache
== NULL_TREE
)
16424 cache
= build_pointer_type (build_qualified_type
16426 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
16430 /* Source-level argument types. */
16431 #define MIPS_ATYPE_VOID void_type_node
16432 #define MIPS_ATYPE_INT integer_type_node
16433 #define MIPS_ATYPE_POINTER ptr_type_node
16434 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
16436 /* Standard mode-based argument types. */
16437 #define MIPS_ATYPE_QI intQI_type_node
16438 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
16439 #define MIPS_ATYPE_HI intHI_type_node
16440 #define MIPS_ATYPE_SI intSI_type_node
16441 #define MIPS_ATYPE_USI unsigned_intSI_type_node
16442 #define MIPS_ATYPE_DI intDI_type_node
16443 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
16444 #define MIPS_ATYPE_SF float_type_node
16445 #define MIPS_ATYPE_DF double_type_node
16447 /* Vector argument types. */
16448 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
16449 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
16450 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
16451 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
16452 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
16453 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
16455 #define MIPS_ATYPE_V2DI \
16456 mips_builtin_vector_type (long_long_integer_type_node, V2DImode)
16457 #define MIPS_ATYPE_V4SI mips_builtin_vector_type (intSI_type_node, V4SImode)
16458 #define MIPS_ATYPE_V8HI mips_builtin_vector_type (intHI_type_node, V8HImode)
16459 #define MIPS_ATYPE_V16QI mips_builtin_vector_type (intQI_type_node, V16QImode)
16460 #define MIPS_ATYPE_V2DF mips_builtin_vector_type (double_type_node, V2DFmode)
16461 #define MIPS_ATYPE_V4SF mips_builtin_vector_type (float_type_node, V4SFmode)
16463 #define MIPS_ATYPE_UV2DI \
16464 mips_builtin_vector_type (long_long_unsigned_type_node, V2DImode)
16465 #define MIPS_ATYPE_UV4SI \
16466 mips_builtin_vector_type (unsigned_intSI_type_node, V4SImode)
16467 #define MIPS_ATYPE_UV8HI \
16468 mips_builtin_vector_type (unsigned_intHI_type_node, V8HImode)
16469 #define MIPS_ATYPE_UV16QI \
16470 mips_builtin_vector_type (unsigned_intQI_type_node, V16QImode)
16472 #define MIPS_ATYPE_UV2SI \
16473 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
16474 #define MIPS_ATYPE_UV4HI \
16475 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
16476 #define MIPS_ATYPE_UV8QI \
16477 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
16479 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
16480 their associated MIPS_ATYPEs. */
16481 #define MIPS_FTYPE_ATYPES1(A, B) \
16482 MIPS_ATYPE_##A, MIPS_ATYPE_##B
16484 #define MIPS_FTYPE_ATYPES2(A, B, C) \
16485 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
16487 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
16488 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
16490 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
16491 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
16494 /* Return the function type associated with function prototype TYPE. */
16497 mips_build_function_type (enum mips_function_type type
)
16499 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
16501 if (types
[(int) type
] == NULL_TREE
)
16504 #define DEF_MIPS_FTYPE(NUM, ARGS) \
16505 case MIPS_FTYPE_NAME##NUM ARGS: \
16506 types[(int) type] \
16507 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
16510 #include "config/mips/mips-ftypes.def"
16511 #undef DEF_MIPS_FTYPE
16513 gcc_unreachable ();
16516 return types
[(int) type
];
16519 /* Implement TARGET_INIT_BUILTINS. */
16522 mips_init_builtins (void)
16524 const struct mips_builtin_description
*d
;
16527 /* Iterate through all of the bdesc arrays, initializing all of the
16528 builtin functions. */
16529 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
16531 d
= &mips_builtins
[i
];
16534 mips_builtin_decls
[i
]
16535 = add_builtin_function (d
->name
,
16536 mips_build_function_type (d
->function_type
),
16537 i
, BUILT_IN_MD
, NULL
, NULL
);
16538 mips_get_builtin_decl_index
[d
->icode
] = i
;
16543 /* Implement TARGET_BUILTIN_DECL. */
16546 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
16548 if (code
>= ARRAY_SIZE (mips_builtins
))
16549 return error_mark_node
;
16550 return mips_builtin_decls
[code
];
16553 /* Implement TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION. */
16556 mips_builtin_vectorized_function (unsigned int fn
, tree type_out
, tree type_in
)
16558 machine_mode in_mode
, out_mode
;
16561 if (TREE_CODE (type_out
) != VECTOR_TYPE
16562 || TREE_CODE (type_in
) != VECTOR_TYPE
16566 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
16567 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
16568 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
16569 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
16571 /* INSN is the name of the associated instruction pattern, without
16572 the leading CODE_FOR_. */
16573 #define MIPS_GET_BUILTIN(INSN) \
16574 mips_builtin_decls[mips_get_builtin_decl_index[CODE_FOR_##INSN]]
16578 case BUILT_IN_SQRT
:
16579 if (out_mode
== DFmode
&& out_n
== 2
16580 && in_mode
== DFmode
&& in_n
== 2)
16581 return MIPS_GET_BUILTIN (msa_fsqrt_d
);
16583 case BUILT_IN_SQRTF
:
16584 if (out_mode
== SFmode
&& out_n
== 4
16585 && in_mode
== SFmode
&& in_n
== 4)
16586 return MIPS_GET_BUILTIN (msa_fsqrt_w
);
16595 /* Take argument ARGNO from EXP's argument list and convert it into
16596 an expand operand. Store the operand in *OP. */
16599 mips_prepare_builtin_arg (struct expand_operand
*op
, tree exp
,
16600 unsigned int argno
)
16605 arg
= CALL_EXPR_ARG (exp
, argno
);
16606 value
= expand_normal (arg
);
16607 create_input_operand (op
, value
, TYPE_MODE (TREE_TYPE (arg
)));
16610 /* Expand instruction ICODE as part of a built-in function sequence.
16611 Use the first NOPS elements of OPS as the instruction's operands.
16612 HAS_TARGET_P is true if operand 0 is a target; it is false if the
16613 instruction has no target.
16615 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
16618 mips_expand_builtin_insn (enum insn_code icode
, unsigned int nops
,
16619 struct expand_operand
*ops
, bool has_target_p
)
16621 machine_mode imode
;
16622 int rangelo
= 0, rangehi
= 0, error_opno
= 0;
16627 /* The third operand of these instructions is in SImode, so we need to
16628 bring the corresponding builtin argument from QImode into SImode. */
16629 case CODE_FOR_loongson_pshufh
:
16630 case CODE_FOR_loongson_psllh
:
16631 case CODE_FOR_loongson_psllw
:
16632 case CODE_FOR_loongson_psrah
:
16633 case CODE_FOR_loongson_psraw
:
16634 case CODE_FOR_loongson_psrlh
:
16635 case CODE_FOR_loongson_psrlw
:
16636 gcc_assert (has_target_p
&& nops
== 3 && ops
[2].mode
== QImode
);
16637 sireg
= gen_reg_rtx (SImode
);
16638 emit_insn (gen_zero_extendqisi2 (sireg
,
16639 force_reg (QImode
, ops
[2].value
)));
16640 ops
[2].value
= sireg
;
16641 ops
[2].mode
= SImode
;
16644 case CODE_FOR_msa_addvi_b
:
16645 case CODE_FOR_msa_addvi_h
:
16646 case CODE_FOR_msa_addvi_w
:
16647 case CODE_FOR_msa_addvi_d
:
16648 case CODE_FOR_msa_clti_u_b
:
16649 case CODE_FOR_msa_clti_u_h
:
16650 case CODE_FOR_msa_clti_u_w
:
16651 case CODE_FOR_msa_clti_u_d
:
16652 case CODE_FOR_msa_clei_u_b
:
16653 case CODE_FOR_msa_clei_u_h
:
16654 case CODE_FOR_msa_clei_u_w
:
16655 case CODE_FOR_msa_clei_u_d
:
16656 case CODE_FOR_msa_maxi_u_b
:
16657 case CODE_FOR_msa_maxi_u_h
:
16658 case CODE_FOR_msa_maxi_u_w
:
16659 case CODE_FOR_msa_maxi_u_d
:
16660 case CODE_FOR_msa_mini_u_b
:
16661 case CODE_FOR_msa_mini_u_h
:
16662 case CODE_FOR_msa_mini_u_w
:
16663 case CODE_FOR_msa_mini_u_d
:
16664 case CODE_FOR_msa_subvi_b
:
16665 case CODE_FOR_msa_subvi_h
:
16666 case CODE_FOR_msa_subvi_w
:
16667 case CODE_FOR_msa_subvi_d
:
16668 gcc_assert (has_target_p
&& nops
== 3);
16669 /* We only generate a vector of constants iff the second argument
16670 is an immediate. We also validate the range of the immediate. */
16671 if (CONST_INT_P (ops
[2].value
))
16675 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16677 ops
[2].mode
= ops
[0].mode
;
16678 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16679 INTVAL (ops
[2].value
));
16686 case CODE_FOR_msa_ceqi_b
:
16687 case CODE_FOR_msa_ceqi_h
:
16688 case CODE_FOR_msa_ceqi_w
:
16689 case CODE_FOR_msa_ceqi_d
:
16690 case CODE_FOR_msa_clti_s_b
:
16691 case CODE_FOR_msa_clti_s_h
:
16692 case CODE_FOR_msa_clti_s_w
:
16693 case CODE_FOR_msa_clti_s_d
:
16694 case CODE_FOR_msa_clei_s_b
:
16695 case CODE_FOR_msa_clei_s_h
:
16696 case CODE_FOR_msa_clei_s_w
:
16697 case CODE_FOR_msa_clei_s_d
:
16698 case CODE_FOR_msa_maxi_s_b
:
16699 case CODE_FOR_msa_maxi_s_h
:
16700 case CODE_FOR_msa_maxi_s_w
:
16701 case CODE_FOR_msa_maxi_s_d
:
16702 case CODE_FOR_msa_mini_s_b
:
16703 case CODE_FOR_msa_mini_s_h
:
16704 case CODE_FOR_msa_mini_s_w
:
16705 case CODE_FOR_msa_mini_s_d
:
16706 gcc_assert (has_target_p
&& nops
== 3);
16707 /* We only generate a vector of constants iff the second argument
16708 is an immediate. We also validate the range of the immediate. */
16709 if (CONST_INT_P (ops
[2].value
))
16713 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16715 ops
[2].mode
= ops
[0].mode
;
16716 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16717 INTVAL (ops
[2].value
));
16724 case CODE_FOR_msa_andi_b
:
16725 case CODE_FOR_msa_ori_b
:
16726 case CODE_FOR_msa_nori_b
:
16727 case CODE_FOR_msa_xori_b
:
16728 gcc_assert (has_target_p
&& nops
== 3);
16729 if (!CONST_INT_P (ops
[2].value
))
16731 ops
[2].mode
= ops
[0].mode
;
16732 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16733 INTVAL (ops
[2].value
));
16736 case CODE_FOR_msa_bmzi_b
:
16737 case CODE_FOR_msa_bmnzi_b
:
16738 case CODE_FOR_msa_bseli_b
:
16739 gcc_assert (has_target_p
&& nops
== 4);
16740 if (!CONST_INT_P (ops
[3].value
))
16742 ops
[3].mode
= ops
[0].mode
;
16743 ops
[3].value
= mips_gen_const_int_vector (ops
[3].mode
,
16744 INTVAL (ops
[3].value
));
16747 case CODE_FOR_msa_fill_b
:
16748 case CODE_FOR_msa_fill_h
:
16749 case CODE_FOR_msa_fill_w
:
16750 case CODE_FOR_msa_fill_d
:
16751 /* Map the built-ins to vector fill operations. We need fix up the mode
16752 for the element being inserted. */
16753 gcc_assert (has_target_p
&& nops
== 2);
16754 imode
= GET_MODE_INNER (ops
[0].mode
);
16755 ops
[1].value
= lowpart_subreg (imode
, ops
[1].value
, ops
[1].mode
);
16756 ops
[1].mode
= imode
;
16759 case CODE_FOR_msa_ilvl_b
:
16760 case CODE_FOR_msa_ilvl_h
:
16761 case CODE_FOR_msa_ilvl_w
:
16762 case CODE_FOR_msa_ilvl_d
:
16763 case CODE_FOR_msa_ilvr_b
:
16764 case CODE_FOR_msa_ilvr_h
:
16765 case CODE_FOR_msa_ilvr_w
:
16766 case CODE_FOR_msa_ilvr_d
:
16767 case CODE_FOR_msa_ilvev_b
:
16768 case CODE_FOR_msa_ilvev_h
:
16769 case CODE_FOR_msa_ilvev_w
:
16770 case CODE_FOR_msa_ilvod_b
:
16771 case CODE_FOR_msa_ilvod_h
:
16772 case CODE_FOR_msa_ilvod_w
:
16773 case CODE_FOR_msa_pckev_b
:
16774 case CODE_FOR_msa_pckev_h
:
16775 case CODE_FOR_msa_pckev_w
:
16776 case CODE_FOR_msa_pckod_b
:
16777 case CODE_FOR_msa_pckod_h
:
16778 case CODE_FOR_msa_pckod_w
:
16779 /* Swap the operands 1 and 2 for interleave operations. Built-ins follow
16780 convention of ISA, which have op1 as higher component and op2 as lower
16781 component. However, the VEC_PERM op in tree and vec_concat in RTL
16782 expects first operand to be lower component, because of which this
16783 swap is needed for builtins. */
16784 gcc_assert (has_target_p
&& nops
== 3);
16785 std::swap (ops
[1], ops
[2]);
16788 case CODE_FOR_msa_slli_b
:
16789 case CODE_FOR_msa_slli_h
:
16790 case CODE_FOR_msa_slli_w
:
16791 case CODE_FOR_msa_slli_d
:
16792 case CODE_FOR_msa_srai_b
:
16793 case CODE_FOR_msa_srai_h
:
16794 case CODE_FOR_msa_srai_w
:
16795 case CODE_FOR_msa_srai_d
:
16796 case CODE_FOR_msa_srli_b
:
16797 case CODE_FOR_msa_srli_h
:
16798 case CODE_FOR_msa_srli_w
:
16799 case CODE_FOR_msa_srli_d
:
16800 gcc_assert (has_target_p
&& nops
== 3);
16801 if (CONST_INT_P (ops
[2].value
))
16804 rangehi
= GET_MODE_UNIT_BITSIZE (ops
[0].mode
) - 1;
16805 if (IN_RANGE (INTVAL (ops
[2].value
), rangelo
, rangehi
))
16807 ops
[2].mode
= ops
[0].mode
;
16808 ops
[2].value
= mips_gen_const_int_vector (ops
[2].mode
,
16809 INTVAL (ops
[2].value
));
16816 case CODE_FOR_msa_insert_b
:
16817 case CODE_FOR_msa_insert_h
:
16818 case CODE_FOR_msa_insert_w
:
16819 case CODE_FOR_msa_insert_d
:
16820 /* Map the built-ins to insert operations. We need to swap operands,
16821 fix up the mode for the element being inserted, and generate
16822 a bit mask for vec_merge. */
16823 gcc_assert (has_target_p
&& nops
== 4);
16824 std::swap (ops
[1], ops
[2]);
16825 std::swap (ops
[1], ops
[3]);
16826 imode
= GET_MODE_INNER (ops
[0].mode
);
16827 ops
[1].value
= lowpart_subreg (imode
, ops
[1].value
, ops
[1].mode
);
16828 ops
[1].mode
= imode
;
16830 rangehi
= GET_MODE_NUNITS (ops
[0].mode
) - 1;
16831 if (CONST_INT_P (ops
[3].value
)
16832 && IN_RANGE (INTVAL (ops
[3].value
), rangelo
, rangehi
))
16833 ops
[3].value
= GEN_INT (1 << INTVAL (ops
[3].value
));
16838 case CODE_FOR_msa_insve_b
:
16839 case CODE_FOR_msa_insve_h
:
16840 case CODE_FOR_msa_insve_w
:
16841 case CODE_FOR_msa_insve_d
:
16842 /* Map the built-ins to element insert operations. We need to swap
16843 operands and generate a bit mask. */
16844 gcc_assert (has_target_p
&& nops
== 4);
16845 std::swap (ops
[1], ops
[2]);
16846 std::swap (ops
[1], ops
[3]);
16848 rangehi
= GET_MODE_NUNITS (ops
[0].mode
) - 1;
16849 if (CONST_INT_P (ops
[3].value
)
16850 && IN_RANGE (INTVAL (ops
[3].value
), rangelo
, rangehi
))
16851 ops
[3].value
= GEN_INT (1 << INTVAL (ops
[3].value
));
16856 case CODE_FOR_msa_shf_b
:
16857 case CODE_FOR_msa_shf_h
:
16858 case CODE_FOR_msa_shf_w
:
16859 case CODE_FOR_msa_shf_w_f
:
16860 gcc_assert (has_target_p
&& nops
== 3);
16861 ops
[2].value
= mips_gen_const_int_vector_shuffle (ops
[0].mode
,
16862 INTVAL (ops
[2].value
));
16865 case CODE_FOR_msa_vshf_b
:
16866 case CODE_FOR_msa_vshf_h
:
16867 case CODE_FOR_msa_vshf_w
:
16868 case CODE_FOR_msa_vshf_d
:
16869 gcc_assert (has_target_p
&& nops
== 4);
16870 std::swap (ops
[1], ops
[3]);
16877 if (error_opno
!= 0)
16879 error ("argument %d to the built-in must be a constant"
16880 " in range %d to %d", error_opno
, rangelo
, rangehi
);
16881 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
16883 else if (!maybe_expand_insn (icode
, nops
, ops
))
16885 error ("invalid argument to built-in function");
16886 return has_target_p
? gen_reg_rtx (ops
[0].mode
) : const0_rtx
;
16888 return has_target_p
? ops
[0].value
: const0_rtx
;
16891 /* Expand a floating-point comparison for built-in function call EXP.
16892 The first NARGS arguments are the values to be compared. ICODE is
16893 the .md pattern that does the comparison and COND is the condition
16894 that is being tested. Return an rtx for the result. */
16897 mips_expand_builtin_compare_1 (enum insn_code icode
,
16898 enum mips_fp_condition cond
,
16899 tree exp
, int nargs
)
16901 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
16905 /* The instruction should have a target operand, an operand for each
16906 argument, and an operand for COND. */
16907 gcc_assert (nargs
+ 2 == insn_data
[(int) icode
].n_generator_args
);
16909 output
= mips_allocate_fcc (insn_data
[(int) icode
].operand
[0].mode
);
16911 create_fixed_operand (&ops
[opno
++], output
);
16912 for (argno
= 0; argno
< nargs
; argno
++)
16913 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
16914 create_integer_operand (&ops
[opno
++], (int) cond
);
16915 return mips_expand_builtin_insn (icode
, opno
, ops
, true);
16918 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
16919 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
16920 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
16921 suggests a good place to put the result. */
16924 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
16927 struct expand_operand ops
[MAX_RECOG_OPERANDS
];
16930 /* Map any target to operand 0. */
16933 create_output_operand (&ops
[opno
++], target
, TYPE_MODE (TREE_TYPE (exp
)));
16935 /* Map the arguments to the other operands. */
16936 gcc_assert (opno
+ call_expr_nargs (exp
)
16937 == insn_data
[icode
].n_generator_args
);
16938 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
16939 mips_prepare_builtin_arg (&ops
[opno
++], exp
, argno
);
16941 return mips_expand_builtin_insn (icode
, opno
, ops
, has_target_p
);
16944 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
16945 function; TYPE says which. EXP is the CALL_EXPR that calls the
16946 function, ICODE is the instruction that should be used to compare
16947 the first two arguments, and COND is the condition it should test.
16948 TARGET, if nonnull, suggests a good place to put the result. */
16951 mips_expand_builtin_movtf (enum mips_builtin_type type
,
16952 enum insn_code icode
, enum mips_fp_condition cond
,
16953 rtx target
, tree exp
)
16955 struct expand_operand ops
[4];
16958 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
, 2);
16959 create_output_operand (&ops
[0], target
, TYPE_MODE (TREE_TYPE (exp
)));
16960 if (type
== MIPS_BUILTIN_MOVT
)
16962 mips_prepare_builtin_arg (&ops
[2], exp
, 2);
16963 mips_prepare_builtin_arg (&ops
[1], exp
, 3);
16967 mips_prepare_builtin_arg (&ops
[1], exp
, 2);
16968 mips_prepare_builtin_arg (&ops
[2], exp
, 3);
16970 create_fixed_operand (&ops
[3], cmp_result
);
16971 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps
,
16975 /* Expand an MSA built-in for a compare and branch instruction specified by
16976 ICODE, set a general-purpose register to 1 if the branch was taken,
16980 mips_expand_builtin_msa_test_branch (enum insn_code icode
, tree exp
)
16982 struct expand_operand ops
[3];
16984 rtx_code_label
*true_label
, *done_label
;
16987 true_label
= gen_label_rtx ();
16988 done_label
= gen_label_rtx ();
16990 create_input_operand (&ops
[0], true_label
, TYPE_MODE (TREE_TYPE (exp
)));
16991 mips_prepare_builtin_arg (&ops
[1], exp
, 0);
16992 create_fixed_operand (&ops
[2], const0_rtx
);
16994 /* Make sure that the operand 1 is a REG. */
16995 if (GET_CODE (ops
[1].value
) != REG
)
16996 ops
[1].value
= force_reg (ops
[1].mode
, ops
[1].value
);
16998 if ((cbranch
= maybe_gen_insn (icode
, 3, ops
)) == NULL_RTX
)
16999 error ("failed to expand built-in function");
17001 cmp_result
= gen_reg_rtx (SImode
);
17003 /* First assume that CMP_RESULT is false. */
17004 mips_emit_move (cmp_result
, const0_rtx
);
17006 /* Branch to TRUE_LABEL if CBRANCH is taken and DONE_LABEL otherwise. */
17007 emit_jump_insn (cbranch
);
17008 emit_jump_insn (gen_jump (done_label
));
17011 /* Set CMP_RESULT to true if the branch was taken. */
17012 emit_label (true_label
);
17013 mips_emit_move (cmp_result
, const1_rtx
);
17015 emit_label (done_label
);
17019 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
17020 into TARGET otherwise. Return TARGET. */
17023 mips_builtin_branch_and_move (rtx condition
, rtx target
,
17024 rtx value_if_true
, rtx value_if_false
)
17026 rtx_code_label
*true_label
, *done_label
;
17028 true_label
= gen_label_rtx ();
17029 done_label
= gen_label_rtx ();
17031 /* First assume that CONDITION is false. */
17032 mips_emit_move (target
, value_if_false
);
17034 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
17035 emit_jump_insn (gen_condjump (condition
, true_label
));
17036 emit_jump_insn (gen_jump (done_label
));
17039 /* Fix TARGET if CONDITION is true. */
17040 emit_label (true_label
);
17041 mips_emit_move (target
, value_if_true
);
17043 emit_label (done_label
);
17047 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
17048 the CALL_EXPR that calls the function, ICODE is the code of the
17049 comparison instruction, and COND is the condition it should test.
17050 TARGET, if nonnull, suggests a good place to put the boolean result. */
17053 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
17054 enum insn_code icode
, enum mips_fp_condition cond
,
17055 rtx target
, tree exp
)
17057 rtx offset
, condition
, cmp_result
;
17059 if (target
== 0 || GET_MODE (target
) != SImode
)
17060 target
= gen_reg_rtx (SImode
);
17061 cmp_result
= mips_expand_builtin_compare_1 (icode
, cond
, exp
,
17062 call_expr_nargs (exp
));
17064 /* If the comparison sets more than one register, we define the result
17065 to be 0 if all registers are false and -1 if all registers are true.
17066 The value of the complete result is indeterminate otherwise. */
17067 switch (builtin_type
)
17069 case MIPS_BUILTIN_CMP_ALL
:
17070 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
17071 return mips_builtin_branch_and_move (condition
, target
,
17072 const0_rtx
, const1_rtx
);
17074 case MIPS_BUILTIN_CMP_UPPER
:
17075 case MIPS_BUILTIN_CMP_LOWER
:
17076 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
17077 condition
= gen_single_cc (cmp_result
, offset
);
17078 return mips_builtin_branch_and_move (condition
, target
,
17079 const1_rtx
, const0_rtx
);
17082 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
17083 return mips_builtin_branch_and_move (condition
, target
,
17084 const1_rtx
, const0_rtx
);
17088 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
17089 if nonnull, suggests a good place to put the boolean result. */
17092 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
17094 rtx condition
, cmp_result
;
17097 if (target
== 0 || GET_MODE (target
) != SImode
)
17098 target
= gen_reg_rtx (SImode
);
17100 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
17102 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
17107 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
17108 return mips_builtin_branch_and_move (condition
, target
,
17109 const1_rtx
, const0_rtx
);
17112 /* Implement TARGET_EXPAND_BUILTIN. */
17115 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
17116 machine_mode mode
, int ignore
)
17119 unsigned int fcode
, avail
;
17120 const struct mips_builtin_description
*d
;
17122 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
17123 fcode
= DECL_FUNCTION_CODE (fndecl
);
17124 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
17125 d
= &mips_builtins
[fcode
];
17126 avail
= d
->avail ();
17127 gcc_assert (avail
!= 0);
17128 if (TARGET_MIPS16
&& !(avail
& BUILTIN_AVAIL_MIPS16
))
17130 error ("built-in function %qE not supported for MIPS16",
17131 DECL_NAME (fndecl
));
17132 return ignore
? const0_rtx
: CONST0_RTX (mode
);
17134 switch (d
->builtin_type
)
17136 case MIPS_BUILTIN_DIRECT
:
17137 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
17139 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
17140 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
17142 case MIPS_BUILTIN_MOVT
:
17143 case MIPS_BUILTIN_MOVF
:
17144 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
17145 d
->cond
, target
, exp
);
17147 case MIPS_BUILTIN_CMP_ANY
:
17148 case MIPS_BUILTIN_CMP_ALL
:
17149 case MIPS_BUILTIN_CMP_UPPER
:
17150 case MIPS_BUILTIN_CMP_LOWER
:
17151 case MIPS_BUILTIN_CMP_SINGLE
:
17152 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
17153 d
->cond
, target
, exp
);
17155 case MIPS_BUILTIN_MSA_TEST_BRANCH
:
17156 return mips_expand_builtin_msa_test_branch (d
->icode
, exp
);
17158 case MIPS_BUILTIN_BPOSGE32
:
17159 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
17161 gcc_unreachable ();
17164 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
17165 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
17166 struct mips16_constant
{
17167 struct mips16_constant
*next
;
17169 rtx_code_label
*label
;
17173 /* Information about an incomplete MIPS16 constant pool. FIRST is the
17174 first constant, HIGHEST_ADDRESS is the highest address that the first
17175 byte of the pool can have, and INSN_ADDRESS is the current instruction
17177 struct mips16_constant_pool
{
17178 struct mips16_constant
*first
;
17179 int highest_address
;
17183 /* Add constant VALUE to POOL and return its label. MODE is the
17184 value's mode (used for CONST_INTs, etc.). */
17186 static rtx_code_label
*
17187 mips16_add_constant (struct mips16_constant_pool
*pool
,
17188 rtx value
, machine_mode mode
)
17190 struct mips16_constant
**p
, *c
;
17191 bool first_of_size_p
;
17193 /* See whether the constant is already in the pool. If so, return the
17194 existing label, otherwise leave P pointing to the place where the
17195 constant should be added.
17197 Keep the pool sorted in increasing order of mode size so that we can
17198 reduce the number of alignments needed. */
17199 first_of_size_p
= true;
17200 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
17202 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
17203 return (*p
)->label
;
17204 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
17206 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
17207 first_of_size_p
= false;
17210 /* In the worst case, the constant needed by the earliest instruction
17211 will end up at the end of the pool. The entire pool must then be
17212 accessible from that instruction.
17214 When adding the first constant, set the pool's highest address to
17215 the address of the first out-of-range byte. Adjust this address
17216 downwards each time a new constant is added. */
17217 if (pool
->first
== 0)
17218 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
17219 of the instruction with the lowest two bits clear. The base PC
17220 value for LDPC has the lowest three bits clear. Assume the worst
17221 case here; namely that the PC-relative instruction occupies the
17222 last 2 bytes in an aligned word. */
17223 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
17224 pool
->highest_address
-= GET_MODE_SIZE (mode
);
17225 if (first_of_size_p
)
17226 /* Take into account the worst possible padding due to alignment. */
17227 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
17229 /* Create a new entry. */
17230 c
= XNEW (struct mips16_constant
);
17233 c
->label
= gen_label_rtx ();
17240 /* Output constant VALUE after instruction INSN and return the last
17241 instruction emitted. MODE is the mode of the constant. */
17244 mips16_emit_constants_1 (machine_mode mode
, rtx value
, rtx_insn
*insn
)
17246 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
17248 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
17249 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
17252 if (SCALAR_FLOAT_MODE_P (mode
))
17253 return emit_insn_after (gen_consttable_float (value
), insn
);
17255 if (VECTOR_MODE_P (mode
))
17259 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
17260 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
17261 CONST_VECTOR_ELT (value
, i
), insn
);
17265 gcc_unreachable ();
17268 /* Dump out the constants in CONSTANTS after INSN. Record the initial
17269 label number in the `consttable' and `consttable_end' insns emitted
17270 at the beginning and the end of the constant pool respectively, so
17271 that individual pools can be uniquely marked as data for the purpose
17275 mips16_emit_constants (struct mips16_constant
*constants
, rtx_insn
*insn
)
17277 int label_num
= constants
? CODE_LABEL_NUMBER (constants
->label
) : 0;
17278 struct mips16_constant
*c
, *next
;
17283 insn
= emit_insn_after (gen_consttable (GEN_INT (label_num
)), insn
);
17284 for (c
= constants
; c
!= NULL
; c
= next
)
17286 /* If necessary, increase the alignment of PC. */
17287 if (align
< GET_MODE_SIZE (c
->mode
))
17289 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
17290 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
17292 align
= GET_MODE_SIZE (c
->mode
);
17294 insn
= emit_label_after (c
->label
, insn
);
17295 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
17301 insn
= emit_insn_after (gen_consttable_end (GEN_INT (label_num
)), insn
);
17303 emit_barrier_after (insn
);
17306 /* Return the length of instruction INSN. */
17309 mips16_insn_length (rtx_insn
*insn
)
17311 if (JUMP_TABLE_DATA_P (insn
))
17313 rtx body
= PATTERN (insn
);
17314 if (GET_CODE (body
) == ADDR_VEC
)
17315 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
17316 else if (GET_CODE (body
) == ADDR_DIFF_VEC
)
17317 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
17319 gcc_unreachable ();
17321 return get_attr_length (insn
);
17324 /* If *X is a symbolic constant that refers to the constant pool, add
17325 the constant to POOL and rewrite *X to use the constant's label. */
17328 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
17331 rtx_code_label
*label
;
17333 split_const (*x
, &base
, &offset
);
17334 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
17336 label
= mips16_add_constant (pool
, copy_rtx (get_pool_constant (base
)),
17337 get_pool_mode (base
));
17338 base
= gen_rtx_LABEL_REF (Pmode
, label
);
17339 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
17343 /* Rewrite INSN so that constant pool references refer to the constant's
17347 mips16_rewrite_pool_refs (rtx_insn
*insn
, struct mips16_constant_pool
*pool
)
17349 subrtx_ptr_iterator::array_type array
;
17350 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), ALL
)
17354 if (force_to_mem_operand (*loc
, Pmode
))
17356 rtx mem
= force_const_mem (GET_MODE (*loc
), *loc
);
17357 validate_change (insn
, loc
, mem
, false);
17362 mips16_rewrite_pool_constant (pool
, &XEXP (*loc
, 0));
17363 iter
.skip_subrtxes ();
17367 if (TARGET_MIPS16_TEXT_LOADS
)
17368 mips16_rewrite_pool_constant (pool
, loc
);
17369 if (GET_CODE (*loc
) == CONST
17370 /* Don't rewrite the __mips16_rdwr symbol. */
17371 || (GET_CODE (*loc
) == UNSPEC
17372 && XINT (*loc
, 1) == UNSPEC_TLS_GET_TP
))
17373 iter
.skip_subrtxes ();
17378 /* Return whether CFG is used in mips_reorg. */
17381 mips_cfg_in_reorg (void)
17383 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
17384 || TARGET_RELAX_PIC_CALLS
);
17387 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
17388 otherwise assume that they are already split. */
17391 mips16_lay_out_constants (bool split_p
)
17393 struct mips16_constant_pool pool
;
17394 rtx_insn
*insn
, *barrier
;
17396 if (!TARGET_MIPS16_PCREL_LOADS
)
17401 if (mips_cfg_in_reorg ())
17402 split_all_insns ();
17404 split_all_insns_noflow ();
17407 memset (&pool
, 0, sizeof (pool
));
17408 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17410 /* Rewrite constant pool references in INSN. */
17411 if (USEFUL_INSN_P (insn
))
17412 mips16_rewrite_pool_refs (insn
, &pool
);
17414 pool
.insn_address
+= mips16_insn_length (insn
);
17416 if (pool
.first
!= NULL
)
17418 /* If there are no natural barriers between the first user of
17419 the pool and the highest acceptable address, we'll need to
17420 create a new instruction to jump around the constant pool.
17421 In the worst case, this instruction will be 4 bytes long.
17423 If it's too late to do this transformation after INSN,
17424 do it immediately before INSN. */
17425 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
17427 rtx_code_label
*label
;
17430 label
= gen_label_rtx ();
17432 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
17433 JUMP_LABEL (jump
) = label
;
17434 LABEL_NUSES (label
) = 1;
17435 barrier
= emit_barrier_after (jump
);
17437 emit_label_after (label
, barrier
);
17438 pool
.insn_address
+= 4;
17441 /* See whether the constant pool is now out of range of the first
17442 user. If so, output the constants after the previous barrier.
17443 Note that any instructions between BARRIER and INSN (inclusive)
17444 will use negative offsets to refer to the pool. */
17445 if (pool
.insn_address
> pool
.highest_address
)
17447 mips16_emit_constants (pool
.first
, barrier
);
17451 else if (BARRIER_P (insn
))
17455 mips16_emit_constants (pool
.first
, get_last_insn ());
17458 /* Return true if it is worth r10k_simplify_address's while replacing
17459 an address with X. We are looking for constants, and for addresses
17460 at a known offset from the incoming stack pointer. */
17463 r10k_simplified_address_p (rtx x
)
17465 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
17467 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
17470 /* X is an expression that appears in INSN. Try to use the UD chains
17471 to simplify it, returning the simplified form on success and the
17472 original form otherwise. Replace the incoming value of $sp with
17473 virtual_incoming_args_rtx (which should never occur in X otherwise). */
17476 r10k_simplify_address (rtx x
, rtx_insn
*insn
)
17478 rtx newx
, op0
, op1
, set
, note
;
17479 rtx_insn
*def_insn
;
17481 struct df_link
*defs
;
17486 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17487 if (op0
!= XEXP (x
, 0))
17488 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
17489 op0
, GET_MODE (XEXP (x
, 0)));
17491 else if (BINARY_P (x
))
17493 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17494 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
17495 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
17496 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
17498 else if (GET_CODE (x
) == LO_SUM
)
17500 /* LO_SUMs can be offset from HIGHs, if we know they won't
17501 overflow. See mips_classify_address for the rationale behind
17503 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
17504 if (GET_CODE (op0
) == HIGH
)
17505 newx
= XEXP (x
, 1);
17507 else if (REG_P (x
))
17509 /* Uses are recorded by regno_reg_rtx, not X itself. */
17510 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
17512 defs
= DF_REF_CHAIN (use
);
17514 /* Require a single definition. */
17515 if (defs
&& defs
->next
== NULL
)
17518 if (DF_REF_IS_ARTIFICIAL (def
))
17520 /* Replace the incoming value of $sp with
17521 virtual_incoming_args_rtx. */
17522 if (x
== stack_pointer_rtx
17523 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR_FOR_FN (cfun
))
17524 newx
= virtual_incoming_args_rtx
;
17526 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
17529 /* Make sure that DEF_INSN is a single set of REG. */
17530 def_insn
= DF_REF_INSN (def
);
17531 if (NONJUMP_INSN_P (def_insn
))
17533 set
= single_set (def_insn
);
17534 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
17536 /* Prefer to use notes, since the def-use chains
17537 are often shorter. */
17538 note
= find_reg_equal_equiv_note (def_insn
);
17540 newx
= XEXP (note
, 0);
17542 newx
= SET_SRC (set
);
17543 newx
= r10k_simplify_address (newx
, def_insn
);
17549 if (newx
&& r10k_simplified_address_p (newx
))
17554 /* Return true if ADDRESS is known to be an uncached address
17555 on R10K systems. */
17558 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
17560 unsigned HOST_WIDE_INT upper
;
17562 /* Check for KSEG1. */
17563 if (address
+ 0x60000000 < 0x20000000)
17566 /* Check for uncached XKPHYS addresses. */
17567 if (Pmode
== DImode
)
17569 upper
= (address
>> 40) & 0xf9ffff;
17570 if (upper
== 0x900000 || upper
== 0xb80000)
17576 /* Return true if we can prove that an access to address X in instruction
17577 INSN would be safe from R10K speculation. This X is a general
17578 expression; it might not be a legitimate address. */
17581 r10k_safe_address_p (rtx x
, rtx_insn
*insn
)
17584 HOST_WIDE_INT offset_val
;
17586 x
= r10k_simplify_address (x
, insn
);
17588 /* Check for references to the stack frame. It doesn't really matter
17589 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
17590 allows us to assume that accesses to any part of the eventual frame
17591 is safe from speculation at any point in the function. */
17592 mips_split_plus (x
, &base
, &offset_val
);
17593 if (base
== virtual_incoming_args_rtx
17594 && offset_val
>= -cfun
->machine
->frame
.total_size
17595 && offset_val
< cfun
->machine
->frame
.args_size
)
17598 /* Check for uncached addresses. */
17599 if (CONST_INT_P (x
))
17600 return r10k_uncached_address_p (INTVAL (x
));
17602 /* Check for accesses to a static object. */
17603 split_const (x
, &base
, &offset
);
17604 return offset_within_block_p (base
, INTVAL (offset
));
17607 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
17608 an in-range access to an automatic variable, or to an object with
17609 a link-time-constant address. */
17612 r10k_safe_mem_expr_p (tree expr
, unsigned HOST_WIDE_INT offset
)
17614 HOST_WIDE_INT bitoffset
, bitsize
;
17615 tree inner
, var_offset
;
17617 int unsigned_p
, reverse_p
, volatile_p
;
17619 inner
= get_inner_reference (expr
, &bitsize
, &bitoffset
, &var_offset
, &mode
,
17620 &unsigned_p
, &reverse_p
, &volatile_p
);
17621 if (!DECL_P (inner
) || !DECL_SIZE_UNIT (inner
) || var_offset
)
17624 offset
+= bitoffset
/ BITS_PER_UNIT
;
17625 return offset
< tree_to_uhwi (DECL_SIZE_UNIT (inner
));
17628 /* Return true if X contains a MEM that is not safe from R10K speculation.
17629 INSN is the instruction that contains X. */
17632 r10k_needs_protection_p_1 (rtx x
, rtx_insn
*insn
)
17634 subrtx_var_iterator::array_type array
;
17635 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, NONCONST
)
17640 if ((MEM_EXPR (mem
)
17641 && MEM_OFFSET_KNOWN_P (mem
)
17642 && r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
17643 || r10k_safe_address_p (XEXP (mem
, 0), insn
))
17644 iter
.skip_subrtxes ();
17652 /* A note_stores callback for which DATA points to an instruction pointer.
17653 If *DATA is nonnull, make it null if it X contains a MEM that is not
17654 safe from R10K speculation. */
17657 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
17660 rtx_insn
**insn_ptr
;
17662 insn_ptr
= (rtx_insn
**) data
;
17663 if (*insn_ptr
&& r10k_needs_protection_p_1 (x
, *insn_ptr
))
17667 /* X is the pattern of a call instruction. Return true if the call is
17668 not to a declared function. */
17671 r10k_needs_protection_p_call (const_rtx x
)
17673 subrtx_iterator::array_type array
;
17674 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
17676 const_rtx mem
= *iter
;
17679 const_rtx addr
= XEXP (mem
, 0);
17680 if (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_DECL (addr
))
17681 iter
.skip_subrtxes ();
17689 /* Return true if instruction INSN needs to be protected by an R10K
17693 r10k_needs_protection_p (rtx_insn
*insn
)
17696 return r10k_needs_protection_p_call (PATTERN (insn
));
17698 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
17700 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
17701 return insn
== NULL_RTX
;
17704 return r10k_needs_protection_p_1 (PATTERN (insn
), insn
);
17707 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
17708 edge is unconditional. */
17711 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
17716 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
17717 if (!single_succ_p (e
->src
)
17718 || !bitmap_bit_p (protected_bbs
, e
->src
->index
)
17719 || (e
->flags
& EDGE_COMPLEX
) != 0)
17724 /* Implement -mr10k-cache-barrier= for the current function. */
17727 r10k_insert_cache_barriers (void)
17729 int *rev_post_order
;
17732 sbitmap protected_bbs
;
17733 rtx_insn
*insn
, *end
;
17734 rtx unprotected_region
;
17738 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
17742 /* Calculate dominators. */
17743 calculate_dominance_info (CDI_DOMINATORS
);
17745 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
17746 X is protected by a cache barrier. */
17747 protected_bbs
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
17748 bitmap_clear (protected_bbs
);
17750 /* Iterate over the basic blocks in reverse post-order. */
17751 rev_post_order
= XNEWVEC (int, last_basic_block_for_fn (cfun
));
17752 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
17753 for (i
= 0; i
< n
; i
++)
17755 bb
= BASIC_BLOCK_FOR_FN (cfun
, rev_post_order
[i
]);
17757 /* If this block is only reached by unconditional edges, and if the
17758 source of every edge is protected, the beginning of the block is
17760 if (r10k_protected_bb_p (bb
, protected_bbs
))
17761 unprotected_region
= NULL_RTX
;
17763 unprotected_region
= pc_rtx
;
17764 end
= NEXT_INSN (BB_END (bb
));
17766 /* UNPROTECTED_REGION is:
17768 - null if we are processing a protected region,
17769 - pc_rtx if we are processing an unprotected region but have
17770 not yet found the first instruction in it
17771 - the first instruction in an unprotected region otherwise. */
17772 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
17774 if (unprotected_region
&& USEFUL_INSN_P (insn
))
17776 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
17777 /* This CACHE instruction protects the following code. */
17778 unprotected_region
= NULL_RTX
;
17781 /* See if INSN is the first instruction in this
17782 unprotected region. */
17783 if (unprotected_region
== pc_rtx
)
17784 unprotected_region
= insn
;
17786 /* See if INSN needs to be protected. If so,
17787 we must insert a cache barrier somewhere between
17788 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
17789 clear which position is better performance-wise,
17790 but as a tie-breaker, we assume that it is better
17791 to allow delay slots to be back-filled where
17792 possible, and that it is better not to insert
17793 barriers in the middle of already-scheduled code.
17794 We therefore insert the barrier at the beginning
17796 if (r10k_needs_protection_p (insn
))
17798 emit_insn_before (gen_r10k_cache_barrier (),
17799 unprotected_region
);
17800 unprotected_region
= NULL_RTX
;
17806 /* The called function is not required to protect the exit path.
17807 The code that follows a call is therefore unprotected. */
17808 unprotected_region
= pc_rtx
;
17811 /* Record whether the end of this block is protected. */
17812 if (unprotected_region
== NULL_RTX
)
17813 bitmap_set_bit (protected_bbs
, bb
->index
);
17815 XDELETEVEC (rev_post_order
);
17817 sbitmap_free (protected_bbs
);
17819 free_dominance_info (CDI_DOMINATORS
);
17822 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
17823 otherwise. If INSN has two call rtx, then store the second one in
17827 mips_call_expr_from_insn (rtx_insn
*insn
, rtx
*second_call
)
17832 if (!CALL_P (insn
))
17835 x
= PATTERN (insn
);
17836 if (GET_CODE (x
) == PARALLEL
)
17838 /* Calls returning complex values have two CALL rtx. Look for the second
17839 one here, and return it via the SECOND_CALL arg. */
17840 x2
= XVECEXP (x
, 0, 1);
17841 if (GET_CODE (x2
) == SET
)
17843 if (GET_CODE (x2
) == CALL
)
17846 x
= XVECEXP (x
, 0, 0);
17848 if (GET_CODE (x
) == SET
)
17850 gcc_assert (GET_CODE (x
) == CALL
);
17855 /* REG is set in DEF. See if the definition is one of the ways we load a
17856 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
17857 If it is, return the symbol reference of the function, otherwise return
17860 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
17861 the values of source registers, otherwise treat such registers as
17862 having an unknown value. */
17865 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
, bool recurse_p
)
17867 rtx_insn
*def_insn
;
17870 if (DF_REF_IS_ARTIFICIAL (def
))
17873 def_insn
= DF_REF_INSN (def
);
17874 set
= single_set (def_insn
);
17875 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
17877 rtx note
, src
, symbol
;
17879 /* First see whether the source is a plain symbol. This is used
17880 when calling symbols that are not lazily bound. */
17881 src
= SET_SRC (set
);
17882 if (GET_CODE (src
) == SYMBOL_REF
)
17885 /* Handle %call16 references. */
17886 symbol
= mips_strip_unspec_call (src
);
17889 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
17893 /* If we have something more complicated, look for a
17894 REG_EQUAL or REG_EQUIV note. */
17895 note
= find_reg_equal_equiv_note (def_insn
);
17896 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
17897 return XEXP (note
, 0);
17899 /* Follow at most one simple register copy. Such copies are
17900 interesting in cases like:
17904 locally_binding_fn (...);
17909 locally_binding_fn (...);
17911 locally_binding_fn (...);
17913 where the load of locally_binding_fn can legitimately be
17914 hoisted or shared. However, we do not expect to see complex
17915 chains of copies, so a full worklist solution to the problem
17916 would probably be overkill. */
17917 if (recurse_p
&& REG_P (src
))
17918 return mips_find_pic_call_symbol (def_insn
, src
, false);
17924 /* Find the definition of the use of REG in INSN. See if the definition
17925 is one of the ways we load a register with a symbol address for a
17926 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
17927 of the function, otherwise return NULL_RTX. RECURSE_P is as for
17928 mips_pic_call_symbol_from_set. */
17931 mips_find_pic_call_symbol (rtx_insn
*insn
, rtx reg
, bool recurse_p
)
17934 struct df_link
*defs
;
17937 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
17940 defs
= DF_REF_CHAIN (use
);
17943 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
17947 /* If we have more than one definition, they need to be identical. */
17948 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
17952 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
, recurse_p
);
17953 if (!rtx_equal_p (symbol
, other
))
17960 /* Replace the args_size operand of the call expression CALL with the
17961 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
17964 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
17968 args_size
= XEXP (call
, 1);
17969 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
17970 gen_rtvec (2, args_size
, symbol
),
17974 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
17975 if instead of the arg_size argument it contains the call attributes. If
17976 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
17977 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
17981 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
17983 rtx args_size
, symbol
;
17985 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
17988 args_size
= operands
[args_size_opno
];
17989 if (GET_CODE (args_size
) != UNSPEC
)
17991 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
17993 symbol
= XVECEXP (args_size
, 0, 1);
17994 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
17996 operands
[args_size_opno
] = symbol
;
18000 /* Use DF to annotate PIC indirect calls with the function symbol they
18004 mips_annotate_pic_calls (void)
18009 FOR_EACH_BB_FN (bb
, cfun
)
18010 FOR_BB_INSNS (bb
, insn
)
18012 rtx call
, reg
, symbol
, second_call
;
18015 call
= mips_call_expr_from_insn (insn
, &second_call
);
18018 gcc_assert (MEM_P (XEXP (call
, 0)));
18019 reg
= XEXP (XEXP (call
, 0), 0);
18023 symbol
= mips_find_pic_call_symbol (insn
, reg
, true);
18026 mips_annotate_pic_call_expr (call
, symbol
);
18028 mips_annotate_pic_call_expr (second_call
, symbol
);
18033 /* A temporary variable used by note_uses callbacks, etc. */
18034 static rtx_insn
*mips_sim_insn
;
18036 /* A structure representing the state of the processor pipeline.
18037 Used by the mips_sim_* family of functions. */
18039 /* The maximum number of instructions that can be issued in a cycle.
18040 (Caches mips_issue_rate.) */
18041 unsigned int issue_rate
;
18043 /* The current simulation time. */
18046 /* How many more instructions can be issued in the current cycle. */
18047 unsigned int insns_left
;
18049 /* LAST_SET[X].INSN is the last instruction to set register X.
18050 LAST_SET[X].TIME is the time at which that instruction was issued.
18051 INSN is null if no instruction has yet set register X. */
18055 } last_set
[FIRST_PSEUDO_REGISTER
];
18057 /* The pipeline's current DFA state. */
18061 /* Reset STATE to the initial simulation state. */
18064 mips_sim_reset (struct mips_sim
*state
)
18066 curr_state
= state
->dfa_state
;
18069 state
->insns_left
= state
->issue_rate
;
18070 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
18071 state_reset (curr_state
);
18073 targetm
.sched
.init (0, false, 0);
18074 advance_state (curr_state
);
18077 /* Initialize STATE before its first use. DFA_STATE points to an
18078 allocated but uninitialized DFA state. */
18081 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
18083 if (targetm
.sched
.init_dfa_pre_cycle_insn
)
18084 targetm
.sched
.init_dfa_pre_cycle_insn ();
18086 if (targetm
.sched
.init_dfa_post_cycle_insn
)
18087 targetm
.sched
.init_dfa_post_cycle_insn ();
18089 state
->issue_rate
= mips_issue_rate ();
18090 state
->dfa_state
= dfa_state
;
18091 mips_sim_reset (state
);
18094 /* Advance STATE by one clock cycle. */
18097 mips_sim_next_cycle (struct mips_sim
*state
)
18099 curr_state
= state
->dfa_state
;
18102 state
->insns_left
= state
->issue_rate
;
18103 advance_state (curr_state
);
18106 /* Advance simulation state STATE until instruction INSN can read
18110 mips_sim_wait_reg (struct mips_sim
*state
, rtx_insn
*insn
, rtx reg
)
18112 unsigned int regno
, end_regno
;
18114 end_regno
= END_REGNO (reg
);
18115 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
18116 if (state
->last_set
[regno
].insn
!= 0)
18120 t
= (state
->last_set
[regno
].time
18121 + insn_latency (state
->last_set
[regno
].insn
, insn
));
18122 while (state
->time
< t
)
18123 mips_sim_next_cycle (state
);
18127 /* A note_uses callback. For each register in *X, advance simulation
18128 state DATA until mips_sim_insn can read the register's value. */
18131 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
18133 subrtx_var_iterator::array_type array
;
18134 FOR_EACH_SUBRTX_VAR (iter
, array
, *x
, NONCONST
)
18136 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *iter
);
18139 /* Advance simulation state STATE until all of INSN's register
18140 dependencies are satisfied. */
18143 mips_sim_wait_regs (struct mips_sim
*state
, rtx_insn
*insn
)
18145 mips_sim_insn
= insn
;
18146 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
18149 /* Advance simulation state STATE until the units required by
18150 instruction INSN are available. */
18153 mips_sim_wait_units (struct mips_sim
*state
, rtx_insn
*insn
)
18157 tmp_state
= alloca (state_size ());
18158 while (state
->insns_left
== 0
18159 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
18160 state_transition (tmp_state
, insn
) >= 0))
18161 mips_sim_next_cycle (state
);
18164 /* Advance simulation state STATE until INSN is ready to issue. */
18167 mips_sim_wait_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18169 mips_sim_wait_regs (state
, insn
);
18170 mips_sim_wait_units (state
, insn
);
18173 /* mips_sim_insn has just set X. Update the LAST_SET array
18174 in simulation state DATA. */
18177 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
18179 struct mips_sim
*state
;
18181 state
= (struct mips_sim
*) data
;
18184 unsigned int regno
, end_regno
;
18186 end_regno
= END_REGNO (x
);
18187 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
18189 state
->last_set
[regno
].insn
= mips_sim_insn
;
18190 state
->last_set
[regno
].time
= state
->time
;
18195 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
18196 can issue immediately (i.e., that mips_sim_wait_insn has already
18200 mips_sim_issue_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18202 curr_state
= state
->dfa_state
;
18204 state_transition (curr_state
, insn
);
18205 state
->insns_left
= targetm
.sched
.variable_issue (0, false, insn
,
18206 state
->insns_left
);
18208 mips_sim_insn
= insn
;
18209 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
18212 /* Simulate issuing a NOP in state STATE. */
18215 mips_sim_issue_nop (struct mips_sim
*state
)
18217 if (state
->insns_left
== 0)
18218 mips_sim_next_cycle (state
);
18219 state
->insns_left
--;
18222 /* Update simulation state STATE so that it's ready to accept the instruction
18223 after INSN. INSN should be part of the main rtl chain, not a member of a
18227 mips_sim_finish_insn (struct mips_sim
*state
, rtx_insn
*insn
)
18229 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
18231 mips_sim_issue_nop (state
);
18233 switch (GET_CODE (SEQ_BEGIN (insn
)))
18237 /* We can't predict the processor state after a call or label. */
18238 mips_sim_reset (state
);
18242 /* The delay slots of branch likely instructions are only executed
18243 when the branch is taken. Therefore, if the caller has simulated
18244 the delay slot instruction, STATE does not really reflect the state
18245 of the pipeline for the instruction after the delay slot. Also,
18246 branch likely instructions tend to incur a penalty when not taken,
18247 so there will probably be an extra delay between the branch and
18248 the instruction after the delay slot. */
18249 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
18250 mips_sim_reset (state
);
18258 /* Use simulator state STATE to calculate the execution time of
18259 instruction sequence SEQ. */
18261 static unsigned int
18262 mips_seq_time (struct mips_sim
*state
, rtx_insn
*seq
)
18264 mips_sim_reset (state
);
18265 for (rtx_insn
*insn
= seq
; insn
; insn
= NEXT_INSN (insn
))
18267 mips_sim_wait_insn (state
, insn
);
18268 mips_sim_issue_insn (state
, insn
);
18270 return state
->time
;
18273 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
18274 setting SETTING, using STATE to simulate instruction sequences. */
18276 static unsigned int
18277 mips_mult_zero_zero_cost (struct mips_sim
*state
, bool setting
)
18279 mips_tuning_info
.fast_mult_zero_zero_p
= setting
;
18282 machine_mode dword_mode
= TARGET_64BIT
? TImode
: DImode
;
18283 rtx hilo
= gen_rtx_REG (dword_mode
, MD_REG_FIRST
);
18284 mips_emit_move_or_split (hilo
, const0_rtx
, SPLIT_FOR_SPEED
);
18286 /* If the target provides mulsidi3_32bit then that's the most likely
18287 consumer of the result. Test for bypasses. */
18288 if (dword_mode
== DImode
&& HAVE_maddsidi4
)
18290 rtx gpr
= gen_rtx_REG (SImode
, GP_REG_FIRST
+ 4);
18291 emit_insn (gen_maddsidi4 (hilo
, gpr
, gpr
, hilo
));
18294 unsigned int time
= mips_seq_time (state
, get_insns ());
18299 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
18300 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
18301 Prefer MULT -- which is shorter -- in the event of a tie. */
18304 mips_set_fast_mult_zero_zero_p (struct mips_sim
*state
)
18306 if (TARGET_MIPS16
|| !ISA_HAS_HILO
)
18307 /* No MTLO or MTHI available for MIPS16. Also, when there are no HI or LO
18308 registers then there is no reason to zero them, arbitrarily choose to
18309 say that "MULT $0,$0" would be faster. */
18310 mips_tuning_info
.fast_mult_zero_zero_p
= true;
18313 unsigned int true_time
= mips_mult_zero_zero_cost (state
, true);
18314 unsigned int false_time
= mips_mult_zero_zero_cost (state
, false);
18315 mips_tuning_info
.fast_mult_zero_zero_p
= (true_time
<= false_time
);
18319 /* Set up costs based on the current architecture and tuning settings. */
18322 mips_set_tuning_info (void)
18324 if (mips_tuning_info
.initialized_p
18325 && mips_tuning_info
.arch
== mips_arch
18326 && mips_tuning_info
.tune
== mips_tune
18327 && mips_tuning_info
.mips16_p
== TARGET_MIPS16
)
18330 mips_tuning_info
.arch
= mips_arch
;
18331 mips_tuning_info
.tune
= mips_tune
;
18332 mips_tuning_info
.mips16_p
= TARGET_MIPS16
;
18333 mips_tuning_info
.initialized_p
= true;
18337 struct mips_sim state
;
18338 mips_sim_init (&state
, alloca (state_size ()));
18340 mips_set_fast_mult_zero_zero_p (&state
);
18345 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
18348 mips_expand_to_rtl_hook (void)
18350 /* We need to call this at a point where we can safely create sequences
18351 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
18352 need to call it at a point where the DFA infrastructure is not
18353 already in use, so we can't just call it lazily on demand.
18355 At present, mips_tuning_info is only needed during post-expand
18356 RTL passes such as split_insns, so this hook should be early enough.
18357 We may need to move the call elsewhere if mips_tuning_info starts
18358 to be used for other things (such as rtx_costs, or expanders that
18359 could be called during gimple optimization). */
18360 mips_set_tuning_info ();
18363 /* The VR4130 pipeline issues aligned pairs of instructions together,
18364 but it stalls the second instruction if it depends on the first.
18365 In order to cut down the amount of logic required, this dependence
18366 check is not based on a full instruction decode. Instead, any non-SPECIAL
18367 instruction is assumed to modify the register specified by bits 20-16
18368 (which is usually the "rt" field).
18370 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
18371 input, so we can end up with a false dependence between the branch
18372 and its delay slot. If this situation occurs in instruction INSN,
18373 try to avoid it by swapping rs and rt. */
18376 vr4130_avoid_branch_rt_conflict (rtx_insn
*insn
)
18378 rtx_insn
*first
, *second
;
18380 first
= SEQ_BEGIN (insn
);
18381 second
= SEQ_END (insn
);
18383 && NONJUMP_INSN_P (second
)
18384 && GET_CODE (PATTERN (first
)) == SET
18385 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
18386 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
18388 /* Check for the right kind of condition. */
18389 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
18390 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
18391 && REG_P (XEXP (cond
, 0))
18392 && REG_P (XEXP (cond
, 1))
18393 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
18394 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
18396 /* SECOND mentions the rt register but not the rs register. */
18397 rtx tmp
= XEXP (cond
, 0);
18398 XEXP (cond
, 0) = XEXP (cond
, 1);
18399 XEXP (cond
, 1) = tmp
;
18404 /* Implement -mvr4130-align. Go through each basic block and simulate the
18405 processor pipeline. If we find that a pair of instructions could execute
18406 in parallel, and the first of those instructions is not 8-byte aligned,
18407 insert a nop to make it aligned. */
18410 vr4130_align_insns (void)
18412 struct mips_sim state
;
18413 rtx_insn
*insn
, *subinsn
, *last
, *last2
, *next
;
18418 /* LAST is the last instruction before INSN to have a nonzero length.
18419 LAST2 is the last such instruction before LAST. */
18423 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
18426 mips_sim_init (&state
, alloca (state_size ()));
18427 for (insn
= get_insns (); insn
!= 0; insn
= next
)
18429 unsigned int length
;
18431 next
= NEXT_INSN (insn
);
18433 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
18434 This isn't really related to the alignment pass, but we do it on
18435 the fly to avoid a separate instruction walk. */
18436 vr4130_avoid_branch_rt_conflict (insn
);
18438 length
= get_attr_length (insn
);
18439 if (length
> 0 && USEFUL_INSN_P (insn
))
18440 FOR_EACH_SUBINSN (subinsn
, insn
)
18442 mips_sim_wait_insn (&state
, subinsn
);
18444 /* If we want this instruction to issue in parallel with the
18445 previous one, make sure that the previous instruction is
18446 aligned. There are several reasons why this isn't worthwhile
18447 when the second instruction is a call:
18449 - Calls are less likely to be performance critical,
18450 - There's a good chance that the delay slot can execute
18451 in parallel with the call.
18452 - The return address would then be unaligned.
18454 In general, if we're going to insert a nop between instructions
18455 X and Y, it's better to insert it immediately after X. That
18456 way, if the nop makes Y aligned, it will also align any labels
18457 between X and Y. */
18458 if (state
.insns_left
!= state
.issue_rate
18459 && !CALL_P (subinsn
))
18461 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
18463 /* SUBINSN is the first instruction in INSN and INSN is
18464 aligned. We want to align the previous instruction
18465 instead, so insert a nop between LAST2 and LAST.
18467 Note that LAST could be either a single instruction
18468 or a branch with a delay slot. In the latter case,
18469 LAST, like INSN, is already aligned, but the delay
18470 slot must have some extra delay that stops it from
18471 issuing at the same time as the branch. We therefore
18472 insert a nop before the branch in order to align its
18474 gcc_assert (last2
);
18475 emit_insn_after (gen_nop (), last2
);
18478 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
18480 /* SUBINSN is the delay slot of INSN, but INSN is
18481 currently unaligned. Insert a nop between
18482 LAST and INSN to align it. */
18484 emit_insn_after (gen_nop (), last
);
18488 mips_sim_issue_insn (&state
, subinsn
);
18490 mips_sim_finish_insn (&state
, insn
);
18492 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
18493 length
= get_attr_length (insn
);
18496 /* If the instruction is an asm statement or multi-instruction
18497 mips.md patern, the length is only an estimate. Insert an
18498 8 byte alignment after it so that the following instructions
18499 can be handled correctly. */
18500 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
18501 && (recog_memoized (insn
) < 0 || length
>= 8))
18503 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
18504 next
= NEXT_INSN (next
);
18505 mips_sim_next_cycle (&state
);
18508 else if (length
& 4)
18509 aligned_p
= !aligned_p
;
18514 /* See whether INSN is an aligned label. */
18515 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
18521 /* This structure records that the current function has a LO_SUM
18522 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
18523 the largest offset applied to BASE by all such LO_SUMs. */
18524 struct mips_lo_sum_offset
{
18526 HOST_WIDE_INT offset
;
18529 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
18532 mips_hash_base (rtx base
)
18534 int do_not_record_p
;
18536 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
18539 /* Hashtable helpers. */
18541 struct mips_lo_sum_offset_hasher
: free_ptr_hash
<mips_lo_sum_offset
>
18543 typedef rtx_def
*compare_type
;
18544 static inline hashval_t
hash (const mips_lo_sum_offset
*);
18545 static inline bool equal (const mips_lo_sum_offset
*, const rtx_def
*);
18548 /* Hash-table callbacks for mips_lo_sum_offsets. */
18551 mips_lo_sum_offset_hasher::hash (const mips_lo_sum_offset
*entry
)
18553 return mips_hash_base (entry
->base
);
18557 mips_lo_sum_offset_hasher::equal (const mips_lo_sum_offset
*entry
,
18558 const rtx_def
*value
)
18560 return rtx_equal_p (entry
->base
, value
);
18563 typedef hash_table
<mips_lo_sum_offset_hasher
> mips_offset_table
;
18565 /* Look up symbolic constant X in HTAB, which is a hash table of
18566 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
18567 paired with a recorded LO_SUM, otherwise record X in the table. */
18570 mips_lo_sum_offset_lookup (mips_offset_table
*htab
, rtx x
,
18571 enum insert_option option
)
18574 mips_lo_sum_offset
**slot
;
18575 struct mips_lo_sum_offset
*entry
;
18577 /* Split X into a base and offset. */
18578 split_const (x
, &base
, &offset
);
18579 if (UNSPEC_ADDRESS_P (base
))
18580 base
= UNSPEC_ADDRESS (base
);
18582 /* Look up the base in the hash table. */
18583 slot
= htab
->find_slot_with_hash (base
, mips_hash_base (base
), option
);
18587 entry
= (struct mips_lo_sum_offset
*) *slot
;
18588 if (option
== INSERT
)
18592 entry
= XNEW (struct mips_lo_sum_offset
);
18593 entry
->base
= base
;
18594 entry
->offset
= INTVAL (offset
);
18599 if (INTVAL (offset
) > entry
->offset
)
18600 entry
->offset
= INTVAL (offset
);
18603 return INTVAL (offset
) <= entry
->offset
;
18606 /* Search X for LO_SUMs and record them in HTAB. */
18609 mips_record_lo_sums (const_rtx x
, mips_offset_table
*htab
)
18611 subrtx_iterator::array_type array
;
18612 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
18613 if (GET_CODE (*iter
) == LO_SUM
)
18614 mips_lo_sum_offset_lookup (htab
, XEXP (*iter
, 1), INSERT
);
18617 /* Return true if INSN is a SET of an orphaned high-part relocation.
18618 HTAB is a hash table of mips_lo_sum_offsets that describes all the
18619 LO_SUMs in the current function. */
18622 mips_orphaned_high_part_p (mips_offset_table
*htab
, rtx_insn
*insn
)
18624 enum mips_symbol_type type
;
18627 set
= single_set (insn
);
18630 /* Check for %his. */
18632 if (GET_CODE (x
) == HIGH
18633 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
18634 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
18636 /* Check for local %gots (and %got_pages, which is redundant but OK). */
18637 if (GET_CODE (x
) == UNSPEC
18638 && XINT (x
, 1) == UNSPEC_LOAD_GOT
18639 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
18640 SYMBOL_CONTEXT_LEA
, &type
)
18641 && type
== SYMBOL_GOTOFF_PAGE
)
18642 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
18647 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
18648 INSN and a previous instruction, avoid it by inserting nops after
18651 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
18652 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
18653 before using the value of that register. *HILO_DELAY counts the
18654 number of instructions since the last hilo hazard (that is,
18655 the number of instructions since the last MFLO or MFHI).
18657 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
18658 for the next instruction.
18660 LO_REG is an rtx for the LO register, used in dependence checking. */
18663 mips_avoid_hazard (rtx_insn
*after
, rtx_insn
*insn
, int *hilo_delay
,
18664 rtx
*delayed_reg
, rtx lo_reg
, bool *fs_delay
)
18669 pattern
= PATTERN (insn
);
18671 /* Do not put the whole function in .set noreorder if it contains
18672 an asm statement. We don't know whether there will be hazards
18673 between the asm statement and the gcc-generated code. */
18674 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
18675 cfun
->machine
->all_noreorder_p
= false;
18677 /* Ignore zero-length instructions (barriers and the like). */
18678 ninsns
= get_attr_length (insn
) / 4;
18682 /* Work out how many nops are needed. Note that we only care about
18683 registers that are explicitly mentioned in the instruction's pattern.
18684 It doesn't matter that calls use the argument registers or that they
18685 clobber hi and lo. */
18686 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
18687 nops
= 2 - *hilo_delay
;
18688 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
18690 /* If processing a forbidden slot hazard then a NOP is required if the
18691 branch instruction was not in a sequence (as the sequence would
18692 imply it is not actually a compact branch anyway) and the current
18693 insn is not an inline asm, and can't go in a delay slot. */
18694 else if (*fs_delay
&& get_attr_can_delay (insn
) == CAN_DELAY_NO
18695 && GET_CODE (PATTERN (after
)) != SEQUENCE
18696 && GET_CODE (pattern
) != ASM_INPUT
18697 && asm_noperands (pattern
) < 0)
18702 /* Insert the nops between this instruction and the previous one.
18703 Each new nop takes us further from the last hilo hazard. */
18704 *hilo_delay
+= nops
;
18706 emit_insn_after (gen_hazard_nop (), after
);
18708 /* Set up the state for the next instruction. */
18709 *hilo_delay
+= ninsns
;
18712 if (INSN_CODE (insn
) >= 0)
18713 switch (get_attr_hazard (insn
))
18718 case HAZARD_FORBIDDEN_SLOT
:
18719 if (TARGET_CB_MAYBE
)
18728 set
= single_set (insn
);
18730 *delayed_reg
= SET_DEST (set
);
18735 /* A SEQUENCE is breakable iff the branch inside it has a compact form
18736 and the target has compact branches. */
18739 mips_breakable_sequence_p (rtx_insn
*insn
)
18741 return (insn
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
18743 && get_attr_compact_form (SEQ_BEGIN (insn
)) != COMPACT_FORM_NEVER
);
18746 /* Remove a SEQUENCE and replace it with the delay slot instruction
18747 followed by the branch and return the instruction in the delay slot.
18748 Return the first of the two new instructions.
18749 Subroutine of mips_reorg_process_insns. */
18752 mips_break_sequence (rtx_insn
*insn
)
18754 rtx_insn
*before
= PREV_INSN (insn
);
18755 rtx_insn
*branch
= SEQ_BEGIN (insn
);
18756 rtx_insn
*ds
= SEQ_END (insn
);
18757 remove_insn (insn
);
18758 add_insn_after (ds
, before
, NULL
);
18759 add_insn_after (branch
, ds
, NULL
);
18763 /* Go through the instruction stream and insert nops where necessary.
18764 Also delete any high-part relocations whose partnering low parts
18765 are now all dead. See if the whole function can then be put into
18766 .set noreorder and .set nomacro. */
18769 mips_reorg_process_insns (void)
18771 rtx_insn
*insn
, *last_insn
, *subinsn
, *next_insn
;
18772 rtx lo_reg
, delayed_reg
;
18776 /* Force all instructions to be split into their final form. */
18777 split_all_insns_noflow ();
18779 /* Recalculate instruction lengths without taking nops into account. */
18780 cfun
->machine
->ignore_hazard_length_p
= true;
18781 shorten_branches (get_insns ());
18783 cfun
->machine
->all_noreorder_p
= true;
18785 /* We don't track MIPS16 PC-relative offsets closely enough to make
18786 a good job of "set .noreorder" code in MIPS16 mode. */
18788 cfun
->machine
->all_noreorder_p
= false;
18790 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
18791 if (!TARGET_EXPLICIT_RELOCS
)
18792 cfun
->machine
->all_noreorder_p
= false;
18794 /* Profiled functions can't be all noreorder because the profiler
18795 support uses assembler macros. */
18797 cfun
->machine
->all_noreorder_p
= false;
18799 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
18800 all noreorder because we rely on the assembler to work around some
18801 errata. The R5900 too has several bugs. */
18802 if (TARGET_FIX_VR4120
18803 || TARGET_FIX_RM7000
18805 || TARGET_MIPS5900
)
18806 cfun
->machine
->all_noreorder_p
= false;
18808 /* The same is true for -mfix-vr4130 if we might generate MFLO or
18809 MFHI instructions. Note that we avoid using MFLO and MFHI if
18810 the VR4130 MACC and DMACC instructions are available instead;
18811 see the *mfhilo_{si,di}_macc patterns. */
18812 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
18813 cfun
->machine
->all_noreorder_p
= false;
18815 mips_offset_table
htab (37);
18817 /* Make a first pass over the instructions, recording all the LO_SUMs. */
18818 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
18819 FOR_EACH_SUBINSN (subinsn
, insn
)
18820 if (USEFUL_INSN_P (subinsn
))
18822 rtx body
= PATTERN (insn
);
18823 int noperands
= asm_noperands (body
);
18824 if (noperands
>= 0)
18826 rtx
*ops
= XALLOCAVEC (rtx
, noperands
);
18827 bool *used
= XALLOCAVEC (bool, noperands
);
18828 const char *string
= decode_asm_operands (body
, ops
, NULL
, NULL
,
18830 get_referenced_operands (string
, used
, noperands
);
18831 for (int i
= 0; i
< noperands
; ++i
)
18833 mips_record_lo_sums (ops
[i
], &htab
);
18836 mips_record_lo_sums (PATTERN (subinsn
), &htab
);
18842 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
18845 /* Make a second pass over the instructions. Delete orphaned
18846 high-part relocations or turn them into NOPs. Avoid hazards
18847 by inserting NOPs. */
18848 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
18850 next_insn
= NEXT_INSN (insn
);
18851 if (USEFUL_INSN_P (insn
))
18853 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
18855 rtx_insn
*next_active
= next_active_insn (insn
);
18856 /* Undo delay slots to avoid bubbles if the next instruction can
18857 be placed in a forbidden slot or the cost of adding an
18858 explicit NOP in a forbidden slot is OK and if the SEQUENCE is
18859 safely breakable. */
18860 if (TARGET_CB_MAYBE
18861 && mips_breakable_sequence_p (insn
)
18862 && INSN_P (SEQ_BEGIN (insn
))
18863 && INSN_P (SEQ_END (insn
))
18865 && INSN_P (next_active
)
18866 && GET_CODE (PATTERN (next_active
)) != SEQUENCE
18867 && get_attr_can_delay (next_active
) == CAN_DELAY_YES
)
18868 || !optimize_size
))
18870 /* To hide a potential pipeline bubble, if we scan backwards
18871 from the current SEQUENCE and find that there is a load
18872 of a value that is used in the CTI and there are no
18873 dependencies between the CTI and instruction in the delay
18874 slot, break the sequence so the load delay is hidden. */
18876 CLEAR_HARD_REG_SET (uses
);
18877 note_uses (&PATTERN (SEQ_BEGIN (insn
)), record_hard_reg_uses
,
18879 HARD_REG_SET delay_sets
;
18880 CLEAR_HARD_REG_SET (delay_sets
);
18881 note_stores (PATTERN (SEQ_END (insn
)), record_hard_reg_sets
,
18884 rtx_insn
*prev
= prev_active_insn (insn
);
18886 && GET_CODE (PATTERN (prev
)) == SET
18887 && MEM_P (SET_SRC (PATTERN (prev
))))
18890 CLEAR_HARD_REG_SET (sets
);
18891 note_stores (PATTERN (prev
), record_hard_reg_sets
,
18894 /* Re-order if safe. */
18895 if (!hard_reg_set_intersect_p (delay_sets
, uses
)
18896 && hard_reg_set_intersect_p (uses
, sets
))
18898 next_insn
= mips_break_sequence (insn
);
18899 /* Need to process the hazards of the newly
18900 introduced instructions. */
18905 /* If we find an orphaned high-part relocation in a delay
18906 slot then we can convert to a compact branch and get
18907 the orphaned high part deleted. */
18908 if (mips_orphaned_high_part_p (&htab
, SEQ_END (insn
)))
18910 next_insn
= mips_break_sequence (insn
);
18911 /* Need to process the hazards of the newly
18912 introduced instructions. */
18917 /* If we find an orphaned high-part relocation in a delay
18918 slot, it's easier to turn that instruction into a NOP than
18919 to delete it. The delay slot will be a NOP either way. */
18920 FOR_EACH_SUBINSN (subinsn
, insn
)
18921 if (INSN_P (subinsn
))
18923 if (mips_orphaned_high_part_p (&htab
, subinsn
))
18925 PATTERN (subinsn
) = gen_nop ();
18926 INSN_CODE (subinsn
) = CODE_FOR_nop
;
18928 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
18929 &delayed_reg
, lo_reg
, &fs_delay
);
18935 /* INSN is a single instruction. Delete it if it's an
18936 orphaned high-part relocation. */
18937 if (mips_orphaned_high_part_p (&htab
, insn
))
18938 delete_insn (insn
);
18939 /* Also delete cache barriers if the last instruction
18940 was an annulled branch. INSN will not be speculatively
18942 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
18944 && JUMP_P (SEQ_BEGIN (last_insn
))
18945 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
18946 delete_insn (insn
);
18949 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
18950 &delayed_reg
, lo_reg
, &fs_delay
);
18951 /* When a compact branch introduces a forbidden slot hazard
18952 and the next useful instruction is a SEQUENCE of a jump
18953 and a non-nop instruction in the delay slot, remove the
18954 sequence and replace it with the delay slot instruction
18955 then the jump to clear the forbidden slot hazard. */
18959 /* Search onwards from the current position looking for
18960 a SEQUENCE. We are looking for pipeline hazards here
18961 and do not need to worry about labels or barriers as
18962 the optimization only undoes delay slot filling which
18963 only affects the order of the branch and its delay
18965 rtx_insn
*next
= next_active_insn (insn
);
18967 && USEFUL_INSN_P (next
)
18968 && GET_CODE (PATTERN (next
)) == SEQUENCE
18969 && mips_breakable_sequence_p (next
))
18972 next_insn
= mips_break_sequence (next
);
18973 /* Need to process the hazards of the newly
18974 introduced instructions. */
18985 /* Return true if the function has a long branch instruction. */
18988 mips_has_long_branch_p (void)
18990 rtx_insn
*insn
, *subinsn
;
18993 /* We need up-to-date instruction lengths. */
18994 shorten_branches (get_insns ());
18996 /* Look for a branch that is longer than normal. The normal length for
18997 non-MIPS16 branches is 8, because the length includes the delay slot.
18998 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
18999 but they have no delay slot. */
19000 normal_length
= (TARGET_MIPS16
? 4 : 8);
19001 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
19002 FOR_EACH_SUBINSN (subinsn
, insn
)
19003 if (JUMP_P (subinsn
)
19004 && get_attr_length (subinsn
) > normal_length
19005 && (any_condjump_p (subinsn
) || any_uncondjump_p (subinsn
)))
19011 /* If we are using a GOT, but have not decided to use a global pointer yet,
19012 see whether we need one to implement long branches. Convert the ghost
19013 global-pointer instructions into real ones if so. */
19016 mips_expand_ghost_gp_insns (void)
19018 /* Quick exit if we already know that we will or won't need a
19020 if (!TARGET_USE_GOT
19021 || cfun
->machine
->global_pointer
== INVALID_REGNUM
19022 || mips_must_initialize_gp_p ())
19025 /* Run a full check for long branches. */
19026 if (!mips_has_long_branch_p ())
19029 /* We've now established that we need $gp. */
19030 cfun
->machine
->must_initialize_gp_p
= true;
19031 split_all_insns_noflow ();
19036 /* Subroutine of mips_reorg to manage passes that require DF. */
19039 mips_df_reorg (void)
19041 /* Create def-use chains. */
19042 df_set_flags (DF_EQ_NOTES
);
19043 df_chain_add_problem (DF_UD_CHAIN
);
19046 if (TARGET_RELAX_PIC_CALLS
)
19047 mips_annotate_pic_calls ();
19049 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
19050 r10k_insert_cache_barriers ();
19052 df_finish_pass (false);
19055 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
19056 called very late in mips_reorg, but the caller is required to run
19057 mips16_lay_out_constants on the result. */
19060 mips16_load_branch_target (rtx dest
, rtx src
)
19062 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
19066 if (mips_cfun_has_cprestore_slot_p ())
19067 mips_emit_move (dest
, mips_cprestore_slot (dest
, true));
19069 mips_emit_move (dest
, pic_offset_table_rtx
);
19070 page
= mips_unspec_address (src
, SYMBOL_GOTOFF_PAGE
);
19071 low
= mips_unspec_address (src
, SYMBOL_GOT_PAGE_OFST
);
19072 emit_insn (gen_rtx_SET (dest
,
19073 PMODE_INSN (gen_unspec_got
, (dest
, page
))));
19074 emit_insn (gen_rtx_SET (dest
, gen_rtx_LO_SUM (Pmode
, dest
, low
)));
19078 src
= mips_unspec_address (src
, SYMBOL_ABSOLUTE
);
19079 mips_emit_move (dest
, src
);
19083 /* If we're compiling a MIPS16 function, look for and split any long branches.
19084 This must be called after all other instruction modifications in
19088 mips16_split_long_branches (void)
19090 bool something_changed
;
19092 if (!TARGET_MIPS16
)
19095 /* Loop until the alignments for all targets are sufficient. */
19099 rtx_jump_insn
*jump_insn
;
19101 shorten_branches (get_insns ());
19102 something_changed
= false;
19103 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
19104 if ((jump_insn
= dyn_cast
<rtx_jump_insn
*> (insn
))
19105 && get_attr_length (jump_insn
) > 4
19106 && (any_condjump_p (jump_insn
) || any_uncondjump_p (jump_insn
)))
19108 rtx old_label
, temp
, saved_temp
;
19109 rtx_code_label
*new_label
;
19111 rtx_insn
*jump
, *jump_sequence
;
19115 /* Free up a MIPS16 register by saving it in $1. */
19116 saved_temp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
19117 temp
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
19118 emit_move_insn (saved_temp
, temp
);
19120 /* Load the branch target into TEMP. */
19121 old_label
= JUMP_LABEL (jump_insn
);
19122 target
= gen_rtx_LABEL_REF (Pmode
, old_label
);
19123 mips16_load_branch_target (temp
, target
);
19125 /* Jump to the target and restore the register's
19127 jump
= emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore
,
19128 (temp
, temp
, saved_temp
)));
19129 JUMP_LABEL (jump
) = old_label
;
19130 LABEL_NUSES (old_label
)++;
19132 /* Rewrite any symbolic references that are supposed to use
19133 a PC-relative constant pool. */
19134 mips16_lay_out_constants (false);
19136 if (simplejump_p (jump_insn
))
19137 /* We're going to replace INSN with a longer form. */
19141 /* Create a branch-around label for the original
19143 new_label
= gen_label_rtx ();
19144 emit_label (new_label
);
19147 jump_sequence
= get_insns ();
19150 emit_insn_after (jump_sequence
, jump_insn
);
19152 invert_jump (jump_insn
, new_label
, false);
19154 delete_insn (jump_insn
);
19155 something_changed
= true;
19158 while (something_changed
);
19161 /* Insert a `.insn' assembly pseudo-op after any labels followed by
19162 a MIPS16 constant pool or no insn at all. This is needed so that
19163 targets that have been optimized away are still marked as code
19164 and therefore branches that remained and point to them are known
19165 to retain the ISA mode and as such can be successfully assembled. */
19168 mips_insert_insn_pseudos (void)
19170 bool insn_pseudo_needed
= TRUE
;
19173 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
19174 switch (GET_CODE (insn
))
19177 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
19178 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE
)
19180 insn_pseudo_needed
= TRUE
;
19183 /* Fall through. */
19186 case JUMP_TABLE_DATA
:
19187 insn_pseudo_needed
= FALSE
;
19190 if (insn_pseudo_needed
)
19192 emit_insn_after (gen_insn_pseudo (), insn
);
19193 insn_pseudo_needed
= FALSE
;
19201 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
19206 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
19207 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
19208 to date if the CFG is available. */
19209 if (mips_cfg_in_reorg ())
19210 compute_bb_for_insn ();
19211 mips16_lay_out_constants (true);
19212 if (mips_cfg_in_reorg ())
19215 free_bb_for_insn ();
19219 /* We use a machine specific pass to do a second machine dependent reorg
19220 pass after delay branch scheduling. */
19222 static unsigned int
19223 mips_machine_reorg2 (void)
19225 mips_reorg_process_insns ();
19227 && TARGET_EXPLICIT_RELOCS
19229 && TARGET_VR4130_ALIGN
)
19230 vr4130_align_insns ();
19231 if (mips_expand_ghost_gp_insns ())
19232 /* The expansion could invalidate some of the VR4130 alignment
19233 optimizations, but this should be an extremely rare case anyhow. */
19234 mips_reorg_process_insns ();
19235 mips16_split_long_branches ();
19236 mips_insert_insn_pseudos ();
19242 const pass_data pass_data_mips_machine_reorg2
=
19244 RTL_PASS
, /* type */
19245 "mach2", /* name */
19246 OPTGROUP_NONE
, /* optinfo_flags */
19247 TV_MACH_DEP
, /* tv_id */
19248 0, /* properties_required */
19249 0, /* properties_provided */
19250 0, /* properties_destroyed */
19251 0, /* todo_flags_start */
19252 0, /* todo_flags_finish */
19255 class pass_mips_machine_reorg2
: public rtl_opt_pass
19258 pass_mips_machine_reorg2(gcc::context
*ctxt
)
19259 : rtl_opt_pass(pass_data_mips_machine_reorg2
, ctxt
)
19262 /* opt_pass methods: */
19263 virtual unsigned int execute (function
*) { return mips_machine_reorg2 (); }
19265 }; // class pass_mips_machine_reorg2
19267 } // anon namespace
19270 make_pass_mips_machine_reorg2 (gcc::context
*ctxt
)
19272 return new pass_mips_machine_reorg2 (ctxt
);
19276 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
19277 in order to avoid duplicating too much logic from elsewhere. */
19280 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
19281 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
19284 rtx this_rtx
, temp1
, temp2
, fnaddr
;
19286 bool use_sibcall_p
;
19288 /* Pretend to be a post-reload pass while generating rtl. */
19289 reload_completed
= 1;
19291 /* Mark the end of the (empty) prologue. */
19292 emit_note (NOTE_INSN_PROLOGUE_END
);
19294 /* Determine if we can use a sibcall to call FUNCTION directly. */
19295 fnaddr
= XEXP (DECL_RTL (function
), 0);
19296 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
19297 && const_call_insn_operand (fnaddr
, Pmode
));
19299 /* Determine if we need to load FNADDR from the GOT. */
19301 && (mips_got_symbol_type_p
19302 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
19304 /* Pick a global pointer. Use a call-clobbered register if
19305 TARGET_CALL_SAVED_GP. */
19306 cfun
->machine
->global_pointer
19307 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
19308 cfun
->machine
->must_initialize_gp_p
= true;
19309 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
19311 /* Set up the global pointer for n32 or n64 abicalls. */
19312 mips_emit_loadgp ();
19315 /* We need two temporary registers in some cases. */
19316 temp1
= gen_rtx_REG (Pmode
, 2);
19317 temp2
= gen_rtx_REG (Pmode
, 3);
19319 /* Find out which register contains the "this" pointer. */
19320 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
19321 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
19323 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
19325 /* Add DELTA to THIS_RTX. */
19328 rtx offset
= GEN_INT (delta
);
19329 if (!SMALL_OPERAND (delta
))
19331 mips_emit_move (temp1
, offset
);
19334 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
19337 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
19338 if (vcall_offset
!= 0)
19342 /* Set TEMP1 to *THIS_RTX. */
19343 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
19345 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
19346 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
19348 /* Load the offset and add it to THIS_RTX. */
19349 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
19350 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
19353 /* Jump to the target function. Use a sibcall if direct jumps are
19354 allowed, otherwise load the address into a register first. */
19357 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
19358 SIBLING_CALL_P (insn
) = 1;
19362 /* This is messy. GAS treats "la $25,foo" as part of a call
19363 sequence and may allow a global "foo" to be lazily bound.
19364 The general move patterns therefore reject this combination.
19366 In this context, lazy binding would actually be OK
19367 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
19368 TARGET_CALL_SAVED_GP; see mips_load_call_address.
19369 We must therefore load the address via a temporary
19370 register if mips_dangerous_for_la25_p.
19372 If we jump to the temporary register rather than $25,
19373 the assembler can use the move insn to fill the jump's
19376 We can use the same technique for MIPS16 code, where $25
19377 is not a valid JR register. */
19378 if (TARGET_USE_PIC_FN_ADDR_REG
19380 && !mips_dangerous_for_la25_p (fnaddr
))
19381 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
19382 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
19384 if (TARGET_USE_PIC_FN_ADDR_REG
19385 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
19386 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
19387 emit_jump_insn (gen_indirect_jump (temp1
));
19390 /* Run just enough of rest_of_compilation. This sequence was
19391 "borrowed" from alpha.c. */
19392 insn
= get_insns ();
19393 split_all_insns_noflow ();
19394 mips16_lay_out_constants (true);
19395 shorten_branches (insn
);
19396 final_start_function (insn
, file
, 1);
19397 final (insn
, file
, 1);
19398 final_end_function ();
19400 /* Clean up the vars set above. Note that final_end_function resets
19401 the global pointer for us. */
19402 reload_completed
= 0;
19406 /* The last argument passed to mips_set_compression_mode,
19407 or negative if the function hasn't been called yet. */
19408 static unsigned int old_compression_mode
= -1;
19410 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
19411 which is either MASK_MIPS16 or MASK_MICROMIPS. */
19414 mips_set_compression_mode (unsigned int compression_mode
)
19417 if (compression_mode
== old_compression_mode
)
19420 /* Restore base settings of various flags. */
19421 target_flags
= mips_base_target_flags
;
19422 flag_schedule_insns
= mips_base_schedule_insns
;
19423 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
19424 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
19425 align_loops
= mips_base_align_loops
;
19426 align_jumps
= mips_base_align_jumps
;
19427 align_functions
= mips_base_align_functions
;
19428 target_flags
&= ~(MASK_MIPS16
| MASK_MICROMIPS
);
19429 target_flags
|= compression_mode
;
19431 if (compression_mode
& MASK_MIPS16
)
19433 /* Switch to MIPS16 mode. */
19434 target_flags
|= MASK_MIPS16
;
19436 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
19437 target_flags
&= ~MASK_SYNCI
;
19439 /* Don't run the scheduler before reload, since it tends to
19440 increase register pressure. */
19441 flag_schedule_insns
= 0;
19443 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
19444 the whole function to be in a single section. */
19445 flag_reorder_blocks_and_partition
= 0;
19447 /* Don't move loop invariants, because it tends to increase
19448 register pressure. It also introduces an extra move in cases
19449 where the constant is the first operand in a two-operand binary
19450 instruction, or when it forms a register argument to a functon
19452 flag_move_loop_invariants
= 0;
19454 target_flags
|= MASK_EXPLICIT_RELOCS
;
19456 /* Experiments suggest we get the best overall section-anchor
19457 results from using the range of an unextended LW or SW. Code
19458 that makes heavy use of byte or short accesses can do better
19459 with ranges of 0...31 and 0...63 respectively, but most code is
19460 sensitive to the range of LW and SW instead. */
19461 targetm
.min_anchor_offset
= 0;
19462 targetm
.max_anchor_offset
= 127;
19464 targetm
.const_anchor
= 0;
19466 /* MIPS16 has no BAL instruction. */
19467 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
19469 /* The R4000 errata don't apply to any known MIPS16 cores.
19470 It's simpler to make the R4000 fixes and MIPS16 mode
19471 mutually exclusive. */
19472 target_flags
&= ~MASK_FIX_R4000
;
19474 if (flag_pic
&& !TARGET_OLDABI
)
19475 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
19478 sorry ("MIPS16 -mxgot code");
19480 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
19481 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
19484 sorry ("MSA MIPS16 code");
19488 /* Switch to microMIPS or the standard encoding. */
19490 if (TARGET_MICROMIPS
)
19491 /* Avoid branch likely. */
19492 target_flags
&= ~MASK_BRANCHLIKELY
;
19494 /* Provide default values for align_* for 64-bit targets. */
19497 if (align_loops
== 0)
19499 if (align_jumps
== 0)
19501 if (align_functions
== 0)
19502 align_functions
= 8;
19505 targetm
.min_anchor_offset
= -32768;
19506 targetm
.max_anchor_offset
= 32767;
19508 targetm
.const_anchor
= 0x8000;
19511 /* (Re)initialize MIPS target internals for new ISA. */
19512 mips_init_relocs ();
19514 if (compression_mode
& MASK_MIPS16
)
19516 if (!mips16_globals
)
19517 mips16_globals
= save_target_globals_default_opts ();
19519 restore_target_globals (mips16_globals
);
19521 else if (compression_mode
& MASK_MICROMIPS
)
19523 if (!micromips_globals
)
19524 micromips_globals
= save_target_globals_default_opts ();
19526 restore_target_globals (micromips_globals
);
19529 restore_target_globals (&default_target_globals
);
19531 old_compression_mode
= compression_mode
;
19534 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
19535 function should use the MIPS16 or microMIPS ISA and switch modes
19539 mips_set_current_function (tree fndecl
)
19541 mips_set_compression_mode (mips_get_compress_mode (fndecl
));
19544 /* Allocate a chunk of memory for per-function machine-dependent data. */
19546 static struct machine_function
*
19547 mips_init_machine_status (void)
19549 return ggc_cleared_alloc
<machine_function
> ();
19552 /* Return the processor associated with the given ISA level, or null
19553 if the ISA isn't valid. */
19555 static const struct mips_cpu_info
*
19556 mips_cpu_info_from_isa (int isa
)
19560 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
19561 if (mips_cpu_info_table
[i
].isa
== isa
)
19562 return mips_cpu_info_table
+ i
;
19567 /* Return a mips_cpu_info entry determined by an option valued
19570 static const struct mips_cpu_info
*
19571 mips_cpu_info_from_opt (int opt
)
19575 case MIPS_ARCH_OPTION_FROM_ABI
:
19576 /* 'from-abi' selects the most compatible architecture for the
19577 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
19578 ABIs. For the EABIs, we have to decide whether we're using
19579 the 32-bit or 64-bit version. */
19580 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
19581 : ABI_NEEDS_64BIT_REGS
? 3
19582 : (TARGET_64BIT
? 3 : 1));
19584 case MIPS_ARCH_OPTION_NATIVE
:
19585 gcc_unreachable ();
19588 return &mips_cpu_info_table
[opt
];
19592 /* Return a default mips_cpu_info entry, given that no -march= option
19593 was explicitly specified. */
19595 static const struct mips_cpu_info
*
19596 mips_default_arch (void)
19598 #if defined (MIPS_CPU_STRING_DEFAULT)
19600 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
19601 if (strcmp (mips_cpu_info_table
[i
].name
, MIPS_CPU_STRING_DEFAULT
) == 0)
19602 return mips_cpu_info_table
+ i
;
19603 gcc_unreachable ();
19604 #elif defined (MIPS_ISA_DEFAULT)
19605 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
);
19607 /* 'from-abi' makes a good default: you get whatever the ABI
19609 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI
);
19613 /* Set up globals to generate code for the ISA or processor
19614 described by INFO. */
19617 mips_set_architecture (const struct mips_cpu_info
*info
)
19621 mips_arch_info
= info
;
19622 mips_arch
= info
->cpu
;
19623 mips_isa
= info
->isa
;
19627 mips_isa_rev
= (mips_isa
& 31) + 1;
19631 /* Likewise for tuning. */
19634 mips_set_tune (const struct mips_cpu_info
*info
)
19638 mips_tune_info
= info
;
19639 mips_tune
= info
->cpu
;
19643 /* Implement TARGET_OPTION_OVERRIDE. */
19646 mips_option_override (void)
19648 int i
, start
, regno
, mode
;
19650 if (global_options_set
.x_mips_isa_option
)
19651 mips_isa_option_info
= &mips_cpu_info_table
[mips_isa_option
];
19653 #ifdef SUBTARGET_OVERRIDE_OPTIONS
19654 SUBTARGET_OVERRIDE_OPTIONS
;
19657 /* MIPS16 and microMIPS cannot coexist. */
19658 if (TARGET_MICROMIPS
&& TARGET_MIPS16
)
19659 error ("unsupported combination: %s", "-mips16 -mmicromips");
19661 /* Prohibit Paired-Single and MSA combination. This is software restriction
19662 rather than architectural. */
19663 if (ISA_HAS_MSA
&& TARGET_PAIRED_SINGLE_FLOAT
)
19664 error ("unsupported combination: %s", "-mmsa -mpaired-single");
19666 /* Save the base compression state and process flags as though we
19667 were generating uncompressed code. */
19668 mips_base_compression_flags
= TARGET_COMPRESSION
;
19669 target_flags
&= ~TARGET_COMPRESSION
;
19671 /* -mno-float overrides -mhard-float and -msoft-float. */
19672 if (TARGET_NO_FLOAT
)
19674 target_flags
|= MASK_SOFT_FLOAT_ABI
;
19675 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
19678 if (TARGET_FLIP_MIPS16
)
19679 TARGET_INTERLINK_COMPRESSED
= 1;
19681 /* Set the small data limit. */
19682 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
19684 : MIPS_DEFAULT_GVALUE
);
19686 /* The following code determines the architecture and register size.
19687 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
19688 The GAS and GCC code should be kept in sync as much as possible. */
19690 if (global_options_set
.x_mips_arch_option
)
19691 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option
));
19693 if (mips_isa_option_info
!= 0)
19695 if (mips_arch_info
== 0)
19696 mips_set_architecture (mips_isa_option_info
);
19697 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
19698 error ("%<-%s%> conflicts with the other architecture options, "
19699 "which specify a %s processor",
19700 mips_isa_option_info
->name
,
19701 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
19704 if (mips_arch_info
== 0)
19705 mips_set_architecture (mips_default_arch ());
19707 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
19708 error ("%<-march=%s%> is not compatible with the selected ABI",
19709 mips_arch_info
->name
);
19711 /* Optimize for mips_arch, unless -mtune selects a different processor. */
19712 if (global_options_set
.x_mips_tune_option
)
19713 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option
));
19715 if (mips_tune_info
== 0)
19716 mips_set_tune (mips_arch_info
);
19718 if ((target_flags_explicit
& MASK_64BIT
) != 0)
19720 /* The user specified the size of the integer registers. Make sure
19721 it agrees with the ABI and ISA. */
19722 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
19723 error ("%<-mgp64%> used with a 32-bit processor");
19724 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
19725 error ("%<-mgp32%> used with a 64-bit ABI");
19726 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
19727 error ("%<-mgp64%> used with a 32-bit ABI");
19731 /* Infer the integer register size from the ABI and processor.
19732 Restrict ourselves to 32-bit registers if that's all the
19733 processor has, or if the ABI cannot handle 64-bit registers. */
19734 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
19735 target_flags
&= ~MASK_64BIT
;
19737 target_flags
|= MASK_64BIT
;
19740 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
19742 if (mips_isa_rev
>= 6 && !TARGET_FLOAT64
)
19743 error ("the %qs architecture does not support %<-mfp32%>",
19744 mips_arch_info
->name
);
19745 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
19746 error ("unsupported combination: %s", "-mfp64 -msingle-float");
19747 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
19748 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
19749 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
19751 if (!ISA_HAS_MXHC1
)
19752 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
19753 " the target supports the mfhc1 and mthc1 instructions");
19754 else if (mips_abi
!= ABI_32
)
19755 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
19761 /* -msingle-float selects 32-bit float registers. On r6 and later,
19762 -mdouble-float selects 64-bit float registers, since the old paired
19763 register model is not supported. In other cases the float registers
19764 should be the same size as the integer ones. */
19765 if (mips_isa_rev
>= 6 && TARGET_DOUBLE_FLOAT
&& !TARGET_FLOATXX
)
19766 target_flags
|= MASK_FLOAT64
;
19767 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
19768 target_flags
|= MASK_FLOAT64
;
19769 else if (mips_abi
== ABI_32
&& ISA_HAS_MSA
&& !TARGET_FLOATXX
)
19770 target_flags
|= MASK_FLOAT64
;
19772 target_flags
&= ~MASK_FLOAT64
;
19775 if (mips_abi
!= ABI_32
&& TARGET_FLOATXX
)
19776 error ("%<-mfpxx%> can only be used with the o32 ABI");
19777 else if (TARGET_FLOAT64
&& TARGET_FLOATXX
)
19778 error ("unsupported combination: %s", "-mfp64 -mfpxx");
19779 else if (ISA_MIPS1
&& !TARGET_FLOAT32
)
19780 error ("%<-march=%s%> requires %<-mfp32%>", mips_arch_info
->name
);
19781 else if (TARGET_FLOATXX
&& !mips_lra_flag
)
19782 error ("%<-mfpxx%> requires %<-mlra%>");
19784 /* End of code shared with GAS. */
19786 /* The R5900 FPU only supports single precision. */
19787 if (TARGET_MIPS5900
&& TARGET_HARD_FLOAT_ABI
&& TARGET_DOUBLE_FLOAT
)
19788 error ("unsupported combination: %s",
19789 "-march=r5900 -mhard-float -mdouble-float");
19791 /* If a -mlong* option was given, check that it matches the ABI,
19792 otherwise infer the -mlong* setting from the other options. */
19793 if ((target_flags_explicit
& MASK_LONG64
) != 0)
19797 if (mips_abi
== ABI_N32
)
19798 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
19799 else if (mips_abi
== ABI_32
)
19800 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
19801 else if (mips_abi
== ABI_O64
&& TARGET_ABICALLS
)
19802 /* We have traditionally allowed non-abicalls code to use
19803 an LP64 form of o64. However, it would take a bit more
19804 effort to support the combination of 32-bit GOT entries
19805 and 64-bit pointers, so we treat the abicalls case as
19807 error ("the combination of %qs and %qs is incompatible with %qs",
19808 "-mabi=o64", "-mabicalls", "-mlong64");
19812 if (mips_abi
== ABI_64
)
19813 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
19818 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
19819 target_flags
|= MASK_LONG64
;
19821 target_flags
&= ~MASK_LONG64
;
19824 if (!TARGET_OLDABI
)
19825 flag_pcc_struct_return
= 0;
19827 /* Decide which rtx_costs structure to use. */
19829 mips_cost
= &mips_rtx_cost_optimize_size
;
19831 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
19833 /* If the user hasn't specified a branch cost, use the processor's
19835 if (mips_branch_cost
== 0)
19836 mips_branch_cost
= mips_cost
->branch_cost
;
19838 /* If neither -mbranch-likely nor -mno-branch-likely was given
19839 on the command line, set MASK_BRANCHLIKELY based on the target
19840 architecture and tuning flags. Annulled delay slots are a
19841 size win, so we only consider the processor-specific tuning
19842 for !optimize_size. */
19843 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
19845 if (ISA_HAS_BRANCHLIKELY
19847 && (mips_tune_info
->tune_flags
19848 & PTF_AVOID_BRANCHLIKELY_SIZE
) == 0)
19851 && (mips_tune_info
->tune_flags
19852 & PTF_AVOID_BRANCHLIKELY_SPEED
) == 0)
19853 || (mips_tune_info
->tune_flags
19854 & PTF_AVOID_BRANCHLIKELY_ALWAYS
) == 0))
19855 target_flags
|= MASK_BRANCHLIKELY
;
19857 target_flags
&= ~MASK_BRANCHLIKELY
;
19859 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
19860 warning (0, "the %qs architecture does not support branch-likely"
19861 " instructions", mips_arch_info
->name
);
19863 /* If the user hasn't specified -mimadd or -mno-imadd set
19864 MASK_IMADD based on the target architecture and tuning
19866 if ((target_flags_explicit
& MASK_IMADD
) == 0)
19868 if (ISA_HAS_MADD_MSUB
&&
19869 (mips_tune_info
->tune_flags
& PTF_AVOID_IMADD
) == 0)
19870 target_flags
|= MASK_IMADD
;
19872 target_flags
&= ~MASK_IMADD
;
19874 else if (TARGET_IMADD
&& !ISA_HAS_MADD_MSUB
)
19875 warning (0, "the %qs architecture does not support madd or msub"
19876 " instructions", mips_arch_info
->name
);
19878 /* If neither -modd-spreg nor -mno-odd-spreg was given on the command
19879 line, set MASK_ODD_SPREG based on the ISA and ABI. */
19880 if ((target_flags_explicit
& MASK_ODD_SPREG
) == 0)
19882 /* Disable TARGET_ODD_SPREG when using the o32 FPXX ABI. */
19883 if (!ISA_HAS_ODD_SPREG
|| TARGET_FLOATXX
)
19884 target_flags
&= ~MASK_ODD_SPREG
;
19886 target_flags
|= MASK_ODD_SPREG
;
19888 else if (TARGET_ODD_SPREG
&& !ISA_HAS_ODD_SPREG
)
19889 warning (0, "the %qs architecture does not support odd single-precision"
19890 " registers", mips_arch_info
->name
);
19892 if (!TARGET_ODD_SPREG
&& TARGET_64BIT
)
19894 error ("unsupported combination: %s", "-mgp64 -mno-odd-spreg");
19895 /* Allow compilation to continue further even though invalid output
19896 will be produced. */
19897 target_flags
|= MASK_ODD_SPREG
;
19900 if (!ISA_HAS_COMPACT_BRANCHES
&& mips_cb
== MIPS_CB_ALWAYS
)
19902 error ("unsupported combination: %qs%s %s",
19903 mips_arch_info
->name
, TARGET_MICROMIPS
? " -mmicromips" : "",
19904 "-mcompact-branches=always");
19906 else if (!ISA_HAS_DELAY_SLOTS
&& mips_cb
== MIPS_CB_NEVER
)
19908 error ("unsupported combination: %qs%s %s",
19909 mips_arch_info
->name
, TARGET_MICROMIPS
? " -mmicromips" : "",
19910 "-mcompact-branches=never");
19913 /* Require explicit relocs for MIPS R6 onwards. This enables simplification
19914 of the compact branch and jump support through the backend. */
19915 if (!TARGET_EXPLICIT_RELOCS
&& mips_isa_rev
>= 6)
19917 error ("unsupported combination: %qs %s",
19918 mips_arch_info
->name
, "-mno-explicit-relocs");
19921 /* The effect of -mabicalls isn't defined for the EABI. */
19922 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
19924 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
19925 target_flags
&= ~MASK_ABICALLS
;
19928 /* PIC requires -mabicalls. */
19931 if (mips_abi
== ABI_EABI
)
19932 error ("cannot generate position-independent code for %qs",
19934 else if (!TARGET_ABICALLS
)
19935 error ("position-independent code requires %qs", "-mabicalls");
19938 if (TARGET_ABICALLS_PIC2
)
19939 /* We need to set flag_pic for executables as well as DSOs
19940 because we may reference symbols that are not defined in
19941 the final executable. (MIPS does not use things like
19942 copy relocs, for example.)
19944 There is a body of code that uses __PIC__ to distinguish
19945 between -mabicalls and -mno-abicalls code. The non-__PIC__
19946 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
19947 long as any indirect jumps use $25. */
19950 /* -mvr4130-align is a "speed over size" optimization: it usually produces
19951 faster code, but at the expense of more nops. Enable it at -O3 and
19953 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
19954 target_flags
|= MASK_VR4130_ALIGN
;
19956 /* Prefer a call to memcpy over inline code when optimizing for size,
19957 though see MOVE_RATIO in mips.h. */
19958 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
19959 target_flags
|= MASK_MEMCPY
;
19961 /* If we have a nonzero small-data limit, check that the -mgpopt
19962 setting is consistent with the other target flags. */
19963 if (mips_small_data_threshold
> 0)
19967 if (!TARGET_EXPLICIT_RELOCS
)
19968 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
19970 TARGET_LOCAL_SDATA
= false;
19971 TARGET_EXTERN_SDATA
= false;
19975 if (TARGET_VXWORKS_RTP
)
19976 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
19978 if (TARGET_ABICALLS
)
19979 warning (0, "cannot use small-data accesses for %qs",
19984 /* Set NaN and ABS defaults. */
19985 if (mips_nan
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
19986 mips_nan
= MIPS_IEEE_754_2008
;
19987 if (mips_abs
== MIPS_IEEE_754_DEFAULT
&& !ISA_HAS_IEEE_754_LEGACY
)
19988 mips_abs
= MIPS_IEEE_754_2008
;
19990 /* Check for IEEE 754 legacy/2008 support. */
19991 if ((mips_nan
== MIPS_IEEE_754_LEGACY
19992 || mips_abs
== MIPS_IEEE_754_LEGACY
)
19993 && !ISA_HAS_IEEE_754_LEGACY
)
19994 warning (0, "the %qs architecture does not support %<-m%s=legacy%>",
19995 mips_arch_info
->name
,
19996 mips_nan
== MIPS_IEEE_754_LEGACY
? "nan" : "abs");
19998 if ((mips_nan
== MIPS_IEEE_754_2008
19999 || mips_abs
== MIPS_IEEE_754_2008
)
20000 && !ISA_HAS_IEEE_754_2008
)
20001 warning (0, "the %qs architecture does not support %<-m%s=2008%>",
20002 mips_arch_info
->name
,
20003 mips_nan
== MIPS_IEEE_754_2008
? "nan" : "abs");
20005 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
20006 for all its floating point. */
20007 if (mips_nan
!= MIPS_IEEE_754_2008
)
20009 REAL_MODE_FORMAT (SFmode
) = &mips_single_format
;
20010 REAL_MODE_FORMAT (DFmode
) = &mips_double_format
;
20011 REAL_MODE_FORMAT (TFmode
) = &mips_quad_format
;
20014 /* Make sure that the user didn't turn off paired single support when
20015 MIPS-3D support is requested. */
20017 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
20018 && !TARGET_PAIRED_SINGLE_FLOAT
)
20019 error ("%<-mips3d%> requires %<-mpaired-single%>");
20021 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
20023 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
20025 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
20026 and TARGET_HARD_FLOAT_ABI are both true. */
20027 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
20029 error ("%qs must be used with %qs",
20030 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
20031 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
20032 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
20036 /* Make sure that when ISA_HAS_MSA is true, TARGET_FLOAT64 and
20037 TARGET_HARD_FLOAT_ABI and both true. */
20038 if (ISA_HAS_MSA
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
20039 error ("%<-mmsa%> must be used with %<-mfp64%> and %<-mhard-float%>");
20041 /* Make sure that -mpaired-single is only used on ISAs that support it.
20042 We must disable it otherwise since it relies on other ISA properties
20043 like ISA_HAS_8CC having their normal values. */
20044 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
20046 error ("the %qs architecture does not support paired-single"
20047 " instructions", mips_arch_info
->name
);
20048 target_flags
&= ~MASK_PAIRED_SINGLE_FLOAT
;
20052 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
20053 && !TARGET_CACHE_BUILTIN
)
20055 error ("%qs requires a target that provides the %qs instruction",
20056 "-mr10k-cache-barrier", "cache");
20057 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
20060 /* If TARGET_DSPR2, enable TARGET_DSP. */
20064 if (TARGET_DSP
&& mips_isa_rev
>= 6)
20066 error ("the %qs architecture does not support DSP instructions",
20067 mips_arch_info
->name
);
20068 TARGET_DSP
= false;
20069 TARGET_DSPR2
= false;
20072 /* .eh_frame addresses should be the same width as a C pointer.
20073 Most MIPS ABIs support only one pointer size, so the assembler
20074 will usually know exactly how big an .eh_frame address is.
20076 Unfortunately, this is not true of the 64-bit EABI. The ABI was
20077 originally defined to use 64-bit pointers (i.e. it is LP64), and
20078 this is still the default mode. However, we also support an n32-like
20079 ILP32 mode, which is selected by -mlong32. The problem is that the
20080 assembler has traditionally not had an -mlong option, so it has
20081 traditionally not known whether we're using the ILP32 or LP64 form.
20083 As it happens, gas versions up to and including 2.19 use _32-bit_
20084 addresses for EABI64 .cfi_* directives. This is wrong for the
20085 default LP64 mode, so we can't use the directives by default.
20086 Moreover, since gas's current behavior is at odds with gcc's
20087 default behavior, it seems unwise to rely on future versions
20088 of gas behaving the same way. We therefore avoid using .cfi
20089 directives for -mlong32 as well. */
20090 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
20091 flag_dwarf2_cfi_asm
= 0;
20093 /* .cfi_* directives generate a read-only section, so fall back on
20094 manual .eh_frame creation if we need the section to be writable. */
20095 if (TARGET_WRITABLE_EH_FRAME
)
20096 flag_dwarf2_cfi_asm
= 0;
20098 mips_init_print_operand_punct ();
20100 /* Set up array to map GCC register number to debug register number.
20101 Ignore the special purpose register numbers. */
20103 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
20105 mips_dbx_regno
[i
] = IGNORED_DWARF_REGNUM
;
20106 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
20107 mips_dwarf_regno
[i
] = i
;
20109 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
20112 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
20113 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
20114 mips_dbx_regno
[i
] = i
+ start
;
20116 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
20117 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
20118 mips_dbx_regno
[i
] = i
+ start
;
20120 /* Accumulator debug registers use big-endian ordering. */
20121 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
20122 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
20123 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
20124 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
20125 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
20127 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
20128 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
20131 /* Set up mips_hard_regno_mode_ok. */
20132 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
20133 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
20134 mips_hard_regno_mode_ok_p
[mode
][regno
]
20135 = mips_hard_regno_mode_ok_uncached (regno
, (machine_mode
) mode
);
20137 /* Function to allocate machine-dependent function status. */
20138 init_machine_status
= &mips_init_machine_status
;
20140 /* Default to working around R4000 errata only if the processor
20141 was selected explicitly. */
20142 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
20143 && strcmp (mips_arch_info
->name
, "r4000") == 0)
20144 target_flags
|= MASK_FIX_R4000
;
20146 /* Default to working around R4400 errata only if the processor
20147 was selected explicitly. */
20148 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
20149 && strcmp (mips_arch_info
->name
, "r4400") == 0)
20150 target_flags
|= MASK_FIX_R4400
;
20152 /* Default to working around R10000 errata only if the processor
20153 was selected explicitly. */
20154 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
20155 && strcmp (mips_arch_info
->name
, "r10000") == 0)
20156 target_flags
|= MASK_FIX_R10000
;
20158 /* Make sure that branch-likely instructions available when using
20159 -mfix-r10000. The instructions are not available if either:
20161 1. -mno-branch-likely was passed.
20162 2. The selected ISA does not support branch-likely and
20163 the command line does not include -mbranch-likely. */
20164 if (TARGET_FIX_R10000
20165 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
20166 ? !ISA_HAS_BRANCHLIKELY
20167 : !TARGET_BRANCHLIKELY
))
20168 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
20170 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
20172 warning (0, "the %qs architecture does not support the synci "
20173 "instruction", mips_arch_info
->name
);
20174 target_flags
&= ~MASK_SYNCI
;
20177 /* Only optimize PIC indirect calls if they are actually required. */
20178 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
20179 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
20181 /* Save base state of options. */
20182 mips_base_target_flags
= target_flags
;
20183 mips_base_schedule_insns
= flag_schedule_insns
;
20184 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
20185 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
20186 mips_base_align_loops
= align_loops
;
20187 mips_base_align_jumps
= align_jumps
;
20188 mips_base_align_functions
= align_functions
;
20190 /* Now select the ISA mode.
20192 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
20193 later if required. */
20194 mips_set_compression_mode (0);
20196 /* We register a second machine specific reorg pass after delay slot
20197 filling. Registering the pass must be done at start up. It's
20198 convenient to do it here. */
20199 opt_pass
*new_pass
= make_pass_mips_machine_reorg2 (g
);
20200 struct register_pass_info insert_pass_mips_machine_reorg2
=
20202 new_pass
, /* pass */
20203 "dbr", /* reference_pass_name */
20204 1, /* ref_pass_instance_number */
20205 PASS_POS_INSERT_AFTER
/* po_op */
20207 register_pass (&insert_pass_mips_machine_reorg2
);
20209 if (TARGET_HARD_FLOAT_ABI
&& TARGET_MIPS5900
)
20210 REAL_MODE_FORMAT (SFmode
) = &spu_single_format
;
20212 mips_register_frame_header_opt ();
20215 /* Swap the register information for registers I and I + 1, which
20216 currently have the wrong endianness. Note that the registers'
20217 fixedness and call-clobberedness might have been set on the
20221 mips_swap_registers (unsigned int i
)
20226 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
20227 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
20229 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
20230 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
20231 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
20232 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
20238 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
20241 mips_conditional_register_usage (void)
20246 /* These DSP control register fields are global. */
20247 global_regs
[CCDSP_PO_REGNUM
] = 1;
20248 global_regs
[CCDSP_SC_REGNUM
] = 1;
20251 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20252 reg_class_contents
[(int) DSP_ACC_REGS
]);
20255 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20256 reg_class_contents
[(int) MD_REGS
]);
20258 if (!TARGET_HARD_FLOAT
)
20260 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20261 reg_class_contents
[(int) FP_REGS
]);
20262 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20263 reg_class_contents
[(int) ST_REGS
]);
20265 else if (!ISA_HAS_8CC
)
20267 /* We only have a single condition-code register. We implement
20268 this by fixing all the condition-code registers and generating
20269 RTL that refers directly to ST_REG_FIRST. */
20270 AND_COMPL_HARD_REG_SET (accessible_reg_set
,
20271 reg_class_contents
[(int) ST_REGS
]);
20273 SET_HARD_REG_BIT (accessible_reg_set
, FPSW_REGNUM
);
20274 fixed_regs
[FPSW_REGNUM
] = call_used_regs
[FPSW_REGNUM
] = 1;
20278 /* In MIPS16 mode, we prohibit the unused $s registers, since they
20279 are call-saved, and saving them via a MIPS16 register would
20280 probably waste more time than just reloading the value.
20282 We permit the $t temporary registers when optimizing for speed
20283 but not when optimizing for space because using them results in
20284 code that is larger (but faster) then not using them. We do
20285 allow $24 (t8) because it is used in CMP and CMPI instructions
20286 and $25 (t9) because it is used as the function call address in
20289 fixed_regs
[18] = call_used_regs
[18] = 1;
20290 fixed_regs
[19] = call_used_regs
[19] = 1;
20291 fixed_regs
[20] = call_used_regs
[20] = 1;
20292 fixed_regs
[21] = call_used_regs
[21] = 1;
20293 fixed_regs
[22] = call_used_regs
[22] = 1;
20294 fixed_regs
[23] = call_used_regs
[23] = 1;
20295 fixed_regs
[26] = call_used_regs
[26] = 1;
20296 fixed_regs
[27] = call_used_regs
[27] = 1;
20297 fixed_regs
[30] = call_used_regs
[30] = 1;
20300 fixed_regs
[8] = call_used_regs
[8] = 1;
20301 fixed_regs
[9] = call_used_regs
[9] = 1;
20302 fixed_regs
[10] = call_used_regs
[10] = 1;
20303 fixed_regs
[11] = call_used_regs
[11] = 1;
20304 fixed_regs
[12] = call_used_regs
[12] = 1;
20305 fixed_regs
[13] = call_used_regs
[13] = 1;
20306 fixed_regs
[14] = call_used_regs
[14] = 1;
20307 fixed_regs
[15] = call_used_regs
[15] = 1;
20310 /* Do not allow HI and LO to be treated as register operands.
20311 There are no MTHI or MTLO instructions (or any real need
20312 for them) and one-way registers cannot easily be reloaded. */
20313 AND_COMPL_HARD_REG_SET (operand_reg_set
,
20314 reg_class_contents
[(int) MD_REGS
]);
20316 /* $f20-$f23 are call-clobbered for n64. */
20317 if (mips_abi
== ABI_64
)
20320 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
20321 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
20323 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
20324 for n32 and o32 FP64. */
20325 if (mips_abi
== ABI_N32
20326 || (mips_abi
== ABI_32
20327 && TARGET_FLOAT64
))
20330 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
20331 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
20333 /* Make sure that double-register accumulator values are correctly
20334 ordered for the current endianness. */
20335 if (TARGET_LITTLE_ENDIAN
)
20337 unsigned int regno
;
20339 mips_swap_registers (MD_REG_FIRST
);
20340 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
20341 mips_swap_registers (regno
);
20345 /* Implement EH_USES. */
20348 mips_eh_uses (unsigned int regno
)
20350 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
20352 /* We need to force certain registers to be live in order to handle
20353 PIC long branches correctly. See mips_must_initialize_gp_p for
20355 if (mips_cfun_has_cprestore_slot_p ())
20357 if (regno
== CPRESTORE_SLOT_REGNUM
)
20362 if (cfun
->machine
->global_pointer
== regno
)
20370 /* Implement EPILOGUE_USES. */
20373 mips_epilogue_uses (unsigned int regno
)
20375 /* Say that the epilogue uses the return address register. Note that
20376 in the case of sibcalls, the values "used by the epilogue" are
20377 considered live at the start of the called function. */
20378 if (regno
== RETURN_ADDR_REGNUM
)
20381 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
20382 See the comment above load_call<mode> for details. */
20383 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
20386 /* An interrupt handler must preserve some registers that are
20387 ordinarily call-clobbered. */
20388 if (cfun
->machine
->interrupt_handler_p
20389 && mips_interrupt_extra_call_saved_reg_p (regno
))
20395 /* Return true if INSN needs to be wrapped in ".set noat".
20396 INSN has NOPERANDS operands, stored in OPVEC. */
20399 mips_need_noat_wrapper_p (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
20401 if (recog_memoized (insn
) >= 0)
20403 subrtx_iterator::array_type array
;
20404 for (int i
= 0; i
< noperands
; i
++)
20405 FOR_EACH_SUBRTX (iter
, array
, opvec
[i
], NONCONST
)
20406 if (REG_P (*iter
) && REGNO (*iter
) == AT_REGNUM
)
20412 /* Implement FINAL_PRESCAN_INSN. Mark MIPS16 inline constant pools
20413 as data for the purpose of disassembly. For simplicity embed the
20414 pool's initial label number in the local symbol produced so that
20415 multiple pools within a single function end up marked with unique
20416 symbols. The label number is carried by the `consttable' insn
20417 emitted at the beginning of each pool. */
20420 mips_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
, int noperands
)
20423 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
20424 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE
)
20425 mips_set_text_contents_type (asm_out_file
, "__pool_",
20426 XINT (XVECEXP (PATTERN (insn
), 0, 0), 0),
20429 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
20430 mips_push_asm_switch (&mips_noat
);
20433 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. Reset text marking to
20434 code after a MIPS16 inline constant pool. Like with the beginning
20435 of a pool table use the pool's initial label number to keep symbols
20436 unique. The label number is carried by the `consttable_end' insn
20437 emitted at the end of each pool. */
20440 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx_insn
*insn
,
20441 rtx
*opvec
, int noperands
)
20443 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
20444 mips_pop_asm_switch (&mips_noat
);
20447 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
20448 && XINT (PATTERN (insn
), 1) == UNSPEC_CONSTTABLE_END
)
20449 mips_set_text_contents_type (asm_out_file
, "__pend_",
20450 XINT (XVECEXP (PATTERN (insn
), 0, 0), 0),
20454 /* Return the function that is used to expand the <u>mulsidi3 pattern.
20455 EXT_CODE is the code of the extension used. Return NULL if widening
20456 multiplication shouldn't be used. */
20459 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
20463 signed_p
= ext_code
== SIGN_EXTEND
;
20466 /* Don't use widening multiplication with MULT when we have DMUL. Even
20467 with the extension of its input operands DMUL is faster. Note that
20468 the extension is not needed for signed multiplication. In order to
20469 ensure that we always remove the redundant sign-extension in this
20470 case we still expand mulsidi3 for DMUL. */
20471 if (ISA_HAS_R6DMUL
)
20472 return signed_p
? gen_mulsidi3_64bit_r6dmul
: NULL
;
20474 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
20477 ? gen_mulsidi3_64bit_mips16
20478 : gen_umulsidi3_64bit_mips16
);
20479 if (TARGET_FIX_R4000
)
20481 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
20486 return (signed_p
? gen_mulsidi3_32bit_r6
: gen_umulsidi3_32bit_r6
);
20489 ? gen_mulsidi3_32bit_mips16
20490 : gen_umulsidi3_32bit_mips16
);
20491 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
20492 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
20493 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
20497 /* Return true if PATTERN matches the kind of instruction generated by
20498 umips_build_save_restore. SAVE_P is true for store. */
20501 umips_save_restore_pattern_p (bool save_p
, rtx pattern
)
20505 HOST_WIDE_INT first_offset
= 0;
20506 rtx first_base
= 0;
20507 unsigned int regmask
= 0;
20509 for (n
= 0; n
< XVECLEN (pattern
, 0); n
++)
20511 rtx set
, reg
, mem
, this_base
;
20512 HOST_WIDE_INT this_offset
;
20514 /* Check that we have a SET. */
20515 set
= XVECEXP (pattern
, 0, n
);
20516 if (GET_CODE (set
) != SET
)
20519 /* Check that the SET is a load (if restoring) or a store
20521 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
20522 if (!MEM_P (mem
) || MEM_VOLATILE_P (mem
))
20525 /* Check that the address is the sum of base and a possibly-zero
20526 constant offset. Determine if the offset is in range. */
20527 mips_split_plus (XEXP (mem
, 0), &this_base
, &this_offset
);
20528 if (!REG_P (this_base
))
20533 if (!UMIPS_12BIT_OFFSET_P (this_offset
))
20535 first_base
= this_base
;
20536 first_offset
= this_offset
;
20540 /* Check that the save slots are consecutive. */
20541 if (REGNO (this_base
) != REGNO (first_base
)
20542 || this_offset
!= first_offset
+ UNITS_PER_WORD
* n
)
20546 /* Check that SET's other operand is a register. */
20547 reg
= save_p
? SET_SRC (set
) : SET_DEST (set
);
20551 regmask
|= 1 << REGNO (reg
);
20554 for (i
= 0; i
< ARRAY_SIZE (umips_swm_mask
); i
++)
20555 if (regmask
== umips_swm_mask
[i
])
20561 /* Return the assembly instruction for microMIPS LWM or SWM.
20562 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
20565 umips_output_save_restore (bool save_p
, rtx pattern
)
20567 static char buffer
[300];
20570 HOST_WIDE_INT offset
;
20571 rtx base
, mem
, set
, last_set
, last_reg
;
20573 /* Parse the pattern. */
20574 gcc_assert (umips_save_restore_pattern_p (save_p
, pattern
));
20576 s
= strcpy (buffer
, save_p
? "swm\t" : "lwm\t");
20578 n
= XVECLEN (pattern
, 0);
20580 set
= XVECEXP (pattern
, 0, 0);
20581 mem
= save_p
? SET_DEST (set
) : SET_SRC (set
);
20582 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
20584 last_set
= XVECEXP (pattern
, 0, n
- 1);
20585 last_reg
= save_p
? SET_SRC (last_set
) : SET_DEST (last_set
);
20587 if (REGNO (last_reg
) == 31)
20590 gcc_assert (n
<= 9);
20594 s
+= sprintf (s
, "%s,", reg_names
[16]);
20596 s
+= sprintf (s
, "%s-%s,", reg_names
[16], reg_names
[15 + n
]);
20598 s
+= sprintf (s
, "%s-%s,%s,", reg_names
[16], reg_names
[23],
20601 if (REGNO (last_reg
) == 31)
20602 s
+= sprintf (s
, "%s,", reg_names
[31]);
20604 s
+= sprintf (s
, "%d(%s)", (int)offset
, reg_names
[REGNO (base
)]);
20608 /* Return true if MEM1 and MEM2 use the same base register, and the
20609 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
20610 register into (from) which the contents of MEM1 will be loaded
20611 (stored), depending on the value of LOAD_P.
20612 SWAP_P is true when the 1st and 2nd instructions are swapped. */
20615 umips_load_store_pair_p_1 (bool load_p
, bool swap_p
,
20616 rtx first_reg
, rtx mem1
, rtx mem2
)
20619 HOST_WIDE_INT offset1
, offset2
;
20621 if (!MEM_P (mem1
) || !MEM_P (mem2
))
20624 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
20625 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
20627 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
20630 /* Avoid invalid load pair instructions. */
20631 if (load_p
&& REGNO (first_reg
) == REGNO (base1
))
20634 /* We must avoid this case for anti-dependence.
20637 first_reg is $2, but the base is $3. */
20640 && REGNO (first_reg
) + 1 == REGNO (base1
))
20643 if (offset2
!= offset1
+ 4)
20646 if (!UMIPS_12BIT_OFFSET_P (offset1
))
20653 mips_load_store_bonding_p (rtx
*operands
, machine_mode mode
, bool load_p
)
20655 rtx reg1
, reg2
, mem1
, mem2
, base1
, base2
;
20656 enum reg_class rc1
, rc2
;
20657 HOST_WIDE_INT offset1
, offset2
;
20661 reg1
= operands
[0];
20662 reg2
= operands
[2];
20663 mem1
= operands
[1];
20664 mem2
= operands
[3];
20668 reg1
= operands
[1];
20669 reg2
= operands
[3];
20670 mem1
= operands
[0];
20671 mem2
= operands
[2];
20674 if (mips_address_insns (XEXP (mem1
, 0), mode
, false) == 0
20675 || mips_address_insns (XEXP (mem2
, 0), mode
, false) == 0)
20678 mips_split_plus (XEXP (mem1
, 0), &base1
, &offset1
);
20679 mips_split_plus (XEXP (mem2
, 0), &base2
, &offset2
);
20681 /* Base regs do not match. */
20682 if (!REG_P (base1
) || !rtx_equal_p (base1
, base2
))
20685 /* Either of the loads is clobbering base register. It is legitimate to bond
20686 loads if second load clobbers base register. However, hardware does not
20687 support such bonding. */
20689 && (REGNO (reg1
) == REGNO (base1
)
20690 || (REGNO (reg2
) == REGNO (base1
))))
20693 /* Loading in same registers. */
20695 && REGNO (reg1
) == REGNO (reg2
))
20698 /* The loads/stores are not of same type. */
20699 rc1
= REGNO_REG_CLASS (REGNO (reg1
));
20700 rc2
= REGNO_REG_CLASS (REGNO (reg2
));
20702 && !reg_class_subset_p (rc1
, rc2
)
20703 && !reg_class_subset_p (rc2
, rc1
))
20706 if (abs (offset1
- offset2
) != GET_MODE_SIZE (mode
))
20712 /* OPERANDS describes the operands to a pair of SETs, in the order
20713 dest1, src1, dest2, src2. Return true if the operands can be used
20714 in an LWP or SWP instruction; LOAD_P says which. */
20717 umips_load_store_pair_p (bool load_p
, rtx
*operands
)
20719 rtx reg1
, reg2
, mem1
, mem2
;
20723 reg1
= operands
[0];
20724 reg2
= operands
[2];
20725 mem1
= operands
[1];
20726 mem2
= operands
[3];
20730 reg1
= operands
[1];
20731 reg2
= operands
[3];
20732 mem1
= operands
[0];
20733 mem2
= operands
[2];
20736 if (REGNO (reg2
) == REGNO (reg1
) + 1)
20737 return umips_load_store_pair_p_1 (load_p
, false, reg1
, mem1
, mem2
);
20739 if (REGNO (reg1
) == REGNO (reg2
) + 1)
20740 return umips_load_store_pair_p_1 (load_p
, true, reg2
, mem2
, mem1
);
20745 /* Return the assembly instruction for a microMIPS LWP or SWP in which
20746 the first register is REG and the first memory slot is MEM.
20747 LOAD_P is true for LWP. */
20750 umips_output_load_store_pair_1 (bool load_p
, rtx reg
, rtx mem
)
20752 rtx ops
[] = {reg
, mem
};
20755 output_asm_insn ("lwp\t%0,%1", ops
);
20757 output_asm_insn ("swp\t%0,%1", ops
);
20760 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
20761 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
20764 umips_output_load_store_pair (bool load_p
, rtx
*operands
)
20766 rtx reg1
, reg2
, mem1
, mem2
;
20769 reg1
= operands
[0];
20770 reg2
= operands
[2];
20771 mem1
= operands
[1];
20772 mem2
= operands
[3];
20776 reg1
= operands
[1];
20777 reg2
= operands
[3];
20778 mem1
= operands
[0];
20779 mem2
= operands
[2];
20782 if (REGNO (reg2
) == REGNO (reg1
) + 1)
20784 umips_output_load_store_pair_1 (load_p
, reg1
, mem1
);
20788 gcc_assert (REGNO (reg1
) == REGNO (reg2
) + 1);
20789 umips_output_load_store_pair_1 (load_p
, reg2
, mem2
);
20792 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
20795 umips_movep_target_p (rtx reg1
, rtx reg2
)
20797 int regno1
, regno2
, pair
;
20799 static const int match
[8] = {
20800 0x00000060, /* 5, 6 */
20801 0x000000a0, /* 5, 7 */
20802 0x000000c0, /* 6, 7 */
20803 0x00200010, /* 4, 21 */
20804 0x00400010, /* 4, 22 */
20805 0x00000030, /* 4, 5 */
20806 0x00000050, /* 4, 6 */
20807 0x00000090 /* 4, 7 */
20810 if (!REG_P (reg1
) || !REG_P (reg2
))
20813 regno1
= REGNO (reg1
);
20814 regno2
= REGNO (reg2
);
20816 if (!GP_REG_P (regno1
) || !GP_REG_P (regno2
))
20819 pair
= (1 << regno1
) | (1 << regno2
);
20821 for (i
= 0; i
< ARRAY_SIZE (match
); i
++)
20822 if (pair
== match
[i
])
20828 /* Return the size in bytes of the trampoline code, padded to
20829 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
20830 function address immediately follow. */
20833 mips_trampoline_code_size (void)
20835 if (TARGET_USE_PIC_FN_ADDR_REG
)
20837 else if (ptr_mode
== DImode
)
20839 else if (ISA_HAS_LOAD_DELAY
)
20845 /* Implement TARGET_TRAMPOLINE_INIT. */
20848 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
20850 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
20853 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
20855 /* Work out the offsets of the pointers from the start of the
20856 trampoline code. */
20857 end_addr_offset
= mips_trampoline_code_size ();
20858 static_chain_offset
= end_addr_offset
;
20859 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
20861 /* Get pointers to the beginning and end of the code block. */
20862 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
20863 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
20865 #define OP(X) gen_int_mode (X, SImode)
20867 /* Build up the code in TRAMPOLINE. */
20869 if (TARGET_USE_PIC_FN_ADDR_REG
)
20871 /* $25 contains the address of the trampoline. Emit code of the form:
20873 l[wd] $1, target_function_offset($25)
20874 l[wd] $static_chain, static_chain_offset($25)
20877 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
20878 target_function_offset
,
20879 PIC_FUNCTION_ADDR_REGNUM
));
20880 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
20881 static_chain_offset
,
20882 PIC_FUNCTION_ADDR_REGNUM
));
20883 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
20884 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
20886 else if (ptr_mode
== DImode
)
20888 /* It's too cumbersome to create the full 64-bit address, so let's
20894 1: l[wd] $25, target_function_offset - 12($31)
20895 l[wd] $static_chain, static_chain_offset - 12($31)
20899 where 12 is the offset of "1:" from the start of the code block. */
20900 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
20901 trampoline
[i
++] = OP (MIPS_BAL (1));
20902 trampoline
[i
++] = OP (MIPS_NOP
);
20903 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
20904 target_function_offset
- 12,
20905 RETURN_ADDR_REGNUM
));
20906 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
20907 static_chain_offset
- 12,
20908 RETURN_ADDR_REGNUM
));
20909 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
20910 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
20914 /* If the target has load delays, emit:
20916 lui $1, %hi(end_addr)
20917 lw $25, %lo(end_addr + ...)($1)
20918 lw $static_chain, %lo(end_addr + ...)($1)
20924 lui $1, %hi(end_addr)
20925 lw $25, %lo(end_addr + ...)($1)
20927 lw $static_chain, %lo(end_addr + ...)($1). */
20929 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
20930 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
20931 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
20932 NULL
, false, OPTAB_WIDEN
);
20933 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
20934 NULL
, false, OPTAB_WIDEN
);
20935 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
20937 /* Emit the LUI. */
20938 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
20939 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
20940 NULL
, false, OPTAB_WIDEN
);
20942 /* Emit the load of the target function. */
20943 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
20944 target_function_offset
- end_addr_offset
,
20946 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
20947 NULL
, false, OPTAB_WIDEN
);
20949 /* Emit the JR here, if we can. */
20950 if (!ISA_HAS_LOAD_DELAY
)
20951 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
20953 /* Emit the load of the static chain register. */
20954 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
20955 static_chain_offset
- end_addr_offset
,
20957 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
20958 NULL
, false, OPTAB_WIDEN
);
20960 /* Emit the JR, if we couldn't above. */
20961 if (ISA_HAS_LOAD_DELAY
)
20963 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
20964 trampoline
[i
++] = OP (MIPS_NOP
);
20970 /* If we are using compact branches we don't have delay slots so
20971 place the instruction that was in the delay slot before the JRC
20974 if (TARGET_CB_ALWAYS
)
20977 temp
= trampoline
[i
-2];
20978 trampoline
[i
-2] = trampoline
[i
-1];
20979 trampoline
[i
-1] = temp
;
20982 /* Copy the trampoline code. Leave any padding uninitialized. */
20983 for (j
= 0; j
< i
; j
++)
20985 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
20986 mips_emit_move (mem
, trampoline
[j
]);
20989 /* Set up the static chain pointer field. */
20990 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
20991 mips_emit_move (mem
, chain_value
);
20993 /* Set up the target function field. */
20994 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
20995 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
20997 /* Flush the code part of the trampoline. */
20998 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
20999 emit_insn (gen_clear_cache (addr
, end_addr
));
21002 /* Implement FUNCTION_PROFILER. */
21004 void mips_function_profiler (FILE *file
)
21007 sorry ("mips16 function profiling");
21008 if (TARGET_LONG_CALLS
)
21010 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
21011 if (Pmode
== DImode
)
21012 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
21014 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
21016 mips_push_asm_switch (&mips_noat
);
21017 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
21018 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
21019 /* _mcount treats $2 as the static chain register. */
21020 if (cfun
->static_chain_decl
!= NULL
)
21021 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
21022 reg_names
[STATIC_CHAIN_REGNUM
]);
21023 if (TARGET_MCOUNT_RA_ADDRESS
)
21025 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
21026 ra save location. */
21027 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
21028 /* ra not saved, pass zero. */
21029 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
21031 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
21032 Pmode
== DImode
? "dla" : "la", reg_names
[12],
21033 cfun
->machine
->frame
.ra_fp_offset
,
21034 reg_names
[STACK_POINTER_REGNUM
]);
21036 if (!TARGET_NEWABI
)
21038 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
21039 TARGET_64BIT
? "dsubu" : "subu",
21040 reg_names
[STACK_POINTER_REGNUM
],
21041 reg_names
[STACK_POINTER_REGNUM
],
21042 Pmode
== DImode
? 16 : 8);
21044 if (TARGET_LONG_CALLS
)
21045 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
21047 fprintf (file
, "\tjal\t_mcount\n");
21048 mips_pop_asm_switch (&mips_noat
);
21049 /* _mcount treats $2 as the static chain register. */
21050 if (cfun
->static_chain_decl
!= NULL
)
21051 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
21055 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
21056 behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
21057 when TARGET_LOONGSON_VECTORS is true. */
21059 static unsigned HOST_WIDE_INT
21060 mips_shift_truncation_mask (machine_mode mode
)
21062 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
21065 return GET_MODE_BITSIZE (mode
) - 1;
21068 /* Implement TARGET_PREPARE_PCH_SAVE. */
21071 mips_prepare_pch_save (void)
21073 /* We are called in a context where the current compression vs.
21074 non-compression setting should be irrelevant. The question then is:
21075 which setting makes most sense at load time?
21077 The PCH is loaded before the first token is read. We should never have
21078 switched into a compression mode by that point, and thus should not have
21079 populated mips16_globals or micromips_globals. Nor can we load the
21080 entire contents of mips16_globals or micromips_globals from the PCH file,
21081 because they contain a combination of GGC and non-GGC data.
21083 There is therefore no point in trying save the GGC part of
21084 mips16_globals/micromips_globals to the PCH file, or to preserve a
21085 compression setting across the PCH save and load. The loading compiler
21086 would not have access to the non-GGC parts of mips16_globals or
21087 micromips_globals (either from the PCH file, or from a copy that the
21088 loading compiler generated itself) and would have to call target_reinit
21091 It therefore seems best to switch back to non-MIPS16 mode and
21092 non-microMIPS mode to save time, and to ensure that mips16_globals and
21093 micromips_globals remain null after a PCH load. */
21094 mips_set_compression_mode (0);
21095 mips16_globals
= 0;
21096 micromips_globals
= 0;
21099 /* Generate or test for an insn that supports a constant permutation. */
21101 #define MAX_VECT_LEN 16
21103 struct expand_vec_perm_d
21105 rtx target
, op0
, op1
;
21106 unsigned char perm
[MAX_VECT_LEN
];
21107 machine_mode vmode
;
21108 unsigned char nelt
;
21113 /* Construct (set target (vec_select op0 (parallel perm))) and
21114 return true if that's a valid instruction in the active ISA. */
21117 mips_expand_vselect (rtx target
, rtx op0
,
21118 const unsigned char *perm
, unsigned nelt
)
21120 rtx rperm
[MAX_VECT_LEN
], x
;
21124 for (i
= 0; i
< nelt
; ++i
)
21125 rperm
[i
] = GEN_INT (perm
[i
]);
21127 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nelt
, rperm
));
21128 x
= gen_rtx_VEC_SELECT (GET_MODE (target
), op0
, x
);
21129 x
= gen_rtx_SET (target
, x
);
21131 insn
= emit_insn (x
);
21132 if (recog_memoized (insn
) < 0)
21134 remove_insn (insn
);
21140 /* Similar, but generate a vec_concat from op0 and op1 as well. */
21143 mips_expand_vselect_vconcat (rtx target
, rtx op0
, rtx op1
,
21144 const unsigned char *perm
, unsigned nelt
)
21146 machine_mode v2mode
;
21149 if (!GET_MODE_2XWIDER_MODE (GET_MODE (op0
)).exists (&v2mode
))
21151 x
= gen_rtx_VEC_CONCAT (v2mode
, op0
, op1
);
21152 return mips_expand_vselect (target
, x
, perm
, nelt
);
21155 /* Recognize patterns for even-odd extraction. */
21158 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d
*d
)
21160 unsigned i
, odd
, nelt
= d
->nelt
;
21161 rtx t0
, t1
, t2
, t3
;
21163 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
21165 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
21172 for (i
= 1; i
< nelt
; ++i
)
21173 if (d
->perm
[i
] != i
* 2 + odd
)
21179 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
21180 t0
= gen_reg_rtx (d
->vmode
);
21181 t1
= gen_reg_rtx (d
->vmode
);
21185 emit_insn (gen_loongson_punpckhhw (t0
, d
->op0
, d
->op1
));
21186 emit_insn (gen_loongson_punpcklhw (t1
, d
->op0
, d
->op1
));
21188 emit_insn (gen_loongson_punpckhhw (d
->target
, t1
, t0
));
21190 emit_insn (gen_loongson_punpcklhw (d
->target
, t1
, t0
));
21194 t2
= gen_reg_rtx (d
->vmode
);
21195 t3
= gen_reg_rtx (d
->vmode
);
21196 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op1
));
21197 emit_insn (gen_loongson_punpcklbh (t1
, d
->op0
, d
->op1
));
21198 emit_insn (gen_loongson_punpckhbh (t2
, t1
, t0
));
21199 emit_insn (gen_loongson_punpcklbh (t3
, t1
, t0
));
21201 emit_insn (gen_loongson_punpckhbh (d
->target
, t3
, t2
));
21203 emit_insn (gen_loongson_punpcklbh (d
->target
, t3
, t2
));
21207 gcc_unreachable ();
21212 /* Recognize patterns for the Loongson PSHUFH instruction. */
21215 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d
*d
)
21220 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
21222 if (d
->vmode
!= V4HImode
)
21227 /* Convert the selector into the packed 8-bit form for pshufh. */
21228 /* Recall that loongson is little-endian only. No big-endian
21229 adjustment required. */
21230 for (i
= mask
= 0; i
< 4; i
++)
21231 mask
|= (d
->perm
[i
] & 3) << (i
* 2);
21232 rmask
= force_reg (SImode
, GEN_INT (mask
));
21234 if (d
->one_vector_p
)
21235 emit_insn (gen_loongson_pshufh (d
->target
, d
->op0
, rmask
));
21238 rtx t0
, t1
, x
, merge
, rmerge
[4];
21240 t0
= gen_reg_rtx (V4HImode
);
21241 t1
= gen_reg_rtx (V4HImode
);
21242 emit_insn (gen_loongson_pshufh (t1
, d
->op1
, rmask
));
21243 emit_insn (gen_loongson_pshufh (t0
, d
->op0
, rmask
));
21245 for (i
= 0; i
< 4; ++i
)
21246 rmerge
[i
] = (d
->perm
[i
] & 4 ? constm1_rtx
: const0_rtx
);
21247 merge
= gen_rtx_CONST_VECTOR (V4HImode
, gen_rtvec_v (4, rmerge
));
21248 merge
= force_reg (V4HImode
, merge
);
21250 x
= gen_rtx_AND (V4HImode
, merge
, t1
);
21251 emit_insn (gen_rtx_SET (t1
, x
));
21253 x
= gen_rtx_NOT (V4HImode
, merge
);
21254 x
= gen_rtx_AND (V4HImode
, x
, t0
);
21255 emit_insn (gen_rtx_SET (t0
, x
));
21257 x
= gen_rtx_IOR (V4HImode
, t0
, t1
);
21258 emit_insn (gen_rtx_SET (d
->target
, x
));
21264 /* Recognize broadcast patterns for the Loongson. */
21267 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d
*d
)
21272 if (!(TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
))
21274 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
21275 if (d
->vmode
!= V8QImode
)
21277 if (!d
->one_vector_p
)
21281 for (i
= 1; i
< 8; ++i
)
21282 if (d
->perm
[i
] != elt
)
21288 /* With one interleave we put two of the desired element adjacent. */
21289 t0
= gen_reg_rtx (V8QImode
);
21291 emit_insn (gen_loongson_punpcklbh (t0
, d
->op0
, d
->op0
));
21293 emit_insn (gen_loongson_punpckhbh (t0
, d
->op0
, d
->op0
));
21295 /* Shuffle that one HImode element into all locations. */
21298 t1
= gen_reg_rtx (V4HImode
);
21299 emit_insn (gen_loongson_pshufh (t1
, gen_lowpart (V4HImode
, t0
),
21300 force_reg (SImode
, GEN_INT (elt
))));
21302 emit_move_insn (d
->target
, gen_lowpart (V8QImode
, t1
));
21306 /* Construct (set target (vec_select op0 (parallel selector))) and
21307 return true if that's a valid instruction in the active ISA. */
21310 mips_expand_msa_shuffle (struct expand_vec_perm_d
*d
)
21312 rtx x
, elts
[MAX_VECT_LEN
];
21320 for (i
= 0; i
< d
->nelt
; i
++)
21321 elts
[i
] = GEN_INT (d
->perm
[i
]);
21323 v
= gen_rtvec_v (d
->nelt
, elts
);
21324 x
= gen_rtx_PARALLEL (VOIDmode
, v
);
21326 if (!mips_const_vector_shuffle_set_p (x
, d
->vmode
))
21329 x
= gen_rtx_VEC_SELECT (d
->vmode
, d
->op0
, x
);
21330 x
= gen_rtx_SET (d
->target
, x
);
21332 insn
= emit_insn (x
);
21333 if (recog_memoized (insn
) < 0)
21335 remove_insn (insn
);
21342 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d
*d
)
21344 unsigned int i
, nelt
= d
->nelt
;
21345 unsigned char perm2
[MAX_VECT_LEN
];
21347 if (d
->one_vector_p
)
21349 /* Try interleave with alternating operands. */
21350 memcpy (perm2
, d
->perm
, sizeof(perm2
));
21351 for (i
= 1; i
< nelt
; i
+= 2)
21353 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
, perm2
, nelt
))
21358 if (mips_expand_vselect_vconcat (d
->target
, d
->op0
, d
->op1
,
21362 /* Try again with swapped operands. */
21363 for (i
= 0; i
< nelt
; ++i
)
21364 perm2
[i
] = (d
->perm
[i
] + nelt
) & (2 * nelt
- 1);
21365 if (mips_expand_vselect_vconcat (d
->target
, d
->op1
, d
->op0
, perm2
, nelt
))
21369 if (mips_expand_vpc_loongson_even_odd (d
))
21371 if (mips_expand_vpc_loongson_pshufh (d
))
21373 if (mips_expand_vpc_loongson_bcast (d
))
21375 if (mips_expand_msa_shuffle (d
))
21380 /* Expand a vec_perm_const pattern. */
21383 mips_expand_vec_perm_const (rtx operands
[4])
21385 struct expand_vec_perm_d d
;
21386 int i
, nelt
, which
;
21387 unsigned char orig_perm
[MAX_VECT_LEN
];
21391 d
.target
= operands
[0];
21392 d
.op0
= operands
[1];
21393 d
.op1
= operands
[2];
21396 d
.vmode
= GET_MODE (d
.target
);
21397 gcc_assert (VECTOR_MODE_P (d
.vmode
));
21398 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
21399 d
.testing_p
= false;
21401 /* This is overly conservative, but ensures we don't get an
21402 uninitialized warning on ORIG_PERM. */
21403 memset (orig_perm
, 0, MAX_VECT_LEN
);
21404 for (i
= which
= 0; i
< nelt
; ++i
)
21406 rtx e
= XVECEXP (sel
, 0, i
);
21407 int ei
= INTVAL (e
) & (2 * nelt
- 1);
21408 which
|= (ei
< nelt
? 1 : 2);
21411 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
21419 d
.one_vector_p
= false;
21420 if (!rtx_equal_p (d
.op0
, d
.op1
))
21425 for (i
= 0; i
< nelt
; ++i
)
21426 d
.perm
[i
] &= nelt
- 1;
21428 d
.one_vector_p
= true;
21433 d
.one_vector_p
= true;
21437 ok
= mips_expand_vec_perm_const_1 (&d
);
21439 /* If we were given a two-vector permutation which just happened to
21440 have both input vectors equal, we folded this into a one-vector
21441 permutation. There are several loongson patterns that are matched
21442 via direct vec_select+vec_concat expansion, but we do not have
21443 support in mips_expand_vec_perm_const_1 to guess the adjustment
21444 that should be made for a single operand. Just try again with
21445 the original permutation. */
21446 if (!ok
&& which
== 3)
21448 d
.op0
= operands
[1];
21449 d
.op1
= operands
[2];
21450 d
.one_vector_p
= false;
21451 memcpy (d
.perm
, orig_perm
, MAX_VECT_LEN
);
21452 ok
= mips_expand_vec_perm_const_1 (&d
);
21458 /* Implement TARGET_SCHED_REASSOCIATION_WIDTH. */
21461 mips_sched_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED
,
21464 if (MSA_SUPPORTED_MODE_P (mode
))
21469 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
21472 mips_vectorize_vec_perm_const_ok (machine_mode vmode
, vec_perm_indices sel
)
21474 struct expand_vec_perm_d d
;
21475 unsigned int i
, nelt
, which
;
21479 d
.nelt
= nelt
= GET_MODE_NUNITS (d
.vmode
);
21480 d
.testing_p
= true;
21482 /* Categorize the set of elements in the selector. */
21483 for (i
= which
= 0; i
< nelt
; ++i
)
21485 unsigned char e
= sel
[i
];
21487 gcc_assert (e
< 2 * nelt
);
21488 which
|= (e
< nelt
? 1 : 2);
21491 /* For all elements from second vector, fold the elements to first. */
21493 for (i
= 0; i
< nelt
; ++i
)
21496 /* Check whether the mask can be applied to the vector type. */
21497 d
.one_vector_p
= (which
!= 3);
21499 d
.target
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 1);
21500 d
.op1
= d
.op0
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 2);
21501 if (!d
.one_vector_p
)
21502 d
.op1
= gen_raw_REG (d
.vmode
, LAST_VIRTUAL_REGISTER
+ 3);
21505 ret
= mips_expand_vec_perm_const_1 (&d
);
21511 /* Expand an integral vector unpack operation. */
21514 mips_expand_vec_unpack (rtx operands
[2], bool unsigned_p
, bool high_p
)
21516 machine_mode imode
= GET_MODE (operands
[1]);
21517 rtx (*unpack
) (rtx
, rtx
, rtx
);
21518 rtx (*cmpFunc
) (rtx
, rtx
, rtx
);
21519 rtx tmp
, dest
, zero
;
21526 if (BYTES_BIG_ENDIAN
!= high_p
)
21527 unpack
= gen_msa_ilvl_w
;
21529 unpack
= gen_msa_ilvr_w
;
21531 cmpFunc
= gen_msa_clt_s_w
;
21535 if (BYTES_BIG_ENDIAN
!= high_p
)
21536 unpack
= gen_msa_ilvl_h
;
21538 unpack
= gen_msa_ilvr_h
;
21540 cmpFunc
= gen_msa_clt_s_h
;
21544 if (BYTES_BIG_ENDIAN
!= high_p
)
21545 unpack
= gen_msa_ilvl_b
;
21547 unpack
= gen_msa_ilvr_b
;
21549 cmpFunc
= gen_msa_clt_s_b
;
21553 gcc_unreachable ();
21559 /* Extract sign extention for each element comparing each element
21560 with immediate zero. */
21561 tmp
= gen_reg_rtx (imode
);
21562 emit_insn (cmpFunc (tmp
, operands
[1], CONST0_RTX (imode
)));
21565 tmp
= force_reg (imode
, CONST0_RTX (imode
));
21567 dest
= gen_reg_rtx (imode
);
21569 emit_insn (unpack (dest
, operands
[1], tmp
));
21570 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
21578 unpack
= gen_loongson_punpckhbh
;
21580 unpack
= gen_loongson_punpcklbh
;
21581 cmpFunc
= gen_loongson_pcmpgtb
;
21585 unpack
= gen_loongson_punpckhhw
;
21587 unpack
= gen_loongson_punpcklhw
;
21588 cmpFunc
= gen_loongson_pcmpgth
;
21591 gcc_unreachable ();
21594 zero
= force_reg (imode
, CONST0_RTX (imode
));
21599 tmp
= gen_reg_rtx (imode
);
21600 emit_insn (cmpFunc (tmp
, zero
, operands
[1]));
21603 dest
= gen_reg_rtx (imode
);
21604 emit_insn (unpack (dest
, operands
[1], tmp
));
21606 emit_move_insn (operands
[0], gen_lowpart (GET_MODE (operands
[0]), dest
));
21609 /* Construct and return PARALLEL RTX with CONST_INTs for HIGH (high_p == TRUE)
21610 or LOW (high_p == FALSE) half of a vector for mode MODE. */
21613 mips_msa_vec_parallel_const_half (machine_mode mode
, bool high_p
)
21615 int nunits
= GET_MODE_NUNITS (mode
);
21616 rtvec v
= rtvec_alloc (nunits
/ 2);
21620 if (BYTES_BIG_ENDIAN
)
21621 base
= high_p
? 0 : nunits
/ 2;
21623 base
= high_p
? nunits
/ 2 : 0;
21625 for (i
= 0; i
< nunits
/ 2; i
++)
21626 RTVEC_ELT (v
, i
) = GEN_INT (base
+ i
);
21628 return gen_rtx_PARALLEL (VOIDmode
, v
);
21631 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
21634 mips_constant_elt_p (rtx x
)
21636 return CONST_INT_P (x
) || GET_CODE (x
) == CONST_DOUBLE
;
21639 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
21642 mips_expand_vi_broadcast (machine_mode vmode
, rtx target
, rtx elt
)
21644 struct expand_vec_perm_d d
;
21648 if (elt
!= const0_rtx
)
21649 elt
= force_reg (GET_MODE_INNER (vmode
), elt
);
21651 elt
= gen_lowpart (DImode
, elt
);
21653 t1
= gen_reg_rtx (vmode
);
21657 emit_insn (gen_loongson_vec_init1_v8qi (t1
, elt
));
21660 emit_insn (gen_loongson_vec_init1_v4hi (t1
, elt
));
21663 gcc_unreachable ();
21666 memset (&d
, 0, sizeof (d
));
21671 d
.nelt
= GET_MODE_NUNITS (vmode
);
21672 d
.one_vector_p
= true;
21674 ok
= mips_expand_vec_perm_const_1 (&d
);
21678 /* Return a const_int vector of VAL with mode MODE. */
21681 mips_gen_const_int_vector (machine_mode mode
, HOST_WIDE_INT val
)
21683 rtx c
= gen_int_mode (val
, GET_MODE_INNER (mode
));
21684 return gen_const_vec_duplicate (mode
, c
);
21687 /* Return a vector of repeated 4-element sets generated from
21688 immediate VAL in mode MODE. */
21691 mips_gen_const_int_vector_shuffle (machine_mode mode
, int val
)
21693 int nunits
= GET_MODE_NUNITS (mode
);
21694 int nsets
= nunits
/ 4;
21695 rtx elts
[MAX_VECT_LEN
];
21699 /* Generate a const_int vector replicating the same 4-element set
21700 from an immediate. */
21701 for (j
= 0; j
< nsets
; j
++, set
= 4 * j
)
21702 for (i
= 0; i
< 4; i
++)
21703 elts
[set
+ i
] = GEN_INT (set
+ ((val
>> (2 * i
)) & 0x3));
21705 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (nunits
, elts
));
21708 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
21709 elements of VALS with zeros, copy the constant vector to TARGET. */
21712 mips_expand_vi_constant (machine_mode vmode
, unsigned nelt
,
21713 rtx target
, rtx vals
)
21715 rtvec vec
= shallow_copy_rtvec (XVEC (vals
, 0));
21718 for (i
= 0; i
< nelt
; ++i
)
21720 rtx elem
= RTVEC_ELT (vec
, i
);
21721 if (!mips_constant_elt_p (elem
))
21722 RTVEC_ELT (vec
, i
) = CONST0_RTX (GET_MODE (elem
));
21725 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, vec
));
21729 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
21732 mips_expand_vi_loongson_one_pinsrh (rtx target
, rtx vals
, unsigned one_var
)
21734 mips_expand_vi_constant (V4HImode
, 4, target
, vals
);
21736 emit_insn (gen_vec_setv4hi (target
, target
, XVECEXP (vals
, 0, one_var
),
21737 GEN_INT (one_var
)));
21740 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
21743 mips_expand_vi_general (machine_mode vmode
, machine_mode imode
,
21744 unsigned nelt
, unsigned nvar
, rtx target
, rtx vals
)
21746 rtx mem
= assign_stack_temp (vmode
, GET_MODE_SIZE (vmode
));
21747 unsigned int i
, isize
= GET_MODE_SIZE (imode
);
21750 mips_expand_vi_constant (vmode
, nelt
, mem
, vals
);
21752 for (i
= 0; i
< nelt
; ++i
)
21754 rtx x
= XVECEXP (vals
, 0, i
);
21755 if (!mips_constant_elt_p (x
))
21756 emit_move_insn (adjust_address (mem
, imode
, i
* isize
), x
);
21759 emit_move_insn (target
, mem
);
21762 /* Expand a vector initialization. */
21765 mips_expand_vector_init (rtx target
, rtx vals
)
21767 machine_mode vmode
= GET_MODE (target
);
21768 machine_mode imode
= GET_MODE_INNER (vmode
);
21769 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
21770 unsigned nvar
= 0, one_var
= -1u;
21771 bool all_same
= true;
21774 for (i
= 0; i
< nelt
; ++i
)
21776 x
= XVECEXP (vals
, 0, i
);
21777 if (!mips_constant_elt_p (x
))
21778 nvar
++, one_var
= i
;
21779 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
21787 rtx same
= XVECEXP (vals
, 0, 0);
21790 if (CONST_INT_P (same
) && nvar
== 0
21791 && mips_signed_immediate_p (INTVAL (same
), 10, 0))
21799 temp
= gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0));
21800 emit_move_insn (target
, temp
);
21804 gcc_unreachable ();
21807 temp
= gen_reg_rtx (imode
);
21808 if (imode
== GET_MODE (same
))
21810 else if (GET_MODE_SIZE (imode
) >= UNITS_PER_WORD
)
21811 temp2
= simplify_gen_subreg (imode
, same
, GET_MODE (same
), 0);
21813 temp2
= lowpart_subreg (imode
, same
, GET_MODE (same
));
21814 emit_move_insn (temp
, temp2
);
21822 mips_emit_move (target
, gen_rtx_VEC_DUPLICATE (vmode
, temp
));
21826 emit_insn (gen_msa_splati_w_f_scalar (target
, temp
));
21830 emit_insn (gen_msa_splati_d_f_scalar (target
, temp
));
21834 gcc_unreachable ();
21839 emit_move_insn (target
, CONST0_RTX (vmode
));
21841 for (i
= 0; i
< nelt
; ++i
)
21843 rtx temp
= gen_reg_rtx (imode
);
21844 emit_move_insn (temp
, XVECEXP (vals
, 0, i
));
21848 emit_insn (gen_vec_setv16qi (target
, temp
, GEN_INT (i
)));
21852 emit_insn (gen_vec_setv8hi (target
, temp
, GEN_INT (i
)));
21856 emit_insn (gen_vec_setv4si (target
, temp
, GEN_INT (i
)));
21860 emit_insn (gen_vec_setv2di (target
, temp
, GEN_INT (i
)));
21864 emit_insn (gen_vec_setv4sf (target
, temp
, GEN_INT (i
)));
21868 emit_insn (gen_vec_setv2df (target
, temp
, GEN_INT (i
)));
21872 gcc_unreachable ();
21879 /* Load constants from the pool, or whatever's handy. */
21882 emit_move_insn (target
, gen_rtx_CONST_VECTOR (vmode
, XVEC (vals
, 0)));
21886 /* For two-part initialization, always use CONCAT. */
21889 rtx op0
= force_reg (imode
, XVECEXP (vals
, 0, 0));
21890 rtx op1
= force_reg (imode
, XVECEXP (vals
, 0, 1));
21891 x
= gen_rtx_VEC_CONCAT (vmode
, op0
, op1
);
21892 emit_insn (gen_rtx_SET (target
, x
));
21896 /* Loongson is the only cpu with vectors with more elements. */
21897 gcc_assert (TARGET_HARD_FLOAT
&& TARGET_LOONGSON_VECTORS
);
21899 /* If all values are identical, broadcast the value. */
21902 mips_expand_vi_broadcast (vmode
, target
, XVECEXP (vals
, 0, 0));
21906 /* If we've only got one non-variable V4HImode, use PINSRH. */
21907 if (nvar
== 1 && vmode
== V4HImode
)
21909 mips_expand_vi_loongson_one_pinsrh (target
, vals
, one_var
);
21913 mips_expand_vi_general (vmode
, imode
, nelt
, nvar
, target
, vals
);
21916 /* Expand a vector reduction. */
21919 mips_expand_vec_reduc (rtx target
, rtx in
, rtx (*gen
)(rtx
, rtx
, rtx
))
21921 machine_mode vmode
= GET_MODE (in
);
21922 unsigned char perm2
[2];
21923 rtx last
, next
, fold
, x
;
21927 fold
= gen_reg_rtx (vmode
);
21931 /* Use PUL/PLU to produce { L, H } op { H, L }.
21932 By reversing the pair order, rather than a pure interleave high,
21933 we avoid erroneous exceptional conditions that we might otherwise
21934 produce from the computation of H op H. */
21937 ok
= mips_expand_vselect_vconcat (fold
, last
, last
, perm2
, 2);
21942 /* Use interleave to produce { H, L } op { H, H }. */
21943 emit_insn (gen_loongson_punpckhwd (fold
, last
, last
));
21947 /* Perform the first reduction with interleave,
21948 and subsequent reductions with shifts. */
21949 emit_insn (gen_loongson_punpckhwd_hi (fold
, last
, last
));
21951 next
= gen_reg_rtx (vmode
);
21952 emit_insn (gen (next
, last
, fold
));
21955 fold
= gen_reg_rtx (vmode
);
21956 x
= force_reg (SImode
, GEN_INT (16));
21957 emit_insn (gen_vec_shr_v4hi (fold
, last
, x
));
21961 emit_insn (gen_loongson_punpckhwd_qi (fold
, last
, last
));
21963 next
= gen_reg_rtx (vmode
);
21964 emit_insn (gen (next
, last
, fold
));
21967 fold
= gen_reg_rtx (vmode
);
21968 x
= force_reg (SImode
, GEN_INT (16));
21969 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
21971 next
= gen_reg_rtx (vmode
);
21972 emit_insn (gen (next
, last
, fold
));
21975 fold
= gen_reg_rtx (vmode
);
21976 x
= force_reg (SImode
, GEN_INT (8));
21977 emit_insn (gen_vec_shr_v8qi (fold
, last
, x
));
21981 gcc_unreachable ();
21984 emit_insn (gen (target
, last
, fold
));
21987 /* Expand a vector minimum/maximum. */
21990 mips_expand_vec_minmax (rtx target
, rtx op0
, rtx op1
,
21991 rtx (*cmp
) (rtx
, rtx
, rtx
), bool min_p
)
21993 machine_mode vmode
= GET_MODE (target
);
21996 tc
= gen_reg_rtx (vmode
);
21997 t0
= gen_reg_rtx (vmode
);
21998 t1
= gen_reg_rtx (vmode
);
22001 emit_insn (cmp (tc
, op0
, op1
));
22003 x
= gen_rtx_AND (vmode
, tc
, (min_p
? op1
: op0
));
22004 emit_insn (gen_rtx_SET (t0
, x
));
22006 x
= gen_rtx_NOT (vmode
, tc
);
22007 x
= gen_rtx_AND (vmode
, x
, (min_p
? op0
: op1
));
22008 emit_insn (gen_rtx_SET (t1
, x
));
22010 x
= gen_rtx_IOR (vmode
, t0
, t1
);
22011 emit_insn (gen_rtx_SET (target
, x
));
22014 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
22017 mips_hard_regno_caller_save_mode (unsigned int regno
,
22018 unsigned int nregs
,
22021 /* For performance, avoid saving/restoring upper parts of a register
22022 by returning MODE as save mode when the mode is known. */
22023 if (mode
== VOIDmode
)
22024 return choose_hard_reg_mode (regno
, nregs
, false);
22029 /* Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and
22030 store the result -1 or 0 in DEST. */
22033 mips_expand_msa_cmp (rtx dest
, enum rtx_code cond
, rtx op0
, rtx op1
)
22035 machine_mode cmp_mode
= GET_MODE (op0
);
22037 bool negate
= false;
22048 cond
= reverse_condition (cond
);
22061 std::swap (op0
, op1
);
22062 cond
= swap_condition (cond
);
22065 gcc_unreachable ();
22067 mips_emit_binary (cond
, dest
, op0
, op1
);
22069 emit_move_insn (dest
, gen_rtx_NOT (GET_MODE (dest
), dest
));
22084 case LTGT
: cond
= NE
; break;
22085 case UNGE
: cond
= UNLE
; std::swap (op0
, op1
); break;
22086 case UNGT
: cond
= UNLT
; std::swap (op0
, op1
); break;
22087 case LE
: unspec
= UNSPEC_MSA_FSLE
; break;
22088 case LT
: unspec
= UNSPEC_MSA_FSLT
; break;
22089 case GE
: unspec
= UNSPEC_MSA_FSLE
; std::swap (op0
, op1
); break;
22090 case GT
: unspec
= UNSPEC_MSA_FSLT
; std::swap (op0
, op1
); break;
22092 gcc_unreachable ();
22095 mips_emit_binary (cond
, dest
, op0
, op1
);
22098 rtx x
= gen_rtx_UNSPEC (GET_MODE (dest
),
22099 gen_rtvec (2, op0
, op1
), unspec
);
22100 emit_insn (gen_rtx_SET (dest
, x
));
22105 gcc_unreachable ();
22110 /* Expand VEC_COND_EXPR, where:
22111 MODE is mode of the result
22112 VIMODE equivalent integer mode
22113 OPERANDS operands of VEC_COND_EXPR. */
22116 mips_expand_vec_cond_expr (machine_mode mode
, machine_mode vimode
,
22119 rtx cond
= operands
[3];
22120 rtx cmp_op0
= operands
[4];
22121 rtx cmp_op1
= operands
[5];
22122 rtx cmp_res
= gen_reg_rtx (vimode
);
22124 mips_expand_msa_cmp (cmp_res
, GET_CODE (cond
), cmp_op0
, cmp_op1
);
22126 /* We handle the following cases:
22127 1) r = a CMP b ? -1 : 0
22128 2) r = a CMP b ? -1 : v
22129 3) r = a CMP b ? v : 0
22130 4) r = a CMP b ? v1 : v2 */
22132 /* Case (1) above. We only move the results. */
22133 if (operands
[1] == CONSTM1_RTX (vimode
)
22134 && operands
[2] == CONST0_RTX (vimode
))
22135 emit_move_insn (operands
[0], cmp_res
);
22138 rtx src1
= gen_reg_rtx (vimode
);
22139 rtx src2
= gen_reg_rtx (vimode
);
22140 rtx mask
= gen_reg_rtx (vimode
);
22143 /* Move the vector result to use it as a mask. */
22144 emit_move_insn (mask
, cmp_res
);
22146 if (register_operand (operands
[1], mode
))
22148 rtx xop1
= operands
[1];
22149 if (mode
!= vimode
)
22151 xop1
= gen_reg_rtx (vimode
);
22152 emit_move_insn (xop1
, gen_rtx_SUBREG (vimode
, operands
[1], 0));
22154 emit_move_insn (src1
, xop1
);
22158 gcc_assert (operands
[1] == CONSTM1_RTX (vimode
));
22159 /* Case (2) if the below doesn't move the mask to src2. */
22160 emit_move_insn (src1
, mask
);
22163 if (register_operand (operands
[2], mode
))
22165 rtx xop2
= operands
[2];
22166 if (mode
!= vimode
)
22168 xop2
= gen_reg_rtx (vimode
);
22169 emit_move_insn (xop2
, gen_rtx_SUBREG (vimode
, operands
[2], 0));
22171 emit_move_insn (src2
, xop2
);
22175 gcc_assert (operands
[2] == CONST0_RTX (mode
));
22176 /* Case (3) if the above didn't move the mask to src1. */
22177 emit_move_insn (src2
, mask
);
22180 /* We deal with case (4) if the mask wasn't moved to either src1 or src2.
22181 In any case, we eventually do vector mask-based copy. */
22182 bsel
= gen_rtx_IOR (vimode
,
22183 gen_rtx_AND (vimode
,
22184 gen_rtx_NOT (vimode
, mask
), src2
),
22185 gen_rtx_AND (vimode
, mask
, src1
));
22186 /* The result is placed back to a register with the mask. */
22187 emit_insn (gen_rtx_SET (mask
, bsel
));
22188 emit_move_insn (operands
[0], gen_rtx_SUBREG (mode
, mask
, 0));
22192 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
22195 mips_case_values_threshold (void)
22197 /* In MIPS16 mode using a larger case threshold generates smaller code. */
22198 if (TARGET_MIPS16
&& optimize_size
)
22201 return default_case_values_threshold ();
22204 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
22207 mips_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
22209 if (!TARGET_HARD_FLOAT_ABI
)
22211 tree exceptions_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22212 tree fcsr_orig_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22213 tree fcsr_mod_var
= create_tmp_var_raw (MIPS_ATYPE_USI
);
22214 tree get_fcsr
= mips_builtin_decls
[MIPS_GET_FCSR
];
22215 tree set_fcsr
= mips_builtin_decls
[MIPS_SET_FCSR
];
22216 tree get_fcsr_hold_call
= build_call_expr (get_fcsr
, 0);
22217 tree hold_assign_orig
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22218 fcsr_orig_var
, get_fcsr_hold_call
);
22219 tree hold_mod_val
= build2 (BIT_AND_EXPR
, MIPS_ATYPE_USI
, fcsr_orig_var
,
22220 build_int_cst (MIPS_ATYPE_USI
, 0xfffff003));
22221 tree hold_assign_mod
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22222 fcsr_mod_var
, hold_mod_val
);
22223 tree set_fcsr_hold_call
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
22224 tree hold_all
= build2 (COMPOUND_EXPR
, MIPS_ATYPE_USI
,
22225 hold_assign_orig
, hold_assign_mod
);
22226 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_all
,
22227 set_fcsr_hold_call
);
22229 *clear
= build_call_expr (set_fcsr
, 1, fcsr_mod_var
);
22231 tree get_fcsr_update_call
= build_call_expr (get_fcsr
, 0);
22232 *update
= build2 (MODIFY_EXPR
, MIPS_ATYPE_USI
,
22233 exceptions_var
, get_fcsr_update_call
);
22234 tree set_fcsr_update_call
= build_call_expr (set_fcsr
, 1, fcsr_orig_var
);
22235 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
22236 set_fcsr_update_call
);
22237 tree atomic_feraiseexcept
22238 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
22239 tree int_exceptions_var
= fold_convert (integer_type_node
,
22241 tree atomic_feraiseexcept_call
= build_call_expr (atomic_feraiseexcept
,
22242 1, int_exceptions_var
);
22243 *update
= build2 (COMPOUND_EXPR
, void_type_node
, *update
,
22244 atomic_feraiseexcept_call
);
22247 /* Implement TARGET_SPILL_CLASS. */
22250 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED
,
22251 machine_mode mode ATTRIBUTE_UNUSED
)
22258 /* Implement TARGET_LRA_P. */
22263 return mips_lra_flag
;
22266 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS. */
22269 mips_ira_change_pseudo_allocno_class (int regno
, reg_class_t allocno_class
,
22270 reg_class_t best_class ATTRIBUTE_UNUSED
)
22272 /* LRA will allocate an FPR for an integer mode pseudo instead of spilling
22273 to memory if an FPR is present in the allocno class. It is rare that
22274 we actually need to place an integer mode value in an FPR so where
22275 possible limit the allocation to GR_REGS. This will slightly pessimize
22276 code that involves integer to/from float conversions as these will have
22277 to reload into FPRs in LRA. Such reloads are sometimes eliminated and
22278 sometimes only partially eliminated. We choose to take this penalty
22279 in order to eliminate usage of FPRs in code that does not use floating
22282 This change has a similar effect to increasing the cost of FPR->GPR
22283 register moves for integer modes so that they are higher than the cost
22284 of memory but changing the allocno class is more reliable.
22286 This is also similar to forbidding integer mode values in FPRs entirely
22287 but this would lead to an inconsistency in the integer to/from float
22288 instructions that say integer mode values must be placed in FPRs. */
22289 if (INTEGRAL_MODE_P (PSEUDO_REGNO_MODE (regno
)) && allocno_class
== ALL_REGS
)
22291 return allocno_class
;
22294 /* Implement TARGET_PROMOTE_FUNCTION_MODE */
22296 /* This function is equivalent to default_promote_function_mode_always_promote
22297 except that it returns a promoted mode even if type is NULL_TREE. This is
22298 needed by libcalls which have no type (only a mode) such as fixed conversion
22299 routines that take a signed or unsigned char/short argument and convert it
22300 to a fixed type. */
22302 static machine_mode
22303 mips_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
22305 int *punsignedp ATTRIBUTE_UNUSED
,
22306 const_tree fntype ATTRIBUTE_UNUSED
,
22307 int for_return ATTRIBUTE_UNUSED
)
22311 if (type
!= NULL_TREE
)
22312 return promote_mode (type
, mode
, punsignedp
);
22314 unsignedp
= *punsignedp
;
22315 PROMOTE_MODE (mode
, unsignedp
, type
);
22316 *punsignedp
= unsignedp
;
22320 /* Implement TARGET_TRULY_NOOP_TRUNCATION. */
22323 mips_truly_noop_truncation (unsigned int outprec
, unsigned int inprec
)
22325 return !TARGET_64BIT
|| inprec
<= 32 || outprec
> 32;
22328 /* Implement TARGET_CONSTANT_ALIGNMENT. */
22330 static HOST_WIDE_INT
22331 mips_constant_alignment (const_tree exp
, HOST_WIDE_INT align
)
22333 if (TREE_CODE (exp
) == STRING_CST
|| TREE_CODE (exp
) == CONSTRUCTOR
)
22334 return MAX (align
, BITS_PER_WORD
);
22338 /* Implement TARGET_STARTING_FRAME_OFFSET. See mips_compute_frame_info
22339 for details about the frame layout. */
22341 static HOST_WIDE_INT
22342 mips_starting_frame_offset (void)
22344 if (FRAME_GROWS_DOWNWARD
)
22346 return crtl
->outgoing_args_size
+ MIPS_GP_SAVE_AREA_SIZE
;
22349 /* Initialize the GCC target structure. */
22350 #undef TARGET_ASM_ALIGNED_HI_OP
22351 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
22352 #undef TARGET_ASM_ALIGNED_SI_OP
22353 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
22354 #undef TARGET_ASM_ALIGNED_DI_OP
22355 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
22357 #undef TARGET_OPTION_OVERRIDE
22358 #define TARGET_OPTION_OVERRIDE mips_option_override
22360 #undef TARGET_LEGITIMIZE_ADDRESS
22361 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
22363 #undef TARGET_ASM_FUNCTION_PROLOGUE
22364 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
22365 #undef TARGET_ASM_FUNCTION_EPILOGUE
22366 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
22367 #undef TARGET_ASM_SELECT_RTX_SECTION
22368 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
22369 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
22370 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
22372 #undef TARGET_SCHED_INIT
22373 #define TARGET_SCHED_INIT mips_sched_init
22374 #undef TARGET_SCHED_REORDER
22375 #define TARGET_SCHED_REORDER mips_sched_reorder
22376 #undef TARGET_SCHED_REORDER2
22377 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
22378 #undef TARGET_SCHED_VARIABLE_ISSUE
22379 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
22380 #undef TARGET_SCHED_ADJUST_COST
22381 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
22382 #undef TARGET_SCHED_ISSUE_RATE
22383 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
22384 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
22385 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
22386 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
22387 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
22388 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
22389 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
22390 mips_multipass_dfa_lookahead
22391 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
22392 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
22393 mips_small_register_classes_for_mode_p
22395 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
22396 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
22398 #undef TARGET_INSERT_ATTRIBUTES
22399 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
22400 #undef TARGET_MERGE_DECL_ATTRIBUTES
22401 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
22402 #undef TARGET_CAN_INLINE_P
22403 #define TARGET_CAN_INLINE_P mips_can_inline_p
22404 #undef TARGET_SET_CURRENT_FUNCTION
22405 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
22407 #undef TARGET_VALID_POINTER_MODE
22408 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
22409 #undef TARGET_REGISTER_MOVE_COST
22410 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
22411 #undef TARGET_REGISTER_PRIORITY
22412 #define TARGET_REGISTER_PRIORITY mips_register_priority
22413 #undef TARGET_MEMORY_MOVE_COST
22414 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
22415 #undef TARGET_RTX_COSTS
22416 #define TARGET_RTX_COSTS mips_rtx_costs
22417 #undef TARGET_ADDRESS_COST
22418 #define TARGET_ADDRESS_COST mips_address_cost
22420 #undef TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P
22421 #define TARGET_NO_SPECULATION_IN_DELAY_SLOTS_P mips_no_speculation_in_delay_slots_p
22423 #undef TARGET_IN_SMALL_DATA_P
22424 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
22426 #undef TARGET_MACHINE_DEPENDENT_REORG
22427 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
22429 #undef TARGET_PREFERRED_RELOAD_CLASS
22430 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
22432 #undef TARGET_EXPAND_TO_RTL_HOOK
22433 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
22434 #undef TARGET_ASM_FILE_START
22435 #define TARGET_ASM_FILE_START mips_file_start
22436 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
22437 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
22438 #undef TARGET_ASM_CODE_END
22439 #define TARGET_ASM_CODE_END mips_code_end
22441 #undef TARGET_INIT_LIBFUNCS
22442 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
22444 #undef TARGET_BUILD_BUILTIN_VA_LIST
22445 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
22446 #undef TARGET_EXPAND_BUILTIN_VA_START
22447 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
22448 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
22449 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
22451 #undef TARGET_PROMOTE_FUNCTION_MODE
22452 #define TARGET_PROMOTE_FUNCTION_MODE mips_promote_function_mode
22453 #undef TARGET_FUNCTION_VALUE
22454 #define TARGET_FUNCTION_VALUE mips_function_value
22455 #undef TARGET_LIBCALL_VALUE
22456 #define TARGET_LIBCALL_VALUE mips_libcall_value
22457 #undef TARGET_FUNCTION_VALUE_REGNO_P
22458 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
22459 #undef TARGET_RETURN_IN_MEMORY
22460 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
22461 #undef TARGET_RETURN_IN_MSB
22462 #define TARGET_RETURN_IN_MSB mips_return_in_msb
22464 #undef TARGET_ASM_OUTPUT_MI_THUNK
22465 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
22466 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
22467 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
22469 #undef TARGET_PRINT_OPERAND
22470 #define TARGET_PRINT_OPERAND mips_print_operand
22471 #undef TARGET_PRINT_OPERAND_ADDRESS
22472 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
22473 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
22474 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
22476 #undef TARGET_SETUP_INCOMING_VARARGS
22477 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
22478 #undef TARGET_STRICT_ARGUMENT_NAMING
22479 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
22480 #undef TARGET_MUST_PASS_IN_STACK
22481 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
22482 #undef TARGET_PASS_BY_REFERENCE
22483 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
22484 #undef TARGET_CALLEE_COPIES
22485 #define TARGET_CALLEE_COPIES mips_callee_copies
22486 #undef TARGET_ARG_PARTIAL_BYTES
22487 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
22488 #undef TARGET_FUNCTION_ARG
22489 #define TARGET_FUNCTION_ARG mips_function_arg
22490 #undef TARGET_FUNCTION_ARG_ADVANCE
22491 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
22492 #undef TARGET_FUNCTION_ARG_PADDING
22493 #define TARGET_FUNCTION_ARG_PADDING mips_function_arg_padding
22494 #undef TARGET_FUNCTION_ARG_BOUNDARY
22495 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
22496 #undef TARGET_GET_RAW_RESULT_MODE
22497 #define TARGET_GET_RAW_RESULT_MODE mips_get_reg_raw_mode
22498 #undef TARGET_GET_RAW_ARG_MODE
22499 #define TARGET_GET_RAW_ARG_MODE mips_get_reg_raw_mode
22501 #undef TARGET_MODE_REP_EXTENDED
22502 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
22504 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
22505 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
22506 mips_builtin_vectorized_function
22507 #undef TARGET_VECTOR_MODE_SUPPORTED_P
22508 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
22510 #undef TARGET_SCALAR_MODE_SUPPORTED_P
22511 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
22513 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
22514 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
22515 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
22516 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
22517 mips_autovectorize_vector_sizes
22519 #undef TARGET_INIT_BUILTINS
22520 #define TARGET_INIT_BUILTINS mips_init_builtins
22521 #undef TARGET_BUILTIN_DECL
22522 #define TARGET_BUILTIN_DECL mips_builtin_decl
22523 #undef TARGET_EXPAND_BUILTIN
22524 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
22526 #undef TARGET_HAVE_TLS
22527 #define TARGET_HAVE_TLS HAVE_AS_TLS
22529 #undef TARGET_CANNOT_FORCE_CONST_MEM
22530 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
22532 #undef TARGET_LEGITIMATE_CONSTANT_P
22533 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
22535 #undef TARGET_ENCODE_SECTION_INFO
22536 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
22538 #undef TARGET_ATTRIBUTE_TABLE
22539 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
22540 /* All our function attributes are related to how out-of-line copies should
22541 be compiled or called. They don't in themselves prevent inlining. */
22542 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
22543 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
22545 #undef TARGET_EXTRA_LIVE_ON_ENTRY
22546 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
22548 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
22549 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
22550 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
22551 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
22553 #undef TARGET_COMP_TYPE_ATTRIBUTES
22554 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
22556 #ifdef HAVE_AS_DTPRELWORD
22557 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
22558 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
22560 #undef TARGET_DWARF_REGISTER_SPAN
22561 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
22562 #undef TARGET_DWARF_FRAME_REG_MODE
22563 #define TARGET_DWARF_FRAME_REG_MODE mips_dwarf_frame_reg_mode
22565 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
22566 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
22568 #undef TARGET_LEGITIMATE_ADDRESS_P
22569 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
22571 #undef TARGET_FRAME_POINTER_REQUIRED
22572 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
22574 #undef TARGET_CAN_ELIMINATE
22575 #define TARGET_CAN_ELIMINATE mips_can_eliminate
22577 #undef TARGET_CONDITIONAL_REGISTER_USAGE
22578 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
22580 #undef TARGET_TRAMPOLINE_INIT
22581 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
22583 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
22584 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
22586 #undef TARGET_SHIFT_TRUNCATION_MASK
22587 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
22589 #undef TARGET_PREPARE_PCH_SAVE
22590 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
22592 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
22593 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
22595 #undef TARGET_SCHED_REASSOCIATION_WIDTH
22596 #define TARGET_SCHED_REASSOCIATION_WIDTH mips_sched_reassociation_width
22598 #undef TARGET_CASE_VALUES_THRESHOLD
22599 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
22601 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
22602 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
22604 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
22605 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
22607 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
22608 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
22609 mips_use_by_pieces_infrastructure_p
22611 #undef TARGET_SPILL_CLASS
22612 #define TARGET_SPILL_CLASS mips_spill_class
22613 #undef TARGET_LRA_P
22614 #define TARGET_LRA_P mips_lra_p
22615 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
22616 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS mips_ira_change_pseudo_allocno_class
22618 #undef TARGET_HARD_REGNO_SCRATCH_OK
22619 #define TARGET_HARD_REGNO_SCRATCH_OK mips_hard_regno_scratch_ok
22621 #undef TARGET_HARD_REGNO_NREGS
22622 #define TARGET_HARD_REGNO_NREGS mips_hard_regno_nregs
22623 #undef TARGET_HARD_REGNO_MODE_OK
22624 #define TARGET_HARD_REGNO_MODE_OK mips_hard_regno_mode_ok
22626 #undef TARGET_MODES_TIEABLE_P
22627 #define TARGET_MODES_TIEABLE_P mips_modes_tieable_p
22629 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
22630 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
22631 mips_hard_regno_call_part_clobbered
22633 /* The architecture reserves bit 0 for MIPS16 so use bit 1 for descriptors. */
22634 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
22635 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2
22637 #undef TARGET_SECONDARY_MEMORY_NEEDED
22638 #define TARGET_SECONDARY_MEMORY_NEEDED mips_secondary_memory_needed
22640 #undef TARGET_CAN_CHANGE_MODE_CLASS
22641 #define TARGET_CAN_CHANGE_MODE_CLASS mips_can_change_mode_class
22643 #undef TARGET_TRULY_NOOP_TRUNCATION
22644 #define TARGET_TRULY_NOOP_TRUNCATION mips_truly_noop_truncation
22646 #undef TARGET_CONSTANT_ALIGNMENT
22647 #define TARGET_CONSTANT_ALIGNMENT mips_constant_alignment
22649 #undef TARGET_STARTING_FRAME_OFFSET
22650 #define TARGET_STARTING_FRAME_OFFSET mips_starting_frame_offset
22652 struct gcc_target targetm
= TARGET_INITIALIZER
;
22654 #include "gt-mips.h"