1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
58 #define STAB_CODE_TYPE enum __stab_debug_code
60 #define STAB_CODE_TYPE int
63 extern tree lookup_name
PARAMS ((tree
));
65 /* Enumeration for all of the relational tests, so that we can build
66 arrays indexed by the test type, and not worry about the order
86 static enum internal_test map_test_to_internal_test
PARAMS ((enum rtx_code
));
87 static int mips16_simple_memory_operand
PARAMS ((rtx
, rtx
,
89 static int m16_check_op
PARAMS ((rtx
, int, int, int));
90 static void block_move_loop
PARAMS ((rtx
, rtx
,
94 static void block_move_call
PARAMS ((rtx
, rtx
, rtx
));
95 static void mips_arg_info
PARAMS ((const CUMULATIVE_ARGS
*,
98 struct mips_arg_info
*));
99 static rtx mips_add_large_offset_to_sp
PARAMS ((HOST_WIDE_INT
));
100 static void mips_annotate_frame_insn
PARAMS ((rtx
, rtx
));
101 static rtx mips_frame_set
PARAMS ((enum machine_mode
,
103 static void mips_emit_frame_related_store
PARAMS ((rtx
, rtx
,
105 static void save_restore_insns
PARAMS ((int, rtx
, long));
106 static void mips16_output_gp_offset
PARAMS ((FILE *, rtx
));
107 static void mips16_fp_args
PARAMS ((FILE *, int, int));
108 static void build_mips16_function_stub
PARAMS ((FILE *));
109 static void mips16_optimize_gp
PARAMS ((rtx
));
110 static rtx add_constant
PARAMS ((struct constant
**,
113 static void dump_constants
PARAMS ((struct constant
*,
115 static rtx mips_find_symbol
PARAMS ((rtx
));
116 static void abort_with_insn
PARAMS ((rtx
, const char *))
118 static int symbolic_expression_p
PARAMS ((rtx
));
119 static bool mips_assemble_integer
PARAMS ((rtx
, unsigned int, int));
120 static void mips_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
121 static void mips_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
122 static void mips_set_architecture
PARAMS ((const struct mips_cpu_info
*));
123 static void mips_set_tune
PARAMS ((const struct mips_cpu_info
*));
124 static bool mips_strict_matching_cpu_name_p
PARAMS ((const char *,
126 static bool mips_matching_cpu_name_p
PARAMS ((const char *,
128 static const struct mips_cpu_info
*mips_parse_cpu
PARAMS ((const char *,
130 static const struct mips_cpu_info
*mips_cpu_info_from_isa
PARAMS ((int));
131 static void copy_file_data
PARAMS ((FILE *, FILE *));
133 static void iris6_asm_named_section_1
PARAMS ((const char *,
136 static void iris6_asm_named_section
PARAMS ((const char *,
138 static int iris_section_align_entry_eq
PARAMS ((const PTR
, const PTR
));
139 static hashval_t iris_section_align_entry_hash
PARAMS ((const PTR
));
140 static int iris6_section_align_1
PARAMS ((void **, void *));
142 static int mips_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
143 static int mips_issue_rate
PARAMS ((void));
145 static struct machine_function
* mips_init_machine_status
PARAMS ((void));
146 static void mips_select_section
PARAMS ((tree
, int, unsigned HOST_WIDE_INT
))
148 static void mips_unique_section
PARAMS ((tree
, int))
150 static void mips_select_rtx_section
PARAMS ((enum machine_mode
, rtx
,
151 unsigned HOST_WIDE_INT
));
152 static int mips_use_dfa_pipeline_interface
PARAMS ((void));
153 static void mips_encode_section_info
PARAMS ((tree
, int));
155 /* Structure to be filled in by compute_frame_size with register
156 save masks, and offsets for the current function. */
158 struct mips_frame_info
GTY(())
160 long total_size
; /* # bytes that the entire frame takes up */
161 long var_size
; /* # bytes that variables take up */
162 long args_size
; /* # bytes that outgoing arguments take up */
163 long extra_size
; /* # bytes of extra gunk */
164 int gp_reg_size
; /* # bytes needed to store gp regs */
165 int fp_reg_size
; /* # bytes needed to store fp regs */
166 long mask
; /* mask of saved gp registers */
167 long fmask
; /* mask of saved fp registers */
168 long gp_save_offset
; /* offset from vfp to store gp registers */
169 long fp_save_offset
; /* offset from vfp to store fp registers */
170 long gp_sp_offset
; /* offset from new sp to store gp registers */
171 long fp_sp_offset
; /* offset from new sp to store fp registers */
172 int initialized
; /* != 0 if frame size already calculated */
173 int num_gp
; /* number of gp registers saved */
174 int num_fp
; /* number of fp registers saved */
177 struct machine_function
GTY(()) {
178 /* Pseudo-reg holding the address of the current function when
179 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS,
180 used by mips_finalize_pic if it was created. */
181 rtx embedded_pic_fnaddr_rtx
;
183 /* Pseudo-reg holding the value of $28 in a mips16 function which
184 refers to GP relative global variables. */
185 rtx mips16_gp_pseudo_rtx
;
187 /* Current frame information, calculated by compute_frame_size. */
188 struct mips_frame_info frame
;
190 /* Length of instructions in function; mips16 only. */
194 /* Information about a single argument. */
197 /* True if the argument is a record or union type. */
200 /* True if the argument is passed in a floating-point register, or
201 would have been if we hadn't run out of registers. */
204 /* The argument's size, in bytes. */
205 unsigned int num_bytes
;
207 /* The number of words passed in registers, rounded up. */
208 unsigned int reg_words
;
210 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
211 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
213 unsigned int reg_offset
;
215 /* The number of words that must be passed on the stack, rounded up. */
216 unsigned int stack_words
;
218 /* The offset from the start of the stack overflow area of the argument's
219 first stack word. Only meaningful when STACK_WORDS is non-zero. */
220 unsigned int stack_offset
;
223 /* Global variables for machine-dependent things. */
225 /* Threshold for data being put into the small data/bss area, instead
226 of the normal data area (references to the small data/bss area take
227 1 instruction, and use the global pointer, references to the normal
228 data area takes 2 instructions). */
229 int mips_section_threshold
= -1;
231 /* Count the number of .file directives, so that .loc is up to date. */
232 int num_source_filenames
= 0;
234 /* Count the number of sdb related labels are generated (to find block
235 start and end boundaries). */
236 int sdb_label_count
= 0;
238 /* Next label # for each statement for Silicon Graphics IRIS systems. */
241 /* Non-zero if inside of a function, because the stupid MIPS asm can't
242 handle .files inside of functions. */
243 int inside_function
= 0;
245 /* Files to separate the text and the data output, so that all of the data
246 can be emitted before the text, which will mean that the assembler will
247 generate smaller code, based on the global pointer. */
248 FILE *asm_out_data_file
;
249 FILE *asm_out_text_file
;
251 /* Linked list of all externals that are to be emitted when optimizing
252 for the global pointer if they haven't been declared by the end of
253 the program with an appropriate .comm or initialization. */
257 struct extern_list
*next
; /* next external */
258 const char *name
; /* name of the external */
259 int size
; /* size in bytes */
262 /* Name of the file containing the current function. */
263 const char *current_function_file
= "";
265 /* Warning given that Mips ECOFF can't support changing files
266 within a function. */
267 int file_in_function_warning
= FALSE
;
269 /* Whether to suppress issuing .loc's because the user attempted
270 to change the filename within a function. */
271 int ignore_line_number
= FALSE
;
273 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
279 /* The next branch instruction is a branch likely, not branch normal. */
280 int mips_branch_likely
;
282 /* Count of delay slots and how many are filled. */
283 int dslots_load_total
;
284 int dslots_load_filled
;
285 int dslots_jump_total
;
286 int dslots_jump_filled
;
288 /* # of nops needed by previous insn */
289 int dslots_number_nops
;
291 /* Number of 1/2/3 word references to data items (ie, not jal's). */
294 /* registers to check for load delay */
295 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
297 /* Cached operands, and operator to compare for use in set/branch/trap
298 on condition codes. */
301 /* what type of branch to use */
302 enum cmp_type branch_type
;
304 /* The target cpu for code generation. */
305 enum processor_type mips_arch
;
306 const struct mips_cpu_info
*mips_arch_info
;
308 /* The target cpu for optimization and scheduling. */
309 enum processor_type mips_tune
;
310 const struct mips_cpu_info
*mips_tune_info
;
312 /* which instruction set architecture to use. */
315 /* which abi to use. */
318 /* Strings to hold which cpu and instruction set architecture to use. */
319 const char *mips_arch_string
; /* for -march=<xxx> */
320 const char *mips_tune_string
; /* for -mtune=<xxx> */
321 const char *mips_isa_string
; /* for -mips{1,2,3,4} */
322 const char *mips_abi_string
; /* for -mabi={32,n32,64,eabi} */
324 /* Whether we are generating mips16 code. This is a synonym for
325 TARGET_MIPS16, and exists for use as an attribute. */
328 /* This variable is set by -mno-mips16. We only care whether
329 -mno-mips16 appears or not, and using a string in this fashion is
330 just a way to avoid using up another bit in target_flags. */
331 const char *mips_no_mips16_string
;
333 /* Whether we are generating mips16 hard float code. In mips16 mode
334 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
335 -msoft-float was not specified by the user, which means that we
336 should arrange to call mips32 hard floating point code. */
337 int mips16_hard_float
;
339 /* This variable is set by -mentry. We only care whether -mentry
340 appears or not, and using a string in this fashion is just a way to
341 avoid using up another bit in target_flags. */
342 const char *mips_entry_string
;
344 const char *mips_cache_flush_func
= CACHE_FLUSH_FUNC
;
346 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
349 /* If TRUE, we split addresses into their high and low parts in the RTL. */
350 int mips_split_addresses
;
352 /* Generating calls to position independent functions? */
353 enum mips_abicalls_type mips_abicalls
;
355 /* High and low marks for floating point values which we will accept
356 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
357 initialized in override_options. */
358 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
360 /* Mode used for saving/restoring general purpose registers. */
361 static enum machine_mode gpr_mode
;
363 /* Array giving truth value on whether or not a given hard register
364 can support a given mode. */
365 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
367 /* The length of all strings seen when compiling for the mips16. This
368 is used to tell how many strings are in the constant pool, so that
369 we can see if we may have an overflow. This is reset each time the
370 constant pool is output. */
371 int mips_string_length
;
373 /* In mips16 mode, we build a list of all the string constants we see
374 in a particular function. */
376 struct string_constant
378 struct string_constant
*next
;
382 static struct string_constant
*string_constants
;
384 /* List of all MIPS punctuation characters used by print_operand. */
385 char mips_print_operand_punct
[256];
387 /* Map GCC register number to debugger register number. */
388 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
390 /* Buffer to use to enclose a load/store operation with %{ %} to
391 turn on .set volatile. */
392 static char volatile_buffer
[60];
394 /* Hardware names for the registers. If -mrnames is used, this
395 will be overwritten with mips_sw_reg_names. */
397 char mips_reg_names
[][8] =
399 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
400 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
401 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
402 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
403 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
404 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
405 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
406 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
407 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
408 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
409 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
410 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
411 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
412 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
413 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
414 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
415 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
416 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
417 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
418 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
419 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
420 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
423 /* Mips software names for the registers, used to overwrite the
424 mips_reg_names array. */
426 char mips_sw_reg_names
[][8] =
428 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
429 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
430 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
431 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
432 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
433 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
434 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
435 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
436 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
437 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
438 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
439 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
440 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
441 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
442 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
443 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
444 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
445 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
446 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
447 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
448 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
449 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
452 /* Map hard register number to register class */
453 const enum reg_class mips_regno_to_class
[] =
455 GR_REGS
, GR_REGS
, M16_NA_REGS
, M16_NA_REGS
,
456 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
457 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
458 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
459 M16_NA_REGS
, M16_NA_REGS
, GR_REGS
, GR_REGS
,
460 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
461 T_REG
, GR_REGS
, GR_REGS
, GR_REGS
,
462 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
463 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
464 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
465 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
466 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
467 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
468 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
469 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
470 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
471 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
472 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
473 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
,
474 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
475 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
476 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
477 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
478 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
479 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
480 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
481 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
482 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
483 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
484 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
485 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
486 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
487 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
488 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
489 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
490 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
491 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
492 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
493 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
494 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
495 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
496 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
497 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
498 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
501 /* Map register constraint character to register class. */
502 enum reg_class mips_char_to_class
[256] =
504 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
505 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
506 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
507 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
508 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
509 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
510 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
511 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
512 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
513 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
514 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
515 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
516 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
517 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
518 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
519 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
520 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
521 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
522 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
523 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
524 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
525 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
526 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
527 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
528 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
529 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
530 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
531 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
532 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
533 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
534 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
535 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
536 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
537 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
538 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
539 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
540 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
541 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
542 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
543 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
544 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
545 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
546 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
547 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
548 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
549 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
550 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
551 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
552 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
553 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
554 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
555 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
556 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
557 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
558 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
559 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
560 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
561 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
562 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
563 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
564 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
565 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
566 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
567 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
570 /* A table describing all the processors gcc knows about. Names are
571 matched in the order listed. The first mention of an ISA level is
572 taken as the canonical name for that ISA.
574 To ease comparison, please keep this table in the same order as
575 gas's mips_cpu_info_table[]. */
576 const struct mips_cpu_info mips_cpu_info_table
[] = {
577 /* Entries for generic ISAs */
578 { "mips1", PROCESSOR_R3000
, 1 },
579 { "mips2", PROCESSOR_R6000
, 2 },
580 { "mips3", PROCESSOR_R4000
, 3 },
581 { "mips4", PROCESSOR_R8000
, 4 },
582 { "mips32", PROCESSOR_R4KC
, 32 },
583 { "mips64", PROCESSOR_R5KC
, 64 },
586 { "r3000", PROCESSOR_R3000
, 1 },
587 { "r2000", PROCESSOR_R3000
, 1 }, /* = r3000 */
588 { "r3900", PROCESSOR_R3900
, 1 },
591 { "r6000", PROCESSOR_R6000
, 2 },
594 { "r4000", PROCESSOR_R4000
, 3 },
595 { "vr4100", PROCESSOR_R4100
, 3 },
596 { "vr4111", PROCESSOR_R4111
, 3 },
597 { "vr4121", PROCESSOR_R4121
, 3 },
598 { "vr4300", PROCESSOR_R4300
, 3 },
599 { "vr4320", PROCESSOR_R4320
, 3 },
600 { "r4400", PROCESSOR_R4000
, 3 }, /* = r4000 */
601 { "r4600", PROCESSOR_R4600
, 3 },
602 { "orion", PROCESSOR_R4600
, 3 }, /* = r4600 */
603 { "r4650", PROCESSOR_R4650
, 3 },
606 { "r8000", PROCESSOR_R8000
, 4 },
607 { "vr5000", PROCESSOR_R5000
, 4 },
608 { "vr5400", PROCESSOR_R5400
, 4 },
609 { "vr5500", PROCESSOR_R5500
, 4 },
613 { "4kc", PROCESSOR_R4KC
, 32 },
614 { "4kp", PROCESSOR_R4KC
, 32 }, /* = 4kc */
617 { "5kc", PROCESSOR_R5KC
, 64 },
618 { "20kc", PROCESSOR_R20KC
, 64 },
619 { "sr71000", PROCESSOR_SR71000
, 64 },
621 /* Broadcom SB-1 CPU core */
622 { "sb1", PROCESSOR_SB1
, 64 },
628 /* Initialize the GCC target structure. */
629 #undef TARGET_ASM_ALIGNED_HI_OP
630 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
631 #undef TARGET_ASM_ALIGNED_SI_OP
632 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
633 #undef TARGET_ASM_INTEGER
634 #define TARGET_ASM_INTEGER mips_assemble_integer
636 #if TARGET_IRIX5 && !TARGET_IRIX6
637 #undef TARGET_ASM_UNALIGNED_HI_OP
638 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
639 #undef TARGET_ASM_UNALIGNED_SI_OP
640 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
641 #undef TARGET_ASM_UNALIGNED_DI_OP
642 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.dword\t"
645 #undef TARGET_ASM_FUNCTION_PROLOGUE
646 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
647 #undef TARGET_ASM_FUNCTION_EPILOGUE
648 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
649 #undef TARGET_ASM_SELECT_RTX_SECTION
650 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
652 #undef TARGET_SCHED_ADJUST_COST
653 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
654 #undef TARGET_SCHED_ISSUE_RATE
655 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
656 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
657 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
659 #undef TARGET_ENCODE_SECTION_INFO
660 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
662 struct gcc_target targetm
= TARGET_INITIALIZER
;
664 /* Return truth value of whether OP can be used as an operands
665 where a register or 16 bit unsigned integer is needed. */
668 uns_arith_operand (op
, mode
)
670 enum machine_mode mode
;
672 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
675 return register_operand (op
, mode
);
678 /* Return truth value of whether OP can be used as an operands
679 where a 16 bit integer is needed */
682 arith_operand (op
, mode
)
684 enum machine_mode mode
;
686 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
689 /* On the mips16, a GP relative value is a signed 16 bit offset. */
690 if (TARGET_MIPS16
&& GET_CODE (op
) == CONST
&& mips16_gp_offset_p (op
))
693 return register_operand (op
, mode
);
696 /* Return truth value of whether OP can be used as an operand in a two
697 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
700 arith32_operand (op
, mode
)
702 enum machine_mode mode
;
704 if (GET_CODE (op
) == CONST_INT
)
707 return register_operand (op
, mode
);
710 /* Return truth value of whether OP is an integer which fits in 16 bits. */
715 enum machine_mode mode ATTRIBUTE_UNUSED
;
717 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
720 /* Return truth value of whether OP is a 32 bit integer which is too big to
721 be loaded with one instruction. */
726 enum machine_mode mode ATTRIBUTE_UNUSED
;
730 if (GET_CODE (op
) != CONST_INT
)
735 /* ior reg,$r0,value */
736 if ((value
& ~ ((HOST_WIDE_INT
) 0x0000ffff)) == 0)
739 /* subu reg,$r0,value */
740 if (((unsigned HOST_WIDE_INT
) (value
+ 32768)) <= 32767)
743 /* lui reg,value>>16 */
744 if ((value
& 0x0000ffff) == 0)
750 /* Return truth value of whether OP is a register or the constant 0.
751 In mips16 mode, we only accept a register, since the mips16 does
755 reg_or_0_operand (op
, mode
)
757 enum machine_mode mode
;
759 switch (GET_CODE (op
))
764 return INTVAL (op
) == 0;
769 return op
== CONST0_RTX (mode
);
773 return register_operand (op
, mode
);
782 /* Return truth value of whether OP is a register or the constant 0,
783 even in mips16 mode. */
786 true_reg_or_0_operand (op
, mode
)
788 enum machine_mode mode
;
790 switch (GET_CODE (op
))
793 return INTVAL (op
) == 0;
796 return op
== CONST0_RTX (mode
);
800 return register_operand (op
, mode
);
809 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
812 mips_const_double_ok (op
, mode
)
814 enum machine_mode mode
;
818 if (GET_CODE (op
) != CONST_DOUBLE
)
821 if (mode
== VOIDmode
)
824 if (mode
!= SFmode
&& mode
!= DFmode
)
827 if (op
== CONST0_RTX (mode
))
830 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
831 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
&& mips_abi
!= ABI_EABI
)
834 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
836 if (REAL_VALUE_ISNAN (d
))
839 if (REAL_VALUE_NEGATIVE (d
))
840 d
= REAL_VALUE_NEGATE (d
);
844 if (REAL_VALUES_LESS (d
, dfhigh
)
845 && REAL_VALUES_LESS (dflow
, d
))
850 if (REAL_VALUES_LESS (d
, sfhigh
)
851 && REAL_VALUES_LESS (sflow
, d
))
858 /* Accept the floating point constant 1 in the appropriate mode. */
861 const_float_1_operand (op
, mode
)
863 enum machine_mode mode
;
866 static REAL_VALUE_TYPE onedf
;
867 static REAL_VALUE_TYPE onesf
;
868 static int one_initialized
;
870 if (GET_CODE (op
) != CONST_DOUBLE
871 || mode
!= GET_MODE (op
)
872 || (mode
!= DFmode
&& mode
!= SFmode
))
875 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
877 /* We only initialize these values if we need them, since we will
878 never get called unless mips_isa >= 4. */
879 if (! one_initialized
)
881 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
882 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
887 return REAL_VALUES_EQUAL (d
, onedf
);
889 return REAL_VALUES_EQUAL (d
, onesf
);
892 /* Return true if a memory load or store of REG plus OFFSET in MODE
893 can be represented in a single word on the mips16. */
896 mips16_simple_memory_operand (reg
, offset
, mode
)
899 enum machine_mode mode
;
906 /* We can't tell, because we don't know how the value will
907 eventually be accessed. Returning 0 here does no great
908 harm; it just prevents some possible instruction scheduling. */
912 size
= GET_MODE_SIZE (mode
);
914 if (INTVAL (offset
) % size
!= 0)
916 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& GET_MODE_SIZE (mode
) == 4)
920 if (INTVAL (offset
) >= 0 && INTVAL (offset
) < (HOST_WIDE_INT
)(off
* size
))
925 /* Return truth value if a memory operand fits in a single instruction
926 (ie, register + small offset). */
929 simple_memory_operand (op
, mode
)
931 enum machine_mode mode
;
933 rtx addr
, plus0
, plus1
;
935 /* Eliminate non-memory operations */
936 if (GET_CODE (op
) != MEM
)
939 /* dword operations really put out 2 instructions, so eliminate them. */
940 /* ??? This isn't strictly correct. It is OK to accept multiword modes
941 here, since the length attributes are being set correctly, but only
942 if the address is offsettable. LO_SUM is not offsettable. */
943 if (GET_MODE_SIZE (GET_MODE (op
)) > (unsigned) UNITS_PER_WORD
)
946 /* Decode the address now. */
948 switch (GET_CODE (addr
))
957 return SMALL_INT (addr
);
960 plus0
= XEXP (addr
, 0);
961 plus1
= XEXP (addr
, 1);
962 if (GET_CODE (plus0
) == REG
963 && GET_CODE (plus1
) == CONST_INT
&& SMALL_INT (plus1
)
965 || mips16_simple_memory_operand (plus0
, plus1
, mode
)))
968 else if (GET_CODE (plus1
) == REG
969 && GET_CODE (plus0
) == CONST_INT
&& SMALL_INT (plus0
)
971 || mips16_simple_memory_operand (plus1
, plus0
, mode
)))
978 /* We used to allow small symbol refs here (ie, stuff in .sdata
979 or .sbss), but this causes some bugs in G++. Also, it won't
980 interfere if the MIPS linker rewrites the store instruction
981 because the function is PIC. */
983 case LABEL_REF
: /* never gp relative */
987 /* If -G 0, we can never have a GP relative memory operation.
988 Also, save some time if not optimizing. */
993 rtx offset
= const0_rtx
;
994 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
995 if (GET_CODE (op
) != SYMBOL_REF
)
998 /* let's be paranoid.... */
999 if (! SMALL_INT (offset
))
1006 return SYMBOL_REF_FLAG (addr
);
1009 /* This SYMBOL_REF case is for the mips16. If the above case is
1010 reenabled, this one should be merged in. */
1012 /* References to the constant pool on the mips16 use a small
1013 offset if the function is small. The only time we care about
1014 getting this right is during delayed branch scheduling, so
1015 don't need to check until then. The machine_dependent_reorg
1016 function will set the total length of the instructions used
1017 in the function (cfun->machine->insns_len). If that is small
1018 enough, we know for sure that this is a small offset. It
1019 would be better if we could take into account the location of
1020 the instruction within the function, but we can't, because we
1021 don't know where we are. */
1023 && CONSTANT_POOL_ADDRESS_P (addr
)
1024 && cfun
->machine
->insns_len
> 0)
1028 size
= cfun
->machine
->insns_len
+ get_pool_size ();
1029 if (GET_MODE_SIZE (mode
) == 4)
1030 return size
< 4 * 0x100;
1031 else if (GET_MODE_SIZE (mode
) == 8)
1032 return size
< 8 * 0x20;
1046 /* Return nonzero for a memory address that can be used to load or store
1050 double_memory_operand (op
, mode
)
1052 enum machine_mode mode
;
1054 if (GET_CODE (op
) != MEM
1055 || ! memory_operand (op
, mode
))
1057 /* During reload, we accept a pseudo register if it has an
1058 appropriate memory address. If we don't do this, we will
1059 wind up reloading into a register, and then reloading that
1060 register from memory, when we could just reload directly from
1062 if (reload_in_progress
1063 && GET_CODE (op
) == REG
1064 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
1065 && reg_renumber
[REGNO (op
)] < 0
1066 && reg_equiv_mem
[REGNO (op
)] != 0
1067 && double_memory_operand (reg_equiv_mem
[REGNO (op
)], mode
))
1070 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
1071 the same test performed for 'm' in find_reloads. */
1073 if (reload_in_progress
1075 && (GET_CODE (op
) == MEM
1076 || (GET_CODE (op
) == REG
1077 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
1078 && reg_renumber
[REGNO (op
)] < 0)))
1081 if (reload_in_progress
1083 && GET_CODE (op
) == MEM
)
1087 addr
= XEXP (op
, 0);
1089 /* During reload on the mips16, we accept a large offset
1090 from the frame pointer or the stack pointer. This large
1091 address will get reloaded anyhow. */
1092 if (GET_CODE (addr
) == PLUS
1093 && GET_CODE (XEXP (addr
, 0)) == REG
1094 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1095 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
1096 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
1097 && ! SMALL_INT (XEXP (addr
, 1)))
1098 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
1099 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
1102 /* Similarly, we accept a case where the memory address is
1103 itself on the stack, and will be reloaded. */
1104 if (GET_CODE (addr
) == MEM
)
1108 maddr
= XEXP (addr
, 0);
1109 if (GET_CODE (maddr
) == PLUS
1110 && GET_CODE (XEXP (maddr
, 0)) == REG
1111 && (REGNO (XEXP (maddr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1112 || REGNO (XEXP (maddr
, 0)) == STACK_POINTER_REGNUM
)
1113 && ((GET_CODE (XEXP (maddr
, 1)) == CONST_INT
1114 && ! SMALL_INT (XEXP (maddr
, 1)))
1115 || (GET_CODE (XEXP (maddr
, 1)) == SYMBOL_REF
1116 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr
, 1)))))
1120 /* We also accept the same case when we have a 16 bit signed
1121 offset mixed in as well. The large address will get
1122 reloaded, and the 16 bit offset will be OK. */
1123 if (GET_CODE (addr
) == PLUS
1124 && GET_CODE (XEXP (addr
, 0)) == MEM
1125 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
1126 && SMALL_INT (XEXP (addr
, 1)))
1128 addr
= XEXP (XEXP (addr
, 0), 0);
1129 if (GET_CODE (addr
) == PLUS
1130 && GET_CODE (XEXP (addr
, 0)) == REG
1131 && (REGNO (XEXP (addr
, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1132 || REGNO (XEXP (addr
, 0)) == STACK_POINTER_REGNUM
)
1133 && ((GET_CODE (XEXP (addr
, 1)) == CONST_INT
1134 && ! SMALL_INT (XEXP (addr
, 1)))
1135 || (GET_CODE (XEXP (addr
, 1)) == SYMBOL_REF
1136 && CONSTANT_POOL_ADDRESS_P (XEXP (addr
, 1)))))
1146 /* In this case we can use an instruction like sd. */
1150 /* Make sure that 4 added to the address is a valid memory address.
1151 This essentially just checks for overflow in an added constant. */
1153 if (CONSTANT_ADDRESS_P (XEXP (op
, 0)))
1156 op
= adjust_address_nv (op
, GET_MODE_CLASS (mode
) == MODE_INT
1157 ? SImode
: SFmode
, 4);
1158 return memory_address_p (GET_MODE (op
), XEXP (op
, 0));
1161 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1164 equality_op (op
, mode
)
1166 enum machine_mode mode
;
1168 if (mode
!= GET_MODE (op
))
1171 return GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
;
1174 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1179 enum machine_mode mode
;
1181 if (mode
!= GET_MODE (op
))
1184 return GET_RTX_CLASS (GET_CODE (op
)) == '<';
1187 /* Return nonzero if the code is a relational operation suitable for a
1188 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1189 We need this in the insn that expands `trap_if' in order to prevent
1190 combine from erroneously altering the condition. */
1193 trap_cmp_op (op
, mode
)
1195 enum machine_mode mode
;
1197 if (mode
!= GET_MODE (op
))
1200 switch (GET_CODE (op
))
1215 /* Return nonzero if the operand is either the PC or a label_ref. */
1218 pc_or_label_operand (op
, mode
)
1220 enum machine_mode mode ATTRIBUTE_UNUSED
;
1225 if (GET_CODE (op
) == LABEL_REF
)
1231 /* Test for a valid operand for a call instruction.
1232 Don't allow the arg pointer register or virtual regs
1233 since they may change into reg + const, which the patterns
1234 can't handle yet. */
1237 call_insn_operand (op
, mode
)
1239 enum machine_mode mode ATTRIBUTE_UNUSED
;
1241 return (CONSTANT_ADDRESS_P (op
)
1242 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
1243 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1244 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)));
1247 /* Return nonzero if OPERAND is valid as a source operand for a move
1251 move_operand (op
, mode
)
1253 enum machine_mode mode
;
1255 /* Accept any general operand after reload has started; doing so
1256 avoids losing if reload does an in-place replacement of a register
1257 with a SYMBOL_REF or CONST. */
1258 return (general_operand (op
, mode
)
1259 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
1260 || reload_in_progress
|| reload_completed
)
1262 && GET_CODE (op
) == SYMBOL_REF
1263 && ! mips16_constant (op
, mode
, 1, 0)));
1266 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1267 This accepts not only general_operand, but also sign extended
1268 move_operands. Note that we need to accept sign extended constants
1269 in case a sign extended register which is used in an expression,
1270 and is equivalent to a constant, is spilled. We need to accept
1271 sign-extended memory in order to reload registers from stack slots,
1272 and so that we generate efficient code for extendsidi2. */
1275 movdi_operand (op
, mode
)
1277 enum machine_mode mode
;
1281 && GET_CODE (op
) == SIGN_EXTEND
1282 && GET_MODE (op
) == DImode
1283 && move_operand (XEXP (op
, 0), SImode
))
1286 return (general_operand (op
, mode
)
1288 && GET_CODE (op
) == SYMBOL_REF
1289 && ! mips16_constant (op
, mode
, 1, 0)));
1292 /* Like register_operand, but when in 64 bit mode also accept a sign
1293 extend of a 32 bit register, since the value is known to be already
1297 se_register_operand (op
, mode
)
1299 enum machine_mode mode
;
1303 && GET_CODE (op
) == SIGN_EXTEND
1304 && GET_MODE (op
) == DImode
1305 && GET_MODE (XEXP (op
, 0)) == SImode
1306 && register_operand (XEXP (op
, 0), SImode
))
1309 return register_operand (op
, mode
);
1312 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1313 extend of a 32 bit register, since the value is known to be already
1317 se_reg_or_0_operand (op
, mode
)
1319 enum machine_mode mode
;
1323 && GET_CODE (op
) == SIGN_EXTEND
1324 && GET_MODE (op
) == DImode
1325 && GET_MODE (XEXP (op
, 0)) == SImode
1326 && register_operand (XEXP (op
, 0), SImode
))
1329 return reg_or_0_operand (op
, mode
);
1332 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1333 extend of a 32 bit register, since the value is known to be already
1337 se_uns_arith_operand (op
, mode
)
1339 enum machine_mode mode
;
1343 && GET_CODE (op
) == SIGN_EXTEND
1344 && GET_MODE (op
) == DImode
1345 && GET_MODE (XEXP (op
, 0)) == SImode
1346 && register_operand (XEXP (op
, 0), SImode
))
1349 return uns_arith_operand (op
, mode
);
1352 /* Like arith_operand, but when in 64 bit mode also accept a sign
1353 extend of a 32 bit register, since the value is known to be already
1357 se_arith_operand (op
, mode
)
1359 enum machine_mode mode
;
1363 && GET_CODE (op
) == SIGN_EXTEND
1364 && GET_MODE (op
) == DImode
1365 && GET_MODE (XEXP (op
, 0)) == SImode
1366 && register_operand (XEXP (op
, 0), SImode
))
1369 return arith_operand (op
, mode
);
1372 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1373 extend of a 32 bit register, since the value is known to be already
1377 se_nonmemory_operand (op
, mode
)
1379 enum machine_mode mode
;
1383 && GET_CODE (op
) == SIGN_EXTEND
1384 && GET_MODE (op
) == DImode
1385 && GET_MODE (XEXP (op
, 0)) == SImode
1386 && register_operand (XEXP (op
, 0), SImode
))
1389 return nonmemory_operand (op
, mode
);
1392 /* Accept any operand that can appear in a mips16 constant table
1393 instruction. We can't use any of the standard operand functions
1394 because for these instructions we accept values that are not
1395 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1398 consttable_operand (op
, mode
)
1400 enum machine_mode mode ATTRIBUTE_UNUSED
;
1402 return CONSTANT_P (op
);
1405 /* Coprocessor operand; return true if rtx is a REG and refers to a
1409 coprocessor_operand (op
, mode
)
1411 enum machine_mode mode ATTRIBUTE_UNUSED
;
1413 return (GET_CODE (op
) == REG
1414 && COP0_REG_FIRST
<= REGNO (op
)
1415 && REGNO (op
) <= COP3_REG_LAST
);
1419 coprocessor2_operand (op
, mode
)
1421 enum machine_mode mode ATTRIBUTE_UNUSED
;
1423 return (GET_CODE (op
) == REG
1424 && COP2_REG_FIRST
<= REGNO (op
)
1425 && REGNO (op
) <= COP2_REG_LAST
);
1428 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1429 possibly with an offset. */
1432 symbolic_operand (op
, mode
)
1434 enum machine_mode mode
;
1436 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1438 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
1440 if (GET_CODE (op
) == CONST
1441 && GET_CODE (XEXP (op
,0)) == PLUS
1442 && GET_CODE (XEXP (XEXP (op
,0), 0)) == SYMBOL_REF
1443 && GET_CODE (XEXP (XEXP (op
,0), 1)) == CONST_INT
)
1448 /* Return nonzero if we split the address into high and low parts. */
1450 /* ??? We should also handle reg+array somewhere. We get four
1451 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1452 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1453 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1454 out of the address, then we have 4 instructions to combine. Perhaps
1455 add a 3->2 define_split for combine. */
1457 /* ??? We could also split a CONST_INT here if it is a large_int().
1458 However, it doesn't seem to be very useful to have %hi(constant).
1459 We would be better off by doing the masking ourselves and then putting
1460 the explicit high part of the constant in the RTL. This will give better
1461 optimization. Also, %hi(constant) needs assembler changes to work.
1462 There is already a define_split that does this. */
1465 mips_check_split (address
, mode
)
1467 enum machine_mode mode
;
1469 /* ??? This is the same check used in simple_memory_operand.
1470 We use it here because LO_SUM is not offsettable. */
1471 if (GET_MODE_SIZE (mode
) > (unsigned) UNITS_PER_WORD
)
1474 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
1475 || (GET_CODE (address
) == CONST
1476 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
1477 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
1478 || GET_CODE (address
) == LABEL_REF
)
1484 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1487 mips_reg_mode_ok_for_base_p (reg
, mode
, strict
)
1489 enum machine_mode mode
;
1493 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg
), mode
)
1494 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg
), mode
));
1497 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1498 returns a nonzero value if XINSN is a legitimate address for a
1499 memory operand of the indicated MODE. STRICT is non-zero if this
1500 function is called during reload. */
1503 mips_legitimate_address_p (mode
, xinsn
, strict
)
1504 enum machine_mode mode
;
1508 if (TARGET_DEBUG_B_MODE
)
1510 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1511 strict
? "" : "not ");
1512 GO_DEBUG_RTX (xinsn
);
1515 /* Check for constant before stripping off SUBREG, so that we don't
1516 accept (subreg (const_int)) which will fail to reload. */
1517 if (CONSTANT_ADDRESS_P (xinsn
)
1518 && ! (mips_split_addresses
&& mips_check_split (xinsn
, mode
))
1519 && (! TARGET_MIPS16
|| mips16_constant (xinsn
, mode
, 1, 0)))
1522 while (GET_CODE (xinsn
) == SUBREG
)
1523 xinsn
= SUBREG_REG (xinsn
);
1525 /* The mips16 can only use the stack pointer as a base register when
1526 loading SImode or DImode values. */
1527 if (GET_CODE (xinsn
) == REG
1528 && mips_reg_mode_ok_for_base_p (xinsn
, mode
, strict
))
1531 if (GET_CODE (xinsn
) == LO_SUM
&& mips_split_addresses
)
1533 register rtx xlow0
= XEXP (xinsn
, 0);
1534 register rtx xlow1
= XEXP (xinsn
, 1);
1536 while (GET_CODE (xlow0
) == SUBREG
)
1537 xlow0
= SUBREG_REG (xlow0
);
1538 if (GET_CODE (xlow0
) == REG
1539 && mips_reg_mode_ok_for_base_p (xlow0
, mode
, strict
)
1540 && mips_check_split (xlow1
, mode
))
1544 if (GET_CODE (xinsn
) == PLUS
)
1546 register rtx xplus0
= XEXP (xinsn
, 0);
1547 register rtx xplus1
= XEXP (xinsn
, 1);
1548 register enum rtx_code code0
;
1549 register enum rtx_code code1
;
1551 while (GET_CODE (xplus0
) == SUBREG
)
1552 xplus0
= SUBREG_REG (xplus0
);
1553 code0
= GET_CODE (xplus0
);
1555 while (GET_CODE (xplus1
) == SUBREG
)
1556 xplus1
= SUBREG_REG (xplus1
);
1557 code1
= GET_CODE (xplus1
);
1559 /* The mips16 can only use the stack pointer as a base register
1560 when loading SImode or DImode values. */
1562 && mips_reg_mode_ok_for_base_p (xplus0
, mode
, strict
))
1564 if (code1
== CONST_INT
&& SMALL_INT (xplus1
))
1567 /* On the mips16, we represent GP relative offsets in RTL.
1568 These are 16 bit signed values, and can serve as register
1571 && mips16_gp_offset_p (xplus1
))
1574 /* For some code sequences, you actually get better code by
1575 pretending that the MIPS supports an address mode of a
1576 constant address + a register, even though the real
1577 machine doesn't support it. This is because the
1578 assembler can use $r1 to load just the high 16 bits, add
1579 in the register, and fold the low 16 bits into the memory
1580 reference, whereas the compiler generates a 4 instruction
1581 sequence. On the other hand, CSE is not as effective.
1582 It would be a win to generate the lui directly, but the
1583 MIPS assembler does not have syntax to generate the
1584 appropriate relocation. */
1586 /* Also accept CONST_INT addresses here, so no else. */
1587 /* Reject combining an embedded PIC text segment reference
1588 with a register. That requires an additional
1590 /* ??? Reject combining an address with a register for the MIPS
1591 64 bit ABI, because the SGI assembler can not handle this. */
1592 if (!TARGET_DEBUG_A_MODE
1593 && (mips_abi
== ABI_32
1594 || mips_abi
== ABI_O64
1595 || mips_abi
== ABI_EABI
)
1596 && CONSTANT_ADDRESS_P (xplus1
)
1597 && ! mips_split_addresses
1598 && (!TARGET_EMBEDDED_PIC
1600 || GET_CODE (XEXP (xplus1
, 0)) != MINUS
)
1601 /* When assembling for machines with 64 bit registers,
1602 the assembler will sign-extend the constant "foo"
1603 in "la x, foo(x)" yielding the wrong result for:
1604 (set (blah:DI) (plus x y)). */
1606 || (code1
== CONST_INT
1607 && trunc_int_for_mode (INTVAL (xplus1
),
1608 SImode
) == INTVAL (xplus1
)))
1614 if (TARGET_DEBUG_B_MODE
)
1615 GO_PRINTF ("Not a legitimate address\n");
1617 /* The address was not legitimate. */
1622 /* We need a lot of little routines to check constant values on the
1623 mips16. These are used to figure out how long the instruction will
1624 be. It would be much better to do this using constraints, but
1625 there aren't nearly enough letters available. */
1628 m16_check_op (op
, low
, high
, mask
)
1634 return (GET_CODE (op
) == CONST_INT
1635 && INTVAL (op
) >= low
1636 && INTVAL (op
) <= high
1637 && (INTVAL (op
) & mask
) == 0);
1641 m16_uimm3_b (op
, mode
)
1643 enum machine_mode mode ATTRIBUTE_UNUSED
;
1645 return m16_check_op (op
, 0x1, 0x8, 0);
1649 m16_simm4_1 (op
, mode
)
1651 enum machine_mode mode ATTRIBUTE_UNUSED
;
1653 return m16_check_op (op
, - 0x8, 0x7, 0);
1657 m16_nsimm4_1 (op
, mode
)
1659 enum machine_mode mode ATTRIBUTE_UNUSED
;
1661 return m16_check_op (op
, - 0x7, 0x8, 0);
1665 m16_simm5_1 (op
, mode
)
1667 enum machine_mode mode ATTRIBUTE_UNUSED
;
1669 return m16_check_op (op
, - 0x10, 0xf, 0);
1673 m16_nsimm5_1 (op
, mode
)
1675 enum machine_mode mode ATTRIBUTE_UNUSED
;
1677 return m16_check_op (op
, - 0xf, 0x10, 0);
1681 m16_uimm5_4 (op
, mode
)
1683 enum machine_mode mode ATTRIBUTE_UNUSED
;
1685 return m16_check_op (op
, (- 0x10) << 2, 0xf << 2, 3);
1689 m16_nuimm5_4 (op
, mode
)
1691 enum machine_mode mode ATTRIBUTE_UNUSED
;
1693 return m16_check_op (op
, (- 0xf) << 2, 0x10 << 2, 3);
1697 m16_simm8_1 (op
, mode
)
1699 enum machine_mode mode ATTRIBUTE_UNUSED
;
1701 return m16_check_op (op
, - 0x80, 0x7f, 0);
1705 m16_nsimm8_1 (op
, mode
)
1707 enum machine_mode mode ATTRIBUTE_UNUSED
;
1709 return m16_check_op (op
, - 0x7f, 0x80, 0);
1713 m16_uimm8_1 (op
, mode
)
1715 enum machine_mode mode ATTRIBUTE_UNUSED
;
1717 return m16_check_op (op
, 0x0, 0xff, 0);
1721 m16_nuimm8_1 (op
, mode
)
1723 enum machine_mode mode ATTRIBUTE_UNUSED
;
1725 return m16_check_op (op
, - 0xff, 0x0, 0);
1729 m16_uimm8_m1_1 (op
, mode
)
1731 enum machine_mode mode ATTRIBUTE_UNUSED
;
1733 return m16_check_op (op
, - 0x1, 0xfe, 0);
1737 m16_uimm8_4 (op
, mode
)
1739 enum machine_mode mode ATTRIBUTE_UNUSED
;
1741 return m16_check_op (op
, 0x0, 0xff << 2, 3);
1745 m16_nuimm8_4 (op
, mode
)
1747 enum machine_mode mode ATTRIBUTE_UNUSED
;
1749 return m16_check_op (op
, (- 0xff) << 2, 0x0, 3);
1753 m16_simm8_8 (op
, mode
)
1755 enum machine_mode mode ATTRIBUTE_UNUSED
;
1757 return m16_check_op (op
, (- 0x80) << 3, 0x7f << 3, 7);
1761 m16_nsimm8_8 (op
, mode
)
1763 enum machine_mode mode ATTRIBUTE_UNUSED
;
1765 return m16_check_op (op
, (- 0x7f) << 3, 0x80 << 3, 7);
1768 /* References to the string table on the mips16 only use a small
1769 offset if the function is small. See the comment in the SYMBOL_REF
1770 case in simple_memory_operand. We can't check for LABEL_REF here,
1771 because the offset is always large if the label is before the
1772 referencing instruction. */
1775 m16_usym8_4 (op
, mode
)
1777 enum machine_mode mode ATTRIBUTE_UNUSED
;
1779 if (GET_CODE (op
) == SYMBOL_REF
1780 && SYMBOL_REF_FLAG (op
)
1781 && cfun
->machine
->insns_len
> 0
1782 && XSTR (op
, 0)[0] == '*'
1783 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1784 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1785 && (cfun
->machine
->insns_len
+ get_pool_size () + mips_string_length
1788 struct string_constant
*l
;
1790 /* Make sure this symbol is on thelist of string constants to be
1791 output for this function. It is possible that it has already
1792 been output, in which case this requires a large offset. */
1793 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1794 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1802 m16_usym5_4 (op
, mode
)
1804 enum machine_mode mode ATTRIBUTE_UNUSED
;
1806 if (GET_CODE (op
) == SYMBOL_REF
1807 && SYMBOL_REF_FLAG (op
)
1808 && cfun
->machine
->insns_len
> 0
1809 && XSTR (op
, 0)[0] == '*'
1810 && strncmp (XSTR (op
, 0) + 1, LOCAL_LABEL_PREFIX
,
1811 sizeof LOCAL_LABEL_PREFIX
- 1) == 0
1812 && (cfun
->machine
->insns_len
+ get_pool_size () + mips_string_length
1815 struct string_constant
*l
;
1817 /* Make sure this symbol is on thelist of string constants to be
1818 output for this function. It is possible that it has already
1819 been output, in which case this requires a large offset. */
1820 for (l
= string_constants
; l
!= NULL
; l
= l
->next
)
1821 if (strcmp (l
->label
, XSTR (op
, 0)) == 0)
1828 /* Returns an operand string for the given instruction's delay slot,
1829 after updating filled delay slot statistics.
1831 We assume that operands[0] is the target register that is set.
1833 In order to check the next insn, most of this functionality is moved
1834 to FINAL_PRESCAN_INSN, and we just set the global variables that
1837 /* ??? This function no longer does anything useful, because final_prescan_insn
1838 now will never emit a nop. */
1841 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
1842 const char *ret
; /* normal string to return */
1843 enum delay_type type
; /* type of delay */
1844 rtx operands
[]; /* operands to use */
1845 rtx cur_insn
; /* current insn */
1847 register rtx set_reg
;
1848 register enum machine_mode mode
;
1849 register rtx next_insn
= cur_insn
? NEXT_INSN (cur_insn
) : NULL_RTX
;
1850 register int num_nops
;
1852 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
1855 else if (type
== DELAY_HILO
)
1861 /* Make sure that we don't put nop's after labels. */
1862 next_insn
= NEXT_INSN (cur_insn
);
1863 while (next_insn
!= 0 && GET_CODE (next_insn
) == NOTE
)
1864 next_insn
= NEXT_INSN (next_insn
);
1866 dslots_load_total
+= num_nops
;
1867 if (TARGET_DEBUG_F_MODE
1869 || type
== DELAY_NONE
1873 || GET_CODE (next_insn
) == CODE_LABEL
1874 || (set_reg
= operands
[0]) == 0)
1876 dslots_number_nops
= 0;
1884 set_reg
= operands
[0];
1888 while (GET_CODE (set_reg
) == SUBREG
)
1889 set_reg
= SUBREG_REG (set_reg
);
1891 mode
= GET_MODE (set_reg
);
1892 dslots_number_nops
= num_nops
;
1893 mips_load_reg
= set_reg
;
1894 if (GET_MODE_SIZE (mode
)
1895 > (unsigned) (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
1896 mips_load_reg2
= gen_rtx_REG (SImode
, REGNO (set_reg
) + 1);
1900 if (type
== DELAY_HILO
)
1902 mips_load_reg3
= gen_rtx_REG (SImode
, MD_REG_FIRST
);
1903 mips_load_reg4
= gen_rtx_REG (SImode
, MD_REG_FIRST
+1);
1915 /* Determine whether a memory reference takes one (based off of the GP
1916 pointer), two (normal), or three (label + reg) instructions, and bump the
1917 appropriate counter for -mstats. */
1920 mips_count_memory_refs (op
, num
)
1926 rtx addr
, plus0
, plus1
;
1927 enum rtx_code code0
, code1
;
1930 if (TARGET_DEBUG_B_MODE
)
1932 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
1936 /* Skip MEM if passed, otherwise handle movsi of address. */
1937 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
1939 /* Loop, going through the address RTL. */
1943 switch (GET_CODE (addr
))
1951 plus0
= XEXP (addr
, 0);
1952 plus1
= XEXP (addr
, 1);
1953 code0
= GET_CODE (plus0
);
1954 code1
= GET_CODE (plus1
);
1964 if (code0
== CONST_INT
)
1979 if (code1
== CONST_INT
)
1986 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1993 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
2003 n_words
= 2; /* always 2 words */
2007 addr
= XEXP (addr
, 0);
2012 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
2024 n_words
+= additional
;
2028 num_refs
[n_words
-1] += num
;
2032 /* Return a pseudo that points to the address of the current function.
2033 The first time it is called for a function, an initializer for the
2034 pseudo is emitted in the beginning of the function. */
2037 embedded_pic_fnaddr_reg ()
2039 if (cfun
->machine
->embedded_pic_fnaddr_rtx
== NULL
)
2043 cfun
->machine
->embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
2045 /* Output code at function start to initialize the pseudo-reg. */
2046 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2047 inline functions, because it is called after RTL for the function
2048 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2049 does not get copied, and ends up not matching the rest of the RTL.
2050 This solution works, but means that we get unnecessary code to
2051 initialize this value every time a function is inlined into another
2054 emit_insn (gen_get_fnaddr (cfun
->machine
->embedded_pic_fnaddr_rtx
,
2055 XEXP (DECL_RTL (current_function_decl
), 0)));
2058 push_topmost_sequence ();
2059 emit_insn_after (seq
, get_insns ());
2060 pop_topmost_sequence ();
2063 return cfun
->machine
->embedded_pic_fnaddr_rtx
;
2066 /* Return RTL for the offset from the current function to the argument.
2067 X is the symbol whose offset from the current function we want. */
2070 embedded_pic_offset (x
)
2073 /* Make sure it is emitted. */
2074 embedded_pic_fnaddr_reg ();
2077 gen_rtx_CONST (Pmode
,
2078 gen_rtx_MINUS (Pmode
, x
,
2079 XEXP (DECL_RTL (current_function_decl
), 0)));
2082 /* Return the appropriate instructions to move one operand to another. */
2085 mips_move_1word (operands
, insn
, unsignedp
)
2090 const char *ret
= 0;
2091 rtx op0
= operands
[0];
2092 rtx op1
= operands
[1];
2093 enum rtx_code code0
= GET_CODE (op0
);
2094 enum rtx_code code1
= GET_CODE (op1
);
2095 enum machine_mode mode
= GET_MODE (op0
);
2096 int subreg_offset0
= 0;
2097 int subreg_offset1
= 0;
2098 enum delay_type delay
= DELAY_NONE
;
2100 while (code0
== SUBREG
)
2102 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2103 GET_MODE (SUBREG_REG (op0
)),
2106 op0
= SUBREG_REG (op0
);
2107 code0
= GET_CODE (op0
);
2110 while (code1
== SUBREG
)
2112 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2113 GET_MODE (SUBREG_REG (op1
)),
2116 op1
= SUBREG_REG (op1
);
2117 code1
= GET_CODE (op1
);
2120 /* For our purposes, a condition code mode is the same as SImode. */
2126 int regno0
= REGNO (op0
) + subreg_offset0
;
2130 int regno1
= REGNO (op1
) + subreg_offset1
;
2132 /* Just in case, don't do anything for assigning a register
2133 to itself, unless we are filling a delay slot. */
2134 if (regno0
== regno1
&& set_nomacro
== 0)
2137 else if (GP_REG_P (regno0
))
2139 if (GP_REG_P (regno1
))
2140 ret
= "move\t%0,%1";
2142 else if (MD_REG_P (regno1
))
2145 if (regno1
!= HILO_REGNUM
)
2151 else if (ST_REG_P (regno1
) && ISA_HAS_8CC
)
2152 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
2157 if (FP_REG_P (regno1
))
2158 ret
= "mfc1\t%0,%1";
2159 else if (ALL_COP_REG_P (regno1
))
2161 static char retval
[] = "mfc_\t%0,%1";
2163 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2166 else if (regno1
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
2167 ret
= "cfc1\t%0,$31";
2171 else if (FP_REG_P (regno0
))
2173 if (GP_REG_P (regno1
))
2176 ret
= "mtc1\t%1,%0";
2179 if (FP_REG_P (regno1
))
2180 ret
= "mov.s\t%0,%1";
2183 else if (MD_REG_P (regno0
))
2185 if (GP_REG_P (regno1
))
2188 if (regno0
!= HILO_REGNUM
&& ! TARGET_MIPS16
)
2193 else if (regno0
== FPSW_REGNUM
&& ! ISA_HAS_8CC
)
2195 if (GP_REG_P (regno1
))
2198 ret
= "ctc1\t%0,$31";
2201 else if (ALL_COP_REG_P (regno0
))
2203 if (GP_REG_P (regno1
))
2205 static char retval
[] = "mtc_\t%1,%0";
2206 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2209 abort_with_insn (insn
,
2210 "mtc0 not supported; it disturbs virtual address translation");
2218 else if (code1
== MEM
)
2223 mips_count_memory_refs (op1
, 1);
2225 if (GP_REG_P (regno0
))
2227 /* For loads, use the mode of the memory item, instead of the
2228 target, so zero/sign extend can use this code as well. */
2229 switch (GET_MODE (op1
))
2238 ret
= ((unsignedp
&& TARGET_64BIT
)
2243 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
2246 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
2251 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
2254 else if (ALL_COP_REG_P (regno0
))
2256 static char retval
[] = "lwc_\t%0,%1";
2257 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2260 abort_with_insn (insn
,
2261 "loads from memory to COP0 are illegal");
2267 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
2269 size_t i
= strlen (ret
);
2270 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2273 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2274 ret
= volatile_buffer
;
2278 else if (code1
== CONST_INT
2279 || (code1
== CONST_DOUBLE
2280 && GET_MODE (op1
) == VOIDmode
))
2282 if (code1
== CONST_DOUBLE
)
2284 /* This can happen when storing constants into long long
2285 bitfields. Just store the least significant word of
2287 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2290 if (INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2292 if (GP_REG_P (regno0
))
2293 ret
= "move\t%0,%z1";
2295 else if (FP_REG_P (regno0
))
2298 ret
= "mtc1\t%z1,%0";
2301 else if (MD_REG_P (regno0
))
2308 else if (GP_REG_P (regno0
))
2310 /* Don't use X format, because that will give out of
2311 range numbers for 64 bit host and 32 bit target. */
2312 if (! TARGET_MIPS16
)
2313 ret
= "li\t%0,%1\t\t\t# %X1";
2316 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2318 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2319 ret
= "li\t%0,%n1\n\tneg\t%0";
2324 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
2326 if (op1
== CONST0_RTX (SFmode
))
2328 if (GP_REG_P (regno0
))
2329 ret
= "move\t%0,%.";
2331 else if (FP_REG_P (regno0
))
2334 ret
= "mtc1\t%.,%0";
2341 ret
= "li.s\t%0,%1";
2345 else if (code1
== LABEL_REF
)
2348 mips_count_memory_refs (op1
, 1);
2353 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2357 && GET_CODE (XEXP (op1
, 0)) == REG
2358 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2360 /* This case arises on the mips16; see
2361 mips16_gp_pseudo_reg. */
2362 ret
= "move\t%0,%+";
2364 else if (TARGET_MIPS16
2365 && code1
== SYMBOL_REF
2366 && SYMBOL_REF_FLAG (op1
)
2367 && (XSTR (op1
, 0)[0] != '*'
2368 || strncmp (XSTR (op1
, 0) + 1,
2370 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2372 /* This can occur when reloading the address of a GP
2373 relative symbol on the mips16. */
2374 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2379 mips_count_memory_refs (op1
, 1);
2385 else if (code1
== PLUS
)
2387 rtx add_op0
= XEXP (op1
, 0);
2388 rtx add_op1
= XEXP (op1
, 1);
2390 if (GET_CODE (XEXP (op1
, 1)) == REG
2391 && GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
2392 add_op0
= XEXP (op1
, 1), add_op1
= XEXP (op1
, 0);
2394 operands
[2] = add_op0
;
2395 operands
[3] = add_op1
;
2396 ret
= "add%:\t%0,%2,%3";
2399 else if (code1
== HIGH
)
2401 operands
[1] = XEXP (op1
, 0);
2402 ret
= "lui\t%0,%%hi(%1)";
2406 else if (code0
== MEM
)
2409 mips_count_memory_refs (op0
, 1);
2413 int regno1
= REGNO (op1
) + subreg_offset1
;
2415 if (GP_REG_P (regno1
))
2419 case SFmode
: ret
= "sw\t%1,%0"; break;
2420 case SImode
: ret
= "sw\t%1,%0"; break;
2421 case HImode
: ret
= "sh\t%1,%0"; break;
2422 case QImode
: ret
= "sb\t%1,%0"; break;
2427 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
2429 else if (ALL_COP_REG_P (regno1
))
2431 static char retval
[] = "swc_\t%1,%0";
2433 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2438 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
2442 case SFmode
: ret
= "sw\t%z1,%0"; break;
2443 case SImode
: ret
= "sw\t%z1,%0"; break;
2444 case HImode
: ret
= "sh\t%z1,%0"; break;
2445 case QImode
: ret
= "sb\t%z1,%0"; break;
2450 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
2454 case SFmode
: ret
= "sw\t%.,%0"; break;
2455 case SImode
: ret
= "sw\t%.,%0"; break;
2456 case HImode
: ret
= "sh\t%.,%0"; break;
2457 case QImode
: ret
= "sb\t%.,%0"; break;
2462 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
2464 size_t i
= strlen (ret
);
2466 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2469 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2470 ret
= volatile_buffer
;
2476 abort_with_insn (insn
, "bad move");
2480 if (delay
!= DELAY_NONE
)
2481 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
2486 /* Return instructions to restore the global pointer from the stack,
2487 assuming TARGET_ABICALLS. Used by exception_receiver to set up
2488 the GP for exception handlers.
2490 OPERANDS is an array of operands whose contents are undefined
2491 on entry. INSN is the exception_handler instruction. */
2494 mips_restore_gp (operands
, insn
)
2495 rtx
*operands
, insn
;
2499 operands
[0] = pic_offset_table_rtx
;
2500 if (frame_pointer_needed
)
2501 loc
= hard_frame_pointer_rtx
;
2503 loc
= stack_pointer_rtx
;
2504 loc
= plus_constant (loc
, cfun
->machine
->frame
.args_size
);
2505 operands
[1] = gen_rtx_MEM (Pmode
, loc
);
2507 return mips_move_1word (operands
, insn
, 0);
2510 /* Return an instruction to sign-extend SImode value SRC and store it
2511 in DImode value DEST. INSN is the original extendsidi2-type insn. */
2514 mips_sign_extend (insn
, dest
, src
)
2515 rtx insn
, dest
, src
;
2517 rtx operands
[MAX_RECOG_OPERANDS
];
2519 if ((register_operand (src
, SImode
) && FP_REG_P (true_regnum (src
)))
2520 || memory_operand (src
, SImode
))
2522 /* If the source is a floating-point register, we need to use a
2523 32-bit move, since the float register is not kept sign-extended.
2524 If the source is in memory, we need a 32-bit load. */
2525 operands
[0] = gen_lowpart_SUBREG (SImode
, dest
);
2527 return mips_move_1word (operands
, insn
, false);
2533 return mips_move_2words (operands
, insn
);
2537 /* Return the appropriate instructions to move 2 words */
2540 mips_move_2words (operands
, insn
)
2544 const char *ret
= 0;
2545 rtx op0
= operands
[0];
2546 rtx op1
= operands
[1];
2547 enum rtx_code code0
= GET_CODE (operands
[0]);
2548 enum rtx_code code1
= GET_CODE (operands
[1]);
2549 int subreg_offset0
= 0;
2550 int subreg_offset1
= 0;
2551 enum delay_type delay
= DELAY_NONE
;
2553 if (code1
== SIGN_EXTEND
)
2554 return mips_sign_extend (insn
, op0
, XEXP (op1
, 0));
2556 while (code0
== SUBREG
)
2558 subreg_offset0
+= subreg_regno_offset (REGNO (SUBREG_REG (op0
)),
2559 GET_MODE (SUBREG_REG (op0
)),
2562 op0
= SUBREG_REG (op0
);
2563 code0
= GET_CODE (op0
);
2566 while (code1
== SUBREG
)
2568 subreg_offset1
+= subreg_regno_offset (REGNO (SUBREG_REG (op1
)),
2569 GET_MODE (SUBREG_REG (op1
)),
2572 op1
= SUBREG_REG (op1
);
2573 code1
= GET_CODE (op1
);
2578 int regno0
= REGNO (op0
) + subreg_offset0
;
2582 int regno1
= REGNO (op1
) + subreg_offset1
;
2584 /* Just in case, don't do anything for assigning a register
2585 to itself, unless we are filling a delay slot. */
2586 if (regno0
== regno1
&& set_nomacro
== 0)
2589 else if (FP_REG_P (regno0
))
2591 if (FP_REG_P (regno1
))
2592 ret
= "mov.d\t%0,%1";
2600 abort_with_insn (insn
, "bad move");
2602 #ifdef TARGET_FP_CALL_32
2603 if (FP_CALL_GP_REG_P (regno1
))
2604 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2607 ret
= "dmtc1\t%1,%0";
2610 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2614 else if (FP_REG_P (regno1
))
2620 abort_with_insn (insn
, "bad move");
2622 #ifdef TARGET_FP_CALL_32
2623 if (FP_CALL_GP_REG_P (regno0
))
2624 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2627 ret
= "dmfc1\t%0,%1";
2630 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2633 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
) && !TARGET_MIPS16
)
2638 if (regno0
!= HILO_REGNUM
)
2640 else if (regno1
== 0)
2641 ret
= "mtlo\t%.\n\tmthi\t%.";
2644 ret
= "mthi\t%M1\n\tmtlo\t%L1";
2647 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
2652 if (regno1
!= HILO_REGNUM
)
2656 ret
= "mfhi\t%M0\n\tmflo\t%L0";
2658 else if (GP_REG_P (regno0
) && ALL_COP_REG_P (regno1
)
2661 static char retval
[] = "dmfc_\t%0,%1";
2664 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2667 else if (ALL_COP_REG_P (regno0
) && GP_REG_P (regno1
)
2670 static char retval
[] = "dmtc_\t%1,%0";
2671 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2674 abort_with_insn (insn
,
2675 "dmtc0 not supported; it disturbs virtual address translation");
2680 else if (TARGET_64BIT
)
2681 ret
= "move\t%0,%1";
2683 else if (regno0
!= (regno1
+1))
2684 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
2687 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
2690 else if (code1
== CONST_DOUBLE
)
2692 /* Move zero from $0 unless !TARGET_64BIT and recipient
2693 is 64-bit fp reg, in which case generate a constant. */
2694 if (op1
!= CONST0_RTX (GET_MODE (op1
))
2695 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
2697 if (GET_MODE (op1
) == DFmode
)
2701 #ifdef TARGET_FP_CALL_32
2702 if (FP_CALL_GP_REG_P (regno0
))
2704 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
2706 split_double (op1
, operands
+ 2, operands
+ 3);
2707 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2710 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2714 /* GNU as emits 64-bit code for li.d if the ISA is 3
2715 or higher. For !TARGET_64BIT && gp registers we
2716 need to avoid this by using two li instructions
2718 if (ISA_HAS_64BIT_REGS
2720 && ! FP_REG_P (regno0
))
2722 split_double (op1
, operands
+ 2, operands
+ 3);
2723 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2726 ret
= "li.d\t%0,%1";
2729 else if (TARGET_64BIT
)
2731 if (! TARGET_MIPS16
)
2737 split_double (op1
, operands
+ 2, operands
+ 3);
2738 ret
= "li\t%0,%2\n\tli\t%D0,%3";
2744 if (GP_REG_P (regno0
))
2746 #ifdef TARGET_FP_CALL_32
2747 && ! FP_CALL_GP_REG_P (regno0
)
2750 : "move\t%0,%.\n\tmove\t%D0,%.");
2752 else if (FP_REG_P (regno0
))
2757 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2762 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0 && ! TARGET_MIPS16
)
2764 if (GP_REG_P (regno0
))
2767 : "move\t%0,%.\n\tmove\t%D0,%.");
2769 else if (FP_REG_P (regno0
))
2776 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2778 else if (MD_REG_P (regno0
))
2781 ret
= (regno0
== HILO_REGNUM
2782 ? "mtlo\t%.\n\tmthi\t%."
2787 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
2788 && GP_REG_P (regno0
))
2794 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2796 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2797 ret
= "li\t%0,%n1\n\tneg\t%0";
2799 else if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2800 ret
= "li\t%0,%1\t\t# %X1";
2801 else if (HOST_BITS_PER_WIDE_INT
< 64)
2802 /* We can't use 'X' for negative numbers, because then we won't
2803 get the right value for the upper 32 bits. */
2804 ret
= (INTVAL (op1
) < 0
2805 ? "dli\t%0,%1\t\t\t# %X1"
2806 : "dli\t%0,%X1\t\t# %1");
2808 /* We must use 'X', because otherwise LONG_MIN will print as
2809 a number that the assembler won't accept. */
2810 ret
= "dli\t%0,%X1\t\t# %1";
2812 else if (HOST_BITS_PER_WIDE_INT
< 64)
2814 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
2817 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2818 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2819 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2821 operands
[2] = GEN_INT (1);
2822 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2826 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2830 /* We use multiple shifts here, to avoid warnings about out
2831 of range shifts on 32 bit hosts. */
2832 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
2834 = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
2837 if (INTVAL (op1
) >= 0 && INTVAL (op1
) <= 0xffff)
2838 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2839 else if (INTVAL (op1
) < 0 && INTVAL (op1
) >= -0xffff)
2841 operands
[2] = GEN_INT (1);
2842 ret
= "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2846 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
2850 else if (code1
== MEM
)
2855 mips_count_memory_refs (op1
, 2);
2857 if (FP_REG_P (regno0
))
2860 else if (ALL_COP_REG_P (regno0
) && TARGET_64BIT
)
2862 static char retval
[] = "ldc_\t%0,%1";
2863 char cop
= COPNUM_AS_CHAR_FROM_REGNUM (regno0
);
2866 abort_with_insn (insn
,
2867 "loads from memory to COP0 are illegal");
2873 else if (TARGET_64BIT
)
2876 #ifdef TARGET_FP_CALL_32
2877 if (FP_CALL_GP_REG_P (regno0
))
2878 ret
= (double_memory_operand (op1
, GET_MODE (op1
))
2879 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2880 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2886 else if (double_memory_operand (op1
, GET_MODE (op1
)))
2887 ret
= (reg_mentioned_p (op0
, op1
)
2888 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2889 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2891 if (ret
!= 0 && MEM_VOLATILE_P (op1
))
2893 size_t i
= strlen (ret
);
2895 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
2898 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
2899 ret
= volatile_buffer
;
2903 else if (code1
== LABEL_REF
)
2906 mips_count_memory_refs (op1
, 2);
2908 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2909 /* We deliberately remove the 'a' from '%1', so that we don't
2910 have to add SIGN_EXTEND support to print_operand_address.
2911 print_operand will just call print_operand_address in this
2912 case, so there is no problem. */
2915 ret
= "dla\t%0,%a1";
2917 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
2921 && GET_CODE (XEXP (op1
, 0)) == REG
2922 && REGNO (XEXP (op1
, 0)) == GP_REG_FIRST
+ 28)
2924 /* This case arises on the mips16; see
2925 mips16_gp_pseudo_reg. */
2926 ret
= "move\t%0,%+";
2928 else if (TARGET_MIPS16
2929 && code1
== SYMBOL_REF
2930 && SYMBOL_REF_FLAG (op1
)
2931 && (XSTR (op1
, 0)[0] != '*'
2932 || strncmp (XSTR (op1
, 0) + 1,
2934 sizeof LOCAL_LABEL_PREFIX
- 1) != 0))
2936 /* This can occur when reloading the address of a GP
2937 relative symbol on the mips16. */
2938 ret
= "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2943 mips_count_memory_refs (op1
, 2);
2945 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
2946 /* We deliberately remove the 'a' from '%1', so that we don't
2947 have to add SIGN_EXTEND support to print_operand_address.
2948 print_operand will just call print_operand_address in this
2949 case, so there is no problem. */
2952 ret
= "dla\t%0,%a1";
2957 else if (code0
== MEM
)
2961 int regno1
= REGNO (op1
) + subreg_offset1
;
2963 if (FP_REG_P (regno1
))
2966 else if (ALL_COP_REG_P (regno1
) && TARGET_64BIT
)
2968 static char retval
[] = "sdc_\t%1,%0";
2970 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1
);
2973 else if (TARGET_64BIT
)
2976 #ifdef TARGET_FP_CALL_32
2977 if (FP_CALL_GP_REG_P (regno1
))
2978 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2984 else if (double_memory_operand (op0
, GET_MODE (op0
)))
2985 ret
= "sw\t%1,%0\n\tsw\t%D1,%D0";
2988 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
2989 || (code1
== CONST_DOUBLE
2990 && op1
== CONST0_RTX (GET_MODE (op1
))))
2992 || double_memory_operand (op0
, GET_MODE (op0
))))
2997 ret
= "sw\t%.,%0\n\tsw\t%.,%D0";
3001 mips_count_memory_refs (op0
, 2);
3003 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
3005 size_t i
= strlen (ret
);
3007 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
3010 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
3011 ret
= volatile_buffer
;
3017 abort_with_insn (insn
, "bad move");
3021 if (delay
!= DELAY_NONE
)
3022 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
3027 /* Provide the costs of an addressing mode that contains ADDR.
3028 If ADDR is not a valid address, its cost is irrelevant. */
3031 mips_address_cost (addr
)
3034 switch (GET_CODE (addr
))
3044 rtx offset
= const0_rtx
;
3045 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
3046 if (GET_CODE (addr
) == LABEL_REF
)
3049 if (GET_CODE (addr
) != SYMBOL_REF
)
3052 if (! SMALL_INT (offset
))
3056 /* ... fall through ... */
3059 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
3063 register rtx plus0
= XEXP (addr
, 0);
3064 register rtx plus1
= XEXP (addr
, 1);
3066 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
3067 plus0
= XEXP (addr
, 1), plus1
= XEXP (addr
, 0);
3069 if (GET_CODE (plus0
) != REG
)
3072 switch (GET_CODE (plus1
))
3075 return SMALL_INT (plus1
) ? 1 : 2;
3082 return mips_address_cost (plus1
) + 1;
3096 /* Return nonzero if X is an address which needs a temporary register when
3097 reloaded while generating PIC code. */
3100 pic_address_needs_scratch (x
)
3103 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3104 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3105 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3106 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3107 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3113 /* Make normal rtx_code into something we can index from an array */
3115 static enum internal_test
3116 map_test_to_internal_test (test_code
)
3117 enum rtx_code test_code
;
3119 enum internal_test test
= ITEST_MAX
;
3123 case EQ
: test
= ITEST_EQ
; break;
3124 case NE
: test
= ITEST_NE
; break;
3125 case GT
: test
= ITEST_GT
; break;
3126 case GE
: test
= ITEST_GE
; break;
3127 case LT
: test
= ITEST_LT
; break;
3128 case LE
: test
= ITEST_LE
; break;
3129 case GTU
: test
= ITEST_GTU
; break;
3130 case GEU
: test
= ITEST_GEU
; break;
3131 case LTU
: test
= ITEST_LTU
; break;
3132 case LEU
: test
= ITEST_LEU
; break;
3140 /* Generate the code to compare two integer values. The return value is:
3141 (reg:SI xx) The pseudo register the comparison is in
3142 0 No register, generate a simple branch.
3144 ??? This is called with result nonzero by the Scond patterns in
3145 mips.md. These patterns are called with a target in the mode of
3146 the Scond instruction pattern. Since this must be a constant, we
3147 must use SImode. This means that if RESULT is non-zero, it will
3148 always be an SImode register, even if TARGET_64BIT is true. We
3149 cope with this by calling convert_move rather than emit_move_insn.
3150 This will sometimes lead to an unnecessary extension of the result;
3162 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
3163 enum rtx_code test_code
; /* relational test (EQ, etc) */
3164 rtx result
; /* result to store comp. or 0 if branch */
3165 rtx cmp0
; /* first operand to compare */
3166 rtx cmp1
; /* second operand to compare */
3167 int *p_invert
; /* NULL or ptr to hold whether branch needs */
3168 /* to reverse its test */
3172 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
3173 int const_low
; /* low bound of constant we can accept */
3174 int const_high
; /* high bound of constant we can accept */
3175 int const_add
; /* constant to add (convert LE -> LT) */
3176 int reverse_regs
; /* reverse registers in test */
3177 int invert_const
; /* != 0 if invert value if cmp1 is constant */
3178 int invert_reg
; /* != 0 if invert value if cmp1 is register */
3179 int unsignedp
; /* != 0 for unsigned comparisons. */
3182 static const struct cmp_info info
[ (int)ITEST_MAX
] = {
3184 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
3185 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
3186 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
3187 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
3188 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
3189 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
3190 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
3191 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
3192 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
3193 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
3196 enum internal_test test
;
3197 enum machine_mode mode
;
3198 const struct cmp_info
*p_info
;
3205 test
= map_test_to_internal_test (test_code
);
3206 if (test
== ITEST_MAX
)
3209 p_info
= &info
[(int) test
];
3210 eqne_p
= (p_info
->test_code
== XOR
);
3212 mode
= GET_MODE (cmp0
);
3213 if (mode
== VOIDmode
)
3214 mode
= GET_MODE (cmp1
);
3216 /* Eliminate simple branches */
3217 branch_p
= (result
== 0);
3220 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
3222 /* Comparisons against zero are simple branches */
3223 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0
3224 && (! TARGET_MIPS16
|| eqne_p
))
3227 /* Test for beq/bne. */
3228 if (eqne_p
&& ! TARGET_MIPS16
)
3232 /* allocate a pseudo to calculate the value in. */
3233 result
= gen_reg_rtx (mode
);
3236 /* Make sure we can handle any constants given to us. */
3237 if (GET_CODE (cmp0
) == CONST_INT
)
3238 cmp0
= force_reg (mode
, cmp0
);
3240 if (GET_CODE (cmp1
) == CONST_INT
)
3242 HOST_WIDE_INT value
= INTVAL (cmp1
);
3244 if (value
< p_info
->const_low
3245 || value
> p_info
->const_high
3246 /* ??? Why? And why wasn't the similar code below modified too? */
3248 && HOST_BITS_PER_WIDE_INT
< 64
3249 && p_info
->const_add
!= 0
3250 && ((p_info
->unsignedp
3251 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
3252 > (unsigned HOST_WIDE_INT
) INTVAL (cmp1
))
3253 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
3254 != (p_info
->const_add
> 0))))
3255 cmp1
= force_reg (mode
, cmp1
);
3258 /* See if we need to invert the result. */
3259 invert
= (GET_CODE (cmp1
) == CONST_INT
3260 ? p_info
->invert_const
: p_info
->invert_reg
);
3262 if (p_invert
!= (int *)0)
3268 /* Comparison to constants, may involve adding 1 to change a LT into LE.
3269 Comparison between two registers, may involve switching operands. */
3270 if (GET_CODE (cmp1
) == CONST_INT
)
3272 if (p_info
->const_add
!= 0)
3274 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
3276 /* If modification of cmp1 caused overflow,
3277 we would get the wrong answer if we follow the usual path;
3278 thus, x > 0xffffffffU would turn into x > 0U. */
3279 if ((p_info
->unsignedp
3280 ? (unsigned HOST_WIDE_INT
) new >
3281 (unsigned HOST_WIDE_INT
) INTVAL (cmp1
)
3282 : new > INTVAL (cmp1
))
3283 != (p_info
->const_add
> 0))
3285 /* This test is always true, but if INVERT is true then
3286 the result of the test needs to be inverted so 0 should
3287 be returned instead. */
3288 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
3292 cmp1
= GEN_INT (new);
3296 else if (p_info
->reverse_regs
)
3303 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
3307 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
3308 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
3311 if (test
== ITEST_NE
)
3313 if (! TARGET_MIPS16
)
3315 convert_move (result
, gen_rtx (GTU
, mode
, reg
, const0_rtx
), 0);
3316 if (p_invert
!= NULL
)
3322 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3323 convert_move (reg2
, gen_rtx (LTU
, mode
, reg
, const1_rtx
), 0);
3328 else if (test
== ITEST_EQ
)
3330 reg2
= invert
? gen_reg_rtx (mode
) : result
;
3331 convert_move (reg2
, gen_rtx_LTU (mode
, reg
, const1_rtx
), 0);
3339 if (! TARGET_MIPS16
)
3343 /* The value is in $24. Copy it to another register, so
3344 that reload doesn't think it needs to store the $24 and
3345 the input to the XOR in the same location. */
3346 reg2
= gen_reg_rtx (mode
);
3347 emit_move_insn (reg2
, reg
);
3349 one
= force_reg (mode
, const1_rtx
);
3351 convert_move (result
, gen_rtx (XOR
, mode
, reg
, one
), 0);
3357 /* Emit the common code for doing conditional branches.
3358 operand[0] is the label to jump to.
3359 The comparison operands are saved away by cmp{si,di,sf,df}. */
3362 gen_conditional_branch (operands
, test_code
)
3364 enum rtx_code test_code
;
3366 enum cmp_type type
= branch_type
;
3367 rtx cmp0
= branch_cmp
[0];
3368 rtx cmp1
= branch_cmp
[1];
3369 enum machine_mode mode
;
3378 mode
= type
== CMP_SI
? SImode
: DImode
;
3380 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
3388 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
3389 /* We don't want to build a comparison against a non-zero
3391 cmp1
= force_reg (mode
, cmp1
);
3398 reg
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
3400 reg
= gen_reg_rtx (CCmode
);
3402 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3403 0 in the instruction built below. The MIPS FPU handles
3404 inequality testing by testing for equality and looking for a
3406 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
3407 gen_rtx (test_code
== NE
? EQ
: test_code
,
3408 CCmode
, cmp0
, cmp1
)));
3410 test_code
= test_code
== NE
? EQ
: NE
;
3418 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
3421 /* Generate the branch. */
3423 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
3432 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
3433 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3434 gen_rtx (test_code
, mode
,
3439 /* Emit the common code for conditional moves. OPERANDS is the array
3440 of operands passed to the conditional move defined_expand. */
3443 gen_conditional_move (operands
)
3446 rtx op0
= branch_cmp
[0];
3447 rtx op1
= branch_cmp
[1];
3448 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3449 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
3450 enum rtx_code move_code
= NE
;
3451 enum machine_mode op_mode
= GET_MODE (operands
[0]);
3452 enum machine_mode cmp_mode
;
3455 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3474 op0
= force_reg (mode
, branch_cmp
[1]);
3475 op1
= branch_cmp
[0];
3479 op0
= force_reg (mode
, branch_cmp
[1]);
3480 op1
= branch_cmp
[0];
3491 op0
= force_reg (mode
, branch_cmp
[1]);
3492 op1
= branch_cmp
[0];
3496 op0
= force_reg (mode
, branch_cmp
[1]);
3497 op1
= branch_cmp
[0];
3504 else if (cmp_code
== NE
)
3505 cmp_code
= EQ
, move_code
= EQ
;
3507 if (mode
== SImode
|| mode
== DImode
)
3509 else if (mode
== SFmode
|| mode
== DFmode
)
3514 cmp_reg
= gen_reg_rtx (cmp_mode
);
3515 emit_insn (gen_rtx_SET (cmp_mode
, cmp_reg
,
3516 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
3518 emit_insn (gen_rtx_SET (op_mode
, operands
[0],
3519 gen_rtx_IF_THEN_ELSE (op_mode
,
3520 gen_rtx (move_code
, VOIDmode
,
3522 CONST0_RTX (SImode
)),
3523 operands
[2], operands
[3])));
3526 /* Emit the common code for conditional moves. OPERANDS is the array
3527 of operands passed to the conditional move defined_expand. */
3530 mips_gen_conditional_trap (operands
)
3534 enum rtx_code cmp_code
= GET_CODE (operands
[0]);
3535 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
3537 /* MIPS conditional trap machine instructions don't have GT or LE
3538 flavors, so we must invert the comparison and convert to LT and
3539 GE, respectively. */
3542 case GT
: cmp_code
= LT
; break;
3543 case LE
: cmp_code
= GE
; break;
3544 case GTU
: cmp_code
= LTU
; break;
3545 case LEU
: cmp_code
= GEU
; break;
3548 if (cmp_code
== GET_CODE (operands
[0]))
3550 op0
= force_reg (mode
, branch_cmp
[0]);
3551 op1
= branch_cmp
[1];
3555 op0
= force_reg (mode
, branch_cmp
[1]);
3556 op1
= branch_cmp
[0];
3558 if (GET_CODE (op1
) == CONST_INT
&& ! SMALL_INT (op1
))
3559 op1
= force_reg (mode
, op1
);
3561 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
3562 gen_rtx (cmp_code
, GET_MODE (operands
[0]), op0
, op1
),
3566 /* Emit code to change the current function's return address to
3567 ADDRESS. SCRATCH is available as a scratch register, if needed.
3568 ADDRESS and SCRATCH are both word-mode GPRs. */
3571 mips_set_return_address (address
, scratch
)
3572 rtx address
, scratch
;
3574 HOST_WIDE_INT gp_offset
;
3576 compute_frame_size (get_frame_size ());
3577 if (((cfun
->machine
->frame
.mask
>> 31) & 1) == 0)
3579 gp_offset
= cfun
->machine
->frame
.gp_sp_offset
;
3581 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3582 if (gp_offset
< 32768)
3583 scratch
= plus_constant (stack_pointer_rtx
, gp_offset
);
3586 emit_move_insn (scratch
, GEN_INT (gp_offset
));
3587 if (Pmode
== DImode
)
3588 emit_insn (gen_adddi3 (scratch
, scratch
, stack_pointer_rtx
));
3590 emit_insn (gen_addsi3 (scratch
, scratch
, stack_pointer_rtx
));
3593 emit_move_insn (gen_rtx_MEM (GET_MODE (address
), scratch
), address
);
3596 /* Write a loop to move a constant number of bytes.
3597 Generate load/stores as follows:
3603 temp<last> = src[MAX_MOVE_REGS-1];
3607 dest[MAX_MOVE_REGS-1] = temp<last>;
3608 src += MAX_MOVE_REGS;
3609 dest += MAX_MOVE_REGS;
3610 } while (src != final);
3612 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3613 registers are needed.
3615 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3616 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3617 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3619 #define MAX_MOVE_REGS 4
3620 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3623 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
3624 rtx dest_reg
; /* register holding destination address */
3625 rtx src_reg
; /* register holding source address */
3626 unsigned int bytes
; /* # bytes to move */
3627 int align
; /* alignment */
3628 rtx orig_dest
; /* original dest */
3629 rtx orig_src
; /* original source for making a reg note */
3631 rtx dest_mem
= replace_equiv_address (orig_dest
, dest_reg
);
3632 rtx src_mem
= replace_equiv_address (orig_src
, src_reg
);
3633 rtx align_rtx
= GEN_INT (align
);
3639 if (bytes
< (unsigned)2 * MAX_MOVE_BYTES
)
3642 leftover
= bytes
% MAX_MOVE_BYTES
;
3645 label
= gen_label_rtx ();
3646 final_src
= gen_reg_rtx (Pmode
);
3647 bytes_rtx
= GEN_INT (bytes
);
3651 if (Pmode
== DImode
)
3653 emit_insn (gen_movdi (final_src
, bytes_rtx
));
3654 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
3658 emit_insn (gen_movsi (final_src
, bytes_rtx
));
3659 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
3664 if (Pmode
== DImode
)
3665 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
3667 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
3672 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
3673 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
3675 if (Pmode
== DImode
)
3677 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
3678 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
3679 emit_insn (gen_cmpdi (src_reg
, final_src
));
3683 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
3684 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
3685 emit_insn (gen_cmpsi (src_reg
, final_src
));
3688 emit_jump_insn (gen_bne (label
));
3691 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, GEN_INT (leftover
),
3695 /* Use a library function to move some bytes. */
3698 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
3703 /* We want to pass the size as Pmode, which will normally be SImode
3704 but will be DImode if we are using 64 bit longs and pointers. */
3705 if (GET_MODE (bytes_rtx
) != VOIDmode
3706 && GET_MODE (bytes_rtx
) != (unsigned) Pmode
)
3707 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
3709 #ifdef TARGET_MEM_FUNCTIONS
3710 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "memcpy"), 0,
3711 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
3712 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
3713 TREE_UNSIGNED (sizetype
)),
3714 TYPE_MODE (sizetype
));
3716 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "bcopy"), 0,
3717 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
3718 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
3719 TREE_UNSIGNED (integer_type_node
)),
3720 TYPE_MODE (integer_type_node
));
3724 /* Expand string/block move operations.
3726 operands[0] is the pointer to the destination.
3727 operands[1] is the pointer to the source.
3728 operands[2] is the number of bytes to move.
3729 operands[3] is the alignment. */
3732 expand_block_move (operands
)
3735 rtx bytes_rtx
= operands
[2];
3736 rtx align_rtx
= operands
[3];
3737 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
3738 unsigned HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
3739 unsigned int align
= INTVAL (align_rtx
);
3740 rtx orig_src
= operands
[1];
3741 rtx orig_dest
= operands
[0];
3745 if (constp
&& bytes
== 0)
3748 if (align
> (unsigned) UNITS_PER_WORD
)
3749 align
= UNITS_PER_WORD
;
3751 /* Move the address into scratch registers. */
3752 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
3753 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
3756 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3758 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
3759 && align
== (unsigned) UNITS_PER_WORD
)
3760 move_by_pieces (orig_dest
, orig_src
, bytes
, align
* BITS_PER_WORD
);
3762 else if (constp
&& bytes
<= (unsigned)2 * MAX_MOVE_BYTES
)
3763 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
3765 replace_equiv_address (orig_src
,
3767 bytes_rtx
, align_rtx
));
3769 else if (constp
&& align
>= (unsigned) UNITS_PER_WORD
&& optimize
)
3770 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
3772 else if (constp
&& optimize
)
3774 /* If the alignment is not word aligned, generate a test at
3775 runtime, to see whether things wound up aligned, and we
3776 can use the faster lw/sw instead ulw/usw. */
3778 rtx temp
= gen_reg_rtx (Pmode
);
3779 rtx aligned_label
= gen_label_rtx ();
3780 rtx join_label
= gen_label_rtx ();
3781 int leftover
= bytes
% MAX_MOVE_BYTES
;
3785 if (Pmode
== DImode
)
3787 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
3788 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3789 emit_insn (gen_cmpdi (temp
, const0_rtx
));
3793 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
3794 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
3795 emit_insn (gen_cmpsi (temp
, const0_rtx
));
3798 emit_jump_insn (gen_beq (aligned_label
));
3800 /* Unaligned loop. */
3801 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
3802 emit_jump_insn (gen_jump (join_label
));
3806 emit_label (aligned_label
);
3807 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
3809 emit_label (join_label
);
3811 /* Bytes at the end of the loop. */
3813 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest
,
3815 replace_equiv_address (orig_src
,
3822 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
3825 /* Emit load/stores for a small constant block_move.
3827 operands[0] is the memory address of the destination.
3828 operands[1] is the memory address of the source.
3829 operands[2] is the number of bytes to move.
3830 operands[3] is the alignment.
3831 operands[4] is a temp register.
3832 operands[5] is a temp register.
3834 operands[3+num_regs] is the last temp register.
3836 The block move type can be one of the following:
3837 BLOCK_MOVE_NORMAL Do all of the block move.
3838 BLOCK_MOVE_NOT_LAST Do all but the last store.
3839 BLOCK_MOVE_LAST Do just the last store. */
3842 output_block_move (insn
, operands
, num_regs
, move_type
)
3846 enum block_move_type move_type
;
3848 rtx dest_reg
= XEXP (operands
[0], 0);
3849 rtx src_reg
= XEXP (operands
[1], 0);
3850 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
3851 int align
= INTVAL (operands
[3]);
3854 int use_lwl_lwr
= 0;
3855 int last_operand
= num_regs
+ 4;
3861 const char *load
; /* load insn without nop */
3862 const char *load_nop
; /* load insn with trailing nop */
3863 const char *store
; /* store insn */
3864 const char *final
; /* if last_store used: NULL or swr */
3865 const char *last_store
; /* last store instruction */
3866 int offset
; /* current offset */
3867 enum machine_mode mode
; /* mode to use on (MEM) */
3870 /* ??? Detect a bug in GCC, where it can give us a register
3871 the same as one of the addressing registers and reduce
3872 the number of registers available. */
3873 for (i
= 4; i
< last_operand
&& safe_regs
< (int) ARRAY_SIZE (xoperands
); i
++)
3874 if (! reg_mentioned_p (operands
[i
], operands
[0])
3875 && ! reg_mentioned_p (operands
[i
], operands
[1]))
3876 xoperands
[safe_regs
++] = operands
[i
];
3878 if (safe_regs
< last_operand
)
3880 xoperands
[0] = operands
[0];
3881 xoperands
[1] = operands
[1];
3882 xoperands
[2] = operands
[2];
3883 xoperands
[3] = operands
[3];
3884 return output_block_move (insn
, xoperands
, safe_regs
- 4, move_type
);
3887 /* If we are given global or static addresses, and we would be
3888 emitting a few instructions, try to save time by using a
3889 temporary register for the pointer. */
3890 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3891 an ldl/ldr instruction pair. We play it safe, and always move
3892 constant addresses into registers when generating N32/N64 code, just
3893 in case we might emit an unaligned load instruction. */
3894 if (num_regs
> 2 && (bytes
> 2 * align
|| move_type
!= BLOCK_MOVE_NORMAL
3895 || mips_abi
== ABI_MEABI
3896 || mips_abi
== ABI_N32
3897 || mips_abi
== ABI_64
))
3899 if (CONSTANT_P (src_reg
))
3902 mips_count_memory_refs (operands
[1], 1);
3904 src_reg
= operands
[3 + num_regs
--];
3905 if (move_type
!= BLOCK_MOVE_LAST
)
3907 xoperands
[1] = operands
[1];
3908 xoperands
[0] = src_reg
;
3909 if (Pmode
== DImode
)
3910 output_asm_insn ("dla\t%0,%1", xoperands
);
3912 output_asm_insn ("la\t%0,%1", xoperands
);
3916 if (CONSTANT_P (dest_reg
))
3919 mips_count_memory_refs (operands
[0], 1);
3921 dest_reg
= operands
[3 + num_regs
--];
3922 if (move_type
!= BLOCK_MOVE_LAST
)
3924 xoperands
[1] = operands
[0];
3925 xoperands
[0] = dest_reg
;
3926 if (Pmode
== DImode
)
3927 output_asm_insn ("dla\t%0,%1", xoperands
);
3929 output_asm_insn ("la\t%0,%1", xoperands
);
3934 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3935 are not offsettable, however, offsettable_address_p says they are
3936 offsettable. I think this is a bug in offsettable_address_p.
3937 For expediency, we fix this by just loading the address into a register
3938 if we happen to get one. */
3940 if (GET_CODE (src_reg
) == LO_SUM
)
3942 src_reg
= operands
[3 + num_regs
--];
3943 if (move_type
!= BLOCK_MOVE_LAST
)
3945 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
3946 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3947 xoperands
[0] = src_reg
;
3948 if (Pmode
== DImode
)
3949 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3951 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3955 if (GET_CODE (dest_reg
) == LO_SUM
)
3957 dest_reg
= operands
[3 + num_regs
--];
3958 if (move_type
!= BLOCK_MOVE_LAST
)
3960 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
3961 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
3962 xoperands
[0] = dest_reg
;
3963 if (Pmode
== DImode
)
3964 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
3966 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
3970 if (num_regs
> (int) ARRAY_SIZE (load_store
))
3971 num_regs
= ARRAY_SIZE (load_store
);
3973 else if (num_regs
< 1)
3974 abort_with_insn (insn
,
3975 "cannot do block move, not enough scratch registers");
3979 load_store
[num
].offset
= offset
;
3981 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
3983 load_store
[num
].load
= "ld\t%0,%1";
3984 load_store
[num
].load_nop
= "ld\t%0,%1%#";
3985 load_store
[num
].store
= "sd\t%0,%1";
3986 load_store
[num
].last_store
= "sd\t%0,%1";
3987 load_store
[num
].final
= 0;
3988 load_store
[num
].mode
= DImode
;
3993 /* ??? Fails because of a MIPS assembler bug? */
3994 else if (TARGET_64BIT
&& bytes
>= 8
3998 if (BYTES_BIG_ENDIAN
)
4000 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
4001 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
4002 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
4003 load_store
[num
].last_store
= "sdr\t%0,%2";
4004 load_store
[num
].final
= "sdl\t%0,%1";
4008 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
4009 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
4010 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
4011 load_store
[num
].last_store
= "sdr\t%0,%1";
4012 load_store
[num
].final
= "sdl\t%0,%2";
4015 load_store
[num
].mode
= DImode
;
4021 else if (bytes
>= 4 && align
>= 4)
4023 load_store
[num
].load
= "lw\t%0,%1";
4024 load_store
[num
].load_nop
= "lw\t%0,%1%#";
4025 load_store
[num
].store
= "sw\t%0,%1";
4026 load_store
[num
].last_store
= "sw\t%0,%1";
4027 load_store
[num
].final
= 0;
4028 load_store
[num
].mode
= SImode
;
4037 if (BYTES_BIG_ENDIAN
)
4039 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
4040 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
4041 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
4042 load_store
[num
].last_store
= "swr\t%0,%2";
4043 load_store
[num
].final
= "swl\t%0,%1";
4047 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
4048 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
4049 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
4050 load_store
[num
].last_store
= "swr\t%0,%1";
4051 load_store
[num
].final
= "swl\t%0,%2";
4054 load_store
[num
].mode
= SImode
;
4060 else if (bytes
>= 2 && align
>= 2)
4062 load_store
[num
].load
= "lh\t%0,%1";
4063 load_store
[num
].load_nop
= "lh\t%0,%1%#";
4064 load_store
[num
].store
= "sh\t%0,%1";
4065 load_store
[num
].last_store
= "sh\t%0,%1";
4066 load_store
[num
].final
= 0;
4067 load_store
[num
].mode
= HImode
;
4073 load_store
[num
].load
= "lb\t%0,%1";
4074 load_store
[num
].load_nop
= "lb\t%0,%1%#";
4075 load_store
[num
].store
= "sb\t%0,%1";
4076 load_store
[num
].last_store
= "sb\t%0,%1";
4077 load_store
[num
].final
= 0;
4078 load_store
[num
].mode
= QImode
;
4083 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
4085 dslots_load_total
++;
4086 dslots_load_filled
++;
4088 if (CONSTANT_P (src_reg
))
4089 mips_count_memory_refs (src_reg
, 1);
4091 if (CONSTANT_P (dest_reg
))
4092 mips_count_memory_refs (dest_reg
, 1);
4095 /* Emit load/stores now if we have run out of registers or are
4096 at the end of the move. */
4098 if (++num
== num_regs
|| bytes
== 0)
4100 /* If only load/store, we need a NOP after the load. */
4103 load_store
[0].load
= load_store
[0].load_nop
;
4104 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
4105 dslots_load_filled
--;
4108 if (move_type
!= BLOCK_MOVE_LAST
)
4110 for (i
= 0; i
< num
; i
++)
4114 if (!operands
[i
+ 4])
4117 if (GET_MODE (operands
[i
+ 4]) != load_store
[i
].mode
)
4118 operands
[i
+ 4] = gen_rtx_REG (load_store
[i
].mode
,
4119 REGNO (operands
[i
+ 4]));
4121 offset
= load_store
[i
].offset
;
4122 xoperands
[0] = operands
[i
+ 4];
4123 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
4124 plus_constant (src_reg
, offset
));
4129 = GET_MODE_SIZE (load_store
[i
].mode
) - 1;
4131 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
4132 plus_constant (src_reg
,
4137 output_asm_insn (load_store
[i
].load
, xoperands
);
4141 for (i
= 0; i
< num
; i
++)
4143 int last_p
= (i
== num
-1 && bytes
== 0);
4144 int offset
= load_store
[i
].offset
;
4146 xoperands
[0] = operands
[i
+ 4];
4147 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
4148 plus_constant (dest_reg
, offset
));
4153 int extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
4154 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
4155 plus_constant (dest_reg
,
4160 if (move_type
== BLOCK_MOVE_NORMAL
)
4161 output_asm_insn (load_store
[i
].store
, xoperands
);
4163 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
4166 output_asm_insn (load_store
[i
].store
, xoperands
);
4168 else if (load_store
[i
].final
!= 0)
4169 output_asm_insn (load_store
[i
].final
, xoperands
);
4173 output_asm_insn (load_store
[i
].last_store
, xoperands
);
4176 num
= 0; /* reset load_store */
4184 /* Argument support functions. */
4186 /* Initialize CUMULATIVE_ARGS for a function. */
4189 init_cumulative_args (cum
, fntype
, libname
)
4190 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
4191 tree fntype
; /* tree ptr for function decl */
4192 rtx libname ATTRIBUTE_UNUSED
; /* SYMBOL_REF of library name or 0 */
4194 static CUMULATIVE_ARGS zero_cum
;
4195 tree param
, next_param
;
4197 if (TARGET_DEBUG_E_MODE
)
4200 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
4203 fputc ('\n', stderr
);
4207 tree ret_type
= TREE_TYPE (fntype
);
4208 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
4209 tree_code_name
[(int)TREE_CODE (fntype
)],
4210 tree_code_name
[(int)TREE_CODE (ret_type
)]);
4215 cum
->prototype
= (fntype
&& TYPE_ARG_TYPES (fntype
));
4217 /* Determine if this function has variable arguments. This is
4218 indicated by the last argument being 'void_type_mode' if there
4219 are no variable arguments. The standard MIPS calling sequence
4220 passes all arguments in the general purpose registers in this case. */
4222 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
4223 param
!= 0; param
= next_param
)
4225 next_param
= TREE_CHAIN (param
);
4226 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
4227 cum
->gp_reg_found
= 1;
4232 mips_arg_info (cum
, mode
, type
, named
, info
)
4233 const CUMULATIVE_ARGS
*cum
;
4234 enum machine_mode mode
;
4237 struct mips_arg_info
*info
;
4240 unsigned int num_words
, max_regs
;
4242 info
->struct_p
= (type
!= 0
4243 && (TREE_CODE (type
) == RECORD_TYPE
4244 || TREE_CODE (type
) == UNION_TYPE
4245 || TREE_CODE (type
) == QUAL_UNION_TYPE
));
4247 /* Decide whether this argument should go in a floating-point register,
4248 assuming one is free. Later code checks for availablity. */
4250 info
->fpr_p
= false;
4251 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
4252 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
)
4258 info
->fpr_p
= (!cum
->gp_reg_found
&& cum
->arg_number
< 2);
4266 /* The MIPS eabi says only structures containing doubles get
4267 passed in a fp register, so force a structure containing
4268 a float to be passed in the integer registers. */
4269 info
->fpr_p
= (named
&& !(mode
== SFmode
&& info
->struct_p
));
4273 info
->fpr_p
= named
;
4278 /* Now decide whether the argument must go in an even-numbered register. */
4283 /* Under the O64 ABI, the second float argument goes in $f13 if it
4284 is a double, but $f14 if it is a single. Otherwise, on a
4285 32-bit double-float machine, each FP argument must start in a
4286 new register pair. */
4287 even_reg_p
= ((mips_abi
== ABI_O64
&& mode
== SFmode
) || FP_INC
> 1);
4289 else if (!TARGET_64BIT
)
4291 if (GET_MODE_CLASS (mode
) == MODE_INT
4292 || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4293 even_reg_p
= (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
);
4295 else if (type
!= NULL_TREE
&& TYPE_ALIGN (type
) > BITS_PER_WORD
)
4299 /* Set REG_OFFSET to the register count we're interested in.
4300 The EABI allocates the floating-point registers separately,
4301 but the other ABIs allocate them like integer registers. */
4302 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4307 info
->reg_offset
+= info
->reg_offset
& 1;
4309 /* The alignment applied to registers is also applied to stack arguments. */
4310 info
->stack_offset
= cum
->stack_words
;
4312 info
->stack_offset
+= info
->stack_offset
& 1;
4314 if (mode
== BLKmode
)
4315 info
->num_bytes
= int_size_in_bytes (type
);
4317 info
->num_bytes
= GET_MODE_SIZE (mode
);
4319 num_words
= (info
->num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4320 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4322 /* Partition the argument between registers and stack. */
4323 info
->reg_words
= MIN (num_words
, max_regs
);
4324 info
->stack_words
= num_words
- info
->reg_words
;
4328 /* Advance the argument to the next argument position. */
4331 function_arg_advance (cum
, mode
, type
, named
)
4332 CUMULATIVE_ARGS
*cum
; /* current arg information */
4333 enum machine_mode mode
; /* current arg mode */
4334 tree type
; /* type of the argument or 0 if lib support */
4335 int named
; /* whether or not the argument was named */
4337 struct mips_arg_info info
;
4339 mips_arg_info (cum
, mode
, type
, named
, &info
);
4341 /* The following is a hack in order to pass 1 byte structures
4342 the same way that the MIPS compiler does (namely by passing
4343 the structure in the high byte or half word of the register).
4344 This also makes varargs work. If we have such a structure,
4345 we save the adjustment RTL, and the call define expands will
4346 emit them. For the VOIDmode argument (argument after the
4347 last real argument), pass back a parallel vector holding each
4348 of the adjustments. */
4350 /* ??? This scheme requires everything smaller than the word size to
4351 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4352 that would mean every int needs to be shifted left, which is very
4353 inefficient. Let's not carry this compatibility to the 64 bit
4354 calling convention for now. */
4357 && info
.reg_words
== 1
4358 && info
.num_bytes
< UNITS_PER_WORD
4360 && mips_abi
!= ABI_EABI
4361 && mips_abi
!= ABI_MEABI
)
4363 rtx amount
= GEN_INT (BITS_PER_WORD
- info
.num_bytes
* BITS_PER_UNIT
);
4364 rtx reg
= gen_rtx_REG (word_mode
, GP_ARG_FIRST
+ info
.reg_offset
);
4367 cum
->adjust
[cum
->num_adjusts
++] = PATTERN (gen_ashldi3 (reg
, reg
, amount
));
4369 cum
->adjust
[cum
->num_adjusts
++] = PATTERN (gen_ashlsi3 (reg
, reg
, amount
));
4373 cum
->gp_reg_found
= true;
4375 /* See the comment above the cumulative args structure in mips.h
4376 for an explanation of what this code does. It assumes the O32
4377 ABI, which passes at most 2 arguments in float registers. */
4378 if (cum
->arg_number
< 2 && info
.fpr_p
)
4379 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << ((cum
->arg_number
- 1) * 2);
4381 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4382 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4383 else if (info
.reg_words
> 0)
4384 cum
->num_fprs
+= FP_INC
;
4386 if (info
.stack_words
> 0)
4387 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4392 /* Return an RTL expression containing the register for the given mode,
4393 or 0 if the argument is to be passed on the stack. */
4396 function_arg (cum
, mode
, type
, named
)
4397 const CUMULATIVE_ARGS
*cum
; /* current arg information */
4398 enum machine_mode mode
; /* current arg mode */
4399 tree type
; /* type of the argument or 0 if lib support */
4400 int named
; /* != 0 for normal args, == 0 for ... args */
4402 struct mips_arg_info info
;
4404 /* We will be called with a mode of VOIDmode after the last argument
4405 has been seen. Whatever we return will be passed to the call
4406 insn. If we need any shifts for small structures, return them in
4407 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4408 mode. Otherwise, if we need a mips16 fp_code, return a REG
4409 with the code stored as the mode. */
4410 if (mode
== VOIDmode
)
4412 if (cum
->num_adjusts
> 0)
4413 return gen_rtx_PARALLEL ((enum machine_mode
) cum
->fp_code
,
4414 gen_rtvec_v (cum
->num_adjusts
,
4415 (rtx
*) cum
->adjust
));
4417 else if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4418 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4424 mips_arg_info (cum
, mode
, type
, named
, &info
);
4426 /* Return straight away if the whole argument is passed on the stack. */
4427 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4431 && TREE_CODE (type
) == RECORD_TYPE
4432 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
)
4433 && TYPE_SIZE_UNIT (type
)
4434 && host_integerp (TYPE_SIZE_UNIT (type
), 1)
4438 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4439 structure contains a double in its entirety, then that 64 bit
4440 chunk is passed in a floating point register. */
4443 /* First check to see if there is any such field. */
4444 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4445 if (TREE_CODE (field
) == FIELD_DECL
4446 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4447 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4448 && host_integerp (bit_position (field
), 0)
4449 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4454 /* Now handle the special case by returning a PARALLEL
4455 indicating where each 64 bit chunk goes. INFO.REG_WORDS
4456 chunks are passed in registers. */
4458 HOST_WIDE_INT bitpos
;
4461 /* assign_parms checks the mode of ENTRY_PARM, so we must
4462 use the actual mode here. */
4463 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4466 field
= TYPE_FIELDS (type
);
4467 for (i
= 0; i
< info
.reg_words
; i
++)
4471 for (; field
; field
= TREE_CHAIN (field
))
4472 if (TREE_CODE (field
) == FIELD_DECL
4473 && int_bit_position (field
) >= bitpos
)
4477 && int_bit_position (field
) == bitpos
4478 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4479 && !TARGET_SOFT_FLOAT
4480 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4481 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4483 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4486 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4487 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4489 bitpos
+= BITS_PER_WORD
;
4495 if (mips_abi
== ABI_MEABI
&& info
.fpr_p
&& !cum
->prototype
)
4497 /* To make K&R varargs work we need to pass floating
4498 point arguments in both integer and FP registers. */
4499 return gen_rtx_PARALLEL
4502 gen_rtx_EXPR_LIST (VOIDmode
,
4507 gen_rtx_EXPR_LIST (VOIDmode
,
4515 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ info
.reg_offset
);
4517 return gen_rtx_REG (mode
, GP_ARG_FIRST
+ info
.reg_offset
);
4521 function_arg_partial_nregs (cum
, mode
, type
, named
)
4522 const CUMULATIVE_ARGS
*cum
; /* current arg information */
4523 enum machine_mode mode
; /* current arg mode */
4524 tree type
; /* type of the argument or 0 if lib support */
4525 int named
; /* != 0 for normal args, == 0 for ... args */
4527 struct mips_arg_info info
;
4529 mips_arg_info (cum
, mode
, type
, named
, &info
);
4530 return info
.stack_words
> 0 ? info
.reg_words
: 0;
4534 mips_setup_incoming_varargs (cum
, mode
, type
, no_rtl
)
4535 const CUMULATIVE_ARGS
*cum
;
4536 enum machine_mode mode
;
4540 CUMULATIVE_ARGS local_cum
;
4541 int gp_saved
, fp_saved
;
4543 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
4546 /* The caller has advanced CUM up to, but not beyond, the last named
4547 argument. Advance a local copy of CUM past the last "real" named
4548 argument, to find out how many registers are left over. */
4551 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, 1);
4553 /* Found out how many registers we need to save. */
4554 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
4555 fp_saved
= (EABI_FLOAT_VARARGS_P
4556 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
4565 ptr
= virtual_incoming_args_rtx
;
4566 if (mips_abi
== ABI_EABI
)
4567 ptr
= plus_constant (ptr
, -gp_saved
* UNITS_PER_WORD
);
4568 mem
= gen_rtx_MEM (BLKmode
, ptr
);
4570 /* va_arg is an array access in this case, which causes
4571 it to get MEM_IN_STRUCT_P set. We must set it here
4572 so that the insn scheduler won't assume that these
4573 stores can't possibly overlap with the va_arg loads. */
4574 if (mips_abi
!= ABI_EABI
&& BYTES_BIG_ENDIAN
)
4575 MEM_SET_IN_STRUCT_P (mem
, 1);
4577 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
, mem
,
4578 gp_saved
, gp_saved
* UNITS_PER_WORD
);
4582 /* We can't use move_block_from_reg, because it will use
4584 enum machine_mode mode
;
4587 /* Set OFF to the offset from virtual_incoming_args_rtx of
4588 the first float register. The FP save area lies below
4589 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4590 off
= -gp_saved
* UNITS_PER_WORD
;
4591 off
&= ~(UNITS_PER_FPVALUE
- 1);
4592 off
-= fp_saved
* UNITS_PER_FPREG
;
4594 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4596 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
; i
+= FP_INC
)
4598 rtx ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
4599 emit_move_insn (gen_rtx_MEM (mode
, ptr
),
4600 gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
4601 off
+= UNITS_PER_FPVALUE
;
4605 return (gp_saved
* UNITS_PER_WORD
) + (fp_saved
* UNITS_PER_FPREG
);
4608 /* Create the va_list data type.
4609 We keep 3 pointers, and two offsets.
4610 Two pointers are to the overflow area, which starts at the CFA.
4611 One of these is constant, for addressing into the GPR save area below it.
4612 The other is advanced up the stack through the overflow region.
4613 The third pointer is to the GPR save area. Since the FPR save area
4614 is just below it, we can address FPR slots off this pointer.
4615 We also keep two one-byte offsets, which are to be subtracted from the
4616 constant pointers to yield addresses in the GPR and FPR save areas.
4617 These are downcounted as float or non-float arguments are used,
4618 and when they get to zero, the argument must be obtained from the
4620 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4621 pointer is enough. It's started at the GPR save area, and is
4623 Note that the GPR save area is not constant size, due to optimization
4624 in the prologue. Hence, we can't use a design with two pointers
4625 and two offsets, although we could have designed this with two pointers
4626 and three offsets. */
4630 mips_build_va_list ()
4632 if (EABI_FLOAT_VARARGS_P
)
4634 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, record
;
4636 record
= make_node (RECORD_TYPE
);
4638 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4640 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4642 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4644 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4645 unsigned_char_type_node
);
4646 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4647 unsigned_char_type_node
);
4650 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4651 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4652 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4653 DECL_FIELD_CONTEXT (f_goff
) = record
;
4654 DECL_FIELD_CONTEXT (f_foff
) = record
;
4656 TYPE_FIELDS (record
) = f_ovfl
;
4657 TREE_CHAIN (f_ovfl
) = f_gtop
;
4658 TREE_CHAIN (f_gtop
) = f_ftop
;
4659 TREE_CHAIN (f_ftop
) = f_goff
;
4660 TREE_CHAIN (f_goff
) = f_foff
;
4662 layout_type (record
);
4666 return ptr_type_node
;
4669 /* Implement va_start. stdarg_p is always 1. */
4672 mips_va_start (valist
, nextarg
)
4676 const CUMULATIVE_ARGS
*cum
= ¤t_function_args_info
;
4678 if (mips_abi
== ABI_EABI
)
4680 int gpr_save_area_size
;
4683 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
4685 if (EABI_FLOAT_VARARGS_P
)
4687 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4688 tree ovfl
, gtop
, ftop
, goff
, foff
;
4691 int fpr_save_area_size
;
4693 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4694 f_gtop
= TREE_CHAIN (f_ovfl
);
4695 f_ftop
= TREE_CHAIN (f_gtop
);
4696 f_goff
= TREE_CHAIN (f_ftop
);
4697 f_foff
= TREE_CHAIN (f_goff
);
4699 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
4700 gtop
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
4701 ftop
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
4702 goff
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
4703 foff
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
4705 /* Emit code to initialize OVFL, which points to the next varargs
4706 stack argument. CUM->STACK_WORDS gives the number of stack
4707 words used by named arguments. */
4708 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4709 if (cum
->stack_words
> 0)
4710 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4711 build_int_2 (cum
->stack_words
* UNITS_PER_WORD
, 0));
4712 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4713 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4715 /* Emit code to initialize GTOP, the top of the GPR save area. */
4716 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4717 t
= build (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
4718 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4720 /* Emit code to initialize FTOP, the top of the FPR save area.
4721 This address is gpr_save_area_bytes below GTOP, rounded
4722 down to the next fp-aligned boundary. */
4723 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4724 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
4725 fpr_offset
&= ~(UNITS_PER_FPVALUE
- 1);
4727 t
= build (PLUS_EXPR
, TREE_TYPE (ftop
), t
,
4728 build_int_2 (-fpr_offset
, -1));
4729 t
= build (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
4730 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4732 /* Emit code to initialize GOFF, the offset from GTOP of the
4733 next GPR argument. */
4734 t
= build (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
4735 build_int_2 (gpr_save_area_size
, 0));
4736 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4738 /* Likewise emit code to initialize FOFF, the offset from FTOP
4739 of the next FPR argument. */
4741 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
4742 t
= build (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
4743 build_int_2 (fpr_save_area_size
, 0));
4744 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4748 /* Everything is in the GPR save area, or in the overflow
4749 area which is contiguous with it. */
4750 nextarg
= plus_constant (nextarg
, -gpr_save_area_size
);
4751 std_expand_builtin_va_start (valist
, nextarg
);
4755 std_expand_builtin_va_start (valist
, nextarg
);
4758 /* Implement va_arg. */
4761 mips_va_arg (valist
, type
)
4764 HOST_WIDE_INT size
, rsize
;
4768 size
= int_size_in_bytes (type
);
4769 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4771 if (mips_abi
== ABI_EABI
)
4777 = function_arg_pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4781 size
= POINTER_SIZE
/ BITS_PER_UNIT
;
4782 rsize
= UNITS_PER_WORD
;
4785 addr_rtx
= gen_reg_rtx (Pmode
);
4787 if (!EABI_FLOAT_VARARGS_P
)
4789 /* Case of all args in a merged stack. No need to check bounds,
4790 just advance valist along the stack. */
4795 && TYPE_ALIGN (type
) > (unsigned) BITS_PER_WORD
)
4797 /* Align the pointer using: ap = (ap + align - 1) & -align,
4798 where align is 2 * UNITS_PER_WORD. */
4799 t
= build (PLUS_EXPR
, TREE_TYPE (gpr
), gpr
,
4800 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
4801 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
4802 build_int_2 (-2 * UNITS_PER_WORD
, -1));
4803 t
= build (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
, t
);
4804 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4807 /* Emit code to set addr_rtx to the valist, and postincrement
4808 the valist by the size of the argument, rounded up to the
4810 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (gpr
), gpr
,
4812 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4814 emit_move_insn (addr_rtx
, r
);
4816 /* Flush the POSTINCREMENT. */
4821 /* Not a simple merged stack. */
4823 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4824 tree ovfl
, top
, off
;
4825 rtx lab_over
= NULL_RTX
, lab_false
;
4826 HOST_WIDE_INT osize
;
4828 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4829 f_gtop
= TREE_CHAIN (f_ovfl
);
4830 f_ftop
= TREE_CHAIN (f_gtop
);
4831 f_goff
= TREE_CHAIN (f_ftop
);
4832 f_foff
= TREE_CHAIN (f_goff
);
4834 /* We maintain separate pointers and offsets for floating-point
4835 and integer arguments, but we need similar code in both cases.
4838 TOP be the top of the register save area;
4839 OFF be the offset from TOP of the next register;
4840 ADDR_RTX be the address of the argument; and
4841 RSIZE be the number of bytes used to store the argument
4842 when it's in the register save area
4843 OSIZE be the number of bytes used to store it when it's
4844 in the stack overflow area
4845 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4847 The code we want is:
4849 1: off &= -rsize; // round down
4852 4: addr_rtx = top - off;
4857 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4858 10: addr_rtx = ovfl + PADDING;
4862 [1] and [9] can sometimes be optimized away. */
4864 lab_false
= gen_label_rtx ();
4865 lab_over
= gen_label_rtx ();
4867 ovfl
= build (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
);
4869 if (TREE_CODE (type
) == REAL_TYPE
)
4871 top
= build (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
);
4872 off
= build (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
);
4874 /* When floating-point registers are saved to the stack,
4875 each one will take up UNITS_PER_FPVALUE bytes, regardless
4876 of the float's precision. */
4877 rsize
= UNITS_PER_FPVALUE
;
4881 top
= build (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
);
4882 off
= build (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
);
4883 if (rsize
> UNITS_PER_WORD
)
4885 /* [1] Emit code for: off &= -rsize. */
4886 t
= build (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
4887 build_int_2 (-rsize
, -1));
4888 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
4889 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4892 /* Every overflow argument must take up at least UNITS_PER_WORD
4893 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4894 than that, such as in the combination -mgp64 -msingle-float
4895 -fshort-double. Doubles passed in registers will then take
4896 up UNITS_PER_FPVALUE bytes, but those passed on the stack
4897 take up UNITS_PER_WORD bytes. */
4898 osize
= MAX (rsize
, UNITS_PER_WORD
);
4900 /* [2] Emit code to branch if off == 0. */
4901 r
= expand_expr (off
, NULL_RTX
, TYPE_MODE (TREE_TYPE (off
)),
4903 emit_cmp_and_jump_insns (r
, const0_rtx
, EQ
, const1_rtx
, GET_MODE (r
),
4906 /* [4] Emit code for: addr_rtx = top - off. */
4907 t
= build (MINUS_EXPR
, TREE_TYPE (top
), top
, off
);
4908 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4910 emit_move_insn (addr_rtx
, r
);
4912 /* [5] Emit code for: off -= rsize. */
4913 t
= build (MINUS_EXPR
, TREE_TYPE (off
), off
, build_int_2 (rsize
, 0));
4914 t
= build (MODIFY_EXPR
, TREE_TYPE (off
), off
, t
);
4915 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4917 /* [7] Emit code to jump over the else clause, then the label
4920 emit_jump (lab_over
);
4922 emit_label (lab_false
);
4924 if (osize
> UNITS_PER_WORD
)
4926 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4927 t
= build (PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
,
4928 build_int_2 (osize
- 1, 0));
4929 t
= build (BIT_AND_EXPR
, TREE_TYPE (ovfl
), t
,
4930 build_int_2 (-osize
, -1));
4931 t
= build (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
4932 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4935 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4936 post-increment ovfl by osize. On big-endian machines,
4937 the argument has OSIZE - RSIZE bytes of leading padding. */
4938 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
,
4940 if (BYTES_BIG_ENDIAN
&& osize
> rsize
)
4941 t
= build (PLUS_EXPR
, TREE_TYPE (t
), t
,
4942 build_int_2 (osize
- rsize
, 0));
4943 r
= expand_expr (t
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4945 emit_move_insn (addr_rtx
, r
);
4948 emit_label (lab_over
);
4952 addr_rtx
= force_reg (Pmode
, addr_rtx
);
4953 r
= gen_rtx_MEM (Pmode
, addr_rtx
);
4954 set_mem_alias_set (r
, get_varargs_alias_set ());
4955 emit_move_insn (addr_rtx
, r
);
4959 if (BYTES_BIG_ENDIAN
&& rsize
!= size
)
4960 addr_rtx
= plus_constant (addr_rtx
, rsize
- size
);
4969 /* ??? The original va-mips.h did always align, despite the fact
4970 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4971 increment mechanism. */
4975 else if (TYPE_ALIGN (type
) > 32)
4980 t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
4981 build_int_2 (align
- 1, 0));
4982 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
, build_int_2 (-align
, -1));
4983 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
4984 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4986 /* Everything past the alignment is standard. */
4987 return std_expand_builtin_va_arg (valist
, type
);
4991 /* Abort after printing out a specific insn. */
4994 abort_with_insn (insn
, reason
)
5003 /* Set up globals to generate code for the ISA or processor
5004 described by INFO. */
5007 mips_set_architecture (info
)
5008 const struct mips_cpu_info
*info
;
5012 mips_arch_info
= info
;
5013 mips_arch
= info
->cpu
;
5014 mips_isa
= info
->isa
;
5019 /* Likewise for tuning. */
5022 mips_set_tune (info
)
5023 const struct mips_cpu_info
*info
;
5027 mips_tune_info
= info
;
5028 mips_tune
= info
->cpu
;
5033 /* Set up the threshold for data to go into the small data area, instead
5034 of the normal data area, and detect any conflicts in the switches. */
5039 int i
, start
, regno
;
5040 enum machine_mode mode
;
5042 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
5044 if (mips_section_threshold
<= 0)
5045 target_flags
&= ~MASK_GPOPT
;
5047 target_flags
|= MASK_GPOPT
;
5049 /* If both single-float and soft-float are set, then clear the one that
5050 was set by TARGET_DEFAULT, leaving the one that was set by the
5051 user. We assume here that the specs prevent both being set by the
5053 #ifdef TARGET_DEFAULT
5054 if (TARGET_SINGLE_FLOAT
&& TARGET_SOFT_FLOAT
)
5055 target_flags
&= ~((TARGET_DEFAULT
) & (MASK_SOFT_FLOAT
| MASK_SINGLE_FLOAT
));
5058 /* Interpret -mabi. */
5059 mips_abi
= MIPS_ABI_DEFAULT
;
5060 if (mips_abi_string
!= 0)
5062 if (strcmp (mips_abi_string
, "32") == 0)
5064 else if (strcmp (mips_abi_string
, "o64") == 0)
5066 else if (strcmp (mips_abi_string
, "n32") == 0)
5068 else if (strcmp (mips_abi_string
, "64") == 0)
5070 else if (strcmp (mips_abi_string
, "eabi") == 0)
5071 mips_abi
= ABI_EABI
;
5072 else if (strcmp (mips_abi_string
, "meabi") == 0)
5073 mips_abi
= ABI_MEABI
;
5075 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string
);
5078 /* The following code determines the architecture and register size.
5079 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5080 The GAS and GCC code should be kept in sync as much as possible. */
5082 if (mips_arch_string
!= 0)
5083 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string
));
5085 if (mips_tune_string
!= 0)
5086 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string
));
5088 if (mips_isa_string
!= 0)
5090 /* Handle -mipsN. */
5091 int level
= atoi (mips_isa_string
);
5094 /* -mips16 specifies an ASE rather than a processor, so don't
5095 change mips_arch here. -mno-mips16 overrides -mips16. */
5096 if (mips_no_mips16_string
== NULL
)
5097 target_flags
|= MASK_MIPS16
;
5099 else if (mips_arch_info
!= 0)
5101 /* -march takes precedence over -mipsN, since it is more descriptive.
5102 There's no harm in specifying both as long as the ISA levels
5104 if (mips_isa
!= level
)
5105 error ("-mips%d conflicts with the other architecture options, which specify a MIPS%d processor",
5110 mips_set_architecture (mips_cpu_info_from_isa (level
));
5111 if (mips_arch_info
== 0)
5112 error ("bad value (%s) for -mips switch", mips_isa_string
);
5116 if (mips_arch_info
== 0)
5118 #ifdef MIPS_CPU_STRING_DEFAULT
5119 mips_set_architecture (mips_parse_cpu ("default CPU",
5120 MIPS_CPU_STRING_DEFAULT
));
5122 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
5126 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
5127 error ("-march=%s is not compatible with the selected ABI",
5128 mips_arch_info
->name
);
5130 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5131 if (mips_tune_info
== 0)
5132 mips_set_tune (mips_arch_info
);
5134 if ((target_flags_explicit
& MASK_64BIT
) != 0)
5136 /* The user specified the size of the integer registers. Make sure
5137 it agrees with the ABI and ISA. */
5138 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
5139 error ("-mgp64 used with a 32-bit processor");
5140 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
5141 error ("-mgp32 used with a 64-bit ABI");
5142 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
5143 error ("-mgp64 used with a 32-bit ABI");
5147 /* Infer the integer register size from the ABI and processor.
5148 Restrict ourselves to 32-bit registers if that's all the
5149 processor has, or if the ABI cannot handle 64-bit registers. */
5150 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
5151 target_flags
&= ~MASK_64BIT
;
5153 target_flags
|= MASK_64BIT
;
5156 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
5158 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5159 only one right answer here. */
5160 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
5161 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5162 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
5163 error ("unsupported combination: %s", "-mgp32 -mfp64");
5164 else if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
5165 error ("unsupported combination: %s", "-mfp64 -msingle-float");
5169 /* -msingle-float selects 32-bit float registers. Otherwise the
5170 float registers should be the same size as the integer ones. */
5171 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
5172 target_flags
|= MASK_FLOAT64
;
5174 target_flags
&= ~MASK_FLOAT64
;
5177 /* End of code shared with GAS. */
5179 if ((target_flags_explicit
& MASK_LONG64
) == 0)
5181 /* If no type size setting options (-mlong64,-mint64,-mlong32)
5182 were used, then set the type sizes. In the EABI in 64 bit mode,
5183 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
5185 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
5186 target_flags
|= MASK_LONG64
;
5188 target_flags
&= ~MASK_LONG64
;
5191 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
5192 flag_pcc_struct_return
= 0;
5194 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
5196 /* If neither -mbranch-likely nor -mno-branch-likely was given
5197 on the command line, set MASK_BRANCHLIKELY based on the target
5200 By default, we enable use of Branch Likely instructions on
5201 all architectures which support them except for MIPS32 and MIPS64
5202 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
5205 The MIPS32 and MIPS64 architecture specifications say "Software
5206 is strongly encouraged to avoid use of Branch Likely
5207 instructions, as they will be removed from a future revision
5208 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
5209 issue those instructions unless instructed to do so by
5211 if (ISA_HAS_BRANCHLIKELY
&& !(ISA_MIPS32
|| ISA_MIPS64
))
5212 target_flags
|= MASK_BRANCHLIKELY
;
5214 target_flags
&= ~MASK_BRANCHLIKELY
;
5216 if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
5217 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
5219 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5220 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5221 /* ??? -non_shared turns off pic code generation, but this is not
5223 if (TARGET_ABICALLS
)
5225 mips_abicalls
= MIPS_ABICALLS_YES
;
5227 if (mips_section_threshold
> 0)
5228 warning ("-G is incompatible with PIC code which is the default");
5231 mips_abicalls
= MIPS_ABICALLS_NO
;
5233 /* -membedded-pic is a form of PIC code suitable for embedded
5234 systems. All calls are made using PC relative addressing, and
5235 all data is addressed using the $gp register. This requires gas,
5236 which does most of the work, and GNU ld, which automatically
5237 expands PC relative calls which are out of range into a longer
5238 instruction sequence. All gcc really does differently is
5239 generate a different sequence for a switch. */
5240 if (TARGET_EMBEDDED_PIC
)
5243 if (TARGET_ABICALLS
)
5244 warning ("-membedded-pic and -mabicalls are incompatible");
5247 warning ("-G and -membedded-pic are incompatible");
5249 /* Setting mips_section_threshold is not required, because gas
5250 will force everything to be GP addressable anyhow, but
5251 setting it will cause gcc to make better estimates of the
5252 number of instructions required to access a particular data
5254 mips_section_threshold
= 0x7fffffff;
5257 /* This optimization requires a linker that can support a R_MIPS_LO16
5258 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5259 GNU ld has this support, but not all other MIPS linkers do, so we enable
5260 this optimization only if the user requests it, or if GNU ld is the
5261 standard linker for this configuration. */
5262 /* ??? This does not work when target addresses are DImode.
5263 This is because we are missing DImode high/lo_sum patterns. */
5264 if (TARGET_GAS
&& ! TARGET_MIPS16
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
5266 mips_split_addresses
= 1;
5268 mips_split_addresses
= 0;
5270 /* -mrnames says to use the MIPS software convention for register
5271 names instead of the hardware names (ie, $a0 instead of $4).
5272 We do this by switching the names in mips_reg_names, which the
5273 reg_names points into via the REGISTER_NAMES macro. */
5275 if (TARGET_NAME_REGS
)
5276 memcpy (mips_reg_names
, mips_sw_reg_names
, sizeof (mips_reg_names
));
5278 /* When compiling for the mips16, we can not use floating point. We
5279 record the original hard float value in mips16_hard_float. */
5282 if (TARGET_SOFT_FLOAT
)
5283 mips16_hard_float
= 0;
5285 mips16_hard_float
= 1;
5286 target_flags
|= MASK_SOFT_FLOAT
;
5288 /* Don't run the scheduler before reload, since it tends to
5289 increase register pressure. */
5290 flag_schedule_insns
= 0;
5293 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5294 to avoid using up another bit in target_flags. */
5295 if (mips_entry_string
!= NULL
)
5297 if (*mips_entry_string
!= '\0')
5298 error ("invalid option `entry%s'", mips_entry_string
);
5300 if (! TARGET_MIPS16
)
5301 warning ("-mentry is only meaningful with -mips-16");
5306 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5307 attributes can access it. */
5313 /* Initialize the high and low values for legitimate floating point
5314 constants. Rather than trying to get the accuracy down to the
5315 last bit, just use approximate ranges. */
5316 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
5317 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
5318 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
5319 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
5321 mips_print_operand_punct
['?'] = 1;
5322 mips_print_operand_punct
['#'] = 1;
5323 mips_print_operand_punct
['&'] = 1;
5324 mips_print_operand_punct
['!'] = 1;
5325 mips_print_operand_punct
['*'] = 1;
5326 mips_print_operand_punct
['@'] = 1;
5327 mips_print_operand_punct
['.'] = 1;
5328 mips_print_operand_punct
['('] = 1;
5329 mips_print_operand_punct
[')'] = 1;
5330 mips_print_operand_punct
['['] = 1;
5331 mips_print_operand_punct
[']'] = 1;
5332 mips_print_operand_punct
['<'] = 1;
5333 mips_print_operand_punct
['>'] = 1;
5334 mips_print_operand_punct
['{'] = 1;
5335 mips_print_operand_punct
['}'] = 1;
5336 mips_print_operand_punct
['^'] = 1;
5337 mips_print_operand_punct
['$'] = 1;
5338 mips_print_operand_punct
['+'] = 1;
5339 mips_print_operand_punct
['~'] = 1;
5341 mips_char_to_class
['d'] = TARGET_MIPS16
? M16_REGS
: GR_REGS
;
5342 mips_char_to_class
['e'] = M16_NA_REGS
;
5343 mips_char_to_class
['t'] = T_REG
;
5344 mips_char_to_class
['f'] = (TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
);
5345 mips_char_to_class
['h'] = HI_REG
;
5346 mips_char_to_class
['l'] = LO_REG
;
5347 mips_char_to_class
['a'] = HILO_REG
;
5348 mips_char_to_class
['x'] = MD_REGS
;
5349 mips_char_to_class
['b'] = ALL_REGS
;
5350 mips_char_to_class
['y'] = GR_REGS
;
5351 mips_char_to_class
['z'] = ST_REGS
;
5352 mips_char_to_class
['B'] = COP0_REGS
;
5353 mips_char_to_class
['C'] = COP2_REGS
;
5354 mips_char_to_class
['D'] = COP3_REGS
;
5356 /* Set up array to map GCC register number to debug register number.
5357 Ignore the special purpose register numbers. */
5359 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5360 mips_dbx_regno
[i
] = -1;
5362 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
5363 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
5364 mips_dbx_regno
[i
] = i
+ start
;
5366 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
5367 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
5368 mips_dbx_regno
[i
] = i
+ start
;
5370 /* Set up array giving whether a given register can hold a given mode.
5371 At present, restrict ints from being in FP registers, because reload
5372 is a little enthusiastic about storing extra values in FP registers,
5373 and this is not good for things like OS kernels. Also, due to the
5374 mandatory delay, it is as fast to load from cached memory as to move
5375 from the FP register. */
5377 for (mode
= VOIDmode
;
5378 mode
!= MAX_MACHINE_MODE
;
5379 mode
= (enum machine_mode
) ((int)mode
+ 1))
5381 register int size
= GET_MODE_SIZE (mode
);
5382 register enum mode_class
class = GET_MODE_CLASS (mode
);
5384 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
5391 temp
= (regno
== FPSW_REGNUM
);
5393 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
5394 || FP_REG_P (regno
));
5397 else if (GP_REG_P (regno
))
5398 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
5400 else if (FP_REG_P (regno
))
5401 temp
= (((regno
% FP_INC
) == 0
5402 /* I think this change is OK regardless of abi, but
5403 I'm being cautions untill I can test this more.
5404 HARD_REGNO_MODE_OK is about whether or not you
5405 can move to and from a register without changing
5406 the value, not about whether math works on the
5408 || (mips_abi
== ABI_MEABI
&& size
<= 4))
5409 && (((class == MODE_FLOAT
|| class == MODE_COMPLEX_FLOAT
)
5410 && size
<= UNITS_PER_FPVALUE
)
5411 /* Allow integer modes that fit into a single
5412 register. We need to put integers into FPRs
5413 when using instructions like cvt and trunc. */
5414 || (class == MODE_INT
&& size
<= UNITS_PER_FPREG
)));
5416 else if (MD_REG_P (regno
))
5417 temp
= (class == MODE_INT
5418 && (size
<= UNITS_PER_WORD
5419 || (regno
== MD_REG_FIRST
5420 && size
== 2 * UNITS_PER_WORD
)));
5422 else if (ALL_COP_REG_P (regno
))
5423 temp
= (class == MODE_INT
&& size
<= UNITS_PER_WORD
);
5427 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
5431 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5432 initialized yet, so we can't use that here. */
5433 gpr_mode
= TARGET_64BIT
? DImode
: SImode
;
5435 /* Provide default values for align_* for 64-bit targets. */
5436 if (TARGET_64BIT
&& !TARGET_MIPS16
)
5438 if (align_loops
== 0)
5440 if (align_jumps
== 0)
5442 if (align_functions
== 0)
5443 align_functions
= 8;
5446 /* Function to allocate machine-dependent function status. */
5447 init_machine_status
= &mips_init_machine_status
;
5450 /* Implement CONDITIONAL_REGISTER_USAGE. */
5453 mips_conditional_register_usage ()
5455 if (!TARGET_HARD_FLOAT
)
5459 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
5460 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5461 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
5462 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5464 else if (! ISA_HAS_8CC
)
5468 /* We only have a single condition code register. We
5469 implement this by hiding all the condition code registers,
5470 and generating RTL that refers directly to ST_REG_FIRST. */
5471 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
5472 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
5474 /* In mips16 mode, we permit the $t temporary registers to be used
5475 for reload. We prohibit the unused $s registers, since they
5476 are caller saved, and saving them via a mips16 register would
5477 probably waste more time than just reloading the value. */
5480 fixed_regs
[18] = call_used_regs
[18] = 1;
5481 fixed_regs
[19] = call_used_regs
[19] = 1;
5482 fixed_regs
[20] = call_used_regs
[20] = 1;
5483 fixed_regs
[21] = call_used_regs
[21] = 1;
5484 fixed_regs
[22] = call_used_regs
[22] = 1;
5485 fixed_regs
[23] = call_used_regs
[23] = 1;
5486 fixed_regs
[26] = call_used_regs
[26] = 1;
5487 fixed_regs
[27] = call_used_regs
[27] = 1;
5488 fixed_regs
[30] = call_used_regs
[30] = 1;
5490 /* fp20-23 are now caller saved. */
5491 if (mips_abi
== ABI_64
)
5494 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
5495 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
5497 /* odd registers from fp21 to fp31 are now caller saved. */
5498 if (mips_abi
== ABI_N32
|| mips_abi
== ABI_MEABI
)
5501 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
5502 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
5506 /* Allocate a chunk of memory for per-function machine-dependent data. */
5507 static struct machine_function
*
5508 mips_init_machine_status ()
5510 return ((struct machine_function
*)
5511 ggc_alloc_cleared (sizeof (struct machine_function
)));
5514 /* On the mips16, we want to allocate $24 (T_REG) before other
5515 registers for instructions for which it is possible. This helps
5516 avoid shuffling registers around in order to set up for an xor,
5517 encouraging the compiler to use a cmp instead. */
5520 mips_order_regs_for_local_alloc ()
5524 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5525 reg_alloc_order
[i
] = i
;
5529 /* It really doesn't matter where we put register 0, since it is
5530 a fixed register anyhow. */
5531 reg_alloc_order
[0] = 24;
5532 reg_alloc_order
[24] = 0;
5537 /* The MIPS debug format wants all automatic variables and arguments
5538 to be in terms of the virtual frame pointer (stack pointer before
5539 any adjustment in the function), while the MIPS 3.0 linker wants
5540 the frame pointer to be the stack pointer after the initial
5541 adjustment. So, we do the adjustment here. The arg pointer (which
5542 is eliminated) points to the virtual frame pointer, while the frame
5543 pointer (which may be eliminated) points to the stack pointer after
5544 the initial adjustments. */
5547 mips_debugger_offset (addr
, offset
)
5549 HOST_WIDE_INT offset
;
5551 rtx offset2
= const0_rtx
;
5552 rtx reg
= eliminate_constant_term (addr
, &offset2
);
5555 offset
= INTVAL (offset2
);
5557 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
5558 || reg
== hard_frame_pointer_rtx
)
5560 HOST_WIDE_INT frame_size
= (!cfun
->machine
->frame
.initialized
)
5561 ? compute_frame_size (get_frame_size ())
5562 : cfun
->machine
->frame
.total_size
;
5564 /* MIPS16 frame is smaller */
5565 if (frame_pointer_needed
&& TARGET_MIPS16
)
5566 frame_size
-= current_function_outgoing_args_size
;
5568 offset
= offset
- frame_size
;
5571 /* sdbout_parms does not want this to crash for unrecognized cases. */
5573 else if (reg
!= arg_pointer_rtx
)
5574 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer");
5580 /* A C compound statement to output to stdio stream STREAM the
5581 assembler syntax for an instruction operand X. X is an RTL
5584 CODE is a value that can be used to specify one of several ways
5585 of printing the operand. It is used when identical operands
5586 must be printed differently depending on the context. CODE
5587 comes from the `%' specification that was used to request
5588 printing of the operand. If the specification was just `%DIGIT'
5589 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5590 is the ASCII code for LTR.
5592 If X is a register, this macro should print the register's name.
5593 The names can be found in an array `reg_names' whose type is
5594 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5596 When the machine description has a specification `%PUNCT' (a `%'
5597 followed by a punctuation character), this macro is called with
5598 a null pointer for X and the punctuation character for CODE.
5600 The MIPS specific codes are:
5602 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5603 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5604 'd' output integer constant in decimal,
5605 'z' if the operand is 0, use $0 instead of normal operand.
5606 'D' print second part of double-word register or memory operand.
5607 'L' print low-order register of double-word register operand.
5608 'M' print high-order register of double-word register operand.
5609 'C' print part of opcode for a branch condition.
5610 'F' print part of opcode for a floating-point branch condition.
5611 'N' print part of opcode for a branch condition, inverted.
5612 'W' print part of opcode for a floating-point branch condition, inverted.
5613 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5614 'B' print 'z' for EQ, 'n' for NE
5615 'b' print 'n' for EQ, 'z' for NE
5616 'T' print 'f' for EQ, 't' for NE
5617 't' print 't' for EQ, 'f' for NE
5618 'Z' print register and a comma, but print nothing for $fcc0
5619 '(' Turn on .set noreorder
5620 ')' Turn on .set reorder
5621 '[' Turn on .set noat
5623 '<' Turn on .set nomacro
5624 '>' Turn on .set macro
5625 '{' Turn on .set volatile (not GAS)
5626 '}' Turn on .set novolatile (not GAS)
5627 '&' Turn on .set noreorder if filling delay slots
5628 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5629 '!' Turn on .set nomacro if filling delay slots
5630 '#' Print nop if in a .set noreorder section.
5631 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5632 '@' Print the name of the assembler temporary register (at or $1).
5633 '.' Print the name of the register with a hard-wired zero (zero or $0).
5634 '^' Print the name of the pic call-through register (t9 or $25).
5635 '$' Print the name of the stack pointer register (sp or $29).
5636 '+' Print the name of the gp register (gp or $28).
5637 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5640 print_operand (file
, op
, letter
)
5641 FILE *file
; /* file to write to */
5642 rtx op
; /* operand to print */
5643 int letter
; /* %<letter> or 0 */
5645 register enum rtx_code code
;
5647 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
5652 if (mips_branch_likely
)
5657 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
5661 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
5665 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
5669 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
5673 fputs (reg_names
[GP_REG_FIRST
+ 28], file
);
5677 if (final_sequence
!= 0 && set_noreorder
++ == 0)
5678 fputs (".set\tnoreorder\n\t", file
);
5682 if (final_sequence
!= 0)
5684 if (set_noreorder
++ == 0)
5685 fputs (".set\tnoreorder\n\t", file
);
5687 if (set_nomacro
++ == 0)
5688 fputs (".set\tnomacro\n\t", file
);
5693 if (final_sequence
!= 0 && set_nomacro
++ == 0)
5694 fputs ("\n\t.set\tnomacro", file
);
5698 if (set_noreorder
!= 0)
5699 fputs ("\n\tnop", file
);
5700 else if (TARGET_STATS
)
5701 fputs ("\n\t#nop", file
);
5706 if (set_noreorder
++ == 0)
5707 fputs (".set\tnoreorder\n\t", file
);
5711 if (set_noreorder
== 0)
5712 error ("internal error: %%) found without a %%( in assembler pattern");
5714 else if (--set_noreorder
== 0)
5715 fputs ("\n\t.set\treorder", file
);
5720 if (set_noat
++ == 0)
5721 fputs (".set\tnoat\n\t", file
);
5726 error ("internal error: %%] found without a %%[ in assembler pattern");
5727 else if (--set_noat
== 0)
5728 fputs ("\n\t.set\tat", file
);
5733 if (set_nomacro
++ == 0)
5734 fputs (".set\tnomacro\n\t", file
);
5738 if (set_nomacro
== 0)
5739 error ("internal error: %%> found without a %%< in assembler pattern");
5740 else if (--set_nomacro
== 0)
5741 fputs ("\n\t.set\tmacro", file
);
5746 if (set_volatile
++ == 0)
5747 fprintf (file
, "%s.set\tvolatile\n\t", TARGET_MIPS_AS
? "" : "#");
5751 if (set_volatile
== 0)
5752 error ("internal error: %%} found without a %%{ in assembler pattern");
5753 else if (--set_volatile
== 0)
5754 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
5760 if (align_labels_log
> 0)
5761 ASM_OUTPUT_ALIGN (file
, align_labels_log
);
5766 error ("PRINT_OPERAND: unknown punctuation '%c'", letter
);
5775 error ("PRINT_OPERAND null pointer");
5779 code
= GET_CODE (op
);
5781 if (code
== SIGN_EXTEND
)
5782 op
= XEXP (op
, 0), code
= GET_CODE (op
);
5787 case EQ
: fputs ("eq", file
); break;
5788 case NE
: fputs ("ne", file
); break;
5789 case GT
: fputs ("gt", file
); break;
5790 case GE
: fputs ("ge", file
); break;
5791 case LT
: fputs ("lt", file
); break;
5792 case LE
: fputs ("le", file
); break;
5793 case GTU
: fputs ("gtu", file
); break;
5794 case GEU
: fputs ("geu", file
); break;
5795 case LTU
: fputs ("ltu", file
); break;
5796 case LEU
: fputs ("leu", file
); break;
5798 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
5801 else if (letter
== 'N')
5804 case EQ
: fputs ("ne", file
); break;
5805 case NE
: fputs ("eq", file
); break;
5806 case GT
: fputs ("le", file
); break;
5807 case GE
: fputs ("lt", file
); break;
5808 case LT
: fputs ("ge", file
); break;
5809 case LE
: fputs ("gt", file
); break;
5810 case GTU
: fputs ("leu", file
); break;
5811 case GEU
: fputs ("ltu", file
); break;
5812 case LTU
: fputs ("geu", file
); break;
5813 case LEU
: fputs ("gtu", file
); break;
5815 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
5818 else if (letter
== 'F')
5821 case EQ
: fputs ("c1f", file
); break;
5822 case NE
: fputs ("c1t", file
); break;
5824 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%F");
5827 else if (letter
== 'W')
5830 case EQ
: fputs ("c1t", file
); break;
5831 case NE
: fputs ("c1f", file
); break;
5833 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%W");
5836 else if (letter
== 'S')
5840 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
5841 assemble_name (file
, buffer
);
5844 else if (letter
== 'Z')
5846 register int regnum
;
5851 regnum
= REGNO (op
);
5852 if (! ST_REG_P (regnum
))
5855 if (regnum
!= ST_REG_FIRST
)
5856 fprintf (file
, "%s,", reg_names
[regnum
]);
5859 else if (code
== REG
|| code
== SUBREG
)
5861 register int regnum
;
5864 regnum
= REGNO (op
);
5866 regnum
= true_regnum (op
);
5868 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
5869 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
5873 fprintf (file
, "%s", reg_names
[regnum
]);
5876 else if (code
== MEM
)
5879 output_address (plus_constant (XEXP (op
, 0), 4));
5881 output_address (XEXP (op
, 0));
5884 else if (code
== CONST_DOUBLE
5885 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
5890 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
5891 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
5895 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
5896 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, 0xffff & INTVAL(op
));
5898 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
5899 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
5901 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
5902 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
5904 else if (letter
== 'z' && GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
5905 fputs (reg_names
[GP_REG_FIRST
], file
);
5907 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
5908 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5910 else if (letter
== 'B')
5911 fputs (code
== EQ
? "z" : "n", file
);
5912 else if (letter
== 'b')
5913 fputs (code
== EQ
? "n" : "z", file
);
5914 else if (letter
== 'T')
5915 fputs (code
== EQ
? "f" : "t", file
);
5916 else if (letter
== 't')
5917 fputs (code
== EQ
? "t" : "f", file
);
5919 else if (code
== CONST
&& GET_CODE (XEXP (op
, 0)) == REG
)
5921 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5922 print_operand (file
, XEXP (op
, 0), letter
);
5925 else if (TARGET_MIPS16
&& code
== CONST
&& mips16_gp_offset_p (op
))
5927 fputs ("%gprel(", file
);
5928 mips16_output_gp_offset (file
, op
);
5933 output_addr_const (file
, op
);
5936 /* A C compound statement to output to stdio stream STREAM the
5937 assembler syntax for an instruction operand that is a memory
5938 reference whose address is ADDR. ADDR is an RTL expression. */
5941 print_operand_address (file
, addr
)
5946 error ("PRINT_OPERAND_ADDRESS, null pointer");
5949 switch (GET_CODE (addr
))
5952 if (! TARGET_MIPS16
&& REGNO (addr
) == ARG_POINTER_REGNUM
)
5953 abort_with_insn (addr
, "arg pointer not eliminated");
5955 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
5960 register rtx arg0
= XEXP (addr
, 0);
5961 register rtx arg1
= XEXP (addr
, 1);
5963 if (! mips_split_addresses
)
5964 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
5966 if (GET_CODE (arg0
) != REG
)
5967 abort_with_insn (addr
,
5968 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
5970 fprintf (file
, "%%lo(");
5971 print_operand_address (file
, arg1
);
5972 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
5978 register rtx reg
= 0;
5979 register rtx offset
= 0;
5980 register rtx arg0
= XEXP (addr
, 0);
5981 register rtx arg1
= XEXP (addr
, 1);
5983 if (GET_CODE (arg0
) == REG
)
5987 if (GET_CODE (offset
) == REG
)
5988 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
5991 else if (GET_CODE (arg1
) == REG
)
5992 reg
= arg1
, offset
= arg0
;
5993 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
5995 output_addr_const (file
, addr
);
5999 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
6001 if (! CONSTANT_P (offset
))
6002 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
6004 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
6005 abort_with_insn (addr
, "arg pointer not eliminated");
6008 && GET_CODE (offset
) == CONST
6009 && mips16_gp_offset_p (offset
))
6011 fputs ("%gprel(", file
);
6012 mips16_output_gp_offset (file
, offset
);
6016 output_addr_const (file
, offset
);
6017 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
6025 output_addr_const (file
, addr
);
6029 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
6034 /* Target hook for assembling integer objects. It appears that the Irix
6035 6 assembler can't handle 64-bit decimal integers, so avoid printing
6036 such an integer here. */
6039 mips_assemble_integer (x
, size
, aligned_p
)
6044 if ((TARGET_64BIT
|| TARGET_GAS
) && size
== 8 && aligned_p
)
6046 fputs ("\t.dword\t", asm_out_file
);
6047 if (HOST_BITS_PER_WIDE_INT
< 64 || GET_CODE (x
) != CONST_INT
)
6048 output_addr_const (asm_out_file
, x
);
6050 print_operand (asm_out_file
, x
, 'X');
6051 fputc ('\n', asm_out_file
);
6054 return default_assemble_integer (x
, size
, aligned_p
);
6057 /* If optimizing for the global pointer, keep track of all of the externs, so
6058 that at the end of the file, we can emit the appropriate .extern
6059 declaration for them, before writing out the text section. We assume all
6060 names passed to us are in the permanent obstack, so they will be valid at
6061 the end of the compilation.
6063 If we have -G 0, or the extern size is unknown, or the object is in a user
6064 specified section that is not .sbss/.sdata, don't bother emitting the
6065 .externs. In the case of user specified sections this behaviour is
6066 required as otherwise GAS will think the object lives in .sbss/.sdata. */
6069 mips_output_external (file
, decl
, name
)
6070 FILE *file ATTRIBUTE_UNUSED
;
6074 register struct extern_list
*p
;
6079 && TREE_CODE (decl
) != FUNCTION_DECL
6080 && !DECL_COMDAT (decl
)
6081 && (len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0
6082 && ((section_name
= DECL_SECTION_NAME (decl
)) == NULL
6083 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
6084 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
6086 p
= (struct extern_list
*) xmalloc (sizeof (struct extern_list
));
6087 p
->next
= extern_head
;
6093 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6094 if (TREE_CODE (decl
) == FUNCTION_DECL
6095 /* ??? Don't include alloca, since gcc will always expand it
6096 inline. If we don't do this, the C++ library fails to build. */
6097 && strcmp (name
, "alloca")
6098 /* ??? Don't include __builtin_next_arg, because then gcc will not
6099 bootstrap under Irix 5.1. */
6100 && strcmp (name
, "__builtin_next_arg"))
6102 p
= (struct extern_list
*) xmalloc (sizeof (struct extern_list
));
6103 p
->next
= extern_head
;
6113 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6115 mips_output_external_libcall (file
, name
)
6116 FILE *file ATTRIBUTE_UNUSED
;
6119 register struct extern_list
*p
;
6121 p
= (struct extern_list
*) xmalloc (sizeof (struct extern_list
));
6122 p
->next
= extern_head
;
6131 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
6132 for .file's that start within a function. If we are smuggling stabs, try to
6133 put out a MIPS ECOFF file and a stab. */
6136 mips_output_filename (stream
, name
)
6140 static int first_time
= 1;
6141 char ltext_label_name
[100];
6143 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6145 if (write_symbols
== DWARF2_DEBUG
)
6147 else if (first_time
)
6151 current_function_file
= name
;
6152 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
6153 /* This tells mips-tfile that stabs will follow. */
6154 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
6155 fprintf (stream
, "\t#@stabs\n");
6158 else if (write_symbols
== DBX_DEBUG
)
6160 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
6161 fprintf (stream
, "%s", ASM_STABS_OP
);
6162 output_quoted_string (stream
, name
);
6163 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
6166 else if (name
!= current_function_file
6167 && strcmp (name
, current_function_file
) != 0)
6169 if (inside_function
&& !TARGET_GAS
)
6171 if (!file_in_function_warning
)
6173 file_in_function_warning
= 1;
6174 ignore_line_number
= 1;
6175 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
6181 current_function_file
= name
;
6182 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
6187 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
6188 as well as a .loc, since it is possible that MIPS ECOFF might not be
6189 able to represent the location for inlines that come from a different
6193 mips_output_lineno (stream
, line
)
6197 if (write_symbols
== DBX_DEBUG
)
6200 fprintf (stream
, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
6201 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
6202 LOCAL_LABEL_PREFIX
, sym_lineno
);
6206 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
6207 (ignore_line_number
) ? "#" : "",
6208 num_source_filenames
, line
);
6210 LABEL_AFTER_LOC (stream
);
6214 /* Output an ASCII string, in a space-saving way. */
6217 mips_output_ascii (stream
, string_param
, len
)
6219 const char *string_param
;
6224 register const unsigned char *string
=
6225 (const unsigned char *)string_param
;
6227 fprintf (stream
, "\t.ascii\t\"");
6228 for (i
= 0; i
< len
; i
++)
6230 register int c
= string
[i
];
6236 putc ('\\', stream
);
6241 case TARGET_NEWLINE
:
6242 fputs ("\\n", stream
);
6244 && (((c
= string
[i
+1]) >= '\040' && c
<= '~')
6245 || c
== TARGET_TAB
))
6246 cur_pos
= 32767; /* break right here */
6252 fputs ("\\t", stream
);
6257 fputs ("\\f", stream
);
6262 fputs ("\\b", stream
);
6267 fputs ("\\r", stream
);
6272 if (c
>= ' ' && c
< 0177)
6279 fprintf (stream
, "\\%03o", c
);
6284 if (cur_pos
> 72 && i
+1 < len
)
6287 fprintf (stream
, "\"\n\t.ascii\t\"");
6290 fprintf (stream
, "\"\n");
6293 /* If defined, a C statement to be executed just prior to the output of
6294 assembler code for INSN, to modify the extracted operands so they will be
6297 Here the argument OPVEC is the vector containing the operands extracted
6298 from INSN, and NOPERANDS is the number of elements of the vector which
6299 contain meaningful data for this insn. The contents of this vector are
6300 what will be used to convert the insn template into assembler code, so you
6301 can change the assembler output by changing the contents of the vector.
6303 We use it to check if the current insn needs a nop in front of it because
6304 of load delays, and also to update the delay slot statistics. */
6306 /* ??? There is no real need for this function, because it never actually
6307 emits a NOP anymore. */
6310 final_prescan_insn (insn
, opvec
, noperands
)
6312 rtx opvec
[] ATTRIBUTE_UNUSED
;
6313 int noperands ATTRIBUTE_UNUSED
;
6315 if (dslots_number_nops
> 0)
6317 rtx pattern
= PATTERN (insn
);
6318 int length
= get_attr_length (insn
);
6320 /* Do we need to emit a NOP? */
6322 || (mips_load_reg
!= 0 && reg_mentioned_p (mips_load_reg
, pattern
))
6323 || (mips_load_reg2
!= 0 && reg_mentioned_p (mips_load_reg2
, pattern
))
6324 || (mips_load_reg3
!= 0 && reg_mentioned_p (mips_load_reg3
, pattern
))
6325 || (mips_load_reg4
!= 0
6326 && reg_mentioned_p (mips_load_reg4
, pattern
)))
6327 fputs ("\t#nop\n", asm_out_file
);
6330 dslots_load_filled
++;
6332 while (--dslots_number_nops
> 0)
6333 fputs ("\t#nop\n", asm_out_file
);
6342 && (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CALL_INSN
))
6343 dslots_jump_total
++;
6346 /* Output at beginning of assembler file.
6348 If we are optimizing to use the global pointer, create a temporary file to
6349 hold all of the text stuff, and write it out to the end. This is needed
6350 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6351 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6352 processed, it generates a two instruction sequence. */
6355 mips_asm_file_start (stream
)
6358 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
6360 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6361 inside of a .set noreorder section jumps to a label outside of the .set
6362 noreorder section. Revision 2.20 just set nobopt silently rather than
6365 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
6366 fprintf (stream
, "\t.set\tnobopt\n");
6370 #if defined(OBJECT_FORMAT_ELF) && !(TARGET_IRIX5 || TARGET_IRIX6)
6371 /* Generate a special section to describe the ABI switches used to
6372 produce the resultant binary. This used to be done by the assembler
6373 setting bits in the ELF header's flags field, but we have run out of
6374 bits. GDB needs this information in order to be able to correctly
6375 debug these binaries. See the function mips_gdbarch_init() in
6376 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6377 causes unnecessary IRIX 6 ld warnings. */
6378 const char * abi_string
= NULL
;
6382 case ABI_32
: abi_string
= "abi32"; break;
6383 case ABI_N32
: abi_string
= "abiN32"; break;
6384 case ABI_64
: abi_string
= "abi64"; break;
6385 case ABI_O64
: abi_string
= "abiO64"; break;
6386 case ABI_EABI
: abi_string
= TARGET_64BIT
? "eabi64" : "eabi32"; break;
6387 case ABI_MEABI
:abi_string
= TARGET_64BIT
? "meabi64" : "meabi32"; break;
6391 /* Note - we use fprintf directly rather than called named_section()
6392 because in this way we can avoid creating an allocated section. We
6393 do not want this section to take up any space in the running
6395 fprintf (stream
, "\t.section .mdebug.%s\n", abi_string
);
6397 /* Restore the default section. */
6398 fprintf (stream
, "\t.previous\n");
6404 /* Generate the pseudo ops that System V.4 wants. */
6405 #ifndef ABICALLS_ASM_OP
6406 #define ABICALLS_ASM_OP "\t.abicalls"
6408 if (TARGET_ABICALLS
)
6409 /* ??? but do not want this (or want pic0) if -non-shared? */
6410 fprintf (stream
, "%s\n", ABICALLS_ASM_OP
);
6413 fprintf (stream
, "\t.set\tmips16\n");
6415 /* This code exists so that we can put all externs before all symbol
6416 references. This is necessary for the MIPS assembler's global pointer
6417 optimizations to work. */
6418 if (TARGET_FILE_SWITCHING
)
6420 asm_out_data_file
= stream
;
6421 asm_out_text_file
= tmpfile ();
6424 asm_out_data_file
= asm_out_text_file
= stream
;
6426 if (flag_verbose_asm
)
6427 fprintf (stream
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6429 mips_section_threshold
, mips_arch_info
->name
, mips_isa
);
6432 /* If we are optimizing the global pointer, emit the text section now and any
6433 small externs which did not have .comm, etc that are needed. Also, give a
6434 warning if the data area is more than 32K and -pic because 3 instructions
6435 are needed to reference the data pointers. */
6438 mips_asm_file_end (file
)
6442 struct extern_list
*p
;
6448 for (p
= extern_head
; p
!= 0; p
= p
->next
)
6450 name_tree
= get_identifier (p
->name
);
6452 /* Positively ensure only one .extern for any given symbol. */
6453 if (! TREE_ASM_WRITTEN (name_tree
))
6455 TREE_ASM_WRITTEN (name_tree
) = 1;
6456 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6458 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
6462 fputs ("\t.extern\t", file
);
6463 assemble_name (file
, p
->name
);
6464 fprintf (file
, ", %d\n", p
->size
);
6470 if (TARGET_FILE_SWITCHING
)
6472 fprintf (file
, "\n\t.text\n");
6473 copy_file_data (file
, asm_out_text_file
);
6478 copy_file_data (to
, from
)
6485 fatal_io_error ("can't rewind temp file");
6487 while ((len
= fread (buffer
, 1, sizeof (buffer
), from
)) > 0)
6488 if (fwrite (buffer
, 1, len
, to
) != len
)
6489 fatal_io_error ("can't write to output file");
6492 fatal_io_error ("can't read from temp file");
6495 fatal_io_error ("can't close temp file");
6498 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6499 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6502 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
6505 const char *init_string
;
6506 const char *final_string
;
6509 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
6510 assemble_name (stream
, name
);
6511 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
6515 tree name_tree
= get_identifier (name
);
6516 TREE_ASM_WRITTEN (name_tree
) = 1;
6520 /* Return the bytes needed to compute the frame pointer from the current
6523 Mips stack frames look like:
6525 Before call After call
6526 +-----------------------+ +-----------------------+
6529 | caller's temps. | | caller's temps. |
6531 +-----------------------+ +-----------------------+
6533 | arguments on stack. | | arguments on stack. |
6535 +-----------------------+ +-----------------------+
6536 | 4 words to save | | 4 words to save |
6537 | arguments passed | | arguments passed |
6538 | in registers, even | | in registers, even |
6539 SP->| if not passed. | VFP->| if not passed. |
6540 +-----------------------+ +-----------------------+
6542 | fp register save |
6544 +-----------------------+
6546 | gp register save |
6548 +-----------------------+
6552 +-----------------------+
6554 | alloca allocations |
6556 +-----------------------+
6558 | GP save for V.4 abi |
6560 +-----------------------+
6562 | arguments on stack |
6564 +-----------------------+
6566 | arguments passed |
6567 | in registers, even |
6568 low SP->| if not passed. |
6569 memory +-----------------------+
6574 compute_frame_size (size
)
6575 HOST_WIDE_INT size
; /* # of var. bytes allocated */
6578 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
6579 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
6580 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
6581 HOST_WIDE_INT extra_size
; /* # extra bytes */
6582 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
6583 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
6584 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
6585 long mask
; /* mask of saved gp registers */
6586 long fmask
; /* mask of saved fp registers */
6593 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
6594 var_size
= MIPS_STACK_ALIGN (size
);
6595 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
6597 /* The MIPS 3.0 linker does not like functions that dynamically
6598 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6599 looks like we are trying to create a second frame pointer to the
6600 function, so allocate some stack space to make it happy. */
6602 if (args_size
== 0 && current_function_calls_alloca
)
6603 args_size
= 4 * UNITS_PER_WORD
;
6605 total_size
= var_size
+ args_size
+ extra_size
;
6606 return_type
= DECL_RESULT (current_function_decl
);
6608 /* Calculate space needed for gp registers. */
6609 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
6611 /* $18 is a special case on the mips16. It may be used to call
6612 a function which returns a floating point value, but it is
6613 marked in call_used_regs. $31 is also a special case. When
6614 not using -mentry, it will be used to copy a return value
6615 into the floating point registers if the return value is
6617 if (MUST_SAVE_REGISTER (regno
)
6619 && regno
== GP_REG_FIRST
+ 18
6620 && regs_ever_live
[regno
])
6622 && regno
== GP_REG_FIRST
+ 31
6623 && mips16_hard_float
6625 && ! aggregate_value_p (return_type
)
6626 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
6627 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
))
6629 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6630 mask
|= 1L << (regno
- GP_REG_FIRST
);
6632 /* The entry and exit pseudo instructions can not save $17
6633 without also saving $16. */
6635 && regno
== GP_REG_FIRST
+ 17
6636 && ! MUST_SAVE_REGISTER (GP_REG_FIRST
+ 16))
6638 gp_reg_size
+= UNITS_PER_WORD
;
6644 /* We need to restore these for the handler. */
6645 if (current_function_calls_eh_return
)
6650 regno
= EH_RETURN_DATA_REGNO (i
);
6651 if (regno
== INVALID_REGNUM
)
6653 gp_reg_size
+= GET_MODE_SIZE (gpr_mode
);
6654 mask
|= 1L << (regno
- GP_REG_FIRST
);
6658 /* This loop must iterate over the same space as its companion in
6659 save_restore_insns. */
6660 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
6661 regno
>= FP_REG_FIRST
;
6664 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6666 fp_reg_size
+= FP_INC
* UNITS_PER_FPREG
;
6667 fmask
|= ((1 << FP_INC
) - 1) << (regno
- FP_REG_FIRST
);
6671 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6672 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
6674 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6675 for leaf routines (total_size == extra_size) to save the gp reg.
6676 The gp reg is callee saved in the 64 bit ABI, so all routines must
6677 save the gp reg. This is not a leaf routine if -p, because of the
6679 if (total_size
== extra_size
6680 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
|| mips_abi
== ABI_EABI
)
6681 && ! current_function_profile
)
6682 total_size
= extra_size
= 0;
6683 else if (TARGET_ABICALLS
)
6685 /* Add the context-pointer to the saved registers. */
6686 gp_reg_size
+= UNITS_PER_WORD
;
6687 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
6688 total_size
-= gp_reg_rounded
;
6689 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
6690 total_size
+= gp_reg_rounded
;
6693 /* Add in space reserved on the stack by the callee for storing arguments
6694 passed in registers. */
6695 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
6696 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
6698 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6699 if (mips_entry
&& total_size
> 0 && total_size
< 32)
6702 /* Save other computed information. */
6703 cfun
->machine
->frame
.total_size
= total_size
;
6704 cfun
->machine
->frame
.var_size
= var_size
;
6705 cfun
->machine
->frame
.args_size
= args_size
;
6706 cfun
->machine
->frame
.extra_size
= extra_size
;
6707 cfun
->machine
->frame
.gp_reg_size
= gp_reg_size
;
6708 cfun
->machine
->frame
.fp_reg_size
= fp_reg_size
;
6709 cfun
->machine
->frame
.mask
= mask
;
6710 cfun
->machine
->frame
.fmask
= fmask
;
6711 cfun
->machine
->frame
.initialized
= reload_completed
;
6712 cfun
->machine
->frame
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
6713 cfun
->machine
->frame
.num_fp
= fp_reg_size
/ (FP_INC
* UNITS_PER_FPREG
);
6717 unsigned long offset
;
6719 /* When using mips_entry, the registers are always saved at the
6720 top of the stack. */
6722 offset
= (args_size
+ extra_size
+ var_size
6723 + gp_reg_size
- GET_MODE_SIZE (gpr_mode
));
6725 offset
= total_size
- GET_MODE_SIZE (gpr_mode
);
6727 cfun
->machine
->frame
.gp_sp_offset
= offset
;
6728 cfun
->machine
->frame
.gp_save_offset
= offset
- total_size
;
6732 cfun
->machine
->frame
.gp_sp_offset
= 0;
6733 cfun
->machine
->frame
.gp_save_offset
= 0;
6738 unsigned long offset
= (args_size
+ extra_size
+ var_size
6739 + gp_reg_rounded
+ fp_reg_size
6740 - FP_INC
* UNITS_PER_FPREG
);
6741 cfun
->machine
->frame
.fp_sp_offset
= offset
;
6742 cfun
->machine
->frame
.fp_save_offset
= offset
- total_size
;
6746 cfun
->machine
->frame
.fp_sp_offset
= 0;
6747 cfun
->machine
->frame
.fp_save_offset
= 0;
6750 /* Ok, we're done. */
6754 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6755 pointer, argument pointer, or return address pointer. TO is either
6756 the stack pointer or hard frame pointer. */
6759 mips_initial_elimination_offset (from
, to
)
6764 /* Set OFFSET to the offset from the stack pointer. */
6767 case FRAME_POINTER_REGNUM
:
6771 case ARG_POINTER_REGNUM
:
6772 compute_frame_size (get_frame_size ());
6773 offset
= cfun
->machine
->frame
.total_size
;
6774 if (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
|| mips_abi
== ABI_MEABI
)
6775 offset
-= current_function_pretend_args_size
;
6778 case RETURN_ADDRESS_POINTER_REGNUM
:
6779 compute_frame_size (get_frame_size ());
6780 offset
= cfun
->machine
->frame
.gp_sp_offset
;
6781 if (BYTES_BIG_ENDIAN
)
6782 offset
+= UNITS_PER_WORD
- (POINTER_SIZE
/ BITS_PER_UNIT
);
6789 if (TARGET_MIPS16
&& to
== HARD_FRAME_POINTER_REGNUM
)
6790 offset
-= current_function_outgoing_args_size
;
6795 /* Common code to emit the insns (or to write the instructions to a file)
6796 to save/restore registers.
6798 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6799 is not modified within save_restore_insns. */
6801 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6803 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6804 and return an rtl expression for the register.
6806 This function is a subroutine of save_restore_insns. It is used when
6807 OFFSET is too large to add in a single instruction. */
6810 mips_add_large_offset_to_sp (offset
)
6811 HOST_WIDE_INT offset
;
6813 rtx reg
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6814 rtx offset_rtx
= GEN_INT (offset
);
6816 emit_move_insn (reg
, offset_rtx
);
6817 if (Pmode
== DImode
)
6818 emit_insn (gen_adddi3 (reg
, reg
, stack_pointer_rtx
));
6820 emit_insn (gen_addsi3 (reg
, reg
, stack_pointer_rtx
));
6824 /* Make INSN frame related and note that it performs the frame-related
6825 operation DWARF_PATTERN. */
6828 mips_annotate_frame_insn (insn
, dwarf_pattern
)
6829 rtx insn
, dwarf_pattern
;
6831 RTX_FRAME_RELATED_P (insn
) = 1;
6832 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
6837 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6838 The expression should only be used to store single registers. */
6841 mips_frame_set (mode
, regno
, offset
)
6842 enum machine_mode mode
;
6846 rtx address
= plus_constant (stack_pointer_rtx
, offset
);
6847 rtx set
= gen_rtx_SET (mode
,
6848 gen_rtx_MEM (mode
, address
),
6849 gen_rtx_REG (mode
, regno
));
6850 RTX_FRAME_RELATED_P (set
) = 1;
6855 /* Emit a move instruction that stores REG in MEM. Make the instruction
6856 frame related and note that it stores REG at (SP + OFFSET). This
6857 function may be asked to store an FPR pair. */
6860 mips_emit_frame_related_store (mem
, reg
, offset
)
6863 HOST_WIDE_INT offset
;
6867 if (GET_MODE (reg
) == DFmode
&& ! TARGET_FLOAT64
)
6869 /* Two registers are being stored, so the frame-related expression
6870 must be a PARALLEL rtx with one SET for each register. The
6871 higher numbered register is stored in the lower address on
6872 big-endian targets. */
6873 int regno1
= TARGET_BIG_ENDIAN
? REGNO (reg
) + 1 : REGNO (reg
);
6874 int regno2
= TARGET_BIG_ENDIAN
? REGNO (reg
) : REGNO (reg
) + 1;
6875 rtx set1
= mips_frame_set (SFmode
, regno1
, offset
);
6876 rtx set2
= mips_frame_set (SFmode
, regno2
, offset
+ UNITS_PER_FPREG
);
6877 dwarf_expr
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set1
, set2
));
6880 dwarf_expr
= mips_frame_set (GET_MODE (reg
), REGNO (reg
), offset
);
6882 mips_annotate_frame_insn (emit_move_insn (mem
, reg
), dwarf_expr
);
6886 save_restore_insns (store_p
, large_reg
, large_offset
)
6887 int store_p
; /* true if this is prologue */
6888 rtx large_reg
; /* register holding large offset constant or NULL */
6889 long large_offset
; /* large constant offset value */
6891 long mask
= cfun
->machine
->frame
.mask
;
6892 long fmask
= cfun
->machine
->frame
.fmask
;
6893 long real_mask
= mask
;
6896 HOST_WIDE_INT base_offset
;
6897 HOST_WIDE_INT gp_offset
;
6898 HOST_WIDE_INT fp_offset
;
6899 HOST_WIDE_INT end_offset
;
6902 if (frame_pointer_needed
6903 && ! BITSET_P (mask
, HARD_FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
6906 /* Do not restore GP under certain conditions. */
6909 && (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
6910 mask
&= ~(1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
));
6912 if (mask
== 0 && fmask
== 0)
6915 /* Save registers starting from high to low. The debuggers prefer at least
6916 the return register be stored at func+4, and also it allows us not to
6917 need a nop in the epilog if at least one register is reloaded in
6918 addition to return address. */
6920 /* Save GP registers if needed. */
6923 /* Pick which pointer to use as a base register. For small frames, just
6924 use the stack pointer. Otherwise, use a temporary register. Save 2
6925 cycles if the save area is near the end of a large frame, by reusing
6926 the constant created in the prologue/epilogue to adjust the stack
6929 gp_offset
= cfun
->machine
->frame
.gp_sp_offset
;
6931 = gp_offset
- (cfun
->machine
->frame
.gp_reg_size
6932 - GET_MODE_SIZE (gpr_mode
));
6934 if (gp_offset
< 0 || end_offset
< 0)
6936 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
6937 (long) gp_offset
, (long) end_offset
);
6939 /* If we see a large frame in mips16 mode, we save the registers
6940 before adjusting the stack pointer, and load them afterward. */
6941 else if (TARGET_MIPS16
&& large_offset
> 32767)
6942 base_reg_rtx
= stack_pointer_rtx
, base_offset
= large_offset
;
6944 else if (gp_offset
< 32768)
6945 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
6947 else if (large_reg
!= 0
6948 && (unsigned HOST_WIDE_INT
) (large_offset
- gp_offset
) < 32768
6949 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
6951 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
6952 base_offset
= large_offset
;
6953 if (Pmode
== DImode
)
6954 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
6955 stack_pointer_rtx
));
6957 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
6958 stack_pointer_rtx
));
6962 base_offset
= gp_offset
;
6963 base_reg_rtx
= mips_add_large_offset_to_sp (base_offset
);
6966 /* When we restore the registers in MIPS16 mode, then if we are
6967 using a frame pointer, and this is not a large frame, the
6968 current stack pointer will be offset by
6969 current_function_outgoing_args_size. Doing it this way lets
6970 us avoid offsetting the frame pointer before copying it into
6971 the stack pointer; there is no instruction to set the stack
6972 pointer to the sum of a register and a constant. */
6975 && frame_pointer_needed
6976 && large_offset
<= 32767)
6977 base_offset
+= current_function_outgoing_args_size
;
6979 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
6981 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
6985 = gen_rtx (MEM
, gpr_mode
,
6986 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
6987 GEN_INT (gp_offset
- base_offset
)));
6989 if (! current_function_calls_eh_return
)
6990 RTX_UNCHANGING_P (mem_rtx
) = 1;
6992 /* The mips16 does not have an instruction to load
6993 $31, so we load $7 instead, and work things out
6994 in mips_expand_epilogue. */
6995 if (TARGET_MIPS16
&& ! store_p
&& regno
== GP_REG_FIRST
+ 31)
6996 reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 7);
6997 /* The mips16 sometimes needs to save $18. */
6998 else if (TARGET_MIPS16
6999 && regno
!= GP_REG_FIRST
+ 31
7000 && ! M16_REG_P (regno
))
7003 reg_rtx
= gen_rtx (REG
, gpr_mode
, 6);
7006 reg_rtx
= gen_rtx (REG
, gpr_mode
, 3);
7007 emit_move_insn (reg_rtx
,
7008 gen_rtx (REG
, gpr_mode
, regno
));
7012 reg_rtx
= gen_rtx (REG
, gpr_mode
, regno
);
7015 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, gp_offset
);
7018 emit_move_insn (reg_rtx
, mem_rtx
);
7020 && regno
!= GP_REG_FIRST
+ 31
7021 && ! M16_REG_P (regno
))
7022 emit_move_insn (gen_rtx (REG
, gpr_mode
, regno
),
7026 /* If the restore is being supressed, still take into account
7027 the offset at which it is stored. */
7028 if (BITSET_P (real_mask
, regno
- GP_REG_FIRST
))
7029 gp_offset
-= GET_MODE_SIZE (gpr_mode
);
7033 base_reg_rtx
= 0, base_offset
= 0;
7035 /* Save floating point registers if needed. */
7038 /* Pick which pointer to use as a base register. */
7039 fp_offset
= cfun
->machine
->frame
.fp_sp_offset
;
7040 end_offset
= fp_offset
- (cfun
->machine
->frame
.fp_reg_size
7041 - UNITS_PER_FPVALUE
);
7043 if (fp_offset
< 0 || end_offset
< 0)
7045 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
7046 (long) fp_offset
, (long) end_offset
);
7048 else if (fp_offset
< 32768)
7049 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
7051 else if (base_reg_rtx
!= 0
7052 && (unsigned HOST_WIDE_INT
) (base_offset
- fp_offset
) < 32768
7053 && (unsigned HOST_WIDE_INT
) (base_offset
- end_offset
) < 32768)
7054 ; /* already set up for gp registers above */
7056 else if (large_reg
!= 0
7057 && (unsigned HOST_WIDE_INT
) (large_offset
- fp_offset
) < 32768
7058 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
7060 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
7061 base_offset
= large_offset
;
7062 if (Pmode
== DImode
)
7063 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
7064 stack_pointer_rtx
));
7066 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
7067 stack_pointer_rtx
));
7071 base_offset
= fp_offset
;
7072 base_reg_rtx
= mips_add_large_offset_to_sp (fp_offset
);
7075 /* This loop must iterate over the same space as its companion in
7076 compute_frame_size. */
7077 for (regno
= (FP_REG_LAST
- FP_INC
+ 1);
7078 regno
>= FP_REG_FIRST
;
7080 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
7082 enum machine_mode sz
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
7083 rtx reg_rtx
= gen_rtx (REG
, sz
, regno
);
7084 rtx mem_rtx
= gen_rtx (MEM
, sz
,
7085 gen_rtx (PLUS
, Pmode
, base_reg_rtx
,
7088 if (! current_function_calls_eh_return
)
7089 RTX_UNCHANGING_P (mem_rtx
) = 1;
7092 mips_emit_frame_related_store (mem_rtx
, reg_rtx
, fp_offset
);
7094 emit_move_insn (reg_rtx
, mem_rtx
);
7096 fp_offset
-= UNITS_PER_FPVALUE
;
7101 /* Set up the stack and frame (if desired) for the function. */
7104 mips_output_function_prologue (file
, size
)
7106 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
7108 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7111 HOST_WIDE_INT tsize
= cfun
->machine
->frame
.total_size
;
7113 /* ??? When is this really needed? At least the GNU assembler does not
7114 need the source filename more than once in the file, beyond what is
7115 emitted by the debug information. */
7117 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
7119 #ifdef SDB_DEBUGGING_INFO
7120 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
7121 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
7124 /* In mips16 mode, we may need to generate a 32 bit to handle
7125 floating point arguments. The linker will arrange for any 32 bit
7126 functions to call this stub, which will then jump to the 16 bit
7128 if (TARGET_MIPS16
&& !TARGET_SOFT_FLOAT
7129 && current_function_args_info
.fp_code
!= 0)
7130 build_mips16_function_stub (file
);
7132 inside_function
= 1;
7134 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7135 /* Get the function name the same way that toplev.c does before calling
7136 assemble_start_function. This is needed so that the name used here
7137 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7138 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7140 if (!flag_inhibit_size_directive
)
7142 fputs ("\t.ent\t", file
);
7143 assemble_name (file
, fnname
);
7147 assemble_name (file
, fnname
);
7148 fputs (":\n", file
);
7151 if (!flag_inhibit_size_directive
)
7153 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7155 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7156 (reg_names
[(frame_pointer_needed
)
7157 ? HARD_FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
7158 ((frame_pointer_needed
&& TARGET_MIPS16
)
7159 ? ((long) tsize
- current_function_outgoing_args_size
)
7161 reg_names
[GP_REG_FIRST
+ 31],
7162 cfun
->machine
->frame
.var_size
,
7163 cfun
->machine
->frame
.num_gp
,
7164 cfun
->machine
->frame
.num_fp
,
7165 current_function_outgoing_args_size
,
7166 cfun
->machine
->frame
.extra_size
);
7168 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7169 fprintf (file
, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7170 cfun
->machine
->frame
.mask
,
7171 cfun
->machine
->frame
.gp_save_offset
,
7172 cfun
->machine
->frame
.fmask
,
7173 cfun
->machine
->frame
.fp_save_offset
);
7176 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7177 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7180 if (mips_entry
&& ! mips_can_use_return_insn ())
7182 int save16
= BITSET_P (cfun
->machine
->frame
.mask
, 16);
7183 int save17
= BITSET_P (cfun
->machine
->frame
.mask
, 17);
7184 int save31
= BITSET_P (cfun
->machine
->frame
.mask
, 31);
7188 /* Look through the initial insns to see if any of them store
7189 the function parameters into the incoming parameter storage
7190 area. If they do, we delete the insn, and save the register
7191 using the entry pseudo-instruction instead. We don't try to
7192 look past a label, jump, or call. */
7193 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
7195 rtx note
, set
, src
, dest
, base
, offset
;
7198 if (GET_CODE (insn
) == CODE_LABEL
7199 || GET_CODE (insn
) == JUMP_INSN
7200 || GET_CODE (insn
) == CALL_INSN
)
7202 if (GET_CODE (insn
) != INSN
)
7204 set
= PATTERN (insn
);
7205 if (GET_CODE (set
) != SET
)
7208 /* An insn storing a function parameter will still have a
7209 REG_EQUIV note on it mentioning the argument pointer. */
7210 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
7211 if (note
== NULL_RTX
)
7213 if (! reg_mentioned_p (arg_pointer_rtx
, XEXP (note
, 0)))
7216 src
= SET_SRC (set
);
7217 if (GET_CODE (src
) != REG
7218 || REGNO (src
) < GP_REG_FIRST
+ 4
7219 || REGNO (src
) > GP_REG_FIRST
+ 7)
7222 dest
= SET_DEST (set
);
7223 if (GET_CODE (dest
) != MEM
)
7225 if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned) UNITS_PER_WORD
)
7227 else if (GET_MODE_SIZE (GET_MODE (dest
)) == (unsigned)2 * UNITS_PER_WORD
7228 && REGNO (src
) < GP_REG_FIRST
+ 7)
7232 offset
= const0_rtx
;
7233 base
= eliminate_constant_term (XEXP (dest
, 0), &offset
);
7234 if (GET_CODE (base
) != REG
7235 || GET_CODE (offset
) != CONST_INT
)
7237 if (REGNO (base
) == (unsigned) STACK_POINTER_REGNUM
7238 && INTVAL (offset
) == tsize
+ (REGNO (src
) - 4) * UNITS_PER_WORD
)
7240 else if (REGNO (base
) == (unsigned) HARD_FRAME_POINTER_REGNUM
7243 + (REGNO (src
) - 4) * UNITS_PER_WORD
7244 - current_function_outgoing_args_size
)))
7249 /* This insn stores a parameter onto the stack, in the same
7250 location where the entry pseudo-instruction will put it.
7251 Delete the insn, and arrange to tell the entry
7252 instruction to save the register. */
7253 PUT_CODE (insn
, NOTE
);
7254 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
7255 NOTE_SOURCE_FILE (insn
) = 0;
7257 hireg
= (REGNO (src
)
7258 + HARD_REGNO_NREGS (REGNO (src
), GET_MODE (dest
))
7260 if (hireg
> savearg
)
7264 /* If this is a varargs function, we need to save all the
7265 registers onto the stack anyhow. */
7266 if (current_function_stdarg
)
7267 savearg
= GP_REG_FIRST
+ 7;
7269 fprintf (file
, "\tentry\t");
7272 if (savearg
== GP_REG_FIRST
+ 4)
7273 fprintf (file
, "%s", reg_names
[savearg
]);
7275 fprintf (file
, "%s-%s", reg_names
[GP_REG_FIRST
+ 4],
7276 reg_names
[savearg
]);
7278 if (save16
|| save17
)
7281 fprintf (file
, ",");
7282 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 16]);
7284 fprintf (file
, "-%s", reg_names
[GP_REG_FIRST
+ 17]);
7288 if (savearg
> 0 || save16
|| save17
)
7289 fprintf (file
, ",");
7290 fprintf (file
, "%s", reg_names
[GP_REG_FIRST
+ 31]);
7292 fprintf (file
, "\n");
7295 if (TARGET_ABICALLS
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
))
7297 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7299 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7300 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
7303 fprintf (file
, "\t%s\t%s,%s,%ld\n",
7304 (Pmode
== DImode
? "dsubu" : "subu"),
7305 sp_str
, sp_str
, (long) tsize
);
7306 fprintf (file
, "\t.cprestore %ld\n", cfun
->machine
->frame
.args_size
);
7309 if (dwarf2out_do_frame ())
7310 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
7314 /* Expand the prologue into a bunch of separate insns. */
7317 mips_expand_prologue ()
7320 HOST_WIDE_INT tsize
;
7322 int last_arg_is_vararg_marker
= 0;
7323 tree fndecl
= current_function_decl
;
7324 tree fntype
= TREE_TYPE (fndecl
);
7325 tree fnargs
= DECL_ARGUMENTS (fndecl
);
7330 CUMULATIVE_ARGS args_so_far
;
7331 rtx reg_18_save
= NULL_RTX
;
7332 int store_args_on_stack
= (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
7333 && (! mips_entry
|| mips_can_use_return_insn ());
7335 /* If struct value address is treated as the first argument, make it so. */
7336 if (aggregate_value_p (DECL_RESULT (fndecl
))
7337 && ! current_function_returns_pcc_struct
7338 && struct_value_incoming_rtx
== 0)
7340 tree type
= build_pointer_type (fntype
);
7341 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
7343 DECL_ARG_TYPE (function_result_decl
) = type
;
7344 TREE_CHAIN (function_result_decl
) = fnargs
;
7345 fnargs
= function_result_decl
;
7348 /* For arguments passed in registers, find the register number
7349 of the first argument in the variable part of the argument list,
7350 otherwise GP_ARG_LAST+1. Note also if the last argument is
7351 the varargs special argument, and treat it as part of the
7354 This is only needed if store_args_on_stack is true. */
7356 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, NULL_RTX
, 0);
7357 regno
= GP_ARG_FIRST
;
7359 for (cur_arg
= fnargs
; cur_arg
!= 0; cur_arg
= next_arg
)
7361 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
7362 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
7365 if (TREE_ADDRESSABLE (passed_type
))
7367 passed_type
= build_pointer_type (passed_type
);
7368 passed_mode
= Pmode
;
7371 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
7373 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
7374 next_arg
= TREE_CHAIN (cur_arg
);
7376 if (entry_parm
&& store_args_on_stack
)
7379 && DECL_NAME (cur_arg
)
7380 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7381 "__builtin_va_alist"))
7382 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)),
7385 last_arg_is_vararg_marker
= 1;
7386 if (GET_CODE (entry_parm
) == REG
)
7387 regno
= REGNO (entry_parm
);
7389 regno
= GP_ARG_LAST
+ 1;
7396 if (GET_CODE (entry_parm
) != REG
)
7399 /* passed in a register, so will get homed automatically */
7400 if (GET_MODE (entry_parm
) == BLKmode
)
7401 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
7403 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
7405 regno
= REGNO (entry_parm
) + words
- 1;
7410 regno
= GP_ARG_LAST
+1;
7415 /* In order to pass small structures by value in registers compatibly with
7416 the MIPS compiler, we need to shift the value into the high part of the
7417 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7418 adjustments to be made as the next_arg_reg variable, so we split up the
7419 insns, and emit them separately. */
7421 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
7422 if (next_arg_reg
!= 0 && GET_CODE (next_arg_reg
) == PARALLEL
)
7424 rtvec adjust
= XVEC (next_arg_reg
, 0);
7425 int num
= GET_NUM_ELEM (adjust
);
7427 for (i
= 0; i
< num
; i
++)
7431 pattern
= RTVEC_ELT (adjust
, i
);
7432 if (GET_CODE (pattern
) != SET
7433 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
7434 abort_with_insn (pattern
, "insn is not a shift");
7435 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
7437 insn
= emit_insn (pattern
);
7439 /* Global life information isn't valid at this point, so we
7440 can't check whether these shifts are actually used. Mark
7441 them MAYBE_DEAD so that flow2 will remove them, and not
7442 complain about dead code in the prologue. */
7443 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, NULL_RTX
,
7448 tsize
= compute_frame_size (get_frame_size ());
7450 /* If this function is a varargs function, store any registers that
7451 would normally hold arguments ($4 - $7) on the stack. */
7452 if (store_args_on_stack
7453 && ((TYPE_ARG_TYPES (fntype
) != 0
7454 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
7456 || last_arg_is_vararg_marker
))
7458 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
7459 rtx ptr
= stack_pointer_rtx
;
7461 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7462 if (TARGET_ABICALLS
)
7465 for (; regno
<= GP_ARG_LAST
; regno
++)
7468 ptr
= gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
, GEN_INT (offset
));
7469 emit_move_insn (gen_rtx (MEM
, gpr_mode
, ptr
),
7470 gen_rtx (REG
, gpr_mode
, regno
));
7472 offset
+= GET_MODE_SIZE (gpr_mode
);
7476 /* If we are using the entry pseudo instruction, it will
7477 automatically subtract 32 from the stack pointer, so we don't
7478 need to. The entry pseudo instruction is emitted by
7479 function_prologue. */
7480 if (mips_entry
&& ! mips_can_use_return_insn ())
7482 if (tsize
> 0 && tsize
<= 32 && frame_pointer_needed
)
7486 /* If we are using a frame pointer with a small stack frame,
7487 we need to initialize it here since it won't be done
7489 if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7491 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7492 if (Pmode
== DImode
)
7493 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7497 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7501 else if (Pmode
== DImode
)
7502 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7503 stack_pointer_rtx
));
7505 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7506 stack_pointer_rtx
));
7508 RTX_FRAME_RELATED_P (insn
) = 1;
7511 /* We may need to save $18, if it is used to call a function
7512 which may return a floating point value. Set up a sequence
7513 of instructions to do so. Later on we emit them at the right
7515 if (TARGET_MIPS16
&& BITSET_P (cfun
->machine
->frame
.mask
, 18))
7517 rtx reg_rtx
= gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 3);
7518 long gp_offset
, base_offset
;
7520 gp_offset
= cfun
->machine
->frame
.gp_sp_offset
;
7521 if (BITSET_P (cfun
->machine
->frame
.mask
, 16))
7522 gp_offset
-= UNITS_PER_WORD
;
7523 if (BITSET_P (cfun
->machine
->frame
.mask
, 17))
7524 gp_offset
-= UNITS_PER_WORD
;
7525 if (BITSET_P (cfun
->machine
->frame
.mask
, 31))
7526 gp_offset
-= UNITS_PER_WORD
;
7528 base_offset
= tsize
;
7532 emit_move_insn (reg_rtx
,
7533 gen_rtx (REG
, gpr_mode
, GP_REG_FIRST
+ 18));
7534 emit_move_insn (gen_rtx (MEM
, gpr_mode
,
7535 gen_rtx (PLUS
, Pmode
, stack_pointer_rtx
,
7539 reg_18_save
= get_insns ();
7548 if (reg_18_save
!= NULL_RTX
)
7549 emit_insn (reg_18_save
);
7555 rtx tsize_rtx
= GEN_INT (tsize
);
7557 /* If we are doing svr4-abi, sp move is done by
7558 function_prologue. In mips16 mode with a large frame, we
7559 save the registers before adjusting the stack. */
7560 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7561 && (!TARGET_MIPS16
|| tsize
<= 32767))
7563 rtx adjustment_rtx
, insn
, dwarf_pattern
;
7567 adjustment_rtx
= gen_rtx (REG
, Pmode
, MIPS_TEMP1_REGNUM
);
7568 emit_move_insn (adjustment_rtx
, tsize_rtx
);
7571 adjustment_rtx
= tsize_rtx
;
7573 if (Pmode
== DImode
)
7574 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7577 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7580 dwarf_pattern
= gen_rtx_SET (Pmode
, stack_pointer_rtx
,
7581 plus_constant (stack_pointer_rtx
,
7584 mips_annotate_frame_insn (insn
, dwarf_pattern
);
7588 save_restore_insns (1, tmp_rtx
, tsize
);
7589 else if (reg_18_save
!= NULL_RTX
)
7590 emit_insn (reg_18_save
);
7592 if ((!TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7598 if (!frame_pointer_needed
)
7601 reg_rtx
= gen_rtx (REG
, Pmode
, 3);
7602 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
7603 emit_move_insn (reg_rtx
, tsize_rtx
);
7604 if (Pmode
== DImode
)
7605 emit_insn (gen_subdi3 (hard_frame_pointer_rtx
,
7606 hard_frame_pointer_rtx
,
7609 emit_insn (gen_subsi3 (hard_frame_pointer_rtx
,
7610 hard_frame_pointer_rtx
,
7612 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
7615 if (frame_pointer_needed
)
7619 /* On the mips16, we encourage the use of unextended
7620 instructions when using the frame pointer by pointing the
7621 frame pointer ahead of the argument space allocated on
7623 if ((! TARGET_ABICALLS
|| (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7627 /* In this case, we have already copied the stack
7628 pointer into the frame pointer, above. We need only
7629 adjust for the outgoing argument size. */
7630 if (current_function_outgoing_args_size
!= 0)
7632 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7633 if (Pmode
== DImode
)
7634 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7635 hard_frame_pointer_rtx
,
7638 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7639 hard_frame_pointer_rtx
,
7643 else if (TARGET_MIPS16
&& current_function_outgoing_args_size
!= 0)
7645 rtx incr
= GEN_INT (current_function_outgoing_args_size
);
7646 if (Pmode
== DImode
)
7647 insn
= emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7651 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7655 else if (Pmode
== DImode
)
7656 insn
= emit_insn (gen_movdi (hard_frame_pointer_rtx
,
7657 stack_pointer_rtx
));
7659 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
7660 stack_pointer_rtx
));
7663 RTX_FRAME_RELATED_P (insn
) = 1;
7666 if (TARGET_ABICALLS
&& (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
))
7667 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0),
7668 gen_rtx_REG (DImode
, 25)));
7671 /* If we are profiling, make sure no instructions are scheduled before
7672 the call to mcount. */
7674 if (current_function_profile
)
7675 emit_insn (gen_blockage ());
7678 /* Do any necessary cleanup after a function to restore stack, frame,
7681 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7682 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7685 mips_output_function_epilogue (file
, size
)
7686 FILE *file ATTRIBUTE_UNUSED
;
7687 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
7689 const char *fnname
= ""; /* FIXME: Correct initialisation? */
7691 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7692 /* Get the function name the same way that toplev.c does before calling
7693 assemble_start_function. This is needed so that the name used here
7694 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7695 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
7697 if (!flag_inhibit_size_directive
)
7699 fputs ("\t.end\t", file
);
7700 assemble_name (file
, fnname
);
7707 int num_gp_regs
= cfun
->machine
->frame
.gp_reg_size
/ 4;
7708 int num_fp_regs
= cfun
->machine
->frame
.fp_reg_size
/ 8;
7709 int num_regs
= num_gp_regs
+ num_fp_regs
;
7710 const char *name
= fnname
;
7715 dslots_load_total
+= num_regs
;
7718 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7719 name
, frame_pointer_needed
? 'y' : 'n',
7720 (cfun
->machine
->frame
.mask
& RA_MASK
) != 0 ? 'n' : 'y',
7721 current_function_calls_alloca
? 'y' : 'n',
7722 current_function_calls_setjmp
? 'y' : 'n',
7723 cfun
->machine
->frame
.total_size
,
7724 current_function_outgoing_args_size
, num_gp_regs
, num_fp_regs
,
7725 dslots_load_total
, dslots_load_filled
,
7726 dslots_jump_total
, dslots_jump_filled
,
7727 num_refs
[0], num_refs
[1], num_refs
[2]);
7729 fputc ('\n', stderr
);
7732 /* Reset state info for each function. */
7733 inside_function
= 0;
7734 ignore_line_number
= 0;
7735 dslots_load_total
= 0;
7736 dslots_jump_total
= 0;
7737 dslots_load_filled
= 0;
7738 dslots_jump_filled
= 0;
7745 while (string_constants
!= NULL
)
7747 struct string_constant
*next
;
7749 next
= string_constants
->next
;
7750 free (string_constants
);
7751 string_constants
= next
;
7754 /* Restore the output file if optimizing the GP (optimizing the GP causes
7755 the text to be diverted to a tempfile, so that data decls come before
7756 references to the data). */
7757 if (TARGET_FILE_SWITCHING
)
7759 asm_out_file
= asm_out_data_file
;
7764 /* Expand the epilogue into a bunch of separate insns. */
7767 mips_expand_epilogue ()
7769 HOST_WIDE_INT tsize
= cfun
->machine
->frame
.total_size
;
7770 rtx tsize_rtx
= GEN_INT (tsize
);
7771 rtx tmp_rtx
= (rtx
)0;
7773 if (mips_can_use_return_insn ())
7775 emit_jump_insn (gen_return ());
7779 if (mips_entry
&& ! mips_can_use_return_insn ())
7782 if (tsize
> 32767 && ! TARGET_MIPS16
)
7784 tmp_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP1_REGNUM
);
7785 emit_move_insn (tmp_rtx
, tsize_rtx
);
7786 tsize_rtx
= tmp_rtx
;
7791 long orig_tsize
= tsize
;
7793 if (frame_pointer_needed
)
7795 emit_insn (gen_blockage ());
7797 /* On the mips16, the frame pointer is offset from the stack
7798 pointer by current_function_outgoing_args_size. We
7799 account for that by changing tsize. Note that this can
7800 actually make tsize negative. */
7803 tsize
-= current_function_outgoing_args_size
;
7805 /* If we have a large frame, it's easier to add to $6
7806 than to $sp, since the mips16 has no instruction to
7807 add a register to $sp. */
7808 if (orig_tsize
> 32767)
7810 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
7812 emit_move_insn (g6_rtx
, GEN_INT (tsize
));
7813 if (Pmode
== DImode
)
7814 emit_insn (gen_adddi3 (hard_frame_pointer_rtx
,
7815 hard_frame_pointer_rtx
,
7818 emit_insn (gen_addsi3 (hard_frame_pointer_rtx
,
7819 hard_frame_pointer_rtx
,
7824 if (tsize
&& tsize
!= orig_tsize
)
7825 tsize_rtx
= GEN_INT (tsize
);
7828 if (Pmode
== DImode
)
7829 emit_insn (gen_movdi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7831 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
7834 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7835 are going to restore it, then we must emit a blockage insn to
7836 prevent the scheduler from moving the restore out of the epilogue. */
7837 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
7838 && (cfun
->machine
->frame
.mask
7839 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
7840 emit_insn (gen_blockage ());
7842 save_restore_insns (0, tmp_rtx
, orig_tsize
);
7844 /* In mips16 mode with a large frame, we adjust the stack
7845 pointer before restoring the registers. In this case, we
7846 should always be using a frame pointer, so everything should
7847 have been handled above. */
7848 if (tsize
> 32767 && TARGET_MIPS16
)
7851 if (current_function_calls_eh_return
)
7853 rtx eh_ofs
= EH_RETURN_STACKADJ_RTX
;
7854 if (Pmode
== DImode
)
7855 emit_insn (gen_adddi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
7857 emit_insn (gen_addsi3 (eh_ofs
, eh_ofs
, tsize_rtx
));
7861 emit_insn (gen_blockage ());
7863 if (tsize
!= 0 || current_function_calls_eh_return
)
7867 if (Pmode
== DImode
)
7868 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7871 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
7876 /* We need to work around not being able to add a register
7877 to the stack pointer directly. Use register $6 as an
7878 intermediate step. */
7880 rtx g6_rtx
= gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 6);
7882 if (Pmode
== DImode
)
7884 emit_insn (gen_movdi (g6_rtx
, stack_pointer_rtx
));
7885 emit_insn (gen_adddi3 (g6_rtx
, g6_rtx
, tsize_rtx
));
7886 emit_insn (gen_movdi (stack_pointer_rtx
, g6_rtx
));
7890 emit_insn (gen_movsi (g6_rtx
, stack_pointer_rtx
));
7891 emit_insn (gen_addsi3 (g6_rtx
, g6_rtx
, tsize_rtx
));
7892 emit_insn (gen_movsi (stack_pointer_rtx
, g6_rtx
));
7899 /* The mips16 loads the return address into $7, not $31. */
7900 if (TARGET_MIPS16
&& (cfun
->machine
->frame
.mask
& RA_MASK
) != 0)
7901 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7902 GP_REG_FIRST
+ 7)));
7904 emit_jump_insn (gen_return_internal (gen_rtx (REG
, Pmode
,
7905 GP_REG_FIRST
+ 31)));
7908 /* Return nonzero if this function is known to have a null epilogue.
7909 This allows the optimizer to omit jumps to jumps if no stack
7913 mips_can_use_return_insn ()
7917 if (! reload_completed
)
7920 if (regs_ever_live
[31] || current_function_profile
)
7923 return_type
= DECL_RESULT (current_function_decl
);
7925 /* In mips16 mode, a function which returns a floating point value
7926 needs to arrange to copy the return value into the floating point
7929 && mips16_hard_float
7930 && ! aggregate_value_p (return_type
)
7931 && GET_MODE_CLASS (DECL_MODE (return_type
)) == MODE_FLOAT
7932 && GET_MODE_SIZE (DECL_MODE (return_type
)) <= UNITS_PER_FPVALUE
)
7935 if (cfun
->machine
->frame
.initialized
)
7936 return cfun
->machine
->frame
.total_size
== 0;
7938 return compute_frame_size (get_frame_size ()) == 0;
7941 /* Returns non-zero if X contains a SYMBOL_REF. */
7944 symbolic_expression_p (x
)
7947 if (GET_CODE (x
) == SYMBOL_REF
)
7950 if (GET_CODE (x
) == CONST
)
7951 return symbolic_expression_p (XEXP (x
, 0));
7953 if (GET_RTX_CLASS (GET_CODE (x
)) == '1')
7954 return symbolic_expression_p (XEXP (x
, 0));
7956 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
7957 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
7958 return (symbolic_expression_p (XEXP (x
, 0))
7959 || symbolic_expression_p (XEXP (x
, 1)));
7964 /* Choose the section to use for the constant rtx expression X that has
7968 mips_select_rtx_section (mode
, x
, align
)
7969 enum machine_mode mode
;
7971 unsigned HOST_WIDE_INT align
;
7975 /* In mips16 mode, the constant table always goes in the same section
7976 as the function, so that constants can be loaded using PC relative
7978 function_section (current_function_decl
);
7980 else if (TARGET_EMBEDDED_DATA
)
7982 /* For embedded applications, always put constants in read-only data,
7983 in order to reduce RAM usage. */
7984 mergeable_constant_section (mode
, align
, 0);
7988 /* For hosted applications, always put constants in small data if
7989 possible, as this gives the best performance. */
7990 /* ??? Consider using mergable small data sections. */
7992 if (GET_MODE_SIZE (mode
) <= (unsigned) mips_section_threshold
7993 && mips_section_threshold
> 0)
7994 SMALL_DATA_SECTION ();
7995 else if (flag_pic
&& symbolic_expression_p (x
))
7997 if (targetm
.have_named_sections
)
7998 named_section (NULL_TREE
, ".data.rel.ro", 3);
8003 mergeable_constant_section (mode
, align
, 0);
8007 /* Choose the section to use for DECL. RELOC is true if its value contains
8008 any relocatable expression.
8010 Some of the logic used here needs to be replicated in
8011 mips_encode_section_info so that references to these symbols are
8012 done correctly. Specifically, at least all symbols assigned here
8013 to rom (.text and/or .rodata) must not be referenced via
8014 mips_encode_section_info with %gprel, as the rom might be too far
8017 If you need to make a change here, you probably should check
8018 mips_encode_section_info to see if it needs a similar change.
8020 ??? This would be fixed by implementing targetm.is_small_data_p. */
8023 mips_select_section (decl
, reloc
, align
)
8026 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
;
8028 int size
= int_size_in_bytes (TREE_TYPE (decl
));
8030 if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
8031 && TREE_CODE (decl
) == STRING_CST
8032 && !flag_writable_strings
)
8033 /* For embedded position independent code, put constant strings in the
8034 text section, because the data section is limited to 64K in size.
8035 For mips16 code, put strings in the text section so that a PC
8036 relative load instruction can be used to get their address. */
8038 else if (TARGET_EMBEDDED_DATA
)
8040 /* For embedded applications, always put an object in read-only data
8041 if possible, in order to reduce RAM usage. */
8043 if (((TREE_CODE (decl
) == VAR_DECL
8044 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
8045 && DECL_INITIAL (decl
)
8046 && (DECL_INITIAL (decl
) == error_mark_node
8047 || TREE_CONSTANT (DECL_INITIAL (decl
))))
8048 /* Deal with calls from output_constant_def_contents. */
8049 || (TREE_CODE (decl
) != VAR_DECL
8050 && (TREE_CODE (decl
) != STRING_CST
8051 || !flag_writable_strings
)))
8052 && ! (flag_pic
&& reloc
))
8053 readonly_data_section ();
8054 else if (size
> 0 && size
<= mips_section_threshold
)
8055 SMALL_DATA_SECTION ();
8061 /* For hosted applications, always put an object in small data if
8062 possible, as this gives the best performance. */
8064 if (size
> 0 && size
<= mips_section_threshold
)
8065 SMALL_DATA_SECTION ();
8066 else if (((TREE_CODE (decl
) == VAR_DECL
8067 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
8068 && DECL_INITIAL (decl
)
8069 && (DECL_INITIAL (decl
) == error_mark_node
8070 || TREE_CONSTANT (DECL_INITIAL (decl
))))
8071 /* Deal with calls from output_constant_def_contents. */
8072 || (TREE_CODE (decl
) != VAR_DECL
8073 && (TREE_CODE (decl
) != STRING_CST
8074 || !flag_writable_strings
)))
8075 && ! (flag_pic
&& reloc
))
8076 readonly_data_section ();
8082 /* When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
8085 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
8086 symbols which are not in the .text section.
8088 When generating mips16 code, SYMBOL_REF_FLAG is set for string
8089 constants which are put in the .text section. We also record the
8090 total length of all such strings; this total is used to decide
8091 whether we need to split the constant table, and need not be
8094 When not mips16 code nor embedded PIC, if a symbol is in a
8095 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
8096 splitting the reference so that gas can generate a gp relative
8099 When TARGET_EMBEDDED_DATA is set, we assume that all const
8100 variables will be stored in ROM, which is too far from %gp to use
8101 %gprel addressing. Note that (1) we include "extern const"
8102 variables in this, which mips_select_section doesn't, and (2) we
8103 can't always tell if they're really const (they might be const C++
8104 objects with non-const constructors), so we err on the side of
8105 caution and won't use %gprel anyway (otherwise we'd have to defer
8106 this decision to the linker/loader). The handling of extern consts
8107 is why the DECL_INITIAL macros differ from mips_select_section. */
8110 mips_encode_section_info (decl
, first
)
8116 if (first
&& TREE_CODE (decl
) == STRING_CST
8117 && ! flag_writable_strings
8118 /* If this string is from a function, and the function will
8119 go in a gnu linkonce section, then we can't directly
8120 access the string. This gets an assembler error
8121 "unsupported PC relative reference to different section".
8122 If we modify SELECT_SECTION to put it in function_section
8123 instead of text_section, it still fails because
8124 DECL_SECTION_NAME isn't set until assemble_start_function.
8125 If we fix that, it still fails because strings are shared
8126 among multiple functions, and we have cross section
8127 references again. We force it to work by putting string
8128 addresses in the constant pool and indirecting. */
8129 && (! current_function_decl
8130 || ! DECL_ONE_ONLY (current_function_decl
)))
8132 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl
), 0)) = 1;
8133 mips_string_length
+= TREE_STRING_LENGTH (decl
);
8137 if (TARGET_EMBEDDED_DATA
8138 && (TREE_CODE (decl
) == VAR_DECL
8139 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
))
8140 && (!DECL_INITIAL (decl
)
8141 || TREE_CONSTANT (DECL_INITIAL (decl
))))
8143 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 0;
8146 else if (TARGET_EMBEDDED_PIC
)
8148 if (TREE_CODE (decl
) == VAR_DECL
)
8149 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
8150 else if (TREE_CODE (decl
) == FUNCTION_DECL
)
8151 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 0;
8152 else if (TREE_CODE (decl
) == STRING_CST
8153 && ! flag_writable_strings
)
8154 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl
), 0)) = 0;
8156 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl
), 0)) = 1;
8159 else if (TREE_CODE (decl
) == VAR_DECL
8160 && DECL_SECTION_NAME (decl
) != NULL_TREE
8161 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
8163 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl
)),
8166 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
8169 /* We can not perform GP optimizations on variables which are in
8170 specific sections, except for .sdata and .sbss which are
8172 else if (TARGET_GP_OPT
&& TREE_CODE (decl
) == VAR_DECL
8173 && DECL_SECTION_NAME (decl
) == NULL_TREE
8174 && ! (TARGET_MIPS16
&& TREE_PUBLIC (decl
)
8175 && (DECL_COMMON (decl
)
8176 || DECL_ONE_ONLY (decl
)
8177 || DECL_WEAK (decl
))))
8179 int size
= int_size_in_bytes (TREE_TYPE (decl
));
8181 if (size
> 0 && size
<= mips_section_threshold
)
8182 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
8187 /* Return register to use for a function return value with VALTYPE for
8188 function FUNC. MODE is used instead of VALTYPE for LIBCALLs. */
8191 mips_function_value (valtype
, func
, mode
)
8193 tree func ATTRIBUTE_UNUSED
;
8194 enum machine_mode mode
;
8196 int reg
= GP_RETURN
;
8197 enum mode_class mclass
;
8202 mode
= TYPE_MODE (valtype
);
8203 unsignedp
= TREE_UNSIGNED (valtype
);
8205 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
8206 the mode just as PROMOTE_MODE does. */
8207 mode
= promote_mode (valtype
, mode
, &unsignedp
, 1);
8209 mclass
= GET_MODE_CLASS (mode
);
8211 if (mclass
== MODE_FLOAT
&& GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
)
8214 else if (mclass
== MODE_COMPLEX_FLOAT
8215 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
* 2)
8217 enum machine_mode cmode
= GET_MODE_INNER (mode
);
8219 return gen_rtx_PARALLEL
8222 gen_rtx_EXPR_LIST (VOIDmode
,
8223 gen_rtx_REG (cmode
, FP_RETURN
),
8225 gen_rtx_EXPR_LIST (VOIDmode
,
8226 gen_rtx_REG (cmode
, FP_RETURN
+ FP_INC
),
8227 GEN_INT (GET_MODE_SIZE (cmode
)))));
8230 else if (valtype
&& TREE_CODE (valtype
) == RECORD_TYPE
8231 && mips_abi
!= ABI_32
8232 && mips_abi
!= ABI_O64
8233 && mips_abi
!= ABI_EABI
)
8235 /* A struct with only one or two floating point fields is returned in
8236 the floating point registers. */
8237 tree field
, fields
[2];
8240 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
8241 field
= TREE_CHAIN (field
))
8243 if (TREE_CODE (field
) != FIELD_DECL
)
8246 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
8249 fields
[i
++] = field
;
8252 /* Must check i, so that we reject structures with no elements. */
8257 /* The structure has DImode, but we don't allow DImode values
8258 in FP registers, so we use a PARALLEL even though it isn't
8259 strictly necessary. */
8260 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
8262 return gen_rtx_PARALLEL
8265 gen_rtx_EXPR_LIST (VOIDmode
,
8266 gen_rtx_REG (field_mode
,
8273 enum machine_mode first_mode
8274 = TYPE_MODE (TREE_TYPE (fields
[0]));
8275 enum machine_mode second_mode
8276 = TYPE_MODE (TREE_TYPE (fields
[1]));
8277 HOST_WIDE_INT first_offset
= int_byte_position (fields
[0]);
8278 HOST_WIDE_INT second_offset
= int_byte_position (fields
[1]);
8280 return gen_rtx_PARALLEL
8283 gen_rtx_EXPR_LIST (VOIDmode
,
8284 gen_rtx_REG (first_mode
,
8286 GEN_INT (first_offset
)),
8287 gen_rtx_EXPR_LIST (VOIDmode
,
8288 gen_rtx_REG (second_mode
,
8290 GEN_INT (second_offset
))));
8295 return gen_rtx_REG (mode
, reg
);
8298 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8299 nonzero when an argument must be passed by reference. */
8302 function_arg_pass_by_reference (cum
, mode
, type
, named
)
8303 const CUMULATIVE_ARGS
*cum
;
8304 enum machine_mode mode
;
8306 int named ATTRIBUTE_UNUSED
;
8310 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
8313 /* We must pass by reference if we would be both passing in registers
8314 and the stack. This is because any subsequent partial arg would be
8315 handled incorrectly in this case.
8317 ??? This is really a kludge. We should either fix GCC so that such
8318 a situation causes an abort and then do something in the MIPS port
8319 to prevent it, or add code to function.c to properly handle the case. */
8320 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8321 here hopefully is not relevant to mips_va_arg. */
8322 if (cum
&& MUST_PASS_IN_STACK (mode
, type
)
8323 && mips_abi
!= ABI_MEABI
8324 && FUNCTION_ARG (*cum
, mode
, type
, named
) != 0)
8327 /* Otherwise, we only do this if EABI is selected. */
8328 if (mips_abi
!= ABI_EABI
)
8331 /* ??? How should SCmode be handled? */
8332 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
8335 size
= int_size_in_bytes (type
);
8336 return size
== -1 || size
> UNITS_PER_WORD
;
8339 /* This function returns the register class required for a secondary
8340 register when copying between one of the registers in CLASS, and X,
8341 using MODE. If IN_P is nonzero, the copy is going from X to the
8342 register, otherwise the register is the source. A return value of
8343 NO_REGS means that no secondary register is required. */
8346 mips_secondary_reload_class (class, mode
, x
, in_p
)
8347 enum reg_class
class;
8348 enum machine_mode mode
;
8352 enum reg_class gr_regs
= TARGET_MIPS16
? M16_REGS
: GR_REGS
;
8356 if (GET_CODE (x
) == SIGN_EXTEND
)
8362 /* We may be called with reg_renumber NULL from regclass.
8363 ??? This is probably a bug. */
8365 regno
= true_regnum (x
);
8368 while (GET_CODE (x
) == SUBREG
)
8370 off
+= subreg_regno_offset (REGNO (SUBREG_REG (x
)),
8371 GET_MODE (SUBREG_REG (x
)),
8377 if (GET_CODE (x
) == REG
)
8378 regno
= REGNO (x
) + off
;
8381 /* 64-bit floating-point registers don't store 32-bit values
8382 in sign-extended form. The only way we can reload
8383 (sign_extend:DI (reg:SI $f0)) is by moving $f0 into
8384 an integer register using a 32-bit move. */
8385 if (FP_REG_P (regno
))
8386 return (class == GR_REGS
? NO_REGS
: GR_REGS
);
8388 /* For the same reason, we can only reload (sign_extend:DI FOO) into
8389 a floating-point register when FOO is an integer register. */
8390 if (class == FP_REGS
)
8391 return (GP_REG_P (regno
) ? NO_REGS
: GR_REGS
);
8394 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
8395 regno
= true_regnum (x
);
8397 gp_reg_p
= TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
8399 /* We always require a general register when copying anything to
8400 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8401 to a general register, or when copying from register 0. */
8402 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
8405 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8406 ? NO_REGS
: gr_regs
);
8407 else if (regno
== HILO_REGNUM
)
8410 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
8411 ? NO_REGS
: gr_regs
);
8413 /* Copying from HI or LO to anywhere other than a general register
8414 requires a general register. */
8415 if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
8417 if (TARGET_MIPS16
&& in_p
)
8419 /* We can't really copy to HI or LO at all in mips16 mode. */
8422 return gp_reg_p
? NO_REGS
: gr_regs
;
8424 if (MD_REG_P (regno
))
8426 if (TARGET_MIPS16
&& ! in_p
)
8428 /* We can't really copy to HI or LO at all in mips16 mode. */
8431 return class == gr_regs
? NO_REGS
: gr_regs
;
8434 /* We can only copy a value to a condition code register from a
8435 floating point register, and even then we require a scratch
8436 floating point register. We can only copy a value out of a
8437 condition code register into a general register. */
8438 if (class == ST_REGS
)
8442 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
8444 if (ST_REG_P (regno
))
8448 return class == GR_REGS
? NO_REGS
: GR_REGS
;
8451 if (class == FP_REGS
)
8453 if (GET_CODE (x
) == MEM
)
8455 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8458 else if (CONSTANT_P (x
) && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
8460 /* We can use the l.s and l.d macros to load floating-point
8461 constants. ??? For l.s, we could probably get better
8462 code by returning GR_REGS here. */
8465 else if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
8467 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8470 else if (FP_REG_P (regno
))
8472 /* In this case we can use mov.s or mov.d. */
8477 /* Otherwise, we need to reload through an integer register. */
8482 /* In mips16 mode, going between memory and anything but M16_REGS
8483 requires an M16_REG. */
8486 if (class != M16_REGS
&& class != M16_NA_REGS
)
8494 /* The stack pointer isn't a valid operand to an add instruction,
8495 so we need to load it into M16_REGS first. This can happen as
8496 a result of register elimination and form_sum converting
8497 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8498 need an extra register if the dest is the same as the other
8499 register. In that case, we can't fix the problem by loading SP
8500 into the dest first. */
8501 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == REG
8502 && GET_CODE (XEXP (x
, 1)) == REG
8503 && (XEXP (x
, 0) == stack_pointer_rtx
8504 || XEXP (x
, 1) == stack_pointer_rtx
))
8505 return (class == M16_REGS
? M16_NA_REGS
: M16_REGS
);
8507 if (class == M16_REGS
|| class == M16_NA_REGS
)
8516 /* This function returns the maximum number of consecutive registers
8517 needed to represent mode MODE in registers of class CLASS. */
8520 mips_class_max_nregs (class, mode
)
8521 enum reg_class
class;
8522 enum machine_mode mode
;
8524 if (class == FP_REGS
)
8527 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8530 /* For each mips16 function which refers to GP relative symbols, we
8531 use a pseudo register, initialized at the start of the function, to
8532 hold the $gp value. */
8535 mips16_gp_pseudo_reg ()
8537 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
8542 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
8543 RTX_UNCHANGING_P (cfun
->machine
->mips16_gp_pseudo_rtx
) = 1;
8545 /* We want to initialize this to a value which gcc will believe
8547 const_gp
= gen_rtx (CONST
, Pmode
,
8548 gen_rtx (REG
, Pmode
, GP_REG_FIRST
+ 28));
8551 emit_move_insn (cfun
->machine
->mips16_gp_pseudo_rtx
,
8553 insn
= get_insns ();
8556 push_topmost_sequence ();
8557 /* We need to emit the initialization after the FUNCTION_BEG
8558 note, so that it will be integrated. */
8559 for (scan
= get_insns (); scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
8560 if (GET_CODE (scan
) == NOTE
8561 && NOTE_LINE_NUMBER (scan
) == NOTE_INSN_FUNCTION_BEG
)
8563 if (scan
== NULL_RTX
)
8564 scan
= get_insns ();
8565 insn
= emit_insn_after (insn
, scan
);
8566 pop_topmost_sequence ();
8569 return cfun
->machine
->mips16_gp_pseudo_rtx
;
8572 /* Return an RTX which represents the signed 16 bit offset from the
8573 $gp register for the given symbol. This is only used on the
8577 mips16_gp_offset (sym
)
8582 if (GET_CODE (sym
) != SYMBOL_REF
8583 || ! SYMBOL_REF_FLAG (sym
))
8586 /* We use a special identifier to represent the value of the gp
8588 gp
= get_identifier ("__mips16_gp_value");
8590 return gen_rtx (CONST
, Pmode
,
8591 gen_rtx (MINUS
, Pmode
, sym
,
8592 gen_rtx (SYMBOL_REF
, Pmode
,
8593 IDENTIFIER_POINTER (gp
))));
8596 /* Return nonzero if the given RTX represents a signed 16 bit offset
8597 from the $gp register. */
8600 mips16_gp_offset_p (x
)
8603 if (GET_CODE (x
) == CONST
)
8606 /* It's OK to add a small integer value to a gp offset. */
8607 if (GET_CODE (x
) == PLUS
)
8609 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8610 && SMALL_INT (XEXP (x
, 1)))
8611 return mips16_gp_offset_p (XEXP (x
, 0));
8612 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
8613 && SMALL_INT (XEXP (x
, 0)))
8614 return mips16_gp_offset_p (XEXP (x
, 1));
8618 /* Make sure it is in the form SYM - __mips16_gp_value. */
8619 return (GET_CODE (x
) == MINUS
8620 && GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
8621 && SYMBOL_REF_FLAG (XEXP (x
, 0))
8622 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
8623 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0);
8626 /* Output a GP offset. We don't want to print the subtraction of
8627 __mips16_gp_value; it is implicitly represented by the %gprel which
8628 should have been printed by the caller. */
8631 mips16_output_gp_offset (file
, x
)
8635 if (GET_CODE (x
) == CONST
)
8638 if (GET_CODE (x
) == PLUS
)
8640 mips16_output_gp_offset (file
, XEXP (x
, 0));
8642 mips16_output_gp_offset (file
, XEXP (x
, 1));
8646 if (GET_CODE (x
) == MINUS
8647 && GET_CODE (XEXP (x
, 1)) == SYMBOL_REF
8648 && strcmp (XSTR (XEXP (x
, 1), 0), "__mips16_gp_value") == 0)
8650 mips16_output_gp_offset (file
, XEXP (x
, 0));
8654 output_addr_const (file
, x
);
8657 /* Return nonzero if a constant should not be output until after the
8658 function. This is true of most string constants, so that we can
8659 use a more efficient PC relative reference. However, a static
8660 inline function may never call assemble_function_end to write out
8661 the constant pool, so don't try to postpone the constant in that
8664 ??? It's really a bug that a static inline function can put stuff
8665 in the constant pool even if the function itself is not output.
8667 We record which string constants we've seen, so that we know which
8668 ones might use the more efficient reference. */
8671 mips16_constant_after_function_p (x
)
8674 if (TREE_CODE (x
) == STRING_CST
8675 && ! flag_writable_strings
8676 && current_function_decl
!= 0
8677 && ! DECL_DEFER_OUTPUT (current_function_decl
)
8678 && ! (DECL_INLINE (current_function_decl
)
8679 && ((! TREE_PUBLIC (current_function_decl
)
8680 && ! TREE_ADDRESSABLE (current_function_decl
)
8681 && ! flag_keep_inline_functions
)
8682 || DECL_EXTERNAL (current_function_decl
))))
8684 struct string_constant
*n
;
8686 n
= (struct string_constant
*) xmalloc (sizeof *n
);
8687 n
->label
= XSTR (XEXP (TREE_CST_RTL (x
), 0), 0);
8688 n
->next
= string_constants
;
8689 string_constants
= n
;
8697 /* Validate a constant for the mips16. This rejects general symbolic
8698 addresses, which must be loaded from memory. If ADDR is nonzero,
8699 this should reject anything which is not a legal address. If
8700 ADDEND is nonzero, this is being added to something else. */
8703 mips16_constant (x
, mode
, addr
, addend
)
8705 enum machine_mode mode
;
8709 while (GET_CODE (x
) == CONST
)
8712 switch (GET_CODE (x
))
8718 return (mips16_constant (XEXP (x
, 0), mode
, addr
, 1)
8719 && mips16_constant (XEXP (x
, 1), mode
, addr
, 1));
8722 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
8724 if (CONSTANT_POOL_ADDRESS_P (x
))
8727 /* If we aren't looking for a memory address, we can accept a GP
8728 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8729 knows how to handle this. We can always accept a string
8730 constant, which is the other case in which SYMBOL_REF_FLAG
8734 && SYMBOL_REF_FLAG (x
)
8735 && mode
== (enum machine_mode
) Pmode
)
8738 /* We can accept a string constant, which will have
8739 SYMBOL_REF_FLAG set but must be recognized by name to
8740 distinguish from a GP accessible symbol. The name of a
8741 string constant will have been generated by
8742 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8743 if (SYMBOL_REF_FLAG (x
))
8745 const char *name
= XSTR (x
, 0);
8747 return (name
[0] == '*'
8748 && strncmp (name
+ 1, LOCAL_LABEL_PREFIX
,
8749 sizeof LOCAL_LABEL_PREFIX
- 1) == 0);
8755 if (addr
&& GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)
8760 if (addr
&& ! addend
)
8762 return INTVAL (x
) > - 0x10000 && INTVAL (x
) <= 0xffff;
8765 /* We need to treat $gp as a legitimate constant, because
8766 mips16_gp_pseudo_reg assumes that. */
8767 return REGNO (x
) == GP_REG_FIRST
+ 28;
8771 /* Write out code to move floating point arguments in or out of
8772 general registers. Output the instructions to FILE. FP_CODE is
8773 the code describing which arguments are present (see the comment at
8774 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8775 we are copying from the floating point registers. */
8778 mips16_fp_args (file
, fp_code
, from_fp_p
)
8787 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8788 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8795 gparg
= GP_ARG_FIRST
;
8796 fparg
= FP_ARG_FIRST
;
8797 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
8801 if ((fparg
& 1) != 0)
8803 fprintf (file
, "\t%s\t%s,%s\n", s
,
8804 reg_names
[gparg
], reg_names
[fparg
]);
8806 else if ((f
& 3) == 2)
8809 fprintf (file
, "\td%s\t%s,%s\n", s
,
8810 reg_names
[gparg
], reg_names
[fparg
]);
8813 if ((fparg
& 1) != 0)
8815 if (TARGET_BIG_ENDIAN
)
8816 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
8817 reg_names
[gparg
], reg_names
[fparg
+ 1], s
,
8818 reg_names
[gparg
+ 1], reg_names
[fparg
]);
8820 fprintf (file
, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s
,
8821 reg_names
[gparg
], reg_names
[fparg
], s
,
8822 reg_names
[gparg
+ 1], reg_names
[fparg
+ 1]);
8835 /* Build a mips16 function stub. This is used for functions which
8836 take aruments in the floating point registers. It is 32 bit code
8837 that moves the floating point args into the general registers, and
8838 then jumps to the 16 bit code. */
8841 build_mips16_function_stub (file
)
8845 char *secname
, *stubname
;
8846 tree stubid
, stubdecl
;
8850 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8851 secname
= (char *) alloca (strlen (fnname
) + 20);
8852 sprintf (secname
, ".mips16.fn.%s", fnname
);
8853 stubname
= (char *) alloca (strlen (fnname
) + 20);
8854 sprintf (stubname
, "__fn_stub_%s", fnname
);
8855 stubid
= get_identifier (stubname
);
8856 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
8857 build_function_type (void_type_node
, NULL_TREE
));
8858 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
8860 fprintf (file
, "\t# Stub function for %s (", current_function_name
);
8862 for (f
= (unsigned int) current_function_args_info
.fp_code
; f
!= 0; f
>>= 2)
8864 fprintf (file
, "%s%s",
8865 need_comma
? ", " : "",
8866 (f
& 3) == 1 ? "float" : "double");
8869 fprintf (file
, ")\n");
8871 fprintf (file
, "\t.set\tnomips16\n");
8872 function_section (stubdecl
);
8873 ASM_OUTPUT_ALIGN (file
, floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
8875 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8876 within a .ent, and we can not emit another .ent. */
8877 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8878 fputs ("\t.ent\t", file
);
8879 assemble_name (file
, stubname
);
8883 assemble_name (file
, stubname
);
8884 fputs (":\n", file
);
8886 /* We don't want the assembler to insert any nops here. */
8887 fprintf (file
, "\t.set\tnoreorder\n");
8889 mips16_fp_args (file
, current_function_args_info
.fp_code
, 1);
8891 fprintf (asm_out_file
, "\t.set\tnoat\n");
8892 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
8893 assemble_name (file
, fnname
);
8894 fprintf (file
, "\n");
8895 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
8896 fprintf (asm_out_file
, "\t.set\tat\n");
8898 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8899 with one of the mfc1 instructions, because the result is not
8900 available for one instruction, so if the very first instruction
8901 in the function refers to the register, it will see the wrong
8903 fprintf (file
, "\tnop\n");
8905 fprintf (file
, "\t.set\treorder\n");
8907 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8908 fputs ("\t.end\t", file
);
8909 assemble_name (file
, stubname
);
8913 fprintf (file
, "\t.set\tmips16\n");
8915 function_section (current_function_decl
);
8918 /* We keep a list of functions for which we have already built stubs
8919 in build_mips16_call_stub. */
8923 struct mips16_stub
*next
;
8928 static struct mips16_stub
*mips16_stubs
;
8930 /* Build a call stub for a mips16 call. A stub is needed if we are
8931 passing any floating point values which should go into the floating
8932 point registers. If we are, and the call turns out to be to a 32
8933 bit function, the stub will be used to move the values into the
8934 floating point registers before calling the 32 bit function. The
8935 linker will magically adjust the function call to either the 16 bit
8936 function or the 32 bit stub, depending upon where the function call
8937 is actually defined.
8939 Similarly, we need a stub if the return value might come back in a
8940 floating point register.
8942 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8943 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8944 is the code built by function_arg. This function returns a nonzero
8945 value if it builds the call instruction itself. */
8948 build_mips16_call_stub (retval
, fnmem
, arg_size
, fp_code
)
8957 char *secname
, *stubname
;
8958 struct mips16_stub
*l
;
8959 tree stubid
, stubdecl
;
8963 /* We don't need to do anything if we aren't in mips16 mode, or if
8964 we were invoked with the -msoft-float option. */
8965 if (! TARGET_MIPS16
|| ! mips16_hard_float
)
8968 /* Figure out whether the value might come back in a floating point
8970 fpret
= (retval
!= 0
8971 && GET_MODE_CLASS (GET_MODE (retval
)) == MODE_FLOAT
8972 && GET_MODE_SIZE (GET_MODE (retval
)) <= UNITS_PER_FPVALUE
);
8974 /* We don't need to do anything if there were no floating point
8975 arguments and the value will not be returned in a floating point
8977 if (fp_code
== 0 && ! fpret
)
8980 if (GET_CODE (fnmem
) != MEM
)
8982 fn
= XEXP (fnmem
, 0);
8984 /* We don't need to do anything if this is a call to a special
8985 mips16 support function. */
8986 if (GET_CODE (fn
) == SYMBOL_REF
8987 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
8990 /* This code will only work for o32 and o64 abis. The other ABI's
8991 require more sophisticated support. */
8992 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_O64
)
8995 /* We can only handle SFmode and DFmode floating point return
8997 if (fpret
&& GET_MODE (retval
) != SFmode
&& GET_MODE (retval
) != DFmode
)
9000 /* If we're calling via a function pointer, then we must always call
9001 via a stub. There are magic stubs provided in libgcc.a for each
9002 of the required cases. Each of them expects the function address
9003 to arrive in register $2. */
9005 if (GET_CODE (fn
) != SYMBOL_REF
)
9009 rtx stub_fn
, stub_mem
, insn
;
9011 /* ??? If this code is modified to support other ABI's, we need
9012 to handle PARALLEL return values here. */
9014 sprintf (buf
, "__mips16_call_stub_%s%d",
9016 ? (GET_MODE (retval
) == SFmode
? "sf_" : "df_")
9019 id
= get_identifier (buf
);
9020 stub_fn
= gen_rtx (SYMBOL_REF
, Pmode
, IDENTIFIER_POINTER (id
));
9021 stub_mem
= gen_rtx (MEM
, Pmode
, stub_fn
);
9023 emit_move_insn (gen_rtx (REG
, Pmode
, 2), fn
);
9025 if (retval
== NULL_RTX
)
9026 insn
= gen_call_internal0 (stub_mem
, arg_size
,
9027 gen_rtx (REG
, SImode
,
9028 GP_REG_FIRST
+ 31));
9030 insn
= gen_call_value_internal0 (retval
, stub_mem
, arg_size
,
9031 gen_rtx (REG
, SImode
,
9032 GP_REG_FIRST
+ 31));
9033 insn
= emit_call_insn (insn
);
9035 /* Put the register usage information on the CALL. */
9036 if (GET_CODE (insn
) != CALL_INSN
)
9038 CALL_INSN_FUNCTION_USAGE (insn
) =
9039 gen_rtx (EXPR_LIST
, VOIDmode
,
9040 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, Pmode
, 2)),
9041 CALL_INSN_FUNCTION_USAGE (insn
));
9043 /* If we are handling a floating point return value, we need to
9044 save $18 in the function prologue. Putting a note on the
9045 call will mean that regs_ever_live[$18] will be true if the
9046 call is not eliminated, and we can check that in the prologue
9049 CALL_INSN_FUNCTION_USAGE (insn
) =
9050 gen_rtx (EXPR_LIST
, VOIDmode
,
9051 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
9052 CALL_INSN_FUNCTION_USAGE (insn
));
9054 /* Return 1 to tell the caller that we've generated the call
9059 /* We know the function we are going to call. If we have already
9060 built a stub, we don't need to do anything further. */
9062 fnname
= XSTR (fn
, 0);
9063 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
9064 if (strcmp (l
->name
, fnname
) == 0)
9069 /* Build a special purpose stub. When the linker sees a
9070 function call in mips16 code, it will check where the target
9071 is defined. If the target is a 32 bit call, the linker will
9072 search for the section defined here. It can tell which
9073 symbol this section is associated with by looking at the
9074 relocation information (the name is unreliable, since this
9075 might be a static function). If such a section is found, the
9076 linker will redirect the call to the start of the magic
9079 If the function does not return a floating point value, the
9080 special stub section is named
9083 If the function does return a floating point value, the stub
9085 .mips16.call.fp.FNNAME
9088 secname
= (char *) alloca (strlen (fnname
) + 40);
9089 sprintf (secname
, ".mips16.call.%s%s",
9092 stubname
= (char *) alloca (strlen (fnname
) + 20);
9093 sprintf (stubname
, "__call_stub_%s%s",
9096 stubid
= get_identifier (stubname
);
9097 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
9098 build_function_type (void_type_node
, NULL_TREE
));
9099 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
9101 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
9103 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
9107 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
9109 fprintf (asm_out_file
, "%s%s",
9110 need_comma
? ", " : "",
9111 (f
& 3) == 1 ? "float" : "double");
9114 fprintf (asm_out_file
, ")\n");
9116 fprintf (asm_out_file
, "\t.set\tnomips16\n");
9117 assemble_start_function (stubdecl
, stubname
);
9119 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9120 fputs ("\t.ent\t", asm_out_file
);
9121 assemble_name (asm_out_file
, stubname
);
9122 fputs ("\n", asm_out_file
);
9124 assemble_name (asm_out_file
, stubname
);
9125 fputs (":\n", asm_out_file
);
9128 /* We build the stub code by hand. That's the only way we can
9129 do it, since we can't generate 32 bit code during a 16 bit
9132 /* We don't want the assembler to insert any nops here. */
9133 fprintf (asm_out_file
, "\t.set\tnoreorder\n");
9135 mips16_fp_args (asm_out_file
, fp_code
, 0);
9139 fprintf (asm_out_file
, "\t.set\tnoat\n");
9140 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
9142 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
9143 fprintf (asm_out_file
, "\t.set\tat\n");
9144 /* Unfortunately, we can't fill the jump delay slot. We
9145 can't fill with one of the mtc1 instructions, because the
9146 result is not available for one instruction, so if the
9147 very first instruction in the function refers to the
9148 register, it will see the wrong value. */
9149 fprintf (asm_out_file
, "\tnop\n");
9153 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
9154 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
9155 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
9156 /* As above, we can't fill the delay slot. */
9157 fprintf (asm_out_file
, "\tnop\n");
9158 if (GET_MODE (retval
) == SFmode
)
9159 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9160 reg_names
[GP_REG_FIRST
+ 2], reg_names
[FP_REG_FIRST
+ 0]);
9163 if (TARGET_BIG_ENDIAN
)
9165 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9166 reg_names
[GP_REG_FIRST
+ 2],
9167 reg_names
[FP_REG_FIRST
+ 1]);
9168 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9169 reg_names
[GP_REG_FIRST
+ 3],
9170 reg_names
[FP_REG_FIRST
+ 0]);
9174 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9175 reg_names
[GP_REG_FIRST
+ 2],
9176 reg_names
[FP_REG_FIRST
+ 0]);
9177 fprintf (asm_out_file
, "\tmfc1\t%s,%s\n",
9178 reg_names
[GP_REG_FIRST
+ 3],
9179 reg_names
[FP_REG_FIRST
+ 1]);
9182 fprintf (asm_out_file
, "\tj\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
9183 /* As above, we can't fill the delay slot. */
9184 fprintf (asm_out_file
, "\tnop\n");
9187 fprintf (asm_out_file
, "\t.set\treorder\n");
9189 #ifdef ASM_DECLARE_FUNCTION_SIZE
9190 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
9193 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9194 fputs ("\t.end\t", asm_out_file
);
9195 assemble_name (asm_out_file
, stubname
);
9196 fputs ("\n", asm_out_file
);
9199 fprintf (asm_out_file
, "\t.set\tmips16\n");
9201 /* Record this stub. */
9202 l
= (struct mips16_stub
*) xmalloc (sizeof *l
);
9203 l
->name
= xstrdup (fnname
);
9205 l
->next
= mips16_stubs
;
9209 /* If we expect a floating point return value, but we've built a
9210 stub which does not expect one, then we're in trouble. We can't
9211 use the existing stub, because it won't handle the floating point
9212 value. We can't build a new stub, because the linker won't know
9213 which stub to use for the various calls in this object file.
9214 Fortunately, this case is illegal, since it means that a function
9215 was declared in two different ways in a single compilation. */
9216 if (fpret
&& ! l
->fpret
)
9217 error ("can not handle inconsistent calls to `%s'", fnname
);
9219 /* If we are calling a stub which handles a floating point return
9220 value, we need to arrange to save $18 in the prologue. We do
9221 this by marking the function call as using the register. The
9222 prologue will later see that it is used, and emit code to save
9229 if (retval
== NULL_RTX
)
9230 insn
= gen_call_internal0 (fnmem
, arg_size
,
9231 gen_rtx (REG
, SImode
,
9232 GP_REG_FIRST
+ 31));
9234 insn
= gen_call_value_internal0 (retval
, fnmem
, arg_size
,
9235 gen_rtx (REG
, SImode
,
9236 GP_REG_FIRST
+ 31));
9237 insn
= emit_call_insn (insn
);
9239 if (GET_CODE (insn
) != CALL_INSN
)
9242 CALL_INSN_FUNCTION_USAGE (insn
) =
9243 gen_rtx (EXPR_LIST
, VOIDmode
,
9244 gen_rtx (USE
, VOIDmode
, gen_rtx (REG
, word_mode
, 18)),
9245 CALL_INSN_FUNCTION_USAGE (insn
));
9247 /* Return 1 to tell the caller that we've generated the call
9252 /* Return 0 to let the caller generate the call insn. */
9256 /* This function looks through the code for a function, and tries to
9257 optimize the usage of the $gp register. We arrange to copy $gp
9258 into a pseudo-register, and then let gcc's normal reload handling
9259 deal with the pseudo-register. Unfortunately, if reload choose to
9260 put the pseudo-register into a call-clobbered register, it will
9261 emit saves and restores for that register around any function
9262 calls. We don't need the saves, and it's faster to copy $gp than
9263 to do an actual restore. ??? This still means that we waste a
9266 This is an optimization, and the code which gcc has actually
9267 generated is correct, so we do not need to catch all cases. */
9270 mips16_optimize_gp (first
)
9273 rtx gpcopy
, slot
, insn
;
9275 /* Look through the instructions. Set GPCOPY to the register which
9276 holds a copy of $gp. Set SLOT to the stack slot where it is
9277 saved. If we find an instruction which sets GPCOPY to anything
9278 other than $gp or SLOT, then we can't use it. If we find an
9279 instruction which sets SLOT to anything other than GPCOPY, we
9284 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9288 if (! INSN_P (insn
))
9291 set
= PATTERN (insn
);
9293 /* We know that all references to memory will be inside a SET,
9294 because there is no other way to access memory on the mips16.
9295 We don't have to worry about a PARALLEL here, because the
9296 mips.md file will never generate them for memory references. */
9297 if (GET_CODE (set
) != SET
)
9300 if (gpcopy
== NULL_RTX
9301 && GET_CODE (SET_SRC (set
)) == CONST
9302 && GET_CODE (XEXP (SET_SRC (set
), 0)) == REG
9303 && REGNO (XEXP (SET_SRC (set
), 0)) == GP_REG_FIRST
+ 28
9304 && GET_CODE (SET_DEST (set
)) == REG
9305 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
9306 gpcopy
= SET_DEST (set
);
9307 else if (slot
== NULL_RTX
9308 && gpcopy
!= NULL_RTX
9309 && GET_CODE (SET_DEST (set
)) == MEM
9310 && GET_CODE (SET_SRC (set
)) == REG
9311 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
)
9312 && GET_MODE (SET_DEST (set
)) == (unsigned) Pmode
)
9316 offset
= const0_rtx
;
9317 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9318 if (GET_CODE (base
) == REG
9319 && (REGNO (base
) == STACK_POINTER_REGNUM
9320 || REGNO (base
) == FRAME_POINTER_REGNUM
))
9321 slot
= SET_DEST (set
);
9323 else if (gpcopy
!= NULL_RTX
9324 && (GET_CODE (SET_DEST (set
)) == REG
9325 || GET_CODE (SET_DEST (set
)) == SUBREG
)
9326 && reg_overlap_mentioned_p (SET_DEST (set
), gpcopy
)
9327 && (GET_CODE (SET_DEST (set
)) != REG
9328 || REGNO (SET_DEST (set
)) != REGNO (gpcopy
)
9329 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
9330 || ((GET_CODE (SET_SRC (set
)) != CONST
9331 || GET_CODE (XEXP (SET_SRC (set
), 0)) != REG
9332 || (REGNO (XEXP (SET_SRC (set
), 0))
9333 != GP_REG_FIRST
+ 28))
9334 && ! rtx_equal_p (SET_SRC (set
), slot
))))
9336 else if (slot
!= NULL_RTX
9337 && GET_CODE (SET_DEST (set
)) == MEM
9338 && rtx_equal_p (SET_DEST (set
), slot
)
9339 && (GET_CODE (SET_SRC (set
)) != REG
9340 || REGNO (SET_SRC (set
)) != REGNO (gpcopy
)))
9344 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9345 different optimization. Any time we find a copy of $28 into a
9346 register, followed by an add of a symbol_ref to that register, we
9347 convert it to load the value from the constant table instead.
9348 The copy and add will take six bytes, just as the load and
9349 constant table entry will take six bytes. However, it is
9350 possible that the constant table entry will be shared.
9352 This could be a peephole optimization, but I don't know if the
9353 peephole code can call force_const_mem.
9355 Using the same register for the copy of $28 and the add of the
9356 symbol_ref is actually pretty likely, since the add instruction
9357 requires the destination and the first addend to be the same
9360 if (insn
!= NULL_RTX
|| gpcopy
== NULL_RTX
|| slot
== NULL_RTX
)
9364 /* This optimization is only reasonable if the constant table
9365 entries are only 4 bytes. */
9366 if (Pmode
!= SImode
)
9369 for (insn
= first
; insn
!= NULL_RTX
; insn
= next
)
9376 next
= NEXT_INSN (next
);
9378 while (next
!= NULL_RTX
9379 && (GET_CODE (next
) == NOTE
9380 || (GET_CODE (next
) == INSN
9381 && (GET_CODE (PATTERN (next
)) == USE
9382 || GET_CODE (PATTERN (next
)) == CLOBBER
))));
9384 if (next
== NULL_RTX
)
9387 if (! INSN_P (insn
))
9390 if (! INSN_P (next
))
9393 set1
= PATTERN (insn
);
9394 if (GET_CODE (set1
) != SET
)
9396 set2
= PATTERN (next
);
9397 if (GET_CODE (set2
) != SET
)
9400 if (GET_CODE (SET_DEST (set1
)) == REG
9401 && GET_CODE (SET_SRC (set1
)) == CONST
9402 && GET_CODE (XEXP (SET_SRC (set1
), 0)) == REG
9403 && REGNO (XEXP (SET_SRC (set1
), 0)) == GP_REG_FIRST
+ 28
9404 && rtx_equal_p (SET_DEST (set1
), SET_DEST (set2
))
9405 && GET_CODE (SET_SRC (set2
)) == PLUS
9406 && rtx_equal_p (SET_DEST (set1
), XEXP (SET_SRC (set2
), 0))
9407 && mips16_gp_offset_p (XEXP (SET_SRC (set2
), 1))
9408 && GET_CODE (XEXP (XEXP (SET_SRC (set2
), 1), 0)) == MINUS
)
9412 /* We've found a case we can change to load from the
9415 sym
= XEXP (XEXP (XEXP (SET_SRC (set2
), 1), 0), 0);
9416 if (GET_CODE (sym
) != SYMBOL_REF
)
9418 emit_insn_after (gen_rtx (SET
, VOIDmode
, SET_DEST (set1
),
9419 force_const_mem (Pmode
, sym
)),
9422 PUT_CODE (insn
, NOTE
);
9423 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9424 NOTE_SOURCE_FILE (insn
) = 0;
9426 PUT_CODE (next
, NOTE
);
9427 NOTE_LINE_NUMBER (next
) = NOTE_INSN_DELETED
;
9428 NOTE_SOURCE_FILE (next
) = 0;
9435 /* We can safely remove all assignments to SLOT from GPCOPY, and
9436 replace all assignments from SLOT to GPCOPY with assignments from
9439 for (insn
= first
; insn
!= NULL_RTX
; insn
= next_active_insn (insn
))
9443 if (! INSN_P (insn
))
9446 set
= PATTERN (insn
);
9447 if (GET_CODE (set
) != SET
9448 || GET_MODE (SET_DEST (set
)) != (unsigned) Pmode
)
9451 if (GET_CODE (SET_DEST (set
)) == MEM
9452 && rtx_equal_p (SET_DEST (set
), slot
)
9453 && GET_CODE (SET_SRC (set
)) == REG
9454 && REGNO (SET_SRC (set
)) == REGNO (gpcopy
))
9456 PUT_CODE (insn
, NOTE
);
9457 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9458 NOTE_SOURCE_FILE (insn
) = 0;
9460 else if (GET_CODE (SET_DEST (set
)) == REG
9461 && REGNO (SET_DEST (set
)) == REGNO (gpcopy
)
9462 && GET_CODE (SET_SRC (set
)) == MEM
9463 && rtx_equal_p (SET_SRC (set
), slot
))
9465 emit_insn_after (gen_rtx (SET
, Pmode
, SET_DEST (set
),
9466 gen_rtx (CONST
, Pmode
,
9467 gen_rtx (REG
, Pmode
,
9468 GP_REG_FIRST
+ 28))),
9470 PUT_CODE (insn
, NOTE
);
9471 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9472 NOTE_SOURCE_FILE (insn
) = 0;
9477 /* We keep a list of constants we which we have to add to internal
9478 constant tables in the middle of large functions. */
9482 struct constant
*next
;
9485 enum machine_mode mode
;
9488 /* Add a constant to the list in *PCONSTANTS. */
9491 add_constant (pconstants
, val
, mode
)
9492 struct constant
**pconstants
;
9494 enum machine_mode mode
;
9498 for (c
= *pconstants
; c
!= NULL
; c
= c
->next
)
9499 if (mode
== c
->mode
&& rtx_equal_p (val
, c
->value
))
9502 c
= (struct constant
*) xmalloc (sizeof *c
);
9505 c
->label
= gen_label_rtx ();
9506 c
->next
= *pconstants
;
9511 /* Dump out the constants in CONSTANTS after INSN. */
9514 dump_constants (constants
, insn
)
9515 struct constant
*constants
;
9526 struct constant
*next
;
9528 switch (GET_MODE_SIZE (c
->mode
))
9535 insn
= emit_insn_after (gen_align_2 (), insn
);
9540 insn
= emit_insn_after (gen_align_4 (), insn
);
9545 insn
= emit_insn_after (gen_align_8 (), insn
);
9550 insn
= emit_label_after (c
->label
, insn
);
9555 r
= gen_consttable_qi (c
->value
);
9558 r
= gen_consttable_hi (c
->value
);
9561 r
= gen_consttable_si (c
->value
);
9564 r
= gen_consttable_sf (c
->value
);
9567 r
= gen_consttable_di (c
->value
);
9570 r
= gen_consttable_df (c
->value
);
9576 insn
= emit_insn_after (r
, insn
);
9583 emit_barrier_after (insn
);
9586 /* Find the symbol in an address expression. */
9589 mips_find_symbol (addr
)
9592 if (GET_CODE (addr
) == MEM
)
9593 addr
= XEXP (addr
, 0);
9594 while (GET_CODE (addr
) == CONST
)
9595 addr
= XEXP (addr
, 0);
9596 if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == LABEL_REF
)
9598 if (GET_CODE (addr
) == PLUS
)
9602 l1
= mips_find_symbol (XEXP (addr
, 0));
9603 l2
= mips_find_symbol (XEXP (addr
, 1));
9604 if (l1
!= NULL_RTX
&& l2
== NULL_RTX
)
9606 else if (l1
== NULL_RTX
&& l2
!= NULL_RTX
)
9612 /* Exported to toplev.c.
9614 Do a final pass over the function, just before delayed branch
9618 machine_dependent_reorg (first
)
9621 int insns_len
, max_internal_pool_size
, pool_size
, addr
, first_constant_ref
;
9623 struct constant
*constants
;
9625 if (! TARGET_MIPS16
)
9628 /* If $gp is used, try to remove stores, and replace loads with
9631 mips16_optimize_gp (first
);
9633 /* Scan the function looking for PC relative loads which may be out
9634 of range. All such loads will either be from the constant table,
9635 or be getting the address of a constant string. If the size of
9636 the function plus the size of the constant table is less than
9637 0x8000, then all loads are in range. */
9640 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9642 insns_len
+= get_attr_length (insn
);
9644 /* ??? We put switch tables in .text, but we don't define
9645 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9646 compute their lengths correctly. */
9647 if (GET_CODE (insn
) == JUMP_INSN
)
9651 body
= PATTERN (insn
);
9652 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
9653 insns_len
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
9654 * GET_MODE_SIZE (GET_MODE (body
)));
9655 insns_len
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
9659 /* Store the original value of insns_len in cfun->machine, so
9660 that simple_memory_operand can look at it. */
9661 cfun
->machine
->insns_len
= insns_len
;
9663 pool_size
= get_pool_size ();
9664 if (insns_len
+ pool_size
+ mips_string_length
< 0x8000)
9667 /* Loop over the insns and figure out what the maximum internal pool
9669 max_internal_pool_size
= 0;
9670 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9672 if (GET_CODE (insn
) == INSN
9673 && GET_CODE (PATTERN (insn
)) == SET
)
9677 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
9678 if (src
== NULL_RTX
)
9680 if (CONSTANT_POOL_ADDRESS_P (src
))
9681 max_internal_pool_size
+= GET_MODE_SIZE (get_pool_mode (src
));
9682 else if (SYMBOL_REF_FLAG (src
))
9683 max_internal_pool_size
+= GET_MODE_SIZE (Pmode
);
9689 first_constant_ref
= -1;
9691 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
9693 if (GET_CODE (insn
) == INSN
9694 && GET_CODE (PATTERN (insn
)) == SET
)
9697 enum machine_mode mode
= VOIDmode
;
9700 src
= mips_find_symbol (SET_SRC (PATTERN (insn
)));
9701 if (src
!= NULL_RTX
&& CONSTANT_POOL_ADDRESS_P (src
))
9703 /* ??? This is very conservative, which means that we
9704 will generate too many copies of the constant table.
9705 The only solution would seem to be some form of
9707 if (((insns_len
- addr
)
9708 + max_internal_pool_size
9709 + get_pool_offset (src
))
9712 val
= get_pool_constant (src
);
9713 mode
= get_pool_mode (src
);
9715 max_internal_pool_size
-= GET_MODE_SIZE (get_pool_mode (src
));
9717 else if (src
!= NULL_RTX
&& SYMBOL_REF_FLAG (src
))
9719 /* Including all of mips_string_length is conservative,
9720 and so is including all of max_internal_pool_size. */
9721 if (((insns_len
- addr
)
9722 + max_internal_pool_size
9724 + mips_string_length
)
9730 max_internal_pool_size
-= Pmode
;
9733 if (val
!= NULL_RTX
)
9737 /* This PC relative load is out of range. ??? In the
9738 case of a string constant, we are only guessing that
9739 it is range, since we don't know the offset of a
9740 particular string constant. */
9742 lab
= add_constant (&constants
, val
, mode
);
9743 newsrc
= gen_rtx (MEM
, mode
,
9744 gen_rtx (LABEL_REF
, VOIDmode
, lab
));
9745 RTX_UNCHANGING_P (newsrc
) = 1;
9746 PATTERN (insn
) = gen_rtx (SET
, VOIDmode
,
9747 SET_DEST (PATTERN (insn
)),
9749 INSN_CODE (insn
) = -1;
9751 if (first_constant_ref
< 0)
9752 first_constant_ref
= addr
;
9756 addr
+= get_attr_length (insn
);
9758 /* ??? We put switch tables in .text, but we don't define
9759 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9760 compute their lengths correctly. */
9761 if (GET_CODE (insn
) == JUMP_INSN
)
9765 body
= PATTERN (insn
);
9766 if (GET_CODE (body
) == ADDR_VEC
|| GET_CODE (body
) == ADDR_DIFF_VEC
)
9767 addr
+= (XVECLEN (body
, GET_CODE (body
) == ADDR_DIFF_VEC
)
9768 * GET_MODE_SIZE (GET_MODE (body
)));
9769 addr
+= GET_MODE_SIZE (GET_MODE (body
)) - 1;
9772 if (GET_CODE (insn
) == BARRIER
)
9774 /* Output any constants we have accumulated. Note that we
9775 don't need to change ADDR, since its only use is
9776 subtraction from INSNS_LEN, and both would be changed by
9778 ??? If the instructions up to the next barrier reuse a
9779 constant, it would often be better to continue
9781 if (constants
!= NULL
)
9782 dump_constants (constants
, insn
);
9784 first_constant_ref
= -1;
9787 if (constants
!= NULL
9788 && (NEXT_INSN (insn
) == NULL
9789 || (first_constant_ref
>= 0
9790 && (((addr
- first_constant_ref
)
9791 + 2 /* for alignment */
9792 + 2 /* for a short jump insn */
9796 /* If we haven't had a barrier within 0x8000 bytes of a
9797 constant reference or we are at the end of the function,
9798 emit a barrier now. */
9800 rtx label
, jump
, barrier
;
9802 label
= gen_label_rtx ();
9803 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
9804 JUMP_LABEL (jump
) = label
;
9805 LABEL_NUSES (label
) = 1;
9806 barrier
= emit_barrier_after (jump
);
9807 emit_label_after (label
, barrier
);
9808 first_constant_ref
= -1;
9812 /* ??? If we output all references to a constant in internal
9813 constants table, we don't need to output the constant in the real
9814 constant table, but we have no way to prevent that. */
9817 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9819 extend_operator (x
, mode
)
9821 enum machine_mode mode ATTRIBUTE_UNUSED
;
9823 enum rtx_code code
= GET_CODE (x
);
9824 return code
== SIGN_EXTEND
|| code
== ZERO_EXTEND
;
9827 /* Accept any operator that can be used to shift the high half of the
9828 input value to the lower half, suitable for truncation. The
9829 remainder (the lower half of the input, and the upper half of the
9830 output) will be discarded. */
9832 highpart_shift_operator (x
, mode
)
9834 enum machine_mode mode ATTRIBUTE_UNUSED
;
9836 enum rtx_code code
= GET_CODE (x
);
9837 return (code
== LSHIFTRT
9843 /* Return a number assessing the cost of moving a register in class
9844 FROM to class TO. The classes are expressed using the enumeration
9845 values such as `GENERAL_REGS'. A value of 2 is the default; other
9846 values are interpreted relative to that.
9848 It is not required that the cost always equal 2 when FROM is the
9849 same as TO; on some machines it is expensive to move between
9850 registers if they are not general registers.
9852 If reload sees an insn consisting of a single `set' between two
9853 hard registers, and if `REGISTER_MOVE_COST' applied to their
9854 classes returns a value of 2, reload does not check to ensure that
9855 the constraints of the insn are met. Setting a cost of other than
9856 2 will allow reload to verify that the constraints are met. You
9857 should do this if the `movM' pattern's constraints do not allow
9860 ??? We make make the cost of moving from HI/LO/HILO/MD into general
9861 registers the same as for one of moving general registers to
9862 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
9863 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
9864 isn't clear if it is wise. And it might not work in all cases. We
9865 could solve the DImode LO reg problem by using a multiply, just
9866 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9867 problem by using divide instructions. divu puts the remainder in
9868 the HI reg, so doing a divide by -1 will move the value in the HI
9869 reg for all values except -1. We could handle that case by using a
9870 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9871 a compare/branch to test the input value to see which instruction
9872 we need to use. This gets pretty messy, but it is feasible. */
9875 mips_register_move_cost (mode
, to
, from
)
9876 enum machine_mode mode ATTRIBUTE_UNUSED
;
9877 enum reg_class to
, from
;
9879 if (from
== M16_REGS
&& GR_REG_CLASS_P (to
))
9881 else if (from
== M16_NA_REGS
&& GR_REG_CLASS_P (to
))
9883 else if (GR_REG_CLASS_P (from
))
9887 else if (to
== M16_NA_REGS
)
9889 else if (GR_REG_CLASS_P (to
))
9896 else if (to
== FP_REGS
)
9898 else if (to
== HI_REG
|| to
== LO_REG
|| to
== MD_REGS
9906 else if (COP_REG_CLASS_P (to
))
9910 } /* GR_REG_CLASS_P (from) */
9911 else if (from
== FP_REGS
)
9913 if (GR_REG_CLASS_P (to
))
9915 else if (to
== FP_REGS
)
9917 else if (to
== ST_REGS
)
9919 } /* from == FP_REGS */
9920 else if (from
== HI_REG
|| from
== LO_REG
|| from
== MD_REGS
9921 || from
== HILO_REG
)
9923 if (GR_REG_CLASS_P (to
))
9930 } /* from == HI_REG, etc. */
9931 else if (from
== ST_REGS
&& GR_REG_CLASS_P (to
))
9933 else if (COP_REG_CLASS_P (from
))
9936 } /* COP_REG_CLASS_P (from) */
9943 /* Return the length of INSN. LENGTH is the initial length computed by
9944 attributes in the machine-description file. */
9947 mips_adjust_insn_length (insn
, length
)
9951 /* A unconditional jump has an unfilled delay slot if it is not part
9952 of a sequence. A conditional jump normally has a delay slot, but
9953 does not on MIPS16. */
9954 if (simplejump_p (insn
)
9955 || (!TARGET_MIPS16
&& (GET_CODE (insn
) == JUMP_INSN
9956 || GET_CODE (insn
) == CALL_INSN
)))
9959 /* All MIPS16 instructions are a measly two bytes. */
9966 /* Output assembly instructions to peform a conditional branch.
9968 INSN is the branch instruction. OPERANDS[0] is the condition.
9969 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9970 of the first operand to the condition. If TWO_OPERANDS_P is
9971 non-zero the comparison takes two operands; OPERANDS[3] will be the
9974 If INVERTED_P is non-zero we are to branch if the condition does
9975 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9977 LENGTH is the length (in bytes) of the sequence we are to generate.
9978 That tells us whether to generate a simple conditional branch, or a
9979 reversed conditional branch around a `jr' instruction. */
9981 mips_output_conditional_branch (insn
,
9994 static char buffer
[200];
9995 /* The kind of comparison we are doing. */
9996 enum rtx_code code
= GET_CODE (operands
[0]);
9997 /* Non-zero if the opcode for the comparison needs a `z' indicating
9998 that it is a comparision against zero. */
10000 /* A string to use in the assembly output to represent the first
10002 const char *op1
= "%z2";
10003 /* A string to use in the assembly output to represent the second
10004 operand. Use the hard-wired zero register if there's no second
10006 const char *op2
= (two_operands_p
? ",%z3" : ",%.");
10007 /* The operand-printing string for the comparison. */
10008 const char *const comp
= (float_p
? "%F0" : "%C0");
10009 /* The operand-printing string for the inverted comparison. */
10010 const char *const inverted_comp
= (float_p
? "%W0" : "%N0");
10012 /* The MIPS processors (for levels of the ISA at least two), have
10013 "likely" variants of each branch instruction. These instructions
10014 annul the instruction in the delay slot if the branch is not
10016 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
10018 if (!two_operands_p
)
10020 /* To compute whether than A > B, for example, we normally
10021 subtract B from A and then look at the sign bit. But, if we
10022 are doing an unsigned comparison, and B is zero, we don't
10023 have to do the subtraction. Instead, we can just check to
10024 see if A is non-zero. Thus, we change the CODE here to
10025 reflect the simpler comparison operation. */
10037 /* A condition which will always be true. */
10043 /* A condition which will always be false. */
10049 /* Not a special case. */
10054 /* Relative comparisons are always done against zero. But
10055 equality comparisons are done between two operands, and therefore
10056 do not require a `z' in the assembly language output. */
10057 need_z_p
= (!float_p
&& code
!= EQ
&& code
!= NE
);
10058 /* For comparisons against zero, the zero is not provided
10063 /* Begin by terminating the buffer. That way we can always use
10064 strcat to add to it. */
10071 /* Just a simple conditional branch. */
10073 sprintf (buffer
, "%%*b%s%%?\t%%Z2%%1",
10074 inverted_p
? inverted_comp
: comp
);
10076 sprintf (buffer
, "%%*b%s%s%%?\t%s%s,%%1",
10077 inverted_p
? inverted_comp
: comp
,
10078 need_z_p
? "z" : "",
10086 /* Generate a reversed conditional branch around ` j'
10101 rtx target
= gen_label_rtx ();
10103 output_asm_insn ("%(%<", 0);
10104 orig_target
= operands
[1];
10105 operands
[1] = target
;
10106 /* Generate the reversed comparison. This takes four
10109 sprintf (buffer
, "%%*b%s\t%%Z2%%1",
10110 inverted_p
? comp
: inverted_comp
);
10112 sprintf (buffer
, "%%*b%s%s\t%s%s,%%1",
10113 inverted_p
? comp
: inverted_comp
,
10114 need_z_p
? "z" : "",
10117 output_asm_insn (buffer
, operands
);
10118 operands
[1] = orig_target
;
10120 output_asm_insn ("nop\n\tj\t%1", operands
);
10123 output_asm_insn ("nop", 0);
10126 /* Output delay slot instruction. */
10127 rtx insn
= final_sequence
;
10128 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
,
10130 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
10132 output_asm_insn ("%>%)", 0);
10133 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
10134 CODE_LABEL_NUMBER (target
));
10138 /* We do not currently use this code. It handles jumps to
10139 arbitrary locations, using `jr', even across a 256MB boundary.
10140 We could add a -mhuge switch, and then use this code instead of
10141 the `j' alternative above when -mhuge was used. */
10146 /* Generate a reversed conditional branch around a `jr'
10160 Not pretty, but allows a conditional branch anywhere in the
10161 32-bit address space. If the original branch is annulled,
10162 then the instruction in the delay slot should be executed
10163 only if the branch is taken. The la instruction is really
10164 a macro which will usually take eight bytes, but sometimes
10165 takes only four, if the instruction to which we're jumping
10166 gets its own entry in the global pointer table, which will
10167 happen if its a case label. The assembler will then
10168 generate only a four-byte sequence, rather than eight, and
10169 there seems to be no way to tell it not to. Thus, we can't
10170 just use a `.+x' addressing form; we don't know what value
10173 So, we resort to using the explicit relocation syntax
10174 available in the assembler and do:
10176 lw $at,%got_page(target)($gp)
10177 daddiu $at,$at,%got_ofst(target)
10179 That way, this always takes up eight bytes, and we can use
10180 the `.+x' form. Of course, these explicit machinations
10181 with relocation will not work with old assemblers. Then
10182 again, neither do out-of-range branches, so we haven't lost
10185 /* The target of the reversed branch. */
10186 const char *const target
10187 = ((mips_branch_likely
|| length
== 20) ? ".+20" : ".+16");
10188 const char *at_register
= mips_reg_names
[ASSEMBLER_SCRATCH_REGNUM
];
10189 const char *gp_register
= mips_reg_names
[PIC_OFFSET_TABLE_REGNUM
];
10192 strcpy (buffer
, "%(%<%[");
10193 c
= strchr (buffer
, '\0');
10194 /* Generate the reversed comparision. This takes four
10197 sprintf (c
, "%%*b%s\t%%Z2%s",
10198 inverted_p
? comp
: inverted_comp
,
10201 sprintf (c
, "%%*b%s%s\t%s%s,%s",
10202 inverted_p
? comp
: inverted_comp
,
10203 need_z_p
? "z" : "",
10207 c
= strchr (buffer
, '\0');
10208 /* Generate the load-address, and jump. This takes twelve
10209 bytes, for a total of 16. */
10211 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
10218 /* The delay slot was unfilled. Since we're inside
10219 .noreorder, the assembler will not fill in the NOP for
10220 us, so we must do it ourselves. */
10221 strcat (buffer
, "\n\tnop");
10222 strcat (buffer
, "%]%>%)");
10235 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10236 with a final "000" replaced by "k". Ignore case.
10238 Note: this function is shared between GCC and GAS. */
10241 mips_strict_matching_cpu_name_p (canonical
, given
)
10242 const char *canonical
, *given
;
10244 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
10245 given
++, canonical
++;
10247 return ((*given
== 0 && *canonical
== 0)
10248 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
10252 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10253 CPU name. We've traditionally allowed a lot of variation here.
10255 Note: this function is shared between GCC and GAS. */
10258 mips_matching_cpu_name_p (canonical
, given
)
10259 const char *canonical
, *given
;
10261 /* First see if the name matches exactly, or with a final "000"
10262 turned into "k". */
10263 if (mips_strict_matching_cpu_name_p (canonical
, given
))
10266 /* If not, try comparing based on numerical designation alone.
10267 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10268 if (TOLOWER (*given
) == 'r')
10270 if (!ISDIGIT (*given
))
10273 /* Skip over some well-known prefixes in the canonical name,
10274 hoping to find a number there too. */
10275 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
10277 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
10279 else if (TOLOWER (canonical
[0]) == 'r')
10282 return mips_strict_matching_cpu_name_p (canonical
, given
);
10286 /* Parse an option that takes the name of a processor as its argument.
10287 OPTION is the name of the option and CPU_STRING is the argument.
10288 Return the corresponding processor enumeration if the CPU_STRING is
10289 recognized, otherwise report an error and return null.
10291 A similar function exists in GAS. */
10293 static const struct mips_cpu_info
*
10294 mips_parse_cpu (option
, cpu_string
)
10295 const char *option
, *cpu_string
;
10297 const struct mips_cpu_info
*p
;
10300 /* In the past, we allowed upper-case CPU names, but it doesn't
10301 work well with the multilib machinery. */
10302 for (s
= cpu_string
; *s
!= 0; s
++)
10305 warning ("the cpu name must be lower case");
10309 /* 'from-abi' selects the most compatible architecture for the given
10310 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10311 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10312 version. Look first at the -mgp options, if given, otherwise base
10313 the choice on MASK_64BIT in TARGET_DEFAULT. */
10314 if (strcasecmp (cpu_string
, "from-abi") == 0)
10315 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
10316 : ABI_NEEDS_64BIT_REGS
? 3
10317 : (TARGET_64BIT
? 3 : 1));
10319 /* 'default' has traditionally been a no-op. Probably not very useful. */
10320 if (strcasecmp (cpu_string
, "default") == 0)
10323 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
10324 if (mips_matching_cpu_name_p (p
->name
, cpu_string
))
10327 error ("bad value (%s) for %s", cpu_string
, option
);
10332 /* Return the processor associated with the given ISA level, or null
10333 if the ISA isn't valid. */
10335 static const struct mips_cpu_info
*
10336 mips_cpu_info_from_isa (isa
)
10339 const struct mips_cpu_info
*p
;
10341 for (p
= mips_cpu_info_table
; p
->name
!= 0; p
++)
10348 /* Adjust the cost of INSN based on the relationship between INSN that
10349 is dependent on DEP_INSN through the dependence LINK. The default
10350 is to make no adjustment to COST.
10352 On the MIPS, ignore the cost of anti- and output-dependencies. */
10354 mips_adjust_cost (insn
, link
, dep
, cost
)
10355 rtx insn ATTRIBUTE_UNUSED
;
10357 rtx dep ATTRIBUTE_UNUSED
;
10360 if (REG_NOTE_KIND (link
) != 0)
10361 return 0; /* Anti or output dependence. */
10365 /* ??? This could be replaced with the default elf version if
10366 TARGET_IS_SMALL_DATA_P is set properly. */
10369 mips_unique_section (decl
, reloc
)
10373 int len
, size
, sec
;
10374 const char *name
, *prefix
;
10376 static const char *const prefixes
[4][2] = {
10377 { ".text.", ".gnu.linkonce.t." },
10378 { ".rodata.", ".gnu.linkonce.r." },
10379 { ".data.", ".gnu.linkonce.d." },
10380 { ".sdata.", ".gnu.linkonce.s." }
10383 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
10384 name
= (* targetm
.strip_name_encoding
) (name
);
10385 size
= int_size_in_bytes (TREE_TYPE (decl
));
10387 /* Determine the base section we are interested in:
10388 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
10389 if (TREE_CODE (decl
) == FUNCTION_DECL
)
10391 else if (DECL_INITIAL (decl
) == 0
10392 || DECL_INITIAL (decl
) == error_mark_node
)
10394 else if ((TARGET_EMBEDDED_PIC
|| TARGET_MIPS16
)
10395 && TREE_CODE (decl
) == STRING_CST
10396 && !flag_writable_strings
)
10398 /* For embedded position independent code, put constant
10399 strings in the text section, because the data section
10400 is limited to 64K in size. For mips16 code, put
10401 strings in the text section so that a PC relative load
10402 instruction can be used to get their address. */
10405 else if (TARGET_EMBEDDED_DATA
)
10407 /* For embedded applications, always put an object in
10408 read-only data if possible, in order to reduce RAM
10411 if (decl_readonly_section (decl
, reloc
))
10413 else if (size
> 0 && size
<= mips_section_threshold
)
10420 /* For hosted applications, always put an object in
10421 small data if possible, as this gives the best
10424 if (size
> 0 && size
<= mips_section_threshold
)
10426 else if (decl_readonly_section (decl
, reloc
))
10432 prefix
= prefixes
[sec
][DECL_ONE_ONLY (decl
)];
10433 len
= strlen (name
) + strlen (prefix
);
10434 string
= alloca (len
+ 1);
10435 sprintf (string
, "%s%s", prefix
, name
);
10437 DECL_SECTION_NAME (decl
) = build_string (len
, string
);
10441 mips_hard_regno_nregs (regno
, mode
)
10443 enum machine_mode mode
;
10445 if (! FP_REG_P (regno
))
10446 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
10448 return ((GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
);
10452 mips_return_in_memory (type
)
10455 /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
10456 returned in memory. Under the new (N32 and 64-bit MIPS ABIs) small
10457 structures are returned in a register. Objects with varying size
10458 must still be returned in memory, of course. */
10460 if (mips_abi
== ABI_32
|| mips_abi
== ABI_O64
)
10461 return (TYPE_MODE (type
) == BLKmode
);
10463 return ((int_size_in_bytes (type
) > (2 * UNITS_PER_WORD
))
10464 || (int_size_in_bytes (type
) == -1));
10472 case PROCESSOR_R3000
: return 1;
10473 case PROCESSOR_R5400
: return 2;
10474 case PROCESSOR_R5500
: return 2;
10484 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
10485 processors that have a DFA pipeline description. */
10488 mips_use_dfa_pipeline_interface ()
10492 case PROCESSOR_R5400
:
10493 case PROCESSOR_R5500
:
10494 case PROCESSOR_SR71000
:
10504 mips_emit_prefetch (operands
)
10507 /* For the mips32/64 architectures the hint fields are arranged
10508 by operation (load/store) and locality (normal/streamed/retained).
10509 Irritatingly, numbers 2 and 3 are reserved leaving no simple
10510 algorithm for figuring the hint. */
10512 int write
= INTVAL (operands
[1]);
10513 int locality
= INTVAL (operands
[2]);
10515 static const char * const alt
[2][4] = {
10530 return alt
[write
][locality
];
10535 #ifdef TARGET_IRIX6
10536 /* Output assembly to switch to section NAME with attribute FLAGS. */
10539 iris6_asm_named_section_1 (name
, flags
, align
)
10541 unsigned int flags
;
10542 unsigned int align
;
10544 unsigned int sh_type
, sh_flags
, sh_entsize
;
10547 if (!(flags
& SECTION_DEBUG
))
10548 sh_flags
|= 2; /* SHF_ALLOC */
10549 if (flags
& SECTION_WRITE
)
10550 sh_flags
|= 1; /* SHF_WRITE */
10551 if (flags
& SECTION_CODE
)
10552 sh_flags
|= 4; /* SHF_EXECINSTR */
10553 if (flags
& SECTION_SMALL
)
10554 sh_flags
|= 0x10000000; /* SHF_MIPS_GPREL */
10555 if (strcmp (name
, ".debug_frame") == 0)
10556 sh_flags
|= 0x08000000; /* SHF_MIPS_NOSTRIP */
10557 if (flags
& SECTION_DEBUG
)
10558 sh_type
= 0x7000001e; /* SHT_MIPS_DWARF */
10559 else if (flags
& SECTION_BSS
)
10560 sh_type
= 8; /* SHT_NOBITS */
10562 sh_type
= 1; /* SHT_PROGBITS */
10564 if (flags
& SECTION_CODE
)
10569 fprintf (asm_out_file
, "\t.section %s,%#x,%#x,%u,%u\n",
10570 name
, sh_type
, sh_flags
, sh_entsize
, align
);
10574 iris6_asm_named_section (name
, flags
)
10576 unsigned int flags
;
10578 if (TARGET_FILE_SWITCHING
&& (flags
& SECTION_CODE
))
10579 asm_out_file
= asm_out_text_file
;
10580 iris6_asm_named_section_1 (name
, flags
, 0);
10583 /* In addition to emitting a .align directive, record the maximum
10584 alignment requested for the current section. */
10586 struct iris_section_align_entry
10590 unsigned int flags
;
10593 static htab_t iris_section_align_htab
;
10594 static FILE *iris_orig_asm_out_file
;
10597 iris_section_align_entry_eq (p1
, p2
)
10601 const struct iris_section_align_entry
*old
= p1
;
10602 const char *new = p2
;
10604 return strcmp (old
->name
, new) == 0;
10608 iris_section_align_entry_hash (p
)
10611 const struct iris_section_align_entry
*old
= p
;
10612 return htab_hash_string (old
->name
);
10616 iris6_asm_output_align (file
, log
)
10620 const char *section
= current_section_name ();
10621 struct iris_section_align_entry
**slot
, *entry
;
10626 slot
= (struct iris_section_align_entry
**)
10627 htab_find_slot_with_hash (iris_section_align_htab
, section
,
10628 htab_hash_string (section
), INSERT
);
10632 entry
= (struct iris_section_align_entry
*)
10633 xmalloc (sizeof (struct iris_section_align_entry
));
10635 entry
->name
= section
;
10637 entry
->flags
= current_section_flags ();
10639 else if (entry
->log
< log
)
10642 fprintf (file
, "\t.align\t%u\n", log
);
10645 /* The Iris assembler does not record alignment from .align directives,
10646 but takes it from the first .section directive seen. Play yet more
10647 file switching games so that we can emit a .section directive at the
10648 beginning of the file with the proper alignment attached. */
10651 iris6_asm_file_start (stream
)
10654 mips_asm_file_start (stream
);
10656 iris_orig_asm_out_file
= asm_out_file
;
10657 stream
= tmpfile ();
10658 asm_out_file
= stream
;
10659 asm_out_data_file
= stream
;
10660 if (! TARGET_FILE_SWITCHING
)
10661 asm_out_text_file
= stream
;
10663 iris_section_align_htab
= htab_create (31, iris_section_align_entry_hash
,
10664 iris_section_align_entry_eq
, NULL
);
10668 iris6_section_align_1 (slot
, data
)
10670 void *data ATTRIBUTE_UNUSED
;
10672 const struct iris_section_align_entry
*entry
10673 = *(const struct iris_section_align_entry
**) slot
;
10675 iris6_asm_named_section_1 (entry
->name
, entry
->flags
, 1 << entry
->log
);
10680 iris6_asm_file_end (stream
)
10683 /* Emit section directives with the proper alignment at the top of the
10684 real output file. */
10685 asm_out_file
= iris_orig_asm_out_file
;
10686 htab_traverse (iris_section_align_htab
, iris6_section_align_1
, NULL
);
10688 /* Copy the data emitted to the temp file to the real output file. */
10689 copy_file_data (asm_out_file
, stream
);
10691 mips_asm_file_end (stream
);
10693 #endif /* TARGET_IRIX6 */
10695 #include "gt-mips.h"