1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 #include "diagnostic.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
139 A signed 16-bit constant address.
142 A constant symbolic address. */
143 enum mips_address_type
{
150 /* Macros to create an enumeration identifier for a function prototype. */
151 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
152 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
153 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
154 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
156 /* Classifies the prototype of a built-in function. */
157 enum mips_function_type
{
158 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
159 #include "config/mips/mips-ftypes.def"
160 #undef DEF_MIPS_FTYPE
164 /* Specifies how a built-in function should be converted into rtl. */
165 enum mips_builtin_type
{
166 /* The function corresponds directly to an .md pattern. The return
167 value is mapped to operand 0 and the arguments are mapped to
168 operands 1 and above. */
171 /* The function corresponds directly to an .md pattern. There is no return
172 value and the arguments are mapped to operands 0 and above. */
173 MIPS_BUILTIN_DIRECT_NO_TARGET
,
175 /* The function corresponds to a comparison instruction followed by
176 a mips_cond_move_tf_ps pattern. The first two arguments are the
177 values to compare and the second two arguments are the vector
178 operands for the movt.ps or movf.ps instruction (in assembly order). */
182 /* The function corresponds to a V2SF comparison instruction. Operand 0
183 of this instruction is the result of the comparison, which has mode
184 CCV2 or CCV4. The function arguments are mapped to operands 1 and
185 above. The function's return value is an SImode boolean that is
186 true under the following conditions:
188 MIPS_BUILTIN_CMP_ANY: one of the registers is true
189 MIPS_BUILTIN_CMP_ALL: all of the registers are true
190 MIPS_BUILTIN_CMP_LOWER: the first register is true
191 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
192 MIPS_BUILTIN_CMP_ANY
,
193 MIPS_BUILTIN_CMP_ALL
,
194 MIPS_BUILTIN_CMP_UPPER
,
195 MIPS_BUILTIN_CMP_LOWER
,
197 /* As above, but the instruction only sets a single $fcc register. */
198 MIPS_BUILTIN_CMP_SINGLE
,
200 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
201 MIPS_BUILTIN_BPOSGE32
204 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
205 #define MIPS_FP_CONDITIONS(MACRO) \
223 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
224 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
225 enum mips_fp_condition
{
226 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
229 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
230 #define STRINGIFY(X) #X
231 static const char *const mips_fp_conditions
[] = {
232 MIPS_FP_CONDITIONS (STRINGIFY
)
235 /* Information about a function's frame layout. */
236 struct mips_frame_info
GTY(()) {
237 /* The size of the frame in bytes. */
238 HOST_WIDE_INT total_size
;
240 /* The number of bytes allocated to variables. */
241 HOST_WIDE_INT var_size
;
243 /* The number of bytes allocated to outgoing function arguments. */
244 HOST_WIDE_INT args_size
;
246 /* The number of bytes allocated to the .cprestore slot, or 0 if there
248 HOST_WIDE_INT cprestore_size
;
250 /* Bit X is set if the function saves or restores GPR X. */
253 /* Likewise FPR X. */
256 /* The number of GPRs and FPRs saved. */
260 /* The offset of the topmost GPR and FPR save slots from the top of
261 the frame, or zero if no such slots are needed. */
262 HOST_WIDE_INT gp_save_offset
;
263 HOST_WIDE_INT fp_save_offset
;
265 /* Likewise, but giving offsets from the bottom of the frame. */
266 HOST_WIDE_INT gp_sp_offset
;
267 HOST_WIDE_INT fp_sp_offset
;
269 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
270 HOST_WIDE_INT arg_pointer_offset
;
272 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
273 HOST_WIDE_INT hard_frame_pointer_offset
;
276 struct machine_function
GTY(()) {
277 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
278 rtx mips16_gp_pseudo_rtx
;
280 /* The number of extra stack bytes taken up by register varargs.
281 This area is allocated by the callee at the very top of the frame. */
284 /* The current frame information, calculated by mips_compute_frame_info. */
285 struct mips_frame_info frame
;
287 /* The register to use as the function's global pointer. */
288 unsigned int global_pointer
;
290 /* True if mips_adjust_insn_length should ignore an instruction's
292 bool ignore_hazard_length_p
;
294 /* True if the whole function is suitable for .set noreorder and
296 bool all_noreorder_p
;
298 /* True if the function is known to have an instruction that needs $gp. */
301 /* True if we have emitted an instruction to initialize
302 mips16_gp_pseudo_rtx. */
303 bool initialized_mips16_gp_pseudo_p
;
306 /* Information about a single argument. */
307 struct mips_arg_info
{
308 /* True if the argument is passed in a floating-point register, or
309 would have been if we hadn't run out of registers. */
312 /* The number of words passed in registers, rounded up. */
313 unsigned int reg_words
;
315 /* For EABI, the offset of the first register from GP_ARG_FIRST or
316 FP_ARG_FIRST. For other ABIs, the offset of the first register from
317 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
318 comment for details).
320 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
322 unsigned int reg_offset
;
324 /* The number of words that must be passed on the stack, rounded up. */
325 unsigned int stack_words
;
327 /* The offset from the start of the stack overflow area of the argument's
328 first stack word. Only meaningful when STACK_WORDS is nonzero. */
329 unsigned int stack_offset
;
332 /* Information about an address described by mips_address_type.
338 REG is the base register and OFFSET is the constant offset.
341 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
342 is the type of symbol it references.
345 SYMBOL_TYPE is the type of symbol that the address references. */
346 struct mips_address_info
{
347 enum mips_address_type type
;
350 enum mips_symbol_type symbol_type
;
353 /* One stage in a constant building sequence. These sequences have
357 A = A CODE[1] VALUE[1]
358 A = A CODE[2] VALUE[2]
361 where A is an accumulator, each CODE[i] is a binary rtl operation
362 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
363 struct mips_integer_op
{
365 unsigned HOST_WIDE_INT value
;
368 /* The largest number of operations needed to load an integer constant.
369 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
370 When the lowest bit is clear, we can try, but reject a sequence with
371 an extra SLL at the end. */
372 #define MIPS_MAX_INTEGER_OPS 7
374 /* Information about a MIPS16e SAVE or RESTORE instruction. */
375 struct mips16e_save_restore_info
{
376 /* The number of argument registers saved by a SAVE instruction.
377 0 for RESTORE instructions. */
380 /* Bit X is set if the instruction saves or restores GPR X. */
383 /* The total number of bytes to allocate. */
387 /* Global variables for machine-dependent things. */
389 /* The -G setting, or the configuration's default small-data limit if
390 no -G option is given. */
391 static unsigned int mips_small_data_threshold
;
393 /* The number of file directives written by mips_output_filename. */
394 int num_source_filenames
;
396 /* The name that appeared in the last .file directive written by
397 mips_output_filename, or "" if mips_output_filename hasn't
398 written anything yet. */
399 const char *current_function_file
= "";
401 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
404 /* Arrays that map GCC register numbers to debugger register numbers. */
405 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
406 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
408 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
413 /* True if we're writing out a branch-likely instruction rather than a
415 static bool mips_branch_likely
;
417 /* The operands passed to the last cmpMM expander. */
420 /* The current instruction-set architecture. */
421 enum processor_type mips_arch
;
422 const struct mips_cpu_info
*mips_arch_info
;
424 /* The processor that we should tune the code for. */
425 enum processor_type mips_tune
;
426 const struct mips_cpu_info
*mips_tune_info
;
428 /* The ISA level associated with mips_arch. */
431 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
432 static const struct mips_cpu_info
*mips_isa_option_info
;
434 /* Which ABI to use. */
435 int mips_abi
= MIPS_ABI_DEFAULT
;
437 /* Which cost information to use. */
438 const struct mips_rtx_cost_data
*mips_cost
;
440 /* The ambient target flags, excluding MASK_MIPS16. */
441 static int mips_base_target_flags
;
443 /* True if MIPS16 is the default mode. */
444 static bool mips_base_mips16
;
446 /* The ambient values of other global variables. */
447 static int mips_base_delayed_branch
; /* flag_delayed_branch */
448 static int mips_base_schedule_insns
; /* flag_schedule_insns */
449 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
450 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
451 static int mips_base_align_loops
; /* align_loops */
452 static int mips_base_align_jumps
; /* align_jumps */
453 static int mips_base_align_functions
; /* align_functions */
455 /* The -mcode-readable setting. */
456 enum mips_code_readable_setting mips_code_readable
= CODE_READABLE_YES
;
458 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
459 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
461 /* Index C is true if character C is a valid PRINT_OPERAND punctation
463 bool mips_print_operand_punct
[256];
465 static GTY (()) int mips_output_filename_first_time
= 1;
467 /* mips_split_p[X] is true if symbols of type X can be split by
468 mips_split_symbol. */
469 bool mips_split_p
[NUM_SYMBOL_TYPES
];
471 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
472 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
473 if they are matched by a special .md file pattern. */
474 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
476 /* Likewise for HIGHs. */
477 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
479 /* Index R is the smallest register class that contains register R. */
480 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
481 LEA_REGS
, LEA_REGS
, M16_NA_REGS
, V1_REG
,
482 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
483 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
484 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
485 M16_NA_REGS
, M16_NA_REGS
, LEA_REGS
, LEA_REGS
,
486 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
487 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
488 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
489 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
490 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
491 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
492 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
493 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
494 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
495 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
496 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
497 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
498 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
499 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
500 NO_REGS
, ALL_REGS
, ALL_REGS
, NO_REGS
,
501 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
502 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
503 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
504 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
505 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
506 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
507 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
508 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
509 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
510 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
511 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
512 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
513 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
514 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
515 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
516 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
517 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
518 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
519 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
520 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
521 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
522 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
523 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
524 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
525 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
526 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
527 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
530 /* The value of TARGET_ATTRIBUTE_TABLE. */
531 const struct attribute_spec mips_attribute_table
[] = {
532 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
533 { "long_call", 0, 0, false, true, true, NULL
},
534 { "far", 0, 0, false, true, true, NULL
},
535 { "near", 0, 0, false, true, true, NULL
},
536 /* We would really like to treat "mips16" and "nomips16" as type
537 attributes, but GCC doesn't provide the hooks we need to support
538 the right conversion rules. As declaration attributes, they affect
539 code generation but don't carry other semantics. */
540 { "mips16", 0, 0, true, false, false, NULL
},
541 { "nomips16", 0, 0, true, false, false, NULL
},
542 { NULL
, 0, 0, false, false, false, NULL
}
545 /* A table describing all the processors GCC knows about. Names are
546 matched in the order listed. The first mention of an ISA level is
547 taken as the canonical name for that ISA.
549 To ease comparison, please keep this table in the same order
550 as GAS's mips_cpu_info_table. Please also make sure that
551 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
552 options correctly. */
553 static const struct mips_cpu_info mips_cpu_info_table
[] = {
554 /* Entries for generic ISAs. */
555 { "mips1", PROCESSOR_R3000
, 1, 0 },
556 { "mips2", PROCESSOR_R6000
, 2, 0 },
557 { "mips3", PROCESSOR_R4000
, 3, 0 },
558 { "mips4", PROCESSOR_R8000
, 4, 0 },
559 /* Prefer not to use branch-likely instructions for generic MIPS32rX
560 and MIPS64rX code. The instructions were officially deprecated
561 in revisions 2 and earlier, but revision 3 is likely to downgrade
562 that to a recommendation to avoid the instructions in code that
563 isn't tuned to a specific processor. */
564 { "mips32", PROCESSOR_4KC
, 32, PTF_AVOID_BRANCHLIKELY
},
565 { "mips32r2", PROCESSOR_M4K
, 33, PTF_AVOID_BRANCHLIKELY
},
566 { "mips64", PROCESSOR_5KC
, 64, PTF_AVOID_BRANCHLIKELY
},
568 /* MIPS I processors. */
569 { "r3000", PROCESSOR_R3000
, 1, 0 },
570 { "r2000", PROCESSOR_R3000
, 1, 0 },
571 { "r3900", PROCESSOR_R3900
, 1, 0 },
573 /* MIPS II processors. */
574 { "r6000", PROCESSOR_R6000
, 2, 0 },
576 /* MIPS III processors. */
577 { "r4000", PROCESSOR_R4000
, 3, 0 },
578 { "vr4100", PROCESSOR_R4100
, 3, 0 },
579 { "vr4111", PROCESSOR_R4111
, 3, 0 },
580 { "vr4120", PROCESSOR_R4120
, 3, 0 },
581 { "vr4130", PROCESSOR_R4130
, 3, 0 },
582 { "vr4300", PROCESSOR_R4300
, 3, 0 },
583 { "r4400", PROCESSOR_R4000
, 3, 0 },
584 { "r4600", PROCESSOR_R4600
, 3, 0 },
585 { "orion", PROCESSOR_R4600
, 3, 0 },
586 { "r4650", PROCESSOR_R4650
, 3, 0 },
587 /* ST Loongson 2E/2F processors. */
588 { "loongson2e", PROCESSOR_LOONGSON_2E
, 3, PTF_AVOID_BRANCHLIKELY
},
589 { "loongson2f", PROCESSOR_LOONGSON_2F
, 3, PTF_AVOID_BRANCHLIKELY
},
591 /* MIPS IV processors. */
592 { "r8000", PROCESSOR_R8000
, 4, 0 },
593 { "vr5000", PROCESSOR_R5000
, 4, 0 },
594 { "vr5400", PROCESSOR_R5400
, 4, 0 },
595 { "vr5500", PROCESSOR_R5500
, 4, PTF_AVOID_BRANCHLIKELY
},
596 { "rm7000", PROCESSOR_R7000
, 4, 0 },
597 { "rm9000", PROCESSOR_R9000
, 4, 0 },
599 /* MIPS32 processors. */
600 { "4kc", PROCESSOR_4KC
, 32, 0 },
601 { "4km", PROCESSOR_4KC
, 32, 0 },
602 { "4kp", PROCESSOR_4KP
, 32, 0 },
603 { "4ksc", PROCESSOR_4KC
, 32, 0 },
605 /* MIPS32 Release 2 processors. */
606 { "m4k", PROCESSOR_M4K
, 33, 0 },
607 { "4kec", PROCESSOR_4KC
, 33, 0 },
608 { "4kem", PROCESSOR_4KC
, 33, 0 },
609 { "4kep", PROCESSOR_4KP
, 33, 0 },
610 { "4ksd", PROCESSOR_4KC
, 33, 0 },
612 { "24kc", PROCESSOR_24KC
, 33, 0 },
613 { "24kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
614 { "24kf", PROCESSOR_24KF2_1
, 33, 0 },
615 { "24kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
616 { "24kfx", PROCESSOR_24KF1_1
, 33, 0 },
617 { "24kx", PROCESSOR_24KF1_1
, 33, 0 },
619 { "24kec", PROCESSOR_24KC
, 33, 0 }, /* 24K with DSP. */
620 { "24kef2_1", PROCESSOR_24KF2_1
, 33, 0 },
621 { "24kef", PROCESSOR_24KF2_1
, 33, 0 },
622 { "24kef1_1", PROCESSOR_24KF1_1
, 33, 0 },
623 { "24kefx", PROCESSOR_24KF1_1
, 33, 0 },
624 { "24kex", PROCESSOR_24KF1_1
, 33, 0 },
626 { "34kc", PROCESSOR_24KC
, 33, 0 }, /* 34K with MT/DSP. */
627 { "34kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
628 { "34kf", PROCESSOR_24KF2_1
, 33, 0 },
629 { "34kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
630 { "34kfx", PROCESSOR_24KF1_1
, 33, 0 },
631 { "34kx", PROCESSOR_24KF1_1
, 33, 0 },
633 { "74kc", PROCESSOR_74KC
, 33, 0 }, /* 74K with DSPr2. */
634 { "74kf2_1", PROCESSOR_74KF2_1
, 33, 0 },
635 { "74kf", PROCESSOR_74KF2_1
, 33, 0 },
636 { "74kf1_1", PROCESSOR_74KF1_1
, 33, 0 },
637 { "74kfx", PROCESSOR_74KF1_1
, 33, 0 },
638 { "74kx", PROCESSOR_74KF1_1
, 33, 0 },
639 { "74kf3_2", PROCESSOR_74KF3_2
, 33, 0 },
641 /* MIPS64 processors. */
642 { "5kc", PROCESSOR_5KC
, 64, 0 },
643 { "5kf", PROCESSOR_5KF
, 64, 0 },
644 { "20kc", PROCESSOR_20KC
, 64, PTF_AVOID_BRANCHLIKELY
},
645 { "sb1", PROCESSOR_SB1
, 64, PTF_AVOID_BRANCHLIKELY
},
646 { "sb1a", PROCESSOR_SB1A
, 64, PTF_AVOID_BRANCHLIKELY
},
647 { "sr71000", PROCESSOR_SR71000
, 64, PTF_AVOID_BRANCHLIKELY
},
650 /* Default costs. If these are used for a processor we should look
651 up the actual costs. */
652 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
653 COSTS_N_INSNS (7), /* fp_mult_sf */ \
654 COSTS_N_INSNS (8), /* fp_mult_df */ \
655 COSTS_N_INSNS (23), /* fp_div_sf */ \
656 COSTS_N_INSNS (36), /* fp_div_df */ \
657 COSTS_N_INSNS (10), /* int_mult_si */ \
658 COSTS_N_INSNS (10), /* int_mult_di */ \
659 COSTS_N_INSNS (69), /* int_div_si */ \
660 COSTS_N_INSNS (69), /* int_div_di */ \
661 2, /* branch_cost */ \
662 4 /* memory_latency */
664 /* Floating-point costs for processors without an FPU. Just assume that
665 all floating-point libcalls are very expensive. */
666 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
667 COSTS_N_INSNS (256), /* fp_mult_sf */ \
668 COSTS_N_INSNS (256), /* fp_mult_df */ \
669 COSTS_N_INSNS (256), /* fp_div_sf */ \
670 COSTS_N_INSNS (256) /* fp_div_df */
672 /* Costs to use when optimizing for size. */
673 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
674 COSTS_N_INSNS (1), /* fp_add */
675 COSTS_N_INSNS (1), /* fp_mult_sf */
676 COSTS_N_INSNS (1), /* fp_mult_df */
677 COSTS_N_INSNS (1), /* fp_div_sf */
678 COSTS_N_INSNS (1), /* fp_div_df */
679 COSTS_N_INSNS (1), /* int_mult_si */
680 COSTS_N_INSNS (1), /* int_mult_di */
681 COSTS_N_INSNS (1), /* int_div_si */
682 COSTS_N_INSNS (1), /* int_div_di */
684 4 /* memory_latency */
687 /* Costs to use when optimizing for speed, indexed by processor. */
688 static const struct mips_rtx_cost_data mips_rtx_cost_data
[PROCESSOR_MAX
] = {
690 COSTS_N_INSNS (2), /* fp_add */
691 COSTS_N_INSNS (4), /* fp_mult_sf */
692 COSTS_N_INSNS (5), /* fp_mult_df */
693 COSTS_N_INSNS (12), /* fp_div_sf */
694 COSTS_N_INSNS (19), /* fp_div_df */
695 COSTS_N_INSNS (12), /* int_mult_si */
696 COSTS_N_INSNS (12), /* int_mult_di */
697 COSTS_N_INSNS (35), /* int_div_si */
698 COSTS_N_INSNS (35), /* int_div_di */
700 4 /* memory_latency */
704 COSTS_N_INSNS (6), /* int_mult_si */
705 COSTS_N_INSNS (6), /* int_mult_di */
706 COSTS_N_INSNS (36), /* int_div_si */
707 COSTS_N_INSNS (36), /* int_div_di */
709 4 /* memory_latency */
713 COSTS_N_INSNS (36), /* int_mult_si */
714 COSTS_N_INSNS (36), /* int_mult_di */
715 COSTS_N_INSNS (37), /* int_div_si */
716 COSTS_N_INSNS (37), /* int_div_di */
718 4 /* memory_latency */
722 COSTS_N_INSNS (4), /* int_mult_si */
723 COSTS_N_INSNS (11), /* int_mult_di */
724 COSTS_N_INSNS (36), /* int_div_si */
725 COSTS_N_INSNS (68), /* int_div_di */
727 4 /* memory_latency */
730 COSTS_N_INSNS (4), /* fp_add */
731 COSTS_N_INSNS (4), /* fp_mult_sf */
732 COSTS_N_INSNS (5), /* fp_mult_df */
733 COSTS_N_INSNS (17), /* fp_div_sf */
734 COSTS_N_INSNS (32), /* fp_div_df */
735 COSTS_N_INSNS (4), /* int_mult_si */
736 COSTS_N_INSNS (11), /* int_mult_di */
737 COSTS_N_INSNS (36), /* int_div_si */
738 COSTS_N_INSNS (68), /* int_div_di */
740 4 /* memory_latency */
743 COSTS_N_INSNS (4), /* fp_add */
744 COSTS_N_INSNS (4), /* fp_mult_sf */
745 COSTS_N_INSNS (5), /* fp_mult_df */
746 COSTS_N_INSNS (17), /* fp_div_sf */
747 COSTS_N_INSNS (32), /* fp_div_df */
748 COSTS_N_INSNS (4), /* int_mult_si */
749 COSTS_N_INSNS (7), /* int_mult_di */
750 COSTS_N_INSNS (42), /* int_div_si */
751 COSTS_N_INSNS (72), /* int_div_di */
753 4 /* memory_latency */
757 COSTS_N_INSNS (5), /* int_mult_si */
758 COSTS_N_INSNS (5), /* int_mult_di */
759 COSTS_N_INSNS (41), /* int_div_si */
760 COSTS_N_INSNS (41), /* int_div_di */
762 4 /* memory_latency */
765 COSTS_N_INSNS (8), /* fp_add */
766 COSTS_N_INSNS (8), /* fp_mult_sf */
767 COSTS_N_INSNS (10), /* fp_mult_df */
768 COSTS_N_INSNS (34), /* fp_div_sf */
769 COSTS_N_INSNS (64), /* fp_div_df */
770 COSTS_N_INSNS (5), /* int_mult_si */
771 COSTS_N_INSNS (5), /* int_mult_di */
772 COSTS_N_INSNS (41), /* int_div_si */
773 COSTS_N_INSNS (41), /* int_div_di */
775 4 /* memory_latency */
778 COSTS_N_INSNS (4), /* fp_add */
779 COSTS_N_INSNS (4), /* fp_mult_sf */
780 COSTS_N_INSNS (5), /* fp_mult_df */
781 COSTS_N_INSNS (17), /* fp_div_sf */
782 COSTS_N_INSNS (32), /* fp_div_df */
783 COSTS_N_INSNS (5), /* int_mult_si */
784 COSTS_N_INSNS (5), /* int_mult_di */
785 COSTS_N_INSNS (41), /* int_div_si */
786 COSTS_N_INSNS (41), /* int_div_di */
788 4 /* memory_latency */
792 COSTS_N_INSNS (5), /* int_mult_si */
793 COSTS_N_INSNS (5), /* int_mult_di */
794 COSTS_N_INSNS (41), /* int_div_si */
795 COSTS_N_INSNS (41), /* int_div_di */
797 4 /* memory_latency */
800 COSTS_N_INSNS (8), /* fp_add */
801 COSTS_N_INSNS (8), /* fp_mult_sf */
802 COSTS_N_INSNS (10), /* fp_mult_df */
803 COSTS_N_INSNS (34), /* fp_div_sf */
804 COSTS_N_INSNS (64), /* fp_div_df */
805 COSTS_N_INSNS (5), /* int_mult_si */
806 COSTS_N_INSNS (5), /* int_mult_di */
807 COSTS_N_INSNS (41), /* int_div_si */
808 COSTS_N_INSNS (41), /* int_div_di */
810 4 /* memory_latency */
813 COSTS_N_INSNS (4), /* fp_add */
814 COSTS_N_INSNS (4), /* fp_mult_sf */
815 COSTS_N_INSNS (5), /* fp_mult_df */
816 COSTS_N_INSNS (17), /* fp_div_sf */
817 COSTS_N_INSNS (32), /* fp_div_df */
818 COSTS_N_INSNS (5), /* int_mult_si */
819 COSTS_N_INSNS (5), /* int_mult_di */
820 COSTS_N_INSNS (41), /* int_div_si */
821 COSTS_N_INSNS (41), /* int_div_di */
823 4 /* memory_latency */
826 COSTS_N_INSNS (6), /* fp_add */
827 COSTS_N_INSNS (6), /* fp_mult_sf */
828 COSTS_N_INSNS (7), /* fp_mult_df */
829 COSTS_N_INSNS (25), /* fp_div_sf */
830 COSTS_N_INSNS (48), /* fp_div_df */
831 COSTS_N_INSNS (5), /* int_mult_si */
832 COSTS_N_INSNS (5), /* int_mult_di */
833 COSTS_N_INSNS (41), /* int_div_si */
834 COSTS_N_INSNS (41), /* int_div_di */
836 4 /* memory_latency */
848 COSTS_N_INSNS (2), /* fp_add */
849 COSTS_N_INSNS (4), /* fp_mult_sf */
850 COSTS_N_INSNS (5), /* fp_mult_df */
851 COSTS_N_INSNS (12), /* fp_div_sf */
852 COSTS_N_INSNS (19), /* fp_div_df */
853 COSTS_N_INSNS (2), /* int_mult_si */
854 COSTS_N_INSNS (2), /* int_mult_di */
855 COSTS_N_INSNS (35), /* int_div_si */
856 COSTS_N_INSNS (35), /* int_div_di */
858 4 /* memory_latency */
861 COSTS_N_INSNS (3), /* fp_add */
862 COSTS_N_INSNS (5), /* fp_mult_sf */
863 COSTS_N_INSNS (6), /* fp_mult_df */
864 COSTS_N_INSNS (15), /* fp_div_sf */
865 COSTS_N_INSNS (16), /* fp_div_df */
866 COSTS_N_INSNS (17), /* int_mult_si */
867 COSTS_N_INSNS (17), /* int_mult_di */
868 COSTS_N_INSNS (38), /* int_div_si */
869 COSTS_N_INSNS (38), /* int_div_di */
871 6 /* memory_latency */
874 COSTS_N_INSNS (6), /* fp_add */
875 COSTS_N_INSNS (7), /* fp_mult_sf */
876 COSTS_N_INSNS (8), /* fp_mult_df */
877 COSTS_N_INSNS (23), /* fp_div_sf */
878 COSTS_N_INSNS (36), /* fp_div_df */
879 COSTS_N_INSNS (10), /* int_mult_si */
880 COSTS_N_INSNS (10), /* int_mult_di */
881 COSTS_N_INSNS (69), /* int_div_si */
882 COSTS_N_INSNS (69), /* int_div_di */
884 6 /* memory_latency */
896 /* The only costs that appear to be updated here are
897 integer multiplication. */
899 COSTS_N_INSNS (4), /* int_mult_si */
900 COSTS_N_INSNS (6), /* int_mult_di */
901 COSTS_N_INSNS (69), /* int_div_si */
902 COSTS_N_INSNS (69), /* int_div_di */
904 4 /* memory_latency */
916 COSTS_N_INSNS (6), /* fp_add */
917 COSTS_N_INSNS (4), /* fp_mult_sf */
918 COSTS_N_INSNS (5), /* fp_mult_df */
919 COSTS_N_INSNS (23), /* fp_div_sf */
920 COSTS_N_INSNS (36), /* fp_div_df */
921 COSTS_N_INSNS (5), /* int_mult_si */
922 COSTS_N_INSNS (5), /* int_mult_di */
923 COSTS_N_INSNS (36), /* int_div_si */
924 COSTS_N_INSNS (36), /* int_div_di */
926 4 /* memory_latency */
929 COSTS_N_INSNS (6), /* fp_add */
930 COSTS_N_INSNS (5), /* fp_mult_sf */
931 COSTS_N_INSNS (6), /* fp_mult_df */
932 COSTS_N_INSNS (30), /* fp_div_sf */
933 COSTS_N_INSNS (59), /* fp_div_df */
934 COSTS_N_INSNS (3), /* int_mult_si */
935 COSTS_N_INSNS (4), /* int_mult_di */
936 COSTS_N_INSNS (42), /* int_div_si */
937 COSTS_N_INSNS (74), /* int_div_di */
939 4 /* memory_latency */
942 COSTS_N_INSNS (6), /* fp_add */
943 COSTS_N_INSNS (5), /* fp_mult_sf */
944 COSTS_N_INSNS (6), /* fp_mult_df */
945 COSTS_N_INSNS (30), /* fp_div_sf */
946 COSTS_N_INSNS (59), /* fp_div_df */
947 COSTS_N_INSNS (5), /* int_mult_si */
948 COSTS_N_INSNS (9), /* int_mult_di */
949 COSTS_N_INSNS (42), /* int_div_si */
950 COSTS_N_INSNS (74), /* int_div_di */
952 4 /* memory_latency */
955 /* The only costs that are changed here are
956 integer multiplication. */
957 COSTS_N_INSNS (6), /* fp_add */
958 COSTS_N_INSNS (7), /* fp_mult_sf */
959 COSTS_N_INSNS (8), /* fp_mult_df */
960 COSTS_N_INSNS (23), /* fp_div_sf */
961 COSTS_N_INSNS (36), /* fp_div_df */
962 COSTS_N_INSNS (5), /* int_mult_si */
963 COSTS_N_INSNS (9), /* int_mult_di */
964 COSTS_N_INSNS (69), /* int_div_si */
965 COSTS_N_INSNS (69), /* int_div_di */
967 4 /* memory_latency */
973 /* The only costs that are changed here are
974 integer multiplication. */
975 COSTS_N_INSNS (6), /* fp_add */
976 COSTS_N_INSNS (7), /* fp_mult_sf */
977 COSTS_N_INSNS (8), /* fp_mult_df */
978 COSTS_N_INSNS (23), /* fp_div_sf */
979 COSTS_N_INSNS (36), /* fp_div_df */
980 COSTS_N_INSNS (3), /* int_mult_si */
981 COSTS_N_INSNS (8), /* int_mult_di */
982 COSTS_N_INSNS (69), /* int_div_si */
983 COSTS_N_INSNS (69), /* int_div_di */
985 4 /* memory_latency */
988 /* These costs are the same as the SB-1A below. */
989 COSTS_N_INSNS (4), /* fp_add */
990 COSTS_N_INSNS (4), /* fp_mult_sf */
991 COSTS_N_INSNS (4), /* fp_mult_df */
992 COSTS_N_INSNS (24), /* fp_div_sf */
993 COSTS_N_INSNS (32), /* fp_div_df */
994 COSTS_N_INSNS (3), /* int_mult_si */
995 COSTS_N_INSNS (4), /* int_mult_di */
996 COSTS_N_INSNS (36), /* int_div_si */
997 COSTS_N_INSNS (68), /* int_div_di */
999 4 /* memory_latency */
1002 /* These costs are the same as the SB-1 above. */
1003 COSTS_N_INSNS (4), /* fp_add */
1004 COSTS_N_INSNS (4), /* fp_mult_sf */
1005 COSTS_N_INSNS (4), /* fp_mult_df */
1006 COSTS_N_INSNS (24), /* fp_div_sf */
1007 COSTS_N_INSNS (32), /* fp_div_df */
1008 COSTS_N_INSNS (3), /* int_mult_si */
1009 COSTS_N_INSNS (4), /* int_mult_di */
1010 COSTS_N_INSNS (36), /* int_div_si */
1011 COSTS_N_INSNS (68), /* int_div_di */
1012 1, /* branch_cost */
1013 4 /* memory_latency */
1020 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1021 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1022 struct mflip_mips16_entry
GTY (()) {
1026 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1028 /* Hash table callbacks for mflip_mips16_htab. */
1031 mflip_mips16_htab_hash (const void *entry
)
1033 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1037 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1039 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1040 (const char *) name
) == 0;
1043 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1044 mode, false if it should next add an attribute for the opposite mode. */
1045 static GTY(()) bool mips16_flipper
;
1047 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1048 for -mflip-mips16. Return true if it should use "mips16" and false if
1049 it should use "nomips16". */
1052 mflip_mips16_use_mips16_p (tree decl
)
1054 struct mflip_mips16_entry
*entry
;
1059 /* Use the opposite of the command-line setting for anonymous decls. */
1060 if (!DECL_NAME (decl
))
1061 return !mips_base_mips16
;
1063 if (!mflip_mips16_htab
)
1064 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1065 mflip_mips16_htab_eq
, NULL
);
1067 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1068 hash
= htab_hash_string (name
);
1069 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1070 entry
= (struct mflip_mips16_entry
*) *slot
;
1073 mips16_flipper
= !mips16_flipper
;
1074 entry
= GGC_NEW (struct mflip_mips16_entry
);
1076 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1079 return entry
->mips16_p
;
1082 /* Predicates to test for presence of "near" and "far"/"long_call"
1083 attributes on the given TYPE. */
1086 mips_near_type_p (const_tree type
)
1088 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1092 mips_far_type_p (const_tree type
)
1094 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1095 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1098 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1101 mips_mips16_decl_p (const_tree decl
)
1103 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1107 mips_nomips16_decl_p (const_tree decl
)
1109 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1112 /* Return true if function DECL is a MIPS16 function. Return the ambient
1113 setting if DECL is null. */
1116 mips_use_mips16_mode_p (tree decl
)
1120 /* Nested functions must use the same frame pointer as their
1121 parent and must therefore use the same ISA mode. */
1122 tree parent
= decl_function_context (decl
);
1125 if (mips_mips16_decl_p (decl
))
1127 if (mips_nomips16_decl_p (decl
))
1130 return mips_base_mips16
;
1133 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1136 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1138 /* Disallow mixed near/far attributes. */
1139 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1141 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1146 /* Implement TARGET_INSERT_ATTRIBUTES. */
1149 mips_insert_attributes (tree decl
, tree
*attributes
)
1152 bool mips16_p
, nomips16_p
;
1154 /* Check for "mips16" and "nomips16" attributes. */
1155 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1156 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1157 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1160 error ("%qs attribute only applies to functions", "mips16");
1162 error ("%qs attribute only applies to functions", "nomips16");
1166 mips16_p
|= mips_mips16_decl_p (decl
);
1167 nomips16_p
|= mips_nomips16_decl_p (decl
);
1168 if (mips16_p
|| nomips16_p
)
1170 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1171 if (mips16_p
&& nomips16_p
)
1172 error ("%qs cannot have both %<mips16%> and "
1173 "%<nomips16%> attributes",
1174 IDENTIFIER_POINTER (DECL_NAME (decl
)));
1176 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1178 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1179 "mips16" attribute, arbitrarily pick one. We must pick the same
1180 setting for duplicate declarations of a function. */
1181 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1182 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1187 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1190 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1192 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1193 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1194 error ("%qs redeclared with conflicting %qs attributes",
1195 IDENTIFIER_POINTER (DECL_NAME (newdecl
)), "mips16");
1196 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1197 error ("%qs redeclared with conflicting %qs attributes",
1198 IDENTIFIER_POINTER (DECL_NAME (newdecl
)), "nomips16");
1200 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1201 DECL_ATTRIBUTES (newdecl
));
1204 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1205 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1208 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1210 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1212 *base_ptr
= XEXP (x
, 0);
1213 *offset_ptr
= INTVAL (XEXP (x
, 1));
1222 static unsigned int mips_build_integer (struct mips_integer_op
*,
1223 unsigned HOST_WIDE_INT
);
1225 /* A subroutine of mips_build_integer, with the same interface.
1226 Assume that the final action in the sequence should be a left shift. */
1229 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1231 unsigned int i
, shift
;
1233 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1234 since signed numbers are easier to load than unsigned ones. */
1236 while ((value
& 1) == 0)
1237 value
/= 2, shift
++;
1239 i
= mips_build_integer (codes
, value
);
1240 codes
[i
].code
= ASHIFT
;
1241 codes
[i
].value
= shift
;
1245 /* As for mips_build_shift, but assume that the final action will be
1246 an IOR or PLUS operation. */
1249 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1251 unsigned HOST_WIDE_INT high
;
1254 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1255 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1257 /* The constant is too complex to load with a simple LUI/ORI pair,
1258 so we want to give the recursive call as many trailing zeros as
1259 possible. In this case, we know bit 16 is set and that the
1260 low 16 bits form a negative number. If we subtract that number
1261 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1262 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1263 codes
[i
].code
= PLUS
;
1264 codes
[i
].value
= CONST_LOW_PART (value
);
1268 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1269 bits gives a value with at least 17 trailing zeros. */
1270 i
= mips_build_integer (codes
, high
);
1271 codes
[i
].code
= IOR
;
1272 codes
[i
].value
= value
& 0xffff;
1277 /* Fill CODES with a sequence of rtl operations to load VALUE.
1278 Return the number of operations needed. */
1281 mips_build_integer (struct mips_integer_op
*codes
,
1282 unsigned HOST_WIDE_INT value
)
1284 if (SMALL_OPERAND (value
)
1285 || SMALL_OPERAND_UNSIGNED (value
)
1286 || LUI_OPERAND (value
))
1288 /* The value can be loaded with a single instruction. */
1289 codes
[0].code
= UNKNOWN
;
1290 codes
[0].value
= value
;
1293 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1295 /* Either the constant is a simple LUI/ORI combination or its
1296 lowest bit is set. We don't want to shift in this case. */
1297 return mips_build_lower (codes
, value
);
1299 else if ((value
& 0xffff) == 0)
1301 /* The constant will need at least three actions. The lowest
1302 16 bits are clear, so the final action will be a shift. */
1303 return mips_build_shift (codes
, value
);
1307 /* The final action could be a shift, add or inclusive OR.
1308 Rather than use a complex condition to select the best
1309 approach, try both mips_build_shift and mips_build_lower
1310 and pick the one that gives the shortest sequence.
1311 Note that this case is only used once per constant. */
1312 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1313 unsigned int cost
, alt_cost
;
1315 cost
= mips_build_shift (codes
, value
);
1316 alt_cost
= mips_build_lower (alt_codes
, value
);
1317 if (alt_cost
< cost
)
1319 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1326 /* Return true if X is a thread-local symbol. */
1329 mips_tls_symbol_p (rtx x
)
1331 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1334 /* Return true if SYMBOL_REF X is associated with a global symbol
1335 (in the STB_GLOBAL sense). */
1338 mips_global_symbol_p (const_rtx x
)
1340 const_tree decl
= SYMBOL_REF_DECL (x
);
1343 return !SYMBOL_REF_LOCAL_P (x
);
1345 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1346 or weak symbols. Relocations in the object file will be against
1347 the target symbol, so it's that symbol's binding that matters here. */
1348 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1351 /* Return true if SYMBOL_REF X binds locally. */
1354 mips_symbol_binds_local_p (const_rtx x
)
1356 return (SYMBOL_REF_DECL (x
)
1357 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1358 : SYMBOL_REF_LOCAL_P (x
));
1361 /* Return true if rtx constants of mode MODE should be put into a small
1365 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1367 return (!TARGET_EMBEDDED_DATA
1368 && TARGET_LOCAL_SDATA
1369 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1372 /* Return true if X should not be moved directly into register $25.
1373 We need this because many versions of GAS will treat "la $25,foo" as
1374 part of a call sequence and so allow a global "foo" to be lazily bound. */
1377 mips_dangerous_for_la25_p (rtx x
)
1379 return (!TARGET_EXPLICIT_RELOCS
1381 && GET_CODE (x
) == SYMBOL_REF
1382 && mips_global_symbol_p (x
));
1385 /* Return the method that should be used to access SYMBOL_REF or
1386 LABEL_REF X in context CONTEXT. */
1388 static enum mips_symbol_type
1389 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1392 return SYMBOL_GOT_DISP
;
1394 if (GET_CODE (x
) == LABEL_REF
)
1396 /* LABEL_REFs are used for jump tables as well as text labels.
1397 Only return SYMBOL_PC_RELATIVE if we know the label is in
1398 the text section. */
1399 if (TARGET_MIPS16_SHORT_JUMP_TABLES
)
1400 return SYMBOL_PC_RELATIVE
;
1402 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1403 return SYMBOL_GOT_PAGE_OFST
;
1405 return SYMBOL_ABSOLUTE
;
1408 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1410 if (SYMBOL_REF_TLS_MODEL (x
))
1413 if (CONSTANT_POOL_ADDRESS_P (x
))
1415 if (TARGET_MIPS16_TEXT_LOADS
)
1416 return SYMBOL_PC_RELATIVE
;
1418 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1419 return SYMBOL_PC_RELATIVE
;
1421 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1422 return SYMBOL_GP_RELATIVE
;
1425 /* Do not use small-data accesses for weak symbols; they may end up
1427 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1428 return SYMBOL_GP_RELATIVE
;
1430 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1433 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1435 /* There are three cases to consider:
1437 - o32 PIC (either with or without explicit relocs)
1438 - n32/n64 PIC without explicit relocs
1439 - n32/n64 PIC with explicit relocs
1441 In the first case, both local and global accesses will use an
1442 R_MIPS_GOT16 relocation. We must correctly predict which of
1443 the two semantics (local or global) the assembler and linker
1444 will apply. The choice depends on the symbol's binding rather
1445 than its visibility.
1447 In the second case, the assembler will not use R_MIPS_GOT16
1448 relocations, but it chooses between local and global accesses
1449 in the same way as for o32 PIC.
1451 In the third case we have more freedom since both forms of
1452 access will work for any kind of symbol. However, there seems
1453 little point in doing things differently. */
1454 if (mips_global_symbol_p (x
))
1455 return SYMBOL_GOT_DISP
;
1457 return SYMBOL_GOT_PAGE_OFST
;
1460 if (TARGET_MIPS16_PCREL_LOADS
&& context
!= SYMBOL_CONTEXT_CALL
)
1461 return SYMBOL_FORCE_TO_MEM
;
1463 return SYMBOL_ABSOLUTE
;
1466 /* Classify the base of symbolic expression X, given that X appears in
1469 static enum mips_symbol_type
1470 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1474 split_const (x
, &x
, &offset
);
1475 if (UNSPEC_ADDRESS_P (x
))
1476 return UNSPEC_ADDRESS_TYPE (x
);
1478 return mips_classify_symbol (x
, context
);
1481 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1482 is the alignment in bytes of SYMBOL_REF X. */
1485 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1487 HOST_WIDE_INT align
;
1489 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1490 return IN_RANGE (offset
, 0, align
- 1);
1493 /* Return true if X is a symbolic constant that can be used in context
1494 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1497 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1498 enum mips_symbol_type
*symbol_type
)
1502 split_const (x
, &x
, &offset
);
1503 if (UNSPEC_ADDRESS_P (x
))
1505 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1506 x
= UNSPEC_ADDRESS (x
);
1508 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1510 *symbol_type
= mips_classify_symbol (x
, context
);
1511 if (*symbol_type
== SYMBOL_TLS
)
1517 if (offset
== const0_rtx
)
1520 /* Check whether a nonzero offset is valid for the underlying
1522 switch (*symbol_type
)
1524 case SYMBOL_ABSOLUTE
:
1525 case SYMBOL_FORCE_TO_MEM
:
1526 case SYMBOL_32_HIGH
:
1527 case SYMBOL_64_HIGH
:
1530 /* If the target has 64-bit pointers and the object file only
1531 supports 32-bit symbols, the values of those symbols will be
1532 sign-extended. In this case we can't allow an arbitrary offset
1533 in case the 32-bit value X + OFFSET has a different sign from X. */
1534 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1535 return offset_within_block_p (x
, INTVAL (offset
));
1537 /* In other cases the relocations can handle any offset. */
1540 case SYMBOL_PC_RELATIVE
:
1541 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1542 In this case, we no longer have access to the underlying constant,
1543 but the original symbol-based access was known to be valid. */
1544 if (GET_CODE (x
) == LABEL_REF
)
1549 case SYMBOL_GP_RELATIVE
:
1550 /* Make sure that the offset refers to something within the
1551 same object block. This should guarantee that the final
1552 PC- or GP-relative offset is within the 16-bit limit. */
1553 return offset_within_block_p (x
, INTVAL (offset
));
1555 case SYMBOL_GOT_PAGE_OFST
:
1556 case SYMBOL_GOTOFF_PAGE
:
1557 /* If the symbol is global, the GOT entry will contain the symbol's
1558 address, and we will apply a 16-bit offset after loading it.
1559 If the symbol is local, the linker should provide enough local
1560 GOT entries for a 16-bit offset, but larger offsets may lead
1562 return SMALL_INT (offset
);
1566 /* There is no carry between the HI and LO REL relocations, so the
1567 offset is only valid if we know it won't lead to such a carry. */
1568 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1570 case SYMBOL_GOT_DISP
:
1571 case SYMBOL_GOTOFF_DISP
:
1572 case SYMBOL_GOTOFF_CALL
:
1573 case SYMBOL_GOTOFF_LOADGP
:
1576 case SYMBOL_GOTTPREL
:
1584 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1585 single instruction. We rely on the fact that, in the worst case,
1586 all instructions involved in a MIPS16 address calculation are usually
1590 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1594 case SYMBOL_ABSOLUTE
:
1595 /* When using 64-bit symbols, we need 5 preparatory instructions,
1598 lui $at,%highest(symbol)
1599 daddiu $at,$at,%higher(symbol)
1601 daddiu $at,$at,%hi(symbol)
1604 The final address is then $at + %lo(symbol). With 32-bit
1605 symbols we just need a preparatory LUI for normal mode and
1606 a preparatory LI and SLL for MIPS16. */
1607 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1609 case SYMBOL_GP_RELATIVE
:
1610 /* Treat GP-relative accesses as taking a single instruction on
1611 MIPS16 too; the copy of $gp can often be shared. */
1614 case SYMBOL_PC_RELATIVE
:
1615 /* PC-relative constants can be only be used with ADDIUPC,
1616 DADDIUPC, LWPC and LDPC. */
1617 if (mode
== MAX_MACHINE_MODE
1618 || GET_MODE_SIZE (mode
) == 4
1619 || GET_MODE_SIZE (mode
) == 8)
1622 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1625 case SYMBOL_FORCE_TO_MEM
:
1626 /* LEAs will be converted into constant-pool references by
1628 if (mode
== MAX_MACHINE_MODE
)
1631 /* The constant must be loaded and then dereferenced. */
1634 case SYMBOL_GOT_DISP
:
1635 /* The constant will have to be loaded from the GOT before it
1636 is used in an address. */
1637 if (mode
!= MAX_MACHINE_MODE
)
1642 case SYMBOL_GOT_PAGE_OFST
:
1643 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1644 local/global classification is accurate. The worst cases are:
1646 (1) For local symbols when generating o32 or o64 code. The assembler
1652 ...and the final address will be $at + %lo(symbol).
1654 (2) For global symbols when -mxgot. The assembler will use:
1656 lui $at,%got_hi(symbol)
1659 ...and the final address will be $at + %got_lo(symbol). */
1662 case SYMBOL_GOTOFF_PAGE
:
1663 case SYMBOL_GOTOFF_DISP
:
1664 case SYMBOL_GOTOFF_CALL
:
1665 case SYMBOL_GOTOFF_LOADGP
:
1666 case SYMBOL_32_HIGH
:
1667 case SYMBOL_64_HIGH
:
1673 case SYMBOL_GOTTPREL
:
1676 /* A 16-bit constant formed by a single relocation, or a 32-bit
1677 constant formed from a high 16-bit relocation and a low 16-bit
1678 relocation. Use mips_split_p to determine which. 32-bit
1679 constants need an "lui; addiu" sequence for normal mode and
1680 an "li; sll; addiu" sequence for MIPS16 mode. */
1681 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1684 /* We don't treat a bare TLS symbol as a constant. */
1690 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1691 to load symbols of type TYPE into a register. Return 0 if the given
1692 type of symbol cannot be used as an immediate operand.
1694 Otherwise, return the number of instructions needed to load or store
1695 values of mode MODE to or from addresses of type TYPE. Return 0 if
1696 the given type of symbol is not valid in addresses.
1698 In both cases, treat extended MIPS16 instructions as two instructions. */
1701 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1703 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1706 /* A for_each_rtx callback. Stop the search if *X references a
1707 thread-local symbol. */
1710 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1712 return mips_tls_symbol_p (*x
);
1715 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1718 mips_cannot_force_const_mem (rtx x
)
1724 /* As an optimization, reject constants that mips_legitimize_move
1727 Suppose we have a multi-instruction sequence that loads constant C
1728 into register R. If R does not get allocated a hard register, and
1729 R is used in an operand that allows both registers and memory
1730 references, reload will consider forcing C into memory and using
1731 one of the instruction's memory alternatives. Returning false
1732 here will force it to use an input reload instead. */
1733 if (GET_CODE (x
) == CONST_INT
)
1736 split_const (x
, &base
, &offset
);
1737 if (symbolic_operand (base
, VOIDmode
) && SMALL_INT (offset
))
1741 /* TLS symbols must be computed by mips_legitimize_move. */
1742 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
1748 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1749 constants when we're using a per-function constant pool. */
1752 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
1753 const_rtx x ATTRIBUTE_UNUSED
)
1755 return !TARGET_MIPS16_PCREL_LOADS
;
1758 /* Return true if register REGNO is a valid base register for mode MODE.
1759 STRICT_P is true if REG_OK_STRICT is in effect. */
1762 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
1765 if (!HARD_REGISTER_NUM_P (regno
))
1769 regno
= reg_renumber
[regno
];
1772 /* These fake registers will be eliminated to either the stack or
1773 hard frame pointer, both of which are usually valid base registers.
1774 Reload deals with the cases where the eliminated form isn't valid. */
1775 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
1778 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1779 values, nothing smaller. There are two problems here:
1781 (a) Instantiating virtual registers can introduce new uses of the
1782 stack pointer. If these virtual registers are valid addresses,
1783 the stack pointer should be too.
1785 (b) Most uses of the stack pointer are not made explicit until
1786 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1787 We don't know until that stage whether we'll be eliminating to the
1788 stack pointer (which needs the restriction) or the hard frame
1789 pointer (which doesn't).
1791 All in all, it seems more consistent to only enforce this restriction
1792 during and after reload. */
1793 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
1794 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
1796 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
1799 /* Return true if X is a valid base register for mode MODE.
1800 STRICT_P is true if REG_OK_STRICT is in effect. */
1803 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
1805 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1809 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
1812 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1813 can address a value of mode MODE. */
1816 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
1818 /* Check that X is a signed 16-bit number. */
1819 if (!const_arith_operand (x
, Pmode
))
1822 /* We may need to split multiword moves, so make sure that every word
1824 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1825 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
1831 /* Return true if a LO_SUM can address a value of mode MODE when the
1832 LO_SUM symbol has type SYMBOL_TYPE. */
1835 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
1837 /* Check that symbols of type SYMBOL_TYPE can be used to access values
1839 if (mips_symbol_insns (symbol_type
, mode
) == 0)
1842 /* Check that there is a known low-part relocation. */
1843 if (mips_lo_relocs
[symbol_type
] == NULL
)
1846 /* We may need to split multiword moves, so make sure that each word
1847 can be accessed without inducing a carry. This is mainly needed
1848 for o64, which has historically only guaranteed 64-bit alignment
1849 for 128-bit types. */
1850 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1851 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
1857 /* Return true if X is a valid address for machine mode MODE. If it is,
1858 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
1862 mips_classify_address (struct mips_address_info
*info
, rtx x
,
1863 enum machine_mode mode
, bool strict_p
)
1865 switch (GET_CODE (x
))
1869 info
->type
= ADDRESS_REG
;
1871 info
->offset
= const0_rtx
;
1872 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
1875 info
->type
= ADDRESS_REG
;
1876 info
->reg
= XEXP (x
, 0);
1877 info
->offset
= XEXP (x
, 1);
1878 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
1879 && mips_valid_offset_p (info
->offset
, mode
));
1882 info
->type
= ADDRESS_LO_SUM
;
1883 info
->reg
= XEXP (x
, 0);
1884 info
->offset
= XEXP (x
, 1);
1885 /* We have to trust the creator of the LO_SUM to do something vaguely
1886 sane. Target-independent code that creates a LO_SUM should also
1887 create and verify the matching HIGH. Target-independent code that
1888 adds an offset to a LO_SUM must prove that the offset will not
1889 induce a carry. Failure to do either of these things would be
1890 a bug, and we are not required to check for it here. The MIPS
1891 backend itself should only create LO_SUMs for valid symbolic
1892 constants, with the high part being either a HIGH or a copy
1895 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
1896 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
1897 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
1900 /* Small-integer addresses don't occur very often, but they
1901 are legitimate if $0 is a valid base register. */
1902 info
->type
= ADDRESS_CONST_INT
;
1903 return !TARGET_MIPS16
&& SMALL_INT (x
);
1908 info
->type
= ADDRESS_SYMBOLIC
;
1909 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
1911 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
1912 && !mips_split_p
[info
->symbol_type
]);
1919 /* Return true if X is a legitimate address for a memory operand of mode
1920 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
1923 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
1925 struct mips_address_info addr
;
1927 return mips_classify_address (&addr
, x
, mode
, strict_p
);
1930 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1933 mips_stack_address_p (rtx x
, enum machine_mode mode
)
1935 struct mips_address_info addr
;
1937 return (mips_classify_address (&addr
, x
, mode
, false)
1938 && addr
.type
== ADDRESS_REG
1939 && addr
.reg
== stack_pointer_rtx
);
1942 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
1943 address instruction. Note that such addresses are not considered
1944 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
1945 is so restricted. */
1948 mips_lwxs_address_p (rtx addr
)
1951 && GET_CODE (addr
) == PLUS
1952 && REG_P (XEXP (addr
, 1)))
1954 rtx offset
= XEXP (addr
, 0);
1955 if (GET_CODE (offset
) == MULT
1956 && REG_P (XEXP (offset
, 0))
1957 && GET_CODE (XEXP (offset
, 1)) == CONST_INT
1958 && INTVAL (XEXP (offset
, 1)) == 4)
1964 /* Return true if a value at OFFSET bytes from base register BASE can be
1965 accessed using an unextended MIPS16 instruction. MODE is the mode of
1968 Usually the offset in an unextended instruction is a 5-bit field.
1969 The offset is unsigned and shifted left once for LH and SH, twice
1970 for LW and SW, and so on. An exception is LWSP and SWSP, which have
1971 an 8-bit immediate field that's shifted left twice. */
1974 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
1975 unsigned HOST_WIDE_INT offset
)
1977 if (offset
% GET_MODE_SIZE (mode
) == 0)
1979 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
1980 return offset
< 256U * GET_MODE_SIZE (mode
);
1981 return offset
< 32U * GET_MODE_SIZE (mode
);
1986 /* Return the number of instructions needed to load or store a value
1987 of mode MODE at address X. Return 0 if X isn't valid for MODE.
1988 Assume that multiword moves may need to be split into word moves
1989 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
1992 For MIPS16 code, count extended instructions as two instructions. */
1995 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
1997 struct mips_address_info addr
;
2000 /* BLKmode is used for single unaligned loads and stores and should
2001 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2002 meaningless, so we have to single it out as a special case one way
2004 if (mode
!= BLKmode
&& might_split_p
)
2005 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2009 if (mips_classify_address (&addr
, x
, mode
, false))
2014 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2015 UINTVAL (addr
.offset
)))
2019 case ADDRESS_LO_SUM
:
2020 return TARGET_MIPS16
? factor
* 2 : factor
;
2022 case ADDRESS_CONST_INT
:
2025 case ADDRESS_SYMBOLIC
:
2026 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2031 /* Return the number of instructions needed to load constant X.
2032 Return 0 if X isn't a valid constant. */
2035 mips_const_insns (rtx x
)
2037 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2038 enum mips_symbol_type symbol_type
;
2041 switch (GET_CODE (x
))
2044 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2046 || !mips_split_p
[symbol_type
])
2049 /* This is simply an LUI for normal mode. It is an extended
2050 LI followed by an extended SLL for MIPS16. */
2051 return TARGET_MIPS16
? 4 : 1;
2055 /* Unsigned 8-bit constants can be loaded using an unextended
2056 LI instruction. Unsigned 16-bit constants can be loaded
2057 using an extended LI. Negative constants must be loaded
2058 using LI and then negated. */
2059 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2060 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2061 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2062 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2065 return mips_build_integer (codes
, INTVAL (x
));
2069 /* Allow zeros for normal mode, where we can use $0. */
2070 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2076 /* See if we can refer to X directly. */
2077 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2078 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2080 /* Otherwise try splitting the constant into a base and offset.
2081 16-bit offsets can be added using an extra ADDIU. Larger offsets
2082 must be calculated separately and then added to the base. */
2083 split_const (x
, &x
, &offset
);
2086 int n
= mips_const_insns (x
);
2089 if (SMALL_INT (offset
))
2092 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2099 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2107 /* Return the number of instructions needed to implement INSN,
2108 given that it loads from or stores to MEM. Count extended
2109 MIPS16 instructions as two instructions. */
2112 mips_load_store_insns (rtx mem
, rtx insn
)
2114 enum machine_mode mode
;
2118 gcc_assert (MEM_P (mem
));
2119 mode
= GET_MODE (mem
);
2121 /* Try to prove that INSN does not need to be split. */
2122 might_split_p
= true;
2123 if (GET_MODE_BITSIZE (mode
) == 64)
2125 set
= single_set (insn
);
2126 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2127 might_split_p
= false;
2130 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2133 /* Return the number of instructions needed for an integer division. */
2136 mips_idiv_insns (void)
2141 if (TARGET_CHECK_ZERO_DIV
)
2143 if (GENERATE_DIVIDE_TRAPS
)
2149 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2154 /* Emit a move from SRC to DEST. Assume that the move expanders can
2155 handle all moves if !can_create_pseudo_p (). The distinction is
2156 important because, unlike emit_move_insn, the move expanders know
2157 how to force Pmode objects into the constant pool even when the
2158 constant pool address is not itself legitimate. */
2161 mips_emit_move (rtx dest
, rtx src
)
2163 return (can_create_pseudo_p ()
2164 ? emit_move_insn (dest
, src
)
2165 : emit_move_insn_1 (dest
, src
));
2168 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2171 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2173 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2174 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2177 /* Compute (CODE OP0 OP1) and store the result in a new register
2178 of mode MODE. Return that new register. */
2181 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2185 reg
= gen_reg_rtx (mode
);
2186 mips_emit_binary (code
, reg
, op0
, op1
);
2190 /* Copy VALUE to a register and return that register. If new pseudos
2191 are allowed, copy it into a new register, otherwise use DEST. */
2194 mips_force_temporary (rtx dest
, rtx value
)
2196 if (can_create_pseudo_p ())
2197 return force_reg (Pmode
, value
);
2200 mips_emit_move (dest
, value
);
2205 /* Emit a call sequence with call pattern PATTERN and return the call
2206 instruction itself (which is not necessarily the last instruction
2207 emitted). LAZY_P is true if the call address is lazily-bound. */
2210 mips_emit_call_insn (rtx pattern
, bool lazy_p
)
2214 insn
= emit_call_insn (pattern
);
2216 /* Lazy-binding stubs require $gp to be valid on entry. */
2218 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2222 /* See the comment above load_call<mode> for details. */
2223 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2224 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2225 emit_insn (gen_update_got_version ());
2230 /* Return an instruction that copies $gp into register REG. We want
2231 GCC to treat the register's value as constant, so that its value
2232 can be rematerialized on demand. */
2235 gen_load_const_gp (rtx reg
)
2237 return (Pmode
== SImode
2238 ? gen_load_const_gp_si (reg
)
2239 : gen_load_const_gp_di (reg
));
2242 /* Return a pseudo register that contains the value of $gp throughout
2243 the current function. Such registers are needed by MIPS16 functions,
2244 for which $gp itself is not a valid base register or addition operand. */
2247 mips16_gp_pseudo_reg (void)
2249 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2250 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2252 /* Don't emit an instruction to initialize the pseudo register if
2253 we are being called from the tree optimizers' cost-calculation
2255 if (!cfun
->machine
->initialized_mips16_gp_pseudo_p
2256 && (current_ir_type () != IR_GIMPLE
|| currently_expanding_to_rtl
))
2258 rtx insn
, scan
, after
;
2260 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2262 push_topmost_sequence ();
2263 /* We need to emit the initialization after the FUNCTION_BEG
2264 note, so that it will be integrated. */
2265 after
= get_insns ();
2266 for (scan
= after
; scan
!= NULL_RTX
; scan
= NEXT_INSN (scan
))
2267 if (NOTE_P (scan
) && NOTE_KIND (scan
) == NOTE_INSN_FUNCTION_BEG
)
2272 insn
= emit_insn_after (insn
, after
);
2273 pop_topmost_sequence ();
2275 cfun
->machine
->initialized_mips16_gp_pseudo_p
= true;
2278 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2281 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2282 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2283 constant in that context and can be split into a high part and a LO_SUM.
2284 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2285 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2287 TEMP is as for mips_force_temporary and is used to load the high
2288 part into a register. */
2291 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*lo_sum_out
)
2293 enum mips_symbol_context context
;
2294 enum mips_symbol_type symbol_type
;
2297 context
= (mode
== MAX_MACHINE_MODE
2298 ? SYMBOL_CONTEXT_LEA
2299 : SYMBOL_CONTEXT_MEM
);
2300 if (!mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2301 || mips_symbol_insns (symbol_type
, mode
) == 0
2302 || !mips_split_p
[symbol_type
])
2307 if (symbol_type
== SYMBOL_GP_RELATIVE
)
2309 if (!can_create_pseudo_p ())
2311 emit_insn (gen_load_const_gp (temp
));
2315 high
= mips16_gp_pseudo_reg ();
2319 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2320 high
= mips_force_temporary (temp
, high
);
2322 *lo_sum_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2327 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2328 then add CONST_INT OFFSET to the result. */
2331 mips_unspec_address_offset (rtx base
, rtx offset
,
2332 enum mips_symbol_type symbol_type
)
2334 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2335 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2336 if (offset
!= const0_rtx
)
2337 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2338 return gen_rtx_CONST (Pmode
, base
);
2341 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2342 type SYMBOL_TYPE. */
2345 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2349 split_const (address
, &base
, &offset
);
2350 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2353 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2354 high part to BASE and return the result. Just return BASE otherwise.
2355 TEMP is as for mips_force_temporary.
2357 The returned expression can be used as the first operand to a LO_SUM. */
2360 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2361 enum mips_symbol_type symbol_type
)
2363 if (mips_split_p
[symbol_type
])
2365 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2366 addr
= mips_force_temporary (temp
, addr
);
2367 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2372 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2373 mips_force_temporary; it is only needed when OFFSET is not a
2377 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2379 if (!SMALL_OPERAND (offset
))
2385 /* Load the full offset into a register so that we can use
2386 an unextended instruction for the address itself. */
2387 high
= GEN_INT (offset
);
2392 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2393 high
= GEN_INT (CONST_HIGH_PART (offset
));
2394 offset
= CONST_LOW_PART (offset
);
2396 high
= mips_force_temporary (temp
, high
);
2397 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2399 return plus_constant (reg
, offset
);
2402 /* The __tls_get_attr symbol. */
2403 static GTY(()) rtx mips_tls_symbol
;
2405 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2406 the TLS symbol we are referencing and TYPE is the symbol type to use
2407 (either global dynamic or local dynamic). V0 is an RTX for the
2408 return value location. */
2411 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2415 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2417 if (!mips_tls_symbol
)
2418 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2420 loc
= mips_unspec_address (sym
, type
);
2424 emit_insn (gen_rtx_SET (Pmode
, a0
,
2425 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2426 insn
= mips_expand_call (v0
, mips_tls_symbol
, const0_rtx
, const0_rtx
, false);
2427 RTL_CONST_CALL_P (insn
) = 1;
2428 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2429 insn
= get_insns ();
2436 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2437 its address. The return value will be both a valid address and a valid
2438 SET_SRC (either a REG or a LO_SUM). */
2441 mips_legitimize_tls_address (rtx loc
)
2443 rtx dest
, insn
, v0
, v1
, tmp1
, tmp2
, eqv
;
2444 enum tls_model model
;
2448 sorry ("MIPS16 TLS");
2449 return gen_reg_rtx (Pmode
);
2452 model
= SYMBOL_REF_TLS_MODEL (loc
);
2453 /* Only TARGET_ABICALLS code can have more than one module; other
2454 code must be be static and should not use a GOT. All TLS models
2455 reduce to local exec in this situation. */
2456 if (!TARGET_ABICALLS
)
2457 model
= TLS_MODEL_LOCAL_EXEC
;
2461 case TLS_MODEL_GLOBAL_DYNAMIC
:
2462 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2463 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2464 dest
= gen_reg_rtx (Pmode
);
2465 emit_libcall_block (insn
, dest
, v0
, loc
);
2468 case TLS_MODEL_LOCAL_DYNAMIC
:
2469 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2470 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2471 tmp1
= gen_reg_rtx (Pmode
);
2473 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2474 share the LDM result with other LD model accesses. */
2475 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2477 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2479 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2480 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2481 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2484 case TLS_MODEL_INITIAL_EXEC
:
2485 v1
= gen_rtx_REG (Pmode
, GP_RETURN
+ 1);
2486 tmp1
= gen_reg_rtx (Pmode
);
2487 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2488 if (Pmode
== DImode
)
2490 emit_insn (gen_tls_get_tp_di (v1
));
2491 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2495 emit_insn (gen_tls_get_tp_si (v1
));
2496 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2498 dest
= gen_reg_rtx (Pmode
);
2499 emit_insn (gen_add3_insn (dest
, tmp1
, v1
));
2502 case TLS_MODEL_LOCAL_EXEC
:
2503 v1
= gen_rtx_REG (Pmode
, GP_RETURN
+ 1);
2504 if (Pmode
== DImode
)
2505 emit_insn (gen_tls_get_tp_di (v1
));
2507 emit_insn (gen_tls_get_tp_si (v1
));
2509 tmp1
= mips_unspec_offset_high (NULL
, v1
, loc
, SYMBOL_TPREL
);
2510 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2511 mips_unspec_address (loc
, SYMBOL_TPREL
));
2520 /* If X is not a valid address for mode MODE, force it into a register. */
2523 mips_force_address (rtx x
, enum machine_mode mode
)
2525 if (!mips_legitimate_address_p (mode
, x
, false))
2526 x
= force_reg (Pmode
, x
);
2530 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2531 be legitimized in a way that the generic machinery might not expect,
2532 put the new address in *XLOC and return true. MODE is the mode of
2533 the memory being accessed. */
2536 mips_legitimize_address (rtx
*xloc
, enum machine_mode mode
)
2539 HOST_WIDE_INT offset
;
2541 if (mips_tls_symbol_p (*xloc
))
2543 *xloc
= mips_legitimize_tls_address (*xloc
);
2547 /* See if the address can split into a high part and a LO_SUM. */
2548 if (mips_split_symbol (NULL
, *xloc
, mode
, &addr
))
2550 *xloc
= mips_force_address (addr
, mode
);
2554 /* Handle BASE + OFFSET using mips_add_offset. */
2555 mips_split_plus (*xloc
, &base
, &offset
);
2558 if (!mips_valid_base_register_p (base
, mode
, false))
2559 base
= copy_to_mode_reg (Pmode
, base
);
2560 addr
= mips_add_offset (NULL
, base
, offset
);
2561 *xloc
= mips_force_address (addr
, mode
);
2567 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2570 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
2572 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2573 enum machine_mode mode
;
2574 unsigned int i
, num_ops
;
2577 mode
= GET_MODE (dest
);
2578 num_ops
= mips_build_integer (codes
, value
);
2580 /* Apply each binary operation to X. Invariant: X is a legitimate
2581 source operand for a SET pattern. */
2582 x
= GEN_INT (codes
[0].value
);
2583 for (i
= 1; i
< num_ops
; i
++)
2585 if (!can_create_pseudo_p ())
2587 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
2591 x
= force_reg (mode
, x
);
2592 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
2595 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
2598 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2599 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2603 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
2607 /* Split moves of big integers into smaller pieces. */
2608 if (splittable_const_int_operand (src
, mode
))
2610 mips_move_integer (dest
, dest
, INTVAL (src
));
2614 /* Split moves of symbolic constants into high/low pairs. */
2615 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
2617 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
2621 /* Generate the appropriate access sequences for TLS symbols. */
2622 if (mips_tls_symbol_p (src
))
2624 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
2628 /* If we have (const (plus symbol offset)), and that expression cannot
2629 be forced into memory, load the symbol first and add in the offset.
2630 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2631 forced into memory, as it usually produces better code. */
2632 split_const (src
, &base
, &offset
);
2633 if (offset
!= const0_rtx
2634 && (targetm
.cannot_force_const_mem (src
)
2635 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
2637 base
= mips_force_temporary (dest
, base
);
2638 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
2642 src
= force_const_mem (mode
, src
);
2644 /* When using explicit relocs, constant pool references are sometimes
2645 not legitimate addresses. */
2646 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
2647 mips_emit_move (dest
, src
);
2650 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2651 sequence that is valid. */
2654 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
2656 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
2658 mips_emit_move (dest
, force_reg (mode
, src
));
2662 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2663 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
2664 && REG_P (src
) && MD_REG_P (REGNO (src
))
2665 && REG_P (dest
) && GP_REG_P (REGNO (dest
)))
2667 int other_regno
= REGNO (src
) == HI_REGNUM
? LO_REGNUM
: HI_REGNUM
;
2668 if (GET_MODE_SIZE (mode
) <= 4)
2669 emit_insn (gen_mfhilo_si (gen_lowpart (SImode
, dest
),
2670 gen_lowpart (SImode
, src
),
2671 gen_rtx_REG (SImode
, other_regno
)));
2673 emit_insn (gen_mfhilo_di (gen_lowpart (DImode
, dest
),
2674 gen_lowpart (DImode
, src
),
2675 gen_rtx_REG (DImode
, other_regno
)));
2679 /* We need to deal with constants that would be legitimate
2680 immediate_operands but aren't legitimate move_operands. */
2681 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
2683 mips_legitimize_const_move (mode
, dest
, src
);
2684 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
2690 /* Return true if value X in context CONTEXT is a small-data address
2691 that can be rewritten as a LO_SUM. */
2694 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
2696 enum mips_symbol_type symbol_type
;
2698 return (TARGET_EXPLICIT_RELOCS
2699 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
2700 && symbol_type
== SYMBOL_GP_RELATIVE
);
2703 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2704 containing MEM, or null if none. */
2707 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
2709 enum mips_symbol_context context
;
2711 if (GET_CODE (*loc
) == LO_SUM
)
2716 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
2721 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
2722 return mips_rewrite_small_data_p (*loc
, context
);
2725 /* Return true if OP refers to small data symbols directly, not through
2729 mips_small_data_pattern_p (rtx op
)
2731 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
2734 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2735 DATA is the containing MEM, or null if none. */
2738 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
2740 enum mips_symbol_context context
;
2744 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
2748 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
2749 if (mips_rewrite_small_data_p (*loc
, context
))
2750 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
2752 if (GET_CODE (*loc
) == LO_SUM
)
2758 /* Rewrite instruction pattern PATTERN so that it refers to small data
2759 using explicit relocations. */
2762 mips_rewrite_small_data (rtx pattern
)
2764 pattern
= copy_insn (pattern
);
2765 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
2769 /* We need a lot of little routines to check the range of MIPS16 immediate
2773 m16_check_op (rtx op
, int low
, int high
, int mask
)
2775 return (GET_CODE (op
) == CONST_INT
2776 && IN_RANGE (INTVAL (op
), low
, high
)
2777 && (INTVAL (op
) & mask
) == 0);
2781 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2783 return m16_check_op (op
, 0x1, 0x8, 0);
2787 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2789 return m16_check_op (op
, -0x8, 0x7, 0);
2793 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2795 return m16_check_op (op
, -0x7, 0x8, 0);
2799 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2801 return m16_check_op (op
, -0x10, 0xf, 0);
2805 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2807 return m16_check_op (op
, -0xf, 0x10, 0);
2811 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2813 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
2817 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2819 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
2823 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2825 return m16_check_op (op
, -0x80, 0x7f, 0);
2829 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2831 return m16_check_op (op
, -0x7f, 0x80, 0);
2835 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2837 return m16_check_op (op
, 0x0, 0xff, 0);
2841 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2843 return m16_check_op (op
, -0xff, 0x0, 0);
2847 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2849 return m16_check_op (op
, -0x1, 0xfe, 0);
2853 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2855 return m16_check_op (op
, 0x0, 0xff << 2, 3);
2859 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2861 return m16_check_op (op
, -0xff << 2, 0x0, 3);
2865 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2867 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
2871 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
2873 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
2876 /* The cost of loading values from the constant pool. It should be
2877 larger than the cost of any constant we want to synthesize inline. */
2878 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2880 /* Return the cost of X when used as an operand to the MIPS16 instruction
2881 that implements CODE. Return -1 if there is no such instruction, or if
2882 X is not a valid immediate operand for it. */
2885 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
2892 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2893 other shifts are extended. The shift patterns truncate the shift
2894 count to the right size, so there are no out-of-range values. */
2895 if (IN_RANGE (x
, 1, 8))
2897 return COSTS_N_INSNS (1);
2900 if (IN_RANGE (x
, -128, 127))
2902 if (SMALL_OPERAND (x
))
2903 return COSTS_N_INSNS (1);
2907 /* Like LE, but reject the always-true case. */
2911 /* We add 1 to the immediate and use SLT. */
2914 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2917 if (IN_RANGE (x
, 0, 255))
2919 if (SMALL_OPERAND_UNSIGNED (x
))
2920 return COSTS_N_INSNS (1);
2925 /* Equality comparisons with 0 are cheap. */
2935 /* Return true if there is a non-MIPS16 instruction that implements CODE
2936 and if that instruction accepts X as an immediate operand. */
2939 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
2946 /* All shift counts are truncated to a valid constant. */
2951 /* Likewise rotates, if the target supports rotates at all. */
2957 /* These instructions take 16-bit unsigned immediates. */
2958 return SMALL_OPERAND_UNSIGNED (x
);
2963 /* These instructions take 16-bit signed immediates. */
2964 return SMALL_OPERAND (x
);
2970 /* The "immediate" forms of these instructions are really
2971 implemented as comparisons with register 0. */
2976 /* Likewise, meaning that the only valid immediate operand is 1. */
2980 /* We add 1 to the immediate and use SLT. */
2981 return SMALL_OPERAND (x
+ 1);
2984 /* Likewise SLTU, but reject the always-true case. */
2985 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
2989 /* The bit position and size are immediate operands. */
2990 return ISA_HAS_EXT_INS
;
2993 /* By default assume that $0 can be used for 0. */
2998 /* Return the cost of binary operation X, given that the instruction
2999 sequence for a word-sized or smaller operation has cost SINGLE_COST
3000 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3003 mips_binary_cost (rtx x
, int single_cost
, int double_cost
)
3007 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3012 + rtx_cost (XEXP (x
, 0), 0)
3013 + rtx_cost (XEXP (x
, 1), GET_CODE (x
)));
3016 /* Return the cost of floating-point multiplications of mode MODE. */
3019 mips_fp_mult_cost (enum machine_mode mode
)
3021 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3024 /* Return the cost of floating-point divisions of mode MODE. */
3027 mips_fp_div_cost (enum machine_mode mode
)
3029 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3032 /* Return the cost of sign-extending OP to mode MODE, not including the
3033 cost of OP itself. */
3036 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3039 /* Extended loads are as cheap as unextended ones. */
3042 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3043 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3046 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3047 /* We can use SEB or SEH. */
3048 return COSTS_N_INSNS (1);
3050 /* We need to use a shift left and a shift right. */
3051 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3054 /* Return the cost of zero-extending OP to mode MODE, not including the
3055 cost of OP itself. */
3058 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3061 /* Extended loads are as cheap as unextended ones. */
3064 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3065 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3066 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3068 if (GENERATE_MIPS16E
)
3069 /* We can use ZEB or ZEH. */
3070 return COSTS_N_INSNS (1);
3073 /* We need to load 0xff or 0xffff into a register and use AND. */
3074 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3076 /* We can use ANDI. */
3077 return COSTS_N_INSNS (1);
3080 /* Implement TARGET_RTX_COSTS. */
3083 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
3085 enum machine_mode mode
= GET_MODE (x
);
3086 bool float_mode_p
= FLOAT_MODE_P (mode
);
3090 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3091 appear in the instruction stream, and the cost of a comparison is
3092 really the cost of the branch or scc condition. At the time of
3093 writing, GCC only uses an explicit outer COMPARE code when optabs
3094 is testing whether a constant is expensive enough to force into a
3095 register. We want optabs to pass such constants through the MIPS
3096 expanders instead, so make all constants very cheap here. */
3097 if (outer_code
== COMPARE
)
3099 gcc_assert (CONSTANT_P (x
));
3107 /* Treat *clear_upper32-style ANDs as having zero cost in the
3108 second operand. The cost is entirely in the first operand.
3110 ??? This is needed because we would otherwise try to CSE
3111 the constant operand. Although that's the right thing for
3112 instructions that continue to be a register operation throughout
3113 compilation, it is disastrous for instructions that could
3114 later be converted into a memory operation. */
3116 && outer_code
== AND
3117 && UINTVAL (x
) == 0xffffffff)
3125 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3134 /* When not optimizing for size, we care more about the cost
3135 of hot code, and hot code is often in a loop. If a constant
3136 operand needs to be forced into a register, we will often be
3137 able to hoist the constant load out of the loop, so the load
3138 should not contribute to the cost. */
3140 || mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3152 if (force_to_mem_operand (x
, VOIDmode
))
3154 *total
= COSTS_N_INSNS (1);
3157 cost
= mips_const_insns (x
);
3160 /* If the constant is likely to be stored in a GPR, SETs of
3161 single-insn constants are as cheap as register sets; we
3162 never want to CSE them.
3164 Don't reduce the cost of storing a floating-point zero in
3165 FPRs. If we have a zero in an FPR for other reasons, we
3166 can get better cfg-cleanup and delayed-branch results by
3167 using it consistently, rather than using $0 sometimes and
3168 an FPR at other times. Also, moves between floating-point
3169 registers are sometimes cheaper than (D)MTC1 $0. */
3171 && outer_code
== SET
3172 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3174 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3175 want to CSE the constant itself. It is usually better to
3176 have N copies of the last operation in the sequence and one
3177 shared copy of the other operations. (Note that this is
3178 not true for MIPS16 code, where the final operation in the
3179 sequence is often an extended instruction.)
3181 Also, if we have a CONST_INT, we don't know whether it is
3182 for a word or doubleword operation, so we cannot rely on
3183 the result of mips_build_integer. */
3184 else if (!TARGET_MIPS16
3185 && (outer_code
== SET
|| mode
== VOIDmode
))
3187 *total
= COSTS_N_INSNS (cost
);
3190 /* The value will need to be fetched from the constant pool. */
3191 *total
= CONSTANT_POOL_COST
;
3195 /* If the address is legitimate, return the number of
3196 instructions it needs. */
3198 cost
= mips_address_insns (addr
, mode
, true);
3201 *total
= COSTS_N_INSNS (cost
+ 1);
3204 /* Check for a scaled indexed address. */
3205 if (mips_lwxs_address_p (addr
))
3207 *total
= COSTS_N_INSNS (2);
3210 /* Otherwise use the default handling. */
3214 *total
= COSTS_N_INSNS (6);
3218 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3222 /* Check for a *clear_upper32 pattern and treat it like a zero
3223 extension. See the pattern's comment for details. */
3226 && CONST_INT_P (XEXP (x
, 1))
3227 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3229 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3230 + rtx_cost (XEXP (x
, 0), 0));
3237 /* Double-word operations use two single-word operations. */
3238 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3246 if (CONSTANT_P (XEXP (x
, 1)))
3247 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3249 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3254 *total
= mips_cost
->fp_add
;
3256 *total
= COSTS_N_INSNS (4);
3260 /* Low-part immediates need an extended MIPS16 instruction. */
3261 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3262 + rtx_cost (XEXP (x
, 0), 0));
3277 /* Branch comparisons have VOIDmode, so use the first operand's
3279 mode
= GET_MODE (XEXP (x
, 0));
3280 if (FLOAT_MODE_P (mode
))
3282 *total
= mips_cost
->fp_add
;
3285 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3290 && ISA_HAS_NMADD_NMSUB (mode
)
3291 && TARGET_FUSED_MADD
3292 && !HONOR_NANS (mode
)
3293 && !HONOR_SIGNED_ZEROS (mode
))
3295 /* See if we can use NMADD or NMSUB. See mips.md for the
3296 associated patterns. */
3297 rtx op0
= XEXP (x
, 0);
3298 rtx op1
= XEXP (x
, 1);
3299 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3301 *total
= (mips_fp_mult_cost (mode
)
3302 + rtx_cost (XEXP (XEXP (op0
, 0), 0), 0)
3303 + rtx_cost (XEXP (op0
, 1), 0)
3304 + rtx_cost (op1
, 0));
3307 if (GET_CODE (op1
) == MULT
)
3309 *total
= (mips_fp_mult_cost (mode
)
3311 + rtx_cost (XEXP (op1
, 0), 0)
3312 + rtx_cost (XEXP (op1
, 1), 0));
3321 /* If this is part of a MADD or MSUB, treat the PLUS as
3324 && TARGET_FUSED_MADD
3325 && GET_CODE (XEXP (x
, 0)) == MULT
)
3328 *total
= mips_cost
->fp_add
;
3332 /* Double-word operations require three single-word operations and
3333 an SLTU. The MIPS16 version then needs to move the result of
3334 the SLTU from $24 to a MIPS16 register. */
3335 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3336 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4));
3341 && ISA_HAS_NMADD_NMSUB (mode
)
3342 && TARGET_FUSED_MADD
3343 && !HONOR_NANS (mode
)
3344 && HONOR_SIGNED_ZEROS (mode
))
3346 /* See if we can use NMADD or NMSUB. See mips.md for the
3347 associated patterns. */
3348 rtx op
= XEXP (x
, 0);
3349 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3350 && GET_CODE (XEXP (op
, 0)) == MULT
)
3352 *total
= (mips_fp_mult_cost (mode
)
3353 + rtx_cost (XEXP (XEXP (op
, 0), 0), 0)
3354 + rtx_cost (XEXP (XEXP (op
, 0), 1), 0)
3355 + rtx_cost (XEXP (op
, 1), 0));
3361 *total
= mips_cost
->fp_add
;
3363 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3368 *total
= mips_fp_mult_cost (mode
);
3369 else if (mode
== DImode
&& !TARGET_64BIT
)
3370 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3371 where the mulsidi3 always includes an MFHI and an MFLO. */
3372 *total
= (optimize_size
3373 ? COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9)
3374 : mips_cost
->int_mult_si
* 3 + 6);
3375 else if (optimize_size
)
3376 *total
= (ISA_HAS_MUL3
? 1 : 2);
3377 else if (mode
== DImode
)
3378 *total
= mips_cost
->int_mult_di
;
3380 *total
= mips_cost
->int_mult_si
;
3384 /* Check for a reciprocal. */
3387 && flag_unsafe_math_optimizations
3388 && XEXP (x
, 0) == CONST1_RTX (mode
))
3390 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3391 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3392 division as being free. */
3393 *total
= rtx_cost (XEXP (x
, 1), 0);
3395 *total
= mips_fp_div_cost (mode
) + rtx_cost (XEXP (x
, 1), 0);
3404 *total
= mips_fp_div_cost (mode
);
3413 /* It is our responsibility to make division by a power of 2
3414 as cheap as 2 register additions if we want the division
3415 expanders to be used for such operations; see the setting
3416 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3417 should always produce shorter code than using
3418 expand_sdiv2_pow2. */
3420 && CONST_INT_P (XEXP (x
, 1))
3421 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3423 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), 0);
3426 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3428 else if (mode
== DImode
)
3429 *total
= mips_cost
->int_div_di
;
3431 *total
= mips_cost
->int_div_si
;
3435 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3439 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3443 case UNSIGNED_FLOAT
:
3446 case FLOAT_TRUNCATE
:
3447 *total
= mips_cost
->fp_add
;
3455 /* Implement TARGET_ADDRESS_COST. */
3458 mips_address_cost (rtx addr
)
3460 return mips_address_insns (addr
, SImode
, false);
3463 /* Return one word of double-word value OP, taking into account the fixed
3464 endianness of certain registers. HIGH_P is true to select the high part,
3465 false to select the low part. */
3468 mips_subword (rtx op
, bool high_p
)
3470 unsigned int byte
, offset
;
3471 enum machine_mode mode
;
3473 mode
= GET_MODE (op
);
3474 if (mode
== VOIDmode
)
3477 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
3478 byte
= UNITS_PER_WORD
;
3482 if (FP_REG_RTX_P (op
))
3484 /* Paired FPRs are always ordered little-endian. */
3485 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
3486 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
3490 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
3492 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
3495 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3498 mips_split_64bit_move_p (rtx dest
, rtx src
)
3503 /* FPR-to-FPR moves can be done in a single instruction, if they're
3505 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
3508 /* Check for floating-point loads and stores. */
3509 if (ISA_HAS_LDC1_SDC1
)
3511 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
3513 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
3519 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3520 this function handles 64-bit moves for which mips_split_64bit_move_p
3521 holds. For 64-bit targets, this function handles 128-bit moves. */
3524 mips_split_doubleword_move (rtx dest
, rtx src
)
3526 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
3528 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
3529 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
3530 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
3531 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
3532 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
3533 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
3534 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
3535 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
3541 /* The operation can be split into two normal moves. Decide in
3542 which order to do them. */
3545 low_dest
= mips_subword (dest
, false);
3546 if (REG_P (low_dest
)
3547 && reg_overlap_mentioned_p (low_dest
, src
))
3549 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
3550 mips_emit_move (low_dest
, mips_subword (src
, false));
3554 mips_emit_move (low_dest
, mips_subword (src
, false));
3555 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
3560 /* Return the appropriate instructions to move SRC into DEST. Assume
3561 that SRC is operand 1 and DEST is operand 0. */
3564 mips_output_move (rtx dest
, rtx src
)
3566 enum rtx_code dest_code
, src_code
;
3567 enum machine_mode mode
;
3568 enum mips_symbol_type symbol_type
;
3571 dest_code
= GET_CODE (dest
);
3572 src_code
= GET_CODE (src
);
3573 mode
= GET_MODE (dest
);
3574 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
3576 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
3579 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
3580 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
3582 if (dest_code
== REG
)
3584 if (GP_REG_P (REGNO (dest
)))
3585 return "move\t%0,%z1";
3587 if (MD_REG_P (REGNO (dest
)))
3590 if (DSP_ACC_REG_P (REGNO (dest
)))
3592 static char retval
[] = "mt__\t%z1,%q0";
3594 retval
[2] = reg_names
[REGNO (dest
)][4];
3595 retval
[3] = reg_names
[REGNO (dest
)][5];
3599 if (FP_REG_P (REGNO (dest
)))
3600 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3602 if (ALL_COP_REG_P (REGNO (dest
)))
3604 static char retval
[] = "dmtc_\t%z1,%0";
3606 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
3607 return dbl_p
? retval
: retval
+ 1;
3610 if (dest_code
== MEM
)
3611 return dbl_p
? "sd\t%z1,%0" : "sw\t%z1,%0";
3613 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
3615 if (src_code
== REG
)
3617 /* Handled by separate patterns. */
3618 gcc_assert (!MD_REG_P (REGNO (src
)));
3620 if (DSP_ACC_REG_P (REGNO (src
)))
3622 static char retval
[] = "mf__\t%0,%q1";
3624 retval
[2] = reg_names
[REGNO (src
)][4];
3625 retval
[3] = reg_names
[REGNO (src
)][5];
3629 if (FP_REG_P (REGNO (src
)))
3630 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3632 if (ALL_COP_REG_P (REGNO (src
)))
3634 static char retval
[] = "dmfc_\t%0,%1";
3636 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
3637 return dbl_p
? retval
: retval
+ 1;
3640 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
3641 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3644 if (src_code
== MEM
)
3645 return dbl_p
? "ld\t%0,%1" : "lw\t%0,%1";
3647 if (src_code
== CONST_INT
)
3649 /* Don't use the X format for the operand itself, because that
3650 will give out-of-range numbers for 64-bit hosts and 32-bit
3653 return "li\t%0,%1\t\t\t# %X1";
3655 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
3658 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
3662 if (src_code
== HIGH
)
3663 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
3665 if (CONST_GP_P (src
))
3666 return "move\t%0,%1";
3668 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
3669 && mips_lo_relocs
[symbol_type
] != 0)
3671 /* A signed 16-bit constant formed by applying a relocation
3672 operator to a symbolic address. */
3673 gcc_assert (!mips_split_p
[symbol_type
]);
3674 return "li\t%0,%R1";
3677 if (symbolic_operand (src
, VOIDmode
))
3679 gcc_assert (TARGET_MIPS16
3680 ? TARGET_MIPS16_TEXT_LOADS
3681 : !TARGET_EXPLICIT_RELOCS
);
3682 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
3685 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
3687 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
3689 if (GET_MODE (dest
) == V2SFmode
)
3690 return "mov.ps\t%0,%1";
3692 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
3695 if (dest_code
== MEM
)
3696 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
3698 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
3700 if (src_code
== MEM
)
3701 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
3703 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
3705 static char retval
[] = "l_c_\t%0,%1";
3707 retval
[1] = (dbl_p
? 'd' : 'w');
3708 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
3711 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
3713 static char retval
[] = "s_c_\t%1,%0";
3715 retval
[1] = (dbl_p
? 'd' : 'w');
3716 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
3722 /* Return true if CMP1 is a suitable second operand for integer ordering
3723 test CODE. See also the *sCC patterns in mips.md. */
3726 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
3732 return reg_or_0_operand (cmp1
, VOIDmode
);
3736 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
3740 return arith_operand (cmp1
, VOIDmode
);
3743 return sle_operand (cmp1
, VOIDmode
);
3746 return sleu_operand (cmp1
, VOIDmode
);
3753 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
3754 integer ordering test *CODE, or if an equivalent combination can
3755 be formed by adjusting *CODE and *CMP1. When returning true, update
3756 *CODE and *CMP1 with the chosen code and operand, otherwise leave
3760 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
3761 enum machine_mode mode
)
3763 HOST_WIDE_INT plus_one
;
3765 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
3768 if (GET_CODE (*cmp1
) == CONST_INT
)
3772 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
3773 if (INTVAL (*cmp1
) < plus_one
)
3776 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3782 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
3786 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
3797 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
3798 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
3799 is nonnull, it's OK to set TARGET to the inverse of the result and
3800 flip *INVERT_PTR instead. */
3803 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
3804 rtx target
, rtx cmp0
, rtx cmp1
)
3806 enum machine_mode mode
;
3808 /* First see if there is a MIPS instruction that can do this operation.
3809 If not, try doing the same for the inverse operation. If that also
3810 fails, force CMP1 into a register and try again. */
3811 mode
= GET_MODE (cmp0
);
3812 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
3813 mips_emit_binary (code
, target
, cmp0
, cmp1
);
3816 enum rtx_code inv_code
= reverse_condition (code
);
3817 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
3819 cmp1
= force_reg (mode
, cmp1
);
3820 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
3822 else if (invert_ptr
== 0)
3826 inv_target
= mips_force_binary (GET_MODE (target
),
3827 inv_code
, cmp0
, cmp1
);
3828 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
3832 *invert_ptr
= !*invert_ptr
;
3833 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
3838 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3839 The register will have the same mode as CMP0. */
3842 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
3844 if (cmp1
== const0_rtx
)
3847 if (uns_arith_operand (cmp1
, VOIDmode
))
3848 return expand_binop (GET_MODE (cmp0
), xor_optab
,
3849 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3851 return expand_binop (GET_MODE (cmp0
), sub_optab
,
3852 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
3855 /* Convert *CODE into a code that can be used in a floating-point
3856 scc instruction (C.cond.fmt). Return true if the values of
3857 the condition code registers will be inverted, with 0 indicating
3858 that the condition holds. */
3861 mips_reversed_fp_cond (enum rtx_code
*code
)
3868 *code
= reverse_condition_maybe_unordered (*code
);
3876 /* Convert a comparison into something that can be used in a branch or
3877 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3878 being compared and *CODE is the code used to compare them.
3880 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3881 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
3882 otherwise any standard branch condition can be used. The standard branch
3885 - EQ or NE between two registers.
3886 - any comparison between a register and zero. */
3889 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
3891 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) == MODE_INT
)
3893 if (!need_eq_ne_p
&& cmp_operands
[1] == const0_rtx
)
3895 *op0
= cmp_operands
[0];
3896 *op1
= cmp_operands
[1];
3898 else if (*code
== EQ
|| *code
== NE
)
3902 *op0
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3907 *op0
= cmp_operands
[0];
3908 *op1
= force_reg (GET_MODE (*op0
), cmp_operands
[1]);
3913 /* The comparison needs a separate scc instruction. Store the
3914 result of the scc in *OP0 and compare it against zero. */
3915 bool invert
= false;
3916 *op0
= gen_reg_rtx (GET_MODE (cmp_operands
[0]));
3917 mips_emit_int_order_test (*code
, &invert
, *op0
,
3918 cmp_operands
[0], cmp_operands
[1]);
3919 *code
= (invert
? EQ
: NE
);
3923 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands
[0])))
3925 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
3926 mips_emit_binary (*code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
3932 enum rtx_code cmp_code
;
3934 /* Floating-point tests use a separate C.cond.fmt comparison to
3935 set a condition code register. The branch or conditional move
3936 will then compare that register against zero.
3938 Set CMP_CODE to the code of the comparison instruction and
3939 *CODE to the code that the branch or move should use. */
3941 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
3943 ? gen_reg_rtx (CCmode
)
3944 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
3946 mips_emit_binary (cmp_code
, *op0
, cmp_operands
[0], cmp_operands
[1]);
3950 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3951 Store the result in TARGET and return true if successful.
3953 On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */
3956 mips_expand_scc (enum rtx_code code
, rtx target
)
3958 if (GET_MODE_CLASS (GET_MODE (cmp_operands
[0])) != MODE_INT
)
3961 if (code
== EQ
|| code
== NE
)
3963 rtx zie
= mips_zero_if_equal (cmp_operands
[0], cmp_operands
[1]);
3964 mips_emit_binary (code
, target
, zie
, const0_rtx
);
3967 mips_emit_int_order_test (code
, 0, target
,
3968 cmp_operands
[0], cmp_operands
[1]);
3972 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
3973 CODE and jump to OPERANDS[0] if the condition holds. */
3976 mips_expand_conditional_branch (rtx
*operands
, enum rtx_code code
)
3978 rtx op0
, op1
, condition
;
3980 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
3981 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
3982 emit_jump_insn (gen_condjump (condition
, operands
[0]));
3987 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3988 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3991 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
3992 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
3997 reversed_p
= mips_reversed_fp_cond (&cond
);
3998 cmp_result
= gen_reg_rtx (CCV2mode
);
3999 emit_insn (gen_scc_ps (cmp_result
,
4000 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4002 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4005 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4009 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
4010 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
4011 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4014 mips_expand_conditional_move (rtx
*operands
)
4019 code
= GET_CODE (operands
[1]);
4020 mips_emit_compare (&code
, &op0
, &op1
, true);
4021 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
),
4022 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4023 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4024 operands
[2], operands
[3])));
4027 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
4028 then trap if the condition holds. */
4031 mips_expand_conditional_trap (enum rtx_code code
)
4034 enum machine_mode mode
;
4036 /* MIPS conditional trap instructions don't have GT or LE flavors,
4037 so we must swap the operands and convert to LT and GE respectively. */
4044 code
= swap_condition (code
);
4045 op0
= cmp_operands
[1];
4046 op1
= cmp_operands
[0];
4050 op0
= cmp_operands
[0];
4051 op1
= cmp_operands
[1];
4055 mode
= GET_MODE (cmp_operands
[0]);
4056 op0
= force_reg (mode
, op0
);
4057 if (!arith_operand (op1
, mode
))
4058 op1
= force_reg (mode
, op1
);
4060 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4061 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4065 /* Initialize *CUM for a call to a function of type FNTYPE. */
4068 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4070 memset (cum
, 0, sizeof (*cum
));
4071 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4072 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4075 /* Fill INFO with information about a single argument. CUM is the
4076 cumulative state for earlier arguments. MODE is the mode of this
4077 argument and TYPE is its type (if known). NAMED is true if this
4078 is a named (fixed) argument rather than a variable one. */
4081 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4082 enum machine_mode mode
, tree type
, int named
)
4084 bool doubleword_aligned_p
;
4085 unsigned int num_bytes
, num_words
, max_regs
;
4087 /* Work out the size of the argument. */
4088 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4089 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4091 /* Decide whether it should go in a floating-point register, assuming
4092 one is free. Later code checks for availability.
4094 The checks against UNITS_PER_FPVALUE handle the soft-float and
4095 single-float cases. */
4099 /* The EABI conventions have traditionally been defined in terms
4100 of TYPE_MODE, regardless of the actual type. */
4101 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4102 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4103 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4108 /* Only leading floating-point scalars are passed in
4109 floating-point registers. We also handle vector floats the same
4110 say, which is OK because they are not covered by the standard ABI. */
4111 info
->fpr_p
= (!cum
->gp_reg_found
4112 && cum
->arg_number
< 2
4114 || SCALAR_FLOAT_TYPE_P (type
)
4115 || VECTOR_FLOAT_TYPE_P (type
))
4116 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4117 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4118 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4123 /* Scalar, complex and vector floating-point types are passed in
4124 floating-point registers, as long as this is a named rather
4125 than a variable argument. */
4126 info
->fpr_p
= (named
4127 && (type
== 0 || FLOAT_TYPE_P (type
))
4128 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4129 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4130 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4131 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4133 /* ??? According to the ABI documentation, the real and imaginary
4134 parts of complex floats should be passed in individual registers.
4135 The real and imaginary parts of stack arguments are supposed
4136 to be contiguous and there should be an extra word of padding
4139 This has two problems. First, it makes it impossible to use a
4140 single "void *" va_list type, since register and stack arguments
4141 are passed differently. (At the time of writing, MIPSpro cannot
4142 handle complex float varargs correctly.) Second, it's unclear
4143 what should happen when there is only one register free.
4145 For now, we assume that named complex floats should go into FPRs
4146 if there are two FPRs free, otherwise they should be passed in the
4147 same way as a struct containing two floats. */
4149 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4150 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4152 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4153 info
->fpr_p
= false;
4163 /* See whether the argument has doubleword alignment. */
4164 doubleword_aligned_p
= FUNCTION_ARG_BOUNDARY (mode
, type
) > BITS_PER_WORD
;
4166 /* Set REG_OFFSET to the register count we're interested in.
4167 The EABI allocates the floating-point registers separately,
4168 but the other ABIs allocate them like integer registers. */
4169 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4173 /* Advance to an even register if the argument is doubleword-aligned. */
4174 if (doubleword_aligned_p
)
4175 info
->reg_offset
+= info
->reg_offset
& 1;
4177 /* Work out the offset of a stack argument. */
4178 info
->stack_offset
= cum
->stack_words
;
4179 if (doubleword_aligned_p
)
4180 info
->stack_offset
+= info
->stack_offset
& 1;
4182 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4184 /* Partition the argument between registers and stack. */
4185 info
->reg_words
= MIN (num_words
, max_regs
);
4186 info
->stack_words
= num_words
- info
->reg_words
;
4189 /* INFO describes a register argument that has the normal format for the
4190 argument's mode. Return the register it uses, assuming that FPRs are
4191 available if HARD_FLOAT_P. */
4194 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4196 if (!info
->fpr_p
|| !hard_float_p
)
4197 return GP_ARG_FIRST
+ info
->reg_offset
;
4198 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4199 /* In o32, the second argument is always passed in $f14
4200 for TARGET_DOUBLE_FLOAT, regardless of whether the
4201 first argument was a word or doubleword. */
4202 return FP_ARG_FIRST
+ 2;
4204 return FP_ARG_FIRST
+ info
->reg_offset
;
4207 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4210 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4212 return !TARGET_OLDABI
;
4215 /* Implement FUNCTION_ARG. */
4218 mips_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4219 tree type
, int named
)
4221 struct mips_arg_info info
;
4223 /* We will be called with a mode of VOIDmode after the last argument
4224 has been seen. Whatever we return will be passed to the call expander.
4225 If we need a MIPS16 fp_code, return a REG with the code stored as
4227 if (mode
== VOIDmode
)
4229 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4230 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4235 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4237 /* Return straight away if the whole argument is passed on the stack. */
4238 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4241 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4242 contains a double in its entirety, then that 64-bit chunk is passed
4243 in a floating-point register. */
4245 && TARGET_HARD_FLOAT
4248 && TREE_CODE (type
) == RECORD_TYPE
4249 && TYPE_SIZE_UNIT (type
)
4250 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
4254 /* First check to see if there is any such field. */
4255 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4256 if (TREE_CODE (field
) == FIELD_DECL
4257 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4258 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4259 && host_integerp (bit_position (field
), 0)
4260 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4265 /* Now handle the special case by returning a PARALLEL
4266 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4267 chunks are passed in registers. */
4269 HOST_WIDE_INT bitpos
;
4272 /* assign_parms checks the mode of ENTRY_PARM, so we must
4273 use the actual mode here. */
4274 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4277 field
= TYPE_FIELDS (type
);
4278 for (i
= 0; i
< info
.reg_words
; i
++)
4282 for (; field
; field
= TREE_CHAIN (field
))
4283 if (TREE_CODE (field
) == FIELD_DECL
4284 && int_bit_position (field
) >= bitpos
)
4288 && int_bit_position (field
) == bitpos
4289 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4290 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4291 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4293 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4296 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4297 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4299 bitpos
+= BITS_PER_WORD
;
4305 /* Handle the n32/n64 conventions for passing complex floating-point
4306 arguments in FPR pairs. The real part goes in the lower register
4307 and the imaginary part goes in the upper register. */
4310 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4313 enum machine_mode inner
;
4316 inner
= GET_MODE_INNER (mode
);
4317 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
4318 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4320 /* Real part in registers, imaginary part on stack. */
4321 gcc_assert (info
.stack_words
== info
.reg_words
);
4322 return gen_rtx_REG (inner
, regno
);
4326 gcc_assert (info
.stack_words
== 0);
4327 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4328 gen_rtx_REG (inner
, regno
),
4330 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4332 regno
+ info
.reg_words
/ 2),
4333 GEN_INT (GET_MODE_SIZE (inner
)));
4334 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
4338 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
4341 /* Implement FUNCTION_ARG_ADVANCE. */
4344 mips_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4345 tree type
, int named
)
4347 struct mips_arg_info info
;
4349 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4352 cum
->gp_reg_found
= true;
4354 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4355 an explanation of what this code does. It assumes that we're using
4356 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4358 if (cum
->arg_number
< 2 && info
.fpr_p
)
4359 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
4361 /* Advance the register count. This has the effect of setting
4362 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4363 argument required us to skip the final GPR and pass the whole
4364 argument on the stack. */
4365 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4366 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4367 else if (info
.reg_words
> 0)
4368 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
4370 /* Advance the stack word count. */
4371 if (info
.stack_words
> 0)
4372 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
4377 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4380 mips_arg_partial_bytes (CUMULATIVE_ARGS
*cum
,
4381 enum machine_mode mode
, tree type
, bool named
)
4383 struct mips_arg_info info
;
4385 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4386 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
4389 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4390 PARM_BOUNDARY bits of alignment, but will be given anything up
4391 to STACK_BOUNDARY bits if the type requires it. */
4394 mips_function_arg_boundary (enum machine_mode mode
, tree type
)
4396 unsigned int alignment
;
4398 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
4399 if (alignment
< PARM_BOUNDARY
)
4400 alignment
= PARM_BOUNDARY
;
4401 if (alignment
> STACK_BOUNDARY
)
4402 alignment
= STACK_BOUNDARY
;
4406 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4407 upward rather than downward. In other words, return true if the
4408 first byte of the stack slot has useful data, false if the last
4412 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
4414 /* On little-endian targets, the first byte of every stack argument
4415 is passed in the first byte of the stack slot. */
4416 if (!BYTES_BIG_ENDIAN
)
4419 /* Otherwise, integral types are padded downward: the last byte of a
4420 stack argument is passed in the last byte of the stack slot. */
4422 ? (INTEGRAL_TYPE_P (type
)
4423 || POINTER_TYPE_P (type
)
4424 || FIXED_POINT_TYPE_P (type
))
4425 : (SCALAR_INT_MODE_P (mode
)
4426 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
4429 /* Big-endian o64 pads floating-point arguments downward. */
4430 if (mips_abi
== ABI_O64
)
4431 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4434 /* Other types are padded upward for o32, o64, n32 and n64. */
4435 if (mips_abi
!= ABI_EABI
)
4438 /* Arguments smaller than a stack slot are padded downward. */
4439 if (mode
!= BLKmode
)
4440 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
4442 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
4445 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4446 if the least significant byte of the register has useful data. Return
4447 the opposite if the most significant byte does. */
4450 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
4452 /* No shifting is required for floating-point arguments. */
4453 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
4454 return !BYTES_BIG_ENDIAN
;
4456 /* Otherwise, apply the same padding to register arguments as we do
4457 to stack arguments. */
4458 return mips_pad_arg_upward (mode
, type
);
4461 /* Return nonzero when an argument must be passed by reference. */
4464 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4465 enum machine_mode mode
, const_tree type
,
4466 bool named ATTRIBUTE_UNUSED
)
4468 if (mips_abi
== ABI_EABI
)
4472 /* ??? How should SCmode be handled? */
4473 if (mode
== DImode
|| mode
== DFmode
4474 || mode
== DQmode
|| mode
== UDQmode
4475 || mode
== DAmode
|| mode
== UDAmode
)
4478 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4479 return size
== -1 || size
> UNITS_PER_WORD
;
4483 /* If we have a variable-sized parameter, we have no choice. */
4484 return targetm
.calls
.must_pass_in_stack (mode
, type
);
4488 /* Implement TARGET_CALLEE_COPIES. */
4491 mips_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
4492 enum machine_mode mode ATTRIBUTE_UNUSED
,
4493 const_tree type ATTRIBUTE_UNUSED
, bool named
)
4495 return mips_abi
== ABI_EABI
&& named
;
4498 /* See whether VALTYPE is a record whose fields should be returned in
4499 floating-point registers. If so, return the number of fields and
4500 list them in FIELDS (which should have two elements). Return 0
4503 For n32 & n64, a structure with one or two fields is returned in
4504 floating-point registers as long as every field has a floating-point
4508 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
4516 if (TREE_CODE (valtype
) != RECORD_TYPE
)
4520 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= TREE_CHAIN (field
))
4522 if (TREE_CODE (field
) != FIELD_DECL
)
4525 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
4531 fields
[i
++] = field
;
4536 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4537 a value in the most significant part of $2/$3 if:
4539 - the target is big-endian;
4541 - the value has a structure or union type (we generalize this to
4542 cover aggregates from other languages too); and
4544 - the structure is not returned in floating-point registers. */
4547 mips_return_in_msb (const_tree valtype
)
4551 return (TARGET_NEWABI
4552 && TARGET_BIG_ENDIAN
4553 && AGGREGATE_TYPE_P (valtype
)
4554 && mips_fpr_return_fields (valtype
, fields
) == 0);
4557 /* Return true if the function return value MODE will get returned in a
4558 floating-point register. */
4561 mips_return_mode_in_fpr_p (enum machine_mode mode
)
4563 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4564 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
4565 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4566 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
4569 /* Return the representation of an FPR return register when the
4570 value being returned in FP_RETURN has mode VALUE_MODE and the
4571 return type itself has mode TYPE_MODE. On NewABI targets,
4572 the two modes may be different for structures like:
4574 struct __attribute__((packed)) foo { float f; }
4576 where we return the SFmode value of "f" in FP_RETURN, but where
4577 the structure itself has mode BLKmode. */
4580 mips_return_fpr_single (enum machine_mode type_mode
,
4581 enum machine_mode value_mode
)
4585 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
4586 if (type_mode
!= value_mode
)
4588 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
4589 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
4594 /* Return a composite value in a pair of floating-point registers.
4595 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4596 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4599 For n32 & n64, $f0 always holds the first value and $f2 the second.
4600 Otherwise the values are packed together as closely as possible. */
4603 mips_return_fpr_pair (enum machine_mode mode
,
4604 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
4605 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
4609 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
4610 return gen_rtx_PARALLEL
4613 gen_rtx_EXPR_LIST (VOIDmode
,
4614 gen_rtx_REG (mode1
, FP_RETURN
),
4616 gen_rtx_EXPR_LIST (VOIDmode
,
4617 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
4618 GEN_INT (offset2
))));
4622 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4623 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4624 VALTYPE is null and MODE is the mode of the return value. */
4627 mips_function_value (const_tree valtype
, enum machine_mode mode
)
4634 mode
= TYPE_MODE (valtype
);
4635 unsigned_p
= TYPE_UNSIGNED (valtype
);
4637 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4638 we must promote the mode just as PROMOTE_MODE does. */
4639 mode
= promote_mode (valtype
, mode
, &unsigned_p
, 1);
4641 /* Handle structures whose fields are returned in $f0/$f2. */
4642 switch (mips_fpr_return_fields (valtype
, fields
))
4645 return mips_return_fpr_single (mode
,
4646 TYPE_MODE (TREE_TYPE (fields
[0])));
4649 return mips_return_fpr_pair (mode
,
4650 TYPE_MODE (TREE_TYPE (fields
[0])),
4651 int_byte_position (fields
[0]),
4652 TYPE_MODE (TREE_TYPE (fields
[1])),
4653 int_byte_position (fields
[1]));
4656 /* If a value is passed in the most significant part of a register, see
4657 whether we have to round the mode up to a whole number of words. */
4658 if (mips_return_in_msb (valtype
))
4660 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
4661 if (size
% UNITS_PER_WORD
!= 0)
4663 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
4664 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
4668 /* For EABI, the class of return register depends entirely on MODE.
4669 For example, "struct { some_type x; }" and "union { some_type x; }"
4670 are returned in the same way as a bare "some_type" would be.
4671 Other ABIs only use FPRs for scalar, complex or vector types. */
4672 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
4673 return gen_rtx_REG (mode
, GP_RETURN
);
4678 /* Handle long doubles for n32 & n64. */
4680 return mips_return_fpr_pair (mode
,
4682 DImode
, GET_MODE_SIZE (mode
) / 2);
4684 if (mips_return_mode_in_fpr_p (mode
))
4686 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4687 return mips_return_fpr_pair (mode
,
4688 GET_MODE_INNER (mode
), 0,
4689 GET_MODE_INNER (mode
),
4690 GET_MODE_SIZE (mode
) / 2);
4692 return gen_rtx_REG (mode
, FP_RETURN
);
4696 return gen_rtx_REG (mode
, GP_RETURN
);
4699 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
4700 all BLKmode objects are returned in memory. Under the n32, n64
4701 and embedded ABIs, small structures are returned in a register.
4702 Objects with varying size must still be returned in memory, of
4706 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
4708 return (TARGET_OLDABI
4709 ? TYPE_MODE (type
) == BLKmode
4710 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
4713 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
4716 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4717 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
4720 CUMULATIVE_ARGS local_cum
;
4721 int gp_saved
, fp_saved
;
4723 /* The caller has advanced CUM up to, but not beyond, the last named
4724 argument. Advance a local copy of CUM past the last "real" named
4725 argument, to find out how many registers are left over. */
4727 FUNCTION_ARG_ADVANCE (local_cum
, mode
, type
, true);
4729 /* Found out how many registers we need to save. */
4730 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
4731 fp_saved
= (EABI_FLOAT_VARARGS_P
4732 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
4741 ptr
= plus_constant (virtual_incoming_args_rtx
,
4742 REG_PARM_STACK_SPACE (cfun
->decl
)
4743 - gp_saved
* UNITS_PER_WORD
);
4744 mem
= gen_frame_mem (BLKmode
, ptr
);
4745 set_mem_alias_set (mem
, get_varargs_alias_set ());
4747 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
4752 /* We can't use move_block_from_reg, because it will use
4754 enum machine_mode mode
;
4757 /* Set OFF to the offset from virtual_incoming_args_rtx of
4758 the first float register. The FP save area lies below
4759 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4760 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
4761 off
-= fp_saved
* UNITS_PER_FPREG
;
4763 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
4765 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
4766 i
+= MAX_FPRS_PER_FMT
)
4770 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
4771 mem
= gen_frame_mem (mode
, ptr
);
4772 set_mem_alias_set (mem
, get_varargs_alias_set ());
4773 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
4774 off
+= UNITS_PER_HWFPVALUE
;
4778 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
4779 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
4780 + fp_saved
* UNITS_PER_FPREG
);
4783 /* Implement TARGET_BUILTIN_VA_LIST. */
4786 mips_build_builtin_va_list (void)
4788 if (EABI_FLOAT_VARARGS_P
)
4790 /* We keep 3 pointers, and two offsets.
4792 Two pointers are to the overflow area, which starts at the CFA.
4793 One of these is constant, for addressing into the GPR save area
4794 below it. The other is advanced up the stack through the
4797 The third pointer is to the bottom of the GPR save area.
4798 Since the FPR save area is just below it, we can address
4799 FPR slots off this pointer.
4801 We also keep two one-byte offsets, which are to be subtracted
4802 from the constant pointers to yield addresses in the GPR and
4803 FPR save areas. These are downcounted as float or non-float
4804 arguments are used, and when they get to zero, the argument
4805 must be obtained from the overflow region. */
4806 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
4809 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
4811 f_ovfl
= build_decl (FIELD_DECL
, get_identifier ("__overflow_argptr"),
4813 f_gtop
= build_decl (FIELD_DECL
, get_identifier ("__gpr_top"),
4815 f_ftop
= build_decl (FIELD_DECL
, get_identifier ("__fpr_top"),
4817 f_goff
= build_decl (FIELD_DECL
, get_identifier ("__gpr_offset"),
4818 unsigned_char_type_node
);
4819 f_foff
= build_decl (FIELD_DECL
, get_identifier ("__fpr_offset"),
4820 unsigned_char_type_node
);
4821 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4822 warn on every user file. */
4823 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
4824 array
= build_array_type (unsigned_char_type_node
,
4825 build_index_type (index
));
4826 f_res
= build_decl (FIELD_DECL
, get_identifier ("__reserved"), array
);
4828 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
4829 DECL_FIELD_CONTEXT (f_gtop
) = record
;
4830 DECL_FIELD_CONTEXT (f_ftop
) = record
;
4831 DECL_FIELD_CONTEXT (f_goff
) = record
;
4832 DECL_FIELD_CONTEXT (f_foff
) = record
;
4833 DECL_FIELD_CONTEXT (f_res
) = record
;
4835 TYPE_FIELDS (record
) = f_ovfl
;
4836 TREE_CHAIN (f_ovfl
) = f_gtop
;
4837 TREE_CHAIN (f_gtop
) = f_ftop
;
4838 TREE_CHAIN (f_ftop
) = f_goff
;
4839 TREE_CHAIN (f_goff
) = f_foff
;
4840 TREE_CHAIN (f_foff
) = f_res
;
4842 layout_type (record
);
4845 else if (TARGET_IRIX
&& TARGET_IRIX6
)
4846 /* On IRIX 6, this type is 'char *'. */
4847 return build_pointer_type (char_type_node
);
4849 /* Otherwise, we use 'void *'. */
4850 return ptr_type_node
;
4853 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
4856 mips_va_start (tree valist
, rtx nextarg
)
4858 if (EABI_FLOAT_VARARGS_P
)
4860 const CUMULATIVE_ARGS
*cum
;
4861 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4862 tree ovfl
, gtop
, ftop
, goff
, foff
;
4864 int gpr_save_area_size
;
4865 int fpr_save_area_size
;
4868 cum
= &crtl
->args
.info
;
4870 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
4872 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
4874 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4875 f_gtop
= TREE_CHAIN (f_ovfl
);
4876 f_ftop
= TREE_CHAIN (f_gtop
);
4877 f_goff
= TREE_CHAIN (f_ftop
);
4878 f_foff
= TREE_CHAIN (f_goff
);
4880 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4882 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
4884 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
4886 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
4888 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
4891 /* Emit code to initialize OVFL, which points to the next varargs
4892 stack argument. CUM->STACK_WORDS gives the number of stack
4893 words used by named arguments. */
4894 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
4895 if (cum
->stack_words
> 0)
4896 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
4897 size_int (cum
->stack_words
* UNITS_PER_WORD
));
4898 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovfl
), ovfl
, t
);
4899 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4901 /* Emit code to initialize GTOP, the top of the GPR save area. */
4902 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
4903 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (gtop
), gtop
, t
);
4904 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4906 /* Emit code to initialize FTOP, the top of the FPR save area.
4907 This address is gpr_save_area_bytes below GTOP, rounded
4908 down to the next fp-aligned boundary. */
4909 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
4910 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
4911 fpr_offset
&= -UNITS_PER_FPVALUE
;
4913 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ftop
), t
,
4914 size_int (-fpr_offset
));
4915 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ftop
), ftop
, t
);
4916 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4918 /* Emit code to initialize GOFF, the offset from GTOP of the
4919 next GPR argument. */
4920 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (goff
), goff
,
4921 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
4922 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4924 /* Likewise emit code to initialize FOFF, the offset from FTOP
4925 of the next FPR argument. */
4926 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (foff
), foff
,
4927 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
4928 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4932 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
4933 std_expand_builtin_va_start (valist
, nextarg
);
4937 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
4940 mips_gimplify_va_arg_expr (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
4945 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
4947 type
= build_pointer_type (type
);
4949 if (!EABI_FLOAT_VARARGS_P
)
4950 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
4953 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
4954 tree ovfl
, top
, off
, align
;
4955 HOST_WIDE_INT size
, rsize
, osize
;
4958 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
4959 f_gtop
= TREE_CHAIN (f_ovfl
);
4960 f_ftop
= TREE_CHAIN (f_gtop
);
4961 f_goff
= TREE_CHAIN (f_ftop
);
4962 f_foff
= TREE_CHAIN (f_goff
);
4966 TOP be the top of the GPR or FPR save area;
4967 OFF be the offset from TOP of the next register;
4968 ADDR_RTX be the address of the argument;
4969 SIZE be the number of bytes in the argument type;
4970 RSIZE be the number of bytes used to store the argument
4971 when it's in the register save area; and
4972 OSIZE be the number of bytes used to store it when it's
4973 in the stack overflow area.
4975 The code we want is:
4977 1: off &= -rsize; // round down
4980 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
4985 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
4986 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
4990 [1] and [9] can sometimes be optimized away. */
4992 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
4994 size
= int_size_in_bytes (type
);
4996 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
4997 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
4999 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5001 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5004 /* When va_start saves FPR arguments to the stack, each slot
5005 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5006 argument's precision. */
5007 rsize
= UNITS_PER_HWFPVALUE
;
5009 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5010 (= PARM_BOUNDARY bits). This can be different from RSIZE
5013 (1) On 32-bit targets when TYPE is a structure such as:
5015 struct s { float f; };
5017 Such structures are passed in paired FPRs, so RSIZE
5018 will be 8 bytes. However, the structure only takes
5019 up 4 bytes of memory, so OSIZE will only be 4.
5021 (2) In combinations such as -mgp64 -msingle-float
5022 -fshort-double. Doubles passed in registers will then take
5023 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5024 stack take up UNITS_PER_WORD bytes. */
5025 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
5029 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5031 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5033 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5034 if (rsize
> UNITS_PER_WORD
)
5036 /* [1] Emit code for: off &= -rsize. */
5037 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), off
,
5038 build_int_cst (NULL_TREE
, -rsize
));
5039 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (off
), off
, t
);
5040 gimplify_and_add (t
, pre_p
);
5045 /* [2] Emit code to branch if off == 0. */
5046 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
5047 build_int_cst (TREE_TYPE (off
), 0));
5048 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
5050 /* [5] Emit code for: off -= rsize. We do this as a form of
5051 post-decrement not available to C. */
5052 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
5053 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
5055 /* [4] Emit code for:
5056 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5057 t
= fold_convert (sizetype
, t
);
5058 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
5059 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (top
), top
, t
);
5060 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
5062 u
= size_int (rsize
- size
);
5063 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5065 COND_EXPR_THEN (addr
) = t
;
5067 if (osize
> UNITS_PER_WORD
)
5069 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5070 u
= size_int (osize
- 1);
5071 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5072 t
= fold_convert (sizetype
, t
);
5073 u
= size_int (-osize
);
5074 t
= build2 (BIT_AND_EXPR
, sizetype
, t
, u
);
5075 t
= fold_convert (TREE_TYPE (ovfl
), t
);
5076 align
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovfl
), ovfl
, t
);
5081 /* [10, 11] Emit code for:
5082 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5084 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
5085 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5086 if (BYTES_BIG_ENDIAN
&& osize
> size
)
5088 u
= size_int (osize
- size
);
5089 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5092 /* String [9] and [10, 11] together. */
5094 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5095 COND_EXPR_ELSE (addr
) = t
;
5097 addr
= fold_convert (build_pointer_type (type
), addr
);
5098 addr
= build_va_arg_indirect_ref (addr
);
5102 addr
= build_va_arg_indirect_ref (addr
);
5107 /* A chained list of functions for which mips16_build_call_stub has already
5108 generated a stub. NAME is the name of the function and FP_RET_P is true
5109 if the function returns a value in floating-point registers. */
5110 struct mips16_stub
{
5111 struct mips16_stub
*next
;
5115 static struct mips16_stub
*mips16_stubs
;
5117 /* Return the two-character string that identifies floating-point
5118 return mode MODE in the name of a MIPS16 function stub. */
5121 mips16_call_stub_mode_suffix (enum machine_mode mode
)
5125 else if (mode
== DFmode
)
5127 else if (mode
== SCmode
)
5129 else if (mode
== DCmode
)
5131 else if (mode
== V2SFmode
)
5137 /* Write instructions to move a 32-bit value between general register
5138 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5139 from GPREG to FPREG and 'f' to move in the opposite direction. */
5142 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5144 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5145 reg_names
[gpreg
], reg_names
[fpreg
]);
5148 /* Likewise for 64-bit values. */
5151 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5154 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
5155 reg_names
[gpreg
], reg_names
[fpreg
]);
5156 else if (TARGET_FLOAT64
)
5158 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5159 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5160 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
5161 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
5165 /* Move the least-significant word. */
5166 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5167 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5168 /* ...then the most significant word. */
5169 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5170 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
5174 /* Write out code to move floating-point arguments into or out of
5175 general registers. FP_CODE is the code describing which arguments
5176 are present (see the comment above the definition of CUMULATIVE_ARGS
5177 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5180 mips_output_args_xfer (int fp_code
, char direction
)
5182 unsigned int gparg
, fparg
, f
;
5183 CUMULATIVE_ARGS cum
;
5185 /* This code only works for o32 and o64. */
5186 gcc_assert (TARGET_OLDABI
);
5188 mips_init_cumulative_args (&cum
, NULL
);
5190 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5192 enum machine_mode mode
;
5193 struct mips_arg_info info
;
5197 else if ((f
& 3) == 2)
5202 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
5203 gparg
= mips_arg_regno (&info
, false);
5204 fparg
= mips_arg_regno (&info
, true);
5207 mips_output_32bit_xfer (direction
, gparg
, fparg
);
5209 mips_output_64bit_xfer (direction
, gparg
, fparg
);
5211 mips_function_arg_advance (&cum
, mode
, NULL
, true);
5215 /* Write a MIPS16 stub for the current function. This stub is used
5216 for functions which take arguments in the floating-point registers.
5217 It is normal-mode code that moves the floating-point arguments
5218 into the general registers and then jumps to the MIPS16 code. */
5221 mips16_build_function_stub (void)
5223 const char *fnname
, *separator
;
5224 char *secname
, *stubname
;
5228 /* Create the name of the stub, and its unique section. */
5229 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5230 fnname
= targetm
.strip_name_encoding (fnname
);
5231 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
5232 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
5234 /* Build a decl for the stub. */
5235 stubdecl
= build_decl (FUNCTION_DECL
, get_identifier (stubname
),
5236 build_function_type (void_type_node
, NULL_TREE
));
5237 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
5238 DECL_RESULT (stubdecl
) = build_decl (RESULT_DECL
, NULL_TREE
, void_type_node
);
5240 /* Output a comment. */
5241 fprintf (asm_out_file
, "\t# Stub function for %s (",
5242 current_function_name ());
5244 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
5246 fprintf (asm_out_file
, "%s%s", separator
,
5247 (f
& 3) == 1 ? "float" : "double");
5250 fprintf (asm_out_file
, ")\n");
5252 /* Write the preamble leading up to the function declaration. */
5253 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5254 switch_to_section (function_section (stubdecl
));
5255 ASM_OUTPUT_ALIGN (asm_out_file
,
5256 floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
));
5258 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
5259 within a .ent, and we cannot emit another .ent. */
5260 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5262 fputs ("\t.ent\t", asm_out_file
);
5263 assemble_name (asm_out_file
, stubname
);
5264 fputs ("\n", asm_out_file
);
5267 /* Start the definition proper. */
5268 assemble_name (asm_out_file
, stubname
);
5269 fputs (":\n", asm_out_file
);
5271 /* Load the address of the MIPS16 function into $at. Do this first so
5272 that targets with coprocessor interlocks can use an MFC1 to fill the
5274 fprintf (asm_out_file
, "\t.set\tnoat\n");
5275 fprintf (asm_out_file
, "\tla\t%s,", reg_names
[GP_REG_FIRST
+ 1]);
5276 assemble_name (asm_out_file
, fnname
);
5277 fprintf (asm_out_file
, "\n");
5279 /* Move the arguments from floating-point registers to general registers. */
5280 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
5282 /* Jump to the MIPS16 function. */
5283 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
5284 fprintf (asm_out_file
, "\t.set\tat\n");
5286 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5288 fputs ("\t.end\t", asm_out_file
);
5289 assemble_name (asm_out_file
, stubname
);
5290 fputs ("\n", asm_out_file
);
5293 switch_to_section (function_section (current_function_decl
));
5296 /* The current function is a MIPS16 function that returns a value in an FPR.
5297 Copy the return value from its soft-float to its hard-float location.
5298 libgcc2 has special non-MIPS16 helper functions for each case. */
5301 mips16_copy_fpr_return_value (void)
5303 rtx fn
, insn
, arg
, call
;
5304 tree id
, return_type
;
5305 enum machine_mode return_mode
;
5307 return_type
= DECL_RESULT (current_function_decl
);
5308 return_mode
= DECL_MODE (return_type
);
5310 id
= get_identifier (ACONCAT (("__mips16_ret_",
5311 mips16_call_stub_mode_suffix (return_mode
),
5313 fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
5314 arg
= gen_rtx_REG (return_mode
, GP_RETURN
);
5315 call
= gen_call_value_internal (arg
, fn
, const0_rtx
);
5316 insn
= mips_emit_call_insn (call
, false);
5317 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), arg
);
5320 /* Consider building a stub for a MIPS16 call to function FN.
5321 RETVAL is the location of the return value, or null if this is
5322 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5323 arguments and FP_CODE is the code built by mips_function_arg;
5324 see the comment above CUMULATIVE_ARGS for details.
5326 If a stub was needed, emit the call and return the call insn itself.
5327 Return null otherwise.
5329 A stub is needed for calls to functions that, in normal mode,
5330 receive arguments in FPRs or return values in FPRs. The stub
5331 copies the arguments from their soft-float positions to their
5332 hard-float positions, calls the real function, then copies the
5333 return value from its hard-float position to its soft-float
5336 We emit a JAL to FN even when FN might need a stub. If FN turns out
5337 to be to a non-MIPS16 function, the linker automatically redirects
5338 the JAL to the stub, otherwise the JAL continues to call FN directly. */
5341 mips16_build_call_stub (rtx retval
, rtx fn
, rtx args_size
, int fp_code
)
5345 struct mips16_stub
*l
;
5348 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5349 we were invoked with the -msoft-float option. */
5350 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
5353 /* Figure out whether the value might come back in a floating-point
5355 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
5357 /* We don't need to do anything if there were no floating-point
5358 arguments and the value will not be returned in a floating-point
5360 if (fp_code
== 0 && !fp_ret_p
)
5363 /* We don't need to do anything if this is a call to a special
5364 MIPS16 support function. */
5365 if (GET_CODE (fn
) == SYMBOL_REF
5366 && strncmp (XSTR (fn
, 0), "__mips16_", 9) == 0)
5369 /* This code will only work for o32 and o64 abis. The other ABI's
5370 require more sophisticated support. */
5371 gcc_assert (TARGET_OLDABI
);
5373 /* If we're calling via a function pointer, use one of the magic
5374 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5375 Each stub expects the function address to arrive in register $2. */
5376 if (GET_CODE (fn
) != SYMBOL_REF
)
5382 /* Create a SYMBOL_REF for the libgcc.a function. */
5384 sprintf (buf
, "__mips16_call_stub_%s_%d",
5385 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
5388 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
5389 id
= get_identifier (buf
);
5390 stub_fn
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (id
));
5392 /* Load the target function into $2. */
5393 mips_emit_move (gen_rtx_REG (Pmode
, 2), fn
);
5395 /* Emit the call. */
5396 if (retval
== NULL_RTX
)
5397 insn
= gen_call_internal (stub_fn
, args_size
);
5399 insn
= gen_call_value_internal (retval
, stub_fn
, args_size
);
5400 insn
= mips_emit_call_insn (insn
, false);
5402 /* Tell GCC that this call does indeed use the value of $2. */
5403 CALL_INSN_FUNCTION_USAGE (insn
) =
5404 gen_rtx_EXPR_LIST (VOIDmode
,
5405 gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 2)),
5406 CALL_INSN_FUNCTION_USAGE (insn
));
5408 /* If we are handling a floating-point return value, we need to
5409 save $18 in the function prologue. Putting a note on the
5410 call will mean that df_regs_ever_live_p ($18) will be true if the
5411 call is not eliminated, and we can check that in the prologue
5414 CALL_INSN_FUNCTION_USAGE (insn
) =
5415 gen_rtx_EXPR_LIST (VOIDmode
,
5416 gen_rtx_USE (VOIDmode
,
5417 gen_rtx_REG (word_mode
, 18)),
5418 CALL_INSN_FUNCTION_USAGE (insn
));
5423 /* We know the function we are going to call. If we have already
5424 built a stub, we don't need to do anything further. */
5425 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
5426 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
5427 if (strcmp (l
->name
, fnname
) == 0)
5432 const char *separator
;
5433 char *secname
, *stubname
;
5434 tree stubid
, stubdecl
;
5437 /* If the function does not return in FPRs, the special stub
5441 If the function does return in FPRs, the stub section is named
5442 .mips16.call.fp.FNNAME
5444 Build a decl for the stub. */
5445 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
5447 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
5449 stubid
= get_identifier (stubname
);
5450 stubdecl
= build_decl (FUNCTION_DECL
, stubid
,
5451 build_function_type (void_type_node
, NULL_TREE
));
5452 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
5453 DECL_RESULT (stubdecl
) = build_decl (RESULT_DECL
, NULL_TREE
,
5456 /* Output a comment. */
5457 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
5459 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
5463 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5465 fprintf (asm_out_file
, "%s%s", separator
,
5466 (f
& 3) == 1 ? "float" : "double");
5469 fprintf (asm_out_file
, ")\n");
5471 /* Write the preamble leading up to the function declaration. */
5472 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5473 assemble_start_function (stubdecl
, stubname
);
5475 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5477 fputs ("\t.ent\t", asm_out_file
);
5478 assemble_name (asm_out_file
, stubname
);
5479 fputs ("\n", asm_out_file
);
5481 assemble_name (asm_out_file
, stubname
);
5482 fputs (":\n", asm_out_file
);
5487 /* Load the address of the MIPS16 function into $at. Do this
5488 first so that targets with coprocessor interlocks can use
5489 an MFC1 to fill the delay slot. */
5490 fprintf (asm_out_file
, "\t.set\tnoat\n");
5491 fprintf (asm_out_file
, "\tla\t%s,%s\n", reg_names
[GP_REG_FIRST
+ 1],
5495 /* Move the arguments from general registers to floating-point
5497 mips_output_args_xfer (fp_code
, 't');
5501 /* Jump to the previously-loaded address. */
5502 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 1]);
5503 fprintf (asm_out_file
, "\t.set\tat\n");
5507 /* Save the return address in $18 and call the non-MIPS16 function.
5508 The stub's caller knows that $18 might be clobbered, even though
5509 $18 is usually a call-saved register. */
5510 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
5511 reg_names
[GP_REG_FIRST
+ 18], reg_names
[GP_REG_FIRST
+ 31]);
5512 fprintf (asm_out_file
, "\tjal\t%s\n", fnname
);
5514 /* Move the result from floating-point registers to
5515 general registers. */
5516 switch (GET_MODE (retval
))
5519 mips_output_32bit_xfer ('f', GP_RETURN
+ 1,
5520 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
5523 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
5524 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
5526 /* On 64-bit targets, complex floats are returned in
5527 a single GPR, such that "sd" on a suitably-aligned
5528 target would store the value correctly. */
5529 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
5530 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
5531 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
5532 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
5533 reg_names
[GP_RETURN
],
5534 reg_names
[GP_RETURN
],
5535 reg_names
[GP_RETURN
+ 1]);
5540 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
5541 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
5545 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
5551 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
5554 #ifdef ASM_DECLARE_FUNCTION_SIZE
5555 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
5558 if (!FUNCTION_NAME_ALREADY_DECLARED
)
5560 fputs ("\t.end\t", asm_out_file
);
5561 assemble_name (asm_out_file
, stubname
);
5562 fputs ("\n", asm_out_file
);
5565 /* Record this stub. */
5566 l
= XNEW (struct mips16_stub
);
5567 l
->name
= xstrdup (fnname
);
5568 l
->fp_ret_p
= fp_ret_p
;
5569 l
->next
= mips16_stubs
;
5573 /* If we expect a floating-point return value, but we've built a
5574 stub which does not expect one, then we're in trouble. We can't
5575 use the existing stub, because it won't handle the floating-point
5576 value. We can't build a new stub, because the linker won't know
5577 which stub to use for the various calls in this object file.
5578 Fortunately, this case is illegal, since it means that a function
5579 was declared in two different ways in a single compilation. */
5580 if (fp_ret_p
&& !l
->fp_ret_p
)
5581 error ("cannot handle inconsistent calls to %qs", fnname
);
5583 if (retval
== NULL_RTX
)
5584 insn
= gen_call_internal_direct (fn
, args_size
);
5586 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
5587 insn
= mips_emit_call_insn (insn
, false);
5589 /* If we are calling a stub which handles a floating-point return
5590 value, we need to arrange to save $18 in the prologue. We do this
5591 by marking the function call as using the register. The prologue
5592 will later see that it is used, and emit code to save it. */
5594 CALL_INSN_FUNCTION_USAGE (insn
) =
5595 gen_rtx_EXPR_LIST (VOIDmode
,
5596 gen_rtx_USE (VOIDmode
, gen_rtx_REG (word_mode
, 18)),
5597 CALL_INSN_FUNCTION_USAGE (insn
));
5602 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5605 mips_ok_for_lazy_binding_p (rtx x
)
5607 return (TARGET_USE_GOT
5608 && GET_CODE (x
) == SYMBOL_REF
5609 && !mips_symbol_binds_local_p (x
));
5612 /* Load function address ADDR into register DEST. SIBCALL_P is true
5613 if the address is needed for a sibling call. Return true if we
5614 used an explicit lazy-binding sequence. */
5617 mips_load_call_address (rtx dest
, rtx addr
, bool sibcall_p
)
5619 /* If we're generating PIC, and this call is to a global function,
5620 try to allow its address to be resolved lazily. This isn't
5621 possible for sibcalls when $gp is call-saved because the value
5622 of $gp on entry to the stub would be our caller's gp, not ours. */
5623 if (TARGET_EXPLICIT_RELOCS
5624 && !(sibcall_p
&& TARGET_CALL_SAVED_GP
)
5625 && mips_ok_for_lazy_binding_p (addr
))
5627 rtx high
, lo_sum_symbol
;
5629 high
= mips_unspec_offset_high (dest
, pic_offset_table_rtx
,
5630 addr
, SYMBOL_GOTOFF_CALL
);
5631 lo_sum_symbol
= mips_unspec_address (addr
, SYMBOL_GOTOFF_CALL
);
5632 if (Pmode
== SImode
)
5633 emit_insn (gen_load_callsi (dest
, high
, lo_sum_symbol
));
5635 emit_insn (gen_load_calldi (dest
, high
, lo_sum_symbol
));
5640 mips_emit_move (dest
, addr
);
5645 /* Expand a "call", "sibcall", "call_value" or "sibcall_value" instruction.
5646 RESULT is where the result will go (null for "call"s and "sibcall"s),
5647 ADDR is the address of the function, ARGS_SIZE is the size of the
5648 arguments and AUX is the value passed to us by mips_function_arg.
5649 SIBCALL_P is true if we are expanding a sibling call, false if we're
5650 expanding a normal call.
5652 Return the call itself. */
5655 mips_expand_call (rtx result
, rtx addr
, rtx args_size
, rtx aux
, bool sibcall_p
)
5657 rtx orig_addr
, pattern
, insn
;
5662 if (!call_insn_operand (addr
, VOIDmode
))
5664 addr
= gen_reg_rtx (Pmode
);
5665 lazy_p
= mips_load_call_address (addr
, orig_addr
, sibcall_p
);
5668 insn
= mips16_build_call_stub (result
, addr
, args_size
,
5669 aux
== 0 ? 0 : (int) GET_MODE (aux
));
5672 gcc_assert (!sibcall_p
&& !lazy_p
);
5677 pattern
= (sibcall_p
5678 ? gen_sibcall_internal (addr
, args_size
)
5679 : gen_call_internal (addr
, args_size
));
5680 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
5682 /* Handle return values created by mips_return_fpr_pair. */
5685 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
5686 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
5689 ? gen_sibcall_value_multiple_internal (reg1
, addr
, args_size
, reg2
)
5690 : gen_call_value_multiple_internal (reg1
, addr
, args_size
, reg2
));
5694 /* Handle return values created by mips_return_fpr_single. */
5695 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
5696 result
= XEXP (XVECEXP (result
, 0, 0), 0);
5697 pattern
= (sibcall_p
5698 ? gen_sibcall_value_internal (result
, addr
, args_size
)
5699 : gen_call_value_internal (result
, addr
, args_size
));
5702 return mips_emit_call_insn (pattern
, lazy_p
);
5705 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5708 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
5710 if (!TARGET_SIBCALLS
)
5713 /* We can't do a sibcall if the called function is a MIPS16 function
5714 because there is no direct "jx" instruction equivalent to "jalx" to
5715 switch the ISA mode. We only care about cases where the sibling
5716 and normal calls would both be direct. */
5717 if (mips_use_mips16_mode_p (decl
)
5718 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
5721 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
5722 functions could be MIPS16 ones unless an attribute explicitly tells
5724 if (TARGET_INTERLINK_MIPS16
5726 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
5727 && !mips_nomips16_decl_p (decl
)
5728 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
5735 /* Emit code to move general operand SRC into condition-code
5736 register DEST given that SCRATCH is a scratch TFmode FPR.
5743 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
5746 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
5750 /* Change the source to SFmode. */
5752 src
= adjust_address (src
, SFmode
, 0);
5753 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
5754 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
5756 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
5757 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
5759 mips_emit_move (copy_rtx (fp1
), src
);
5760 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
5761 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
5764 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5765 Assume that the areas do not overlap. */
5768 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
5770 HOST_WIDE_INT offset
, delta
;
5771 unsigned HOST_WIDE_INT bits
;
5773 enum machine_mode mode
;
5776 /* Work out how many bits to move at a time. If both operands have
5777 half-word alignment, it is usually better to move in half words.
5778 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5779 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5780 Otherwise move word-sized chunks. */
5781 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
5782 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
5783 bits
= BITS_PER_WORD
/ 2;
5785 bits
= BITS_PER_WORD
;
5787 mode
= mode_for_size (bits
, MODE_INT
, 0);
5788 delta
= bits
/ BITS_PER_UNIT
;
5790 /* Allocate a buffer for the temporary registers. */
5791 regs
= alloca (sizeof (rtx
) * length
/ delta
);
5793 /* Load as many BITS-sized chunks as possible. Use a normal load if
5794 the source has enough alignment, otherwise use left/right pairs. */
5795 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
5797 regs
[i
] = gen_reg_rtx (mode
);
5798 if (MEM_ALIGN (src
) >= bits
)
5799 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
5802 rtx part
= adjust_address (src
, BLKmode
, offset
);
5803 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0))
5808 /* Copy the chunks to the destination. */
5809 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
5810 if (MEM_ALIGN (dest
) >= bits
)
5811 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
5814 rtx part
= adjust_address (dest
, BLKmode
, offset
);
5815 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
5819 /* Mop up any left-over bytes. */
5820 if (offset
< length
)
5822 src
= adjust_address (src
, BLKmode
, offset
);
5823 dest
= adjust_address (dest
, BLKmode
, offset
);
5824 move_by_pieces (dest
, src
, length
- offset
,
5825 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
5829 /* Helper function for doing a loop-based block operation on memory
5830 reference MEM. Each iteration of the loop will operate on LENGTH
5833 Create a new base register for use within the loop and point it to
5834 the start of MEM. Create a new memory reference that uses this
5835 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5838 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
5839 rtx
*loop_reg
, rtx
*loop_mem
)
5841 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
5843 /* Although the new mem does not refer to a known location,
5844 it does keep up to LENGTH bytes of alignment. */
5845 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
5846 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
5849 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
5850 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
5851 the memory regions do not overlap. */
5854 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
5855 HOST_WIDE_INT bytes_per_iter
)
5857 rtx label
, src_reg
, dest_reg
, final_src
;
5858 HOST_WIDE_INT leftover
;
5860 leftover
= length
% bytes_per_iter
;
5863 /* Create registers and memory references for use within the loop. */
5864 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
5865 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
5867 /* Calculate the value that SRC_REG should have after the last iteration
5869 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
5872 /* Emit the start of the loop. */
5873 label
= gen_label_rtx ();
5876 /* Emit the loop body. */
5877 mips_block_move_straight (dest
, src
, bytes_per_iter
);
5879 /* Move on to the next block. */
5880 mips_emit_move (src_reg
, plus_constant (src_reg
, bytes_per_iter
));
5881 mips_emit_move (dest_reg
, plus_constant (dest_reg
, bytes_per_iter
));
5883 /* Emit the loop condition. */
5884 if (Pmode
== DImode
)
5885 emit_insn (gen_cmpdi (src_reg
, final_src
));
5887 emit_insn (gen_cmpsi (src_reg
, final_src
));
5888 emit_jump_insn (gen_bne (label
));
5890 /* Mop up any left-over bytes. */
5892 mips_block_move_straight (dest
, src
, leftover
);
5895 /* Expand a movmemsi instruction, which copies LENGTH bytes from
5896 memory reference SRC to memory reference DEST. */
5899 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
5901 if (GET_CODE (length
) == CONST_INT
)
5903 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
5905 mips_block_move_straight (dest
, src
, INTVAL (length
));
5910 mips_block_move_loop (dest
, src
, INTVAL (length
),
5911 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
5918 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5921 mips_expand_synci_loop (rtx begin
, rtx end
)
5923 rtx inc
, label
, cmp
, cmp_result
;
5925 /* Load INC with the cache line size (rdhwr INC,$1). */
5926 inc
= gen_reg_rtx (SImode
);
5927 emit_insn (gen_rdhwr (inc
, const1_rtx
));
5929 /* Loop back to here. */
5930 label
= gen_label_rtx ();
5933 emit_insn (gen_synci (begin
));
5935 cmp
= mips_force_binary (Pmode
, GTU
, begin
, end
);
5937 mips_emit_binary (PLUS
, begin
, begin
, inc
);
5939 cmp_result
= gen_rtx_EQ (VOIDmode
, cmp
, const0_rtx
);
5940 emit_jump_insn (gen_condjump (cmp_result
, label
));
5943 /* Expand a QI or HI mode atomic memory operation.
5945 GENERATOR contains a pointer to the gen_* function that generates
5946 the SI mode underlying atomic operation using masks that we
5949 RESULT is the return register for the operation. Its value is NULL
5952 MEM is the location of the atomic access.
5954 OLDVAL is the first operand for the operation.
5956 NEWVAL is the optional second operand for the operation. Its value
5957 is NULL if unused. */
5960 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
5961 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
5963 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
5964 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
5966 enum machine_mode mode
;
5968 mode
= GET_MODE (mem
);
5970 /* Compute the address of the containing SImode value. */
5971 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
5972 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
5973 force_reg (Pmode
, GEN_INT (-4)));
5975 /* Create a memory reference for it. */
5976 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
5977 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
5978 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
5980 /* Work out the byte offset of the QImode or HImode value,
5981 counting from the least significant byte. */
5982 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
5983 if (TARGET_BIG_ENDIAN
)
5984 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
5986 /* Multiply by eight to convert the shift value from bytes to bits. */
5987 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
5989 /* Make the final shift an SImode value, so that it can be used in
5990 SImode operations. */
5991 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
5993 /* Set MASK to an inclusive mask of the QImode or HImode value. */
5994 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
5995 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
5996 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
5998 /* Compute the equivalent exclusive mask. */
5999 inverted_mask
= gen_reg_rtx (SImode
);
6000 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
6001 gen_rtx_NOT (SImode
, mask
)));
6003 /* Shift the old value into place. */
6004 if (oldval
!= const0_rtx
)
6006 oldval
= convert_modes (SImode
, mode
, oldval
, true);
6007 oldval
= force_reg (SImode
, oldval
);
6008 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
6011 /* Do the same for the new value. */
6012 if (newval
&& newval
!= const0_rtx
)
6014 newval
= convert_modes (SImode
, mode
, newval
, true);
6015 newval
= force_reg (SImode
, newval
);
6016 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
6019 /* Do the SImode atomic access. */
6021 res
= gen_reg_rtx (SImode
);
6023 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
6025 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
6027 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
6033 /* Shift and convert the result. */
6034 mips_emit_binary (AND
, res
, res
, mask
);
6035 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
6036 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
6040 /* Return true if it is possible to use left/right accesses for a
6041 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6042 returning true, update *OP, *LEFT and *RIGHT as follows:
6044 *OP is a BLKmode reference to the whole field.
6046 *LEFT is a QImode reference to the first byte if big endian or
6047 the last byte if little endian. This address can be used in the
6048 left-side instructions (LWL, SWL, LDL, SDL).
6050 *RIGHT is a QImode reference to the opposite end of the field and
6051 can be used in the patterning right-side instruction. */
6054 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
6055 rtx
*left
, rtx
*right
)
6059 /* Check that the operand really is a MEM. Not all the extv and
6060 extzv predicates are checked. */
6064 /* Check that the size is valid. */
6065 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
6068 /* We can only access byte-aligned values. Since we are always passed
6069 a reference to the first byte of the field, it is not necessary to
6070 do anything with BITPOS after this check. */
6071 if (bitpos
% BITS_PER_UNIT
!= 0)
6074 /* Reject aligned bitfields: we want to use a normal load or store
6075 instead of a left/right pair. */
6076 if (MEM_ALIGN (*op
) >= width
)
6079 /* Adjust *OP to refer to the whole field. This also has the effect
6080 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6081 *op
= adjust_address (*op
, BLKmode
, 0);
6082 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
6084 /* Get references to both ends of the field. We deliberately don't
6085 use the original QImode *OP for FIRST since the new BLKmode one
6086 might have a simpler address. */
6087 first
= adjust_address (*op
, QImode
, 0);
6088 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
6090 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6091 correspond to the MSB and RIGHT to the LSB. */
6092 if (TARGET_BIG_ENDIAN
)
6093 *left
= first
, *right
= last
;
6095 *left
= last
, *right
= first
;
6100 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6101 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6102 the operation is the equivalent of:
6104 (set DEST (*_extract SRC WIDTH BITPOS))
6106 Return true on success. */
6109 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
6110 HOST_WIDE_INT bitpos
)
6112 rtx left
, right
, temp
;
6114 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6115 be a paradoxical word_mode subreg. This is the only case in which
6116 we allow the destination to be larger than the source. */
6117 if (GET_CODE (dest
) == SUBREG
6118 && GET_MODE (dest
) == DImode
6119 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
6120 dest
= SUBREG_REG (dest
);
6122 /* After the above adjustment, the destination must be the same
6123 width as the source. */
6124 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
6127 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
6130 temp
= gen_reg_rtx (GET_MODE (dest
));
6131 if (GET_MODE (dest
) == DImode
)
6133 emit_insn (gen_mov_ldl (temp
, src
, left
));
6134 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
6138 emit_insn (gen_mov_lwl (temp
, src
, left
));
6139 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
6144 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6145 BITPOS and SRC are the operands passed to the expander; the operation
6146 is the equivalent of:
6148 (set (zero_extract DEST WIDTH BITPOS) SRC)
6150 Return true on success. */
6153 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
6154 HOST_WIDE_INT bitpos
)
6157 enum machine_mode mode
;
6159 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
6162 mode
= mode_for_size (width
, MODE_INT
, 0);
6163 src
= gen_lowpart (mode
, src
);
6166 emit_insn (gen_mov_sdl (dest
, src
, left
));
6167 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
6171 emit_insn (gen_mov_swl (dest
, src
, left
));
6172 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
6177 /* Return true if X is a MEM with the same size as MODE. */
6180 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
6187 size
= MEM_SIZE (x
);
6188 return size
&& INTVAL (size
) == GET_MODE_SIZE (mode
);
6191 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6192 source of an "ext" instruction or the destination of an "ins"
6193 instruction. OP must be a register operand and the following
6194 conditions must hold:
6196 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6197 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6198 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6200 Also reject lengths equal to a word as they are better handled
6201 by the move patterns. */
6204 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
6206 if (!ISA_HAS_EXT_INS
6207 || !register_operand (op
, VOIDmode
)
6208 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
6211 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
6214 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
6220 /* Return true if -msplit-addresses is selected and should be honored.
6222 -msplit-addresses is a half-way house between explicit relocations
6223 and the traditional assembler macros. It can split absolute 32-bit
6224 symbolic constants into a high/lo_sum pair but uses macros for other
6227 Like explicit relocation support for REL targets, it relies
6228 on GNU extensions in the assembler and the linker.
6230 Although this code should work for -O0, it has traditionally
6231 been treated as an optimization. */
6234 mips_split_addresses_p (void)
6236 return (TARGET_SPLIT_ADDRESSES
6240 && !ABI_HAS_64BIT_SYMBOLS
);
6243 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6246 mips_init_relocs (void)
6248 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
6249 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
6250 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
6252 if (ABI_HAS_64BIT_SYMBOLS
)
6254 if (TARGET_EXPLICIT_RELOCS
)
6256 mips_split_p
[SYMBOL_64_HIGH
] = true;
6257 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
6258 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
6260 mips_split_p
[SYMBOL_64_MID
] = true;
6261 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
6262 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
6264 mips_split_p
[SYMBOL_64_LOW
] = true;
6265 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
6266 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
6268 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
6269 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
6274 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses_p () || TARGET_MIPS16
)
6276 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
6277 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
6278 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
6280 mips_lo_relocs
[SYMBOL_32_HIGH
] = "%hi(";
6286 /* The high part is provided by a pseudo copy of $gp. */
6287 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
6288 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
6291 if (TARGET_EXPLICIT_RELOCS
)
6293 /* Small data constants are kept whole until after reload,
6294 then lowered by mips_rewrite_small_data. */
6295 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
6297 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
6300 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
6301 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
6305 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
6306 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
6311 /* The HIGH and LO_SUM are matched by special .md patterns. */
6312 mips_split_p
[SYMBOL_GOT_DISP
] = true;
6314 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
6315 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
6316 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
6318 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
6319 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
6320 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
6325 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
6327 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
6328 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
6334 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
6335 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
6336 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
6339 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
6340 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
6342 mips_split_p
[SYMBOL_DTPREL
] = true;
6343 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
6344 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
6346 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
6348 mips_split_p
[SYMBOL_TPREL
] = true;
6349 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
6350 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
6352 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
6355 /* If OP is an UNSPEC address, return the address to which it refers,
6356 otherwise return OP itself. */
6359 mips_strip_unspec_address (rtx op
)
6363 split_const (op
, &base
, &offset
);
6364 if (UNSPEC_ADDRESS_P (base
))
6365 op
= plus_constant (UNSPEC_ADDRESS (base
), INTVAL (offset
));
6369 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6370 in context CONTEXT. RELOCS is the array of relocations to use. */
6373 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
6374 const char **relocs
)
6376 enum mips_symbol_type symbol_type
;
6379 symbol_type
= mips_classify_symbolic_expression (op
, context
);
6380 gcc_assert (relocs
[symbol_type
]);
6382 fputs (relocs
[symbol_type
], file
);
6383 output_addr_const (file
, mips_strip_unspec_address (op
));
6384 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
6389 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6390 The punctuation characters are:
6392 '(' Start a nested ".set noreorder" block.
6393 ')' End a nested ".set noreorder" block.
6394 '[' Start a nested ".set noat" block.
6395 ']' End a nested ".set noat" block.
6396 '<' Start a nested ".set nomacro" block.
6397 '>' End a nested ".set nomacro" block.
6398 '*' Behave like %(%< if generating a delayed-branch sequence.
6399 '#' Print a nop if in a ".set noreorder" block.
6400 '/' Like '#', but do nothing within a delayed-branch sequence.
6401 '?' Print "l" if mips_branch_likely is true
6402 '.' Print the name of the register with a hard-wired zero (zero or $0).
6403 '@' Print the name of the assembler temporary register (at or $1).
6404 '^' Print the name of the pic call-through register (t9 or $25).
6405 '+' Print the name of the gp register (usually gp or $28).
6406 '$' Print the name of the stack pointer register (sp or $29).
6407 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6408 '-' Print ".set pop" under the same conditions for '|'.
6410 See also mips_init_print_operand_pucnt. */
6413 mips_print_operand_punctuation (FILE *file
, int ch
)
6418 if (set_noreorder
++ == 0)
6419 fputs (".set\tnoreorder\n\t", file
);
6423 gcc_assert (set_noreorder
> 0);
6424 if (--set_noreorder
== 0)
6425 fputs ("\n\t.set\treorder", file
);
6429 if (set_noat
++ == 0)
6430 fputs (".set\tnoat\n\t", file
);
6434 gcc_assert (set_noat
> 0);
6435 if (--set_noat
== 0)
6436 fputs ("\n\t.set\tat", file
);
6440 if (set_nomacro
++ == 0)
6441 fputs (".set\tnomacro\n\t", file
);
6445 gcc_assert (set_nomacro
> 0);
6446 if (--set_nomacro
== 0)
6447 fputs ("\n\t.set\tmacro", file
);
6451 if (final_sequence
!= 0)
6453 mips_print_operand_punctuation (file
, '(');
6454 mips_print_operand_punctuation (file
, '<');
6459 if (set_noreorder
!= 0)
6460 fputs ("\n\tnop", file
);
6464 /* Print an extra newline so that the delayed insn is separated
6465 from the following ones. This looks neater and is consistent
6466 with non-nop delayed sequences. */
6467 if (set_noreorder
!= 0 && final_sequence
== 0)
6468 fputs ("\n\tnop\n", file
);
6472 if (mips_branch_likely
)
6477 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
6481 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
6485 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
6489 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
6493 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
6498 fputs (".set\tpush\n\t.set\tmips2\n\t", file
);
6503 fputs ("\n\t.set\tpop", file
);
6512 /* Initialize mips_print_operand_punct. */
6515 mips_init_print_operand_punct (void)
6519 for (p
= "()[]<>*#/?.@^+$|-"; *p
; p
++)
6520 mips_print_operand_punct
[(unsigned char) *p
] = true;
6523 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6524 associated with condition CODE. Print the condition part of the
6528 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
6542 /* Conveniently, the MIPS names for these conditions are the same
6543 as their RTL equivalents. */
6544 fputs (GET_RTX_NAME (code
), file
);
6548 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
6553 /* Likewise floating-point branches. */
6556 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
6561 fputs ("c1f", file
);
6565 fputs ("c1t", file
);
6569 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
6574 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6576 'X' Print CONST_INT OP in hexadecimal format.
6577 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6578 'd' Print CONST_INT OP in decimal.
6579 'h' Print the high-part relocation associated with OP, after stripping
6581 'R' Print the low-part relocation associated with OP.
6582 'C' Print the integer branch condition for comparison OP.
6583 'N' Print the inverse of the integer branch condition for comparison OP.
6584 'F' Print the FPU branch condition for comparison OP.
6585 'W' Print the inverse of the FPU branch condition for comparison OP.
6586 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6587 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6588 't' Like 'T', but with the EQ/NE cases reversed
6589 'Y' Print mips_fp_conditions[INTVAL (OP)]
6590 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6591 'q' Print a DSP accumulator register.
6592 'D' Print the second part of a double-word register or memory operand.
6593 'L' Print the low-order register in a double-word register operand.
6594 'M' Print high-order register in a double-word register operand.
6595 'z' Print $0 if OP is zero, otherwise print OP normally. */
6598 mips_print_operand (FILE *file
, rtx op
, int letter
)
6602 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
6604 mips_print_operand_punctuation (file
, letter
);
6609 code
= GET_CODE (op
);
6614 if (GET_CODE (op
) == CONST_INT
)
6615 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
6617 output_operand_lossage ("invalid use of '%%%c'", letter
);
6621 if (GET_CODE (op
) == CONST_INT
)
6622 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
6624 output_operand_lossage ("invalid use of '%%%c'", letter
);
6628 if (GET_CODE (op
) == CONST_INT
)
6629 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
6631 output_operand_lossage ("invalid use of '%%%c'", letter
);
6637 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
6641 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
6645 mips_print_int_branch_condition (file
, code
, letter
);
6649 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
6653 mips_print_float_branch_condition (file
, code
, letter
);
6657 mips_print_float_branch_condition (file
, reverse_condition (code
),
6664 int truth
= (code
== NE
) == (letter
== 'T');
6665 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
6670 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
6671 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
6673 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6680 mips_print_operand (file
, op
, 0);
6686 if (code
== REG
&& MD_REG_P (REGNO (op
)))
6687 fprintf (file
, "$ac0");
6688 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
6689 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
6691 output_operand_lossage ("invalid use of '%%%c'", letter
);
6699 unsigned int regno
= REGNO (op
);
6700 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
6701 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
6704 fprintf (file
, "%s", reg_names
[regno
]);
6710 output_address (plus_constant (XEXP (op
, 0), 4));
6712 output_address (XEXP (op
, 0));
6716 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
6717 fputs (reg_names
[GP_REG_FIRST
], file
);
6718 else if (CONST_GP_P (op
))
6719 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
6721 output_addr_const (file
, mips_strip_unspec_address (op
));
6727 /* Output address operand X to FILE. */
6730 mips_print_operand_address (FILE *file
, rtx x
)
6732 struct mips_address_info addr
;
6734 if (mips_classify_address (&addr
, x
, word_mode
, true))
6738 mips_print_operand (file
, addr
.offset
, 0);
6739 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
6742 case ADDRESS_LO_SUM
:
6743 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
6745 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
6748 case ADDRESS_CONST_INT
:
6749 output_addr_const (file
, x
);
6750 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
6753 case ADDRESS_SYMBOLIC
:
6754 output_addr_const (file
, mips_strip_unspec_address (x
));
6760 /* Implement TARGET_ENCODE_SECTION_INFO. */
6763 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
6765 default_encode_section_info (decl
, rtl
, first
);
6767 if (TREE_CODE (decl
) == FUNCTION_DECL
)
6769 rtx symbol
= XEXP (rtl
, 0);
6770 tree type
= TREE_TYPE (decl
);
6772 /* Encode whether the symbol is short or long. */
6773 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
6774 || mips_far_type_p (type
))
6775 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
6779 /* Implement TARGET_SELECT_RTX_SECTION. */
6782 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
6783 unsigned HOST_WIDE_INT align
)
6785 /* ??? Consider using mergeable small data sections. */
6786 if (mips_rtx_constant_in_small_data_p (mode
))
6787 return get_named_section (NULL
, ".sdata", 0);
6789 return default_elf_select_rtx_section (mode
, x
, align
);
6792 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6794 The complication here is that, with the combination TARGET_ABICALLS
6795 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6796 therefore not be included in the read-only part of a DSO. Handle such
6797 cases by selecting a normal data section instead of a read-only one.
6798 The logic apes that in default_function_rodata_section. */
6801 mips_function_rodata_section (tree decl
)
6803 if (!TARGET_ABICALLS
|| TARGET_GPWORD
)
6804 return default_function_rodata_section (decl
);
6806 if (decl
&& DECL_SECTION_NAME (decl
))
6808 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
6809 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
6811 char *rname
= ASTRDUP (name
);
6813 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
6815 else if (flag_function_sections
6816 && flag_data_sections
6817 && strncmp (name
, ".text.", 6) == 0)
6819 char *rname
= ASTRDUP (name
);
6820 memcpy (rname
+ 1, "data", 4);
6821 return get_section (rname
, SECTION_WRITE
, decl
);
6824 return data_section
;
6827 /* Implement TARGET_IN_SMALL_DATA_P. */
6830 mips_in_small_data_p (const_tree decl
)
6832 unsigned HOST_WIDE_INT size
;
6834 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
6837 /* We don't yet generate small-data references for -mabicalls
6838 or VxWorks RTP code. See the related -G handling in
6839 mips_override_options. */
6840 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
6843 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
6847 /* Reject anything that isn't in a known small-data section. */
6848 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
6849 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
6852 /* If a symbol is defined externally, the assembler will use the
6853 usual -G rules when deciding how to implement macros. */
6854 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
6857 else if (TARGET_EMBEDDED_DATA
)
6859 /* Don't put constants into the small data section: we want them
6860 to be in ROM rather than RAM. */
6861 if (TREE_CODE (decl
) != VAR_DECL
)
6864 if (TREE_READONLY (decl
)
6865 && !TREE_SIDE_EFFECTS (decl
)
6866 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
6870 /* Enforce -mlocal-sdata. */
6871 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
6874 /* Enforce -mextern-sdata. */
6875 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
6877 if (DECL_EXTERNAL (decl
))
6879 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
6883 /* We have traditionally not treated zero-sized objects as small data,
6884 so this is now effectively part of the ABI. */
6885 size
= int_size_in_bytes (TREE_TYPE (decl
));
6886 return size
> 0 && size
<= mips_small_data_threshold
;
6889 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6890 anchors for small data: the GP register acts as an anchor in that
6891 case. We also don't want to use them for PC-relative accesses,
6892 where the PC acts as an anchor. */
6895 mips_use_anchors_for_symbol_p (const_rtx symbol
)
6897 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
6899 case SYMBOL_PC_RELATIVE
:
6900 case SYMBOL_GP_RELATIVE
:
6904 return default_use_anchors_for_symbol_p (symbol
);
6908 /* The MIPS debug format wants all automatic variables and arguments
6909 to be in terms of the virtual frame pointer (stack pointer before
6910 any adjustment in the function), while the MIPS 3.0 linker wants
6911 the frame pointer to be the stack pointer after the initial
6912 adjustment. So, we do the adjustment here. The arg pointer (which
6913 is eliminated) points to the virtual frame pointer, while the frame
6914 pointer (which may be eliminated) points to the stack pointer after
6915 the initial adjustments. */
6918 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
6920 rtx offset2
= const0_rtx
;
6921 rtx reg
= eliminate_constant_term (addr
, &offset2
);
6924 offset
= INTVAL (offset2
);
6926 if (reg
== stack_pointer_rtx
6927 || reg
== frame_pointer_rtx
6928 || reg
== hard_frame_pointer_rtx
)
6930 offset
-= cfun
->machine
->frame
.total_size
;
6931 if (reg
== hard_frame_pointer_rtx
)
6932 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
6935 /* sdbout_parms does not want this to crash for unrecognized cases. */
6937 else if (reg
!= arg_pointer_rtx
)
6938 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
6945 /* Implement ASM_OUTPUT_EXTERNAL. */
6948 mips_output_external (FILE *file
, tree decl
, const char *name
)
6950 default_elf_asm_output_external (file
, decl
, name
);
6952 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6953 set in order to avoid putting out names that are never really
6955 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
6957 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
6959 /* When using assembler macros, emit .extern directives for
6960 all small-data externs so that the assembler knows how
6963 In most cases it would be safe (though pointless) to emit
6964 .externs for other symbols too. One exception is when an
6965 object is within the -G limit but declared by the user to
6966 be in a section other than .sbss or .sdata. */
6967 fputs ("\t.extern\t", file
);
6968 assemble_name (file
, name
);
6969 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
6970 int_size_in_bytes (TREE_TYPE (decl
)));
6972 else if (TARGET_IRIX
6973 && mips_abi
== ABI_32
6974 && TREE_CODE (decl
) == FUNCTION_DECL
)
6976 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6977 `.global name .text' directive for every used but
6978 undefined function. If we don't, the linker may perform
6979 an optimization (skipping over the insns that set $gp)
6980 when it is unsafe. */
6981 fputs ("\t.globl ", file
);
6982 assemble_name (file
, name
);
6983 fputs (" .text\n", file
);
6988 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
6991 mips_output_filename (FILE *stream
, const char *name
)
6993 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6995 if (write_symbols
== DWARF2_DEBUG
)
6997 else if (mips_output_filename_first_time
)
6999 mips_output_filename_first_time
= 0;
7000 num_source_filenames
+= 1;
7001 current_function_file
= name
;
7002 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7003 output_quoted_string (stream
, name
);
7004 putc ('\n', stream
);
7006 /* If we are emitting stabs, let dbxout.c handle this (except for
7007 the mips_output_filename_first_time case). */
7008 else if (write_symbols
== DBX_DEBUG
)
7010 else if (name
!= current_function_file
7011 && strcmp (name
, current_function_file
) != 0)
7013 num_source_filenames
+= 1;
7014 current_function_file
= name
;
7015 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7016 output_quoted_string (stream
, name
);
7017 putc ('\n', stream
);
7021 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7023 static void ATTRIBUTE_UNUSED
7024 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7029 fputs ("\t.dtprelword\t", file
);
7033 fputs ("\t.dtpreldword\t", file
);
7039 output_addr_const (file
, x
);
7040 fputs ("+0x8000", file
);
7043 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7046 mips_dwarf_register_span (rtx reg
)
7049 enum machine_mode mode
;
7051 /* By default, GCC maps increasing register numbers to increasing
7052 memory locations, but paired FPRs are always little-endian,
7053 regardless of the prevailing endianness. */
7054 mode
= GET_MODE (reg
);
7055 if (FP_REG_P (REGNO (reg
))
7056 && TARGET_BIG_ENDIAN
7057 && MAX_FPRS_PER_FMT
> 1
7058 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
7060 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
7061 high
= mips_subword (reg
, true);
7062 low
= mips_subword (reg
, false);
7063 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
7069 /* Implement ASM_OUTPUT_ASCII. */
7072 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
7078 fprintf (stream
, "\t.ascii\t\"");
7079 for (i
= 0; i
< len
; i
++)
7083 c
= (unsigned char) string
[i
];
7086 if (c
== '\\' || c
== '\"')
7088 putc ('\\', stream
);
7096 fprintf (stream
, "\\%03o", c
);
7100 if (cur_pos
> 72 && i
+1 < len
)
7103 fprintf (stream
, "\"\n\t.ascii\t\"");
7106 fprintf (stream
, "\"\n");
7109 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7110 macros, mark the symbol as written so that mips_asm_output_external
7111 won't emit an .extern for it. STREAM is the output file, NAME is the
7112 name of the symbol, INIT_STRING is the string that should be written
7113 before the symbol and FINAL_STRING is the string that should be
7114 written after it. FINAL_STRING is a printf format that consumes the
7115 remaining arguments. */
7118 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
7119 const char *final_string
, ...)
7123 fputs (init_string
, stream
);
7124 assemble_name (stream
, name
);
7125 va_start (ap
, final_string
);
7126 vfprintf (stream
, final_string
, ap
);
7129 if (!TARGET_EXPLICIT_RELOCS
)
7131 tree name_tree
= get_identifier (name
);
7132 TREE_ASM_WRITTEN (name_tree
) = 1;
7136 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7137 NAME is the name of the object and ALIGN is the required alignment
7138 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7139 alignment argument. */
7142 mips_declare_common_object (FILE *stream
, const char *name
,
7143 const char *init_string
,
7144 unsigned HOST_WIDE_INT size
,
7145 unsigned int align
, bool takes_alignment_p
)
7147 if (!takes_alignment_p
)
7149 size
+= (align
/ BITS_PER_UNIT
) - 1;
7150 size
-= size
% (align
/ BITS_PER_UNIT
);
7151 mips_declare_object (stream
, name
, init_string
,
7152 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
7155 mips_declare_object (stream
, name
, init_string
,
7156 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
7157 size
, align
/ BITS_PER_UNIT
);
7160 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7161 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7164 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
7165 unsigned HOST_WIDE_INT size
,
7168 /* If the target wants uninitialized const declarations in
7169 .rdata then don't put them in .comm. */
7170 if (TARGET_EMBEDDED_DATA
7171 && TARGET_UNINIT_CONST_IN_RODATA
7172 && TREE_CODE (decl
) == VAR_DECL
7173 && TREE_READONLY (decl
)
7174 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
7176 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
7177 targetm
.asm_out
.globalize_label (stream
, name
);
7179 switch_to_section (readonly_data_section
);
7180 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
7181 mips_declare_object (stream
, name
, "",
7182 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
7186 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
7190 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7191 extern int size_directive_output
;
7193 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7194 definitions except that it uses mips_declare_object to emit the label. */
7197 mips_declare_object_name (FILE *stream
, const char *name
,
7198 tree decl ATTRIBUTE_UNUSED
)
7200 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7201 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
7204 size_directive_output
= 0;
7205 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
7209 size_directive_output
= 1;
7210 size
= int_size_in_bytes (TREE_TYPE (decl
));
7211 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7214 mips_declare_object (stream
, name
, "", ":\n");
7217 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7220 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
7224 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
7225 if (!flag_inhibit_size_directive
7226 && DECL_SIZE (decl
) != 0
7229 && DECL_INITIAL (decl
) == error_mark_node
7230 && !size_directive_output
)
7234 size_directive_output
= 1;
7235 size
= int_size_in_bytes (TREE_TYPE (decl
));
7236 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
7241 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7242 with the current ABI. */
7245 mips_mdebug_abi_name (void)
7258 return TARGET_64BIT
? "eabi64" : "eabi32";
7264 /* Implement TARGET_ASM_FILE_START. */
7267 mips_file_start (void)
7269 default_file_start ();
7271 /* Generate a special section to describe the ABI switches used to
7272 produce the resultant binary. This is unnecessary on IRIX and
7273 causes unwanted warnings from the native linker. */
7276 /* Record the ABI itself. Modern versions of binutils encode
7277 this information in the ELF header flags, but GDB needs the
7278 information in order to correctly debug binaries produced by
7279 older binutils. See the function mips_gdbarch_init in
7281 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
7282 mips_mdebug_abi_name ());
7284 /* There is no ELF header flag to distinguish long32 forms of the
7285 EABI from long64 forms. Emit a special section to help tools
7286 such as GDB. Do the same for o64, which is sometimes used with
7288 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
7289 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
7290 "\t.previous\n", TARGET_LONG64
? 64 : 32);
7292 #ifdef HAVE_AS_GNU_ATTRIBUTE
7293 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
7294 (TARGET_HARD_FLOAT_ABI
7295 ? (TARGET_DOUBLE_FLOAT
7296 ? ((!TARGET_64BIT
&& TARGET_FLOAT64
) ? 4 : 1) : 2) : 3));
7300 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7301 if (TARGET_ABICALLS
)
7302 fprintf (asm_out_file
, "\t.abicalls\n");
7304 if (flag_verbose_asm
)
7305 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7307 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
7310 /* Make the last instruction frame-related and note that it performs
7311 the operation described by FRAME_PATTERN. */
7314 mips_set_frame_expr (rtx frame_pattern
)
7318 insn
= get_last_insn ();
7319 RTX_FRAME_RELATED_P (insn
) = 1;
7320 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7325 /* Return a frame-related rtx that stores REG at MEM.
7326 REG must be a single register. */
7329 mips_frame_set (rtx mem
, rtx reg
)
7333 /* If we're saving the return address register and the DWARF return
7334 address column differs from the hard register number, adjust the
7335 note reg to refer to the former. */
7336 if (REGNO (reg
) == GP_REG_FIRST
+ 31
7337 && DWARF_FRAME_RETURN_COLUMN
!= GP_REG_FIRST
+ 31)
7338 reg
= gen_rtx_REG (GET_MODE (reg
), DWARF_FRAME_RETURN_COLUMN
);
7340 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
7341 RTX_FRAME_RELATED_P (set
) = 1;
7346 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7347 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7348 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7349 static const unsigned char mips16e_s2_s8_regs
[] = {
7350 30, 23, 22, 21, 20, 19, 18
7352 static const unsigned char mips16e_a0_a3_regs
[] = {
7356 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7357 ordered from the uppermost in memory to the lowest in memory. */
7358 static const unsigned char mips16e_save_restore_regs
[] = {
7359 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7362 /* Return the index of the lowest X in the range [0, SIZE) for which
7363 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7366 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
7371 for (i
= 0; i
< size
; i
++)
7372 if (BITSET_P (mask
, regs
[i
]))
7378 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7379 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7380 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7381 is true for all indexes (X, SIZE). */
7384 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
7385 unsigned int size
, unsigned int *num_regs_ptr
)
7389 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
7390 for (i
++; i
< size
; i
++)
7391 if (!BITSET_P (*mask_ptr
, regs
[i
]))
7394 *mask_ptr
|= 1 << regs
[i
];
7398 /* Return a simplified form of X using the register values in REG_VALUES.
7399 REG_VALUES[R] is the last value assigned to hard register R, or null
7400 if R has not been modified.
7402 This function is rather limited, but is good enough for our purposes. */
7405 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
7407 x
= avoid_constant_pool_reference (x
);
7411 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
7412 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
7413 x0
, GET_MODE (XEXP (x
, 0)));
7416 if (ARITHMETIC_P (x
))
7418 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
7419 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
7420 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
7424 && reg_values
[REGNO (x
)]
7425 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
7426 return reg_values
[REGNO (x
)];
7431 /* Return true if (set DEST SRC) stores an argument register into its
7432 caller-allocated save slot, storing the number of that argument
7433 register in *REGNO_PTR if so. REG_VALUES is as for
7434 mips16e_collect_propagate_value. */
7437 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
7438 unsigned int *regno_ptr
)
7440 unsigned int argno
, regno
;
7441 HOST_WIDE_INT offset
, required_offset
;
7444 /* Check that this is a word-mode store. */
7445 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
7448 /* Check that the register being saved is an unmodified argument
7450 regno
= REGNO (src
);
7451 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
7453 argno
= regno
- GP_ARG_FIRST
;
7455 /* Check whether the address is an appropriate stack-pointer or
7456 frame-pointer access. */
7457 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
7458 mips_split_plus (addr
, &base
, &offset
);
7459 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
7460 if (base
== hard_frame_pointer_rtx
)
7461 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
7462 else if (base
!= stack_pointer_rtx
)
7464 if (offset
!= required_offset
)
7471 /* A subroutine of mips_expand_prologue, called only when generating
7472 MIPS16e SAVE instructions. Search the start of the function for any
7473 instructions that save argument registers into their caller-allocated
7474 save slots. Delete such instructions and return a value N such that
7475 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7476 instructions redundant. */
7479 mips16e_collect_argument_saves (void)
7481 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
7482 rtx insn
, next
, set
, dest
, src
;
7483 unsigned int nargs
, regno
;
7485 push_topmost_sequence ();
7487 memset (reg_values
, 0, sizeof (reg_values
));
7488 for (insn
= get_insns (); insn
; insn
= next
)
7490 next
= NEXT_INSN (insn
);
7497 set
= PATTERN (insn
);
7498 if (GET_CODE (set
) != SET
)
7501 dest
= SET_DEST (set
);
7502 src
= SET_SRC (set
);
7503 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
7505 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
7508 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
7511 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
7512 reg_values
[REGNO (dest
)]
7513 = mips16e_collect_propagate_value (src
, reg_values
);
7517 pop_topmost_sequence ();
7522 /* Return a move between register REGNO and memory location SP + OFFSET.
7523 Make the move a load if RESTORE_P, otherwise make it a frame-related
7527 mips16e_save_restore_reg (bool restore_p
, HOST_WIDE_INT offset
,
7532 mem
= gen_frame_mem (SImode
, plus_constant (stack_pointer_rtx
, offset
));
7533 reg
= gen_rtx_REG (SImode
, regno
);
7535 ? gen_rtx_SET (VOIDmode
, reg
, mem
)
7536 : mips_frame_set (mem
, reg
));
7539 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7540 The instruction must:
7542 - Allocate or deallocate SIZE bytes in total; SIZE is known
7545 - Save or restore as many registers in *MASK_PTR as possible.
7546 The instruction saves the first registers at the top of the
7547 allocated area, with the other registers below it.
7549 - Save NARGS argument registers above the allocated area.
7551 (NARGS is always zero if RESTORE_P.)
7553 The SAVE and RESTORE instructions cannot save and restore all general
7554 registers, so there may be some registers left over for the caller to
7555 handle. Destructively modify *MASK_PTR so that it contains the registers
7556 that still need to be saved or restored. The caller can save these
7557 registers in the memory immediately below *OFFSET_PTR, which is a
7558 byte offset from the bottom of the allocated stack area. */
7561 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
7562 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
7566 HOST_WIDE_INT offset
, top_offset
;
7567 unsigned int i
, regno
;
7570 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
7572 /* Calculate the number of elements in the PARALLEL. We need one element
7573 for the stack adjustment, one for each argument register save, and one
7574 for each additional register move. */
7576 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
7577 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
7580 /* Create the final PARALLEL. */
7581 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
7584 /* Add the stack pointer adjustment. */
7585 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7586 plus_constant (stack_pointer_rtx
,
7587 restore_p
? size
: -size
));
7588 RTX_FRAME_RELATED_P (set
) = 1;
7589 XVECEXP (pattern
, 0, n
++) = set
;
7591 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7592 top_offset
= restore_p
? size
: 0;
7594 /* Save the arguments. */
7595 for (i
= 0; i
< nargs
; i
++)
7597 offset
= top_offset
+ i
* UNITS_PER_WORD
;
7598 set
= mips16e_save_restore_reg (restore_p
, offset
, GP_ARG_FIRST
+ i
);
7599 XVECEXP (pattern
, 0, n
++) = set
;
7602 /* Then fill in the other register moves. */
7603 offset
= top_offset
;
7604 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
7606 regno
= mips16e_save_restore_regs
[i
];
7607 if (BITSET_P (*mask_ptr
, regno
))
7609 offset
-= UNITS_PER_WORD
;
7610 set
= mips16e_save_restore_reg (restore_p
, offset
, regno
);
7611 XVECEXP (pattern
, 0, n
++) = set
;
7612 *mask_ptr
&= ~(1 << regno
);
7616 /* Tell the caller what offset it should use for the remaining registers. */
7617 *offset_ptr
= size
+ (offset
- top_offset
);
7619 gcc_assert (n
== XVECLEN (pattern
, 0));
7624 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7625 pointer. Return true if PATTERN matches the kind of instruction
7626 generated by mips16e_build_save_restore. If INFO is nonnull,
7627 initialize it when returning true. */
7630 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
7631 struct mips16e_save_restore_info
*info
)
7633 unsigned int i
, nargs
, mask
, extra
;
7634 HOST_WIDE_INT top_offset
, save_offset
, offset
;
7635 rtx set
, reg
, mem
, base
;
7638 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
7641 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7642 top_offset
= adjust
> 0 ? adjust
: 0;
7644 /* Interpret all other members of the PARALLEL. */
7645 save_offset
= top_offset
- UNITS_PER_WORD
;
7649 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
7651 /* Check that we have a SET. */
7652 set
= XVECEXP (pattern
, 0, n
);
7653 if (GET_CODE (set
) != SET
)
7656 /* Check that the SET is a load (if restoring) or a store
7658 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
7662 /* Check that the address is the sum of the stack pointer and a
7663 possibly-zero constant offset. */
7664 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
7665 if (base
!= stack_pointer_rtx
)
7668 /* Check that SET's other operand is a register. */
7669 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
7673 /* Check for argument saves. */
7674 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
7675 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
7677 else if (offset
== save_offset
)
7679 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
7680 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
7683 mask
|= 1 << REGNO (reg
);
7684 save_offset
-= UNITS_PER_WORD
;
7690 /* Check that the restrictions on register ranges are met. */
7692 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
7693 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
7694 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
7695 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
7699 /* Make sure that the topmost argument register is not saved twice.
7700 The checks above ensure that the same is then true for the other
7701 argument registers. */
7702 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
7705 /* Pass back information, if requested. */
7708 info
->nargs
= nargs
;
7710 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
7716 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7717 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7718 the null terminator. */
7721 mips16e_add_register_range (char *s
, unsigned int min_reg
,
7722 unsigned int max_reg
)
7724 if (min_reg
!= max_reg
)
7725 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
7727 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
7731 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7732 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7735 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
7737 static char buffer
[300];
7739 struct mips16e_save_restore_info info
;
7740 unsigned int i
, end
;
7743 /* Parse the pattern. */
7744 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
7747 /* Add the mnemonic. */
7748 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
7751 /* Save the arguments. */
7753 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
7754 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
7755 else if (info
.nargs
== 1)
7756 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
7758 /* Emit the amount of stack space to allocate or deallocate. */
7759 s
+= sprintf (s
, "%d", (int) info
.size
);
7761 /* Save or restore $16. */
7762 if (BITSET_P (info
.mask
, 16))
7763 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
7765 /* Save or restore $17. */
7766 if (BITSET_P (info
.mask
, 17))
7767 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
7769 /* Save or restore registers in the range $s2...$s8, which
7770 mips16e_s2_s8_regs lists in decreasing order. Note that this
7771 is a software register range; the hardware registers are not
7772 numbered consecutively. */
7773 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
7774 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
7776 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
7777 mips16e_s2_s8_regs
[i
]);
7779 /* Save or restore registers in the range $a0...$a3. */
7780 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
7781 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
7783 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
7784 mips16e_a0_a3_regs
[end
- 1]);
7786 /* Save or restore $31. */
7787 if (BITSET_P (info
.mask
, 31))
7788 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 31]);
7793 /* Return true if the current function has an insn that implicitly
7797 mips_function_has_gp_insn (void)
7799 /* Don't bother rechecking if we found one last time. */
7800 if (!cfun
->machine
->has_gp_insn_p
)
7804 push_topmost_sequence ();
7805 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7806 if (USEFUL_INSN_P (insn
)
7807 && (get_attr_got (insn
) != GOT_UNSET
7808 || mips_small_data_pattern_p (PATTERN (insn
))))
7810 cfun
->machine
->has_gp_insn_p
= true;
7813 pop_topmost_sequence ();
7815 return cfun
->machine
->has_gp_insn_p
;
7818 /* Return the register that should be used as the global pointer
7819 within this function. Return 0 if the function doesn't need
7820 a global pointer. */
7823 mips_global_pointer (void)
7827 /* $gp is always available unless we're using a GOT. */
7828 if (!TARGET_USE_GOT
)
7829 return GLOBAL_POINTER_REGNUM
;
7831 /* We must always provide $gp when it is used implicitly. */
7832 if (!TARGET_EXPLICIT_RELOCS
)
7833 return GLOBAL_POINTER_REGNUM
;
7835 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7838 return GLOBAL_POINTER_REGNUM
;
7840 /* If the function has a nonlocal goto, $gp must hold the correct
7841 global pointer for the target function. */
7842 if (crtl
->has_nonlocal_goto
)
7843 return GLOBAL_POINTER_REGNUM
;
7845 /* If the gp is never referenced, there's no need to initialize it.
7846 Note that reload can sometimes introduce constant pool references
7847 into a function that otherwise didn't need them. For example,
7848 suppose we have an instruction like:
7850 (set (reg:DF R1) (float:DF (reg:SI R2)))
7852 If R2 turns out to be constant such as 1, the instruction may have a
7853 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7854 using this constant if R2 doesn't get allocated to a register.
7856 In cases like these, reload will have added the constant to the pool
7857 but no instruction will yet refer to it. */
7858 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM
)
7859 && !crtl
->uses_const_pool
7860 && !mips_function_has_gp_insn ())
7863 /* We need a global pointer, but perhaps we can use a call-clobbered
7864 register instead of $gp. */
7865 if (TARGET_CALL_SAVED_GP
&& current_function_is_leaf
)
7866 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
7867 if (!df_regs_ever_live_p (regno
)
7868 && call_really_used_regs
[regno
]
7869 && !fixed_regs
[regno
]
7870 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
7873 return GLOBAL_POINTER_REGNUM
;
7876 /* Return true if the current function returns its value in a floating-point
7877 register in MIPS16 mode. */
7880 mips16_cfun_returns_in_fpr_p (void)
7882 tree return_type
= DECL_RESULT (current_function_decl
);
7883 return (TARGET_MIPS16
7884 && TARGET_HARD_FLOAT_ABI
7885 && !aggregate_value_p (return_type
, current_function_decl
)
7886 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
7889 /* Return true if the current function must save register REGNO. */
7892 mips_save_reg_p (unsigned int regno
)
7894 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7895 if we have not chosen a call-clobbered substitute. */
7896 if (regno
== GLOBAL_POINTER_REGNUM
)
7897 return TARGET_CALL_SAVED_GP
&& cfun
->machine
->global_pointer
== regno
;
7899 /* Check call-saved registers. */
7900 if ((crtl
->saves_all_registers
|| df_regs_ever_live_p (regno
))
7901 && !call_really_used_regs
[regno
])
7904 /* Save both registers in an FPR pair if either one is used. This is
7905 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7906 register to be used without the even register. */
7907 if (FP_REG_P (regno
)
7908 && MAX_FPRS_PER_FMT
== 2
7909 && df_regs_ever_live_p (regno
+ 1)
7910 && !call_really_used_regs
[regno
+ 1])
7913 /* We need to save the old frame pointer before setting up a new one. */
7914 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
7917 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7918 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
7921 /* We need to save the incoming return address if it is ever clobbered
7922 within the function, if __builtin_eh_return is being used to set a
7923 different return address, or if a stub is being used to return a
7925 if (regno
== GP_REG_FIRST
+ 31
7926 && (df_regs_ever_live_p (regno
)
7927 || crtl
->calls_eh_return
7928 || mips16_cfun_returns_in_fpr_p ()))
7934 /* Populate the current function's mips_frame_info structure.
7936 MIPS stack frames look like:
7938 +-------------------------------+
7940 | incoming stack arguments |
7942 +-------------------------------+
7944 | caller-allocated save area |
7945 A | for register arguments |
7947 +-------------------------------+ <-- incoming stack pointer
7949 | callee-allocated save area |
7950 B | for arguments that are |
7951 | split between registers and |
7954 +-------------------------------+ <-- arg_pointer_rtx
7956 C | callee-allocated save area |
7957 | for register varargs |
7959 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
7960 | | + UNITS_PER_HWFPVALUE
7963 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
7964 | | + UNITS_PER_WORD
7967 +-------------------------------+
7969 | local variables | | var_size
7971 +-------------------------------+
7973 | $gp save area | | cprestore_size
7975 P +-------------------------------+ <-- hard_frame_pointer_rtx for
7977 | outgoing stack arguments |
7979 +-------------------------------+
7981 | caller-allocated save area |
7982 | for register arguments |
7984 +-------------------------------+ <-- stack_pointer_rtx
7986 hard_frame_pointer_rtx for
7989 At least two of A, B and C will be empty.
7991 Dynamic stack allocations such as alloca insert data at point P.
7992 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7993 hard_frame_pointer_rtx unchanged. */
7996 mips_compute_frame_info (void)
7998 struct mips_frame_info
*frame
;
7999 HOST_WIDE_INT offset
, size
;
8000 unsigned int regno
, i
;
8002 frame
= &cfun
->machine
->frame
;
8003 memset (frame
, 0, sizeof (*frame
));
8004 size
= get_frame_size ();
8006 cfun
->machine
->global_pointer
= mips_global_pointer ();
8008 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
8009 area and the $gp save slot. This area isn't needed in leaf functions,
8010 but if the target-independent frame size is nonzero, we're committed
8011 to allocating it anyway. */
8012 if (size
== 0 && current_function_is_leaf
)
8014 /* The MIPS 3.0 linker does not like functions that dynamically
8015 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8016 looks like we are trying to create a second frame pointer to the
8017 function, so allocate some stack space to make it happy. */
8018 if (cfun
->calls_alloca
)
8019 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
8021 frame
->args_size
= 0;
8022 frame
->cprestore_size
= 0;
8026 frame
->args_size
= crtl
->outgoing_args_size
;
8027 frame
->cprestore_size
= STARTING_FRAME_OFFSET
- frame
->args_size
;
8029 offset
= frame
->args_size
+ frame
->cprestore_size
;
8031 /* Move above the local variables. */
8032 frame
->var_size
= MIPS_STACK_ALIGN (size
);
8033 offset
+= frame
->var_size
;
8035 /* Find out which GPRs we need to save. */
8036 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
8037 if (mips_save_reg_p (regno
))
8040 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
8043 /* If this function calls eh_return, we must also save and restore the
8044 EH data registers. */
8045 if (crtl
->calls_eh_return
)
8046 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
8049 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
8052 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8053 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8054 save all later registers too. */
8055 if (GENERATE_MIPS16E_SAVE_RESTORE
)
8057 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
8058 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
8059 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
8060 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
8063 /* Move above the GPR save area. */
8064 if (frame
->num_gp
> 0)
8066 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
8067 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
8070 /* Find out which FPRs we need to save. This loop must iterate over
8071 the same space as its companion in mips_for_each_saved_reg. */
8072 if (TARGET_HARD_FLOAT
)
8073 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
8074 if (mips_save_reg_p (regno
))
8076 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
8077 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
8080 /* Move above the FPR save area. */
8081 if (frame
->num_fp
> 0)
8083 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
8084 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
8087 /* Move above the callee-allocated varargs save area. */
8088 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
8089 frame
->arg_pointer_offset
= offset
;
8091 /* Move above the callee-allocated area for pretend stack arguments. */
8092 offset
+= crtl
->args
.pretend_args_size
;
8093 frame
->total_size
= offset
;
8095 /* Work out the offsets of the save areas from the top of the frame. */
8096 if (frame
->gp_sp_offset
> 0)
8097 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
8098 if (frame
->fp_sp_offset
> 0)
8099 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
8101 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8102 arguments. This tends to increase the chances of using unextended
8103 instructions for local variables and incoming arguments. */
8105 frame
->hard_frame_pointer_offset
= frame
->args_size
;
8108 /* Return the style of GP load sequence that is being used for the
8109 current function. */
8111 enum mips_loadgp_style
8112 mips_current_loadgp_style (void)
8114 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== 0)
8120 if (TARGET_ABSOLUTE_ABICALLS
)
8121 return LOADGP_ABSOLUTE
;
8123 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
8126 /* Implement FRAME_POINTER_REQUIRED. */
8129 mips_frame_pointer_required (void)
8131 /* If the function contains dynamic stack allocations, we need to
8132 use the frame pointer to access the static parts of the frame. */
8133 if (cfun
->calls_alloca
)
8136 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8137 reload may be unable to compute the address of a local variable,
8138 since there is no way to add a large constant to the stack pointer
8139 without using a second temporary register. */
8142 mips_compute_frame_info ();
8143 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
8150 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8151 or argument pointer. TO is either the stack pointer or hard frame
8155 mips_initial_elimination_offset (int from
, int to
)
8157 HOST_WIDE_INT offset
;
8159 mips_compute_frame_info ();
8161 /* Set OFFSET to the offset from the soft frame pointer, which is also
8162 the offset from the end-of-prologue stack pointer. */
8165 case FRAME_POINTER_REGNUM
:
8169 case ARG_POINTER_REGNUM
:
8170 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
8177 if (to
== HARD_FRAME_POINTER_REGNUM
)
8178 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8183 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8186 mips_extra_live_on_entry (bitmap regs
)
8190 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8191 the global pointer. */
8192 if (!TARGET_ABSOLUTE_ABICALLS
)
8193 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
8195 /* See the comment above load_call<mode> for details. */
8196 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
8200 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
8204 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
8209 return get_hard_reg_initial_val (Pmode
, GP_REG_FIRST
+ 31);
8212 /* Emit code to change the current function's return address to
8213 ADDRESS. SCRATCH is available as a scratch register, if needed.
8214 ADDRESS and SCRATCH are both word-mode GPRs. */
8217 mips_set_return_address (rtx address
, rtx scratch
)
8221 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, 31));
8222 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
8223 cfun
->machine
->frame
.gp_sp_offset
);
8224 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
8227 /* Restore $gp from its save slot. Valid only when using o32 or
8231 mips_restore_gp (void)
8235 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
);
8237 base
= frame_pointer_needed
? hard_frame_pointer_rtx
: stack_pointer_rtx
;
8238 address
= mips_add_offset (pic_offset_table_rtx
, base
,
8239 crtl
->outgoing_args_size
);
8240 mips_emit_move (pic_offset_table_rtx
, gen_frame_mem (Pmode
, address
));
8241 if (!TARGET_EXPLICIT_RELOCS
)
8242 emit_insn (gen_blockage ());
8245 /* A function to save or store a register. The first argument is the
8246 register and the second is the stack slot. */
8247 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
8249 /* Use FN to save or restore register REGNO. MODE is the register's
8250 mode and OFFSET is the offset of its save slot from the current
8254 mips_save_restore_reg (enum machine_mode mode
, int regno
,
8255 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
8259 mem
= gen_frame_mem (mode
, plus_constant (stack_pointer_rtx
, offset
));
8260 fn (gen_rtx_REG (mode
, regno
), mem
);
8263 /* Call FN for each register that is saved by the current function.
8264 SP_OFFSET is the offset of the current stack pointer from the start
8268 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
8270 enum machine_mode fpr_mode
;
8271 HOST_WIDE_INT offset
;
8274 /* Save registers starting from high to low. The debuggers prefer at least
8275 the return register be stored at func+4, and also it allows us not to
8276 need a nop in the epilogue if at least one register is reloaded in
8277 addition to return address. */
8278 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
8279 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
8280 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
8282 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
8283 offset
-= UNITS_PER_WORD
;
8286 /* This loop must iterate over the same space as its companion in
8287 mips_compute_frame_info. */
8288 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
8289 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
8290 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
8291 regno
>= FP_REG_FIRST
;
8292 regno
-= MAX_FPRS_PER_FMT
)
8293 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
8295 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
8296 offset
-= GET_MODE_SIZE (fpr_mode
);
8300 /* If we're generating n32 or n64 abicalls, and the current function
8301 does not use $28 as its global pointer, emit a cplocal directive.
8302 Use pic_offset_table_rtx as the argument to the directive. */
8305 mips_output_cplocal (void)
8307 if (!TARGET_EXPLICIT_RELOCS
8308 && cfun
->machine
->global_pointer
> 0
8309 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
8310 output_asm_insn (".cplocal %+", 0);
8313 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
8316 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
8320 #ifdef SDB_DEBUGGING_INFO
8321 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
8322 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
8325 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
8326 floating-point arguments. */
8328 && TARGET_HARD_FLOAT_ABI
8329 && crtl
->args
.info
.fp_code
!= 0)
8330 mips16_build_function_stub ();
8332 /* Select the MIPS16 mode for this function. */
8334 fprintf (file
, "\t.set\tmips16\n");
8336 fprintf (file
, "\t.set\tnomips16\n");
8338 if (!FUNCTION_NAME_ALREADY_DECLARED
)
8340 /* Get the function name the same way that toplev.c does before calling
8341 assemble_start_function. This is needed so that the name used here
8342 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8343 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8345 if (!flag_inhibit_size_directive
)
8347 fputs ("\t.ent\t", file
);
8348 assemble_name (file
, fnname
);
8352 assemble_name (file
, fnname
);
8353 fputs (":\n", file
);
8356 /* Stop mips_file_end from treating this function as external. */
8357 if (TARGET_IRIX
&& mips_abi
== ABI_32
)
8358 TREE_ASM_WRITTEN (DECL_NAME (cfun
->decl
)) = 1;
8360 /* Output MIPS-specific frame information. */
8361 if (!flag_inhibit_size_directive
)
8363 const struct mips_frame_info
*frame
;
8365 frame
= &cfun
->machine
->frame
;
8367 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
8369 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
8370 "# vars= " HOST_WIDE_INT_PRINT_DEC
8372 ", args= " HOST_WIDE_INT_PRINT_DEC
8373 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
8374 reg_names
[frame_pointer_needed
8375 ? HARD_FRAME_POINTER_REGNUM
8376 : STACK_POINTER_REGNUM
],
8377 (frame_pointer_needed
8378 ? frame
->total_size
- frame
->hard_frame_pointer_offset
8379 : frame
->total_size
),
8380 reg_names
[GP_REG_FIRST
+ 31],
8382 frame
->num_gp
, frame
->num_fp
,
8384 frame
->cprestore_size
);
8386 /* .mask MASK, OFFSET. */
8387 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
8388 frame
->mask
, frame
->gp_save_offset
);
8390 /* .fmask MASK, OFFSET. */
8391 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
8392 frame
->fmask
, frame
->fp_save_offset
);
8395 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
8396 Also emit the ".set noreorder; .set nomacro" sequence for functions
8398 if (mips_current_loadgp_style () == LOADGP_OLDABI
)
8400 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
8401 if (!cfun
->machine
->all_noreorder_p
)
8402 output_asm_insn ("%(.cpload\t%^%)", 0);
8404 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8406 else if (cfun
->machine
->all_noreorder_p
)
8407 output_asm_insn ("%(%<", 0);
8409 /* Tell the assembler which register we're using as the global
8410 pointer. This is needed for thunks, since they can use either
8411 explicit relocs or assembler macros. */
8412 mips_output_cplocal ();
8415 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
8418 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
8419 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
8421 /* Reinstate the normal $gp. */
8422 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
8423 mips_output_cplocal ();
8425 if (cfun
->machine
->all_noreorder_p
)
8427 /* Avoid using %>%) since it adds excess whitespace. */
8428 output_asm_insn (".set\tmacro", 0);
8429 output_asm_insn (".set\treorder", 0);
8430 set_noreorder
= set_nomacro
= 0;
8433 if (!FUNCTION_NAME_ALREADY_DECLARED
&& !flag_inhibit_size_directive
)
8437 /* Get the function name the same way that toplev.c does before calling
8438 assemble_start_function. This is needed so that the name used here
8439 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8440 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
8441 fputs ("\t.end\t", file
);
8442 assemble_name (file
, fnname
);
8447 /* Save register REG to MEM. Make the instruction frame-related. */
8450 mips_save_reg (rtx reg
, rtx mem
)
8452 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
8456 if (mips_split_64bit_move_p (mem
, reg
))
8457 mips_split_doubleword_move (mem
, reg
);
8459 mips_emit_move (mem
, reg
);
8461 x1
= mips_frame_set (mips_subword (mem
, false),
8462 mips_subword (reg
, false));
8463 x2
= mips_frame_set (mips_subword (mem
, true),
8464 mips_subword (reg
, true));
8465 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
8470 && REGNO (reg
) != GP_REG_FIRST
+ 31
8471 && !M16_REG_P (REGNO (reg
)))
8473 /* Save a non-MIPS16 register by moving it through a temporary.
8474 We don't need to do this for $31 since there's a special
8475 instruction for it. */
8476 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg
)), reg
);
8477 mips_emit_move (mem
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
8480 mips_emit_move (mem
, reg
);
8482 mips_set_frame_expr (mips_frame_set (mem
, reg
));
8486 /* The __gnu_local_gp symbol. */
8488 static GTY(()) rtx mips_gnu_local_gp
;
8490 /* If we're generating n32 or n64 abicalls, emit instructions
8491 to set up the global pointer. */
8494 mips_emit_loadgp (void)
8496 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
8498 pic_reg
= pic_offset_table_rtx
;
8499 switch (mips_current_loadgp_style ())
8501 case LOADGP_ABSOLUTE
:
8502 if (mips_gnu_local_gp
== NULL
)
8504 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
8505 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
8507 emit_insn (Pmode
== SImode
8508 ? gen_loadgp_absolute_si (pic_reg
, mips_gnu_local_gp
)
8509 : gen_loadgp_absolute_di (pic_reg
, mips_gnu_local_gp
));
8513 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
8514 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
8515 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
8516 emit_insn (Pmode
== SImode
8517 ? gen_loadgp_newabi_si (pic_reg
, offset
, incoming_address
)
8518 : gen_loadgp_newabi_di (pic_reg
, offset
, incoming_address
));
8519 if (!TARGET_EXPLICIT_RELOCS
)
8520 emit_insn (gen_loadgp_blockage ());
8524 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
8525 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
8526 emit_insn (Pmode
== SImode
8527 ? gen_loadgp_rtp_si (pic_reg
, base
, index
)
8528 : gen_loadgp_rtp_di (pic_reg
, base
, index
));
8529 if (!TARGET_EXPLICIT_RELOCS
)
8530 emit_insn (gen_loadgp_blockage ());
8538 /* Expand the "prologue" pattern. */
8541 mips_expand_prologue (void)
8543 const struct mips_frame_info
*frame
;
8548 if (cfun
->machine
->global_pointer
> 0)
8549 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
8551 frame
= &cfun
->machine
->frame
;
8552 size
= frame
->total_size
;
8554 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8555 bytes beforehand; this is enough to cover the register save area
8556 without going out of range. */
8557 if ((frame
->mask
| frame
->fmask
) != 0)
8559 HOST_WIDE_INT step1
;
8561 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
8562 if (GENERATE_MIPS16E_SAVE_RESTORE
)
8564 HOST_WIDE_INT offset
;
8565 unsigned int mask
, regno
;
8567 /* Try to merge argument stores into the save instruction. */
8568 nargs
= mips16e_collect_argument_saves ();
8570 /* Build the save instruction. */
8572 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
8574 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8577 /* Check if we need to save other registers. */
8578 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
8579 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
8581 offset
-= UNITS_PER_WORD
;
8582 mips_save_restore_reg (word_mode
, regno
,
8583 offset
, mips_save_reg
);
8588 insn
= gen_add3_insn (stack_pointer_rtx
,
8591 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8593 mips_for_each_saved_reg (size
, mips_save_reg
);
8597 /* Allocate the rest of the frame. */
8600 if (SMALL_OPERAND (-size
))
8601 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
8603 GEN_INT (-size
)))) = 1;
8606 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
8609 /* There are no instructions to add or subtract registers
8610 from the stack pointer, so use the frame pointer as a
8611 temporary. We should always be using a frame pointer
8612 in this case anyway. */
8613 gcc_assert (frame_pointer_needed
);
8614 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8615 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
8616 hard_frame_pointer_rtx
,
8617 MIPS_PROLOGUE_TEMP (Pmode
)));
8618 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
8621 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
8623 MIPS_PROLOGUE_TEMP (Pmode
)));
8625 /* Describe the combined effect of the previous instructions. */
8627 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8628 plus_constant (stack_pointer_rtx
, -size
)));
8632 /* Set up the frame pointer, if we're using one. */
8633 if (frame_pointer_needed
)
8635 HOST_WIDE_INT offset
;
8637 offset
= frame
->hard_frame_pointer_offset
;
8640 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8641 RTX_FRAME_RELATED_P (insn
) = 1;
8643 else if (SMALL_OPERAND (offset
))
8645 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
8646 stack_pointer_rtx
, GEN_INT (offset
));
8647 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
8651 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
8652 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
8653 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
8654 hard_frame_pointer_rtx
,
8655 MIPS_PROLOGUE_TEMP (Pmode
)));
8657 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
8658 plus_constant (stack_pointer_rtx
, offset
)));
8662 mips_emit_loadgp ();
8664 /* Initialize the $gp save slot. */
8665 if (frame
->cprestore_size
> 0)
8666 emit_insn (gen_cprestore (GEN_INT (crtl
->outgoing_args_size
)));
8668 /* If we are profiling, make sure no instructions are scheduled before
8669 the call to mcount. */
8671 emit_insn (gen_blockage ());
8674 /* Emit instructions to restore register REG from slot MEM. */
8677 mips_restore_reg (rtx reg
, rtx mem
)
8679 /* There's no MIPS16 instruction to load $31 directly. Load into
8680 $7 instead and adjust the return insn appropriately. */
8681 if (TARGET_MIPS16
&& REGNO (reg
) == GP_REG_FIRST
+ 31)
8682 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
8684 if (TARGET_MIPS16
&& !M16_REG_P (REGNO (reg
)))
8686 /* Can't restore directly; move through a temporary. */
8687 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg
)), mem
);
8688 mips_emit_move (reg
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
8691 mips_emit_move (reg
, mem
);
8694 /* Emit any instructions needed before a return. */
8697 mips_expand_before_return (void)
8699 /* When using a call-clobbered gp, we start out with unified call
8700 insns that include instructions to restore the gp. We then split
8701 these unified calls after reload. These split calls explicitly
8702 clobber gp, so there is no need to define
8703 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
8705 For consistency, we should also insert an explicit clobber of $28
8706 before return insns, so that the post-reload optimizers know that
8707 the register is not live on exit. */
8708 if (TARGET_CALL_CLOBBERED_GP
)
8709 emit_clobber (pic_offset_table_rtx
);
8712 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
8716 mips_expand_epilogue (bool sibcall_p
)
8718 const struct mips_frame_info
*frame
;
8719 HOST_WIDE_INT step1
, step2
;
8722 if (!sibcall_p
&& mips_can_use_return_insn ())
8724 emit_jump_insn (gen_return ());
8728 /* In MIPS16 mode, if the return value should go into a floating-point
8729 register, we need to call a helper routine to copy it over. */
8730 if (mips16_cfun_returns_in_fpr_p ())
8731 mips16_copy_fpr_return_value ();
8733 /* Split the frame into two. STEP1 is the amount of stack we should
8734 deallocate before restoring the registers. STEP2 is the amount we
8735 should deallocate afterwards.
8737 Start off by assuming that no registers need to be restored. */
8738 frame
= &cfun
->machine
->frame
;
8739 step1
= frame
->total_size
;
8742 /* Work out which register holds the frame address. */
8743 if (!frame_pointer_needed
)
8744 base
= stack_pointer_rtx
;
8747 base
= hard_frame_pointer_rtx
;
8748 step1
-= frame
->hard_frame_pointer_offset
;
8751 /* If we need to restore registers, deallocate as much stack as
8752 possible in the second step without going out of range. */
8753 if ((frame
->mask
| frame
->fmask
) != 0)
8755 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
8759 /* Set TARGET to BASE + STEP1. */
8765 /* Get an rtx for STEP1 that we can add to BASE. */
8766 adjust
= GEN_INT (step1
);
8767 if (!SMALL_OPERAND (step1
))
8769 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
8770 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
8773 /* Normal mode code can copy the result straight into $sp. */
8775 target
= stack_pointer_rtx
;
8777 emit_insn (gen_add3_insn (target
, base
, adjust
));
8780 /* Copy TARGET into the stack pointer. */
8781 if (target
!= stack_pointer_rtx
)
8782 mips_emit_move (stack_pointer_rtx
, target
);
8784 /* If we're using addressing macros, $gp is implicitly used by all
8785 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8787 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
8788 emit_insn (gen_blockage ());
8790 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
8792 unsigned int regno
, mask
;
8793 HOST_WIDE_INT offset
;
8796 /* Generate the restore instruction. */
8798 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
8800 /* Restore any other registers manually. */
8801 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
8802 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
8804 offset
-= UNITS_PER_WORD
;
8805 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
8808 /* Restore the remaining registers and deallocate the final bit
8810 emit_insn (restore
);
8814 /* Restore the registers. */
8815 mips_for_each_saved_reg (frame
->total_size
- step2
, mips_restore_reg
);
8817 /* Deallocate the final bit of the frame. */
8819 emit_insn (gen_add3_insn (stack_pointer_rtx
,
8824 /* Add in the __builtin_eh_return stack adjustment. We need to
8825 use a temporary in MIPS16 code. */
8826 if (crtl
->calls_eh_return
)
8830 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
8831 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
8832 MIPS_EPILOGUE_TEMP (Pmode
),
8833 EH_RETURN_STACKADJ_RTX
));
8834 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
8837 emit_insn (gen_add3_insn (stack_pointer_rtx
,
8839 EH_RETURN_STACKADJ_RTX
));
8846 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8847 path will restore the return address into $7 rather than $31. */
8849 && !GENERATE_MIPS16E_SAVE_RESTORE
8850 && BITSET_P (frame
->mask
, 31))
8851 regno
= GP_REG_FIRST
+ 7;
8853 regno
= GP_REG_FIRST
+ 31;
8854 mips_expand_before_return ();
8855 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, regno
)));
8859 /* Return nonzero if this function is known to have a null epilogue.
8860 This allows the optimizer to omit jumps to jumps if no stack
8864 mips_can_use_return_insn (void)
8866 if (!reload_completed
)
8872 /* In MIPS16 mode, a function that returns a floating-point value
8873 needs to arrange to copy the return value into the floating-point
8875 if (mips16_cfun_returns_in_fpr_p ())
8878 return cfun
->machine
->frame
.total_size
== 0;
8881 /* Return true if register REGNO can store a value of mode MODE.
8882 The result of this function is cached in mips_hard_regno_mode_ok. */
8885 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
8888 enum mode_class
class;
8890 if (mode
== CCV2mode
)
8893 && (regno
- ST_REG_FIRST
) % 2 == 0);
8895 if (mode
== CCV4mode
)
8898 && (regno
- ST_REG_FIRST
) % 4 == 0);
8903 return regno
== FPSW_REGNUM
;
8905 return (ST_REG_P (regno
)
8907 || FP_REG_P (regno
));
8910 size
= GET_MODE_SIZE (mode
);
8911 class = GET_MODE_CLASS (mode
);
8913 if (GP_REG_P (regno
))
8914 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
8916 if (FP_REG_P (regno
)
8917 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
8918 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
8920 /* Allow TFmode for CCmode reloads. */
8921 if (mode
== TFmode
&& ISA_HAS_8CC
)
8924 if (class == MODE_FLOAT
8925 || class == MODE_COMPLEX_FLOAT
8926 || class == MODE_VECTOR_FLOAT
)
8927 return size
<= UNITS_PER_FPVALUE
;
8929 /* Allow integer modes that fit into a single register. We need
8930 to put integers into FPRs when using instructions like CVT
8931 and TRUNC. There's no point allowing sizes smaller than a word,
8932 because the FPU has no appropriate load/store instructions. */
8933 if (class == MODE_INT
)
8934 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
8937 if (ACC_REG_P (regno
)
8938 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
8940 if (size
<= UNITS_PER_WORD
)
8943 if (size
<= UNITS_PER_WORD
* 2)
8944 return (DSP_ACC_REG_P (regno
)
8945 ? ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0
8946 : regno
== MD_REG_FIRST
);
8949 if (ALL_COP_REG_P (regno
))
8950 return class == MODE_INT
&& size
<= UNITS_PER_WORD
;
8952 if (regno
== GOT_VERSION_REGNUM
)
8953 return mode
== SImode
;
8958 /* Implement HARD_REGNO_NREGS. */
8961 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
8963 if (ST_REG_P (regno
))
8964 /* The size of FP status registers is always 4, because they only hold
8965 CCmode values, and CCmode is always considered to be 4 bytes wide. */
8966 return (GET_MODE_SIZE (mode
) + 3) / 4;
8968 if (FP_REG_P (regno
))
8969 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
8971 /* All other registers are word-sized. */
8972 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8975 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
8976 in mips_hard_regno_nregs. */
8979 mips_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
8985 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) class]);
8986 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
8988 size
= MIN (size
, 4);
8989 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
8991 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
8993 size
= MIN (size
, UNITS_PER_FPREG
);
8994 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
8996 if (!hard_reg_set_empty_p (left
))
8997 size
= MIN (size
, UNITS_PER_WORD
);
8998 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
9001 /* Implement CANNOT_CHANGE_MODE_CLASS. */
9004 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED
,
9005 enum machine_mode to ATTRIBUTE_UNUSED
,
9006 enum reg_class
class)
9008 /* There are several problems with changing the modes of values
9009 in floating-point registers:
9011 - When a multi-word value is stored in paired floating-point
9012 registers, the first register always holds the low word.
9013 We therefore can't allow FPRs to change between single-word
9014 and multi-word modes on big-endian targets.
9016 - GCC assumes that each word of a multiword register can be accessed
9017 individually using SUBREGs. This is not true for floating-point
9018 registers if they are bigger than a word.
9020 - Loading a 32-bit value into a 64-bit floating-point register
9021 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
9022 We can't allow FPRs to change from SImode to to a wider mode on
9025 - If the FPU has already interpreted a value in one format, we must
9026 not ask it to treat the value as having a different format.
9028 We therefore disallow all mode changes involving FPRs. */
9029 return reg_classes_intersect_p (FP_REGS
, class);
9032 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
9035 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
9040 return TARGET_HARD_FLOAT
;
9043 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
9046 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
9053 /* Implement MODES_TIEABLE_P. */
9056 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
9058 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
9059 prefer to put one of them in FPRs. */
9060 return (mode1
== mode2
9061 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
9062 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
9065 /* Implement PREFERRED_RELOAD_CLASS. */
9068 mips_preferred_reload_class (rtx x
, enum reg_class
class)
9070 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, class))
9073 if (reg_class_subset_p (FP_REGS
, class)
9074 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
9077 if (reg_class_subset_p (GR_REGS
, class))
9080 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, class))
9086 /* Implement REGISTER_MOVE_COST. */
9089 mips_register_move_cost (enum machine_mode mode
,
9090 enum reg_class to
, enum reg_class from
)
9094 /* ??? We cannot move general registers into HI and LO because
9095 MIPS16 has no MTHI and MTLO instructions. Make the cost of
9096 moves in the opposite direction just as high, which stops the
9097 register allocators from using HI and LO for pseudos. */
9098 if (reg_class_subset_p (from
, GENERAL_REGS
)
9099 && reg_class_subset_p (to
, GENERAL_REGS
))
9101 if (reg_class_subset_p (from
, M16_REGS
)
9102 || reg_class_subset_p (to
, M16_REGS
))
9108 else if (reg_class_subset_p (from
, GENERAL_REGS
))
9110 if (reg_class_subset_p (to
, GENERAL_REGS
))
9112 if (reg_class_subset_p (to
, FP_REGS
))
9114 if (reg_class_subset_p (to
, ALL_COP_AND_GR_REGS
))
9116 if (reg_class_subset_p (to
, ACC_REGS
))
9119 else if (reg_class_subset_p (to
, GENERAL_REGS
))
9121 if (reg_class_subset_p (from
, FP_REGS
))
9123 if (reg_class_subset_p (from
, ST_REGS
))
9124 /* LUI followed by MOVF. */
9126 if (reg_class_subset_p (from
, ALL_COP_AND_GR_REGS
))
9128 if (reg_class_subset_p (from
, ACC_REGS
))
9131 else if (reg_class_subset_p (from
, FP_REGS
))
9133 if (reg_class_subset_p (to
, FP_REGS
)
9134 && mips_mode_ok_for_mov_fmt_p (mode
))
9136 if (reg_class_subset_p (to
, ST_REGS
))
9137 /* An expensive sequence. */
9144 /* Return the register class required for a secondary register when
9145 copying between one of the registers in CLASS and value X, which
9146 has mode MODE. X is the source of the move if IN_P, otherwise it
9147 is the destination. Return NO_REGS if no secondary register is
9151 mips_secondary_reload_class (enum reg_class
class,
9152 enum machine_mode mode
, rtx x
, bool in_p
)
9156 /* If X is a constant that cannot be loaded into $25, it must be loaded
9157 into some other GPR. No other register class allows a direct move. */
9158 if (mips_dangerous_for_la25_p (x
))
9159 return reg_class_subset_p (class, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
9161 regno
= true_regnum (x
);
9164 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9165 if (!reg_class_subset_p (class, M16_REGS
) && !M16_REG_P (regno
))
9168 /* We can't really copy to HI or LO at all in MIPS16 mode. */
9169 if (in_p
? reg_classes_intersect_p (class, ACC_REGS
) : ACC_REG_P (regno
))
9175 /* Copying from accumulator registers to anywhere other than a general
9176 register requires a temporary general register. */
9177 if (reg_class_subset_p (class, ACC_REGS
))
9178 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
9179 if (ACC_REG_P (regno
))
9180 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
9182 /* We can only copy a value to a condition code register from a
9183 floating-point register, and even then we require a scratch
9184 floating-point register. We can only copy a value out of a
9185 condition-code register into a general register. */
9186 if (reg_class_subset_p (class, ST_REGS
))
9190 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
9192 if (ST_REG_P (regno
))
9196 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
9199 if (reg_class_subset_p (class, FP_REGS
))
9202 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
9203 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9204 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9207 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
9208 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9211 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (x
))
9212 /* We can force the constant to memory and use lwc1
9213 and ldc1. As above, we will use pairs of lwc1s if
9214 ldc1 is not supported. */
9217 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
9218 /* In this case we can use mov.fmt. */
9221 /* Otherwise, we need to reload through an integer register. */
9224 if (FP_REG_P (regno
))
9225 return reg_class_subset_p (class, GR_REGS
) ? NO_REGS
: GR_REGS
;
9230 /* Implement TARGET_MODE_REP_EXTENDED. */
9233 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
9235 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
9236 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
9242 /* Implement TARGET_VALID_POINTER_MODE. */
9245 mips_valid_pointer_mode (enum machine_mode mode
)
9247 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
9250 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
9253 mips_vector_mode_supported_p (enum machine_mode mode
)
9258 return TARGET_PAIRED_SINGLE_FLOAT
;
9275 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9278 mips_scalar_mode_supported_p (enum machine_mode mode
)
9280 if (ALL_FIXED_POINT_MODE_P (mode
)
9281 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
9284 return default_scalar_mode_supported_p (mode
);
9287 /* Implement TARGET_INIT_LIBFUNCS. */
9289 #include "config/gofast.h"
9292 mips_init_libfuncs (void)
9294 if (TARGET_FIX_VR4120
)
9296 /* Register the special divsi3 and modsi3 functions needed to work
9297 around VR4120 division errata. */
9298 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
9299 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
9302 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
9304 /* Register the MIPS16 -mhard-float stubs. */
9305 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
9306 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
9307 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
9308 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
9310 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
9311 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
9312 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
9313 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
9314 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
9315 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
9316 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
9318 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
9319 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
9320 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
9322 if (TARGET_DOUBLE_FLOAT
)
9324 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
9325 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
9326 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
9327 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
9329 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
9330 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
9331 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
9332 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
9333 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
9334 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
9335 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
9337 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
9338 "__mips16_extendsfdf2");
9339 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
9340 "__mips16_truncdfsf2");
9341 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
9342 "__mips16_fix_truncdfsi");
9343 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
9344 "__mips16_floatsidf");
9345 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
9346 "__mips16_floatunsidf");
9350 /* Register the gofast functions if selected using --enable-gofast. */
9351 gofast_maybe_init_libfuncs ();
9354 /* Return the length of INSN. LENGTH is the initial length computed by
9355 attributes in the machine-description file. */
9358 mips_adjust_insn_length (rtx insn
, int length
)
9360 /* A unconditional jump has an unfilled delay slot if it is not part
9361 of a sequence. A conditional jump normally has a delay slot, but
9362 does not on MIPS16. */
9363 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
9366 /* See how many nops might be needed to avoid hardware hazards. */
9367 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
9368 switch (get_attr_hazard (insn
))
9382 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
9383 the .md file length attributes are 4-based for both modes.
9384 Adjust the MIPS16 ones here. */
9391 /* Return an asm sequence to start a noat block and load the address
9392 of a label into $1. */
9395 mips_output_load_label (void)
9397 if (TARGET_EXPLICIT_RELOCS
)
9401 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9404 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9407 if (ISA_HAS_LOAD_DELAY
)
9408 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9409 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9413 if (Pmode
== DImode
)
9414 return "%[dla\t%@,%0";
9416 return "%[la\t%@,%0";
9420 /* Return the assembly code for INSN, which has the operands given by
9421 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9422 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9423 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9424 version of BRANCH_IF_TRUE. */
9427 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
9428 const char *branch_if_true
,
9429 const char *branch_if_false
)
9431 unsigned int length
;
9432 rtx taken
, not_taken
;
9434 length
= get_attr_length (insn
);
9437 /* Just a simple conditional branch. */
9438 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
9439 return branch_if_true
;
9442 /* Generate a reversed branch around a direct jump. This fallback does
9443 not use branch-likely instructions. */
9444 mips_branch_likely
= false;
9445 not_taken
= gen_label_rtx ();
9446 taken
= operands
[1];
9448 /* Generate the reversed branch to NOT_TAKEN. */
9449 operands
[1] = not_taken
;
9450 output_asm_insn (branch_if_false
, operands
);
9452 /* If INSN has a delay slot, we must provide delay slots for both the
9453 branch to NOT_TAKEN and the conditional jump. We must also ensure
9454 that INSN's delay slot is executed in the appropriate cases. */
9457 /* This first delay slot will always be executed, so use INSN's
9458 delay slot if is not annulled. */
9459 if (!INSN_ANNULLED_BRANCH_P (insn
))
9461 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
9462 asm_out_file
, optimize
, 1, NULL
);
9463 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
9466 output_asm_insn ("nop", 0);
9467 fprintf (asm_out_file
, "\n");
9470 /* Output the unconditional branch to TAKEN. */
9472 output_asm_insn ("j\t%0%/", &taken
);
9475 output_asm_insn (mips_output_load_label (), &taken
);
9476 output_asm_insn ("jr\t%@%]%/", 0);
9479 /* Now deal with its delay slot; see above. */
9482 /* This delay slot will only be executed if the branch is taken.
9483 Use INSN's delay slot if is annulled. */
9484 if (INSN_ANNULLED_BRANCH_P (insn
))
9486 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
9487 asm_out_file
, optimize
, 1, NULL
);
9488 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
9491 output_asm_insn ("nop", 0);
9492 fprintf (asm_out_file
, "\n");
9495 /* Output NOT_TAKEN. */
9496 targetm
.asm_out
.internal_label (asm_out_file
, "L",
9497 CODE_LABEL_NUMBER (not_taken
));
9501 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9502 if some ordering condition is true. The condition is given by
9503 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9504 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9505 its second is always zero. */
9508 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
9510 const char *branch
[2];
9512 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9513 Make BRANCH[0] branch on the inverse condition. */
9514 switch (GET_CODE (operands
[0]))
9516 /* These cases are equivalent to comparisons against zero. */
9518 inverted_p
= !inverted_p
;
9521 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%1");
9522 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%1");
9525 /* These cases are always true or always false. */
9527 inverted_p
= !inverted_p
;
9530 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%1");
9531 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%1");
9535 branch
[!inverted_p
] = MIPS_BRANCH ("b%C0z", "%2,%1");
9536 branch
[inverted_p
] = MIPS_BRANCH ("b%N0z", "%2,%1");
9539 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
9542 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
9543 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
9545 When working around R4000 and R4400 errata, we need to make sure that
9546 the division is not immediately followed by a shift[1][2]. We also
9547 need to stop the division from being put into a branch delay slot[3].
9548 The easiest way to avoid both problems is to add a nop after the
9549 division. When a divide-by-zero check is needed, this nop can be
9550 used to fill the branch delay slot.
9552 [1] If a double-word or a variable shift executes immediately
9553 after starting an integer division, the shift may give an
9554 incorrect result. See quotations of errata #16 and #28 from
9555 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9556 in mips.md for details.
9558 [2] A similar bug to [1] exists for all revisions of the
9559 R4000 and the R4400 when run in an MC configuration.
9560 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9562 "19. In this following sequence:
9564 ddiv (or ddivu or div or divu)
9565 dsll32 (or dsrl32, dsra32)
9567 if an MPT stall occurs, while the divide is slipping the cpu
9568 pipeline, then the following double shift would end up with an
9571 Workaround: The compiler needs to avoid generating any
9572 sequence with divide followed by extended double shift."
9574 This erratum is also present in "MIPS R4400MC Errata, Processor
9575 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9576 & 3.0" as errata #10 and #4, respectively.
9578 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9579 (also valid for MIPS R4000MC processors):
9581 "52. R4000SC: This bug does not apply for the R4000PC.
9583 There are two flavors of this bug:
9585 1) If the instruction just after divide takes an RF exception
9586 (tlb-refill, tlb-invalid) and gets an instruction cache
9587 miss (both primary and secondary) and the line which is
9588 currently in secondary cache at this index had the first
9589 data word, where the bits 5..2 are set, then R4000 would
9590 get a wrong result for the div.
9595 ------------------- # end-of page. -tlb-refill
9600 ------------------- # end-of page. -tlb-invalid
9603 2) If the divide is in the taken branch delay slot, where the
9604 target takes RF exception and gets an I-cache miss for the
9605 exception vector or where I-cache miss occurs for the
9606 target address, under the above mentioned scenarios, the
9607 div would get wrong results.
9610 j r2 # to next page mapped or unmapped
9611 div r8,r9 # this bug would be there as long
9612 # as there is an ICache miss and
9613 nop # the "data pattern" is present
9616 beq r0, r0, NextPage # to Next page
9620 This bug is present for div, divu, ddiv, and ddivu
9623 Workaround: For item 1), OS could make sure that the next page
9624 after the divide instruction is also mapped. For item 2), the
9625 compiler could make sure that the divide instruction is not in
9626 the branch delay slot."
9628 These processors have PRId values of 0x00004220 and 0x00004300 for
9629 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9632 mips_output_division (const char *division
, rtx
*operands
)
9637 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
9639 output_asm_insn (s
, operands
);
9642 if (TARGET_CHECK_ZERO_DIV
)
9646 output_asm_insn (s
, operands
);
9647 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
9649 else if (GENERATE_DIVIDE_TRAPS
)
9651 output_asm_insn (s
, operands
);
9656 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
9657 output_asm_insn (s
, operands
);
9658 s
= "break\t7%)\n1:";
9664 /* Return true if IN_INSN is a multiply-add or multiply-subtract
9665 instruction and if OUT_INSN assigns to the accumulator operand. */
9668 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
9672 x
= single_set (in_insn
);
9678 if (GET_CODE (x
) == PLUS
9679 && GET_CODE (XEXP (x
, 0)) == MULT
9680 && reg_set_p (XEXP (x
, 1), out_insn
))
9683 if (GET_CODE (x
) == MINUS
9684 && GET_CODE (XEXP (x
, 1)) == MULT
9685 && reg_set_p (XEXP (x
, 0), out_insn
))
9691 /* True if the dependency between OUT_INSN and IN_INSN is on the store
9692 data rather than the address. We need this because the cprestore
9693 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
9694 which causes the default routine to abort. We just return false
9698 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
9700 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
9703 return !store_data_bypass_p (out_insn
, in_insn
);
9706 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9707 dependencies have no cost, except on the 20Kc where output-dependence
9708 is treated like input-dependence. */
9711 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
9712 rtx dep ATTRIBUTE_UNUSED
, int cost
)
9714 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
9717 if (REG_NOTE_KIND (link
) != 0)
9722 /* Return the number of instructions that can be issued per cycle. */
9725 mips_issue_rate (void)
9729 case PROCESSOR_74KC
:
9730 case PROCESSOR_74KF2_1
:
9731 case PROCESSOR_74KF1_1
:
9732 case PROCESSOR_74KF3_2
:
9733 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9734 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9735 but in reality only a maximum of 3 insns can be issued as
9736 floating-point loads and stores also require a slot in the
9740 case PROCESSOR_20KC
:
9741 case PROCESSOR_R4130
:
9742 case PROCESSOR_R5400
:
9743 case PROCESSOR_R5500
:
9744 case PROCESSOR_R7000
:
9745 case PROCESSOR_R9000
:
9749 case PROCESSOR_SB1A
:
9750 /* This is actually 4, but we get better performance if we claim 3.
9751 This is partly because of unwanted speculative code motion with the
9752 larger number, and partly because in most common cases we can't
9753 reach the theoretical max of 4. */
9761 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9762 be as wide as the scheduling freedom in the DFA. */
9765 mips_multipass_dfa_lookahead (void)
9767 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9774 /* Remove the instruction at index LOWER from ready queue READY and
9775 reinsert it in front of the instruction at index HIGHER. LOWER must
9779 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
9784 new_head
= ready
[lower
];
9785 for (i
= lower
; i
< higher
; i
++)
9786 ready
[i
] = ready
[i
+ 1];
9787 ready
[i
] = new_head
;
9790 /* If the priority of the instruction at POS2 in the ready queue READY
9791 is within LIMIT units of that of the instruction at POS1, swap the
9792 instructions if POS2 is not already less than POS1. */
9795 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
9798 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
9803 ready
[pos1
] = ready
[pos2
];
9808 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9809 that may clobber hi or lo. */
9810 static rtx mips_macc_chains_last_hilo
;
9812 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9813 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9816 mips_macc_chains_record (rtx insn
)
9818 if (get_attr_may_clobber_hilo (insn
))
9819 mips_macc_chains_last_hilo
= insn
;
9822 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9823 has NREADY elements, looking for a multiply-add or multiply-subtract
9824 instruction that is cumulative with mips_macc_chains_last_hilo.
9825 If there is one, promote it ahead of anything else that might
9826 clobber hi or lo. */
9829 mips_macc_chains_reorder (rtx
*ready
, int nready
)
9833 if (mips_macc_chains_last_hilo
!= 0)
9834 for (i
= nready
- 1; i
>= 0; i
--)
9835 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
9837 for (j
= nready
- 1; j
> i
; j
--)
9838 if (recog_memoized (ready
[j
]) >= 0
9839 && get_attr_may_clobber_hilo (ready
[j
]))
9841 mips_promote_ready (ready
, i
, j
);
9848 /* The last instruction to be scheduled. */
9849 static rtx vr4130_last_insn
;
9851 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9852 points to an rtx that is initially an instruction. Nullify the rtx
9853 if the instruction uses the value of register X. */
9856 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
9861 insn_ptr
= (rtx
*) data
;
9864 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
9868 /* Return true if there is true register dependence between vr4130_last_insn
9872 vr4130_true_reg_dependence_p (rtx insn
)
9874 note_stores (PATTERN (vr4130_last_insn
),
9875 vr4130_true_reg_dependence_p_1
, &insn
);
9879 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9880 the ready queue and that INSN2 is the instruction after it, return
9881 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9882 in which INSN1 and INSN2 can probably issue in parallel, but for
9883 which (INSN2, INSN1) should be less sensitive to instruction
9884 alignment than (INSN1, INSN2). See 4130.md for more details. */
9887 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
9889 sd_iterator_def sd_it
;
9892 /* Check for the following case:
9894 1) there is some other instruction X with an anti dependence on INSN1;
9895 2) X has a higher priority than INSN2; and
9896 3) X is an arithmetic instruction (and thus has no unit restrictions).
9898 If INSN1 is the last instruction blocking X, it would better to
9899 choose (INSN1, X) over (INSN2, INSN1). */
9900 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
9901 if (DEP_TYPE (dep
) == REG_DEP_ANTI
9902 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
9903 && recog_memoized (DEP_CON (dep
)) >= 0
9904 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
9907 if (vr4130_last_insn
!= 0
9908 && recog_memoized (insn1
) >= 0
9909 && recog_memoized (insn2
) >= 0)
9911 /* See whether INSN1 and INSN2 use different execution units,
9912 or if they are both ALU-type instructions. If so, they can
9913 probably execute in parallel. */
9914 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
9915 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
9916 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
9918 /* If only one of the instructions has a dependence on
9919 vr4130_last_insn, prefer to schedule the other one first. */
9920 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
9921 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
9922 if (dep1_p
!= dep2_p
)
9925 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9926 is not an ALU-type instruction and if INSN1 uses the same
9927 execution unit. (Note that if this condition holds, we already
9928 know that INSN2 uses a different execution unit.) */
9929 if (class1
!= VR4130_CLASS_ALU
9930 && recog_memoized (vr4130_last_insn
) >= 0
9931 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
9938 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9939 queue with at least two instructions. Swap the first two if
9940 vr4130_swap_insns_p says that it could be worthwhile. */
9943 vr4130_reorder (rtx
*ready
, int nready
)
9945 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
9946 mips_promote_ready (ready
, nready
- 2, nready
- 1);
9949 /* Record whether last 74k AGEN instruction was a load or store. */
9950 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
9952 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
9953 resets to TYPE_UNKNOWN state. */
9956 mips_74k_agen_init (rtx insn
)
9958 if (!insn
|| !NONJUMP_INSN_P (insn
))
9959 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
9962 enum attr_type type
= get_attr_type (insn
);
9963 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
9964 mips_last_74k_agen_insn
= type
;
9968 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
9969 loads to be grouped together, and multiple stores to be grouped
9970 together. Swap things around in the ready queue to make this happen. */
9973 mips_74k_agen_reorder (rtx
*ready
, int nready
)
9976 int store_pos
, load_pos
;
9981 for (i
= nready
- 1; i
>= 0; i
--)
9983 rtx insn
= ready
[i
];
9984 if (USEFUL_INSN_P (insn
))
9985 switch (get_attr_type (insn
))
9988 if (store_pos
== -1)
10002 if (load_pos
== -1 || store_pos
== -1)
10005 switch (mips_last_74k_agen_insn
)
10008 /* Prefer to schedule loads since they have a higher latency. */
10010 /* Swap loads to the front of the queue. */
10011 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
10014 /* Swap stores to the front of the queue. */
10015 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
10022 /* Implement TARGET_SCHED_INIT. */
10025 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10026 int max_ready ATTRIBUTE_UNUSED
)
10028 mips_macc_chains_last_hilo
= 0;
10029 vr4130_last_insn
= 0;
10030 mips_74k_agen_init (NULL_RTX
);
10033 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
10036 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10037 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
10039 if (!reload_completed
10040 && TUNE_MACC_CHAINS
10042 mips_macc_chains_reorder (ready
, *nreadyp
);
10044 if (reload_completed
10046 && !TARGET_VR4130_ALIGN
10048 vr4130_reorder (ready
, *nreadyp
);
10051 mips_74k_agen_reorder (ready
, *nreadyp
);
10053 return mips_issue_rate ();
10056 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10059 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
10060 rtx insn
, int more
)
10062 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
10063 if (USEFUL_INSN_P (insn
))
10066 if (!reload_completed
&& TUNE_MACC_CHAINS
)
10067 mips_macc_chains_record (insn
);
10068 vr4130_last_insn
= insn
;
10070 mips_74k_agen_init (insn
);
10075 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10076 return the first operand of the associated PREF or PREFX insn. */
10079 mips_prefetch_cookie (rtx write
, rtx locality
)
10081 /* store_streamed / load_streamed. */
10082 if (INTVAL (locality
) <= 0)
10083 return GEN_INT (INTVAL (write
) + 4);
10085 /* store / load. */
10086 if (INTVAL (locality
) <= 2)
10089 /* store_retained / load_retained. */
10090 return GEN_INT (INTVAL (write
) + 6);
10093 /* This structure describes a single built-in function. */
10094 struct mips_builtin_description
{
10095 /* The code of the main .md file instruction. See mips_builtin_type
10096 for more information. */
10097 enum insn_code icode
;
10099 /* The floating-point comparison code to use with ICODE, if any. */
10100 enum mips_fp_condition cond
;
10102 /* The name of the built-in function. */
10105 /* Specifies how the function should be expanded. */
10106 enum mips_builtin_type builtin_type
;
10108 /* The function's prototype. */
10109 enum mips_function_type function_type
;
10111 /* The target flags required for this function. */
10115 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10116 FUNCTION_TYPE and TARGET_FLAGS are mips_builtin_description fields. */
10117 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10118 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10119 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10121 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
10122 require TARGET_FLAGS. */
10123 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10124 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10125 "__builtin_mips_" #INSN "_" #COND "_s", \
10126 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10127 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10128 "__builtin_mips_" #INSN "_" #COND "_d", \
10129 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10131 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10132 The lower and upper forms require TARGET_FLAGS while the any and all
10133 forms require MASK_MIPS3D. */
10134 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10135 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10136 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10137 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10138 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10139 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10140 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10141 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10142 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10143 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10144 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10145 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10146 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10148 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10149 require MASK_MIPS3D. */
10150 #define CMP_4S_BUILTINS(INSN, COND) \
10151 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10152 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10153 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10155 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10156 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10157 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10160 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10161 instruction requires TARGET_FLAGS. */
10162 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10163 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10164 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10165 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10167 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10168 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10169 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10172 /* Define all the built-in functions related to C.cond.fmt condition COND. */
10173 #define CMP_BUILTINS(COND) \
10174 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10175 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10176 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10177 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10178 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10179 CMP_4S_BUILTINS (c, COND), \
10180 CMP_4S_BUILTINS (cabs, COND)
10182 static const struct mips_builtin_description mips_ps_bdesc
[] = {
10183 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10184 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10185 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10186 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10187 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, MASK_PAIRED_SINGLE_FLOAT
),
10188 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10189 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10190 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
),
10192 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
,
10193 MASK_PAIRED_SINGLE_FLOAT
),
10194 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10195 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10196 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10197 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10199 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10200 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10201 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10202 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10203 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10204 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10206 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, MASK_MIPS3D
),
10207 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, MASK_MIPS3D
),
10208 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_MIPS3D
),
10209 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, MASK_MIPS3D
),
10210 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, MASK_MIPS3D
),
10211 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, MASK_MIPS3D
),
10213 MIPS_FP_CONDITIONS (CMP_BUILTINS
)
10216 /* Built-in functions for the SB-1 processor. */
10218 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10220 static const struct mips_builtin_description mips_sb1_bdesc
[] = {
10221 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, MASK_PAIRED_SINGLE_FLOAT
)
10224 /* Built-in functions for the DSP ASE. */
10226 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10227 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10228 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10229 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10230 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10232 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10233 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10234 mips_builtin_description fields. */
10235 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10236 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10237 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10239 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10240 branch instruction. TARGET_FLAGS is a mips_builtin_description field. */
10241 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10242 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10243 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10245 static const struct mips_builtin_description mips_dsp_bdesc
[] = {
10246 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10247 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10248 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10249 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10250 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10251 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10252 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10253 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10254 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10255 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10256 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10257 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10258 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10259 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, MASK_DSP
),
10260 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, MASK_DSP
),
10261 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10262 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10263 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10264 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, MASK_DSP
),
10265 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10266 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10267 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, MASK_DSP
),
10268 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10269 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10270 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10271 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10272 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10273 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10274 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10275 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, MASK_DSP
),
10276 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10277 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10278 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10279 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10280 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSP
),
10281 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10282 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSP
),
10283 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10284 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10285 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, MASK_DSP
),
10286 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10287 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10288 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10289 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10290 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, MASK_DSP
),
10291 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, MASK_DSP
),
10292 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, MASK_DSP
),
10293 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10294 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10295 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, MASK_DSP
),
10296 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10297 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10298 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10299 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10300 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10301 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, MASK_DSP
),
10302 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSP
),
10303 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10304 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSP
),
10305 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, MASK_DSP
),
10306 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, MASK_DSP
),
10307 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10308 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10309 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, MASK_DSP
),
10310 BPOSGE_BUILTIN (32, MASK_DSP
),
10312 /* The following are for the MIPS DSP ASE REV 2. */
10313 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, MASK_DSPR2
),
10314 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10315 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10316 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10317 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10318 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10319 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10320 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10321 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10322 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10323 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10324 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10325 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10326 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10327 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10328 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10329 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10330 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10331 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, MASK_DSPR2
),
10332 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSPR2
),
10333 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, MASK_DSPR2
),
10334 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, MASK_DSPR2
),
10335 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10336 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10337 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10338 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, MASK_DSPR2
),
10339 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10340 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10341 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10342 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10343 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10344 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, MASK_DSPR2
),
10345 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
),
10346 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, MASK_DSPR2
)
10349 static const struct mips_builtin_description mips_dsp_32only_bdesc
[] = {
10350 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10351 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10352 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10353 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, MASK_DSP
),
10354 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10355 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10356 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10357 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10358 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSP
),
10359 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10360 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10361 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10362 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSP
),
10363 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10364 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10365 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10366 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10367 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10368 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, MASK_DSP
),
10369 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10370 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, MASK_DSP
),
10372 /* The following are for the MIPS DSP ASE REV 2. */
10373 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10374 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10375 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSPR2
),
10376 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, MASK_DSPR2
),
10377 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, MASK_DSPR2
),
10378 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, MASK_DSPR2
),
10379 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10380 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, MASK_DSPR2
),
10381 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, MASK_DSPR2
),
10382 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10383 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10384 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10385 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10386 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
),
10387 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, MASK_DSPR2
)
10390 /* This structure describes an array of mips_builtin_description entries. */
10391 struct mips_bdesc_map
{
10392 /* The array that this entry describes. */
10393 const struct mips_builtin_description
*bdesc
;
10395 /* The number of entries in BDESC. */
10398 /* The target processor that supports the functions in BDESC.
10399 PROCESSOR_MAX means we enable them for all processors. */
10400 enum processor_type proc
;
10402 /* The functions in BDESC are not supported if any of these
10403 target flags are set. */
10404 int unsupported_target_flags
;
10407 /* All MIPS-specific built-in functions. */
10408 static const struct mips_bdesc_map mips_bdesc_arrays
[] = {
10409 { mips_ps_bdesc
, ARRAY_SIZE (mips_ps_bdesc
), PROCESSOR_MAX
, 0 },
10410 { mips_sb1_bdesc
, ARRAY_SIZE (mips_sb1_bdesc
), PROCESSOR_SB1
, 0 },
10411 { mips_dsp_bdesc
, ARRAY_SIZE (mips_dsp_bdesc
), PROCESSOR_MAX
, 0 },
10412 { mips_dsp_32only_bdesc
, ARRAY_SIZE (mips_dsp_32only_bdesc
),
10413 PROCESSOR_MAX
, MASK_64BIT
}
10416 /* MODE is a vector mode whose elements have type TYPE. Return the type
10417 of the vector itself. */
10420 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
10422 static tree types
[(int) MAX_MACHINE_MODE
];
10424 if (types
[(int) mode
] == NULL_TREE
)
10425 types
[(int) mode
] = build_vector_type_for_mode (type
, mode
);
10426 return types
[(int) mode
];
10429 /* Source-level argument types. */
10430 #define MIPS_ATYPE_VOID void_type_node
10431 #define MIPS_ATYPE_INT integer_type_node
10432 #define MIPS_ATYPE_POINTER ptr_type_node
10434 /* Standard mode-based argument types. */
10435 #define MIPS_ATYPE_SI intSI_type_node
10436 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10437 #define MIPS_ATYPE_DI intDI_type_node
10438 #define MIPS_ATYPE_SF float_type_node
10439 #define MIPS_ATYPE_DF double_type_node
10441 /* Vector argument types. */
10442 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10443 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10444 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10446 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10447 their associated MIPS_ATYPEs. */
10448 #define MIPS_FTYPE_ATYPES1(A, B) \
10449 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10451 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10452 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10454 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10455 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10457 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10458 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10461 /* Return the function type associated with function prototype TYPE. */
10464 mips_build_function_type (enum mips_function_type type
)
10466 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
10468 if (types
[(int) type
] == NULL_TREE
)
10471 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10472 case MIPS_FTYPE_NAME##NUM ARGS: \
10473 types[(int) type] \
10474 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10477 #include "config/mips/mips-ftypes.def"
10478 #undef DEF_MIPS_FTYPE
10480 gcc_unreachable ();
10483 return types
[(int) type
];
10486 /* Implement TARGET_INIT_BUILTINS. */
10489 mips_init_builtins (void)
10491 const struct mips_builtin_description
*d
;
10492 const struct mips_bdesc_map
*m
;
10493 unsigned int offset
;
10495 /* Iterate through all of the bdesc arrays, initializing all of the
10496 builtin functions. */
10498 for (m
= mips_bdesc_arrays
;
10499 m
< &mips_bdesc_arrays
[ARRAY_SIZE (mips_bdesc_arrays
)];
10502 if ((m
->proc
== PROCESSOR_MAX
|| m
->proc
== mips_arch
)
10503 && (m
->unsupported_target_flags
& target_flags
) == 0)
10504 for (d
= m
->bdesc
; d
< &m
->bdesc
[m
->size
]; d
++)
10505 if ((d
->target_flags
& target_flags
) == d
->target_flags
)
10506 add_builtin_function (d
->name
,
10507 mips_build_function_type (d
->function_type
),
10508 d
- m
->bdesc
+ offset
,
10509 BUILT_IN_MD
, NULL
, NULL
);
10514 /* Take argument ARGNO from EXP's argument list and convert it into a
10515 form suitable for input operand OPNO of instruction ICODE. Return the
10519 mips_prepare_builtin_arg (enum insn_code icode
,
10520 unsigned int opno
, tree exp
, unsigned int argno
)
10523 enum machine_mode mode
;
10525 value
= expand_normal (CALL_EXPR_ARG (exp
, argno
));
10526 mode
= insn_data
[icode
].operand
[opno
].mode
;
10527 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
10529 value
= copy_to_mode_reg (mode
, value
);
10530 /* Check the predicate again. */
10531 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
10533 error ("invalid argument to built-in function");
10541 /* Return an rtx suitable for output operand OP of instruction ICODE.
10542 If TARGET is non-null, try to use it where possible. */
10545 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
10547 enum machine_mode mode
;
10549 mode
= insn_data
[icode
].operand
[op
].mode
;
10550 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
10551 target
= gen_reg_rtx (mode
);
10556 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
10557 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
10558 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
10559 suggests a good place to put the result. */
10562 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
10565 rtx ops
[MAX_RECOG_OPERANDS
];
10568 /* Map any target to operand 0. */
10572 ops
[opno
] = mips_prepare_builtin_target (icode
, opno
, target
);
10576 /* Map the arguments to the other operands. The n_operands value
10577 for an expander includes match_dups and match_scratches as well as
10578 match_operands, so n_operands is only an upper bound on the number
10579 of arguments to the expander function. */
10580 gcc_assert (opno
+ call_expr_nargs (exp
) <= insn_data
[icode
].n_operands
);
10581 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++, opno
++)
10582 ops
[opno
] = mips_prepare_builtin_arg (icode
, opno
, exp
, argno
);
10587 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1]));
10591 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2]));
10595 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2], ops
[3]));
10599 gcc_unreachable ();
10604 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
10605 function; TYPE says which. EXP is the CALL_EXPR that calls the
10606 function, ICODE is the instruction that should be used to compare
10607 the first two arguments, and COND is the condition it should test.
10608 TARGET, if nonnull, suggests a good place to put the result. */
10611 mips_expand_builtin_movtf (enum mips_builtin_type type
,
10612 enum insn_code icode
, enum mips_fp_condition cond
,
10613 rtx target
, tree exp
)
10615 rtx cmp_result
, op0
, op1
;
10617 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10618 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 0);
10619 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 1);
10620 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
, GEN_INT (cond
)));
10622 icode
= CODE_FOR_mips_cond_move_tf_ps
;
10623 target
= mips_prepare_builtin_target (icode
, 0, target
);
10624 if (type
== MIPS_BUILTIN_MOVT
)
10626 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 2);
10627 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 3);
10631 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 2);
10632 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 3);
10634 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
10638 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10639 into TARGET otherwise. Return TARGET. */
10642 mips_builtin_branch_and_move (rtx condition
, rtx target
,
10643 rtx value_if_true
, rtx value_if_false
)
10645 rtx true_label
, done_label
;
10647 true_label
= gen_label_rtx ();
10648 done_label
= gen_label_rtx ();
10650 /* First assume that CONDITION is false. */
10651 mips_emit_move (target
, value_if_false
);
10653 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10654 emit_jump_insn (gen_condjump (condition
, true_label
));
10655 emit_jump_insn (gen_jump (done_label
));
10658 /* Fix TARGET if CONDITION is true. */
10659 emit_label (true_label
);
10660 mips_emit_move (target
, value_if_true
);
10662 emit_label (done_label
);
10666 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
10667 the CALL_EXPR that calls the function, ICODE is the code of the
10668 comparison instruction, and COND is the condition it should test.
10669 TARGET, if nonnull, suggests a good place to put the boolean result. */
10672 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
10673 enum insn_code icode
, enum mips_fp_condition cond
,
10674 rtx target
, tree exp
)
10676 rtx offset
, condition
, cmp_result
, args
[MAX_RECOG_OPERANDS
];
10679 if (target
== 0 || GET_MODE (target
) != SImode
)
10680 target
= gen_reg_rtx (SImode
);
10682 /* The instruction should have a target operand, an operand for each
10683 argument, and an operand for COND. */
10684 gcc_assert (call_expr_nargs (exp
) + 2 == insn_data
[icode
].n_operands
);
10686 /* Prepare the operands to the comparison. */
10687 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
10688 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
10689 args
[argno
] = mips_prepare_builtin_arg (icode
, argno
+ 1, exp
, argno
);
10691 switch (insn_data
[icode
].n_operands
)
10694 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
10699 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
10700 args
[2], args
[3], GEN_INT (cond
)));
10704 gcc_unreachable ();
10707 /* If the comparison sets more than one register, we define the result
10708 to be 0 if all registers are false and -1 if all registers are true.
10709 The value of the complete result is indeterminate otherwise. */
10710 switch (builtin_type
)
10712 case MIPS_BUILTIN_CMP_ALL
:
10713 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
10714 return mips_builtin_branch_and_move (condition
, target
,
10715 const0_rtx
, const1_rtx
);
10717 case MIPS_BUILTIN_CMP_UPPER
:
10718 case MIPS_BUILTIN_CMP_LOWER
:
10719 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
10720 condition
= gen_single_cc (cmp_result
, offset
);
10721 return mips_builtin_branch_and_move (condition
, target
,
10722 const1_rtx
, const0_rtx
);
10725 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
10726 return mips_builtin_branch_and_move (condition
, target
,
10727 const1_rtx
, const0_rtx
);
10731 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
10732 if nonnull, suggests a good place to put the boolean result. */
10735 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
10737 rtx condition
, cmp_result
;
10740 if (target
== 0 || GET_MODE (target
) != SImode
)
10741 target
= gen_reg_rtx (SImode
);
10743 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
10745 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
10750 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
10751 return mips_builtin_branch_and_move (condition
, target
,
10752 const1_rtx
, const0_rtx
);
10755 /* EXP is a CALL_EXPR that calls the function described by BDESC.
10756 Expand the call and return an rtx for its return value.
10757 TARGET, if nonnull, suggests a good place to put this value. */
10760 mips_expand_builtin_1 (const struct mips_builtin_description
*bdesc
,
10761 tree exp
, rtx target
)
10763 switch (bdesc
->builtin_type
)
10765 case MIPS_BUILTIN_DIRECT
:
10766 return mips_expand_builtin_direct (bdesc
->icode
, target
, exp
, true);
10768 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
10769 return mips_expand_builtin_direct (bdesc
->icode
, target
, exp
, false);
10771 case MIPS_BUILTIN_MOVT
:
10772 case MIPS_BUILTIN_MOVF
:
10773 return mips_expand_builtin_movtf (bdesc
->builtin_type
, bdesc
->icode
,
10774 bdesc
->cond
, target
, exp
);
10776 case MIPS_BUILTIN_CMP_ANY
:
10777 case MIPS_BUILTIN_CMP_ALL
:
10778 case MIPS_BUILTIN_CMP_UPPER
:
10779 case MIPS_BUILTIN_CMP_LOWER
:
10780 case MIPS_BUILTIN_CMP_SINGLE
:
10781 return mips_expand_builtin_compare (bdesc
->builtin_type
, bdesc
->icode
,
10782 bdesc
->cond
, target
, exp
);
10784 case MIPS_BUILTIN_BPOSGE32
:
10785 return mips_expand_builtin_bposge (bdesc
->builtin_type
, target
);
10787 gcc_unreachable ();
10790 /* Implement TARGET_EXPAND_BUILTIN. */
10793 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
10794 enum machine_mode mode ATTRIBUTE_UNUSED
,
10795 int ignore ATTRIBUTE_UNUSED
)
10798 unsigned int fcode
;
10799 const struct mips_bdesc_map
*m
;
10801 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10802 fcode
= DECL_FUNCTION_CODE (fndecl
);
10805 error ("built-in function %qs not supported for MIPS16",
10806 IDENTIFIER_POINTER (DECL_NAME (fndecl
)));
10810 for (m
= mips_bdesc_arrays
;
10811 m
< &mips_bdesc_arrays
[ARRAY_SIZE (mips_bdesc_arrays
)];
10814 if (fcode
< m
->size
)
10815 return mips_expand_builtin_1 (m
->bdesc
+ fcode
, exp
, target
);
10818 gcc_unreachable ();
10821 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
10822 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
10823 struct mips16_constant
{
10824 struct mips16_constant
*next
;
10827 enum machine_mode mode
;
10830 /* Information about an incomplete MIPS16 constant pool. FIRST is the
10831 first constant, HIGHEST_ADDRESS is the highest address that the first
10832 byte of the pool can have, and INSN_ADDRESS is the current instruction
10834 struct mips16_constant_pool
{
10835 struct mips16_constant
*first
;
10836 int highest_address
;
10840 /* Add constant VALUE to POOL and return its label. MODE is the
10841 value's mode (used for CONST_INTs, etc.). */
10844 mips16_add_constant (struct mips16_constant_pool
*pool
,
10845 rtx value
, enum machine_mode mode
)
10847 struct mips16_constant
**p
, *c
;
10848 bool first_of_size_p
;
10850 /* See whether the constant is already in the pool. If so, return the
10851 existing label, otherwise leave P pointing to the place where the
10852 constant should be added.
10854 Keep the pool sorted in increasing order of mode size so that we can
10855 reduce the number of alignments needed. */
10856 first_of_size_p
= true;
10857 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
10859 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
10860 return (*p
)->label
;
10861 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
10863 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
10864 first_of_size_p
= false;
10867 /* In the worst case, the constant needed by the earliest instruction
10868 will end up at the end of the pool. The entire pool must then be
10869 accessible from that instruction.
10871 When adding the first constant, set the pool's highest address to
10872 the address of the first out-of-range byte. Adjust this address
10873 downwards each time a new constant is added. */
10874 if (pool
->first
== 0)
10875 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
10876 of the instruction with the lowest two bits clear. The base PC
10877 value for LDPC has the lowest three bits clear. Assume the worst
10878 case here; namely that the PC-relative instruction occupies the
10879 last 2 bytes in an aligned word. */
10880 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
10881 pool
->highest_address
-= GET_MODE_SIZE (mode
);
10882 if (first_of_size_p
)
10883 /* Take into account the worst possible padding due to alignment. */
10884 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
10886 /* Create a new entry. */
10887 c
= XNEW (struct mips16_constant
);
10890 c
->label
= gen_label_rtx ();
10897 /* Output constant VALUE after instruction INSN and return the last
10898 instruction emitted. MODE is the mode of the constant. */
10901 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
10903 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
10905 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
10906 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
10909 if (SCALAR_FLOAT_MODE_P (mode
))
10910 return emit_insn_after (gen_consttable_float (value
), insn
);
10912 if (VECTOR_MODE_P (mode
))
10916 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
10917 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
10918 CONST_VECTOR_ELT (value
, i
), insn
);
10922 gcc_unreachable ();
10925 /* Dump out the constants in CONSTANTS after INSN. */
10928 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
10930 struct mips16_constant
*c
, *next
;
10934 for (c
= constants
; c
!= NULL
; c
= next
)
10936 /* If necessary, increase the alignment of PC. */
10937 if (align
< GET_MODE_SIZE (c
->mode
))
10939 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
10940 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
10942 align
= GET_MODE_SIZE (c
->mode
);
10944 insn
= emit_label_after (c
->label
, insn
);
10945 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
10951 emit_barrier_after (insn
);
10954 /* Return the length of instruction INSN. */
10957 mips16_insn_length (rtx insn
)
10961 rtx body
= PATTERN (insn
);
10962 if (GET_CODE (body
) == ADDR_VEC
)
10963 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
10964 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
10965 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
10967 return get_attr_length (insn
);
10970 /* If *X is a symbolic constant that refers to the constant pool, add
10971 the constant to POOL and rewrite *X to use the constant's label. */
10974 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
10976 rtx base
, offset
, label
;
10978 split_const (*x
, &base
, &offset
);
10979 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
10981 label
= mips16_add_constant (pool
, get_pool_constant (base
),
10982 get_pool_mode (base
));
10983 base
= gen_rtx_LABEL_REF (Pmode
, label
);
10984 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
10988 /* This structure is used to communicate with mips16_rewrite_pool_refs.
10989 INSN is the instruction we're rewriting and POOL points to the current
10991 struct mips16_rewrite_pool_refs_info
{
10993 struct mips16_constant_pool
*pool
;
10996 /* Rewrite *X so that constant pool references refer to the constant's
10997 label instead. DATA points to a mips16_rewrite_pool_refs_info
11001 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
11003 struct mips16_rewrite_pool_refs_info
*info
= data
;
11005 if (force_to_mem_operand (*x
, Pmode
))
11007 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
11008 validate_change (info
->insn
, x
, mem
, false);
11013 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
11017 if (TARGET_MIPS16_TEXT_LOADS
)
11018 mips16_rewrite_pool_constant (info
->pool
, x
);
11020 return GET_CODE (*x
) == CONST
? -1 : 0;
11023 /* Build MIPS16 constant pools. */
11026 mips16_lay_out_constants (void)
11028 struct mips16_constant_pool pool
;
11029 struct mips16_rewrite_pool_refs_info info
;
11032 if (!TARGET_MIPS16_PCREL_LOADS
)
11036 memset (&pool
, 0, sizeof (pool
));
11037 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11039 /* Rewrite constant pool references in INSN. */
11044 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
11047 pool
.insn_address
+= mips16_insn_length (insn
);
11049 if (pool
.first
!= NULL
)
11051 /* If there are no natural barriers between the first user of
11052 the pool and the highest acceptable address, we'll need to
11053 create a new instruction to jump around the constant pool.
11054 In the worst case, this instruction will be 4 bytes long.
11056 If it's too late to do this transformation after INSN,
11057 do it immediately before INSN. */
11058 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
11062 label
= gen_label_rtx ();
11064 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
11065 JUMP_LABEL (jump
) = label
;
11066 LABEL_NUSES (label
) = 1;
11067 barrier
= emit_barrier_after (jump
);
11069 emit_label_after (label
, barrier
);
11070 pool
.insn_address
+= 4;
11073 /* See whether the constant pool is now out of range of the first
11074 user. If so, output the constants after the previous barrier.
11075 Note that any instructions between BARRIER and INSN (inclusive)
11076 will use negative offsets to refer to the pool. */
11077 if (pool
.insn_address
> pool
.highest_address
)
11079 mips16_emit_constants (pool
.first
, barrier
);
11083 else if (BARRIER_P (insn
))
11087 mips16_emit_constants (pool
.first
, get_last_insn ());
11090 /* A temporary variable used by for_each_rtx callbacks, etc. */
11091 static rtx mips_sim_insn
;
11093 /* A structure representing the state of the processor pipeline.
11094 Used by the mips_sim_* family of functions. */
11096 /* The maximum number of instructions that can be issued in a cycle.
11097 (Caches mips_issue_rate.) */
11098 unsigned int issue_rate
;
11100 /* The current simulation time. */
11103 /* How many more instructions can be issued in the current cycle. */
11104 unsigned int insns_left
;
11106 /* LAST_SET[X].INSN is the last instruction to set register X.
11107 LAST_SET[X].TIME is the time at which that instruction was issued.
11108 INSN is null if no instruction has yet set register X. */
11112 } last_set
[FIRST_PSEUDO_REGISTER
];
11114 /* The pipeline's current DFA state. */
11118 /* Reset STATE to the initial simulation state. */
11121 mips_sim_reset (struct mips_sim
*state
)
11124 state
->insns_left
= state
->issue_rate
;
11125 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
11126 state_reset (state
->dfa_state
);
11129 /* Initialize STATE before its first use. DFA_STATE points to an
11130 allocated but uninitialized DFA state. */
11133 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
11135 state
->issue_rate
= mips_issue_rate ();
11136 state
->dfa_state
= dfa_state
;
11137 mips_sim_reset (state
);
11140 /* Advance STATE by one clock cycle. */
11143 mips_sim_next_cycle (struct mips_sim
*state
)
11146 state
->insns_left
= state
->issue_rate
;
11147 state_transition (state
->dfa_state
, 0);
11150 /* Advance simulation state STATE until instruction INSN can read
11154 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
11156 unsigned int regno
, end_regno
;
11158 end_regno
= END_REGNO (reg
);
11159 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
11160 if (state
->last_set
[regno
].insn
!= 0)
11164 t
= (state
->last_set
[regno
].time
11165 + insn_latency (state
->last_set
[regno
].insn
, insn
));
11166 while (state
->time
< t
)
11167 mips_sim_next_cycle (state
);
11171 /* A for_each_rtx callback. If *X is a register, advance simulation state
11172 DATA until mips_sim_insn can read the register's value. */
11175 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
11178 mips_sim_wait_reg (data
, mips_sim_insn
, *x
);
11182 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
11185 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
11187 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
11190 /* Advance simulation state STATE until all of INSN's register
11191 dependencies are satisfied. */
11194 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
11196 mips_sim_insn
= insn
;
11197 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
11200 /* Advance simulation state STATE until the units required by
11201 instruction INSN are available. */
11204 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
11208 tmp_state
= alloca (state_size ());
11209 while (state
->insns_left
== 0
11210 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
11211 state_transition (tmp_state
, insn
) >= 0))
11212 mips_sim_next_cycle (state
);
11215 /* Advance simulation state STATE until INSN is ready to issue. */
11218 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
11220 mips_sim_wait_regs (state
, insn
);
11221 mips_sim_wait_units (state
, insn
);
11224 /* mips_sim_insn has just set X. Update the LAST_SET array
11225 in simulation state DATA. */
11228 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
11230 struct mips_sim
*state
;
11235 unsigned int regno
, end_regno
;
11237 end_regno
= END_REGNO (x
);
11238 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
11240 state
->last_set
[regno
].insn
= mips_sim_insn
;
11241 state
->last_set
[regno
].time
= state
->time
;
11246 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
11247 can issue immediately (i.e., that mips_sim_wait_insn has already
11251 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
11253 state_transition (state
->dfa_state
, insn
);
11254 state
->insns_left
--;
11256 mips_sim_insn
= insn
;
11257 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
11260 /* Simulate issuing a NOP in state STATE. */
11263 mips_sim_issue_nop (struct mips_sim
*state
)
11265 if (state
->insns_left
== 0)
11266 mips_sim_next_cycle (state
);
11267 state
->insns_left
--;
11270 /* Update simulation state STATE so that it's ready to accept the instruction
11271 after INSN. INSN should be part of the main rtl chain, not a member of a
11275 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
11277 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11279 mips_sim_issue_nop (state
);
11281 switch (GET_CODE (SEQ_BEGIN (insn
)))
11285 /* We can't predict the processor state after a call or label. */
11286 mips_sim_reset (state
);
11290 /* The delay slots of branch likely instructions are only executed
11291 when the branch is taken. Therefore, if the caller has simulated
11292 the delay slot instruction, STATE does not really reflect the state
11293 of the pipeline for the instruction after the delay slot. Also,
11294 branch likely instructions tend to incur a penalty when not taken,
11295 so there will probably be an extra delay between the branch and
11296 the instruction after the delay slot. */
11297 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
11298 mips_sim_reset (state
);
11306 /* The VR4130 pipeline issues aligned pairs of instructions together,
11307 but it stalls the second instruction if it depends on the first.
11308 In order to cut down the amount of logic required, this dependence
11309 check is not based on a full instruction decode. Instead, any non-SPECIAL
11310 instruction is assumed to modify the register specified by bits 20-16
11311 (which is usually the "rt" field).
11313 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
11314 input, so we can end up with a false dependence between the branch
11315 and its delay slot. If this situation occurs in instruction INSN,
11316 try to avoid it by swapping rs and rt. */
11319 vr4130_avoid_branch_rt_conflict (rtx insn
)
11323 first
= SEQ_BEGIN (insn
);
11324 second
= SEQ_END (insn
);
11326 && NONJUMP_INSN_P (second
)
11327 && GET_CODE (PATTERN (first
)) == SET
11328 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
11329 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
11331 /* Check for the right kind of condition. */
11332 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
11333 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
11334 && REG_P (XEXP (cond
, 0))
11335 && REG_P (XEXP (cond
, 1))
11336 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
11337 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
11339 /* SECOND mentions the rt register but not the rs register. */
11340 rtx tmp
= XEXP (cond
, 0);
11341 XEXP (cond
, 0) = XEXP (cond
, 1);
11342 XEXP (cond
, 1) = tmp
;
11347 /* Implement -mvr4130-align. Go through each basic block and simulate the
11348 processor pipeline. If we find that a pair of instructions could execute
11349 in parallel, and the first of those instructions is not 8-byte aligned,
11350 insert a nop to make it aligned. */
11353 vr4130_align_insns (void)
11355 struct mips_sim state
;
11356 rtx insn
, subinsn
, last
, last2
, next
;
11361 /* LAST is the last instruction before INSN to have a nonzero length.
11362 LAST2 is the last such instruction before LAST. */
11366 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11369 mips_sim_init (&state
, alloca (state_size ()));
11370 for (insn
= get_insns (); insn
!= 0; insn
= next
)
11372 unsigned int length
;
11374 next
= NEXT_INSN (insn
);
11376 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11377 This isn't really related to the alignment pass, but we do it on
11378 the fly to avoid a separate instruction walk. */
11379 vr4130_avoid_branch_rt_conflict (insn
);
11381 if (USEFUL_INSN_P (insn
))
11382 FOR_EACH_SUBINSN (subinsn
, insn
)
11384 mips_sim_wait_insn (&state
, subinsn
);
11386 /* If we want this instruction to issue in parallel with the
11387 previous one, make sure that the previous instruction is
11388 aligned. There are several reasons why this isn't worthwhile
11389 when the second instruction is a call:
11391 - Calls are less likely to be performance critical,
11392 - There's a good chance that the delay slot can execute
11393 in parallel with the call.
11394 - The return address would then be unaligned.
11396 In general, if we're going to insert a nop between instructions
11397 X and Y, it's better to insert it immediately after X. That
11398 way, if the nop makes Y aligned, it will also align any labels
11399 between X and Y. */
11400 if (state
.insns_left
!= state
.issue_rate
11401 && !CALL_P (subinsn
))
11403 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
11405 /* SUBINSN is the first instruction in INSN and INSN is
11406 aligned. We want to align the previous instruction
11407 instead, so insert a nop between LAST2 and LAST.
11409 Note that LAST could be either a single instruction
11410 or a branch with a delay slot. In the latter case,
11411 LAST, like INSN, is already aligned, but the delay
11412 slot must have some extra delay that stops it from
11413 issuing at the same time as the branch. We therefore
11414 insert a nop before the branch in order to align its
11416 emit_insn_after (gen_nop (), last2
);
11419 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
11421 /* SUBINSN is the delay slot of INSN, but INSN is
11422 currently unaligned. Insert a nop between
11423 LAST and INSN to align it. */
11424 emit_insn_after (gen_nop (), last
);
11428 mips_sim_issue_insn (&state
, subinsn
);
11430 mips_sim_finish_insn (&state
, insn
);
11432 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11433 length
= get_attr_length (insn
);
11436 /* If the instruction is an asm statement or multi-instruction
11437 mips.md patern, the length is only an estimate. Insert an
11438 8 byte alignment after it so that the following instructions
11439 can be handled correctly. */
11440 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
11441 && (recog_memoized (insn
) < 0 || length
>= 8))
11443 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
11444 next
= NEXT_INSN (next
);
11445 mips_sim_next_cycle (&state
);
11448 else if (length
& 4)
11449 aligned_p
= !aligned_p
;
11454 /* See whether INSN is an aligned label. */
11455 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
11461 /* This structure records that the current function has a LO_SUM
11462 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
11463 the largest offset applied to BASE by all such LO_SUMs. */
11464 struct mips_lo_sum_offset
{
11466 HOST_WIDE_INT offset
;
11469 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
11472 mips_hash_base (rtx base
)
11474 int do_not_record_p
;
11476 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
11479 /* Hash-table callbacks for mips_lo_sum_offsets. */
11482 mips_lo_sum_offset_hash (const void *entry
)
11484 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
11488 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
11490 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
11491 (const_rtx
) value
);
11494 /* Look up symbolic constant X in HTAB, which is a hash table of
11495 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
11496 paired with a recorded LO_SUM, otherwise record X in the table. */
11499 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
11503 struct mips_lo_sum_offset
*entry
;
11505 /* Split X into a base and offset. */
11506 split_const (x
, &base
, &offset
);
11507 if (UNSPEC_ADDRESS_P (base
))
11508 base
= UNSPEC_ADDRESS (base
);
11510 /* Look up the base in the hash table. */
11511 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
11515 entry
= (struct mips_lo_sum_offset
*) *slot
;
11516 if (option
== INSERT
)
11520 entry
= XNEW (struct mips_lo_sum_offset
);
11521 entry
->base
= base
;
11522 entry
->offset
= INTVAL (offset
);
11527 if (INTVAL (offset
) > entry
->offset
)
11528 entry
->offset
= INTVAL (offset
);
11531 return INTVAL (offset
) <= entry
->offset
;
11534 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
11535 Record every LO_SUM in *LOC. */
11538 mips_record_lo_sum (rtx
*loc
, void *data
)
11540 if (GET_CODE (*loc
) == LO_SUM
)
11541 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
11545 /* Return true if INSN is a SET of an orphaned high-part relocation.
11546 HTAB is a hash table of mips_lo_sum_offsets that describes all the
11547 LO_SUMs in the current function. */
11550 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
11552 enum mips_symbol_type type
;
11555 set
= single_set (insn
);
11558 /* Check for %his. */
11560 if (GET_CODE (x
) == HIGH
11561 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
11562 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
11564 /* Check for local %gots (and %got_pages, which is redundant but OK). */
11565 if (GET_CODE (x
) == UNSPEC
11566 && XINT (x
, 1) == UNSPEC_LOAD_GOT
11567 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
11568 SYMBOL_CONTEXT_LEA
, &type
)
11569 && type
== SYMBOL_GOTOFF_PAGE
)
11570 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
11575 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
11576 INSN and a previous instruction, avoid it by inserting nops after
11579 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
11580 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
11581 before using the value of that register. *HILO_DELAY counts the
11582 number of instructions since the last hilo hazard (that is,
11583 the number of instructions since the last MFLO or MFHI).
11585 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
11586 for the next instruction.
11588 LO_REG is an rtx for the LO register, used in dependence checking. */
11591 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
11592 rtx
*delayed_reg
, rtx lo_reg
)
11597 pattern
= PATTERN (insn
);
11599 /* Do not put the whole function in .set noreorder if it contains
11600 an asm statement. We don't know whether there will be hazards
11601 between the asm statement and the gcc-generated code. */
11602 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
11603 cfun
->machine
->all_noreorder_p
= false;
11605 /* Ignore zero-length instructions (barriers and the like). */
11606 ninsns
= get_attr_length (insn
) / 4;
11610 /* Work out how many nops are needed. Note that we only care about
11611 registers that are explicitly mentioned in the instruction's pattern.
11612 It doesn't matter that calls use the argument registers or that they
11613 clobber hi and lo. */
11614 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
11615 nops
= 2 - *hilo_delay
;
11616 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
11621 /* Insert the nops between this instruction and the previous one.
11622 Each new nop takes us further from the last hilo hazard. */
11623 *hilo_delay
+= nops
;
11625 emit_insn_after (gen_hazard_nop (), after
);
11627 /* Set up the state for the next instruction. */
11628 *hilo_delay
+= ninsns
;
11630 if (INSN_CODE (insn
) >= 0)
11631 switch (get_attr_hazard (insn
))
11641 set
= single_set (insn
);
11643 *delayed_reg
= SET_DEST (set
);
11648 /* Go through the instruction stream and insert nops where necessary.
11649 Also delete any high-part relocations whose partnering low parts
11650 are now all dead. See if the whole function can then be put into
11651 .set noreorder and .set nomacro. */
11654 mips_reorg_process_insns (void)
11656 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
11660 /* Force all instructions to be split into their final form. */
11661 split_all_insns_noflow ();
11663 /* Recalculate instruction lengths without taking nops into account. */
11664 cfun
->machine
->ignore_hazard_length_p
= true;
11665 shorten_branches (get_insns ());
11667 cfun
->machine
->all_noreorder_p
= true;
11669 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
11670 if (!TARGET_EXPLICIT_RELOCS
)
11671 cfun
->machine
->all_noreorder_p
= false;
11673 /* Profiled functions can't be all noreorder because the profiler
11674 support uses assembler macros. */
11676 cfun
->machine
->all_noreorder_p
= false;
11678 /* Code compiled with -mfix-vr4120 can't be all noreorder because
11679 we rely on the assembler to work around some errata. */
11680 if (TARGET_FIX_VR4120
)
11681 cfun
->machine
->all_noreorder_p
= false;
11683 /* The same is true for -mfix-vr4130 if we might generate MFLO or
11684 MFHI instructions. Note that we avoid using MFLO and MFHI if
11685 the VR4130 MACC and DMACC instructions are available instead;
11686 see the *mfhilo_{si,di}_macc patterns. */
11687 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
11688 cfun
->machine
->all_noreorder_p
= false;
11690 htab
= htab_create (37, mips_lo_sum_offset_hash
,
11691 mips_lo_sum_offset_eq
, free
);
11693 /* Make a first pass over the instructions, recording all the LO_SUMs. */
11694 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
11695 FOR_EACH_SUBINSN (subinsn
, insn
)
11696 if (INSN_P (subinsn
))
11697 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
11702 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
11704 /* Make a second pass over the instructions. Delete orphaned
11705 high-part relocations or turn them into NOPs. Avoid hazards
11706 by inserting NOPs. */
11707 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
11709 next_insn
= NEXT_INSN (insn
);
11712 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
11714 /* If we find an orphaned high-part relocation in a delay
11715 slot, it's easier to turn that instruction into a NOP than
11716 to delete it. The delay slot will be a NOP either way. */
11717 FOR_EACH_SUBINSN (subinsn
, insn
)
11718 if (INSN_P (subinsn
))
11720 if (mips_orphaned_high_part_p (htab
, subinsn
))
11722 PATTERN (subinsn
) = gen_nop ();
11723 INSN_CODE (subinsn
) = CODE_FOR_nop
;
11725 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
11726 &delayed_reg
, lo_reg
);
11732 /* INSN is a single instruction. Delete it if it's an
11733 orphaned high-part relocation. */
11734 if (mips_orphaned_high_part_p (htab
, insn
))
11735 delete_insn (insn
);
11738 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
11739 &delayed_reg
, lo_reg
);
11746 htab_delete (htab
);
11749 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
11754 mips16_lay_out_constants ();
11755 if (mips_base_delayed_branch
)
11756 dbr_schedule (get_insns ());
11757 mips_reorg_process_insns ();
11758 if (TARGET_EXPLICIT_RELOCS
&& TUNE_MIPS4130
&& TARGET_VR4130_ALIGN
)
11759 vr4130_align_insns ();
11762 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
11763 in order to avoid duplicating too much logic from elsewhere. */
11766 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11767 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11770 rtx
this, temp1
, temp2
, insn
, fnaddr
;
11771 bool use_sibcall_p
;
11773 /* Pretend to be a post-reload pass while generating rtl. */
11774 reload_completed
= 1;
11776 /* Mark the end of the (empty) prologue. */
11777 emit_note (NOTE_INSN_PROLOGUE_END
);
11779 /* Determine if we can use a sibcall to call FUNCTION directly. */
11780 fnaddr
= XEXP (DECL_RTL (function
), 0);
11781 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
11782 && const_call_insn_operand (fnaddr
, Pmode
));
11784 /* Determine if we need to load FNADDR from the GOT. */
11785 if (!use_sibcall_p
)
11786 switch (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))
11788 case SYMBOL_GOT_PAGE_OFST
:
11789 case SYMBOL_GOT_DISP
:
11790 /* Pick a global pointer. Use a call-clobbered register if
11791 TARGET_CALL_SAVED_GP. */
11792 cfun
->machine
->global_pointer
=
11793 TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
11794 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
11796 /* Set up the global pointer for n32 or n64 abicalls. */
11797 mips_emit_loadgp ();
11804 /* We need two temporary registers in some cases. */
11805 temp1
= gen_rtx_REG (Pmode
, 2);
11806 temp2
= gen_rtx_REG (Pmode
, 3);
11808 /* Find out which register contains the "this" pointer. */
11809 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11810 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
11812 this = gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
11814 /* Add DELTA to THIS. */
11817 rtx offset
= GEN_INT (delta
);
11818 if (!SMALL_OPERAND (delta
))
11820 mips_emit_move (temp1
, offset
);
11823 emit_insn (gen_add3_insn (this, this, offset
));
11826 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
11827 if (vcall_offset
!= 0)
11831 /* Set TEMP1 to *THIS. */
11832 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this));
11834 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
11835 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
11837 /* Load the offset and add it to THIS. */
11838 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
11839 emit_insn (gen_add3_insn (this, this, temp1
));
11842 /* Jump to the target function. Use a sibcall if direct jumps are
11843 allowed, otherwise load the address into a register first. */
11846 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
11847 SIBLING_CALL_P (insn
) = 1;
11851 /* This is messy. GAS treats "la $25,foo" as part of a call
11852 sequence and may allow a global "foo" to be lazily bound.
11853 The general move patterns therefore reject this combination.
11855 In this context, lazy binding would actually be OK
11856 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
11857 TARGET_CALL_SAVED_GP; see mips_load_call_address.
11858 We must therefore load the address via a temporary
11859 register if mips_dangerous_for_la25_p.
11861 If we jump to the temporary register rather than $25, the assembler
11862 can use the move insn to fill the jump's delay slot. */
11863 if (TARGET_USE_PIC_FN_ADDR_REG
11864 && !mips_dangerous_for_la25_p (fnaddr
))
11865 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
11866 mips_load_call_address (temp1
, fnaddr
, true);
11868 if (TARGET_USE_PIC_FN_ADDR_REG
11869 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
11870 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
11871 emit_jump_insn (gen_indirect_jump (temp1
));
11874 /* Run just enough of rest_of_compilation. This sequence was
11875 "borrowed" from alpha.c. */
11876 insn
= get_insns ();
11877 insn_locators_alloc ();
11878 split_all_insns_noflow ();
11879 mips16_lay_out_constants ();
11880 shorten_branches (insn
);
11881 final_start_function (insn
, file
, 1);
11882 final (insn
, file
, 1);
11883 final_end_function ();
11884 free_after_compilation (cfun
);
11886 /* Clean up the vars set above. Note that final_end_function resets
11887 the global pointer for us. */
11888 reload_completed
= 0;
11891 /* The last argument passed to mips_set_mips16_mode, or negative if the
11892 function hasn't been called yet. */
11893 static GTY(()) int was_mips16_p
= -1;
11895 /* Set up the target-dependent global state so that it matches the
11896 current function's ISA mode. */
11899 mips_set_mips16_mode (int mips16_p
)
11901 if (mips16_p
== was_mips16_p
)
11904 /* Restore base settings of various flags. */
11905 target_flags
= mips_base_target_flags
;
11906 flag_schedule_insns
= mips_base_schedule_insns
;
11907 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
11908 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
11909 align_loops
= mips_base_align_loops
;
11910 align_jumps
= mips_base_align_jumps
;
11911 align_functions
= mips_base_align_functions
;
11915 /* Switch to MIPS16 mode. */
11916 target_flags
|= MASK_MIPS16
;
11918 /* Don't run the scheduler before reload, since it tends to
11919 increase register pressure. */
11920 flag_schedule_insns
= 0;
11922 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
11923 the whole function to be in a single section. */
11924 flag_reorder_blocks_and_partition
= 0;
11926 /* Don't move loop invariants, because it tends to increase
11927 register pressure. It also introduces an extra move in cases
11928 where the constant is the first operand in a two-operand binary
11929 instruction, or when it forms a register argument to a functon
11931 flag_move_loop_invariants
= 0;
11933 /* Silently disable -mexplicit-relocs since it doesn't apply
11934 to MIPS16 code. Even so, it would overly pedantic to warn
11935 about "-mips16 -mexplicit-relocs", especially given that
11936 we use a %gprel() operator. */
11937 target_flags
&= ~MASK_EXPLICIT_RELOCS
;
11939 /* Experiments suggest we get the best overall section-anchor
11940 results from using the range of an unextended LW or SW. Code
11941 that makes heavy use of byte or short accesses can do better
11942 with ranges of 0...31 and 0...63 respectively, but most code is
11943 sensitive to the range of LW and SW instead. */
11944 targetm
.min_anchor_offset
= 0;
11945 targetm
.max_anchor_offset
= 127;
11947 if (flag_pic
|| TARGET_ABICALLS
)
11948 sorry ("MIPS16 PIC");
11950 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
11951 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
11955 /* Switch to normal (non-MIPS16) mode. */
11956 target_flags
&= ~MASK_MIPS16
;
11958 /* Provide default values for align_* for 64-bit targets. */
11961 if (align_loops
== 0)
11963 if (align_jumps
== 0)
11965 if (align_functions
== 0)
11966 align_functions
= 8;
11969 targetm
.min_anchor_offset
= -32768;
11970 targetm
.max_anchor_offset
= 32767;
11973 /* (Re)initialize MIPS target internals for new ISA. */
11974 mips_init_relocs ();
11976 if (was_mips16_p
>= 0)
11977 /* Reinitialize target-dependent state. */
11980 was_mips16_p
= mips16_p
;
11983 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
11984 function should use the MIPS16 ISA and switch modes accordingly. */
11987 mips_set_current_function (tree fndecl
)
11989 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
11992 /* Allocate a chunk of memory for per-function machine-dependent data. */
11994 static struct machine_function
*
11995 mips_init_machine_status (void)
11997 return ((struct machine_function
*)
11998 ggc_alloc_cleared (sizeof (struct machine_function
)));
12001 /* Return the processor associated with the given ISA level, or null
12002 if the ISA isn't valid. */
12004 static const struct mips_cpu_info
*
12005 mips_cpu_info_from_isa (int isa
)
12009 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
12010 if (mips_cpu_info_table
[i
].isa
== isa
)
12011 return mips_cpu_info_table
+ i
;
12016 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
12017 with a final "000" replaced by "k". Ignore case.
12019 Note: this function is shared between GCC and GAS. */
12022 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
12024 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
12025 given
++, canonical
++;
12027 return ((*given
== 0 && *canonical
== 0)
12028 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
12031 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
12032 CPU name. We've traditionally allowed a lot of variation here.
12034 Note: this function is shared between GCC and GAS. */
12037 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
12039 /* First see if the name matches exactly, or with a final "000"
12040 turned into "k". */
12041 if (mips_strict_matching_cpu_name_p (canonical
, given
))
12044 /* If not, try comparing based on numerical designation alone.
12045 See if GIVEN is an unadorned number, or 'r' followed by a number. */
12046 if (TOLOWER (*given
) == 'r')
12048 if (!ISDIGIT (*given
))
12051 /* Skip over some well-known prefixes in the canonical name,
12052 hoping to find a number there too. */
12053 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
12055 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
12057 else if (TOLOWER (canonical
[0]) == 'r')
12060 return mips_strict_matching_cpu_name_p (canonical
, given
);
12063 /* Return the mips_cpu_info entry for the processor or ISA given
12064 by CPU_STRING. Return null if the string isn't recognized.
12066 A similar function exists in GAS. */
12068 static const struct mips_cpu_info
*
12069 mips_parse_cpu (const char *cpu_string
)
12074 /* In the past, we allowed upper-case CPU names, but it doesn't
12075 work well with the multilib machinery. */
12076 for (s
= cpu_string
; *s
!= 0; s
++)
12079 warning (0, "CPU names must be lower case");
12083 /* 'from-abi' selects the most compatible architecture for the given
12084 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
12085 EABIs, we have to decide whether we're using the 32-bit or 64-bit
12087 if (strcasecmp (cpu_string
, "from-abi") == 0)
12088 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
12089 : ABI_NEEDS_64BIT_REGS
? 3
12090 : (TARGET_64BIT
? 3 : 1));
12092 /* 'default' has traditionally been a no-op. Probably not very useful. */
12093 if (strcasecmp (cpu_string
, "default") == 0)
12096 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
12097 if (mips_matching_cpu_name_p (mips_cpu_info_table
[i
].name
, cpu_string
))
12098 return mips_cpu_info_table
+ i
;
12103 /* Set up globals to generate code for the ISA or processor
12104 described by INFO. */
12107 mips_set_architecture (const struct mips_cpu_info
*info
)
12111 mips_arch_info
= info
;
12112 mips_arch
= info
->cpu
;
12113 mips_isa
= info
->isa
;
12117 /* Likewise for tuning. */
12120 mips_set_tune (const struct mips_cpu_info
*info
)
12124 mips_tune_info
= info
;
12125 mips_tune
= info
->cpu
;
12129 /* Implement TARGET_HANDLE_OPTION. */
12132 mips_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
12137 if (strcmp (arg
, "32") == 0)
12139 else if (strcmp (arg
, "o64") == 0)
12140 mips_abi
= ABI_O64
;
12141 else if (strcmp (arg
, "n32") == 0)
12142 mips_abi
= ABI_N32
;
12143 else if (strcmp (arg
, "64") == 0)
12145 else if (strcmp (arg
, "eabi") == 0)
12146 mips_abi
= ABI_EABI
;
12153 return mips_parse_cpu (arg
) != 0;
12156 mips_isa_option_info
= mips_parse_cpu (ACONCAT (("mips", arg
, NULL
)));
12157 return mips_isa_option_info
!= 0;
12159 case OPT_mno_flush_func
:
12160 mips_cache_flush_func
= NULL
;
12163 case OPT_mcode_readable_
:
12164 if (strcmp (arg
, "yes") == 0)
12165 mips_code_readable
= CODE_READABLE_YES
;
12166 else if (strcmp (arg
, "pcrel") == 0)
12167 mips_code_readable
= CODE_READABLE_PCREL
;
12168 else if (strcmp (arg
, "no") == 0)
12169 mips_code_readable
= CODE_READABLE_NO
;
12179 /* Implement OVERRIDE_OPTIONS. */
12182 mips_override_options (void)
12184 int i
, start
, regno
, mode
;
12186 #ifdef SUBTARGET_OVERRIDE_OPTIONS
12187 SUBTARGET_OVERRIDE_OPTIONS
;
12190 /* Set the small data limit. */
12191 mips_small_data_threshold
= (g_switch_set
12193 : MIPS_DEFAULT_GVALUE
);
12195 /* The following code determines the architecture and register size.
12196 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
12197 The GAS and GCC code should be kept in sync as much as possible. */
12199 if (mips_arch_string
!= 0)
12200 mips_set_architecture (mips_parse_cpu (mips_arch_string
));
12202 if (mips_isa_option_info
!= 0)
12204 if (mips_arch_info
== 0)
12205 mips_set_architecture (mips_isa_option_info
);
12206 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
12207 error ("%<-%s%> conflicts with the other architecture options, "
12208 "which specify a %s processor",
12209 mips_isa_option_info
->name
,
12210 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
12213 if (mips_arch_info
== 0)
12215 #ifdef MIPS_CPU_STRING_DEFAULT
12216 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT
));
12218 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
12222 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
12223 error ("%<-march=%s%> is not compatible with the selected ABI",
12224 mips_arch_info
->name
);
12226 /* Optimize for mips_arch, unless -mtune selects a different processor. */
12227 if (mips_tune_string
!= 0)
12228 mips_set_tune (mips_parse_cpu (mips_tune_string
));
12230 if (mips_tune_info
== 0)
12231 mips_set_tune (mips_arch_info
);
12233 if ((target_flags_explicit
& MASK_64BIT
) != 0)
12235 /* The user specified the size of the integer registers. Make sure
12236 it agrees with the ABI and ISA. */
12237 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
12238 error ("%<-mgp64%> used with a 32-bit processor");
12239 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
12240 error ("%<-mgp32%> used with a 64-bit ABI");
12241 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
12242 error ("%<-mgp64%> used with a 32-bit ABI");
12246 /* Infer the integer register size from the ABI and processor.
12247 Restrict ourselves to 32-bit registers if that's all the
12248 processor has, or if the ABI cannot handle 64-bit registers. */
12249 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
12250 target_flags
&= ~MASK_64BIT
;
12252 target_flags
|= MASK_64BIT
;
12255 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
12257 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
12258 error ("unsupported combination: %s", "-mfp64 -msingle-float");
12259 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
12260 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
12261 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
12263 if (!ISA_HAS_MXHC1
)
12264 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
12265 " the target supports the mfhc1 and mthc1 instructions");
12266 else if (mips_abi
!= ABI_32
)
12267 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
12273 /* -msingle-float selects 32-bit float registers. Otherwise the
12274 float registers should be the same size as the integer ones. */
12275 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
12276 target_flags
|= MASK_FLOAT64
;
12278 target_flags
&= ~MASK_FLOAT64
;
12281 /* End of code shared with GAS. */
12283 /* If no -mlong* option was given, infer it from the other options. */
12284 if ((target_flags_explicit
& MASK_LONG64
) == 0)
12286 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
12287 target_flags
|= MASK_LONG64
;
12289 target_flags
&= ~MASK_LONG64
;
12292 if (!TARGET_OLDABI
)
12293 flag_pcc_struct_return
= 0;
12295 /* Decide which rtx_costs structure to use. */
12297 mips_cost
= &mips_rtx_cost_optimize_size
;
12299 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
12301 /* If the user hasn't specified a branch cost, use the processor's
12303 if (mips_branch_cost
== 0)
12304 mips_branch_cost
= mips_cost
->branch_cost
;
12306 /* If neither -mbranch-likely nor -mno-branch-likely was given
12307 on the command line, set MASK_BRANCHLIKELY based on the target
12308 architecture and tuning flags. Annulled delay slots are a
12309 size win, so we only consider the processor-specific tuning
12310 for !optimize_size. */
12311 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
12313 if (ISA_HAS_BRANCHLIKELY
12315 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
12316 target_flags
|= MASK_BRANCHLIKELY
;
12318 target_flags
&= ~MASK_BRANCHLIKELY
;
12320 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
12321 warning (0, "the %qs architecture does not support branch-likely"
12322 " instructions", mips_arch_info
->name
);
12324 /* The effect of -mabicalls isn't defined for the EABI. */
12325 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
12327 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
12328 target_flags
&= ~MASK_ABICALLS
;
12331 /* MIPS16 cannot generate PIC yet. */
12332 if (TARGET_MIPS16
&& (flag_pic
|| TARGET_ABICALLS
))
12334 sorry ("MIPS16 PIC");
12335 target_flags
&= ~MASK_ABICALLS
;
12336 flag_pic
= flag_pie
= flag_shlib
= 0;
12339 if (TARGET_ABICALLS
)
12340 /* We need to set flag_pic for executables as well as DSOs
12341 because we may reference symbols that are not defined in
12342 the final executable. (MIPS does not use things like
12343 copy relocs, for example.)
12345 Also, there is a body of code that uses __PIC__ to distinguish
12346 between -mabicalls and -mno-abicalls code. */
12349 /* -mvr4130-align is a "speed over size" optimization: it usually produces
12350 faster code, but at the expense of more nops. Enable it at -O3 and
12352 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
12353 target_flags
|= MASK_VR4130_ALIGN
;
12355 /* Prefer a call to memcpy over inline code when optimizing for size,
12356 though see MOVE_RATIO in mips.h. */
12357 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
12358 target_flags
|= MASK_MEMCPY
;
12360 /* If we have a nonzero small-data limit, check that the -mgpopt
12361 setting is consistent with the other target flags. */
12362 if (mips_small_data_threshold
> 0)
12366 if (!TARGET_MIPS16
&& !TARGET_EXPLICIT_RELOCS
)
12367 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
12369 TARGET_LOCAL_SDATA
= false;
12370 TARGET_EXTERN_SDATA
= false;
12374 if (TARGET_VXWORKS_RTP
)
12375 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
12377 if (TARGET_ABICALLS
)
12378 warning (0, "cannot use small-data accesses for %qs",
12383 #ifdef MIPS_TFMODE_FORMAT
12384 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
12387 /* Make sure that the user didn't turn off paired single support when
12388 MIPS-3D support is requested. */
12390 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
12391 && !TARGET_PAIRED_SINGLE_FLOAT
)
12392 error ("%<-mips3d%> requires %<-mpaired-single%>");
12394 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
12396 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
12398 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
12399 and TARGET_HARD_FLOAT_ABI are both true. */
12400 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
12401 error ("%qs must be used with %qs",
12402 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
12403 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
12405 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
12407 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
12408 warning (0, "the %qs architecture does not support paired-single"
12409 " instructions", mips_arch_info
->name
);
12411 /* If TARGET_DSPR2, enable MASK_DSP. */
12413 target_flags
|= MASK_DSP
;
12415 mips_init_print_operand_punct ();
12417 /* Set up array to map GCC register number to debug register number.
12418 Ignore the special purpose register numbers. */
12420 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12422 mips_dbx_regno
[i
] = INVALID_REGNUM
;
12423 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
12424 mips_dwarf_regno
[i
] = i
;
12426 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
12429 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
12430 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
12431 mips_dbx_regno
[i
] = i
+ start
;
12433 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
12434 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
12435 mips_dbx_regno
[i
] = i
+ start
;
12437 /* Accumulator debug registers use big-endian ordering. */
12438 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
12439 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
12440 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
12441 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
12442 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
12444 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
12445 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
12448 /* Set up mips_hard_regno_mode_ok. */
12449 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
12450 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12451 mips_hard_regno_mode_ok
[(int)mode
][regno
]
12452 = mips_hard_regno_mode_ok_p (regno
, mode
);
12454 /* Function to allocate machine-dependent function status. */
12455 init_machine_status
= &mips_init_machine_status
;
12457 /* Default to working around R4000 errata only if the processor
12458 was selected explicitly. */
12459 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
12460 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
12461 target_flags
|= MASK_FIX_R4000
;
12463 /* Default to working around R4400 errata only if the processor
12464 was selected explicitly. */
12465 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
12466 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
12467 target_flags
|= MASK_FIX_R4400
;
12469 /* Save base state of options. */
12470 mips_base_mips16
= TARGET_MIPS16
;
12471 mips_base_target_flags
= target_flags
;
12472 mips_base_delayed_branch
= flag_delayed_branch
;
12473 mips_base_schedule_insns
= flag_schedule_insns
;
12474 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
12475 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
12476 mips_base_align_loops
= align_loops
;
12477 mips_base_align_jumps
= align_jumps
;
12478 mips_base_align_functions
= align_functions
;
12480 /* Now select the ISA mode. */
12481 mips_set_mips16_mode (mips_base_mips16
);
12483 /* We call dbr_schedule from within mips_reorg. */
12484 flag_delayed_branch
= 0;
12487 /* Swap the register information for registers I and I + 1, which
12488 currently have the wrong endianness. Note that the registers'
12489 fixedness and call-clobberedness might have been set on the
12493 mips_swap_registers (unsigned int i
)
12498 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12499 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12501 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
12502 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
12503 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
12504 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
12510 /* Implement CONDITIONAL_REGISTER_USAGE. */
12513 mips_conditional_register_usage (void)
12519 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
12520 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12522 if (!TARGET_HARD_FLOAT
)
12526 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
12527 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12528 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
12529 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12531 else if (! ISA_HAS_8CC
)
12535 /* We only have a single condition-code register. We implement
12536 this by fixing all the condition-code registers and generating
12537 RTL that refers directly to ST_REG_FIRST. */
12538 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
12539 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
12541 /* In MIPS16 mode, we permit the $t temporary registers to be used
12542 for reload. We prohibit the unused $s registers, since they
12543 are call-saved, and saving them via a MIPS16 register would
12544 probably waste more time than just reloading the value. */
12547 fixed_regs
[18] = call_used_regs
[18] = 1;
12548 fixed_regs
[19] = call_used_regs
[19] = 1;
12549 fixed_regs
[20] = call_used_regs
[20] = 1;
12550 fixed_regs
[21] = call_used_regs
[21] = 1;
12551 fixed_regs
[22] = call_used_regs
[22] = 1;
12552 fixed_regs
[23] = call_used_regs
[23] = 1;
12553 fixed_regs
[26] = call_used_regs
[26] = 1;
12554 fixed_regs
[27] = call_used_regs
[27] = 1;
12555 fixed_regs
[30] = call_used_regs
[30] = 1;
12557 /* $f20-$f23 are call-clobbered for n64. */
12558 if (mips_abi
== ABI_64
)
12561 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
12562 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
12564 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
12566 if (mips_abi
== ABI_N32
)
12569 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
12570 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
12572 /* Make sure that double-register accumulator values are correctly
12573 ordered for the current endianness. */
12574 if (TARGET_LITTLE_ENDIAN
)
12576 unsigned int regno
;
12578 mips_swap_registers (MD_REG_FIRST
);
12579 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
12580 mips_swap_registers (regno
);
12584 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
12585 other registers for instructions for which it is possible. This
12586 encourages the compiler to use CMP in cases where an XOR would
12587 require some register shuffling. */
12590 mips_order_regs_for_local_alloc (void)
12594 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
12595 reg_alloc_order
[i
] = i
;
12599 /* It really doesn't matter where we put register 0, since it is
12600 a fixed register anyhow. */
12601 reg_alloc_order
[0] = 24;
12602 reg_alloc_order
[24] = 0;
12606 /* Initialize the GCC target structure. */
12607 #undef TARGET_ASM_ALIGNED_HI_OP
12608 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
12609 #undef TARGET_ASM_ALIGNED_SI_OP
12610 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
12611 #undef TARGET_ASM_ALIGNED_DI_OP
12612 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
12614 #undef TARGET_ASM_FUNCTION_PROLOGUE
12615 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
12616 #undef TARGET_ASM_FUNCTION_EPILOGUE
12617 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
12618 #undef TARGET_ASM_SELECT_RTX_SECTION
12619 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
12620 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
12621 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
12623 #undef TARGET_SCHED_INIT
12624 #define TARGET_SCHED_INIT mips_sched_init
12625 #undef TARGET_SCHED_REORDER
12626 #define TARGET_SCHED_REORDER mips_sched_reorder
12627 #undef TARGET_SCHED_REORDER2
12628 #define TARGET_SCHED_REORDER2 mips_sched_reorder
12629 #undef TARGET_SCHED_VARIABLE_ISSUE
12630 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
12631 #undef TARGET_SCHED_ADJUST_COST
12632 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
12633 #undef TARGET_SCHED_ISSUE_RATE
12634 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
12635 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12636 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12637 mips_multipass_dfa_lookahead
12639 #undef TARGET_DEFAULT_TARGET_FLAGS
12640 #define TARGET_DEFAULT_TARGET_FLAGS \
12642 | TARGET_CPU_DEFAULT \
12643 | TARGET_ENDIAN_DEFAULT \
12644 | TARGET_FP_EXCEPTIONS_DEFAULT \
12645 | MASK_CHECK_ZERO_DIV \
12647 #undef TARGET_HANDLE_OPTION
12648 #define TARGET_HANDLE_OPTION mips_handle_option
12650 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12651 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
12653 #undef TARGET_INSERT_ATTRIBUTES
12654 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
12655 #undef TARGET_MERGE_DECL_ATTRIBUTES
12656 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
12657 #undef TARGET_SET_CURRENT_FUNCTION
12658 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
12660 #undef TARGET_VALID_POINTER_MODE
12661 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
12662 #undef TARGET_RTX_COSTS
12663 #define TARGET_RTX_COSTS mips_rtx_costs
12664 #undef TARGET_ADDRESS_COST
12665 #define TARGET_ADDRESS_COST mips_address_cost
12667 #undef TARGET_IN_SMALL_DATA_P
12668 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
12670 #undef TARGET_MACHINE_DEPENDENT_REORG
12671 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
12673 #undef TARGET_ASM_FILE_START
12674 #define TARGET_ASM_FILE_START mips_file_start
12675 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
12676 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
12678 #undef TARGET_INIT_LIBFUNCS
12679 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
12681 #undef TARGET_BUILD_BUILTIN_VA_LIST
12682 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
12683 #undef TARGET_EXPAND_BUILTIN_VA_START
12684 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
12685 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12686 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
12688 #undef TARGET_PROMOTE_FUNCTION_ARGS
12689 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
12690 #undef TARGET_PROMOTE_FUNCTION_RETURN
12691 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
12692 #undef TARGET_PROMOTE_PROTOTYPES
12693 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
12695 #undef TARGET_RETURN_IN_MEMORY
12696 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
12697 #undef TARGET_RETURN_IN_MSB
12698 #define TARGET_RETURN_IN_MSB mips_return_in_msb
12700 #undef TARGET_ASM_OUTPUT_MI_THUNK
12701 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
12702 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12703 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12705 #undef TARGET_SETUP_INCOMING_VARARGS
12706 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
12707 #undef TARGET_STRICT_ARGUMENT_NAMING
12708 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
12709 #undef TARGET_MUST_PASS_IN_STACK
12710 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12711 #undef TARGET_PASS_BY_REFERENCE
12712 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
12713 #undef TARGET_CALLEE_COPIES
12714 #define TARGET_CALLEE_COPIES mips_callee_copies
12715 #undef TARGET_ARG_PARTIAL_BYTES
12716 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
12718 #undef TARGET_MODE_REP_EXTENDED
12719 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
12721 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12722 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
12724 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12725 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
12727 #undef TARGET_INIT_BUILTINS
12728 #define TARGET_INIT_BUILTINS mips_init_builtins
12729 #undef TARGET_EXPAND_BUILTIN
12730 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
12732 #undef TARGET_HAVE_TLS
12733 #define TARGET_HAVE_TLS HAVE_AS_TLS
12735 #undef TARGET_CANNOT_FORCE_CONST_MEM
12736 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
12738 #undef TARGET_ENCODE_SECTION_INFO
12739 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
12741 #undef TARGET_ATTRIBUTE_TABLE
12742 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
12743 /* All our function attributes are related to how out-of-line copies should
12744 be compiled or called. They don't in themselves prevent inlining. */
12745 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
12746 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
12748 #undef TARGET_EXTRA_LIVE_ON_ENTRY
12749 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
12751 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12752 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
12753 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
12754 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
12756 #undef TARGET_COMP_TYPE_ATTRIBUTES
12757 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
12759 #ifdef HAVE_AS_DTPRELWORD
12760 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12761 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
12763 #undef TARGET_DWARF_REGISTER_SPAN
12764 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
12766 struct gcc_target targetm
= TARGET_INITIALIZER
;
12768 #include "gt-mips.h"