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builtins.c (get_memory_rtx): Fix comment.
[thirdparty/gcc.git] / gcc / config / mips / mips.h
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY_SPEED
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target when optimizing code for speed, typically because
50 the branches are always predicted taken and so incur a large overhead
51 when not taken.
52
53 PTF_AVOID_BRANCHLIKELY_SIZE
54 As above but when optimizing for size.
55
56 PTF_AVOID_BRANCHLIKELY_ALWAYS
57 As above but regardless of whether we optimize for speed or size.
58
59 PTF_AVOID_IMADD
60 Set if it is usually not profitable to use the integer MADD or MSUB
61 instructions because of the overhead of getting the result out of
62 the HI/LO registers. */
63
64 #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1
65 #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2
66 #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \
67 PTF_AVOID_BRANCHLIKELY_SIZE)
68 #define PTF_AVOID_IMADD 0x4
69
70 /* Information about one recognized processor. Defined here for the
71 benefit of TARGET_CPU_CPP_BUILTINS. */
72 struct mips_cpu_info {
73 /* The 'canonical' name of the processor as far as GCC is concerned.
74 It's typically a manufacturer's prefix followed by a numerical
75 designation. It should be lowercase. */
76 const char *name;
77
78 /* The internal processor number that most closely matches this
79 entry. Several processors can have the same value, if there's no
80 difference between them from GCC's point of view. */
81 enum processor cpu;
82
83 /* The ISA level that the processor implements. */
84 int isa;
85
86 /* A mask of PTF_* values. */
87 unsigned int tune_flags;
88 };
89
90 #include "config/mips/mips-opts.h"
91
92 /* Macros to silence warnings about numbers being signed in traditional
93 C and unsigned in ISO C when compiled on 32-bit hosts. */
94
95 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
96 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
97 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
98
99 \f
100 /* Run-time compilation parameters selecting different hardware subsets. */
101
102 /* True if we are generating position-independent VxWorks RTP code. */
103 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
104
105 /* Compact branches must not be used if the user either selects the
106 'never' policy or the 'optimal' policy on a core that lacks
107 compact branch instructions. */
108 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \
109 || (mips_cb == MIPS_CB_OPTIMAL \
110 && !ISA_HAS_COMPACT_BRANCHES))
111
112 /* Compact branches may be used if the user either selects the
113 'always' policy or the 'optimal' policy on a core that supports
114 compact branch instructions. */
115 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \
116 || (mips_cb == MIPS_CB_OPTIMAL \
117 && ISA_HAS_COMPACT_BRANCHES))
118
119 /* Compact branches must always be generated if the user selects
120 the 'always' policy or the 'optimal' policy om a core that
121 lacks delay slot branch instructions. */
122 #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \
123 || (mips_cb == MIPS_CB_OPTIMAL \
124 && !ISA_HAS_DELAY_SLOTS))
125
126 /* Special handling for JRC that exists in microMIPSR3 as well as R6
127 ISAs with full compact branch support. */
128 #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \
129 || TARGET_MICROMIPS) \
130 && mips_cb != MIPS_CB_NEVER)
131
132 /* True if the output file is marked as ".abicalls; .option pic0"
133 (-call_nonpic). */
134 #define TARGET_ABICALLS_PIC0 \
135 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
136
137 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
138 #define TARGET_ABICALLS_PIC2 \
139 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
140
141 /* True if the call patterns should be split into a jalr followed by
142 an instruction to restore $gp. It is only safe to split the load
143 from the call when every use of $gp is explicit.
144
145 See mips_must_initialize_gp_p for details about how we manage the
146 global pointer. */
147
148 #define TARGET_SPLIT_CALLS \
149 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
150
151 /* True if we're generating a form of -mabicalls in which we can use
152 operators like %hi and %lo to refer to locally-binding symbols.
153 We can only do this for -mno-shared, and only then if we can use
154 relocation operations instead of assembly macros. It isn't really
155 worth using absolute sequences for 64-bit symbols because GOT
156 accesses are so much shorter. */
157
158 #define TARGET_ABSOLUTE_ABICALLS \
159 (TARGET_ABICALLS \
160 && !TARGET_SHARED \
161 && TARGET_EXPLICIT_RELOCS \
162 && !ABI_HAS_64BIT_SYMBOLS)
163
164 /* True if we can optimize sibling calls. For simplicity, we only
165 handle cases in which call_insn_operand will reject invalid
166 sibcall addresses. There are two cases in which this isn't true:
167
168 - TARGET_MIPS16. call_insn_operand accepts constant addresses
169 but there is no direct jump instruction. It isn't worth
170 using sibling calls in this case anyway; they would usually
171 be longer than normal calls.
172
173 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
174 accepts global constants, but all sibcalls must be indirect. */
175 #define TARGET_SIBCALLS \
176 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
177
178 /* True if we need to use a global offset table to access some symbols. */
179 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
180
181 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
182 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
183
184 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
185 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
186
187 /* True if we should use .cprestore to store to the cprestore slot.
188
189 We continue to use .cprestore for explicit-reloc code so that JALs
190 inside inline asms will work correctly. */
191 #define TARGET_CPRESTORE_DIRECTIVE \
192 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
193
194 /* True if we can use the J and JAL instructions. */
195 #define TARGET_ABSOLUTE_JUMPS \
196 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
197
198 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
199 This is true for both the PIC and non-PIC VxWorks RTP modes. */
200 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
201
202 /* True if .gpword or .gpdword should be used for switch tables. */
203 #define TARGET_GPWORD \
204 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
205
206 /* True if the output must have a writable .eh_frame.
207 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
208 #ifdef HAVE_LD_PERSONALITY_RELAXATION
209 #define TARGET_WRITABLE_EH_FRAME 0
210 #else
211 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
212 #endif
213
214 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
215 #ifdef HAVE_AS_DSPR1_MULT
216 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
217 #else
218 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
219 #endif
220
221 /* ISA has LSA available. */
222 #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA)
223
224 /* ISA has DLSA available. */
225 #define ISA_HAS_DLSA (TARGET_64BIT \
226 && (mips_isa_rev >= 6 \
227 || ISA_HAS_MSA))
228
229 /* The ISA compression flags that are currently in effect. */
230 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
231
232 /* Generate mips16 code */
233 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
234 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
235 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
236 /* Generate mips16e register save/restore sequences. */
237 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
238
239 /* True if we're generating a form of MIPS16 code in which general
240 text loads are allowed. */
241 #define TARGET_MIPS16_TEXT_LOADS \
242 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
243
244 /* True if we're generating a form of MIPS16 code in which PC-relative
245 loads are allowed. */
246 #define TARGET_MIPS16_PCREL_LOADS \
247 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
248
249 /* Generic ISA defines. */
250 #define ISA_MIPS1 (mips_isa == 1)
251 #define ISA_MIPS2 (mips_isa == 2)
252 #define ISA_MIPS3 (mips_isa == 3)
253 #define ISA_MIPS4 (mips_isa == 4)
254 #define ISA_MIPS32 (mips_isa == 32)
255 #define ISA_MIPS32R2 (mips_isa == 33)
256 #define ISA_MIPS32R3 (mips_isa == 34)
257 #define ISA_MIPS32R5 (mips_isa == 36)
258 #define ISA_MIPS32R6 (mips_isa == 37)
259 #define ISA_MIPS64 (mips_isa == 64)
260 #define ISA_MIPS64R2 (mips_isa == 65)
261 #define ISA_MIPS64R3 (mips_isa == 66)
262 #define ISA_MIPS64R5 (mips_isa == 68)
263 #define ISA_MIPS64R6 (mips_isa == 69)
264
265 /* Architecture target defines. */
266 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
267 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
268 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
269 #define TARGET_GS464 (mips_arch == PROCESSOR_GS464)
270 #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E)
271 #define TARGET_GS264E (mips_arch == PROCESSOR_GS264E)
272 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
273 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
274 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
275 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
276 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
277 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
278 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
279 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
280 #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000)
281 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
282 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
283 || mips_arch == PROCESSOR_OCTEON2 \
284 || mips_arch == PROCESSOR_OCTEON3)
285 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
286 || mips_arch == PROCESSOR_OCTEON3)
287 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
288 || mips_arch == PROCESSOR_SB1A)
289 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
290 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
291
292 /* Scheduling target defines. */
293 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
294 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
295 || mips_tune == PROCESSOR_24KF2_1 \
296 || mips_tune == PROCESSOR_24KF1_1)
297 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
298 || mips_tune == PROCESSOR_74KF2_1 \
299 || mips_tune == PROCESSOR_74KF1_1 \
300 || mips_tune == PROCESSOR_74KF3_2)
301 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
302 || mips_tune == PROCESSOR_LOONGSON_2F)
303 #define TUNE_GS464 (mips_tune == PROCESSOR_GS464)
304 #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E)
305 #define TUNE_GS264E (mips_tune == PROCESSOR_GS264E)
306 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
307 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
308 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
309 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
310 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
311 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
312 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
313 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
314 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
315 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
316 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
317 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
318 || mips_tune == PROCESSOR_OCTEON2 \
319 || mips_tune == PROCESSOR_OCTEON3)
320 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
321 || mips_tune == PROCESSOR_SB1A)
322 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
323 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
324 #define TUNE_P6600 (mips_tune == PROCESSOR_P6600)
325
326 /* True if the pre-reload scheduler should try to create chains of
327 multiply-add or multiply-subtract instructions. For example,
328 suppose we have:
329
330 t1 = a * b
331 t2 = t1 + c * d
332 t3 = e * f
333 t4 = t3 - g * h
334
335 t1 will have a higher priority than t2 and t3 will have a higher
336 priority than t4. However, before reload, there is no dependence
337 between t1 and t3, and they can often have similar priorities.
338 The scheduler will then tend to prefer:
339
340 t1 = a * b
341 t3 = e * f
342 t2 = t1 + c * d
343 t4 = t3 - g * h
344
345 which stops us from making full use of macc/madd-style instructions.
346 This sort of situation occurs frequently in Fourier transforms and
347 in unrolled loops.
348
349 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
350 queue so that chained multiply-add and multiply-subtract instructions
351 appear ahead of any other instruction that is likely to clobber lo.
352 In the example above, if t2 and t3 become ready at the same time,
353 the code ensures that t2 is scheduled first.
354
355 Multiply-accumulate instructions are a bigger win for some targets
356 than others, so this macro is defined on an opt-in basis. */
357 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
358 || TUNE_MIPS4120 \
359 || TUNE_MIPS4130 \
360 || TUNE_24K \
361 || TUNE_P5600)
362
363 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
364 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
365
366 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
367 directly accessible, while the command-line options select
368 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
369 in use. */
370 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
371 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
372
373 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
374 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
375 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
376
377 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
378 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
379 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
380 && !TARGET_ODD_SPREG)
381
382 /* False if SC acts as a memory barrier with respect to itself,
383 otherwise a SYNC will be emitted after SC for atomic operations
384 that require ordering between the SC and following loads and
385 stores. It does not tell anything about ordering of loads and
386 stores prior to and following the SC, only about the SC itself and
387 those loads and stores follow it. */
388 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
389
390 /* Define preprocessor macros for the -march and -mtune options.
391 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
392 processor. If INFO's canonical name is "foo", define PREFIX to
393 be "foo", and define an additional macro PREFIX_FOO. */
394 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
395 do \
396 { \
397 char *macro, *p; \
398 \
399 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
400 for (p = macro; *p != 0; p++) \
401 if (*p == '+') \
402 *p = 'P'; \
403 else \
404 *p = TOUPPER (*p); \
405 \
406 builtin_define (macro); \
407 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
408 free (macro); \
409 } \
410 while (0)
411
412 /* Target CPU builtins. */
413 #define TARGET_CPU_CPP_BUILTINS() \
414 do \
415 { \
416 builtin_assert ("machine=mips"); \
417 builtin_assert ("cpu=mips"); \
418 builtin_define ("__mips__"); \
419 builtin_define ("_mips"); \
420 \
421 /* We do this here because __mips is defined below and so we \
422 can't use builtin_define_std. We don't ever want to define \
423 "mips" for VxWorks because some of the VxWorks headers \
424 construct include filenames from a root directory macro, \
425 an architecture macro and a filename, where the architecture \
426 macro expands to 'mips'. If we define 'mips' to 1, the \
427 architecture macro expands to 1 as well. */ \
428 if (!flag_iso && !TARGET_VXWORKS) \
429 builtin_define ("mips"); \
430 \
431 if (TARGET_64BIT) \
432 builtin_define ("__mips64"); \
433 \
434 /* Treat _R3000 and _R4000 like register-size \
435 defines, which is how they've historically \
436 been used. */ \
437 if (TARGET_64BIT) \
438 { \
439 builtin_define_std ("R4000"); \
440 builtin_define ("_R4000"); \
441 } \
442 else \
443 { \
444 builtin_define_std ("R3000"); \
445 builtin_define ("_R3000"); \
446 } \
447 \
448 if (TARGET_FLOAT64) \
449 builtin_define ("__mips_fpr=64"); \
450 else if (TARGET_FLOATXX) \
451 builtin_define ("__mips_fpr=0"); \
452 else \
453 builtin_define ("__mips_fpr=32"); \
454 \
455 if (mips_base_compression_flags & MASK_MIPS16) \
456 builtin_define ("__mips16"); \
457 \
458 if (TARGET_MIPS3D) \
459 builtin_define ("__mips3d"); \
460 \
461 if (TARGET_SMARTMIPS) \
462 builtin_define ("__mips_smartmips"); \
463 \
464 if (mips_base_compression_flags & MASK_MICROMIPS) \
465 builtin_define ("__mips_micromips"); \
466 \
467 if (TARGET_MCU) \
468 builtin_define ("__mips_mcu"); \
469 \
470 if (TARGET_EVA) \
471 builtin_define ("__mips_eva"); \
472 \
473 if (TARGET_DSP) \
474 { \
475 builtin_define ("__mips_dsp"); \
476 if (TARGET_DSPR2) \
477 { \
478 builtin_define ("__mips_dspr2"); \
479 builtin_define ("__mips_dsp_rev=2"); \
480 } \
481 else \
482 builtin_define ("__mips_dsp_rev=1"); \
483 } \
484 \
485 if (ISA_HAS_MSA) \
486 { \
487 builtin_define ("__mips_msa"); \
488 builtin_define ("__mips_msa_width=128"); \
489 } \
490 \
491 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
492 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
493 \
494 if (ISA_MIPS1) \
495 { \
496 builtin_define ("__mips=1"); \
497 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
498 } \
499 else if (ISA_MIPS2) \
500 { \
501 builtin_define ("__mips=2"); \
502 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
503 } \
504 else if (ISA_MIPS3) \
505 { \
506 builtin_define ("__mips=3"); \
507 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
508 } \
509 else if (ISA_MIPS4) \
510 { \
511 builtin_define ("__mips=4"); \
512 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
513 } \
514 else if (mips_isa >= 32 && mips_isa < 64) \
515 { \
516 builtin_define ("__mips=32"); \
517 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
518 } \
519 else if (mips_isa >= 64) \
520 { \
521 builtin_define ("__mips=64"); \
522 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
523 } \
524 if (mips_isa_rev > 0) \
525 builtin_define_with_int_value ("__mips_isa_rev", \
526 mips_isa_rev); \
527 \
528 switch (mips_abi) \
529 { \
530 case ABI_32: \
531 builtin_define ("_ABIO32=1"); \
532 builtin_define ("_MIPS_SIM=_ABIO32"); \
533 break; \
534 \
535 case ABI_N32: \
536 builtin_define ("_ABIN32=2"); \
537 builtin_define ("_MIPS_SIM=_ABIN32"); \
538 break; \
539 \
540 case ABI_64: \
541 builtin_define ("_ABI64=3"); \
542 builtin_define ("_MIPS_SIM=_ABI64"); \
543 break; \
544 \
545 case ABI_O64: \
546 builtin_define ("_ABIO64=4"); \
547 builtin_define ("_MIPS_SIM=_ABIO64"); \
548 break; \
549 } \
550 \
551 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
552 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
553 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
554 builtin_define_with_int_value ("_MIPS_FPSET", \
555 32 / MAX_FPRS_PER_FMT); \
556 builtin_define_with_int_value ("_MIPS_SPFPSET", \
557 TARGET_ODD_SPREG ? 32 : 16); \
558 \
559 /* These defines reflect the ABI in use, not whether the \
560 FPU is directly accessible. */ \
561 if (TARGET_NO_FLOAT) \
562 builtin_define ("__mips_no_float"); \
563 else if (TARGET_HARD_FLOAT_ABI) \
564 builtin_define ("__mips_hard_float"); \
565 else \
566 builtin_define ("__mips_soft_float"); \
567 \
568 if (TARGET_SINGLE_FLOAT) \
569 builtin_define ("__mips_single_float"); \
570 \
571 if (TARGET_PAIRED_SINGLE_FLOAT) \
572 builtin_define ("__mips_paired_single_float"); \
573 \
574 if (mips_abs == MIPS_IEEE_754_2008) \
575 builtin_define ("__mips_abs2008"); \
576 \
577 if (mips_nan == MIPS_IEEE_754_2008) \
578 builtin_define ("__mips_nan2008"); \
579 \
580 if (TARGET_BIG_ENDIAN) \
581 { \
582 builtin_define_std ("MIPSEB"); \
583 builtin_define ("_MIPSEB"); \
584 } \
585 else \
586 { \
587 builtin_define_std ("MIPSEL"); \
588 builtin_define ("_MIPSEL"); \
589 } \
590 \
591 /* Whether calls should go through $25. The separate __PIC__ \
592 macro indicates whether abicalls code might use a GOT. */ \
593 if (TARGET_ABICALLS) \
594 builtin_define ("__mips_abicalls"); \
595 \
596 /* Whether Loongson vector modes are enabled. */ \
597 if (TARGET_LOONGSON_MMI) \
598 { \
599 builtin_define ("__mips_loongson_vector_rev"); \
600 builtin_define ("__mips_loongson_mmi"); \
601 } \
602 \
603 /* Whether Loongson EXT modes are enabled. */ \
604 if (TARGET_LOONGSON_EXT) \
605 { \
606 builtin_define ("__mips_loongson_ext"); \
607 if (TARGET_LOONGSON_EXT2) \
608 { \
609 builtin_define ("__mips_loongson_ext2"); \
610 builtin_define ("__mips_loongson_ext_rev=2"); \
611 } \
612 else \
613 builtin_define ("__mips_loongson_ext_rev=1"); \
614 } \
615 \
616 /* Historical Octeon macro. */ \
617 if (TARGET_OCTEON) \
618 builtin_define ("__OCTEON__"); \
619 \
620 if (TARGET_SYNCI) \
621 builtin_define ("__mips_synci"); \
622 \
623 /* Macros dependent on the C dialect. */ \
624 if (preprocessing_asm_p ()) \
625 { \
626 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
627 builtin_define ("_LANGUAGE_ASSEMBLY"); \
628 } \
629 else if (c_dialect_cxx ()) \
630 { \
631 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
632 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
633 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
634 } \
635 else \
636 { \
637 builtin_define_std ("LANGUAGE_C"); \
638 builtin_define ("_LANGUAGE_C"); \
639 } \
640 if (c_dialect_objc ()) \
641 { \
642 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
643 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
644 /* Bizarre, but retained for backwards compatibility. */ \
645 builtin_define_std ("LANGUAGE_C"); \
646 builtin_define ("_LANGUAGE_C"); \
647 } \
648 \
649 if (mips_abi == ABI_EABI) \
650 builtin_define ("__mips_eabi"); \
651 \
652 if (TARGET_CACHE_BUILTIN) \
653 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
654 if (!ISA_HAS_LXC1_SXC1) \
655 builtin_define ("__mips_no_lxc1_sxc1"); \
656 if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \
657 builtin_define ("__mips_no_madd4"); \
658 } \
659 while (0)
660
661 /* Target CPU versions for D. */
662 #define TARGET_D_CPU_VERSIONS mips_d_target_versions
663
664 /* Default target_flags if no switches are specified */
665
666 #ifndef TARGET_DEFAULT
667 #define TARGET_DEFAULT 0
668 #endif
669
670 #ifndef TARGET_CPU_DEFAULT
671 #define TARGET_CPU_DEFAULT 0
672 #endif
673
674 #ifndef TARGET_ENDIAN_DEFAULT
675 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
676 #endif
677
678 #ifdef IN_LIBGCC2
679 #undef TARGET_64BIT
680 /* Make this compile time constant for libgcc2 */
681 #ifdef __mips64
682 #define TARGET_64BIT 1
683 #else
684 #define TARGET_64BIT 0
685 #endif
686 #endif /* IN_LIBGCC2 */
687
688 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
689 when compiled with hardware floating point. This is because MIPS16
690 code cannot save and restore the floating-point registers, which is
691 important if in a mixed MIPS16/non-MIPS16 environment. */
692
693 #ifdef IN_LIBGCC2
694 #if __mips_hard_float
695 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
696 #endif
697 #endif /* IN_LIBGCC2 */
698
699 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
700
701 #ifndef MULTILIB_ENDIAN_DEFAULT
702 #if TARGET_ENDIAN_DEFAULT == 0
703 #define MULTILIB_ENDIAN_DEFAULT "EL"
704 #else
705 #define MULTILIB_ENDIAN_DEFAULT "EB"
706 #endif
707 #endif
708
709 #ifndef MULTILIB_ISA_DEFAULT
710 #if MIPS_ISA_DEFAULT == 1
711 #define MULTILIB_ISA_DEFAULT "mips1"
712 #elif MIPS_ISA_DEFAULT == 2
713 #define MULTILIB_ISA_DEFAULT "mips2"
714 #elif MIPS_ISA_DEFAULT == 3
715 #define MULTILIB_ISA_DEFAULT "mips3"
716 #elif MIPS_ISA_DEFAULT == 4
717 #define MULTILIB_ISA_DEFAULT "mips4"
718 #elif MIPS_ISA_DEFAULT == 32
719 #define MULTILIB_ISA_DEFAULT "mips32"
720 #elif MIPS_ISA_DEFAULT == 33
721 #define MULTILIB_ISA_DEFAULT "mips32r2"
722 #elif MIPS_ISA_DEFAULT == 37
723 #define MULTILIB_ISA_DEFAULT "mips32r6"
724 #elif MIPS_ISA_DEFAULT == 64
725 #define MULTILIB_ISA_DEFAULT "mips64"
726 #elif MIPS_ISA_DEFAULT == 65
727 #define MULTILIB_ISA_DEFAULT "mips64r2"
728 #elif MIPS_ISA_DEFAULT == 69
729 #define MULTILIB_ISA_DEFAULT "mips64r6"
730 #else
731 #define MULTILIB_ISA_DEFAULT "mips1"
732 #endif
733 #endif
734
735 #ifndef MIPS_ABI_DEFAULT
736 #define MIPS_ABI_DEFAULT ABI_32
737 #endif
738
739 /* Use the most portable ABI flag for the ASM specs. */
740
741 #if MIPS_ABI_DEFAULT == ABI_32
742 #define MULTILIB_ABI_DEFAULT "mabi=32"
743 #elif MIPS_ABI_DEFAULT == ABI_O64
744 #define MULTILIB_ABI_DEFAULT "mabi=o64"
745 #elif MIPS_ABI_DEFAULT == ABI_N32
746 #define MULTILIB_ABI_DEFAULT "mabi=n32"
747 #elif MIPS_ABI_DEFAULT == ABI_64
748 #define MULTILIB_ABI_DEFAULT "mabi=64"
749 #elif MIPS_ABI_DEFAULT == ABI_EABI
750 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
751 #endif
752
753 #ifndef MULTILIB_DEFAULTS
754 #define MULTILIB_DEFAULTS \
755 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
756 #endif
757
758 /* We must pass -EL to the linker by default for little endian embedded
759 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
760 linker will default to using big-endian output files. The OUTPUT_FORMAT
761 line must be in the linker script, otherwise -EB/-EL will not work. */
762
763 #ifndef ENDIAN_SPEC
764 #if TARGET_ENDIAN_DEFAULT == 0
765 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
766 #else
767 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
768 #endif
769 #endif
770
771 /* A spec condition that matches all non-mips16 -mips arguments. */
772
773 #define MIPS_ISA_LEVEL_OPTION_SPEC \
774 "mips1|mips2|mips3|mips4|mips32*|mips64*"
775
776 /* A spec condition that matches all non-mips16 architecture arguments. */
777
778 #define MIPS_ARCH_OPTION_SPEC \
779 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
780
781 /* A spec that infers a -mips argument from an -march argument. */
782
783 #define MIPS_ISA_LEVEL_SPEC \
784 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
785 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
786 %{march=mips2|march=r6000:-mips2} \
787 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
788 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
789 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
790 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
791 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
792 |march=34k*|march=74k*|march=m14k*|march=1004k* \
793 |march=interaptiv: -mips32r2} \
794 %{march=mips32r3: -mips32r3} \
795 %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \
796 %{march=mips32r6: -mips32r6} \
797 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
798 |march=xlr: -mips64} \
799 %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \
800 |march=octeon|march=xlp: -mips64r2} \
801 %{march=mips64r3: -mips64r3} \
802 %{march=mips64r5: -mips64r5} \
803 %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}"
804
805 /* A spec that injects the default multilib ISA if no architecture is
806 specified. */
807
808 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
809 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
810 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
811
812 /* A spec that infers a -mhard-float or -msoft-float setting from an
813 -march argument. Note that soft-float and hard-float code are not
814 link-compatible. */
815
816 #define MIPS_ARCH_FLOAT_SPEC \
817 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
818 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
819 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
820 |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
821 march=*: -mhard-float}"
822
823 /* A spec condition that matches 32-bit options. It only works if
824 MIPS_ISA_LEVEL_SPEC has been applied. */
825
826 #define MIPS_32BIT_OPTION_SPEC \
827 "mips1|mips2|mips32*|mgp32"
828
829 /* A spec condition that matches architectures should be targeted with
830 o32 FPXX for compatibility reasons. */
831 #define MIPS_FPXX_OPTION_SPEC \
832 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
833 mips64|mips64r2|mips64r3|mips64r5"
834
835 /* Infer a -msynci setting from a -mips argument, on the assumption that
836 -msynci is desired where possible. */
837 #define MIPS_ISA_SYNCI_SPEC \
838 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
839 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
840
841 /* Infer a -mnan=2008 setting from a -mips argument. */
842 #define MIPS_ISA_NAN2008_SPEC \
843 "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \
844 %{!msoft-float:-mnan=2008}}"
845
846 #if (MIPS_ABI_DEFAULT == ABI_O64 \
847 || MIPS_ABI_DEFAULT == ABI_N32 \
848 || MIPS_ABI_DEFAULT == ABI_64)
849 #define OPT_ARCH64 "mabi=32|mgp32:;"
850 #define OPT_ARCH32 "mabi=32|mgp32"
851 #else
852 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
853 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
854 #endif
855
856 /* Support for a compile-time default CPU, et cetera. The rules are:
857 --with-arch is ignored if -march is specified or a -mips is specified
858 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
859 --with-tune is ignored if -mtune is specified; likewise
860 --with-tune-32 and --with-tune-64.
861 --with-abi is ignored if -mabi is specified.
862 --with-float is ignored if -mhard-float or -msoft-float are
863 specified.
864 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
865 specified.
866 --with-nan is ignored if -mnan is specified.
867 --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are
868 specified.
869 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
870 or -mno-odd-spreg are specified.
871 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
872 specified. */
873 #define OPTION_DEFAULT_SPECS \
874 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
875 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
876 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
877 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
878 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
879 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
880 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
881 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
882 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
883 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
884 {"fp_32", "%{" OPT_ARCH32 \
885 ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \
886 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
887 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
888 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
889 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
890 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
891 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \
892 {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
893 {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
894
895 /* A spec that infers the:
896 -mnan=2008 setting from a -mips argument,
897 -mdsp setting from a -march argument.
898 -mloongson-mmi setting from a -march argument. */
899 #define BASE_DRIVER_SELF_SPECS \
900 MIPS_ISA_NAN2008_SPEC, \
901 MIPS_ASE_DSP_SPEC, \
902 MIPS_ASE_LOONGSON_MMI_SPEC, \
903 MIPS_ASE_LOONGSON_EXT_SPEC, \
904 MIPS_ASE_MSA_SPEC
905
906
907 #define MIPS_ASE_DSP_SPEC \
908 "%{!mno-dsp: \
909 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \
910 |march=interaptiv: -mdsp} \
911 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
912
913 #define MIPS_ASE_LOONGSON_MMI_SPEC \
914 "%{!mno-loongson-mmi: \
915 %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}"
916
917 #define MIPS_ASE_LOONGSON_EXT_SPEC \
918 "%{!mno-loongson-ext: \
919 %{march=loongson3a|march=gs464: -mloongson-ext} \
920 %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \
921 -mloongson-ext2 -mloongson-ext}}}"
922
923 #define MIPS_ASE_MSA_SPEC \
924 "%{!mno-msa: \
925 %{march=gs264e: -mmsa}}"
926
927 #define DRIVER_SELF_SPECS \
928 MIPS_ISA_LEVEL_SPEC, \
929 BASE_DRIVER_SELF_SPECS
930
931 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
932 && ISA_HAS_COND_TRAP)
933
934 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
935
936 /* True if the ABI can only work with 64-bit integer registers. We
937 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
938 otherwise floating-point registers must also be 64-bit. */
939 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
940
941 /* Likewise for 32-bit regs. */
942 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
943
944 /* True if the file format uses 64-bit symbols. At present, this is
945 only true for n64, which uses 64-bit ELF. */
946 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
947
948 /* True if symbols are 64 bits wide. This is usually determined by
949 the ABI's file format, but it can be overridden by -msym32. Note that
950 overriding the size with -msym32 changes the ABI of relocatable objects,
951 although it doesn't change the ABI of a fully-linked object. */
952 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
953 && Pmode == DImode \
954 && !TARGET_SYM32)
955
956 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
957 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
958 || ISA_MIPS4 \
959 || ISA_MIPS64 \
960 || ISA_MIPS64R2 \
961 || ISA_MIPS64R3 \
962 || ISA_MIPS64R5 \
963 || ISA_MIPS64R6)
964
965 #define ISA_HAS_JR (mips_isa_rev <= 5)
966
967 #define ISA_HAS_DELAY_SLOTS 1
968
969 #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6)
970
971 /* ISA has branch likely instructions (e.g. mips2). */
972 /* Disable branchlikely for tx39 until compare rewrite. They haven't
973 been generated up to this point. */
974 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
975
976 /* ISA has 32 single-precision registers. */
977 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
978 && !TARGET_GS464) \
979 || TARGET_FLOAT64 \
980 || TARGET_MIPS5900)
981
982 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
983 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
984 || TARGET_MIPS5400 \
985 || TARGET_MIPS5500 \
986 || TARGET_MIPS5900 \
987 || TARGET_MIPS7000 \
988 || TARGET_MIPS9000 \
989 || TARGET_MAD \
990 || (mips_isa_rev >= 1 \
991 && mips_isa_rev <= 5)) \
992 && !TARGET_MIPS16)
993
994 /* ISA has a three-operand multiplication instruction. */
995 #define ISA_HAS_DMUL3 (TARGET_64BIT \
996 && TARGET_OCTEON \
997 && !TARGET_MIPS16)
998
999 /* ISA has HI and LO registers. */
1000 #define ISA_HAS_HILO (mips_isa_rev <= 5)
1001
1002 /* ISA supports instructions DMULT and DMULTU. */
1003 #define ISA_HAS_DMULT (TARGET_64BIT \
1004 && !TARGET_MIPS5900 \
1005 && mips_isa_rev <= 5)
1006
1007 /* ISA supports instructions MULT and MULTU. */
1008 #define ISA_HAS_MULT (mips_isa_rev <= 5)
1009
1010 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
1011 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
1012
1013 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
1014 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
1015
1016 /* For Loongson, it is preferable to use the Loongson-specific division and
1017 modulo instructions instead of the regular (D)DIV(U) instruction,
1018 because the former are faster and can also have the effect of reducing
1019 code size. */
1020 #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \
1021 || TARGET_GS464) \
1022 && !TARGET_MIPS16)
1023
1024 /* ISA supports instructions DDIV and DDIVU. */
1025 #define ISA_HAS_DDIV (TARGET_64BIT \
1026 && !TARGET_MIPS5900 \
1027 && !ISA_AVOID_DIV_HILO \
1028 && mips_isa_rev <= 5)
1029
1030 /* ISA supports instructions DIV and DIVU.
1031 This is always true, but the macro is needed for ISA_HAS_<D>DIV
1032 in mips.md. */
1033 #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \
1034 && mips_isa_rev <= 5)
1035
1036 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
1037 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
1038
1039 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
1040 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
1041
1042 /* ISA has the floating-point conditional move instructions introduced
1043 in mips4. */
1044 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
1045 || (mips_isa_rev >= 1 \
1046 && mips_isa_rev <= 5)) \
1047 && !TARGET_MIPS5500 \
1048 && !TARGET_MIPS16)
1049
1050 /* ISA has the integer conditional move instructions introduced in mips4 and
1051 ST Loongson 2E/2F. */
1052 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
1053 || TARGET_MIPS5900 \
1054 || TARGET_LOONGSON_2EF)
1055
1056 /* ISA has LDC1 and SDC1. */
1057 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
1058 && !TARGET_MIPS5900 \
1059 && !TARGET_MIPS16)
1060
1061 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
1062 branch on CC, and move (both FP and non-FP) on CC. */
1063 #define ISA_HAS_8CC (ISA_MIPS4 \
1064 || (mips_isa_rev >= 1 \
1065 && mips_isa_rev <= 5))
1066
1067 /* ISA has the FP condition code instructions that store the flag in an
1068 FP register. */
1069 #define ISA_HAS_CCF (mips_isa_rev >= 6)
1070
1071 #define ISA_HAS_SEL (mips_isa_rev >= 6)
1072
1073 /* This is a catch all for other mips4 instructions: indexed load, the
1074 FP madd and msub instructions, and the FP recip and recip sqrt
1075 instructions. Note that this macro should only be used by other
1076 ISA_HAS_* macros. */
1077 #define ISA_HAS_FP4 ((ISA_MIPS4 \
1078 || ISA_MIPS64 \
1079 || (mips_isa_rev >= 2 \
1080 && mips_isa_rev <= 5)) \
1081 && !TARGET_MIPS16)
1082
1083 /* ISA has floating-point indexed load and store instructions
1084 (LWXC1, LDXC1, SWXC1 and SDXC1). */
1085 #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \
1086 && mips_lxc1_sxc1)
1087
1088 /* ISA has paired-single instructions. */
1089 #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \
1090 || (mips_isa_rev >= 2 \
1091 && mips_isa_rev <= 5)) \
1092 && !TARGET_OCTEON)
1093
1094 /* ISA has conditional trap instructions. */
1095 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
1096 && !TARGET_MIPS16)
1097
1098 /* ISA has conditional trap with immediate instructions. */
1099 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
1100 && mips_isa_rev <= 5 \
1101 && !TARGET_MIPS16)
1102
1103 /* ISA has integer multiply-accumulate instructions, madd and msub. */
1104 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
1105 && mips_isa_rev <= 5)
1106
1107 /* Integer multiply-accumulate instructions should be generated. */
1108 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
1109
1110 /* ISA has 4 operand fused madd instructions of the form
1111 'd = [+-] (a * b [+-] c)'. */
1112 #define ISA_HAS_FUSED_MADD4 (mips_madd4 \
1113 && (TARGET_MIPS8000 \
1114 || TARGET_GS464 \
1115 || TARGET_GS464E \
1116 || TARGET_GS264E))
1117
1118 /* ISA has 4 operand unfused madd instructions of the form
1119 'd = [+-] (a * b [+-] c)'. */
1120 #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \
1121 && ISA_HAS_FP4 \
1122 && !TARGET_MIPS8000 \
1123 && !TARGET_GS464 \
1124 && !TARGET_GS464E \
1125 && !TARGET_GS264E)
1126
1127 /* ISA has 3 operand r6 fused madd instructions of the form
1128 'c = c [+-] (a * b)'. */
1129 #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6)
1130
1131 /* ISA has 3 operand loongson fused madd instructions of the form
1132 'c = [+-] (a * b [+-] c)'. */
1133 #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF
1134
1135 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1136 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1137 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1138 this restriction to the MIPS IV ISA too. */
1139 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1140 (((ISA_HAS_FP4 \
1141 && ((MODE) == SFmode \
1142 || ((TARGET_FLOAT64 \
1143 || mips_isa_rev >= 2) \
1144 && (MODE) == DFmode))) \
1145 || (((MODE) == SFmode \
1146 || (MODE) == DFmode) \
1147 && (mips_isa_rev >= 6)) \
1148 || (TARGET_SB1 \
1149 && (MODE) == V2SFmode)) \
1150 && !TARGET_MIPS16)
1151
1152 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1153
1154 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1155
1156 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1157
1158 /* ISA has count leading zeroes/ones instruction (not implemented). */
1159 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1160
1161 /* ISA has count trailing zeroes/ones instruction. */
1162 #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2)
1163
1164 /* ISA has three operand multiply instructions that put
1165 the high part in an accumulator: mulhi or mulhiu. */
1166 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1167 || TARGET_MIPS5500 \
1168 || TARGET_SR71K) \
1169 && !TARGET_MIPS16)
1170
1171 /* ISA has three operand multiply instructions that negate the
1172 result and put the result in an accumulator. */
1173 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1174 || TARGET_MIPS5500 \
1175 || TARGET_SR71K) \
1176 && !TARGET_MIPS16)
1177
1178 /* ISA has three operand multiply instructions that subtract the
1179 result from a 4th operand and put the result in an accumulator. */
1180 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1181 || TARGET_MIPS5500 \
1182 || TARGET_SR71K) \
1183 && !TARGET_MIPS16)
1184
1185 /* ISA has three operand multiply instructions that add the result
1186 to a 4th operand and put the result in an accumulator. */
1187 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1188 || TARGET_MIPS4130 \
1189 || TARGET_MIPS5400 \
1190 || TARGET_MIPS5500 \
1191 || TARGET_SR71K) \
1192 && !TARGET_MIPS16)
1193
1194 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1195 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1196 || TARGET_MIPS4130) \
1197 && !TARGET_MIPS16)
1198
1199 /* ISA has the "ror" (rotate right) instructions. */
1200 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1201 || TARGET_MIPS5400 \
1202 || TARGET_MIPS5500 \
1203 || TARGET_SR71K \
1204 || TARGET_SMARTMIPS) \
1205 && !TARGET_MIPS16)
1206
1207 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1208 64-bit targets also provide DSBH and DSHD. */
1209 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1210
1211 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1212 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1213 || TARGET_LOONGSON_2EF \
1214 || TARGET_MIPS5900 \
1215 || mips_isa_rev >= 1) \
1216 && !TARGET_MIPS16)
1217
1218 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1219 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
1220
1221 /* ISA has data indexed prefetch instructions. This controls use of
1222 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1223 (prefx is a cop1x instruction, so can only be used if FP is
1224 enabled.) */
1225 #define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \
1226 || TARGET_LOONGSON_EXT \
1227 || TARGET_LOONGSON_EXT2)
1228
1229 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1230 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1231 also requires TARGET_DOUBLE_FLOAT. */
1232 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1233
1234 /* ISA includes the MIPS32r2 seb and seh instructions. */
1235 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1236
1237 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1238 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1239
1240 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1241 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1242 && mips_isa_rev >= 2)
1243
1244 /* ISA has lwxs instruction (load w/scaled index address. */
1245 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1246 && !TARGET_MIPS16)
1247
1248 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1249 #define ISA_HAS_LBX (TARGET_OCTEON2)
1250 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1251 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1252 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1253 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1254 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1255 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1256 && TARGET_64BIT)
1257
1258 /* The DSP ASE is available. */
1259 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1260
1261 /* Revision 2 of the DSP ASE is available. */
1262 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1263
1264 /* The MSA ASE is available. */
1265 #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16)
1266
1267 /* True if the result of a load is not available to the next instruction.
1268 A nop will then be needed between instructions like "lw $4,..."
1269 and "addiu $4,$4,1". */
1270 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1271 && !TARGET_MIPS3900 \
1272 && !TARGET_MIPS5900 \
1273 && !TARGET_MIPS16 \
1274 && !TARGET_MICROMIPS)
1275
1276 /* Likewise mtc1 and mfc1. */
1277 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1278 && !TARGET_MIPS5900 \
1279 && !TARGET_LOONGSON_2EF)
1280
1281 /* Likewise floating-point comparisons. */
1282 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1283 && !TARGET_MIPS5900 \
1284 && !TARGET_LOONGSON_2EF)
1285
1286 /* True if mflo and mfhi can be immediately followed by instructions
1287 which write to the HI and LO registers.
1288
1289 According to MIPS specifications, MIPS ISAs I, II, and III need
1290 (at least) two instructions between the reads of HI/LO and
1291 instructions which write them, and later ISAs do not. Contradicting
1292 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1293 the UM for the NEC Vr5000) document needing the instructions between
1294 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1295 MIPS64 and later ISAs to have the interlocks, plus any specific
1296 earlier-ISA CPUs for which CPU documentation declares that the
1297 instructions are really interlocked. */
1298 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1299 || TARGET_MIPS5500 \
1300 || TARGET_MIPS5900 \
1301 || TARGET_LOONGSON_2EF)
1302
1303 /* ISA includes synci, jr.hb and jalr.hb. */
1304 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1305
1306 /* ISA includes sync. */
1307 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1308 #define GENERATE_SYNC \
1309 (target_flags_explicit & MASK_LLSC \
1310 ? TARGET_LLSC && !TARGET_MIPS16 \
1311 : ISA_HAS_SYNC)
1312
1313 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1314 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1315 instructions. */
1316 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1317 #define GENERATE_LL_SC \
1318 (target_flags_explicit & MASK_LLSC \
1319 ? TARGET_LLSC && !TARGET_MIPS16 \
1320 : ISA_HAS_LL_SC)
1321
1322 #define ISA_HAS_SWAP (TARGET_XLP)
1323 #define ISA_HAS_LDADD (TARGET_XLP)
1324
1325 /* ISA includes the baddu instruction. */
1326 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1327
1328 /* ISA includes the bbit* instructions. */
1329 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1330
1331 /* ISA includes the cins instruction. */
1332 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1333
1334 /* ISA includes the exts instruction. */
1335 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1336
1337 /* ISA includes the seq and sne instructions. */
1338 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1339
1340 /* ISA includes the pop instruction. */
1341 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1342
1343 /* The CACHE instruction is available in non-MIPS16 code. */
1344 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1345
1346 /* The CACHE instruction is available. */
1347 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1348 \f
1349 /* Tell collect what flags to pass to nm. */
1350 #ifndef NM_FLAGS
1351 #define NM_FLAGS "-Bn"
1352 #endif
1353
1354 \f
1355 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1356 the assembler. It may be overridden by subtargets.
1357
1358 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1359 COFF debugging info. */
1360
1361 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1362 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1363 %{g} %{g0} %{g1} %{g2} %{g3} \
1364 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1365 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1366 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}"
1367 #endif
1368
1369 /* FP_ASM_SPEC represents the floating-point options that must be passed
1370 to the assembler when FPXX support exists. Prior to that point the
1371 assembler could accept the options but were not required for
1372 correctness. We only add the options when absolutely necessary
1373 because passing -msoft-float to the assembler will cause it to reject
1374 all hard-float instructions which may require some user code to be
1375 updated. */
1376
1377 #ifdef HAVE_AS_DOT_MODULE
1378 #define FP_ASM_SPEC "\
1379 %{mhard-float} %{msoft-float} \
1380 %{msingle-float} %{mdouble-float}"
1381 #else
1382 #define FP_ASM_SPEC
1383 #endif
1384
1385 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1386 overridden by subtargets. */
1387
1388 #ifndef SUBTARGET_ASM_SPEC
1389 #define SUBTARGET_ASM_SPEC ""
1390 #endif
1391
1392 #undef ASM_SPEC
1393 #define ASM_SPEC "\
1394 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1395 %{mips32*} %{mips64*} \
1396 %{mips16} %{mno-mips16:-no-mips16} \
1397 %{mmicromips} %{mno-micromips} \
1398 %{mips3d} %{mno-mips3d:-no-mips3d} \
1399 %{mdmx} %{mno-mdmx:-no-mdmx} \
1400 %{mdsp} %{mno-dsp} \
1401 %{mdspr2} %{mno-dspr2} \
1402 %{mmcu} %{mno-mcu} \
1403 %{meva} %{mno-eva} \
1404 %{mvirt} %{mno-virt} \
1405 %{mxpa} %{mno-xpa} \
1406 %{mcrc} %{mno-crc} \
1407 %{mginv} %{mno-ginv} \
1408 %{mmsa} %{mno-msa} \
1409 %{mloongson-mmi} %{mno-loongson-mmi} \
1410 %{mloongson-ext} %{mno-loongson-ext} \
1411 %{mloongson-ext2} %{mno-loongson-ext2} \
1412 %{msmartmips} %{mno-smartmips} \
1413 %{mmt} %{mno-mt} \
1414 %{mfix-r5900} %{mno-fix-r5900} \
1415 %{mfix-rm7000} %{mno-fix-rm7000} \
1416 %{mfix-vr4120} %{mfix-vr4130} \
1417 %{mfix-24k} \
1418 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1419 %(subtarget_asm_debugging_spec) \
1420 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1421 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1422 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1423 %{modd-spreg} %{mno-odd-spreg} \
1424 %{mshared} %{mno-shared} \
1425 %{msym32} %{mno-sym32} \
1426 %{mtune=*}" \
1427 FP_ASM_SPEC "\
1428 %(subtarget_asm_spec)"
1429
1430 /* Extra switches sometimes passed to the linker. */
1431
1432 #ifndef LINK_SPEC
1433 #define LINK_SPEC "\
1434 %(endian_spec) \
1435 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1436 %{shared}"
1437 #endif /* LINK_SPEC defined */
1438
1439
1440 /* Specs for the compiler proper */
1441
1442 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1443 overridden by subtargets. */
1444 #ifndef SUBTARGET_CC1_SPEC
1445 #define SUBTARGET_CC1_SPEC ""
1446 #endif
1447
1448 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1449
1450 #undef CC1_SPEC
1451 #define CC1_SPEC "\
1452 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1453 %(subtarget_cc1_spec)"
1454
1455 /* Preprocessor specs. */
1456
1457 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1458 overridden by subtargets. */
1459 #ifndef SUBTARGET_CPP_SPEC
1460 #define SUBTARGET_CPP_SPEC ""
1461 #endif
1462
1463 #define CPP_SPEC "%(subtarget_cpp_spec)"
1464
1465 /* This macro defines names of additional specifications to put in the specs
1466 that can be used in various specifications like CC1_SPEC. Its definition
1467 is an initializer with a subgrouping for each command option.
1468
1469 Each subgrouping contains a string constant, that defines the
1470 specification name, and a string constant that used by the GCC driver
1471 program.
1472
1473 Do not define this macro if it does not need to do anything. */
1474
1475 #define EXTRA_SPECS \
1476 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1477 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1478 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1479 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1480 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1481 { "endian_spec", ENDIAN_SPEC }, \
1482 SUBTARGET_EXTRA_SPECS
1483
1484 #ifndef SUBTARGET_EXTRA_SPECS
1485 #define SUBTARGET_EXTRA_SPECS
1486 #endif
1487 \f
1488 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1489 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1490
1491 #ifndef PREFERRED_DEBUGGING_TYPE
1492 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1493 #endif
1494
1495 /* The size of DWARF addresses should be the same as the size of symbols
1496 in the target file format. They shouldn't depend on things like -msym32,
1497 because many DWARF consumers do not allow the mixture of address sizes
1498 that one would then get from linking -msym32 code with -msym64 code.
1499
1500 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1501 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1502 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1503
1504 /* By default, turn on GDB extensions. */
1505 #define DEFAULT_GDB_EXTENSIONS 1
1506
1507 /* Registers may have a prefix which can be ignored when matching
1508 user asm and register definitions. */
1509 #ifndef REGISTER_PREFIX
1510 #define REGISTER_PREFIX "$"
1511 #endif
1512
1513 /* Local compiler-generated symbols must have a prefix that the assembler
1514 understands. By default, this is $, although some targets (e.g.,
1515 NetBSD-ELF) need to override this. */
1516
1517 #ifndef LOCAL_LABEL_PREFIX
1518 #define LOCAL_LABEL_PREFIX "$"
1519 #endif
1520
1521 /* By default on the mips, external symbols do not have an underscore
1522 prepended, but some targets (e.g., NetBSD) require this. */
1523
1524 #ifndef USER_LABEL_PREFIX
1525 #define USER_LABEL_PREFIX ""
1526 #endif
1527
1528 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1529 since the length can run past this up to a continuation point. */
1530 #undef DBX_CONTIN_LENGTH
1531 #define DBX_CONTIN_LENGTH 1500
1532
1533 /* How to renumber registers for dbx and gdb. */
1534 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1535
1536 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1537 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1538
1539 /* The DWARF 2 CFA column which tracks the return address. */
1540 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1541
1542 /* Before the prologue, RA lives in r31. */
1543 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1544
1545 /* Describe how we implement __builtin_eh_return. */
1546 #define EH_RETURN_DATA_REGNO(N) \
1547 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1548
1549 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1550
1551 #define EH_USES(N) mips_eh_uses (N)
1552
1553 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1554 The default for this in 64-bit mode is 8, which causes problems with
1555 SFmode register saves. */
1556 #define DWARF_CIE_DATA_ALIGNMENT -4
1557
1558 /* Correct the offset of automatic variables and arguments. Note that
1559 the MIPS debug format wants all automatic variables and arguments
1560 to be in terms of the virtual frame pointer (stack pointer before
1561 any adjustment in the function), while the MIPS 3.0 linker wants
1562 the frame pointer to be the stack pointer after the initial
1563 adjustment. */
1564
1565 #define DEBUGGER_AUTO_OFFSET(X) \
1566 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1567 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1568 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1569 \f
1570 /* Target machine storage layout */
1571
1572 #define BITS_BIG_ENDIAN 0
1573 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1574 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1575
1576 #define MAX_BITS_PER_WORD 64
1577
1578 /* Width of a word, in units (bytes). */
1579 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1580 #ifndef IN_LIBGCC2
1581 #define MIN_UNITS_PER_WORD 4
1582 #endif
1583
1584 /* Width of a MSA vector register in bytes. */
1585 #define UNITS_PER_MSA_REG 16
1586 /* Width of a MSA vector register in bits. */
1587 #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT)
1588
1589 /* For MIPS, width of a floating point register. */
1590 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1591
1592 /* The number of consecutive floating-point registers needed to store the
1593 largest format supported by the FPU. */
1594 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1595
1596 /* The number of consecutive floating-point registers needed to store the
1597 smallest format supported by the FPU. */
1598 #define MIN_FPRS_PER_FMT \
1599 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1600
1601 /* The largest size of value that can be held in floating-point
1602 registers and moved with a single instruction. */
1603 #define UNITS_PER_HWFPVALUE \
1604 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1605
1606 /* The largest size of value that can be held in floating-point
1607 registers. */
1608 #define UNITS_PER_FPVALUE \
1609 (TARGET_SOFT_FLOAT_ABI ? 0 \
1610 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1611 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1612
1613 /* The number of bytes in a double. */
1614 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1615
1616 /* Set the sizes of the core types. */
1617 #define SHORT_TYPE_SIZE 16
1618 #define INT_TYPE_SIZE 32
1619 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1620 #define LONG_LONG_TYPE_SIZE 64
1621
1622 #define FLOAT_TYPE_SIZE 32
1623 #define DOUBLE_TYPE_SIZE 64
1624 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1625
1626 /* Define the sizes of fixed-point types. */
1627 #define SHORT_FRACT_TYPE_SIZE 8
1628 #define FRACT_TYPE_SIZE 16
1629 #define LONG_FRACT_TYPE_SIZE 32
1630 #define LONG_LONG_FRACT_TYPE_SIZE 64
1631
1632 #define SHORT_ACCUM_TYPE_SIZE 16
1633 #define ACCUM_TYPE_SIZE 32
1634 #define LONG_ACCUM_TYPE_SIZE 64
1635 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1636 doesn't support 128-bit integers for MIPS32 currently. */
1637 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1638
1639 /* long double is not a fixed mode, but the idea is that, if we
1640 support long double, we also want a 128-bit integer type. */
1641 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1642
1643 /* Width in bits of a pointer. */
1644 #ifndef POINTER_SIZE
1645 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1646 #endif
1647
1648 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1649 #define PARM_BOUNDARY BITS_PER_WORD
1650
1651 /* Allocation boundary (in *bits*) for the code of a function. */
1652 #define FUNCTION_BOUNDARY 32
1653
1654 /* Alignment of field after `int : 0' in a structure. */
1655 #define EMPTY_FIELD_BOUNDARY 32
1656
1657 /* Every structure's size must be a multiple of this. */
1658 /* 8 is observed right on a DECstation and on riscos 4.02. */
1659 #define STRUCTURE_SIZE_BOUNDARY 8
1660
1661 /* There is no point aligning anything to a rounder boundary than
1662 LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is
1663 BITS_PER_MSA_REG. */
1664 #define BIGGEST_ALIGNMENT \
1665 (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE)
1666
1667 /* All accesses must be aligned. */
1668 #define STRICT_ALIGNMENT 1
1669
1670 /* Define this if you wish to imitate the way many other C compilers
1671 handle alignment of bitfields and the structures that contain
1672 them.
1673
1674 The behavior is that the type written for a bit-field (`int',
1675 `short', or other integer type) imposes an alignment for the
1676 entire structure, as if the structure really did contain an
1677 ordinary field of that type. In addition, the bit-field is placed
1678 within the structure so that it would fit within such a field,
1679 not crossing a boundary for it.
1680
1681 Thus, on most machines, a bit-field whose type is written as `int'
1682 would not cross a four-byte boundary, and would force four-byte
1683 alignment for the whole structure. (The alignment used may not
1684 be four bytes; it is controlled by the other alignment
1685 parameters.)
1686
1687 If the macro is defined, its definition should be a C expression;
1688 a nonzero value for the expression enables this behavior. */
1689
1690 #define PCC_BITFIELD_TYPE_MATTERS 1
1691
1692 /* If defined, a C expression to compute the alignment for a static
1693 variable. TYPE is the data type, and ALIGN is the alignment that
1694 the object would ordinarily have. The value of this macro is used
1695 instead of that alignment to align the object.
1696
1697 If this macro is not defined, then ALIGN is used.
1698
1699 One use of this macro is to increase alignment of medium-size
1700 data to make it all fit in fewer cache lines. Another is to
1701 cause character arrays to be word-aligned so that `strcpy' calls
1702 that copy constants to character arrays can be done inline. */
1703
1704 #undef DATA_ALIGNMENT
1705 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1706 ((((ALIGN) < BITS_PER_WORD) \
1707 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1708 || TREE_CODE (TYPE) == UNION_TYPE \
1709 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1710
1711 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1712 character arrays to be word-aligned so that `strcpy' calls that copy
1713 constants to character arrays can be done inline, and 'strcmp' can be
1714 optimised to use word loads. */
1715 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1716 DATA_ALIGNMENT (TYPE, ALIGN)
1717
1718 #define PAD_VARARGS_DOWN \
1719 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1720
1721 /* Define if operations between registers always perform the operation
1722 on the full register even if a narrower mode is specified. */
1723 #define WORD_REGISTER_OPERATIONS 1
1724
1725 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1726 moves. All other references are zero extended. */
1727 #define LOAD_EXTEND_OP(MODE) \
1728 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1729 ? SIGN_EXTEND : ZERO_EXTEND)
1730
1731 /* Define this macro if it is advisable to hold scalars in registers
1732 in a wider mode than that declared by the program. In such cases,
1733 the value is constrained to be within the bounds of the declared
1734 type, but kept valid in the wider mode. The signedness of the
1735 extension may differ from that of the type. */
1736
1737 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1738 if (GET_MODE_CLASS (MODE) == MODE_INT \
1739 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1740 { \
1741 if ((MODE) == SImode) \
1742 (UNSIGNEDP) = 0; \
1743 (MODE) = Pmode; \
1744 }
1745
1746 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1747 Extensions of pointers to word_mode must be signed. */
1748 #define POINTERS_EXTEND_UNSIGNED false
1749
1750 /* Define if loading short immediate values into registers sign extends. */
1751 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1752
1753 /* The [d]clz instructions have the natural values at 0. */
1754
1755 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1756 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1757 \f
1758 /* Standard register usage. */
1759
1760 /* Number of hardware registers. We have:
1761
1762 - 32 integer registers
1763 - 32 floating point registers
1764 - 8 condition code registers
1765 - 2 accumulator registers (hi and lo)
1766 - 32 registers each for coprocessors 0, 2 and 3
1767 - 4 fake registers:
1768 - ARG_POINTER_REGNUM
1769 - FRAME_POINTER_REGNUM
1770 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1771 - CPRESTORE_SLOT_REGNUM
1772 - 2 dummy entries that were used at various times in the past.
1773 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1774 - 6 DSP control registers */
1775
1776 #define FIRST_PSEUDO_REGISTER 188
1777
1778 /* By default, fix the kernel registers ($26 and $27), the global
1779 pointer ($28) and the stack pointer ($29). This can change
1780 depending on the command-line options.
1781
1782 Regarding coprocessor registers: without evidence to the contrary,
1783 it's best to assume that each coprocessor register has a unique
1784 use. This can be overridden, in, e.g., mips_option_override or
1785 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1786 inappropriate for a particular target. */
1787
1788 #define FIXED_REGISTERS \
1789 { \
1790 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1791 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1792 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1793 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1794 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1795 /* COP0 registers */ \
1796 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1797 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1798 /* COP2 registers */ \
1799 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1800 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1801 /* COP3 registers */ \
1802 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1803 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1804 /* 6 DSP accumulator registers & 6 control registers */ \
1805 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1806 }
1807
1808
1809 /* Set up this array for o32 by default.
1810
1811 Note that we don't mark $31 as a call-clobbered register. The idea is
1812 that it's really the call instructions themselves which clobber $31.
1813 We don't care what the called function does with it afterwards.
1814
1815 This approach makes it easier to implement sibcalls. Unlike normal
1816 calls, sibcalls don't clobber $31, so the register reaches the
1817 called function in tact. EPILOGUE_USES says that $31 is useful
1818 to the called function. */
1819
1820 #define CALL_USED_REGISTERS \
1821 { \
1822 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1823 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1824 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1825 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1826 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1827 /* COP0 registers */ \
1828 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1829 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1830 /* COP2 registers */ \
1831 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1832 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1833 /* COP3 registers */ \
1834 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1835 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1836 /* 6 DSP accumulator registers & 6 control registers */ \
1837 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1838 }
1839
1840
1841 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1842
1843 #define CALL_REALLY_USED_REGISTERS \
1844 { /* General registers. */ \
1845 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1846 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1847 /* Floating-point registers. */ \
1848 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1849 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1850 /* Others. */ \
1851 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1852 /* COP0 registers */ \
1853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1854 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1855 /* COP2 registers */ \
1856 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1857 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1858 /* COP3 registers */ \
1859 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1860 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1861 /* 6 DSP accumulator registers & 6 control registers */ \
1862 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1863 }
1864
1865 /* Internal macros to classify a register number as to whether it's a
1866 general purpose register, a floating point register, a
1867 multiply/divide register, or a status register. */
1868
1869 #define GP_REG_FIRST 0
1870 #define GP_REG_LAST 31
1871 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1872 #define GP_DBX_FIRST 0
1873 #define K0_REG_NUM (GP_REG_FIRST + 26)
1874 #define K1_REG_NUM (GP_REG_FIRST + 27)
1875 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1876
1877 #define FP_REG_FIRST 32
1878 #define FP_REG_LAST 63
1879 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1880 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1881
1882 #define MD_REG_FIRST 64
1883 #define MD_REG_LAST 65
1884 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1885 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1886
1887 #define MSA_REG_FIRST FP_REG_FIRST
1888 #define MSA_REG_LAST FP_REG_LAST
1889 #define MSA_REG_NUM FP_REG_NUM
1890
1891 /* The DWARF 2 CFA column which tracks the return address from a
1892 signal handler context. This means that to maintain backwards
1893 compatibility, no hard register can be assigned this column if it
1894 would need to be handled by the DWARF unwinder. */
1895 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1896
1897 #define ST_REG_FIRST 67
1898 #define ST_REG_LAST 74
1899 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1900
1901
1902 /* FIXME: renumber. */
1903 #define COP0_REG_FIRST 80
1904 #define COP0_REG_LAST 111
1905 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1906
1907 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1908 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1909 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1910
1911 #define COP2_REG_FIRST 112
1912 #define COP2_REG_LAST 143
1913 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1914
1915 #define COP3_REG_FIRST 144
1916 #define COP3_REG_LAST 175
1917 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1918
1919 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1920 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1921 #define ALL_COP_REG_LAST COP3_REG_LAST
1922 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1923
1924 #define DSP_ACC_REG_FIRST 176
1925 #define DSP_ACC_REG_LAST 181
1926 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1927
1928 #define AT_REGNUM (GP_REG_FIRST + 1)
1929 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1930 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1931
1932 /* A few bitfield locations for the coprocessor registers. */
1933 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1934 the cause register for the EIC interrupt mode. */
1935 #define CAUSE_IPL 10
1936 /* COP1 Enable is at bit 29 of the status register. */
1937 #define SR_COP1 29
1938 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1939 #define SR_IPL 10
1940 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status
1941 register. */
1942 #define SR_IM0 8
1943 /* Exception Level is at bit 1 of the status register. */
1944 #define SR_EXL 1
1945 /* Interrupt Enable is at bit 0 of the status register. */
1946 #define SR_IE 0
1947
1948 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1949 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1950 should be used instead. */
1951 #define FPSW_REGNUM ST_REG_FIRST
1952
1953 #define GP_REG_P(REGNO) \
1954 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1955 #define M16_REG_P(REGNO) \
1956 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1957 #define M16STORE_REG_P(REGNO) \
1958 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1959 #define FP_REG_P(REGNO) \
1960 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1961 #define MD_REG_P(REGNO) \
1962 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1963 #define ST_REG_P(REGNO) \
1964 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1965 #define COP0_REG_P(REGNO) \
1966 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1967 #define COP2_REG_P(REGNO) \
1968 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1969 #define COP3_REG_P(REGNO) \
1970 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1971 #define ALL_COP_REG_P(REGNO) \
1972 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1973 /* Test if REGNO is one of the 6 new DSP accumulators. */
1974 #define DSP_ACC_REG_P(REGNO) \
1975 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1976 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1977 #define ACC_REG_P(REGNO) \
1978 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1979 #define MSA_REG_P(REGNO) \
1980 ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM)
1981
1982 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1983 #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X)))
1984
1985 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1986 to initialize the mips16 gp pseudo register. */
1987 #define CONST_GP_P(X) \
1988 (GET_CODE (X) == CONST \
1989 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1990 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1991
1992 /* Return coprocessor number from register number. */
1993
1994 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1995 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1996 : COP3_REG_P (REGNO) ? '3' : '?')
1997
1998
1999 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
2000 mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
2001
2002 /* Select a register mode required for caller save of hard regno REGNO. */
2003 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
2004 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
2005
2006 /* Register to use for pushing function arguments. */
2007 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
2008
2009 /* These two registers don't really exist: they get eliminated to either
2010 the stack or hard frame pointer. */
2011 #define ARG_POINTER_REGNUM 77
2012 #define FRAME_POINTER_REGNUM 78
2013
2014 /* $30 is not available on the mips16, so we use $17 as the frame
2015 pointer. */
2016 #define HARD_FRAME_POINTER_REGNUM \
2017 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
2018
2019 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
2020 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
2021
2022 /* Register in which static-chain is passed to a function. */
2023 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
2024
2025 /* Registers used as temporaries in prologue/epilogue code:
2026
2027 - If a MIPS16 PIC function needs access to _gp, it first loads
2028 the value into MIPS16_PIC_TEMP and then copies it to $gp.
2029
2030 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
2031 register. The register must not conflict with MIPS16_PIC_TEMP.
2032
2033 - If we aren't generating MIPS16 code, the prologue can also use
2034 MIPS_PROLOGUE_TEMP2 as a general temporary register.
2035
2036 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
2037 register.
2038
2039 If we're generating MIPS16 code, these registers must come from the
2040 core set of 8. The prologue registers mustn't conflict with any
2041 incoming arguments, the static chain pointer, or the frame pointer.
2042 The epilogue temporary mustn't conflict with the return registers,
2043 the PIC call register ($25), the frame pointer, the EH stack adjustment,
2044 or the EH data registers.
2045
2046 If we're generating interrupt handlers, we use K0 as a temporary register
2047 in prologue/epilogue code. */
2048
2049 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
2050 #define MIPS_PROLOGUE_TEMP_REGNUM \
2051 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
2052 #define MIPS_PROLOGUE_TEMP2_REGNUM \
2053 (TARGET_MIPS16 \
2054 ? (gcc_unreachable (), INVALID_REGNUM) \
2055 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
2056 #define MIPS_EPILOGUE_TEMP_REGNUM \
2057 (cfun->machine->interrupt_handler_p \
2058 ? K0_REG_NUM \
2059 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
2060
2061 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
2062 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
2063 #define MIPS_PROLOGUE_TEMP2(MODE) \
2064 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
2065 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
2066
2067 /* Define this macro if it is as good or better to call a constant
2068 function address than to call an address kept in a register. */
2069 #define NO_FUNCTION_CSE 1
2070
2071 /* The ABI-defined global pointer. Sometimes we use a different
2072 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
2073 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
2074
2075 /* We normally use $28 as the global pointer. However, when generating
2076 n32/64 PIC, it is better for leaf functions to use a call-clobbered
2077 register instead. They can then avoid saving and restoring $28
2078 and perhaps avoid using a frame at all.
2079
2080 When a leaf function uses something other than $28, mips_expand_prologue
2081 will modify pic_offset_table_rtx in place. Take the register number
2082 from there after reload. */
2083 #define PIC_OFFSET_TABLE_REGNUM \
2084 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
2085 \f
2086 /* Define the classes of registers for register constraints in the
2087 machine description. Also define ranges of constants.
2088
2089 One of the classes must always be named ALL_REGS and include all hard regs.
2090 If there is more than one class, another class must be named NO_REGS
2091 and contain no registers.
2092
2093 The name GENERAL_REGS must be the name of a class (or an alias for
2094 another name such as ALL_REGS). This is the class of registers
2095 that is allowed by "g" or "r" in a register constraint.
2096 Also, registers outside this class are allocated only when
2097 instructions express preferences for them.
2098
2099 The classes must be numbered in nondecreasing order; that is,
2100 a larger-numbered class must never be contained completely
2101 in a smaller-numbered class.
2102
2103 For any two classes, it is very desirable that there be another
2104 class that represents their union. */
2105
2106 enum reg_class
2107 {
2108 NO_REGS, /* no registers in set */
2109 M16_STORE_REGS, /* microMIPS store registers */
2110 M16_REGS, /* mips16 directly accessible registers */
2111 M16_SP_REGS, /* mips16 + $sp */
2112 T_REG, /* mips16 T register ($24) */
2113 M16_T_REGS, /* mips16 registers plus T register */
2114 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2115 V1_REG, /* Register $v1 ($3) used for TLS access. */
2116 SPILL_REGS, /* All but $sp and call preserved regs are in here */
2117 LEA_REGS, /* Every GPR except $25 */
2118 GR_REGS, /* integer registers */
2119 FP_REGS, /* floating point registers */
2120 MD0_REG, /* first multiply/divide register */
2121 MD1_REG, /* second multiply/divide register */
2122 MD_REGS, /* multiply/divide registers (hi/lo) */
2123 COP0_REGS, /* generic coprocessor classes */
2124 COP2_REGS,
2125 COP3_REGS,
2126 ST_REGS, /* status registers (fp status) */
2127 DSP_ACC_REGS, /* DSP accumulator registers */
2128 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
2129 FRAME_REGS, /* $arg and $frame */
2130 GR_AND_MD0_REGS, /* union classes */
2131 GR_AND_MD1_REGS,
2132 GR_AND_MD_REGS,
2133 GR_AND_ACC_REGS,
2134 ALL_REGS, /* all registers */
2135 LIM_REG_CLASSES /* max value + 1 */
2136 };
2137
2138 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2139
2140 #define GENERAL_REGS GR_REGS
2141
2142 /* An initializer containing the names of the register classes as C
2143 string constants. These names are used in writing some of the
2144 debugging dumps. */
2145
2146 #define REG_CLASS_NAMES \
2147 { \
2148 "NO_REGS", \
2149 "M16_STORE_REGS", \
2150 "M16_REGS", \
2151 "M16_SP_REGS", \
2152 "T_REG", \
2153 "M16_T_REGS", \
2154 "PIC_FN_ADDR_REG", \
2155 "V1_REG", \
2156 "SPILL_REGS", \
2157 "LEA_REGS", \
2158 "GR_REGS", \
2159 "FP_REGS", \
2160 "MD0_REG", \
2161 "MD1_REG", \
2162 "MD_REGS", \
2163 /* coprocessor registers */ \
2164 "COP0_REGS", \
2165 "COP2_REGS", \
2166 "COP3_REGS", \
2167 "ST_REGS", \
2168 "DSP_ACC_REGS", \
2169 "ACC_REGS", \
2170 "FRAME_REGS", \
2171 "GR_AND_MD0_REGS", \
2172 "GR_AND_MD1_REGS", \
2173 "GR_AND_MD_REGS", \
2174 "GR_AND_ACC_REGS", \
2175 "ALL_REGS" \
2176 }
2177
2178 /* An initializer containing the contents of the register classes,
2179 as integers which are bit masks. The Nth integer specifies the
2180 contents of class N. The way the integer MASK is interpreted is
2181 that register R is in the class if `MASK & (1 << R)' is 1.
2182
2183 When the machine has more than 32 registers, an integer does not
2184 suffice. Then the integers are replaced by sub-initializers,
2185 braced groupings containing several integers. Each
2186 sub-initializer must be suitable as an initializer for the type
2187 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2188
2189 #define REG_CLASS_CONTENTS \
2190 { \
2191 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2192 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2193 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2194 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2195 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2196 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2197 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2198 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2199 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2200 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2201 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2202 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2203 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2204 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2205 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2206 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2207 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2208 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2209 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2210 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2211 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2212 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2213 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2214 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2215 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2216 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2217 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2218 }
2219
2220
2221 /* A C expression whose value is a register class containing hard
2222 register REGNO. In general there is more that one such class;
2223 choose a class which is "minimal", meaning that no smaller class
2224 also contains the register. */
2225
2226 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2227
2228 /* A macro whose definition is the name of the class to which a
2229 valid base register must belong. A base register is one used in
2230 an address which is the register value plus a displacement. */
2231
2232 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2233
2234 /* A macro whose definition is the name of the class to which a
2235 valid index register must belong. An index register is one used
2236 in an address where its value is either multiplied by a scale
2237 factor or added to another register (as well as added to a
2238 displacement). */
2239
2240 #define INDEX_REG_CLASS NO_REGS
2241
2242 /* We generally want to put call-clobbered registers ahead of
2243 call-saved ones. (IRA expects this.) */
2244
2245 #define REG_ALLOC_ORDER \
2246 { /* Accumulator registers. When GPRs and accumulators have equal \
2247 cost, we generally prefer to use accumulators. For example, \
2248 a division of multiplication result is better allocated to LO, \
2249 so that we put the MFLO at the point of use instead of at the \
2250 point of definition. It's also needed if we're to take advantage \
2251 of the extra accumulators available with -mdspr2. In some cases, \
2252 it can also help to reduce register pressure. */ \
2253 64, 65,176,177,178,179,180,181, \
2254 /* Call-clobbered GPRs. */ \
2255 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2256 24, 25, 31, \
2257 /* The global pointer. This is call-clobbered for o32 and o64 \
2258 abicalls, call-saved for n32 and n64 abicalls, and a program \
2259 invariant otherwise. Putting it between the call-clobbered \
2260 and call-saved registers should cope with all eventualities. */ \
2261 28, \
2262 /* Call-saved GPRs. */ \
2263 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2264 /* GPRs that can never be exposed to the register allocator. */ \
2265 0, 26, 27, 29, \
2266 /* Call-clobbered FPRs. */ \
2267 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2268 48, 49, 50, 51, \
2269 /* FPRs that are usually call-saved. The odd ones are actually \
2270 call-clobbered for n32, but listing them ahead of the even \
2271 registers might encourage the register allocator to fragment \
2272 the available FPR pairs. We need paired FPRs to store long \
2273 doubles, so it isn't clear that using a different order \
2274 for n32 would be a win. */ \
2275 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2276 /* None of the remaining classes have defined call-saved \
2277 registers. */ \
2278 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2279 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2280 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2281 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2282 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2283 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2284 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2285 182,183,184,185,186,187 \
2286 }
2287
2288 /* True if VALUE is an unsigned 6-bit number. */
2289
2290 #define UIMM6_OPERAND(VALUE) \
2291 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2292
2293 /* True if VALUE is a signed 10-bit number. */
2294
2295 #define IMM10_OPERAND(VALUE) \
2296 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2297
2298 /* True if VALUE is a signed 16-bit number. */
2299
2300 #define SMALL_OPERAND(VALUE) \
2301 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2302
2303 /* True if VALUE is an unsigned 16-bit number. */
2304
2305 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2306 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2307
2308 /* True if VALUE can be loaded into a register using LUI. */
2309
2310 #define LUI_OPERAND(VALUE) \
2311 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2312 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2313
2314 /* Return a value X with the low 16 bits clear, and such that
2315 VALUE - X is a signed 16-bit value. */
2316
2317 #define CONST_HIGH_PART(VALUE) \
2318 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2319
2320 #define CONST_LOW_PART(VALUE) \
2321 ((VALUE) - CONST_HIGH_PART (VALUE))
2322
2323 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2324 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2325 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2326 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2327 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2328
2329 /* The HI and LO registers can only be reloaded via the general
2330 registers. Condition code registers can only be loaded to the
2331 general registers, and from the floating point registers. */
2332
2333 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2334 mips_secondary_reload_class (CLASS, MODE, X, true)
2335 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2336 mips_secondary_reload_class (CLASS, MODE, X, false)
2337
2338 /* Return the maximum number of consecutive registers
2339 needed to represent mode MODE in a register of class CLASS. */
2340
2341 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2342 \f
2343 /* Stack layout; function entry, exit and calling. */
2344
2345 #define STACK_GROWS_DOWNWARD 1
2346
2347 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
2348 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
2349
2350 /* Size of the area allocated in the frame to save the GP. */
2351
2352 #define MIPS_GP_SAVE_AREA_SIZE \
2353 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2354
2355 #define RETURN_ADDR_RTX mips_return_addr
2356
2357 /* Mask off the MIPS16 ISA bit in unwind addresses.
2358
2359 The reason for this is a little subtle. When unwinding a call,
2360 we are given the call's return address, which on most targets
2361 is the address of the following instruction. However, what we
2362 actually want to find is the EH region for the call itself.
2363 The target-independent unwind code therefore searches for "RA - 1".
2364
2365 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2366 RA - 1 is therefore the real (even-valued) start of the return
2367 instruction. EH region labels are usually odd-valued MIPS16 symbols
2368 too, so a search for an even address within a MIPS16 region would
2369 usually work.
2370
2371 However, there is an exception. If the end of an EH region is also
2372 the end of a function, the end label is allowed to be even. This is
2373 necessary because a following non-MIPS16 function may also need EH
2374 information for its first instruction.
2375
2376 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2377 non-ISA-encoded address. This probably isn't ideal, but it is
2378 the traditional (legacy) behavior. It is therefore only safe
2379 to search MIPS EH regions for an _odd-valued_ address.
2380
2381 Masking off the ISA bit means that the target-independent code
2382 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2383 #define MASK_RETURN_ADDR GEN_INT (-2)
2384
2385
2386 /* Similarly, don't use the least-significant bit to tell pointers to
2387 code from vtable index. */
2388
2389 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2390
2391 /* The eliminations to $17 are only used for mips16 code. See the
2392 definition of HARD_FRAME_POINTER_REGNUM. */
2393
2394 #define ELIMINABLE_REGS \
2395 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2396 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2397 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2398 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2399 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2400 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2401
2402 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2403 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2404
2405 /* Allocate stack space for arguments at the beginning of each function. */
2406 #define ACCUMULATE_OUTGOING_ARGS 1
2407
2408 /* The argument pointer always points to the first argument. */
2409 #define FIRST_PARM_OFFSET(FNDECL) 0
2410
2411 /* o32 and o64 reserve stack space for all argument registers. */
2412 #define REG_PARM_STACK_SPACE(FNDECL) \
2413 (TARGET_OLDABI \
2414 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2415 : 0)
2416
2417 /* Define this if it is the responsibility of the caller to
2418 allocate the area reserved for arguments passed in registers.
2419 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2420 of this macro is to determine whether the space is included in
2421 `crtl->outgoing_args_size'. */
2422 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2423
2424 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2425 \f
2426 /* Symbolic macros for the registers used to return integer and floating
2427 point values. */
2428
2429 #define GP_RETURN (GP_REG_FIRST + 2)
2430 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2431
2432 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2433
2434 /* Symbolic macros for the first/last argument registers. */
2435
2436 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2437 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2438 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2439 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2440
2441 /* True if MODE is vector and supported in a MSA vector register. */
2442 #define MSA_SUPPORTED_MODE_P(MODE) \
2443 (ISA_HAS_MSA \
2444 && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \
2445 && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
2446 || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT))
2447
2448 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2449 are used for returning complex double values in soft-float code, so $6 is the
2450 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2451 $gp itself as the temporary. */
2452 #define POST_CALL_TMP_REG \
2453 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2454
2455 /* 1 if N is a possible register number for function argument passing.
2456 We have no FP argument registers when soft-float. Special handling
2457 is required for O32 where only even numbered registers are used for
2458 O32-FPXX and O32-FP64. */
2459
2460 #define FUNCTION_ARG_REGNO_P(N) \
2461 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2462 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2463 && (mips_abi != ABI_32 \
2464 || TARGET_FLOAT32 \
2465 || ((N) % 2 == 0)))) \
2466 && !fixed_regs[N])
2467 \f
2468 /* This structure has to cope with two different argument allocation
2469 schemes. Most MIPS ABIs view the arguments as a structure, of which
2470 the first N words go in registers and the rest go on the stack. If I
2471 < N, the Ith word might go in Ith integer argument register or in a
2472 floating-point register. For these ABIs, we only need to remember
2473 the offset of the current argument into the structure.
2474
2475 The EABI instead allocates the integer and floating-point arguments
2476 separately. The first N words of FP arguments go in FP registers,
2477 the rest go on the stack. Likewise, the first N words of the other
2478 arguments go in integer registers, and the rest go on the stack. We
2479 need to maintain three counts: the number of integer registers used,
2480 the number of floating-point registers used, and the number of words
2481 passed on the stack.
2482
2483 We could keep separate information for the two ABIs (a word count for
2484 the standard ABIs, and three separate counts for the EABI). But it
2485 seems simpler to view the standard ABIs as forms of EABI that do not
2486 allocate floating-point registers.
2487
2488 So for the standard ABIs, the first N words are allocated to integer
2489 registers, and mips_function_arg decides on an argument-by-argument
2490 basis whether that argument should really go in an integer register,
2491 or in a floating-point one. */
2492
2493 typedef struct mips_args {
2494 /* Always true for varargs functions. Otherwise true if at least
2495 one argument has been passed in an integer register. */
2496 int gp_reg_found;
2497
2498 /* The number of arguments seen so far. */
2499 unsigned int arg_number;
2500
2501 /* The number of integer registers used so far. For all ABIs except
2502 EABI, this is the number of words that have been added to the
2503 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2504 unsigned int num_gprs;
2505
2506 /* For EABI, the number of floating-point registers used so far. */
2507 unsigned int num_fprs;
2508
2509 /* The number of words passed on the stack. */
2510 unsigned int stack_words;
2511
2512 /* On the mips16, we need to keep track of which floating point
2513 arguments were passed in general registers, but would have been
2514 passed in the FP regs if this were a 32-bit function, so that we
2515 can move them to the FP regs if we wind up calling a 32-bit
2516 function. We record this information in fp_code, encoded in base
2517 four. A zero digit means no floating point argument, a one digit
2518 means an SFmode argument, and a two digit means a DFmode argument,
2519 and a three digit is not used. The low order digit is the first
2520 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2521 an SFmode argument. ??? A more sophisticated approach will be
2522 needed if MIPS_ABI != ABI_32. */
2523 int fp_code;
2524
2525 /* True if the function has a prototype. */
2526 int prototype;
2527 } CUMULATIVE_ARGS;
2528
2529 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2530 for a call to a function whose data type is FNTYPE.
2531 For a library call, FNTYPE is 0. */
2532
2533 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2534 mips_init_cumulative_args (&CUM, FNTYPE)
2535
2536 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2537 (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD)
2538
2539 /* True if using EABI and varargs can be passed in floating-point
2540 registers. Under these conditions, we need a more complex form
2541 of va_list, which tracks GPR, FPR and stack arguments separately. */
2542 #define EABI_FLOAT_VARARGS_P \
2543 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2544
2545 \f
2546 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2547
2548 /* Treat LOC as a byte offset from the stack pointer and round it up
2549 to the next fully-aligned offset. */
2550 #define MIPS_STACK_ALIGN(LOC) \
2551 (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
2552
2553 \f
2554 /* Output assembler code to FILE to increment profiler label # LABELNO
2555 for profiling a function entry. */
2556
2557 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2558
2559 /* The profiler preserves all interesting registers, including $31. */
2560 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2561
2562 /* No mips port has ever used the profiler counter word, so don't emit it
2563 or the label for it. */
2564
2565 #define NO_PROFILE_COUNTERS 1
2566
2567 /* Define this macro if the code for function profiling should come
2568 before the function prologue. Normally, the profiling code comes
2569 after. */
2570
2571 /* #define PROFILE_BEFORE_PROLOGUE */
2572
2573 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2574 the stack pointer does not matter. The value is tested only in
2575 functions that have frame pointers.
2576 No definition is equivalent to always zero. */
2577
2578 #define EXIT_IGNORE_STACK 1
2579
2580 \f
2581 /* Trampolines are a block of code followed by two pointers. */
2582
2583 #define TRAMPOLINE_SIZE \
2584 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2585
2586 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2587 pointers from a single LUI base. */
2588
2589 #define TRAMPOLINE_ALIGNMENT 64
2590
2591 /* mips_trampoline_init calls this library function to flush
2592 program and data caches. */
2593
2594 #ifndef CACHE_FLUSH_FUNC
2595 #define CACHE_FLUSH_FUNC "_flush_cache"
2596 #endif
2597
2598 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2599 /* Flush both caches. We need to flush the data cache in case \
2600 the system has a write-back cache. */ \
2601 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2602 LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \
2603 GEN_INT (3), TYPE_MODE (integer_type_node))
2604
2605 \f
2606 /* Addressing modes, and classification of registers for them. */
2607
2608 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2609 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2610 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2611 \f
2612 /* Maximum number of registers that can appear in a valid memory address. */
2613
2614 #define MAX_REGS_PER_ADDRESS 1
2615
2616 /* Check for constness inline but use mips_legitimate_address_p
2617 to check whether a constant really is an address. */
2618
2619 #define CONSTANT_ADDRESS_P(X) \
2620 (CONSTANT_P (X) && memory_address_p (SImode, X))
2621
2622 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2623 'the start of the function that this code is output in'. */
2624
2625 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2626 do { \
2627 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2628 asm_fprintf ((FILE), "%U%s", \
2629 XSTR (XEXP (DECL_RTL (current_function_decl), \
2630 0), 0)); \
2631 else \
2632 asm_fprintf ((FILE), "%U%s", (NAME)); \
2633 } while (0)
2634 \f
2635 /* Flag to mark a function decl symbol that requires a long call. */
2636 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2637 #define SYMBOL_REF_LONG_CALL_P(X) \
2638 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2639
2640 /* This flag marks functions that cannot be lazily bound. */
2641 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2642 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2643 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2644
2645 /* True if we're generating a form of MIPS16 code in which jump tables
2646 are stored in the text section and encoded as 16-bit PC-relative
2647 offsets. This is only possible when general text loads are allowed,
2648 since the table access itself will be an "lh" instruction. If the
2649 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2650 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2651
2652 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2653
2654 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2655
2656 /* Only use short offsets if their range will not overflow. */
2657 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2658 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2659 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2660 : SImode)
2661
2662 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2663
2664 /* Define this as 1 if `char' should by default be signed; else as 0. */
2665 #ifndef DEFAULT_SIGNED_CHAR
2666 #define DEFAULT_SIGNED_CHAR 1
2667 #endif
2668
2669 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2670 we generally don't want to use them for copying arbitrary data.
2671 A single N-word move is usually the same cost as N single-word moves. */
2672 #define MOVE_MAX UNITS_PER_WORD
2673 /* We don't modify it for MSA as it is only used by the classic reload. */
2674 #define MAX_MOVE_MAX 8
2675
2676 /* Define this macro as a C expression which is nonzero if
2677 accessing less than a word of memory (i.e. a `char' or a
2678 `short') is no faster than accessing a word of memory, i.e., if
2679 such access require more than one instruction or if there is no
2680 difference in cost between byte and (aligned) word loads.
2681
2682 On RISC machines, it tends to generate better code to define
2683 this as 1, since it avoids making a QI or HI mode register.
2684
2685 But, generating word accesses for -mips16 is generally bad as shifts
2686 (often extended) would be needed for byte accesses. */
2687 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2688
2689 /* Standard MIPS integer shifts truncate the shift amount to the
2690 width of the shifted operand. However, Loongson MMI shifts
2691 do not truncate the shift amount at all. */
2692 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI)
2693
2694
2695 /* Specify the machine mode that pointers have.
2696 After generation of rtl, the compiler makes no further distinction
2697 between pointers and any other objects of this machine mode. */
2698
2699 #ifndef Pmode
2700 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2701 #endif
2702
2703 /* Give call MEMs SImode since it is the "most permissive" mode
2704 for both 32-bit and 64-bit targets. */
2705
2706 #define FUNCTION_MODE SImode
2707
2708 \f
2709 /* We allocate $fcc registers by hand and can't cope with moves of
2710 CCmode registers to and from pseudos (or memory). */
2711 #define AVOID_CCMODE_COPIES
2712
2713 /* A C expression for the cost of a branch instruction. A value of
2714 1 is the default; other values are interpreted relative to that. */
2715
2716 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2717 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2718
2719 /* The MIPS port has several functions that return an instruction count.
2720 Multiplying the count by this value gives the number of bytes that
2721 the instructions occupy. */
2722 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2723
2724 /* The length of a NOP in bytes. */
2725 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2726
2727 /* If defined, modifies the length assigned to instruction INSN as a
2728 function of the context in which it is used. LENGTH is an lvalue
2729 that contains the initially computed length of the insn and should
2730 be updated with the correct length of the insn. */
2731 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2732 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2733
2734 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2735 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2736 its operands. */
2737 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2738 "%*" OPCODE "%?\t" OPERANDS "%/"
2739
2740 #define MIPS_BRANCH_C(OPCODE, OPERANDS) \
2741 "%*" OPCODE "%:\t" OPERANDS
2742
2743 /* Return an asm string that forces INSN to be treated as an absolute
2744 J or JAL instruction instead of an assembler macro. */
2745 #define MIPS_ABSOLUTE_JUMP(INSN) \
2746 (TARGET_ABICALLS_PIC2 \
2747 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2748 : INSN)
2749
2750 \f
2751 /* Control the assembler format that we output. */
2752
2753 /* Output to assembler file text saying following lines
2754 may contain character constants, extra white space, comments, etc. */
2755
2756 #ifndef ASM_APP_ON
2757 #define ASM_APP_ON " #APP\n"
2758 #endif
2759
2760 /* Output to assembler file text saying following lines
2761 no longer contain unusual constructs. */
2762
2763 #ifndef ASM_APP_OFF
2764 #define ASM_APP_OFF " #NO_APP\n"
2765 #endif
2766
2767 #define REGISTER_NAMES \
2768 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2769 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2770 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2771 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2772 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2773 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2774 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2775 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2776 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2777 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2778 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2779 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2780 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2781 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2782 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2783 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2784 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2785 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2786 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2787 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2788 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2789 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2790 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2791 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2792
2793 /* List the "software" names for each register. Also list the numerical
2794 names for $fp and $sp. */
2795
2796 #define ADDITIONAL_REGISTER_NAMES \
2797 { \
2798 { "$29", 29 + GP_REG_FIRST }, \
2799 { "$30", 30 + GP_REG_FIRST }, \
2800 { "at", 1 + GP_REG_FIRST }, \
2801 { "v0", 2 + GP_REG_FIRST }, \
2802 { "v1", 3 + GP_REG_FIRST }, \
2803 { "a0", 4 + GP_REG_FIRST }, \
2804 { "a1", 5 + GP_REG_FIRST }, \
2805 { "a2", 6 + GP_REG_FIRST }, \
2806 { "a3", 7 + GP_REG_FIRST }, \
2807 { "t0", 8 + GP_REG_FIRST }, \
2808 { "t1", 9 + GP_REG_FIRST }, \
2809 { "t2", 10 + GP_REG_FIRST }, \
2810 { "t3", 11 + GP_REG_FIRST }, \
2811 { "t4", 12 + GP_REG_FIRST }, \
2812 { "t5", 13 + GP_REG_FIRST }, \
2813 { "t6", 14 + GP_REG_FIRST }, \
2814 { "t7", 15 + GP_REG_FIRST }, \
2815 { "s0", 16 + GP_REG_FIRST }, \
2816 { "s1", 17 + GP_REG_FIRST }, \
2817 { "s2", 18 + GP_REG_FIRST }, \
2818 { "s3", 19 + GP_REG_FIRST }, \
2819 { "s4", 20 + GP_REG_FIRST }, \
2820 { "s5", 21 + GP_REG_FIRST }, \
2821 { "s6", 22 + GP_REG_FIRST }, \
2822 { "s7", 23 + GP_REG_FIRST }, \
2823 { "t8", 24 + GP_REG_FIRST }, \
2824 { "t9", 25 + GP_REG_FIRST }, \
2825 { "k0", 26 + GP_REG_FIRST }, \
2826 { "k1", 27 + GP_REG_FIRST }, \
2827 { "gp", 28 + GP_REG_FIRST }, \
2828 { "sp", 29 + GP_REG_FIRST }, \
2829 { "fp", 30 + GP_REG_FIRST }, \
2830 { "ra", 31 + GP_REG_FIRST }, \
2831 { "$w0", 0 + FP_REG_FIRST }, \
2832 { "$w1", 1 + FP_REG_FIRST }, \
2833 { "$w2", 2 + FP_REG_FIRST }, \
2834 { "$w3", 3 + FP_REG_FIRST }, \
2835 { "$w4", 4 + FP_REG_FIRST }, \
2836 { "$w5", 5 + FP_REG_FIRST }, \
2837 { "$w6", 6 + FP_REG_FIRST }, \
2838 { "$w7", 7 + FP_REG_FIRST }, \
2839 { "$w8", 8 + FP_REG_FIRST }, \
2840 { "$w9", 9 + FP_REG_FIRST }, \
2841 { "$w10", 10 + FP_REG_FIRST }, \
2842 { "$w11", 11 + FP_REG_FIRST }, \
2843 { "$w12", 12 + FP_REG_FIRST }, \
2844 { "$w13", 13 + FP_REG_FIRST }, \
2845 { "$w14", 14 + FP_REG_FIRST }, \
2846 { "$w15", 15 + FP_REG_FIRST }, \
2847 { "$w16", 16 + FP_REG_FIRST }, \
2848 { "$w17", 17 + FP_REG_FIRST }, \
2849 { "$w18", 18 + FP_REG_FIRST }, \
2850 { "$w19", 19 + FP_REG_FIRST }, \
2851 { "$w20", 20 + FP_REG_FIRST }, \
2852 { "$w21", 21 + FP_REG_FIRST }, \
2853 { "$w22", 22 + FP_REG_FIRST }, \
2854 { "$w23", 23 + FP_REG_FIRST }, \
2855 { "$w24", 24 + FP_REG_FIRST }, \
2856 { "$w25", 25 + FP_REG_FIRST }, \
2857 { "$w26", 26 + FP_REG_FIRST }, \
2858 { "$w27", 27 + FP_REG_FIRST }, \
2859 { "$w28", 28 + FP_REG_FIRST }, \
2860 { "$w29", 29 + FP_REG_FIRST }, \
2861 { "$w30", 30 + FP_REG_FIRST }, \
2862 { "$w31", 31 + FP_REG_FIRST } \
2863 }
2864
2865 #define DBR_OUTPUT_SEQEND(STREAM) \
2866 do \
2867 { \
2868 /* Undo the effect of '%*'. */ \
2869 mips_pop_asm_switch (&mips_nomacro); \
2870 mips_pop_asm_switch (&mips_noreorder); \
2871 /* Emit a blank line after the delay slot for emphasis. */ \
2872 fputs ("\n", STREAM); \
2873 } \
2874 while (0)
2875
2876 /* The MIPS implementation uses some labels for its own purpose. The
2877 following lists what labels are created, and are all formed by the
2878 pattern $L[a-z].*. The machine independent portion of GCC creates
2879 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2880
2881 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2882 $Lb[0-9]+ Begin blocks for MIPS debug support
2883 $Lc[0-9]+ Label for use in s<xx> operation.
2884 $Le[0-9]+ End blocks for MIPS debug support */
2885
2886 #undef ASM_DECLARE_OBJECT_NAME
2887 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2888 mips_declare_object (STREAM, NAME, "", ":\n")
2889
2890 /* Globalizing directive for a label. */
2891 #define GLOBAL_ASM_OP "\t.globl\t"
2892
2893 /* This says how to define a global common symbol. */
2894
2895 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2896
2897 /* This says how to define a local common symbol (i.e., not visible to
2898 linker). */
2899
2900 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2901 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2902 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2903 #endif
2904
2905 /* This says how to output an external. It would be possible not to
2906 output anything and let undefined symbol become external. However
2907 the assembler uses length information on externals to allocate in
2908 data/sdata bss/sbss, thereby saving exec time. */
2909
2910 #undef ASM_OUTPUT_EXTERNAL
2911 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2912 mips_output_external(STREAM,DECL,NAME)
2913
2914 /* This is how to declare a function name. The actual work of
2915 emitting the label is moved to function_prologue, so that we can
2916 get the line number correctly emitted before the .ent directive,
2917 and after any .file directives. Define as empty so that the function
2918 is not declared before the .ent directive elsewhere. */
2919
2920 #undef ASM_DECLARE_FUNCTION_NAME
2921 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2922
2923 /* This is how to store into the string LABEL
2924 the symbol_ref name of an internal numbered label where
2925 PREFIX is the class of label and NUM is the number within the class.
2926 This is suitable for output with `assemble_name'. */
2927
2928 #undef ASM_GENERATE_INTERNAL_LABEL
2929 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2930 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2931
2932 /* Print debug labels as "foo = ." rather than "foo:" because they should
2933 represent a byte pointer rather than an ISA-encoded address. This is
2934 particularly important for code like:
2935
2936 $LFBxxx = .
2937 .cfi_startproc
2938 ...
2939 .section .gcc_except_table,...
2940 ...
2941 .uleb128 foo-$LFBxxx
2942
2943 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2944 likewise a byte pointer rather than an ISA-encoded address.
2945
2946 At the time of writing, this hook is not used for the function end
2947 label:
2948
2949 $LFExxx:
2950 .end foo
2951
2952 But this doesn't matter, because GAS doesn't treat a pre-.end label
2953 as a MIPS16 one anyway. */
2954
2955 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2956 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2957
2958 /* This is how to output an element of a case-vector that is absolute. */
2959
2960 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2961 fprintf (STREAM, "\t%s\t%sL%d\n", \
2962 ptr_mode == DImode ? ".dword" : ".word", \
2963 LOCAL_LABEL_PREFIX, \
2964 VALUE)
2965
2966 /* This is how to output an element of a case-vector. We can make the
2967 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2968 is supported. */
2969
2970 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2971 do { \
2972 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2973 { \
2974 if (GET_MODE (BODY) == HImode) \
2975 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2976 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2977 else \
2978 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2979 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2980 } \
2981 else if (TARGET_GPWORD) \
2982 fprintf (STREAM, "\t%s\t%sL%d\n", \
2983 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2984 LOCAL_LABEL_PREFIX, VALUE); \
2985 else if (TARGET_RTP_PIC) \
2986 { \
2987 /* Make the entry relative to the start of the function. */ \
2988 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2989 fprintf (STREAM, "\t%s\t%sL%d-", \
2990 Pmode == DImode ? ".dword" : ".word", \
2991 LOCAL_LABEL_PREFIX, VALUE); \
2992 assemble_name (STREAM, XSTR (fnsym, 0)); \
2993 fprintf (STREAM, "\n"); \
2994 } \
2995 else \
2996 fprintf (STREAM, "\t%s\t%sL%d\n", \
2997 ptr_mode == DImode ? ".dword" : ".word", \
2998 LOCAL_LABEL_PREFIX, VALUE); \
2999 } while (0)
3000
3001 /* Mark inline jump tables as data for the purpose of disassembly. For
3002 simplicity embed the jump table's label number in the local symbol
3003 produced so that multiple jump tables within a single function end
3004 up marked with unique symbols. Retain the alignment setting from
3005 `elfos.h' as we are replacing the definition from there. */
3006
3007 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
3008 #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \
3009 do \
3010 { \
3011 ASM_OUTPUT_ALIGN ((STREAM), 2); \
3012 if (JUMP_TABLES_IN_TEXT_SECTION) \
3013 mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \
3014 } \
3015 while (0)
3016
3017 /* Reset text marking to code after an inline jump table. Like with
3018 the beginning of a jump table use the label number to keep symbols
3019 unique. */
3020
3021 #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \
3022 do \
3023 if (JUMP_TABLES_IN_TEXT_SECTION) \
3024 mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \
3025 while (0)
3026
3027 /* This is how to output an assembler line
3028 that says to advance the location counter
3029 to a multiple of 2**LOG bytes. */
3030
3031 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3032 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3033
3034 /* This is how to output an assembler line to advance the location
3035 counter by SIZE bytes. */
3036
3037 #undef ASM_OUTPUT_SKIP
3038 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3039 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3040
3041 /* This is how to output a string. */
3042 #undef ASM_OUTPUT_ASCII
3043 #define ASM_OUTPUT_ASCII mips_output_ascii
3044
3045 \f
3046 /* Default to -G 8 */
3047 #ifndef MIPS_DEFAULT_GVALUE
3048 #define MIPS_DEFAULT_GVALUE 8
3049 #endif
3050
3051 /* Define the strings to put out for each section in the object file. */
3052 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3053 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3054
3055 #undef READONLY_DATA_SECTION_ASM_OP
3056 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3057 \f
3058 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3059 do \
3060 { \
3061 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
3062 TARGET_64BIT ? "daddiu" : "addiu", \
3063 reg_names[STACK_POINTER_REGNUM], \
3064 reg_names[STACK_POINTER_REGNUM], \
3065 TARGET_64BIT ? "sd" : "sw", \
3066 reg_names[REGNO], \
3067 reg_names[STACK_POINTER_REGNUM]); \
3068 } \
3069 while (0)
3070
3071 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3072 do \
3073 { \
3074 mips_push_asm_switch (&mips_noreorder); \
3075 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3076 TARGET_64BIT ? "ld" : "lw", \
3077 reg_names[REGNO], \
3078 reg_names[STACK_POINTER_REGNUM], \
3079 TARGET_64BIT ? "daddu" : "addu", \
3080 reg_names[STACK_POINTER_REGNUM], \
3081 reg_names[STACK_POINTER_REGNUM]); \
3082 mips_pop_asm_switch (&mips_noreorder); \
3083 } \
3084 while (0)
3085
3086 /* How to start an assembler comment.
3087 The leading space is important (the mips native assembler requires it). */
3088 #ifndef ASM_COMMENT_START
3089 #define ASM_COMMENT_START " #"
3090 #endif
3091 \f
3092 #undef SIZE_TYPE
3093 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3094
3095 #undef PTRDIFF_TYPE
3096 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3097
3098 /* The minimum alignment of any expanded block move. */
3099 #define MIPS_MIN_MOVE_MEM_ALIGN 16
3100
3101 /* The maximum number of bytes that can be copied by one iteration of
3102 a cpymemsi loop; see mips_block_move_loop. */
3103 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3104 (UNITS_PER_WORD * 4)
3105
3106 /* The maximum number of bytes that can be copied by a straight-line
3107 implementation of cpymemsi; see mips_block_move_straight. We want
3108 to make sure that any loop-based implementation will iterate at
3109 least twice. */
3110 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3111 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3112
3113 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3114 values were determined experimentally by benchmarking with CSiBE.
3115 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3116 for o32 where we have to restore $gp afterwards as well as make an
3117 indirect call), but in practice, bumping this up higher for
3118 TARGET_ABICALLS doesn't make much difference to code size. */
3119
3120 #define MIPS_CALL_RATIO 8
3121
3122 /* Any loop-based implementation of cpymemsi will have at least
3123 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3124 moves, so allow individual copies of fewer elements.
3125
3126 When cpymemsi is not available, use a value approximating
3127 the length of a memcpy call sequence, so that move_by_pieces
3128 will generate inline code if it is shorter than a function call.
3129 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3130 we'll have to generate a load/store pair for each, halve the
3131 value of MIPS_CALL_RATIO to take that into account. */
3132
3133 #define MOVE_RATIO(speed) \
3134 (HAVE_cpymemsi \
3135 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3136 : MIPS_CALL_RATIO / 2)
3137
3138 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3139 of the length of a memset call, but use the default otherwise. */
3140
3141 #define CLEAR_RATIO(speed)\
3142 ((speed) ? 15 : MIPS_CALL_RATIO)
3143
3144 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3145 optimizing for size adjust the ratio to account for the overhead of
3146 loading the constant and replicating it across the word. */
3147
3148 #define SET_RATIO(speed) \
3149 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3150 \f
3151 /* Since the bits of the _init and _fini function is spread across
3152 many object files, each potentially with its own GP, we must assume
3153 we need to load our GP. We don't preserve $gp or $ra, since each
3154 init/fini chunk is supposed to initialize $gp, and crti/crtn
3155 already take care of preserving $ra and, when appropriate, $gp. */
3156 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3157 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3158 asm (SECTION_OP "\n\
3159 .set push\n\
3160 .set nomips16\n\
3161 .set noreorder\n\
3162 bal 1f\n\
3163 nop\n\
3164 1: .cpload $31\n\
3165 .set reorder\n\
3166 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3167 jalr $25\n\
3168 .set pop\n\
3169 " TEXT_SECTION_ASM_OP);
3170 #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32)
3171 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3172 asm (SECTION_OP "\n\
3173 .set push\n\
3174 .set nomips16\n\
3175 .set noreorder\n\
3176 bal 1f\n\
3177 nop\n\
3178 1: .set reorder\n\
3179 .cpsetup $31, $2, 1b\n\
3180 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3181 jalr $25\n\
3182 .set pop\n\
3183 " TEXT_SECTION_ASM_OP);
3184 #elif (defined _ABI64 && _MIPS_SIM == _ABI64)
3185 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3186 asm (SECTION_OP "\n\
3187 .set push\n\
3188 .set nomips16\n\
3189 .set noreorder\n\
3190 bal 1f\n\
3191 nop\n\
3192 1: .set reorder\n\
3193 .cpsetup $31, $2, 1b\n\
3194 dla $25, " USER_LABEL_PREFIX #FUNC "\n\
3195 jalr $25\n\
3196 .set pop\n\
3197 " TEXT_SECTION_ASM_OP);
3198 #endif
3199
3200 #ifndef HAVE_AS_TLS
3201 #define HAVE_AS_TLS 0
3202 #endif
3203
3204 #ifndef HAVE_AS_NAN
3205 #define HAVE_AS_NAN 0
3206 #endif
3207
3208 #ifndef USED_FOR_TARGET
3209 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3210 struct mips_asm_switch {
3211 /* The FOO in the description above. */
3212 const char *name;
3213
3214 /* The current block nesting level, or 0 if we aren't in a block. */
3215 int nesting_level;
3216 };
3217
3218 extern const enum reg_class mips_regno_to_class[];
3219 extern const char *current_function_file; /* filename current function is in */
3220 extern int num_source_filenames; /* current .file # */
3221 extern struct mips_asm_switch mips_noreorder;
3222 extern struct mips_asm_switch mips_nomacro;
3223 extern struct mips_asm_switch mips_noat;
3224 extern int mips_dbx_regno[];
3225 extern int mips_dwarf_regno[];
3226 extern bool mips_split_p[];
3227 extern bool mips_split_hi_p[];
3228 extern bool mips_use_pcrel_pool_p[];
3229 extern const char *mips_lo_relocs[];
3230 extern const char *mips_hi_relocs[];
3231 extern enum processor mips_arch; /* which cpu to codegen for */
3232 extern enum processor mips_tune; /* which cpu to schedule for */
3233 extern int mips_isa; /* architectural level */
3234 extern int mips_isa_rev;
3235 extern const struct mips_cpu_info *mips_arch_info;
3236 extern const struct mips_cpu_info *mips_tune_info;
3237 extern unsigned int mips_base_compression_flags;
3238 extern GTY(()) struct target_globals *mips16_globals;
3239 extern GTY(()) struct target_globals *micromips_globals;
3240
3241 /* Information about a function's frame layout. */
3242 struct GTY(()) mips_frame_info {
3243 /* The size of the frame in bytes. */
3244 HOST_WIDE_INT total_size;
3245
3246 /* The number of bytes allocated to variables. */
3247 HOST_WIDE_INT var_size;
3248
3249 /* The number of bytes allocated to outgoing function arguments. */
3250 HOST_WIDE_INT args_size;
3251
3252 /* The number of bytes allocated to the .cprestore slot, or 0 if there
3253 is no such slot. */
3254 HOST_WIDE_INT cprestore_size;
3255
3256 /* Bit X is set if the function saves or restores GPR X. */
3257 unsigned int mask;
3258
3259 /* Likewise FPR X. */
3260 unsigned int fmask;
3261
3262 /* Likewise doubleword accumulator X ($acX). */
3263 unsigned int acc_mask;
3264
3265 /* The number of GPRs, FPRs, doubleword accumulators and COP0
3266 registers saved. */
3267 unsigned int num_gp;
3268 unsigned int num_fp;
3269 unsigned int num_acc;
3270 unsigned int num_cop0_regs;
3271
3272 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
3273 save slots from the top of the frame, or zero if no such slots are
3274 needed. */
3275 HOST_WIDE_INT gp_save_offset;
3276 HOST_WIDE_INT fp_save_offset;
3277 HOST_WIDE_INT acc_save_offset;
3278 HOST_WIDE_INT cop0_save_offset;
3279
3280 /* Likewise, but giving offsets from the bottom of the frame. */
3281 HOST_WIDE_INT gp_sp_offset;
3282 HOST_WIDE_INT fp_sp_offset;
3283 HOST_WIDE_INT acc_sp_offset;
3284 HOST_WIDE_INT cop0_sp_offset;
3285
3286 /* Similar, but the value passed to _mcount. */
3287 HOST_WIDE_INT ra_fp_offset;
3288
3289 /* The offset of arg_pointer_rtx from the bottom of the frame. */
3290 HOST_WIDE_INT arg_pointer_offset;
3291
3292 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
3293 HOST_WIDE_INT hard_frame_pointer_offset;
3294 };
3295
3296 /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */
3297 enum mips_int_mask
3298 {
3299 INT_MASK_EIC = -1,
3300 INT_MASK_SW0 = 0,
3301 INT_MASK_SW1 = 1,
3302 INT_MASK_HW0 = 2,
3303 INT_MASK_HW1 = 3,
3304 INT_MASK_HW2 = 4,
3305 INT_MASK_HW3 = 5,
3306 INT_MASK_HW4 = 6,
3307 INT_MASK_HW5 = 7
3308 };
3309
3310 /* Enumeration to mark the existence of the shadow register set.
3311 SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack
3312 pointer. */
3313 enum mips_shadow_set
3314 {
3315 SHADOW_SET_NO,
3316 SHADOW_SET_YES,
3317 SHADOW_SET_INTSTACK
3318 };
3319
3320 struct GTY(()) machine_function {
3321 /* The next floating-point condition-code register to allocate
3322 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
3323 unsigned int next_fcc;
3324
3325 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
3326 rtx mips16_gp_pseudo_rtx;
3327
3328 /* The number of extra stack bytes taken up by register varargs.
3329 This area is allocated by the callee at the very top of the frame. */
3330 int varargs_size;
3331
3332 /* The current frame information, calculated by mips_compute_frame_info. */
3333 struct mips_frame_info frame;
3334
3335 /* The register to use as the function's global pointer, or INVALID_REGNUM
3336 if the function doesn't need one. */
3337 unsigned int global_pointer;
3338
3339 /* How many instructions it takes to load a label into $AT, or 0 if
3340 this property hasn't yet been calculated. */
3341 unsigned int load_label_num_insns;
3342
3343 /* True if mips_adjust_insn_length should ignore an instruction's
3344 hazard attribute. */
3345 bool ignore_hazard_length_p;
3346
3347 /* True if the whole function is suitable for .set noreorder and
3348 .set nomacro. */
3349 bool all_noreorder_p;
3350
3351 /* True if the function has "inflexible" and "flexible" references
3352 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
3353 and mips_cfun_has_flexible_gp_ref_p for details. */
3354 bool has_inflexible_gp_insn_p;
3355 bool has_flexible_gp_insn_p;
3356
3357 /* True if the function's prologue must load the global pointer
3358 value into pic_offset_table_rtx and store the same value in
3359 the function's cprestore slot (if any). Even if this value
3360 is currently false, we may decide to set it to true later;
3361 see mips_must_initialize_gp_p () for details. */
3362 bool must_initialize_gp_p;
3363
3364 /* True if the current function must restore $gp after any potential
3365 clobber. This value is only meaningful during the first post-epilogue
3366 split_insns pass; see mips_must_initialize_gp_p () for details. */
3367 bool must_restore_gp_when_clobbered_p;
3368
3369 /* True if this is an interrupt handler. */
3370 bool interrupt_handler_p;
3371
3372 /* Records the way in which interrupts should be masked. Only used if
3373 interrupts are not kept masked. */
3374 enum mips_int_mask int_mask;
3375
3376 /* Records if this is an interrupt handler that uses shadow registers. */
3377 enum mips_shadow_set use_shadow_register_set;
3378
3379 /* True if this is an interrupt handler that should keep interrupts
3380 masked. */
3381 bool keep_interrupts_masked_p;
3382
3383 /* True if this is an interrupt handler that should use DERET
3384 instead of ERET. */
3385 bool use_debug_exception_return_p;
3386
3387 /* True if at least one of the formal parameters to a function must be
3388 written to the frame header (probably so its address can be taken). */
3389 bool does_not_use_frame_header;
3390
3391 /* True if none of the functions that are called by this function need
3392 stack space allocated for their arguments. */
3393 bool optimize_call_stack;
3394
3395 /* True if one of the functions calling this function may not allocate
3396 a frame header. */
3397 bool callers_may_not_allocate_frame;
3398
3399 /* True if GCC stored callee saved registers in the frame header. */
3400 bool use_frame_header_for_callee_saved_regs;
3401 };
3402 #endif
3403
3404 /* Enable querying of DFA units. */
3405 #define CPU_UNITS_QUERY 1
3406
3407 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3408 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3409
3410 /* As on most targets, we want the .eh_frame section to be read-only where
3411 possible. And as on most targets, this means two things:
3412
3413 (a) Non-locally-binding pointers must have an indirect encoding,
3414 so that the addresses in the .eh_frame section itself become
3415 locally-binding.
3416
3417 (b) A shared library's .eh_frame section must encode locally-binding
3418 pointers in a relative (relocation-free) form.
3419
3420 However, MIPS has traditionally not allowed directives like:
3421
3422 .long x-.
3423
3424 in cases where "x" is in a different section, or is not defined in the
3425 same assembly file. We are therefore unable to emit the PC-relative
3426 form required by (b) at assembly time.
3427
3428 Fortunately, the linker is able to convert absolute addresses into
3429 PC-relative addresses on our behalf. Unfortunately, only certain
3430 versions of the linker know how to do this for indirect pointers,
3431 and for personality data. We must fall back on using writable
3432 .eh_frame sections for shared libraries if the linker does not
3433 support this feature. */
3434 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3435 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3436
3437 /* For switching between MIPS16 and non-MIPS16 modes. */
3438 #define SWITCHABLE_TARGET 1
3439
3440 /* Several named MIPS patterns depend on Pmode. These patterns have the
3441 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3442 Add the appropriate suffix to generator function NAME and invoke it
3443 with arguments ARGS. */
3444 #define PMODE_INSN(NAME, ARGS) \
3445 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3446
3447 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3448 need to change these from /lib and /usr/lib. */
3449 #if MIPS_ABI_DEFAULT == ABI_N32
3450 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3451 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3452 #elif MIPS_ABI_DEFAULT == ABI_64
3453 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3454 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3455 #endif
3456
3457 /* Load store bonding is not supported by micromips and fix_24k. The
3458 performance can be degraded for those targets. Hence, do not bond for
3459 micromips or fix_24k. */
3460 #define ENABLE_LD_ST_PAIRS \
3461 (TARGET_LOAD_STORE_PAIRS \
3462 && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \
3463 && !TARGET_MICROMIPS && !TARGET_FIX_24K)
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