1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name
;
30 extern char call_used_regs
[];
31 extern int may_call_alloca
;
32 extern char **save_argv
;
33 extern int target_flags
;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI
, /* compare four byte integers */
40 CMP_DI
, /* compare eight byte integers */
41 CMP_SF
, /* compare single precision floats */
42 CMP_DF
, /* compare double precision floats */
43 CMP_MAX
/* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE
, /* no delay slot */
49 DELAY_LOAD
, /* load from memory delay */
50 DELAY_HILO
, /* move from/to hi/lo registers */
51 DELAY_FCMP
/* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
76 /* Recast the cpu class to be the cpu attribute. */
77 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
79 /* Which ABI to use. These are constants because abi64.h must check their
80 value at preprocessing time.
82 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
83 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
90 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
91 which is not the same as the above EABI (defined by Cygnus,
92 Greenhills, and Toshiba?). MEABI is not yet complete or published,
93 but at this point it looks like N32 as far as calling conventions go,
94 but allows for either 32 or 64 bit registers.
96 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
97 EABI the legacy EABI. In the end we may end up calling both ABI's
98 EABI but give them different version numbers, but for now I'm going
99 with different names. */
102 /* Whether to emit abicalls code sequences or not. */
104 enum mips_abicalls_type
{
109 /* Recast the abicalls class to be the abicalls attribute. */
110 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
112 /* Which type of block move to do (whether or not the last store is
113 split out so it can fill a branch delay slot). */
115 enum block_move_type
{
116 BLOCK_MOVE_NORMAL
, /* generate complete block move */
117 BLOCK_MOVE_NOT_LAST
, /* generate all but last store */
118 BLOCK_MOVE_LAST
/* generate just the last store */
121 extern char mips_reg_names
[][8]; /* register names (a0 vs. $4). */
122 extern char mips_print_operand_punct
[256]; /* print_operand punctuation chars */
123 extern const char *current_function_file
; /* filename current function is in */
124 extern int num_source_filenames
; /* current .file # */
125 extern int inside_function
; /* != 0 if inside of a function */
126 extern int ignore_line_number
; /* != 0 if we are to ignore next .loc */
127 extern int file_in_function_warning
; /* warning given about .file in func */
128 extern int sdb_label_count
; /* block start/end next label # */
129 extern int sdb_begin_function_line
; /* Starting Line of current function */
130 extern int mips_section_threshold
; /* # bytes of data/sdata cutoff */
131 extern int g_switch_value
; /* value of the -G xx switch */
132 extern int g_switch_set
; /* whether -G xx was passed. */
133 extern int sym_lineno
; /* sgi next label # for each stmt */
134 extern int set_noreorder
; /* # of nested .set noreorder's */
135 extern int set_nomacro
; /* # of nested .set nomacro's */
136 extern int set_noat
; /* # of nested .set noat's */
137 extern int set_volatile
; /* # of nested .set volatile's */
138 extern int mips_branch_likely
; /* emit 'l' after br (branch likely) */
139 extern int mips_dbx_regno
[]; /* Map register # to debug register # */
140 extern struct rtx_def
*branch_cmp
[2]; /* operands for compare */
141 extern enum cmp_type branch_type
; /* what type of branch to use */
142 extern enum processor_type mips_arch
; /* which cpu to codegen for */
143 extern enum processor_type mips_tune
; /* which cpu to schedule for */
144 extern enum mips_abicalls_type mips_abicalls
;/* for svr4 abi pic calls */
145 extern int mips_isa
; /* architectural level */
146 extern int mips16
; /* whether generating mips16 code */
147 extern int mips16_hard_float
; /* mips16 without -msoft-float */
148 extern int mips_entry
; /* generate entry/exit for mips16 */
149 extern const char *mips_cpu_string
; /* for -mcpu=<xxx> */
150 extern const char *mips_arch_string
; /* for -march=<xxx> */
151 extern const char *mips_tune_string
; /* for -mtune=<xxx> */
152 extern const char *mips_isa_string
; /* for -mips{1,2,3,4} */
153 extern const char *mips_abi_string
; /* for -mabi={32,n32,64} */
154 extern const char *mips_entry_string
; /* for -mentry */
155 extern const char *mips_no_mips16_string
;/* for -mno-mips16 */
156 extern const char *mips_explicit_type_size_string
;/* for -mexplicit-type-size */
157 extern const char *mips_cache_flush_func
;/* for -mflush-func= and -mno-flush-func */
158 extern int mips_split_addresses
; /* perform high/lo_sum support */
159 extern int dslots_load_total
; /* total # load related delay slots */
160 extern int dslots_load_filled
; /* # filled load delay slots */
161 extern int dslots_jump_total
; /* total # jump related delay slots */
162 extern int dslots_jump_filled
; /* # filled jump delay slots */
163 extern int dslots_number_nops
; /* # of nops needed by previous insn */
164 extern int num_refs
[3]; /* # 1/2/3 word references */
165 extern struct rtx_def
*mips_load_reg
; /* register to check for load delay */
166 extern struct rtx_def
*mips_load_reg2
; /* 2nd reg to check for load delay */
167 extern struct rtx_def
*mips_load_reg3
; /* 3rd reg to check for load delay */
168 extern struct rtx_def
*mips_load_reg4
; /* 4th reg to check for load delay */
169 extern int mips_string_length
; /* length of strings for mips16 */
171 /* Functions to change what output section we are using. */
172 extern void rdata_section
PARAMS ((void));
173 extern void sdata_section
PARAMS ((void));
174 extern void sbss_section
PARAMS ((void));
176 /* Stubs for half-pic support if not OSF/1 reference platform. */
179 #define HALF_PIC_P() 0
180 #define HALF_PIC_NUMBER_PTRS 0
181 #define HALF_PIC_NUMBER_REFS 0
182 #define HALF_PIC_ENCODE(DECL)
183 #define HALF_PIC_DECLARE(NAME)
184 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
185 #define HALF_PIC_ADDRESS_P(X) 0
186 #define HALF_PIC_PTR(X) X
187 #define HALF_PIC_FINISH(STREAM)
190 /* Macros to silence warnings about numbers being signed in traditional
191 C and unsigned in ISO C when compiled on 32-bit hosts. */
193 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
194 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
195 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
198 /* Run-time compilation parameters selecting different hardware subsets. */
200 /* Macros used in the machine description to test the flags. */
202 /* Bits for real switches */
203 #define MASK_INT64 0x00000001 /* ints are 64 bits */
204 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
205 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
206 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
207 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
208 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
209 #define MASK_STATS 0x00000040 /* print statistics to stderr */
210 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
211 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
212 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
213 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
214 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
215 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
216 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
217 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
218 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
219 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
220 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
221 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
222 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
223 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
224 #define MASK_NO_CHECK_ZERO_DIV \
225 0x00200000 /* divide by zero checking */
226 #define MASK_CHECK_RANGE_DIV \
227 0x00400000 /* divide result range checking */
228 #define MASK_UNINIT_CONST_IN_RODATA \
229 0x00800000 /* Store uninitialized
231 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
232 multiply-add operations. */
234 /* Debug switches, not documented */
235 #define MASK_DEBUG 0 /* unused */
236 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
237 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
238 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
239 #define MASK_DEBUG_D 0 /* don't do define_split's */
240 #define MASK_DEBUG_E 0 /* function_arg debug */
241 #define MASK_DEBUG_F 0 /* ??? */
242 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
243 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
244 #define MASK_DEBUG_I 0 /* unused */
246 /* Dummy switches used only in specs */
247 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
249 /* r4000 64 bit sizes */
250 #define TARGET_INT64 (target_flags & MASK_INT64)
251 #define TARGET_LONG64 (target_flags & MASK_LONG64)
252 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
253 #define TARGET_64BIT (target_flags & MASK_64BIT)
255 /* Mips vs. GNU linker */
256 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
258 /* Mips vs. GNU assembler */
259 #define TARGET_GAS (target_flags & MASK_GAS)
260 #define TARGET_MIPS_AS (!TARGET_GAS)
263 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
264 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
265 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
266 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
267 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
268 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
269 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
270 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
271 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
272 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
274 /* Reg. Naming in .s ($21 vs. $a0) */
275 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
277 /* Optimize for Sdata/Sbss */
278 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
280 /* print program statistics */
281 #define TARGET_STATS (target_flags & MASK_STATS)
283 /* call memcpy instead of inline code */
284 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
286 /* .abicalls, etc from Pyramid V.4 */
287 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
289 /* OSF pic references to externs */
290 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
292 /* software floating point */
293 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
294 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
296 /* always call through a register */
297 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
299 /* generate embedded PIC code;
301 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
303 /* for embedded systems, optimize for
304 reduced RAM space instead of for
306 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
308 /* always store uninitialized const
309 variables in rodata, requires
310 TARGET_EMBEDDED_DATA. */
311 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
313 /* generate big endian code. */
314 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
316 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
317 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
319 #define TARGET_MAD (target_flags & MASK_MAD)
321 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
323 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
325 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
326 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
328 /* This is true if we must enable the assembly language file switching
331 #define TARGET_FILE_SWITCHING \
332 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
334 /* We must disable the function end stabs when doing the file switching trick,
335 because the Lscope stabs end up in the wrong place, making it impossible
336 to debug the resulting code. */
337 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
339 /* Generate mips16 code */
340 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
342 /* Architecture target defines. */
343 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
344 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
345 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
346 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
347 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
348 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
350 /* Scheduling target defines. */
351 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
352 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
353 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
354 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
355 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
357 /* Macro to define tables used to set the flags.
358 This is a list in braces of pairs in braces,
359 each pair being { "NAME", VALUE }
360 where VALUE is the bits to set or minus the bits to clear.
361 An empty string NAME is used to identify the default VALUE. */
363 #define TARGET_SWITCHES \
366 N_("No default crt0.o") }, \
367 {"int64", MASK_INT64 | MASK_LONG64, \
368 N_("Use 64-bit int type")}, \
369 {"long64", MASK_LONG64, \
370 N_("Use 64-bit long type")}, \
371 {"long32", -(MASK_LONG64 | MASK_INT64), \
372 N_("Use 32-bit long type")}, \
373 {"split-addresses", MASK_SPLIT_ADDR, \
374 N_("Optimize lui/addiu address loads")}, \
375 {"no-split-addresses", -MASK_SPLIT_ADDR, \
376 N_("Don't optimize lui/addiu address loads")}, \
377 {"mips-as", -MASK_GAS, \
378 N_("Use MIPS as")}, \
381 {"rnames", MASK_NAME_REGS, \
382 N_("Use symbolic register names")}, \
383 {"no-rnames", -MASK_NAME_REGS, \
384 N_("Don't use symbolic register names")}, \
385 {"gpOPT", MASK_GPOPT, \
386 N_("Use GP relative sdata/sbss sections")}, \
387 {"gpopt", MASK_GPOPT, \
388 N_("Use GP relative sdata/sbss sections")}, \
389 {"no-gpOPT", -MASK_GPOPT, \
390 N_("Don't use GP relative sdata/sbss sections")}, \
391 {"no-gpopt", -MASK_GPOPT, \
392 N_("Don't use GP relative sdata/sbss sections")}, \
393 {"stats", MASK_STATS, \
394 N_("Output compiler statistics")}, \
395 {"no-stats", -MASK_STATS, \
396 N_("Don't output compiler statistics")}, \
397 {"memcpy", MASK_MEMCPY, \
398 N_("Don't optimize block moves")}, \
399 {"no-memcpy", -MASK_MEMCPY, \
400 N_("Optimize block moves")}, \
401 {"mips-tfile", MASK_MIPS_TFILE, \
402 N_("Use mips-tfile asm postpass")}, \
403 {"no-mips-tfile", -MASK_MIPS_TFILE, \
404 N_("Don't use mips-tfile asm postpass")}, \
405 {"soft-float", MASK_SOFT_FLOAT, \
406 N_("Use software floating point")}, \
407 {"hard-float", -MASK_SOFT_FLOAT, \
408 N_("Use hardware floating point")}, \
409 {"fp64", MASK_FLOAT64, \
410 N_("Use 64-bit FP registers")}, \
411 {"fp32", -MASK_FLOAT64, \
412 N_("Use 32-bit FP registers")}, \
413 {"gp64", MASK_64BIT, \
414 N_("Use 64-bit general registers")}, \
415 {"gp32", -MASK_64BIT, \
416 N_("Use 32-bit general registers")}, \
417 {"abicalls", MASK_ABICALLS, \
418 N_("Use Irix PIC")}, \
419 {"no-abicalls", -MASK_ABICALLS, \
420 N_("Don't use Irix PIC")}, \
421 {"half-pic", MASK_HALF_PIC, \
422 N_("Use OSF PIC")}, \
423 {"no-half-pic", -MASK_HALF_PIC, \
424 N_("Don't use OSF PIC")}, \
425 {"long-calls", MASK_LONG_CALLS, \
426 N_("Use indirect calls")}, \
427 {"no-long-calls", -MASK_LONG_CALLS, \
428 N_("Don't use indirect calls")}, \
429 {"embedded-pic", MASK_EMBEDDED_PIC, \
430 N_("Use embedded PIC")}, \
431 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
432 N_("Don't use embedded PIC")}, \
433 {"embedded-data", MASK_EMBEDDED_DATA, \
434 N_("Use ROM instead of RAM")}, \
435 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
436 N_("Don't use ROM instead of RAM")}, \
437 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
438 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
439 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
440 N_("Don't put uninitialized constants in ROM")}, \
441 {"eb", MASK_BIG_ENDIAN, \
442 N_("Use big-endian byte order")}, \
443 {"el", -MASK_BIG_ENDIAN, \
444 N_("Use little-endian byte order")}, \
445 {"single-float", MASK_SINGLE_FLOAT, \
446 N_("Use single (32-bit) FP only")}, \
447 {"double-float", -MASK_SINGLE_FLOAT, \
448 N_("Don't use single (32-bit) FP only")}, \
450 N_("Use multiply accumulate")}, \
451 {"no-mad", -MASK_MAD, \
452 N_("Don't use multiply accumulate")}, \
453 {"no-fused-madd", MASK_NO_FUSED_MADD, \
454 N_("Don't generate fused multiply/add instructions")}, \
455 {"fused-madd", -MASK_NO_FUSED_MADD, \
456 N_("Generate fused multiply/add instructions")}, \
457 {"fix4300", MASK_4300_MUL_FIX, \
458 N_("Work around early 4300 hardware bug")}, \
459 {"no-fix4300", -MASK_4300_MUL_FIX, \
460 N_("Don't work around early 4300 hardware bug")}, \
462 N_("Optimize for 3900")}, \
464 N_("Optimize for 4650")}, \
465 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
466 N_("Trap on integer divide by zero")}, \
467 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
468 N_("Don't trap on integer divide by zero")}, \
469 {"check-range-division",MASK_CHECK_RANGE_DIV, \
470 N_("Trap on integer divide overflow")}, \
471 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
472 N_("Don't trap on integer divide overflow")}, \
473 {"debug", MASK_DEBUG, \
475 {"debuga", MASK_DEBUG_A, \
477 {"debugb", MASK_DEBUG_B, \
479 {"debugc", MASK_DEBUG_C, \
481 {"debugd", MASK_DEBUG_D, \
483 {"debuge", MASK_DEBUG_E, \
485 {"debugf", MASK_DEBUG_F, \
487 {"debugg", MASK_DEBUG_G, \
489 {"debugh", MASK_DEBUG_H, \
491 {"debugi", MASK_DEBUG_I, \
493 {"", (TARGET_DEFAULT \
494 | TARGET_CPU_DEFAULT \
495 | TARGET_ENDIAN_DEFAULT), \
499 /* Default target_flags if no switches are specified */
501 #ifndef TARGET_DEFAULT
502 #define TARGET_DEFAULT 0
505 #ifndef TARGET_CPU_DEFAULT
506 #define TARGET_CPU_DEFAULT 0
509 #ifndef TARGET_ENDIAN_DEFAULT
511 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
513 #define TARGET_ENDIAN_DEFAULT 0
517 #ifndef MIPS_ISA_DEFAULT
518 #define MIPS_ISA_DEFAULT 1
523 /* Make this compile time constant for libgcc2 */
525 #define TARGET_64BIT 1
527 #define TARGET_64BIT 0
529 #endif /* IN_LIBGCC2 */
531 #ifndef MULTILIB_ENDIAN_DEFAULT
532 #if TARGET_ENDIAN_DEFAULT == 0
533 #define MULTILIB_ENDIAN_DEFAULT "EL"
535 #define MULTILIB_ENDIAN_DEFAULT "EB"
539 #ifndef MULTILIB_ISA_DEFAULT
540 # if MIPS_ISA_DEFAULT == 1
541 # define MULTILIB_ISA_DEFAULT "mips1"
543 # if MIPS_ISA_DEFAULT == 2
544 # define MULTILIB_ISA_DEFAULT "mips2"
546 # if MIPS_ISA_DEFAULT == 3
547 # define MULTILIB_ISA_DEFAULT "mips3"
549 # if MIPS_ISA_DEFAULT == 4
550 # define MULTILIB_ISA_DEFAULT "mips4"
552 # if MIPS_ISA_DEFAULT == 32
553 # define MULTILIB_ISA_DEFAULT "mips32"
555 # if MIPS_ISA_DEFAULT == 64
556 # define MULTILIB_ISA_DEFAULT "mips64"
558 # define MULTILIB_ISA_DEFAULT "mips1"
567 #ifndef MULTILIB_DEFAULTS
568 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
571 /* We must pass -EL to the linker by default for little endian embedded
572 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
573 linker will default to using big-endian output files. The OUTPUT_FORMAT
574 line must be in the linker script, otherwise -EB/-EL will not work. */
577 #if TARGET_ENDIAN_DEFAULT == 0
578 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
580 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
584 #define TARGET_OPTIONS \
586 SUBTARGET_TARGET_OPTIONS \
587 { "cpu=", &mips_cpu_string, \
588 N_("Specify CPU for scheduling purposes")}, \
589 { "tune=", &mips_tune_string, \
590 N_("Specify CPU for scheduling purposes")}, \
591 { "arch=", &mips_arch_string, \
592 N_("Specify CPU for code generation purposes")}, \
593 { "ips", &mips_isa_string, \
594 N_("Specify a Standard MIPS ISA")}, \
595 { "entry", &mips_entry_string, \
596 N_("Use mips16 entry/exit psuedo ops")}, \
597 { "no-mips16", &mips_no_mips16_string, \
598 N_("Don't use MIPS16 instructions")}, \
599 { "explicit-type-size", &mips_explicit_type_size_string, \
601 { "no-flush-func", &mips_cache_flush_func, \
602 N_("Don't call any cache flush functions")}, \
603 { "flush-func=", &mips_cache_flush_func, \
604 N_("Specify cache flush function")}, \
607 /* This is meant to be redefined in the host dependent files. */
608 #define SUBTARGET_TARGET_OPTIONS
610 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
612 /* Generate three-operand multiply instructions for SImode. */
613 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
618 /* Generate three-operand multiply instructions for DImode. */
619 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
622 /* Macros to decide whether certain features are available or not,
623 depending on the instruction set architecture level. */
625 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
626 #define HAVE_SQRT_P() (mips_isa != 1)
628 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
629 #define ISA_HAS_64BIT_REGS (mips_isa == 3 \
633 /* ISA has branch likely instructions (eg. mips2). */
634 /* Disable branchlikely for tx39 until compare rewrite. They haven't
635 been generated up to this point. */
636 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
639 /* ISA has the conditional move instructions introduced in mips4. */
640 #define ISA_HAS_CONDMOVE ((mips_isa == 4 \
645 /* ISA has just the integer condition move instructions (movn,movz) */
646 #define ISA_HAS_INT_CONDMOVE 0
648 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
649 branch on CC, and move (both FP and non-FP) on CC. */
650 #define ISA_HAS_8CC (mips_isa == 4 \
654 /* This is a catch all for the other new mips4 instructions: indexed load and
655 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
656 and the FP recip and recip sqrt instructions */
657 #define ISA_HAS_FP4 (mips_isa == 4 \
660 /* ISA has conditional trap instructions. */
661 #define ISA_HAS_COND_TRAP (mips_isa >= 2 \
664 /* ISA has multiply-accumulate instructions, madd and msub. */
665 #define ISA_HAS_MADD_MSUB ((mips_isa == 32 \
667 ) && ! TARGET_MIPS16)
669 /* ISA has nmadd and nmsub instructions. */
670 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
673 /* ISA has count leading zeroes/ones instruction (not implemented). */
674 #define ISA_HAS_CLZ_CLO ((mips_isa == 32 \
676 ) && ! TARGET_MIPS16)
678 /* ISA has double-word count leading zeroes/ones instruction (not
680 #define ISA_HAS_DCLZ_DCLO (mips_isa == 64 \
683 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
684 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
685 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
686 target_flags, and -mgp64 sets MASK_64BIT.
688 Setting MASK_64BIT in target_flags will cause gcc to assume that
689 registers are 64 bits wide. int, long and void * will be 32 bit;
690 this may be changed with -mint64 or -mlong64.
692 The gen* programs link code that refers to MASK_64BIT. They don't
693 actually use the information in target_flags; they just refer to
696 /* Switch Recognition by gcc.c. Add -G xx support */
698 #undef SWITCH_TAKES_ARG
699 #define SWITCH_TAKES_ARG(CHAR) \
700 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
702 /* Sometimes certain combinations of command options do not make sense
703 on a particular target machine. You can define a macro
704 `OVERRIDE_OPTIONS' to take account of this. This macro, if
705 defined, is executed once just after all the command options have
708 On the MIPS, it is used to handle -G. We also use it to set up all
709 of the tables referenced in the other macros. */
711 #define OVERRIDE_OPTIONS override_options ()
713 /* Zero or more C statements that may conditionally modify two
714 variables `fixed_regs' and `call_used_regs' (both of type `char
715 []') after they have been initialized from the two preceding
718 This is necessary in case the fixed or call-clobbered registers
719 depend on target flags.
721 You need not define this macro if it has no work to do.
723 If the usage of an entire class of registers depends on the target
724 flags, you may indicate this to GCC by using this macro to modify
725 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
726 the classes which should not be used by GCC. Also define the macro
727 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
728 letter for a class that shouldn't be used.
730 (However, if this class is not included in `GENERAL_REGS' and all
731 of the insn patterns whose constraints permit this class are
732 controlled by target switches, then GCC will automatically avoid
733 using these registers when the target switches are opposed to
736 #define CONDITIONAL_REGISTER_USAGE \
739 if (!TARGET_HARD_FLOAT) \
743 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
744 fixed_regs[regno] = call_used_regs[regno] = 1; \
745 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
746 fixed_regs[regno] = call_used_regs[regno] = 1; \
748 else if (! ISA_HAS_8CC) \
752 /* We only have a single condition code register. We \
753 implement this by hiding all the condition code registers, \
754 and generating RTL that refers directly to ST_REG_FIRST. */ \
755 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
756 fixed_regs[regno] = call_used_regs[regno] = 1; \
758 /* In mips16 mode, we permit the $t temporary registers to be used \
759 for reload. We prohibit the unused $s registers, since they \
760 are caller saved, and saving them via a mips16 register would \
761 probably waste more time than just reloading the value. */ \
764 fixed_regs[18] = call_used_regs[18] = 1; \
765 fixed_regs[19] = call_used_regs[19] = 1; \
766 fixed_regs[20] = call_used_regs[20] = 1; \
767 fixed_regs[21] = call_used_regs[21] = 1; \
768 fixed_regs[22] = call_used_regs[22] = 1; \
769 fixed_regs[23] = call_used_regs[23] = 1; \
770 fixed_regs[26] = call_used_regs[26] = 1; \
771 fixed_regs[27] = call_used_regs[27] = 1; \
772 fixed_regs[30] = call_used_regs[30] = 1; \
774 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
778 /* This is meant to be redefined in the host dependent files. */
779 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
781 /* Show we can debug even without a frame pointer. */
782 #define CAN_DEBUG_WITHOUT_FP
784 /* Complain about missing specs and predefines that should be defined in each
785 of the target tm files to override the defaults. This is mostly a place-
786 holder until I can get each of the files updated [mm]. */
788 #if defined(OSF_OS) \
789 || defined(DECSTATION) \
790 || defined(SGI_TARGET) \
791 || defined(MIPS_NEWS) \
792 || defined(MIPS_SYSV) \
793 || defined(MIPS_SVR4) \
794 || defined(MIPS_BSD43)
796 #ifndef CPP_PREDEFINES
797 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
801 #error "Define LIB_SPEC in the appropriate tm.h file"
804 #ifndef STARTFILE_SPEC
805 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
809 #error "Define MACHINE_TYPE in the appropriate tm.h file"
813 /* Tell collect what flags to pass to nm. */
815 #define NM_FLAGS "-Bn"
819 /* Names to predefine in the preprocessor for this target machine. */
821 #ifndef CPP_PREDEFINES
822 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
823 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
824 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
827 /* Assembler specs. */
829 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
832 #define MIPS_AS_ASM_SPEC "\
833 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
834 %{pipe: %e-pipe is not supported} \
835 %{K} %(subtarget_mips_as_asm_spec)"
837 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
838 rather than gas. It may be overridden by subtargets. */
840 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
841 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
844 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
847 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
852 #ifndef MIPS_ABI_DEFAULT
853 #define MIPS_ABI_DEFAULT ABI_32
856 #ifndef ABI_GAS_ASM_SPEC
857 #define ABI_GAS_ASM_SPEC ""
860 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
861 GAS_ASM_SPEC as the default, depending upon the value of
864 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
867 #define TARGET_ASM_SPEC "\
868 %{mmips-as: %(mips_as_asm_spec)} \
869 %{!mmips-as: %(gas_asm_spec)}"
873 #define TARGET_ASM_SPEC "\
874 %{!mgas: %(mips_as_asm_spec)} \
875 %{mgas: %(gas_asm_spec)}"
879 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
880 to the assembler. It may be overridden by subtargets. */
881 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
882 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
884 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
887 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
888 the assembler. It may be overridden by subtargets. */
889 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
890 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
891 %{g} %{g0} %{g1} %{g2} %{g3} \
892 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
893 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
894 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
895 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
898 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
899 overridden by subtargets. */
901 #ifndef SUBTARGET_ASM_SPEC
902 #define SUBTARGET_ASM_SPEC ""
905 /* ASM_SPEC is the set of arguments to pass to the assembler. */
909 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
910 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
911 %(subtarget_asm_optimizing_spec) \
912 %(subtarget_asm_debugging_spec) \
914 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
916 %(subtarget_asm_spec)"
918 /* Specify to run a post-processor, mips-tfile after the assembler
919 has run to stuff the mips debug information into the object file.
920 This is needed because the $#!%^ MIPS assembler provides no way
921 of specifying such information in the assembly file. If we are
922 cross compiling, disable mips-tfile unless the user specifies
925 #ifndef ASM_FINAL_SPEC
926 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
928 #define ASM_FINAL_SPEC "\
929 %{mmips-as: %{!mno-mips-tfile: \
930 \n mips-tfile %{v*: -v} \
932 %{!K: %{save-temps: -I %b.o~}} \
933 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
934 %{.s:%i} %{!.s:%g.s}}}"
938 #define ASM_FINAL_SPEC "\
939 %{!mgas: %{!mno-mips-tfile: \
940 \n mips-tfile %{v*: -v} \
942 %{!K: %{save-temps: -I %b.o~}} \
943 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
944 %{.s:%i} %{!.s:%g.s}}}"
947 #endif /* ASM_FINAL_SPEC */
949 /* Redefinition of libraries used. Mips doesn't support normal
950 UNIX style profiling via calling _mcount. It does offer
951 profiling that samples the PC, so do what we can... */
954 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
957 /* Extra switches sometimes passed to the linker. */
958 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
959 will interpret it as a -b option. */
964 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
965 %{bestGnum} %{shared} %{non_shared}"
966 #endif /* LINK_SPEC defined */
969 /* Specs for the compiler proper */
971 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
972 overridden by subtargets. */
973 #ifndef SUBTARGET_CC1_SPEC
974 #define SUBTARGET_CC1_SPEC ""
977 /* Deal with historic options. */
979 #define CC1_CPU_SPEC "\
981 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
982 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
983 %{m4650:-march=r4650 -mmad -msingle-float \
984 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
987 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
988 /* Note, we will need to adjust the following if we ever find a MIPS variant
989 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
990 that show up in this case. */
994 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
995 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
996 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
997 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
998 %{mips32:-mfp32 -mgp32} \
999 %{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1000 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
1001 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
1002 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
1003 %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
1004 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1005 %{pic-none: -mno-half-pic} \
1006 %{pic-lib: -mhalf-pic} \
1007 %{pic-extern: -mhalf-pic} \
1008 %{pic-calls: -mhalf-pic} \
1010 %(subtarget_cc1_spec) \
1014 /* Preprocessor specs. */
1016 /* Rules for SIZE_TYPE and PTRDIFF_TYPE are:
1018 both gp64 and long64 (not the options, but the corresponding flags,
1019 so defaults came into play) are required in order to have `long' in
1020 SIZE_TYPE and PTRDIFF_TYPE.
1022 on eabi, -mips1, -mips2 and -mips32 disable gp64, whereas mips3,
1023 -mips4, -mips5 and -mips64 enable it.
1025 on other ABIs, -mips* options do not affect gp32/64, but the
1026 default ISA affects the default gp size.
1028 -mgp32 disables gp64, whereas -mgp64 enables it.
1030 on eabi, gp64 implies long64.
1032 -mlong64, and -mabi=64 are the only other ways to enable long64.
1036 #if MIPS_ISA_DEFAULT != 3 && MIPS_ISA_DEFAULT != 4 && MIPS_ISA_DEFAULT != 5 && MIPS_ISA_DEFAULT != 64
1038 /* 32-bit cases first. */
1040 #if MIPS_ABI_DEFAULT == ABI_EABI
1041 #define LONG_MAX_SPEC "\
1042 %{mlong64:-D__LONG_MAX__=9223372036854775807L}\
1044 %{mabi=eabi|!mabi=*:\
1045 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1046 %{mips3|mips4|mips5|mips64|mgp64: \
1047 -D__LONG_MAX__=9223372036854775807L}}}}}}}} \
1049 #else /* ABI_DEFAULT != ABI_EABI */
1050 #define LONG_MAX_SPEC "\
1051 %{mlong64:-D__LONG_MAX__=9223372036854775807L}\
1054 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1055 %{mips3|mips4|mips5|mips64|mgp64: \
1056 -D__LONG_MAX__=9223372036854775807L}}}}}}}} \
1062 /* 64-bit default ISA. */
1063 #if MIPS_ABI_DEFAULT == ABI_EABI
1064 #define LONG_MAX_SPEC "\
1065 %{mlong64:-D__LONG_MAX__=9223372036854775807L}\
1067 %{mabi=eabi|!mabi=*:\
1068 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1069 -D__LONG_MAX__=9223372036854775807L}}}}}}}\
1071 #else /* ABI_DEFAULT != ABI_EABI */
1072 #define LONG_MAX_SPEC "\
1073 %{mlong64:-D__LONG_MAX__=9223372036854775807L}\
1076 %{!mips1:%{!mips2:%{!mips32:%{!mgp32:%{!mlong32: \
1077 -D__LONG_MAX__=9223372036854775807L}}}}}}}\
1083 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1084 overridden by subtargets. */
1085 #ifndef SUBTARGET_CPP_SPEC
1086 #define SUBTARGET_CPP_SPEC ""
1089 /* Define appropriate macros for fpr register size. */
1090 #ifndef CPP_FPR_SPEC
1091 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
1092 #define CPP_FPR_SPEC "-D__mips_fpr=64"
1094 #define CPP_FPR_SPEC "-D__mips_fpr=32"
1098 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
1099 of the source file extension. */
1100 #undef CPLUSPLUS_CPP_SPEC
1101 #define CPLUSPLUS_CPP_SPEC "\
1102 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
1105 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1109 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1110 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1111 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1112 %(subtarget_cpp_size_spec) \
1113 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1114 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1115 %{mips32:-U__mips -D__mips=32} \
1116 %{mips64:-U__mips -D__mips=64 -D__mips64} \
1117 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1118 %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
1119 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1120 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1121 %{msoft-float:-D__mips_soft_float} \
1122 %{mabi=eabi:-D__mips_eabi} \
1123 %{mips16:%{!mno-mips16:-D__mips16}} \
1124 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1125 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1127 %(subtarget_cpp_spec) "
1130 /* This macro defines names of additional specifications to put in the specs
1131 that can be used in various specifications like CC1_SPEC. Its definition
1132 is an initializer with a subgrouping for each command option.
1134 Each subgrouping contains a string constant, that defines the
1135 specification name, and a string constant that used by the GNU CC driver
1138 Do not define this macro if it does not need to do anything. */
1140 #define EXTRA_SPECS \
1141 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1142 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
1143 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1144 { "long_max_spec", LONG_MAX_SPEC }, \
1145 { "cpp_fpr_spec", CPP_FPR_SPEC }, \
1146 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1147 { "gas_asm_spec", GAS_ASM_SPEC }, \
1148 { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \
1149 { "target_asm_spec", TARGET_ASM_SPEC }, \
1150 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1151 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1152 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1153 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1154 { "endian_spec", ENDIAN_SPEC }, \
1155 SUBTARGET_EXTRA_SPECS
1157 #ifndef SUBTARGET_EXTRA_SPECS
1158 #define SUBTARGET_EXTRA_SPECS
1161 /* If defined, this macro is an additional prefix to try after
1162 `STANDARD_EXEC_PREFIX'. */
1164 #ifndef MD_EXEC_PREFIX
1165 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1168 #ifndef MD_STARTFILE_PREFIX
1169 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1173 /* Print subsidiary information on the compiler version in use. */
1175 #define MIPS_VERSION "[AL 1.1, MM 40]"
1177 #ifndef MACHINE_TYPE
1178 #define MACHINE_TYPE "BSD Mips"
1181 #ifndef TARGET_VERSION_INTERNAL
1182 #define TARGET_VERSION_INTERNAL(STREAM) \
1183 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1186 #ifndef TARGET_VERSION
1187 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1191 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1192 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1193 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1195 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1196 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1199 /* By default, turn on GDB extensions. */
1200 #define DEFAULT_GDB_EXTENSIONS 1
1202 /* If we are passing smuggling stabs through the MIPS ECOFF object
1203 format, put a comment in front of the .stab<x> operation so
1204 that the MIPS assembler does not choke. The mips-tfile program
1205 will correctly put the stab into the object file. */
1207 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1208 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1209 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1211 /* Local compiler-generated symbols must have a prefix that the assembler
1212 understands. By default, this is $, although some targets (e.g.,
1213 NetBSD-ELF) need to override this. */
1215 #ifndef LOCAL_LABEL_PREFIX
1216 #define LOCAL_LABEL_PREFIX "$"
1219 /* By default on the mips, external symbols do not have an underscore
1220 prepended, but some targets (e.g., NetBSD) require this. */
1222 #ifndef USER_LABEL_PREFIX
1223 #define USER_LABEL_PREFIX ""
1226 /* Forward references to tags are allowed. */
1227 #define SDB_ALLOW_FORWARD_REFERENCES
1229 /* Unknown tags are also allowed. */
1230 #define SDB_ALLOW_UNKNOWN_REFERENCES
1232 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1233 since the length can run past this up to a continuation point. */
1234 #undef DBX_CONTIN_LENGTH
1235 #define DBX_CONTIN_LENGTH 1500
1237 /* How to renumber registers for dbx and gdb. */
1238 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1240 /* The mapping from gcc register number to DWARF 2 CFA column number.
1241 This mapping does not allow for tracking register 0, since SGI's broken
1242 dwarf reader thinks column 0 is used for the frame address, but since
1243 register 0 is fixed this is not a problem. */
1244 #define DWARF_FRAME_REGNUM(REG) \
1245 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1247 /* The DWARF 2 CFA column which tracks the return address. */
1248 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1250 /* Before the prologue, RA lives in r31. */
1251 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1253 /* Describe how we implement __builtin_eh_return. */
1254 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1255 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1257 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1258 The default for this in 64-bit mode is 8, which causes problems with
1259 SFmode register saves. */
1260 #define DWARF_CIE_DATA_ALIGNMENT 4
1262 /* Overrides for the COFF debug format. */
1263 #define PUT_SDB_SCL(a) \
1265 extern FILE *asm_out_text_file; \
1266 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1269 #define PUT_SDB_INT_VAL(a) \
1271 extern FILE *asm_out_text_file; \
1272 fprintf (asm_out_text_file, "\t.val\t"); \
1273 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1274 fprintf (asm_out_text_file, ";"); \
1277 #define PUT_SDB_VAL(a) \
1279 extern FILE *asm_out_text_file; \
1280 fputs ("\t.val\t", asm_out_text_file); \
1281 output_addr_const (asm_out_text_file, (a)); \
1282 fputc (';', asm_out_text_file); \
1285 #define PUT_SDB_DEF(a) \
1287 extern FILE *asm_out_text_file; \
1288 fprintf (asm_out_text_file, "\t%s.def\t", \
1289 (TARGET_GAS) ? "" : "#"); \
1290 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1291 fputc (';', asm_out_text_file); \
1294 #define PUT_SDB_PLAIN_DEF(a) \
1296 extern FILE *asm_out_text_file; \
1297 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1298 (TARGET_GAS) ? "" : "#", (a)); \
1301 #define PUT_SDB_ENDEF \
1303 extern FILE *asm_out_text_file; \
1304 fprintf (asm_out_text_file, "\t.endef\n"); \
1307 #define PUT_SDB_TYPE(a) \
1309 extern FILE *asm_out_text_file; \
1310 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1313 #define PUT_SDB_SIZE(a) \
1315 extern FILE *asm_out_text_file; \
1316 fprintf (asm_out_text_file, "\t.size\t"); \
1317 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1318 fprintf (asm_out_text_file, ";"); \
1321 #define PUT_SDB_DIM(a) \
1323 extern FILE *asm_out_text_file; \
1324 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1327 #ifndef PUT_SDB_START_DIM
1328 #define PUT_SDB_START_DIM \
1330 extern FILE *asm_out_text_file; \
1331 fprintf (asm_out_text_file, "\t.dim\t"); \
1335 #ifndef PUT_SDB_NEXT_DIM
1336 #define PUT_SDB_NEXT_DIM(a) \
1338 extern FILE *asm_out_text_file; \
1339 fprintf (asm_out_text_file, "%d,", a); \
1343 #ifndef PUT_SDB_LAST_DIM
1344 #define PUT_SDB_LAST_DIM(a) \
1346 extern FILE *asm_out_text_file; \
1347 fprintf (asm_out_text_file, "%d;", a); \
1351 #define PUT_SDB_TAG(a) \
1353 extern FILE *asm_out_text_file; \
1354 fprintf (asm_out_text_file, "\t.tag\t"); \
1355 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1356 fputc (';', asm_out_text_file); \
1359 /* For block start and end, we create labels, so that
1360 later we can figure out where the correct offset is.
1361 The normal .ent/.end serve well enough for functions,
1362 so those are just commented out. */
1364 #define PUT_SDB_BLOCK_START(LINE) \
1366 extern FILE *asm_out_text_file; \
1367 fprintf (asm_out_text_file, \
1368 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1369 LOCAL_LABEL_PREFIX, \
1371 (TARGET_GAS) ? "" : "#", \
1372 LOCAL_LABEL_PREFIX, \
1375 sdb_label_count++; \
1378 #define PUT_SDB_BLOCK_END(LINE) \
1380 extern FILE *asm_out_text_file; \
1381 fprintf (asm_out_text_file, \
1382 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1383 LOCAL_LABEL_PREFIX, \
1385 (TARGET_GAS) ? "" : "#", \
1386 LOCAL_LABEL_PREFIX, \
1389 sdb_label_count++; \
1392 #define PUT_SDB_FUNCTION_START(LINE)
1394 #define PUT_SDB_FUNCTION_END(LINE) \
1396 extern FILE *asm_out_text_file; \
1397 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1400 #define PUT_SDB_EPILOGUE_END(NAME)
1402 #define PUT_SDB_SRC_FILE(FILENAME) \
1404 extern FILE *asm_out_text_file; \
1405 output_file_directive (asm_out_text_file, (FILENAME)); \
1408 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1409 sprintf ((BUFFER), ".%dfake", (NUMBER));
1411 /* Correct the offset of automatic variables and arguments. Note that
1412 the MIPS debug format wants all automatic variables and arguments
1413 to be in terms of the virtual frame pointer (stack pointer before
1414 any adjustment in the function), while the MIPS 3.0 linker wants
1415 the frame pointer to be the stack pointer after the initial
1418 #define DEBUGGER_AUTO_OFFSET(X) \
1419 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1420 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1421 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1423 /* Tell collect that the object format is ECOFF */
1424 #ifndef OBJECT_FORMAT_ROSE
1425 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1426 #define EXTENDED_COFF /* ECOFF, not normal coff */
1429 /* Target machine storage layout */
1431 /* Define this if most significant bit is lowest numbered
1432 in instructions that operate on numbered bit-fields.
1434 #define BITS_BIG_ENDIAN 0
1436 /* Define this if most significant byte of a word is the lowest numbered. */
1437 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1439 /* Define this if most significant word of a multiword number is the lowest. */
1440 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1442 /* Define this to set the endianness to use in libgcc2.c, which can
1443 not depend on target_flags. */
1444 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1445 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1447 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1450 #define MAX_BITS_PER_WORD 64
1452 /* Width of a word, in units (bytes). */
1453 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1454 #define MIN_UNITS_PER_WORD 4
1456 /* For MIPS, width of a floating point register. */
1457 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1459 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1460 the next available register. */
1461 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1463 /* The largest size of value that can be held in floating-point registers. */
1464 #define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1466 /* The number of bytes in a double. */
1467 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1469 /* A C expression for the size in bits of the type `int' on the
1470 target machine. If you don't define this, the default is one
1472 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1474 /* Tell the preprocessor the maximum size of wchar_t. */
1475 #ifndef MAX_WCHAR_TYPE_SIZE
1476 #ifndef WCHAR_TYPE_SIZE
1477 #define MAX_WCHAR_TYPE_SIZE 64
1481 /* A C expression for the size in bits of the type `short' on the
1482 target machine. If you don't define this, the default is half a
1483 word. (If this would be less than one storage unit, it is
1484 rounded up to one unit.) */
1485 #define SHORT_TYPE_SIZE 16
1487 /* A C expression for the size in bits of the type `long' on the
1488 target machine. If you don't define this, the default is one
1490 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1491 #define MAX_LONG_TYPE_SIZE 64
1493 /* A C expression for the size in bits of the type `long long' on the
1494 target machine. If you don't define this, the default is two
1496 #define LONG_LONG_TYPE_SIZE 64
1498 /* A C expression for the size in bits of the type `float' on the
1499 target machine. If you don't define this, the default is one
1501 #define FLOAT_TYPE_SIZE 32
1503 /* A C expression for the size in bits of the type `double' on the
1504 target machine. If you don't define this, the default is two
1506 #define DOUBLE_TYPE_SIZE 64
1508 /* A C expression for the size in bits of the type `long double' on
1509 the target machine. If you don't define this, the default is two
1511 #define LONG_DOUBLE_TYPE_SIZE 64
1513 /* Width in bits of a pointer.
1514 See also the macro `Pmode' defined below. */
1515 #ifndef POINTER_SIZE
1516 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1519 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1520 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1522 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1523 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1524 || mips_abi == ABI_64 \
1525 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1527 /* Allocation boundary (in *bits*) for the code of a function. */
1528 #define FUNCTION_BOUNDARY 32
1530 /* Alignment of field after `int : 0' in a structure. */
1531 #define EMPTY_FIELD_BOUNDARY 32
1533 /* Every structure's size must be a multiple of this. */
1534 /* 8 is observed right on a DECstation and on riscos 4.02. */
1535 #define STRUCTURE_SIZE_BOUNDARY 8
1537 /* There is no point aligning anything to a rounder boundary than this. */
1538 #define BIGGEST_ALIGNMENT 64
1540 /* Set this nonzero if move instructions will actually fail to work
1541 when given unaligned data. */
1542 #define STRICT_ALIGNMENT 1
1544 /* Define this if you wish to imitate the way many other C compilers
1545 handle alignment of bitfields and the structures that contain
1548 The behavior is that the type written for a bitfield (`int',
1549 `short', or other integer type) imposes an alignment for the
1550 entire structure, as if the structure really did contain an
1551 ordinary field of that type. In addition, the bitfield is placed
1552 within the structure so that it would fit within such a field,
1553 not crossing a boundary for it.
1555 Thus, on most machines, a bitfield whose type is written as `int'
1556 would not cross a four-byte boundary, and would force four-byte
1557 alignment for the whole structure. (The alignment used may not
1558 be four bytes; it is controlled by the other alignment
1561 If the macro is defined, its definition should be a C expression;
1562 a nonzero value for the expression enables this behavior. */
1564 #define PCC_BITFIELD_TYPE_MATTERS 1
1566 /* If defined, a C expression to compute the alignment given to a
1567 constant that is being placed in memory. CONSTANT is the constant
1568 and ALIGN is the alignment that the object would ordinarily have.
1569 The value of this macro is used instead of that alignment to align
1572 If this macro is not defined, then ALIGN is used.
1574 The typical use of this macro is to increase alignment for string
1575 constants to be word aligned so that `strcpy' calls that copy
1576 constants can be done inline. */
1578 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1579 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1580 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1582 /* If defined, a C expression to compute the alignment for a static
1583 variable. TYPE is the data type, and ALIGN is the alignment that
1584 the object would ordinarily have. The value of this macro is used
1585 instead of that alignment to align the object.
1587 If this macro is not defined, then ALIGN is used.
1589 One use of this macro is to increase alignment of medium-size
1590 data to make it all fit in fewer cache lines. Another is to
1591 cause character arrays to be word-aligned so that `strcpy' calls
1592 that copy constants to character arrays can be done inline. */
1594 #undef DATA_ALIGNMENT
1595 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1596 ((((ALIGN) < BITS_PER_WORD) \
1597 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1598 || TREE_CODE (TYPE) == UNION_TYPE \
1599 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1602 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1604 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1605 || mips_abi == ABI_MEABI \
1606 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1608 /* Define this macro if an argument declared as `char' or `short' in a
1609 prototype should actually be passed as an `int'. In addition to
1610 avoiding errors in certain cases of mismatch, it also makes for
1611 better code on certain machines. */
1613 #define PROMOTE_PROTOTYPES 1
1615 /* Define if operations between registers always perform the operation
1616 on the full register even if a narrower mode is specified. */
1617 #define WORD_REGISTER_OPERATIONS
1619 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1620 will either zero-extend or sign-extend. The value of this macro should
1621 be the code that says which one of the two operations is implicitly
1624 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1625 moves. All other referces are zero extended. */
1626 #define LOAD_EXTEND_OP(MODE) \
1627 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1628 ? SIGN_EXTEND : ZERO_EXTEND)
1630 /* Define this macro if it is advisable to hold scalars in registers
1631 in a wider mode than that declared by the program. In such cases,
1632 the value is constrained to be within the bounds of the declared
1633 type, but kept valid in the wider mode. The signedness of the
1634 extension may differ from that of the type.
1636 We promote any value smaller than SImode up to SImode. We don't
1637 want to promote to DImode when in 64 bit mode, because that would
1638 prevent us from using the faster SImode multiply and divide
1641 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1642 if (GET_MODE_CLASS (MODE) == MODE_INT \
1643 && GET_MODE_SIZE (MODE) < 4) \
1646 /* Define this if function arguments should also be promoted using the above
1649 #define PROMOTE_FUNCTION_ARGS
1651 /* Likewise, if the function return value is promoted. */
1653 #define PROMOTE_FUNCTION_RETURN
1655 /* Standard register usage. */
1657 /* Number of actual hardware registers.
1658 The hardware registers are assigned numbers for the compiler
1659 from 0 to just below FIRST_PSEUDO_REGISTER.
1660 All registers that the compiler knows about must be given numbers,
1661 even those that are not normally considered general registers.
1663 On the Mips, we have 32 integer registers, 32 floating point
1664 registers, 8 condition code registers, and the special registers
1665 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1666 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1667 processor.) The 8 condition code registers are only used if
1668 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1669 represents a 64 bit value stored as two 32 bit values in the hi and
1670 lo registers; this is the result of the mult instruction. rap is a
1671 pointer to the stack where the return address reg ($31) was stored.
1672 This is needed for C++ exception handling. */
1674 #define FIRST_PSEUDO_REGISTER 176
1676 /* 1 for registers that have pervasive standard uses
1677 and are not available for the register allocator.
1679 On the MIPS, see conventions, page D-2 */
1681 /* Regarding coprocessor registers: without evidence to the contrary,
1682 it's best to assume that each coprocessor register has a unique
1683 use. This can be overridden, in, e.g., override_options() or
1684 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1685 for a particular target. */
1687 #define FIXED_REGISTERS \
1689 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1690 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1691 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1692 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1693 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
1694 /* COP0 registers */ \
1695 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1696 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1697 /* COP2 registers */ \
1698 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1699 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1700 /* COP3 registers */ \
1701 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1702 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1706 /* 1 for registers not available across function calls.
1707 These must include the FIXED_REGISTERS and also any
1708 registers that can be used without being saved.
1709 The latter must include the registers where values are returned
1710 and the register where structure-value addresses are passed.
1711 Aside from that, you can include as many other registers as you like. */
1713 #define CALL_USED_REGISTERS \
1715 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1716 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1717 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1718 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1719 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1720 /* COP0 registers */ \
1721 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1722 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1723 /* COP2 registers */ \
1724 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1725 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1726 /* COP3 registers */ \
1727 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1728 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1731 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1732 problem which makes CALL_USED_REGISTERS *always* include
1733 all the FIXED_REGISTERS. Until this problem has been
1734 resolved this macro can be used to overcome this situation.
1735 In particular, block_propagate() requires this list
1736 be acurate, or we can remove registers which should be live.
1737 This macro is used in regs_invalidated_by_call. */
1740 #define CALL_REALLY_USED_REGISTERS \
1741 { /* General registers. */ \
1742 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1743 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1744 /* Floating-point registers. */ \
1745 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1746 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1748 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1749 /* COP0 registers */ \
1750 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1751 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1752 /* COP2 registers */ \
1753 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1754 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1755 /* COP3 registers */ \
1756 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1757 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1760 /* Internal macros to classify a register number as to whether it's a
1761 general purpose register, a floating point register, a
1762 multiply/divide register, or a status register. */
1764 #define GP_REG_FIRST 0
1765 #define GP_REG_LAST 31
1766 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1767 #define GP_DBX_FIRST 0
1769 #define FP_REG_FIRST 32
1770 #define FP_REG_LAST 63
1771 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1772 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1774 #define MD_REG_FIRST 64
1775 #define MD_REG_LAST 66
1776 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1778 #define ST_REG_FIRST 67
1779 #define ST_REG_LAST 74
1780 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1782 #define RAP_REG_NUM 75
1784 #define COP0_REG_FIRST 80
1785 #define COP0_REG_LAST 111
1786 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1788 #define COP2_REG_FIRST 112
1789 #define COP2_REG_LAST 143
1790 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1792 #define COP3_REG_FIRST 144
1793 #define COP3_REG_LAST 175
1794 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1795 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1796 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1798 #define AT_REGNUM (GP_REG_FIRST + 1)
1799 #define HI_REGNUM (MD_REG_FIRST + 0)
1800 #define LO_REGNUM (MD_REG_FIRST + 1)
1801 #define HILO_REGNUM (MD_REG_FIRST + 2)
1803 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1804 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1805 should be used instead. */
1806 #define FPSW_REGNUM ST_REG_FIRST
1808 #define GP_REG_P(REGNO) \
1809 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1810 #define M16_REG_P(REGNO) \
1811 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1812 #define FP_REG_P(REGNO) \
1813 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1814 #define MD_REG_P(REGNO) \
1815 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1816 #define ST_REG_P(REGNO) \
1817 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1818 #define COP0_REG_P(REGNO) \
1819 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1820 #define COP2_REG_P(REGNO) \
1821 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1822 #define COP3_REG_P(REGNO) \
1823 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1824 #define ALL_COP_REG_P(REGNO) \
1825 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1827 /* Return coprocessor number from register number. */
1829 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1830 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1831 : COP3_REG_P (REGNO) ? '3' : '?')
1833 /* Return number of consecutive hard regs needed starting at reg REGNO
1834 to hold something of mode MODE.
1835 This is ordinarily the length in words of a value of mode MODE
1836 but can be less for certain modes in special long registers.
1838 On the MIPS, all general registers are one word long. Except on
1839 the R4000 with the FR bit set, the floating point uses register
1840 pairs, with the second register not being allocable. */
1842 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1844 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1845 MODE. In 32 bit mode, require that DImode and DFmode be in even
1846 registers. For DImode, this makes some of the insns easier to
1847 write, since you don't have to worry about a DImode value in
1848 registers 3 & 4, producing a result in 4 & 5.
1850 To make the code simpler HARD_REGNO_MODE_OK now just references an
1851 array built in override_options. Because machmodes.h is not yet
1852 included before this file is processed, the MODE bound can't be
1855 extern char mips_hard_regno_mode_ok
[][FIRST_PSEUDO_REGISTER
];
1857 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1858 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1860 /* Value is 1 if it is a good idea to tie two pseudo registers
1861 when one has mode MODE1 and one has mode MODE2.
1862 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1863 for any hard reg, then this must be 0 for correct output. */
1864 #define MODES_TIEABLE_P(MODE1, MODE2) \
1865 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1866 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1867 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1868 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1870 /* MIPS pc is not overloaded on a register. */
1871 /* #define PC_REGNUM xx */
1873 /* Register to use for pushing function arguments. */
1874 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1876 /* Offset from the stack pointer to the first available location. Use
1877 the default value zero. */
1878 /* #define STACK_POINTER_OFFSET 0 */
1880 /* Base register for access to local variables of the function. We
1881 pretend that the frame pointer is $1, and then eliminate it to
1882 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1883 a fixed register, and will not be used for anything else. */
1884 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1886 /* Temporary scratch register for use by the assembler. */
1887 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1889 /* $30 is not available on the mips16, so we use $17 as the frame
1891 #define HARD_FRAME_POINTER_REGNUM \
1892 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1894 /* Value should be nonzero if functions must have frame pointers.
1895 Zero means the frame pointer need not be set up (and parms
1896 may be accessed via the stack pointer) in functions that seem suitable.
1897 This is computed in `reload', in reload1.c. */
1898 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1900 /* Base register for access to arguments of the function. */
1901 #define ARG_POINTER_REGNUM GP_REG_FIRST
1903 /* Fake register that holds the address on the stack of the
1904 current function's return address. */
1905 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1907 /* Register in which static-chain is passed to a function. */
1908 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1910 /* If the structure value address is passed in a register, then
1911 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1912 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1914 /* If the structure value address is not passed in a register, define
1915 `STRUCT_VALUE' as an expression returning an RTX for the place
1916 where the address is passed. If it returns 0, the address is
1917 passed as an "invisible" first argument. */
1918 #define STRUCT_VALUE 0
1920 /* Mips registers used in prologue/epilogue code when the stack frame
1921 is larger than 32K bytes. These registers must come from the
1922 scratch register set, and not used for passing and returning
1923 arguments and any other information used in the calling sequence
1924 (such as pic). Must start at 12, since t0/t3 are parameter passing
1925 registers in the 64 bit ABI. */
1927 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1928 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1930 /* Define this macro if it is as good or better to call a constant
1931 function address than to call an address kept in a register. */
1932 #define NO_FUNCTION_CSE 1
1934 /* Define this macro if it is as good or better for a function to
1935 call itself with an explicit address than to call an address
1936 kept in a register. */
1937 #define NO_RECURSIVE_FUNCTION_CSE 1
1939 /* The register number of the register used to address a table of
1940 static data addresses in memory. In some cases this register is
1941 defined by a processor's "application binary interface" (ABI).
1942 When this macro is defined, RTL is generated for this register
1943 once, as with the stack pointer and frame pointer registers. If
1944 this macro is not defined, it is up to the machine-dependent
1945 files to allocate such a register (if necessary). */
1946 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1948 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1950 /* Define the classes of registers for register constraints in the
1951 machine description. Also define ranges of constants.
1953 One of the classes must always be named ALL_REGS and include all hard regs.
1954 If there is more than one class, another class must be named NO_REGS
1955 and contain no registers.
1957 The name GENERAL_REGS must be the name of a class (or an alias for
1958 another name such as ALL_REGS). This is the class of registers
1959 that is allowed by "g" or "r" in a register constraint.
1960 Also, registers outside this class are allocated only when
1961 instructions express preferences for them.
1963 The classes must be numbered in nondecreasing order; that is,
1964 a larger-numbered class must never be contained completely
1965 in a smaller-numbered class.
1967 For any two classes, it is very desirable that there be another
1968 class that represents their union. */
1972 NO_REGS
, /* no registers in set */
1973 M16_NA_REGS
, /* mips16 regs not used to pass args */
1974 M16_REGS
, /* mips16 directly accessible registers */
1975 T_REG
, /* mips16 T register ($24) */
1976 M16_T_REGS
, /* mips16 registers plus T register */
1977 GR_REGS
, /* integer registers */
1978 FP_REGS
, /* floating point registers */
1979 HI_REG
, /* hi register */
1980 LO_REG
, /* lo register */
1981 HILO_REG
, /* hilo register pair for 64 bit mode mult */
1982 MD_REGS
, /* multiply/divide registers (hi/lo) */
1983 COP0_REGS
, /* generic coprocessor classes */
1986 HI_AND_GR_REGS
, /* union classes */
1994 ALL_COP_AND_GR_REGS
,
1995 ST_REGS
, /* status registers (fp status) */
1996 ALL_REGS
, /* all registers */
1997 LIM_REG_CLASSES
/* max value + 1 */
2000 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2002 #define GENERAL_REGS GR_REGS
2004 /* An initializer containing the names of the register classes as C
2005 string constants. These names are used in writing some of the
2008 #define REG_CLASS_NAMES \
2021 /* coprocessor registers */ \
2027 "HILO_AND_GR_REGS", \
2029 "COP0_AND_GR_REGS", \
2030 "COP2_AND_GR_REGS", \
2031 "COP3_AND_GR_REGS", \
2033 "ALL_COP_AND_GR_REGS", \
2038 /* An initializer containing the contents of the register classes,
2039 as integers which are bit masks. The Nth integer specifies the
2040 contents of class N. The way the integer MASK is interpreted is
2041 that register R is in the class if `MASK & (1 << R)' is 1.
2043 When the machine has more than 32 registers, an integer does not
2044 suffice. Then the integers are replaced by sub-initializers,
2045 braced groupings containing several integers. Each
2046 sub-initializer must be suitable as an initializer for the type
2047 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2049 #define REG_CLASS_CONTENTS \
2051 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2052 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2053 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2054 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2055 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2056 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2057 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2058 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2059 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2060 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2061 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2062 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2063 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2064 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2065 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2066 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2067 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2068 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2069 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2070 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2071 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2072 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2073 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2074 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2075 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2079 /* A C expression whose value is a register class containing hard
2080 register REGNO. In general there is more that one such class;
2081 choose a class which is "minimal", meaning that no smaller class
2082 also contains the register. */
2084 extern const enum reg_class mips_regno_to_class
[];
2086 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2088 /* A macro whose definition is the name of the class to which a
2089 valid base register must belong. A base register is one used in
2090 an address which is the register value plus a displacement. */
2092 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2094 /* A macro whose definition is the name of the class to which a
2095 valid index register must belong. An index register is one used
2096 in an address where its value is either multiplied by a scale
2097 factor or added to another register (as well as added to a
2100 #define INDEX_REG_CLASS NO_REGS
2102 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2103 registers explicitly used in the rtl to be used as spill registers
2104 but prevents the compiler from extending the lifetime of these
2107 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2109 /* This macro is used later on in the file. */
2110 #define GR_REG_CLASS_P(CLASS) \
2111 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2112 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2114 /* This macro is also used later on in the file. */
2115 #define COP_REG_CLASS_P(CLASS) \
2116 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2118 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2119 is the default value (allocate the registers in numeric order). We
2120 define it just so that we can override it for the mips16 target in
2121 ORDER_REGS_FOR_LOCAL_ALLOC. */
2123 #define REG_ALLOC_ORDER \
2124 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2125 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2126 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2127 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2128 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2129 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2130 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2131 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2132 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2133 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2134 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2137 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2138 to be rearranged based on a particular function. On the mips16, we
2139 want to allocate $24 (T_REG) before other registers for
2140 instructions for which it is possible. */
2142 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2144 /* REGISTER AND CONSTANT CLASSES */
2146 /* Get reg_class from a letter such as appears in the machine
2149 DEFINED REGISTER CLASSES:
2151 'd' General (aka integer) registers
2152 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2153 'y' General registers (in both mips16 and non mips16 mode)
2154 'e' mips16 non argument registers (M16_NA_REGS)
2155 't' mips16 temporary register ($24)
2156 'f' Floating point registers
2159 'x' Multiply/divide registers
2161 'z' FP Status register
2165 'b' All registers */
2167 extern enum reg_class mips_char_to_class
[256];
2169 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2171 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2172 string can be used to stand for particular ranges of immediate
2173 operands. This macro defines what the ranges are. C is the
2174 letter, and VALUE is a constant value. Return 1 if VALUE is
2175 in the range specified by C. */
2179 `I' is used for the range of constants an arithmetic insn can
2180 actually contain (16 bits signed integers).
2182 `J' is used for the range which is just zero (ie, $r0).
2184 `K' is used for the range of constants a logical insn can actually
2185 contain (16 bit zero-extended integers).
2187 `L' is used for the range of constants that be loaded with lui
2188 (ie, the bottom 16 bits are zero).
2190 `M' is used for the range of constants that take two words to load
2191 (ie, not matched by `I', `K', and `L').
2193 `N' is used for negative 16 bit constants other than -65536.
2195 `O' is a 15 bit signed integer.
2197 `P' is used for positive 16 bit constants. */
2199 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2200 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2202 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2203 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2204 : (C) == 'J' ? ((VALUE) == 0) \
2205 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2206 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2207 && (((VALUE) & ~2147483647) == 0 \
2208 || ((VALUE) & ~2147483647) == ~2147483647)) \
2209 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2210 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2211 && (((VALUE) & 0x0000ffff) != 0 \
2212 || (((VALUE) & ~2147483647) != 0 \
2213 && ((VALUE) & ~2147483647) != ~2147483647))) \
2214 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2215 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2216 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2219 /* Similar, but for floating constants, and defining letters G and H.
2220 Here VALUE is the CONST_DOUBLE rtx itself. */
2224 'G' : Floating point 0 */
2226 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2228 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2230 /* Letters in the range `Q' through `U' may be defined in a
2231 machine-dependent fashion to stand for arbitrary operand types.
2232 The machine description macro `EXTRA_CONSTRAINT' is passed the
2233 operand as its first argument and the constraint letter as its
2236 `Q' is for mips16 GP relative constants
2237 `R' is for memory references which take 1 word for the instruction.
2238 `S' is for references to extern items which are PIC for OSF/rose.
2239 `T' is for memory addresses that can be used to load two words. */
2241 #define EXTRA_CONSTRAINT(OP,CODE) \
2242 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2243 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2244 && mips16_gp_offset_p (OP)) \
2245 : (GET_CODE (OP) != MEM) ? FALSE \
2246 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2247 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2248 && HALF_PIC_ADDRESS_P (OP)) \
2251 /* Given an rtx X being reloaded into a reg required to be
2252 in class CLASS, return the class of reg to actually use.
2253 In general this is just CLASS; but on some machines
2254 in some cases it is preferable to use a more restrictive class. */
2256 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2257 ((CLASS) != ALL_REGS \
2258 ? (! TARGET_MIPS16 \
2260 : ((CLASS) != GR_REGS \
2263 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2264 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2265 ? (TARGET_SOFT_FLOAT \
2266 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2268 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2269 || GET_MODE (X) == VOIDmode) \
2270 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2273 /* Certain machines have the property that some registers cannot be
2274 copied to some other registers without using memory. Define this
2275 macro on those machines to be a C expression that is non-zero if
2276 objects of mode MODE in registers of CLASS1 can only be copied to
2277 registers of class CLASS2 by storing a register of CLASS1 into
2278 memory and loading that memory location into a register of CLASS2.
2280 Do not define this macro if its value would always be zero. */
2282 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2283 ((!TARGET_DEBUG_H_MODE \
2284 && GET_MODE_CLASS (MODE) == MODE_INT \
2285 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2286 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2287 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2288 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2289 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2291 /* The HI and LO registers can only be reloaded via the general
2292 registers. Condition code registers can only be loaded to the
2293 general registers, and from the floating point registers. */
2295 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2296 mips_secondary_reload_class (CLASS, MODE, X, 1)
2297 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2298 mips_secondary_reload_class (CLASS, MODE, X, 0)
2300 /* Return the maximum number of consecutive registers
2301 needed to represent mode MODE in a register of class CLASS. */
2303 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2305 /* If defined, gives a class of registers that cannot be used as the
2306 operand of a SUBREG that changes the mode of the object illegally.
2307 When FP regs are larger than integer regs... Er, anyone remember what
2310 In little-endian mode, the hi-lo registers are numbered backwards,
2311 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
2312 word as intended. */
2314 #define CLASS_CANNOT_CHANGE_MODE \
2315 (TARGET_BIG_ENDIAN \
2316 ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS) \
2317 : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG))
2319 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2321 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2322 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2324 /* Stack layout; function entry, exit and calling. */
2326 /* Define this if pushing a word on the stack
2327 makes the stack pointer a smaller address. */
2328 #define STACK_GROWS_DOWNWARD
2330 /* Define this if the nominal address of the stack frame
2331 is at the high-address end of the local variables;
2332 that is, each additional local variable allocated
2333 goes at a more negative offset in the frame. */
2334 /* #define FRAME_GROWS_DOWNWARD */
2336 /* Offset within stack frame to start allocating local variables at.
2337 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2338 first local allocated. Otherwise, it is the offset to the BEGINNING
2339 of the first local allocated. */
2340 #define STARTING_FRAME_OFFSET \
2341 (current_function_outgoing_args_size \
2342 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2344 /* Offset from the stack pointer register to an item dynamically
2345 allocated on the stack, e.g., by `alloca'.
2347 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2348 length of the outgoing arguments. The default is correct for most
2349 machines. See `function.c' for details.
2351 The MIPS ABI states that functions which dynamically allocate the
2352 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2353 we are trying to create a second frame pointer to the function, so
2354 allocate some stack space to make it happy.
2356 However, the linker currently complains about linking any code that
2357 dynamically allocates stack space, and there seems to be a bug in
2358 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2361 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2362 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2363 ? 4*UNITS_PER_WORD \
2364 : current_function_outgoing_args_size)
2367 /* The return address for the current frame is in r31 is this is a leaf
2368 function. Otherwise, it is on the stack. It is at a variable offset
2369 from sp/fp/ap, so we define a fake hard register rap which is a
2370 poiner to the return address on the stack. This always gets eliminated
2371 during reload to be either the frame pointer or the stack pointer plus
2374 /* ??? This definition fails for leaf functions. There is currently no
2375 general solution for this problem. */
2377 /* ??? There appears to be no way to get the return address of any previous
2378 frame except by disassembling instructions in the prologue/epilogue.
2379 So currently we support only the current frame. */
2381 #define RETURN_ADDR_RTX(count, frame) \
2383 ? (leaf_function_p () \
2384 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
2385 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
2386 RETURN_ADDRESS_POINTER_REGNUM))) \
2389 /* Since the mips16 ISA mode is encoded in the least-significant bit
2390 of the address, mask it off return addresses for purposes of
2391 finding exception handling regions. */
2393 #define MASK_RETURN_ADDR GEN_INT (-2)
2395 /* Similarly, don't use the least-significant bit to tell pointers to
2396 code from vtable index. */
2398 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2400 /* Structure to be filled in by compute_frame_size with register
2401 save masks, and offsets for the current function. */
2403 struct mips_frame_info
2405 long total_size
; /* # bytes that the entire frame takes up */
2406 long var_size
; /* # bytes that variables take up */
2407 long args_size
; /* # bytes that outgoing arguments take up */
2408 long extra_size
; /* # bytes of extra gunk */
2409 int gp_reg_size
; /* # bytes needed to store gp regs */
2410 int fp_reg_size
; /* # bytes needed to store fp regs */
2411 long mask
; /* mask of saved gp registers */
2412 long fmask
; /* mask of saved fp registers */
2413 long gp_save_offset
; /* offset from vfp to store gp registers */
2414 long fp_save_offset
; /* offset from vfp to store fp registers */
2415 long gp_sp_offset
; /* offset from new sp to store gp registers */
2416 long fp_sp_offset
; /* offset from new sp to store fp registers */
2417 int initialized
; /* != 0 if frame size already calculated */
2418 int num_gp
; /* number of gp registers saved */
2419 int num_fp
; /* number of fp registers saved */
2420 long insns_len
; /* length of insns; mips16 only */
2423 extern struct mips_frame_info current_frame_info
;
2425 /* If defined, this macro specifies a table of register pairs used to
2426 eliminate unneeded registers that point into the stack frame. If
2427 it is not defined, the only elimination attempted by the compiler
2428 is to replace references to the frame pointer with references to
2431 The definition of this macro is a list of structure
2432 initializations, each of which specifies an original and
2433 replacement register.
2435 On some machines, the position of the argument pointer is not
2436 known until the compilation is completed. In such a case, a
2437 separate hard register must be used for the argument pointer.
2438 This register can be eliminated by replacing it with either the
2439 frame pointer or the argument pointer, depending on whether or not
2440 the frame pointer has been eliminated.
2442 In this case, you might specify:
2443 #define ELIMINABLE_REGS \
2444 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2445 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2446 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2448 Note that the elimination of the argument pointer with the stack
2449 pointer is specified first since that is the preferred elimination.
2451 The eliminations to $17 are only used on the mips16. See the
2452 definition of HARD_FRAME_POINTER_REGNUM. */
2454 #define ELIMINABLE_REGS \
2455 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2456 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2457 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2458 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2459 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2460 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2461 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2462 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2463 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2465 /* A C expression that returns non-zero if the compiler is allowed to
2466 try to replace register number FROM-REG with register number
2467 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2468 defined, and will usually be the constant 1, since most of the
2469 cases preventing register elimination are things that the compiler
2470 already knows about.
2472 When not in mips16 and mips64, we can always eliminate to the
2473 frame pointer. We can eliminate to the stack pointer unless
2474 a frame pointer is needed. In mips16 mode, we need a frame
2475 pointer for a large frame; otherwise, reload may be unable
2476 to compute the address of a local variable, since there is
2477 no way to add a large constant to the stack pointer
2478 without using a temporary register.
2480 In mips16, for some instructions (eg lwu), we can't eliminate the
2481 frame pointer for the stack pointer. These instructions are
2482 only generated in TARGET_64BIT mode.
2485 #define CAN_ELIMINATE(FROM, TO) \
2486 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
2487 && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
2488 || (TO) == HARD_FRAME_POINTER_REGNUM)) \
2489 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2490 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2491 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2492 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2493 && (! TARGET_MIPS16 \
2494 || compute_frame_size (get_frame_size ()) < 32768)))))
2496 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2497 specifies the initial difference between the specified pair of
2498 registers. This macro must be defined if `ELIMINABLE_REGS' is
2501 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2502 { compute_frame_size (get_frame_size ()); \
2503 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2504 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2505 (OFFSET) = - current_function_outgoing_args_size; \
2506 else if ((FROM) == FRAME_POINTER_REGNUM) \
2508 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2509 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2510 (OFFSET) = (current_frame_info.total_size \
2511 - current_function_outgoing_args_size \
2512 - ((mips_abi != ABI_32 \
2513 && mips_abi != ABI_O64 \
2514 && mips_abi != ABI_EABI) \
2515 ? current_function_pretend_args_size \
2517 else if ((FROM) == ARG_POINTER_REGNUM) \
2518 (OFFSET) = (current_frame_info.total_size \
2519 - ((mips_abi != ABI_32 \
2520 && mips_abi != ABI_O64 \
2521 && mips_abi != ABI_EABI) \
2522 ? current_function_pretend_args_size \
2524 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2525 so we must add 4 bytes to the offset to get the right value. */ \
2526 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2528 (OFFSET) = current_frame_info.gp_sp_offset \
2529 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2530 * (BYTES_BIG_ENDIAN != 0)); \
2531 if (TARGET_MIPS16 && (TO) != STACK_POINTER_REGNUM) \
2532 (OFFSET) -= current_function_outgoing_args_size; \
2538 /* If we generate an insn to push BYTES bytes,
2539 this says how many the stack pointer really advances by.
2540 On the VAX, sp@- in a byte insn really pushes a word. */
2542 /* #define PUSH_ROUNDING(BYTES) 0 */
2544 /* If defined, the maximum amount of space required for outgoing
2545 arguments will be computed and placed into the variable
2546 `current_function_outgoing_args_size'. No space will be pushed
2547 onto the stack for each call; instead, the function prologue
2548 should increase the stack frame size by this amount.
2550 It is not proper to define both `PUSH_ROUNDING' and
2551 `ACCUMULATE_OUTGOING_ARGS'. */
2552 #define ACCUMULATE_OUTGOING_ARGS 1
2554 /* Offset from the argument pointer register to the first argument's
2555 address. On some machines it may depend on the data type of the
2558 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2559 the first argument's address.
2561 On the MIPS, we must skip the first argument position if we are
2562 returning a structure or a union, to account for its address being
2563 passed in $4. However, at the current time, this produces a compiler
2564 that can't bootstrap, so comment it out for now. */
2567 #define FIRST_PARM_OFFSET(FNDECL) \
2569 && TREE_TYPE (FNDECL) != 0 \
2570 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2571 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2572 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2576 #define FIRST_PARM_OFFSET(FNDECL) 0
2579 /* When a parameter is passed in a register, stack space is still
2580 allocated for it. For the MIPS, stack space must be allocated, cf
2581 Asm Lang Prog Guide page 7-8.
2583 BEWARE that some space is also allocated for non existing arguments
2584 in register. In case an argument list is of form GF used registers
2585 are a0 (a2,a3), but we should push over a1... */
2587 #define REG_PARM_STACK_SPACE(FNDECL) \
2588 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2590 /* Define this if it is the responsibility of the caller to
2591 allocate the area reserved for arguments passed in registers.
2592 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2593 of this macro is to determine whether the space is included in
2594 `current_function_outgoing_args_size'. */
2595 #define OUTGOING_REG_PARM_STACK_SPACE
2597 /* Align stack frames on 64 bits (Double Word ). */
2598 #ifndef STACK_BOUNDARY
2599 #define STACK_BOUNDARY 64
2602 /* Make sure 4 words are always allocated on the stack. */
2604 #ifndef STACK_ARGS_ADJUST
2605 #define STACK_ARGS_ADJUST(SIZE) \
2607 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2608 SIZE.constant = 4 * UNITS_PER_WORD; \
2613 /* A C expression that should indicate the number of bytes of its
2614 own arguments that a function pops on returning, or 0
2615 if the function pops no arguments and the caller must therefore
2616 pop them all after the function returns.
2618 FUNDECL is the declaration node of the function (as a tree).
2620 FUNTYPE is a C variable whose value is a tree node that
2621 describes the function in question. Normally it is a node of
2622 type `FUNCTION_TYPE' that describes the data type of the function.
2623 From this it is possible to obtain the data types of the value
2624 and arguments (if known).
2626 When a call to a library function is being considered, FUNTYPE
2627 will contain an identifier node for the library function. Thus,
2628 if you need to distinguish among various library functions, you
2629 can do so by their names. Note that "library function" in this
2630 context means a function used to perform arithmetic, whose name
2631 is known specially in the compiler and was not mentioned in the
2632 C code being compiled.
2634 STACK-SIZE is the number of bytes of arguments passed on the
2635 stack. If a variable number of bytes is passed, it is zero, and
2636 argument popping will always be the responsibility of the
2637 calling function. */
2639 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2642 /* Symbolic macros for the registers used to return integer and floating
2645 #define GP_RETURN (GP_REG_FIRST + 2)
2646 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2648 /* Symbolic macros for the first/last argument registers. */
2650 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2651 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2652 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2653 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2655 #define MAX_ARGS_IN_REGISTERS 4
2657 /* Define how to find the value returned by a library function
2658 assuming the value has mode MODE. Because we define
2659 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2660 PROMOTE_MODE does. */
2662 #define LIBCALL_VALUE(MODE) \
2663 mips_function_value (NULL_TREE, NULL, (MODE))
2665 /* Define how to find the value returned by a function.
2666 VALTYPE is the data type of the value (as a tree).
2667 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2668 otherwise, FUNC is 0. */
2670 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2671 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2673 /* 1 if N is a possible register number for a function value.
2674 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2675 Currently, R2 and F0 are only implemented here (C has no complex type) */
2677 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2679 /* 1 if N is a possible register number for function argument passing.
2680 We have no FP argument registers when soft-float. When FP registers
2681 are 32 bits, we can't directly reference the odd numbered ones. */
2682 /* For o64 we should be checking the mode for SFmode as well. */
2684 #define FUNCTION_ARG_REGNO_P(N) \
2685 ((((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2686 || ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST \
2687 && (((N) % FP_INC) == 0 \
2688 && (! mips_abi == ABI_O64))) \
2691 /* A C expression which can inhibit the returning of certain function
2692 values in registers, based on the type of value. A nonzero value says
2693 to return the function value in memory, just as large structures are
2694 always returned. Here TYPE will be a C expression of type
2695 `tree', representing the data type of the value.
2697 Note that values of mode `BLKmode' must be explicitly
2698 handled by this macro. Also, the option `-fpcc-struct-return'
2699 takes effect regardless of this macro. On most systems, it is
2700 possible to leave the macro undefined; this causes a default
2701 definition to be used, whose value is the constant 1 for BLKmode
2702 values, and 0 otherwise.
2704 GCC normally converts 1 byte structures into chars, 2 byte
2705 structs into shorts, and 4 byte structs into ints, and returns
2706 them this way. Defining the following macro overrides this,
2707 to give us MIPS cc compatibility. */
2709 #define RETURN_IN_MEMORY(TYPE) \
2710 mips_return_in_memory (TYPE)
2712 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2713 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2717 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2720 /* Define a data type for recording info about an argument list
2721 during the scan of that argument list. This data type should
2722 hold all necessary information about the function itself
2723 and about the args processed so far, enough to enable macros
2724 such as FUNCTION_ARG to determine where the next arg should go.
2726 This structure has to cope with two different argument allocation
2727 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2728 first N words go in registers and the rest go on the stack. If I < N,
2729 the Ith word might go in Ith integer argument register or the
2730 Ith floating-point one. In some cases, it has to go in both (see
2731 function_arg). For these ABIs, we only need to remember the number
2732 of words passed so far.
2734 The EABI instead allocates the integer and floating-point arguments
2735 separately. The first N words of FP arguments go in FP registers,
2736 the rest go on the stack. Likewise, the first N words of the other
2737 arguments go in integer registers, and the rest go on the stack. We
2738 need to maintain three counts: the number of integer registers used,
2739 the number of floating-point registers used, and the number of words
2740 passed on the stack.
2742 We could keep separate information for the two ABIs (a word count for
2743 the standard ABIs, and three separate counts for the EABI). But it
2744 seems simpler to view the standard ABIs as forms of EABI that do not
2745 allocate floating-point registers.
2747 So for the standard ABIs, the first N words are allocated to integer
2748 registers, and function_arg decides on an argument-by-argument basis
2749 whether that argument should really go in an integer register, or in
2750 a floating-point one. */
2752 typedef struct mips_args
{
2753 /* Always true for varargs functions. Otherwise true if at least
2754 one argument has been passed in an integer register. */
2757 /* The number of arguments seen so far. */
2758 unsigned int arg_number
;
2760 /* For EABI, the number of integer registers used so far. For other
2761 ABIs, the number of words passed in registers (whether integer
2762 or floating-point). */
2763 unsigned int num_gprs
;
2765 /* For EABI, the number of floating-point registers used so far. */
2766 unsigned int num_fprs
;
2768 /* The number of words passed on the stack. */
2769 unsigned int stack_words
;
2771 /* On the mips16, we need to keep track of which floating point
2772 arguments were passed in general registers, but would have been
2773 passed in the FP regs if this were a 32 bit function, so that we
2774 can move them to the FP regs if we wind up calling a 32 bit
2775 function. We record this information in fp_code, encoded in base
2776 four. A zero digit means no floating point argument, a one digit
2777 means an SFmode argument, and a two digit means a DFmode argument,
2778 and a three digit is not used. The low order digit is the first
2779 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2780 an SFmode argument. ??? A more sophisticated approach will be
2781 needed if MIPS_ABI != ABI_32. */
2784 /* True if the function has a prototype. */
2787 /* When a structure does not take up a full register, the argument
2788 should sometimes be shifted left so that it occupies the high part
2789 of the register. These two fields describe an array of ashl
2790 patterns for doing this. See function_arg_advance, which creates
2791 the shift patterns, and function_arg, which returns them when given
2792 a VOIDmode argument. */
2793 unsigned int num_adjusts
;
2794 struct rtx_def
*adjust
[MAX_ARGS_IN_REGISTERS
];
2797 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2798 for a call to a function whose data type is FNTYPE.
2799 For a library call, FNTYPE is 0.
2803 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2804 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2806 /* Update the data in CUM to advance over an argument
2807 of mode MODE and data type TYPE.
2808 (TYPE is null for libcalls where that information may not be available.) */
2810 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2811 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2813 /* Determine where to put an argument to a function.
2814 Value is zero to push the argument on the stack,
2815 or a hard register in which to store the argument.
2817 MODE is the argument's machine mode.
2818 TYPE is the data type of the argument (as a tree).
2819 This is null for libcalls where that information may
2821 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2822 the preceding args and about the function being called.
2823 NAMED is nonzero if this argument is a named parameter
2824 (otherwise it is an extra parameter matching an ellipsis). */
2826 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2827 function_arg( &CUM, MODE, TYPE, NAMED)
2829 /* For an arg passed partly in registers and partly in memory,
2830 this is the number of registers used.
2831 For args passed entirely in registers or entirely in memory, zero. */
2833 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2834 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2836 /* If defined, a C expression that gives the alignment boundary, in
2837 bits, of an argument with the specified mode and type. If it is
2838 not defined, `PARM_BOUNDARY' is used for all arguments. */
2840 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2842 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2844 : TYPE_ALIGN(TYPE)) \
2845 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2847 : GET_MODE_ALIGNMENT(MODE)))
2849 /* True if using EABI and varargs can be passed in floating-point
2850 registers. Under these conditions, we need a more complex form
2851 of va_list, which tracks GPR, FPR and stack arguments separately. */
2852 #define EABI_FLOAT_VARARGS_P \
2853 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2856 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2858 #define MUST_SAVE_REGISTER(regno) \
2859 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2860 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2861 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2863 /* ALIGN FRAMES on double word boundaries */
2864 #ifndef MIPS_STACK_ALIGN
2865 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2869 /* Define the `__builtin_va_list' type for the ABI. */
2870 #define BUILD_VA_LIST_TYPE(VALIST) \
2871 (VALIST) = mips_build_va_list ()
2873 /* Implement `va_start' for varargs and stdarg. */
2874 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2875 mips_va_start (stdarg, valist, nextarg)
2877 /* Implement `va_arg'. */
2878 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2879 mips_va_arg (valist, type)
2881 /* Output assembler code to FILE to increment profiler label # LABELNO
2882 for profiling a function entry. */
2884 #define FUNCTION_PROFILER(FILE, LABELNO) \
2886 if (TARGET_MIPS16) \
2887 sorry ("mips16 function profiling"); \
2888 fprintf (FILE, "\t.set\tnoat\n"); \
2889 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2890 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2892 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2893 TARGET_64BIT ? "dsubu" : "subu", \
2894 reg_names[STACK_POINTER_REGNUM], \
2895 reg_names[STACK_POINTER_REGNUM], \
2896 Pmode == DImode ? 16 : 8); \
2897 fprintf (FILE, "\tjal\t_mcount\n"); \
2898 fprintf (FILE, "\t.set\tat\n"); \
2901 /* Define this macro if the code for function profiling should come
2902 before the function prologue. Normally, the profiling code comes
2905 /* #define PROFILE_BEFORE_PROLOGUE */
2907 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2908 the stack pointer does not matter. The value is tested only in
2909 functions that have frame pointers.
2910 No definition is equivalent to always zero. */
2912 #define EXIT_IGNORE_STACK 1
2915 /* A C statement to output, on the stream FILE, assembler code for a
2916 block of data that contains the constant parts of a trampoline.
2917 This code should not include a label--the label is taken care of
2920 #define TRAMPOLINE_TEMPLATE(STREAM) \
2922 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2923 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2924 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2925 if (Pmode == DImode) \
2927 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2928 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2932 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2933 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2935 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2936 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2937 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2938 if (Pmode == DImode) \
2940 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2941 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2945 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2946 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2950 /* A C expression for the size in bytes of the trampoline, as an
2953 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2955 /* Alignment required for trampolines, in bits. */
2957 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2959 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2960 program and data caches. */
2962 #ifndef CACHE_FLUSH_FUNC
2963 #define CACHE_FLUSH_FUNC "_flush_cache"
2966 /* A C statement to initialize the variable parts of a trampoline.
2967 ADDR is an RTX for the address of the trampoline; FNADDR is an
2968 RTX for the address of the nested function; STATIC_CHAIN is an
2969 RTX for the static chain value that should be passed to the
2970 function when it is called. */
2972 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2975 if (Pmode == DImode) \
2977 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2978 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2982 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2983 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2986 /* Flush both caches. We need to flush the data cache in case \
2987 the system has a write-back cache. */ \
2988 /* ??? Should check the return value for errors. */ \
2989 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2990 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2991 0, VOIDmode, 3, addr, Pmode, \
2992 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2993 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2996 /* Addressing modes, and classification of registers for them. */
2998 /* #define HAVE_POST_INCREMENT 0 */
2999 /* #define HAVE_POST_DECREMENT 0 */
3001 /* #define HAVE_PRE_DECREMENT 0 */
3002 /* #define HAVE_PRE_INCREMENT 0 */
3004 /* These assume that REGNO is a hard or pseudo reg number.
3005 They give nonzero only if REGNO is a hard reg of the suitable class
3006 or a pseudo reg currently allocated to a suitable hard reg.
3007 These definitions are NOT overridden anywhere. */
3009 #define BASE_REG_P(regno, mode) \
3011 ? (M16_REG_P (regno) \
3012 || (regno) == FRAME_POINTER_REGNUM \
3013 || (regno) == ARG_POINTER_REGNUM \
3014 || ((regno) == STACK_POINTER_REGNUM \
3015 && (GET_MODE_SIZE (mode) == 4 \
3016 || GET_MODE_SIZE (mode) == 8))) \
3019 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
3020 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3023 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3024 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3026 #define REGNO_OK_FOR_INDEX_P(regno) 0
3027 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3028 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3030 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3031 and check its validity for a certain class.
3032 We have two alternate definitions for each of them.
3033 The usual definition accepts all pseudo regs; the other rejects them all.
3034 The symbol REG_OK_STRICT causes the latter definition to be used.
3036 Most source files want to accept pseudo regs in the hope that
3037 they will get allocated to the class that the insn wants them to be in.
3038 Some source files that are used after register allocation
3039 need to be strict. */
3041 #ifndef REG_OK_STRICT
3042 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3043 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3045 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3046 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3049 #define REG_OK_FOR_INDEX_P(X) 0
3052 /* Maximum number of registers that can appear in a valid memory address. */
3054 #define MAX_REGS_PER_ADDRESS 1
3056 /* A C compound statement with a conditional `goto LABEL;' executed
3057 if X (an RTX) is a legitimate memory address on the target
3058 machine for a memory operand of mode MODE.
3060 It usually pays to define several simpler macros to serve as
3061 subroutines for this one. Otherwise it may be too complicated
3064 This macro must exist in two variants: a strict variant and a
3065 non-strict one. The strict variant is used in the reload pass.
3066 It must be defined so that any pseudo-register that has not been
3067 allocated a hard register is considered a memory reference. In
3068 contexts where some kind of register is required, a
3069 pseudo-register with no hard register must be rejected.
3071 The non-strict variant is used in other passes. It must be
3072 defined to accept all pseudo-registers in every context where
3073 some kind of register is required.
3075 Compiler source files that want to use the strict variant of
3076 this macro define the macro `REG_OK_STRICT'. You should use an
3077 `#ifdef REG_OK_STRICT' conditional to define the strict variant
3078 in that case and the non-strict variant otherwise.
3080 Typically among the subroutines used to define
3081 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
3082 acceptable registers for various purposes (one for base
3083 registers, one for index registers, and so on). Then only these
3084 subroutine macros need have two variants; the higher levels of
3085 macros may be the same whether strict or not.
3087 Normally, constant addresses which are the sum of a `symbol_ref'
3088 and an integer are stored inside a `const' RTX to mark them as
3089 constant. Therefore, there is no need to recognize such sums
3090 specifically as legitimate addresses. Normally you would simply
3091 recognize any `const' as legitimate.
3093 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
3094 constant sums that are not marked with `const'. It assumes
3095 that a naked `plus' indicates indexing. If so, then you *must*
3096 reject such naked constant sums as illegitimate addresses, so
3097 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
3099 On some machines, whether a symbolic address is legitimate
3100 depends on the section that the address refers to. On these
3101 machines, define the macro `ENCODE_SECTION_INFO' to store the
3102 information into the `symbol_ref', and then check for it here.
3103 When you see a `const', you will have to look inside it to find
3104 the `symbol_ref' in order to determine the section. */
3107 #define GO_PRINTF(x) fprintf(stderr, (x))
3108 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3109 #define GO_DEBUG_RTX(x) debug_rtx(x)
3112 #define GO_PRINTF(x)
3113 #define GO_PRINTF2(x,y)
3114 #define GO_DEBUG_RTX(x)
3117 #ifdef REG_OK_STRICT
3118 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3120 if (mips_legitimate_address_p (MODE, X, 1)) \
3124 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3126 if (mips_legitimate_address_p (MODE, X, 0)) \
3131 /* A C expression that is 1 if the RTX X is a constant which is a
3132 valid address. This is defined to be the same as `CONSTANT_P (X)',
3133 but rejecting CONST_DOUBLE. */
3134 /* When pic, we must reject addresses of the form symbol+large int.
3135 This is because an instruction `sw $4,s+70000' needs to be converted
3136 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3137 assembler would use $at as a temp to load in the large offset. In this
3138 case $at is already in use. We convert such problem addresses to
3139 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3140 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
3141 #define CONSTANT_ADDRESS_P(X) \
3142 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3143 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3144 || (GET_CODE (X) == CONST \
3145 && ! (flag_pic && pic_address_needs_scratch (X)) \
3146 && (mips_abi == ABI_32 \
3147 || mips_abi == ABI_O64 \
3148 || mips_abi == ABI_EABI))) \
3149 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
3151 /* Define this, so that when PIC, reload won't try to reload invalid
3152 addresses which require two reload registers. */
3154 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3156 /* Nonzero if the constant value X is a legitimate general operand.
3157 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3159 At present, GAS doesn't understand li.[sd], so don't allow it
3160 to be generated at present. Also, the MIPS assembler does not
3161 grok li.d Infinity. */
3163 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3164 Note that the Irix 6 assembler problem may already be fixed.
3165 Note also that the GET_CODE (X) == CONST test catches the mips16
3166 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3167 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3168 ABI_64 to work together, we'll need to fix this. */
3169 #define LEGITIMATE_CONSTANT_P(X) \
3170 ((GET_CODE (X) != CONST_DOUBLE \
3171 || mips_const_double_ok (X, GET_MODE (X))) \
3172 && ! (GET_CODE (X) == CONST \
3174 && (mips_abi == ABI_N32 \
3175 || mips_abi == ABI_64)) \
3176 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3178 /* A C compound statement that attempts to replace X with a valid
3179 memory address for an operand of mode MODE. WIN will be a C
3180 statement label elsewhere in the code; the macro definition may
3183 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3185 to avoid further processing if the address has become legitimate.
3187 X will always be the result of a call to `break_out_memory_refs',
3188 and OLDX will be the operand that was given to that function to
3191 The code generated by this macro should not alter the
3192 substructure of X. If it transforms X into a more legitimate
3193 form, it should assign X (which will always be a C variable) a
3196 It is not necessary for this macro to come up with a legitimate
3197 address. The compiler has standard ways of doing so in all
3198 cases. In fact, it is safe for this macro to do nothing. But
3199 often a machine-dependent strategy can generate better code.
3201 For the MIPS, transform:
3203 memory(X + <large int>)
3207 Y = <large int> & ~0x7fff;
3209 memory (Z + (<large int> & 0x7fff));
3211 This is for CSE to find several similar references, and only use one Z.
3213 When PIC, convert addresses of the form memory (symbol+large int) to
3214 memory (reg+large int). */
3217 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3219 register rtx xinsn = (X); \
3221 if (TARGET_DEBUG_B_MODE) \
3223 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3224 GO_DEBUG_RTX (xinsn); \
3227 if (mips_split_addresses && mips_check_split (X, MODE)) \
3229 /* ??? Is this ever executed? */ \
3230 X = gen_rtx_LO_SUM (Pmode, \
3231 copy_to_mode_reg (Pmode, \
3232 gen_rtx (HIGH, Pmode, X)), \
3237 if (GET_CODE (xinsn) == CONST \
3238 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3239 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3240 || (mips_abi != ABI_32 \
3241 && mips_abi != ABI_O64 \
3242 && mips_abi != ABI_EABI))) \
3244 rtx ptr_reg = gen_reg_rtx (Pmode); \
3245 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3247 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3249 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3250 if (SMALL_INT (constant)) \
3252 /* Otherwise we fall through so the code below will fix the \
3257 if (GET_CODE (xinsn) == PLUS) \
3259 register rtx xplus0 = XEXP (xinsn, 0); \
3260 register rtx xplus1 = XEXP (xinsn, 1); \
3261 register enum rtx_code code0 = GET_CODE (xplus0); \
3262 register enum rtx_code code1 = GET_CODE (xplus1); \
3264 if (code0 != REG && code1 == REG) \
3266 xplus0 = XEXP (xinsn, 1); \
3267 xplus1 = XEXP (xinsn, 0); \
3268 code0 = GET_CODE (xplus0); \
3269 code1 = GET_CODE (xplus1); \
3272 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3273 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3275 rtx int_reg = gen_reg_rtx (Pmode); \
3276 rtx ptr_reg = gen_reg_rtx (Pmode); \
3278 emit_move_insn (int_reg, \
3279 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3281 emit_insn (gen_rtx_SET (VOIDmode, \
3283 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3285 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3290 if (TARGET_DEBUG_B_MODE) \
3291 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3295 /* A C statement or compound statement with a conditional `goto
3296 LABEL;' executed if memory address X (an RTX) can have different
3297 meanings depending on the machine mode of the memory reference it
3300 Autoincrement and autodecrement addresses typically have
3301 mode-dependent effects because the amount of the increment or
3302 decrement is the size of the operand being addressed. Some
3303 machines have other mode-dependent addresses. Many RISC machines
3304 have no mode-dependent addresses.
3306 You may assume that ADDR is a valid address for the machine. */
3308 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3311 /* Define this macro if references to a symbol must be treated
3312 differently depending on something about the variable or
3313 function named by the symbol (such as what section it is in).
3315 The macro definition, if any, is executed immediately after the
3316 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3317 The value of the rtl will be a `mem' whose address is a
3320 The usual thing for this macro to do is to a flag in the
3321 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3322 name string in the `symbol_ref' (if one bit is not enough
3325 The best way to modify the name string is by adding text to the
3326 beginning, with suitable punctuation to prevent any ambiguity.
3327 Allocate the new name in `saveable_obstack'. You will have to
3328 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3329 and output the name accordingly.
3331 You can also check the information stored in the `symbol_ref' in
3332 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3333 `PRINT_OPERAND_ADDRESS'.
3335 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3338 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3339 symbols which are not in the .text section.
3341 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3342 constants which are put in the .text section. We also record the
3343 total length of all such strings; this total is used to decide
3344 whether we need to split the constant table, and need not be
3347 When not mips16 code nor embedded PIC, if a symbol is in a
3348 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3349 splitting the reference so that gas can generate a gp relative
3352 When TARGET_EMBEDDED_DATA is set, we assume that all const
3353 variables will be stored in ROM, which is too far from %gp to use
3354 %gprel addressing. Note that (1) we include "extern const"
3355 variables in this, which mips_select_section doesn't, and (2) we
3356 can't always tell if they're really const (they might be const C++
3357 objects with non-const constructors), so we err on the side of
3358 caution and won't use %gprel anyway (otherwise we'd have to defer
3359 this decision to the linker/loader). The handling of extern consts
3360 is why the DECL_INITIAL macros differ from mips_select_section.
3362 If you are changing this macro, you should look at
3363 mips_select_section and see if it needs a similar change. */
3365 #define ENCODE_SECTION_INFO(DECL, FIRST) \
3368 if (TARGET_MIPS16) \
3370 if ((FIRST) && TREE_CODE (DECL) == STRING_CST \
3371 && ! flag_writable_strings \
3372 /* If this string is from a function, and the function will \
3373 go in a gnu linkonce section, then we can't directly \
3374 access the string. This gets an assembler error \
3375 "unsupported PC relative reference to different section".\
3376 If we modify SELECT_SECTION to put it in function_section\
3377 instead of text_section, it still fails because \
3378 DECL_SECTION_NAME isn't set until assemble_start_function.\
3379 If we fix that, it still fails because strings are shared\
3380 among multiple functions, and we have cross section \
3381 references again. We force it to work by putting string \
3382 addresses in the constant pool and indirecting. */ \
3383 && (! current_function_decl \
3384 || ! DECL_ONE_ONLY (current_function_decl))) \
3386 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3387 mips_string_length += TREE_STRING_LENGTH (DECL); \
3391 if (TARGET_EMBEDDED_DATA \
3392 && (TREE_CODE (DECL) == VAR_DECL \
3393 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3394 && (!DECL_INITIAL (DECL) \
3395 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3397 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3400 else if (TARGET_EMBEDDED_PIC) \
3402 if (TREE_CODE (DECL) == VAR_DECL) \
3403 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3404 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3405 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3406 else if (TREE_CODE (DECL) == STRING_CST \
3407 && ! flag_writable_strings) \
3408 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3410 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3413 else if (TREE_CODE (DECL) == VAR_DECL \
3414 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3415 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3417 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3420 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3423 /* We can not perform GP optimizations on variables which are in \
3424 specific sections, except for .sdata and .sbss which are \
3426 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3427 && DECL_SECTION_NAME (DECL) == NULL_TREE \
3428 && ! (TARGET_MIPS16 && TREE_PUBLIC (DECL) \
3429 && (DECL_COMMON (DECL) \
3430 || DECL_ONE_ONLY (DECL) \
3431 || DECL_WEAK (DECL)))) \
3433 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3435 if (size > 0 && size <= mips_section_threshold) \
3436 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3439 else if (HALF_PIC_P ()) \
3442 HALF_PIC_ENCODE (DECL); \
3447 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3448 'the start of the function that this code is output in'. */
3450 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3451 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3452 asm_fprintf ((FILE), "%U%s", \
3453 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3455 asm_fprintf ((FILE), "%U%s", (NAME))
3457 /* The mips16 wants the constant pool to be after the function,
3458 because the PC relative load instructions use unsigned offsets. */
3460 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3462 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3463 mips_string_length = 0;
3466 /* In mips16 mode, put most string constants after the function. */
3467 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3468 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3471 /* Specify the machine mode that this machine uses
3472 for the index in the tablejump instruction.
3473 ??? Using HImode in mips16 mode can cause overflow. However, the
3474 overflow is no more likely than the overflow in a branch
3475 instruction. Large functions can currently break in both ways. */
3476 #define CASE_VECTOR_MODE \
3477 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3479 /* Define as C expression which evaluates to nonzero if the tablejump
3480 instruction expects the table to contain offsets from the address of the
3482 Do not define this if the table should contain absolute addresses. */
3483 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3485 /* Define this as 1 if `char' should by default be signed; else as 0. */
3486 #ifndef DEFAULT_SIGNED_CHAR
3487 #define DEFAULT_SIGNED_CHAR 1
3490 /* Max number of bytes we can move from memory to memory
3491 in one reasonably fast instruction. */
3492 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3493 #define MAX_MOVE_MAX 8
3495 /* Define this macro as a C expression which is nonzero if
3496 accessing less than a word of memory (i.e. a `char' or a
3497 `short') is no faster than accessing a word of memory, i.e., if
3498 such access require more than one instruction or if there is no
3499 difference in cost between byte and (aligned) word loads.
3501 On RISC machines, it tends to generate better code to define
3502 this as 1, since it avoids making a QI or HI mode register. */
3503 #define SLOW_BYTE_ACCESS 1
3505 /* We assume that the store-condition-codes instructions store 0 for false
3506 and some other value for true. This is the value stored for true. */
3508 #define STORE_FLAG_VALUE 1
3510 /* Define this to be nonzero if shift instructions ignore all but the low-order
3512 #define SHIFT_COUNT_TRUNCATED 1
3514 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3515 is done just by pretending it is already truncated. */
3516 /* In 64 bit mode, 32 bit instructions require that register values be properly
3517 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3518 converts a value >32 bits to a value <32 bits. */
3519 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3520 Something needs to be done about this. Perhaps not use any 32 bit
3521 instructions? Perhaps use PROMOTE_MODE? */
3522 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3523 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3525 /* Specify the machine mode that pointers have.
3526 After generation of rtl, the compiler makes no further distinction
3527 between pointers and any other objects of this machine mode.
3529 For MIPS we make pointers are the smaller of longs and gp-registers. */
3532 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3535 /* A function address in a call instruction
3536 is a word address (for indexing purposes)
3537 so give the MEM rtx a words's mode. */
3539 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3541 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3542 memset, instead of the BSD functions bcopy and bzero. */
3544 #if defined(MIPS_SYSV) || defined(OSF_OS)
3545 #define TARGET_MEM_FUNCTIONS
3549 /* A part of a C `switch' statement that describes the relative
3550 costs of constant RTL expressions. It must contain `case'
3551 labels for expression codes `const_int', `const', `symbol_ref',
3552 `label_ref' and `const_double'. Each case must ultimately reach
3553 a `return' statement to return the relative cost of the use of
3554 that kind of constant value in an expression. The cost may
3555 depend on the precise value of the constant, which is available
3556 for examination in X.
3558 CODE is the expression code--redundant, since it can be obtained
3559 with `GET_CODE (X)'. */
3561 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3563 if (! TARGET_MIPS16) \
3565 /* Always return 0, since we don't have different sized \
3566 instructions, hence different costs according to Richard \
3570 if ((OUTER_CODE) == SET) \
3572 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3574 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3575 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3576 return COSTS_N_INSNS (1); \
3578 return COSTS_N_INSNS (2); \
3580 /* A PLUS could be an address. We don't want to force an address \
3581 to use a register, so accept any signed 16 bit value without \
3583 if ((OUTER_CODE) == PLUS \
3584 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3586 /* A number between 1 and 8 inclusive is efficient for a shift. \
3587 Otherwise, we will need an extended instruction. */ \
3588 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3589 || (OUTER_CODE) == LSHIFTRT) \
3591 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3593 return COSTS_N_INSNS (1); \
3595 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3596 if ((OUTER_CODE) == XOR \
3597 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3599 /* We may be able to use slt or sltu for a comparison with a \
3600 signed 16 bit value. (The boundary conditions aren't quite \
3601 right, but this is just a heuristic anyhow.) */ \
3602 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3603 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3604 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3605 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3606 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3608 /* Equality comparisons with 0 are cheap. */ \
3609 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3610 && INTVAL (X) == 0) \
3613 /* Otherwise, work out the cost to load the value into a \
3615 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3616 return COSTS_N_INSNS (1); \
3617 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3618 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3619 return COSTS_N_INSNS (2); \
3621 return COSTS_N_INSNS (3); \
3624 return COSTS_N_INSNS (2); \
3628 rtx offset = const0_rtx; \
3629 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3631 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3633 /* Treat this like a signed 16 bit CONST_INT. */ \
3634 if ((OUTER_CODE) == PLUS) \
3636 else if ((OUTER_CODE) == SET) \
3637 return COSTS_N_INSNS (1); \
3639 return COSTS_N_INSNS (2); \
3642 if (GET_CODE (symref) == LABEL_REF) \
3643 return COSTS_N_INSNS (2); \
3645 if (GET_CODE (symref) != SYMBOL_REF) \
3646 return COSTS_N_INSNS (4); \
3648 /* let's be paranoid.... */ \
3649 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3650 return COSTS_N_INSNS (2); \
3652 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3656 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3658 case CONST_DOUBLE: \
3661 if (TARGET_MIPS16) \
3662 return COSTS_N_INSNS (4); \
3663 split_double (X, &high, &low); \
3664 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3665 || low == CONST0_RTX (GET_MODE (low))) \
3669 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3670 This can be used, for example, to indicate how costly a multiply
3671 instruction is. In writing this macro, you can use the construct
3672 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3674 This macro is optional; do not define it if the default cost
3675 assumptions are adequate for the target machine.
3677 If -mdebugd is used, change the multiply cost to 2, so multiply by
3678 a constant isn't converted to a series of shifts. This helps
3679 strength reduction, and also makes it easier to identify what the
3680 compiler is doing. */
3682 /* ??? Fix this to be right for the R8000. */
3683 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3686 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3687 if (simple_memory_operand (X, GET_MODE (X))) \
3688 return COSTS_N_INSNS (num_words); \
3690 return COSTS_N_INSNS (2*num_words); \
3694 return COSTS_N_INSNS (6); \
3697 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3702 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3703 return COSTS_N_INSNS (2); \
3710 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3711 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3717 enum machine_mode xmode = GET_MODE (X); \
3718 if (xmode == SFmode || xmode == DFmode) \
3719 return COSTS_N_INSNS (1); \
3721 return COSTS_N_INSNS (4); \
3727 enum machine_mode xmode = GET_MODE (X); \
3728 if (xmode == SFmode || xmode == DFmode) \
3732 return COSTS_N_INSNS (2); \
3733 else if (TUNE_MIPS6000) \
3734 return COSTS_N_INSNS (3); \
3736 return COSTS_N_INSNS (6); \
3739 if (xmode == DImode && !TARGET_64BIT) \
3740 return COSTS_N_INSNS (4); \
3746 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3753 enum machine_mode xmode = GET_MODE (X); \
3754 if (xmode == SFmode) \
3759 return COSTS_N_INSNS (4); \
3760 else if (TUNE_MIPS6000) \
3761 return COSTS_N_INSNS (5); \
3763 return COSTS_N_INSNS (7); \
3766 if (xmode == DFmode) \
3771 return COSTS_N_INSNS (5); \
3772 else if (TUNE_MIPS6000) \
3773 return COSTS_N_INSNS (6); \
3775 return COSTS_N_INSNS (8); \
3778 if (TUNE_MIPS3000) \
3779 return COSTS_N_INSNS (12); \
3780 else if (TUNE_MIPS3900) \
3781 return COSTS_N_INSNS (2); \
3782 else if (TUNE_MIPS6000) \
3783 return COSTS_N_INSNS (17); \
3784 else if (TUNE_MIPS5000) \
3785 return COSTS_N_INSNS (5); \
3787 return COSTS_N_INSNS (10); \
3793 enum machine_mode xmode = GET_MODE (X); \
3794 if (xmode == SFmode) \
3798 return COSTS_N_INSNS (12); \
3799 else if (TUNE_MIPS6000) \
3800 return COSTS_N_INSNS (15); \
3802 return COSTS_N_INSNS (23); \
3805 if (xmode == DFmode) \
3809 return COSTS_N_INSNS (19); \
3810 else if (TUNE_MIPS6000) \
3811 return COSTS_N_INSNS (16); \
3813 return COSTS_N_INSNS (36); \
3816 /* fall through */ \
3822 return COSTS_N_INSNS (35); \
3823 else if (TUNE_MIPS6000) \
3824 return COSTS_N_INSNS (38); \
3825 else if (TUNE_MIPS5000) \
3826 return COSTS_N_INSNS (36); \
3828 return COSTS_N_INSNS (69); \
3831 /* A sign extend from SImode to DImode in 64 bit mode is often \
3832 zero instructions, because the result can often be used \
3833 directly by another instruction; we'll call it one. */ \
3834 if (TARGET_64BIT && GET_MODE (X) == DImode \
3835 && GET_MODE (XEXP (X, 0)) == SImode) \
3836 return COSTS_N_INSNS (1); \
3838 return COSTS_N_INSNS (2); \
3841 if (TARGET_64BIT && GET_MODE (X) == DImode \
3842 && GET_MODE (XEXP (X, 0)) == SImode) \
3843 return COSTS_N_INSNS (2); \
3845 return COSTS_N_INSNS (1);
3847 /* An expression giving the cost of an addressing mode that
3848 contains ADDRESS. If not defined, the cost is computed from the
3849 form of the ADDRESS expression and the `CONST_COSTS' values.
3851 For most CISC machines, the default cost is a good approximation
3852 of the true cost of the addressing mode. However, on RISC
3853 machines, all instructions normally have the same length and
3854 execution time. Hence all addresses will have equal costs.
3856 In cases where more than one form of an address is known, the
3857 form with the lowest cost will be used. If multiple forms have
3858 the same, lowest, cost, the one that is the most complex will be
3861 For example, suppose an address that is equal to the sum of a
3862 register and a constant is used twice in the same basic block.
3863 When this macro is not defined, the address will be computed in
3864 a register and memory references will be indirect through that
3865 register. On machines where the cost of the addressing mode
3866 containing the sum is no higher than that of a simple indirect
3867 reference, this will produce an additional instruction and
3868 possibly require an additional register. Proper specification
3869 of this macro eliminates this overhead for such machines.
3871 Similar use of this macro is made in strength reduction of loops.
3873 ADDRESS need not be valid as an address. In such a case, the
3874 cost is not relevant and can be any value; invalid addresses
3875 need not be assigned a different cost.
3877 On machines where an address involving more than one register is
3878 as cheap as an address computation involving only one register,
3879 defining `ADDRESS_COST' to reflect this can cause two registers
3880 to be live over a region of code where only one would have been
3881 if `ADDRESS_COST' were not defined in that manner. This effect
3882 should be considered in the definition of this macro.
3883 Equivalent costs should probably only be given to addresses with
3884 different numbers of registers on machines with lots of registers.
3886 This macro will normally either not be defined or be defined as
3889 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3891 /* A C expression for the cost of moving data from a register in
3892 class FROM to one in class TO. The classes are expressed using
3893 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3894 the default; other values are interpreted relative to that.
3896 It is not required that the cost always equal 2 when FROM is the
3897 same as TO; on some machines it is expensive to move between
3898 registers if they are not general registers.
3900 If reload sees an insn consisting of a single `set' between two
3901 hard registers, and if `REGISTER_MOVE_COST' applied to their
3902 classes returns a value of 2, reload does not check to ensure
3903 that the constraints of the insn are met. Setting a cost of
3904 other than 2 will allow reload to verify that the constraints are
3905 met. You should do this if the `movM' pattern's constraints do
3906 not allow such copying. */
3908 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3909 mips_register_move_cost (MODE, FROM, TO)
3911 /* ??? Fix this to be right for the R8000. */
3912 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3913 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3914 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3916 /* Define if copies to/from condition code registers should be avoided.
3918 This is needed for the MIPS because reload_outcc is not complete;
3919 it needs to handle cases where the source is a general or another
3920 condition code register. */
3921 #define AVOID_CCMODE_COPIES
3923 /* A C expression for the cost of a branch instruction. A value of
3924 1 is the default; other values are interpreted relative to that. */
3926 /* ??? Fix this to be right for the R8000. */
3927 #define BRANCH_COST \
3929 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3932 /* If defined, modifies the length assigned to instruction INSN as a
3933 function of the context in which it is used. LENGTH is an lvalue
3934 that contains the initially computed length of the insn and should
3935 be updated with the correct length of the insn. */
3936 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3937 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3940 /* Optionally define this if you have added predicates to
3941 `MACHINE.c'. This macro is called within an initializer of an
3942 array of structures. The first field in the structure is the
3943 name of a predicate and the second field is an array of rtl
3944 codes. For each predicate, list all rtl codes that can be in
3945 expressions matched by the predicate. The list should have a
3946 trailing comma. Here is an example of two entries in the list
3947 for a typical RISC machine:
3949 #define PREDICATE_CODES \
3950 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3951 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3953 Defining this macro does not affect the generated code (however,
3954 incorrect definitions that omit an rtl code that may be matched
3955 by the predicate can cause the compiler to malfunction).
3956 Instead, it allows the table built by `genrecog' to be more
3957 compact and efficient, thus speeding up the compiler. The most
3958 important predicates to include in the list specified by this
3959 macro are thoses used in the most insn patterns. */
3961 #define PREDICATE_CODES \
3962 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3963 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3964 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3965 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3966 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3967 {"small_int", { CONST_INT }}, \
3968 {"large_int", { CONST_INT }}, \
3969 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3970 {"const_float_1_operand", { CONST_DOUBLE }}, \
3971 {"simple_memory_operand", { MEM, SUBREG }}, \
3972 {"equality_op", { EQ, NE }}, \
3973 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3975 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3976 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3977 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3978 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3979 SYMBOL_REF, LABEL_REF, SUBREG, \
3981 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3982 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3983 MEM, SIGN_EXTEND }}, \
3984 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3985 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3987 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3989 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3991 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3992 SYMBOL_REF, LABEL_REF, SUBREG, \
3993 REG, SIGN_EXTEND }}, \
3994 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3995 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3996 CONST_DOUBLE, CONST }}, \
3997 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3998 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
4000 /* A list of predicates that do special things with modes, and so
4001 should not elicit warnings for VOIDmode match_operand. */
4003 #define SPECIAL_MODE_PREDICATES \
4004 "pc_or_label_operand",
4007 /* If defined, a C statement to be executed just prior to the
4008 output of assembler code for INSN, to modify the extracted
4009 operands so they will be output differently.
4011 Here the argument OPVEC is the vector containing the operands
4012 extracted from INSN, and NOPERANDS is the number of elements of
4013 the vector which contain meaningful data for this insn. The
4014 contents of this vector are what will be used to convert the
4015 insn template into assembler code, so you can change the
4016 assembler output by changing the contents of the vector.
4018 We use it to check if the current insn needs a nop in front of it
4019 because of load delays, and also to update the delay slot
4022 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
4023 final_prescan_insn (INSN, OPVEC, NOPERANDS)
4026 /* Control the assembler format that we output. */
4028 /* Output at beginning of assembler file.
4029 If we are optimizing to use the global pointer, create a temporary
4030 file to hold all of the text stuff, and write it out to the end.
4031 This is needed because the MIPS assembler is evidently one pass,
4032 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4033 declaration when the code is processed, it generates a two
4034 instruction sequence. */
4036 #undef ASM_FILE_START
4037 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
4039 /* Output to assembler file text saying following lines
4040 may contain character constants, extra white space, comments, etc. */
4043 #define ASM_APP_ON " #APP\n"
4046 /* Output to assembler file text saying following lines
4047 no longer contain unusual constructs. */
4050 #define ASM_APP_OFF " #NO_APP\n"
4053 /* How to refer to registers in assembler output.
4054 This sequence is indexed by compiler's hard-register-number (see above).
4056 In order to support the two different conventions for register names,
4057 we use the name of a table set up in mips.c, which is overwritten
4058 if -mrnames is used. */
4060 #define REGISTER_NAMES \
4062 &mips_reg_names[ 0][0], \
4063 &mips_reg_names[ 1][0], \
4064 &mips_reg_names[ 2][0], \
4065 &mips_reg_names[ 3][0], \
4066 &mips_reg_names[ 4][0], \
4067 &mips_reg_names[ 5][0], \
4068 &mips_reg_names[ 6][0], \
4069 &mips_reg_names[ 7][0], \
4070 &mips_reg_names[ 8][0], \
4071 &mips_reg_names[ 9][0], \
4072 &mips_reg_names[10][0], \
4073 &mips_reg_names[11][0], \
4074 &mips_reg_names[12][0], \
4075 &mips_reg_names[13][0], \
4076 &mips_reg_names[14][0], \
4077 &mips_reg_names[15][0], \
4078 &mips_reg_names[16][0], \
4079 &mips_reg_names[17][0], \
4080 &mips_reg_names[18][0], \
4081 &mips_reg_names[19][0], \
4082 &mips_reg_names[20][0], \
4083 &mips_reg_names[21][0], \
4084 &mips_reg_names[22][0], \
4085 &mips_reg_names[23][0], \
4086 &mips_reg_names[24][0], \
4087 &mips_reg_names[25][0], \
4088 &mips_reg_names[26][0], \
4089 &mips_reg_names[27][0], \
4090 &mips_reg_names[28][0], \
4091 &mips_reg_names[29][0], \
4092 &mips_reg_names[30][0], \
4093 &mips_reg_names[31][0], \
4094 &mips_reg_names[32][0], \
4095 &mips_reg_names[33][0], \
4096 &mips_reg_names[34][0], \
4097 &mips_reg_names[35][0], \
4098 &mips_reg_names[36][0], \
4099 &mips_reg_names[37][0], \
4100 &mips_reg_names[38][0], \
4101 &mips_reg_names[39][0], \
4102 &mips_reg_names[40][0], \
4103 &mips_reg_names[41][0], \
4104 &mips_reg_names[42][0], \
4105 &mips_reg_names[43][0], \
4106 &mips_reg_names[44][0], \
4107 &mips_reg_names[45][0], \
4108 &mips_reg_names[46][0], \
4109 &mips_reg_names[47][0], \
4110 &mips_reg_names[48][0], \
4111 &mips_reg_names[49][0], \
4112 &mips_reg_names[50][0], \
4113 &mips_reg_names[51][0], \
4114 &mips_reg_names[52][0], \
4115 &mips_reg_names[53][0], \
4116 &mips_reg_names[54][0], \
4117 &mips_reg_names[55][0], \
4118 &mips_reg_names[56][0], \
4119 &mips_reg_names[57][0], \
4120 &mips_reg_names[58][0], \
4121 &mips_reg_names[59][0], \
4122 &mips_reg_names[60][0], \
4123 &mips_reg_names[61][0], \
4124 &mips_reg_names[62][0], \
4125 &mips_reg_names[63][0], \
4126 &mips_reg_names[64][0], \
4127 &mips_reg_names[65][0], \
4128 &mips_reg_names[66][0], \
4129 &mips_reg_names[67][0], \
4130 &mips_reg_names[68][0], \
4131 &mips_reg_names[69][0], \
4132 &mips_reg_names[70][0], \
4133 &mips_reg_names[71][0], \
4134 &mips_reg_names[72][0], \
4135 &mips_reg_names[73][0], \
4136 &mips_reg_names[74][0], \
4137 &mips_reg_names[75][0], \
4138 &mips_reg_names[76][0], \
4139 &mips_reg_names[77][0], \
4140 &mips_reg_names[78][0], \
4141 &mips_reg_names[79][0], \
4142 &mips_reg_names[80][0], \
4143 &mips_reg_names[81][0], \
4144 &mips_reg_names[82][0], \
4145 &mips_reg_names[83][0], \
4146 &mips_reg_names[84][0], \
4147 &mips_reg_names[85][0], \
4148 &mips_reg_names[86][0], \
4149 &mips_reg_names[87][0], \
4150 &mips_reg_names[88][0], \
4151 &mips_reg_names[89][0], \
4152 &mips_reg_names[90][0], \
4153 &mips_reg_names[91][0], \
4154 &mips_reg_names[92][0], \
4155 &mips_reg_names[93][0], \
4156 &mips_reg_names[94][0], \
4157 &mips_reg_names[95][0], \
4158 &mips_reg_names[96][0], \
4159 &mips_reg_names[97][0], \
4160 &mips_reg_names[98][0], \
4161 &mips_reg_names[99][0], \
4162 &mips_reg_names[100][0], \
4163 &mips_reg_names[101][0], \
4164 &mips_reg_names[102][0], \
4165 &mips_reg_names[103][0], \
4166 &mips_reg_names[104][0], \
4167 &mips_reg_names[105][0], \
4168 &mips_reg_names[106][0], \
4169 &mips_reg_names[107][0], \
4170 &mips_reg_names[108][0], \
4171 &mips_reg_names[109][0], \
4172 &mips_reg_names[110][0], \
4173 &mips_reg_names[111][0], \
4174 &mips_reg_names[112][0], \
4175 &mips_reg_names[113][0], \
4176 &mips_reg_names[114][0], \
4177 &mips_reg_names[115][0], \
4178 &mips_reg_names[116][0], \
4179 &mips_reg_names[117][0], \
4180 &mips_reg_names[118][0], \
4181 &mips_reg_names[119][0], \
4182 &mips_reg_names[120][0], \
4183 &mips_reg_names[121][0], \
4184 &mips_reg_names[122][0], \
4185 &mips_reg_names[123][0], \
4186 &mips_reg_names[124][0], \
4187 &mips_reg_names[125][0], \
4188 &mips_reg_names[126][0], \
4189 &mips_reg_names[127][0], \
4190 &mips_reg_names[128][0], \
4191 &mips_reg_names[129][0], \
4192 &mips_reg_names[130][0], \
4193 &mips_reg_names[131][0], \
4194 &mips_reg_names[132][0], \
4195 &mips_reg_names[133][0], \
4196 &mips_reg_names[134][0], \
4197 &mips_reg_names[135][0], \
4198 &mips_reg_names[136][0], \
4199 &mips_reg_names[137][0], \
4200 &mips_reg_names[138][0], \
4201 &mips_reg_names[139][0], \
4202 &mips_reg_names[140][0], \
4203 &mips_reg_names[141][0], \
4204 &mips_reg_names[142][0], \
4205 &mips_reg_names[143][0], \
4206 &mips_reg_names[144][0], \
4207 &mips_reg_names[145][0], \
4208 &mips_reg_names[146][0], \
4209 &mips_reg_names[147][0], \
4210 &mips_reg_names[148][0], \
4211 &mips_reg_names[149][0], \
4212 &mips_reg_names[150][0], \
4213 &mips_reg_names[151][0], \
4214 &mips_reg_names[152][0], \
4215 &mips_reg_names[153][0], \
4216 &mips_reg_names[154][0], \
4217 &mips_reg_names[155][0], \
4218 &mips_reg_names[156][0], \
4219 &mips_reg_names[157][0], \
4220 &mips_reg_names[158][0], \
4221 &mips_reg_names[159][0], \
4222 &mips_reg_names[160][0], \
4223 &mips_reg_names[161][0], \
4224 &mips_reg_names[162][0], \
4225 &mips_reg_names[163][0], \
4226 &mips_reg_names[164][0], \
4227 &mips_reg_names[165][0], \
4228 &mips_reg_names[166][0], \
4229 &mips_reg_names[167][0], \
4230 &mips_reg_names[168][0], \
4231 &mips_reg_names[169][0], \
4232 &mips_reg_names[170][0], \
4233 &mips_reg_names[171][0], \
4234 &mips_reg_names[172][0], \
4235 &mips_reg_names[173][0], \
4236 &mips_reg_names[174][0], \
4237 &mips_reg_names[175][0] \
4240 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4241 So define this for it. */
4242 #define DEBUG_REGISTER_NAMES \
4244 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4245 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4246 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4247 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4248 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4249 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4250 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4251 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4252 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4253 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
4254 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
4255 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
4256 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
4257 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
4258 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
4259 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
4260 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
4261 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
4262 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
4263 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
4264 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
4265 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
4268 /* If defined, a C initializer for an array of structures
4269 containing a name and a register number. This macro defines
4270 additional names for hard registers, thus allowing the `asm'
4271 option in declarations to refer to registers using alternate
4274 We define both names for the integer registers here. */
4276 #define ADDITIONAL_REGISTER_NAMES \
4278 { "$0", 0 + GP_REG_FIRST }, \
4279 { "$1", 1 + GP_REG_FIRST }, \
4280 { "$2", 2 + GP_REG_FIRST }, \
4281 { "$3", 3 + GP_REG_FIRST }, \
4282 { "$4", 4 + GP_REG_FIRST }, \
4283 { "$5", 5 + GP_REG_FIRST }, \
4284 { "$6", 6 + GP_REG_FIRST }, \
4285 { "$7", 7 + GP_REG_FIRST }, \
4286 { "$8", 8 + GP_REG_FIRST }, \
4287 { "$9", 9 + GP_REG_FIRST }, \
4288 { "$10", 10 + GP_REG_FIRST }, \
4289 { "$11", 11 + GP_REG_FIRST }, \
4290 { "$12", 12 + GP_REG_FIRST }, \
4291 { "$13", 13 + GP_REG_FIRST }, \
4292 { "$14", 14 + GP_REG_FIRST }, \
4293 { "$15", 15 + GP_REG_FIRST }, \
4294 { "$16", 16 + GP_REG_FIRST }, \
4295 { "$17", 17 + GP_REG_FIRST }, \
4296 { "$18", 18 + GP_REG_FIRST }, \
4297 { "$19", 19 + GP_REG_FIRST }, \
4298 { "$20", 20 + GP_REG_FIRST }, \
4299 { "$21", 21 + GP_REG_FIRST }, \
4300 { "$22", 22 + GP_REG_FIRST }, \
4301 { "$23", 23 + GP_REG_FIRST }, \
4302 { "$24", 24 + GP_REG_FIRST }, \
4303 { "$25", 25 + GP_REG_FIRST }, \
4304 { "$26", 26 + GP_REG_FIRST }, \
4305 { "$27", 27 + GP_REG_FIRST }, \
4306 { "$28", 28 + GP_REG_FIRST }, \
4307 { "$29", 29 + GP_REG_FIRST }, \
4308 { "$30", 30 + GP_REG_FIRST }, \
4309 { "$31", 31 + GP_REG_FIRST }, \
4310 { "$sp", 29 + GP_REG_FIRST }, \
4311 { "$fp", 30 + GP_REG_FIRST }, \
4312 { "at", 1 + GP_REG_FIRST }, \
4313 { "v0", 2 + GP_REG_FIRST }, \
4314 { "v1", 3 + GP_REG_FIRST }, \
4315 { "a0", 4 + GP_REG_FIRST }, \
4316 { "a1", 5 + GP_REG_FIRST }, \
4317 { "a2", 6 + GP_REG_FIRST }, \
4318 { "a3", 7 + GP_REG_FIRST }, \
4319 { "t0", 8 + GP_REG_FIRST }, \
4320 { "t1", 9 + GP_REG_FIRST }, \
4321 { "t2", 10 + GP_REG_FIRST }, \
4322 { "t3", 11 + GP_REG_FIRST }, \
4323 { "t4", 12 + GP_REG_FIRST }, \
4324 { "t5", 13 + GP_REG_FIRST }, \
4325 { "t6", 14 + GP_REG_FIRST }, \
4326 { "t7", 15 + GP_REG_FIRST }, \
4327 { "s0", 16 + GP_REG_FIRST }, \
4328 { "s1", 17 + GP_REG_FIRST }, \
4329 { "s2", 18 + GP_REG_FIRST }, \
4330 { "s3", 19 + GP_REG_FIRST }, \
4331 { "s4", 20 + GP_REG_FIRST }, \
4332 { "s5", 21 + GP_REG_FIRST }, \
4333 { "s6", 22 + GP_REG_FIRST }, \
4334 { "s7", 23 + GP_REG_FIRST }, \
4335 { "t8", 24 + GP_REG_FIRST }, \
4336 { "t9", 25 + GP_REG_FIRST }, \
4337 { "k0", 26 + GP_REG_FIRST }, \
4338 { "k1", 27 + GP_REG_FIRST }, \
4339 { "gp", 28 + GP_REG_FIRST }, \
4340 { "sp", 29 + GP_REG_FIRST }, \
4341 { "fp", 30 + GP_REG_FIRST }, \
4342 { "ra", 31 + GP_REG_FIRST }, \
4343 { "$sp", 29 + GP_REG_FIRST }, \
4344 { "$fp", 30 + GP_REG_FIRST } \
4345 ALL_COP_ADDITIONAL_REGISTER_NAMES \
4348 /* This is meant to be redefined in the host dependent files. It is a
4349 set of alternative names and regnums for mips coprocessors. */
4351 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
4353 /* A C compound statement to output to stdio stream STREAM the
4354 assembler syntax for an instruction operand X. X is an RTL
4357 CODE is a value that can be used to specify one of several ways
4358 of printing the operand. It is used when identical operands
4359 must be printed differently depending on the context. CODE
4360 comes from the `%' specification that was used to request
4361 printing of the operand. If the specification was just `%DIGIT'
4362 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4363 is the ASCII code for LTR.
4365 If X is a register, this macro should print the register's name.
4366 The names can be found in an array `reg_names' whose type is
4367 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4369 When the machine description has a specification `%PUNCT' (a `%'
4370 followed by a punctuation character), this macro is called with
4371 a null pointer for X and the punctuation character for CODE.
4373 See mips.c for the MIPS specific codes. */
4375 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4377 /* A C expression which evaluates to true if CODE is a valid
4378 punctuation character for use in the `PRINT_OPERAND' macro. If
4379 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4380 punctuation characters (except for the standard one, `%') are
4381 used in this way. */
4383 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4385 /* A C compound statement to output to stdio stream STREAM the
4386 assembler syntax for an instruction operand that is a memory
4387 reference whose address is ADDR. ADDR is an RTL expression.
4389 On some machines, the syntax for a symbolic address depends on
4390 the section that the address refers to. On these machines,
4391 define the macro `ENCODE_SECTION_INFO' to store the information
4392 into the `symbol_ref', and then check for it here. */
4394 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4397 /* A C statement, to be executed after all slot-filler instructions
4398 have been output. If necessary, call `dbr_sequence_length' to
4399 determine the number of slots filled in a sequence (zero if not
4400 currently outputting a sequence), to decide how many no-ops to
4401 output, or whatever.
4403 Don't define this macro if it has nothing to do, but it is
4404 helpful in reading assembly output if the extent of the delay
4405 sequence is made explicit (e.g. with white space).
4407 Note that output routines for instructions with delay slots must
4408 be prepared to deal with not being output as part of a sequence
4409 (i.e. when the scheduling pass is not run, or when no slot
4410 fillers could be found.) The variable `final_sequence' is null
4411 when not processing a sequence, otherwise it contains the
4412 `sequence' rtx being output. */
4414 #define DBR_OUTPUT_SEQEND(STREAM) \
4417 if (set_nomacro > 0 && --set_nomacro == 0) \
4418 fputs ("\t.set\tmacro\n", STREAM); \
4420 if (set_noreorder > 0 && --set_noreorder == 0) \
4421 fputs ("\t.set\treorder\n", STREAM); \
4423 dslots_jump_filled++; \
4424 fputs ("\n", STREAM); \
4429 /* How to tell the debugger about changes of source files. Note, the
4430 mips ECOFF format cannot deal with changes of files inside of
4431 functions, which means the output of parser generators like bison
4432 is generally not debuggable without using the -l switch. Lose,
4433 lose, lose. Silicon graphics seems to want all .file's hardwired
4436 #ifndef SET_FILE_NUMBER
4437 #define SET_FILE_NUMBER() ++num_source_filenames
4440 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4441 mips_output_filename (STREAM, NAME)
4443 /* This is defined so that it can be overridden in iris6.h. */
4444 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4447 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4448 output_quoted_string (STREAM, NAME); \
4449 fputs ("\n", STREAM); \
4453 /* This is how to output a note the debugger telling it the line number
4454 to which the following sequence of instructions corresponds.
4455 Silicon graphics puts a label after each .loc. */
4457 #ifndef LABEL_AFTER_LOC
4458 #define LABEL_AFTER_LOC(STREAM)
4461 #ifndef ASM_OUTPUT_SOURCE_LINE
4462 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4463 mips_output_lineno (STREAM, LINE)
4466 /* The MIPS implementation uses some labels for its own purpose. The
4467 following lists what labels are created, and are all formed by the
4468 pattern $L[a-z].*. The machine independent portion of GCC creates
4469 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4471 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4472 $Lb[0-9]+ Begin blocks for MIPS debug support
4473 $Lc[0-9]+ Label for use in s<xx> operation.
4474 $Le[0-9]+ End blocks for MIPS debug support
4475 $Lp\..+ Half-pic labels. */
4477 /* This is how to output the definition of a user-level label named NAME,
4478 such as the label on a static function or variable NAME.
4480 If we are optimizing the gp, remember that this label has been put
4481 out, so we know not to emit an .extern for it in mips_asm_file_end.
4482 We use one of the common bits in the IDENTIFIER tree node for this,
4483 since those bits seem to be unused, and we don't have any method
4484 of getting the decl nodes from the name. */
4486 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4488 assemble_name (STREAM, NAME); \
4489 fputs (":\n", STREAM); \
4493 /* A C statement (sans semicolon) to output to the stdio stream
4494 STREAM any text necessary for declaring the name NAME of an
4495 initialized variable which is being defined. This macro must
4496 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4497 The argument DECL is the `VAR_DECL' tree node representing the
4500 If this macro is not defined, then the variable name is defined
4501 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4503 #undef ASM_DECLARE_OBJECT_NAME
4504 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4507 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4508 HALF_PIC_DECLARE (NAME); \
4513 /* This is how to output a command to make the user-level label named NAME
4514 defined for reference from other files. */
4516 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4518 fputs ("\t.globl\t", STREAM); \
4519 assemble_name (STREAM, NAME); \
4520 fputs ("\n", STREAM); \
4523 /* This says how to define a global common symbol. */
4525 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4527 /* If the target wants uninitialized const declarations in \
4528 .rdata then don't put them in .comm */ \
4529 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4530 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4531 && (DECL_INITIAL (DECL) == 0 \
4532 || DECL_INITIAL (DECL) == error_mark_node)) \
4534 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4535 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4537 READONLY_DATA_SECTION (); \
4538 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4539 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4543 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4548 /* This says how to define a local common symbol (ie, not visible to
4551 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4552 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4555 /* This says how to output an external. It would be possible not to
4556 output anything and let undefined symbol become external. However
4557 the assembler uses length information on externals to allocate in
4558 data/sdata bss/sbss, thereby saving exec time. */
4560 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4561 mips_output_external(STREAM,DECL,NAME)
4563 /* This says what to print at the end of the assembly file */
4565 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4568 /* Play switch file games if we're optimizing the global pointer. */
4571 #define TEXT_SECTION() \
4573 extern FILE *asm_out_text_file; \
4574 if (TARGET_FILE_SWITCHING) \
4575 asm_out_file = asm_out_text_file; \
4576 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4577 fputc ('\n', asm_out_file); \
4581 /* This is how to declare a function name. The actual work of
4582 emitting the label is moved to function_prologue, so that we can
4583 get the line number correctly emitted before the .ent directive,
4584 and after any .file directives. */
4586 #undef ASM_DECLARE_FUNCTION_NAME
4587 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4588 HALF_PIC_DECLARE (NAME)
4590 /* This is how to output an internal numbered label where
4591 PREFIX is the class of label and NUM is the number within the class. */
4593 #undef ASM_OUTPUT_INTERNAL_LABEL
4594 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4595 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4597 /* This is how to store into the string LABEL
4598 the symbol_ref name of an internal numbered label where
4599 PREFIX is the class of label and NUM is the number within the class.
4600 This is suitable for output with `assemble_name'. */
4602 #undef ASM_GENERATE_INTERNAL_LABEL
4603 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4604 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4606 /* This is how to output an element of a case-vector that is absolute. */
4608 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4609 fprintf (STREAM, "\t%s\t%sL%d\n", \
4610 Pmode == DImode ? ".dword" : ".word", \
4611 LOCAL_LABEL_PREFIX, \
4614 /* This is how to output an element of a case-vector that is relative.
4615 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4616 TARGET_EMBEDDED_PIC). */
4618 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4620 if (TARGET_MIPS16) \
4621 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4622 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4623 else if (TARGET_EMBEDDED_PIC) \
4624 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4625 Pmode == DImode ? ".dword" : ".word", \
4626 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4627 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4628 fprintf (STREAM, "\t%s\t%sL%d\n", \
4629 Pmode == DImode ? ".gpdword" : ".gpword", \
4630 LOCAL_LABEL_PREFIX, VALUE); \
4632 fprintf (STREAM, "\t%s\t%sL%d\n", \
4633 Pmode == DImode ? ".dword" : ".word", \
4634 LOCAL_LABEL_PREFIX, VALUE); \
4637 /* When generating embedded PIC or mips16 code we want to put the jump
4638 table in the .text section. In all other cases, we want to put the
4639 jump table in the .rdata section. Unfortunately, we can't use
4640 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4641 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4642 section if appropriate. */
4643 #undef ASM_OUTPUT_CASE_LABEL
4644 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4646 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4647 function_section (current_function_decl); \
4648 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4651 /* This is how to output an assembler line
4652 that says to advance the location counter
4653 to a multiple of 2**LOG bytes. */
4655 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4656 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4658 /* This is how to output an assembler line to advance the location
4659 counter by SIZE bytes. */
4661 #undef ASM_OUTPUT_SKIP
4662 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4663 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4665 /* This is how to output a string. */
4666 #undef ASM_OUTPUT_ASCII
4667 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4668 mips_output_ascii (STREAM, STRING, LEN)
4670 /* Handle certain cpp directives used in header files on sysV. */
4671 #define SCCS_DIRECTIVE
4673 /* Output #ident as a in the read-only data section. */
4674 #undef ASM_OUTPUT_IDENT
4675 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4677 const char *p = STRING; \
4678 int size = strlen (p) + 1; \
4680 assemble_string (p, size); \
4683 /* Default to -G 8 */
4684 #ifndef MIPS_DEFAULT_GVALUE
4685 #define MIPS_DEFAULT_GVALUE 8
4688 /* Define the strings to put out for each section in the object file. */
4689 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4690 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4691 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4692 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4693 #undef READONLY_DATA_SECTION
4694 #define READONLY_DATA_SECTION rdata_section
4695 #define SMALL_DATA_SECTION sdata_section
4697 /* What other sections we support other than the normal .data/.text. */
4699 #undef EXTRA_SECTIONS
4700 #define EXTRA_SECTIONS in_sdata, in_rdata
4702 /* Define the additional functions to select our additional sections. */
4704 /* on the MIPS it is not a good idea to put constants in the text
4705 section, since this defeats the sdata/data mechanism. This is
4706 especially true when -O is used. In this case an effort is made to
4707 address with faster (gp) register relative addressing, which can
4708 only get at sdata and sbss items (there is no stext !!) However,
4709 if the constant is too large for sdata, and it's readonly, it
4710 will go into the .rdata section. */
4712 #undef EXTRA_SECTION_FUNCTIONS
4713 #define EXTRA_SECTION_FUNCTIONS \
4717 if (in_section != in_sdata) \
4719 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4720 in_section = in_sdata; \
4727 if (in_section != in_rdata) \
4729 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4730 in_section = in_rdata; \
4734 /* Given a decl node or constant node, choose the section to output it in
4735 and select that section. */
4737 #undef SELECT_RTX_SECTION
4738 #define SELECT_RTX_SECTION(MODE, RTX, ALIGN) \
4739 mips_select_rtx_section (MODE, RTX)
4741 #undef TARGET_ASM_SELECT_SECTION
4742 #define TARGET_ASM_SELECT_SECTION mips_select_section
4744 /* Store in OUTPUT a string (made with alloca) containing
4745 an assembler-name for a local static variable named NAME.
4746 LABELNO is an integer which is different for each call. */
4748 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4749 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4750 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4752 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4755 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4756 TARGET_64BIT ? "dsubu" : "subu", \
4757 reg_names[STACK_POINTER_REGNUM], \
4758 reg_names[STACK_POINTER_REGNUM], \
4759 TARGET_64BIT ? "sd" : "sw", \
4761 reg_names[STACK_POINTER_REGNUM]); \
4765 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4768 if (! set_noreorder) \
4769 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4771 dslots_load_total++; \
4772 dslots_load_filled++; \
4773 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4774 TARGET_64BIT ? "ld" : "lw", \
4776 reg_names[STACK_POINTER_REGNUM], \
4777 TARGET_64BIT ? "daddu" : "addu", \
4778 reg_names[STACK_POINTER_REGNUM], \
4779 reg_names[STACK_POINTER_REGNUM]); \
4781 if (! set_noreorder) \
4782 fprintf (STREAM, "\t.set\treorder\n"); \
4786 /* How to start an assembler comment.
4787 The leading space is important (the mips native assembler requires it). */
4788 #ifndef ASM_COMMENT_START
4789 #define ASM_COMMENT_START " #"
4793 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4794 and mips-tdump.c to print them out.
4796 These must match the corresponding definitions in gdb/mipsread.c.
4797 Unfortunately, gcc and gdb do not currently share any directories. */
4799 #define CODE_MASK 0x8F300
4800 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4801 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4802 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4805 /* Default definitions for size_t and ptrdiff_t. */
4808 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4811 #ifndef PTRDIFF_TYPE
4812 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4815 /* See mips_expand_prologue's use of loadgp for when this should be
4818 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4819 && mips_abi != ABI_32 \
4820 && mips_abi != ABI_O64)
4822 /* In mips16 mode, we need to look through the function to check for
4823 PC relative loads that are out of range. */
4824 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4826 /* We need to use a special set of functions to handle hard floating
4827 point code in mips16 mode. */
4829 #ifndef INIT_SUBTARGET_OPTABS
4830 #define INIT_SUBTARGET_OPTABS
4833 #define INIT_TARGET_OPTABS \
4836 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4837 INIT_SUBTARGET_OPTABS; \
4840 add_optab->handlers[(int) SFmode].libfunc = \
4841 init_one_libfunc ("__mips16_addsf3"); \
4842 sub_optab->handlers[(int) SFmode].libfunc = \
4843 init_one_libfunc ("__mips16_subsf3"); \
4844 smul_optab->handlers[(int) SFmode].libfunc = \
4845 init_one_libfunc ("__mips16_mulsf3"); \
4846 sdiv_optab->handlers[(int) SFmode].libfunc = \
4847 init_one_libfunc ("__mips16_divsf3"); \
4849 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4850 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4851 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4852 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4853 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4854 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4856 floatsisf_libfunc = \
4857 init_one_libfunc ("__mips16_floatsisf"); \
4859 init_one_libfunc ("__mips16_fixsfsi"); \
4861 if (TARGET_DOUBLE_FLOAT) \
4863 add_optab->handlers[(int) DFmode].libfunc = \
4864 init_one_libfunc ("__mips16_adddf3"); \
4865 sub_optab->handlers[(int) DFmode].libfunc = \
4866 init_one_libfunc ("__mips16_subdf3"); \
4867 smul_optab->handlers[(int) DFmode].libfunc = \
4868 init_one_libfunc ("__mips16_muldf3"); \
4869 sdiv_optab->handlers[(int) DFmode].libfunc = \
4870 init_one_libfunc ("__mips16_divdf3"); \
4872 extendsfdf2_libfunc = \
4873 init_one_libfunc ("__mips16_extendsfdf2"); \
4874 truncdfsf2_libfunc = \
4875 init_one_libfunc ("__mips16_truncdfsf2"); \
4878 init_one_libfunc ("__mips16_eqdf2"); \
4880 init_one_libfunc ("__mips16_nedf2"); \
4882 init_one_libfunc ("__mips16_gtdf2"); \
4884 init_one_libfunc ("__mips16_gedf2"); \
4886 init_one_libfunc ("__mips16_ltdf2"); \
4888 init_one_libfunc ("__mips16_ledf2"); \
4890 floatsidf_libfunc = \
4891 init_one_libfunc ("__mips16_floatsidf"); \
4893 init_one_libfunc ("__mips16_fixdfsi"); \
projects / thirdparty / gcc.git / blob