1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989-2015 Free Software Foundation, Inc.
3 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
4 ;; Changes by Michael Meissner, meissner@osf.org
5 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 ;; Brendan Eich, brendan@microunity.com.
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 (define_enum "processor" [
74 (define_c_enum "unspec" [
75 ;; Unaligned accesses.
81 ;; Integer operations that are too cumbersome to describe directly.
86 ;; Floating-point moves.
93 ;; Floating-point environment.
106 UNSPEC_POTENTIAL_CPRESTORE
111 UNSPEC_SET_GOT_VERSION
112 UNSPEC_UPDATE_GOT_VERSION
114 ;; Symbolic accesses.
119 UNSPEC_UNSHIFTED_HIGH
121 ;; MIPS16 constant pools.
123 UNSPEC_CONSTTABLE_INT
124 UNSPEC_CONSTTABLE_FLOAT
126 ;; Blockage and synchronisation.
133 ;; Cache manipulation.
135 UNSPEC_R10K_CACHE_BARRIER
137 ;; Interrupt handling.
145 ;; Used in a call expression in place of args_size. It's present for PIC
146 ;; indirect calls where it contains args_size and the function symbol.
149 ;; MIPS16 casesi jump table dispatch.
150 UNSPEC_CASESI_DISPATCH
153 UNSPEC_PROBE_STACK_RANGE
157 [(TLS_GET_TP_REGNUM 3)
161 (PIC_FUNCTION_ADDR_REGNUM 25)
162 (RETURN_ADDR_REGNUM 31)
163 (CPRESTORE_SLOT_REGNUM 76)
164 (GOT_VERSION_REGNUM 79)
166 ;; PIC long branch sequences are never longer than 100 bytes.
167 (MAX_PIC_BRANCH_LENGTH 100)
171 (include "predicates.md")
172 (include "constraints.md")
174 ;; ....................
178 ;; ....................
180 (define_attr "got" "unset,xgot_high,load"
181 (const_string "unset"))
183 ;; For jal instructions, this attribute is DIRECT when the target address
184 ;; is symbolic and INDIRECT when it is a register.
185 (define_attr "jal" "unset,direct,indirect"
186 (const_string "unset"))
188 ;; This attribute is YES if the instruction is a jal macro (not a
189 ;; real jal instruction).
191 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
192 ;; an instruction to restore $gp. Direct jals are also macros for
193 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
195 (define_attr "jal_macro" "no,yes"
196 (cond [(eq_attr "jal" "direct")
197 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
198 ? JAL_MACRO_YES : JAL_MACRO_NO)")
199 (eq_attr "jal" "indirect")
200 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
201 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
202 (const_string "no")))
204 ;; Classification of moves, extensions and truncations. Most values
205 ;; are as for "type" (see below) but there are also the following
206 ;; move-specific values:
208 ;; constN move an N-constraint integer into a MIPS16 register
209 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
210 ;; to produce a sign-extended DEST, even if SRC is not
211 ;; properly sign-extended
212 ;; ext_ins EXT, DEXT, INS or DINS instruction
213 ;; andi a single ANDI instruction
214 ;; loadpool move a constant into a MIPS16 register by loading it
216 ;; shift_shift a shift left followed by a shift right
218 ;; This attribute is used to determine the instruction's length and
219 ;; scheduling type. For doubleword moves, the attribute always describes
220 ;; the split instructions; in some cases, it is more appropriate for the
221 ;; scheduling type to be "multi" instead.
222 (define_attr "move_type"
223 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove,
224 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
226 (const_string "unknown"))
228 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
229 (const_string "unknown"))
231 ;; Main data type used by the insn
232 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
233 (const_string "unknown"))
235 ;; True if the main data type is twice the size of a word.
236 (define_attr "dword_mode" "no,yes"
237 (cond [(and (eq_attr "mode" "DI,DF")
238 (not (match_test "TARGET_64BIT")))
241 (and (eq_attr "mode" "TI,TF")
242 (match_test "TARGET_64BIT"))
243 (const_string "yes")]
244 (const_string "no")))
246 ;; Attributes describing a sync loop. These loops have the form:
248 ;; if (RELEASE_BARRIER == YES) sync
250 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
251 ;; CMP = 0 [delay slot]
252 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
253 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
254 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
255 ;; $AT |= $TMP1 | $TMP3
256 ;; if (!commit (*MEM = $AT)) goto 1.
257 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
259 ;; if (ACQUIRE_BARRIER == YES) sync
262 ;; where "$" values are temporaries and where the other values are
263 ;; specified by the attributes below. Values are specified as operand
264 ;; numbers and insns are specified as enums. If no operand number is
265 ;; specified, the following values are used instead:
270 ;; - INCLUSIVE_MASK: -1
271 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
272 ;; - EXCLUSIVE_MASK: 0
274 ;; MEM and INSN1_OP2 are required.
276 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
277 ;; but the gen* programs don't yet support that.
278 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
279 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
280 (define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
281 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
282 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
283 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
284 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
285 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
286 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
287 (const_string "move"))
288 (define_attr "sync_insn2" "nop,and,xor,not"
289 (const_string "nop"))
290 ;; Memory model specifier.
291 ;; "0"-"9" values specify the operand that stores the memory model value.
292 ;; "10" specifies MEMMODEL_ACQ_REL,
293 ;; "11" specifies MEMMODEL_ACQUIRE.
294 (define_attr "sync_memmodel" "" (const_int 10))
296 ;; Accumulator operand for madd patterns.
297 (define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
299 ;; Classification of each insn.
300 ;; branch conditional branch
301 ;; jump unconditional jump
302 ;; call unconditional call
303 ;; load load instruction(s)
304 ;; fpload floating point load
305 ;; fpidxload floating point indexed load
306 ;; store store instruction(s)
307 ;; fpstore floating point store
308 ;; fpidxstore floating point indexed store
309 ;; prefetch memory prefetch (register + offset)
310 ;; prefetchx memory indexed prefetch (register + register)
311 ;; condmove conditional moves
312 ;; mtc transfer to coprocessor
313 ;; mfc transfer from coprocessor
314 ;; mthi transfer to a hi register
315 ;; mtlo transfer to a lo register
316 ;; mfhi transfer from a hi register
317 ;; mflo transfer from a lo register
318 ;; const load constant
319 ;; arith integer arithmetic instructions
320 ;; logical integer logical instructions
321 ;; shift integer shift instructions
322 ;; slt set less than instructions
323 ;; signext sign extend instructions
324 ;; clz the clz and clo instructions
325 ;; pop the pop instruction
326 ;; trap trap if instructions
327 ;; imul integer multiply 2 operands
328 ;; imul3 integer multiply 3 operands
329 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
330 ;; imadd integer multiply-add
331 ;; idiv integer divide 2 operands
332 ;; idiv3 integer divide 3 operands
333 ;; move integer register move ({,D}ADD{,U} with rt = 0)
334 ;; fmove floating point register move
335 ;; fadd floating point add/subtract
336 ;; fmul floating point multiply
337 ;; fmadd floating point multiply-add
338 ;; fdiv floating point divide
339 ;; frdiv floating point reciprocal divide
340 ;; frdiv1 floating point reciprocal divide step 1
341 ;; frdiv2 floating point reciprocal divide step 2
342 ;; fabs floating point absolute value
343 ;; fneg floating point negation
344 ;; fcmp floating point compare
345 ;; fcvt floating point convert
346 ;; fsqrt floating point square root
347 ;; frsqrt floating point reciprocal square root
348 ;; frsqrt1 floating point reciprocal square root step1
349 ;; frsqrt2 floating point reciprocal square root step2
350 ;; dspmac DSP MAC instructions not saturating the accumulator
351 ;; dspmacsat DSP MAC instructions that saturate the accumulator
352 ;; accext DSP accumulator extract instructions
353 ;; accmod DSP accumulator modify instructions
354 ;; dspalu DSP ALU instructions not saturating the result
355 ;; dspalusat DSP ALU instructions that saturate the result
356 ;; multi multiword sequence (or user asm statements)
357 ;; atomic atomic memory update instruction
358 ;; syncloop memory atomic operation implemented as a sync loop
360 ;; ghost an instruction that produces no real code
361 ;; multimem microMIPS multiword load and store
363 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
364 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
365 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
366 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
367 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
368 multi,atomic,syncloop,nop,ghost,multimem"
369 (cond [(eq_attr "jal" "!unset") (const_string "call")
370 (eq_attr "got" "load") (const_string "load")
372 (eq_attr "alu_type" "add,sub") (const_string "arith")
374 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
376 ;; If a doubleword move uses these expensive instructions,
377 ;; it is usually better to schedule them in the same way
378 ;; as the singleword form, rather than as "multi".
379 (eq_attr "move_type" "load") (const_string "load")
380 (eq_attr "move_type" "fpload") (const_string "fpload")
381 (eq_attr "move_type" "store") (const_string "store")
382 (eq_attr "move_type" "fpstore") (const_string "fpstore")
383 (eq_attr "move_type" "mtc") (const_string "mtc")
384 (eq_attr "move_type" "mfc") (const_string "mfc")
385 (eq_attr "move_type" "mtlo") (const_string "mtlo")
386 (eq_attr "move_type" "mflo") (const_string "mflo")
388 ;; These types of move are always single insns.
389 (eq_attr "move_type" "imul") (const_string "imul")
390 (eq_attr "move_type" "fmove") (const_string "fmove")
391 (eq_attr "move_type" "loadpool") (const_string "load")
392 (eq_attr "move_type" "signext") (const_string "signext")
393 (eq_attr "move_type" "ext_ins") (const_string "arith")
394 (eq_attr "move_type" "arith") (const_string "arith")
395 (eq_attr "move_type" "logical") (const_string "logical")
396 (eq_attr "move_type" "sll0") (const_string "shift")
397 (eq_attr "move_type" "andi") (const_string "logical")
399 ;; These types of move are always split.
400 (eq_attr "move_type" "constN,shift_shift")
401 (const_string "multi")
403 ;; These types of move are split for doubleword modes only.
404 (and (eq_attr "move_type" "move,const")
405 (eq_attr "dword_mode" "yes"))
406 (const_string "multi")
407 (eq_attr "move_type" "move") (const_string "move")
408 (eq_attr "move_type" "const") (const_string "const")
409 (eq_attr "sync_mem" "!none") (const_string "syncloop")]
410 (const_string "unknown")))
412 ;; Mode for conversion types (fcvt)
413 ;; I2S integer to float single (SI/DI to SF)
414 ;; I2D integer to float double (SI/DI to DF)
415 ;; S2I float to integer (SF to SI/DI)
416 ;; D2I float to integer (DF to SI/DI)
417 ;; D2S double to float single
418 ;; S2D float single to double
420 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
421 (const_string "unknown"))
423 ;; Is this an extended instruction in mips16 mode?
424 (define_attr "extended_mips16" "no,yes"
425 (if_then_else (ior ;; In general, constant-pool loads are extended
426 ;; instructions. We don't yet optimize for 16-bit
427 ;; PC-relative references.
428 (eq_attr "move_type" "sll0,loadpool")
429 (eq_attr "jal" "direct")
430 (eq_attr "got" "load"))
432 (const_string "no")))
434 (define_attr "compression" "none,all,micromips32,micromips"
435 (const_string "none"))
437 (define_attr "enabled" "no,yes"
438 (cond [;; The o32 FPXX and FP64A ABI extensions prohibit direct moves between
439 ;; GR_REG and FR_REG for 64-bit values.
440 (and (eq_attr "move_type" "mtc,mfc")
441 (match_test "(TARGET_FLOATXX && !ISA_HAS_MXHC1)
442 || TARGET_O32_FP64A_ABI")
443 (eq_attr "dword_mode" "yes"))
445 (and (eq_attr "compression" "micromips32,micromips")
446 (match_test "!TARGET_MICROMIPS"))
448 (const_string "yes")))
450 ;; The number of individual instructions that a non-branch pattern generates,
451 ;; using units of BASE_INSN_LENGTH.
452 (define_attr "insn_count" ""
453 (cond [;; "Ghost" instructions occupy no space.
454 (eq_attr "type" "ghost")
457 ;; Extended instructions count as 2.
458 (and (eq_attr "extended_mips16" "yes")
459 (match_test "TARGET_MIPS16"))
462 ;; A GOT load followed by an add of $gp. This is not used for MIPS16.
463 (eq_attr "got" "xgot_high")
466 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
467 ;; They are extended instructions on MIPS16 targets.
468 (eq_attr "move_type" "shift_shift")
469 (if_then_else (match_test "TARGET_MIPS16")
473 ;; Check for doubleword moves that are decomposed into two
474 ;; instructions. The individual instructions are unextended
476 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
477 (eq_attr "dword_mode" "yes"))
480 ;; Constants, loads and stores are handled by external routines.
481 (and (eq_attr "move_type" "const,constN")
482 (eq_attr "dword_mode" "yes"))
483 (symbol_ref "mips_split_const_insns (operands[1])")
484 (eq_attr "move_type" "const,constN")
485 (symbol_ref "mips_const_insns (operands[1])")
486 (eq_attr "move_type" "load,fpload")
487 (symbol_ref "mips_load_store_insns (operands[1], insn)")
488 (eq_attr "move_type" "store,fpstore")
489 (symbol_ref "mips_load_store_insns (operands[0], insn)
490 + (TARGET_FIX_24K ? 1 : 0)")
492 ;; In the worst case, a call macro will take 8 instructions:
494 ;; lui $25,%call_hi(FOO)
496 ;; lw $25,%call_lo(FOO)($25)
502 (eq_attr "jal_macro" "yes")
505 ;; Various VR4120 errata require a nop to be inserted after a macc
506 ;; instruction. The assembler does this for us, so account for
507 ;; the worst-case length here.
508 (and (eq_attr "type" "imadd")
509 (match_test "TARGET_FIX_VR4120"))
512 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
513 ;; the result of the second one is missed. The assembler should work
514 ;; around this by inserting a nop after the first dmult.
515 (and (eq_attr "type" "imul,imul3")
516 (eq_attr "mode" "DI")
517 (match_test "TARGET_FIX_VR4120"))
520 (eq_attr "type" "idiv,idiv3")
521 (symbol_ref "mips_idiv_insns ()")
523 (not (eq_attr "sync_mem" "none"))
524 (symbol_ref "mips_sync_loop_insns (insn, operands)")]
527 ;; Length of instruction in bytes. The default is derived from "insn_count",
528 ;; but there are special cases for branches (which must be handled here)
529 ;; and for compressed single instructions.
530 (define_attr "length" ""
531 (cond [(and (ior (eq_attr "compression" "micromips,all")
532 (and (eq_attr "compression" "micromips32")
533 (eq_attr "mode" "SI,SF")))
534 (eq_attr "dword_mode" "no")
535 (match_test "TARGET_MICROMIPS"))
538 ;; Direct microMIPS branch instructions have a range of
539 ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc].
540 ;; If a branch is outside this range, we have a choice of two
543 ;; For PIC, an out-of-range branch like:
548 ;; becomes the equivalent of:
557 ;; The non-PIC case is similar except that we use a direct
558 ;; jump instead of an la/jr pair. Since the target of this
559 ;; jump is an absolute 28-bit bit address (the other bits
560 ;; coming from the address of the delay slot) this form cannot
561 ;; cross a 256MB boundary. We could provide the option of
562 ;; using la/jr in this case too, but we do not do so at
565 ;; The value we specify here does not account for the delay slot
566 ;; instruction, whose length is added separately. If the RTL
567 ;; pattern has no explicit delay slot, mips_adjust_insn_length
568 ;; will add the length of the implicit nop. The range of
569 ;; [-0x20000, 0x1fffc] from the address of the delay slot
570 ;; therefore translates to a range of:
572 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
573 ;; == [-0x1fffc, 0x1fff8]
575 ;; from the shorten_branches reference address.
576 (and (eq_attr "type" "branch")
577 (not (match_test "TARGET_MIPS16")))
578 (cond [;; Any variant can handle the 17-bit range.
579 (and (le (minus (match_dup 0) (pc)) (const_int 65532))
580 (le (minus (pc) (match_dup 0)) (const_int 65534)))
583 ;; The 18-bit range is OK other than for microMIPS.
584 (and (not (match_test "TARGET_MICROMIPS"))
585 (and (le (minus (match_dup 0) (pc)) (const_int 131064))
586 (le (minus (pc) (match_dup 0)) (const_int 131068))))
589 ;; The non-PIC case: branch, first delay slot, and J.
590 (match_test "TARGET_ABSOLUTE_JUMPS")
593 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
594 ;; mips_adjust_insn_length substitutes the correct length.
596 ;; Note that we can't simply use (symbol_ref ...) here
597 ;; because genattrtab needs to know the maximum length
599 (const_int MAX_PIC_BRANCH_LENGTH))
601 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
602 ;; from the address of the following instruction, which leads
605 ;; [-(0x100 - sizeof (branch)), 0xfe]
608 ;; from the shorten_branches reference address. Extended branches
609 ;; likewise have a range of [-0x10000, 0xfffe] from the address
610 ;; of the following instruction, which leads to a range of:
612 ;; [-(0x10000 - sizeof (branch)), 0xfffe]
613 ;; == [-0xfffc, 0xfffe]
615 ;; from the reference address.
617 ;; When a branch is out of range, mips_reorg splits it into a form
618 ;; that uses in-range branches. There are four basic sequences:
620 ;; (1) Absolute addressing with a readable text segment
621 ;; (32-bit addresses):
624 ;; move $1,$2 2 bytes
625 ;; lw $2,label 2 bytes
627 ;; move $2,$1 2 bytes
628 ;; .align 2 0 or 2 bytes
630 ;; .word target 4 bytes
632 ;; (16 bytes in the worst case)
634 ;; (2) Absolute addressing with a readable text segment
635 ;; (64-bit addresses):
638 ;; move $1,$2 2 bytes
639 ;; ld $2,label 2 bytes
641 ;; move $2,$1 2 bytes
642 ;; .align 3 0 to 6 bytes
644 ;; .dword target 8 bytes
646 ;; (24 bytes in the worst case)
648 ;; (3) Absolute addressing without a readable text segment
649 ;; (which requires 32-bit addresses at present):
652 ;; move $1,$2 2 bytes
653 ;; lui $2,%hi(target) 4 bytes
656 ;; addiu $2,%lo(target) 4 bytes
658 ;; move $2,$1 2 bytes
662 ;; (4) PIC addressing (which requires 32-bit addresses at present):
665 ;; move $1,$2 2 bytes
666 ;; lw $2,cprestore 0, 2 or 4 bytes
667 ;; lw $2,%got(target)($2) 4 bytes
668 ;; addiu $2,%lo(target) 4 bytes
670 ;; move $2,$1 2 bytes
672 ;; (20 bytes in the worst case)
673 (and (eq_attr "type" "branch")
674 (match_test "TARGET_MIPS16"))
675 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
676 (le (minus (pc) (match_dup 0)) (const_int 254)))
678 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
679 (le (minus (pc) (match_dup 0)) (const_int 65532)))
681 (and (match_test "TARGET_ABICALLS")
682 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
684 (match_test "Pmode == SImode")
687 (symbol_ref "get_attr_insn_count (insn) * BASE_INSN_LENGTH")))
689 ;; Attribute describing the processor.
690 (define_enum_attr "cpu" "processor"
691 (const (symbol_ref "mips_tune")))
693 ;; The type of hardware hazard associated with this instruction.
694 ;; DELAY means that the next instruction cannot read the result
695 ;; of this one. HILO means that the next two instructions cannot
696 ;; write to HI or LO.
697 (define_attr "hazard" "none,delay,hilo"
698 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
699 (match_test "ISA_HAS_LOAD_DELAY"))
700 (const_string "delay")
702 (and (eq_attr "type" "mfc,mtc")
703 (match_test "ISA_HAS_XFER_DELAY"))
704 (const_string "delay")
706 (and (eq_attr "type" "fcmp")
707 (match_test "ISA_HAS_FCMP_DELAY"))
708 (const_string "delay")
710 ;; The r4000 multiplication patterns include an mflo instruction.
711 (and (eq_attr "type" "imul")
712 (match_test "TARGET_FIX_R4000"))
713 (const_string "hilo")
715 (and (eq_attr "type" "mfhi,mflo")
716 (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
717 (const_string "hilo")]
718 (const_string "none")))
720 ;; Can the instruction be put into a delay slot?
721 (define_attr "can_delay" "no,yes"
722 (if_then_else (and (eq_attr "type" "!branch,call,jump")
723 (eq_attr "hazard" "none")
724 (match_test "get_attr_insn_count (insn) == 1"))
726 (const_string "no")))
728 ;; Attribute defining whether or not we can use the branch-likely
730 (define_attr "branch_likely" "no,yes"
731 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
733 (const_string "no")))
735 ;; True if an instruction might assign to hi or lo when reloaded.
736 ;; This is used by the TUNE_MACC_CHAINS code.
737 (define_attr "may_clobber_hilo" "no,yes"
738 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
740 (const_string "no")))
742 ;; Describe a user's asm statement.
743 (define_asm_attributes
744 [(set_attr "type" "multi")
745 (set_attr "can_delay" "no")])
747 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
748 ;; from the same template.
749 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
751 ;; A copy of GPR that can be used when a pattern has two independent
753 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
755 (define_mode_iterator MOVEP1 [SI SF])
756 (define_mode_iterator MOVEP2 [SI SF])
757 (define_mode_iterator JOIN_MODE [HI
759 (SF "TARGET_HARD_FLOAT")
760 (DF "TARGET_HARD_FLOAT
761 && TARGET_DOUBLE_FLOAT")])
763 ;; This mode iterator allows :HILO to be used as the mode of the
764 ;; concatenated HI and LO registers.
765 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
767 ;; This mode iterator allows :P to be used for patterns that operate on
768 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
769 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
771 ;; This mode iterator allows :MOVECC to be used anywhere that a
772 ;; conditional-move-type condition is needed.
773 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
774 (CC "TARGET_HARD_FLOAT
775 && !TARGET_LOONGSON_2EF
776 && !TARGET_MIPS5900")])
778 ;; This mode iterator allows :FPCC to be used anywhere that an FP condition
780 (define_mode_iterator FPCC [(CC "!ISA_HAS_CCF")
781 (CCF "ISA_HAS_CCF")])
783 ;; 32-bit integer moves for which we provide move patterns.
784 (define_mode_iterator IMOVE32
793 (V4UQQ "TARGET_DSP")])
795 ;; 64-bit modes for which we provide move patterns.
796 (define_mode_iterator MOVE64
798 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
799 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
800 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
801 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
803 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
804 (define_mode_iterator MOVE128 [TI TF])
806 ;; This mode iterator allows the QI and HI extension patterns to be
807 ;; defined from the same template.
808 (define_mode_iterator SHORT [QI HI])
810 ;; Likewise the 64-bit truncate-and-shift patterns.
811 (define_mode_iterator SUBDI [QI HI SI])
813 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
814 ;; floating-point mode is allowed.
815 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
816 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
817 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
819 ;; Like ANYF, but only applies to scalar modes.
820 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
821 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
823 ;; A floating-point mode for which moves involving FPRs may need to be split.
824 (define_mode_iterator SPLITF
825 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
826 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
827 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
828 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
829 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
830 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
831 (TF "TARGET_64BIT && TARGET_FLOAT64")])
833 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
834 ;; 32-bit version and "dsubu" in the 64-bit version.
835 (define_mode_attr d [(SI "") (DI "d")
836 (QQ "") (HQ "") (SQ "") (DQ "d")
837 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
838 (HA "") (SA "") (DA "d")
839 (UHA "") (USA "") (UDA "d")])
841 ;; Same as d but upper-case.
842 (define_mode_attr D [(SI "") (DI "D")
843 (QQ "") (HQ "") (SQ "") (DQ "D")
844 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
845 (HA "") (SA "") (DA "D")
846 (UHA "") (USA "") (UDA "D")])
848 ;; This attribute gives the length suffix for a load or store instruction.
849 ;; The same suffixes work for zero and sign extensions.
850 (define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
851 (define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
853 ;; This attributes gives the mode mask of a SHORT.
854 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
856 ;; Mode attributes for GPR loads.
857 (define_mode_attr load [(SI "lw") (DI "ld")])
858 ;; Instruction names for stores.
859 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
861 ;; Similarly for MIPS IV indexed FPR loads and stores.
862 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
863 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
865 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
866 ;; are different. Some forms of unextended addiu have an 8-bit immediate
867 ;; field but the equivalent daddiu has only a 5-bit field.
868 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
870 ;; This attribute gives the best constraint to use for registers of
872 (define_mode_attr reg [(SI "d") (DI "d") (CC "z") (CCF "f")])
874 ;; This attribute gives the format suffix for floating-point operations.
875 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
877 ;; This attribute gives the upper-case mode name for one unit of a
878 ;; floating-point mode.
879 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
881 ;; This attribute gives the integer mode that has the same size as a
883 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
884 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
885 (HA "HI") (SA "SI") (DA "DI")
886 (UHA "HI") (USA "SI") (UDA "DI")
887 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
888 (V2HQ "SI") (V2HA "SI")])
890 ;; This attribute gives the integer mode that has half the size of
891 ;; the controlling mode.
892 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
893 (V2SI "SI") (V4HI "SI") (V8QI "SI")
896 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
898 ;; In certain cases, div.s and div.ps may have a rounding error
899 ;; and/or wrong inexact flag.
901 ;; Therefore, we only allow div.s if not working around SB-1 rev2
902 ;; errata or if a slight loss of precision is OK.
903 (define_mode_attr divide_condition
904 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
905 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
907 ;; This attribute gives the conditions under which SQRT.fmt instructions
909 (define_mode_attr sqrt_condition
910 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
912 ;; This attribute provides the correct mnemonic for each FP condition mode.
913 (define_mode_attr fpcmp [(CC "c") (CCF "cmp")])
915 ;; This code iterator allows signed and unsigned widening multiplications
916 ;; to use the same template.
917 (define_code_iterator any_extend [sign_extend zero_extend])
919 ;; This code iterator allows the two right shift instructions to be
920 ;; generated from the same template.
921 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
923 ;; This code iterator allows the three shift instructions to be generated
924 ;; from the same template.
925 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
927 ;; This code iterator allows unsigned and signed division to be generated
928 ;; from the same template.
929 (define_code_iterator any_div [div udiv])
931 ;; This code iterator allows unsigned and signed modulus to be generated
932 ;; from the same template.
933 (define_code_iterator any_mod [mod umod])
935 ;; This code iterator allows all native floating-point comparisons to be
936 ;; generated from the same template.
937 (define_code_iterator fcond [unordered uneq unlt unle eq lt le
938 (ordered "ISA_HAS_CCF")
942 ;; This code iterator is used for comparisons that can be implemented
943 ;; by swapping the operands.
944 (define_code_iterator swapped_fcond [ge gt unge ungt])
946 ;; Equality operators.
947 (define_code_iterator equality_op [eq ne])
949 ;; These code iterators allow the signed and unsigned scc operations to use
950 ;; the same template.
951 (define_code_iterator any_gt [gt gtu])
952 (define_code_iterator any_ge [ge geu])
953 (define_code_iterator any_lt [lt ltu])
954 (define_code_iterator any_le [le leu])
956 (define_code_iterator any_return [return simple_return])
958 ;; <u> expands to an empty string when doing a signed operation and
959 ;; "u" when doing an unsigned operation.
960 (define_code_attr u [(sign_extend "") (zero_extend "u")
968 ;; <U> is like <u> except uppercase.
969 (define_code_attr U [(sign_extend "") (zero_extend "U")])
971 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
972 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
974 ;; <optab> expands to the name of the optab for a particular code.
975 (define_code_attr optab [(ashift "ashl")
984 (simple_return "simple_return")])
986 ;; <insn> expands to the name of the insn that implements a particular code.
987 (define_code_attr insn [(ashift "sll")
996 ;; <immediate_insn> expands to the name of the insn that implements
997 ;; a particular code to operate on immediate values.
998 (define_code_attr immediate_insn [(ior "ori")
1002 (define_code_attr shift_compression [(ashift "micromips32")
1003 (lshiftrt "micromips32")
1006 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
1007 (define_code_attr fcond [(unordered "un")
1018 ;; Similar, but for swapped conditions.
1019 (define_code_attr swapped_fcond [(ge "le")
1024 ;; The value of the bit when the branch is taken for branch_bit patterns.
1025 ;; Comparison is always against zero so this depends on the operator.
1026 (define_code_attr bbv [(eq "0") (ne "1")])
1028 ;; This is the inverse value of bbv.
1029 (define_code_attr bbinv [(eq "1") (ne "0")])
1031 ;; The sel mnemonic to use depending on the condition test.
1032 (define_code_attr sel [(eq "seleqz") (ne "selnez")])
1033 (define_code_attr selinv [(eq "selnez") (ne "seleqz")])
1035 ;; .........................
1037 ;; Branch, call and jump delay slots
1039 ;; .........................
1041 (define_delay (and (eq_attr "type" "branch")
1042 (not (match_test "TARGET_MIPS16"))
1043 (eq_attr "branch_likely" "yes"))
1044 [(eq_attr "can_delay" "yes")
1046 (eq_attr "can_delay" "yes")])
1048 ;; Branches that don't have likely variants do not annul on false.
1049 (define_delay (and (eq_attr "type" "branch")
1050 (not (match_test "TARGET_MIPS16"))
1051 (eq_attr "branch_likely" "no"))
1052 [(eq_attr "can_delay" "yes")
1056 (define_delay (eq_attr "type" "jump")
1057 [(eq_attr "can_delay" "yes")
1061 (define_delay (and (eq_attr "type" "call")
1062 (eq_attr "jal_macro" "no"))
1063 [(eq_attr "can_delay" "yes")
1067 ;; Pipeline descriptions.
1069 ;; generic.md provides a fallback for processors without a specific
1070 ;; pipeline description. It is derived from the old define_function_unit
1071 ;; version and uses the "alu" and "imuldiv" units declared below.
1073 ;; Some of the processor-specific files are also derived from old
1074 ;; define_function_unit descriptions and simply override the parts of
1075 ;; generic.md that don't apply. The other processor-specific files
1076 ;; are self-contained.
1077 (define_automaton "alu,imuldiv")
1079 (define_cpu_unit "alu" "alu")
1080 (define_cpu_unit "imuldiv" "imuldiv")
1082 ;; Ghost instructions produce no real code and introduce no hazards.
1083 ;; They exist purely to express an effect on dataflow.
1084 (define_insn_reservation "ghost" 0
1085 (eq_attr "type" "ghost")
1088 (include "p5600.md")
1106 (include "10000.md")
1107 (include "loongson2ef.md")
1108 (include "loongson3a.md")
1109 (include "octeon.md")
1111 (include "sr71k.md")
1114 (include "generic.md")
1117 ;; ....................
1119 ;; CONDITIONAL TRAPS
1121 ;; ....................
1125 [(trap_if (const_int 1) (const_int 0))]
1128 if (ISA_HAS_COND_TRAP)
1129 return "teq\t$0,$0";
1130 else if (TARGET_MIPS16)
1135 [(set_attr "type" "trap")])
1137 (define_expand "ctrap<mode>4"
1138 [(trap_if (match_operator 0 "comparison_operator"
1139 [(match_operand:GPR 1 "reg_or_0_operand")
1140 (match_operand:GPR 2 "arith_operand")])
1141 (match_operand 3 "const_0_operand"))]
1142 "ISA_HAS_COND_TRAPI || ISA_HAS_COND_TRAP"
1144 mips_expand_conditional_trap (operands[0]);
1148 (define_insn "*conditional_trap_reg<mode>"
1149 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1150 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1151 (match_operand:GPR 2 "reg_or_0_operand" "dJ")])
1153 "ISA_HAS_COND_TRAP && !ISA_HAS_COND_TRAPI"
1155 [(set_attr "type" "trap")])
1157 (define_insn "*conditional_trap<mode>"
1158 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1159 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1160 (match_operand:GPR 2 "arith_operand" "dI")])
1162 "ISA_HAS_COND_TRAPI"
1164 [(set_attr "type" "trap")])
1167 ;; ....................
1171 ;; ....................
1174 (define_insn "add<mode>3"
1175 [(set (match_operand:ANYF 0 "register_operand" "=f")
1176 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1177 (match_operand:ANYF 2 "register_operand" "f")))]
1179 "add.<fmt>\t%0,%1,%2"
1180 [(set_attr "type" "fadd")
1181 (set_attr "mode" "<UNITMODE>")])
1183 (define_expand "add<mode>3"
1184 [(set (match_operand:GPR 0 "register_operand")
1185 (plus:GPR (match_operand:GPR 1 "register_operand")
1186 (match_operand:GPR 2 "arith_operand")))]
1189 (define_insn "*add<mode>3"
1190 [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!u,!ks,!d,d")
1191 (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,!ks,!ks,0,d")
1192 (match_operand:GPR 2 "arith_operand" "!u,d,Uead,Uuw6,Uesp,Usb4,Q")))]
1195 if (which_alternative == 0
1196 || which_alternative == 1)
1197 return "<d>addu\t%0,%1,%2";
1199 return "<d>addiu\t%0,%1,%2";
1201 [(set_attr "alu_type" "add")
1202 (set_attr "compression" "micromips32,*,micromips32,micromips32,micromips32,micromips32,*")
1203 (set_attr "mode" "<MODE>")])
1205 (define_insn "*add<mode>3_mips16"
1206 [(set (match_operand:GPR 0 "register_operand" "=ks,ks,d,d,d,d,d,d,d")
1207 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,ks,ks,0,0,d,d,d")
1208 (match_operand:GPR 2 "arith_operand" "Usd8,Q,Uuw<si8_di5>,Q,Usb<si8_di5>,Q,Usb4,O,d")))]
1220 [(set_attr "alu_type" "add")
1221 (set_attr "mode" "<MODE>")
1222 (set_attr "extended_mips16" "no,yes,no,yes,no,yes,no,yes,no")])
1224 ;; On the mips16, we can sometimes split an add of a constant which is
1225 ;; a 4 byte instruction into two adds which are both 2 byte
1226 ;; instructions. There are two cases: one where we are adding a
1227 ;; constant plus a register to another register, and one where we are
1228 ;; simply adding a constant to a register.
1231 [(set (match_operand:SI 0 "d_operand")
1232 (plus:SI (match_dup 0)
1233 (match_operand:SI 1 "const_int_operand")))]
1234 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1235 && ((INTVAL (operands[1]) > 0x7f
1236 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1237 || (INTVAL (operands[1]) < - 0x80
1238 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1239 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1240 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1242 HOST_WIDE_INT val = INTVAL (operands[1]);
1246 operands[1] = GEN_INT (0x7f);
1247 operands[2] = GEN_INT (val - 0x7f);
1251 operands[1] = GEN_INT (- 0x80);
1252 operands[2] = GEN_INT (val + 0x80);
1257 [(set (match_operand:SI 0 "d_operand")
1258 (plus:SI (match_operand:SI 1 "d_operand")
1259 (match_operand:SI 2 "const_int_operand")))]
1260 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1261 && REGNO (operands[0]) != REGNO (operands[1])
1262 && ((INTVAL (operands[2]) > 0x7
1263 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1264 || (INTVAL (operands[2]) < - 0x8
1265 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1266 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1267 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1269 HOST_WIDE_INT val = INTVAL (operands[2]);
1273 operands[2] = GEN_INT (0x7);
1274 operands[3] = GEN_INT (val - 0x7);
1278 operands[2] = GEN_INT (- 0x8);
1279 operands[3] = GEN_INT (val + 0x8);
1284 [(set (match_operand:DI 0 "d_operand")
1285 (plus:DI (match_dup 0)
1286 (match_operand:DI 1 "const_int_operand")))]
1287 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1288 && ((INTVAL (operands[1]) > 0xf
1289 && INTVAL (operands[1]) <= 0xf + 0xf)
1290 || (INTVAL (operands[1]) < - 0x10
1291 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1292 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1293 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1295 HOST_WIDE_INT val = INTVAL (operands[1]);
1299 operands[1] = GEN_INT (0xf);
1300 operands[2] = GEN_INT (val - 0xf);
1304 operands[1] = GEN_INT (- 0x10);
1305 operands[2] = GEN_INT (val + 0x10);
1310 [(set (match_operand:DI 0 "d_operand")
1311 (plus:DI (match_operand:DI 1 "d_operand")
1312 (match_operand:DI 2 "const_int_operand")))]
1313 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1314 && REGNO (operands[0]) != REGNO (operands[1])
1315 && ((INTVAL (operands[2]) > 0x7
1316 && INTVAL (operands[2]) <= 0x7 + 0xf)
1317 || (INTVAL (operands[2]) < - 0x8
1318 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1319 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1320 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1322 HOST_WIDE_INT val = INTVAL (operands[2]);
1326 operands[2] = GEN_INT (0x7);
1327 operands[3] = GEN_INT (val - 0x7);
1331 operands[2] = GEN_INT (- 0x8);
1332 operands[3] = GEN_INT (val + 0x8);
1336 (define_insn "*addsi3_extended"
1337 [(set (match_operand:DI 0 "register_operand" "=d,d")
1339 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1340 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1341 "TARGET_64BIT && !TARGET_MIPS16"
1345 [(set_attr "alu_type" "add")
1346 (set_attr "mode" "SI")])
1348 ;; Split this insn so that the addiu splitters can have a crack at it.
1349 ;; Use a conservative length estimate until the split.
1350 (define_insn_and_split "*addsi3_extended_mips16"
1351 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1353 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1354 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1355 "TARGET_64BIT && TARGET_MIPS16"
1357 "&& reload_completed"
1358 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1359 { operands[3] = gen_lowpart (SImode, operands[0]); }
1360 [(set_attr "alu_type" "add")
1361 (set_attr "mode" "SI")
1362 (set_attr "extended_mips16" "yes")])
1364 ;; Combiner patterns for unsigned byte-add.
1366 (define_insn "*baddu_si_eb"
1367 [(set (match_operand:SI 0 "register_operand" "=d")
1370 (plus:SI (match_operand:SI 1 "register_operand" "d")
1371 (match_operand:SI 2 "register_operand" "d")) 3)))]
1372 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1374 [(set_attr "alu_type" "add")])
1376 (define_insn "*baddu_si_el"
1377 [(set (match_operand:SI 0 "register_operand" "=d")
1380 (plus:SI (match_operand:SI 1 "register_operand" "d")
1381 (match_operand:SI 2 "register_operand" "d")) 0)))]
1382 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1384 [(set_attr "alu_type" "add")])
1386 (define_insn "*baddu_di<mode>"
1387 [(set (match_operand:GPR 0 "register_operand" "=d")
1390 (plus:DI (match_operand:DI 1 "register_operand" "d")
1391 (match_operand:DI 2 "register_operand" "d")))))]
1392 "ISA_HAS_BADDU && TARGET_64BIT"
1394 [(set_attr "alu_type" "add")])
1397 ;; ....................
1401 ;; ....................
1404 (define_insn "sub<mode>3"
1405 [(set (match_operand:ANYF 0 "register_operand" "=f")
1406 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1407 (match_operand:ANYF 2 "register_operand" "f")))]
1409 "sub.<fmt>\t%0,%1,%2"
1410 [(set_attr "type" "fadd")
1411 (set_attr "mode" "<UNITMODE>")])
1413 (define_insn "sub<mode>3"
1414 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
1415 (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d")
1416 (match_operand:GPR 2 "register_operand" "!u,d")))]
1419 [(set_attr "alu_type" "sub")
1420 (set_attr "compression" "micromips32,*")
1421 (set_attr "mode" "<MODE>")])
1423 (define_insn "*subsi3_extended"
1424 [(set (match_operand:DI 0 "register_operand" "=d")
1426 (minus:SI (match_operand:SI 1 "register_operand" "d")
1427 (match_operand:SI 2 "register_operand" "d"))))]
1430 [(set_attr "alu_type" "sub")
1431 (set_attr "mode" "DI")])
1434 ;; ....................
1438 ;; ....................
1441 (define_expand "mul<mode>3"
1442 [(set (match_operand:SCALARF 0 "register_operand")
1443 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1444 (match_operand:SCALARF 2 "register_operand")))]
1448 (define_insn "*mul<mode>3"
1449 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1450 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1451 (match_operand:SCALARF 2 "register_operand" "f")))]
1452 "!TARGET_4300_MUL_FIX"
1453 "mul.<fmt>\t%0,%1,%2"
1454 [(set_attr "type" "fmul")
1455 (set_attr "mode" "<MODE>")])
1457 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1458 ;; operands may corrupt immediately following multiplies. This is a
1459 ;; simple fix to insert NOPs.
1461 (define_insn "*mul<mode>3_r4300"
1462 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1463 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1464 (match_operand:SCALARF 2 "register_operand" "f")))]
1465 "TARGET_4300_MUL_FIX"
1466 "mul.<fmt>\t%0,%1,%2\;nop"
1467 [(set_attr "type" "fmul")
1468 (set_attr "mode" "<MODE>")
1469 (set_attr "insn_count" "2")])
1471 (define_insn "mulv2sf3"
1472 [(set (match_operand:V2SF 0 "register_operand" "=f")
1473 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1474 (match_operand:V2SF 2 "register_operand" "f")))]
1475 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1477 [(set_attr "type" "fmul")
1478 (set_attr "mode" "SF")])
1480 ;; The original R4000 has a cpu bug. If a double-word or a variable
1481 ;; shift executes while an integer multiplication is in progress, the
1482 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1483 ;; with the mult on the R4000.
1485 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1486 ;; (also valid for MIPS R4000MC processors):
1488 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1489 ;; this errata description.
1490 ;; The following code sequence causes the R4000 to incorrectly
1491 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1492 ;; instruction. If the dsra32 instruction is executed during an
1493 ;; integer multiply, the dsra32 will only shift by the amount in
1494 ;; specified in the instruction rather than the amount plus 32
1496 ;; instruction 1: mult rs,rt integer multiply
1497 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1498 ;; right arithmetic + 32
1499 ;; Workaround: A dsra32 instruction placed after an integer
1500 ;; multiply should not be one of the 11 instructions after the
1501 ;; multiply instruction."
1505 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1506 ;; the following description.
1507 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1508 ;; 64-bit versions) may produce incorrect results under the
1509 ;; following conditions:
1510 ;; 1) An integer multiply is currently executing
1511 ;; 2) These types of shift instructions are executed immediately
1512 ;; following an integer divide instruction.
1514 ;; 1) Make sure no integer multiply is running wihen these
1515 ;; instruction are executed. If this cannot be predicted at
1516 ;; compile time, then insert a "mfhi" to R0 instruction
1517 ;; immediately after the integer multiply instruction. This
1518 ;; will cause the integer multiply to complete before the shift
1520 ;; 2) Separate integer divide and these two classes of shift
1521 ;; instructions by another instruction or a noop."
1523 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1526 (define_expand "mul<mode>3"
1527 [(set (match_operand:GPR 0 "register_operand")
1528 (mult:GPR (match_operand:GPR 1 "register_operand")
1529 (match_operand:GPR 2 "register_operand")))]
1530 "ISA_HAS_<D>MULT || ISA_HAS_R6<D>MUL"
1534 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>MUL)
1535 emit_insn (gen_mul<mode>3_mul3_nohilo (operands[0], operands[1],
1537 else if (ISA_HAS_<D>MUL3)
1538 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1539 else if (TARGET_MIPS16)
1541 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
1542 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2]));
1543 emit_move_insn (operands[0], lo);
1545 else if (TARGET_FIX_R4000)
1546 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1549 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1553 (define_insn "mul<mode>3_mul3_nohilo"
1554 [(set (match_operand:GPR 0 "register_operand" "=d")
1555 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1556 (match_operand:GPR 2 "register_operand" "d")))]
1557 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>MUL"
1559 if (TARGET_LOONGSON_2EF)
1560 return "<d>multu.g\t%0,%1,%2";
1561 else if (TARGET_LOONGSON_3A)
1562 return "gs<d>multu\t%0,%1,%2";
1564 return "<d>mul\t%0,%1,%2";
1566 [(set_attr "type" "imul3nc")
1567 (set_attr "mode" "<MODE>")])
1569 (define_insn "mul<mode>3_mul3"
1570 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1571 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1572 (match_operand:GPR 2 "register_operand" "d,d")))
1573 (clobber (match_scratch:GPR 3 "=l,X"))]
1576 if (which_alternative == 1)
1577 return "<d>mult\t%1,%2";
1578 if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900))
1579 return "mult\t%0,%1,%2";
1580 return "<d>mul\t%0,%1,%2";
1582 [(set_attr "type" "imul3,imul")
1583 (set_attr "mode" "<MODE>")])
1585 ;; If a register gets allocated to LO, and we spill to memory, the reload
1586 ;; will include a move from LO to a GPR. Merge it into the multiplication
1587 ;; if it can set the GPR directly.
1590 ;; Operand 1: GPR (1st multiplication operand)
1591 ;; Operand 2: GPR (2nd multiplication operand)
1592 ;; Operand 3: GPR (destination)
1595 [(set (match_operand:SI 0 "lo_operand")
1596 (mult:SI (match_operand:SI 1 "d_operand")
1597 (match_operand:SI 2 "d_operand")))
1598 (clobber (scratch:SI))])
1599 (set (match_operand:SI 3 "d_operand")
1601 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1604 (mult:SI (match_dup 1)
1606 (clobber (match_dup 0))])])
1608 (define_insn "mul<mode>3_internal"
1609 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
1610 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1611 (match_operand:GPR 2 "register_operand" "d")))]
1612 "ISA_HAS_<D>MULT && !TARGET_FIX_R4000"
1614 [(set_attr "type" "imul")
1615 (set_attr "mode" "<MODE>")])
1617 (define_insn "mul<mode>3_r4000"
1618 [(set (match_operand:GPR 0 "register_operand" "=d")
1619 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1620 (match_operand:GPR 2 "register_operand" "d")))
1621 (clobber (match_scratch:GPR 3 "=l"))]
1622 "ISA_HAS_<D>MULT && TARGET_FIX_R4000"
1623 "<d>mult\t%1,%2\;mflo\t%0"
1624 [(set_attr "type" "imul")
1625 (set_attr "mode" "<MODE>")
1626 (set_attr "insn_count" "2")])
1628 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1629 ;; of "mult; mflo". They have the same latency, but the first form gives
1630 ;; us an extra cycle to compute the operands.
1633 ;; Operand 1: GPR (1st multiplication operand)
1634 ;; Operand 2: GPR (2nd multiplication operand)
1635 ;; Operand 3: GPR (destination)
1637 [(set (match_operand:SI 0 "lo_operand")
1638 (mult:SI (match_operand:SI 1 "d_operand")
1639 (match_operand:SI 2 "d_operand")))
1640 (set (match_operand:SI 3 "d_operand")
1642 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1647 (plus:SI (mult:SI (match_dup 1)
1651 (plus:SI (mult:SI (match_dup 1)
1655 ;; Multiply-accumulate patterns
1657 ;; This pattern is first matched by combine, which tries to use the
1658 ;; pattern wherever it can. We don't know until later whether it
1659 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1660 ;; so we need to keep both options open.
1662 ;; The second alternative has a "?" marker because it is generally
1663 ;; one instruction more costly than the first alternative. This "?"
1664 ;; marker is enough to convey the relative costs to the register
1667 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1668 ;; reloads of the other operands, even though operands 4 and 5 need no
1669 ;; copy instructions. Reload therefore thinks that the second alternative
1670 ;; is two reloads more costly than the first. We add "*?*?" to the first
1671 ;; alternative as a counterweight.
1673 ;; LRA simulates reload but the cost of reloading scratches is lower
1674 ;; than of the classic reload. For the time being, removing the counterweight
1675 ;; for LRA is more profitable.
1676 (define_insn "*mul_acc_si"
1677 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?")
1678 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1679 (match_operand:SI 2 "register_operand" "d,d,d"))
1680 (match_operand:SI 3 "register_operand" "0,0,d")))
1681 (clobber (match_scratch:SI 4 "=X,X,l"))
1682 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1683 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1688 [(set_attr "type" "imadd")
1689 (set_attr "accum_in" "3")
1690 (set_attr "mode" "SI")
1691 (set_attr "insn_count" "1,1,2")
1692 (set (attr "enabled")
1693 (cond [(and (eq_attr "alternative" "0")
1694 (match_test "!mips_lra_flag"))
1695 (const_string "yes")
1696 (and (eq_attr "alternative" "1")
1697 (match_test "mips_lra_flag"))
1698 (const_string "yes")
1699 (eq_attr "alternative" "2")
1700 (const_string "yes")]
1701 (const_string "no")))])
1703 ;; The same idea applies here. The middle alternative needs one less
1704 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1705 (define_insn "*mul_acc_si_r3900"
1706 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d*?,d?")
1707 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
1708 (match_operand:SI 2 "register_operand" "d,d,d,d"))
1709 (match_operand:SI 3 "register_operand" "0,0,l,d")))
1710 (clobber (match_scratch:SI 4 "=X,X,3,l"))
1711 (clobber (match_scratch:SI 5 "=X,X,X,&d"))]
1712 "TARGET_MIPS3900 && !TARGET_MIPS16"
1718 [(set_attr "type" "imadd")
1719 (set_attr "accum_in" "3")
1720 (set_attr "mode" "SI")
1721 (set_attr "insn_count" "1,1,1,2")
1722 (set (attr "enabled")
1723 (cond [(and (eq_attr "alternative" "0")
1724 (match_test "!mips_lra_flag"))
1725 (const_string "yes")
1726 (and (eq_attr "alternative" "1")
1727 (match_test "mips_lra_flag"))
1728 (const_string "yes")
1729 (eq_attr "alternative" "2,3")
1730 (const_string "yes")]
1731 (const_string "no")))])
1733 ;; Split *mul_acc_si if both the source and destination accumulator
1736 [(set (match_operand:SI 0 "d_operand")
1737 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1738 (match_operand:SI 2 "d_operand"))
1739 (match_operand:SI 3 "d_operand")))
1740 (clobber (match_operand:SI 4 "lo_operand"))
1741 (clobber (match_operand:SI 5 "d_operand"))]
1743 [(parallel [(set (match_dup 5)
1744 (mult:SI (match_dup 1) (match_dup 2)))
1745 (clobber (match_dup 4))])
1746 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1749 (define_insn "*macc"
1750 [(set (match_operand:SI 0 "register_operand" "=l,d")
1751 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1752 (match_operand:SI 2 "register_operand" "d,d"))
1753 (match_operand:SI 3 "register_operand" "0,l")))
1754 (clobber (match_scratch:SI 4 "=X,3"))]
1757 if (which_alternative == 1)
1758 return "macc\t%0,%1,%2";
1759 else if (TARGET_MIPS5500)
1760 return "madd\t%1,%2";
1762 /* The VR4130 assumes that there is a two-cycle latency between a macc
1763 that "writes" to $0 and an instruction that reads from it. We avoid
1764 this by assigning to $1 instead. */
1765 return "%[macc\t%@,%1,%2%]";
1767 [(set_attr "type" "imadd")
1768 (set_attr "accum_in" "3")
1769 (set_attr "mode" "SI")])
1771 (define_insn "*msac"
1772 [(set (match_operand:SI 0 "register_operand" "=l,d")
1773 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1774 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1775 (match_operand:SI 3 "register_operand" "d,d"))))
1776 (clobber (match_scratch:SI 4 "=X,1"))]
1779 if (which_alternative == 1)
1780 return "msac\t%0,%2,%3";
1781 else if (TARGET_MIPS5500)
1782 return "msub\t%2,%3";
1784 return "msac\t$0,%2,%3";
1786 [(set_attr "type" "imadd")
1787 (set_attr "accum_in" "1")
1788 (set_attr "mode" "SI")])
1790 ;; An msac-like instruction implemented using negation and a macc.
1791 (define_insn_and_split "*msac_using_macc"
1792 [(set (match_operand:SI 0 "register_operand" "=l,d")
1793 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1794 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1795 (match_operand:SI 3 "register_operand" "d,d"))))
1796 (clobber (match_scratch:SI 4 "=X,1"))
1797 (clobber (match_scratch:SI 5 "=d,d"))]
1798 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1800 "&& reload_completed"
1802 (neg:SI (match_dup 3)))
1805 (plus:SI (mult:SI (match_dup 2)
1808 (clobber (match_dup 4))])]
1810 [(set_attr "type" "imadd")
1811 (set_attr "accum_in" "1")
1812 (set_attr "insn_count" "2")])
1814 ;; Patterns generated by the define_peephole2 below.
1816 (define_insn "*macc2"
1817 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1818 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1819 (match_operand:SI 2 "register_operand" "d"))
1821 (set (match_operand:SI 3 "register_operand" "=d")
1822 (plus:SI (mult:SI (match_dup 1)
1825 "ISA_HAS_MACC && reload_completed"
1827 [(set_attr "type" "imadd")
1828 (set_attr "accum_in" "0")
1829 (set_attr "mode" "SI")])
1831 (define_insn "*msac2"
1832 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1833 (minus:SI (match_dup 0)
1834 (mult:SI (match_operand:SI 1 "register_operand" "d")
1835 (match_operand:SI 2 "register_operand" "d"))))
1836 (set (match_operand:SI 3 "register_operand" "=d")
1837 (minus:SI (match_dup 0)
1838 (mult:SI (match_dup 1)
1840 "ISA_HAS_MSAC && reload_completed"
1842 [(set_attr "type" "imadd")
1843 (set_attr "accum_in" "0")
1844 (set_attr "mode" "SI")])
1846 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1850 ;; Operand 1: macc/msac
1851 ;; Operand 2: GPR (destination)
1854 [(set (match_operand:SI 0 "lo_operand")
1855 (match_operand:SI 1 "macc_msac_operand"))
1856 (clobber (scratch:SI))])
1857 (set (match_operand:SI 2 "d_operand")
1860 [(parallel [(set (match_dup 0)
1865 ;; When we have a three-address multiplication instruction, it should
1866 ;; be faster to do a separate multiply and add, rather than moving
1867 ;; something into LO in order to use a macc instruction.
1869 ;; This peephole needs a scratch register to cater for the case when one
1870 ;; of the multiplication operands is the same as the destination.
1872 ;; Operand 0: GPR (scratch)
1874 ;; Operand 2: GPR (addend)
1875 ;; Operand 3: GPR (destination)
1876 ;; Operand 4: macc/msac
1877 ;; Operand 5: new multiplication
1878 ;; Operand 6: new addition/subtraction
1880 [(match_scratch:SI 0 "d")
1881 (set (match_operand:SI 1 "lo_operand")
1882 (match_operand:SI 2 "d_operand"))
1885 [(set (match_operand:SI 3 "d_operand")
1886 (match_operand:SI 4 "macc_msac_operand"))
1887 (clobber (match_dup 1))])]
1888 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1889 [(parallel [(set (match_dup 0)
1891 (clobber (match_dup 1))])
1895 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1896 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1897 operands[2], operands[0]);
1900 ;; Same as above, except LO is the initial target of the macc.
1902 ;; Operand 0: GPR (scratch)
1904 ;; Operand 2: GPR (addend)
1905 ;; Operand 3: macc/msac
1906 ;; Operand 4: GPR (destination)
1907 ;; Operand 5: new multiplication
1908 ;; Operand 6: new addition/subtraction
1910 [(match_scratch:SI 0 "d")
1911 (set (match_operand:SI 1 "lo_operand")
1912 (match_operand:SI 2 "d_operand"))
1916 (match_operand:SI 3 "macc_msac_operand"))
1917 (clobber (scratch:SI))])
1919 (set (match_operand:SI 4 "d_operand")
1921 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1922 [(parallel [(set (match_dup 0)
1924 (clobber (match_dup 1))])
1928 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1929 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1930 operands[2], operands[0]);
1933 ;; See the comment above *mul_add_si for details.
1934 (define_insn "*mul_sub_si"
1935 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?")
1936 (minus:SI (match_operand:SI 1 "register_operand" "0,0,d")
1937 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1938 (match_operand:SI 3 "register_operand" "d,d,d"))))
1939 (clobber (match_scratch:SI 4 "=X,X,l"))
1940 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1941 "GENERATE_MADD_MSUB"
1946 [(set_attr "type" "imadd")
1947 (set_attr "accum_in" "1")
1948 (set_attr "mode" "SI")
1949 (set_attr "insn_count" "1,1,2")
1950 (set (attr "enabled")
1951 (cond [(and (eq_attr "alternative" "0")
1952 (match_test "!mips_lra_flag"))
1953 (const_string "yes")
1954 (and (eq_attr "alternative" "1")
1955 (match_test "mips_lra_flag"))
1956 (const_string "yes")
1957 (eq_attr "alternative" "2")
1958 (const_string "yes")]
1959 (const_string "no")))])
1961 ;; Split *mul_sub_si if both the source and destination accumulator
1964 [(set (match_operand:SI 0 "d_operand")
1965 (minus:SI (match_operand:SI 1 "d_operand")
1966 (mult:SI (match_operand:SI 2 "d_operand")
1967 (match_operand:SI 3 "d_operand"))))
1968 (clobber (match_operand:SI 4 "lo_operand"))
1969 (clobber (match_operand:SI 5 "d_operand"))]
1971 [(parallel [(set (match_dup 5)
1972 (mult:SI (match_dup 2) (match_dup 3)))
1973 (clobber (match_dup 4))])
1974 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1977 (define_insn "*muls"
1978 [(set (match_operand:SI 0 "register_operand" "=l,d")
1979 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1980 (match_operand:SI 2 "register_operand" "d,d"))))
1981 (clobber (match_scratch:SI 3 "=X,l"))]
1986 [(set_attr "type" "imul,imul3")
1987 (set_attr "mode" "SI")])
1989 (define_expand "<u>mulsidi3"
1990 [(set (match_operand:DI 0 "register_operand")
1991 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1992 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1993 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
1995 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1996 emit_insn (fn (operands[0], operands[1], operands[2]));
2000 (define_expand "<u>mulsidi3_32bit_r6"
2001 [(set (match_operand:DI 0 "register_operand")
2002 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2003 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2004 "!TARGET_64BIT && ISA_HAS_R6MUL"
2006 rtx dest = gen_reg_rtx (DImode);
2007 rtx low = mips_subword (dest, 0);
2008 rtx high = mips_subword (dest, 1);
2010 emit_insn (gen_mulsi3_mul3_nohilo (low, operands[1], operands[2]));
2011 emit_insn (gen_<su>mulsi3_highpart_r6 (high, operands[1], operands[2]));
2013 emit_move_insn (mips_subword (operands[0], 0), low);
2014 emit_move_insn (mips_subword (operands[0], 1), high);
2018 (define_expand "<u>mulsidi3_32bit_mips16"
2019 [(set (match_operand:DI 0 "register_operand")
2020 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2021 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2022 "!TARGET_64BIT && TARGET_MIPS16"
2026 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2027 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2028 emit_move_insn (operands[0], hilo);
2032 ;; As well as being named patterns, these instructions are used by the
2033 ;; __builtin_mips_mult<u>() functions. We must always make those functions
2034 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2035 (define_insn "<u>mulsidi3_32bit"
2036 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2037 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2038 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
2039 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP) && ISA_HAS_MULT"
2041 if (ISA_HAS_DSP_MULT)
2042 return "mult<u>\t%q0,%1,%2";
2044 return "mult<u>\t%1,%2";
2046 [(set_attr "type" "imul")
2047 (set_attr "mode" "SI")])
2049 (define_insn "<u>mulsidi3_32bit_r4000"
2050 [(set (match_operand:DI 0 "register_operand" "=d")
2051 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2052 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2053 (clobber (match_scratch:DI 3 "=x"))]
2054 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP && ISA_HAS_MULT"
2055 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2056 [(set_attr "type" "imul")
2057 (set_attr "mode" "SI")
2058 (set_attr "insn_count" "3")])
2060 (define_insn_and_split "<u>mulsidi3_64bit"
2061 [(set (match_operand:DI 0 "register_operand" "=d")
2062 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2063 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2064 (clobber (match_scratch:TI 3 "=x"))
2065 (clobber (match_scratch:DI 4 "=d"))]
2066 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3
2067 && !TARGET_MIPS16 && ISA_HAS_MULT"
2069 "&& reload_completed"
2072 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
2073 operands[2], operands[4]));
2076 [(set_attr "type" "imul")
2077 (set_attr "mode" "SI")
2078 (set (attr "insn_count")
2079 (if_then_else (match_test "ISA_HAS_EXT_INS")
2083 (define_expand "<u>mulsidi3_64bit_mips16"
2084 [(set (match_operand:DI 0 "register_operand")
2085 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2086 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2087 "TARGET_64BIT && TARGET_MIPS16"
2089 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
2090 operands[2], gen_reg_rtx (DImode)));
2094 (define_expand "<u>mulsidi3_64bit_split"
2095 [(set (match_operand:DI 0 "register_operand")
2096 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2097 (any_extend:DI (match_operand:SI 2 "register_operand"))))
2098 (clobber (match_operand:DI 3 "register_operand"))]
2103 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2104 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2106 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM));
2107 emit_insn (gen_mfhidi_ti (operands[3], hilo));
2109 if (ISA_HAS_EXT_INS)
2110 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32),
2114 /* Zero-extend the low part. */
2115 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32));
2116 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32));
2118 /* Shift the high part into place. */
2119 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32));
2121 /* OR the two halves together. */
2122 mips_emit_binary (IOR, operands[0], operands[0], operands[3]);
2127 (define_insn "<u>mulsidi3_64bit_hilo"
2128 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2131 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2132 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
2134 "TARGET_64BIT && !TARGET_FIX_R4000"
2136 [(set_attr "type" "imul")
2137 (set_attr "mode" "SI")])
2139 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
2140 (define_insn "mulsidi3_64bit_dmul"
2141 [(set (match_operand:DI 0 "register_operand" "=d")
2142 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2143 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2144 (clobber (match_scratch:DI 3 "=l"))]
2147 [(set_attr "type" "imul3")
2148 (set_attr "mode" "DI")])
2150 (define_insn "mulsidi3_64bit_r6dmul"
2151 [(set (match_operand:DI 0 "register_operand" "=d")
2152 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2153 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
2156 [(set_attr "type" "imul3nc")
2157 (set_attr "mode" "DI")])
2159 ;; Widening multiply with negation.
2160 (define_insn "*muls<u>_di"
2161 [(set (match_operand:DI 0 "muldiv_target_operand" "=x")
2164 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2165 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2166 "!TARGET_64BIT && ISA_HAS_MULS"
2168 [(set_attr "type" "imul")
2169 (set_attr "mode" "SI")])
2171 ;; As well as being named patterns, these instructions are used by the
2172 ;; __builtin_mips_msub<u>() functions. We must always make those functions
2173 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2175 ;; This leads to a slight inconsistency. We honor any tuning overrides
2176 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
2177 ;; even if !ISA_HAS_DSP_MULT.
2178 (define_insn "<u>msubsidi4"
2179 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2181 (match_operand:DI 3 "muldiv_target_operand" "0")
2183 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2184 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2185 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
2187 if (ISA_HAS_DSP_MULT)
2188 return "msub<u>\t%q0,%1,%2";
2189 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
2190 return "msub<u>\t%1,%2";
2192 return "msac<u>\t$0,%1,%2";
2194 [(set_attr "type" "imadd")
2195 (set_attr "accum_in" "3")
2196 (set_attr "mode" "SI")])
2198 ;; _highpart patterns
2200 (define_expand "<su>mulsi3_highpart"
2201 [(set (match_operand:SI 0 "register_operand")
2204 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2205 (any_extend:DI (match_operand:SI 2 "register_operand")))
2210 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
2213 else if (TARGET_MIPS16)
2214 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2216 else if (ISA_HAS_R6MUL)
2217 emit_insn (gen_<su>mulsi3_highpart_r6 (operands[0], operands[1],
2220 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
2225 (define_insn "<su>mulsi3_highpart_r6"
2226 [(set (match_operand:SI 0 "register_operand" "=d")
2229 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2230 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2234 [(set_attr "type" "imul3nc")
2235 (set_attr "mode" "SI")])
2237 (define_insn_and_split "<su>mulsi3_highpart_internal"
2238 [(set (match_operand:SI 0 "register_operand" "=d")
2241 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2242 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2244 (clobber (match_scratch:SI 3 "=l"))]
2245 "ISA_HAS_MULT && !ISA_HAS_MULHI && !TARGET_MIPS16"
2246 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2247 "&& reload_completed && !TARGET_FIX_R4000"
2250 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2254 [(set_attr "type" "imul")
2255 (set_attr "mode" "SI")
2256 (set_attr "insn_count" "2")])
2258 (define_expand "<su>mulsi3_highpart_split"
2259 [(set (match_operand:SI 0 "register_operand")
2262 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2263 (any_extend:DI (match_operand:SI 2 "register_operand")))
2271 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2272 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2273 emit_insn (gen_mfhisi_ti (operands[0], hilo));
2277 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2278 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2279 emit_insn (gen_mfhisi_di (operands[0], hilo));
2284 (define_insn "<su>mulsi3_highpart_mulhi_internal"
2285 [(set (match_operand:SI 0 "register_operand" "=d")
2289 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2290 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2292 (clobber (match_scratch:SI 3 "=l"))]
2294 "mulhi<u>\t%0,%1,%2"
2295 [(set_attr "type" "imul3")
2296 (set_attr "mode" "SI")])
2298 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
2299 [(set (match_operand:SI 0 "register_operand" "=d")
2304 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2305 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2307 (clobber (match_scratch:SI 3 "=l"))]
2309 "mulshi<u>\t%0,%1,%2"
2310 [(set_attr "type" "imul3")
2311 (set_attr "mode" "SI")])
2313 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
2314 ;; errata MD(0), which says that dmultu does not always produce the
2316 (define_expand "<su>muldi3_highpart"
2317 [(set (match_operand:DI 0 "register_operand")
2320 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2321 (any_extend:TI (match_operand:DI 2 "register_operand")))
2325 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120))"
2328 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2330 else if (ISA_HAS_R6DMUL)
2331 emit_insn (gen_<su>muldi3_highpart_r6 (operands[0], operands[1],
2334 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1],
2339 (define_insn "<su>muldi3_highpart_r6"
2340 [(set (match_operand:DI 0 "register_operand" "=d")
2343 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2344 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2348 [(set_attr "type" "imul3nc")
2349 (set_attr "mode" "DI")])
2351 (define_insn_and_split "<su>muldi3_highpart_internal"
2352 [(set (match_operand:DI 0 "register_operand" "=d")
2355 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2356 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2358 (clobber (match_scratch:DI 3 "=l"))]
2361 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2362 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2363 "&& reload_completed && !TARGET_FIX_R4000"
2366 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2370 [(set_attr "type" "imul")
2371 (set_attr "mode" "DI")
2372 (set_attr "insn_count" "2")])
2374 (define_expand "<su>muldi3_highpart_split"
2375 [(set (match_operand:DI 0 "register_operand")
2378 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2379 (any_extend:TI (match_operand:DI 2 "register_operand")))
2385 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2386 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2387 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2391 (define_expand "<u>mulditi3"
2392 [(set (match_operand:TI 0 "register_operand")
2393 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2394 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2395 "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2401 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2402 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2403 emit_move_insn (operands[0], hilo);
2405 else if (TARGET_FIX_R4000)
2406 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2408 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2413 (define_insn "<u>mulditi3_internal"
2414 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2415 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2416 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2418 && !TARGET_FIX_R4000
2419 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2421 [(set_attr "type" "imul")
2422 (set_attr "mode" "DI")])
2424 (define_insn "<u>mulditi3_r4000"
2425 [(set (match_operand:TI 0 "register_operand" "=d")
2426 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2427 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2428 (clobber (match_scratch:TI 3 "=x"))]
2431 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2432 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2433 [(set_attr "type" "imul")
2434 (set_attr "mode" "DI")
2435 (set_attr "insn_count" "3")])
2437 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2438 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2440 (define_insn "madsi"
2441 [(set (match_operand:SI 0 "register_operand" "+l")
2442 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2443 (match_operand:SI 2 "register_operand" "d"))
2447 [(set_attr "type" "imadd")
2448 (set_attr "accum_in" "0")
2449 (set_attr "mode" "SI")])
2451 ;; See the comment above <u>msubsidi4 for the relationship between
2452 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2453 (define_insn "<u>maddsidi4"
2454 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2456 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2457 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2458 (match_operand:DI 3 "muldiv_target_operand" "0")))]
2459 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2463 return "mad<u>\t%1,%2";
2464 else if (ISA_HAS_DSP_MULT)
2465 return "madd<u>\t%q0,%1,%2";
2466 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2467 return "madd<u>\t%1,%2";
2469 /* See comment in *macc. */
2470 return "%[macc<u>\t%@,%1,%2%]";
2472 [(set_attr "type" "imadd")
2473 (set_attr "accum_in" "3")
2474 (set_attr "mode" "SI")])
2476 ;; Floating point multiply accumulate instructions.
2478 (define_expand "fma<mode>4"
2479 [(set (match_operand:ANYF 0 "register_operand")
2480 (fma:ANYF (match_operand:ANYF 1 "register_operand")
2481 (match_operand:ANYF 2 "register_operand")
2482 (match_operand:ANYF 3 "register_operand")))]
2483 "ISA_HAS_FUSED_MADDF || ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4")
2485 (define_insn "*fma<mode>4_madd3"
2486 [(set (match_operand:ANYF 0 "register_operand" "=f")
2487 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2488 (match_operand:ANYF 2 "register_operand" "f")
2489 (match_operand:ANYF 3 "register_operand" "0")))]
2490 "ISA_HAS_FUSED_MADD3"
2491 "madd.<fmt>\t%0,%1,%2"
2492 [(set_attr "type" "fmadd")
2493 (set_attr "mode" "<UNITMODE>")])
2495 (define_insn "*fma<mode>4_madd4"
2496 [(set (match_operand:ANYF 0 "register_operand" "=f")
2497 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2498 (match_operand:ANYF 2 "register_operand" "f")
2499 (match_operand:ANYF 3 "register_operand" "f")))]
2500 "ISA_HAS_FUSED_MADD4"
2501 "madd.<fmt>\t%0,%3,%1,%2"
2502 [(set_attr "type" "fmadd")
2503 (set_attr "mode" "<UNITMODE>")])
2505 (define_insn "*fma<mode>4_maddf"
2506 [(set (match_operand:ANYF 0 "register_operand" "=f")
2507 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2508 (match_operand:ANYF 2 "register_operand" "f")
2509 (match_operand:ANYF 3 "register_operand" "0")))]
2510 "ISA_HAS_FUSED_MADDF"
2511 "maddf.<fmt>\t%0,%1,%2"
2512 [(set_attr "type" "fmadd")
2513 (set_attr "mode" "<UNITMODE>")])
2515 ;; The fms, fnma, and fnms instructions can be used even when HONOR_NANS
2516 ;; is true because while IEEE 754-2008 requires the negate operation to
2517 ;; negate the sign of a NAN and the MIPS neg instruction does not do this,
2518 ;; the fma part of the instruction has no requirement on how the sign of
2519 ;; a NAN is handled and so the final sign bit of the entire operation is
2522 (define_expand "fms<mode>4"
2523 [(set (match_operand:ANYF 0 "register_operand")
2524 (fma:ANYF (match_operand:ANYF 1 "register_operand")
2525 (match_operand:ANYF 2 "register_operand")
2526 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))]
2527 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)")
2529 (define_insn "*fms<mode>4_msub3"
2530 [(set (match_operand:ANYF 0 "register_operand" "=f")
2531 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2532 (match_operand:ANYF 2 "register_operand" "f")
2533 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))]
2534 "ISA_HAS_FUSED_MADD3"
2535 "msub.<fmt>\t%0,%1,%2"
2536 [(set_attr "type" "fmadd")
2537 (set_attr "mode" "<UNITMODE>")])
2539 (define_insn "*fms<mode>4_msub4"
2540 [(set (match_operand:ANYF 0 "register_operand" "=f")
2541 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2542 (match_operand:ANYF 2 "register_operand" "f")
2543 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))]
2544 "ISA_HAS_FUSED_MADD4"
2545 "msub.<fmt>\t%0,%3,%1,%2"
2546 [(set_attr "type" "fmadd")
2547 (set_attr "mode" "<UNITMODE>")])
2549 ;; fnma is defined in GCC as (fma (neg op1) op2 op3)
2550 ;; (-op1 * op2) + op3 ==> -(op1 * op2) + op3 ==> -((op1 * op2) - op3)
2551 ;; The mips nmsub instructions implement -((op1 * op2) - op3)
2552 ;; This transformation means we may return the wrong signed zero
2553 ;; so we check HONOR_SIGNED_ZEROS.
2555 (define_expand "fnma<mode>4"
2556 [(set (match_operand:ANYF 0 "register_operand")
2557 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand"))
2558 (match_operand:ANYF 2 "register_operand")
2559 (match_operand:ANYF 3 "register_operand")))]
2560 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)
2561 && !HONOR_SIGNED_ZEROS (<MODE>mode)")
2563 (define_insn "*fnma<mode>4_nmsub3"
2564 [(set (match_operand:ANYF 0 "register_operand" "=f")
2565 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2566 (match_operand:ANYF 2 "register_operand" "f")
2567 (match_operand:ANYF 3 "register_operand" "0")))]
2568 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2569 "nmsub.<fmt>\t%0,%1,%2"
2570 [(set_attr "type" "fmadd")
2571 (set_attr "mode" "<UNITMODE>")])
2573 (define_insn "*fnma<mode>4_nmsub4"
2574 [(set (match_operand:ANYF 0 "register_operand" "=f")
2575 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2576 (match_operand:ANYF 2 "register_operand" "f")
2577 (match_operand:ANYF 3 "register_operand" "f")))]
2578 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2579 "nmsub.<fmt>\t%0,%3,%1,%2"
2580 [(set_attr "type" "fmadd")
2581 (set_attr "mode" "<UNITMODE>")])
2583 ;; fnms is defined as: (fma (neg op1) op2 (neg op3))
2584 ;; ((-op1) * op2) - op3 ==> -(op1 * op2) - op3 ==> -((op1 * op2) + op3)
2585 ;; The mips nmadd instructions implement -((op1 * op2) + op3)
2586 ;; This transformation means we may return the wrong signed zero
2587 ;; so we check HONOR_SIGNED_ZEROS.
2589 (define_expand "fnms<mode>4"
2590 [(set (match_operand:ANYF 0 "register_operand")
2592 (neg:ANYF (match_operand:ANYF 1 "register_operand"))
2593 (match_operand:ANYF 2 "register_operand")
2594 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))]
2595 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)
2596 && !HONOR_SIGNED_ZEROS (<MODE>mode)")
2598 (define_insn "*fnms<mode>4_nmadd3"
2599 [(set (match_operand:ANYF 0 "register_operand" "=f")
2601 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2602 (match_operand:ANYF 2 "register_operand" "f")
2603 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))]
2604 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2605 "nmadd.<fmt>\t%0,%1,%2"
2606 [(set_attr "type" "fmadd")
2607 (set_attr "mode" "<UNITMODE>")])
2609 (define_insn "*fnms<mode>4_nmadd4"
2610 [(set (match_operand:ANYF 0 "register_operand" "=f")
2612 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2613 (match_operand:ANYF 2 "register_operand" "f")
2614 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))]
2615 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2616 "nmadd.<fmt>\t%0,%3,%1,%2"
2617 [(set_attr "type" "fmadd")
2618 (set_attr "mode" "<UNITMODE>")])
2620 ;; Non-fused Floating point multiply accumulate instructions.
2622 ;; These instructions are not fused and round in between the multiply
2623 ;; and the add (or subtract) so they are equivalent to the separate
2624 ;; multiply and add/sub instructions.
2626 (define_insn "*madd4<mode>"
2627 [(set (match_operand:ANYF 0 "register_operand" "=f")
2628 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2629 (match_operand:ANYF 2 "register_operand" "f"))
2630 (match_operand:ANYF 3 "register_operand" "f")))]
2631 "ISA_HAS_UNFUSED_MADD4"
2632 "madd.<fmt>\t%0,%3,%1,%2"
2633 [(set_attr "type" "fmadd")
2634 (set_attr "mode" "<UNITMODE>")])
2636 (define_insn "*msub4<mode>"
2637 [(set (match_operand:ANYF 0 "register_operand" "=f")
2638 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2639 (match_operand:ANYF 2 "register_operand" "f"))
2640 (match_operand:ANYF 3 "register_operand" "f")))]
2641 "ISA_HAS_UNFUSED_MADD4"
2642 "msub.<fmt>\t%0,%3,%1,%2"
2643 [(set_attr "type" "fmadd")
2644 (set_attr "mode" "<UNITMODE>")])
2646 ;; Like with the fused fms, fnma, and fnms instructions, these unfused
2647 ;; instructions can be used even if HONOR_NANS is set because while
2648 ;; IEEE 754-2008 requires the negate operation to negate the sign of a
2649 ;; NAN and the MIPS neg instruction does not do this, the multiply and
2650 ;; add (or subtract) part of the instruction has no requirement on how
2651 ;; the sign of a NAN is handled and so the final sign bit of the entire
2652 ;; operation is undefined.
2654 (define_insn "*nmadd4<mode>"
2655 [(set (match_operand:ANYF 0 "register_operand" "=f")
2656 (neg:ANYF (plus:ANYF
2657 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2658 (match_operand:ANYF 2 "register_operand" "f"))
2659 (match_operand:ANYF 3 "register_operand" "f"))))]
2660 "ISA_HAS_UNFUSED_MADD4"
2661 "nmadd.<fmt>\t%0,%3,%1,%2"
2662 [(set_attr "type" "fmadd")
2663 (set_attr "mode" "<UNITMODE>")])
2665 (define_insn "*nmsub4<mode>"
2666 [(set (match_operand:ANYF 0 "register_operand" "=f")
2667 (neg:ANYF (minus:ANYF
2668 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2669 (match_operand:ANYF 2 "register_operand" "f"))
2670 (match_operand:ANYF 3 "register_operand" "f"))))]
2671 "ISA_HAS_UNFUSED_MADD4"
2672 "nmsub.<fmt>\t%0,%3,%1,%2"
2673 [(set_attr "type" "fmadd")
2674 (set_attr "mode" "<UNITMODE>")])
2676 ;; Fast-math Non-fused Floating point multiply accumulate instructions.
2678 ;; These instructions are not fused but the expressions they match are
2679 ;; not exactly what the instruction implements in the sense that they
2680 ;; may not generate the properly signed zeros.
2682 ;; This instruction recognizes ((-op1) * op2) - op3 and generates an
2683 ;; nmadd which is really -((op1 * op2) + op3). They are equivalent
2684 ;; except for the sign bit when the result is zero or NaN.
2686 (define_insn "*nmadd4<mode>_fastmath"
2687 [(set (match_operand:ANYF 0 "register_operand" "=f")
2689 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2690 (match_operand:ANYF 2 "register_operand" "f"))
2691 (match_operand:ANYF 3 "register_operand" "f")))]
2692 "ISA_HAS_UNFUSED_MADD4
2693 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2694 "nmadd.<fmt>\t%0,%3,%1,%2"
2695 [(set_attr "type" "fmadd")
2696 (set_attr "mode" "<UNITMODE>")])
2698 ;; This instruction recognizes (op1 - (op2 * op3) and generates an
2699 ;; nmsub which is really -((op2 * op3) - op1). They are equivalent
2700 ;; except for the sign bit when the result is zero or NaN.
2702 (define_insn "*nmsub4<mode>_fastmath"
2703 [(set (match_operand:ANYF 0 "register_operand" "=f")
2705 (match_operand:ANYF 1 "register_operand" "f")
2706 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2707 (match_operand:ANYF 3 "register_operand" "f"))))]
2708 "ISA_HAS_UNFUSED_MADD4
2709 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2710 "nmsub.<fmt>\t%0,%1,%2,%3"
2711 [(set_attr "type" "fmadd")
2712 (set_attr "mode" "<UNITMODE>")])
2715 ;; ....................
2717 ;; DIVISION and REMAINDER
2719 ;; ....................
2722 (define_expand "div<mode>3"
2723 [(set (match_operand:ANYF 0 "register_operand")
2724 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2725 (match_operand:ANYF 2 "register_operand")))]
2726 "<divide_condition>"
2728 if (const_1_operand (operands[1], <MODE>mode))
2729 if (!(ISA_HAS_FP_RECIP_RSQRT (<MODE>mode)
2730 && flag_unsafe_math_optimizations))
2731 operands[1] = force_reg (<MODE>mode, operands[1]);
2734 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2736 ;; If an mfc1 or dmfc1 happens to access the floating point register
2737 ;; file at the same time a long latency operation (div, sqrt, recip,
2738 ;; sqrt) iterates an intermediate result back through the floating
2739 ;; point register file bypass, then instead returning the correct
2740 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2741 ;; result of the long latency operation.
2743 ;; The workaround is to insert an unconditional 'mov' from/to the
2744 ;; long latency op destination register.
2746 (define_insn "*div<mode>3"
2747 [(set (match_operand:ANYF 0 "register_operand" "=f")
2748 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2749 (match_operand:ANYF 2 "register_operand" "f")))]
2750 "<divide_condition>"
2753 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2755 return "div.<fmt>\t%0,%1,%2";
2757 [(set_attr "type" "fdiv")
2758 (set_attr "mode" "<UNITMODE>")
2759 (set (attr "insn_count")
2760 (if_then_else (match_test "TARGET_FIX_SB1")
2764 (define_insn "*recip<mode>3"
2765 [(set (match_operand:ANYF 0 "register_operand" "=f")
2766 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2767 (match_operand:ANYF 2 "register_operand" "f")))]
2768 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
2771 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2773 return "recip.<fmt>\t%0,%2";
2775 [(set_attr "type" "frdiv")
2776 (set_attr "mode" "<UNITMODE>")
2777 (set (attr "insn_count")
2778 (if_then_else (match_test "TARGET_FIX_SB1")
2782 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2783 ;; with negative operands. We use special libgcc functions instead.
2784 (define_expand "divmod<mode>4"
2786 [(set (match_operand:GPR 0 "register_operand")
2787 (div:GPR (match_operand:GPR 1 "register_operand")
2788 (match_operand:GPR 2 "register_operand")))
2789 (set (match_operand:GPR 3 "register_operand")
2790 (mod:GPR (match_dup 1)
2792 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
2796 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
2797 emit_insn (gen_divmod<mode>4_mips16 (operands[0], operands[1],
2798 operands[2], operands[3], lo));
2803 (define_insn_and_split "*divmod<mode>4"
2804 [(set (match_operand:GPR 0 "register_operand" "=l")
2805 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2806 (match_operand:GPR 2 "register_operand" "d")))
2807 (set (match_operand:GPR 3 "register_operand" "=d")
2808 (mod:GPR (match_dup 1)
2810 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && !TARGET_MIPS16"
2812 "&& reload_completed"
2815 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2818 [(set_attr "type" "idiv")
2819 (set_attr "mode" "<MODE>")
2820 (set_attr "insn_count" "2")])
2822 ;; Expand generates divmod instructions for individual division and modulus
2823 ;; operations. We then rely on CSE to reuse earlier divmods where possible.
2824 ;; This means that, when generating MIPS16 code, it is better not to expose
2825 ;; the fixed LO register until after CSE has finished. However, it's still
2826 ;; better to split before register allocation, so that we don't allocate
2827 ;; one of the scarce MIPS16 registers to an unused result.
2828 (define_insn_and_split "divmod<mode>4_mips16"
2829 [(set (match_operand:GPR 0 "register_operand" "=d")
2830 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2831 (match_operand:GPR 2 "register_operand" "d")))
2832 (set (match_operand:GPR 3 "register_operand" "=d")
2833 (mod:GPR (match_dup 1)
2835 (clobber (match_operand:GPR 4 "lo_operand" "=l"))]
2836 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && TARGET_MIPS16"
2838 "&& cse_not_expected"
2841 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2842 emit_move_insn (operands[0], operands[4]);
2845 [(set_attr "type" "idiv")
2846 (set_attr "mode" "<MODE>")
2847 (set_attr "insn_count" "3")])
2849 (define_expand "udivmod<mode>4"
2851 [(set (match_operand:GPR 0 "register_operand")
2852 (udiv:GPR (match_operand:GPR 1 "register_operand")
2853 (match_operand:GPR 2 "register_operand")))
2854 (set (match_operand:GPR 3 "register_operand")
2855 (umod:GPR (match_dup 1)
2857 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
2861 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
2862 emit_insn (gen_udivmod<mode>4_mips16 (operands[0], operands[1],
2863 operands[2], operands[3], lo));
2868 (define_insn_and_split "*udivmod<mode>4"
2869 [(set (match_operand:GPR 0 "register_operand" "=l")
2870 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2871 (match_operand:GPR 2 "register_operand" "d")))
2872 (set (match_operand:GPR 3 "register_operand" "=d")
2873 (umod:GPR (match_dup 1)
2875 "ISA_HAS_<D>DIV && !TARGET_MIPS16"
2880 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2883 [(set_attr "type" "idiv")
2884 (set_attr "mode" "<MODE>")
2885 (set_attr "insn_count" "2")])
2887 ;; See the comment above "divmod<mode>4_mips16" for the split timing.
2888 (define_insn_and_split "udivmod<mode>4_mips16"
2889 [(set (match_operand:GPR 0 "register_operand" "=d")
2890 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2891 (match_operand:GPR 2 "register_operand" "d")))
2892 (set (match_operand:GPR 3 "register_operand" "=d")
2893 (umod:GPR (match_dup 1)
2895 (clobber (match_operand:GPR 4 "lo_operand" "=l"))]
2896 "ISA_HAS_<D>DIV && TARGET_MIPS16"
2901 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2902 emit_move_insn (operands[0], operands[4]);
2905 [(set_attr "type" "idiv")
2906 (set_attr "mode" "<MODE>")
2907 (set_attr "insn_count" "3")])
2909 (define_expand "<u>divmod<mode>4_split"
2910 [(set (match_operand:GPR 0 "register_operand")
2911 (any_mod:GPR (match_operand:GPR 1 "register_operand")
2912 (match_operand:GPR 2 "register_operand")))]
2919 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2920 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1],
2922 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo));
2926 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2927 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1],
2929 emit_insn (gen_mfhi<mode>_di (operands[0], hilo));
2934 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2935 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x")
2937 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2938 (match_operand:GPR 2 "register_operand" "d"))]
2940 "ISA_HAS_<GPR:D>DIV"
2941 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2942 [(set_attr "type" "idiv")
2943 (set_attr "mode" "<GPR:MODE>")])
2945 ;; Integer division and modulus.
2947 (define_insn "<u>div<mode>3"
2948 [(set (match_operand:GPR 0 "register_operand" "=&d")
2949 (any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2950 (match_operand:GPR 2 "register_operand" "d")))]
2951 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>DIV"
2953 if (TARGET_LOONGSON_2EF)
2954 return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands);
2955 else if (TARGET_LOONGSON_3A)
2956 return mips_output_division ("gs<d>div<u>\t%0,%1,%2", operands);
2958 return mips_output_division ("<d>div<u>\t%0,%1,%2", operands);
2960 [(set_attr "type" "idiv3")
2961 (set_attr "mode" "<MODE>")])
2963 (define_insn "<u>mod<mode>3"
2964 [(set (match_operand:GPR 0 "register_operand" "=&d")
2965 (any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
2966 (match_operand:GPR 2 "register_operand" "d")))]
2967 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>DIV"
2969 if (TARGET_LOONGSON_2EF)
2970 return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands);
2971 else if (TARGET_LOONGSON_3A)
2972 return mips_output_division ("gs<d>mod<u>\t%0,%1,%2", operands);
2974 return mips_output_division ("<d>mod<u>\t%0,%1,%2", operands);
2976 [(set_attr "type" "idiv3")
2977 (set_attr "mode" "<MODE>")])
2980 ;; ....................
2984 ;; ....................
2986 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2987 ;; "*div[sd]f3" comment for details).
2989 (define_insn "sqrt<mode>2"
2990 [(set (match_operand:ANYF 0 "register_operand" "=f")
2991 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2995 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2997 return "sqrt.<fmt>\t%0,%1";
2999 [(set_attr "type" "fsqrt")
3000 (set_attr "mode" "<UNITMODE>")
3001 (set (attr "insn_count")
3002 (if_then_else (match_test "TARGET_FIX_SB1")
3006 (define_insn "*rsqrt<mode>a"
3007 [(set (match_operand:ANYF 0 "register_operand" "=f")
3008 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
3009 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
3010 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
3013 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
3015 return "rsqrt.<fmt>\t%0,%2";
3017 [(set_attr "type" "frsqrt")
3018 (set_attr "mode" "<UNITMODE>")
3019 (set (attr "insn_count")
3020 (if_then_else (match_test "TARGET_FIX_SB1")
3024 (define_insn "*rsqrt<mode>b"
3025 [(set (match_operand:ANYF 0 "register_operand" "=f")
3026 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
3027 (match_operand:ANYF 2 "register_operand" "f"))))]
3028 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
3031 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
3033 return "rsqrt.<fmt>\t%0,%2";
3035 [(set_attr "type" "frsqrt")
3036 (set_attr "mode" "<UNITMODE>")
3037 (set (attr "insn_count")
3038 (if_then_else (match_test "TARGET_FIX_SB1")
3043 ;; ....................
3047 ;; ....................
3049 ;; Do not use the integer abs macro instruction, since that signals an
3050 ;; exception on -2147483648 (sigh).
3052 ;; The "legacy" (as opposed to "2008") form of ABS.fmt is an arithmetic
3053 ;; instruction that treats all NaN inputs as invalid; it does not clear
3054 ;; their sign bit. We therefore can't use that form if the signs of
3057 (define_insn "abs<mode>2"
3058 [(set (match_operand:ANYF 0 "register_operand" "=f")
3059 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
3060 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)"
3062 [(set_attr "type" "fabs")
3063 (set_attr "mode" "<UNITMODE>")])
3066 ;; ...................
3068 ;; Count leading zeroes.
3070 ;; ...................
3073 (define_insn "clz<mode>2"
3074 [(set (match_operand:GPR 0 "register_operand" "=d")
3075 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
3078 [(set_attr "type" "clz")
3079 (set_attr "mode" "<MODE>")])
3082 ;; ...................
3084 ;; Count number of set bits.
3086 ;; ...................
3089 (define_insn "popcount<mode>2"
3090 [(set (match_operand:GPR 0 "register_operand" "=d")
3091 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
3094 [(set_attr "type" "pop")
3095 (set_attr "mode" "<MODE>")])
3097 ;; The POP instruction is special as it does not take into account the upper
3098 ;; 32bits and is documented that way.
3099 (define_insn "*popcountdi2_trunc"
3100 [(set (match_operand:SI 0 "register_operand" "=d")
3101 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))]
3102 "ISA_HAS_POP && TARGET_64BIT"
3104 [(set_attr "type" "pop")
3105 (set_attr "mode" "SI")])
3108 ;; ....................
3110 ;; NEGATION and ONE'S COMPLEMENT
3112 ;; ....................
3114 (define_insn "negsi2"
3115 [(set (match_operand:SI 0 "register_operand" "=d")
3116 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
3120 return "neg\t%0,%1";
3122 return "subu\t%0,%.,%1";
3124 [(set_attr "alu_type" "sub")
3125 (set_attr "mode" "SI")])
3127 (define_insn "negdi2"
3128 [(set (match_operand:DI 0 "register_operand" "=d")
3129 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
3130 "TARGET_64BIT && !TARGET_MIPS16"
3132 [(set_attr "alu_type" "sub")
3133 (set_attr "mode" "DI")])
3135 ;; The "legacy" (as opposed to "2008") form of NEG.fmt is an arithmetic
3136 ;; instruction that treats all NaN inputs as invalid; it does not flip
3137 ;; their sign bit. We therefore can't use that form if the signs of
3140 (define_insn "neg<mode>2"
3141 [(set (match_operand:ANYF 0 "register_operand" "=f")
3142 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
3143 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)"
3145 [(set_attr "type" "fneg")
3146 (set_attr "mode" "<UNITMODE>")])
3148 (define_insn "one_cmpl<mode>2"
3149 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
3150 (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))]
3154 return "not\t%0,%1";
3156 return "nor\t%0,%.,%1";
3158 [(set_attr "alu_type" "not")
3159 (set_attr "compression" "micromips,*")
3160 (set_attr "mode" "<MODE>")])
3163 ;; ....................
3167 ;; ....................
3170 ;; Many of these instructions use trivial define_expands, because we
3171 ;; want to use a different set of constraints when TARGET_MIPS16.
3173 (define_expand "and<mode>3"
3174 [(set (match_operand:GPR 0 "register_operand")
3175 (and:GPR (match_operand:GPR 1 "register_operand")
3176 (match_operand:GPR 2 "and_reg_operand")))])
3178 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
3179 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
3180 ;; Note that this variant does not trigger for SI mode because we require
3181 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
3182 ;; sign-extended SImode value.
3184 ;; These are possible combinations for operand 1 and 2. The table
3185 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
3186 ;; 16=MIPS16, x=match, S=split):
3188 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
3194 ;; 0xffff_ffff x S x S x
3199 (define_insn "*and<mode>3"
3200 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d")
3201 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d")
3202 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))]
3203 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
3207 switch (which_alternative)
3210 operands[1] = gen_lowpart (QImode, operands[1]);
3211 return "lbu\t%0,%1";
3213 operands[1] = gen_lowpart (HImode, operands[1]);
3214 return "lhu\t%0,%1";
3216 operands[1] = gen_lowpart (SImode, operands[1]);
3217 return "lwu\t%0,%1";
3220 return "andi\t%0,%1,%x2";
3222 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
3223 operands[2] = GEN_INT (len);
3224 return "<d>ext\t%0,%1,0,%2";
3229 return "and\t%0,%1,%2";
3234 [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical")
3235 (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*")
3236 (set_attr "mode" "<MODE>")])
3238 (define_insn "*and<mode>3_mips16"
3239 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3240 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0")
3241 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
3242 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
3244 switch (which_alternative)
3247 operands[1] = gen_lowpart (QImode, operands[1]);
3248 return "lbu\t%0,%1";
3250 operands[1] = gen_lowpart (HImode, operands[1]);
3251 return "lhu\t%0,%1";
3253 operands[1] = gen_lowpart (SImode, operands[1]);
3254 return "lwu\t%0,%1";
3258 return "and\t%0,%2";
3263 [(set_attr "move_type" "load,load,load,shift_shift,logical")
3264 (set_attr "mode" "<MODE>")])
3266 (define_expand "ior<mode>3"
3267 [(set (match_operand:GPR 0 "register_operand")
3268 (ior:GPR (match_operand:GPR 1 "register_operand")
3269 (match_operand:GPR 2 "uns_arith_operand")))]
3273 operands[2] = force_reg (<MODE>mode, operands[2]);
3276 (define_insn "*ior<mode>3"
3277 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3278 (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
3279 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
3285 [(set_attr "alu_type" "or")
3286 (set_attr "compression" "micromips,*,*")
3287 (set_attr "mode" "<MODE>")])
3289 (define_insn "*ior<mode>3_mips16"
3290 [(set (match_operand:GPR 0 "register_operand" "=d")
3291 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
3292 (match_operand:GPR 2 "register_operand" "d")))]
3295 [(set_attr "alu_type" "or")
3296 (set_attr "mode" "<MODE>")])
3298 (define_expand "xor<mode>3"
3299 [(set (match_operand:GPR 0 "register_operand")
3300 (xor:GPR (match_operand:GPR 1 "register_operand")
3301 (match_operand:GPR 2 "uns_arith_operand")))]
3305 (define_insn "*xor<mode>3"
3306 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3307 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
3308 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
3314 [(set_attr "alu_type" "xor")
3315 (set_attr "compression" "micromips,*,*")
3316 (set_attr "mode" "<MODE>")])
3318 (define_insn "*xor<mode>3_mips16"
3319 [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t")
3320 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d")
3321 (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))]
3328 [(set_attr "alu_type" "xor")
3329 (set_attr "mode" "<MODE>")
3330 (set_attr "extended_mips16" "no,no,yes,no")])
3332 (define_insn "*nor<mode>3"
3333 [(set (match_operand:GPR 0 "register_operand" "=d")
3334 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
3335 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
3338 [(set_attr "alu_type" "nor")
3339 (set_attr "mode" "<MODE>")])
3342 ;; ....................
3346 ;; ....................
3350 (define_insn "truncdfsf2"
3351 [(set (match_operand:SF 0 "register_operand" "=f")
3352 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3353 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3355 [(set_attr "type" "fcvt")
3356 (set_attr "cnv_mode" "D2S")
3357 (set_attr "mode" "SF")])
3359 ;; Integer truncation patterns. Truncating SImode values to smaller
3360 ;; modes is a no-op, as it is for most other GCC ports. Truncating
3361 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
3362 ;; need to make sure that the lower 32 bits are properly sign-extended
3363 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
3364 ;; smaller than SImode is equivalent to two separate truncations:
3367 ;; DI ---> HI == DI ---> SI ---> HI
3368 ;; DI ---> QI == DI ---> SI ---> QI
3370 ;; Step A needs a real instruction but step B does not.
3372 (define_insn "truncdi<mode>2"
3373 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
3374 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
3379 [(set_attr "move_type" "sll0,store")
3380 (set_attr "mode" "SI")])
3382 ;; Combiner patterns to optimize shift/truncate combinations.
3384 (define_insn "*ashr_trunc<mode>"
3385 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3387 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3388 (match_operand:DI 2 "const_arith_operand" ""))))]
3389 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3391 [(set_attr "type" "shift")
3392 (set_attr "mode" "<MODE>")])
3394 (define_insn "*lshr32_trunc<mode>"
3395 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3397 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3399 "TARGET_64BIT && !TARGET_MIPS16"
3401 [(set_attr "type" "shift")
3402 (set_attr "mode" "<MODE>")])
3404 ;; Logical shift by more than 32 results in proper SI values so truncation is
3405 ;; removed by the middle end. Note that a logical shift by 32 is handled by
3406 ;; the previous pattern.
3407 (define_insn "*<optab>_trunc<mode>_exts"
3408 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3410 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
3411 (match_operand:DI 2 "const_arith_operand" ""))))]
3412 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
3414 [(set_attr "type" "arith")
3415 (set_attr "mode" "<MODE>")])
3418 ;; ....................
3422 ;; ....................
3426 (define_expand "zero_extendsidi2"
3427 [(set (match_operand:DI 0 "register_operand")
3428 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
3431 (define_insn_and_split "*zero_extendsidi2"
3432 [(set (match_operand:DI 0 "register_operand" "=d,d")
3433 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3434 "TARGET_64BIT && !ISA_HAS_EXT_INS"
3438 "&& reload_completed && REG_P (operands[1])"
3440 (ashift:DI (match_dup 1) (const_int 32)))
3442 (lshiftrt:DI (match_dup 0) (const_int 32)))]
3443 { operands[1] = gen_lowpart (DImode, operands[1]); }
3444 [(set_attr "move_type" "shift_shift,load")
3445 (set_attr "mode" "DI")])
3447 (define_insn "*zero_extendsidi2_dext"
3448 [(set (match_operand:DI 0 "register_operand" "=d,d")
3449 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3450 "TARGET_64BIT && ISA_HAS_EXT_INS"
3454 [(set_attr "move_type" "arith,load")
3455 (set_attr "mode" "DI")])
3457 ;; See the comment before the *and<mode>3 pattern why this is generated by
3461 [(set (match_operand:DI 0 "register_operand")
3462 (and:DI (match_operand:DI 1 "register_operand")
3463 (const_int 4294967295)))]
3464 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
3466 (ashift:DI (match_dup 1) (const_int 32)))
3468 (lshiftrt:DI (match_dup 0) (const_int 32)))])
3470 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
3471 [(set (match_operand:GPR 0 "register_operand")
3472 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3475 if (TARGET_MIPS16 && !GENERATE_MIPS16E
3476 && !memory_operand (operands[1], <SHORT:MODE>mode))
3478 emit_insn (gen_and<GPR:mode>3 (operands[0],
3479 gen_lowpart (<GPR:MODE>mode, operands[1]),
3480 force_reg (<GPR:MODE>mode,
3481 GEN_INT (<SHORT:mask>))));
3486 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
3487 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3489 (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))]
3492 andi\t%0,%1,<SHORT:mask>
3493 andi\t%0,%1,<SHORT:mask>
3494 l<SHORT:size>u\t%0,%1"
3495 [(set_attr "move_type" "andi,andi,load")
3496 (set_attr "compression" "micromips,*,*")
3497 (set_attr "mode" "<GPR:MODE>")])
3499 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
3500 [(set (match_operand:GPR 0 "register_operand" "=d")
3501 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
3503 "ze<SHORT:size>\t%0"
3504 ;; This instruction is effectively a special encoding of ANDI.
3505 [(set_attr "move_type" "andi")
3506 (set_attr "mode" "<GPR:MODE>")])
3508 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
3509 [(set (match_operand:GPR 0 "register_operand" "=d")
3510 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
3512 "l<SHORT:size>u\t%0,%1"
3513 [(set_attr "move_type" "load")
3514 (set_attr "mode" "<GPR:MODE>")])
3516 (define_expand "zero_extendqihi2"
3517 [(set (match_operand:HI 0 "register_operand")
3518 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3521 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
3523 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
3529 (define_insn "*zero_extendqihi2"
3530 [(set (match_operand:HI 0 "register_operand" "=d,d")
3531 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3536 [(set_attr "move_type" "andi,load")
3537 (set_attr "mode" "HI")])
3539 (define_insn "*zero_extendqihi2_mips16"
3540 [(set (match_operand:HI 0 "register_operand" "=d")
3541 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3544 [(set_attr "move_type" "load")
3545 (set_attr "mode" "HI")])
3547 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3549 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
3550 [(set (match_operand:GPR 0 "register_operand" "=d")
3552 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3553 "TARGET_64BIT && !TARGET_MIPS16"
3555 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3556 return "andi\t%0,%1,%x2";
3558 [(set_attr "alu_type" "and")
3559 (set_attr "mode" "<GPR:MODE>")])
3561 (define_insn "*zero_extendhi_truncqi"
3562 [(set (match_operand:HI 0 "register_operand" "=d")
3564 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3565 "TARGET_64BIT && !TARGET_MIPS16"
3567 [(set_attr "alu_type" "and")
3568 (set_attr "mode" "HI")])
3571 ;; ....................
3575 ;; ....................
3578 ;; Those for integer source operand are ordered widest source type first.
3580 ;; When TARGET_64BIT, all SImode integer and accumulator registers
3581 ;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
3582 ;; and truncdisi2). We can therefore get rid of register->register
3583 ;; instructions if we constrain the source to be in the same register as
3586 ;; Only the pre-reload scheduler sees the type of the register alternatives;
3587 ;; we split them into nothing before the post-reload scheduler runs.
3588 ;; These alternatives therefore have type "move" in order to reflect
3589 ;; what happens if the two pre-reload operands cannot be tied, and are
3590 ;; instead allocated two separate GPRs. We don't distinguish between
3591 ;; the GPR and LO cases because we don't usually know during pre-reload
3592 ;; scheduling whether an operand will be LO or not.
3593 (define_insn_and_split "extendsidi2"
3594 [(set (match_operand:DI 0 "register_operand" "=d,l,d")
3595 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
3601 "&& reload_completed && register_operand (operands[1], VOIDmode)"
3604 emit_note (NOTE_INSN_DELETED);
3607 [(set_attr "move_type" "move,move,load")
3608 (set_attr "mode" "DI")])
3610 (define_expand "extend<SHORT:mode><GPR:mode>2"
3611 [(set (match_operand:GPR 0 "register_operand")
3612 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3615 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
3616 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3617 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3621 l<SHORT:size>\t%0,%1"
3622 [(set_attr "move_type" "signext,load")
3623 (set_attr "mode" "<GPR:MODE>")])
3625 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3626 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3628 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3629 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3632 l<SHORT:size>\t%0,%1"
3633 "&& reload_completed && REG_P (operands[1])"
3634 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3635 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3637 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3638 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3639 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3641 [(set_attr "move_type" "shift_shift,load")
3642 (set_attr "mode" "<GPR:MODE>")])
3644 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3645 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3647 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3650 se<SHORT:size>\t%0,%1
3651 l<SHORT:size>\t%0,%1"
3652 [(set_attr "move_type" "signext,load")
3653 (set_attr "mode" "<GPR:MODE>")])
3655 (define_expand "extendqihi2"
3656 [(set (match_operand:HI 0 "register_operand")
3657 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3660 (define_insn "*extendqihi2_mips16e"
3661 [(set (match_operand:HI 0 "register_operand" "=d,d")
3662 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3667 [(set_attr "move_type" "signext,load")
3668 (set_attr "mode" "SI")])
3670 (define_insn_and_split "*extendqihi2"
3671 [(set (match_operand:HI 0 "register_operand" "=d,d")
3673 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3674 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3678 "&& reload_completed && REG_P (operands[1])"
3679 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3680 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3682 operands[0] = gen_lowpart (SImode, operands[0]);
3683 operands[1] = gen_lowpart (SImode, operands[1]);
3684 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3685 - GET_MODE_BITSIZE (QImode));
3687 [(set_attr "move_type" "shift_shift,load")
3688 (set_attr "mode" "SI")])
3690 (define_insn "*extendqihi2_seb"
3691 [(set (match_operand:HI 0 "register_operand" "=d,d")
3693 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3698 [(set_attr "move_type" "signext,load")
3699 (set_attr "mode" "SI")])
3701 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3702 ;; use the shift/truncate patterns.
3704 (define_insn_and_split "*extenddi_truncate<mode>"
3705 [(set (match_operand:DI 0 "register_operand" "=d")
3707 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3708 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3710 "&& reload_completed"
3712 (ashift:DI (match_dup 1)
3715 (ashiftrt:DI (match_dup 2)
3718 operands[2] = gen_lowpart (DImode, operands[0]);
3719 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3721 [(set_attr "move_type" "shift_shift")
3722 (set_attr "mode" "DI")])
3724 (define_insn_and_split "*extendsi_truncate<mode>"
3725 [(set (match_operand:SI 0 "register_operand" "=d")
3727 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3728 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3730 "&& reload_completed"
3732 (ashift:DI (match_dup 1)
3735 (truncate:SI (ashiftrt:DI (match_dup 2)
3738 operands[2] = gen_lowpart (DImode, operands[0]);
3739 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3741 [(set_attr "move_type" "shift_shift")
3742 (set_attr "mode" "SI")])
3744 (define_insn_and_split "*extendhi_truncateqi"
3745 [(set (match_operand:HI 0 "register_operand" "=d")
3747 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3748 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3750 "&& reload_completed"
3752 (ashift:DI (match_dup 1)
3755 (truncate:HI (ashiftrt:DI (match_dup 2)
3758 operands[2] = gen_lowpart (DImode, operands[0]);
3760 [(set_attr "move_type" "shift_shift")
3761 (set_attr "mode" "SI")])
3763 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3764 [(set (match_operand:GPR 0 "register_operand" "=d")
3766 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3767 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3769 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3770 return "exts\t%0,%1,0,%m2";
3772 [(set_attr "type" "arith")
3773 (set_attr "mode" "<GPR:MODE>")])
3775 (define_insn "*extendhi_truncateqi_exts"
3776 [(set (match_operand:HI 0 "register_operand" "=d")
3778 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3779 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3781 [(set_attr "type" "arith")
3782 (set_attr "mode" "SI")])
3784 (define_insn "extendsfdf2"
3785 [(set (match_operand:DF 0 "register_operand" "=f")
3786 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3787 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3789 [(set_attr "type" "fcvt")
3790 (set_attr "cnv_mode" "S2D")
3791 (set_attr "mode" "DF")])
3794 ;; ....................
3798 ;; ....................
3800 (define_expand "fix_truncdfsi2"
3801 [(set (match_operand:SI 0 "register_operand")
3802 (fix:SI (match_operand:DF 1 "register_operand")))]
3803 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3805 if (!ISA_HAS_TRUNC_W)
3807 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3812 (define_insn "fix_truncdfsi2_insn"
3813 [(set (match_operand:SI 0 "register_operand" "=f")
3814 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3815 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3817 [(set_attr "type" "fcvt")
3818 (set_attr "mode" "DF")
3819 (set_attr "cnv_mode" "D2I")])
3821 (define_insn "fix_truncdfsi2_macro"
3822 [(set (match_operand:SI 0 "register_operand" "=f")
3823 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3824 (clobber (match_scratch:DF 2 "=d"))]
3825 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3827 if (mips_nomacro.nesting_level > 0)
3828 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3830 return "trunc.w.d %0,%1,%2";
3832 [(set_attr "type" "fcvt")
3833 (set_attr "mode" "DF")
3834 (set_attr "cnv_mode" "D2I")
3835 (set_attr "insn_count" "9")])
3837 (define_expand "fix_truncsfsi2"
3838 [(set (match_operand:SI 0 "register_operand")
3839 (fix:SI (match_operand:SF 1 "register_operand")))]
3842 if (!ISA_HAS_TRUNC_W)
3844 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3849 (define_insn "fix_truncsfsi2_insn"
3850 [(set (match_operand:SI 0 "register_operand" "=f")
3851 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3852 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3854 [(set_attr "type" "fcvt")
3855 (set_attr "mode" "SF")
3856 (set_attr "cnv_mode" "S2I")])
3858 (define_insn "fix_truncsfsi2_macro"
3859 [(set (match_operand:SI 0 "register_operand" "=f")
3860 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3861 (clobber (match_scratch:SF 2 "=d"))]
3862 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3864 if (mips_nomacro.nesting_level > 0)
3865 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3867 return "trunc.w.s %0,%1,%2";
3869 [(set_attr "type" "fcvt")
3870 (set_attr "mode" "SF")
3871 (set_attr "cnv_mode" "S2I")
3872 (set_attr "insn_count" "9")])
3875 (define_insn "fix_truncdfdi2"
3876 [(set (match_operand:DI 0 "register_operand" "=f")
3877 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3878 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3880 [(set_attr "type" "fcvt")
3881 (set_attr "mode" "DF")
3882 (set_attr "cnv_mode" "D2I")])
3885 (define_insn "fix_truncsfdi2"
3886 [(set (match_operand:DI 0 "register_operand" "=f")
3887 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3888 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3890 [(set_attr "type" "fcvt")
3891 (set_attr "mode" "SF")
3892 (set_attr "cnv_mode" "S2I")])
3895 (define_insn "floatsidf2"
3896 [(set (match_operand:DF 0 "register_operand" "=f")
3897 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3898 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3900 [(set_attr "type" "fcvt")
3901 (set_attr "mode" "DF")
3902 (set_attr "cnv_mode" "I2D")])
3905 (define_insn "floatdidf2"
3906 [(set (match_operand:DF 0 "register_operand" "=f")
3907 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3908 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3910 [(set_attr "type" "fcvt")
3911 (set_attr "mode" "DF")
3912 (set_attr "cnv_mode" "I2D")])
3915 (define_insn "floatsisf2"
3916 [(set (match_operand:SF 0 "register_operand" "=f")
3917 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3920 [(set_attr "type" "fcvt")
3921 (set_attr "mode" "SF")
3922 (set_attr "cnv_mode" "I2S")])
3925 (define_insn "floatdisf2"
3926 [(set (match_operand:SF 0 "register_operand" "=f")
3927 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3928 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3930 [(set_attr "type" "fcvt")
3931 (set_attr "mode" "SF")
3932 (set_attr "cnv_mode" "I2S")])
3935 (define_expand "fixuns_truncdfsi2"
3936 [(set (match_operand:SI 0 "register_operand")
3937 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3938 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3940 rtx reg1 = gen_reg_rtx (DFmode);
3941 rtx reg2 = gen_reg_rtx (DFmode);
3942 rtx reg3 = gen_reg_rtx (SImode);
3943 rtx_code_label *label1 = gen_label_rtx ();
3944 rtx_code_label *label2 = gen_label_rtx ();
3946 REAL_VALUE_TYPE offset;
3948 real_2expN (&offset, 31, DFmode);
3950 if (reg1) /* Turn off complaints about unreached code. */
3952 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3953 do_pending_stack_adjust ();
3955 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3956 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3958 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3959 emit_jump_insn (gen_rtx_SET (pc_rtx,
3960 gen_rtx_LABEL_REF (VOIDmode, label2)));
3963 emit_label (label1);
3964 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3965 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3966 (BITMASK_HIGH, SImode)));
3968 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3969 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3971 emit_label (label2);
3973 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3974 fields, and can't be used for REG_NOTES anyway). */
3975 emit_use (stack_pointer_rtx);
3981 (define_expand "fixuns_truncdfdi2"
3982 [(set (match_operand:DI 0 "register_operand")
3983 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3984 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3986 rtx reg1 = gen_reg_rtx (DFmode);
3987 rtx reg2 = gen_reg_rtx (DFmode);
3988 rtx reg3 = gen_reg_rtx (DImode);
3989 rtx_code_label *label1 = gen_label_rtx ();
3990 rtx_code_label *label2 = gen_label_rtx ();
3992 REAL_VALUE_TYPE offset;
3994 real_2expN (&offset, 63, DFmode);
3996 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3997 do_pending_stack_adjust ();
3999 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4000 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
4002 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
4003 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4006 emit_label (label1);
4007 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4008 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
4009 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4011 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
4012 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4014 emit_label (label2);
4016 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4017 fields, and can't be used for REG_NOTES anyway). */
4018 emit_use (stack_pointer_rtx);
4023 (define_expand "fixuns_truncsfsi2"
4024 [(set (match_operand:SI 0 "register_operand")
4025 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
4028 rtx reg1 = gen_reg_rtx (SFmode);
4029 rtx reg2 = gen_reg_rtx (SFmode);
4030 rtx reg3 = gen_reg_rtx (SImode);
4031 rtx_code_label *label1 = gen_label_rtx ();
4032 rtx_code_label *label2 = gen_label_rtx ();
4034 REAL_VALUE_TYPE offset;
4036 real_2expN (&offset, 31, SFmode);
4038 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
4039 do_pending_stack_adjust ();
4041 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4042 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
4044 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
4045 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4048 emit_label (label1);
4049 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4050 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
4051 (BITMASK_HIGH, SImode)));
4053 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
4054 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4056 emit_label (label2);
4058 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4059 fields, and can't be used for REG_NOTES anyway). */
4060 emit_use (stack_pointer_rtx);
4065 (define_expand "fixuns_truncsfdi2"
4066 [(set (match_operand:DI 0 "register_operand")
4067 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
4068 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4070 rtx reg1 = gen_reg_rtx (SFmode);
4071 rtx reg2 = gen_reg_rtx (SFmode);
4072 rtx reg3 = gen_reg_rtx (DImode);
4073 rtx_code_label *label1 = gen_label_rtx ();
4074 rtx_code_label *label2 = gen_label_rtx ();
4076 REAL_VALUE_TYPE offset;
4078 real_2expN (&offset, 63, SFmode);
4080 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
4081 do_pending_stack_adjust ();
4083 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4084 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
4086 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
4087 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4090 emit_label (label1);
4091 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4092 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
4093 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4095 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
4096 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4098 emit_label (label2);
4100 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4101 fields, and can't be used for REG_NOTES anyway). */
4102 emit_use (stack_pointer_rtx);
4107 ;; ....................
4111 ;; ....................
4113 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
4115 (define_expand "extvmisalign<mode>"
4116 [(set (match_operand:GPR 0 "register_operand")
4117 (sign_extract:GPR (match_operand:BLK 1 "memory_operand")
4118 (match_operand 2 "const_int_operand")
4119 (match_operand 3 "const_int_operand")))]
4122 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
4123 INTVAL (operands[2]),
4124 INTVAL (operands[3]),
4125 /*unsigned=*/ false))
4131 (define_expand "extv<mode>"
4132 [(set (match_operand:GPR 0 "register_operand")
4133 (sign_extract:GPR (match_operand:GPR 1 "register_operand")
4134 (match_operand 2 "const_int_operand")
4135 (match_operand 3 "const_int_operand")))]
4138 if (UINTVAL (operands[2]) > 32)
4142 (define_insn "*extv<mode>"
4143 [(set (match_operand:GPR 0 "register_operand" "=d")
4144 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
4145 (match_operand 2 "const_int_operand" "")
4146 (match_operand 3 "const_int_operand" "")))]
4147 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
4148 "exts\t%0,%1,%3,%m2"
4149 [(set_attr "type" "arith")
4150 (set_attr "mode" "<MODE>")])
4152 (define_expand "extzvmisalign<mode>"
4153 [(set (match_operand:GPR 0 "register_operand")
4154 (zero_extract:GPR (match_operand:BLK 1 "memory_operand")
4155 (match_operand 2 "const_int_operand")
4156 (match_operand 3 "const_int_operand")))]
4159 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
4160 INTVAL (operands[2]),
4161 INTVAL (operands[3]),
4162 /*unsigned=*/ true))
4168 (define_expand "extzv<mode>"
4169 [(set (match_operand:GPR 0 "register_operand")
4170 (zero_extract:GPR (match_operand:GPR 1 "register_operand")
4171 (match_operand 2 "const_int_operand")
4172 (match_operand 3 "const_int_operand")))]
4175 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
4176 INTVAL (operands[3])))
4180 (define_insn "*extzv<mode>"
4181 [(set (match_operand:GPR 0 "register_operand" "=d")
4182 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
4183 (match_operand 2 "const_int_operand" "")
4184 (match_operand 3 "const_int_operand" "")))]
4185 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
4186 INTVAL (operands[3]))"
4187 "<d>ext\t%0,%1,%3,%2"
4188 [(set_attr "type" "arith")
4189 (set_attr "mode" "<MODE>")])
4191 (define_insn "*extzv_truncsi_exts"
4192 [(set (match_operand:SI 0 "register_operand" "=d")
4194 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
4195 (match_operand 2 "const_int_operand" "")
4196 (match_operand 3 "const_int_operand" ""))))]
4197 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
4199 [(set_attr "type" "arith")
4200 (set_attr "mode" "SI")])
4203 (define_expand "insvmisalign<mode>"
4204 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")
4205 (match_operand 1 "const_int_operand")
4206 (match_operand 2 "const_int_operand"))
4207 (match_operand:GPR 3 "reg_or_0_operand"))]
4210 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
4211 INTVAL (operands[1]),
4212 INTVAL (operands[2])))
4218 (define_expand "insv<mode>"
4219 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand")
4220 (match_operand 1 "const_int_operand")
4221 (match_operand 2 "const_int_operand"))
4222 (match_operand:GPR 3 "reg_or_0_operand"))]
4225 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
4226 INTVAL (operands[2])))
4230 (define_insn "*insv<mode>"
4231 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
4232 (match_operand:SI 1 "const_int_operand" "")
4233 (match_operand:SI 2 "const_int_operand" ""))
4234 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
4235 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
4236 INTVAL (operands[2]))"
4237 "<d>ins\t%0,%z3,%2,%1"
4238 [(set_attr "type" "arith")
4239 (set_attr "mode" "<MODE>")])
4241 ;; Combiner pattern for cins (clear and insert bit field). We can
4242 ;; implement mask-and-shift-left operation with this. Note that if
4243 ;; the upper bit of the mask is set in an SImode operation, the mask
4244 ;; itself will be sign-extended. mask_low_and_shift_len will
4245 ;; therefore be greater than our threshold of 32.
4247 (define_insn "*cins<mode>"
4248 [(set (match_operand:GPR 0 "register_operand" "=d")
4250 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
4251 (match_operand:GPR 2 "const_int_operand" ""))
4252 (match_operand:GPR 3 "const_int_operand" "")))]
4254 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
4257 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
4258 return "cins\t%0,%1,%2,%m3";
4260 [(set_attr "type" "shift")
4261 (set_attr "mode" "<MODE>")])
4263 ;; Unaligned word moves generated by the bit field patterns.
4265 ;; As far as the rtl is concerned, both the left-part and right-part
4266 ;; instructions can access the whole field. However, the real operand
4267 ;; refers to just the first or the last byte (depending on endianness).
4268 ;; We therefore use two memory operands to each instruction, one to
4269 ;; describe the rtl effect and one to use in the assembly output.
4271 ;; Operands 0 and 1 are the rtl-level target and source respectively.
4272 ;; This allows us to use the standard length calculations for the "load"
4273 ;; and "store" type attributes.
4275 (define_insn "mov_<load>l"
4276 [(set (match_operand:GPR 0 "register_operand" "=d")
4277 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
4278 (match_operand:QI 2 "memory_operand" "ZC")]
4280 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
4282 [(set_attr "move_type" "load")
4283 (set_attr "mode" "<MODE>")])
4285 (define_insn "mov_<load>r"
4286 [(set (match_operand:GPR 0 "register_operand" "=d")
4287 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
4288 (match_operand:QI 2 "memory_operand" "ZC")
4289 (match_operand:GPR 3 "register_operand" "0")]
4290 UNSPEC_LOAD_RIGHT))]
4291 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
4293 [(set_attr "move_type" "load")
4294 (set_attr "mode" "<MODE>")])
4296 (define_insn "mov_<store>l"
4297 [(set (match_operand:BLK 0 "memory_operand" "=m")
4298 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4299 (match_operand:QI 2 "memory_operand" "ZC")]
4300 UNSPEC_STORE_LEFT))]
4301 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
4303 [(set_attr "move_type" "store")
4304 (set_attr "mode" "<MODE>")])
4306 (define_insn "mov_<store>r"
4307 [(set (match_operand:BLK 0 "memory_operand" "+m")
4308 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4309 (match_operand:QI 2 "memory_operand" "ZC")
4311 UNSPEC_STORE_RIGHT))]
4312 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
4314 [(set_attr "move_type" "store")
4315 (set_attr "mode" "<MODE>")])
4317 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
4318 ;; The required value is:
4320 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
4322 ;; which translates to:
4324 ;; lui op0,%highest(op1)
4325 ;; daddiu op0,op0,%higher(op1)
4327 ;; daddiu op0,op0,%hi(op1)
4330 ;; The split is deferred until after flow2 to allow the peephole2 below
4332 (define_insn_and_split "*lea_high64"
4333 [(set (match_operand:DI 0 "register_operand" "=d")
4334 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
4335 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4337 "&& epilogue_completed"
4338 [(set (match_dup 0) (high:DI (match_dup 2)))
4339 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
4340 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
4341 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4342 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
4344 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4345 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
4347 [(set_attr "insn_count" "5")])
4349 ;; Use a scratch register to reduce the latency of the above pattern
4350 ;; on superscalar machines. The optimized sequence is:
4352 ;; lui op1,%highest(op2)
4354 ;; daddiu op1,op1,%higher(op2)
4356 ;; daddu op1,op1,op0
4358 [(set (match_operand:DI 1 "d_operand")
4359 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
4360 (match_scratch:DI 0 "d")]
4361 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4362 [(set (match_dup 1) (high:DI (match_dup 3)))
4363 (set (match_dup 0) (high:DI (match_dup 4)))
4364 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
4365 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
4366 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
4368 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
4369 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
4372 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
4373 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
4374 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
4375 ;; used once. We can then use the sequence:
4377 ;; lui op0,%highest(op1)
4379 ;; daddiu op0,op0,%higher(op1)
4380 ;; daddiu op2,op2,%lo(op1)
4382 ;; daddu op0,op0,op2
4384 ;; which takes 4 cycles on most superscalar targets.
4385 (define_insn_and_split "*lea64"
4386 [(set (match_operand:DI 0 "register_operand" "=d")
4387 (match_operand:DI 1 "absolute_symbolic_operand" ""))
4388 (clobber (match_scratch:DI 2 "=&d"))]
4390 && TARGET_EXPLICIT_RELOCS
4391 && ABI_HAS_64BIT_SYMBOLS
4392 && cse_not_expected"
4394 "&& reload_completed"
4395 [(set (match_dup 0) (high:DI (match_dup 3)))
4396 (set (match_dup 2) (high:DI (match_dup 4)))
4397 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4398 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
4399 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
4400 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
4402 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4403 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
4405 [(set_attr "insn_count" "6")])
4407 ;; Split HIGHs into:
4412 ;; on MIPS16 targets.
4414 [(set (match_operand:P 0 "d_operand")
4415 (high:P (match_operand:P 1 "symbolic_operand_with_high")))]
4416 "TARGET_MIPS16 && reload_completed"
4417 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH))
4418 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))])
4420 (define_insn "*unshifted_high"
4421 [(set (match_operand:P 0 "d_operand" "=d")
4422 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")]
4423 UNSPEC_UNSHIFTED_HIGH))]
4426 [(set_attr "extended_mips16" "yes")])
4428 ;; Insns to fetch a symbol from a big GOT.
4430 (define_insn_and_split "*xgot_hi<mode>"
4431 [(set (match_operand:P 0 "register_operand" "=d")
4432 (high:P (match_operand:P 1 "got_disp_operand" "")))]
4433 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4435 "&& reload_completed"
4436 [(set (match_dup 0) (high:P (match_dup 2)))
4437 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
4439 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
4440 operands[3] = pic_offset_table_rtx;
4442 [(set_attr "got" "xgot_high")
4443 (set_attr "mode" "<MODE>")])
4445 (define_insn_and_split "*xgot_lo<mode>"
4446 [(set (match_operand:P 0 "register_operand" "=d")
4447 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4448 (match_operand:P 2 "got_disp_operand" "")))]
4449 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4451 "&& reload_completed"
4453 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
4454 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
4455 [(set_attr "got" "load")
4456 (set_attr "mode" "<MODE>")])
4458 ;; Insns to fetch a symbol from a normal GOT.
4460 (define_insn_and_split "*got_disp<mode>"
4461 [(set (match_operand:P 0 "register_operand" "=d")
4462 (match_operand:P 1 "got_disp_operand" ""))]
4463 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
4465 "&& reload_completed"
4466 [(set (match_dup 0) (match_dup 2))]
4467 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
4468 [(set_attr "got" "load")
4469 (set_attr "mode" "<MODE>")])
4471 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
4473 (define_insn_and_split "*got_page<mode>"
4474 [(set (match_operand:P 0 "register_operand" "=d")
4475 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
4476 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
4478 "&& reload_completed"
4479 [(set (match_dup 0) (match_dup 2))]
4480 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
4481 [(set_attr "got" "load")
4482 (set_attr "mode" "<MODE>")])
4484 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
4485 (define_expand "unspec_got_<mode>"
4486 [(unspec:P [(match_operand:P 0)
4487 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
4489 ;; Lower-level instructions for loading an address from the GOT.
4490 ;; We could use MEMs, but an unspec gives more optimization
4493 (define_insn "load_got<mode>"
4494 [(set (match_operand:P 0 "register_operand" "=d")
4495 (unspec:P [(match_operand:P 1 "register_operand" "d")
4496 (match_operand:P 2 "immediate_operand" "")]
4499 "<load>\t%0,%R2(%1)"
4500 [(set_attr "got" "load")
4501 (set_attr "mode" "<MODE>")])
4503 ;; Instructions for adding the low 16 bits of an address to a register.
4504 ;; Operand 2 is the address: mips_print_operand works out which relocation
4505 ;; should be applied.
4507 (define_insn "*low<mode>"
4508 [(set (match_operand:P 0 "register_operand" "=d")
4509 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4510 (match_operand:P 2 "immediate_operand" "")))]
4512 "<d>addiu\t%0,%1,%R2"
4513 [(set_attr "alu_type" "add")
4514 (set_attr "mode" "<MODE>")])
4516 (define_insn "*low<mode>_mips16"
4517 [(set (match_operand:P 0 "register_operand" "=d")
4518 (lo_sum:P (match_operand:P 1 "register_operand" "0")
4519 (match_operand:P 2 "immediate_operand" "")))]
4522 [(set_attr "alu_type" "add")
4523 (set_attr "mode" "<MODE>")
4524 (set_attr "extended_mips16" "yes")])
4526 ;; Expose MIPS16 uses of the global pointer after reload if the function
4527 ;; is responsible for setting up the register itself.
4529 [(set (match_operand:GPR 0 "d_operand")
4530 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
4531 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
4532 [(set (match_dup 0) (match_dup 1))]
4533 { operands[1] = pic_offset_table_rtx; })
4535 ;; Allow combine to split complex const_int load sequences, using operand 2
4536 ;; to store the intermediate results. See move_operand for details.
4538 [(set (match_operand:GPR 0 "register_operand")
4539 (match_operand:GPR 1 "splittable_const_int_operand"))
4540 (clobber (match_operand:GPR 2 "register_operand"))]
4544 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
4548 ;; Likewise, for symbolic operands.
4550 [(set (match_operand:P 0 "register_operand")
4551 (match_operand:P 1))
4552 (clobber (match_operand:P 2 "register_operand"))]
4553 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
4554 [(set (match_dup 0) (match_dup 3))]
4556 mips_split_symbol (operands[2], operands[1],
4557 MAX_MACHINE_MODE, &operands[3]);
4560 ;; 64-bit integer moves
4562 ;; Unlike most other insns, the move insns can't be split with
4563 ;; different predicates, because register spilling and other parts of
4564 ;; the compiler, have memoized the insn number already.
4566 (define_expand "movdi"
4567 [(set (match_operand:DI 0 "")
4568 (match_operand:DI 1 ""))]
4571 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4575 ;; For mips16, we need a special case to handle storing $31 into
4576 ;; memory, since we don't have a constraint to match $31. This
4577 ;; instruction can be generated by save_restore_insns.
4579 (define_insn "*mov<mode>_ra"
4580 [(set (match_operand:GPR 0 "stack_operand" "=m")
4581 (reg:GPR RETURN_ADDR_REGNUM))]
4584 [(set_attr "move_type" "store")
4585 (set_attr "mode" "<MODE>")])
4587 (define_insn "*movdi_32bit"
4588 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
4589 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
4590 "!TARGET_64BIT && !TARGET_MIPS16
4591 && (register_operand (operands[0], DImode)
4592 || reg_or_0_operand (operands[1], DImode))"
4593 { return mips_output_move (operands[0], operands[1]); }
4594 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
4596 (if_then_else (eq_attr "move_type" "imul")
4598 (const_string "DI")))])
4600 (define_insn "*movdi_32bit_mips16"
4601 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4602 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
4603 "!TARGET_64BIT && TARGET_MIPS16
4604 && (register_operand (operands[0], DImode)
4605 || register_operand (operands[1], DImode))"
4606 { return mips_output_move (operands[0], operands[1]); }
4607 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4608 (set_attr "mode" "DI")])
4610 (define_insn "*movdi_64bit"
4611 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
4612 (match_operand:DI 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4613 "TARGET_64BIT && !TARGET_MIPS16
4614 && (register_operand (operands[0], DImode)
4615 || reg_or_0_operand (operands[1], DImode))"
4616 { return mips_output_move (operands[0], operands[1]); }
4617 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore")
4618 (set_attr "mode" "DI")])
4620 (define_insn "*movdi_64bit_mips16"
4621 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4622 (match_operand:DI 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4623 "TARGET_64BIT && TARGET_MIPS16
4624 && (register_operand (operands[0], DImode)
4625 || register_operand (operands[1], DImode))"
4626 { return mips_output_move (operands[0], operands[1]); }
4627 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4628 (set_attr "mode" "DI")])
4630 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4631 ;; when the original load is a 4 byte instruction but the add and the
4632 ;; load are 2 2 byte instructions.
4635 [(set (match_operand:DI 0 "d_operand")
4636 (mem:DI (plus:DI (match_dup 0)
4637 (match_operand:DI 1 "const_int_operand"))))]
4638 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4639 && !TARGET_DEBUG_D_MODE
4640 && ((INTVAL (operands[1]) < 0
4641 && INTVAL (operands[1]) >= -0x10)
4642 || (INTVAL (operands[1]) >= 32 * 8
4643 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4644 || (INTVAL (operands[1]) >= 0
4645 && INTVAL (operands[1]) < 32 * 8
4646 && (INTVAL (operands[1]) & 7) != 0))"
4647 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4648 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4650 HOST_WIDE_INT val = INTVAL (operands[1]);
4653 operands[2] = const0_rtx;
4654 else if (val >= 32 * 8)
4658 operands[1] = GEN_INT (0x8 + off);
4659 operands[2] = GEN_INT (val - off - 0x8);
4665 operands[1] = GEN_INT (off);
4666 operands[2] = GEN_INT (val - off);
4670 ;; 32-bit Integer moves
4672 ;; Unlike most other insns, the move insns can't be split with
4673 ;; different predicates, because register spilling and other parts of
4674 ;; the compiler, have memoized the insn number already.
4676 (define_expand "mov<mode>"
4677 [(set (match_operand:IMOVE32 0 "")
4678 (match_operand:IMOVE32 1 ""))]
4681 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4685 ;; The difference between these two is whether or not ints are allowed
4686 ;; in FP registers (off by default, use -mdebugh to enable).
4688 (define_insn "*mov<mode>_internal"
4689 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4690 (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!kbJ,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4692 && (register_operand (operands[0], <MODE>mode)
4693 || reg_or_0_operand (operands[1], <MODE>mode))"
4694 { return mips_output_move (operands[0], operands[1]); }
4695 [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore")
4696 (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*")
4697 (set_attr "mode" "SI")])
4699 (define_insn "*mov<mode>_mips16"
4700 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4701 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4703 && (register_operand (operands[0], <MODE>mode)
4704 || register_operand (operands[1], <MODE>mode))"
4705 { return mips_output_move (operands[0], operands[1]); }
4706 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4707 (set_attr "mode" "SI")])
4709 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4710 ;; when the original load is a 4 byte instruction but the add and the
4711 ;; load are 2 2 byte instructions.
4714 [(set (match_operand:SI 0 "d_operand")
4715 (mem:SI (plus:SI (match_dup 0)
4716 (match_operand:SI 1 "const_int_operand"))))]
4717 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4718 && ((INTVAL (operands[1]) < 0
4719 && INTVAL (operands[1]) >= -0x80)
4720 || (INTVAL (operands[1]) >= 32 * 4
4721 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4722 || (INTVAL (operands[1]) >= 0
4723 && INTVAL (operands[1]) < 32 * 4
4724 && (INTVAL (operands[1]) & 3) != 0))"
4725 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4726 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4728 HOST_WIDE_INT val = INTVAL (operands[1]);
4731 operands[2] = const0_rtx;
4732 else if (val >= 32 * 4)
4736 operands[1] = GEN_INT (0x7c + off);
4737 operands[2] = GEN_INT (val - off - 0x7c);
4743 operands[1] = GEN_INT (off);
4744 operands[2] = GEN_INT (val - off);
4748 ;; On the mips16, we can split a load of certain constants into a load
4749 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4753 [(set (match_operand:SI 0 "d_operand")
4754 (match_operand:SI 1 "const_int_operand"))]
4755 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4756 && INTVAL (operands[1]) >= 0x100
4757 && INTVAL (operands[1]) <= 0xff + 0x7f"
4758 [(set (match_dup 0) (match_dup 1))
4759 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4761 int val = INTVAL (operands[1]);
4763 operands[1] = GEN_INT (0xff);
4764 operands[2] = GEN_INT (val - 0xff);
4767 ;; MIPS4 supports loading and storing a floating point register from
4768 ;; the sum of two general registers. We use two versions for each of
4769 ;; these four instructions: one where the two general registers are
4770 ;; SImode, and one where they are DImode. This is because general
4771 ;; registers will be in SImode when they hold 32-bit values, but,
4772 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4773 ;; instructions will still work correctly.
4775 ;; ??? Perhaps it would be better to support these instructions by
4776 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4777 ;; these instructions can only be used to load and store floating
4778 ;; point registers, that would probably cause trouble in reload.
4780 (define_insn "*<ANYF:loadx>_<P:mode>"
4781 [(set (match_operand:ANYF 0 "register_operand" "=f")
4782 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4783 (match_operand:P 2 "register_operand" "d"))))]
4785 "<ANYF:loadx>\t%0,%1(%2)"
4786 [(set_attr "type" "fpidxload")
4787 (set_attr "mode" "<ANYF:UNITMODE>")])
4789 (define_insn "*<ANYF:storex>_<P:mode>"
4790 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4791 (match_operand:P 2 "register_operand" "d")))
4792 (match_operand:ANYF 0 "register_operand" "f"))]
4794 "<ANYF:storex>\t%0,%1(%2)"
4795 [(set_attr "type" "fpidxstore")
4796 (set_attr "mode" "<ANYF:UNITMODE>")])
4798 ;; Scaled indexed address load.
4799 ;; Per md.texi, we only need to look for a pattern with multiply in the
4800 ;; address expression, not shift.
4802 (define_insn "*lwxs"
4803 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4805 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4807 (match_operand:P 2 "register_operand" "d"))))]
4810 [(set_attr "type" "load")
4811 (set_attr "mode" "SI")])
4813 ;; 16-bit Integer moves
4815 ;; Unlike most other insns, the move insns can't be split with
4816 ;; different predicates, because register spilling and other parts of
4817 ;; the compiler, have memoized the insn number already.
4818 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4820 (define_expand "movhi"
4821 [(set (match_operand:HI 0 "")
4822 (match_operand:HI 1 ""))]
4825 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4829 (define_insn "*movhi_internal"
4830 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d")
4831 (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!kbJ,dJ,*d*J,*a"))]
4833 && (register_operand (operands[0], HImode)
4834 || reg_or_0_operand (operands[1], HImode))"
4835 { return mips_output_move (operands[0], operands[1]); }
4836 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4837 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4838 (set_attr "mode" "HI")])
4840 (define_insn "*movhi_mips16"
4841 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4842 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4844 && (register_operand (operands[0], HImode)
4845 || register_operand (operands[1], HImode))"
4846 { return mips_output_move (operands[0], operands[1]); }
4847 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4848 (set_attr "mode" "HI")])
4850 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4851 ;; when the original load is a 4 byte instruction but the add and the
4852 ;; load are 2 2 byte instructions.
4855 [(set (match_operand:HI 0 "d_operand")
4856 (mem:HI (plus:SI (match_dup 0)
4857 (match_operand:SI 1 "const_int_operand"))))]
4858 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4859 && ((INTVAL (operands[1]) < 0
4860 && INTVAL (operands[1]) >= -0x80)
4861 || (INTVAL (operands[1]) >= 32 * 2
4862 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4863 || (INTVAL (operands[1]) >= 0
4864 && INTVAL (operands[1]) < 32 * 2
4865 && (INTVAL (operands[1]) & 1) != 0))"
4866 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4867 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4869 HOST_WIDE_INT val = INTVAL (operands[1]);
4872 operands[2] = const0_rtx;
4873 else if (val >= 32 * 2)
4877 operands[1] = GEN_INT (0x7e + off);
4878 operands[2] = GEN_INT (val - off - 0x7e);
4884 operands[1] = GEN_INT (off);
4885 operands[2] = GEN_INT (val - off);
4889 ;; 8-bit Integer moves
4891 ;; Unlike most other insns, the move insns can't be split with
4892 ;; different predicates, because register spilling and other parts of
4893 ;; the compiler, have memoized the insn number already.
4894 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4896 (define_expand "movqi"
4897 [(set (match_operand:QI 0 "")
4898 (match_operand:QI 1 ""))]
4901 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4905 (define_insn "*movqi_internal"
4906 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d")
4907 (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!kbJ,dJ,*d*J,*a"))]
4909 && (register_operand (operands[0], QImode)
4910 || reg_or_0_operand (operands[1], QImode))"
4911 { return mips_output_move (operands[0], operands[1]); }
4912 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4913 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4914 (set_attr "mode" "QI")])
4916 (define_insn "*movqi_mips16"
4917 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4918 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4920 && (register_operand (operands[0], QImode)
4921 || register_operand (operands[1], QImode))"
4922 { return mips_output_move (operands[0], operands[1]); }
4923 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4924 (set_attr "mode" "QI")])
4926 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4927 ;; when the original load is a 4 byte instruction but the add and the
4928 ;; load are 2 2 byte instructions.
4931 [(set (match_operand:QI 0 "d_operand")
4932 (mem:QI (plus:SI (match_dup 0)
4933 (match_operand:SI 1 "const_int_operand"))))]
4934 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4935 && ((INTVAL (operands[1]) < 0
4936 && INTVAL (operands[1]) >= -0x80)
4937 || (INTVAL (operands[1]) >= 32
4938 && INTVAL (operands[1]) <= 31 + 0x7f))"
4939 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4940 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4942 HOST_WIDE_INT val = INTVAL (operands[1]);
4945 operands[2] = const0_rtx;
4948 operands[1] = GEN_INT (0x7f);
4949 operands[2] = GEN_INT (val - 0x7f);
4953 ;; 32-bit floating point moves
4955 (define_expand "movsf"
4956 [(set (match_operand:SF 0 "")
4957 (match_operand:SF 1 ""))]
4960 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4964 (define_insn "movccf"
4965 [(set (match_operand:CCF 0 "nonimmediate_operand" "=f,f,m")
4966 (match_operand:CCF 1 "nonimmediate_operand" "f,m,f"))]
4968 { return mips_output_move (operands[0], operands[1]); }
4969 [(set_attr "move_type" "fmove,fpload,fpstore")])
4971 (define_insn "*movsf_hardfloat"
4972 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4973 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4975 && (register_operand (operands[0], SFmode)
4976 || reg_or_0_operand (operands[1], SFmode))"
4977 { return mips_output_move (operands[0], operands[1]); }
4978 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4979 (set_attr "mode" "SF")])
4981 (define_insn "*movsf_softfloat"
4982 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4983 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4984 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4985 && (register_operand (operands[0], SFmode)
4986 || reg_or_0_operand (operands[1], SFmode))"
4987 { return mips_output_move (operands[0], operands[1]); }
4988 [(set_attr "move_type" "move,load,store")
4989 (set_attr "mode" "SF")])
4991 (define_insn "*movsf_mips16"
4992 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4993 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4995 && (register_operand (operands[0], SFmode)
4996 || register_operand (operands[1], SFmode))"
4997 { return mips_output_move (operands[0], operands[1]); }
4998 [(set_attr "move_type" "move,move,move,load,store")
4999 (set_attr "mode" "SF")])
5001 ;; 64-bit floating point moves
5003 (define_expand "movdf"
5004 [(set (match_operand:DF 0 "")
5005 (match_operand:DF 1 ""))]
5008 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
5012 (define_insn "*movdf_hardfloat"
5013 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
5014 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
5015 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
5016 && (register_operand (operands[0], DFmode)
5017 || reg_or_0_operand (operands[1], DFmode))"
5018 { return mips_output_move (operands[0], operands[1]); }
5019 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
5020 (set_attr "mode" "DF")])
5022 (define_insn "*movdf_softfloat"
5023 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
5024 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
5025 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
5026 && (register_operand (operands[0], DFmode)
5027 || reg_or_0_operand (operands[1], DFmode))"
5028 { return mips_output_move (operands[0], operands[1]); }
5029 [(set_attr "move_type" "move,load,store")
5030 (set_attr "mode" "DF")])
5032 (define_insn "*movdf_mips16"
5033 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
5034 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
5036 && (register_operand (operands[0], DFmode)
5037 || register_operand (operands[1], DFmode))"
5038 { return mips_output_move (operands[0], operands[1]); }
5039 [(set_attr "move_type" "move,move,move,load,store")
5040 (set_attr "mode" "DF")])
5042 ;; 128-bit integer moves
5044 (define_expand "movti"
5045 [(set (match_operand:TI 0)
5046 (match_operand:TI 1))]
5049 if (mips_legitimize_move (TImode, operands[0], operands[1]))
5053 (define_insn "*movti"
5054 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d")
5055 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))]
5058 && (register_operand (operands[0], TImode)
5059 || reg_or_0_operand (operands[1], TImode))"
5060 { return mips_output_move (operands[0], operands[1]); }
5061 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo")
5063 (if_then_else (eq_attr "move_type" "imul")
5065 (const_string "TI")))])
5067 (define_insn "*movti_mips16"
5068 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
5069 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
5072 && (register_operand (operands[0], TImode)
5073 || register_operand (operands[1], TImode))"
5075 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
5076 (set_attr "mode" "TI")])
5078 ;; 128-bit floating point moves
5080 (define_expand "movtf"
5081 [(set (match_operand:TF 0)
5082 (match_operand:TF 1))]
5085 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
5089 ;; This pattern handles both hard- and soft-float cases.
5090 (define_insn "*movtf"
5091 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
5092 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
5095 && (register_operand (operands[0], TFmode)
5096 || reg_or_0_operand (operands[1], TFmode))"
5098 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
5099 (set_attr "mode" "TF")])
5101 (define_insn "*movtf_mips16"
5102 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
5103 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
5106 && (register_operand (operands[0], TFmode)
5107 || register_operand (operands[1], TFmode))"
5109 [(set_attr "move_type" "move,move,move,load,store")
5110 (set_attr "mode" "TF")])
5113 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
5114 (match_operand:MOVE64 1 "move_operand"))]
5115 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
5118 mips_split_move_insn (operands[0], operands[1], curr_insn);
5123 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
5124 (match_operand:MOVE128 1 "move_operand"))]
5125 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
5128 mips_split_move_insn (operands[0], operands[1], curr_insn);
5132 ;; When generating mips16 code, split moves of negative constants into
5133 ;; a positive "li" followed by a negation.
5135 [(set (match_operand 0 "d_operand")
5136 (match_operand 1 "const_int_operand"))]
5137 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
5141 (neg:SI (match_dup 2)))]
5143 operands[2] = gen_lowpart (SImode, operands[0]);
5144 operands[3] = GEN_INT (-INTVAL (operands[1]));
5147 ;; 64-bit paired-single floating point moves
5149 (define_expand "movv2sf"
5150 [(set (match_operand:V2SF 0)
5151 (match_operand:V2SF 1))]
5152 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
5154 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
5158 (define_insn "*movv2sf"
5159 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
5160 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
5162 && TARGET_PAIRED_SINGLE_FLOAT
5163 && (register_operand (operands[0], V2SFmode)
5164 || reg_or_0_operand (operands[1], V2SFmode))"
5165 { return mips_output_move (operands[0], operands[1]); }
5166 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
5167 (set_attr "mode" "DF")])
5169 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
5170 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
5172 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
5173 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
5174 ;; and the errata related to -mfix-vr4130.
5175 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
5176 [(set (match_operand:GPR 0 "register_operand" "=d")
5177 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")]
5180 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
5181 [(set_attr "type" "mfhi")
5182 (set_attr "mode" "<GPR:MODE>")])
5184 ;; Set the high part of a HI/LO value, given that the low part has
5185 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
5186 ;; why we can't just use (reg:GPR HI_REGNUM).
5187 (define_insn "mthi<GPR:mode>_<HILO:mode>"
5188 [(set (match_operand:HILO 0 "register_operand" "=x")
5189 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
5190 (match_operand:GPR 2 "register_operand" "l")]
5194 [(set_attr "type" "mthi")
5195 (set_attr "mode" "SI")])
5197 ;; Emit a doubleword move in which exactly one of the operands is
5198 ;; a floating-point register. We can't just emit two normal moves
5199 ;; because of the constraints imposed by the FPU register model;
5200 ;; see mips_cannot_change_mode_class for details. Instead, we keep
5201 ;; the FPR whole and use special patterns to refer to each word of
5202 ;; the other operand.
5204 (define_expand "move_doubleword_fpr<mode>"
5205 [(set (match_operand:SPLITF 0)
5206 (match_operand:SPLITF 1))]
5209 if (FP_REG_RTX_P (operands[0]))
5211 rtx low = mips_subword (operands[1], 0);
5212 rtx high = mips_subword (operands[1], 1);
5213 emit_insn (gen_load_low<mode> (operands[0], low));
5214 if (ISA_HAS_MXHC1 && !TARGET_64BIT)
5215 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
5217 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
5221 rtx low = mips_subword (operands[0], 0);
5222 rtx high = mips_subword (operands[0], 1);
5223 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
5224 if (ISA_HAS_MXHC1 && !TARGET_64BIT)
5225 emit_insn (gen_mfhc1<mode> (high, operands[1]));
5227 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
5232 ;; Load the low word of operand 0 with operand 1.
5233 (define_insn "load_low<mode>"
5234 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
5235 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
5239 operands[0] = mips_subword (operands[0], 0);
5240 return mips_output_move (operands[0], operands[1]);
5242 [(set_attr "move_type" "mtc,fpload")
5243 (set_attr "mode" "<HALFMODE>")])
5245 ;; Load the high word of operand 0 from operand 1, preserving the value
5247 (define_insn "load_high<mode>"
5248 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
5249 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
5250 (match_operand:SPLITF 2 "register_operand" "0,0")]
5254 operands[0] = mips_subword (operands[0], 1);
5255 return mips_output_move (operands[0], operands[1]);
5257 [(set_attr "move_type" "mtc,fpload")
5258 (set_attr "mode" "<HALFMODE>")])
5260 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
5261 ;; high word and 0 to store the low word.
5262 (define_insn "store_word<mode>"
5263 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
5264 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
5265 (match_operand 2 "const_int_operand")]
5266 UNSPEC_STORE_WORD))]
5269 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
5270 return mips_output_move (operands[0], operands[1]);
5272 [(set_attr "move_type" "mfc,fpstore")
5273 (set_attr "mode" "<HALFMODE>")])
5275 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
5276 ;; value in the low word.
5277 (define_insn "mthc1<mode>"
5278 [(set (match_operand:SPLITF 0 "register_operand" "=f")
5279 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
5280 (match_operand:SPLITF 2 "register_operand" "0")]
5282 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
5284 [(set_attr "move_type" "mtc")
5285 (set_attr "mode" "<HALFMODE>")])
5287 ;; Move high word of operand 1 to operand 0 using mfhc1.
5288 (define_insn "mfhc1<mode>"
5289 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
5290 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
5292 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
5294 [(set_attr "move_type" "mfc")
5295 (set_attr "mode" "<HALFMODE>")])
5297 ;; Move a constant that satisfies CONST_GP_P into operand 0.
5298 (define_expand "load_const_gp_<mode>"
5299 [(set (match_operand:P 0 "register_operand" "=d")
5300 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
5302 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
5303 ;; of _gp from the start of this function. Operand 1 is the incoming
5304 ;; function address.
5305 (define_insn_and_split "loadgp_newabi_<mode>"
5306 [(set (match_operand:P 0 "register_operand" "=&d")
5307 (unspec:P [(match_operand:P 1)
5308 (match_operand:P 2 "register_operand" "d")]
5310 "mips_current_loadgp_style () == LOADGP_NEWABI"
5311 { return mips_must_initialize_gp_p () ? "#" : ""; }
5312 "&& mips_must_initialize_gp_p ()"
5313 [(set (match_dup 0) (match_dup 3))
5314 (set (match_dup 0) (match_dup 4))
5315 (set (match_dup 0) (match_dup 5))]
5317 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
5318 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
5319 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
5321 [(set_attr "type" "ghost")])
5323 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
5324 (define_insn_and_split "loadgp_absolute_<mode>"
5325 [(set (match_operand:P 0 "register_operand" "=d")
5326 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
5327 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
5328 { return mips_must_initialize_gp_p () ? "#" : ""; }
5329 "&& mips_must_initialize_gp_p ()"
5332 mips_emit_move (operands[0], operands[1]);
5335 [(set_attr "type" "ghost")])
5337 ;; This blockage instruction prevents the gp load from being
5338 ;; scheduled after an implicit use of gp. It also prevents
5339 ;; the load from being deleted as dead.
5340 (define_insn "loadgp_blockage"
5341 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
5344 [(set_attr "type" "ghost")])
5346 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
5347 ;; and operand 1 is the __GOTT_INDEX__ symbol.
5348 (define_insn_and_split "loadgp_rtp_<mode>"
5349 [(set (match_operand:P 0 "register_operand" "=d")
5350 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
5351 (match_operand:P 2 "symbol_ref_operand")]
5353 "mips_current_loadgp_style () == LOADGP_RTP"
5354 { return mips_must_initialize_gp_p () ? "#" : ""; }
5355 "&& mips_must_initialize_gp_p ()"
5356 [(set (match_dup 0) (high:P (match_dup 3)))
5357 (set (match_dup 0) (unspec:P [(match_dup 0)
5358 (match_dup 3)] UNSPEC_LOAD_GOT))
5359 (set (match_dup 0) (unspec:P [(match_dup 0)
5360 (match_dup 4)] UNSPEC_LOAD_GOT))]
5362 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
5363 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
5365 [(set_attr "type" "ghost")])
5367 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
5368 ;; global pointer and operand 1 is the MIPS16 register that holds
5369 ;; the required value.
5370 (define_insn_and_split "copygp_mips16_<mode>"
5371 [(set (match_operand:P 0 "register_operand" "=y")
5372 (unspec:P [(match_operand:P 1 "register_operand" "d")]
5375 { return mips_must_initialize_gp_p () ? "#" : ""; }
5376 "&& mips_must_initialize_gp_p ()"
5377 [(set (match_dup 0) (match_dup 1))]
5379 [(set_attr "type" "ghost")])
5381 ;; A placeholder for where the cprestore instruction should go,
5382 ;; if we decide we need one. Operand 0 and operand 1 are as for
5383 ;; "cprestore". Operand 2 is a register that holds the gp value.
5385 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
5386 ;; otherwise any register that holds the correct value will do.
5387 (define_insn_and_split "potential_cprestore_<mode>"
5388 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5389 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5390 (match_operand:P 2 "register_operand" "d,d")]
5391 UNSPEC_POTENTIAL_CPRESTORE))
5392 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))]
5393 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
5394 { return mips_must_initialize_gp_p () ? "#" : ""; }
5395 "mips_must_initialize_gp_p ()"
5398 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
5399 operands[2], operands[3]);
5402 [(set_attr "type" "ghost")])
5404 ;; Emit a .cprestore directive, which normally expands to a single store
5405 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
5406 ;; for the cprestore slot. Operand 1 is the offset of the slot from
5407 ;; the stack pointer. (This is redundant with operand 0, but it makes
5408 ;; things a little simpler.)
5409 (define_insn "cprestore_<mode>"
5410 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5411 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5414 "TARGET_CPRESTORE_DIRECTIVE"
5416 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
5417 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
5419 return ".cprestore\t%1";
5421 [(set_attr "type" "store")
5422 (set_attr "insn_count" "1,3")])
5424 (define_insn "use_cprestore_<mode>"
5425 [(set (reg:P CPRESTORE_SLOT_REGNUM)
5426 (match_operand:P 0 "cprestore_load_slot_operand"))]
5429 [(set_attr "type" "ghost")])
5431 ;; Expand in-line code to clear the instruction cache between operand[0] and
5433 (define_expand "clear_cache"
5434 [(match_operand 0 "pmode_register_operand")
5435 (match_operand 1 "pmode_register_operand")]
5441 mips_expand_synci_loop (operands[0], operands[1]);
5442 emit_insn (gen_sync ());
5443 emit_insn (PMODE_INSN (gen_clear_hazard, ()));
5445 else if (mips_cache_flush_func && mips_cache_flush_func[0])
5447 rtx len = gen_reg_rtx (Pmode);
5448 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
5449 MIPS_ICACHE_SYNC (operands[0], len);
5455 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
5457 { return mips_output_sync (); })
5459 (define_insn "synci"
5460 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
5465 (define_insn "rdhwr_synci_step_<mode>"
5466 [(set (match_operand:P 0 "register_operand" "=d")
5467 (unspec_volatile [(const_int 1)]
5472 (define_insn "clear_hazard_<mode>"
5473 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
5474 (clobber (reg:P RETURN_ADDR_REGNUM))]
5477 return "%(%<bal\t1f\n"
5479 "1:\t<d>addiu\t$31,$31,12\n"
5483 [(set_attr "insn_count" "5")])
5485 ;; Cache operations for R4000-style caches.
5486 (define_insn "mips_cache"
5487 [(set (mem:BLK (scratch))
5488 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
5489 (match_operand:QI 1 "address_operand" "ZD")]
5490 UNSPEC_MIPS_CACHE))]
5494 ;; Similar, but with the operands hard-coded to an R10K cache barrier
5495 ;; operation. We keep the pattern distinct so that we can identify
5496 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
5497 ;; the operation is never inserted into a delay slot.
5498 (define_insn "r10k_cache_barrier"
5499 [(set (mem:BLK (scratch))
5500 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
5503 [(set_attr "can_delay" "no")])
5505 ;; Block moves, see mips.c for more details.
5506 ;; Argument 0 is the destination
5507 ;; Argument 1 is the source
5508 ;; Argument 2 is the length
5509 ;; Argument 3 is the alignment
5511 (define_expand "movmemsi"
5512 [(parallel [(set (match_operand:BLK 0 "general_operand")
5513 (match_operand:BLK 1 "general_operand"))
5514 (use (match_operand:SI 2 ""))
5515 (use (match_operand:SI 3 "const_int_operand"))])]
5516 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5518 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5525 ;; ....................
5529 ;; ....................
5531 (define_expand "<optab><mode>3"
5532 [(set (match_operand:GPR 0 "register_operand")
5533 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5534 (match_operand:SI 2 "arith_operand")))]
5537 /* On the mips16, a shift of more than 8 is a four byte instruction,
5538 so, for a shift between 8 and 16, it is just as fast to do two
5539 shifts of 8 or less. If there is a lot of shifting going on, we
5540 may win in CSE. Otherwise combine will put the shifts back
5541 together again. This can be called by mips_function_arg, so we must
5542 be careful not to allocate a new register if we've reached the
5546 && CONST_INT_P (operands[2])
5547 && INTVAL (operands[2]) > 8
5548 && INTVAL (operands[2]) <= 16
5549 && !reload_in_progress
5550 && !reload_completed)
5552 rtx temp = gen_reg_rtx (<MODE>mode);
5554 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5555 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5556 GEN_INT (INTVAL (operands[2]) - 8)));
5561 (define_insn "*<optab><mode>3"
5562 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
5563 (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d")
5564 (match_operand:SI 2 "arith_operand" "Uib3,dI")))]
5567 if (CONST_INT_P (operands[2]))
5568 operands[2] = GEN_INT (INTVAL (operands[2])
5569 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5571 return "<d><insn>\t%0,%1,%2";
5573 [(set_attr "type" "shift")
5574 (set_attr "compression" "<shift_compression>,none")
5575 (set_attr "mode" "<MODE>")])
5577 (define_insn "*<optab>si3_extend"
5578 [(set (match_operand:DI 0 "register_operand" "=d")
5580 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5581 (match_operand:SI 2 "arith_operand" "dI"))))]
5582 "TARGET_64BIT && !TARGET_MIPS16"
5584 if (CONST_INT_P (operands[2]))
5585 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5587 return "<insn>\t%0,%1,%2";
5589 [(set_attr "type" "shift")
5590 (set_attr "mode" "SI")])
5592 (define_insn "*<optab>si3_mips16"
5593 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
5594 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d,d")
5595 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5598 if (which_alternative == 0)
5599 return "<insn>\t%0,%2";
5601 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5602 return "<insn>\t%0,%1,%2";
5604 [(set_attr "type" "shift")
5605 (set_attr "mode" "SI")
5606 (set_attr "extended_mips16" "no,no,yes")])
5608 (define_insn "<GPR:d>lsa"
5609 [(set (match_operand:GPR 0 "register_operand" "=d")
5610 (plus:GPR (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
5611 (match_operand 2 "const_immlsa_operand" ""))
5612 (match_operand:GPR 3 "register_operand" "d")))]
5613 "ISA_HAS_<GPR:D>LSA"
5614 "<GPR:d>lsa\t%0,%1,%3,%2"
5615 [(set_attr "type" "arith")
5616 (set_attr "mode" "<GPR:MODE>")])
5618 ;; We need separate DImode MIPS16 patterns because of the irregularity
5620 (define_insn "*ashldi3_mips16"
5621 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5622 (ashift:DI (match_operand:DI 1 "register_operand" "0,d,d")
5623 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5624 "TARGET_64BIT && TARGET_MIPS16"
5626 if (which_alternative == 0)
5627 return "dsll\t%0,%2";
5629 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5630 return "dsll\t%0,%1,%2";
5632 [(set_attr "type" "shift")
5633 (set_attr "mode" "DI")
5634 (set_attr "extended_mips16" "no,no,yes")])
5636 (define_insn "*ashrdi3_mips16"
5637 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5638 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5639 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5640 "TARGET_64BIT && TARGET_MIPS16"
5642 if (CONST_INT_P (operands[2]))
5643 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5645 return "dsra\t%0,%2";
5647 [(set_attr "type" "shift")
5648 (set_attr "mode" "DI")
5649 (set_attr "extended_mips16" "no,no,yes")])
5651 (define_insn "*lshrdi3_mips16"
5652 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5653 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5654 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5655 "TARGET_64BIT && TARGET_MIPS16"
5657 if (CONST_INT_P (operands[2]))
5658 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5660 return "dsrl\t%0,%2";
5662 [(set_attr "type" "shift")
5663 (set_attr "mode" "DI")
5664 (set_attr "extended_mips16" "no,no,yes")])
5666 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5669 [(set (match_operand:GPR 0 "d_operand")
5670 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5671 (match_operand:GPR 2 "const_int_operand")))]
5672 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5673 && INTVAL (operands[2]) > 8
5674 && INTVAL (operands[2]) <= 16"
5675 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5676 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5677 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5679 ;; If we load a byte on the mips16 as a bitfield, the resulting
5680 ;; sequence of instructions is too complicated for combine, because it
5681 ;; involves four instructions: a load, a shift, a constant load into a
5682 ;; register, and an and (the key problem here is that the mips16 does
5683 ;; not have and immediate). We recognize a shift of a load in order
5684 ;; to make it simple enough for combine to understand.
5686 ;; The instruction count here is the worst case.
5687 (define_insn_and_split ""
5688 [(set (match_operand:SI 0 "register_operand" "=d")
5689 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5690 (match_operand:SI 2 "immediate_operand" "I")))]
5694 [(set (match_dup 0) (match_dup 1))
5695 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5697 [(set_attr "type" "load")
5698 (set_attr "mode" "SI")
5699 (set (attr "insn_count")
5700 (symbol_ref "mips_load_store_insns (operands[1], insn) + 2"))])
5702 (define_insn "rotr<mode>3"
5703 [(set (match_operand:GPR 0 "register_operand" "=d")
5704 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5705 (match_operand:SI 2 "arith_operand" "dI")))]
5708 if (CONST_INT_P (operands[2]))
5709 gcc_assert (INTVAL (operands[2]) >= 0
5710 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5712 return "<d>ror\t%0,%1,%2";
5714 [(set_attr "type" "shift")
5715 (set_attr "mode" "<MODE>")])
5717 (define_insn "bswaphi2"
5718 [(set (match_operand:HI 0 "register_operand" "=d")
5719 (bswap:HI (match_operand:HI 1 "register_operand" "d")))]
5722 [(set_attr "type" "shift")])
5724 (define_insn_and_split "bswapsi2"
5725 [(set (match_operand:SI 0 "register_operand" "=d")
5726 (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
5727 "ISA_HAS_WSBH && ISA_HAS_ROR"
5730 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
5731 (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
5733 [(set_attr "insn_count" "2")])
5735 (define_insn_and_split "bswapdi2"
5736 [(set (match_operand:DI 0 "register_operand" "=d")
5737 (bswap:DI (match_operand:DI 1 "register_operand" "d")))]
5738 "TARGET_64BIT && ISA_HAS_WSBH"
5741 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH))
5742 (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))]
5744 [(set_attr "insn_count" "2")])
5747 [(set (match_operand:SI 0 "register_operand" "=d")
5748 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))]
5751 [(set_attr "type" "shift")])
5754 [(set (match_operand:DI 0 "register_operand" "=d")
5755 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))]
5756 "TARGET_64BIT && ISA_HAS_WSBH"
5758 [(set_attr "type" "shift")])
5761 [(set (match_operand:DI 0 "register_operand" "=d")
5762 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))]
5763 "TARGET_64BIT && ISA_HAS_WSBH"
5765 [(set_attr "type" "shift")])
5768 ;; ....................
5770 ;; CONDITIONAL BRANCHES
5772 ;; ....................
5774 ;; Conditional branches on floating-point equality tests.
5776 (define_insn "*branch_fp_<mode>"
5779 (match_operator 1 "equality_operator"
5780 [(match_operand:FPCC 2 "register_operand" "<reg>")
5782 (label_ref (match_operand 0 "" ""))
5786 return mips_output_conditional_branch (insn, operands,
5787 MIPS_BRANCH ("b%F1", "%Z2%0"),
5788 MIPS_BRANCH ("b%W1", "%Z2%0"));
5790 [(set_attr "type" "branch")])
5792 (define_insn "*branch_fp_inverted_<mode>"
5795 (match_operator 1 "equality_operator"
5796 [(match_operand:FPCC 2 "register_operand" "<reg>")
5799 (label_ref (match_operand 0 "" ""))))]
5802 return mips_output_conditional_branch (insn, operands,
5803 MIPS_BRANCH ("b%W1", "%Z2%0"),
5804 MIPS_BRANCH ("b%F1", "%Z2%0"));
5806 [(set_attr "type" "branch")])
5808 ;; Conditional branches on ordered comparisons with zero.
5810 (define_insn "*branch_order<mode>"
5813 (match_operator 1 "order_operator"
5814 [(match_operand:GPR 2 "register_operand" "d")
5816 (label_ref (match_operand 0 "" ""))
5819 { return mips_output_order_conditional_branch (insn, operands, false); }
5820 [(set_attr "type" "branch")])
5822 (define_insn "*branch_order<mode>_inverted"
5825 (match_operator 1 "order_operator"
5826 [(match_operand:GPR 2 "register_operand" "d")
5829 (label_ref (match_operand 0 "" ""))))]
5831 { return mips_output_order_conditional_branch (insn, operands, true); }
5832 [(set_attr "type" "branch")])
5834 ;; Conditional branch on equality comparison.
5836 (define_insn "*branch_equality<mode>"
5839 (match_operator 1 "equality_operator"
5840 [(match_operand:GPR 2 "register_operand" "d")
5841 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5842 (label_ref (match_operand 0 "" ""))
5846 /* For a simple BNEZ or BEQZ microMIPS branch. */
5847 if (TARGET_MICROMIPS
5848 && operands[3] == const0_rtx
5849 && get_attr_length (insn) <= 8)
5850 return mips_output_conditional_branch (insn, operands,
5852 "%*b%N1z%:\t%2,%0");
5854 return mips_output_conditional_branch (insn, operands,
5855 MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
5856 MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
5858 [(set_attr "type" "branch")])
5860 (define_insn "*branch_equality<mode>_inverted"
5863 (match_operator 1 "equality_operator"
5864 [(match_operand:GPR 2 "register_operand" "d")
5865 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5867 (label_ref (match_operand 0 "" ""))))]
5870 /* For a simple BNEZ or BEQZ microMIPS branch. */
5871 if (TARGET_MICROMIPS
5872 && operands[3] == const0_rtx
5873 && get_attr_length (insn) <= 8)
5874 return mips_output_conditional_branch (insn, operands,
5876 "%*b%C0z%:\t%2,%1");
5878 return mips_output_conditional_branch (insn, operands,
5879 MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
5880 MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
5882 [(set_attr "type" "branch")])
5886 (define_insn "*branch_equality<mode>_mips16"
5889 (match_operator 1 "equality_operator"
5890 [(match_operand:GPR 2 "register_operand" "d,t")
5892 (label_ref (match_operand 0 "" ""))
5898 [(set_attr "type" "branch")])
5900 (define_insn "*branch_equality<mode>_mips16_inverted"
5903 (match_operator 1 "equality_operator"
5904 [(match_operand:GPR 2 "register_operand" "d,t")
5907 (label_ref (match_operand 0 "" ""))))]
5912 [(set_attr "type" "branch")])
5914 (define_expand "cbranch<mode>4"
5916 (if_then_else (match_operator 0 "comparison_operator"
5917 [(match_operand:GPR 1 "register_operand")
5918 (match_operand:GPR 2 "nonmemory_operand")])
5919 (label_ref (match_operand 3 ""))
5923 mips_expand_conditional_branch (operands);
5927 (define_expand "cbranch<mode>4"
5929 (if_then_else (match_operator 0 "comparison_operator"
5930 [(match_operand:SCALARF 1 "register_operand")
5931 (match_operand:SCALARF 2 "register_operand")])
5932 (label_ref (match_operand 3 ""))
5936 mips_expand_conditional_branch (operands);
5940 ;; Used to implement built-in functions.
5941 (define_expand "condjump"
5943 (if_then_else (match_operand 0)
5944 (label_ref (match_operand 1))
5947 ;; Branch if bit is set/clear.
5949 (define_insn "*branch_bit<bbv><mode>"
5952 (equality_op (zero_extract:GPR
5953 (match_operand:GPR 1 "register_operand" "d")
5955 (match_operand 2 "const_int_operand" ""))
5957 (label_ref (match_operand 0 ""))
5959 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5962 mips_output_conditional_branch (insn, operands,
5963 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5964 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5966 [(set_attr "type" "branch")
5967 (set_attr "branch_likely" "no")])
5969 (define_insn "*branch_bit<bbv><mode>_inverted"
5972 (equality_op (zero_extract:GPR
5973 (match_operand:GPR 1 "register_operand" "d")
5975 (match_operand 2 "const_int_operand" ""))
5978 (label_ref (match_operand 0 ""))))]
5979 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5982 mips_output_conditional_branch (insn, operands,
5983 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5984 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5986 [(set_attr "type" "branch")
5987 (set_attr "branch_likely" "no")])
5990 ;; ....................
5992 ;; SETTING A REGISTER FROM A COMPARISON
5994 ;; ....................
5996 ;; Destination is always set in SI mode.
5998 (define_expand "cstore<mode>4"
5999 [(set (match_operand:SI 0 "register_operand")
6000 (match_operator:SI 1 "mips_cstore_operator"
6001 [(match_operand:GPR 2 "register_operand")
6002 (match_operand:GPR 3 "nonmemory_operand")]))]
6005 mips_expand_scc (operands);
6009 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
6010 [(set (match_operand:GPR2 0 "register_operand" "=d")
6011 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
6013 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6015 [(set_attr "type" "slt")
6016 (set_attr "mode" "<GPR:MODE>")])
6018 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
6019 [(set (match_operand:GPR2 0 "register_operand" "=t")
6020 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
6022 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6024 [(set_attr "type" "slt")
6025 (set_attr "mode" "<GPR:MODE>")])
6027 ;; Generate sltiu unless using seq results in better code.
6028 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
6029 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
6030 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
6031 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
6037 [(set_attr "type" "slt")
6038 (set_attr "mode" "<GPR:MODE>")])
6040 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
6041 [(set (match_operand:GPR2 0 "register_operand" "=d")
6042 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
6044 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6046 [(set_attr "type" "slt")
6047 (set_attr "mode" "<GPR:MODE>")])
6049 ;; Generate sltu unless using sne results in better code.
6050 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
6051 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
6052 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
6053 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
6059 [(set_attr "type" "slt")
6060 (set_attr "mode" "<GPR:MODE>")])
6062 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
6063 [(set (match_operand:GPR2 0 "register_operand" "=d")
6064 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6065 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
6068 [(set_attr "type" "slt")
6069 (set_attr "mode" "<GPR:MODE>")])
6071 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
6072 [(set (match_operand:GPR2 0 "register_operand" "=t")
6073 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6074 (match_operand:GPR 2 "register_operand" "d")))]
6077 [(set_attr "type" "slt")
6078 (set_attr "mode" "<GPR:MODE>")])
6080 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
6081 [(set (match_operand:GPR2 0 "register_operand" "=d")
6082 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
6086 [(set_attr "type" "slt")
6087 (set_attr "mode" "<GPR:MODE>")])
6089 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
6090 [(set (match_operand:GPR2 0 "register_operand" "=d")
6091 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6092 (match_operand:GPR 2 "arith_operand" "dI")))]
6095 [(set_attr "type" "slt")
6096 (set_attr "mode" "<GPR:MODE>")])
6098 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
6099 [(set (match_operand:GPR2 0 "register_operand" "=t,t,t")
6100 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d,d")
6101 (match_operand:GPR 2 "arith_operand" "d,Uub8,I")))]
6104 [(set_attr "type" "slt")
6105 (set_attr "mode" "<GPR:MODE>")
6106 (set_attr "extended_mips16" "no,no,yes")])
6108 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
6109 [(set (match_operand:GPR2 0 "register_operand" "=d")
6110 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
6111 (match_operand:GPR 2 "sle_operand" "")))]
6114 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
6115 return "slt<u>\t%0,%1,%2";
6117 [(set_attr "type" "slt")
6118 (set_attr "mode" "<GPR:MODE>")])
6120 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
6121 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
6122 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
6123 (match_operand:GPR 2 "sle_operand" "Udb8,i")))]
6126 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
6127 return "slt<u>\t%1,%2";
6129 [(set_attr "type" "slt")
6130 (set_attr "mode" "<GPR:MODE>")
6131 (set_attr "extended_mips16" "no,yes")])
6134 ;; ....................
6136 ;; FLOATING POINT COMPARISONS
6138 ;; ....................
6140 (define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>"
6141 [(set (match_operand:FPCC 0 "register_operand" "=<reg>")
6142 (fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f")
6143 (match_operand:SCALARF 2 "register_operand" "f")))]
6145 "<fpcmp>.<fcond>.<fmt>\t%Z0%1,%2"
6146 [(set_attr "type" "fcmp")
6147 (set_attr "mode" "FPSW")])
6149 (define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>"
6150 [(set (match_operand:FPCC 0 "register_operand" "=<reg>")
6151 (swapped_fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f")
6152 (match_operand:SCALARF 2 "register_operand" "f")))]
6154 "<fpcmp>.<swapped_fcond>.<fmt>\t%Z0%2,%1"
6155 [(set_attr "type" "fcmp")
6156 (set_attr "mode" "FPSW")])
6159 ;; ....................
6161 ;; UNCONDITIONAL BRANCHES
6163 ;; ....................
6165 ;; Unconditional branches.
6167 (define_expand "jump"
6169 (label_ref (match_operand 0)))])
6171 (define_insn "*jump_absolute"
6173 (label_ref (match_operand 0)))]
6174 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
6176 if (get_attr_length (insn) <= 8)
6177 return "%*b\t%l0%/";
6179 return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/");
6181 [(set_attr "type" "branch")])
6183 (define_insn "*jump_pic"
6185 (label_ref (match_operand 0)))]
6186 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
6188 if (get_attr_length (insn) <= 8)
6189 return "%*b\t%l0%/";
6192 mips_output_load_label (operands[0]);
6193 return "%*jr\t%@%/%]";
6196 [(set_attr "type" "branch")])
6198 ;; We need a different insn for the mips16, because a mips16 branch
6199 ;; does not have a delay slot.
6201 (define_insn "*jump_mips16"
6203 (label_ref (match_operand 0 "" "")))]
6206 [(set_attr "type" "branch")
6207 (set (attr "length")
6208 ;; This calculation is like the normal branch one, but the
6209 ;; range of the unextended instruction is [-0x800, 0x7fe] rather
6210 ;; than [-0x100, 0xfe]. This translates to a range of:
6212 ;; [-(0x800 - sizeof (branch)), 0x7fe]
6213 ;; == [-0x7fe, 0x7fe]
6215 ;; from the shorten_branches reference address. Long-branch
6216 ;; sequences will replace this one, so the minimum length
6217 ;; is one instruction shorter than for conditional branches.
6218 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
6219 (le (minus (pc) (match_dup 0)) (const_int 2046)))
6221 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
6222 (le (minus (pc) (match_dup 0)) (const_int 65532)))
6224 (and (match_test "TARGET_ABICALLS")
6225 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
6227 (match_test "Pmode == SImode")
6229 ] (const_int 22)))])
6231 (define_expand "indirect_jump"
6232 [(set (pc) (match_operand 0 "register_operand"))]
6235 operands[0] = force_reg (Pmode, operands[0]);
6236 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0])));
6240 (define_insn "indirect_jump_<mode>"
6241 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
6244 if (TARGET_MICROMIPS)
6245 return "%*jr%:\t%0";
6249 [(set_attr "type" "jump")
6250 (set_attr "mode" "none")])
6252 ;; A combined jump-and-move instruction, used for MIPS16 long-branch
6253 ;; sequences. Having a dedicated pattern is more convenient than
6254 ;; creating a SEQUENCE for this special case.
6255 (define_insn "indirect_jump_and_restore_<mode>"
6256 [(set (pc) (match_operand:P 1 "register_operand" "d"))
6257 (set (match_operand:P 0 "register_operand" "=d")
6258 (match_operand:P 2 "register_operand" "y"))]
6260 "%(%<jr\t%1\;move\t%0,%2%>%)"
6261 [(set_attr "type" "multi")
6262 (set_attr "extended_mips16" "yes")])
6264 (define_expand "tablejump"
6266 (match_operand 0 "register_operand"))
6267 (use (label_ref (match_operand 1 "")))]
6268 "!TARGET_MIPS16_SHORT_JUMP_TABLES"
6271 operands[0] = expand_binop (Pmode, add_optab, operands[0],
6272 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
6273 else if (TARGET_RTP_PIC)
6275 /* When generating RTP PIC, we use case table entries that are relative
6276 to the start of the function. Add the function's address to the
6278 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6279 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
6280 start, 0, 0, OPTAB_WIDEN);
6283 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1])));
6287 (define_insn "tablejump_<mode>"
6289 (match_operand:P 0 "register_operand" "d"))
6290 (use (label_ref (match_operand 1 "" "")))]
6293 if (TARGET_MICROMIPS)
6294 return "%*jr%:\t%0";
6298 [(set_attr "type" "jump")
6299 (set_attr "mode" "none")])
6301 ;; For MIPS16, we don't know whether a given jump table will use short or
6302 ;; word-sized offsets until late in compilation, when we are able to determine
6303 ;; the sizes of the insns which comprise the containing function. This
6304 ;; necessitates the use of the casesi rather than the tablejump pattern, since
6305 ;; the latter tries to calculate the index of the offset to jump through early
6306 ;; in compilation, i.e. at expand time, when nothing is known about the
6307 ;; eventual function layout.
6309 (define_expand "casesi"
6310 [(match_operand:SI 0 "register_operand" "") ; index to jump on
6311 (match_operand:SI 1 "const_int_operand" "") ; lower bound
6312 (match_operand:SI 2 "const_int_operand" "") ; total range
6313 (match_operand 3 "" "") ; table label
6314 (match_operand 4 "" "")] ; out of range label
6315 "TARGET_MIPS16_SHORT_JUMP_TABLES"
6317 if (operands[1] != const0_rtx)
6319 rtx reg = gen_reg_rtx (SImode);
6320 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode);
6322 if (!arith_operand (offset, SImode))
6323 offset = force_reg (SImode, offset);
6325 emit_insn (gen_addsi3 (reg, operands[0], offset));
6329 if (!arith_operand (operands[0], SImode))
6330 operands[0] = force_reg (SImode, operands[0]);
6332 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
6334 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16,
6335 (operands[0], operands[2],
6336 operands[3], operands[4])));
6341 (define_insn "casesi_internal_mips16_<mode>"
6344 (leu (match_operand:SI 0 "register_operand" "d")
6345 (match_operand:SI 1 "arith_operand" "dI"))
6348 (label_ref (match_operand 2 "" ""))]
6349 UNSPEC_CASESI_DISPATCH)
6350 (label_ref (match_operand 3 "" ""))))
6351 (clobber (match_scratch:P 4 "=d"))
6352 (clobber (match_scratch:P 5 "=d"))
6353 (clobber (reg:SI MIPS16_T_REGNUM))]
6354 "TARGET_MIPS16_SHORT_JUMP_TABLES"
6356 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
6358 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
6360 output_asm_insn ("sltu\t%0, %1", operands);
6361 output_asm_insn ("bteqz\t%3", operands);
6363 switch (GET_MODE (diff_vec))
6366 output_asm_insn ("sll\t%5, %0, 1", operands);
6367 output_asm_insn ("la\t%4, %2", operands);
6368 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
6369 output_asm_insn ("lh\t%5, 0(%5)", operands);
6373 output_asm_insn ("sll\t%5, %0, 2", operands);
6374 output_asm_insn ("la\t%4, %2", operands);
6375 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
6376 output_asm_insn ("lw\t%5, 0(%5)", operands);
6383 output_asm_insn ("addu\t%4, %4, %5", operands);
6387 [(set_attr "insn_count" "16")])
6389 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
6390 ;; While it is possible to either pull it off the stack (in the
6391 ;; o32 case) or recalculate it given t9 and our target label,
6392 ;; it takes 3 or 4 insns to do so.
6394 (define_expand "builtin_setjmp_setup"
6395 [(use (match_operand 0 "register_operand"))]
6400 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3);
6401 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
6405 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
6406 ;; that older code did recalculate the gp from $25. Continue to jump through
6407 ;; $25 for compatibility (we lose nothing by doing so).
6409 (define_expand "builtin_longjmp"
6410 [(use (match_operand 0 "register_operand"))]
6413 /* The elements of the buffer are, in order: */
6414 int W = GET_MODE_SIZE (Pmode);
6415 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6416 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W));
6417 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W));
6418 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W));
6419 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6420 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
6421 The target is bound to be using $28 as the global pointer
6422 but the current function might not be. */
6423 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
6425 /* This bit is similar to expand_builtin_longjmp except that it
6426 restores $gp as well. */
6427 mips_emit_move (hard_frame_pointer_rtx, fp);
6428 mips_emit_move (pv, lab);
6429 emit_stack_restore (SAVE_NONLOCAL, stack);
6430 mips_emit_move (gp, gpv);
6431 emit_use (hard_frame_pointer_rtx);
6432 emit_use (stack_pointer_rtx);
6434 emit_indirect_jump (pv);
6439 ;; ....................
6441 ;; Function prologue/epilogue
6443 ;; ....................
6446 (define_expand "prologue"
6450 mips_expand_prologue ();
6454 ;; Block any insns from being moved before this point, since the
6455 ;; profiling call to mcount can use various registers that aren't
6456 ;; saved or used to pass arguments.
6458 (define_insn "blockage"
6459 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
6462 [(set_attr "type" "ghost")
6463 (set_attr "mode" "none")])
6465 (define_insn "probe_stack_range_<P:mode>"
6466 [(set (match_operand:P 0 "register_operand" "=d")
6467 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
6468 (match_operand:P 2 "register_operand" "d")]
6469 UNSPEC_PROBE_STACK_RANGE))]
6471 { return mips_output_probe_stack_range (operands[0], operands[2]); }
6472 [(set_attr "type" "unknown")
6473 (set_attr "can_delay" "no")
6474 (set_attr "mode" "<MODE>")])
6476 (define_expand "epilogue"
6480 mips_expand_epilogue (false);
6484 (define_expand "sibcall_epilogue"
6488 mips_expand_epilogue (true);
6492 ;; Trivial return. Make it look like a normal return insn as that
6493 ;; allows jump optimizations to work better.
6495 (define_expand "return"
6497 "mips_can_use_return_insn ()"
6498 { mips_expand_before_return (); })
6500 (define_expand "simple_return"
6503 { mips_expand_before_return (); })
6505 (define_insn "*<optab>"
6509 if (TARGET_MICROMIPS)
6510 return "%*jr%:\t$31";
6512 return "%*j\t$31%/";
6514 [(set_attr "type" "jump")
6515 (set_attr "mode" "none")])
6519 (define_insn "<optab>_internal"
6521 (use (match_operand 0 "pmode_register_operand" ""))]
6524 if (TARGET_MICROMIPS)
6525 return "%*jr%:\t%0";
6529 [(set_attr "type" "jump")
6530 (set_attr "mode" "none")])
6532 ;; Exception return.
6533 (define_insn "mips_eret"
6535 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
6538 [(set_attr "type" "trap")
6539 (set_attr "mode" "none")])
6541 ;; Debug exception return.
6542 (define_insn "mips_deret"
6544 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
6547 [(set_attr "type" "trap")
6548 (set_attr "mode" "none")])
6550 ;; Disable interrupts.
6551 (define_insn "mips_di"
6552 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
6555 [(set_attr "type" "trap")
6556 (set_attr "mode" "none")])
6558 ;; Execution hazard barrier.
6559 (define_insn "mips_ehb"
6560 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
6563 [(set_attr "type" "trap")
6564 (set_attr "mode" "none")])
6566 ;; Read GPR from previous shadow register set.
6567 (define_insn "mips_rdpgpr_<mode>"
6568 [(set (match_operand:P 0 "register_operand" "=d")
6569 (unspec_volatile:P [(match_operand:P 1 "register_operand" "d")]
6573 [(set_attr "type" "move")
6574 (set_attr "mode" "<MODE>")])
6576 ;; Move involving COP0 registers.
6577 (define_insn "cop0_move"
6578 [(set (match_operand:SI 0 "register_operand" "=B,d")
6579 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
6582 { return mips_output_move (operands[0], operands[1]); }
6583 [(set_attr "type" "mtc,mfc")
6584 (set_attr "mode" "SI")])
6586 ;; This is used in compiling the unwind routines.
6587 (define_expand "eh_return"
6588 [(use (match_operand 0 "general_operand"))]
6591 if (GET_MODE (operands[0]) != word_mode)
6592 operands[0] = convert_to_mode (word_mode, operands[0], 0);
6594 emit_insn (gen_eh_set_lr_di (operands[0]));
6596 emit_insn (gen_eh_set_lr_si (operands[0]));
6600 ;; Clobber the return address on the stack. We can't expand this
6601 ;; until we know where it will be put in the stack frame.
6603 (define_insn "eh_set_lr_si"
6604 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6605 (clobber (match_scratch:SI 1 "=&d"))]
6609 (define_insn "eh_set_lr_di"
6610 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6611 (clobber (match_scratch:DI 1 "=&d"))]
6616 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
6617 (clobber (match_scratch 1))]
6621 mips_set_return_address (operands[0], operands[1]);
6625 (define_expand "exception_receiver"
6629 /* See the comment above load_call<mode> for details. */
6630 emit_insn (gen_set_got_version ());
6632 /* If we have a call-clobbered $gp, restore it from its save slot. */
6633 if (HAVE_restore_gp_si)
6634 emit_insn (gen_restore_gp_si ());
6635 else if (HAVE_restore_gp_di)
6636 emit_insn (gen_restore_gp_di ());
6640 (define_expand "nonlocal_goto_receiver"
6644 /* See the comment above load_call<mode> for details. */
6645 emit_insn (gen_set_got_version ());
6649 ;; Restore $gp from its .cprestore stack slot. The instruction remains
6650 ;; volatile until all uses of $28 are exposed.
6651 (define_insn_and_split "restore_gp_<mode>"
6653 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP))
6654 (clobber (match_scratch:P 0 "=&d"))]
6655 "TARGET_CALL_CLOBBERED_GP"
6657 "&& epilogue_completed"
6660 mips_restore_gp_from_cprestore_slot (operands[0]);
6663 [(set_attr "type" "ghost")])
6665 ;; Move between $gp and its register save slot.
6666 (define_insn_and_split "move_gp<mode>"
6667 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
6668 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
6671 { return mips_must_initialize_gp_p () ? "#" : ""; }
6672 "mips_must_initialize_gp_p ()"
6675 mips_emit_move (operands[0], operands[1]);
6678 [(set_attr "type" "ghost")])
6681 ;; ....................
6685 ;; ....................
6687 ;; Instructions to load a call address from the GOT. The address might
6688 ;; point to a function or to a lazy binding stub. In the latter case,
6689 ;; the stub will use the dynamic linker to resolve the function, which
6690 ;; in turn will change the GOT entry to point to the function's real
6693 ;; This means that every call, even pure and constant ones, can
6694 ;; potentially modify the GOT entry. And once a stub has been called,
6695 ;; we must not call it again.
6697 ;; We represent this restriction using an imaginary, fixed, call-saved
6698 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
6699 ;; live throughout the function and to change its value after every
6700 ;; potential call site. This stops any rtx value that uses the register
6701 ;; from being computed before an earlier call. To do this, we:
6703 ;; - Ensure that the register is live on entry to the function,
6704 ;; so that it is never thought to be used uninitalized.
6706 ;; - Ensure that the register is live on exit from the function,
6707 ;; so that it is live throughout.
6709 ;; - Make each call (lazily-bound or not) use the current value
6710 ;; of GOT_VERSION_REGNUM, so that updates of the register are
6711 ;; not moved across call boundaries.
6713 ;; - Add "ghost" definitions of the register to the beginning of
6714 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
6715 ;; edges may involve calls that normal paths don't. (E.g. the
6716 ;; unwinding code that handles a non-call exception may change
6717 ;; lazily-bound GOT entries.) We do this by making the
6718 ;; exception_receiver and nonlocal_goto_receiver expanders emit
6719 ;; a set_got_version instruction.
6721 ;; - After each call (lazily-bound or not), use a "ghost"
6722 ;; update_got_version instruction to change the register's value.
6723 ;; This instruction mimics the _possible_ effect of the dynamic
6724 ;; resolver during the call and it remains live even if the call
6725 ;; itself becomes dead.
6727 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
6728 ;; The register is therefore not a valid register_operand
6729 ;; and cannot be moved to or from other registers.
6731 (define_insn "load_call<mode>"
6732 [(set (match_operand:P 0 "register_operand" "=d")
6733 (unspec:P [(match_operand:P 1 "register_operand" "d")
6734 (match_operand:P 2 "immediate_operand" "")
6735 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
6737 "<load>\t%0,%R2(%1)"
6738 [(set_attr "got" "load")
6739 (set_attr "mode" "<MODE>")])
6741 (define_insn "set_got_version"
6742 [(set (reg:SI GOT_VERSION_REGNUM)
6743 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
6746 [(set_attr "type" "ghost")])
6748 (define_insn "update_got_version"
6749 [(set (reg:SI GOT_VERSION_REGNUM)
6750 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
6753 [(set_attr "type" "ghost")])
6755 ;; Sibling calls. All these patterns use jump instructions.
6757 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
6758 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
6759 ;; is defined in terms of call_insn_operand, the same is true of the
6762 ;; When we use an indirect jump, we need a register that will be
6763 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
6764 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
6765 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
6768 (define_expand "sibcall"
6769 [(parallel [(call (match_operand 0 "")
6770 (match_operand 1 ""))
6771 (use (match_operand 2 "")) ;; next_arg_reg
6772 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6775 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
6776 operands[1], operands[2], false);
6780 (define_insn "sibcall_internal"
6781 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
6782 (match_operand 1 "" ""))]
6783 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6785 if (TARGET_MICROMIPS)
6786 return MICROMIPS_J ("j", operands, 0);
6788 return MIPS_CALL ("j", operands, 0, 1);
6790 [(set_attr "jal" "indirect,direct")
6791 (set_attr "jal_macro" "no")])
6793 (define_expand "sibcall_value"
6794 [(parallel [(set (match_operand 0 "")
6795 (call (match_operand 1 "")
6796 (match_operand 2 "")))
6797 (use (match_operand 3 ""))])] ;; next_arg_reg
6800 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
6801 operands[2], operands[3], false);
6805 (define_insn "sibcall_value_internal"
6806 [(set (match_operand 0 "register_operand" "")
6807 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6808 (match_operand 2 "" "")))]
6809 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6811 if (TARGET_MICROMIPS)
6812 return MICROMIPS_J ("j", operands, 1);
6814 return MIPS_CALL ("j", operands, 1, 2);
6816 [(set_attr "jal" "indirect,direct")
6817 (set_attr "jal_macro" "no")])
6819 (define_insn "sibcall_value_multiple_internal"
6820 [(set (match_operand 0 "register_operand" "")
6821 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6822 (match_operand 2 "" "")))
6823 (set (match_operand 3 "register_operand" "")
6824 (call (mem:SI (match_dup 1))
6826 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6828 if (TARGET_MICROMIPS)
6829 return MICROMIPS_J ("j", operands, 1);
6831 return MIPS_CALL ("j", operands, 1, 2);
6833 [(set_attr "jal" "indirect,direct")
6834 (set_attr "jal_macro" "no")])
6836 (define_expand "call"
6837 [(parallel [(call (match_operand 0 "")
6838 (match_operand 1 ""))
6839 (use (match_operand 2 "")) ;; next_arg_reg
6840 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6843 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6844 operands[1], operands[2], false);
6848 ;; This instruction directly corresponds to an assembly-language "jal".
6849 ;; There are four cases:
6852 ;; Both symbolic and register destinations are OK. The pattern
6853 ;; always expands to a single mips instruction.
6855 ;; - -mabicalls/-mno-explicit-relocs:
6856 ;; Again, both symbolic and register destinations are OK.
6857 ;; The call is treated as a multi-instruction black box.
6859 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6860 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6863 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6864 ;; Only "jal $25" is allowed. The call is actually two instructions:
6865 ;; "jalr $25" followed by an insn to reload $gp.
6867 ;; In the last case, we can generate the individual instructions with
6868 ;; a define_split. There are several things to be wary of:
6870 ;; - We can't expose the load of $gp before reload. If we did,
6871 ;; it might get removed as dead, but reload can introduce new
6872 ;; uses of $gp by rematerializing constants.
6874 ;; - We shouldn't restore $gp after calls that never return.
6875 ;; It isn't valid to insert instructions between a noreturn
6876 ;; call and the following barrier.
6878 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6879 ;; instruction preserves $gp and so have no effect on its liveness.
6880 ;; But once we generate the separate insns, it becomes obvious that
6881 ;; $gp is not live on entry to the call.
6883 (define_insn_and_split "call_internal"
6884 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6885 (match_operand 1 "" ""))
6886 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6888 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6889 "reload_completed && TARGET_SPLIT_CALLS"
6892 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6895 [(set_attr "jal" "indirect,direct")])
6897 (define_insn "call_split"
6898 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6899 (match_operand 1 "" ""))
6900 (clobber (reg:SI RETURN_ADDR_REGNUM))
6901 (clobber (reg:SI 28))]
6902 "TARGET_SPLIT_CALLS"
6903 { return MIPS_CALL ("jal", operands, 0, 1); }
6904 [(set_attr "jal" "indirect,direct")
6905 (set_attr "jal_macro" "no")])
6907 ;; A pattern for calls that must be made directly. It is used for
6908 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6909 ;; stub; the linker relies on the call relocation type to detect when
6910 ;; such redirection is needed.
6911 (define_insn_and_split "call_internal_direct"
6912 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6915 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6917 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6918 "reload_completed && TARGET_SPLIT_CALLS"
6921 mips_split_call (curr_insn,
6922 gen_call_direct_split (operands[0], operands[1]));
6925 [(set_attr "jal" "direct")])
6927 (define_insn "call_direct_split"
6928 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6931 (clobber (reg:SI RETURN_ADDR_REGNUM))
6932 (clobber (reg:SI 28))]
6933 "TARGET_SPLIT_CALLS"
6934 { return MIPS_CALL ("jal", operands, 0, -1); }
6935 [(set_attr "jal" "direct")
6936 (set_attr "jal_macro" "no")])
6938 (define_expand "call_value"
6939 [(parallel [(set (match_operand 0 "")
6940 (call (match_operand 1 "")
6941 (match_operand 2 "")))
6942 (use (match_operand 3 ""))])] ;; next_arg_reg
6945 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6946 operands[2], operands[3], false);
6950 ;; See comment for call_internal.
6951 (define_insn_and_split "call_value_internal"
6952 [(set (match_operand 0 "register_operand" "")
6953 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6954 (match_operand 2 "" "")))
6955 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6957 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6958 "reload_completed && TARGET_SPLIT_CALLS"
6961 mips_split_call (curr_insn,
6962 gen_call_value_split (operands[0], operands[1],
6966 [(set_attr "jal" "indirect,direct")])
6968 (define_insn "call_value_split"
6969 [(set (match_operand 0 "register_operand" "")
6970 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6971 (match_operand 2 "" "")))
6972 (clobber (reg:SI RETURN_ADDR_REGNUM))
6973 (clobber (reg:SI 28))]
6974 "TARGET_SPLIT_CALLS"
6975 { return MIPS_CALL ("jal", operands, 1, 2); }
6976 [(set_attr "jal" "indirect,direct")
6977 (set_attr "jal_macro" "no")])
6979 ;; See call_internal_direct.
6980 (define_insn_and_split "call_value_internal_direct"
6981 [(set (match_operand 0 "register_operand")
6982 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6985 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6987 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6988 "reload_completed && TARGET_SPLIT_CALLS"
6991 mips_split_call (curr_insn,
6992 gen_call_value_direct_split (operands[0], operands[1],
6996 [(set_attr "jal" "direct")])
6998 (define_insn "call_value_direct_split"
6999 [(set (match_operand 0 "register_operand")
7000 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
7003 (clobber (reg:SI RETURN_ADDR_REGNUM))
7004 (clobber (reg:SI 28))]
7005 "TARGET_SPLIT_CALLS"
7006 { return MIPS_CALL ("jal", operands, 1, -1); }
7007 [(set_attr "jal" "direct")
7008 (set_attr "jal_macro" "no")])
7010 ;; See comment for call_internal.
7011 (define_insn_and_split "call_value_multiple_internal"
7012 [(set (match_operand 0 "register_operand" "")
7013 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7014 (match_operand 2 "" "")))
7015 (set (match_operand 3 "register_operand" "")
7016 (call (mem:SI (match_dup 1))
7018 (clobber (reg:SI RETURN_ADDR_REGNUM))]
7020 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
7021 "reload_completed && TARGET_SPLIT_CALLS"
7024 mips_split_call (curr_insn,
7025 gen_call_value_multiple_split (operands[0], operands[1],
7026 operands[2], operands[3]));
7029 [(set_attr "jal" "indirect,direct")])
7031 (define_insn "call_value_multiple_split"
7032 [(set (match_operand 0 "register_operand" "")
7033 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7034 (match_operand 2 "" "")))
7035 (set (match_operand 3 "register_operand" "")
7036 (call (mem:SI (match_dup 1))
7038 (clobber (reg:SI RETURN_ADDR_REGNUM))
7039 (clobber (reg:SI 28))]
7040 "TARGET_SPLIT_CALLS"
7041 { return MIPS_CALL ("jal", operands, 1, 2); }
7042 [(set_attr "jal" "indirect,direct")
7043 (set_attr "jal_macro" "no")])
7045 ;; Call subroutine returning any type.
7047 (define_expand "untyped_call"
7048 [(parallel [(call (match_operand 0 "")
7050 (match_operand 1 "")
7051 (match_operand 2 "")])]
7056 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7058 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7060 rtx set = XVECEXP (operands[2], 0, i);
7061 mips_emit_move (SET_DEST (set), SET_SRC (set));
7064 emit_insn (gen_blockage ());
7069 ;; ....................
7073 ;; ....................
7077 (define_insn "prefetch"
7078 [(prefetch (match_operand:QI 0 "address_operand" "ZD")
7079 (match_operand 1 "const_int_operand" "n")
7080 (match_operand 2 "const_int_operand" "n"))]
7081 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
7083 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
7085 /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */
7087 return "ld\t$0,%a0";
7089 return "lw\t$0,%a0";
7091 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
7092 return "pref\t%1,%a0";
7094 [(set_attr "type" "prefetch")])
7096 (define_insn "*prefetch_indexed_<mode>"
7097 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
7098 (match_operand:P 1 "register_operand" "d"))
7099 (match_operand 2 "const_int_operand" "n")
7100 (match_operand 3 "const_int_operand" "n"))]
7101 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7103 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
7104 return "prefx\t%2,%1(%0)";
7106 [(set_attr "type" "prefetchx")])
7112 [(set_attr "type" "nop")
7113 (set_attr "mode" "none")])
7115 ;; Like nop, but commented out when outside a .set noreorder block.
7116 (define_insn "hazard_nop"
7120 if (mips_noreorder.nesting_level > 0)
7125 [(set_attr "type" "nop")])
7127 ;; MIPS4 Conditional move instructions.
7129 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
7130 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7132 (match_operator 4 "equality_operator"
7133 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
7135 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
7136 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
7141 [(set_attr "type" "condmove")
7142 (set_attr "mode" "<GPR:MODE>")])
7144 (define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne"
7145 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7147 (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>")
7148 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
7149 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
7154 [(set_attr "type" "condmove")
7155 (set_attr "mode" "<GPR:MODE>")])
7157 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
7158 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
7159 (if_then_else:SCALARF
7160 (match_operator 4 "equality_operator"
7161 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
7163 (match_operand:SCALARF 2 "register_operand" "f,0")
7164 (match_operand:SCALARF 3 "register_operand" "0,f")))]
7165 "ISA_HAS_FP_CONDMOVE"
7167 mov%T4.<fmt>\t%0,%2,%1
7168 mov%t4.<fmt>\t%0,%3,%1"
7169 [(set_attr "type" "condmove")
7170 (set_attr "mode" "<SCALARF:MODE>")])
7172 (define_insn "*sel<code><GPR:mode>_using_<GPR2:mode>"
7173 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7175 (equality_op:GPR2 (match_operand:GPR2 1 "register_operand" "d,d")
7177 (match_operand:GPR 2 "reg_or_0_operand" "d,J")
7178 (match_operand:GPR 3 "reg_or_0_operand" "J,d")))]
7180 && (register_operand (operands[2], <GPR:MODE>mode)
7181 != register_operand (operands[3], <GPR:MODE>mode))"
7185 [(set_attr "type" "condmove")
7186 (set_attr "mode" "<GPR:MODE>")])
7188 ;; sel.fmt copies the 3rd argument when the 1st is non-zero and the 2nd
7189 ;; argument if the 1st is zero. This means operand 2 and 3 are
7190 ;; inverted in the instruction.
7192 (define_insn "*sel<mode>"
7193 [(set (match_operand:SCALARF 0 "register_operand" "=f,f,f")
7194 (if_then_else:SCALARF
7195 (ne:CCF (match_operand:CCF 1 "register_operand" "0,f,f")
7197 (match_operand:SCALARF 2 "reg_or_0_operand" "f,G,f")
7198 (match_operand:SCALARF 3 "reg_or_0_operand" "f,f,G")))]
7199 "ISA_HAS_SEL && ISA_HAS_CCF"
7202 seleqz.<fmt>\t%0,%3,%1
7203 selnez.<fmt>\t%0,%2,%1"
7204 [(set_attr "type" "condmove")
7205 (set_attr "mode" "<SCALARF:MODE>")])
7207 ;; These are the main define_expand's used to make conditional moves.
7209 (define_expand "mov<mode>cc"
7210 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
7211 (set (match_operand:GPR 0 "register_operand")
7212 (if_then_else:GPR (match_dup 5)
7213 (match_operand:GPR 2 "reg_or_0_operand")
7214 (match_operand:GPR 3 "reg_or_0_operand")))]
7215 "ISA_HAS_CONDMOVE || ISA_HAS_SEL"
7217 if (!ISA_HAS_FP_CONDMOVE
7218 && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0))))
7221 mips_expand_conditional_move (operands);
7225 (define_expand "mov<mode>cc"
7226 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
7227 (set (match_operand:SCALARF 0 "register_operand")
7228 (if_then_else:SCALARF (match_dup 5)
7229 (match_operand:SCALARF 2 "reg_or_0_operand")
7230 (match_operand:SCALARF 3 "reg_or_0_operand")))]
7231 "ISA_HAS_FP_CONDMOVE
7232 || (ISA_HAS_SEL && ISA_HAS_CCF)"
7234 if (ISA_HAS_SEL && !FLOAT_MODE_P (GET_MODE (XEXP (operands[1], 0))))
7237 /* Workaround an LRA bug which means that tied operands in the sel.fmt
7238 pattern lead to the double precision destination of sel.d getting
7239 reloaded with the full register file usable and the restrictions on
7240 whether the CCFmode input can be used in odd-numbered single-precision
7241 registers are ignored. For consistency reasons the CCF mode values
7242 must be guaranteed to only exist in the even-registers because of
7243 the unusual duality between single and double precision values. */
7244 if (ISA_HAS_SEL && <MODE>mode == DFmode
7245 && (!TARGET_ODD_SPREG || TARGET_FLOATXX))
7248 mips_expand_conditional_move (operands);
7253 ;; ....................
7255 ;; mips16 inline constant tables
7257 ;; ....................
7260 (define_insn "consttable_tls_reloc"
7261 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "")
7262 (match_operand 1 "const_int_operand" "")]
7263 UNSPEC_CONSTTABLE_INT)]
7264 "TARGET_MIPS16_PCREL_LOADS"
7265 { return mips_output_tls_reloc_directive (&operands[0]); }
7266 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
7268 (define_insn "consttable_int"
7269 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
7270 (match_operand 1 "const_int_operand" "")]
7271 UNSPEC_CONSTTABLE_INT)]
7274 assemble_integer (mips_strip_unspec_address (operands[0]),
7275 INTVAL (operands[1]),
7276 BITS_PER_UNIT * INTVAL (operands[1]), 1);
7279 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
7281 (define_insn "consttable_float"
7282 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
7283 UNSPEC_CONSTTABLE_FLOAT)]
7288 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
7289 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
7290 assemble_real (d, GET_MODE (operands[0]),
7291 GET_MODE_BITSIZE (GET_MODE (operands[0])));
7294 [(set (attr "length")
7295 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
7297 (define_insn "align"
7298 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
7301 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
7304 [(match_operand 0 "small_data_pattern")]
7307 { operands[0] = mips_rewrite_small_data (operands[0]); })
7310 ;; ....................
7312 ;; MIPS16e Save/Restore
7314 ;; ....................
7317 (define_insn "*mips16e_save_restore"
7318 [(match_parallel 0 ""
7319 [(set (match_operand:SI 1 "register_operand")
7320 (plus:SI (match_dup 1)
7321 (match_operand:SI 2 "const_int_operand")))])]
7322 "operands[1] == stack_pointer_rtx
7323 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
7324 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
7325 [(set_attr "type" "arith")
7326 (set_attr "extended_mips16" "yes")])
7328 ;; Thread-Local Storage
7330 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
7331 ;; MIPS architecture defines this register, and no current
7332 ;; implementation provides it; instead, any OS which supports TLS is
7333 ;; expected to trap and emulate this instruction. rdhwr is part of the
7334 ;; MIPS 32r2 specification, but we use it on any architecture because
7335 ;; we expect it to be emulated. Use .set to force the assembler to
7338 ;; We do not use a constraint to force the destination to be $3
7339 ;; because $3 can appear explicitly as a function return value.
7340 ;; If we leave the use of $3 implicit in the constraints until
7341 ;; reload, we may end up making a $3 return value live across
7342 ;; the instruction, leading to a spill failure when reloading it.
7343 (define_insn_and_split "tls_get_tp_<mode>"
7344 [(set (match_operand:P 0 "register_operand" "=d")
7345 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
7346 (clobber (reg:P TLS_GET_TP_REGNUM))]
7347 "HAVE_AS_TLS && !TARGET_MIPS16"
7349 "&& reload_completed"
7350 [(set (reg:P TLS_GET_TP_REGNUM)
7351 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
7352 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
7354 [(set_attr "type" "unknown")
7355 (set_attr "mode" "<MODE>")
7356 (set_attr "insn_count" "2")])
7358 (define_insn "*tls_get_tp_<mode>_split"
7359 [(set (reg:P TLS_GET_TP_REGNUM)
7360 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
7361 "HAVE_AS_TLS && !TARGET_MIPS16"
7363 if (mips_isa_rev >= 2)
7364 return "rdhwr\t$3,$29";
7366 return ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop";
7368 [(set_attr "type" "unknown")
7369 ; Since rdhwr always generates a trap for now, putting it in a delay
7370 ; slot would make the kernel's emulation of it much slower.
7371 (set_attr "can_delay" "no")
7372 (set_attr "mode" "<MODE>")])
7374 ;; In MIPS16 mode, the TLS base pointer is accessed by a
7375 ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not
7376 ;; accessible in MIPS16.
7378 ;; This is not represented as a call insn, to avoid the
7379 ;; unnecesarry clobbering of caller-save registers by a
7380 ;; function consisting only of: "rdhwr $3,$29; j $31; nop;"
7382 ;; A $25 clobber is added to cater for a $25 load stub added by the
7383 ;; linker to __mips16_rdhwr when the call is made from non-PIC code.
7385 (define_insn_and_split "tls_get_tp_mips16_<mode>"
7386 [(set (match_operand:P 0 "register_operand" "=d")
7387 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")]
7389 (clobber (reg:P TLS_GET_TP_REGNUM))
7390 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7391 (clobber (reg:P RETURN_ADDR_REGNUM))]
7392 "HAVE_AS_TLS && TARGET_MIPS16"
7394 "&& reload_completed"
7395 [(parallel [(set (reg:P TLS_GET_TP_REGNUM)
7396 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP))
7397 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7398 (clobber (reg:P RETURN_ADDR_REGNUM))])
7399 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
7401 [(set_attr "type" "multi")
7402 (set_attr "insn_count" "4")
7403 (set_attr "mode" "<MODE>")])
7405 (define_insn "*tls_get_tp_mips16_call_<mode>"
7406 [(set (reg:P TLS_GET_TP_REGNUM)
7407 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")]
7409 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7410 (clobber (reg:P RETURN_ADDR_REGNUM))]
7411 "HAVE_AS_TLS && TARGET_MIPS16"
7412 { return MIPS_CALL ("jal", operands, 0, -1); }
7413 [(set_attr "type" "call")
7414 (set_attr "insn_count" "3")
7415 (set_attr "mode" "<MODE>")])
7417 ;; Named pattern for expanding thread pointer reference.
7418 (define_expand "get_thread_pointer<mode>"
7419 [(match_operand:P 0 "register_operand" "=d")]
7422 mips_expand_thread_pointer (operands[0]);
7426 ;; __builtin_mips_get_fcsr: move the FCSR into operand 0.
7427 (define_expand "mips_get_fcsr"
7428 [(set (match_operand:SI 0 "register_operand")
7429 (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
7430 "TARGET_HARD_FLOAT_ABI"
7434 mips16_expand_get_fcsr (operands[0]);
7439 (define_insn "*mips_get_fcsr"
7440 [(set (match_operand:SI 0 "register_operand" "=d")
7441 (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
7445 ;; See tls_get_tp_mips16_<mode> for why this form is used.
7446 (define_insn "mips_get_fcsr_mips16_<mode>"
7447 [(set (reg:SI GET_FCSR_REGNUM)
7448 (unspec:SI [(match_operand:P 0 "call_insn_operand" "dS")]
7450 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7451 (clobber (reg:P RETURN_ADDR_REGNUM))]
7452 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16"
7453 { return MIPS_CALL ("jal", operands, 0, -1); }
7454 [(set_attr "type" "call")
7455 (set_attr "insn_count" "3")])
7457 ;; __builtin_mips_set_fcsr: move operand 0 into the FCSR.
7458 (define_expand "mips_set_fcsr"
7459 [(unspec_volatile [(match_operand:SI 0 "register_operand")]
7461 "TARGET_HARD_FLOAT_ABI"
7465 mips16_expand_set_fcsr (operands[0]);
7470 (define_insn "*mips_set_fcsr"
7471 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
7476 ;; See tls_get_tp_mips16_<mode> for why this form is used.
7477 (define_insn "mips_set_fcsr_mips16_<mode>"
7478 [(unspec_volatile:SI [(match_operand:P 0 "call_insn_operand" "dS")
7479 (reg:SI SET_FCSR_REGNUM)] UNSPEC_SET_FCSR)
7480 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7481 (clobber (reg:P RETURN_ADDR_REGNUM))]
7482 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16"
7483 { return MIPS_CALL ("jal", operands, 0, -1); }
7484 [(set_attr "type" "call")
7485 (set_attr "insn_count" "3")])
7487 ;; Match paired HI/SI/SF/DFmode load/stores.
7488 (define_insn "*join2_load_store<JOIN_MODE:mode>"
7489 [(set (match_operand:JOIN_MODE 0 "nonimmediate_operand" "=d,f,m,m")
7490 (match_operand:JOIN_MODE 1 "nonimmediate_operand" "m,m,d,f"))
7491 (set (match_operand:JOIN_MODE 2 "nonimmediate_operand" "=d,f,m,m")
7492 (match_operand:JOIN_MODE 3 "nonimmediate_operand" "m,m,d,f"))]
7493 "ENABLE_LD_ST_PAIRS && reload_completed"
7495 bool load_p = (which_alternative == 0 || which_alternative == 1);
7496 /* Reg-renaming pass reuses base register if it is dead after bonded loads.
7497 Hardware does not bond those loads, even when they are consecutive.
7498 However, order of the loads need to be checked for correctness. */
7499 if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[1]))
7501 output_asm_insn (mips_output_move (operands[0], operands[1]),
7503 output_asm_insn (mips_output_move (operands[2], operands[3]),
7508 output_asm_insn (mips_output_move (operands[2], operands[3]),
7510 output_asm_insn (mips_output_move (operands[0], operands[1]),
7515 [(set_attr "move_type" "load,fpload,store,fpstore")
7516 (set_attr "insn_count" "2,2,2,2")])
7518 ;; 2 HI/SI/SF/DF loads are joined.
7519 ;; P5600 does not support bonding of two LBs, hence QI mode is not included.
7520 ;; The loads must be non-volatile as they might be reordered at the time of asm
7523 [(set (match_operand:JOIN_MODE 0 "register_operand")
7524 (match_operand:JOIN_MODE 1 "non_volatile_mem_operand"))
7525 (set (match_operand:JOIN_MODE 2 "register_operand")
7526 (match_operand:JOIN_MODE 3 "non_volatile_mem_operand"))]
7528 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, true)"
7529 [(parallel [(set (match_dup 0)
7535 ;; 2 HI/SI/SF/DF stores are joined.
7536 ;; P5600 does not support bonding of two SBs, hence QI mode is not included.
7538 [(set (match_operand:JOIN_MODE 0 "memory_operand")
7539 (match_operand:JOIN_MODE 1 "register_operand"))
7540 (set (match_operand:JOIN_MODE 2 "memory_operand")
7541 (match_operand:JOIN_MODE 3 "register_operand"))]
7543 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, false)"
7544 [(parallel [(set (match_dup 0)
7550 ;; Match paired HImode loads.
7551 (define_insn "*join2_loadhi"
7552 [(set (match_operand:SI 0 "register_operand" "=r")
7553 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand" "m")))
7554 (set (match_operand:SI 2 "register_operand" "=r")
7555 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand" "m")))]
7556 "ENABLE_LD_ST_PAIRS && reload_completed"
7558 /* Reg-renaming pass reuses base register if it is dead after bonded loads.
7559 Hardware does not bond those loads, even when they are consecutive.
7560 However, order of the loads need to be checked for correctness. */
7561 if (!reg_overlap_mentioned_p (operands[0], operands[1]))
7563 output_asm_insn ("lh<u>\t%0,%1", operands);
7564 output_asm_insn ("lh<u>\t%2,%3", operands);
7568 output_asm_insn ("lh<u>\t%2,%3", operands);
7569 output_asm_insn ("lh<u>\t%0,%1", operands);
7574 [(set_attr "move_type" "load")
7575 (set_attr "insn_count" "2")])
7578 ;; 2 HI loads are joined.
7580 [(set (match_operand:SI 0 "register_operand")
7581 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand")))
7582 (set (match_operand:SI 2 "register_operand")
7583 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand")))]
7585 && mips_load_store_bonding_p (operands, HImode, true)"
7586 [(parallel [(set (match_dup 0)
7587 (any_extend:SI (match_dup 1)))
7589 (any_extend:SI (match_dup 3)))])]
7593 ;; Synchronization instructions.
7597 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
7599 (include "mips-ps-3d.md")
7601 ; The MIPS DSP Instructions.
7603 (include "mips-dsp.md")
7605 ; The MIPS DSP REV 2 Instructions.
7607 (include "mips-dspr2.md")
7609 ; MIPS fixed-point instructions.
7610 (include "mips-fixed.md")
7612 ; microMIPS patterns.
7613 (include "micromips.md")
7615 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
7616 (include "loongson.md")
7618 (define_c_enum "unspec" [
7619 UNSPEC_ADDRESS_FIRST