1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989-2018 Free Software Foundation, Inc.
3 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
4 ;; Changes by Michael Meissner, meissner@osf.org
5 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 ;; Brendan Eich, brendan@microunity.com.
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 (define_enum "processor" [
75 (define_c_enum "unspec" [
76 ;; Unaligned accesses.
82 ;; Integer operations that are too cumbersome to describe directly.
87 ;; Floating-point moves.
94 ;; Floating-point environment.
107 UNSPEC_POTENTIAL_CPRESTORE
112 UNSPEC_SET_GOT_VERSION
113 UNSPEC_UPDATE_GOT_VERSION
115 ;; Symbolic accesses.
120 UNSPEC_UNSHIFTED_HIGH
122 ;; MIPS16 constant pools.
125 UNSPEC_CONSTTABLE_END
126 UNSPEC_CONSTTABLE_INT
127 UNSPEC_CONSTTABLE_FLOAT
129 ;; Blockage and synchronisation.
136 ;; Cache manipulation.
138 UNSPEC_R10K_CACHE_BARRIER
140 ;; Interrupt handling.
148 ;; Used in a call expression in place of args_size. It's present for PIC
149 ;; indirect calls where it contains args_size and the function symbol.
152 ;; MIPS16 casesi jump table dispatch.
153 UNSPEC_CASESI_DISPATCH
156 UNSPEC_PROBE_STACK_RANGE
158 ;; The `.insn' pseudo-op.
163 [(TLS_GET_TP_REGNUM 3)
166 (PIC_FUNCTION_ADDR_REGNUM 25)
167 (RETURN_ADDR_REGNUM 31)
168 (CPRESTORE_SLOT_REGNUM 76)
169 (GOT_VERSION_REGNUM 79)
171 ;; PIC long branch sequences are never longer than 100 bytes.
172 (MAX_PIC_BRANCH_LENGTH 100)
176 (include "predicates.md")
177 (include "constraints.md")
179 ;; ....................
183 ;; ....................
185 (define_attr "got" "unset,xgot_high,load"
186 (const_string "unset"))
188 ;; For jal instructions, this attribute is DIRECT when the target address
189 ;; is symbolic and INDIRECT when it is a register.
190 (define_attr "jal" "unset,direct,indirect"
191 (const_string "unset"))
193 ;; This attribute is YES if the instruction is a jal macro (not a
194 ;; real jal instruction).
196 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
197 ;; an instruction to restore $gp. Direct jals are also macros for
198 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
200 (define_attr "jal_macro" "no,yes"
201 (cond [(eq_attr "jal" "direct")
202 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
203 ? JAL_MACRO_YES : JAL_MACRO_NO)")
204 (eq_attr "jal" "indirect")
205 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
206 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
207 (const_string "no")))
209 ;; Classification of moves, extensions and truncations. Most values
210 ;; are as for "type" (see below) but there are also the following
211 ;; move-specific values:
213 ;; constN move an N-constraint integer into a MIPS16 register
214 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
215 ;; to produce a sign-extended DEST, even if SRC is not
216 ;; properly sign-extended
217 ;; ext_ins EXT, DEXT, INS or DINS instruction
218 ;; andi a single ANDI instruction
219 ;; loadpool move a constant into a MIPS16 register by loading it
221 ;; shift_shift a shift left followed by a shift right
223 ;; This attribute is used to determine the instruction's length and
224 ;; scheduling type. For doubleword moves, the attribute always describes
225 ;; the split instructions; in some cases, it is more appropriate for the
226 ;; scheduling type to be "multi" instead.
227 (define_attr "move_type"
228 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove,
229 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
231 (const_string "unknown"))
233 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor,simd_add"
234 (const_string "unknown"))
236 ;; Main data type used by the insn
237 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW,
238 V2DI,V4SI,V8HI,V16QI,V2DF,V4SF"
239 (const_string "unknown"))
241 ;; True if the main data type is twice the size of a word.
242 (define_attr "dword_mode" "no,yes"
243 (cond [(and (eq_attr "mode" "DI,DF")
244 (not (match_test "TARGET_64BIT")))
247 (and (eq_attr "mode" "TI,TF")
248 (match_test "TARGET_64BIT"))
249 (const_string "yes")]
250 (const_string "no")))
252 ;; True if the main data type is four times of the size of a word.
253 (define_attr "qword_mode" "no,yes"
254 (cond [(and (eq_attr "mode" "TI,TF")
255 (not (match_test "TARGET_64BIT")))
256 (const_string "yes")]
257 (const_string "no")))
259 ;; Attributes describing a sync loop. These loops have the form:
261 ;; if (RELEASE_BARRIER == YES) sync
263 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
264 ;; CMP = 0 [delay slot]
265 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
266 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
267 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
268 ;; $AT |= $TMP1 | $TMP3
269 ;; if (!commit (*MEM = $AT)) goto 1.
270 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
272 ;; if (ACQUIRE_BARRIER == YES) sync
275 ;; where "$" values are temporaries and where the other values are
276 ;; specified by the attributes below. Values are specified as operand
277 ;; numbers and insns are specified as enums. If no operand number is
278 ;; specified, the following values are used instead:
283 ;; - INCLUSIVE_MASK: -1
284 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
285 ;; - EXCLUSIVE_MASK: 0
287 ;; MEM and INSN1_OP2 are required.
289 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
290 ;; but the gen* programs don't yet support that.
291 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
292 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
293 (define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
294 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
295 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
296 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
297 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
298 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
299 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
300 (const_string "move"))
301 (define_attr "sync_insn2" "nop,and,xor,not"
302 (const_string "nop"))
303 ;; Memory model specifier.
304 ;; "0"-"9" values specify the operand that stores the memory model value.
305 ;; "10" specifies MEMMODEL_ACQ_REL,
306 ;; "11" specifies MEMMODEL_ACQUIRE.
307 (define_attr "sync_memmodel" "" (const_int 10))
309 ;; Accumulator operand for madd patterns.
310 (define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
312 ;; Classification of each insn.
313 ;; branch conditional branch
314 ;; jump unconditional jump
315 ;; call unconditional call
316 ;; load load instruction(s)
317 ;; fpload floating point load
318 ;; fpidxload floating point indexed load
319 ;; store store instruction(s)
320 ;; fpstore floating point store
321 ;; fpidxstore floating point indexed store
322 ;; prefetch memory prefetch (register + offset)
323 ;; prefetchx memory indexed prefetch (register + register)
324 ;; condmove conditional moves
325 ;; mtc transfer to coprocessor
326 ;; mfc transfer from coprocessor
327 ;; mthi transfer to a hi register
328 ;; mtlo transfer to a lo register
329 ;; mfhi transfer from a hi register
330 ;; mflo transfer from a lo register
331 ;; const load constant
332 ;; arith integer arithmetic instructions
333 ;; logical integer logical instructions
334 ;; shift integer shift instructions
335 ;; slt set less than instructions
336 ;; signext sign extend instructions
337 ;; clz the clz and clo instructions
338 ;; pop the pop instruction
339 ;; trap trap if instructions
340 ;; imul integer multiply 2 operands
341 ;; imul3 integer multiply 3 operands
342 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
343 ;; imadd integer multiply-add
344 ;; idiv integer divide 2 operands
345 ;; idiv3 integer divide 3 operands
346 ;; move integer register move ({,D}ADD{,U} with rt = 0)
347 ;; fmove floating point register move
348 ;; fadd floating point add/subtract
349 ;; fmul floating point multiply
350 ;; fmadd floating point multiply-add
351 ;; fdiv floating point divide
352 ;; frdiv floating point reciprocal divide
353 ;; frdiv1 floating point reciprocal divide step 1
354 ;; frdiv2 floating point reciprocal divide step 2
355 ;; fabs floating point absolute value
356 ;; fneg floating point negation
357 ;; fcmp floating point compare
358 ;; fcvt floating point convert
359 ;; fsqrt floating point square root
360 ;; frsqrt floating point reciprocal square root
361 ;; frsqrt1 floating point reciprocal square root step1
362 ;; frsqrt2 floating point reciprocal square root step2
363 ;; dspmac DSP MAC instructions not saturating the accumulator
364 ;; dspmacsat DSP MAC instructions that saturate the accumulator
365 ;; accext DSP accumulator extract instructions
366 ;; accmod DSP accumulator modify instructions
367 ;; dspalu DSP ALU instructions not saturating the result
368 ;; dspalusat DSP ALU instructions that saturate the result
369 ;; multi multiword sequence (or user asm statements)
370 ;; atomic atomic memory update instruction
371 ;; syncloop memory atomic operation implemented as a sync loop
373 ;; ghost an instruction that produces no real code
374 ;; multimem microMIPS multiword load and store
376 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
377 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
378 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
379 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
380 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
381 multi,atomic,syncloop,nop,ghost,multimem,
382 simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd,
383 simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp,
384 simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill,
385 simd_permute,simd_shf,simd_sat,simd_pcnt,simd_copy,simd_branch,simd_cmsa,
386 simd_fminmax,simd_logic,simd_move,simd_load,simd_store"
387 (cond [(eq_attr "jal" "!unset") (const_string "call")
388 (eq_attr "got" "load") (const_string "load")
390 (eq_attr "alu_type" "add,sub") (const_string "arith")
392 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
394 ;; If a doubleword move uses these expensive instructions,
395 ;; it is usually better to schedule them in the same way
396 ;; as the singleword form, rather than as "multi".
397 (eq_attr "move_type" "load") (const_string "load")
398 (eq_attr "move_type" "fpload") (const_string "fpload")
399 (eq_attr "move_type" "store") (const_string "store")
400 (eq_attr "move_type" "fpstore") (const_string "fpstore")
401 (eq_attr "move_type" "mtc") (const_string "mtc")
402 (eq_attr "move_type" "mfc") (const_string "mfc")
403 (eq_attr "move_type" "mtlo") (const_string "mtlo")
404 (eq_attr "move_type" "mflo") (const_string "mflo")
406 ;; These types of move are always single insns.
407 (eq_attr "move_type" "imul") (const_string "imul")
408 (eq_attr "move_type" "fmove") (const_string "fmove")
409 (eq_attr "move_type" "loadpool") (const_string "load")
410 (eq_attr "move_type" "signext") (const_string "signext")
411 (eq_attr "move_type" "ext_ins") (const_string "arith")
412 (eq_attr "move_type" "arith") (const_string "arith")
413 (eq_attr "move_type" "logical") (const_string "logical")
414 (eq_attr "move_type" "sll0") (const_string "shift")
415 (eq_attr "move_type" "andi") (const_string "logical")
417 ;; These types of move are always split.
418 (eq_attr "move_type" "constN,shift_shift")
419 (const_string "multi")
421 ;; These types of move are split for quadword modes only.
422 (and (eq_attr "move_type" "move,const")
423 (eq_attr "qword_mode" "yes"))
424 (const_string "multi")
426 ;; These types of move are split for doubleword modes only.
427 (and (eq_attr "move_type" "move,const")
428 (eq_attr "dword_mode" "yes"))
429 (const_string "multi")
430 (eq_attr "move_type" "move") (const_string "move")
431 (eq_attr "move_type" "const") (const_string "const")
432 (eq_attr "sync_mem" "!none") (const_string "syncloop")]
433 (const_string "unknown")))
435 (define_attr "compact_form" "always,maybe,never"
436 (cond [(eq_attr "jal" "direct")
437 (const_string "always")
438 (eq_attr "jal" "indirect")
439 (const_string "maybe")
440 (eq_attr "type" "jump")
441 (const_string "maybe")]
442 (const_string "never")))
444 ;; Mode for conversion types (fcvt)
445 ;; I2S integer to float single (SI/DI to SF)
446 ;; I2D integer to float double (SI/DI to DF)
447 ;; S2I float to integer (SF to SI/DI)
448 ;; D2I float to integer (DF to SI/DI)
449 ;; D2S double to float single
450 ;; S2D float single to double
452 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
453 (const_string "unknown"))
455 ;; Is this an extended instruction in mips16 mode?
456 (define_attr "extended_mips16" "no,yes"
457 (if_then_else (ior ;; In general, constant-pool loads are extended
458 ;; instructions. We don't yet optimize for 16-bit
459 ;; PC-relative references.
460 (eq_attr "move_type" "sll0,loadpool")
461 (eq_attr "jal" "direct")
462 (eq_attr "got" "load"))
464 (const_string "no")))
466 (define_attr "compression" "none,all,micromips32,micromips"
467 (const_string "none"))
469 (define_attr "enabled" "no,yes"
470 (cond [;; The o32 FPXX and FP64A ABI extensions prohibit direct moves between
471 ;; GR_REG and FR_REG for 64-bit values.
472 (and (eq_attr "move_type" "mtc,mfc")
473 (match_test "(TARGET_FLOATXX && !ISA_HAS_MXHC1)
474 || TARGET_O32_FP64A_ABI")
475 (eq_attr "dword_mode" "yes"))
477 (and (eq_attr "compression" "micromips32,micromips")
478 (match_test "!TARGET_MICROMIPS"))
480 (const_string "yes")))
482 ;; The number of individual instructions that a non-branch pattern generates,
483 ;; using units of BASE_INSN_LENGTH.
484 (define_attr "insn_count" ""
485 (cond [;; "Ghost" instructions occupy no space.
486 (eq_attr "type" "ghost")
489 ;; Extended instructions count as 2.
490 (and (eq_attr "extended_mips16" "yes")
491 (match_test "TARGET_MIPS16"))
494 ;; A GOT load followed by an add of $gp. This is not used for MIPS16.
495 (eq_attr "got" "xgot_high")
498 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
499 ;; They are extended instructions on MIPS16 targets.
500 (eq_attr "move_type" "shift_shift")
501 (if_then_else (match_test "TARGET_MIPS16")
505 ;; Check for doubleword moves that are decomposed into two
506 ;; instructions. The individual instructions are unextended
508 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
509 (eq_attr "dword_mode" "yes"))
512 ;; Check for quadword moves that are decomposed into four
514 (and (eq_attr "move_type" "mtc,mfc,move")
515 (eq_attr "qword_mode" "yes"))
518 ;; Constants, loads and stores are handled by external routines.
519 (and (eq_attr "move_type" "const,constN")
520 (eq_attr "dword_mode" "yes"))
521 (symbol_ref "mips_split_const_insns (operands[1])")
522 (eq_attr "move_type" "const,constN")
523 (symbol_ref "mips_const_insns (operands[1])")
524 (eq_attr "move_type" "load,fpload")
525 (symbol_ref "mips_load_store_insns (operands[1], insn)")
526 (eq_attr "move_type" "store,fpstore")
527 (symbol_ref "mips_load_store_insns (operands[0], insn)
528 + (TARGET_FIX_24K ? 1 : 0)")
530 ;; In the worst case, a call macro will take 8 instructions:
532 ;; lui $25,%call_hi(FOO)
534 ;; lw $25,%call_lo(FOO)($25)
540 (eq_attr "jal_macro" "yes")
543 ;; Various VR4120 errata require a nop to be inserted after a macc
544 ;; instruction. The assembler does this for us, so account for
545 ;; the worst-case length here.
546 (and (eq_attr "type" "imadd")
547 (match_test "TARGET_FIX_VR4120"))
550 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
551 ;; the result of the second one is missed. The assembler should work
552 ;; around this by inserting a nop after the first dmult.
553 (and (eq_attr "type" "imul,imul3")
554 (eq_attr "mode" "DI")
555 (match_test "TARGET_FIX_VR4120"))
558 (eq_attr "type" "idiv,idiv3")
559 (symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))")
561 (not (eq_attr "sync_mem" "none"))
562 (symbol_ref "mips_sync_loop_insns (insn, operands)")]
565 ;; Length of instruction in bytes. The default is derived from "insn_count",
566 ;; but there are special cases for branches (which must be handled here)
567 ;; and for compressed single instructions.
568 (define_attr "length" ""
569 (cond [(and (ior (eq_attr "compression" "micromips,all")
570 (and (eq_attr "compression" "micromips32")
571 (eq_attr "mode" "SI,SF")))
572 (eq_attr "dword_mode" "no")
573 (match_test "TARGET_MICROMIPS"))
576 ;; Direct microMIPS branch instructions have a range of
577 ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc].
578 ;; If a branch is outside this range, we have a choice of two
581 ;; For PIC, an out-of-range branch like:
586 ;; becomes the equivalent of:
595 ;; The non-PIC case is similar except that we use a direct
596 ;; jump instead of an la/jr pair. Since the target of this
597 ;; jump is an absolute 28-bit bit address (the other bits
598 ;; coming from the address of the delay slot) this form cannot
599 ;; cross a 256MB boundary. We could provide the option of
600 ;; using la/jr in this case too, but we do not do so at
603 ;; The value we specify here does not account for the delay slot
604 ;; instruction, whose length is added separately. If the RTL
605 ;; pattern has no explicit delay slot, mips_adjust_insn_length
606 ;; will add the length of the implicit nop. The range of
607 ;; [-0x20000, 0x1fffc] from the address of the delay slot
608 ;; therefore translates to a range of:
610 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
611 ;; == [-0x1fffc, 0x1fff8]
613 ;; from the shorten_branches reference address.
614 (and (eq_attr "type" "branch")
615 (not (match_test "TARGET_MIPS16")))
616 (cond [;; Any variant can handle the 17-bit range.
617 (and (le (minus (match_dup 0) (pc)) (const_int 65532))
618 (le (minus (pc) (match_dup 0)) (const_int 65534)))
621 ;; The 18-bit range is OK other than for microMIPS.
622 (and (not (match_test "TARGET_MICROMIPS"))
623 (and (le (minus (match_dup 0) (pc)) (const_int 131064))
624 (le (minus (pc) (match_dup 0)) (const_int 131068))))
627 ;; The non-PIC case: branch, first delay slot, and J.
628 (match_test "TARGET_ABSOLUTE_JUMPS")
631 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
632 ;; mips_adjust_insn_length substitutes the correct length.
634 ;; Note that we can't simply use (symbol_ref ...) here
635 ;; because genattrtab needs to know the maximum length
637 (const_int MAX_PIC_BRANCH_LENGTH))
639 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
640 ;; from the address of the following instruction, which leads
643 ;; [-(0x100 - sizeof (branch)), 0xfe]
646 ;; from the shorten_branches reference address. Extended branches
647 ;; likewise have a range of [-0x10000, 0xfffe] from the address
648 ;; of the following instruction, which leads to a range of:
650 ;; [-(0x10000 - sizeof (branch)), 0xfffe]
651 ;; == [-0xfffc, 0xfffe]
653 ;; from the reference address.
655 ;; When a branch is out of range, mips_reorg splits it into a form
656 ;; that uses in-range branches. There are four basic sequences:
658 ;; (1) Absolute addressing with a readable text segment
659 ;; (32-bit addresses):
662 ;; move $1,$2 2 bytes
663 ;; lw $2,label 2 bytes
665 ;; move $2,$1 2 bytes
666 ;; .align 2 0 or 2 bytes
668 ;; .word target 4 bytes
670 ;; (16 bytes in the worst case)
672 ;; (2) Absolute addressing with a readable text segment
673 ;; (64-bit addresses):
676 ;; move $1,$2 2 bytes
677 ;; ld $2,label 2 bytes
679 ;; move $2,$1 2 bytes
680 ;; .align 3 0 to 6 bytes
682 ;; .dword target 8 bytes
684 ;; (24 bytes in the worst case)
686 ;; (3) Absolute addressing without a readable text segment
687 ;; (which requires 32-bit addresses at present):
690 ;; move $1,$2 2 bytes
691 ;; lui $2,%hi(target) 4 bytes
694 ;; addiu $2,%lo(target) 4 bytes
696 ;; move $2,$1 2 bytes
700 ;; (4) PIC addressing (which requires 32-bit addresses at present):
703 ;; move $1,$2 2 bytes
704 ;; lw $2,cprestore 0, 2 or 4 bytes
705 ;; lw $2,%got(target)($2) 4 bytes
706 ;; addiu $2,%lo(target) 4 bytes
708 ;; move $2,$1 2 bytes
710 ;; (20 bytes in the worst case)
711 (and (eq_attr "type" "branch")
712 (match_test "TARGET_MIPS16"))
713 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
714 (le (minus (pc) (match_dup 0)) (const_int 254)))
716 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
717 (le (minus (pc) (match_dup 0)) (const_int 65532)))
719 (and (match_test "TARGET_ABICALLS")
720 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
722 (match_test "Pmode == SImode")
725 (symbol_ref "get_attr_insn_count (insn) * BASE_INSN_LENGTH")))
727 ;; Attribute describing the processor.
728 (define_enum_attr "cpu" "processor"
729 (const (symbol_ref "mips_tune")))
731 ;; The type of hardware hazard associated with this instruction.
732 ;; DELAY means that the next instruction cannot read the result
733 ;; of this one. HILO means that the next two instructions cannot
734 ;; write to HI or LO.
735 (define_attr "hazard" "none,delay,hilo,forbidden_slot"
736 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
737 (match_test "ISA_HAS_LOAD_DELAY"))
738 (const_string "delay")
740 (and (eq_attr "type" "mfc,mtc")
741 (match_test "ISA_HAS_XFER_DELAY"))
742 (const_string "delay")
744 (and (eq_attr "type" "fcmp")
745 (match_test "ISA_HAS_FCMP_DELAY"))
746 (const_string "delay")
748 ;; The r4000 multiplication patterns include an mflo instruction.
749 (and (eq_attr "type" "imul")
750 (match_test "TARGET_FIX_R4000"))
751 (const_string "hilo")
753 (and (eq_attr "type" "mfhi,mflo")
754 (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
755 (const_string "hilo")]
756 (const_string "none")))
758 ;; Can the instruction be put into a delay slot?
759 (define_attr "can_delay" "no,yes"
760 (if_then_else (and (eq_attr "type" "!branch,call,jump")
761 (eq_attr "hazard" "none")
762 (match_test "get_attr_insn_count (insn) == 1"))
764 (const_string "no")))
766 ;; Attribute defining whether or not we can use the branch-likely
768 (define_attr "branch_likely" "no,yes"
769 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
771 (const_string "no")))
773 ;; True if an instruction might assign to hi or lo when reloaded.
774 ;; This is used by the TUNE_MACC_CHAINS code.
775 (define_attr "may_clobber_hilo" "no,yes"
776 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
778 (const_string "no")))
780 ;; Describe a user's asm statement.
781 (define_asm_attributes
782 [(set_attr "type" "multi")
783 (set_attr "can_delay" "no")])
785 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
786 ;; from the same template.
787 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
789 ;; A copy of GPR that can be used when a pattern has two independent
791 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
793 (define_mode_iterator MOVEP1 [SI SF])
794 (define_mode_iterator MOVEP2 [SI SF])
795 (define_mode_iterator JOIN_MODE [HI
797 (SF "TARGET_HARD_FLOAT")
798 (DF "TARGET_HARD_FLOAT
799 && TARGET_DOUBLE_FLOAT")])
801 ;; This mode iterator allows :HILO to be used as the mode of the
802 ;; concatenated HI and LO registers.
803 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
805 ;; This mode iterator allows :P to be used for patterns that operate on
806 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
807 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
809 ;; This mode iterator allows :MOVECC to be used anywhere that a
810 ;; conditional-move-type condition is needed.
811 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
812 (CC "TARGET_HARD_FLOAT
813 && !TARGET_LOONGSON_2EF
814 && !TARGET_MIPS5900")])
816 ;; This mode iterator allows :FPCC to be used anywhere that an FP condition
818 (define_mode_iterator FPCC [(CC "!ISA_HAS_CCF")
819 (CCF "ISA_HAS_CCF")])
821 ;; 32-bit integer moves for which we provide move patterns.
822 (define_mode_iterator IMOVE32
831 (V4UQQ "TARGET_DSP")])
833 ;; 64-bit modes for which we provide move patterns.
834 (define_mode_iterator MOVE64
836 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
837 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI")
838 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI")
839 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI")])
841 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
842 (define_mode_iterator MOVE128 [TI TF])
844 ;; This mode iterator allows the QI and HI extension patterns to be
845 ;; defined from the same template.
846 (define_mode_iterator SHORT [QI HI])
848 ;; Likewise the 64-bit truncate-and-shift patterns.
849 (define_mode_iterator SUBDI [QI HI SI])
851 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
852 ;; floating-point mode is allowed.
853 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
854 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
855 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
857 ;; Like ANYF, but only applies to scalar modes.
858 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
859 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
861 ;; A floating-point mode for which moves involving FPRs may need to be split.
862 (define_mode_iterator SPLITF
863 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
864 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
865 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
866 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_MMI")
867 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_MMI")
868 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_MMI")
869 (TF "TARGET_64BIT && TARGET_FLOAT64")])
871 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
872 ;; 32-bit version and "dsubu" in the 64-bit version.
873 (define_mode_attr d [(SI "") (DI "d")
874 (QQ "") (HQ "") (SQ "") (DQ "d")
875 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
876 (HA "") (SA "") (DA "d")
877 (UHA "") (USA "") (UDA "d")])
879 ;; Same as d but upper-case.
880 (define_mode_attr D [(SI "") (DI "D")
881 (QQ "") (HQ "") (SQ "") (DQ "D")
882 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
883 (HA "") (SA "") (DA "D")
884 (UHA "") (USA "") (UDA "D")])
886 ;; This attribute gives the length suffix for a load or store instruction.
887 ;; The same suffixes work for zero and sign extensions.
888 (define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
889 (define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
891 ;; This attributes gives the mode mask of a SHORT.
892 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
894 ;; Mode attributes for GPR loads.
895 (define_mode_attr load [(SI "lw") (DI "ld")])
896 ;; Instruction names for stores.
897 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
899 ;; Similarly for MIPS IV indexed FPR loads and stores.
900 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
901 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
903 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
904 ;; are different. Some forms of unextended addiu have an 8-bit immediate
905 ;; field but the equivalent daddiu has only a 5-bit field.
906 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
908 ;; This attribute gives the best constraint to use for registers of
910 (define_mode_attr reg [(SI "d") (DI "d") (CC "z") (CCF "f")])
912 ;; This attribute gives the format suffix for floating-point operations.
913 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
915 ;; This attribute gives the upper-case mode name for one unit of a
916 ;; floating-point mode or vector mode.
917 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF") (V4SF "SF")
918 (V16QI "QI") (V8HI "HI") (V4SI "SI") (V2DI "DI")
921 ;; As above, but in lower case.
922 (define_mode_attr unitmode [(SF "sf") (DF "df") (V2SF "sf") (V4SF "sf")
923 (V16QI "qi") (V8QI "qi") (V8HI "hi") (V4HI "hi")
924 (V4SI "si") (V2SI "si") (V2DI "di") (V2DF "df")])
926 ;; This attribute gives the integer mode that has the same size as a
928 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
929 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
930 (HA "HI") (SA "SI") (DA "DI")
931 (UHA "HI") (USA "SI") (UDA "DI")
932 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
933 (V2HQ "SI") (V2HA "SI")])
935 ;; This attribute gives the integer mode that has half the size of
936 ;; the controlling mode.
937 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
938 (V2SI "SI") (V4HI "SI") (V8QI "SI")
941 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
943 ;; In certain cases, div.s and div.ps may have a rounding error
944 ;; and/or wrong inexact flag.
946 ;; Therefore, we only allow div.s if not working around SB-1 rev2
947 ;; errata or if a slight loss of precision is OK.
948 (define_mode_attr divide_condition
949 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
950 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
952 ;; This attribute gives the conditions under which SQRT.fmt instructions
954 (define_mode_attr sqrt_condition
955 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
957 ;; This attribute provides the correct mnemonic for each FP condition mode.
958 (define_mode_attr fpcmp [(CC "c") (CCF "cmp")])
960 ;; This code iterator allows signed and unsigned widening multiplications
961 ;; to use the same template.
962 (define_code_iterator any_extend [sign_extend zero_extend])
964 ;; This code iterator allows the two right shift instructions to be
965 ;; generated from the same template.
966 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
968 ;; This code iterator allows the three shift instructions to be generated
969 ;; from the same template.
970 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
972 ;; This code iterator allows unsigned and signed division to be generated
973 ;; from the same template.
974 (define_code_iterator any_div [div udiv])
976 ;; This code iterator allows unsigned and signed modulus to be generated
977 ;; from the same template.
978 (define_code_iterator any_mod [mod umod])
980 ;; This code iterator allows addition and subtraction to be generated
981 ;; from the same template.
982 (define_code_iterator addsub [plus minus])
984 ;; This code iterator allows all native floating-point comparisons to be
985 ;; generated from the same template.
986 (define_code_iterator fcond [unordered uneq unlt unle eq lt le
987 (ordered "ISA_HAS_CCF")
991 ;; This code iterator is used for comparisons that can be implemented
992 ;; by swapping the operands.
993 (define_code_iterator swapped_fcond [ge gt unge ungt])
995 ;; Equality operators.
996 (define_code_iterator equality_op [eq ne])
998 ;; These code iterators allow the signed and unsigned scc operations to use
999 ;; the same template.
1000 (define_code_iterator any_gt [gt gtu])
1001 (define_code_iterator any_ge [ge geu])
1002 (define_code_iterator any_lt [lt ltu])
1003 (define_code_iterator any_le [le leu])
1005 (define_code_iterator any_return [return simple_return])
1007 ;; <u> expands to an empty string when doing a signed operation and
1008 ;; "u" when doing an unsigned operation.
1009 (define_code_attr u [(sign_extend "") (zero_extend "u")
1017 ;; <U> is like <u> except uppercase.
1018 (define_code_attr U [(sign_extend "") (zero_extend "U")])
1020 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
1021 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
1023 ;; <optab> expands to the name of the optab for a particular code.
1024 (define_code_attr optab [(ashift "ashl")
1033 (simple_return "simple_return")])
1035 ;; <insn> expands to the name of the insn that implements a particular code.
1036 (define_code_attr insn [(ashift "sll")
1045 ;; <immediate_insn> expands to the name of the insn that implements
1046 ;; a particular code to operate on immediate values.
1047 (define_code_attr immediate_insn [(ior "ori")
1051 (define_code_attr shift_compression [(ashift "micromips32")
1052 (lshiftrt "micromips32")
1055 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
1056 (define_code_attr fcond [(unordered "un")
1067 ;; Similar, but for swapped conditions.
1068 (define_code_attr swapped_fcond [(ge "le")
1073 ;; The value of the bit when the branch is taken for branch_bit patterns.
1074 ;; Comparison is always against zero so this depends on the operator.
1075 (define_code_attr bbv [(eq "0") (ne "1")])
1077 ;; This is the inverse value of bbv.
1078 (define_code_attr bbinv [(eq "1") (ne "0")])
1080 ;; The sel mnemonic to use depending on the condition test.
1081 (define_code_attr sel [(eq "seleqz") (ne "selnez")])
1082 (define_code_attr selinv [(eq "selnez") (ne "seleqz")])
1084 ;; .........................
1086 ;; Branch, call and jump delay slots
1088 ;; .........................
1090 (define_delay (and (eq_attr "type" "branch")
1091 (not (match_test "TARGET_MIPS16"))
1092 (eq_attr "branch_likely" "yes"))
1093 [(eq_attr "can_delay" "yes")
1095 (eq_attr "can_delay" "yes")])
1097 ;; Branches that have delay slots and don't have likely variants do
1098 ;; not annul on false.
1099 (define_delay (and (eq_attr "type" "branch")
1100 (not (match_test "TARGET_MIPS16"))
1101 (ior (match_test "TARGET_CB_NEVER")
1102 (and (eq_attr "compact_form" "maybe")
1103 (not (match_test "TARGET_CB_ALWAYS")))
1104 (eq_attr "compact_form" "never"))
1105 (eq_attr "branch_likely" "no"))
1106 [(eq_attr "can_delay" "yes")
1110 (define_delay (and (eq_attr "type" "jump")
1111 (ior (match_test "TARGET_CB_NEVER")
1112 (and (eq_attr "compact_form" "maybe")
1113 (not (match_test "TARGET_CB_ALWAYS")))
1114 (eq_attr "compact_form" "never")))
1115 [(eq_attr "can_delay" "yes")
1119 ;; Call type instructions should never have a compact form as the
1120 ;; type is only used for MIPS16 patterns. For safety put the compact
1121 ;; branch detection condition in anyway.
1122 (define_delay (and (eq_attr "type" "call")
1123 (eq_attr "jal_macro" "no")
1124 (ior (match_test "TARGET_CB_NEVER")
1125 (and (eq_attr "compact_form" "maybe")
1126 (not (match_test "TARGET_CB_ALWAYS")))
1127 (eq_attr "compact_form" "never")))
1128 [(eq_attr "can_delay" "yes")
1132 ;; Pipeline descriptions.
1134 ;; generic.md provides a fallback for processors without a specific
1135 ;; pipeline description. It is derived from the old define_function_unit
1136 ;; version and uses the "alu" and "imuldiv" units declared below.
1138 ;; Some of the processor-specific files are also derived from old
1139 ;; define_function_unit descriptions and simply override the parts of
1140 ;; generic.md that don't apply. The other processor-specific files
1141 ;; are self-contained.
1142 (define_automaton "alu,imuldiv")
1144 (define_cpu_unit "alu" "alu")
1145 (define_cpu_unit "imuldiv" "imuldiv")
1147 ;; Ghost instructions produce no real code and introduce no hazards.
1148 ;; They exist purely to express an effect on dataflow.
1149 (define_insn_reservation "ghost" 0
1150 (eq_attr "type" "ghost")
1153 (include "i6400.md")
1154 (include "p5600.md")
1155 (include "m5100.md")
1156 (include "p6600.md")
1174 (include "10000.md")
1175 (include "loongson2ef.md")
1176 (include "gs464.md")
1177 (include "octeon.md")
1179 (include "sr71k.md")
1182 (include "generic.md")
1185 ;; ....................
1187 ;; CONDITIONAL TRAPS
1189 ;; ....................
1193 [(trap_if (const_int 1) (const_int 0))]
1196 if (ISA_HAS_COND_TRAP)
1197 return "teq\t$0,$0";
1198 else if (TARGET_MIPS16)
1203 [(set_attr "type" "trap")])
1205 (define_expand "ctrap<mode>4"
1206 [(trap_if (match_operator 0 "comparison_operator"
1207 [(match_operand:GPR 1 "reg_or_0_operand")
1208 (match_operand:GPR 2 "arith_operand")])
1209 (match_operand 3 "const_0_operand"))]
1210 "ISA_HAS_COND_TRAPI || ISA_HAS_COND_TRAP"
1212 mips_expand_conditional_trap (operands[0]);
1216 (define_insn "*conditional_trap_reg<mode>"
1217 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1218 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1219 (match_operand:GPR 2 "reg_or_0_operand" "dJ")])
1221 "ISA_HAS_COND_TRAP && !ISA_HAS_COND_TRAPI"
1223 [(set_attr "type" "trap")])
1225 (define_insn "*conditional_trap<mode>"
1226 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1227 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1228 (match_operand:GPR 2 "arith_operand" "dI")])
1230 "ISA_HAS_COND_TRAPI"
1232 [(set_attr "type" "trap")])
1235 ;; ....................
1239 ;; ....................
1242 (define_insn "add<mode>3"
1243 [(set (match_operand:ANYF 0 "register_operand" "=f")
1244 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1245 (match_operand:ANYF 2 "register_operand" "f")))]
1247 "add.<fmt>\t%0,%1,%2"
1248 [(set_attr "type" "fadd")
1249 (set_attr "mode" "<UNITMODE>")])
1251 (define_expand "add<mode>3"
1252 [(set (match_operand:GPR 0 "register_operand")
1253 (plus:GPR (match_operand:GPR 1 "register_operand")
1254 (match_operand:GPR 2 "arith_operand")))]
1257 (define_insn "*add<mode>3"
1258 [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!u,!ks,!d,d")
1259 (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,!ks,!ks,0,d")
1260 (match_operand:GPR 2 "arith_operand" "!u,d,Uead,Uuw6,Uesp,Usb4,Q")))]
1263 if (which_alternative == 0
1264 || which_alternative == 1)
1265 return "<d>addu\t%0,%1,%2";
1267 return "<d>addiu\t%0,%1,%2";
1269 [(set_attr "alu_type" "add")
1270 (set_attr "compression" "micromips32,*,micromips32,micromips32,micromips32,micromips32,*")
1271 (set_attr "mode" "<MODE>")])
1273 (define_insn "*add<mode>3_mips16"
1274 [(set (match_operand:GPR 0 "register_operand" "=ks,ks,d,d,d,d,d,d,d")
1275 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,ks,ks,0,0,d,d,d")
1276 (match_operand:GPR 2 "arith_operand" "Usd8,Q,Uuw<si8_di5>,Q,Usb<si8_di5>,Q,Usb4,O,d")))]
1288 [(set_attr "alu_type" "add")
1289 (set_attr "mode" "<MODE>")
1290 (set_attr "extended_mips16" "no,yes,no,yes,no,yes,no,yes,no")])
1292 ;; On the mips16, we can sometimes split an add of a constant which is
1293 ;; a 4 byte instruction into two adds which are both 2 byte
1294 ;; instructions. There are two cases: one where we are adding a
1295 ;; constant plus a register to another register, and one where we are
1296 ;; simply adding a constant to a register.
1299 [(set (match_operand:SI 0 "d_operand")
1300 (plus:SI (match_dup 0)
1301 (match_operand:SI 1 "const_int_operand")))]
1302 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1303 && ((INTVAL (operands[1]) > 0x7f
1304 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1305 || (INTVAL (operands[1]) < - 0x80
1306 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1307 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1308 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1310 HOST_WIDE_INT val = INTVAL (operands[1]);
1314 operands[1] = GEN_INT (0x7f);
1315 operands[2] = GEN_INT (val - 0x7f);
1319 operands[1] = GEN_INT (- 0x80);
1320 operands[2] = GEN_INT (val + 0x80);
1325 [(set (match_operand:SI 0 "d_operand")
1326 (plus:SI (match_operand:SI 1 "d_operand")
1327 (match_operand:SI 2 "const_int_operand")))]
1328 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1329 && REGNO (operands[0]) != REGNO (operands[1])
1330 && ((INTVAL (operands[2]) > 0x7
1331 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1332 || (INTVAL (operands[2]) < - 0x8
1333 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1334 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1335 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1337 HOST_WIDE_INT val = INTVAL (operands[2]);
1341 operands[2] = GEN_INT (0x7);
1342 operands[3] = GEN_INT (val - 0x7);
1346 operands[2] = GEN_INT (- 0x8);
1347 operands[3] = GEN_INT (val + 0x8);
1352 [(set (match_operand:DI 0 "d_operand")
1353 (plus:DI (match_dup 0)
1354 (match_operand:DI 1 "const_int_operand")))]
1355 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1356 && ((INTVAL (operands[1]) > 0xf
1357 && INTVAL (operands[1]) <= 0xf + 0xf)
1358 || (INTVAL (operands[1]) < - 0x10
1359 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1360 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1361 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1363 HOST_WIDE_INT val = INTVAL (operands[1]);
1367 operands[1] = GEN_INT (0xf);
1368 operands[2] = GEN_INT (val - 0xf);
1372 operands[1] = GEN_INT (- 0x10);
1373 operands[2] = GEN_INT (val + 0x10);
1378 [(set (match_operand:DI 0 "d_operand")
1379 (plus:DI (match_operand:DI 1 "d_operand")
1380 (match_operand:DI 2 "const_int_operand")))]
1381 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1382 && REGNO (operands[0]) != REGNO (operands[1])
1383 && ((INTVAL (operands[2]) > 0x7
1384 && INTVAL (operands[2]) <= 0x7 + 0xf)
1385 || (INTVAL (operands[2]) < - 0x8
1386 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1387 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1388 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1390 HOST_WIDE_INT val = INTVAL (operands[2]);
1394 operands[2] = GEN_INT (0x7);
1395 operands[3] = GEN_INT (val - 0x7);
1399 operands[2] = GEN_INT (- 0x8);
1400 operands[3] = GEN_INT (val + 0x8);
1404 (define_insn "*addsi3_extended"
1405 [(set (match_operand:DI 0 "register_operand" "=d,d")
1407 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1408 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1409 "TARGET_64BIT && !TARGET_MIPS16"
1413 [(set_attr "alu_type" "add")
1414 (set_attr "mode" "SI")])
1416 ;; Split this insn so that the addiu splitters can have a crack at it.
1417 ;; Use a conservative length estimate until the split.
1418 (define_insn_and_split "*addsi3_extended_mips16"
1419 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1421 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1422 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1423 "TARGET_64BIT && TARGET_MIPS16"
1425 "&& reload_completed"
1426 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1427 { operands[3] = gen_lowpart (SImode, operands[0]); }
1428 [(set_attr "alu_type" "add")
1429 (set_attr "mode" "SI")
1430 (set_attr "extended_mips16" "yes")])
1432 ;; Combiner patterns for unsigned byte-add.
1434 (define_insn "*baddu_si_eb"
1435 [(set (match_operand:SI 0 "register_operand" "=d")
1438 (plus:SI (match_operand:SI 1 "register_operand" "d")
1439 (match_operand:SI 2 "register_operand" "d")) 3)))]
1440 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1442 [(set_attr "alu_type" "add")])
1444 (define_insn "*baddu_si_el"
1445 [(set (match_operand:SI 0 "register_operand" "=d")
1448 (plus:SI (match_operand:SI 1 "register_operand" "d")
1449 (match_operand:SI 2 "register_operand" "d")) 0)))]
1450 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1452 [(set_attr "alu_type" "add")])
1454 (define_insn "*baddu_di<mode>"
1455 [(set (match_operand:GPR 0 "register_operand" "=d")
1458 (plus:DI (match_operand:DI 1 "register_operand" "d")
1459 (match_operand:DI 2 "register_operand" "d")))))]
1460 "ISA_HAS_BADDU && TARGET_64BIT"
1462 [(set_attr "alu_type" "add")])
1465 ;; ....................
1469 ;; ....................
1472 (define_insn "sub<mode>3"
1473 [(set (match_operand:ANYF 0 "register_operand" "=f")
1474 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1475 (match_operand:ANYF 2 "register_operand" "f")))]
1477 "sub.<fmt>\t%0,%1,%2"
1478 [(set_attr "type" "fadd")
1479 (set_attr "mode" "<UNITMODE>")])
1481 (define_insn "sub<mode>3"
1482 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
1483 (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d")
1484 (match_operand:GPR 2 "register_operand" "!u,d")))]
1487 [(set_attr "alu_type" "sub")
1488 (set_attr "compression" "micromips32,*")
1489 (set_attr "mode" "<MODE>")])
1491 (define_insn "*subsi3_extended"
1492 [(set (match_operand:DI 0 "register_operand" "=d")
1494 (minus:SI (match_operand:SI 1 "register_operand" "d")
1495 (match_operand:SI 2 "register_operand" "d"))))]
1498 [(set_attr "alu_type" "sub")
1499 (set_attr "mode" "DI")])
1502 ;; ....................
1506 ;; ....................
1509 (define_expand "mul<mode>3"
1510 [(set (match_operand:SCALARF 0 "register_operand")
1511 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1512 (match_operand:SCALARF 2 "register_operand")))]
1516 (define_insn "*mul<mode>3"
1517 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1518 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1519 (match_operand:SCALARF 2 "register_operand" "f")))]
1520 "!TARGET_4300_MUL_FIX"
1521 "mul.<fmt>\t%0,%1,%2"
1522 [(set_attr "type" "fmul")
1523 (set_attr "mode" "<MODE>")])
1525 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1526 ;; operands may corrupt immediately following multiplies. This is a
1527 ;; simple fix to insert NOPs.
1529 (define_insn "*mul<mode>3_r4300"
1530 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1531 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1532 (match_operand:SCALARF 2 "register_operand" "f")))]
1533 "TARGET_4300_MUL_FIX"
1534 "mul.<fmt>\t%0,%1,%2\;nop"
1535 [(set_attr "type" "fmul")
1536 (set_attr "mode" "<MODE>")
1537 (set_attr "insn_count" "2")])
1539 (define_insn "mulv2sf3"
1540 [(set (match_operand:V2SF 0 "register_operand" "=f")
1541 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1542 (match_operand:V2SF 2 "register_operand" "f")))]
1543 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1545 [(set_attr "type" "fmul")
1546 (set_attr "mode" "SF")])
1548 ;; The original R4000 has a cpu bug. If a double-word or a variable
1549 ;; shift executes while an integer multiplication is in progress, the
1550 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1551 ;; with the mult on the R4000.
1553 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1554 ;; (also valid for MIPS R4000MC processors):
1556 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1557 ;; this errata description.
1558 ;; The following code sequence causes the R4000 to incorrectly
1559 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1560 ;; instruction. If the dsra32 instruction is executed during an
1561 ;; integer multiply, the dsra32 will only shift by the amount in
1562 ;; specified in the instruction rather than the amount plus 32
1564 ;; instruction 1: mult rs,rt integer multiply
1565 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1566 ;; right arithmetic + 32
1567 ;; Workaround: A dsra32 instruction placed after an integer
1568 ;; multiply should not be one of the 11 instructions after the
1569 ;; multiply instruction."
1573 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1574 ;; the following description.
1575 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1576 ;; 64-bit versions) may produce incorrect results under the
1577 ;; following conditions:
1578 ;; 1) An integer multiply is currently executing
1579 ;; 2) These types of shift instructions are executed immediately
1580 ;; following an integer divide instruction.
1582 ;; 1) Make sure no integer multiply is running wihen these
1583 ;; instruction are executed. If this cannot be predicted at
1584 ;; compile time, then insert a "mfhi" to R0 instruction
1585 ;; immediately after the integer multiply instruction. This
1586 ;; will cause the integer multiply to complete before the shift
1588 ;; 2) Separate integer divide and these two classes of shift
1589 ;; instructions by another instruction or a noop."
1591 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1594 (define_expand "mul<mode>3"
1595 [(set (match_operand:GPR 0 "register_operand")
1596 (mult:GPR (match_operand:GPR 1 "register_operand")
1597 (match_operand:GPR 2 "register_operand")))]
1598 "ISA_HAS_<D>MULT || ISA_HAS_R6<D>MUL"
1602 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>MUL)
1603 emit_insn (gen_mul<mode>3_mul3_nohilo (operands[0], operands[1],
1605 else if (ISA_HAS_<D>MUL3)
1606 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1607 else if (TARGET_MIPS16)
1609 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
1610 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2]));
1611 emit_move_insn (operands[0], lo);
1613 else if (TARGET_FIX_R4000)
1614 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1617 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1621 (define_insn "mul<mode>3_mul3_nohilo"
1622 [(set (match_operand:GPR 0 "register_operand" "=d")
1623 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1624 (match_operand:GPR 2 "register_operand" "d")))]
1625 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>MUL"
1627 if (TARGET_LOONGSON_2EF)
1628 return "<d>multu.g\t%0,%1,%2";
1629 else if (TARGET_LOONGSON_EXT)
1630 return "gs<d>multu\t%0,%1,%2";
1632 return "<d>mul\t%0,%1,%2";
1634 [(set_attr "type" "imul3nc")
1635 (set_attr "mode" "<MODE>")])
1637 (define_insn "mul<mode>3_mul3"
1638 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1639 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1640 (match_operand:GPR 2 "register_operand" "d,d")))
1641 (clobber (match_scratch:GPR 3 "=l,X"))]
1644 if (which_alternative == 1)
1645 return "<d>mult\t%1,%2";
1646 if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900))
1647 return "mult\t%0,%1,%2";
1648 return "<d>mul\t%0,%1,%2";
1650 [(set_attr "type" "imul3,imul")
1651 (set_attr "mode" "<MODE>")])
1653 ;; If a register gets allocated to LO, and we spill to memory, the reload
1654 ;; will include a move from LO to a GPR. Merge it into the multiplication
1655 ;; if it can set the GPR directly.
1658 ;; Operand 1: GPR (1st multiplication operand)
1659 ;; Operand 2: GPR (2nd multiplication operand)
1660 ;; Operand 3: GPR (destination)
1663 [(set (match_operand:SI 0 "lo_operand")
1664 (mult:SI (match_operand:SI 1 "d_operand")
1665 (match_operand:SI 2 "d_operand")))
1666 (clobber (scratch:SI))])
1667 (set (match_operand:SI 3 "d_operand")
1669 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1672 (mult:SI (match_dup 1)
1674 (clobber (match_dup 0))])])
1676 (define_insn "mul<mode>3_internal"
1677 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
1678 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1679 (match_operand:GPR 2 "register_operand" "d")))]
1680 "ISA_HAS_<D>MULT && !TARGET_FIX_R4000"
1682 [(set_attr "type" "imul")
1683 (set_attr "mode" "<MODE>")])
1685 (define_insn "mul<mode>3_r4000"
1686 [(set (match_operand:GPR 0 "register_operand" "=d")
1687 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1688 (match_operand:GPR 2 "register_operand" "d")))
1689 (clobber (match_scratch:GPR 3 "=l"))]
1690 "ISA_HAS_<D>MULT && TARGET_FIX_R4000"
1691 "<d>mult\t%1,%2\;mflo\t%0"
1692 [(set_attr "type" "imul")
1693 (set_attr "mode" "<MODE>")
1694 (set_attr "insn_count" "2")])
1696 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1697 ;; of "mult; mflo". They have the same latency, but the first form gives
1698 ;; us an extra cycle to compute the operands.
1701 ;; Operand 1: GPR (1st multiplication operand)
1702 ;; Operand 2: GPR (2nd multiplication operand)
1703 ;; Operand 3: GPR (destination)
1705 [(set (match_operand:SI 0 "lo_operand")
1706 (mult:SI (match_operand:SI 1 "d_operand")
1707 (match_operand:SI 2 "d_operand")))
1708 (set (match_operand:SI 3 "d_operand")
1710 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1715 (plus:SI (mult:SI (match_dup 1)
1719 (plus:SI (mult:SI (match_dup 1)
1723 ;; Multiply-accumulate patterns
1725 ;; This pattern is first matched by combine, which tries to use the
1726 ;; pattern wherever it can. We don't know until later whether it
1727 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1728 ;; so we need to keep both options open.
1730 ;; The second alternative has a "?" marker because it is generally
1731 ;; one instruction more costly than the first alternative. This "?"
1732 ;; marker is enough to convey the relative costs to the register
1735 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1736 ;; reloads of the other operands, even though operands 4 and 5 need no
1737 ;; copy instructions. Reload therefore thinks that the second alternative
1738 ;; is two reloads more costly than the first. We add "*?*?" to the first
1739 ;; alternative as a counterweight.
1741 ;; LRA simulates reload but the cost of reloading scratches is lower
1742 ;; than of the classic reload. For the time being, removing the counterweight
1743 ;; for LRA is more profitable.
1744 (define_insn "*mul_acc_si"
1745 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?")
1746 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1747 (match_operand:SI 2 "register_operand" "d,d,d"))
1748 (match_operand:SI 3 "register_operand" "0,0,d")))
1749 (clobber (match_scratch:SI 4 "=X,X,l"))
1750 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1751 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1756 [(set_attr "type" "imadd")
1757 (set_attr "accum_in" "3")
1758 (set_attr "mode" "SI")
1759 (set_attr "insn_count" "1,1,2")
1760 (set (attr "enabled")
1761 (cond [(and (eq_attr "alternative" "0")
1762 (match_test "!mips_lra_flag"))
1763 (const_string "yes")
1764 (and (eq_attr "alternative" "1")
1765 (match_test "mips_lra_flag"))
1766 (const_string "yes")
1767 (eq_attr "alternative" "2")
1768 (const_string "yes")]
1769 (const_string "no")))])
1771 ;; The same idea applies here. The middle alternative needs one less
1772 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1773 (define_insn "*mul_acc_si_r3900"
1774 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d*?,d?")
1775 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
1776 (match_operand:SI 2 "register_operand" "d,d,d,d"))
1777 (match_operand:SI 3 "register_operand" "0,0,l,d")))
1778 (clobber (match_scratch:SI 4 "=X,X,3,l"))
1779 (clobber (match_scratch:SI 5 "=X,X,X,&d"))]
1780 "TARGET_MIPS3900 && !TARGET_MIPS16"
1786 [(set_attr "type" "imadd")
1787 (set_attr "accum_in" "3")
1788 (set_attr "mode" "SI")
1789 (set_attr "insn_count" "1,1,1,2")
1790 (set (attr "enabled")
1791 (cond [(and (eq_attr "alternative" "0")
1792 (match_test "!mips_lra_flag"))
1793 (const_string "yes")
1794 (and (eq_attr "alternative" "1")
1795 (match_test "mips_lra_flag"))
1796 (const_string "yes")
1797 (eq_attr "alternative" "2,3")
1798 (const_string "yes")]
1799 (const_string "no")))])
1801 ;; Split *mul_acc_si if both the source and destination accumulator
1804 [(set (match_operand:SI 0 "d_operand")
1805 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1806 (match_operand:SI 2 "d_operand"))
1807 (match_operand:SI 3 "d_operand")))
1808 (clobber (match_operand:SI 4 "lo_operand"))
1809 (clobber (match_operand:SI 5 "d_operand"))]
1811 [(parallel [(set (match_dup 5)
1812 (mult:SI (match_dup 1) (match_dup 2)))
1813 (clobber (match_dup 4))])
1814 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1817 (define_insn "*macc"
1818 [(set (match_operand:SI 0 "register_operand" "=l,d")
1819 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1820 (match_operand:SI 2 "register_operand" "d,d"))
1821 (match_operand:SI 3 "register_operand" "0,l")))
1822 (clobber (match_scratch:SI 4 "=X,3"))]
1825 if (which_alternative == 1)
1826 return "macc\t%0,%1,%2";
1827 else if (TARGET_MIPS5500)
1828 return "madd\t%1,%2";
1830 /* The VR4130 assumes that there is a two-cycle latency between a macc
1831 that "writes" to $0 and an instruction that reads from it. We avoid
1832 this by assigning to $1 instead. */
1833 return "%[macc\t%@,%1,%2%]";
1835 [(set_attr "type" "imadd")
1836 (set_attr "accum_in" "3")
1837 (set_attr "mode" "SI")])
1839 (define_insn "*msac"
1840 [(set (match_operand:SI 0 "register_operand" "=l,d")
1841 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1842 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1843 (match_operand:SI 3 "register_operand" "d,d"))))
1844 (clobber (match_scratch:SI 4 "=X,1"))]
1847 if (which_alternative == 1)
1848 return "msac\t%0,%2,%3";
1849 else if (TARGET_MIPS5500)
1850 return "msub\t%2,%3";
1852 return "msac\t$0,%2,%3";
1854 [(set_attr "type" "imadd")
1855 (set_attr "accum_in" "1")
1856 (set_attr "mode" "SI")])
1858 ;; An msac-like instruction implemented using negation and a macc.
1859 (define_insn_and_split "*msac_using_macc"
1860 [(set (match_operand:SI 0 "register_operand" "=l,d")
1861 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1862 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1863 (match_operand:SI 3 "register_operand" "d,d"))))
1864 (clobber (match_scratch:SI 4 "=X,1"))
1865 (clobber (match_scratch:SI 5 "=d,d"))]
1866 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1868 "&& reload_completed"
1870 (neg:SI (match_dup 3)))
1873 (plus:SI (mult:SI (match_dup 2)
1876 (clobber (match_dup 4))])]
1878 [(set_attr "type" "imadd")
1879 (set_attr "accum_in" "1")
1880 (set_attr "insn_count" "2")])
1882 ;; Patterns generated by the define_peephole2 below.
1884 (define_insn "*macc2"
1885 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1886 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1887 (match_operand:SI 2 "register_operand" "d"))
1889 (set (match_operand:SI 3 "register_operand" "=d")
1890 (plus:SI (mult:SI (match_dup 1)
1893 "ISA_HAS_MACC && reload_completed"
1895 [(set_attr "type" "imadd")
1896 (set_attr "accum_in" "0")
1897 (set_attr "mode" "SI")])
1899 (define_insn "*msac2"
1900 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1901 (minus:SI (match_dup 0)
1902 (mult:SI (match_operand:SI 1 "register_operand" "d")
1903 (match_operand:SI 2 "register_operand" "d"))))
1904 (set (match_operand:SI 3 "register_operand" "=d")
1905 (minus:SI (match_dup 0)
1906 (mult:SI (match_dup 1)
1908 "ISA_HAS_MSAC && reload_completed"
1910 [(set_attr "type" "imadd")
1911 (set_attr "accum_in" "0")
1912 (set_attr "mode" "SI")])
1914 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1918 ;; Operand 1: macc/msac
1919 ;; Operand 2: GPR (destination)
1922 [(set (match_operand:SI 0 "lo_operand")
1923 (match_operand:SI 1 "macc_msac_operand"))
1924 (clobber (scratch:SI))])
1925 (set (match_operand:SI 2 "d_operand")
1928 [(parallel [(set (match_dup 0)
1933 ;; When we have a three-address multiplication instruction, it should
1934 ;; be faster to do a separate multiply and add, rather than moving
1935 ;; something into LO in order to use a macc instruction.
1937 ;; This peephole needs a scratch register to cater for the case when one
1938 ;; of the multiplication operands is the same as the destination.
1940 ;; Operand 0: GPR (scratch)
1942 ;; Operand 2: GPR (addend)
1943 ;; Operand 3: GPR (destination)
1944 ;; Operand 4: macc/msac
1945 ;; Operand 5: new multiplication
1946 ;; Operand 6: new addition/subtraction
1948 [(match_scratch:SI 0 "d")
1949 (set (match_operand:SI 1 "lo_operand")
1950 (match_operand:SI 2 "d_operand"))
1953 [(set (match_operand:SI 3 "d_operand")
1954 (match_operand:SI 4 "macc_msac_operand"))
1955 (clobber (match_dup 1))])]
1956 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1957 [(parallel [(set (match_dup 0)
1959 (clobber (match_dup 1))])
1963 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1964 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1965 operands[2], operands[0]);
1968 ;; Same as above, except LO is the initial target of the macc.
1970 ;; Operand 0: GPR (scratch)
1972 ;; Operand 2: GPR (addend)
1973 ;; Operand 3: macc/msac
1974 ;; Operand 4: GPR (destination)
1975 ;; Operand 5: new multiplication
1976 ;; Operand 6: new addition/subtraction
1978 [(match_scratch:SI 0 "d")
1979 (set (match_operand:SI 1 "lo_operand")
1980 (match_operand:SI 2 "d_operand"))
1984 (match_operand:SI 3 "macc_msac_operand"))
1985 (clobber (scratch:SI))])
1987 (set (match_operand:SI 4 "d_operand")
1989 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1990 [(parallel [(set (match_dup 0)
1992 (clobber (match_dup 1))])
1996 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1997 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1998 operands[2], operands[0]);
2001 ;; See the comment above *mul_add_si for details.
2002 (define_insn "*mul_sub_si"
2003 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?")
2004 (minus:SI (match_operand:SI 1 "register_operand" "0,0,d")
2005 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
2006 (match_operand:SI 3 "register_operand" "d,d,d"))))
2007 (clobber (match_scratch:SI 4 "=X,X,l"))
2008 (clobber (match_scratch:SI 5 "=X,X,&d"))]
2009 "GENERATE_MADD_MSUB"
2014 [(set_attr "type" "imadd")
2015 (set_attr "accum_in" "1")
2016 (set_attr "mode" "SI")
2017 (set_attr "insn_count" "1,1,2")
2018 (set (attr "enabled")
2019 (cond [(and (eq_attr "alternative" "0")
2020 (match_test "!mips_lra_flag"))
2021 (const_string "yes")
2022 (and (eq_attr "alternative" "1")
2023 (match_test "mips_lra_flag"))
2024 (const_string "yes")
2025 (eq_attr "alternative" "2")
2026 (const_string "yes")]
2027 (const_string "no")))])
2029 ;; Split *mul_sub_si if both the source and destination accumulator
2032 [(set (match_operand:SI 0 "d_operand")
2033 (minus:SI (match_operand:SI 1 "d_operand")
2034 (mult:SI (match_operand:SI 2 "d_operand")
2035 (match_operand:SI 3 "d_operand"))))
2036 (clobber (match_operand:SI 4 "lo_operand"))
2037 (clobber (match_operand:SI 5 "d_operand"))]
2039 [(parallel [(set (match_dup 5)
2040 (mult:SI (match_dup 2) (match_dup 3)))
2041 (clobber (match_dup 4))])
2042 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
2045 (define_insn "*muls"
2046 [(set (match_operand:SI 0 "register_operand" "=l,d")
2047 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
2048 (match_operand:SI 2 "register_operand" "d,d"))))
2049 (clobber (match_scratch:SI 3 "=X,l"))]
2054 [(set_attr "type" "imul,imul3")
2055 (set_attr "mode" "SI")])
2057 (define_expand "<u>mulsidi3"
2058 [(set (match_operand:DI 0 "register_operand")
2059 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2060 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2061 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
2063 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
2064 emit_insn (fn (operands[0], operands[1], operands[2]));
2068 (define_expand "<u>mulsidi3_32bit_r6"
2069 [(set (match_operand:DI 0 "register_operand")
2070 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2071 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2072 "!TARGET_64BIT && ISA_HAS_R6MUL"
2074 rtx dest = gen_reg_rtx (DImode);
2075 rtx low = mips_subword (dest, 0);
2076 rtx high = mips_subword (dest, 1);
2078 emit_insn (gen_mulsi3_mul3_nohilo (low, operands[1], operands[2]));
2079 emit_insn (gen_<su>mulsi3_highpart_r6 (high, operands[1], operands[2]));
2081 emit_move_insn (mips_subword (operands[0], 0), low);
2082 emit_move_insn (mips_subword (operands[0], 1), high);
2086 (define_expand "<u>mulsidi3_32bit_mips16"
2087 [(set (match_operand:DI 0 "register_operand")
2088 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2089 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2090 "!TARGET_64BIT && TARGET_MIPS16"
2094 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2095 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2096 emit_move_insn (operands[0], hilo);
2100 ;; As well as being named patterns, these instructions are used by the
2101 ;; __builtin_mips_mult<u>() functions. We must always make those functions
2102 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2103 (define_insn "<u>mulsidi3_32bit"
2104 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2105 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2106 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
2107 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP) && ISA_HAS_MULT"
2109 if (ISA_HAS_DSP_MULT)
2110 return "mult<u>\t%q0,%1,%2";
2112 return "mult<u>\t%1,%2";
2114 [(set_attr "type" "imul")
2115 (set_attr "mode" "SI")])
2117 (define_insn "<u>mulsidi3_32bit_r4000"
2118 [(set (match_operand:DI 0 "register_operand" "=d")
2119 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2120 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2121 (clobber (match_scratch:DI 3 "=x"))]
2122 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP && ISA_HAS_MULT"
2123 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2124 [(set_attr "type" "imul")
2125 (set_attr "mode" "SI")
2126 (set_attr "insn_count" "3")])
2128 (define_insn_and_split "<u>mulsidi3_64bit"
2129 [(set (match_operand:DI 0 "register_operand" "=d")
2130 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2131 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2132 (clobber (match_scratch:TI 3 "=x"))
2133 (clobber (match_scratch:DI 4 "=d"))]
2134 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3
2135 && !TARGET_MIPS16 && ISA_HAS_MULT"
2137 "&& reload_completed"
2140 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
2141 operands[2], operands[4]));
2144 [(set_attr "type" "imul")
2145 (set_attr "mode" "SI")
2146 (set (attr "insn_count")
2147 (if_then_else (match_test "ISA_HAS_EXT_INS")
2151 (define_expand "<u>mulsidi3_64bit_mips16"
2152 [(set (match_operand:DI 0 "register_operand")
2153 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2154 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2155 "TARGET_64BIT && TARGET_MIPS16"
2157 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
2158 operands[2], gen_reg_rtx (DImode)));
2162 (define_expand "<u>mulsidi3_64bit_split"
2163 [(set (match_operand:DI 0 "register_operand")
2164 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2165 (any_extend:DI (match_operand:SI 2 "register_operand"))))
2166 (clobber (match_operand:DI 3 "register_operand"))]
2171 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2172 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2174 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM));
2175 emit_insn (gen_mfhidi_ti (operands[3], hilo));
2177 if (ISA_HAS_EXT_INS)
2178 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32),
2182 /* Zero-extend the low part. */
2183 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32));
2184 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32));
2186 /* Shift the high part into place. */
2187 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32));
2189 /* OR the two halves together. */
2190 mips_emit_binary (IOR, operands[0], operands[0], operands[3]);
2195 (define_insn "<u>mulsidi3_64bit_hilo"
2196 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2199 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2200 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
2202 "TARGET_64BIT && !TARGET_FIX_R4000"
2204 [(set_attr "type" "imul")
2205 (set_attr "mode" "SI")])
2207 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
2208 (define_insn "mulsidi3_64bit_dmul"
2209 [(set (match_operand:DI 0 "register_operand" "=d")
2210 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2211 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2212 (clobber (match_scratch:DI 3 "=l"))]
2215 [(set_attr "type" "imul3")
2216 (set_attr "mode" "DI")])
2218 (define_insn "mulsidi3_64bit_r6dmul"
2219 [(set (match_operand:DI 0 "register_operand" "=d")
2220 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2221 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
2224 [(set_attr "type" "imul3nc")
2225 (set_attr "mode" "DI")])
2227 ;; Widening multiply with negation.
2228 (define_insn "*muls<u>_di"
2229 [(set (match_operand:DI 0 "muldiv_target_operand" "=x")
2232 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2233 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2234 "!TARGET_64BIT && ISA_HAS_MULS"
2236 [(set_attr "type" "imul")
2237 (set_attr "mode" "SI")])
2239 ;; As well as being named patterns, these instructions are used by the
2240 ;; __builtin_mips_msub<u>() functions. We must always make those functions
2241 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2243 ;; This leads to a slight inconsistency. We honor any tuning overrides
2244 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
2245 ;; even if !ISA_HAS_DSP_MULT.
2246 (define_insn "<u>msubsidi4"
2247 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2249 (match_operand:DI 3 "muldiv_target_operand" "0")
2251 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2252 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2253 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
2255 if (ISA_HAS_DSP_MULT)
2256 return "msub<u>\t%q0,%1,%2";
2257 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
2258 return "msub<u>\t%1,%2";
2260 return "msac<u>\t$0,%1,%2";
2262 [(set_attr "type" "imadd")
2263 (set_attr "accum_in" "3")
2264 (set_attr "mode" "SI")])
2266 ;; _highpart patterns
2268 (define_expand "<su>mulsi3_highpart"
2269 [(set (match_operand:SI 0 "register_operand")
2272 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2273 (any_extend:DI (match_operand:SI 2 "register_operand")))
2278 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
2281 else if (TARGET_MIPS16)
2282 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2284 else if (ISA_HAS_R6MUL)
2285 emit_insn (gen_<su>mulsi3_highpart_r6 (operands[0], operands[1],
2288 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
2293 (define_insn "<su>mulsi3_highpart_r6"
2294 [(set (match_operand:SI 0 "register_operand" "=d")
2297 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2298 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2302 [(set_attr "type" "imul3nc")
2303 (set_attr "mode" "SI")])
2305 (define_insn_and_split "<su>mulsi3_highpart_internal"
2306 [(set (match_operand:SI 0 "register_operand" "=d")
2309 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2310 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2312 (clobber (match_scratch:SI 3 "=l"))]
2313 "ISA_HAS_MULT && !ISA_HAS_MULHI && !TARGET_MIPS16"
2314 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2315 "&& reload_completed && !TARGET_FIX_R4000"
2318 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2322 [(set_attr "type" "imul")
2323 (set_attr "mode" "SI")
2324 (set_attr "insn_count" "2")])
2326 (define_expand "<su>mulsi3_highpart_split"
2327 [(set (match_operand:SI 0 "register_operand")
2330 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2331 (any_extend:DI (match_operand:SI 2 "register_operand")))
2339 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2340 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2341 emit_insn (gen_mfhisi_ti (operands[0], hilo));
2345 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2346 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2347 emit_insn (gen_mfhisi_di (operands[0], hilo));
2352 (define_insn "<su>mulsi3_highpart_mulhi_internal"
2353 [(set (match_operand:SI 0 "register_operand" "=d")
2357 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2358 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2360 (clobber (match_scratch:SI 3 "=l"))]
2362 "mulhi<u>\t%0,%1,%2"
2363 [(set_attr "type" "imul3")
2364 (set_attr "mode" "SI")])
2366 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
2367 [(set (match_operand:SI 0 "register_operand" "=d")
2372 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2373 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2375 (clobber (match_scratch:SI 3 "=l"))]
2377 "mulshi<u>\t%0,%1,%2"
2378 [(set_attr "type" "imul3")
2379 (set_attr "mode" "SI")])
2381 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
2382 ;; errata MD(0), which says that dmultu does not always produce the
2384 (define_expand "<su>muldi3_highpart"
2385 [(set (match_operand:DI 0 "register_operand")
2388 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2389 (any_extend:TI (match_operand:DI 2 "register_operand")))
2393 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120))"
2396 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2398 else if (ISA_HAS_R6DMUL)
2399 emit_insn (gen_<su>muldi3_highpart_r6 (operands[0], operands[1],
2402 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1],
2407 (define_insn "<su>muldi3_highpart_r6"
2408 [(set (match_operand:DI 0 "register_operand" "=d")
2411 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2412 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2416 [(set_attr "type" "imul3nc")
2417 (set_attr "mode" "DI")])
2419 (define_insn_and_split "<su>muldi3_highpart_internal"
2420 [(set (match_operand:DI 0 "register_operand" "=d")
2423 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2424 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2426 (clobber (match_scratch:DI 3 "=l"))]
2429 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2430 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2431 "&& reload_completed && !TARGET_FIX_R4000"
2434 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2438 [(set_attr "type" "imul")
2439 (set_attr "mode" "DI")
2440 (set_attr "insn_count" "2")])
2442 (define_expand "<su>muldi3_highpart_split"
2443 [(set (match_operand:DI 0 "register_operand")
2446 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2447 (any_extend:TI (match_operand:DI 2 "register_operand")))
2453 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2454 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2455 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2459 (define_expand "<u>mulditi3"
2460 [(set (match_operand:TI 0 "register_operand")
2461 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2462 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2463 "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2469 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2470 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2471 emit_move_insn (operands[0], hilo);
2473 else if (TARGET_FIX_R4000)
2474 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2476 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2481 (define_insn "<u>mulditi3_internal"
2482 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2483 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2484 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2486 && !TARGET_FIX_R4000
2487 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2489 [(set_attr "type" "imul")
2490 (set_attr "mode" "DI")])
2492 (define_insn "<u>mulditi3_r4000"
2493 [(set (match_operand:TI 0 "register_operand" "=d")
2494 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2495 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2496 (clobber (match_scratch:TI 3 "=x"))]
2499 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2500 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2501 [(set_attr "type" "imul")
2502 (set_attr "mode" "DI")
2503 (set_attr "insn_count" "3")])
2505 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2506 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2508 (define_insn "madsi"
2509 [(set (match_operand:SI 0 "register_operand" "+l")
2510 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2511 (match_operand:SI 2 "register_operand" "d"))
2515 [(set_attr "type" "imadd")
2516 (set_attr "accum_in" "0")
2517 (set_attr "mode" "SI")])
2519 ;; See the comment above <u>msubsidi4 for the relationship between
2520 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2521 (define_insn "<u>maddsidi4"
2522 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2524 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2525 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2526 (match_operand:DI 3 "muldiv_target_operand" "0")))]
2527 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2531 return "mad<u>\t%1,%2";
2532 else if (ISA_HAS_DSP_MULT)
2533 return "madd<u>\t%q0,%1,%2";
2534 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2535 return "madd<u>\t%1,%2";
2537 /* See comment in *macc. */
2538 return "%[macc<u>\t%@,%1,%2%]";
2540 [(set_attr "type" "imadd")
2541 (set_attr "accum_in" "3")
2542 (set_attr "mode" "SI")])
2544 ;; Floating point multiply accumulate instructions.
2546 (define_expand "fma<mode>4"
2547 [(set (match_operand:ANYF 0 "register_operand")
2548 (fma:ANYF (match_operand:ANYF 1 "register_operand")
2549 (match_operand:ANYF 2 "register_operand")
2550 (match_operand:ANYF 3 "register_operand")))]
2551 "ISA_HAS_FUSED_MADDF || ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4")
2553 (define_insn "*fma<mode>4_madd3"
2554 [(set (match_operand:ANYF 0 "register_operand" "=f")
2555 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2556 (match_operand:ANYF 2 "register_operand" "f")
2557 (match_operand:ANYF 3 "register_operand" "0")))]
2558 "ISA_HAS_FUSED_MADD3"
2559 "madd.<fmt>\t%0,%1,%2"
2560 [(set_attr "type" "fmadd")
2561 (set_attr "mode" "<UNITMODE>")])
2563 (define_insn "*fma<mode>4_madd4"
2564 [(set (match_operand:ANYF 0 "register_operand" "=f")
2565 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2566 (match_operand:ANYF 2 "register_operand" "f")
2567 (match_operand:ANYF 3 "register_operand" "f")))]
2568 "ISA_HAS_FUSED_MADD4"
2569 "madd.<fmt>\t%0,%3,%1,%2"
2570 [(set_attr "type" "fmadd")
2571 (set_attr "mode" "<UNITMODE>")])
2573 (define_insn "*fma<mode>4_maddf"
2574 [(set (match_operand:ANYF 0 "register_operand" "=f")
2575 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2576 (match_operand:ANYF 2 "register_operand" "f")
2577 (match_operand:ANYF 3 "register_operand" "0")))]
2578 "ISA_HAS_FUSED_MADDF"
2579 "maddf.<fmt>\t%0,%1,%2"
2580 [(set_attr "type" "fmadd")
2581 (set_attr "mode" "<UNITMODE>")])
2583 ;; The fms, fnma, and fnms instructions can be used even when HONOR_NANS
2584 ;; is true because while IEEE 754-2008 requires the negate operation to
2585 ;; negate the sign of a NAN and the MIPS neg instruction does not do this,
2586 ;; the fma part of the instruction has no requirement on how the sign of
2587 ;; a NAN is handled and so the final sign bit of the entire operation is
2590 (define_expand "fms<mode>4"
2591 [(set (match_operand:ANYF 0 "register_operand")
2592 (fma:ANYF (match_operand:ANYF 1 "register_operand")
2593 (match_operand:ANYF 2 "register_operand")
2594 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))]
2595 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)")
2597 (define_insn "*fms<mode>4_msub3"
2598 [(set (match_operand:ANYF 0 "register_operand" "=f")
2599 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2600 (match_operand:ANYF 2 "register_operand" "f")
2601 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))]
2602 "ISA_HAS_FUSED_MADD3"
2603 "msub.<fmt>\t%0,%1,%2"
2604 [(set_attr "type" "fmadd")
2605 (set_attr "mode" "<UNITMODE>")])
2607 (define_insn "*fms<mode>4_msub4"
2608 [(set (match_operand:ANYF 0 "register_operand" "=f")
2609 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2610 (match_operand:ANYF 2 "register_operand" "f")
2611 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))]
2612 "ISA_HAS_FUSED_MADD4"
2613 "msub.<fmt>\t%0,%3,%1,%2"
2614 [(set_attr "type" "fmadd")
2615 (set_attr "mode" "<UNITMODE>")])
2617 ;; fnma is defined in GCC as (fma (neg op1) op2 op3)
2618 ;; (-op1 * op2) + op3 ==> -(op1 * op2) + op3 ==> -((op1 * op2) - op3)
2619 ;; The mips nmsub instructions implement -((op1 * op2) - op3)
2620 ;; This transformation means we may return the wrong signed zero
2621 ;; so we check HONOR_SIGNED_ZEROS.
2623 (define_expand "fnma<mode>4"
2624 [(set (match_operand:ANYF 0 "register_operand")
2625 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand"))
2626 (match_operand:ANYF 2 "register_operand")
2627 (match_operand:ANYF 3 "register_operand")))]
2628 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)
2629 && !HONOR_SIGNED_ZEROS (<MODE>mode)")
2631 (define_insn "*fnma<mode>4_nmsub3"
2632 [(set (match_operand:ANYF 0 "register_operand" "=f")
2633 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2634 (match_operand:ANYF 2 "register_operand" "f")
2635 (match_operand:ANYF 3 "register_operand" "0")))]
2636 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2637 "nmsub.<fmt>\t%0,%1,%2"
2638 [(set_attr "type" "fmadd")
2639 (set_attr "mode" "<UNITMODE>")])
2641 (define_insn "*fnma<mode>4_nmsub4"
2642 [(set (match_operand:ANYF 0 "register_operand" "=f")
2643 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2644 (match_operand:ANYF 2 "register_operand" "f")
2645 (match_operand:ANYF 3 "register_operand" "f")))]
2646 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2647 "nmsub.<fmt>\t%0,%3,%1,%2"
2648 [(set_attr "type" "fmadd")
2649 (set_attr "mode" "<UNITMODE>")])
2651 ;; fnms is defined as: (fma (neg op1) op2 (neg op3))
2652 ;; ((-op1) * op2) - op3 ==> -(op1 * op2) - op3 ==> -((op1 * op2) + op3)
2653 ;; The mips nmadd instructions implement -((op1 * op2) + op3)
2654 ;; This transformation means we may return the wrong signed zero
2655 ;; so we check HONOR_SIGNED_ZEROS.
2657 (define_expand "fnms<mode>4"
2658 [(set (match_operand:ANYF 0 "register_operand")
2660 (neg:ANYF (match_operand:ANYF 1 "register_operand"))
2661 (match_operand:ANYF 2 "register_operand")
2662 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))]
2663 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)
2664 && !HONOR_SIGNED_ZEROS (<MODE>mode)")
2666 (define_insn "*fnms<mode>4_nmadd3"
2667 [(set (match_operand:ANYF 0 "register_operand" "=f")
2669 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2670 (match_operand:ANYF 2 "register_operand" "f")
2671 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))]
2672 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2673 "nmadd.<fmt>\t%0,%1,%2"
2674 [(set_attr "type" "fmadd")
2675 (set_attr "mode" "<UNITMODE>")])
2677 (define_insn "*fnms<mode>4_nmadd4"
2678 [(set (match_operand:ANYF 0 "register_operand" "=f")
2680 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2681 (match_operand:ANYF 2 "register_operand" "f")
2682 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))]
2683 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2684 "nmadd.<fmt>\t%0,%3,%1,%2"
2685 [(set_attr "type" "fmadd")
2686 (set_attr "mode" "<UNITMODE>")])
2688 ;; Non-fused Floating point multiply accumulate instructions.
2690 ;; These instructions are not fused and round in between the multiply
2691 ;; and the add (or subtract) so they are equivalent to the separate
2692 ;; multiply and add/sub instructions.
2694 (define_insn "*madd4<mode>"
2695 [(set (match_operand:ANYF 0 "register_operand" "=f")
2696 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2697 (match_operand:ANYF 2 "register_operand" "f"))
2698 (match_operand:ANYF 3 "register_operand" "f")))]
2699 "ISA_HAS_UNFUSED_MADD4"
2700 "madd.<fmt>\t%0,%3,%1,%2"
2701 [(set_attr "type" "fmadd")
2702 (set_attr "mode" "<UNITMODE>")])
2704 (define_insn "*msub4<mode>"
2705 [(set (match_operand:ANYF 0 "register_operand" "=f")
2706 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2707 (match_operand:ANYF 2 "register_operand" "f"))
2708 (match_operand:ANYF 3 "register_operand" "f")))]
2709 "ISA_HAS_UNFUSED_MADD4"
2710 "msub.<fmt>\t%0,%3,%1,%2"
2711 [(set_attr "type" "fmadd")
2712 (set_attr "mode" "<UNITMODE>")])
2714 ;; Like with the fused fms, fnma, and fnms instructions, these unfused
2715 ;; instructions can be used even if HONOR_NANS is set because while
2716 ;; IEEE 754-2008 requires the negate operation to negate the sign of a
2717 ;; NAN and the MIPS neg instruction does not do this, the multiply and
2718 ;; add (or subtract) part of the instruction has no requirement on how
2719 ;; the sign of a NAN is handled and so the final sign bit of the entire
2720 ;; operation is undefined.
2722 (define_insn "*nmadd4<mode>"
2723 [(set (match_operand:ANYF 0 "register_operand" "=f")
2724 (neg:ANYF (plus:ANYF
2725 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2726 (match_operand:ANYF 2 "register_operand" "f"))
2727 (match_operand:ANYF 3 "register_operand" "f"))))]
2728 "ISA_HAS_UNFUSED_MADD4"
2729 "nmadd.<fmt>\t%0,%3,%1,%2"
2730 [(set_attr "type" "fmadd")
2731 (set_attr "mode" "<UNITMODE>")])
2733 (define_insn "*nmsub4<mode>"
2734 [(set (match_operand:ANYF 0 "register_operand" "=f")
2735 (neg:ANYF (minus:ANYF
2736 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2737 (match_operand:ANYF 2 "register_operand" "f"))
2738 (match_operand:ANYF 3 "register_operand" "f"))))]
2739 "ISA_HAS_UNFUSED_MADD4"
2740 "nmsub.<fmt>\t%0,%3,%1,%2"
2741 [(set_attr "type" "fmadd")
2742 (set_attr "mode" "<UNITMODE>")])
2744 ;; Fast-math Non-fused Floating point multiply accumulate instructions.
2746 ;; These instructions are not fused but the expressions they match are
2747 ;; not exactly what the instruction implements in the sense that they
2748 ;; may not generate the properly signed zeros.
2750 ;; This instruction recognizes ((-op1) * op2) - op3 and generates an
2751 ;; nmadd which is really -((op1 * op2) + op3). They are equivalent
2752 ;; except for the sign bit when the result is zero or NaN.
2754 (define_insn "*nmadd4<mode>_fastmath"
2755 [(set (match_operand:ANYF 0 "register_operand" "=f")
2757 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2758 (match_operand:ANYF 2 "register_operand" "f"))
2759 (match_operand:ANYF 3 "register_operand" "f")))]
2760 "ISA_HAS_UNFUSED_MADD4
2761 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2762 "nmadd.<fmt>\t%0,%3,%1,%2"
2763 [(set_attr "type" "fmadd")
2764 (set_attr "mode" "<UNITMODE>")])
2766 ;; This instruction recognizes (op1 - (op2 * op3) and generates an
2767 ;; nmsub which is really -((op2 * op3) - op1). They are equivalent
2768 ;; except for the sign bit when the result is zero or NaN.
2770 (define_insn "*nmsub4<mode>_fastmath"
2771 [(set (match_operand:ANYF 0 "register_operand" "=f")
2773 (match_operand:ANYF 1 "register_operand" "f")
2774 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2775 (match_operand:ANYF 3 "register_operand" "f"))))]
2776 "ISA_HAS_UNFUSED_MADD4
2777 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2778 "nmsub.<fmt>\t%0,%1,%2,%3"
2779 [(set_attr "type" "fmadd")
2780 (set_attr "mode" "<UNITMODE>")])
2783 ;; ....................
2785 ;; DIVISION and REMAINDER
2787 ;; ....................
2790 (define_expand "div<mode>3"
2791 [(set (match_operand:ANYF 0 "register_operand")
2792 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2793 (match_operand:ANYF 2 "register_operand")))]
2794 "<divide_condition>"
2796 if (const_1_operand (operands[1], <MODE>mode))
2797 if (!(ISA_HAS_FP_RECIP_RSQRT (<MODE>mode)
2798 && flag_unsafe_math_optimizations))
2799 operands[1] = force_reg (<MODE>mode, operands[1]);
2802 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2804 ;; If an mfc1 or dmfc1 happens to access the floating point register
2805 ;; file at the same time a long latency operation (div, sqrt, recip,
2806 ;; sqrt) iterates an intermediate result back through the floating
2807 ;; point register file bypass, then instead returning the correct
2808 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2809 ;; result of the long latency operation.
2811 ;; The workaround is to insert an unconditional 'mov' from/to the
2812 ;; long latency op destination register.
2814 (define_insn "*div<mode>3"
2815 [(set (match_operand:ANYF 0 "register_operand" "=f")
2816 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2817 (match_operand:ANYF 2 "register_operand" "f")))]
2818 "<divide_condition>"
2821 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2823 return "div.<fmt>\t%0,%1,%2";
2825 [(set_attr "type" "fdiv")
2826 (set_attr "mode" "<UNITMODE>")
2827 (set (attr "insn_count")
2828 (if_then_else (match_test "TARGET_FIX_SB1")
2832 (define_insn "*recip<mode>3"
2833 [(set (match_operand:ANYF 0 "register_operand" "=f")
2834 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2835 (match_operand:ANYF 2 "register_operand" "f")))]
2836 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
2839 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2841 return "recip.<fmt>\t%0,%2";
2843 [(set_attr "type" "frdiv")
2844 (set_attr "mode" "<UNITMODE>")
2845 (set (attr "insn_count")
2846 (if_then_else (match_test "TARGET_FIX_SB1")
2850 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2851 ;; with negative operands. We use special libgcc functions instead.
2852 (define_expand "divmod<mode>4"
2854 [(set (match_operand:GPR 0 "register_operand")
2855 (div:GPR (match_operand:GPR 1 "register_operand")
2856 (match_operand:GPR 2 "register_operand")))
2857 (set (match_operand:GPR 3 "register_operand")
2858 (mod:GPR (match_dup 1)
2860 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
2864 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
2865 emit_insn (gen_divmod<mode>4_mips16 (operands[0], operands[1],
2866 operands[2], operands[3], lo));
2871 (define_insn_and_split "*divmod<mode>4"
2872 [(set (match_operand:GPR 0 "register_operand" "=l")
2873 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2874 (match_operand:GPR 2 "register_operand" "d")))
2875 (set (match_operand:GPR 3 "register_operand" "=d")
2876 (mod:GPR (match_dup 1)
2878 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && !TARGET_MIPS16"
2880 "&& reload_completed"
2883 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2886 [(set_attr "type" "idiv")
2887 (set_attr "mode" "<MODE>")
2888 (set_attr "insn_count" "2")])
2890 ;; Expand generates divmod instructions for individual division and modulus
2891 ;; operations. We then rely on CSE to reuse earlier divmods where possible.
2892 ;; This means that, when generating MIPS16 code, it is better not to expose
2893 ;; the fixed LO register until after CSE has finished. However, it's still
2894 ;; better to split before register allocation, so that we don't allocate
2895 ;; one of the scarce MIPS16 registers to an unused result.
2896 (define_insn_and_split "divmod<mode>4_mips16"
2897 [(set (match_operand:GPR 0 "register_operand" "=d")
2898 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2899 (match_operand:GPR 2 "register_operand" "d")))
2900 (set (match_operand:GPR 3 "register_operand" "=d")
2901 (mod:GPR (match_dup 1)
2903 (clobber (match_operand:GPR 4 "lo_operand" "=l"))]
2904 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && TARGET_MIPS16"
2906 "&& cse_not_expected"
2909 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2910 emit_move_insn (operands[0], operands[4]);
2913 [(set_attr "type" "idiv")
2914 (set_attr "mode" "<MODE>")
2915 (set_attr "insn_count" "3")])
2917 (define_expand "udivmod<mode>4"
2919 [(set (match_operand:GPR 0 "register_operand")
2920 (udiv:GPR (match_operand:GPR 1 "register_operand")
2921 (match_operand:GPR 2 "register_operand")))
2922 (set (match_operand:GPR 3 "register_operand")
2923 (umod:GPR (match_dup 1)
2925 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
2929 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
2930 emit_insn (gen_udivmod<mode>4_mips16 (operands[0], operands[1],
2931 operands[2], operands[3], lo));
2936 (define_insn_and_split "*udivmod<mode>4"
2937 [(set (match_operand:GPR 0 "register_operand" "=l")
2938 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2939 (match_operand:GPR 2 "register_operand" "d")))
2940 (set (match_operand:GPR 3 "register_operand" "=d")
2941 (umod:GPR (match_dup 1)
2943 "ISA_HAS_<D>DIV && !TARGET_MIPS16"
2948 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2951 [(set_attr "type" "idiv")
2952 (set_attr "mode" "<MODE>")
2953 (set_attr "insn_count" "2")])
2955 ;; See the comment above "divmod<mode>4_mips16" for the split timing.
2956 (define_insn_and_split "udivmod<mode>4_mips16"
2957 [(set (match_operand:GPR 0 "register_operand" "=d")
2958 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2959 (match_operand:GPR 2 "register_operand" "d")))
2960 (set (match_operand:GPR 3 "register_operand" "=d")
2961 (umod:GPR (match_dup 1)
2963 (clobber (match_operand:GPR 4 "lo_operand" "=l"))]
2964 "ISA_HAS_<D>DIV && TARGET_MIPS16"
2969 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2970 emit_move_insn (operands[0], operands[4]);
2973 [(set_attr "type" "idiv")
2974 (set_attr "mode" "<MODE>")
2975 (set_attr "insn_count" "3")])
2977 (define_expand "<u>divmod<mode>4_split"
2978 [(set (match_operand:GPR 0 "register_operand")
2979 (any_mod:GPR (match_operand:GPR 1 "register_operand")
2980 (match_operand:GPR 2 "register_operand")))]
2987 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2988 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1],
2990 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo));
2994 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2995 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1],
2997 emit_insn (gen_mfhi<mode>_di (operands[0], hilo));
3002 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
3003 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x")
3005 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
3006 (match_operand:GPR 2 "register_operand" "d"))]
3008 "ISA_HAS_<GPR:D>DIV"
3009 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
3010 [(set_attr "type" "idiv")
3011 (set_attr "mode" "<GPR:MODE>")])
3013 ;; Integer division and modulus.
3015 (define_insn "<u>div<mode>3"
3016 [(set (match_operand:GPR 0 "register_operand" "=&d")
3017 (any_div:GPR (match_operand:GPR 1 "register_operand" "d")
3018 (match_operand:GPR 2 "register_operand" "d")))]
3019 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>DIV"
3021 if (TARGET_LOONGSON_2EF)
3022 return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands);
3023 else if (TARGET_LOONGSON_EXT)
3024 return mips_output_division ("gs<d>div<u>\t%0,%1,%2", operands);
3026 return mips_output_division ("<d>div<u>\t%0,%1,%2", operands);
3028 [(set_attr "type" "idiv3")
3029 (set_attr "mode" "<MODE>")])
3031 (define_insn "<u>mod<mode>3"
3032 [(set (match_operand:GPR 0 "register_operand" "=&d")
3033 (any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
3034 (match_operand:GPR 2 "register_operand" "d")))]
3035 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || ISA_HAS_R6<D>DIV"
3037 if (TARGET_LOONGSON_2EF)
3038 return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands);
3039 else if (TARGET_LOONGSON_EXT)
3040 return mips_output_division ("gs<d>mod<u>\t%0,%1,%2", operands);
3042 return mips_output_division ("<d>mod<u>\t%0,%1,%2", operands);
3044 [(set_attr "type" "idiv3")
3045 (set_attr "mode" "<MODE>")])
3048 ;; ....................
3052 ;; ....................
3054 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
3055 ;; "*div[sd]f3" comment for details).
3057 (define_insn "sqrt<mode>2"
3058 [(set (match_operand:ANYF 0 "register_operand" "=f")
3059 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
3063 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
3065 return "sqrt.<fmt>\t%0,%1";
3067 [(set_attr "type" "fsqrt")
3068 (set_attr "mode" "<UNITMODE>")
3069 (set (attr "insn_count")
3070 (if_then_else (match_test "TARGET_FIX_SB1")
3074 (define_insn "*rsqrt<mode>a"
3075 [(set (match_operand:ANYF 0 "register_operand" "=f")
3076 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
3077 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
3078 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
3081 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
3083 return "rsqrt.<fmt>\t%0,%2";
3085 [(set_attr "type" "frsqrt")
3086 (set_attr "mode" "<UNITMODE>")
3087 (set (attr "insn_count")
3088 (if_then_else (match_test "TARGET_FIX_SB1")
3092 (define_insn "*rsqrt<mode>b"
3093 [(set (match_operand:ANYF 0 "register_operand" "=f")
3094 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
3095 (match_operand:ANYF 2 "register_operand" "f"))))]
3096 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
3099 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
3101 return "rsqrt.<fmt>\t%0,%2";
3103 [(set_attr "type" "frsqrt")
3104 (set_attr "mode" "<UNITMODE>")
3105 (set (attr "insn_count")
3106 (if_then_else (match_test "TARGET_FIX_SB1")
3111 ;; ....................
3115 ;; ....................
3117 ;; Do not use the integer abs macro instruction, since that signals an
3118 ;; exception on -2147483648 (sigh).
3120 ;; The "legacy" (as opposed to "2008") form of ABS.fmt is an arithmetic
3121 ;; instruction that treats all NaN inputs as invalid; it does not clear
3122 ;; their sign bit. We therefore can't use that form if the signs of
3125 (define_insn "abs<mode>2"
3126 [(set (match_operand:ANYF 0 "register_operand" "=f")
3127 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
3128 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)"
3130 [(set_attr "type" "fabs")
3131 (set_attr "mode" "<UNITMODE>")])
3134 ;; ...................
3136 ;; Count leading zeroes.
3138 ;; ...................
3141 (define_insn "clz<mode>2"
3142 [(set (match_operand:GPR 0 "register_operand" "=d")
3143 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
3146 [(set_attr "type" "clz")
3147 (set_attr "mode" "<MODE>")])
3150 ;; ...................
3152 ;; Count tailing zeroes.
3154 ;; ...................
3157 (define_insn "ctz<mode>2"
3158 [(set (match_operand:GPR 0 "register_operand" "=d")
3159 (ctz:GPR (match_operand:GPR 1 "register_operand" "d")))]
3162 [(set_attr "type" "clz")
3163 (set_attr "mode" "<MODE>")])
3167 ;; ...................
3169 ;; Count number of set bits.
3171 ;; ...................
3174 (define_insn "popcount<mode>2"
3175 [(set (match_operand:GPR 0 "register_operand" "=d")
3176 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
3179 [(set_attr "type" "pop")
3180 (set_attr "mode" "<MODE>")])
3182 ;; The POP instruction is special as it does not take into account the upper
3183 ;; 32bits and is documented that way.
3184 (define_insn "*popcountdi2_trunc"
3185 [(set (match_operand:SI 0 "register_operand" "=d")
3186 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))]
3187 "ISA_HAS_POP && TARGET_64BIT"
3189 [(set_attr "type" "pop")
3190 (set_attr "mode" "SI")])
3193 ;; ....................
3195 ;; NEGATION and ONE'S COMPLEMENT
3197 ;; ....................
3199 (define_insn "negsi2"
3200 [(set (match_operand:SI 0 "register_operand" "=d")
3201 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
3205 return "neg\t%0,%1";
3207 return "subu\t%0,%.,%1";
3209 [(set_attr "alu_type" "sub")
3210 (set_attr "mode" "SI")])
3212 (define_insn "negdi2"
3213 [(set (match_operand:DI 0 "register_operand" "=d")
3214 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
3215 "TARGET_64BIT && !TARGET_MIPS16"
3217 [(set_attr "alu_type" "sub")
3218 (set_attr "mode" "DI")])
3220 ;; The "legacy" (as opposed to "2008") form of NEG.fmt is an arithmetic
3221 ;; instruction that treats all NaN inputs as invalid; it does not flip
3222 ;; their sign bit. We therefore can't use that form if the signs of
3225 (define_insn "neg<mode>2"
3226 [(set (match_operand:ANYF 0 "register_operand" "=f")
3227 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
3228 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)"
3230 [(set_attr "type" "fneg")
3231 (set_attr "mode" "<UNITMODE>")])
3233 (define_insn "one_cmpl<mode>2"
3234 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
3235 (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))]
3239 return "not\t%0,%1";
3241 return "nor\t%0,%.,%1";
3243 [(set_attr "alu_type" "not")
3244 (set_attr "compression" "micromips,*")
3245 (set_attr "mode" "<MODE>")])
3248 ;; ....................
3252 ;; ....................
3255 ;; Many of these instructions use trivial define_expands, because we
3256 ;; want to use a different set of constraints when TARGET_MIPS16.
3258 (define_expand "and<mode>3"
3259 [(set (match_operand:GPR 0 "register_operand")
3260 (and:GPR (match_operand:GPR 1 "register_operand")
3261 (match_operand:GPR 2 "and_reg_operand")))])
3263 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
3264 ;; zero_extendsidi2 because of TARGET_TRULY_NOOP_TRUNCATION, so handle these
3265 ;; here. Note that this variant does not trigger for SI mode because we
3266 ;; require a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
3267 ;; sign-extended SImode value.
3269 ;; These are possible combinations for operand 1 and 2. The table
3270 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
3271 ;; 16=MIPS16, x=match, S=split):
3273 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
3279 ;; 0xffff_ffff x S x S x
3284 (define_insn "*and<mode>3"
3285 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d")
3286 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d")
3287 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))]
3288 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
3292 switch (which_alternative)
3295 operands[1] = gen_lowpart (QImode, operands[1]);
3296 return "lbu\t%0,%1";
3298 operands[1] = gen_lowpart (HImode, operands[1]);
3299 return "lhu\t%0,%1";
3301 operands[1] = gen_lowpart (SImode, operands[1]);
3302 return "lwu\t%0,%1";
3305 return "andi\t%0,%1,%x2";
3307 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
3308 operands[2] = GEN_INT (len);
3309 return "<d>ext\t%0,%1,0,%2";
3314 return "and\t%0,%1,%2";
3319 [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical")
3320 (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*")
3321 (set_attr "mode" "<MODE>")])
3323 (define_insn "*and<mode>3_mips16"
3324 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3325 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0")
3326 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
3327 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
3329 switch (which_alternative)
3332 operands[1] = gen_lowpart (QImode, operands[1]);
3333 return "lbu\t%0,%1";
3335 operands[1] = gen_lowpart (HImode, operands[1]);
3336 return "lhu\t%0,%1";
3338 operands[1] = gen_lowpart (SImode, operands[1]);
3339 return "lwu\t%0,%1";
3343 return "and\t%0,%2";
3348 [(set_attr "move_type" "load,load,load,shift_shift,logical")
3349 (set_attr "mode" "<MODE>")])
3351 (define_expand "ior<mode>3"
3352 [(set (match_operand:GPR 0 "register_operand")
3353 (ior:GPR (match_operand:GPR 1 "register_operand")
3354 (match_operand:GPR 2 "uns_arith_operand")))]
3358 operands[2] = force_reg (<MODE>mode, operands[2]);
3361 (define_insn "*ior<mode>3"
3362 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3363 (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
3364 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
3370 [(set_attr "alu_type" "or")
3371 (set_attr "compression" "micromips,*,*")
3372 (set_attr "mode" "<MODE>")])
3374 (define_insn "*ior<mode>3_mips16"
3375 [(set (match_operand:GPR 0 "register_operand" "=d")
3376 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
3377 (match_operand:GPR 2 "register_operand" "d")))]
3380 [(set_attr "alu_type" "or")
3381 (set_attr "mode" "<MODE>")])
3383 (define_expand "xor<mode>3"
3384 [(set (match_operand:GPR 0 "register_operand")
3385 (xor:GPR (match_operand:GPR 1 "register_operand")
3386 (match_operand:GPR 2 "uns_arith_operand")))]
3390 (define_insn "*xor<mode>3"
3391 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3392 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
3393 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
3399 [(set_attr "alu_type" "xor")
3400 (set_attr "compression" "micromips,*,*")
3401 (set_attr "mode" "<MODE>")])
3403 (define_insn "*xor<mode>3_mips16"
3404 [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t")
3405 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d")
3406 (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))]
3413 [(set_attr "alu_type" "xor")
3414 (set_attr "mode" "<MODE>")
3415 (set_attr "extended_mips16" "no,no,yes,no")])
3417 (define_insn "*nor<mode>3"
3418 [(set (match_operand:GPR 0 "register_operand" "=d")
3419 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
3420 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
3423 [(set_attr "alu_type" "nor")
3424 (set_attr "mode" "<MODE>")])
3427 ;; ....................
3431 ;; ....................
3435 (define_insn "truncdfsf2"
3436 [(set (match_operand:SF 0 "register_operand" "=f")
3437 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3438 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3440 [(set_attr "type" "fcvt")
3441 (set_attr "cnv_mode" "D2S")
3442 (set_attr "mode" "SF")])
3444 ;; Integer truncation patterns. Truncating SImode values to smaller
3445 ;; modes is a no-op, as it is for most other GCC ports. Truncating
3446 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
3447 ;; need to make sure that the lower 32 bits are properly sign-extended
3448 ;; (see TARGET_TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
3449 ;; smaller than SImode is equivalent to two separate truncations:
3452 ;; DI ---> HI == DI ---> SI ---> HI
3453 ;; DI ---> QI == DI ---> SI ---> QI
3455 ;; Step A needs a real instruction but step B does not.
3457 (define_insn "truncdi<mode>2"
3458 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
3459 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
3464 [(set_attr "move_type" "sll0,store")
3465 (set_attr "mode" "SI")])
3467 ;; Combiner patterns to optimize shift/truncate combinations.
3469 (define_insn "*ashr_trunc<mode>"
3470 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3472 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3473 (match_operand:DI 2 "const_arith_operand" ""))))]
3474 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3476 [(set_attr "type" "shift")
3477 (set_attr "mode" "<MODE>")])
3479 (define_insn "*lshr32_trunc<mode>"
3480 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3482 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3484 "TARGET_64BIT && !TARGET_MIPS16"
3486 [(set_attr "type" "shift")
3487 (set_attr "mode" "<MODE>")])
3489 ;; Logical shift by more than 32 results in proper SI values so truncation is
3490 ;; removed by the middle end. Note that a logical shift by 32 is handled by
3491 ;; the previous pattern.
3492 (define_insn "*<optab>_trunc<mode>_exts"
3493 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3495 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
3496 (match_operand:DI 2 "const_arith_operand" ""))))]
3497 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
3499 [(set_attr "type" "arith")
3500 (set_attr "mode" "<MODE>")])
3503 ;; ....................
3507 ;; ....................
3511 (define_expand "zero_extendsidi2"
3512 [(set (match_operand:DI 0 "register_operand")
3513 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
3516 (define_insn_and_split "*zero_extendsidi2"
3517 [(set (match_operand:DI 0 "register_operand" "=d,d")
3518 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3519 "TARGET_64BIT && !ISA_HAS_EXT_INS"
3523 "&& reload_completed && REG_P (operands[1])"
3525 (ashift:DI (match_dup 1) (const_int 32)))
3527 (lshiftrt:DI (match_dup 0) (const_int 32)))]
3528 { operands[1] = gen_lowpart (DImode, operands[1]); }
3529 [(set_attr "move_type" "shift_shift,load")
3530 (set_attr "mode" "DI")])
3532 (define_insn "*zero_extendsidi2_dext"
3533 [(set (match_operand:DI 0 "register_operand" "=d,d")
3534 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3535 "TARGET_64BIT && ISA_HAS_EXT_INS"
3539 [(set_attr "move_type" "arith,load")
3540 (set_attr "mode" "DI")])
3542 ;; See the comment before the *and<mode>3 pattern why this is generated by
3546 [(set (match_operand:DI 0 "register_operand")
3547 (and:DI (match_operand:DI 1 "register_operand")
3548 (const_int 4294967295)))]
3549 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
3551 (ashift:DI (match_dup 1) (const_int 32)))
3553 (lshiftrt:DI (match_dup 0) (const_int 32)))])
3555 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
3556 [(set (match_operand:GPR 0 "register_operand")
3557 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3560 if (TARGET_MIPS16 && !GENERATE_MIPS16E
3561 && !memory_operand (operands[1], <SHORT:MODE>mode))
3563 emit_insn (gen_and<GPR:mode>3 (operands[0],
3564 gen_lowpart (<GPR:MODE>mode, operands[1]),
3565 force_reg (<GPR:MODE>mode,
3566 GEN_INT (<SHORT:mask>))));
3571 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
3572 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3574 (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))]
3577 andi\t%0,%1,<SHORT:mask>
3578 andi\t%0,%1,<SHORT:mask>
3579 l<SHORT:size>u\t%0,%1"
3580 [(set_attr "move_type" "andi,andi,load")
3581 (set_attr "compression" "micromips,*,*")
3582 (set_attr "mode" "<GPR:MODE>")])
3584 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
3585 [(set (match_operand:GPR 0 "register_operand" "=d")
3586 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
3588 "ze<SHORT:size>\t%0"
3589 ;; This instruction is effectively a special encoding of ANDI.
3590 [(set_attr "move_type" "andi")
3591 (set_attr "mode" "<GPR:MODE>")])
3593 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
3594 [(set (match_operand:GPR 0 "register_operand" "=d")
3595 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
3597 "l<SHORT:size>u\t%0,%1"
3598 [(set_attr "move_type" "load")
3599 (set_attr "mode" "<GPR:MODE>")])
3601 (define_expand "zero_extendqihi2"
3602 [(set (match_operand:HI 0 "register_operand")
3603 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3606 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
3608 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
3614 (define_insn "*zero_extendqihi2"
3615 [(set (match_operand:HI 0 "register_operand" "=d,d")
3616 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3621 [(set_attr "move_type" "andi,load")
3622 (set_attr "mode" "HI")])
3624 (define_insn "*zero_extendqihi2_mips16"
3625 [(set (match_operand:HI 0 "register_operand" "=d")
3626 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3629 [(set_attr "move_type" "load")
3630 (set_attr "mode" "HI")])
3632 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3634 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
3635 [(set (match_operand:GPR 0 "register_operand" "=d")
3637 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3638 "TARGET_64BIT && !TARGET_MIPS16"
3640 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3641 return "andi\t%0,%1,%x2";
3643 [(set_attr "alu_type" "and")
3644 (set_attr "mode" "<GPR:MODE>")])
3646 (define_insn "*zero_extendhi_truncqi"
3647 [(set (match_operand:HI 0 "register_operand" "=d")
3649 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3650 "TARGET_64BIT && !TARGET_MIPS16"
3652 [(set_attr "alu_type" "and")
3653 (set_attr "mode" "HI")])
3656 ;; ....................
3660 ;; ....................
3663 ;; Those for integer source operand are ordered widest source type first.
3665 ;; When TARGET_64BIT, all SImode integer and accumulator registers
3666 ;; should already be in sign-extended form (see TARGET_TRULY_NOOP_TRUNCATION
3667 ;; and truncdisi2). We can therefore get rid of register->register
3668 ;; instructions if we constrain the source to be in the same register as
3671 ;; Only the pre-reload scheduler sees the type of the register alternatives;
3672 ;; we split them into nothing before the post-reload scheduler runs.
3673 ;; These alternatives therefore have type "move" in order to reflect
3674 ;; what happens if the two pre-reload operands cannot be tied, and are
3675 ;; instead allocated two separate GPRs. We don't distinguish between
3676 ;; the GPR and LO cases because we don't usually know during pre-reload
3677 ;; scheduling whether an operand will be LO or not.
3678 (define_insn_and_split "extendsidi2"
3679 [(set (match_operand:DI 0 "register_operand" "=d,l,d")
3680 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
3686 "&& reload_completed && register_operand (operands[1], VOIDmode)"
3689 emit_note (NOTE_INSN_DELETED);
3692 [(set_attr "move_type" "move,move,load")
3693 (set_attr "mode" "DI")])
3695 (define_expand "extend<SHORT:mode><GPR:mode>2"
3696 [(set (match_operand:GPR 0 "register_operand")
3697 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3700 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
3701 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3702 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3706 l<SHORT:size>\t%0,%1"
3707 [(set_attr "move_type" "signext,load")
3708 (set_attr "mode" "<GPR:MODE>")])
3710 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3711 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3713 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3714 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3717 l<SHORT:size>\t%0,%1"
3718 "&& reload_completed && REG_P (operands[1])"
3719 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3720 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3722 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3723 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3724 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3726 [(set_attr "move_type" "shift_shift,load")
3727 (set_attr "mode" "<GPR:MODE>")])
3729 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3730 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3732 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3735 se<SHORT:size>\t%0,%1
3736 l<SHORT:size>\t%0,%1"
3737 [(set_attr "move_type" "signext,load")
3738 (set_attr "mode" "<GPR:MODE>")])
3740 (define_expand "extendqihi2"
3741 [(set (match_operand:HI 0 "register_operand")
3742 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3745 (define_insn "*extendqihi2_mips16e"
3746 [(set (match_operand:HI 0 "register_operand" "=d,d")
3747 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3752 [(set_attr "move_type" "signext,load")
3753 (set_attr "mode" "SI")])
3755 (define_insn_and_split "*extendqihi2"
3756 [(set (match_operand:HI 0 "register_operand" "=d,d")
3758 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3759 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3763 "&& reload_completed && REG_P (operands[1])"
3764 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3765 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3767 operands[0] = gen_lowpart (SImode, operands[0]);
3768 operands[1] = gen_lowpart (SImode, operands[1]);
3769 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3770 - GET_MODE_BITSIZE (QImode));
3772 [(set_attr "move_type" "shift_shift,load")
3773 (set_attr "mode" "SI")])
3775 (define_insn "*extendqihi2_seb"
3776 [(set (match_operand:HI 0 "register_operand" "=d,d")
3778 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3783 [(set_attr "move_type" "signext,load")
3784 (set_attr "mode" "SI")])
3786 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3787 ;; use the shift/truncate patterns.
3789 (define_insn_and_split "*extenddi_truncate<mode>"
3790 [(set (match_operand:DI 0 "register_operand" "=d")
3792 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3793 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3795 "&& reload_completed"
3797 (ashift:DI (match_dup 1)
3800 (ashiftrt:DI (match_dup 2)
3803 operands[2] = gen_lowpart (DImode, operands[0]);
3804 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3806 [(set_attr "move_type" "shift_shift")
3807 (set_attr "mode" "DI")])
3809 (define_insn_and_split "*extendsi_truncate<mode>"
3810 [(set (match_operand:SI 0 "register_operand" "=d")
3812 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3813 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3815 "&& reload_completed"
3817 (ashift:DI (match_dup 1)
3820 (truncate:SI (ashiftrt:DI (match_dup 2)
3823 operands[2] = gen_lowpart (DImode, operands[0]);
3824 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3826 [(set_attr "move_type" "shift_shift")
3827 (set_attr "mode" "SI")])
3829 (define_insn_and_split "*extendhi_truncateqi"
3830 [(set (match_operand:HI 0 "register_operand" "=d")
3832 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3833 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3835 "&& reload_completed"
3837 (ashift:DI (match_dup 1)
3840 (truncate:HI (ashiftrt:DI (match_dup 2)
3843 operands[2] = gen_lowpart (DImode, operands[0]);
3845 [(set_attr "move_type" "shift_shift")
3846 (set_attr "mode" "SI")])
3848 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3849 [(set (match_operand:GPR 0 "register_operand" "=d")
3851 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3852 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3854 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3855 return "exts\t%0,%1,0,%m2";
3857 [(set_attr "type" "arith")
3858 (set_attr "mode" "<GPR:MODE>")])
3860 (define_insn "*extendhi_truncateqi_exts"
3861 [(set (match_operand:HI 0 "register_operand" "=d")
3863 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3864 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3866 [(set_attr "type" "arith")
3867 (set_attr "mode" "SI")])
3869 (define_insn "extendsfdf2"
3870 [(set (match_operand:DF 0 "register_operand" "=f")
3871 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3872 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3874 [(set_attr "type" "fcvt")
3875 (set_attr "cnv_mode" "S2D")
3876 (set_attr "mode" "DF")])
3879 ;; ....................
3883 ;; ....................
3885 (define_expand "fix_truncdfsi2"
3886 [(set (match_operand:SI 0 "register_operand")
3887 (fix:SI (match_operand:DF 1 "register_operand")))]
3888 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3890 if (!ISA_HAS_TRUNC_W)
3892 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3897 (define_insn "fix_truncdfsi2_insn"
3898 [(set (match_operand:SI 0 "register_operand" "=f")
3899 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3900 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3902 [(set_attr "type" "fcvt")
3903 (set_attr "mode" "DF")
3904 (set_attr "cnv_mode" "D2I")])
3906 (define_insn "fix_truncdfsi2_macro"
3907 [(set (match_operand:SI 0 "register_operand" "=f")
3908 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3909 (clobber (match_scratch:DF 2 "=d"))]
3910 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3912 if (mips_nomacro.nesting_level > 0)
3913 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3915 return "trunc.w.d %0,%1,%2";
3917 [(set_attr "type" "fcvt")
3918 (set_attr "mode" "DF")
3919 (set_attr "cnv_mode" "D2I")
3920 (set_attr "insn_count" "9")])
3922 (define_expand "fix_truncsfsi2"
3923 [(set (match_operand:SI 0 "register_operand")
3924 (fix:SI (match_operand:SF 1 "register_operand")))]
3927 if (!ISA_HAS_TRUNC_W)
3929 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3934 (define_insn "fix_truncsfsi2_insn"
3935 [(set (match_operand:SI 0 "register_operand" "=f")
3936 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3937 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3939 [(set_attr "type" "fcvt")
3940 (set_attr "mode" "SF")
3941 (set_attr "cnv_mode" "S2I")])
3943 (define_insn "fix_truncsfsi2_macro"
3944 [(set (match_operand:SI 0 "register_operand" "=f")
3945 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3946 (clobber (match_scratch:SF 2 "=d"))]
3947 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3949 if (mips_nomacro.nesting_level > 0)
3950 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3952 return "trunc.w.s %0,%1,%2";
3954 [(set_attr "type" "fcvt")
3955 (set_attr "mode" "SF")
3956 (set_attr "cnv_mode" "S2I")
3957 (set_attr "insn_count" "9")])
3960 (define_insn "fix_truncdfdi2"
3961 [(set (match_operand:DI 0 "register_operand" "=f")
3962 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3963 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3965 [(set_attr "type" "fcvt")
3966 (set_attr "mode" "DF")
3967 (set_attr "cnv_mode" "D2I")])
3970 (define_insn "fix_truncsfdi2"
3971 [(set (match_operand:DI 0 "register_operand" "=f")
3972 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3973 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3975 [(set_attr "type" "fcvt")
3976 (set_attr "mode" "SF")
3977 (set_attr "cnv_mode" "S2I")])
3980 (define_insn "floatsidf2"
3981 [(set (match_operand:DF 0 "register_operand" "=f")
3982 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3983 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3985 [(set_attr "type" "fcvt")
3986 (set_attr "mode" "DF")
3987 (set_attr "cnv_mode" "I2D")])
3990 (define_insn "floatdidf2"
3991 [(set (match_operand:DF 0 "register_operand" "=f")
3992 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3993 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3995 [(set_attr "type" "fcvt")
3996 (set_attr "mode" "DF")
3997 (set_attr "cnv_mode" "I2D")])
4000 (define_insn "floatsisf2"
4001 [(set (match_operand:SF 0 "register_operand" "=f")
4002 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4005 [(set_attr "type" "fcvt")
4006 (set_attr "mode" "SF")
4007 (set_attr "cnv_mode" "I2S")])
4010 (define_insn "floatdisf2"
4011 [(set (match_operand:SF 0 "register_operand" "=f")
4012 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4013 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
4015 [(set_attr "type" "fcvt")
4016 (set_attr "mode" "SF")
4017 (set_attr "cnv_mode" "I2S")])
4020 (define_expand "fixuns_truncdfsi2"
4021 [(set (match_operand:SI 0 "register_operand")
4022 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
4023 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4025 rtx reg1 = gen_reg_rtx (DFmode);
4026 rtx reg2 = gen_reg_rtx (DFmode);
4027 rtx reg3 = gen_reg_rtx (SImode);
4028 rtx_code_label *label1 = gen_label_rtx ();
4029 rtx_code_label *label2 = gen_label_rtx ();
4031 REAL_VALUE_TYPE offset;
4033 real_2expN (&offset, 31, DFmode);
4035 if (reg1) /* Turn off complaints about unreached code. */
4037 mips_emit_move (reg1, const_double_from_real_value (offset, DFmode));
4038 do_pending_stack_adjust ();
4040 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4041 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
4043 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
4044 emit_jump_insn (gen_rtx_SET (pc_rtx,
4045 gen_rtx_LABEL_REF (VOIDmode, label2)));
4048 emit_label (label1);
4049 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4050 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
4051 (BITMASK_HIGH, SImode)));
4053 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
4054 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4056 emit_label (label2);
4058 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4059 fields, and can't be used for REG_NOTES anyway). */
4060 emit_use (stack_pointer_rtx);
4066 (define_expand "fixuns_truncdfdi2"
4067 [(set (match_operand:DI 0 "register_operand")
4068 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
4069 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4071 rtx reg1 = gen_reg_rtx (DFmode);
4072 rtx reg2 = gen_reg_rtx (DFmode);
4073 rtx reg3 = gen_reg_rtx (DImode);
4074 rtx_code_label *label1 = gen_label_rtx ();
4075 rtx_code_label *label2 = gen_label_rtx ();
4077 REAL_VALUE_TYPE offset;
4079 real_2expN (&offset, 63, DFmode);
4081 mips_emit_move (reg1, const_double_from_real_value (offset, DFmode));
4082 do_pending_stack_adjust ();
4084 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4085 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
4087 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
4088 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4091 emit_label (label1);
4092 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4093 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
4094 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4096 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
4097 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4099 emit_label (label2);
4101 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4102 fields, and can't be used for REG_NOTES anyway). */
4103 emit_use (stack_pointer_rtx);
4108 (define_expand "fixuns_truncsfsi2"
4109 [(set (match_operand:SI 0 "register_operand")
4110 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
4113 rtx reg1 = gen_reg_rtx (SFmode);
4114 rtx reg2 = gen_reg_rtx (SFmode);
4115 rtx reg3 = gen_reg_rtx (SImode);
4116 rtx_code_label *label1 = gen_label_rtx ();
4117 rtx_code_label *label2 = gen_label_rtx ();
4119 REAL_VALUE_TYPE offset;
4121 real_2expN (&offset, 31, SFmode);
4123 mips_emit_move (reg1, const_double_from_real_value (offset, SFmode));
4124 do_pending_stack_adjust ();
4126 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4127 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
4129 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
4130 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4133 emit_label (label1);
4134 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4135 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
4136 (BITMASK_HIGH, SImode)));
4138 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
4139 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4141 emit_label (label2);
4143 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4144 fields, and can't be used for REG_NOTES anyway). */
4145 emit_use (stack_pointer_rtx);
4150 (define_expand "fixuns_truncsfdi2"
4151 [(set (match_operand:DI 0 "register_operand")
4152 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
4153 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4155 rtx reg1 = gen_reg_rtx (SFmode);
4156 rtx reg2 = gen_reg_rtx (SFmode);
4157 rtx reg3 = gen_reg_rtx (DImode);
4158 rtx_code_label *label1 = gen_label_rtx ();
4159 rtx_code_label *label2 = gen_label_rtx ();
4161 REAL_VALUE_TYPE offset;
4163 real_2expN (&offset, 63, SFmode);
4165 mips_emit_move (reg1, const_double_from_real_value (offset, SFmode));
4166 do_pending_stack_adjust ();
4168 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4169 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
4171 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
4172 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4175 emit_label (label1);
4176 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4177 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
4178 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4180 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
4181 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4183 emit_label (label2);
4185 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4186 fields, and can't be used for REG_NOTES anyway). */
4187 emit_use (stack_pointer_rtx);
4192 ;; ....................
4196 ;; ....................
4198 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
4200 (define_expand "extvmisalign<mode>"
4201 [(set (match_operand:GPR 0 "register_operand")
4202 (sign_extract:GPR (match_operand:BLK 1 "memory_operand")
4203 (match_operand 2 "const_int_operand")
4204 (match_operand 3 "const_int_operand")))]
4207 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
4208 INTVAL (operands[2]),
4209 INTVAL (operands[3]),
4210 /*unsigned=*/ false))
4216 (define_expand "extv<mode>"
4217 [(set (match_operand:GPR 0 "register_operand")
4218 (sign_extract:GPR (match_operand:GPR 1 "register_operand")
4219 (match_operand 2 "const_int_operand")
4220 (match_operand 3 "const_int_operand")))]
4223 if (UINTVAL (operands[2]) > 32)
4227 (define_insn "*extv<mode>"
4228 [(set (match_operand:GPR 0 "register_operand" "=d")
4229 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
4230 (match_operand 2 "const_int_operand" "")
4231 (match_operand 3 "const_int_operand" "")))]
4232 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
4233 "exts\t%0,%1,%3,%m2"
4234 [(set_attr "type" "arith")
4235 (set_attr "mode" "<MODE>")])
4237 (define_expand "extzvmisalign<mode>"
4238 [(set (match_operand:GPR 0 "register_operand")
4239 (zero_extract:GPR (match_operand:BLK 1 "memory_operand")
4240 (match_operand 2 "const_int_operand")
4241 (match_operand 3 "const_int_operand")))]
4244 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
4245 INTVAL (operands[2]),
4246 INTVAL (operands[3]),
4247 /*unsigned=*/ true))
4253 (define_expand "extzv<mode>"
4254 [(set (match_operand:GPR 0 "register_operand")
4255 (zero_extract:GPR (match_operand:GPR 1 "register_operand")
4256 (match_operand 2 "const_int_operand")
4257 (match_operand 3 "const_int_operand")))]
4260 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
4261 INTVAL (operands[3])))
4265 (define_insn "*extzv<mode>"
4266 [(set (match_operand:GPR 0 "register_operand" "=d")
4267 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
4268 (match_operand 2 "const_int_operand" "")
4269 (match_operand 3 "const_int_operand" "")))]
4270 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
4271 INTVAL (operands[3]))"
4272 "<d>ext\t%0,%1,%3,%2"
4273 [(set_attr "type" "arith")
4274 (set_attr "mode" "<MODE>")])
4276 (define_insn "*extzv_truncsi_exts"
4277 [(set (match_operand:SI 0 "register_operand" "=d")
4279 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
4280 (match_operand 2 "const_int_operand" "")
4281 (match_operand 3 "const_int_operand" ""))))]
4282 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
4284 [(set_attr "type" "arith")
4285 (set_attr "mode" "SI")])
4288 (define_expand "insvmisalign<mode>"
4289 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")
4290 (match_operand 1 "const_int_operand")
4291 (match_operand 2 "const_int_operand"))
4292 (match_operand:GPR 3 "reg_or_0_operand"))]
4295 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
4296 INTVAL (operands[1]),
4297 INTVAL (operands[2])))
4303 (define_expand "insv<mode>"
4304 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand")
4305 (match_operand 1 "const_int_operand")
4306 (match_operand 2 "const_int_operand"))
4307 (match_operand:GPR 3 "reg_or_0_operand"))]
4310 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
4311 INTVAL (operands[2])))
4315 (define_insn "*insv<mode>"
4316 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
4317 (match_operand:SI 1 "const_int_operand" "")
4318 (match_operand:SI 2 "const_int_operand" ""))
4319 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
4320 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
4321 INTVAL (operands[2]))"
4322 "<d>ins\t%0,%z3,%2,%1"
4323 [(set_attr "type" "arith")
4324 (set_attr "mode" "<MODE>")])
4326 ;; Combiner pattern for cins (clear and insert bit field). We can
4327 ;; implement mask-and-shift-left operation with this. Note that if
4328 ;; the upper bit of the mask is set in an SImode operation, the mask
4329 ;; itself will be sign-extended. mask_low_and_shift_len will
4330 ;; therefore be greater than our threshold of 32.
4332 (define_insn "*cins<mode>"
4333 [(set (match_operand:GPR 0 "register_operand" "=d")
4335 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
4336 (match_operand:GPR 2 "const_int_operand" ""))
4337 (match_operand:GPR 3 "const_int_operand" "")))]
4339 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
4342 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
4343 return "cins\t%0,%1,%2,%m3";
4345 [(set_attr "type" "shift")
4346 (set_attr "mode" "<MODE>")])
4348 ;; Unaligned word moves generated by the bit field patterns.
4350 ;; As far as the rtl is concerned, both the left-part and right-part
4351 ;; instructions can access the whole field. However, the real operand
4352 ;; refers to just the first or the last byte (depending on endianness).
4353 ;; We therefore use two memory operands to each instruction, one to
4354 ;; describe the rtl effect and one to use in the assembly output.
4356 ;; Operands 0 and 1 are the rtl-level target and source respectively.
4357 ;; This allows us to use the standard length calculations for the "load"
4358 ;; and "store" type attributes.
4360 (define_insn "mov_<load>l"
4361 [(set (match_operand:GPR 0 "register_operand" "=d")
4362 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
4363 (match_operand:QI 2 "memory_operand" "ZC")]
4365 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
4367 [(set_attr "move_type" "load")
4368 (set_attr "mode" "<MODE>")])
4370 (define_insn "mov_<load>r"
4371 [(set (match_operand:GPR 0 "register_operand" "=d")
4372 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
4373 (match_operand:QI 2 "memory_operand" "ZC")
4374 (match_operand:GPR 3 "register_operand" "0")]
4375 UNSPEC_LOAD_RIGHT))]
4376 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
4378 [(set_attr "move_type" "load")
4379 (set_attr "mode" "<MODE>")])
4381 (define_insn "mov_<store>l"
4382 [(set (match_operand:BLK 0 "memory_operand" "=m")
4383 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4384 (match_operand:QI 2 "memory_operand" "ZC")]
4385 UNSPEC_STORE_LEFT))]
4386 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
4388 [(set_attr "move_type" "store")
4389 (set_attr "mode" "<MODE>")])
4391 (define_insn "mov_<store>r"
4392 [(set (match_operand:BLK 0 "memory_operand" "+m")
4393 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4394 (match_operand:QI 2 "memory_operand" "ZC")
4396 UNSPEC_STORE_RIGHT))]
4397 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
4399 [(set_attr "move_type" "store")
4400 (set_attr "mode" "<MODE>")])
4402 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
4403 ;; The required value is:
4405 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
4407 ;; which translates to:
4409 ;; lui op0,%highest(op1)
4410 ;; daddiu op0,op0,%higher(op1)
4412 ;; daddiu op0,op0,%hi(op1)
4415 ;; The split is deferred until after flow2 to allow the peephole2 below
4417 (define_insn_and_split "*lea_high64"
4418 [(set (match_operand:DI 0 "register_operand" "=d")
4419 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
4420 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4422 "&& epilogue_completed"
4423 [(set (match_dup 0) (high:DI (match_dup 2)))
4424 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
4425 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
4426 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4427 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
4429 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4430 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
4432 [(set_attr "insn_count" "5")])
4434 ;; Use a scratch register to reduce the latency of the above pattern
4435 ;; on superscalar machines. The optimized sequence is:
4437 ;; lui op1,%highest(op2)
4439 ;; daddiu op1,op1,%higher(op2)
4441 ;; daddu op1,op1,op0
4443 [(set (match_operand:DI 1 "d_operand")
4444 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
4445 (match_scratch:DI 0 "d")]
4446 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4447 [(set (match_dup 1) (high:DI (match_dup 3)))
4448 (set (match_dup 0) (high:DI (match_dup 4)))
4449 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
4450 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
4451 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
4453 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
4454 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
4457 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
4458 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
4459 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
4460 ;; used once. We can then use the sequence:
4462 ;; lui op0,%highest(op1)
4464 ;; daddiu op0,op0,%higher(op1)
4465 ;; daddiu op2,op2,%lo(op1)
4467 ;; daddu op0,op0,op2
4469 ;; which takes 4 cycles on most superscalar targets.
4470 (define_insn_and_split "*lea64"
4471 [(set (match_operand:DI 0 "register_operand" "=d")
4472 (match_operand:DI 1 "absolute_symbolic_operand" ""))
4473 (clobber (match_scratch:DI 2 "=&d"))]
4475 && TARGET_EXPLICIT_RELOCS
4476 && ABI_HAS_64BIT_SYMBOLS
4477 && cse_not_expected"
4479 "&& reload_completed"
4480 [(set (match_dup 0) (high:DI (match_dup 3)))
4481 (set (match_dup 2) (high:DI (match_dup 4)))
4482 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4483 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
4484 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
4485 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
4487 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4488 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
4490 [(set_attr "insn_count" "6")])
4492 ;; Split HIGHs into:
4497 ;; on MIPS16 targets.
4499 [(set (match_operand:P 0 "d_operand")
4500 (high:P (match_operand:P 1 "symbolic_operand_with_high")))]
4501 "TARGET_MIPS16 && reload_completed"
4502 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH))
4503 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))])
4505 (define_insn "*unshifted_high"
4506 [(set (match_operand:P 0 "d_operand" "=d")
4507 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")]
4508 UNSPEC_UNSHIFTED_HIGH))]
4511 [(set_attr "extended_mips16" "yes")])
4513 ;; Insns to fetch a symbol from a big GOT.
4515 (define_insn_and_split "*xgot_hi<mode>"
4516 [(set (match_operand:P 0 "register_operand" "=d")
4517 (high:P (match_operand:P 1 "got_disp_operand" "")))]
4518 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4520 "&& reload_completed"
4521 [(set (match_dup 0) (high:P (match_dup 2)))
4522 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
4524 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
4525 operands[3] = pic_offset_table_rtx;
4527 [(set_attr "got" "xgot_high")
4528 (set_attr "mode" "<MODE>")])
4530 (define_insn_and_split "*xgot_lo<mode>"
4531 [(set (match_operand:P 0 "register_operand" "=d")
4532 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4533 (match_operand:P 2 "got_disp_operand" "")))]
4534 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4536 "&& reload_completed"
4538 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
4539 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
4540 [(set_attr "got" "load")
4541 (set_attr "mode" "<MODE>")])
4543 ;; Insns to fetch a symbol from a normal GOT.
4545 (define_insn_and_split "*got_disp<mode>"
4546 [(set (match_operand:P 0 "register_operand" "=d")
4547 (match_operand:P 1 "got_disp_operand" ""))]
4548 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
4550 "&& reload_completed"
4551 [(set (match_dup 0) (match_dup 2))]
4552 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
4553 [(set_attr "got" "load")
4554 (set_attr "mode" "<MODE>")])
4556 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
4558 (define_insn_and_split "*got_page<mode>"
4559 [(set (match_operand:P 0 "register_operand" "=d")
4560 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
4561 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
4563 "&& reload_completed"
4564 [(set (match_dup 0) (match_dup 2))]
4565 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
4566 [(set_attr "got" "load")
4567 (set_attr "mode" "<MODE>")])
4569 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
4570 (define_expand "unspec_got_<mode>"
4571 [(unspec:P [(match_operand:P 0)
4572 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
4574 ;; Lower-level instructions for loading an address from the GOT.
4575 ;; We could use MEMs, but an unspec gives more optimization
4578 (define_insn "load_got<mode>"
4579 [(set (match_operand:P 0 "register_operand" "=d")
4580 (unspec:P [(match_operand:P 1 "register_operand" "d")
4581 (match_operand:P 2 "immediate_operand" "")]
4584 "<load>\t%0,%R2(%1)"
4585 [(set_attr "got" "load")
4586 (set_attr "mode" "<MODE>")])
4588 ;; Instructions for adding the low 16 bits of an address to a register.
4589 ;; Operand 2 is the address: mips_print_operand works out which relocation
4590 ;; should be applied.
4592 (define_insn "*low<mode>"
4593 [(set (match_operand:P 0 "register_operand" "=d")
4594 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4595 (match_operand:P 2 "immediate_operand" "")))]
4597 "<d>addiu\t%0,%1,%R2"
4598 [(set_attr "alu_type" "add")
4599 (set_attr "mode" "<MODE>")])
4601 (define_insn "*low<mode>_mips16"
4602 [(set (match_operand:P 0 "register_operand" "=d")
4603 (lo_sum:P (match_operand:P 1 "register_operand" "0")
4604 (match_operand:P 2 "immediate_operand" "")))]
4607 [(set_attr "alu_type" "add")
4608 (set_attr "mode" "<MODE>")
4609 (set_attr "extended_mips16" "yes")])
4611 ;; Expose MIPS16 uses of the global pointer after reload if the function
4612 ;; is responsible for setting up the register itself.
4614 [(set (match_operand:GPR 0 "d_operand")
4615 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
4616 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
4617 [(set (match_dup 0) (match_dup 1))]
4618 { operands[1] = pic_offset_table_rtx; })
4620 ;; Allow combine to split complex const_int load sequences, using operand 2
4621 ;; to store the intermediate results. See move_operand for details.
4623 [(set (match_operand:GPR 0 "register_operand")
4624 (match_operand:GPR 1 "splittable_const_int_operand"))
4625 (clobber (match_operand:GPR 2 "register_operand"))]
4629 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
4633 ;; Likewise, for symbolic operands.
4635 [(set (match_operand:P 0 "register_operand")
4636 (match_operand:P 1))
4637 (clobber (match_operand:P 2 "register_operand"))]
4638 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
4639 [(set (match_dup 0) (match_dup 3))]
4641 mips_split_symbol (operands[2], operands[1],
4642 MAX_MACHINE_MODE, &operands[3]);
4645 ;; 64-bit integer moves
4647 ;; Unlike most other insns, the move insns can't be split with
4648 ;; different predicates, because register spilling and other parts of
4649 ;; the compiler, have memoized the insn number already.
4651 (define_expand "movdi"
4652 [(set (match_operand:DI 0 "")
4653 (match_operand:DI 1 ""))]
4656 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4660 ;; For mips16, we need a special case to handle storing $31 into
4661 ;; memory, since we don't have a constraint to match $31. This
4662 ;; instruction can be generated by save_restore_insns.
4664 (define_insn "*mov<mode>_ra"
4665 [(set (match_operand:GPR 0 "stack_operand" "=m")
4666 (reg:GPR RETURN_ADDR_REGNUM))]
4669 [(set_attr "move_type" "store")
4670 (set_attr "mode" "<MODE>")])
4672 (define_insn "*movdi_32bit"
4673 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
4674 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
4675 "!TARGET_64BIT && !TARGET_MIPS16
4676 && (register_operand (operands[0], DImode)
4677 || reg_or_0_operand (operands[1], DImode))"
4678 { return mips_output_move (operands[0], operands[1]); }
4679 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
4681 (if_then_else (eq_attr "move_type" "imul")
4683 (const_string "DI")))])
4685 (define_insn "*movdi_32bit_mips16"
4686 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4687 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
4688 "!TARGET_64BIT && TARGET_MIPS16
4689 && (register_operand (operands[0], DImode)
4690 || register_operand (operands[1], DImode))"
4691 { return mips_output_move (operands[0], operands[1]); }
4692 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4693 (set_attr "mode" "DI")])
4695 (define_insn "*movdi_64bit"
4696 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
4697 (match_operand:DI 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4698 "TARGET_64BIT && !TARGET_MIPS16
4699 && (register_operand (operands[0], DImode)
4700 || reg_or_0_operand (operands[1], DImode))"
4701 { return mips_output_move (operands[0], operands[1]); }
4702 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore")
4703 (set_attr "mode" "DI")])
4705 (define_insn "*movdi_64bit_mips16"
4706 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4707 (match_operand:DI 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4708 "TARGET_64BIT && TARGET_MIPS16
4709 && (register_operand (operands[0], DImode)
4710 || register_operand (operands[1], DImode))"
4711 { return mips_output_move (operands[0], operands[1]); }
4712 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4713 (set_attr "mode" "DI")])
4715 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4716 ;; when the original load is a 4 byte instruction but the add and the
4717 ;; load are 2 2 byte instructions.
4720 [(set (match_operand:DI 0 "d_operand")
4721 (mem:DI (plus:DI (match_dup 0)
4722 (match_operand:DI 1 "const_int_operand"))))]
4723 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4724 && !TARGET_DEBUG_D_MODE
4725 && ((INTVAL (operands[1]) < 0
4726 && INTVAL (operands[1]) >= -0x10)
4727 || (INTVAL (operands[1]) >= 32 * 8
4728 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4729 || (INTVAL (operands[1]) >= 0
4730 && INTVAL (operands[1]) < 32 * 8
4731 && (INTVAL (operands[1]) & 7) != 0))"
4732 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4733 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4735 HOST_WIDE_INT val = INTVAL (operands[1]);
4738 operands[2] = const0_rtx;
4739 else if (val >= 32 * 8)
4743 operands[1] = GEN_INT (0x8 + off);
4744 operands[2] = GEN_INT (val - off - 0x8);
4750 operands[1] = GEN_INT (off);
4751 operands[2] = GEN_INT (val - off);
4755 ;; 32-bit Integer moves
4757 ;; Unlike most other insns, the move insns can't be split with
4758 ;; different predicates, because register spilling and other parts of
4759 ;; the compiler, have memoized the insn number already.
4761 (define_expand "mov<mode>"
4762 [(set (match_operand:IMOVE32 0 "")
4763 (match_operand:IMOVE32 1 ""))]
4766 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4770 ;; The difference between these two is whether or not ints are allowed
4771 ;; in FP registers (off by default, use -mdebugh to enable).
4773 (define_insn "*mov<mode>_internal"
4774 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4775 (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!kbJ,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4777 && (register_operand (operands[0], <MODE>mode)
4778 || reg_or_0_operand (operands[1], <MODE>mode))"
4779 { return mips_output_move (operands[0], operands[1]); }
4780 [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore")
4781 (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*")
4782 (set_attr "mode" "SI")])
4784 (define_insn "*mov<mode>_mips16"
4785 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4786 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4788 && (register_operand (operands[0], <MODE>mode)
4789 || register_operand (operands[1], <MODE>mode))"
4790 { return mips_output_move (operands[0], operands[1]); }
4791 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4792 (set_attr "mode" "SI")])
4794 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4795 ;; when the original load is a 4 byte instruction but the add and the
4796 ;; load are 2 2 byte instructions.
4799 [(set (match_operand:SI 0 "d_operand")
4800 (mem:SI (plus:SI (match_dup 0)
4801 (match_operand:SI 1 "const_int_operand"))))]
4802 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4803 && ((INTVAL (operands[1]) < 0
4804 && INTVAL (operands[1]) >= -0x80)
4805 || (INTVAL (operands[1]) >= 32 * 4
4806 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4807 || (INTVAL (operands[1]) >= 0
4808 && INTVAL (operands[1]) < 32 * 4
4809 && (INTVAL (operands[1]) & 3) != 0))"
4810 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4811 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4813 HOST_WIDE_INT val = INTVAL (operands[1]);
4816 operands[2] = const0_rtx;
4817 else if (val >= 32 * 4)
4821 operands[1] = GEN_INT (0x7c + off);
4822 operands[2] = GEN_INT (val - off - 0x7c);
4828 operands[1] = GEN_INT (off);
4829 operands[2] = GEN_INT (val - off);
4833 ;; On the mips16, we can split a load of certain constants into a load
4834 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4838 [(set (match_operand:SI 0 "d_operand")
4839 (match_operand:SI 1 "const_int_operand"))]
4840 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4841 && INTVAL (operands[1]) >= 0x100
4842 && INTVAL (operands[1]) <= 0xff + 0x7f"
4843 [(set (match_dup 0) (match_dup 1))
4844 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4846 int val = INTVAL (operands[1]);
4848 operands[1] = GEN_INT (0xff);
4849 operands[2] = GEN_INT (val - 0xff);
4852 ;; MIPS4 supports loading and storing a floating point register from
4853 ;; the sum of two general registers. We use two versions for each of
4854 ;; these four instructions: one where the two general registers are
4855 ;; SImode, and one where they are DImode. This is because general
4856 ;; registers will be in SImode when they hold 32-bit values, but,
4857 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4858 ;; instructions will still work correctly.
4860 ;; ??? Perhaps it would be better to support these instructions by
4861 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4862 ;; these instructions can only be used to load and store floating
4863 ;; point registers, that would probably cause trouble in reload.
4865 (define_insn "*<ANYF:loadx>_<P:mode>"
4866 [(set (match_operand:ANYF 0 "register_operand" "=f")
4867 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4868 (match_operand:P 2 "register_operand" "d"))))]
4870 "<ANYF:loadx>\t%0,%1(%2)"
4871 [(set_attr "type" "fpidxload")
4872 (set_attr "mode" "<ANYF:UNITMODE>")])
4874 (define_insn "*<ANYF:storex>_<P:mode>"
4875 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4876 (match_operand:P 2 "register_operand" "d")))
4877 (match_operand:ANYF 0 "register_operand" "f"))]
4879 "<ANYF:storex>\t%0,%1(%2)"
4880 [(set_attr "type" "fpidxstore")
4881 (set_attr "mode" "<ANYF:UNITMODE>")])
4883 ;; Scaled indexed address load.
4884 ;; Per md.texi, we only need to look for a pattern with multiply in the
4885 ;; address expression, not shift.
4887 (define_insn "*lwxs"
4888 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4890 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4892 (match_operand:P 2 "register_operand" "d"))))]
4895 [(set_attr "type" "load")
4896 (set_attr "mode" "SI")])
4898 ;; 16-bit Integer moves
4900 ;; Unlike most other insns, the move insns can't be split with
4901 ;; different predicates, because register spilling and other parts of
4902 ;; the compiler, have memoized the insn number already.
4903 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4905 (define_expand "movhi"
4906 [(set (match_operand:HI 0 "")
4907 (match_operand:HI 1 ""))]
4910 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4914 (define_insn "*movhi_internal"
4915 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d")
4916 (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!kbJ,dJ,*d*J,*a"))]
4918 && (register_operand (operands[0], HImode)
4919 || reg_or_0_operand (operands[1], HImode))"
4920 { return mips_output_move (operands[0], operands[1]); }
4921 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4922 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4923 (set_attr "mode" "HI")])
4925 (define_insn "*movhi_mips16"
4926 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4927 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4929 && (register_operand (operands[0], HImode)
4930 || register_operand (operands[1], HImode))"
4931 { return mips_output_move (operands[0], operands[1]); }
4932 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4933 (set_attr "mode" "HI")])
4935 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4936 ;; when the original load is a 4 byte instruction but the add and the
4937 ;; load are 2 2 byte instructions.
4940 [(set (match_operand:HI 0 "d_operand")
4941 (mem:HI (plus:SI (match_dup 0)
4942 (match_operand:SI 1 "const_int_operand"))))]
4943 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4944 && ((INTVAL (operands[1]) < 0
4945 && INTVAL (operands[1]) >= -0x80)
4946 || (INTVAL (operands[1]) >= 32 * 2
4947 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4948 || (INTVAL (operands[1]) >= 0
4949 && INTVAL (operands[1]) < 32 * 2
4950 && (INTVAL (operands[1]) & 1) != 0))"
4951 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4952 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4954 HOST_WIDE_INT val = INTVAL (operands[1]);
4957 operands[2] = const0_rtx;
4958 else if (val >= 32 * 2)
4962 operands[1] = GEN_INT (0x7e + off);
4963 operands[2] = GEN_INT (val - off - 0x7e);
4969 operands[1] = GEN_INT (off);
4970 operands[2] = GEN_INT (val - off);
4974 ;; 8-bit Integer moves
4976 ;; Unlike most other insns, the move insns can't be split with
4977 ;; different predicates, because register spilling and other parts of
4978 ;; the compiler, have memoized the insn number already.
4979 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4981 (define_expand "movqi"
4982 [(set (match_operand:QI 0 "")
4983 (match_operand:QI 1 ""))]
4986 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4990 (define_insn "*movqi_internal"
4991 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d")
4992 (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!kbJ,dJ,*d*J,*a"))]
4994 && (register_operand (operands[0], QImode)
4995 || reg_or_0_operand (operands[1], QImode))"
4996 { return mips_output_move (operands[0], operands[1]); }
4997 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4998 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4999 (set_attr "mode" "QI")])
5001 (define_insn "*movqi_mips16"
5002 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
5003 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
5005 && (register_operand (operands[0], QImode)
5006 || register_operand (operands[1], QImode))"
5007 { return mips_output_move (operands[0], operands[1]); }
5008 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
5009 (set_attr "mode" "QI")])
5011 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
5012 ;; when the original load is a 4 byte instruction but the add and the
5013 ;; load are 2 2 byte instructions.
5016 [(set (match_operand:QI 0 "d_operand")
5017 (mem:QI (plus:SI (match_dup 0)
5018 (match_operand:SI 1 "const_int_operand"))))]
5019 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5020 && ((INTVAL (operands[1]) < 0
5021 && INTVAL (operands[1]) >= -0x80)
5022 || (INTVAL (operands[1]) >= 32
5023 && INTVAL (operands[1]) <= 31 + 0x7f))"
5024 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
5025 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
5027 HOST_WIDE_INT val = INTVAL (operands[1]);
5030 operands[2] = const0_rtx;
5033 operands[1] = GEN_INT (0x7f);
5034 operands[2] = GEN_INT (val - 0x7f);
5038 ;; 32-bit floating point moves
5040 (define_expand "movsf"
5041 [(set (match_operand:SF 0 "")
5042 (match_operand:SF 1 ""))]
5045 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
5049 (define_insn "movccf"
5050 [(set (match_operand:CCF 0 "nonimmediate_operand" "=f,f,m")
5051 (match_operand:CCF 1 "nonimmediate_operand" "f,m,f"))]
5053 { return mips_output_move (operands[0], operands[1]); }
5054 [(set_attr "move_type" "fmove,fpload,fpstore")])
5056 (define_insn "*movsf_hardfloat"
5057 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
5058 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
5060 && (register_operand (operands[0], SFmode)
5061 || reg_or_0_operand (operands[1], SFmode))"
5062 { return mips_output_move (operands[0], operands[1]); }
5063 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
5064 (set_attr "mode" "SF")])
5066 (define_insn "*movsf_softfloat"
5067 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
5068 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
5069 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
5070 && (register_operand (operands[0], SFmode)
5071 || reg_or_0_operand (operands[1], SFmode))"
5072 { return mips_output_move (operands[0], operands[1]); }
5073 [(set_attr "move_type" "move,load,store")
5074 (set_attr "mode" "SF")])
5076 (define_insn "*movsf_mips16"
5077 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
5078 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
5080 && (register_operand (operands[0], SFmode)
5081 || register_operand (operands[1], SFmode))"
5082 { return mips_output_move (operands[0], operands[1]); }
5083 [(set_attr "move_type" "move,move,move,load,store")
5084 (set_attr "mode" "SF")])
5086 ;; 64-bit floating point moves
5088 (define_expand "movdf"
5089 [(set (match_operand:DF 0 "")
5090 (match_operand:DF 1 ""))]
5093 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
5097 (define_insn "*movdf_hardfloat"
5098 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
5099 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
5100 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
5101 && (register_operand (operands[0], DFmode)
5102 || reg_or_0_operand (operands[1], DFmode))"
5103 { return mips_output_move (operands[0], operands[1]); }
5104 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
5105 (set_attr "mode" "DF")])
5107 (define_insn "*movdf_softfloat"
5108 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
5109 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
5110 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
5111 && (register_operand (operands[0], DFmode)
5112 || reg_or_0_operand (operands[1], DFmode))"
5113 { return mips_output_move (operands[0], operands[1]); }
5114 [(set_attr "move_type" "move,load,store")
5115 (set_attr "mode" "DF")])
5117 (define_insn "*movdf_mips16"
5118 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
5119 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
5121 && (register_operand (operands[0], DFmode)
5122 || register_operand (operands[1], DFmode))"
5123 { return mips_output_move (operands[0], operands[1]); }
5124 [(set_attr "move_type" "move,move,move,load,store")
5125 (set_attr "mode" "DF")])
5127 ;; 128-bit integer moves
5129 (define_expand "movti"
5130 [(set (match_operand:TI 0)
5131 (match_operand:TI 1))]
5134 if (mips_legitimize_move (TImode, operands[0], operands[1]))
5138 (define_insn "*movti"
5139 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d")
5140 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))]
5143 && (register_operand (operands[0], TImode)
5144 || reg_or_0_operand (operands[1], TImode))"
5145 { return mips_output_move (operands[0], operands[1]); }
5146 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo")
5148 (if_then_else (eq_attr "move_type" "imul")
5150 (const_string "TI")))])
5152 (define_insn "*movti_mips16"
5153 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
5154 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
5157 && (register_operand (operands[0], TImode)
5158 || register_operand (operands[1], TImode))"
5160 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
5161 (set_attr "mode" "TI")])
5163 ;; 128-bit floating point moves
5165 (define_expand "movtf"
5166 [(set (match_operand:TF 0)
5167 (match_operand:TF 1))]
5170 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
5174 ;; This pattern handles both hard- and soft-float cases.
5175 (define_insn "*movtf"
5176 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
5177 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
5180 && (register_operand (operands[0], TFmode)
5181 || reg_or_0_operand (operands[1], TFmode))"
5183 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
5184 (set_attr "mode" "TF")])
5186 (define_insn "*movtf_mips16"
5187 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
5188 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
5191 && (register_operand (operands[0], TFmode)
5192 || register_operand (operands[1], TFmode))"
5194 [(set_attr "move_type" "move,move,move,load,store")
5195 (set_attr "mode" "TF")])
5198 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
5199 (match_operand:MOVE64 1 "move_operand"))]
5200 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
5203 mips_split_move_insn (operands[0], operands[1], curr_insn);
5208 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
5209 (match_operand:MOVE128 1 "move_operand"))]
5210 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
5213 mips_split_move_insn (operands[0], operands[1], curr_insn);
5217 ;; When generating mips16 code, split moves of negative constants into
5218 ;; a positive "li" followed by a negation.
5220 [(set (match_operand 0 "d_operand")
5221 (match_operand 1 "const_int_operand"))]
5222 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
5226 (neg:SI (match_dup 2)))]
5228 operands[2] = gen_lowpart (SImode, operands[0]);
5229 operands[3] = GEN_INT (-INTVAL (operands[1]));
5232 ;; 64-bit paired-single floating point moves
5234 (define_expand "movv2sf"
5235 [(set (match_operand:V2SF 0)
5236 (match_operand:V2SF 1))]
5237 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
5239 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
5243 (define_insn "*movv2sf"
5244 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
5245 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
5247 && TARGET_PAIRED_SINGLE_FLOAT
5248 && (register_operand (operands[0], V2SFmode)
5249 || reg_or_0_operand (operands[1], V2SFmode))"
5250 { return mips_output_move (operands[0], operands[1]); }
5251 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
5252 (set_attr "mode" "DF")])
5254 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
5255 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
5257 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
5258 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
5259 ;; and the errata related to -mfix-vr4130.
5260 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
5261 [(set (match_operand:GPR 0 "register_operand" "=d")
5262 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")]
5265 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
5266 [(set_attr "type" "mfhi")
5267 (set_attr "mode" "<GPR:MODE>")])
5269 ;; Set the high part of a HI/LO value, given that the low part has
5270 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
5271 ;; why we can't just use (reg:GPR HI_REGNUM).
5272 (define_insn "mthi<GPR:mode>_<HILO:mode>"
5273 [(set (match_operand:HILO 0 "register_operand" "=x")
5274 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
5275 (match_operand:GPR 2 "register_operand" "l")]
5279 [(set_attr "type" "mthi")
5280 (set_attr "mode" "SI")])
5282 ;; Emit a doubleword move in which exactly one of the operands is
5283 ;; a floating-point register. We can't just emit two normal moves
5284 ;; because of the constraints imposed by the FPU register model;
5285 ;; see mips_cannot_change_mode_class for details. Instead, we keep
5286 ;; the FPR whole and use special patterns to refer to each word of
5287 ;; the other operand.
5289 (define_expand "move_doubleword_fpr<mode>"
5290 [(set (match_operand:SPLITF 0)
5291 (match_operand:SPLITF 1))]
5294 if (FP_REG_RTX_P (operands[0]))
5296 rtx low = mips_subword (operands[1], 0);
5297 rtx high = mips_subword (operands[1], 1);
5298 emit_insn (gen_load_low<mode> (operands[0], low));
5299 if (ISA_HAS_MXHC1 && !TARGET_64BIT)
5300 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
5302 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
5306 rtx low = mips_subword (operands[0], 0);
5307 rtx high = mips_subword (operands[0], 1);
5308 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
5309 if (ISA_HAS_MXHC1 && !TARGET_64BIT)
5310 emit_insn (gen_mfhc1<mode> (high, operands[1]));
5312 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
5317 ;; Load the low word of operand 0 with operand 1.
5318 (define_insn "load_low<mode>"
5319 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
5320 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
5324 operands[0] = mips_subword (operands[0], 0);
5325 return mips_output_move (operands[0], operands[1]);
5327 [(set_attr "move_type" "mtc,fpload")
5328 (set_attr "mode" "<HALFMODE>")])
5330 ;; Load the high word of operand 0 from operand 1, preserving the value
5332 (define_insn "load_high<mode>"
5333 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
5334 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
5335 (match_operand:SPLITF 2 "register_operand" "0,0")]
5339 operands[0] = mips_subword (operands[0], 1);
5340 return mips_output_move (operands[0], operands[1]);
5342 [(set_attr "move_type" "mtc,fpload")
5343 (set_attr "mode" "<HALFMODE>")])
5345 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
5346 ;; high word and 0 to store the low word.
5347 (define_insn "store_word<mode>"
5348 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
5349 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
5350 (match_operand 2 "const_int_operand")]
5351 UNSPEC_STORE_WORD))]
5354 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
5355 return mips_output_move (operands[0], operands[1]);
5357 [(set_attr "move_type" "mfc,fpstore")
5358 (set_attr "mode" "<HALFMODE>")])
5360 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
5361 ;; value in the low word.
5362 (define_insn "mthc1<mode>"
5363 [(set (match_operand:SPLITF 0 "register_operand" "=f")
5364 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
5365 (match_operand:SPLITF 2 "register_operand" "0")]
5367 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
5369 [(set_attr "move_type" "mtc")
5370 (set_attr "mode" "<HALFMODE>")])
5372 ;; Move high word of operand 1 to operand 0 using mfhc1.
5373 (define_insn "mfhc1<mode>"
5374 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
5375 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
5377 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
5379 [(set_attr "move_type" "mfc")
5380 (set_attr "mode" "<HALFMODE>")])
5382 ;; Move a constant that satisfies CONST_GP_P into operand 0.
5383 (define_expand "load_const_gp_<mode>"
5384 [(set (match_operand:P 0 "register_operand" "=d")
5385 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
5387 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
5388 ;; of _gp from the start of this function. Operand 1 is the incoming
5389 ;; function address.
5390 (define_insn_and_split "loadgp_newabi_<mode>"
5391 [(set (match_operand:P 0 "register_operand" "=&d")
5392 (unspec:P [(match_operand:P 1)
5393 (match_operand:P 2 "register_operand" "d")]
5395 "mips_current_loadgp_style () == LOADGP_NEWABI"
5396 { return mips_must_initialize_gp_p () ? "#" : ""; }
5397 "&& mips_must_initialize_gp_p ()"
5398 [(set (match_dup 0) (match_dup 3))
5399 (set (match_dup 0) (match_dup 4))
5400 (set (match_dup 0) (match_dup 5))]
5402 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
5403 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
5404 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
5406 [(set_attr "type" "ghost")])
5408 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
5409 (define_insn_and_split "loadgp_absolute_<mode>"
5410 [(set (match_operand:P 0 "register_operand" "=d")
5411 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
5412 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
5413 { return mips_must_initialize_gp_p () ? "#" : ""; }
5414 "&& mips_must_initialize_gp_p ()"
5417 mips_emit_move (operands[0], operands[1]);
5420 [(set_attr "type" "ghost")])
5422 ;; This blockage instruction prevents the gp load from being
5423 ;; scheduled after an implicit use of gp. It also prevents
5424 ;; the load from being deleted as dead.
5425 (define_insn "loadgp_blockage"
5426 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
5429 [(set_attr "type" "ghost")])
5431 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
5432 ;; and operand 1 is the __GOTT_INDEX__ symbol.
5433 (define_insn_and_split "loadgp_rtp_<mode>"
5434 [(set (match_operand:P 0 "register_operand" "=d")
5435 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
5436 (match_operand:P 2 "symbol_ref_operand")]
5438 "mips_current_loadgp_style () == LOADGP_RTP"
5439 { return mips_must_initialize_gp_p () ? "#" : ""; }
5440 "&& mips_must_initialize_gp_p ()"
5441 [(set (match_dup 0) (high:P (match_dup 3)))
5442 (set (match_dup 0) (unspec:P [(match_dup 0)
5443 (match_dup 3)] UNSPEC_LOAD_GOT))
5444 (set (match_dup 0) (unspec:P [(match_dup 0)
5445 (match_dup 4)] UNSPEC_LOAD_GOT))]
5447 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
5448 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
5450 [(set_attr "type" "ghost")])
5452 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
5453 ;; global pointer and operand 1 is the MIPS16 register that holds
5454 ;; the required value.
5455 (define_insn_and_split "copygp_mips16_<mode>"
5456 [(set (match_operand:P 0 "register_operand" "=y")
5457 (unspec:P [(match_operand:P 1 "register_operand" "d")]
5460 { return mips_must_initialize_gp_p () ? "#" : ""; }
5461 "&& mips_must_initialize_gp_p ()"
5462 [(set (match_dup 0) (match_dup 1))]
5464 [(set_attr "type" "ghost")])
5466 ;; A placeholder for where the cprestore instruction should go,
5467 ;; if we decide we need one. Operand 0 and operand 1 are as for
5468 ;; "cprestore". Operand 2 is a register that holds the gp value.
5470 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
5471 ;; otherwise any register that holds the correct value will do.
5472 (define_insn_and_split "potential_cprestore_<mode>"
5473 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5474 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5475 (match_operand:P 2 "register_operand" "d,d")]
5476 UNSPEC_POTENTIAL_CPRESTORE))
5477 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))]
5478 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
5479 { return mips_must_initialize_gp_p () ? "#" : ""; }
5480 "mips_must_initialize_gp_p ()"
5483 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
5484 operands[2], operands[3]);
5487 [(set_attr "type" "ghost")])
5489 ;; Emit a .cprestore directive, which normally expands to a single store
5490 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
5491 ;; for the cprestore slot. Operand 1 is the offset of the slot from
5492 ;; the stack pointer. (This is redundant with operand 0, but it makes
5493 ;; things a little simpler.)
5494 (define_insn "cprestore_<mode>"
5495 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5496 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5499 "TARGET_CPRESTORE_DIRECTIVE"
5501 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
5502 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
5504 return ".cprestore\t%1";
5506 [(set_attr "type" "store")
5507 (set_attr "insn_count" "1,3")])
5509 (define_insn "use_cprestore_<mode>"
5510 [(set (reg:P CPRESTORE_SLOT_REGNUM)
5511 (match_operand:P 0 "cprestore_load_slot_operand"))]
5514 [(set_attr "type" "ghost")])
5516 ;; Expand in-line code to clear the instruction cache between operand[0] and
5518 (define_expand "clear_cache"
5519 [(match_operand 0 "pmode_register_operand")
5520 (match_operand 1 "pmode_register_operand")]
5526 mips_expand_synci_loop (operands[0], operands[1]);
5527 emit_insn (gen_sync ());
5528 emit_insn (PMODE_INSN (gen_clear_hazard, ()));
5530 else if (mips_cache_flush_func && mips_cache_flush_func[0])
5532 rtx len = gen_reg_rtx (Pmode);
5533 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
5534 MIPS_ICACHE_SYNC (operands[0], len);
5540 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
5542 { return mips_output_sync (); })
5544 (define_insn "synci"
5545 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
5550 (define_insn "rdhwr_synci_step_<mode>"
5551 [(set (match_operand:P 0 "register_operand" "=d")
5552 (unspec_volatile [(const_int 1)]
5557 (define_insn "clear_hazard_<mode>"
5558 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
5559 (clobber (reg:P RETURN_ADDR_REGNUM))]
5562 return "%(%<bal\t1f\n"
5564 "1:\t<d>addiu\t$31,$31,12\n"
5568 [(set_attr "insn_count" "5")])
5570 ;; Cache operations for R4000-style caches.
5571 (define_insn "mips_cache"
5572 [(set (mem:BLK (scratch))
5573 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
5574 (match_operand:QI 1 "address_operand" "ZD")]
5575 UNSPEC_MIPS_CACHE))]
5579 ;; Similar, but with the operands hard-coded to an R10K cache barrier
5580 ;; operation. We keep the pattern distinct so that we can identify
5581 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
5582 ;; the operation is never inserted into a delay slot.
5583 (define_insn "r10k_cache_barrier"
5584 [(set (mem:BLK (scratch))
5585 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
5588 [(set_attr "can_delay" "no")])
5590 ;; Block moves, see mips.c for more details.
5591 ;; Argument 0 is the destination
5592 ;; Argument 1 is the source
5593 ;; Argument 2 is the length
5594 ;; Argument 3 is the alignment
5596 (define_expand "movmemsi"
5597 [(parallel [(set (match_operand:BLK 0 "general_operand")
5598 (match_operand:BLK 1 "general_operand"))
5599 (use (match_operand:SI 2 ""))
5600 (use (match_operand:SI 3 "const_int_operand"))])]
5601 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5603 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5610 ;; ....................
5614 ;; ....................
5616 (define_expand "<optab><mode>3"
5617 [(set (match_operand:GPR 0 "register_operand")
5618 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5619 (match_operand:SI 2 "arith_operand")))]
5622 /* On the mips16, a shift of more than 8 is a four byte instruction,
5623 so, for a shift between 8 and 16, it is just as fast to do two
5624 shifts of 8 or less. If there is a lot of shifting going on, we
5625 may win in CSE. Otherwise combine will put the shifts back
5626 together again. This can be called by mips_function_arg, so we must
5627 be careful not to allocate a new register if we've reached the
5631 && CONST_INT_P (operands[2])
5632 && INTVAL (operands[2]) > 8
5633 && INTVAL (operands[2]) <= 16
5634 && !reload_in_progress
5635 && !reload_completed)
5637 rtx temp = gen_reg_rtx (<MODE>mode);
5639 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5640 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5641 GEN_INT (INTVAL (operands[2]) - 8)));
5646 (define_insn "*<optab><mode>3"
5647 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
5648 (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d")
5649 (match_operand:SI 2 "arith_operand" "Uib3,dI")))]
5652 if (CONST_INT_P (operands[2]))
5653 operands[2] = GEN_INT (INTVAL (operands[2])
5654 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5656 return "<d><insn>\t%0,%1,%2";
5658 [(set_attr "type" "shift")
5659 (set_attr "compression" "<shift_compression>,none")
5660 (set_attr "mode" "<MODE>")])
5662 (define_insn "*<optab>si3_extend"
5663 [(set (match_operand:DI 0 "register_operand" "=d")
5665 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5666 (match_operand:SI 2 "arith_operand" "dI"))))]
5667 "TARGET_64BIT && !TARGET_MIPS16"
5669 if (CONST_INT_P (operands[2]))
5670 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5672 return "<insn>\t%0,%1,%2";
5674 [(set_attr "type" "shift")
5675 (set_attr "mode" "SI")])
5677 (define_insn "*<optab>si3_mips16"
5678 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
5679 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d,d")
5680 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5683 if (which_alternative == 0)
5684 return "<insn>\t%0,%2";
5686 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5687 return "<insn>\t%0,%1,%2";
5689 [(set_attr "type" "shift")
5690 (set_attr "mode" "SI")
5691 (set_attr "extended_mips16" "no,no,yes")])
5693 (define_insn "<GPR:d>lsa"
5694 [(set (match_operand:GPR 0 "register_operand" "=d")
5695 (plus:GPR (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
5696 (match_operand 2 "const_immlsa_operand" ""))
5697 (match_operand:GPR 3 "register_operand" "d")))]
5698 "ISA_HAS_<GPR:D>LSA"
5699 "<GPR:d>lsa\t%0,%1,%3,%2"
5700 [(set_attr "type" "arith")
5701 (set_attr "mode" "<GPR:MODE>")])
5703 ;; We need separate DImode MIPS16 patterns because of the irregularity
5705 (define_insn "*ashldi3_mips16"
5706 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5707 (ashift:DI (match_operand:DI 1 "register_operand" "0,d,d")
5708 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5709 "TARGET_64BIT && TARGET_MIPS16"
5711 if (which_alternative == 0)
5712 return "dsll\t%0,%2";
5714 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5715 return "dsll\t%0,%1,%2";
5717 [(set_attr "type" "shift")
5718 (set_attr "mode" "DI")
5719 (set_attr "extended_mips16" "no,no,yes")])
5721 (define_insn "*ashrdi3_mips16"
5722 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5723 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5724 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5725 "TARGET_64BIT && TARGET_MIPS16"
5727 if (CONST_INT_P (operands[2]))
5728 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5730 return "dsra\t%0,%2";
5732 [(set_attr "type" "shift")
5733 (set_attr "mode" "DI")
5734 (set_attr "extended_mips16" "no,no,yes")])
5736 (define_insn "*lshrdi3_mips16"
5737 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5738 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5739 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5740 "TARGET_64BIT && TARGET_MIPS16"
5742 if (CONST_INT_P (operands[2]))
5743 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5745 return "dsrl\t%0,%2";
5747 [(set_attr "type" "shift")
5748 (set_attr "mode" "DI")
5749 (set_attr "extended_mips16" "no,no,yes")])
5751 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5754 [(set (match_operand:GPR 0 "d_operand")
5755 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5756 (match_operand:GPR 2 "const_int_operand")))]
5757 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5758 && INTVAL (operands[2]) > 8
5759 && INTVAL (operands[2]) <= 16"
5760 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5761 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5762 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5764 ;; If we load a byte on the mips16 as a bitfield, the resulting
5765 ;; sequence of instructions is too complicated for combine, because it
5766 ;; involves four instructions: a load, a shift, a constant load into a
5767 ;; register, and an and (the key problem here is that the mips16 does
5768 ;; not have and immediate). We recognize a shift of a load in order
5769 ;; to make it simple enough for combine to understand.
5771 ;; The instruction count here is the worst case.
5772 (define_insn_and_split ""
5773 [(set (match_operand:SI 0 "register_operand" "=d")
5774 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5775 (match_operand:SI 2 "immediate_operand" "I")))]
5779 [(set (match_dup 0) (match_dup 1))
5780 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5782 [(set_attr "type" "load")
5783 (set_attr "mode" "SI")
5784 (set (attr "insn_count")
5785 (symbol_ref "mips_load_store_insns (operands[1], insn) + 2"))])
5787 (define_insn "rotr<mode>3"
5788 [(set (match_operand:GPR 0 "register_operand" "=d")
5789 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5790 (match_operand:SI 2 "arith_operand" "dI")))]
5793 if (CONST_INT_P (operands[2]))
5794 gcc_assert (INTVAL (operands[2]) >= 0
5795 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5797 return "<d>ror\t%0,%1,%2";
5799 [(set_attr "type" "shift")
5800 (set_attr "mode" "<MODE>")])
5802 (define_insn "bswaphi2"
5803 [(set (match_operand:HI 0 "register_operand" "=d")
5804 (bswap:HI (match_operand:HI 1 "register_operand" "d")))]
5807 [(set_attr "type" "shift")])
5809 (define_insn_and_split "bswapsi2"
5810 [(set (match_operand:SI 0 "register_operand" "=d")
5811 (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
5812 "ISA_HAS_WSBH && ISA_HAS_ROR"
5815 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
5816 (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
5818 [(set_attr "insn_count" "2")])
5820 (define_insn_and_split "bswapdi2"
5821 [(set (match_operand:DI 0 "register_operand" "=d")
5822 (bswap:DI (match_operand:DI 1 "register_operand" "d")))]
5823 "TARGET_64BIT && ISA_HAS_WSBH"
5826 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH))
5827 (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))]
5829 [(set_attr "insn_count" "2")])
5832 [(set (match_operand:SI 0 "register_operand" "=d")
5833 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))]
5836 [(set_attr "type" "shift")])
5839 [(set (match_operand:DI 0 "register_operand" "=d")
5840 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))]
5841 "TARGET_64BIT && ISA_HAS_WSBH"
5843 [(set_attr "type" "shift")])
5846 [(set (match_operand:DI 0 "register_operand" "=d")
5847 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))]
5848 "TARGET_64BIT && ISA_HAS_WSBH"
5850 [(set_attr "type" "shift")])
5853 ;; ....................
5855 ;; CONDITIONAL BRANCHES
5857 ;; ....................
5859 ;; Conditional branches on floating-point equality tests.
5861 (define_insn "*branch_fp_<mode>"
5864 (match_operator 1 "equality_operator"
5865 [(match_operand:FPCC 2 "register_operand" "<reg>")
5867 (label_ref (match_operand 0 "" ""))
5871 return mips_output_conditional_branch (insn, operands,
5872 MIPS_BRANCH ("b%F1", "%Z2%0"),
5873 MIPS_BRANCH ("b%W1", "%Z2%0"));
5875 [(set_attr "type" "branch")])
5877 (define_insn "*branch_fp_inverted_<mode>"
5880 (match_operator 1 "equality_operator"
5881 [(match_operand:FPCC 2 "register_operand" "<reg>")
5884 (label_ref (match_operand 0 "" ""))))]
5887 return mips_output_conditional_branch (insn, operands,
5888 MIPS_BRANCH ("b%W1", "%Z2%0"),
5889 MIPS_BRANCH ("b%F1", "%Z2%0"));
5891 [(set_attr "type" "branch")])
5893 ;; Conditional branches on ordered comparisons with zero.
5895 (define_insn "*branch_order<mode>"
5898 (match_operator 1 "order_operator"
5899 [(match_operand:GPR 2 "register_operand" "d,d")
5900 (match_operand:GPR 3 "reg_or_0_operand" "J,d")])
5901 (label_ref (match_operand 0 "" ""))
5904 { return mips_output_order_conditional_branch (insn, operands, false); }
5905 [(set_attr "type" "branch")
5906 (set_attr "compact_form" "maybe,always")
5907 (set_attr "hazard" "forbidden_slot")])
5909 (define_insn "*branch_order<mode>_inverted"
5912 (match_operator 1 "order_operator"
5913 [(match_operand:GPR 2 "register_operand" "d,d")
5914 (match_operand:GPR 3 "reg_or_0_operand" "J,d")])
5916 (label_ref (match_operand 0 "" ""))))]
5918 { return mips_output_order_conditional_branch (insn, operands, true); }
5919 [(set_attr "type" "branch")
5920 (set_attr "compact_form" "maybe,always")
5921 (set_attr "hazard" "forbidden_slot")])
5923 ;; Conditional branch on equality comparison.
5925 (define_insn "*branch_equality<mode>"
5928 (match_operator 1 "equality_operator"
5929 [(match_operand:GPR 2 "register_operand" "d")
5930 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5931 (label_ref (match_operand 0 "" ""))
5934 { return mips_output_equal_conditional_branch (insn, operands, false); }
5935 [(set_attr "type" "branch")
5936 (set_attr "compact_form" "maybe")
5937 (set_attr "hazard" "forbidden_slot")])
5939 (define_insn "*branch_equality<mode>_inverted"
5942 (match_operator 1 "equality_operator"
5943 [(match_operand:GPR 2 "register_operand" "d")
5944 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5946 (label_ref (match_operand 0 "" ""))))]
5948 { return mips_output_equal_conditional_branch (insn, operands, true); }
5949 [(set_attr "type" "branch")
5950 (set_attr "compact_form" "maybe")
5951 (set_attr "hazard" "forbidden_slot")])
5955 (define_insn "*branch_equality<mode>_mips16"
5958 (match_operator 1 "equality_operator"
5959 [(match_operand:GPR 2 "register_operand" "d,t")
5961 (label_ref (match_operand 0 "" ""))
5967 [(set_attr "type" "branch")])
5969 (define_insn "*branch_equality<mode>_mips16_inverted"
5972 (match_operator 1 "equality_operator"
5973 [(match_operand:GPR 2 "register_operand" "d,t")
5976 (label_ref (match_operand 0 "" ""))))]
5981 [(set_attr "type" "branch")])
5983 (define_expand "cbranch<mode>4"
5985 (if_then_else (match_operator 0 "comparison_operator"
5986 [(match_operand:GPR 1 "register_operand")
5987 (match_operand:GPR 2 "nonmemory_operand")])
5988 (label_ref (match_operand 3 ""))
5992 mips_expand_conditional_branch (operands);
5996 (define_expand "cbranch<mode>4"
5998 (if_then_else (match_operator 0 "comparison_operator"
5999 [(match_operand:SCALARF 1 "register_operand")
6000 (match_operand:SCALARF 2 "register_operand")])
6001 (label_ref (match_operand 3 ""))
6005 mips_expand_conditional_branch (operands);
6009 ;; Used to implement built-in functions.
6010 (define_expand "condjump"
6012 (if_then_else (match_operand 0)
6013 (label_ref (match_operand 1))
6016 ;; Branch if bit is set/clear.
6018 (define_insn "*branch_bit<bbv><mode>"
6021 (equality_op (zero_extract:GPR
6022 (match_operand:GPR 1 "register_operand" "d")
6024 (match_operand 2 "const_int_operand" ""))
6026 (label_ref (match_operand 0 ""))
6028 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
6031 mips_output_conditional_branch (insn, operands,
6032 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
6033 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
6035 [(set_attr "type" "branch")
6036 (set_attr "branch_likely" "no")])
6038 (define_insn "*branch_bit<bbv><mode>_inverted"
6041 (equality_op (zero_extract:GPR
6042 (match_operand:GPR 1 "register_operand" "d")
6044 (match_operand 2 "const_int_operand" ""))
6047 (label_ref (match_operand 0 ""))))]
6048 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
6051 mips_output_conditional_branch (insn, operands,
6052 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
6053 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
6055 [(set_attr "type" "branch")
6056 (set_attr "branch_likely" "no")])
6059 ;; ....................
6061 ;; SETTING A REGISTER FROM A COMPARISON
6063 ;; ....................
6065 ;; Destination is always set in SI mode.
6067 (define_expand "cstore<mode>4"
6068 [(set (match_operand:SI 0 "register_operand")
6069 (match_operator:SI 1 "mips_cstore_operator"
6070 [(match_operand:GPR 2 "register_operand")
6071 (match_operand:GPR 3 "nonmemory_operand")]))]
6074 mips_expand_scc (operands);
6078 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
6079 [(set (match_operand:GPR2 0 "register_operand" "=d")
6080 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
6082 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6084 [(set_attr "type" "slt")
6085 (set_attr "mode" "<GPR:MODE>")])
6087 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
6088 [(set (match_operand:GPR2 0 "register_operand" "=t")
6089 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
6091 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6093 [(set_attr "type" "slt")
6094 (set_attr "mode" "<GPR:MODE>")])
6096 ;; Generate sltiu unless using seq results in better code.
6097 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
6098 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
6099 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
6100 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
6106 [(set_attr "type" "slt")
6107 (set_attr "mode" "<GPR:MODE>")])
6109 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
6110 [(set (match_operand:GPR2 0 "register_operand" "=d")
6111 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
6113 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6115 [(set_attr "type" "slt")
6116 (set_attr "mode" "<GPR:MODE>")])
6118 ;; Generate sltu unless using sne results in better code.
6119 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
6120 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
6121 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
6122 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
6128 [(set_attr "type" "slt")
6129 (set_attr "mode" "<GPR:MODE>")])
6131 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
6132 [(set (match_operand:GPR2 0 "register_operand" "=d")
6133 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6134 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
6137 [(set_attr "type" "slt")
6138 (set_attr "mode" "<GPR:MODE>")])
6140 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
6141 [(set (match_operand:GPR2 0 "register_operand" "=t")
6142 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6143 (match_operand:GPR 2 "register_operand" "d")))]
6146 [(set_attr "type" "slt")
6147 (set_attr "mode" "<GPR:MODE>")])
6149 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
6150 [(set (match_operand:GPR2 0 "register_operand" "=d")
6151 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
6155 [(set_attr "type" "slt")
6156 (set_attr "mode" "<GPR:MODE>")])
6158 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
6159 [(set (match_operand:GPR2 0 "register_operand" "=d")
6160 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6161 (match_operand:GPR 2 "arith_operand" "dI")))]
6164 [(set_attr "type" "slt")
6165 (set_attr "mode" "<GPR:MODE>")])
6167 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
6168 [(set (match_operand:GPR2 0 "register_operand" "=t,t,t")
6169 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d,d")
6170 (match_operand:GPR 2 "arith_operand" "d,Uub8,I")))]
6173 [(set_attr "type" "slt")
6174 (set_attr "mode" "<GPR:MODE>")
6175 (set_attr "extended_mips16" "no,no,yes")])
6177 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
6178 [(set (match_operand:GPR2 0 "register_operand" "=d")
6179 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
6180 (match_operand:GPR 2 "sle_operand" "")))]
6183 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
6184 return "slt<u>\t%0,%1,%2";
6186 [(set_attr "type" "slt")
6187 (set_attr "mode" "<GPR:MODE>")])
6189 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
6190 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
6191 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
6192 (match_operand:GPR 2 "sle_operand" "Udb8,i")))]
6195 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
6196 return "slt<u>\t%1,%2";
6198 [(set_attr "type" "slt")
6199 (set_attr "mode" "<GPR:MODE>")
6200 (set_attr "extended_mips16" "no,yes")])
6203 ;; ....................
6205 ;; FLOATING POINT COMPARISONS
6207 ;; ....................
6209 (define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>"
6210 [(set (match_operand:FPCC 0 "register_operand" "=<reg>")
6211 (fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f")
6212 (match_operand:SCALARF 2 "register_operand" "f")))]
6214 "<fpcmp>.<fcond>.<fmt>\t%Z0%1,%2"
6215 [(set_attr "type" "fcmp")
6216 (set_attr "mode" "FPSW")])
6218 (define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>"
6219 [(set (match_operand:FPCC 0 "register_operand" "=<reg>")
6220 (swapped_fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f")
6221 (match_operand:SCALARF 2 "register_operand" "f")))]
6223 "<fpcmp>.<swapped_fcond>.<fmt>\t%Z0%2,%1"
6224 [(set_attr "type" "fcmp")
6225 (set_attr "mode" "FPSW")])
6228 ;; ....................
6230 ;; UNCONDITIONAL BRANCHES
6232 ;; ....................
6234 ;; Unconditional branches.
6236 (define_expand "jump"
6238 (label_ref (match_operand 0)))])
6240 (define_insn "*jump_absolute"
6242 (label_ref (match_operand 0)))]
6243 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
6245 if (get_attr_length (insn) <= 8)
6247 if (TARGET_CB_MAYBE)
6248 return MIPS_ABSOLUTE_JUMP ("%*b%:\t%l0");
6250 return MIPS_ABSOLUTE_JUMP ("%*b\t%l0%/");
6254 if (TARGET_CB_MAYBE && !final_sequence)
6255 return MIPS_ABSOLUTE_JUMP ("%*bc\t%l0");
6257 return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/");
6260 [(set_attr "type" "branch")
6261 (set_attr "compact_form" "maybe")])
6263 (define_insn "*jump_pic"
6265 (label_ref (match_operand 0)))]
6266 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
6268 if (get_attr_length (insn) <= 8)
6270 if (TARGET_CB_MAYBE)
6271 return "%*b%:\t%l0";
6273 return "%*b\t%l0%/";
6277 mips_output_load_label (operands[0]);
6278 if (TARGET_CB_MAYBE)
6279 return "%*jr%:\t%@%]";
6281 return "%*jr\t%@%/%]";
6284 [(set_attr "type" "branch")
6285 (set_attr "compact_form" "maybe")])
6287 ;; We need a different insn for the mips16, because a mips16 branch
6288 ;; does not have a delay slot.
6290 (define_insn "*jump_mips16"
6292 (label_ref (match_operand 0 "" "")))]
6295 [(set_attr "type" "branch")
6296 (set (attr "length")
6297 ;; This calculation is like the normal branch one, but the
6298 ;; range of the unextended instruction is [-0x800, 0x7fe] rather
6299 ;; than [-0x100, 0xfe]. This translates to a range of:
6301 ;; [-(0x800 - sizeof (branch)), 0x7fe]
6302 ;; == [-0x7fe, 0x7fe]
6304 ;; from the shorten_branches reference address. Long-branch
6305 ;; sequences will replace this one, so the minimum length
6306 ;; is one instruction shorter than for conditional branches.
6307 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
6308 (le (minus (pc) (match_dup 0)) (const_int 2046)))
6310 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
6311 (le (minus (pc) (match_dup 0)) (const_int 65532)))
6313 (and (match_test "TARGET_ABICALLS")
6314 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
6316 (match_test "Pmode == SImode")
6318 ] (const_int 22)))])
6320 (define_expand "indirect_jump"
6321 [(set (pc) (match_operand 0 "register_operand"))]
6324 operands[0] = force_reg (Pmode, operands[0]);
6325 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0])));
6329 (define_insn "indirect_jump_<mode>"
6330 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
6333 return mips_output_jump (operands, 0, -1, false);
6335 [(set_attr "type" "jump")
6336 (set_attr "mode" "none")])
6338 ;; A combined jump-and-move instruction, used for MIPS16 long-branch
6339 ;; sequences. Having a dedicated pattern is more convenient than
6340 ;; creating a SEQUENCE for this special case.
6341 (define_insn "indirect_jump_and_restore_<mode>"
6342 [(set (pc) (match_operand:P 1 "register_operand" "d"))
6343 (set (match_operand:P 0 "register_operand" "=d")
6344 (match_operand:P 2 "register_operand" "y"))]
6346 "%(%<jr\t%1\;move\t%0,%2%>%)"
6347 [(set_attr "type" "multi")
6348 (set_attr "extended_mips16" "yes")])
6350 (define_expand "tablejump"
6352 (match_operand 0 "register_operand"))
6353 (use (label_ref (match_operand 1 "")))]
6354 "!TARGET_MIPS16_SHORT_JUMP_TABLES"
6357 operands[0] = expand_binop (Pmode, add_optab, operands[0],
6358 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
6359 else if (TARGET_RTP_PIC)
6361 /* When generating RTP PIC, we use case table entries that are relative
6362 to the start of the function. Add the function's address to the
6364 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6365 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
6366 start, 0, 0, OPTAB_WIDEN);
6369 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1])));
6373 (define_insn "tablejump_<mode>"
6375 (match_operand:P 0 "register_operand" "d"))
6376 (use (label_ref (match_operand 1 "" "")))]
6379 return mips_output_jump (operands, 0, -1, false);
6381 [(set_attr "type" "jump")
6382 (set_attr "mode" "none")])
6384 ;; For MIPS16, we don't know whether a given jump table will use short or
6385 ;; word-sized offsets until late in compilation, when we are able to determine
6386 ;; the sizes of the insns which comprise the containing function. This
6387 ;; necessitates the use of the casesi rather than the tablejump pattern, since
6388 ;; the latter tries to calculate the index of the offset to jump through early
6389 ;; in compilation, i.e. at expand time, when nothing is known about the
6390 ;; eventual function layout.
6392 (define_expand "casesi"
6393 [(match_operand:SI 0 "register_operand" "") ; index to jump on
6394 (match_operand:SI 1 "const_int_operand" "") ; lower bound
6395 (match_operand:SI 2 "const_int_operand" "") ; total range
6396 (match_operand 3 "" "") ; table label
6397 (match_operand 4 "" "")] ; out of range label
6398 "TARGET_MIPS16_SHORT_JUMP_TABLES"
6400 if (operands[1] != const0_rtx)
6402 rtx reg = gen_reg_rtx (SImode);
6403 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode);
6405 if (!arith_operand (offset, SImode))
6406 offset = force_reg (SImode, offset);
6408 emit_insn (gen_addsi3 (reg, operands[0], offset));
6412 if (!arith_operand (operands[0], SImode))
6413 operands[0] = force_reg (SImode, operands[0]);
6415 emit_cmp_and_jump_insns (operands[0], operands[2], GTU,
6416 NULL_RTX, SImode, 1, operands[4]);
6417 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16,
6418 (operands[0], operands[3])));
6422 (define_insn "casesi_internal_mips16_<mode>"
6424 (unspec:P [(match_operand:SI 0 "register_operand" "d")
6425 (label_ref (match_operand 1 "" ""))]
6426 UNSPEC_CASESI_DISPATCH))
6427 (clobber (match_scratch:P 2 "=d"))
6428 (clobber (match_scratch:P 3 "=d"))]
6429 "TARGET_MIPS16_SHORT_JUMP_TABLES"
6431 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])));
6433 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
6435 switch (GET_MODE (diff_vec))
6438 output_asm_insn ("sll\t%3,%0,1", operands);
6439 output_asm_insn ("<d>la\t%2,%1", operands);
6440 output_asm_insn ("<d>addu\t%3,%2,%3", operands);
6441 output_asm_insn ("lh\t%3,0(%3)", operands);
6445 output_asm_insn ("sll\t%3,%0,2", operands);
6446 output_asm_insn ("<d>la\t%2,%1", operands);
6447 output_asm_insn ("<d>addu\t%3,%2,%3", operands);
6448 output_asm_insn ("lw\t%3,0(%3)", operands);
6455 output_asm_insn ("<d>addu\t%2,%2,%3", operands);
6457 if (GENERATE_MIPS16E)
6462 [(set (attr "insn_count")
6463 (if_then_else (match_test "GENERATE_MIPS16E")
6465 (const_string "7")))])
6467 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
6468 ;; While it is possible to either pull it off the stack (in the
6469 ;; o32 case) or recalculate it given t9 and our target label,
6470 ;; it takes 3 or 4 insns to do so.
6472 (define_expand "builtin_setjmp_setup"
6473 [(use (match_operand 0 "register_operand"))]
6478 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3);
6479 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
6483 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
6484 ;; that older code did recalculate the gp from $25. Continue to jump through
6485 ;; $25 for compatibility (we lose nothing by doing so).
6487 (define_expand "builtin_longjmp"
6488 [(use (match_operand 0 "register_operand"))]
6491 /* The elements of the buffer are, in order: */
6492 int W = GET_MODE_SIZE (Pmode);
6493 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6494 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W));
6495 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W));
6496 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W));
6497 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6498 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
6499 The target is bound to be using $28 as the global pointer
6500 but the current function might not be. */
6501 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
6503 /* This bit is similar to expand_builtin_longjmp except that it
6504 restores $gp as well. */
6505 mips_emit_move (hard_frame_pointer_rtx, fp);
6506 mips_emit_move (pv, lab);
6507 emit_stack_restore (SAVE_NONLOCAL, stack);
6508 mips_emit_move (gp, gpv);
6509 emit_use (hard_frame_pointer_rtx);
6510 emit_use (stack_pointer_rtx);
6512 emit_indirect_jump (pv);
6517 ;; ....................
6519 ;; Function prologue/epilogue
6521 ;; ....................
6524 (define_expand "prologue"
6528 mips_expand_prologue ();
6532 ;; Block any insns from being moved before this point, since the
6533 ;; profiling call to mcount can use various registers that aren't
6534 ;; saved or used to pass arguments.
6536 (define_insn "blockage"
6537 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
6540 [(set_attr "type" "ghost")
6541 (set_attr "mode" "none")])
6543 (define_insn "probe_stack_range_<P:mode>"
6544 [(set (match_operand:P 0 "register_operand" "=d")
6545 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
6546 (match_operand:P 2 "register_operand" "d")]
6547 UNSPEC_PROBE_STACK_RANGE))]
6549 { return mips_output_probe_stack_range (operands[0], operands[2]); }
6550 [(set_attr "type" "unknown")
6551 (set_attr "can_delay" "no")
6552 (set_attr "mode" "<MODE>")])
6554 (define_expand "epilogue"
6558 mips_expand_epilogue (false);
6562 (define_expand "sibcall_epilogue"
6566 mips_expand_epilogue (true);
6570 ;; Trivial return. Make it look like a normal return insn as that
6571 ;; allows jump optimizations to work better.
6573 (define_expand "return"
6575 "mips_can_use_return_insn ()"
6576 { mips_expand_before_return (); })
6578 (define_expand "simple_return"
6581 { mips_expand_before_return (); })
6583 (define_insn "*<optab>"
6587 operands[0] = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
6588 return mips_output_jump (operands, 0, -1, false);
6590 [(set_attr "type" "jump")
6591 (set_attr "mode" "none")])
6595 (define_insn "<optab>_internal"
6597 (use (match_operand 0 "pmode_register_operand" ""))]
6600 return mips_output_jump (operands, 0, -1, false);
6602 [(set_attr "type" "jump")
6603 (set_attr "mode" "none")])
6605 ;; Exception return.
6606 (define_insn "mips_eret"
6608 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
6611 [(set_attr "type" "trap")
6612 (set_attr "mode" "none")])
6614 ;; Debug exception return.
6615 (define_insn "mips_deret"
6617 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
6620 [(set_attr "type" "trap")
6621 (set_attr "mode" "none")])
6623 ;; Disable interrupts.
6624 (define_insn "mips_di"
6625 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
6628 [(set_attr "type" "trap")
6629 (set_attr "mode" "none")])
6631 ;; Execution hazard barrier.
6632 (define_insn "mips_ehb"
6633 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
6636 [(set_attr "type" "trap")
6637 (set_attr "mode" "none")])
6639 ;; Read GPR from previous shadow register set.
6640 (define_insn "mips_rdpgpr_<mode>"
6641 [(set (match_operand:P 0 "register_operand" "=d")
6642 (unspec_volatile:P [(match_operand:P 1 "register_operand" "d")]
6646 [(set_attr "type" "move")
6647 (set_attr "mode" "<MODE>")])
6649 ;; Move involving COP0 registers.
6650 (define_insn "cop0_move"
6651 [(set (match_operand:SI 0 "register_operand" "=B,d")
6652 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
6655 { return mips_output_move (operands[0], operands[1]); }
6656 [(set_attr "type" "mtc,mfc")
6657 (set_attr "mode" "SI")])
6659 ;; This is used in compiling the unwind routines.
6660 (define_expand "eh_return"
6661 [(use (match_operand 0 "general_operand"))]
6664 if (GET_MODE (operands[0]) != word_mode)
6665 operands[0] = convert_to_mode (word_mode, operands[0], 0);
6667 emit_insn (gen_eh_set_lr_di (operands[0]));
6669 emit_insn (gen_eh_set_lr_si (operands[0]));
6673 ;; Clobber the return address on the stack. We can't expand this
6674 ;; until we know where it will be put in the stack frame.
6676 (define_insn "eh_set_lr_si"
6677 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6678 (clobber (match_scratch:SI 1 "=&d"))]
6682 (define_insn "eh_set_lr_di"
6683 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6684 (clobber (match_scratch:DI 1 "=&d"))]
6689 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
6690 (clobber (match_scratch 1))]
6694 mips_set_return_address (operands[0], operands[1]);
6698 (define_expand "exception_receiver"
6702 /* See the comment above load_call<mode> for details. */
6703 emit_insn (gen_set_got_version ());
6705 /* If we have a call-clobbered $gp, restore it from its save slot. */
6706 if (HAVE_restore_gp_si)
6707 emit_insn (gen_restore_gp_si ());
6708 else if (HAVE_restore_gp_di)
6709 emit_insn (gen_restore_gp_di ());
6713 (define_expand "nonlocal_goto_receiver"
6717 /* See the comment above load_call<mode> for details. */
6718 emit_insn (gen_set_got_version ());
6722 ;; Restore $gp from its .cprestore stack slot. The instruction remains
6723 ;; volatile until all uses of $28 are exposed.
6724 (define_insn_and_split "restore_gp_<mode>"
6726 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP))
6727 (clobber (match_scratch:P 0 "=&d"))]
6728 "TARGET_CALL_CLOBBERED_GP"
6730 "&& epilogue_completed"
6733 mips_restore_gp_from_cprestore_slot (operands[0]);
6736 [(set_attr "type" "ghost")])
6738 ;; Move between $gp and its register save slot.
6739 (define_insn_and_split "move_gp<mode>"
6740 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
6741 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
6744 { return mips_must_initialize_gp_p () ? "#" : ""; }
6745 "mips_must_initialize_gp_p ()"
6748 mips_emit_move (operands[0], operands[1]);
6751 [(set_attr "type" "ghost")])
6754 ;; ....................
6758 ;; ....................
6760 ;; Instructions to load a call address from the GOT. The address might
6761 ;; point to a function or to a lazy binding stub. In the latter case,
6762 ;; the stub will use the dynamic linker to resolve the function, which
6763 ;; in turn will change the GOT entry to point to the function's real
6766 ;; This means that every call, even pure and constant ones, can
6767 ;; potentially modify the GOT entry. And once a stub has been called,
6768 ;; we must not call it again.
6770 ;; We represent this restriction using an imaginary, fixed, call-saved
6771 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
6772 ;; live throughout the function and to change its value after every
6773 ;; potential call site. This stops any rtx value that uses the register
6774 ;; from being computed before an earlier call. To do this, we:
6776 ;; - Ensure that the register is live on entry to the function,
6777 ;; so that it is never thought to be used uninitalized.
6779 ;; - Ensure that the register is live on exit from the function,
6780 ;; so that it is live throughout.
6782 ;; - Make each call (lazily-bound or not) use the current value
6783 ;; of GOT_VERSION_REGNUM, so that updates of the register are
6784 ;; not moved across call boundaries.
6786 ;; - Add "ghost" definitions of the register to the beginning of
6787 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
6788 ;; edges may involve calls that normal paths don't. (E.g. the
6789 ;; unwinding code that handles a non-call exception may change
6790 ;; lazily-bound GOT entries.) We do this by making the
6791 ;; exception_receiver and nonlocal_goto_receiver expanders emit
6792 ;; a set_got_version instruction.
6794 ;; - After each call (lazily-bound or not), use a "ghost"
6795 ;; update_got_version instruction to change the register's value.
6796 ;; This instruction mimics the _possible_ effect of the dynamic
6797 ;; resolver during the call and it remains live even if the call
6798 ;; itself becomes dead.
6800 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
6801 ;; The register is therefore not a valid register_operand
6802 ;; and cannot be moved to or from other registers.
6804 (define_insn "load_call<mode>"
6805 [(set (match_operand:P 0 "register_operand" "=d")
6806 (unspec:P [(match_operand:P 1 "register_operand" "d")
6807 (match_operand:P 2 "immediate_operand" "")
6808 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
6810 "<load>\t%0,%R2(%1)"
6811 [(set_attr "got" "load")
6812 (set_attr "mode" "<MODE>")])
6814 (define_insn "set_got_version"
6815 [(set (reg:SI GOT_VERSION_REGNUM)
6816 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
6819 [(set_attr "type" "ghost")])
6821 (define_insn "update_got_version"
6822 [(set (reg:SI GOT_VERSION_REGNUM)
6823 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
6826 [(set_attr "type" "ghost")])
6828 ;; Sibling calls. All these patterns use jump instructions.
6830 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
6831 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
6832 ;; is defined in terms of call_insn_operand, the same is true of the
6835 ;; When we use an indirect jump, we need a register that will be
6836 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
6837 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
6838 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
6841 (define_expand "sibcall"
6842 [(parallel [(call (match_operand 0 "")
6843 (match_operand 1 ""))
6844 (use (match_operand 2 "")) ;; next_arg_reg
6845 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6848 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
6849 operands[1], operands[2], false);
6853 (define_insn "sibcall_internal"
6854 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
6855 (match_operand 1 "" ""))]
6856 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6857 { return mips_output_jump (operands, 0, 1, false); }
6858 [(set_attr "jal" "indirect,direct")
6859 (set_attr "jal_macro" "no")])
6861 (define_expand "sibcall_value"
6862 [(parallel [(set (match_operand 0 "")
6863 (call (match_operand 1 "")
6864 (match_operand 2 "")))
6865 (use (match_operand 3 ""))])] ;; next_arg_reg
6868 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
6869 operands[2], operands[3], false);
6873 (define_insn "sibcall_value_internal"
6874 [(set (match_operand 0 "register_operand" "")
6875 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6876 (match_operand 2 "" "")))]
6877 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6878 { return mips_output_jump (operands, 1, 2, false); }
6879 [(set_attr "jal" "indirect,direct")
6880 (set_attr "jal_macro" "no")])
6882 (define_insn "sibcall_value_multiple_internal"
6883 [(set (match_operand 0 "register_operand" "")
6884 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6885 (match_operand 2 "" "")))
6886 (set (match_operand 3 "register_operand" "")
6887 (call (mem:SI (match_dup 1))
6889 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6890 { return mips_output_jump (operands, 1, 2, false); }
6891 [(set_attr "jal" "indirect,direct")
6892 (set_attr "jal_macro" "no")])
6894 (define_expand "call"
6895 [(parallel [(call (match_operand 0 "")
6896 (match_operand 1 ""))
6897 (use (match_operand 2 "")) ;; next_arg_reg
6898 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6901 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6902 operands[1], operands[2], false);
6906 ;; This instruction directly corresponds to an assembly-language "jal".
6907 ;; There are four cases:
6910 ;; Both symbolic and register destinations are OK. The pattern
6911 ;; always expands to a single mips instruction.
6913 ;; - -mabicalls/-mno-explicit-relocs:
6914 ;; Again, both symbolic and register destinations are OK.
6915 ;; The call is treated as a multi-instruction black box.
6917 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6918 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6921 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6922 ;; Only "jal $25" is allowed. The call is actually two instructions:
6923 ;; "jalr $25" followed by an insn to reload $gp.
6925 ;; In the last case, we can generate the individual instructions with
6926 ;; a define_split. There are several things to be wary of:
6928 ;; - We can't expose the load of $gp before reload. If we did,
6929 ;; it might get removed as dead, but reload can introduce new
6930 ;; uses of $gp by rematerializing constants.
6932 ;; - We shouldn't restore $gp after calls that never return.
6933 ;; It isn't valid to insert instructions between a noreturn
6934 ;; call and the following barrier.
6936 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6937 ;; instruction preserves $gp and so have no effect on its liveness.
6938 ;; But once we generate the separate insns, it becomes obvious that
6939 ;; $gp is not live on entry to the call.
6941 (define_insn_and_split "call_internal"
6942 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6943 (match_operand 1 "" ""))
6944 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6947 return (TARGET_SPLIT_CALLS ? "#"
6948 : mips_output_jump (operands, 0, 1, true));
6950 "reload_completed && TARGET_SPLIT_CALLS"
6953 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6956 [(set_attr "jal" "indirect,direct")])
6958 (define_insn "call_split"
6959 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6960 (match_operand 1 "" ""))
6961 (clobber (reg:SI RETURN_ADDR_REGNUM))
6962 (clobber (reg:SI 28))]
6963 "TARGET_SPLIT_CALLS"
6964 { return mips_output_jump (operands, 0, 1, true); }
6965 [(set_attr "jal" "indirect,direct")
6966 (set_attr "jal_macro" "no")])
6968 ;; A pattern for calls that must be made directly. It is used for
6969 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6970 ;; stub; the linker relies on the call relocation type to detect when
6971 ;; such redirection is needed.
6972 (define_insn_and_split "call_internal_direct"
6973 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6976 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6979 return (TARGET_SPLIT_CALLS ? "#"
6980 : mips_output_jump (operands, 0, -1, true));
6982 "reload_completed && TARGET_SPLIT_CALLS"
6985 mips_split_call (curr_insn,
6986 gen_call_direct_split (operands[0], operands[1]));
6989 [(set_attr "jal" "direct")])
6991 (define_insn "call_direct_split"
6992 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6995 (clobber (reg:SI RETURN_ADDR_REGNUM))
6996 (clobber (reg:SI 28))]
6997 "TARGET_SPLIT_CALLS"
6998 { return mips_output_jump (operands, 0, -1, true); }
6999 [(set_attr "jal" "direct")
7000 (set_attr "jal_macro" "no")])
7002 (define_expand "call_value"
7003 [(parallel [(set (match_operand 0 "")
7004 (call (match_operand 1 "")
7005 (match_operand 2 "")))
7006 (use (match_operand 3 ""))])] ;; next_arg_reg
7009 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
7010 operands[2], operands[3], false);
7014 ;; See comment for call_internal.
7015 (define_insn_and_split "call_value_internal"
7016 [(set (match_operand 0 "register_operand" "")
7017 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7018 (match_operand 2 "" "")))
7019 (clobber (reg:SI RETURN_ADDR_REGNUM))]
7022 return (TARGET_SPLIT_CALLS ? "#"
7023 : mips_output_jump (operands, 1, 2, true));
7025 "reload_completed && TARGET_SPLIT_CALLS"
7028 mips_split_call (curr_insn,
7029 gen_call_value_split (operands[0], operands[1],
7033 [(set_attr "jal" "indirect,direct")])
7035 (define_insn "call_value_split"
7036 [(set (match_operand 0 "register_operand" "")
7037 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7038 (match_operand 2 "" "")))
7039 (clobber (reg:SI RETURN_ADDR_REGNUM))
7040 (clobber (reg:SI 28))]
7041 "TARGET_SPLIT_CALLS"
7042 { return mips_output_jump (operands, 1, 2, true); }
7043 [(set_attr "jal" "indirect,direct")
7044 (set_attr "jal_macro" "no")])
7046 ;; See call_internal_direct.
7047 (define_insn_and_split "call_value_internal_direct"
7048 [(set (match_operand 0 "register_operand")
7049 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
7052 (clobber (reg:SI RETURN_ADDR_REGNUM))]
7055 return (TARGET_SPLIT_CALLS ? "#"
7056 : mips_output_jump (operands, 1, -1, true));
7058 "reload_completed && TARGET_SPLIT_CALLS"
7061 mips_split_call (curr_insn,
7062 gen_call_value_direct_split (operands[0], operands[1],
7066 [(set_attr "jal" "direct")])
7068 (define_insn "call_value_direct_split"
7069 [(set (match_operand 0 "register_operand")
7070 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
7073 (clobber (reg:SI RETURN_ADDR_REGNUM))
7074 (clobber (reg:SI 28))]
7075 "TARGET_SPLIT_CALLS"
7076 { return mips_output_jump (operands, 1, -1, true); }
7077 [(set_attr "jal" "direct")
7078 (set_attr "jal_macro" "no")])
7080 ;; See comment for call_internal.
7081 (define_insn_and_split "call_value_multiple_internal"
7082 [(set (match_operand 0 "register_operand" "")
7083 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7084 (match_operand 2 "" "")))
7085 (set (match_operand 3 "register_operand" "")
7086 (call (mem:SI (match_dup 1))
7088 (clobber (reg:SI RETURN_ADDR_REGNUM))]
7091 return (TARGET_SPLIT_CALLS ? "#"
7092 : mips_output_jump (operands, 1, 2, true));
7094 "reload_completed && TARGET_SPLIT_CALLS"
7097 mips_split_call (curr_insn,
7098 gen_call_value_multiple_split (operands[0], operands[1],
7099 operands[2], operands[3]));
7102 [(set_attr "jal" "indirect,direct")])
7104 (define_insn "call_value_multiple_split"
7105 [(set (match_operand 0 "register_operand" "")
7106 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7107 (match_operand 2 "" "")))
7108 (set (match_operand 3 "register_operand" "")
7109 (call (mem:SI (match_dup 1))
7111 (clobber (reg:SI RETURN_ADDR_REGNUM))
7112 (clobber (reg:SI 28))]
7113 "TARGET_SPLIT_CALLS"
7114 { return mips_output_jump (operands, 1, 2, true); }
7115 [(set_attr "jal" "indirect,direct")
7116 (set_attr "jal_macro" "no")])
7118 ;; Call subroutine returning any type.
7120 (define_expand "untyped_call"
7121 [(parallel [(call (match_operand 0 "")
7123 (match_operand 1 "")
7124 (match_operand 2 "")])]
7129 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
7131 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7133 rtx set = XVECEXP (operands[2], 0, i);
7134 mips_emit_move (SET_DEST (set), SET_SRC (set));
7137 emit_insn (gen_blockage ());
7142 ;; ....................
7146 ;; ....................
7150 (define_insn "prefetch"
7151 [(prefetch (match_operand:QI 0 "address_operand" "ZD")
7152 (match_operand 1 "const_int_operand" "n")
7153 (match_operand 2 "const_int_operand" "n"))]
7154 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
7156 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
7158 /* Loongson ext2 implementation pref insnstructions. */
7159 if (TARGET_LOONGSON_EXT2)
7161 operands[1] = mips_loongson_ext2_prefetch_cookie (operands[1],
7163 return "pref\t%1, %a0";
7165 /* Loongson 2[ef] and Loongson ext use load to $0 for prefetching. */
7167 return "ld\t$0,%a0";
7169 return "lw\t$0,%a0";
7171 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
7172 return "pref\t%1,%a0";
7174 [(set_attr "type" "prefetch")])
7176 (define_insn "*prefetch_indexed_<mode>"
7177 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
7178 (match_operand:P 1 "register_operand" "d"))
7179 (match_operand 2 "const_int_operand" "n")
7180 (match_operand 3 "const_int_operand" "n"))]
7181 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7183 if (TARGET_LOONGSON_EXT || TARGET_LOONGSON_EXT2)
7185 /* Loongson ext2 implementation pref insnstructions. */
7186 if (TARGET_LOONGSON_EXT2)
7188 operands[2] = mips_loongson_ext2_prefetch_cookie (operands[2],
7190 return "prefx\t%2,%1(%0)";
7192 /* Loongson Loongson ext use index load to $0 for prefetching. */
7194 return "gsldx\t$0,0(%0,%1)";
7196 return "gslwx\t$0,0(%0,%1)";
7198 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
7199 return "prefx\t%2,%1(%0)";
7201 [(set_attr "type" "prefetchx")])
7207 [(set_attr "type" "nop")
7208 (set_attr "mode" "none")])
7210 ;; Like nop, but commented out when outside a .set noreorder block.
7211 (define_insn "hazard_nop"
7215 if (mips_noreorder.nesting_level > 0)
7220 [(set_attr "type" "nop")])
7222 ;; The `.insn' pseudo-op.
7223 (define_insn "insn_pseudo"
7224 [(unspec_volatile [(const_int 0)] UNSPEC_INSN_PSEUDO)]
7227 [(set_attr "mode" "none")
7228 (set_attr "insn_count" "0")])
7230 ;; MIPS4 Conditional move instructions.
7232 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
7233 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7235 (match_operator 4 "equality_operator"
7236 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
7238 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
7239 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
7244 [(set_attr "type" "condmove")
7245 (set_attr "mode" "<GPR:MODE>")])
7247 (define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne"
7248 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7250 (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>")
7251 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
7252 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
7257 [(set_attr "type" "condmove")
7258 (set_attr "mode" "<GPR:MODE>")])
7260 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
7261 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
7262 (if_then_else:SCALARF
7263 (match_operator 4 "equality_operator"
7264 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
7266 (match_operand:SCALARF 2 "register_operand" "f,0")
7267 (match_operand:SCALARF 3 "register_operand" "0,f")))]
7268 "ISA_HAS_FP_CONDMOVE"
7270 mov%T4.<fmt>\t%0,%2,%1
7271 mov%t4.<fmt>\t%0,%3,%1"
7272 [(set_attr "type" "condmove")
7273 (set_attr "mode" "<SCALARF:MODE>")])
7275 (define_insn "*sel<code><GPR:mode>_using_<GPR2:mode>"
7276 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7278 (equality_op:GPR2 (match_operand:GPR2 1 "register_operand" "d,d")
7280 (match_operand:GPR 2 "reg_or_0_operand" "d,J")
7281 (match_operand:GPR 3 "reg_or_0_operand" "J,d")))]
7283 && (register_operand (operands[2], <GPR:MODE>mode)
7284 != register_operand (operands[3], <GPR:MODE>mode))"
7288 [(set_attr "type" "condmove")
7289 (set_attr "mode" "<GPR:MODE>")])
7291 ;; sel.fmt copies the 3rd argument when the 1st is non-zero and the 2nd
7292 ;; argument if the 1st is zero. This means operand 2 and 3 are
7293 ;; inverted in the instruction.
7295 (define_insn "*sel<mode>"
7296 [(set (match_operand:SCALARF 0 "register_operand" "=f,f,f")
7297 (if_then_else:SCALARF
7298 (ne:CCF (match_operand:CCF 1 "register_operand" "0,f,f")
7300 (match_operand:SCALARF 2 "reg_or_0_operand" "f,G,f")
7301 (match_operand:SCALARF 3 "reg_or_0_operand" "f,f,G")))]
7302 "ISA_HAS_SEL && ISA_HAS_CCF"
7305 seleqz.<fmt>\t%0,%3,%1
7306 selnez.<fmt>\t%0,%2,%1"
7307 [(set_attr "type" "condmove")
7308 (set_attr "mode" "<SCALARF:MODE>")])
7310 ;; These are the main define_expand's used to make conditional moves.
7312 (define_expand "mov<mode>cc"
7313 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
7314 (set (match_operand:GPR 0 "register_operand")
7315 (if_then_else:GPR (match_dup 5)
7316 (match_operand:GPR 2 "reg_or_0_operand")
7317 (match_operand:GPR 3 "reg_or_0_operand")))]
7318 "ISA_HAS_CONDMOVE || ISA_HAS_SEL"
7320 if (!ISA_HAS_FP_CONDMOVE
7321 && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0))))
7324 mips_expand_conditional_move (operands);
7328 (define_expand "mov<mode>cc"
7329 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
7330 (set (match_operand:SCALARF 0 "register_operand")
7331 (if_then_else:SCALARF (match_dup 5)
7332 (match_operand:SCALARF 2 "reg_or_0_operand")
7333 (match_operand:SCALARF 3 "reg_or_0_operand")))]
7334 "ISA_HAS_FP_CONDMOVE
7335 || (ISA_HAS_SEL && ISA_HAS_CCF)"
7337 if (ISA_HAS_SEL && !FLOAT_MODE_P (GET_MODE (XEXP (operands[1], 0))))
7340 /* Workaround an LRA bug which means that tied operands in the sel.fmt
7341 pattern lead to the double precision destination of sel.d getting
7342 reloaded with the full register file usable and the restrictions on
7343 whether the CCFmode input can be used in odd-numbered single-precision
7344 registers are ignored. For consistency reasons the CCF mode values
7345 must be guaranteed to only exist in the even-registers because of
7346 the unusual duality between single and double precision values. */
7347 if (ISA_HAS_SEL && <MODE>mode == DFmode
7348 && (!TARGET_ODD_SPREG || TARGET_FLOATXX))
7351 mips_expand_conditional_move (operands);
7356 ;; ....................
7358 ;; mips16 inline constant tables
7360 ;; ....................
7363 (define_insn "consttable"
7364 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
7368 [(set_attr "mode" "none")
7369 (set_attr "insn_count" "0")])
7371 (define_insn "consttable_end"
7372 [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
7373 UNSPEC_CONSTTABLE_END)]
7376 [(set_attr "mode" "none")
7377 (set_attr "insn_count" "0")])
7379 (define_insn "consttable_tls_reloc"
7380 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "")
7381 (match_operand 1 "const_int_operand" "")]
7382 UNSPEC_CONSTTABLE_INT)]
7383 "TARGET_MIPS16_PCREL_LOADS"
7384 { return mips_output_tls_reloc_directive (&operands[0]); }
7385 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
7387 (define_insn "consttable_int"
7388 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
7389 (match_operand 1 "const_int_operand" "")]
7390 UNSPEC_CONSTTABLE_INT)]
7393 assemble_integer (mips_strip_unspec_address (operands[0]),
7394 INTVAL (operands[1]),
7395 BITS_PER_UNIT * INTVAL (operands[1]), 1);
7398 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
7400 (define_insn "consttable_float"
7401 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
7402 UNSPEC_CONSTTABLE_FLOAT)]
7405 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
7406 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
7407 as_a <scalar_float_mode> (GET_MODE (operands[0])),
7408 GET_MODE_BITSIZE (GET_MODE (operands[0])));
7411 [(set (attr "length")
7412 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
7414 (define_insn "align"
7415 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
7418 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
7421 [(match_operand 0 "small_data_pattern")]
7424 { operands[0] = mips_rewrite_small_data (operands[0]); })
7427 ;; ....................
7429 ;; MIPS16e Save/Restore
7431 ;; ....................
7434 (define_insn "*mips16e_save_restore"
7435 [(match_parallel 0 ""
7436 [(set (match_operand:SI 1 "register_operand")
7437 (plus:SI (match_dup 1)
7438 (match_operand:SI 2 "const_int_operand")))])]
7439 "operands[1] == stack_pointer_rtx
7440 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
7441 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
7442 [(set_attr "type" "arith")
7443 (set_attr "extended_mips16" "yes")])
7445 ;; Thread-Local Storage
7447 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
7448 ;; MIPS architecture defines this register, and no current
7449 ;; implementation provides it; instead, any OS which supports TLS is
7450 ;; expected to trap and emulate this instruction. rdhwr is part of the
7451 ;; MIPS 32r2 specification, but we use it on any architecture because
7452 ;; we expect it to be emulated. Use .set to force the assembler to
7455 ;; We do not use a constraint to force the destination to be $3
7456 ;; because $3 can appear explicitly as a function return value.
7457 ;; If we leave the use of $3 implicit in the constraints until
7458 ;; reload, we may end up making a $3 return value live across
7459 ;; the instruction, leading to a spill failure when reloading it.
7460 (define_insn_and_split "tls_get_tp_<mode>"
7461 [(set (match_operand:P 0 "register_operand" "=d")
7462 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
7463 (clobber (reg:P TLS_GET_TP_REGNUM))]
7464 "HAVE_AS_TLS && !TARGET_MIPS16"
7466 "&& reload_completed"
7467 [(set (reg:P TLS_GET_TP_REGNUM)
7468 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
7469 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
7471 [(set_attr "type" "unknown")
7472 (set_attr "mode" "<MODE>")
7473 (set_attr "insn_count" "2")])
7475 (define_insn "*tls_get_tp_<mode>_split"
7476 [(set (reg:P TLS_GET_TP_REGNUM)
7477 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
7478 "HAVE_AS_TLS && !TARGET_MIPS16"
7480 if (mips_isa_rev >= 2)
7481 return "rdhwr\t$3,$29";
7483 return ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop";
7485 [(set_attr "type" "unknown")
7486 ; Since rdhwr always generates a trap for now, putting it in a delay
7487 ; slot would make the kernel's emulation of it much slower.
7488 (set_attr "can_delay" "no")
7489 (set_attr "mode" "<MODE>")])
7491 ;; In MIPS16 mode, the TLS base pointer is accessed by a
7492 ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not
7493 ;; accessible in MIPS16.
7495 ;; This is not represented as a call insn, to avoid the
7496 ;; unnecesarry clobbering of caller-save registers by a
7497 ;; function consisting only of: "rdhwr $3,$29; j $31; nop;"
7499 ;; A $25 clobber is added to cater for a $25 load stub added by the
7500 ;; linker to __mips16_rdhwr when the call is made from non-PIC code.
7502 (define_insn_and_split "tls_get_tp_mips16_<mode>"
7503 [(set (match_operand:P 0 "register_operand" "=d")
7504 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")]
7506 (clobber (reg:P TLS_GET_TP_REGNUM))
7507 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7508 (clobber (reg:P RETURN_ADDR_REGNUM))]
7509 "HAVE_AS_TLS && TARGET_MIPS16"
7511 "&& reload_completed"
7512 [(parallel [(set (reg:P TLS_GET_TP_REGNUM)
7513 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP))
7514 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7515 (clobber (reg:P RETURN_ADDR_REGNUM))])
7516 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
7518 [(set_attr "type" "multi")
7519 (set_attr "insn_count" "4")
7520 (set_attr "mode" "<MODE>")])
7522 (define_insn "*tls_get_tp_mips16_call_<mode>"
7523 [(set (reg:P TLS_GET_TP_REGNUM)
7524 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")]
7526 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7527 (clobber (reg:P RETURN_ADDR_REGNUM))]
7528 "HAVE_AS_TLS && TARGET_MIPS16"
7529 { return mips_output_jump (operands, 0, -1, true); }
7530 [(set_attr "type" "call")
7531 (set_attr "insn_count" "3")
7532 (set_attr "mode" "<MODE>")])
7534 ;; Named pattern for expanding thread pointer reference.
7535 (define_expand "get_thread_pointer<mode>"
7536 [(match_operand:P 0 "register_operand" "=d")]
7539 mips_expand_thread_pointer (operands[0]);
7543 ;; __builtin_mips_get_fcsr: move the FCSR into operand 0.
7544 (define_expand "mips_get_fcsr"
7545 [(set (match_operand:SI 0 "register_operand")
7546 (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
7547 "TARGET_HARD_FLOAT_ABI"
7551 mips16_expand_get_fcsr (operands[0]);
7556 (define_insn "*mips_get_fcsr"
7557 [(set (match_operand:SI 0 "register_operand" "=d")
7558 (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
7562 ;; See tls_get_tp_mips16_<mode> for why this form is used.
7563 (define_insn "mips_get_fcsr_mips16_<mode>"
7564 [(set (reg:SI GET_FCSR_REGNUM)
7565 (unspec:SI [(match_operand:P 0 "call_insn_operand" "dS")]
7567 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7568 (clobber (reg:P RETURN_ADDR_REGNUM))]
7569 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16"
7570 { return mips_output_jump (operands, 0, -1, true); }
7571 [(set_attr "type" "call")
7572 (set_attr "insn_count" "3")])
7574 ;; __builtin_mips_set_fcsr: move operand 0 into the FCSR.
7575 (define_expand "mips_set_fcsr"
7576 [(unspec_volatile [(match_operand:SI 0 "register_operand")]
7578 "TARGET_HARD_FLOAT_ABI"
7582 mips16_expand_set_fcsr (operands[0]);
7587 (define_insn "*mips_set_fcsr"
7588 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
7593 ;; See tls_get_tp_mips16_<mode> for why this form is used.
7594 (define_insn "mips_set_fcsr_mips16_<mode>"
7595 [(unspec_volatile:SI [(match_operand:P 0 "call_insn_operand" "dS")
7596 (reg:SI SET_FCSR_REGNUM)] UNSPEC_SET_FCSR)
7597 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7598 (clobber (reg:P RETURN_ADDR_REGNUM))]
7599 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16"
7600 { return mips_output_jump (operands, 0, -1, true); }
7601 [(set_attr "type" "call")
7602 (set_attr "insn_count" "3")])
7604 ;; Match paired HI/SI/SF/DFmode load/stores.
7605 (define_insn "*join2_load_store<JOIN_MODE:mode>"
7606 [(set (match_operand:JOIN_MODE 0 "nonimmediate_operand" "=d,f,m,m")
7607 (match_operand:JOIN_MODE 1 "nonimmediate_operand" "m,m,d,f"))
7608 (set (match_operand:JOIN_MODE 2 "nonimmediate_operand" "=d,f,m,m")
7609 (match_operand:JOIN_MODE 3 "nonimmediate_operand" "m,m,d,f"))]
7610 "ENABLE_LD_ST_PAIRS && reload_completed"
7612 bool load_p = (which_alternative == 0 || which_alternative == 1);
7613 /* Reg-renaming pass reuses base register if it is dead after bonded loads.
7614 Hardware does not bond those loads, even when they are consecutive.
7615 However, order of the loads need to be checked for correctness. */
7616 if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[1]))
7618 output_asm_insn (mips_output_move (operands[0], operands[1]),
7620 output_asm_insn (mips_output_move (operands[2], operands[3]),
7625 output_asm_insn (mips_output_move (operands[2], operands[3]),
7627 output_asm_insn (mips_output_move (operands[0], operands[1]),
7632 [(set_attr "move_type" "load,fpload,store,fpstore")
7633 (set_attr "insn_count" "2,2,2,2")])
7635 ;; 2 HI/SI/SF/DF loads are joined.
7636 ;; P5600 does not support bonding of two LBs, hence QI mode is not included.
7637 ;; The loads must be non-volatile as they might be reordered at the time of asm
7640 [(set (match_operand:JOIN_MODE 0 "register_operand")
7641 (match_operand:JOIN_MODE 1 "non_volatile_mem_operand"))
7642 (set (match_operand:JOIN_MODE 2 "register_operand")
7643 (match_operand:JOIN_MODE 3 "non_volatile_mem_operand"))]
7645 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, true)"
7646 [(parallel [(set (match_dup 0)
7652 ;; 2 HI/SI/SF/DF stores are joined.
7653 ;; P5600 does not support bonding of two SBs, hence QI mode is not included.
7655 [(set (match_operand:JOIN_MODE 0 "memory_operand")
7656 (match_operand:JOIN_MODE 1 "register_operand"))
7657 (set (match_operand:JOIN_MODE 2 "memory_operand")
7658 (match_operand:JOIN_MODE 3 "register_operand"))]
7660 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, false)"
7661 [(parallel [(set (match_dup 0)
7667 ;; Match paired HImode loads.
7668 (define_insn "*join2_loadhi"
7669 [(set (match_operand:SI 0 "register_operand" "=r")
7670 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand" "m")))
7671 (set (match_operand:SI 2 "register_operand" "=r")
7672 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand" "m")))]
7673 "ENABLE_LD_ST_PAIRS && reload_completed"
7675 /* Reg-renaming pass reuses base register if it is dead after bonded loads.
7676 Hardware does not bond those loads, even when they are consecutive.
7677 However, order of the loads need to be checked for correctness. */
7678 if (!reg_overlap_mentioned_p (operands[0], operands[1]))
7680 output_asm_insn ("lh<u>\t%0,%1", operands);
7681 output_asm_insn ("lh<u>\t%2,%3", operands);
7685 output_asm_insn ("lh<u>\t%2,%3", operands);
7686 output_asm_insn ("lh<u>\t%0,%1", operands);
7691 [(set_attr "move_type" "load")
7692 (set_attr "insn_count" "2")])
7695 ;; 2 HI loads are joined.
7697 [(set (match_operand:SI 0 "register_operand")
7698 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand")))
7699 (set (match_operand:SI 2 "register_operand")
7700 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand")))]
7702 && mips_load_store_bonding_p (operands, HImode, true)"
7703 [(parallel [(set (match_dup 0)
7704 (any_extend:SI (match_dup 1)))
7706 (any_extend:SI (match_dup 3)))])]
7710 ;; Synchronization instructions.
7714 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
7716 (include "mips-ps-3d.md")
7718 ; The MIPS DSP Instructions.
7720 (include "mips-dsp.md")
7722 ; The MIPS DSP REV 2 Instructions.
7724 (include "mips-dspr2.md")
7726 ; MIPS fixed-point instructions.
7727 (include "mips-fixed.md")
7729 ; microMIPS patterns.
7730 (include "micromips.md")
7732 ; Loongson MultiMedia extensions Instructions (MMI) patterns.
7733 (include "loongson-mmi.md")
7735 ; The MIPS MSA Instructions.
7736 (include "mips-msa.md")
7738 (define_c_enum "unspec" [
7739 UNSPEC_ADDRESS_FIRST