1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
4 ;; Changes by Michael Meissner, meissner@osf.org
5 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 ;; Brendan Eich, brendan@microunity.com.
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 (define_enum "processor" [
69 (define_c_enum "unspec" [
70 ;; Unaligned accesses.
76 ;; Floating-point moves.
92 UNSPEC_POTENTIAL_CPRESTORE
97 UNSPEC_SET_GOT_VERSION
98 UNSPEC_UPDATE_GOT_VERSION
100 ;; Symbolic accesses.
105 UNSPEC_UNSHIFTED_HIGH
107 ;; MIPS16 constant pools.
109 UNSPEC_CONSTTABLE_INT
110 UNSPEC_CONSTTABLE_FLOAT
112 ;; Blockage and synchronisation.
119 ;; Cache manipulation.
121 UNSPEC_R10K_CACHE_BARRIER
123 ;; Interrupt handling.
131 ;; Used in a call expression in place of args_size. It's present for PIC
132 ;; indirect calls where it contains args_size and the function symbol.
135 ;; MIPS16 casesi jump table dispatch.
136 UNSPEC_CASESI_DISPATCH
139 UNSPEC_PROBE_STACK_RANGE
143 [(TLS_GET_TP_REGNUM 3)
145 (PIC_FUNCTION_ADDR_REGNUM 25)
146 (RETURN_ADDR_REGNUM 31)
147 (CPRESTORE_SLOT_REGNUM 76)
148 (GOT_VERSION_REGNUM 79)
150 ;; PIC long branch sequences are never longer than 100 bytes.
151 (MAX_PIC_BRANCH_LENGTH 100)
155 (include "predicates.md")
156 (include "constraints.md")
158 ;; ....................
162 ;; ....................
164 (define_attr "got" "unset,xgot_high,load"
165 (const_string "unset"))
167 ;; For jal instructions, this attribute is DIRECT when the target address
168 ;; is symbolic and INDIRECT when it is a register.
169 (define_attr "jal" "unset,direct,indirect"
170 (const_string "unset"))
172 ;; This attribute is YES if the instruction is a jal macro (not a
173 ;; real jal instruction).
175 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
176 ;; an instruction to restore $gp. Direct jals are also macros for
177 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
179 (define_attr "jal_macro" "no,yes"
180 (cond [(eq_attr "jal" "direct")
181 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
182 ? JAL_MACRO_YES : JAL_MACRO_NO)")
183 (eq_attr "jal" "indirect")
184 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
185 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
186 (const_string "no")))
188 ;; Classification of moves, extensions and truncations. Most values
189 ;; are as for "type" (see below) but there are also the following
190 ;; move-specific values:
192 ;; constN move an N-constraint integer into a MIPS16 register
193 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
194 ;; to produce a sign-extended DEST, even if SRC is not
195 ;; properly sign-extended
196 ;; ext_ins EXT, DEXT, INS or DINS instruction
197 ;; andi a single ANDI instruction
198 ;; loadpool move a constant into a MIPS16 register by loading it
200 ;; shift_shift a shift left followed by a shift right
202 ;; This attribute is used to determine the instruction's length and
203 ;; scheduling type. For doubleword moves, the attribute always describes
204 ;; the split instructions; in some cases, it is more appropriate for the
205 ;; scheduling type to be "multi" instead.
206 (define_attr "move_type"
207 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove,
208 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
210 (const_string "unknown"))
212 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
213 (const_string "unknown"))
215 ;; Main data type used by the insn
216 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
217 (const_string "unknown"))
219 ;; True if the main data type is twice the size of a word.
220 (define_attr "dword_mode" "no,yes"
221 (cond [(and (eq_attr "mode" "DI,DF")
222 (not (match_test "TARGET_64BIT")))
225 (and (eq_attr "mode" "TI,TF")
226 (match_test "TARGET_64BIT"))
227 (const_string "yes")]
228 (const_string "no")))
230 ;; Attributes describing a sync loop. These loops have the form:
232 ;; if (RELEASE_BARRIER == YES) sync
234 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
235 ;; CMP = 0 [delay slot]
236 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
237 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
238 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
239 ;; $AT |= $TMP1 | $TMP3
240 ;; if (!commit (*MEM = $AT)) goto 1.
241 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
243 ;; if (ACQUIRE_BARRIER == YES) sync
246 ;; where "$" values are temporaries and where the other values are
247 ;; specified by the attributes below. Values are specified as operand
248 ;; numbers and insns are specified as enums. If no operand number is
249 ;; specified, the following values are used instead:
254 ;; - INCLUSIVE_MASK: -1
255 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
256 ;; - EXCLUSIVE_MASK: 0
258 ;; MEM and INSN1_OP2 are required.
260 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
261 ;; but the gen* programs don't yet support that.
262 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
263 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
264 (define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
265 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
266 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
267 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
268 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
269 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
270 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
271 (const_string "move"))
272 (define_attr "sync_insn2" "nop,and,xor,not"
273 (const_string "nop"))
274 ;; Memory model specifier.
275 ;; "0"-"9" values specify the operand that stores the memory model value.
276 ;; "10" specifies MEMMODEL_ACQ_REL,
277 ;; "11" specifies MEMMODEL_ACQUIRE.
278 (define_attr "sync_memmodel" "" (const_int 10))
280 ;; Accumulator operand for madd patterns.
281 (define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
283 ;; Classification of each insn.
284 ;; branch conditional branch
285 ;; jump unconditional jump
286 ;; call unconditional call
287 ;; load load instruction(s)
288 ;; fpload floating point load
289 ;; fpidxload floating point indexed load
290 ;; store store instruction(s)
291 ;; fpstore floating point store
292 ;; fpidxstore floating point indexed store
293 ;; prefetch memory prefetch (register + offset)
294 ;; prefetchx memory indexed prefetch (register + register)
295 ;; condmove conditional moves
296 ;; mtc transfer to coprocessor
297 ;; mfc transfer from coprocessor
298 ;; mthi transfer to a hi register
299 ;; mtlo transfer to a lo register
300 ;; mfhi transfer from a hi register
301 ;; mflo transfer from a lo register
302 ;; const load constant
303 ;; arith integer arithmetic instructions
304 ;; logical integer logical instructions
305 ;; shift integer shift instructions
306 ;; slt set less than instructions
307 ;; signext sign extend instructions
308 ;; clz the clz and clo instructions
309 ;; pop the pop instruction
310 ;; trap trap if instructions
311 ;; imul integer multiply 2 operands
312 ;; imul3 integer multiply 3 operands
313 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
314 ;; imadd integer multiply-add
315 ;; idiv integer divide 2 operands
316 ;; idiv3 integer divide 3 operands
317 ;; move integer register move ({,D}ADD{,U} with rt = 0)
318 ;; fmove floating point register move
319 ;; fadd floating point add/subtract
320 ;; fmul floating point multiply
321 ;; fmadd floating point multiply-add
322 ;; fdiv floating point divide
323 ;; frdiv floating point reciprocal divide
324 ;; frdiv1 floating point reciprocal divide step 1
325 ;; frdiv2 floating point reciprocal divide step 2
326 ;; fabs floating point absolute value
327 ;; fneg floating point negation
328 ;; fcmp floating point compare
329 ;; fcvt floating point convert
330 ;; fsqrt floating point square root
331 ;; frsqrt floating point reciprocal square root
332 ;; frsqrt1 floating point reciprocal square root step1
333 ;; frsqrt2 floating point reciprocal square root step2
334 ;; dspmac DSP MAC instructions not saturating the accumulator
335 ;; dspmacsat DSP MAC instructions that saturate the accumulator
336 ;; accext DSP accumulator extract instructions
337 ;; accmod DSP accumulator modify instructions
338 ;; dspalu DSP ALU instructions not saturating the result
339 ;; dspalusat DSP ALU instructions that saturate the result
340 ;; multi multiword sequence (or user asm statements)
341 ;; atomic atomic memory update instruction
342 ;; syncloop memory atomic operation implemented as a sync loop
344 ;; ghost an instruction that produces no real code
345 ;; multimem microMIPS multiword load and store
347 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
348 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
349 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
350 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
351 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
352 multi,atomic,syncloop,nop,ghost,multimem"
353 (cond [(eq_attr "jal" "!unset") (const_string "call")
354 (eq_attr "got" "load") (const_string "load")
356 (eq_attr "alu_type" "add,sub") (const_string "arith")
358 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
360 ;; If a doubleword move uses these expensive instructions,
361 ;; it is usually better to schedule them in the same way
362 ;; as the singleword form, rather than as "multi".
363 (eq_attr "move_type" "load") (const_string "load")
364 (eq_attr "move_type" "fpload") (const_string "fpload")
365 (eq_attr "move_type" "store") (const_string "store")
366 (eq_attr "move_type" "fpstore") (const_string "fpstore")
367 (eq_attr "move_type" "mtc") (const_string "mtc")
368 (eq_attr "move_type" "mfc") (const_string "mfc")
369 (eq_attr "move_type" "mtlo") (const_string "mtlo")
370 (eq_attr "move_type" "mflo") (const_string "mflo")
372 ;; These types of move are always single insns.
373 (eq_attr "move_type" "imul") (const_string "imul")
374 (eq_attr "move_type" "fmove") (const_string "fmove")
375 (eq_attr "move_type" "loadpool") (const_string "load")
376 (eq_attr "move_type" "signext") (const_string "signext")
377 (eq_attr "move_type" "ext_ins") (const_string "arith")
378 (eq_attr "move_type" "arith") (const_string "arith")
379 (eq_attr "move_type" "logical") (const_string "logical")
380 (eq_attr "move_type" "sll0") (const_string "shift")
381 (eq_attr "move_type" "andi") (const_string "logical")
383 ;; These types of move are always split.
384 (eq_attr "move_type" "constN,shift_shift")
385 (const_string "multi")
387 ;; These types of move are split for doubleword modes only.
388 (and (eq_attr "move_type" "move,const")
389 (eq_attr "dword_mode" "yes"))
390 (const_string "multi")
391 (eq_attr "move_type" "move") (const_string "move")
392 (eq_attr "move_type" "const") (const_string "const")
393 (eq_attr "sync_mem" "!none") (const_string "syncloop")]
394 (const_string "unknown")))
396 ;; Mode for conversion types (fcvt)
397 ;; I2S integer to float single (SI/DI to SF)
398 ;; I2D integer to float double (SI/DI to DF)
399 ;; S2I float to integer (SF to SI/DI)
400 ;; D2I float to integer (DF to SI/DI)
401 ;; D2S double to float single
402 ;; S2D float single to double
404 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
405 (const_string "unknown"))
407 ;; Is this an extended instruction in mips16 mode?
408 (define_attr "extended_mips16" "no,yes"
409 (if_then_else (ior (eq_attr "move_type" "sll0")
410 (eq_attr "jal" "direct"))
412 (const_string "no")))
414 (define_attr "compression" "none,all,micromips"
415 (const_string "none"))
417 (define_attr "enabled" "no,yes"
418 (if_then_else (ior (eq_attr "compression" "all,none")
419 (and (eq_attr "compression" "micromips")
420 (match_test "TARGET_MICROMIPS")))
422 (const_string "no")))
424 ;; Length of instruction in bytes.
425 (define_attr "length" ""
426 (cond [(and (eq_attr "extended_mips16" "yes")
427 (match_test "TARGET_MIPS16"))
430 (and (eq_attr "compression" "micromips,all")
431 (eq_attr "dword_mode" "no")
432 (match_test "TARGET_MICROMIPS"))
435 ;; Direct microMIPS branch instructions have a range of
436 ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc].
437 ;; If a branch is outside this range, we have a choice of two
440 ;; For PIC, an out-of-range branch like:
445 ;; becomes the equivalent of:
454 ;; The non-PIC case is similar except that we use a direct
455 ;; jump instead of an la/jr pair. Since the target of this
456 ;; jump is an absolute 28-bit bit address (the other bits
457 ;; coming from the address of the delay slot) this form cannot
458 ;; cross a 256MB boundary. We could provide the option of
459 ;; using la/jr in this case too, but we do not do so at
462 ;; The value we specify here does not account for the delay slot
463 ;; instruction, whose length is added separately. If the RTL
464 ;; pattern has no explicit delay slot, mips_adjust_insn_length
465 ;; will add the length of the implicit nop. The range of
466 ;; [-0x20000, 0x1fffc] from the address of the delay slot
467 ;; therefore translates to a range of:
469 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
470 ;; == [-0x1fffc, 0x1fff8]
472 ;; from the shorten_branches reference address.
473 (and (eq_attr "type" "branch")
474 (not (match_test "TARGET_MIPS16")))
475 (cond [;; Any variant can handle the 17-bit range.
476 (and (le (minus (match_dup 0) (pc)) (const_int 65532))
477 (le (minus (pc) (match_dup 0)) (const_int 65534)))
480 ;; The 18-bit range is OK other than for microMIPS.
481 (and (not (match_test "TARGET_MICROMIPS"))
482 (and (le (minus (match_dup 0) (pc)) (const_int 131064))
483 (le (minus (pc) (match_dup 0)) (const_int 131068))))
486 ;; The non-PIC case: branch, first delay slot, and J.
487 (match_test "TARGET_ABSOLUTE_JUMPS")
490 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
491 ;; mips_adjust_insn_length substitutes the correct length.
493 ;; Note that we can't simply use (symbol_ref ...) here
494 ;; because genattrtab needs to know the maximum length
496 (const_int MAX_PIC_BRANCH_LENGTH))
498 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
499 ;; from the address of the following instruction, which leads
502 ;; [-(0x100 - sizeof (branch)), 0xfe]
505 ;; from the shorten_branches reference address. Extended branches
506 ;; likewise have a range of [-0x10000, 0xfffe] from the address
507 ;; of the following instruction, which leads to a range of:
509 ;; [-(0x10000 - sizeof (branch)), 0xfffe]
510 ;; == [-0xfffc, 0xfffe]
512 ;; from the reference address.
514 ;; When a branch is out of range, mips_reorg splits it into a form
515 ;; that uses in-range branches. There are four basic sequences:
517 ;; (1) Absolute addressing with a readable text segment
518 ;; (32-bit addresses):
521 ;; move $1,$2 2 bytes
522 ;; lw $2,label 2 bytes
524 ;; move $2,$1 2 bytes
525 ;; .align 2 0 or 2 bytes
527 ;; .word target 4 bytes
529 ;; (16 bytes in the worst case)
531 ;; (2) Absolute addressing with a readable text segment
532 ;; (64-bit addresses):
535 ;; move $1,$2 2 bytes
536 ;; ld $2,label 2 bytes
538 ;; move $2,$1 2 bytes
539 ;; .align 3 0 to 6 bytes
541 ;; .dword target 8 bytes
543 ;; (24 bytes in the worst case)
545 ;; (3) Absolute addressing without a readable text segment
546 ;; (which requires 32-bit addresses at present):
549 ;; move $1,$2 2 bytes
550 ;; lui $2,%hi(target) 4 bytes
553 ;; addiu $2,%lo(target) 4 bytes
555 ;; move $2,$1 2 bytes
559 ;; (4) PIC addressing (which requires 32-bit addresses at present):
562 ;; move $1,$2 2 bytes
563 ;; lw $2,cprestore 0, 2 or 4 bytes
564 ;; lw $2,%got(target)($2) 4 bytes
565 ;; addiu $2,%lo(target) 4 bytes
567 ;; move $2,$1 2 bytes
569 ;; (20 bytes in the worst case)
570 (and (eq_attr "type" "branch")
571 (match_test "TARGET_MIPS16"))
572 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
573 (le (minus (pc) (match_dup 0)) (const_int 254)))
575 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
576 (le (minus (pc) (match_dup 0)) (const_int 65532)))
578 (and (match_test "TARGET_ABICALLS")
579 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
581 (match_test "Pmode == SImode")
585 ;; "Ghost" instructions occupy no space.
586 (eq_attr "type" "ghost")
589 ;; GOT loads are extended MIPS16 instructions and 4-byte
590 ;; microMIPS instructions.
591 (eq_attr "got" "load")
594 ;; A GOT load followed by an add of $gp.
595 (eq_attr "got" "xgot_high")
598 ;; In general, constant-pool loads are extended instructions.
599 (eq_attr "move_type" "loadpool")
602 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
603 ;; They are extended instructions on MIPS16 targets.
604 (eq_attr "move_type" "shift_shift")
607 ;; Check for doubleword moves that are decomposed into two
608 ;; instructions. The individual instructions are unextended
609 ;; MIPS16 ones or 2-byte microMIPS ones.
610 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
611 (eq_attr "dword_mode" "yes"))
612 (if_then_else (match_test "TARGET_COMPRESSION")
616 ;; Doubleword CONST{,N} moves are split into two word
618 (and (eq_attr "move_type" "const,constN")
619 (eq_attr "dword_mode" "yes"))
620 (symbol_ref "mips_split_const_insns (operands[1]) * BASE_INSN_LENGTH")
622 ;; Otherwise, constants, loads and stores are handled by external
624 (eq_attr "move_type" "const,constN")
625 (symbol_ref "mips_const_insns (operands[1]) * BASE_INSN_LENGTH")
626 (eq_attr "move_type" "load,fpload")
627 (symbol_ref "mips_load_store_insns (operands[1], insn)
629 (eq_attr "move_type" "store,fpstore")
630 (symbol_ref "mips_load_store_insns (operands[0], insn)
632 + (TARGET_FIX_24K ? NOP_INSN_LENGTH : 0)")
634 ;; In the worst case, a call macro will take 8 instructions:
636 ;; lui $25,%call_hi(FOO)
638 ;; lw $25,%call_lo(FOO)($25)
644 (eq_attr "jal_macro" "yes")
647 ;; Various VR4120 errata require a nop to be inserted after a macc
648 ;; instruction. The assembler does this for us, so account for
649 ;; the worst-case length here.
650 (and (eq_attr "type" "imadd")
651 (match_test "TARGET_FIX_VR4120"))
654 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
655 ;; the result of the second one is missed. The assembler should work
656 ;; around this by inserting a nop after the first dmult.
657 (and (eq_attr "type" "imul,imul3")
658 (and (eq_attr "mode" "DI")
659 (match_test "TARGET_FIX_VR4120")))
662 (eq_attr "type" "idiv,idiv3")
663 (symbol_ref "mips_idiv_insns () * BASE_INSN_LENGTH")
665 (not (eq_attr "sync_mem" "none"))
666 (symbol_ref "mips_sync_loop_insns (insn, operands)
669 (match_test "TARGET_MIPS16")
673 ;; Attribute describing the processor.
674 (define_enum_attr "cpu" "processor"
675 (const (symbol_ref "mips_tune")))
677 ;; The type of hardware hazard associated with this instruction.
678 ;; DELAY means that the next instruction cannot read the result
679 ;; of this one. HILO means that the next two instructions cannot
680 ;; write to HI or LO.
681 (define_attr "hazard" "none,delay,hilo"
682 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
683 (match_test "ISA_HAS_LOAD_DELAY"))
684 (const_string "delay")
686 (and (eq_attr "type" "mfc,mtc")
687 (match_test "ISA_HAS_XFER_DELAY"))
688 (const_string "delay")
690 (and (eq_attr "type" "fcmp")
691 (match_test "ISA_HAS_FCMP_DELAY"))
692 (const_string "delay")
694 ;; The r4000 multiplication patterns include an mflo instruction.
695 (and (eq_attr "type" "imul")
696 (match_test "TARGET_FIX_R4000"))
697 (const_string "hilo")
699 (and (eq_attr "type" "mfhi,mflo")
700 (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
701 (const_string "hilo")]
702 (const_string "none")))
704 ;; Is it a single instruction?
705 (define_attr "single_insn" "no,yes"
706 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
707 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
709 ;; Can the instruction be put into a delay slot?
710 (define_attr "can_delay" "no,yes"
711 (if_then_else (and (eq_attr "type" "!branch,call,jump")
712 (and (eq_attr "hazard" "none")
713 (eq_attr "single_insn" "yes")))
715 (const_string "no")))
717 ;; Attribute defining whether or not we can use the branch-likely
719 (define_attr "branch_likely" "no,yes"
720 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
722 (const_string "no")))
724 ;; True if an instruction might assign to hi or lo when reloaded.
725 ;; This is used by the TUNE_MACC_CHAINS code.
726 (define_attr "may_clobber_hilo" "no,yes"
727 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
729 (const_string "no")))
731 ;; Describe a user's asm statement.
732 (define_asm_attributes
733 [(set_attr "type" "multi")
734 (set_attr "can_delay" "no")])
736 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
737 ;; from the same template.
738 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
740 ;; A copy of GPR that can be used when a pattern has two independent
742 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
744 (define_mode_iterator MOVEP1 [SI SF])
745 (define_mode_iterator MOVEP2 [SI SF])
747 ;; This mode iterator allows :HILO to be used as the mode of the
748 ;; concatenated HI and LO registers.
749 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
751 ;; This mode iterator allows :P to be used for patterns that operate on
752 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
753 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
755 ;; This mode iterator allows :MOVECC to be used anywhere that a
756 ;; conditional-move-type condition is needed.
757 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
758 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
760 ;; 32-bit integer moves for which we provide move patterns.
761 (define_mode_iterator IMOVE32
770 (V4UQQ "TARGET_DSP")])
772 ;; 64-bit modes for which we provide move patterns.
773 (define_mode_iterator MOVE64
775 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
776 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
777 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
778 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
780 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
781 (define_mode_iterator MOVE128 [TI TF])
783 ;; This mode iterator allows the QI and HI extension patterns to be
784 ;; defined from the same template.
785 (define_mode_iterator SHORT [QI HI])
787 ;; Likewise the 64-bit truncate-and-shift patterns.
788 (define_mode_iterator SUBDI [QI HI SI])
790 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
791 ;; floating-point mode is allowed.
792 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
793 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
794 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
796 ;; Like ANYF, but only applies to scalar modes.
797 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
798 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
800 ;; A floating-point mode for which moves involving FPRs may need to be split.
801 (define_mode_iterator SPLITF
802 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
803 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
804 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
805 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
806 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
807 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
808 (TF "TARGET_64BIT && TARGET_FLOAT64")])
810 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
811 ;; 32-bit version and "dsubu" in the 64-bit version.
812 (define_mode_attr d [(SI "") (DI "d")
813 (QQ "") (HQ "") (SQ "") (DQ "d")
814 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
815 (HA "") (SA "") (DA "d")
816 (UHA "") (USA "") (UDA "d")])
818 ;; Same as d but upper-case.
819 (define_mode_attr D [(SI "") (DI "D")
820 (QQ "") (HQ "") (SQ "") (DQ "D")
821 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
822 (HA "") (SA "") (DA "D")
823 (UHA "") (USA "") (UDA "D")])
825 ;; This attribute gives the length suffix for a load or store instruction.
826 ;; The same suffixes work for zero and sign extensions.
827 (define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
828 (define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
830 ;; This attributes gives the mode mask of a SHORT.
831 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
833 ;; Mode attributes for GPR loads.
834 (define_mode_attr load [(SI "lw") (DI "ld")])
835 ;; Instruction names for stores.
836 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
838 ;; Similarly for MIPS IV indexed FPR loads and stores.
839 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
840 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
842 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
843 ;; are different. Some forms of unextended addiu have an 8-bit immediate
844 ;; field but the equivalent daddiu has only a 5-bit field.
845 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
847 ;; This attribute gives the best constraint to use for registers of
849 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
851 ;; This attribute gives the format suffix for floating-point operations.
852 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
854 ;; This attribute gives the upper-case mode name for one unit of a
855 ;; floating-point mode.
856 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
858 ;; This attribute gives the integer mode that has the same size as a
860 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
861 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
862 (HA "HI") (SA "SI") (DA "DI")
863 (UHA "HI") (USA "SI") (UDA "DI")
864 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
865 (V2HQ "SI") (V2HA "SI")])
867 ;; This attribute gives the integer mode that has half the size of
868 ;; the controlling mode.
869 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
870 (V2SI "SI") (V4HI "SI") (V8QI "SI")
873 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
875 ;; In certain cases, div.s and div.ps may have a rounding error
876 ;; and/or wrong inexact flag.
878 ;; Therefore, we only allow div.s if not working around SB-1 rev2
879 ;; errata or if a slight loss of precision is OK.
880 (define_mode_attr divide_condition
881 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
882 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
884 ;; This attribute gives the conditions under which SQRT.fmt instructions
886 (define_mode_attr sqrt_condition
887 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
889 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
890 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
891 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
892 ;; so for safety's sake, we apply this restriction to all targets.
893 (define_mode_attr recip_condition
895 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
896 (V2SF "TARGET_SB1")])
898 ;; This code iterator allows signed and unsigned widening multiplications
899 ;; to use the same template.
900 (define_code_iterator any_extend [sign_extend zero_extend])
902 ;; This code iterator allows the two right shift instructions to be
903 ;; generated from the same template.
904 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
906 ;; This code iterator allows the three shift instructions to be generated
907 ;; from the same template.
908 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
910 ;; This code iterator allows unsigned and signed division to be generated
911 ;; from the same template.
912 (define_code_iterator any_div [div udiv])
914 ;; This code iterator allows unsigned and signed modulus to be generated
915 ;; from the same template.
916 (define_code_iterator any_mod [mod umod])
918 ;; This code iterator allows all native floating-point comparisons to be
919 ;; generated from the same template.
920 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
922 ;; This code iterator is used for comparisons that can be implemented
923 ;; by swapping the operands.
924 (define_code_iterator swapped_fcond [ge gt unge ungt])
926 ;; Equality operators.
927 (define_code_iterator equality_op [eq ne])
929 ;; These code iterators allow the signed and unsigned scc operations to use
930 ;; the same template.
931 (define_code_iterator any_gt [gt gtu])
932 (define_code_iterator any_ge [ge geu])
933 (define_code_iterator any_lt [lt ltu])
934 (define_code_iterator any_le [le leu])
936 (define_code_iterator any_return [return simple_return])
938 ;; <u> expands to an empty string when doing a signed operation and
939 ;; "u" when doing an unsigned operation.
940 (define_code_attr u [(sign_extend "") (zero_extend "u")
948 ;; <U> is like <u> except uppercase.
949 (define_code_attr U [(sign_extend "") (zero_extend "U")])
951 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
952 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
954 ;; <optab> expands to the name of the optab for a particular code.
955 (define_code_attr optab [(ashift "ashl")
964 (simple_return "simple_return")])
966 ;; <insn> expands to the name of the insn that implements a particular code.
967 (define_code_attr insn [(ashift "sll")
976 ;; <immediate_insn> expands to the name of the insn that implements
977 ;; a particular code to operate on immediate values.
978 (define_code_attr immediate_insn [(ior "ori")
982 (define_code_attr shift_compression [(ashift "micromips")
983 (lshiftrt "micromips")
986 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
987 (define_code_attr fcond [(unordered "un")
995 ;; Similar, but for swapped conditions.
996 (define_code_attr swapped_fcond [(ge "le")
1001 ;; The value of the bit when the branch is taken for branch_bit patterns.
1002 ;; Comparison is always against zero so this depends on the operator.
1003 (define_code_attr bbv [(eq "0") (ne "1")])
1005 ;; This is the inverse value of bbv.
1006 (define_code_attr bbinv [(eq "1") (ne "0")])
1008 ;; .........................
1010 ;; Branch, call and jump delay slots
1012 ;; .........................
1014 (define_delay (and (eq_attr "type" "branch")
1015 (not (match_test "TARGET_MIPS16"))
1016 (eq_attr "branch_likely" "yes"))
1017 [(eq_attr "can_delay" "yes")
1019 (eq_attr "can_delay" "yes")])
1021 ;; Branches that don't have likely variants do not annul on false.
1022 (define_delay (and (eq_attr "type" "branch")
1023 (not (match_test "TARGET_MIPS16"))
1024 (eq_attr "branch_likely" "no"))
1025 [(eq_attr "can_delay" "yes")
1029 (define_delay (eq_attr "type" "jump")
1030 [(eq_attr "can_delay" "yes")
1034 (define_delay (and (eq_attr "type" "call")
1035 (eq_attr "jal_macro" "no"))
1036 [(eq_attr "can_delay" "yes")
1040 ;; Pipeline descriptions.
1042 ;; generic.md provides a fallback for processors without a specific
1043 ;; pipeline description. It is derived from the old define_function_unit
1044 ;; version and uses the "alu" and "imuldiv" units declared below.
1046 ;; Some of the processor-specific files are also derived from old
1047 ;; define_function_unit descriptions and simply override the parts of
1048 ;; generic.md that don't apply. The other processor-specific files
1049 ;; are self-contained.
1050 (define_automaton "alu,imuldiv")
1052 (define_cpu_unit "alu" "alu")
1053 (define_cpu_unit "imuldiv" "imuldiv")
1055 ;; Ghost instructions produce no real code and introduce no hazards.
1056 ;; They exist purely to express an effect on dataflow.
1057 (define_insn_reservation "ghost" 0
1058 (eq_attr "type" "ghost")
1078 (include "10000.md")
1079 (include "loongson2ef.md")
1080 (include "loongson3a.md")
1081 (include "octeon.md")
1083 (include "sr71k.md")
1086 (include "generic.md")
1089 ;; ....................
1091 ;; CONDITIONAL TRAPS
1093 ;; ....................
1097 [(trap_if (const_int 1) (const_int 0))]
1100 if (ISA_HAS_COND_TRAP)
1101 return "teq\t$0,$0";
1102 else if (TARGET_MIPS16)
1107 [(set_attr "type" "trap")])
1109 (define_expand "ctrap<mode>4"
1110 [(trap_if (match_operator 0 "comparison_operator"
1111 [(match_operand:GPR 1 "reg_or_0_operand")
1112 (match_operand:GPR 2 "arith_operand")])
1113 (match_operand 3 "const_0_operand"))]
1116 mips_expand_conditional_trap (operands[0]);
1120 (define_insn "*conditional_trap<mode>"
1121 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1122 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1123 (match_operand:GPR 2 "arith_operand" "dI")])
1127 [(set_attr "type" "trap")])
1130 ;; ....................
1134 ;; ....................
1137 (define_insn "add<mode>3"
1138 [(set (match_operand:ANYF 0 "register_operand" "=f")
1139 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1140 (match_operand:ANYF 2 "register_operand" "f")))]
1142 "add.<fmt>\t%0,%1,%2"
1143 [(set_attr "type" "fadd")
1144 (set_attr "mode" "<UNITMODE>")])
1146 (define_expand "add<mode>3"
1147 [(set (match_operand:GPR 0 "register_operand")
1148 (plus:GPR (match_operand:GPR 1 "register_operand")
1149 (match_operand:GPR 2 "arith_operand")))]
1152 (define_insn "*add<mode>3"
1153 [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!u,!ks,!d,d")
1154 (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,!ks,!ks,0,d")
1155 (match_operand:GPR 2 "arith_operand" "!u,d,Uead,Uuw6,Uesp,Usb4,Q")))]
1158 if (which_alternative == 0
1159 || which_alternative == 1)
1160 return "<d>addu\t%0,%1,%2";
1162 return "<d>addiu\t%0,%1,%2";
1164 [(set_attr "alu_type" "add")
1165 (set_attr "compression" "micromips,*,micromips,micromips,micromips,micromips,*")
1166 (set_attr "mode" "<MODE>")])
1168 (define_insn "*add<mode>3_mips16"
1169 [(set (match_operand:GPR 0 "register_operand" "=ks,ks,d,d,d,d,d,d,d")
1170 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,ks,ks,0,0,d,d,d")
1171 (match_operand:GPR 2 "arith_operand" "Usd8,Q,Uuw<si8_di5>,Q,Usb<si8_di5>,Q,Usb4,O,d")))]
1183 [(set_attr "alu_type" "add")
1184 (set_attr "mode" "<MODE>")
1185 (set_attr "extended_mips16" "no,yes,no,yes,no,yes,no,yes,no")])
1187 ;; On the mips16, we can sometimes split an add of a constant which is
1188 ;; a 4 byte instruction into two adds which are both 2 byte
1189 ;; instructions. There are two cases: one where we are adding a
1190 ;; constant plus a register to another register, and one where we are
1191 ;; simply adding a constant to a register.
1194 [(set (match_operand:SI 0 "d_operand")
1195 (plus:SI (match_dup 0)
1196 (match_operand:SI 1 "const_int_operand")))]
1197 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1198 && ((INTVAL (operands[1]) > 0x7f
1199 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1200 || (INTVAL (operands[1]) < - 0x80
1201 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1202 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1203 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1205 HOST_WIDE_INT val = INTVAL (operands[1]);
1209 operands[1] = GEN_INT (0x7f);
1210 operands[2] = GEN_INT (val - 0x7f);
1214 operands[1] = GEN_INT (- 0x80);
1215 operands[2] = GEN_INT (val + 0x80);
1220 [(set (match_operand:SI 0 "d_operand")
1221 (plus:SI (match_operand:SI 1 "d_operand")
1222 (match_operand:SI 2 "const_int_operand")))]
1223 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1224 && REGNO (operands[0]) != REGNO (operands[1])
1225 && ((INTVAL (operands[2]) > 0x7
1226 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1227 || (INTVAL (operands[2]) < - 0x8
1228 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1229 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1230 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1232 HOST_WIDE_INT val = INTVAL (operands[2]);
1236 operands[2] = GEN_INT (0x7);
1237 operands[3] = GEN_INT (val - 0x7);
1241 operands[2] = GEN_INT (- 0x8);
1242 operands[3] = GEN_INT (val + 0x8);
1247 [(set (match_operand:DI 0 "d_operand")
1248 (plus:DI (match_dup 0)
1249 (match_operand:DI 1 "const_int_operand")))]
1250 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1251 && ((INTVAL (operands[1]) > 0xf
1252 && INTVAL (operands[1]) <= 0xf + 0xf)
1253 || (INTVAL (operands[1]) < - 0x10
1254 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1255 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1256 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1258 HOST_WIDE_INT val = INTVAL (operands[1]);
1262 operands[1] = GEN_INT (0xf);
1263 operands[2] = GEN_INT (val - 0xf);
1267 operands[1] = GEN_INT (- 0x10);
1268 operands[2] = GEN_INT (val + 0x10);
1273 [(set (match_operand:DI 0 "d_operand")
1274 (plus:DI (match_operand:DI 1 "d_operand")
1275 (match_operand:DI 2 "const_int_operand")))]
1276 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1277 && REGNO (operands[0]) != REGNO (operands[1])
1278 && ((INTVAL (operands[2]) > 0x7
1279 && INTVAL (operands[2]) <= 0x7 + 0xf)
1280 || (INTVAL (operands[2]) < - 0x8
1281 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1282 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1283 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1285 HOST_WIDE_INT val = INTVAL (operands[2]);
1289 operands[2] = GEN_INT (0x7);
1290 operands[3] = GEN_INT (val - 0x7);
1294 operands[2] = GEN_INT (- 0x8);
1295 operands[3] = GEN_INT (val + 0x8);
1299 (define_insn "*addsi3_extended"
1300 [(set (match_operand:DI 0 "register_operand" "=d,d")
1302 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1303 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1304 "TARGET_64BIT && !TARGET_MIPS16"
1308 [(set_attr "alu_type" "add")
1309 (set_attr "mode" "SI")])
1311 ;; Split this insn so that the addiu splitters can have a crack at it.
1312 ;; Use a conservative length estimate until the split.
1313 (define_insn_and_split "*addsi3_extended_mips16"
1314 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1316 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1317 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1318 "TARGET_64BIT && TARGET_MIPS16"
1320 "&& reload_completed"
1321 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1322 { operands[3] = gen_lowpart (SImode, operands[0]); }
1323 [(set_attr "alu_type" "add")
1324 (set_attr "mode" "SI")
1325 (set_attr "extended_mips16" "yes")])
1327 ;; Combiner patterns for unsigned byte-add.
1329 (define_insn "*baddu_si"
1330 [(set (match_operand:SI 0 "register_operand" "=d")
1332 (plus:QI (match_operand:QI 1 "register_operand" "d")
1333 (match_operand:QI 2 "register_operand" "d"))))]
1336 [(set_attr "alu_type" "add")])
1338 (define_insn "*baddu_di<mode>"
1339 [(set (match_operand:GPR 0 "register_operand" "=d")
1341 (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d"))
1342 (truncate:QI (match_operand:DI 2 "register_operand" "d")))))]
1343 "ISA_HAS_BADDU && TARGET_64BIT"
1345 [(set_attr "alu_type" "add")])
1348 ;; ....................
1352 ;; ....................
1355 (define_insn "sub<mode>3"
1356 [(set (match_operand:ANYF 0 "register_operand" "=f")
1357 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1358 (match_operand:ANYF 2 "register_operand" "f")))]
1360 "sub.<fmt>\t%0,%1,%2"
1361 [(set_attr "type" "fadd")
1362 (set_attr "mode" "<UNITMODE>")])
1364 (define_insn "sub<mode>3"
1365 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
1366 (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d")
1367 (match_operand:GPR 2 "register_operand" "!u,d")))]
1370 [(set_attr "alu_type" "sub")
1371 (set_attr "compression" "micromips,*")
1372 (set_attr "mode" "<MODE>")])
1374 (define_insn "*subsi3_extended"
1375 [(set (match_operand:DI 0 "register_operand" "=d")
1377 (minus:SI (match_operand:SI 1 "register_operand" "d")
1378 (match_operand:SI 2 "register_operand" "d"))))]
1381 [(set_attr "alu_type" "sub")
1382 (set_attr "mode" "DI")])
1385 ;; ....................
1389 ;; ....................
1392 (define_expand "mul<mode>3"
1393 [(set (match_operand:SCALARF 0 "register_operand")
1394 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1395 (match_operand:SCALARF 2 "register_operand")))]
1399 (define_insn "*mul<mode>3"
1400 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1401 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1402 (match_operand:SCALARF 2 "register_operand" "f")))]
1403 "!TARGET_4300_MUL_FIX"
1404 "mul.<fmt>\t%0,%1,%2"
1405 [(set_attr "type" "fmul")
1406 (set_attr "mode" "<MODE>")])
1408 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1409 ;; operands may corrupt immediately following multiplies. This is a
1410 ;; simple fix to insert NOPs.
1412 (define_insn "*mul<mode>3_r4300"
1413 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1414 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1415 (match_operand:SCALARF 2 "register_operand" "f")))]
1416 "TARGET_4300_MUL_FIX"
1417 "mul.<fmt>\t%0,%1,%2\;nop"
1418 [(set_attr "type" "fmul")
1419 (set_attr "mode" "<MODE>")
1420 (set_attr "length" "8")])
1422 (define_insn "mulv2sf3"
1423 [(set (match_operand:V2SF 0 "register_operand" "=f")
1424 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1425 (match_operand:V2SF 2 "register_operand" "f")))]
1426 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1428 [(set_attr "type" "fmul")
1429 (set_attr "mode" "SF")])
1431 ;; The original R4000 has a cpu bug. If a double-word or a variable
1432 ;; shift executes while an integer multiplication is in progress, the
1433 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1434 ;; with the mult on the R4000.
1436 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1437 ;; (also valid for MIPS R4000MC processors):
1439 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1440 ;; this errata description.
1441 ;; The following code sequence causes the R4000 to incorrectly
1442 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1443 ;; instruction. If the dsra32 instruction is executed during an
1444 ;; integer multiply, the dsra32 will only shift by the amount in
1445 ;; specified in the instruction rather than the amount plus 32
1447 ;; instruction 1: mult rs,rt integer multiply
1448 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1449 ;; right arithmetic + 32
1450 ;; Workaround: A dsra32 instruction placed after an integer
1451 ;; multiply should not be one of the 11 instructions after the
1452 ;; multiply instruction."
1456 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1457 ;; the following description.
1458 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1459 ;; 64-bit versions) may produce incorrect results under the
1460 ;; following conditions:
1461 ;; 1) An integer multiply is currently executing
1462 ;; 2) These types of shift instructions are executed immediately
1463 ;; following an integer divide instruction.
1465 ;; 1) Make sure no integer multiply is running wihen these
1466 ;; instruction are executed. If this cannot be predicted at
1467 ;; compile time, then insert a "mfhi" to R0 instruction
1468 ;; immediately after the integer multiply instruction. This
1469 ;; will cause the integer multiply to complete before the shift
1471 ;; 2) Separate integer divide and these two classes of shift
1472 ;; instructions by another instruction or a noop."
1474 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1477 (define_expand "mul<mode>3"
1478 [(set (match_operand:GPR 0 "register_operand")
1479 (mult:GPR (match_operand:GPR 1 "register_operand")
1480 (match_operand:GPR 2 "register_operand")))]
1485 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
1486 emit_insn (gen_mul<mode>3_mul3_loongson (operands[0], operands[1],
1488 else if (ISA_HAS_<D>MUL3)
1489 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1490 else if (TARGET_MIPS16)
1492 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
1493 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2]));
1494 emit_move_insn (operands[0], lo);
1496 else if (TARGET_FIX_R4000)
1497 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1500 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1504 (define_insn "mul<mode>3_mul3_loongson"
1505 [(set (match_operand:GPR 0 "register_operand" "=d")
1506 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1507 (match_operand:GPR 2 "register_operand" "d")))]
1508 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A"
1510 if (TARGET_LOONGSON_2EF)
1511 return "<d>multu.g\t%0,%1,%2";
1513 return "gs<d>multu\t%0,%1,%2";
1515 [(set_attr "type" "imul3nc")
1516 (set_attr "mode" "<MODE>")])
1518 (define_insn "mul<mode>3_mul3"
1519 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1520 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1521 (match_operand:GPR 2 "register_operand" "d,d")))
1522 (clobber (match_scratch:GPR 3 "=l,X"))]
1525 if (which_alternative == 1)
1526 return "<d>mult\t%1,%2";
1527 if (<MODE>mode == SImode && TARGET_MIPS3900)
1528 return "mult\t%0,%1,%2";
1529 return "<d>mul\t%0,%1,%2";
1531 [(set_attr "type" "imul3,imul")
1532 (set_attr "mode" "<MODE>")])
1534 ;; If a register gets allocated to LO, and we spill to memory, the reload
1535 ;; will include a move from LO to a GPR. Merge it into the multiplication
1536 ;; if it can set the GPR directly.
1539 ;; Operand 1: GPR (1st multiplication operand)
1540 ;; Operand 2: GPR (2nd multiplication operand)
1541 ;; Operand 3: GPR (destination)
1544 [(set (match_operand:SI 0 "lo_operand")
1545 (mult:SI (match_operand:SI 1 "d_operand")
1546 (match_operand:SI 2 "d_operand")))
1547 (clobber (scratch:SI))])
1548 (set (match_operand:SI 3 "d_operand")
1550 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1553 (mult:SI (match_dup 1)
1555 (clobber (match_dup 0))])])
1557 (define_insn "mul<mode>3_internal"
1558 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
1559 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1560 (match_operand:GPR 2 "register_operand" "d")))]
1563 [(set_attr "type" "imul")
1564 (set_attr "mode" "<MODE>")])
1566 (define_insn "mul<mode>3_r4000"
1567 [(set (match_operand:GPR 0 "register_operand" "=d")
1568 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1569 (match_operand:GPR 2 "register_operand" "d")))
1570 (clobber (match_scratch:GPR 3 "=l"))]
1572 "<d>mult\t%1,%2\;mflo\t%0"
1573 [(set_attr "type" "imul")
1574 (set_attr "mode" "<MODE>")
1575 (set_attr "length" "8")])
1577 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1578 ;; of "mult; mflo". They have the same latency, but the first form gives
1579 ;; us an extra cycle to compute the operands.
1582 ;; Operand 1: GPR (1st multiplication operand)
1583 ;; Operand 2: GPR (2nd multiplication operand)
1584 ;; Operand 3: GPR (destination)
1586 [(set (match_operand:SI 0 "lo_operand")
1587 (mult:SI (match_operand:SI 1 "d_operand")
1588 (match_operand:SI 2 "d_operand")))
1589 (set (match_operand:SI 3 "d_operand")
1591 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1596 (plus:SI (mult:SI (match_dup 1)
1600 (plus:SI (mult:SI (match_dup 1)
1604 ;; Multiply-accumulate patterns
1606 ;; This pattern is first matched by combine, which tries to use the
1607 ;; pattern wherever it can. We don't know until later whether it
1608 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1609 ;; so we need to keep both options open.
1611 ;; The second alternative has a "?" marker because it is generally
1612 ;; one instruction more costly than the first alternative. This "?"
1613 ;; marker is enough to convey the relative costs to the register
1616 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1617 ;; reloads of the other operands, even though operands 4 and 5 need no
1618 ;; copy instructions. Reload therefore thinks that the second alternative
1619 ;; is two reloads more costly than the first. We add "*?*?" to the first
1620 ;; alternative as a counterweight.
1621 (define_insn "*mul_acc_si"
1622 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1623 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1624 (match_operand:SI 2 "register_operand" "d,d"))
1625 (match_operand:SI 3 "register_operand" "0,d")))
1626 (clobber (match_scratch:SI 4 "=X,l"))
1627 (clobber (match_scratch:SI 5 "=X,&d"))]
1628 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1632 [(set_attr "type" "imadd")
1633 (set_attr "accum_in" "3")
1634 (set_attr "mode" "SI")
1635 (set_attr "length" "4,8")])
1637 ;; The same idea applies here. The middle alternative needs one less
1638 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1639 (define_insn "*mul_acc_si_r3900"
1640 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1641 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1642 (match_operand:SI 2 "register_operand" "d,d,d"))
1643 (match_operand:SI 3 "register_operand" "0,l,d")))
1644 (clobber (match_scratch:SI 4 "=X,3,l"))
1645 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1646 "TARGET_MIPS3900 && !TARGET_MIPS16"
1651 [(set_attr "type" "imadd")
1652 (set_attr "accum_in" "3")
1653 (set_attr "mode" "SI")
1654 (set_attr "length" "4,4,8")])
1656 ;; Split *mul_acc_si if both the source and destination accumulator
1659 [(set (match_operand:SI 0 "d_operand")
1660 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1661 (match_operand:SI 2 "d_operand"))
1662 (match_operand:SI 3 "d_operand")))
1663 (clobber (match_operand:SI 4 "lo_operand"))
1664 (clobber (match_operand:SI 5 "d_operand"))]
1666 [(parallel [(set (match_dup 5)
1667 (mult:SI (match_dup 1) (match_dup 2)))
1668 (clobber (match_dup 4))])
1669 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1672 (define_insn "*macc"
1673 [(set (match_operand:SI 0 "register_operand" "=l,d")
1674 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1675 (match_operand:SI 2 "register_operand" "d,d"))
1676 (match_operand:SI 3 "register_operand" "0,l")))
1677 (clobber (match_scratch:SI 4 "=X,3"))]
1680 if (which_alternative == 1)
1681 return "macc\t%0,%1,%2";
1682 else if (TARGET_MIPS5500)
1683 return "madd\t%1,%2";
1685 /* The VR4130 assumes that there is a two-cycle latency between a macc
1686 that "writes" to $0 and an instruction that reads from it. We avoid
1687 this by assigning to $1 instead. */
1688 return "%[macc\t%@,%1,%2%]";
1690 [(set_attr "type" "imadd")
1691 (set_attr "accum_in" "3")
1692 (set_attr "mode" "SI")])
1694 (define_insn "*msac"
1695 [(set (match_operand:SI 0 "register_operand" "=l,d")
1696 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1697 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1698 (match_operand:SI 3 "register_operand" "d,d"))))
1699 (clobber (match_scratch:SI 4 "=X,1"))]
1702 if (which_alternative == 1)
1703 return "msac\t%0,%2,%3";
1704 else if (TARGET_MIPS5500)
1705 return "msub\t%2,%3";
1707 return "msac\t$0,%2,%3";
1709 [(set_attr "type" "imadd")
1710 (set_attr "accum_in" "1")
1711 (set_attr "mode" "SI")])
1713 ;; An msac-like instruction implemented using negation and a macc.
1714 (define_insn_and_split "*msac_using_macc"
1715 [(set (match_operand:SI 0 "register_operand" "=l,d")
1716 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1717 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1718 (match_operand:SI 3 "register_operand" "d,d"))))
1719 (clobber (match_scratch:SI 4 "=X,1"))
1720 (clobber (match_scratch:SI 5 "=d,d"))]
1721 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1723 "&& reload_completed"
1725 (neg:SI (match_dup 3)))
1728 (plus:SI (mult:SI (match_dup 2)
1731 (clobber (match_dup 4))])]
1733 [(set_attr "type" "imadd")
1734 (set_attr "accum_in" "1")
1735 (set_attr "length" "8")])
1737 ;; Patterns generated by the define_peephole2 below.
1739 (define_insn "*macc2"
1740 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1741 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1742 (match_operand:SI 2 "register_operand" "d"))
1744 (set (match_operand:SI 3 "register_operand" "=d")
1745 (plus:SI (mult:SI (match_dup 1)
1748 "ISA_HAS_MACC && reload_completed"
1750 [(set_attr "type" "imadd")
1751 (set_attr "accum_in" "0")
1752 (set_attr "mode" "SI")])
1754 (define_insn "*msac2"
1755 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1756 (minus:SI (match_dup 0)
1757 (mult:SI (match_operand:SI 1 "register_operand" "d")
1758 (match_operand:SI 2 "register_operand" "d"))))
1759 (set (match_operand:SI 3 "register_operand" "=d")
1760 (minus:SI (match_dup 0)
1761 (mult:SI (match_dup 1)
1763 "ISA_HAS_MSAC && reload_completed"
1765 [(set_attr "type" "imadd")
1766 (set_attr "accum_in" "0")
1767 (set_attr "mode" "SI")])
1769 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1773 ;; Operand 1: macc/msac
1774 ;; Operand 2: GPR (destination)
1777 [(set (match_operand:SI 0 "lo_operand")
1778 (match_operand:SI 1 "macc_msac_operand"))
1779 (clobber (scratch:SI))])
1780 (set (match_operand:SI 2 "d_operand")
1783 [(parallel [(set (match_dup 0)
1788 ;; When we have a three-address multiplication instruction, it should
1789 ;; be faster to do a separate multiply and add, rather than moving
1790 ;; something into LO in order to use a macc instruction.
1792 ;; This peephole needs a scratch register to cater for the case when one
1793 ;; of the multiplication operands is the same as the destination.
1795 ;; Operand 0: GPR (scratch)
1797 ;; Operand 2: GPR (addend)
1798 ;; Operand 3: GPR (destination)
1799 ;; Operand 4: macc/msac
1800 ;; Operand 5: new multiplication
1801 ;; Operand 6: new addition/subtraction
1803 [(match_scratch:SI 0 "d")
1804 (set (match_operand:SI 1 "lo_operand")
1805 (match_operand:SI 2 "d_operand"))
1808 [(set (match_operand:SI 3 "d_operand")
1809 (match_operand:SI 4 "macc_msac_operand"))
1810 (clobber (match_dup 1))])]
1811 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1812 [(parallel [(set (match_dup 0)
1814 (clobber (match_dup 1))])
1818 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1819 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1820 operands[2], operands[0]);
1823 ;; Same as above, except LO is the initial target of the macc.
1825 ;; Operand 0: GPR (scratch)
1827 ;; Operand 2: GPR (addend)
1828 ;; Operand 3: macc/msac
1829 ;; Operand 4: GPR (destination)
1830 ;; Operand 5: new multiplication
1831 ;; Operand 6: new addition/subtraction
1833 [(match_scratch:SI 0 "d")
1834 (set (match_operand:SI 1 "lo_operand")
1835 (match_operand:SI 2 "d_operand"))
1839 (match_operand:SI 3 "macc_msac_operand"))
1840 (clobber (scratch:SI))])
1842 (set (match_operand:SI 4 "d_operand")
1844 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1845 [(parallel [(set (match_dup 0)
1847 (clobber (match_dup 1))])
1851 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1852 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1853 operands[2], operands[0]);
1856 ;; See the comment above *mul_add_si for details.
1857 (define_insn "*mul_sub_si"
1858 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1859 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1860 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1861 (match_operand:SI 3 "register_operand" "d,d"))))
1862 (clobber (match_scratch:SI 4 "=X,l"))
1863 (clobber (match_scratch:SI 5 "=X,&d"))]
1864 "GENERATE_MADD_MSUB"
1868 [(set_attr "type" "imadd")
1869 (set_attr "accum_in" "1")
1870 (set_attr "mode" "SI")
1871 (set_attr "length" "4,8")])
1873 ;; Split *mul_sub_si if both the source and destination accumulator
1876 [(set (match_operand:SI 0 "d_operand")
1877 (minus:SI (match_operand:SI 1 "d_operand")
1878 (mult:SI (match_operand:SI 2 "d_operand")
1879 (match_operand:SI 3 "d_operand"))))
1880 (clobber (match_operand:SI 4 "lo_operand"))
1881 (clobber (match_operand:SI 5 "d_operand"))]
1883 [(parallel [(set (match_dup 5)
1884 (mult:SI (match_dup 2) (match_dup 3)))
1885 (clobber (match_dup 4))])
1886 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1889 (define_insn "*muls"
1890 [(set (match_operand:SI 0 "register_operand" "=l,d")
1891 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1892 (match_operand:SI 2 "register_operand" "d,d"))))
1893 (clobber (match_scratch:SI 3 "=X,l"))]
1898 [(set_attr "type" "imul,imul3")
1899 (set_attr "mode" "SI")])
1901 (define_expand "<u>mulsidi3"
1902 [(set (match_operand:DI 0 "register_operand")
1903 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1904 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1905 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
1907 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1908 emit_insn (fn (operands[0], operands[1], operands[2]));
1912 (define_expand "<u>mulsidi3_32bit_mips16"
1913 [(set (match_operand:DI 0 "register_operand")
1914 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1915 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1916 "!TARGET_64BIT && TARGET_MIPS16"
1920 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1921 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1922 emit_move_insn (operands[0], hilo);
1926 ;; As well as being named patterns, these instructions are used by the
1927 ;; __builtin_mips_mult<u>() functions. We must always make those functions
1928 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1929 (define_insn "<u>mulsidi3_32bit"
1930 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
1931 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1932 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1933 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP)"
1935 if (ISA_HAS_DSP_MULT)
1936 return "mult<u>\t%q0,%1,%2";
1938 return "mult<u>\t%1,%2";
1940 [(set_attr "type" "imul")
1941 (set_attr "mode" "SI")])
1943 (define_insn "<u>mulsidi3_32bit_r4000"
1944 [(set (match_operand:DI 0 "register_operand" "=d")
1945 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1946 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1947 (clobber (match_scratch:DI 3 "=x"))]
1948 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP"
1949 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1950 [(set_attr "type" "imul")
1951 (set_attr "mode" "SI")
1952 (set_attr "length" "12")])
1954 (define_insn_and_split "<u>mulsidi3_64bit"
1955 [(set (match_operand:DI 0 "register_operand" "=d")
1956 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1957 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1958 (clobber (match_scratch:TI 3 "=x"))
1959 (clobber (match_scratch:DI 4 "=d"))]
1960 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3 && !TARGET_MIPS16"
1962 "&& reload_completed"
1965 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1966 operands[2], operands[4]));
1969 [(set_attr "type" "imul")
1970 (set_attr "mode" "SI")
1971 (set (attr "length")
1972 (if_then_else (match_test "ISA_HAS_EXT_INS")
1976 (define_expand "<u>mulsidi3_64bit_mips16"
1977 [(set (match_operand:DI 0 "register_operand")
1978 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1979 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1980 "TARGET_64BIT && TARGET_MIPS16"
1982 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1983 operands[2], gen_reg_rtx (DImode)));
1987 (define_expand "<u>mulsidi3_64bit_split"
1988 [(set (match_operand:DI 0 "register_operand")
1989 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1990 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1991 (clobber (match_operand:DI 3 "register_operand"))]
1996 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1997 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1999 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM));
2000 emit_insn (gen_mfhidi_ti (operands[3], hilo));
2002 if (ISA_HAS_EXT_INS)
2003 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32),
2007 /* Zero-extend the low part. */
2008 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32));
2009 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32));
2011 /* Shift the high part into place. */
2012 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32));
2014 /* OR the two halves together. */
2015 mips_emit_binary (IOR, operands[0], operands[0], operands[3]);
2020 (define_insn "<u>mulsidi3_64bit_hilo"
2021 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2024 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2025 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
2027 "TARGET_64BIT && !TARGET_FIX_R4000"
2029 [(set_attr "type" "imul")
2030 (set_attr "mode" "SI")])
2032 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
2033 (define_insn "mulsidi3_64bit_dmul"
2034 [(set (match_operand:DI 0 "register_operand" "=d")
2035 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2036 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2037 (clobber (match_scratch:DI 3 "=l"))]
2038 "TARGET_64BIT && ISA_HAS_DMUL3"
2040 [(set_attr "type" "imul3")
2041 (set_attr "mode" "DI")])
2043 ;; Widening multiply with negation.
2044 (define_insn "*muls<u>_di"
2045 [(set (match_operand:DI 0 "muldiv_target_operand" "=x")
2048 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2049 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2050 "!TARGET_64BIT && ISA_HAS_MULS"
2052 [(set_attr "type" "imul")
2053 (set_attr "mode" "SI")])
2055 ;; As well as being named patterns, these instructions are used by the
2056 ;; __builtin_mips_msub<u>() functions. We must always make those functions
2057 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2059 ;; This leads to a slight inconsistency. We honor any tuning overrides
2060 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
2061 ;; even if !ISA_HAS_DSP_MULT.
2062 (define_insn "<u>msubsidi4"
2063 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2065 (match_operand:DI 3 "muldiv_target_operand" "0")
2067 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2068 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2069 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
2071 if (ISA_HAS_DSP_MULT)
2072 return "msub<u>\t%q0,%1,%2";
2073 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
2074 return "msub<u>\t%1,%2";
2076 return "msac<u>\t$0,%1,%2";
2078 [(set_attr "type" "imadd")
2079 (set_attr "accum_in" "3")
2080 (set_attr "mode" "SI")])
2082 ;; _highpart patterns
2084 (define_expand "<su>mulsi3_highpart"
2085 [(set (match_operand:SI 0 "register_operand")
2088 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2089 (any_extend:DI (match_operand:SI 2 "register_operand")))
2094 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
2097 else if (TARGET_MIPS16)
2098 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2101 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
2106 (define_insn_and_split "<su>mulsi3_highpart_internal"
2107 [(set (match_operand:SI 0 "register_operand" "=d")
2110 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2111 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2113 (clobber (match_scratch:SI 3 "=l"))]
2114 "!ISA_HAS_MULHI && !TARGET_MIPS16"
2115 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2116 "&& reload_completed && !TARGET_FIX_R4000"
2119 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2123 [(set_attr "type" "imul")
2124 (set_attr "mode" "SI")
2125 (set_attr "length" "8")])
2127 (define_expand "<su>mulsi3_highpart_split"
2128 [(set (match_operand:SI 0 "register_operand")
2131 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2132 (any_extend:DI (match_operand:SI 2 "register_operand")))
2140 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2141 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2142 emit_insn (gen_mfhisi_ti (operands[0], hilo));
2146 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2147 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2148 emit_insn (gen_mfhisi_di (operands[0], hilo));
2153 (define_insn "<su>mulsi3_highpart_mulhi_internal"
2154 [(set (match_operand:SI 0 "register_operand" "=d")
2158 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2159 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2161 (clobber (match_scratch:SI 3 "=l"))]
2163 "mulhi<u>\t%0,%1,%2"
2164 [(set_attr "type" "imul3")
2165 (set_attr "mode" "SI")])
2167 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
2168 [(set (match_operand:SI 0 "register_operand" "=d")
2173 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2174 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2176 (clobber (match_scratch:SI 3 "=l"))]
2178 "mulshi<u>\t%0,%1,%2"
2179 [(set_attr "type" "imul3")
2180 (set_attr "mode" "SI")])
2182 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
2183 ;; errata MD(0), which says that dmultu does not always produce the
2185 (define_expand "<su>muldi3_highpart"
2186 [(set (match_operand:DI 0 "register_operand")
2189 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2190 (any_extend:TI (match_operand:DI 2 "register_operand")))
2192 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2195 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2198 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1],
2203 (define_insn_and_split "<su>muldi3_highpart_internal"
2204 [(set (match_operand:DI 0 "register_operand" "=d")
2207 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2208 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2210 (clobber (match_scratch:DI 3 "=l"))]
2213 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2214 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2215 "&& reload_completed && !TARGET_FIX_R4000"
2218 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2222 [(set_attr "type" "imul")
2223 (set_attr "mode" "DI")
2224 (set_attr "length" "8")])
2226 (define_expand "<su>muldi3_highpart_split"
2227 [(set (match_operand:DI 0 "register_operand")
2230 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2231 (any_extend:TI (match_operand:DI 2 "register_operand")))
2237 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2238 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2239 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2243 (define_expand "<u>mulditi3"
2244 [(set (match_operand:TI 0 "register_operand")
2245 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2246 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2247 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2253 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2254 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2255 emit_move_insn (operands[0], hilo);
2257 else if (TARGET_FIX_R4000)
2258 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2260 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2265 (define_insn "<u>mulditi3_internal"
2266 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2267 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2268 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2270 && !TARGET_FIX_R4000
2271 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2273 [(set_attr "type" "imul")
2274 (set_attr "mode" "DI")])
2276 (define_insn "<u>mulditi3_r4000"
2277 [(set (match_operand:TI 0 "register_operand" "=d")
2278 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2279 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2280 (clobber (match_scratch:TI 3 "=x"))]
2283 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2284 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2285 [(set_attr "type" "imul")
2286 (set_attr "mode" "DI")
2287 (set_attr "length" "12")])
2289 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2290 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2292 (define_insn "madsi"
2293 [(set (match_operand:SI 0 "register_operand" "+l")
2294 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2295 (match_operand:SI 2 "register_operand" "d"))
2299 [(set_attr "type" "imadd")
2300 (set_attr "accum_in" "0")
2301 (set_attr "mode" "SI")])
2303 ;; See the comment above <u>msubsidi4 for the relationship between
2304 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2305 (define_insn "<u>maddsidi4"
2306 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2308 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2309 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2310 (match_operand:DI 3 "muldiv_target_operand" "0")))]
2311 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2315 return "mad<u>\t%1,%2";
2316 else if (ISA_HAS_DSP_MULT)
2317 return "madd<u>\t%q0,%1,%2";
2318 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2319 return "madd<u>\t%1,%2";
2321 /* See comment in *macc. */
2322 return "%[macc<u>\t%@,%1,%2%]";
2324 [(set_attr "type" "imadd")
2325 (set_attr "accum_in" "3")
2326 (set_attr "mode" "SI")])
2328 ;; Floating point multiply accumulate instructions.
2330 (define_insn "*madd4<mode>"
2331 [(set (match_operand:ANYF 0 "register_operand" "=f")
2332 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2333 (match_operand:ANYF 2 "register_operand" "f"))
2334 (match_operand:ANYF 3 "register_operand" "f")))]
2335 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2336 "madd.<fmt>\t%0,%3,%1,%2"
2337 [(set_attr "type" "fmadd")
2338 (set_attr "accum_in" "3")
2339 (set_attr "mode" "<UNITMODE>")])
2341 (define_insn "*madd3<mode>"
2342 [(set (match_operand:ANYF 0 "register_operand" "=f")
2343 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2344 (match_operand:ANYF 2 "register_operand" "f"))
2345 (match_operand:ANYF 3 "register_operand" "0")))]
2346 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2347 "madd.<fmt>\t%0,%1,%2"
2348 [(set_attr "type" "fmadd")
2349 (set_attr "accum_in" "3")
2350 (set_attr "mode" "<UNITMODE>")])
2352 (define_insn "*msub4<mode>"
2353 [(set (match_operand:ANYF 0 "register_operand" "=f")
2354 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2355 (match_operand:ANYF 2 "register_operand" "f"))
2356 (match_operand:ANYF 3 "register_operand" "f")))]
2357 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2358 "msub.<fmt>\t%0,%3,%1,%2"
2359 [(set_attr "type" "fmadd")
2360 (set_attr "accum_in" "3")
2361 (set_attr "mode" "<UNITMODE>")])
2363 (define_insn "*msub3<mode>"
2364 [(set (match_operand:ANYF 0 "register_operand" "=f")
2365 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2366 (match_operand:ANYF 2 "register_operand" "f"))
2367 (match_operand:ANYF 3 "register_operand" "0")))]
2368 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2369 "msub.<fmt>\t%0,%1,%2"
2370 [(set_attr "type" "fmadd")
2371 (set_attr "accum_in" "3")
2372 (set_attr "mode" "<UNITMODE>")])
2374 (define_insn "*nmadd4<mode>"
2375 [(set (match_operand:ANYF 0 "register_operand" "=f")
2376 (neg:ANYF (plus:ANYF
2377 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2378 (match_operand:ANYF 2 "register_operand" "f"))
2379 (match_operand:ANYF 3 "register_operand" "f"))))]
2380 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2381 && TARGET_FUSED_MADD
2382 && HONOR_SIGNED_ZEROS (<MODE>mode)
2383 && !HONOR_NANS (<MODE>mode)"
2384 "nmadd.<fmt>\t%0,%3,%1,%2"
2385 [(set_attr "type" "fmadd")
2386 (set_attr "accum_in" "3")
2387 (set_attr "mode" "<UNITMODE>")])
2389 (define_insn "*nmadd3<mode>"
2390 [(set (match_operand:ANYF 0 "register_operand" "=f")
2391 (neg:ANYF (plus:ANYF
2392 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2393 (match_operand:ANYF 2 "register_operand" "f"))
2394 (match_operand:ANYF 3 "register_operand" "0"))))]
2395 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2396 && TARGET_FUSED_MADD
2397 && HONOR_SIGNED_ZEROS (<MODE>mode)
2398 && !HONOR_NANS (<MODE>mode)"
2399 "nmadd.<fmt>\t%0,%1,%2"
2400 [(set_attr "type" "fmadd")
2401 (set_attr "accum_in" "3")
2402 (set_attr "mode" "<UNITMODE>")])
2404 (define_insn "*nmadd4<mode>_fastmath"
2405 [(set (match_operand:ANYF 0 "register_operand" "=f")
2407 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2408 (match_operand:ANYF 2 "register_operand" "f"))
2409 (match_operand:ANYF 3 "register_operand" "f")))]
2410 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2411 && TARGET_FUSED_MADD
2412 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2413 && !HONOR_NANS (<MODE>mode)"
2414 "nmadd.<fmt>\t%0,%3,%1,%2"
2415 [(set_attr "type" "fmadd")
2416 (set_attr "accum_in" "3")
2417 (set_attr "mode" "<UNITMODE>")])
2419 (define_insn "*nmadd3<mode>_fastmath"
2420 [(set (match_operand:ANYF 0 "register_operand" "=f")
2422 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2423 (match_operand:ANYF 2 "register_operand" "f"))
2424 (match_operand:ANYF 3 "register_operand" "0")))]
2425 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2426 && TARGET_FUSED_MADD
2427 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2428 && !HONOR_NANS (<MODE>mode)"
2429 "nmadd.<fmt>\t%0,%1,%2"
2430 [(set_attr "type" "fmadd")
2431 (set_attr "accum_in" "3")
2432 (set_attr "mode" "<UNITMODE>")])
2434 (define_insn "*nmsub4<mode>"
2435 [(set (match_operand:ANYF 0 "register_operand" "=f")
2436 (neg:ANYF (minus:ANYF
2437 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2438 (match_operand:ANYF 3 "register_operand" "f"))
2439 (match_operand:ANYF 1 "register_operand" "f"))))]
2440 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2441 && TARGET_FUSED_MADD
2442 && HONOR_SIGNED_ZEROS (<MODE>mode)
2443 && !HONOR_NANS (<MODE>mode)"
2444 "nmsub.<fmt>\t%0,%1,%2,%3"
2445 [(set_attr "type" "fmadd")
2446 (set_attr "accum_in" "1")
2447 (set_attr "mode" "<UNITMODE>")])
2449 (define_insn "*nmsub3<mode>"
2450 [(set (match_operand:ANYF 0 "register_operand" "=f")
2451 (neg:ANYF (minus:ANYF
2452 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2453 (match_operand:ANYF 3 "register_operand" "f"))
2454 (match_operand:ANYF 1 "register_operand" "0"))))]
2455 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2456 && TARGET_FUSED_MADD
2457 && HONOR_SIGNED_ZEROS (<MODE>mode)
2458 && !HONOR_NANS (<MODE>mode)"
2459 "nmsub.<fmt>\t%0,%1,%2"
2460 [(set_attr "type" "fmadd")
2461 (set_attr "accum_in" "1")
2462 (set_attr "mode" "<UNITMODE>")])
2464 (define_insn "*nmsub4<mode>_fastmath"
2465 [(set (match_operand:ANYF 0 "register_operand" "=f")
2467 (match_operand:ANYF 1 "register_operand" "f")
2468 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2469 (match_operand:ANYF 3 "register_operand" "f"))))]
2470 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2471 && TARGET_FUSED_MADD
2472 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2473 && !HONOR_NANS (<MODE>mode)"
2474 "nmsub.<fmt>\t%0,%1,%2,%3"
2475 [(set_attr "type" "fmadd")
2476 (set_attr "accum_in" "1")
2477 (set_attr "mode" "<UNITMODE>")])
2479 (define_insn "*nmsub3<mode>_fastmath"
2480 [(set (match_operand:ANYF 0 "register_operand" "=f")
2482 (match_operand:ANYF 1 "register_operand" "f")
2483 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2484 (match_operand:ANYF 3 "register_operand" "0"))))]
2485 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2486 && TARGET_FUSED_MADD
2487 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2488 && !HONOR_NANS (<MODE>mode)"
2489 "nmsub.<fmt>\t%0,%1,%2"
2490 [(set_attr "type" "fmadd")
2491 (set_attr "accum_in" "1")
2492 (set_attr "mode" "<UNITMODE>")])
2495 ;; ....................
2497 ;; DIVISION and REMAINDER
2499 ;; ....................
2502 (define_expand "div<mode>3"
2503 [(set (match_operand:ANYF 0 "register_operand")
2504 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2505 (match_operand:ANYF 2 "register_operand")))]
2506 "<divide_condition>"
2508 if (const_1_operand (operands[1], <MODE>mode))
2509 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2510 operands[1] = force_reg (<MODE>mode, operands[1]);
2513 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2515 ;; If an mfc1 or dmfc1 happens to access the floating point register
2516 ;; file at the same time a long latency operation (div, sqrt, recip,
2517 ;; sqrt) iterates an intermediate result back through the floating
2518 ;; point register file bypass, then instead returning the correct
2519 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2520 ;; result of the long latency operation.
2522 ;; The workaround is to insert an unconditional 'mov' from/to the
2523 ;; long latency op destination register.
2525 (define_insn "*div<mode>3"
2526 [(set (match_operand:ANYF 0 "register_operand" "=f")
2527 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2528 (match_operand:ANYF 2 "register_operand" "f")))]
2529 "<divide_condition>"
2532 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2534 return "div.<fmt>\t%0,%1,%2";
2536 [(set_attr "type" "fdiv")
2537 (set_attr "mode" "<UNITMODE>")
2538 (set (attr "length")
2539 (if_then_else (match_test "TARGET_FIX_SB1")
2543 (define_insn "*recip<mode>3"
2544 [(set (match_operand:ANYF 0 "register_operand" "=f")
2545 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2546 (match_operand:ANYF 2 "register_operand" "f")))]
2547 "<recip_condition> && flag_unsafe_math_optimizations"
2550 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2552 return "recip.<fmt>\t%0,%2";
2554 [(set_attr "type" "frdiv")
2555 (set_attr "mode" "<UNITMODE>")
2556 (set (attr "length")
2557 (if_then_else (match_test "TARGET_FIX_SB1")
2561 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2562 ;; with negative operands. We use special libgcc functions instead.
2564 ;; Expand generates divmod instructions for individual division and modulus
2565 ;; operations. We then rely on CSE to reuse earlier divmods where possible.
2566 ;; This means that, when generating MIPS16 code, it is better not to expose
2567 ;; the fixed LO register until after CSE has finished. However, it's still
2568 ;; better to split before register allocation, so that we don't allocate
2569 ;; one of the scarce MIPS16 registers to an unused result.
2570 (define_insn_and_split "divmod<mode>4"
2571 [(set (match_operand:GPR 0 "register_operand" "=kl")
2572 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2573 (match_operand:GPR 2 "register_operand" "d")))
2574 (set (match_operand:GPR 3 "register_operand" "=d")
2575 (mod:GPR (match_dup 1)
2577 "!TARGET_FIX_VR4120"
2579 "&& ((TARGET_MIPS16 && cse_not_expected) || reload_completed)"
2582 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2584 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2587 [(set_attr "type" "idiv")
2588 (set_attr "mode" "<MODE>")
2589 (set_attr "length" "8")])
2591 ;; See the comment above "divmod<mode>4" for the MIPS16 handling.
2592 (define_insn_and_split "udivmod<mode>4"
2593 [(set (match_operand:GPR 0 "register_operand" "=kl")
2594 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2595 (match_operand:GPR 2 "register_operand" "d")))
2596 (set (match_operand:GPR 3 "register_operand" "=d")
2597 (umod:GPR (match_dup 1)
2601 "(TARGET_MIPS16 && cse_not_expected) || reload_completed"
2604 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2606 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2609 [(set_attr "type" "idiv")
2610 (set_attr "mode" "<MODE>")
2611 (set_attr "length" "8")])
2613 (define_expand "<u>divmod<mode>4_split"
2614 [(set (match_operand:GPR 0 "register_operand")
2615 (any_mod:GPR (match_operand:GPR 1 "register_operand")
2616 (match_operand:GPR 2 "register_operand")))]
2623 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2624 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1],
2626 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo));
2630 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2631 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1],
2633 emit_insn (gen_mfhi<mode>_di (operands[0], hilo));
2638 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2639 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x")
2641 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2642 (match_operand:GPR 2 "register_operand" "d"))]
2645 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2646 [(set_attr "type" "idiv")
2647 (set_attr "mode" "<GPR:MODE>")])
2650 ;; ....................
2654 ;; ....................
2656 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2657 ;; "*div[sd]f3" comment for details).
2659 (define_insn "sqrt<mode>2"
2660 [(set (match_operand:ANYF 0 "register_operand" "=f")
2661 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2665 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2667 return "sqrt.<fmt>\t%0,%1";
2669 [(set_attr "type" "fsqrt")
2670 (set_attr "mode" "<UNITMODE>")
2671 (set (attr "length")
2672 (if_then_else (match_test "TARGET_FIX_SB1")
2676 (define_insn "*rsqrt<mode>a"
2677 [(set (match_operand:ANYF 0 "register_operand" "=f")
2678 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2679 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2680 "<recip_condition> && flag_unsafe_math_optimizations"
2683 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2685 return "rsqrt.<fmt>\t%0,%2";
2687 [(set_attr "type" "frsqrt")
2688 (set_attr "mode" "<UNITMODE>")
2689 (set (attr "length")
2690 (if_then_else (match_test "TARGET_FIX_SB1")
2694 (define_insn "*rsqrt<mode>b"
2695 [(set (match_operand:ANYF 0 "register_operand" "=f")
2696 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2697 (match_operand:ANYF 2 "register_operand" "f"))))]
2698 "<recip_condition> && flag_unsafe_math_optimizations"
2701 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2703 return "rsqrt.<fmt>\t%0,%2";
2705 [(set_attr "type" "frsqrt")
2706 (set_attr "mode" "<UNITMODE>")
2707 (set (attr "length")
2708 (if_then_else (match_test "TARGET_FIX_SB1")
2713 ;; ....................
2717 ;; ....................
2719 ;; Do not use the integer abs macro instruction, since that signals an
2720 ;; exception on -2147483648 (sigh).
2722 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2723 ;; invalid; it does not clear their sign bits. We therefore can't use
2724 ;; abs.fmt if the signs of NaNs matter.
2726 (define_insn "abs<mode>2"
2727 [(set (match_operand:ANYF 0 "register_operand" "=f")
2728 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2729 "!HONOR_NANS (<MODE>mode)"
2731 [(set_attr "type" "fabs")
2732 (set_attr "mode" "<UNITMODE>")])
2735 ;; ...................
2737 ;; Count leading zeroes.
2739 ;; ...................
2742 (define_insn "clz<mode>2"
2743 [(set (match_operand:GPR 0 "register_operand" "=d")
2744 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2747 [(set_attr "type" "clz")
2748 (set_attr "mode" "<MODE>")])
2751 ;; ...................
2753 ;; Count number of set bits.
2755 ;; ...................
2758 (define_insn "popcount<mode>2"
2759 [(set (match_operand:GPR 0 "register_operand" "=d")
2760 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2763 [(set_attr "type" "pop")
2764 (set_attr "mode" "<MODE>")])
2766 ;; The POP instruction is special as it does not take into account the upper
2767 ;; 32bits and is documented that way.
2768 (define_insn "*popcountdi2_trunc"
2769 [(set (match_operand:SI 0 "register_operand" "=d")
2770 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))]
2771 "ISA_HAS_POP && TARGET_64BIT"
2773 [(set_attr "type" "pop")
2774 (set_attr "mode" "SI")])
2777 ;; ....................
2779 ;; NEGATION and ONE'S COMPLEMENT
2781 ;; ....................
2783 (define_insn "negsi2"
2784 [(set (match_operand:SI 0 "register_operand" "=d")
2785 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2789 return "neg\t%0,%1";
2791 return "subu\t%0,%.,%1";
2793 [(set_attr "alu_type" "sub")
2794 (set_attr "mode" "SI")])
2796 (define_insn "negdi2"
2797 [(set (match_operand:DI 0 "register_operand" "=d")
2798 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2799 "TARGET_64BIT && !TARGET_MIPS16"
2801 [(set_attr "alu_type" "sub")
2802 (set_attr "mode" "DI")])
2804 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2805 ;; invalid; it does not flip their sign bit. We therefore can't use
2806 ;; neg.fmt if the signs of NaNs matter.
2808 (define_insn "neg<mode>2"
2809 [(set (match_operand:ANYF 0 "register_operand" "=f")
2810 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2811 "!HONOR_NANS (<MODE>mode)"
2813 [(set_attr "type" "fneg")
2814 (set_attr "mode" "<UNITMODE>")])
2816 (define_insn "one_cmpl<mode>2"
2817 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
2818 (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))]
2822 return "not\t%0,%1";
2824 return "nor\t%0,%.,%1";
2826 [(set_attr "alu_type" "not")
2827 (set_attr "compression" "micromips,*")
2828 (set_attr "mode" "<MODE>")])
2831 ;; ....................
2835 ;; ....................
2838 ;; Many of these instructions use trivial define_expands, because we
2839 ;; want to use a different set of constraints when TARGET_MIPS16.
2841 (define_expand "and<mode>3"
2842 [(set (match_operand:GPR 0 "register_operand")
2843 (and:GPR (match_operand:GPR 1 "register_operand")
2844 (match_operand:GPR 2 "and_reg_operand")))])
2846 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
2847 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
2848 ;; Note that this variant does not trigger for SI mode because we require
2849 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
2850 ;; sign-extended SImode value.
2852 ;; These are possible combinations for operand 1 and 2. The table
2853 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
2854 ;; 16=MIPS16, x=match, S=split):
2856 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
2862 ;; 0xffff_ffff x S x S x
2867 (define_insn "*and<mode>3"
2868 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d")
2869 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d")
2870 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))]
2871 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2875 switch (which_alternative)
2878 operands[1] = gen_lowpart (QImode, operands[1]);
2879 return "lbu\t%0,%1";
2881 operands[1] = gen_lowpart (HImode, operands[1]);
2882 return "lhu\t%0,%1";
2884 operands[1] = gen_lowpart (SImode, operands[1]);
2885 return "lwu\t%0,%1";
2888 return "andi\t%0,%1,%x2";
2890 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
2891 operands[2] = GEN_INT (len);
2892 return "<d>ext\t%0,%1,0,%2";
2897 return "and\t%0,%1,%2";
2902 [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical")
2903 (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*")
2904 (set_attr "mode" "<MODE>")])
2906 (define_insn "*and<mode>3_mips16"
2907 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
2908 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0")
2909 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
2910 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2912 switch (which_alternative)
2915 operands[1] = gen_lowpart (QImode, operands[1]);
2916 return "lbu\t%0,%1";
2918 operands[1] = gen_lowpart (HImode, operands[1]);
2919 return "lhu\t%0,%1";
2921 operands[1] = gen_lowpart (SImode, operands[1]);
2922 return "lwu\t%0,%1";
2926 return "and\t%0,%2";
2931 [(set_attr "move_type" "load,load,load,shift_shift,logical")
2932 (set_attr "mode" "<MODE>")])
2934 (define_expand "ior<mode>3"
2935 [(set (match_operand:GPR 0 "register_operand")
2936 (ior:GPR (match_operand:GPR 1 "register_operand")
2937 (match_operand:GPR 2 "uns_arith_operand")))]
2941 operands[2] = force_reg (<MODE>mode, operands[2]);
2944 (define_insn "*ior<mode>3"
2945 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
2946 (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2947 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
2953 [(set_attr "alu_type" "or")
2954 (set_attr "compression" "micromips,*,*")
2955 (set_attr "mode" "<MODE>")])
2957 (define_insn "*ior<mode>3_mips16"
2958 [(set (match_operand:GPR 0 "register_operand" "=d")
2959 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2960 (match_operand:GPR 2 "register_operand" "d")))]
2963 [(set_attr "alu_type" "or")
2964 (set_attr "mode" "<MODE>")])
2966 (define_expand "xor<mode>3"
2967 [(set (match_operand:GPR 0 "register_operand")
2968 (xor:GPR (match_operand:GPR 1 "register_operand")
2969 (match_operand:GPR 2 "uns_arith_operand")))]
2973 (define_insn "*xor<mode>3"
2974 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
2975 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2976 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
2982 [(set_attr "alu_type" "xor")
2983 (set_attr "compression" "micromips,*,*")
2984 (set_attr "mode" "<MODE>")])
2986 (define_insn "*xor<mode>3_mips16"
2987 [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t")
2988 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d")
2989 (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))]
2996 [(set_attr "alu_type" "xor")
2997 (set_attr "mode" "<MODE>")
2998 (set_attr "extended_mips16" "no,no,yes,no")])
3000 (define_insn "*nor<mode>3"
3001 [(set (match_operand:GPR 0 "register_operand" "=d")
3002 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
3003 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
3006 [(set_attr "alu_type" "nor")
3007 (set_attr "mode" "<MODE>")])
3010 ;; ....................
3014 ;; ....................
3018 (define_insn "truncdfsf2"
3019 [(set (match_operand:SF 0 "register_operand" "=f")
3020 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3021 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3023 [(set_attr "type" "fcvt")
3024 (set_attr "cnv_mode" "D2S")
3025 (set_attr "mode" "SF")])
3027 ;; Integer truncation patterns. Truncating SImode values to smaller
3028 ;; modes is a no-op, as it is for most other GCC ports. Truncating
3029 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
3030 ;; need to make sure that the lower 32 bits are properly sign-extended
3031 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
3032 ;; smaller than SImode is equivalent to two separate truncations:
3035 ;; DI ---> HI == DI ---> SI ---> HI
3036 ;; DI ---> QI == DI ---> SI ---> QI
3038 ;; Step A needs a real instruction but step B does not.
3040 (define_insn "truncdi<mode>2"
3041 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
3042 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
3047 [(set_attr "move_type" "sll0,store")
3048 (set_attr "mode" "SI")])
3050 ;; Combiner patterns to optimize shift/truncate combinations.
3052 (define_insn "*ashr_trunc<mode>"
3053 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3055 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3056 (match_operand:DI 2 "const_arith_operand" ""))))]
3057 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3059 [(set_attr "type" "shift")
3060 (set_attr "mode" "<MODE>")])
3062 (define_insn "*lshr32_trunc<mode>"
3063 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3065 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3067 "TARGET_64BIT && !TARGET_MIPS16"
3069 [(set_attr "type" "shift")
3070 (set_attr "mode" "<MODE>")])
3072 ;; Logical shift by more than 32 results in proper SI values so truncation is
3073 ;; removed by the middle end. Note that a logical shift by 32 is handled by
3074 ;; the previous pattern.
3075 (define_insn "*<optab>_trunc<mode>_exts"
3076 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3078 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
3079 (match_operand:DI 2 "const_arith_operand" ""))))]
3080 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
3082 [(set_attr "type" "arith")
3083 (set_attr "mode" "<MODE>")])
3086 ;; ....................
3090 ;; ....................
3094 (define_expand "zero_extendsidi2"
3095 [(set (match_operand:DI 0 "register_operand")
3096 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
3099 (define_insn_and_split "*zero_extendsidi2"
3100 [(set (match_operand:DI 0 "register_operand" "=d,d")
3101 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3102 "TARGET_64BIT && !ISA_HAS_EXT_INS"
3106 "&& reload_completed && REG_P (operands[1])"
3108 (ashift:DI (match_dup 1) (const_int 32)))
3110 (lshiftrt:DI (match_dup 0) (const_int 32)))]
3111 { operands[1] = gen_lowpart (DImode, operands[1]); }
3112 [(set_attr "move_type" "shift_shift,load")
3113 (set_attr "mode" "DI")])
3115 (define_insn "*zero_extendsidi2_dext"
3116 [(set (match_operand:DI 0 "register_operand" "=d,d")
3117 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3118 "TARGET_64BIT && ISA_HAS_EXT_INS"
3122 [(set_attr "move_type" "arith,load")
3123 (set_attr "mode" "DI")])
3125 ;; See the comment before the *and<mode>3 pattern why this is generated by
3129 [(set (match_operand:DI 0 "register_operand")
3130 (and:DI (match_operand:DI 1 "register_operand")
3131 (const_int 4294967295)))]
3132 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
3134 (ashift:DI (match_dup 1) (const_int 32)))
3136 (lshiftrt:DI (match_dup 0) (const_int 32)))])
3138 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
3139 [(set (match_operand:GPR 0 "register_operand")
3140 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3143 if (TARGET_MIPS16 && !GENERATE_MIPS16E
3144 && !memory_operand (operands[1], <SHORT:MODE>mode))
3146 emit_insn (gen_and<GPR:mode>3 (operands[0],
3147 gen_lowpart (<GPR:MODE>mode, operands[1]),
3148 force_reg (<GPR:MODE>mode,
3149 GEN_INT (<SHORT:mask>))));
3154 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
3155 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3157 (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))]
3160 andi\t%0,%1,<SHORT:mask>
3161 andi\t%0,%1,<SHORT:mask>
3162 l<SHORT:size>u\t%0,%1"
3163 [(set_attr "move_type" "andi,andi,load")
3164 (set_attr "compression" "micromips,*,*")
3165 (set_attr "mode" "<GPR:MODE>")])
3167 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
3168 [(set (match_operand:GPR 0 "register_operand" "=d")
3169 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
3171 "ze<SHORT:size>\t%0"
3172 ;; This instruction is effectively a special encoding of ANDI.
3173 [(set_attr "move_type" "andi")
3174 (set_attr "mode" "<GPR:MODE>")])
3176 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
3177 [(set (match_operand:GPR 0 "register_operand" "=d")
3178 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
3180 "l<SHORT:size>u\t%0,%1"
3181 [(set_attr "move_type" "load")
3182 (set_attr "mode" "<GPR:MODE>")])
3184 (define_expand "zero_extendqihi2"
3185 [(set (match_operand:HI 0 "register_operand")
3186 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3189 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
3191 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
3197 (define_insn "*zero_extendqihi2"
3198 [(set (match_operand:HI 0 "register_operand" "=d,d")
3199 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3204 [(set_attr "move_type" "andi,load")
3205 (set_attr "mode" "HI")])
3207 (define_insn "*zero_extendqihi2_mips16"
3208 [(set (match_operand:HI 0 "register_operand" "=d")
3209 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3212 [(set_attr "move_type" "load")
3213 (set_attr "mode" "HI")])
3215 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3217 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
3218 [(set (match_operand:GPR 0 "register_operand" "=d")
3220 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3221 "TARGET_64BIT && !TARGET_MIPS16"
3223 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3224 return "andi\t%0,%1,%x2";
3226 [(set_attr "alu_type" "and")
3227 (set_attr "mode" "<GPR:MODE>")])
3229 (define_insn "*zero_extendhi_truncqi"
3230 [(set (match_operand:HI 0 "register_operand" "=d")
3232 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3233 "TARGET_64BIT && !TARGET_MIPS16"
3235 [(set_attr "alu_type" "and")
3236 (set_attr "mode" "HI")])
3239 ;; ....................
3243 ;; ....................
3246 ;; Those for integer source operand are ordered widest source type first.
3248 ;; When TARGET_64BIT, all SImode integer and accumulator registers
3249 ;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
3250 ;; and truncdisi2). We can therefore get rid of register->register
3251 ;; instructions if we constrain the source to be in the same register as
3254 ;; Only the pre-reload scheduler sees the type of the register alternatives;
3255 ;; we split them into nothing before the post-reload scheduler runs.
3256 ;; These alternatives therefore have type "move" in order to reflect
3257 ;; what happens if the two pre-reload operands cannot be tied, and are
3258 ;; instead allocated two separate GPRs. We don't distinguish between
3259 ;; the GPR and LO cases because we don't usually know during pre-reload
3260 ;; scheduling whether an operand will be LO or not.
3261 (define_insn_and_split "extendsidi2"
3262 [(set (match_operand:DI 0 "register_operand" "=d,l,d")
3263 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
3269 "&& reload_completed && register_operand (operands[1], VOIDmode)"
3272 emit_note (NOTE_INSN_DELETED);
3275 [(set_attr "move_type" "move,move,load")
3276 (set_attr "mode" "DI")])
3278 (define_expand "extend<SHORT:mode><GPR:mode>2"
3279 [(set (match_operand:GPR 0 "register_operand")
3280 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3283 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
3284 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3285 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3289 l<SHORT:size>\t%0,%1"
3290 [(set_attr "move_type" "signext,load")
3291 (set_attr "mode" "<GPR:MODE>")])
3293 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3294 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3296 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3297 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3300 l<SHORT:size>\t%0,%1"
3301 "&& reload_completed && REG_P (operands[1])"
3302 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3303 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3305 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3306 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3307 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3309 [(set_attr "move_type" "shift_shift,load")
3310 (set_attr "mode" "<GPR:MODE>")])
3312 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3313 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3315 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3318 se<SHORT:size>\t%0,%1
3319 l<SHORT:size>\t%0,%1"
3320 [(set_attr "move_type" "signext,load")
3321 (set_attr "mode" "<GPR:MODE>")])
3323 (define_expand "extendqihi2"
3324 [(set (match_operand:HI 0 "register_operand")
3325 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3328 (define_insn "*extendqihi2_mips16e"
3329 [(set (match_operand:HI 0 "register_operand" "=d,d")
3330 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3335 [(set_attr "move_type" "signext,load")
3336 (set_attr "mode" "SI")])
3338 (define_insn_and_split "*extendqihi2"
3339 [(set (match_operand:HI 0 "register_operand" "=d,d")
3341 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3342 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3346 "&& reload_completed && REG_P (operands[1])"
3347 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3348 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3350 operands[0] = gen_lowpart (SImode, operands[0]);
3351 operands[1] = gen_lowpart (SImode, operands[1]);
3352 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3353 - GET_MODE_BITSIZE (QImode));
3355 [(set_attr "move_type" "shift_shift,load")
3356 (set_attr "mode" "SI")])
3358 (define_insn "*extendqihi2_seb"
3359 [(set (match_operand:HI 0 "register_operand" "=d,d")
3361 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3366 [(set_attr "move_type" "signext,load")
3367 (set_attr "mode" "SI")])
3369 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3370 ;; use the shift/truncate patterns.
3372 (define_insn_and_split "*extenddi_truncate<mode>"
3373 [(set (match_operand:DI 0 "register_operand" "=d")
3375 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3376 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3378 "&& reload_completed"
3380 (ashift:DI (match_dup 1)
3383 (ashiftrt:DI (match_dup 2)
3386 operands[2] = gen_lowpart (DImode, operands[0]);
3387 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3389 [(set_attr "move_type" "shift_shift")
3390 (set_attr "mode" "DI")])
3392 (define_insn_and_split "*extendsi_truncate<mode>"
3393 [(set (match_operand:SI 0 "register_operand" "=d")
3395 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3396 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3398 "&& reload_completed"
3400 (ashift:DI (match_dup 1)
3403 (truncate:SI (ashiftrt:DI (match_dup 2)
3406 operands[2] = gen_lowpart (DImode, operands[0]);
3407 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3409 [(set_attr "move_type" "shift_shift")
3410 (set_attr "mode" "SI")])
3412 (define_insn_and_split "*extendhi_truncateqi"
3413 [(set (match_operand:HI 0 "register_operand" "=d")
3415 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3416 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3418 "&& reload_completed"
3420 (ashift:DI (match_dup 1)
3423 (truncate:HI (ashiftrt:DI (match_dup 2)
3426 operands[2] = gen_lowpart (DImode, operands[0]);
3428 [(set_attr "move_type" "shift_shift")
3429 (set_attr "mode" "SI")])
3431 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3432 [(set (match_operand:GPR 0 "register_operand" "=d")
3434 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3435 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3437 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3438 return "exts\t%0,%1,0,%m2";
3440 [(set_attr "type" "arith")
3441 (set_attr "mode" "<GPR:MODE>")])
3443 (define_insn "*extendhi_truncateqi_exts"
3444 [(set (match_operand:HI 0 "register_operand" "=d")
3446 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3447 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3449 [(set_attr "type" "arith")
3450 (set_attr "mode" "SI")])
3452 (define_insn "extendsfdf2"
3453 [(set (match_operand:DF 0 "register_operand" "=f")
3454 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3455 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3457 [(set_attr "type" "fcvt")
3458 (set_attr "cnv_mode" "S2D")
3459 (set_attr "mode" "DF")])
3462 ;; ....................
3466 ;; ....................
3468 (define_expand "fix_truncdfsi2"
3469 [(set (match_operand:SI 0 "register_operand")
3470 (fix:SI (match_operand:DF 1 "register_operand")))]
3471 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3473 if (!ISA_HAS_TRUNC_W)
3475 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3480 (define_insn "fix_truncdfsi2_insn"
3481 [(set (match_operand:SI 0 "register_operand" "=f")
3482 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3483 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3485 [(set_attr "type" "fcvt")
3486 (set_attr "mode" "DF")
3487 (set_attr "cnv_mode" "D2I")])
3489 (define_insn "fix_truncdfsi2_macro"
3490 [(set (match_operand:SI 0 "register_operand" "=f")
3491 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3492 (clobber (match_scratch:DF 2 "=d"))]
3493 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3495 if (mips_nomacro.nesting_level > 0)
3496 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3498 return "trunc.w.d %0,%1,%2";
3500 [(set_attr "type" "fcvt")
3501 (set_attr "mode" "DF")
3502 (set_attr "cnv_mode" "D2I")
3503 (set_attr "length" "36")])
3505 (define_expand "fix_truncsfsi2"
3506 [(set (match_operand:SI 0 "register_operand")
3507 (fix:SI (match_operand:SF 1 "register_operand")))]
3510 if (!ISA_HAS_TRUNC_W)
3512 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3517 (define_insn "fix_truncsfsi2_insn"
3518 [(set (match_operand:SI 0 "register_operand" "=f")
3519 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3520 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3522 [(set_attr "type" "fcvt")
3523 (set_attr "mode" "SF")
3524 (set_attr "cnv_mode" "S2I")])
3526 (define_insn "fix_truncsfsi2_macro"
3527 [(set (match_operand:SI 0 "register_operand" "=f")
3528 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3529 (clobber (match_scratch:SF 2 "=d"))]
3530 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3532 if (mips_nomacro.nesting_level > 0)
3533 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3535 return "trunc.w.s %0,%1,%2";
3537 [(set_attr "type" "fcvt")
3538 (set_attr "mode" "SF")
3539 (set_attr "cnv_mode" "S2I")
3540 (set_attr "length" "36")])
3543 (define_insn "fix_truncdfdi2"
3544 [(set (match_operand:DI 0 "register_operand" "=f")
3545 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3546 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3548 [(set_attr "type" "fcvt")
3549 (set_attr "mode" "DF")
3550 (set_attr "cnv_mode" "D2I")])
3553 (define_insn "fix_truncsfdi2"
3554 [(set (match_operand:DI 0 "register_operand" "=f")
3555 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3556 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3558 [(set_attr "type" "fcvt")
3559 (set_attr "mode" "SF")
3560 (set_attr "cnv_mode" "S2I")])
3563 (define_insn "floatsidf2"
3564 [(set (match_operand:DF 0 "register_operand" "=f")
3565 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3566 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3568 [(set_attr "type" "fcvt")
3569 (set_attr "mode" "DF")
3570 (set_attr "cnv_mode" "I2D")])
3573 (define_insn "floatdidf2"
3574 [(set (match_operand:DF 0 "register_operand" "=f")
3575 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3576 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3578 [(set_attr "type" "fcvt")
3579 (set_attr "mode" "DF")
3580 (set_attr "cnv_mode" "I2D")])
3583 (define_insn "floatsisf2"
3584 [(set (match_operand:SF 0 "register_operand" "=f")
3585 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3588 [(set_attr "type" "fcvt")
3589 (set_attr "mode" "SF")
3590 (set_attr "cnv_mode" "I2S")])
3593 (define_insn "floatdisf2"
3594 [(set (match_operand:SF 0 "register_operand" "=f")
3595 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3596 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3598 [(set_attr "type" "fcvt")
3599 (set_attr "mode" "SF")
3600 (set_attr "cnv_mode" "I2S")])
3603 (define_expand "fixuns_truncdfsi2"
3604 [(set (match_operand:SI 0 "register_operand")
3605 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3606 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3608 rtx reg1 = gen_reg_rtx (DFmode);
3609 rtx reg2 = gen_reg_rtx (DFmode);
3610 rtx reg3 = gen_reg_rtx (SImode);
3611 rtx label1 = gen_label_rtx ();
3612 rtx label2 = gen_label_rtx ();
3614 REAL_VALUE_TYPE offset;
3616 real_2expN (&offset, 31, DFmode);
3618 if (reg1) /* Turn off complaints about unreached code. */
3620 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3621 do_pending_stack_adjust ();
3623 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3624 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3626 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3627 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3628 gen_rtx_LABEL_REF (VOIDmode, label2)));
3631 emit_label (label1);
3632 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3633 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3634 (BITMASK_HIGH, SImode)));
3636 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3637 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3639 emit_label (label2);
3641 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3642 fields, and can't be used for REG_NOTES anyway). */
3643 emit_use (stack_pointer_rtx);
3649 (define_expand "fixuns_truncdfdi2"
3650 [(set (match_operand:DI 0 "register_operand")
3651 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3652 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3654 rtx reg1 = gen_reg_rtx (DFmode);
3655 rtx reg2 = gen_reg_rtx (DFmode);
3656 rtx reg3 = gen_reg_rtx (DImode);
3657 rtx label1 = gen_label_rtx ();
3658 rtx label2 = gen_label_rtx ();
3660 REAL_VALUE_TYPE offset;
3662 real_2expN (&offset, 63, DFmode);
3664 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3665 do_pending_stack_adjust ();
3667 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3668 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3670 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3671 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3672 gen_rtx_LABEL_REF (VOIDmode, label2)));
3675 emit_label (label1);
3676 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3677 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3678 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3680 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3681 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3683 emit_label (label2);
3685 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3686 fields, and can't be used for REG_NOTES anyway). */
3687 emit_use (stack_pointer_rtx);
3692 (define_expand "fixuns_truncsfsi2"
3693 [(set (match_operand:SI 0 "register_operand")
3694 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3697 rtx reg1 = gen_reg_rtx (SFmode);
3698 rtx reg2 = gen_reg_rtx (SFmode);
3699 rtx reg3 = gen_reg_rtx (SImode);
3700 rtx label1 = gen_label_rtx ();
3701 rtx label2 = gen_label_rtx ();
3703 REAL_VALUE_TYPE offset;
3705 real_2expN (&offset, 31, SFmode);
3707 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3708 do_pending_stack_adjust ();
3710 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3711 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3713 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3714 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3715 gen_rtx_LABEL_REF (VOIDmode, label2)));
3718 emit_label (label1);
3719 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3720 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3721 (BITMASK_HIGH, SImode)));
3723 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3724 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3726 emit_label (label2);
3728 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3729 fields, and can't be used for REG_NOTES anyway). */
3730 emit_use (stack_pointer_rtx);
3735 (define_expand "fixuns_truncsfdi2"
3736 [(set (match_operand:DI 0 "register_operand")
3737 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3738 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3740 rtx reg1 = gen_reg_rtx (SFmode);
3741 rtx reg2 = gen_reg_rtx (SFmode);
3742 rtx reg3 = gen_reg_rtx (DImode);
3743 rtx label1 = gen_label_rtx ();
3744 rtx label2 = gen_label_rtx ();
3746 REAL_VALUE_TYPE offset;
3748 real_2expN (&offset, 63, SFmode);
3750 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3751 do_pending_stack_adjust ();
3753 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3754 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3756 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3757 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3758 gen_rtx_LABEL_REF (VOIDmode, label2)));
3761 emit_label (label1);
3762 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3763 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3764 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3766 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3767 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3769 emit_label (label2);
3771 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3772 fields, and can't be used for REG_NOTES anyway). */
3773 emit_use (stack_pointer_rtx);
3778 ;; ....................
3782 ;; ....................
3784 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3786 (define_expand "extvmisalign<mode>"
3787 [(set (match_operand:GPR 0 "register_operand")
3788 (sign_extract:GPR (match_operand:BLK 1 "memory_operand")
3789 (match_operand 2 "const_int_operand")
3790 (match_operand 3 "const_int_operand")))]
3793 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3794 INTVAL (operands[2]),
3795 INTVAL (operands[3]),
3796 /*unsigned=*/ false))
3802 (define_expand "extv<mode>"
3803 [(set (match_operand:GPR 0 "register_operand")
3804 (sign_extract:GPR (match_operand:GPR 1 "register_operand")
3805 (match_operand 2 "const_int_operand")
3806 (match_operand 3 "const_int_operand")))]
3809 if (UINTVAL (operands[2]) > 32)
3813 (define_insn "*extv<mode>"
3814 [(set (match_operand:GPR 0 "register_operand" "=d")
3815 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3816 (match_operand 2 "const_int_operand" "")
3817 (match_operand 3 "const_int_operand" "")))]
3818 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3819 "exts\t%0,%1,%3,%m2"
3820 [(set_attr "type" "arith")
3821 (set_attr "mode" "<MODE>")])
3823 (define_expand "extzvmisalign<mode>"
3824 [(set (match_operand:GPR 0 "register_operand")
3825 (zero_extract:GPR (match_operand:BLK 1 "memory_operand")
3826 (match_operand 2 "const_int_operand")
3827 (match_operand 3 "const_int_operand")))]
3830 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3831 INTVAL (operands[2]),
3832 INTVAL (operands[3]),
3833 /*unsigned=*/ true))
3839 (define_expand "extzv<mode>"
3840 [(set (match_operand:GPR 0 "register_operand")
3841 (zero_extract:GPR (match_operand:GPR 1 "register_operand")
3842 (match_operand 2 "const_int_operand")
3843 (match_operand 3 "const_int_operand")))]
3846 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3847 INTVAL (operands[3])))
3851 (define_insn "*extzv<mode>"
3852 [(set (match_operand:GPR 0 "register_operand" "=d")
3853 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3854 (match_operand 2 "const_int_operand" "")
3855 (match_operand 3 "const_int_operand" "")))]
3856 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3857 INTVAL (operands[3]))"
3858 "<d>ext\t%0,%1,%3,%2"
3859 [(set_attr "type" "arith")
3860 (set_attr "mode" "<MODE>")])
3862 (define_insn "*extzv_truncsi_exts"
3863 [(set (match_operand:SI 0 "register_operand" "=d")
3865 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3866 (match_operand 2 "const_int_operand" "")
3867 (match_operand 3 "const_int_operand" ""))))]
3868 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3870 [(set_attr "type" "arith")
3871 (set_attr "mode" "SI")])
3874 (define_expand "insvmisalign<mode>"
3875 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")
3876 (match_operand 1 "const_int_operand")
3877 (match_operand 2 "const_int_operand"))
3878 (match_operand:GPR 3 "reg_or_0_operand"))]
3881 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3882 INTVAL (operands[1]),
3883 INTVAL (operands[2])))
3889 (define_expand "insv<mode>"
3890 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand")
3891 (match_operand 1 "const_int_operand")
3892 (match_operand 2 "const_int_operand"))
3893 (match_operand:GPR 3 "reg_or_0_operand"))]
3896 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3897 INTVAL (operands[2])))
3901 (define_insn "*insv<mode>"
3902 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3903 (match_operand:SI 1 "const_int_operand" "")
3904 (match_operand:SI 2 "const_int_operand" ""))
3905 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3906 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3907 INTVAL (operands[2]))"
3908 "<d>ins\t%0,%z3,%2,%1"
3909 [(set_attr "type" "arith")
3910 (set_attr "mode" "<MODE>")])
3912 ;; Combiner pattern for cins (clear and insert bit field). We can
3913 ;; implement mask-and-shift-left operation with this. Note that if
3914 ;; the upper bit of the mask is set in an SImode operation, the mask
3915 ;; itself will be sign-extended. mask_low_and_shift_len will
3916 ;; therefore be greater than our threshold of 32.
3918 (define_insn "*cins<mode>"
3919 [(set (match_operand:GPR 0 "register_operand" "=d")
3921 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3922 (match_operand:GPR 2 "const_int_operand" ""))
3923 (match_operand:GPR 3 "const_int_operand" "")))]
3925 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3928 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3929 return "cins\t%0,%1,%2,%m3";
3931 [(set_attr "type" "shift")
3932 (set_attr "mode" "<MODE>")])
3934 ;; Unaligned word moves generated by the bit field patterns.
3936 ;; As far as the rtl is concerned, both the left-part and right-part
3937 ;; instructions can access the whole field. However, the real operand
3938 ;; refers to just the first or the last byte (depending on endianness).
3939 ;; We therefore use two memory operands to each instruction, one to
3940 ;; describe the rtl effect and one to use in the assembly output.
3942 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3943 ;; This allows us to use the standard length calculations for the "load"
3944 ;; and "store" type attributes.
3946 (define_insn "mov_<load>l"
3947 [(set (match_operand:GPR 0 "register_operand" "=d")
3948 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3949 (match_operand:QI 2 "memory_operand" "ZC")]
3951 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3953 [(set_attr "move_type" "load")
3954 (set_attr "mode" "<MODE>")])
3956 (define_insn "mov_<load>r"
3957 [(set (match_operand:GPR 0 "register_operand" "=d")
3958 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3959 (match_operand:QI 2 "memory_operand" "ZC")
3960 (match_operand:GPR 3 "register_operand" "0")]
3961 UNSPEC_LOAD_RIGHT))]
3962 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3964 [(set_attr "move_type" "load")
3965 (set_attr "mode" "<MODE>")])
3967 (define_insn "mov_<store>l"
3968 [(set (match_operand:BLK 0 "memory_operand" "=m")
3969 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3970 (match_operand:QI 2 "memory_operand" "ZC")]
3971 UNSPEC_STORE_LEFT))]
3972 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3974 [(set_attr "move_type" "store")
3975 (set_attr "mode" "<MODE>")])
3977 (define_insn "mov_<store>r"
3978 [(set (match_operand:BLK 0 "memory_operand" "+m")
3979 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3980 (match_operand:QI 2 "memory_operand" "ZC")
3982 UNSPEC_STORE_RIGHT))]
3983 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3985 [(set_attr "move_type" "store")
3986 (set_attr "mode" "<MODE>")])
3988 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3989 ;; The required value is:
3991 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3993 ;; which translates to:
3995 ;; lui op0,%highest(op1)
3996 ;; daddiu op0,op0,%higher(op1)
3998 ;; daddiu op0,op0,%hi(op1)
4001 ;; The split is deferred until after flow2 to allow the peephole2 below
4003 (define_insn_and_split "*lea_high64"
4004 [(set (match_operand:DI 0 "register_operand" "=d")
4005 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
4006 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4008 "&& epilogue_completed"
4009 [(set (match_dup 0) (high:DI (match_dup 2)))
4010 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
4011 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
4012 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4013 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
4015 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4016 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
4018 [(set_attr "length" "20")])
4020 ;; Use a scratch register to reduce the latency of the above pattern
4021 ;; on superscalar machines. The optimized sequence is:
4023 ;; lui op1,%highest(op2)
4025 ;; daddiu op1,op1,%higher(op2)
4027 ;; daddu op1,op1,op0
4029 [(set (match_operand:DI 1 "d_operand")
4030 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
4031 (match_scratch:DI 0 "d")]
4032 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4033 [(set (match_dup 1) (high:DI (match_dup 3)))
4034 (set (match_dup 0) (high:DI (match_dup 4)))
4035 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
4036 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
4037 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
4039 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
4040 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
4043 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
4044 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
4045 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
4046 ;; used once. We can then use the sequence:
4048 ;; lui op0,%highest(op1)
4050 ;; daddiu op0,op0,%higher(op1)
4051 ;; daddiu op2,op2,%lo(op1)
4053 ;; daddu op0,op0,op2
4055 ;; which takes 4 cycles on most superscalar targets.
4056 (define_insn_and_split "*lea64"
4057 [(set (match_operand:DI 0 "register_operand" "=d")
4058 (match_operand:DI 1 "absolute_symbolic_operand" ""))
4059 (clobber (match_scratch:DI 2 "=&d"))]
4060 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
4062 "&& reload_completed"
4063 [(set (match_dup 0) (high:DI (match_dup 3)))
4064 (set (match_dup 2) (high:DI (match_dup 4)))
4065 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4066 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
4067 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
4068 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
4070 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4071 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
4073 [(set_attr "length" "24")])
4075 ;; Split HIGHs into:
4080 ;; on MIPS16 targets.
4082 [(set (match_operand:P 0 "d_operand")
4083 (high:P (match_operand:P 1 "symbolic_operand_with_high")))]
4084 "TARGET_MIPS16 && reload_completed"
4085 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH))
4086 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))])
4088 (define_insn "*unshifted_high"
4089 [(set (match_operand:P 0 "d_operand" "=d")
4090 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")]
4091 UNSPEC_UNSHIFTED_HIGH))]
4094 [(set_attr "extended_mips16" "yes")])
4096 ;; Insns to fetch a symbol from a big GOT.
4098 (define_insn_and_split "*xgot_hi<mode>"
4099 [(set (match_operand:P 0 "register_operand" "=d")
4100 (high:P (match_operand:P 1 "got_disp_operand" "")))]
4101 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4103 "&& reload_completed"
4104 [(set (match_dup 0) (high:P (match_dup 2)))
4105 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
4107 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
4108 operands[3] = pic_offset_table_rtx;
4110 [(set_attr "got" "xgot_high")
4111 (set_attr "mode" "<MODE>")])
4113 (define_insn_and_split "*xgot_lo<mode>"
4114 [(set (match_operand:P 0 "register_operand" "=d")
4115 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4116 (match_operand:P 2 "got_disp_operand" "")))]
4117 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4119 "&& reload_completed"
4121 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
4122 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
4123 [(set_attr "got" "load")
4124 (set_attr "mode" "<MODE>")])
4126 ;; Insns to fetch a symbol from a normal GOT.
4128 (define_insn_and_split "*got_disp<mode>"
4129 [(set (match_operand:P 0 "register_operand" "=d")
4130 (match_operand:P 1 "got_disp_operand" ""))]
4131 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
4133 "&& reload_completed"
4134 [(set (match_dup 0) (match_dup 2))]
4135 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
4136 [(set_attr "got" "load")
4137 (set_attr "mode" "<MODE>")])
4139 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
4141 (define_insn_and_split "*got_page<mode>"
4142 [(set (match_operand:P 0 "register_operand" "=d")
4143 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
4144 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
4146 "&& reload_completed"
4147 [(set (match_dup 0) (match_dup 2))]
4148 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
4149 [(set_attr "got" "load")
4150 (set_attr "mode" "<MODE>")])
4152 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
4153 (define_expand "unspec_got_<mode>"
4154 [(unspec:P [(match_operand:P 0)
4155 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
4157 ;; Lower-level instructions for loading an address from the GOT.
4158 ;; We could use MEMs, but an unspec gives more optimization
4161 (define_insn "load_got<mode>"
4162 [(set (match_operand:P 0 "register_operand" "=d")
4163 (unspec:P [(match_operand:P 1 "register_operand" "d")
4164 (match_operand:P 2 "immediate_operand" "")]
4167 "<load>\t%0,%R2(%1)"
4168 [(set_attr "got" "load")
4169 (set_attr "mode" "<MODE>")])
4171 ;; Instructions for adding the low 16 bits of an address to a register.
4172 ;; Operand 2 is the address: mips_print_operand works out which relocation
4173 ;; should be applied.
4175 (define_insn "*low<mode>"
4176 [(set (match_operand:P 0 "register_operand" "=d")
4177 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4178 (match_operand:P 2 "immediate_operand" "")))]
4180 "<d>addiu\t%0,%1,%R2"
4181 [(set_attr "alu_type" "add")
4182 (set_attr "mode" "<MODE>")])
4184 (define_insn "*low<mode>_mips16"
4185 [(set (match_operand:P 0 "register_operand" "=d")
4186 (lo_sum:P (match_operand:P 1 "register_operand" "0")
4187 (match_operand:P 2 "immediate_operand" "")))]
4190 [(set_attr "alu_type" "add")
4191 (set_attr "mode" "<MODE>")
4192 (set_attr "extended_mips16" "yes")])
4194 ;; Expose MIPS16 uses of the global pointer after reload if the function
4195 ;; is responsible for setting up the register itself.
4197 [(set (match_operand:GPR 0 "d_operand")
4198 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
4199 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
4200 [(set (match_dup 0) (match_dup 1))]
4201 { operands[1] = pic_offset_table_rtx; })
4203 ;; Allow combine to split complex const_int load sequences, using operand 2
4204 ;; to store the intermediate results. See move_operand for details.
4206 [(set (match_operand:GPR 0 "register_operand")
4207 (match_operand:GPR 1 "splittable_const_int_operand"))
4208 (clobber (match_operand:GPR 2 "register_operand"))]
4212 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
4216 ;; Likewise, for symbolic operands.
4218 [(set (match_operand:P 0 "register_operand")
4219 (match_operand:P 1))
4220 (clobber (match_operand:P 2 "register_operand"))]
4221 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
4222 [(set (match_dup 0) (match_dup 3))]
4224 mips_split_symbol (operands[2], operands[1],
4225 MAX_MACHINE_MODE, &operands[3]);
4228 ;; 64-bit integer moves
4230 ;; Unlike most other insns, the move insns can't be split with
4231 ;; different predicates, because register spilling and other parts of
4232 ;; the compiler, have memoized the insn number already.
4234 (define_expand "movdi"
4235 [(set (match_operand:DI 0 "")
4236 (match_operand:DI 1 ""))]
4239 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4243 ;; For mips16, we need a special case to handle storing $31 into
4244 ;; memory, since we don't have a constraint to match $31. This
4245 ;; instruction can be generated by save_restore_insns.
4247 (define_insn "*mov<mode>_ra"
4248 [(set (match_operand:GPR 0 "stack_operand" "=m")
4249 (reg:GPR RETURN_ADDR_REGNUM))]
4252 [(set_attr "move_type" "store")
4253 (set_attr "mode" "<MODE>")])
4255 (define_insn "*movdi_32bit"
4256 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
4257 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
4258 "!TARGET_64BIT && !TARGET_MIPS16
4259 && (register_operand (operands[0], DImode)
4260 || reg_or_0_operand (operands[1], DImode))"
4261 { return mips_output_move (operands[0], operands[1]); }
4262 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
4264 (if_then_else (eq_attr "move_type" "imul")
4266 (const_string "DI")))])
4268 (define_insn "*movdi_32bit_mips16"
4269 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4270 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
4271 "!TARGET_64BIT && TARGET_MIPS16
4272 && (register_operand (operands[0], DImode)
4273 || register_operand (operands[1], DImode))"
4274 { return mips_output_move (operands[0], operands[1]); }
4275 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4276 (set_attr "mode" "DI")])
4278 (define_insn "*movdi_64bit"
4279 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
4280 (match_operand:DI 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4281 "TARGET_64BIT && !TARGET_MIPS16
4282 && (register_operand (operands[0], DImode)
4283 || reg_or_0_operand (operands[1], DImode))"
4284 { return mips_output_move (operands[0], operands[1]); }
4285 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore")
4286 (set_attr "mode" "DI")])
4288 (define_insn "*movdi_64bit_mips16"
4289 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4290 (match_operand:DI 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4291 "TARGET_64BIT && TARGET_MIPS16
4292 && (register_operand (operands[0], DImode)
4293 || register_operand (operands[1], DImode))"
4294 { return mips_output_move (operands[0], operands[1]); }
4295 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4296 (set_attr "mode" "DI")])
4298 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4299 ;; when the original load is a 4 byte instruction but the add and the
4300 ;; load are 2 2 byte instructions.
4303 [(set (match_operand:DI 0 "d_operand")
4304 (mem:DI (plus:DI (match_dup 0)
4305 (match_operand:DI 1 "const_int_operand"))))]
4306 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4307 && !TARGET_DEBUG_D_MODE
4308 && ((INTVAL (operands[1]) < 0
4309 && INTVAL (operands[1]) >= -0x10)
4310 || (INTVAL (operands[1]) >= 32 * 8
4311 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4312 || (INTVAL (operands[1]) >= 0
4313 && INTVAL (operands[1]) < 32 * 8
4314 && (INTVAL (operands[1]) & 7) != 0))"
4315 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4316 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4318 HOST_WIDE_INT val = INTVAL (operands[1]);
4321 operands[2] = const0_rtx;
4322 else if (val >= 32 * 8)
4326 operands[1] = GEN_INT (0x8 + off);
4327 operands[2] = GEN_INT (val - off - 0x8);
4333 operands[1] = GEN_INT (off);
4334 operands[2] = GEN_INT (val - off);
4338 ;; 32-bit Integer moves
4340 ;; Unlike most other insns, the move insns can't be split with
4341 ;; different predicates, because register spilling and other parts of
4342 ;; the compiler, have memoized the insn number already.
4344 (define_expand "mov<mode>"
4345 [(set (match_operand:IMOVE32 0 "")
4346 (match_operand:IMOVE32 1 ""))]
4349 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4353 ;; The difference between these two is whether or not ints are allowed
4354 ;; in FP registers (off by default, use -mdebugh to enable).
4356 (define_insn "*mov<mode>_internal"
4357 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4358 (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!u,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4360 && (register_operand (operands[0], <MODE>mode)
4361 || reg_or_0_operand (operands[1], <MODE>mode))"
4362 { return mips_output_move (operands[0], operands[1]); }
4363 [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore")
4364 (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*")
4365 (set_attr "mode" "SI")])
4367 (define_insn "*mov<mode>_mips16"
4368 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4369 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4371 && (register_operand (operands[0], <MODE>mode)
4372 || register_operand (operands[1], <MODE>mode))"
4373 { return mips_output_move (operands[0], operands[1]); }
4374 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4375 (set_attr "mode" "SI")])
4377 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4378 ;; when the original load is a 4 byte instruction but the add and the
4379 ;; load are 2 2 byte instructions.
4382 [(set (match_operand:SI 0 "d_operand")
4383 (mem:SI (plus:SI (match_dup 0)
4384 (match_operand:SI 1 "const_int_operand"))))]
4385 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4386 && ((INTVAL (operands[1]) < 0
4387 && INTVAL (operands[1]) >= -0x80)
4388 || (INTVAL (operands[1]) >= 32 * 4
4389 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4390 || (INTVAL (operands[1]) >= 0
4391 && INTVAL (operands[1]) < 32 * 4
4392 && (INTVAL (operands[1]) & 3) != 0))"
4393 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4394 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4396 HOST_WIDE_INT val = INTVAL (operands[1]);
4399 operands[2] = const0_rtx;
4400 else if (val >= 32 * 4)
4404 operands[1] = GEN_INT (0x7c + off);
4405 operands[2] = GEN_INT (val - off - 0x7c);
4411 operands[1] = GEN_INT (off);
4412 operands[2] = GEN_INT (val - off);
4416 ;; On the mips16, we can split a load of certain constants into a load
4417 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4421 [(set (match_operand:SI 0 "d_operand")
4422 (match_operand:SI 1 "const_int_operand"))]
4423 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4424 && INTVAL (operands[1]) >= 0x100
4425 && INTVAL (operands[1]) <= 0xff + 0x7f"
4426 [(set (match_dup 0) (match_dup 1))
4427 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4429 int val = INTVAL (operands[1]);
4431 operands[1] = GEN_INT (0xff);
4432 operands[2] = GEN_INT (val - 0xff);
4435 ;; MIPS4 supports loading and storing a floating point register from
4436 ;; the sum of two general registers. We use two versions for each of
4437 ;; these four instructions: one where the two general registers are
4438 ;; SImode, and one where they are DImode. This is because general
4439 ;; registers will be in SImode when they hold 32-bit values, but,
4440 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4441 ;; instructions will still work correctly.
4443 ;; ??? Perhaps it would be better to support these instructions by
4444 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4445 ;; these instructions can only be used to load and store floating
4446 ;; point registers, that would probably cause trouble in reload.
4448 (define_insn "*<ANYF:loadx>_<P:mode>"
4449 [(set (match_operand:ANYF 0 "register_operand" "=f")
4450 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4451 (match_operand:P 2 "register_operand" "d"))))]
4453 "<ANYF:loadx>\t%0,%1(%2)"
4454 [(set_attr "type" "fpidxload")
4455 (set_attr "mode" "<ANYF:UNITMODE>")])
4457 (define_insn "*<ANYF:storex>_<P:mode>"
4458 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4459 (match_operand:P 2 "register_operand" "d")))
4460 (match_operand:ANYF 0 "register_operand" "f"))]
4462 "<ANYF:storex>\t%0,%1(%2)"
4463 [(set_attr "type" "fpidxstore")
4464 (set_attr "mode" "<ANYF:UNITMODE>")])
4466 ;; Scaled indexed address load.
4467 ;; Per md.texi, we only need to look for a pattern with multiply in the
4468 ;; address expression, not shift.
4470 (define_insn "*lwxs"
4471 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4473 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4475 (match_operand:P 2 "register_operand" "d"))))]
4478 [(set_attr "type" "load")
4479 (set_attr "mode" "SI")])
4481 ;; 16-bit Integer moves
4483 ;; Unlike most other insns, the move insns can't be split with
4484 ;; different predicates, because register spilling and other parts of
4485 ;; the compiler, have memoized the insn number already.
4486 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4488 (define_expand "movhi"
4489 [(set (match_operand:HI 0 "")
4490 (match_operand:HI 1 ""))]
4493 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4497 (define_insn "*movhi_internal"
4498 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d")
4499 (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!u,dJ,*d*J,*a"))]
4501 && (register_operand (operands[0], HImode)
4502 || reg_or_0_operand (operands[1], HImode))"
4503 { return mips_output_move (operands[0], operands[1]); }
4504 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4505 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4506 (set_attr "mode" "HI")])
4508 (define_insn "*movhi_mips16"
4509 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4510 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4512 && (register_operand (operands[0], HImode)
4513 || register_operand (operands[1], HImode))"
4514 { return mips_output_move (operands[0], operands[1]); }
4515 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4516 (set_attr "mode" "HI")])
4518 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4519 ;; when the original load is a 4 byte instruction but the add and the
4520 ;; load are 2 2 byte instructions.
4523 [(set (match_operand:HI 0 "d_operand")
4524 (mem:HI (plus:SI (match_dup 0)
4525 (match_operand:SI 1 "const_int_operand"))))]
4526 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4527 && ((INTVAL (operands[1]) < 0
4528 && INTVAL (operands[1]) >= -0x80)
4529 || (INTVAL (operands[1]) >= 32 * 2
4530 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4531 || (INTVAL (operands[1]) >= 0
4532 && INTVAL (operands[1]) < 32 * 2
4533 && (INTVAL (operands[1]) & 1) != 0))"
4534 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4535 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4537 HOST_WIDE_INT val = INTVAL (operands[1]);
4540 operands[2] = const0_rtx;
4541 else if (val >= 32 * 2)
4545 operands[1] = GEN_INT (0x7e + off);
4546 operands[2] = GEN_INT (val - off - 0x7e);
4552 operands[1] = GEN_INT (off);
4553 operands[2] = GEN_INT (val - off);
4557 ;; 8-bit Integer moves
4559 ;; Unlike most other insns, the move insns can't be split with
4560 ;; different predicates, because register spilling and other parts of
4561 ;; the compiler, have memoized the insn number already.
4562 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4564 (define_expand "movqi"
4565 [(set (match_operand:QI 0 "")
4566 (match_operand:QI 1 ""))]
4569 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4573 (define_insn "*movqi_internal"
4574 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d")
4575 (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!u,dJ,*d*J,*a"))]
4577 && (register_operand (operands[0], QImode)
4578 || reg_or_0_operand (operands[1], QImode))"
4579 { return mips_output_move (operands[0], operands[1]); }
4580 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4581 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4582 (set_attr "mode" "QI")])
4584 (define_insn "*movqi_mips16"
4585 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4586 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4588 && (register_operand (operands[0], QImode)
4589 || register_operand (operands[1], QImode))"
4590 { return mips_output_move (operands[0], operands[1]); }
4591 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4592 (set_attr "mode" "QI")])
4594 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4595 ;; when the original load is a 4 byte instruction but the add and the
4596 ;; load are 2 2 byte instructions.
4599 [(set (match_operand:QI 0 "d_operand")
4600 (mem:QI (plus:SI (match_dup 0)
4601 (match_operand:SI 1 "const_int_operand"))))]
4602 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4603 && ((INTVAL (operands[1]) < 0
4604 && INTVAL (operands[1]) >= -0x80)
4605 || (INTVAL (operands[1]) >= 32
4606 && INTVAL (operands[1]) <= 31 + 0x7f))"
4607 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4608 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4610 HOST_WIDE_INT val = INTVAL (operands[1]);
4613 operands[2] = const0_rtx;
4616 operands[1] = GEN_INT (0x7f);
4617 operands[2] = GEN_INT (val - 0x7f);
4621 ;; 32-bit floating point moves
4623 (define_expand "movsf"
4624 [(set (match_operand:SF 0 "")
4625 (match_operand:SF 1 ""))]
4628 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4632 (define_insn "*movsf_hardfloat"
4633 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4634 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4636 && (register_operand (operands[0], SFmode)
4637 || reg_or_0_operand (operands[1], SFmode))"
4638 { return mips_output_move (operands[0], operands[1]); }
4639 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4640 (set_attr "mode" "SF")])
4642 (define_insn "*movsf_softfloat"
4643 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4644 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4645 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4646 && (register_operand (operands[0], SFmode)
4647 || reg_or_0_operand (operands[1], SFmode))"
4648 { return mips_output_move (operands[0], operands[1]); }
4649 [(set_attr "move_type" "move,load,store")
4650 (set_attr "mode" "SF")])
4652 (define_insn "*movsf_mips16"
4653 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4654 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4656 && (register_operand (operands[0], SFmode)
4657 || register_operand (operands[1], SFmode))"
4658 { return mips_output_move (operands[0], operands[1]); }
4659 [(set_attr "move_type" "move,move,move,load,store")
4660 (set_attr "mode" "SF")])
4662 ;; 64-bit floating point moves
4664 (define_expand "movdf"
4665 [(set (match_operand:DF 0 "")
4666 (match_operand:DF 1 ""))]
4669 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4673 (define_insn "*movdf_hardfloat"
4674 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4675 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4676 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4677 && (register_operand (operands[0], DFmode)
4678 || reg_or_0_operand (operands[1], DFmode))"
4679 { return mips_output_move (operands[0], operands[1]); }
4680 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4681 (set_attr "mode" "DF")])
4683 (define_insn "*movdf_softfloat"
4684 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4685 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4686 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4687 && (register_operand (operands[0], DFmode)
4688 || reg_or_0_operand (operands[1], DFmode))"
4689 { return mips_output_move (operands[0], operands[1]); }
4690 [(set_attr "move_type" "move,load,store")
4691 (set_attr "mode" "DF")])
4693 (define_insn "*movdf_mips16"
4694 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4695 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4697 && (register_operand (operands[0], DFmode)
4698 || register_operand (operands[1], DFmode))"
4699 { return mips_output_move (operands[0], operands[1]); }
4700 [(set_attr "move_type" "move,move,move,load,store")
4701 (set_attr "mode" "DF")])
4703 ;; 128-bit integer moves
4705 (define_expand "movti"
4706 [(set (match_operand:TI 0)
4707 (match_operand:TI 1))]
4710 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4714 (define_insn "*movti"
4715 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d")
4716 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))]
4719 && (register_operand (operands[0], TImode)
4720 || reg_or_0_operand (operands[1], TImode))"
4721 { return mips_output_move (operands[0], operands[1]); }
4722 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo")
4724 (if_then_else (eq_attr "move_type" "imul")
4726 (const_string "TI")))])
4728 (define_insn "*movti_mips16"
4729 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4730 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4733 && (register_operand (operands[0], TImode)
4734 || register_operand (operands[1], TImode))"
4736 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4737 (set_attr "mode" "TI")])
4739 ;; 128-bit floating point moves
4741 (define_expand "movtf"
4742 [(set (match_operand:TF 0)
4743 (match_operand:TF 1))]
4746 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4750 ;; This pattern handles both hard- and soft-float cases.
4751 (define_insn "*movtf"
4752 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4753 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4756 && (register_operand (operands[0], TFmode)
4757 || reg_or_0_operand (operands[1], TFmode))"
4759 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4760 (set_attr "mode" "TF")])
4762 (define_insn "*movtf_mips16"
4763 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4764 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4767 && (register_operand (operands[0], TFmode)
4768 || register_operand (operands[1], TFmode))"
4770 [(set_attr "move_type" "move,move,move,load,store")
4771 (set_attr "mode" "TF")])
4774 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4775 (match_operand:MOVE64 1 "move_operand"))]
4776 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
4779 mips_split_move_insn (operands[0], operands[1], curr_insn);
4784 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4785 (match_operand:MOVE128 1 "move_operand"))]
4786 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
4789 mips_split_move_insn (operands[0], operands[1], curr_insn);
4793 ;; When generating mips16 code, split moves of negative constants into
4794 ;; a positive "li" followed by a negation.
4796 [(set (match_operand 0 "d_operand")
4797 (match_operand 1 "const_int_operand"))]
4798 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4802 (neg:SI (match_dup 2)))]
4804 operands[2] = gen_lowpart (SImode, operands[0]);
4805 operands[3] = GEN_INT (-INTVAL (operands[1]));
4808 ;; 64-bit paired-single floating point moves
4810 (define_expand "movv2sf"
4811 [(set (match_operand:V2SF 0)
4812 (match_operand:V2SF 1))]
4813 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4815 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4819 (define_insn "*movv2sf"
4820 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4821 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4823 && TARGET_PAIRED_SINGLE_FLOAT
4824 && (register_operand (operands[0], V2SFmode)
4825 || reg_or_0_operand (operands[1], V2SFmode))"
4826 { return mips_output_move (operands[0], operands[1]); }
4827 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4828 (set_attr "mode" "DF")])
4830 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4831 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4833 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4834 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4835 ;; and the errata related to -mfix-vr4130.
4836 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4837 [(set (match_operand:GPR 0 "register_operand" "=d")
4838 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")]
4841 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4842 [(set_attr "type" "mfhi")
4843 (set_attr "mode" "<GPR:MODE>")])
4845 ;; Set the high part of a HI/LO value, given that the low part has
4846 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4847 ;; why we can't just use (reg:GPR HI_REGNUM).
4848 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4849 [(set (match_operand:HILO 0 "register_operand" "=x")
4850 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4851 (match_operand:GPR 2 "register_operand" "l")]
4855 [(set_attr "type" "mthi")
4856 (set_attr "mode" "SI")])
4858 ;; Emit a doubleword move in which exactly one of the operands is
4859 ;; a floating-point register. We can't just emit two normal moves
4860 ;; because of the constraints imposed by the FPU register model;
4861 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4862 ;; the FPR whole and use special patterns to refer to each word of
4863 ;; the other operand.
4865 (define_expand "move_doubleword_fpr<mode>"
4866 [(set (match_operand:SPLITF 0)
4867 (match_operand:SPLITF 1))]
4870 if (FP_REG_RTX_P (operands[0]))
4872 rtx low = mips_subword (operands[1], 0);
4873 rtx high = mips_subword (operands[1], 1);
4874 emit_insn (gen_load_low<mode> (operands[0], low));
4875 if (TARGET_FLOAT64 && !TARGET_64BIT)
4876 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4878 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4882 rtx low = mips_subword (operands[0], 0);
4883 rtx high = mips_subword (operands[0], 1);
4884 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4885 if (TARGET_FLOAT64 && !TARGET_64BIT)
4886 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4888 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4893 ;; Load the low word of operand 0 with operand 1.
4894 (define_insn "load_low<mode>"
4895 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4896 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4900 operands[0] = mips_subword (operands[0], 0);
4901 return mips_output_move (operands[0], operands[1]);
4903 [(set_attr "move_type" "mtc,fpload")
4904 (set_attr "mode" "<HALFMODE>")])
4906 ;; Load the high word of operand 0 from operand 1, preserving the value
4908 (define_insn "load_high<mode>"
4909 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4910 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4911 (match_operand:SPLITF 2 "register_operand" "0,0")]
4915 operands[0] = mips_subword (operands[0], 1);
4916 return mips_output_move (operands[0], operands[1]);
4918 [(set_attr "move_type" "mtc,fpload")
4919 (set_attr "mode" "<HALFMODE>")])
4921 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4922 ;; high word and 0 to store the low word.
4923 (define_insn "store_word<mode>"
4924 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4925 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4926 (match_operand 2 "const_int_operand")]
4927 UNSPEC_STORE_WORD))]
4930 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4931 return mips_output_move (operands[0], operands[1]);
4933 [(set_attr "move_type" "mfc,fpstore")
4934 (set_attr "mode" "<HALFMODE>")])
4936 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4937 ;; value in the low word.
4938 (define_insn "mthc1<mode>"
4939 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4940 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4941 (match_operand:SPLITF 2 "register_operand" "0")]
4943 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4945 [(set_attr "move_type" "mtc")
4946 (set_attr "mode" "<HALFMODE>")])
4948 ;; Move high word of operand 1 to operand 0 using mfhc1.
4949 (define_insn "mfhc1<mode>"
4950 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4951 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4953 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4955 [(set_attr "move_type" "mfc")
4956 (set_attr "mode" "<HALFMODE>")])
4958 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4959 (define_expand "load_const_gp_<mode>"
4960 [(set (match_operand:P 0 "register_operand" "=d")
4961 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4963 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4964 ;; of _gp from the start of this function. Operand 1 is the incoming
4965 ;; function address.
4966 (define_insn_and_split "loadgp_newabi_<mode>"
4967 [(set (match_operand:P 0 "register_operand" "=&d")
4968 (unspec:P [(match_operand:P 1)
4969 (match_operand:P 2 "register_operand" "d")]
4971 "mips_current_loadgp_style () == LOADGP_NEWABI"
4972 { return mips_must_initialize_gp_p () ? "#" : ""; }
4973 "&& mips_must_initialize_gp_p ()"
4974 [(set (match_dup 0) (match_dup 3))
4975 (set (match_dup 0) (match_dup 4))
4976 (set (match_dup 0) (match_dup 5))]
4978 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4979 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4980 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4982 [(set_attr "type" "ghost")])
4984 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4985 (define_insn_and_split "loadgp_absolute_<mode>"
4986 [(set (match_operand:P 0 "register_operand" "=d")
4987 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4988 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4989 { return mips_must_initialize_gp_p () ? "#" : ""; }
4990 "&& mips_must_initialize_gp_p ()"
4993 mips_emit_move (operands[0], operands[1]);
4996 [(set_attr "type" "ghost")])
4998 ;; This blockage instruction prevents the gp load from being
4999 ;; scheduled after an implicit use of gp. It also prevents
5000 ;; the load from being deleted as dead.
5001 (define_insn "loadgp_blockage"
5002 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
5005 [(set_attr "type" "ghost")])
5007 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
5008 ;; and operand 1 is the __GOTT_INDEX__ symbol.
5009 (define_insn_and_split "loadgp_rtp_<mode>"
5010 [(set (match_operand:P 0 "register_operand" "=d")
5011 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
5012 (match_operand:P 2 "symbol_ref_operand")]
5014 "mips_current_loadgp_style () == LOADGP_RTP"
5015 { return mips_must_initialize_gp_p () ? "#" : ""; }
5016 "&& mips_must_initialize_gp_p ()"
5017 [(set (match_dup 0) (high:P (match_dup 3)))
5018 (set (match_dup 0) (unspec:P [(match_dup 0)
5019 (match_dup 3)] UNSPEC_LOAD_GOT))
5020 (set (match_dup 0) (unspec:P [(match_dup 0)
5021 (match_dup 4)] UNSPEC_LOAD_GOT))]
5023 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
5024 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
5026 [(set_attr "type" "ghost")])
5028 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
5029 ;; global pointer and operand 1 is the MIPS16 register that holds
5030 ;; the required value.
5031 (define_insn_and_split "copygp_mips16_<mode>"
5032 [(set (match_operand:P 0 "register_operand" "=y")
5033 (unspec:P [(match_operand:P 1 "register_operand" "d")]
5036 { return mips_must_initialize_gp_p () ? "#" : ""; }
5037 "&& mips_must_initialize_gp_p ()"
5038 [(set (match_dup 0) (match_dup 1))]
5040 [(set_attr "type" "ghost")])
5042 ;; A placeholder for where the cprestore instruction should go,
5043 ;; if we decide we need one. Operand 0 and operand 1 are as for
5044 ;; "cprestore". Operand 2 is a register that holds the gp value.
5046 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
5047 ;; otherwise any register that holds the correct value will do.
5048 (define_insn_and_split "potential_cprestore_<mode>"
5049 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5050 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5051 (match_operand:P 2 "register_operand" "d,d")]
5052 UNSPEC_POTENTIAL_CPRESTORE))
5053 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))]
5054 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
5055 { return mips_must_initialize_gp_p () ? "#" : ""; }
5056 "mips_must_initialize_gp_p ()"
5059 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
5060 operands[2], operands[3]);
5063 [(set_attr "type" "ghost")])
5065 ;; Emit a .cprestore directive, which normally expands to a single store
5066 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
5067 ;; for the cprestore slot. Operand 1 is the offset of the slot from
5068 ;; the stack pointer. (This is redundant with operand 0, but it makes
5069 ;; things a little simpler.)
5070 (define_insn "cprestore_<mode>"
5071 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5072 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5075 "TARGET_CPRESTORE_DIRECTIVE"
5077 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
5078 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
5080 return ".cprestore\t%1";
5082 [(set_attr "type" "store")
5083 (set_attr "length" "4,12")])
5085 (define_insn "use_cprestore_<mode>"
5086 [(set (reg:P CPRESTORE_SLOT_REGNUM)
5087 (match_operand:P 0 "cprestore_load_slot_operand"))]
5090 [(set_attr "type" "ghost")])
5092 ;; Expand in-line code to clear the instruction cache between operand[0] and
5094 (define_expand "clear_cache"
5095 [(match_operand 0 "pmode_register_operand")
5096 (match_operand 1 "pmode_register_operand")]
5102 mips_expand_synci_loop (operands[0], operands[1]);
5103 emit_insn (gen_sync ());
5104 emit_insn (PMODE_INSN (gen_clear_hazard, ()));
5106 else if (mips_cache_flush_func && mips_cache_flush_func[0])
5108 rtx len = gen_reg_rtx (Pmode);
5109 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
5110 MIPS_ICACHE_SYNC (operands[0], len);
5116 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
5118 { return mips_output_sync (); })
5120 (define_insn "synci"
5121 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
5126 (define_insn "rdhwr_synci_step_<mode>"
5127 [(set (match_operand:P 0 "register_operand" "=d")
5128 (unspec_volatile [(const_int 1)]
5133 (define_insn "clear_hazard_<mode>"
5134 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
5135 (clobber (reg:P RETURN_ADDR_REGNUM))]
5138 return "%(%<bal\t1f\n"
5140 "1:\t<d>addiu\t$31,$31,12\n"
5144 [(set_attr "length" "20")])
5146 ;; Cache operations for R4000-style caches.
5147 (define_insn "mips_cache"
5148 [(set (mem:BLK (scratch))
5149 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
5150 (match_operand:QI 1 "address_operand" "p")]
5151 UNSPEC_MIPS_CACHE))]
5155 ;; Similar, but with the operands hard-coded to an R10K cache barrier
5156 ;; operation. We keep the pattern distinct so that we can identify
5157 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
5158 ;; the operation is never inserted into a delay slot.
5159 (define_insn "r10k_cache_barrier"
5160 [(set (mem:BLK (scratch))
5161 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
5164 [(set_attr "can_delay" "no")])
5166 ;; Block moves, see mips.c for more details.
5167 ;; Argument 0 is the destination
5168 ;; Argument 1 is the source
5169 ;; Argument 2 is the length
5170 ;; Argument 3 is the alignment
5172 (define_expand "movmemsi"
5173 [(parallel [(set (match_operand:BLK 0 "general_operand")
5174 (match_operand:BLK 1 "general_operand"))
5175 (use (match_operand:SI 2 ""))
5176 (use (match_operand:SI 3 "const_int_operand"))])]
5177 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5179 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5186 ;; ....................
5190 ;; ....................
5192 (define_expand "<optab><mode>3"
5193 [(set (match_operand:GPR 0 "register_operand")
5194 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5195 (match_operand:SI 2 "arith_operand")))]
5198 /* On the mips16, a shift of more than 8 is a four byte instruction,
5199 so, for a shift between 8 and 16, it is just as fast to do two
5200 shifts of 8 or less. If there is a lot of shifting going on, we
5201 may win in CSE. Otherwise combine will put the shifts back
5202 together again. This can be called by mips_function_arg, so we must
5203 be careful not to allocate a new register if we've reached the
5207 && CONST_INT_P (operands[2])
5208 && INTVAL (operands[2]) > 8
5209 && INTVAL (operands[2]) <= 16
5210 && !reload_in_progress
5211 && !reload_completed)
5213 rtx temp = gen_reg_rtx (<MODE>mode);
5215 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5216 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5217 GEN_INT (INTVAL (operands[2]) - 8)));
5222 (define_insn "*<optab><mode>3"
5223 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
5224 (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d")
5225 (match_operand:SI 2 "arith_operand" "Uib3,dI")))]
5228 if (CONST_INT_P (operands[2]))
5229 operands[2] = GEN_INT (INTVAL (operands[2])
5230 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5232 return "<d><insn>\t%0,%1,%2";
5234 [(set_attr "type" "shift")
5235 (set_attr "compression" "<shift_compression>,none")
5236 (set_attr "mode" "<MODE>")])
5238 (define_insn "*<optab>si3_extend"
5239 [(set (match_operand:DI 0 "register_operand" "=d")
5241 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5242 (match_operand:SI 2 "arith_operand" "dI"))))]
5243 "TARGET_64BIT && !TARGET_MIPS16"
5245 if (CONST_INT_P (operands[2]))
5246 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5248 return "<insn>\t%0,%1,%2";
5250 [(set_attr "type" "shift")
5251 (set_attr "mode" "SI")])
5253 (define_insn "*<optab>si3_mips16"
5254 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
5255 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d,d")
5256 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5259 if (which_alternative == 0)
5260 return "<insn>\t%0,%2";
5262 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5263 return "<insn>\t%0,%1,%2";
5265 [(set_attr "type" "shift")
5266 (set_attr "mode" "SI")
5267 (set_attr "extended_mips16" "no,no,yes")])
5269 ;; We need separate DImode MIPS16 patterns because of the irregularity
5271 (define_insn "*ashldi3_mips16"
5272 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5273 (ashift:DI (match_operand:DI 1 "register_operand" "0,d,d")
5274 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5275 "TARGET_64BIT && TARGET_MIPS16"
5277 if (which_alternative == 0)
5278 return "dsll\t%0,%2";
5280 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5281 return "dsll\t%0,%1,%2";
5283 [(set_attr "type" "shift")
5284 (set_attr "mode" "DI")
5285 (set_attr "extended_mips16" "no,no,yes")])
5287 (define_insn "*ashrdi3_mips16"
5288 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5289 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5290 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5291 "TARGET_64BIT && TARGET_MIPS16"
5293 if (CONST_INT_P (operands[2]))
5294 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5296 return "dsra\t%0,%2";
5298 [(set_attr "type" "shift")
5299 (set_attr "mode" "DI")
5300 (set_attr "extended_mips16" "no,no,yes")])
5302 (define_insn "*lshrdi3_mips16"
5303 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5304 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5305 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5306 "TARGET_64BIT && TARGET_MIPS16"
5308 if (CONST_INT_P (operands[2]))
5309 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5311 return "dsrl\t%0,%2";
5313 [(set_attr "type" "shift")
5314 (set_attr "mode" "DI")
5315 (set_attr "extended_mips16" "no,no,yes")])
5317 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5320 [(set (match_operand:GPR 0 "d_operand")
5321 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5322 (match_operand:GPR 2 "const_int_operand")))]
5323 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5324 && INTVAL (operands[2]) > 8
5325 && INTVAL (operands[2]) <= 16"
5326 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5327 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5328 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5330 ;; If we load a byte on the mips16 as a bitfield, the resulting
5331 ;; sequence of instructions is too complicated for combine, because it
5332 ;; involves four instructions: a load, a shift, a constant load into a
5333 ;; register, and an and (the key problem here is that the mips16 does
5334 ;; not have and immediate). We recognize a shift of a load in order
5335 ;; to make it simple enough for combine to understand.
5337 ;; The length here is the worst case: the length of the split version
5338 ;; will be more accurate.
5339 (define_insn_and_split ""
5340 [(set (match_operand:SI 0 "register_operand" "=d")
5341 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5342 (match_operand:SI 2 "immediate_operand" "I")))]
5346 [(set (match_dup 0) (match_dup 1))
5347 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5349 [(set_attr "type" "load")
5350 (set_attr "mode" "SI")
5351 (set_attr "length" "8")])
5353 (define_insn "rotr<mode>3"
5354 [(set (match_operand:GPR 0 "register_operand" "=d")
5355 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5356 (match_operand:SI 2 "arith_operand" "dI")))]
5359 if (CONST_INT_P (operands[2]))
5360 gcc_assert (INTVAL (operands[2]) >= 0
5361 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5363 return "<d>ror\t%0,%1,%2";
5365 [(set_attr "type" "shift")
5366 (set_attr "mode" "<MODE>")])
5369 ;; ....................
5371 ;; CONDITIONAL BRANCHES
5373 ;; ....................
5375 ;; Conditional branches on floating-point equality tests.
5377 (define_insn "*branch_fp"
5380 (match_operator 1 "equality_operator"
5381 [(match_operand:CC 2 "register_operand" "z")
5383 (label_ref (match_operand 0 "" ""))
5387 return mips_output_conditional_branch (insn, operands,
5388 MIPS_BRANCH ("b%F1", "%Z2%0"),
5389 MIPS_BRANCH ("b%W1", "%Z2%0"));
5391 [(set_attr "type" "branch")])
5393 (define_insn "*branch_fp_inverted"
5396 (match_operator 1 "equality_operator"
5397 [(match_operand:CC 2 "register_operand" "z")
5400 (label_ref (match_operand 0 "" ""))))]
5403 return mips_output_conditional_branch (insn, operands,
5404 MIPS_BRANCH ("b%W1", "%Z2%0"),
5405 MIPS_BRANCH ("b%F1", "%Z2%0"));
5407 [(set_attr "type" "branch")])
5409 ;; Conditional branches on ordered comparisons with zero.
5411 (define_insn "*branch_order<mode>"
5414 (match_operator 1 "order_operator"
5415 [(match_operand:GPR 2 "register_operand" "d")
5417 (label_ref (match_operand 0 "" ""))
5420 { return mips_output_order_conditional_branch (insn, operands, false); }
5421 [(set_attr "type" "branch")])
5423 (define_insn "*branch_order<mode>_inverted"
5426 (match_operator 1 "order_operator"
5427 [(match_operand:GPR 2 "register_operand" "d")
5430 (label_ref (match_operand 0 "" ""))))]
5432 { return mips_output_order_conditional_branch (insn, operands, true); }
5433 [(set_attr "type" "branch")])
5435 ;; Conditional branch on equality comparison.
5437 (define_insn "*branch_equality<mode>"
5440 (match_operator 1 "equality_operator"
5441 [(match_operand:GPR 2 "register_operand" "d")
5442 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5443 (label_ref (match_operand 0 "" ""))
5447 /* For a simple BNEZ or BEQZ microMIPS branch. */
5448 if (TARGET_MICROMIPS
5449 && operands[3] == const0_rtx
5450 && get_attr_length (insn) <= 8)
5451 return mips_output_conditional_branch (insn, operands,
5453 "%*b%N1z%:\t%2,%0");
5455 return mips_output_conditional_branch (insn, operands,
5456 MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
5457 MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
5459 [(set_attr "type" "branch")])
5461 (define_insn "*branch_equality<mode>_inverted"
5464 (match_operator 1 "equality_operator"
5465 [(match_operand:GPR 2 "register_operand" "d")
5466 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5468 (label_ref (match_operand 0 "" ""))))]
5471 /* For a simple BNEZ or BEQZ microMIPS branch. */
5472 if (TARGET_MICROMIPS
5473 && operands[3] == const0_rtx
5474 && get_attr_length (insn) <= 8)
5475 return mips_output_conditional_branch (insn, operands,
5477 "%*b%C0z%:\t%2,%1");
5479 return mips_output_conditional_branch (insn, operands,
5480 MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
5481 MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
5483 [(set_attr "type" "branch")])
5487 (define_insn "*branch_equality<mode>_mips16"
5490 (match_operator 1 "equality_operator"
5491 [(match_operand:GPR 2 "register_operand" "d,t")
5493 (label_ref (match_operand 0 "" ""))
5499 [(set_attr "type" "branch")])
5501 (define_insn "*branch_equality<mode>_mips16_inverted"
5504 (match_operator 1 "equality_operator"
5505 [(match_operand:GPR 2 "register_operand" "d,t")
5508 (label_ref (match_operand 0 "" ""))))]
5513 [(set_attr "type" "branch")])
5515 (define_expand "cbranch<mode>4"
5517 (if_then_else (match_operator 0 "comparison_operator"
5518 [(match_operand:GPR 1 "register_operand")
5519 (match_operand:GPR 2 "nonmemory_operand")])
5520 (label_ref (match_operand 3 ""))
5524 mips_expand_conditional_branch (operands);
5528 (define_expand "cbranch<mode>4"
5530 (if_then_else (match_operator 0 "comparison_operator"
5531 [(match_operand:SCALARF 1 "register_operand")
5532 (match_operand:SCALARF 2 "register_operand")])
5533 (label_ref (match_operand 3 ""))
5537 mips_expand_conditional_branch (operands);
5541 ;; Used to implement built-in functions.
5542 (define_expand "condjump"
5544 (if_then_else (match_operand 0)
5545 (label_ref (match_operand 1))
5548 ;; Branch if bit is set/clear.
5550 (define_insn "*branch_bit<bbv><mode>"
5553 (equality_op (zero_extract:GPR
5554 (match_operand:GPR 1 "register_operand" "d")
5556 (match_operand 2 "const_int_operand" ""))
5558 (label_ref (match_operand 0 ""))
5560 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5563 mips_output_conditional_branch (insn, operands,
5564 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5565 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5567 [(set_attr "type" "branch")
5568 (set_attr "branch_likely" "no")])
5570 (define_insn "*branch_bit<bbv><mode>_inverted"
5573 (equality_op (zero_extract:GPR
5574 (match_operand:GPR 1 "register_operand" "d")
5576 (match_operand 2 "const_int_operand" ""))
5579 (label_ref (match_operand 0 ""))))]
5580 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5583 mips_output_conditional_branch (insn, operands,
5584 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5585 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5587 [(set_attr "type" "branch")
5588 (set_attr "branch_likely" "no")])
5591 ;; ....................
5593 ;; SETTING A REGISTER FROM A COMPARISON
5595 ;; ....................
5597 ;; Destination is always set in SI mode.
5599 (define_expand "cstore<mode>4"
5600 [(set (match_operand:SI 0 "register_operand")
5601 (match_operator:SI 1 "mips_cstore_operator"
5602 [(match_operand:GPR 2 "register_operand")
5603 (match_operand:GPR 3 "nonmemory_operand")]))]
5606 mips_expand_scc (operands);
5610 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5611 [(set (match_operand:GPR2 0 "register_operand" "=d")
5612 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5614 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5616 [(set_attr "type" "slt")
5617 (set_attr "mode" "<GPR:MODE>")])
5619 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5620 [(set (match_operand:GPR2 0 "register_operand" "=t")
5621 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5623 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5625 [(set_attr "type" "slt")
5626 (set_attr "mode" "<GPR:MODE>")])
5628 ;; Generate sltiu unless using seq results in better code.
5629 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5630 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5631 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5632 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5638 [(set_attr "type" "slt")
5639 (set_attr "mode" "<GPR:MODE>")])
5641 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5642 [(set (match_operand:GPR2 0 "register_operand" "=d")
5643 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5645 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5647 [(set_attr "type" "slt")
5648 (set_attr "mode" "<GPR:MODE>")])
5650 ;; Generate sltu unless using sne results in better code.
5651 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5652 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5653 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5654 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5660 [(set_attr "type" "slt")
5661 (set_attr "mode" "<GPR:MODE>")])
5663 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5664 [(set (match_operand:GPR2 0 "register_operand" "=d")
5665 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5666 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5669 [(set_attr "type" "slt")
5670 (set_attr "mode" "<GPR:MODE>")])
5672 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5673 [(set (match_operand:GPR2 0 "register_operand" "=t")
5674 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5675 (match_operand:GPR 2 "register_operand" "d")))]
5678 [(set_attr "type" "slt")
5679 (set_attr "mode" "<GPR:MODE>")])
5681 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5682 [(set (match_operand:GPR2 0 "register_operand" "=d")
5683 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5687 [(set_attr "type" "slt")
5688 (set_attr "mode" "<GPR:MODE>")])
5690 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5691 [(set (match_operand:GPR2 0 "register_operand" "=d")
5692 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5693 (match_operand:GPR 2 "arith_operand" "dI")))]
5696 [(set_attr "type" "slt")
5697 (set_attr "mode" "<GPR:MODE>")])
5699 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5700 [(set (match_operand:GPR2 0 "register_operand" "=t,t,t")
5701 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d,d")
5702 (match_operand:GPR 2 "arith_operand" "d,Uub8,I")))]
5705 [(set_attr "type" "slt")
5706 (set_attr "mode" "<GPR:MODE>")
5707 (set_attr "extended_mips16" "no,no,yes")])
5709 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5710 [(set (match_operand:GPR2 0 "register_operand" "=d")
5711 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5712 (match_operand:GPR 2 "sle_operand" "")))]
5715 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5716 return "slt<u>\t%0,%1,%2";
5718 [(set_attr "type" "slt")
5719 (set_attr "mode" "<GPR:MODE>")])
5721 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5722 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5723 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5724 (match_operand:GPR 2 "sle_operand" "Udb8,i")))]
5727 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5728 return "slt<u>\t%1,%2";
5730 [(set_attr "type" "slt")
5731 (set_attr "mode" "<GPR:MODE>")
5732 (set_attr "extended_mips16" "no,yes")])
5735 ;; ....................
5737 ;; FLOATING POINT COMPARISONS
5739 ;; ....................
5741 (define_insn "s<code>_<mode>"
5742 [(set (match_operand:CC 0 "register_operand" "=z")
5743 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5744 (match_operand:SCALARF 2 "register_operand" "f")))]
5746 "c.<fcond>.<fmt>\t%Z0%1,%2"
5747 [(set_attr "type" "fcmp")
5748 (set_attr "mode" "FPSW")])
5750 (define_insn "s<code>_<mode>"
5751 [(set (match_operand:CC 0 "register_operand" "=z")
5752 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5753 (match_operand:SCALARF 2 "register_operand" "f")))]
5755 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5756 [(set_attr "type" "fcmp")
5757 (set_attr "mode" "FPSW")])
5760 ;; ....................
5762 ;; UNCONDITIONAL BRANCHES
5764 ;; ....................
5766 ;; Unconditional branches.
5768 (define_expand "jump"
5770 (label_ref (match_operand 0)))])
5772 (define_insn "*jump_absolute"
5774 (label_ref (match_operand 0)))]
5775 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
5777 /* Use a branch for microMIPS. The assembler will choose
5778 a 16-bit branch, a 32-bit branch, or a 32-bit jump. */
5779 if (TARGET_MICROMIPS && !TARGET_ABICALLS_PIC2)
5780 return "%*b\t%l0%/";
5782 return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/");
5784 [(set_attr "type" "jump")])
5786 (define_insn "*jump_pic"
5788 (label_ref (match_operand 0)))]
5789 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
5791 if (get_attr_length (insn) <= 8)
5792 return "%*b\t%l0%/";
5795 mips_output_load_label (operands[0]);
5796 return "%*jr\t%@%/%]";
5799 [(set_attr "type" "branch")])
5801 ;; We need a different insn for the mips16, because a mips16 branch
5802 ;; does not have a delay slot.
5804 (define_insn "*jump_mips16"
5806 (label_ref (match_operand 0 "" "")))]
5809 [(set_attr "type" "branch")
5810 (set (attr "length")
5811 ;; This calculation is like the normal branch one, but the
5812 ;; range of the unextended instruction is [-0x800, 0x7fe] rather
5813 ;; than [-0x100, 0xfe]. This translates to a range of:
5815 ;; [-(0x800 - sizeof (branch)), 0x7fe]
5816 ;; == [-0x7fe, 0x7fe]
5818 ;; from the shorten_branches reference address. Long-branch
5819 ;; sequences will replace this one, so the minimum length
5820 ;; is one instruction shorter than for conditional branches.
5821 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
5822 (le (minus (pc) (match_dup 0)) (const_int 2046)))
5824 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
5825 (le (minus (pc) (match_dup 0)) (const_int 65532)))
5827 (and (match_test "TARGET_ABICALLS")
5828 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
5830 (match_test "Pmode == SImode")
5832 ] (const_int 22)))])
5834 (define_expand "indirect_jump"
5835 [(set (pc) (match_operand 0 "register_operand"))]
5838 operands[0] = force_reg (Pmode, operands[0]);
5839 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0])));
5843 (define_insn "indirect_jump_<mode>"
5844 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5847 if (TARGET_MICROMIPS)
5848 return "%*jr%:\t%0";
5852 [(set_attr "type" "jump")
5853 (set_attr "mode" "none")])
5855 ;; A combined jump-and-move instruction, used for MIPS16 long-branch
5856 ;; sequences. Having a dedicated pattern is more convenient than
5857 ;; creating a SEQUENCE for this special case.
5858 (define_insn "indirect_jump_and_restore_<mode>"
5859 [(set (pc) (match_operand:P 1 "register_operand" "d"))
5860 (set (match_operand:P 0 "register_operand" "=d")
5861 (match_operand:P 2 "register_operand" "y"))]
5863 "%(%<jr\t%1\;move\t%0,%2%>%)"
5864 [(set_attr "type" "multi")
5865 (set_attr "extended_mips16" "yes")])
5867 (define_expand "tablejump"
5869 (match_operand 0 "register_operand"))
5870 (use (label_ref (match_operand 1 "")))]
5871 "!TARGET_MIPS16_SHORT_JUMP_TABLES"
5874 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5875 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5876 else if (TARGET_RTP_PIC)
5878 /* When generating RTP PIC, we use case table entries that are relative
5879 to the start of the function. Add the function's address to the
5881 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5882 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5883 start, 0, 0, OPTAB_WIDEN);
5886 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1])));
5890 (define_insn "tablejump_<mode>"
5892 (match_operand:P 0 "register_operand" "d"))
5893 (use (label_ref (match_operand 1 "" "")))]
5896 if (TARGET_MICROMIPS)
5897 return "%*jr%:\t%0";
5901 [(set_attr "type" "jump")
5902 (set_attr "mode" "none")])
5904 ;; For MIPS16, we don't know whether a given jump table will use short or
5905 ;; word-sized offsets until late in compilation, when we are able to determine
5906 ;; the sizes of the insns which comprise the containing function. This
5907 ;; necessitates the use of the casesi rather than the tablejump pattern, since
5908 ;; the latter tries to calculate the index of the offset to jump through early
5909 ;; in compilation, i.e. at expand time, when nothing is known about the
5910 ;; eventual function layout.
5912 (define_expand "casesi"
5913 [(match_operand:SI 0 "register_operand" "") ; index to jump on
5914 (match_operand:SI 1 "const_int_operand" "") ; lower bound
5915 (match_operand:SI 2 "const_int_operand" "") ; total range
5916 (match_operand 3 "" "") ; table label
5917 (match_operand 4 "" "")] ; out of range label
5918 "TARGET_MIPS16_SHORT_JUMP_TABLES"
5920 if (operands[1] != const0_rtx)
5922 rtx reg = gen_reg_rtx (SImode);
5923 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode);
5925 if (!arith_operand (offset, SImode))
5926 offset = force_reg (SImode, offset);
5928 emit_insn (gen_addsi3 (reg, operands[0], offset));
5932 if (!arith_operand (operands[0], SImode))
5933 operands[0] = force_reg (SImode, operands[0]);
5935 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5937 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16,
5938 (operands[0], operands[2],
5939 operands[3], operands[4])));
5944 (define_insn "casesi_internal_mips16_<mode>"
5947 (leu (match_operand:SI 0 "register_operand" "d")
5948 (match_operand:SI 1 "arith_operand" "dI"))
5951 (label_ref (match_operand 2 "" ""))]
5952 UNSPEC_CASESI_DISPATCH)
5953 (label_ref (match_operand 3 "" ""))))
5954 (clobber (match_scratch:P 4 "=d"))
5955 (clobber (match_scratch:P 5 "=d"))
5956 (clobber (reg:SI MIPS16_T_REGNUM))]
5957 "TARGET_MIPS16_SHORT_JUMP_TABLES"
5959 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
5961 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
5963 output_asm_insn ("sltu\t%0, %1", operands);
5964 output_asm_insn ("bteqz\t%3", operands);
5966 switch (GET_MODE (diff_vec))
5969 output_asm_insn ("sll\t%5, %0, 1", operands);
5970 output_asm_insn ("la\t%4, %2", operands);
5971 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
5972 output_asm_insn ("lh\t%5, 0(%5)", operands);
5976 output_asm_insn ("sll\t%5, %0, 2", operands);
5977 output_asm_insn ("la\t%4, %2", operands);
5978 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
5979 output_asm_insn ("lw\t%5, 0(%5)", operands);
5986 output_asm_insn ("addu\t%4, %4, %5", operands);
5990 [(set_attr "length" "32")])
5992 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5993 ;; While it is possible to either pull it off the stack (in the
5994 ;; o32 case) or recalculate it given t9 and our target label,
5995 ;; it takes 3 or 4 insns to do so.
5997 (define_expand "builtin_setjmp_setup"
5998 [(use (match_operand 0 "register_operand"))]
6003 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3);
6004 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
6008 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
6009 ;; that older code did recalculate the gp from $25. Continue to jump through
6010 ;; $25 for compatibility (we lose nothing by doing so).
6012 (define_expand "builtin_longjmp"
6013 [(use (match_operand 0 "register_operand"))]
6016 /* The elements of the buffer are, in order: */
6017 int W = GET_MODE_SIZE (Pmode);
6018 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6019 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W));
6020 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W));
6021 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W));
6022 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6023 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
6024 The target is bound to be using $28 as the global pointer
6025 but the current function might not be. */
6026 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
6028 /* This bit is similar to expand_builtin_longjmp except that it
6029 restores $gp as well. */
6030 mips_emit_move (hard_frame_pointer_rtx, fp);
6031 mips_emit_move (pv, lab);
6032 emit_stack_restore (SAVE_NONLOCAL, stack);
6033 mips_emit_move (gp, gpv);
6034 emit_use (hard_frame_pointer_rtx);
6035 emit_use (stack_pointer_rtx);
6037 emit_indirect_jump (pv);
6042 ;; ....................
6044 ;; Function prologue/epilogue
6046 ;; ....................
6049 (define_expand "prologue"
6053 mips_expand_prologue ();
6057 ;; Block any insns from being moved before this point, since the
6058 ;; profiling call to mcount can use various registers that aren't
6059 ;; saved or used to pass arguments.
6061 (define_insn "blockage"
6062 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
6065 [(set_attr "type" "ghost")
6066 (set_attr "mode" "none")])
6068 (define_insn "probe_stack_range_<P:mode>"
6069 [(set (match_operand:P 0 "register_operand" "=d")
6070 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
6071 (match_operand:P 2 "register_operand" "d")]
6072 UNSPEC_PROBE_STACK_RANGE))]
6074 { return mips_output_probe_stack_range (operands[0], operands[2]); }
6075 [(set_attr "type" "unknown")
6076 (set_attr "can_delay" "no")
6077 (set_attr "mode" "<MODE>")])
6079 (define_expand "epilogue"
6083 mips_expand_epilogue (false);
6087 (define_expand "sibcall_epilogue"
6091 mips_expand_epilogue (true);
6095 ;; Trivial return. Make it look like a normal return insn as that
6096 ;; allows jump optimizations to work better.
6098 (define_expand "return"
6100 "mips_can_use_return_insn ()"
6101 { mips_expand_before_return (); })
6103 (define_expand "simple_return"
6106 { mips_expand_before_return (); })
6108 (define_insn "*<optab>"
6112 [(set_attr "type" "jump")
6113 (set_attr "mode" "none")])
6117 (define_insn "<optab>_internal"
6119 (use (match_operand 0 "pmode_register_operand" ""))]
6122 if (TARGET_MICROMIPS)
6123 return "%*jr%:\t%0";
6127 [(set_attr "type" "jump")
6128 (set_attr "mode" "none")])
6130 ;; Exception return.
6131 (define_insn "mips_eret"
6133 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
6136 [(set_attr "type" "trap")
6137 (set_attr "mode" "none")])
6139 ;; Debug exception return.
6140 (define_insn "mips_deret"
6142 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
6145 [(set_attr "type" "trap")
6146 (set_attr "mode" "none")])
6148 ;; Disable interrupts.
6149 (define_insn "mips_di"
6150 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
6153 [(set_attr "type" "trap")
6154 (set_attr "mode" "none")])
6156 ;; Execution hazard barrier.
6157 (define_insn "mips_ehb"
6158 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
6161 [(set_attr "type" "trap")
6162 (set_attr "mode" "none")])
6164 ;; Read GPR from previous shadow register set.
6165 (define_insn "mips_rdpgpr"
6166 [(set (match_operand:SI 0 "register_operand" "=d")
6167 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
6171 [(set_attr "type" "move")
6172 (set_attr "mode" "SI")])
6174 ;; Move involving COP0 registers.
6175 (define_insn "cop0_move"
6176 [(set (match_operand:SI 0 "register_operand" "=B,d")
6177 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
6180 { return mips_output_move (operands[0], operands[1]); }
6181 [(set_attr "type" "mtc,mfc")
6182 (set_attr "mode" "SI")])
6184 ;; This is used in compiling the unwind routines.
6185 (define_expand "eh_return"
6186 [(use (match_operand 0 "general_operand"))]
6189 if (GET_MODE (operands[0]) != word_mode)
6190 operands[0] = convert_to_mode (word_mode, operands[0], 0);
6192 emit_insn (gen_eh_set_lr_di (operands[0]));
6194 emit_insn (gen_eh_set_lr_si (operands[0]));
6198 ;; Clobber the return address on the stack. We can't expand this
6199 ;; until we know where it will be put in the stack frame.
6201 (define_insn "eh_set_lr_si"
6202 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6203 (clobber (match_scratch:SI 1 "=&d"))]
6207 (define_insn "eh_set_lr_di"
6208 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6209 (clobber (match_scratch:DI 1 "=&d"))]
6214 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
6215 (clobber (match_scratch 1))]
6219 mips_set_return_address (operands[0], operands[1]);
6223 (define_expand "exception_receiver"
6227 /* See the comment above load_call<mode> for details. */
6228 emit_insn (gen_set_got_version ());
6230 /* If we have a call-clobbered $gp, restore it from its save slot. */
6231 if (HAVE_restore_gp_si)
6232 emit_insn (gen_restore_gp_si ());
6233 else if (HAVE_restore_gp_di)
6234 emit_insn (gen_restore_gp_di ());
6238 (define_expand "nonlocal_goto_receiver"
6242 /* See the comment above load_call<mode> for details. */
6243 emit_insn (gen_set_got_version ());
6247 ;; Restore $gp from its .cprestore stack slot. The instruction remains
6248 ;; volatile until all uses of $28 are exposed.
6249 (define_insn_and_split "restore_gp_<mode>"
6251 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP))
6252 (clobber (match_scratch:P 0 "=&d"))]
6253 "TARGET_CALL_CLOBBERED_GP"
6255 "&& epilogue_completed"
6258 mips_restore_gp_from_cprestore_slot (operands[0]);
6261 [(set_attr "type" "ghost")])
6263 ;; Move between $gp and its register save slot.
6264 (define_insn_and_split "move_gp<mode>"
6265 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
6266 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
6269 { return mips_must_initialize_gp_p () ? "#" : ""; }
6270 "mips_must_initialize_gp_p ()"
6273 mips_emit_move (operands[0], operands[1]);
6276 [(set_attr "type" "ghost")])
6279 ;; ....................
6283 ;; ....................
6285 ;; Instructions to load a call address from the GOT. The address might
6286 ;; point to a function or to a lazy binding stub. In the latter case,
6287 ;; the stub will use the dynamic linker to resolve the function, which
6288 ;; in turn will change the GOT entry to point to the function's real
6291 ;; This means that every call, even pure and constant ones, can
6292 ;; potentially modify the GOT entry. And once a stub has been called,
6293 ;; we must not call it again.
6295 ;; We represent this restriction using an imaginary, fixed, call-saved
6296 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
6297 ;; live throughout the function and to change its value after every
6298 ;; potential call site. This stops any rtx value that uses the register
6299 ;; from being computed before an earlier call. To do this, we:
6301 ;; - Ensure that the register is live on entry to the function,
6302 ;; so that it is never thought to be used uninitalized.
6304 ;; - Ensure that the register is live on exit from the function,
6305 ;; so that it is live throughout.
6307 ;; - Make each call (lazily-bound or not) use the current value
6308 ;; of GOT_VERSION_REGNUM, so that updates of the register are
6309 ;; not moved across call boundaries.
6311 ;; - Add "ghost" definitions of the register to the beginning of
6312 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
6313 ;; edges may involve calls that normal paths don't. (E.g. the
6314 ;; unwinding code that handles a non-call exception may change
6315 ;; lazily-bound GOT entries.) We do this by making the
6316 ;; exception_receiver and nonlocal_goto_receiver expanders emit
6317 ;; a set_got_version instruction.
6319 ;; - After each call (lazily-bound or not), use a "ghost"
6320 ;; update_got_version instruction to change the register's value.
6321 ;; This instruction mimics the _possible_ effect of the dynamic
6322 ;; resolver during the call and it remains live even if the call
6323 ;; itself becomes dead.
6325 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
6326 ;; The register is therefore not a valid register_operand
6327 ;; and cannot be moved to or from other registers.
6329 (define_insn "load_call<mode>"
6330 [(set (match_operand:P 0 "register_operand" "=d")
6331 (unspec:P [(match_operand:P 1 "register_operand" "d")
6332 (match_operand:P 2 "immediate_operand" "")
6333 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
6335 "<load>\t%0,%R2(%1)"
6336 [(set_attr "got" "load")
6337 (set_attr "mode" "<MODE>")])
6339 (define_insn "set_got_version"
6340 [(set (reg:SI GOT_VERSION_REGNUM)
6341 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
6344 [(set_attr "type" "ghost")])
6346 (define_insn "update_got_version"
6347 [(set (reg:SI GOT_VERSION_REGNUM)
6348 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
6351 [(set_attr "type" "ghost")])
6353 ;; Sibling calls. All these patterns use jump instructions.
6355 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
6356 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
6357 ;; is defined in terms of call_insn_operand, the same is true of the
6360 ;; When we use an indirect jump, we need a register that will be
6361 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
6362 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
6363 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
6366 (define_expand "sibcall"
6367 [(parallel [(call (match_operand 0 "")
6368 (match_operand 1 ""))
6369 (use (match_operand 2 "")) ;; next_arg_reg
6370 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6373 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
6374 operands[1], operands[2], false);
6378 (define_insn "sibcall_internal"
6379 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
6380 (match_operand 1 "" ""))]
6381 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6383 if (TARGET_MICROMIPS)
6384 return MICROMIPS_J ("j", operands, 0);
6386 return MIPS_CALL ("j", operands, 0, 1);
6388 [(set_attr "jal" "indirect,direct")
6389 (set_attr "jal_macro" "no")])
6391 (define_expand "sibcall_value"
6392 [(parallel [(set (match_operand 0 "")
6393 (call (match_operand 1 "")
6394 (match_operand 2 "")))
6395 (use (match_operand 3 ""))])] ;; next_arg_reg
6398 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
6399 operands[2], operands[3], false);
6403 (define_insn "sibcall_value_internal"
6404 [(set (match_operand 0 "register_operand" "")
6405 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6406 (match_operand 2 "" "")))]
6407 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6409 if (TARGET_MICROMIPS)
6410 return MICROMIPS_J ("j", operands, 1);
6412 return MIPS_CALL ("j", operands, 1, 2);
6414 [(set_attr "jal" "indirect,direct")
6415 (set_attr "jal_macro" "no")])
6417 (define_insn "sibcall_value_multiple_internal"
6418 [(set (match_operand 0 "register_operand" "")
6419 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6420 (match_operand 2 "" "")))
6421 (set (match_operand 3 "register_operand" "")
6422 (call (mem:SI (match_dup 1))
6424 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6426 if (TARGET_MICROMIPS)
6427 return MICROMIPS_J ("j", operands, 1);
6429 return MIPS_CALL ("j", operands, 1, 2);
6431 [(set_attr "jal" "indirect,direct")
6432 (set_attr "jal_macro" "no")])
6434 (define_expand "call"
6435 [(parallel [(call (match_operand 0 "")
6436 (match_operand 1 ""))
6437 (use (match_operand 2 "")) ;; next_arg_reg
6438 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6441 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6442 operands[1], operands[2], false);
6446 ;; This instruction directly corresponds to an assembly-language "jal".
6447 ;; There are four cases:
6450 ;; Both symbolic and register destinations are OK. The pattern
6451 ;; always expands to a single mips instruction.
6453 ;; - -mabicalls/-mno-explicit-relocs:
6454 ;; Again, both symbolic and register destinations are OK.
6455 ;; The call is treated as a multi-instruction black box.
6457 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6458 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6461 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6462 ;; Only "jal $25" is allowed. The call is actually two instructions:
6463 ;; "jalr $25" followed by an insn to reload $gp.
6465 ;; In the last case, we can generate the individual instructions with
6466 ;; a define_split. There are several things to be wary of:
6468 ;; - We can't expose the load of $gp before reload. If we did,
6469 ;; it might get removed as dead, but reload can introduce new
6470 ;; uses of $gp by rematerializing constants.
6472 ;; - We shouldn't restore $gp after calls that never return.
6473 ;; It isn't valid to insert instructions between a noreturn
6474 ;; call and the following barrier.
6476 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6477 ;; instruction preserves $gp and so have no effect on its liveness.
6478 ;; But once we generate the separate insns, it becomes obvious that
6479 ;; $gp is not live on entry to the call.
6481 (define_insn_and_split "call_internal"
6482 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6483 (match_operand 1 "" ""))
6484 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6486 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6487 "reload_completed && TARGET_SPLIT_CALLS"
6490 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6493 [(set_attr "jal" "indirect,direct")])
6495 (define_insn "call_split"
6496 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6497 (match_operand 1 "" ""))
6498 (clobber (reg:SI RETURN_ADDR_REGNUM))
6499 (clobber (reg:SI 28))]
6500 "TARGET_SPLIT_CALLS"
6501 { return MIPS_CALL ("jal", operands, 0, 1); }
6502 [(set_attr "jal" "indirect,direct")
6503 (set_attr "jal_macro" "no")])
6505 ;; A pattern for calls that must be made directly. It is used for
6506 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6507 ;; stub; the linker relies on the call relocation type to detect when
6508 ;; such redirection is needed.
6509 (define_insn_and_split "call_internal_direct"
6510 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6513 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6515 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6516 "reload_completed && TARGET_SPLIT_CALLS"
6519 mips_split_call (curr_insn,
6520 gen_call_direct_split (operands[0], operands[1]));
6523 [(set_attr "jal" "direct")])
6525 (define_insn "call_direct_split"
6526 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6529 (clobber (reg:SI RETURN_ADDR_REGNUM))
6530 (clobber (reg:SI 28))]
6531 "TARGET_SPLIT_CALLS"
6532 { return MIPS_CALL ("jal", operands, 0, -1); }
6533 [(set_attr "jal" "direct")
6534 (set_attr "jal_macro" "no")])
6536 (define_expand "call_value"
6537 [(parallel [(set (match_operand 0 "")
6538 (call (match_operand 1 "")
6539 (match_operand 2 "")))
6540 (use (match_operand 3 ""))])] ;; next_arg_reg
6543 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6544 operands[2], operands[3], false);
6548 ;; See comment for call_internal.
6549 (define_insn_and_split "call_value_internal"
6550 [(set (match_operand 0 "register_operand" "")
6551 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6552 (match_operand 2 "" "")))
6553 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6555 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6556 "reload_completed && TARGET_SPLIT_CALLS"
6559 mips_split_call (curr_insn,
6560 gen_call_value_split (operands[0], operands[1],
6564 [(set_attr "jal" "indirect,direct")])
6566 (define_insn "call_value_split"
6567 [(set (match_operand 0 "register_operand" "")
6568 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6569 (match_operand 2 "" "")))
6570 (clobber (reg:SI RETURN_ADDR_REGNUM))
6571 (clobber (reg:SI 28))]
6572 "TARGET_SPLIT_CALLS"
6573 { return MIPS_CALL ("jal", operands, 1, 2); }
6574 [(set_attr "jal" "indirect,direct")
6575 (set_attr "jal_macro" "no")])
6577 ;; See call_internal_direct.
6578 (define_insn_and_split "call_value_internal_direct"
6579 [(set (match_operand 0 "register_operand")
6580 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6583 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6585 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6586 "reload_completed && TARGET_SPLIT_CALLS"
6589 mips_split_call (curr_insn,
6590 gen_call_value_direct_split (operands[0], operands[1],
6594 [(set_attr "jal" "direct")])
6596 (define_insn "call_value_direct_split"
6597 [(set (match_operand 0 "register_operand")
6598 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6601 (clobber (reg:SI RETURN_ADDR_REGNUM))
6602 (clobber (reg:SI 28))]
6603 "TARGET_SPLIT_CALLS"
6604 { return MIPS_CALL ("jal", operands, 1, -1); }
6605 [(set_attr "jal" "direct")
6606 (set_attr "jal_macro" "no")])
6608 ;; See comment for call_internal.
6609 (define_insn_and_split "call_value_multiple_internal"
6610 [(set (match_operand 0 "register_operand" "")
6611 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6612 (match_operand 2 "" "")))
6613 (set (match_operand 3 "register_operand" "")
6614 (call (mem:SI (match_dup 1))
6616 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6618 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6619 "reload_completed && TARGET_SPLIT_CALLS"
6622 mips_split_call (curr_insn,
6623 gen_call_value_multiple_split (operands[0], operands[1],
6624 operands[2], operands[3]));
6627 [(set_attr "jal" "indirect,direct")])
6629 (define_insn "call_value_multiple_split"
6630 [(set (match_operand 0 "register_operand" "")
6631 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6632 (match_operand 2 "" "")))
6633 (set (match_operand 3 "register_operand" "")
6634 (call (mem:SI (match_dup 1))
6636 (clobber (reg:SI RETURN_ADDR_REGNUM))
6637 (clobber (reg:SI 28))]
6638 "TARGET_SPLIT_CALLS"
6639 { return MIPS_CALL ("jal", operands, 1, 2); }
6640 [(set_attr "jal" "indirect,direct")
6641 (set_attr "jal_macro" "no")])
6643 ;; Call subroutine returning any type.
6645 (define_expand "untyped_call"
6646 [(parallel [(call (match_operand 0 "")
6648 (match_operand 1 "")
6649 (match_operand 2 "")])]
6654 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6656 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6658 rtx set = XVECEXP (operands[2], 0, i);
6659 mips_emit_move (SET_DEST (set), SET_SRC (set));
6662 emit_insn (gen_blockage ());
6667 ;; ....................
6671 ;; ....................
6675 (define_insn "prefetch"
6676 [(prefetch (match_operand:QI 0 "address_operand" "ZD")
6677 (match_operand 1 "const_int_operand" "n")
6678 (match_operand 2 "const_int_operand" "n"))]
6679 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6681 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
6682 /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching. */
6683 return "ld\t$0,%a0";
6684 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6685 return "pref\t%1,%a0";
6687 [(set_attr "type" "prefetch")])
6689 (define_insn "*prefetch_indexed_<mode>"
6690 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6691 (match_operand:P 1 "register_operand" "d"))
6692 (match_operand 2 "const_int_operand" "n")
6693 (match_operand 3 "const_int_operand" "n"))]
6694 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6696 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6697 return "prefx\t%2,%1(%0)";
6699 [(set_attr "type" "prefetchx")])
6705 [(set_attr "type" "nop")
6706 (set_attr "mode" "none")])
6708 ;; Like nop, but commented out when outside a .set noreorder block.
6709 (define_insn "hazard_nop"
6713 if (mips_noreorder.nesting_level > 0)
6718 [(set_attr "type" "nop")])
6720 ;; MIPS4 Conditional move instructions.
6722 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6723 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6725 (match_operator:MOVECC 4 "equality_operator"
6726 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6728 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6729 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6734 [(set_attr "type" "condmove")
6735 (set_attr "mode" "<GPR:MODE>")])
6737 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6738 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6739 (if_then_else:SCALARF
6740 (match_operator:MOVECC 4 "equality_operator"
6741 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6743 (match_operand:SCALARF 2 "register_operand" "f,0")
6744 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6745 "ISA_HAS_FP_CONDMOVE"
6747 mov%T4.<fmt>\t%0,%2,%1
6748 mov%t4.<fmt>\t%0,%3,%1"
6749 [(set_attr "type" "condmove")
6750 (set_attr "mode" "<SCALARF:MODE>")])
6752 ;; These are the main define_expand's used to make conditional moves.
6754 (define_expand "mov<mode>cc"
6755 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6756 (set (match_operand:GPR 0 "register_operand")
6757 (if_then_else:GPR (match_dup 5)
6758 (match_operand:GPR 2 "reg_or_0_operand")
6759 (match_operand:GPR 3 "reg_or_0_operand")))]
6762 mips_expand_conditional_move (operands);
6766 (define_expand "mov<mode>cc"
6767 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6768 (set (match_operand:SCALARF 0 "register_operand")
6769 (if_then_else:SCALARF (match_dup 5)
6770 (match_operand:SCALARF 2 "register_operand")
6771 (match_operand:SCALARF 3 "register_operand")))]
6772 "ISA_HAS_FP_CONDMOVE"
6774 mips_expand_conditional_move (operands);
6779 ;; ....................
6781 ;; mips16 inline constant tables
6783 ;; ....................
6786 (define_insn "consttable_tls_reloc"
6787 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "")
6788 (match_operand 1 "const_int_operand" "")]
6789 UNSPEC_CONSTTABLE_INT)]
6790 "TARGET_MIPS16_PCREL_LOADS"
6791 { return mips_output_tls_reloc_directive (&operands[0]); }
6792 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6794 (define_insn "consttable_int"
6795 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6796 (match_operand 1 "const_int_operand" "")]
6797 UNSPEC_CONSTTABLE_INT)]
6800 assemble_integer (mips_strip_unspec_address (operands[0]),
6801 INTVAL (operands[1]),
6802 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6805 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6807 (define_insn "consttable_float"
6808 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6809 UNSPEC_CONSTTABLE_FLOAT)]
6814 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6815 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6816 assemble_real (d, GET_MODE (operands[0]),
6817 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6820 [(set (attr "length")
6821 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6823 (define_insn "align"
6824 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6827 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6830 [(match_operand 0 "small_data_pattern")]
6833 { operands[0] = mips_rewrite_small_data (operands[0]); })
6836 ;; ....................
6838 ;; MIPS16e Save/Restore
6840 ;; ....................
6843 (define_insn "*mips16e_save_restore"
6844 [(match_parallel 0 ""
6845 [(set (match_operand:SI 1 "register_operand")
6846 (plus:SI (match_dup 1)
6847 (match_operand:SI 2 "const_int_operand")))])]
6848 "operands[1] == stack_pointer_rtx
6849 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6850 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6851 [(set_attr "type" "arith")
6852 (set_attr "extended_mips16" "yes")])
6854 ;; Thread-Local Storage
6856 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6857 ;; MIPS architecture defines this register, and no current
6858 ;; implementation provides it; instead, any OS which supports TLS is
6859 ;; expected to trap and emulate this instruction. rdhwr is part of the
6860 ;; MIPS 32r2 specification, but we use it on any architecture because
6861 ;; we expect it to be emulated. Use .set to force the assembler to
6864 ;; We do not use a constraint to force the destination to be $3
6865 ;; because $3 can appear explicitly as a function return value.
6866 ;; If we leave the use of $3 implicit in the constraints until
6867 ;; reload, we may end up making a $3 return value live across
6868 ;; the instruction, leading to a spill failure when reloading it.
6869 (define_insn_and_split "tls_get_tp_<mode>"
6870 [(set (match_operand:P 0 "register_operand" "=d")
6871 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6872 (clobber (reg:P TLS_GET_TP_REGNUM))]
6873 "HAVE_AS_TLS && !TARGET_MIPS16"
6875 "&& reload_completed"
6876 [(set (reg:P TLS_GET_TP_REGNUM)
6877 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6878 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6880 [(set_attr "type" "unknown")
6881 ; Since rdhwr always generates a trap for now, putting it in a delay
6882 ; slot would make the kernel's emulation of it much slower.
6883 (set_attr "can_delay" "no")
6884 (set_attr "mode" "<MODE>")
6885 (set_attr "length" "8")])
6887 (define_insn "*tls_get_tp_<mode>_split"
6888 [(set (reg:P TLS_GET_TP_REGNUM)
6889 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6890 "HAVE_AS_TLS && !TARGET_MIPS16"
6891 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6892 [(set_attr "type" "unknown")
6893 ; See tls_get_tp_<mode>
6894 (set_attr "can_delay" "no")
6895 (set_attr "mode" "<MODE>")])
6897 ;; In MIPS16 mode, the TLS base pointer is accessed by a
6898 ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not
6899 ;; accessible in MIPS16.
6901 ;; This is not represented as a call insn, to avoid the
6902 ;; unnecesarry clobbering of caller-save registers by a
6903 ;; function consisting only of: "rdhwr $3,$29; j $31; nop;"
6905 ;; A $25 clobber is added to cater for a $25 load stub added by the
6906 ;; linker to __mips16_rdhwr when the call is made from non-PIC code.
6908 (define_insn_and_split "tls_get_tp_mips16_<mode>"
6909 [(set (match_operand:P 0 "register_operand" "=d")
6910 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")]
6912 (clobber (reg:P TLS_GET_TP_REGNUM))
6913 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6914 (clobber (reg:P RETURN_ADDR_REGNUM))]
6915 "HAVE_AS_TLS && TARGET_MIPS16"
6917 "&& reload_completed"
6918 [(parallel [(set (reg:P TLS_GET_TP_REGNUM)
6919 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP))
6920 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6921 (clobber (reg:P RETURN_ADDR_REGNUM))])
6922 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6924 [(set_attr "type" "multi")
6925 (set_attr "length" "8")
6926 (set_attr "mode" "<MODE>")])
6928 (define_insn "*tls_get_tp_mips16_call_<mode>"
6929 [(set (reg:P TLS_GET_TP_REGNUM)
6930 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")]
6932 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6933 (clobber (reg:P RETURN_ADDR_REGNUM))]
6934 "HAVE_AS_TLS && TARGET_MIPS16"
6935 { return MIPS_CALL ("jal", operands, 0, -1); }
6936 [(set_attr "type" "call")
6937 (set_attr "length" "6")
6938 (set_attr "mode" "<MODE>")])
6940 ;; Named pattern for expanding thread pointer reference.
6941 (define_expand "get_thread_pointer<mode>"
6942 [(match_operand:P 0 "register_operand" "=d")]
6945 mips_expand_thread_pointer (operands[0]);
6950 ;; Synchronization instructions.
6954 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6956 (include "mips-ps-3d.md")
6958 ; The MIPS DSP Instructions.
6960 (include "mips-dsp.md")
6962 ; The MIPS DSP REV 2 Instructions.
6964 (include "mips-dspr2.md")
6966 ; MIPS fixed-point instructions.
6967 (include "mips-fixed.md")
6969 ; microMIPS patterns.
6970 (include "micromips.md")
6972 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6973 (include "loongson.md")
6975 (define_c_enum "unspec" [
6976 UNSPEC_ADDRESS_FIRST