1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989-2016 Free Software Foundation, Inc.
3 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
4 ;; Changes by Michael Meissner, meissner@osf.org
5 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 ;; Brendan Eich, brendan@microunity.com.
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 (define_enum "processor" [
74 (define_c_enum "unspec" [
75 ;; Unaligned accesses.
81 ;; Integer operations that are too cumbersome to describe directly.
86 ;; Floating-point moves.
93 ;; Floating-point environment.
106 UNSPEC_POTENTIAL_CPRESTORE
111 UNSPEC_SET_GOT_VERSION
112 UNSPEC_UPDATE_GOT_VERSION
114 ;; Symbolic accesses.
119 UNSPEC_UNSHIFTED_HIGH
121 ;; MIPS16 constant pools.
123 UNSPEC_CONSTTABLE_INT
124 UNSPEC_CONSTTABLE_FLOAT
126 ;; Blockage and synchronisation.
133 ;; Cache manipulation.
135 UNSPEC_R10K_CACHE_BARRIER
137 ;; Interrupt handling.
145 ;; Used in a call expression in place of args_size. It's present for PIC
146 ;; indirect calls where it contains args_size and the function symbol.
149 ;; MIPS16 casesi jump table dispatch.
150 UNSPEC_CASESI_DISPATCH
153 UNSPEC_PROBE_STACK_RANGE
157 [(TLS_GET_TP_REGNUM 3)
161 (PIC_FUNCTION_ADDR_REGNUM 25)
162 (RETURN_ADDR_REGNUM 31)
163 (CPRESTORE_SLOT_REGNUM 76)
164 (GOT_VERSION_REGNUM 79)
166 ;; PIC long branch sequences are never longer than 100 bytes.
167 (MAX_PIC_BRANCH_LENGTH 100)
171 (include "predicates.md")
172 (include "constraints.md")
174 ;; ....................
178 ;; ....................
180 (define_attr "got" "unset,xgot_high,load"
181 (const_string "unset"))
183 ;; For jal instructions, this attribute is DIRECT when the target address
184 ;; is symbolic and INDIRECT when it is a register.
185 (define_attr "jal" "unset,direct,indirect"
186 (const_string "unset"))
188 ;; This attribute is YES if the instruction is a jal macro (not a
189 ;; real jal instruction).
191 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
192 ;; an instruction to restore $gp. Direct jals are also macros for
193 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
195 (define_attr "jal_macro" "no,yes"
196 (cond [(eq_attr "jal" "direct")
197 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
198 ? JAL_MACRO_YES : JAL_MACRO_NO)")
199 (eq_attr "jal" "indirect")
200 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
201 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
202 (const_string "no")))
204 ;; Classification of moves, extensions and truncations. Most values
205 ;; are as for "type" (see below) but there are also the following
206 ;; move-specific values:
208 ;; constN move an N-constraint integer into a MIPS16 register
209 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
210 ;; to produce a sign-extended DEST, even if SRC is not
211 ;; properly sign-extended
212 ;; ext_ins EXT, DEXT, INS or DINS instruction
213 ;; andi a single ANDI instruction
214 ;; loadpool move a constant into a MIPS16 register by loading it
216 ;; shift_shift a shift left followed by a shift right
218 ;; This attribute is used to determine the instruction's length and
219 ;; scheduling type. For doubleword moves, the attribute always describes
220 ;; the split instructions; in some cases, it is more appropriate for the
221 ;; scheduling type to be "multi" instead.
222 (define_attr "move_type"
223 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove,
224 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
226 (const_string "unknown"))
228 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor,simd_add"
229 (const_string "unknown"))
231 ;; Main data type used by the insn
232 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW,
233 V2DI,V4SI,V8HI,V16QI,V2DF,V4SF"
234 (const_string "unknown"))
236 ;; True if the main data type is twice the size of a word.
237 (define_attr "dword_mode" "no,yes"
238 (cond [(and (eq_attr "mode" "DI,DF")
239 (not (match_test "TARGET_64BIT")))
242 (and (eq_attr "mode" "TI,TF")
243 (match_test "TARGET_64BIT"))
244 (const_string "yes")]
245 (const_string "no")))
247 ;; True if the main data type is four times of the size of a word.
248 (define_attr "qword_mode" "no,yes"
249 (cond [(and (eq_attr "mode" "TI,TF")
250 (not (match_test "TARGET_64BIT")))
251 (const_string "yes")]
252 (const_string "no")))
254 ;; Attributes describing a sync loop. These loops have the form:
256 ;; if (RELEASE_BARRIER == YES) sync
258 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
259 ;; CMP = 0 [delay slot]
260 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
261 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
262 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
263 ;; $AT |= $TMP1 | $TMP3
264 ;; if (!commit (*MEM = $AT)) goto 1.
265 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
267 ;; if (ACQUIRE_BARRIER == YES) sync
270 ;; where "$" values are temporaries and where the other values are
271 ;; specified by the attributes below. Values are specified as operand
272 ;; numbers and insns are specified as enums. If no operand number is
273 ;; specified, the following values are used instead:
278 ;; - INCLUSIVE_MASK: -1
279 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
280 ;; - EXCLUSIVE_MASK: 0
282 ;; MEM and INSN1_OP2 are required.
284 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
285 ;; but the gen* programs don't yet support that.
286 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
287 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
288 (define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
289 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
290 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
291 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
292 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
293 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
294 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
295 (const_string "move"))
296 (define_attr "sync_insn2" "nop,and,xor,not"
297 (const_string "nop"))
298 ;; Memory model specifier.
299 ;; "0"-"9" values specify the operand that stores the memory model value.
300 ;; "10" specifies MEMMODEL_ACQ_REL,
301 ;; "11" specifies MEMMODEL_ACQUIRE.
302 (define_attr "sync_memmodel" "" (const_int 10))
304 ;; Accumulator operand for madd patterns.
305 (define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
307 ;; Classification of each insn.
308 ;; branch conditional branch
309 ;; jump unconditional jump
310 ;; call unconditional call
311 ;; load load instruction(s)
312 ;; fpload floating point load
313 ;; fpidxload floating point indexed load
314 ;; store store instruction(s)
315 ;; fpstore floating point store
316 ;; fpidxstore floating point indexed store
317 ;; prefetch memory prefetch (register + offset)
318 ;; prefetchx memory indexed prefetch (register + register)
319 ;; condmove conditional moves
320 ;; mtc transfer to coprocessor
321 ;; mfc transfer from coprocessor
322 ;; mthi transfer to a hi register
323 ;; mtlo transfer to a lo register
324 ;; mfhi transfer from a hi register
325 ;; mflo transfer from a lo register
326 ;; const load constant
327 ;; arith integer arithmetic instructions
328 ;; logical integer logical instructions
329 ;; shift integer shift instructions
330 ;; slt set less than instructions
331 ;; signext sign extend instructions
332 ;; clz the clz and clo instructions
333 ;; pop the pop instruction
334 ;; trap trap if instructions
335 ;; imul integer multiply 2 operands
336 ;; imul3 integer multiply 3 operands
337 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
338 ;; imadd integer multiply-add
339 ;; idiv integer divide 2 operands
340 ;; idiv3 integer divide 3 operands
341 ;; move integer register move ({,D}ADD{,U} with rt = 0)
342 ;; fmove floating point register move
343 ;; fadd floating point add/subtract
344 ;; fmul floating point multiply
345 ;; fmadd floating point multiply-add
346 ;; fdiv floating point divide
347 ;; frdiv floating point reciprocal divide
348 ;; frdiv1 floating point reciprocal divide step 1
349 ;; frdiv2 floating point reciprocal divide step 2
350 ;; fabs floating point absolute value
351 ;; fneg floating point negation
352 ;; fcmp floating point compare
353 ;; fcvt floating point convert
354 ;; fsqrt floating point square root
355 ;; frsqrt floating point reciprocal square root
356 ;; frsqrt1 floating point reciprocal square root step1
357 ;; frsqrt2 floating point reciprocal square root step2
358 ;; dspmac DSP MAC instructions not saturating the accumulator
359 ;; dspmacsat DSP MAC instructions that saturate the accumulator
360 ;; accext DSP accumulator extract instructions
361 ;; accmod DSP accumulator modify instructions
362 ;; dspalu DSP ALU instructions not saturating the result
363 ;; dspalusat DSP ALU instructions that saturate the result
364 ;; multi multiword sequence (or user asm statements)
365 ;; atomic atomic memory update instruction
366 ;; syncloop memory atomic operation implemented as a sync loop
368 ;; ghost an instruction that produces no real code
369 ;; multimem microMIPS multiword load and store
371 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
372 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
373 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
374 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
375 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
376 multi,atomic,syncloop,nop,ghost,multimem,
377 simd_div,simd_fclass,simd_flog2,simd_fadd,simd_fcvt,simd_fmul,simd_fmadd,
378 simd_fdiv,simd_bitins,simd_bitmov,simd_insert,simd_sld,simd_mul,simd_fcmp,
379 simd_fexp2,simd_int_arith,simd_bit,simd_shift,simd_splat,simd_fill,
380 simd_permute,simd_shf,simd_sat,simd_pcnt,simd_copy,simd_branch,simd_cmsa,
381 simd_fminmax,simd_logic,simd_move,simd_load,simd_store"
382 (cond [(eq_attr "jal" "!unset") (const_string "call")
383 (eq_attr "got" "load") (const_string "load")
385 (eq_attr "alu_type" "add,sub") (const_string "arith")
387 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
389 ;; If a doubleword move uses these expensive instructions,
390 ;; it is usually better to schedule them in the same way
391 ;; as the singleword form, rather than as "multi".
392 (eq_attr "move_type" "load") (const_string "load")
393 (eq_attr "move_type" "fpload") (const_string "fpload")
394 (eq_attr "move_type" "store") (const_string "store")
395 (eq_attr "move_type" "fpstore") (const_string "fpstore")
396 (eq_attr "move_type" "mtc") (const_string "mtc")
397 (eq_attr "move_type" "mfc") (const_string "mfc")
398 (eq_attr "move_type" "mtlo") (const_string "mtlo")
399 (eq_attr "move_type" "mflo") (const_string "mflo")
401 ;; These types of move are always single insns.
402 (eq_attr "move_type" "imul") (const_string "imul")
403 (eq_attr "move_type" "fmove") (const_string "fmove")
404 (eq_attr "move_type" "loadpool") (const_string "load")
405 (eq_attr "move_type" "signext") (const_string "signext")
406 (eq_attr "move_type" "ext_ins") (const_string "arith")
407 (eq_attr "move_type" "arith") (const_string "arith")
408 (eq_attr "move_type" "logical") (const_string "logical")
409 (eq_attr "move_type" "sll0") (const_string "shift")
410 (eq_attr "move_type" "andi") (const_string "logical")
412 ;; These types of move are always split.
413 (eq_attr "move_type" "constN,shift_shift")
414 (const_string "multi")
416 ;; These types of move are split for quadword modes only.
417 (and (eq_attr "move_type" "move,const")
418 (eq_attr "qword_mode" "yes"))
419 (const_string "multi")
421 ;; These types of move are split for doubleword modes only.
422 (and (eq_attr "move_type" "move,const")
423 (eq_attr "dword_mode" "yes"))
424 (const_string "multi")
425 (eq_attr "move_type" "move") (const_string "move")
426 (eq_attr "move_type" "const") (const_string "const")
427 (eq_attr "sync_mem" "!none") (const_string "syncloop")]
428 (const_string "unknown")))
430 (define_attr "compact_form" "always,maybe,never"
431 (cond [(eq_attr "jal" "direct")
432 (const_string "always")
433 (eq_attr "jal" "indirect")
434 (const_string "maybe")
435 (eq_attr "type" "jump")
436 (const_string "maybe")]
437 (const_string "never")))
439 ;; Mode for conversion types (fcvt)
440 ;; I2S integer to float single (SI/DI to SF)
441 ;; I2D integer to float double (SI/DI to DF)
442 ;; S2I float to integer (SF to SI/DI)
443 ;; D2I float to integer (DF to SI/DI)
444 ;; D2S double to float single
445 ;; S2D float single to double
447 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
448 (const_string "unknown"))
450 ;; Is this an extended instruction in mips16 mode?
451 (define_attr "extended_mips16" "no,yes"
452 (if_then_else (ior ;; In general, constant-pool loads are extended
453 ;; instructions. We don't yet optimize for 16-bit
454 ;; PC-relative references.
455 (eq_attr "move_type" "sll0,loadpool")
456 (eq_attr "jal" "direct")
457 (eq_attr "got" "load"))
459 (const_string "no")))
461 (define_attr "compression" "none,all,micromips32,micromips"
462 (const_string "none"))
464 (define_attr "enabled" "no,yes"
465 (cond [;; The o32 FPXX and FP64A ABI extensions prohibit direct moves between
466 ;; GR_REG and FR_REG for 64-bit values.
467 (and (eq_attr "move_type" "mtc,mfc")
468 (match_test "(TARGET_FLOATXX && !ISA_HAS_MXHC1)
469 || TARGET_O32_FP64A_ABI")
470 (eq_attr "dword_mode" "yes"))
472 (and (eq_attr "compression" "micromips32,micromips")
473 (match_test "!TARGET_MICROMIPS"))
475 (const_string "yes")))
477 ;; The number of individual instructions that a non-branch pattern generates,
478 ;; using units of BASE_INSN_LENGTH.
479 (define_attr "insn_count" ""
480 (cond [;; "Ghost" instructions occupy no space.
481 (eq_attr "type" "ghost")
484 ;; Extended instructions count as 2.
485 (and (eq_attr "extended_mips16" "yes")
486 (match_test "TARGET_MIPS16"))
489 ;; A GOT load followed by an add of $gp. This is not used for MIPS16.
490 (eq_attr "got" "xgot_high")
493 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
494 ;; They are extended instructions on MIPS16 targets.
495 (eq_attr "move_type" "shift_shift")
496 (if_then_else (match_test "TARGET_MIPS16")
500 ;; Check for doubleword moves that are decomposed into two
501 ;; instructions. The individual instructions are unextended
503 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
504 (eq_attr "dword_mode" "yes"))
507 ;; Check for quadword moves that are decomposed into four
509 (and (eq_attr "move_type" "mtc,mfc,move")
510 (eq_attr "qword_mode" "yes"))
513 ;; Constants, loads and stores are handled by external routines.
514 (and (eq_attr "move_type" "const,constN")
515 (eq_attr "dword_mode" "yes"))
516 (symbol_ref "mips_split_const_insns (operands[1])")
517 (eq_attr "move_type" "const,constN")
518 (symbol_ref "mips_const_insns (operands[1])")
519 (eq_attr "move_type" "load,fpload")
520 (symbol_ref "mips_load_store_insns (operands[1], insn)")
521 (eq_attr "move_type" "store,fpstore")
522 (symbol_ref "mips_load_store_insns (operands[0], insn)
523 + (TARGET_FIX_24K ? 1 : 0)")
525 ;; In the worst case, a call macro will take 8 instructions:
527 ;; lui $25,%call_hi(FOO)
529 ;; lw $25,%call_lo(FOO)($25)
535 (eq_attr "jal_macro" "yes")
538 ;; Various VR4120 errata require a nop to be inserted after a macc
539 ;; instruction. The assembler does this for us, so account for
540 ;; the worst-case length here.
541 (and (eq_attr "type" "imadd")
542 (match_test "TARGET_FIX_VR4120"))
545 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
546 ;; the result of the second one is missed. The assembler should work
547 ;; around this by inserting a nop after the first dmult.
548 (and (eq_attr "type" "imul,imul3")
549 (eq_attr "mode" "DI")
550 (match_test "TARGET_FIX_VR4120"))
553 (eq_attr "type" "idiv,idiv3")
554 (symbol_ref "mips_idiv_insns (GET_MODE (PATTERN (insn)))")
556 (not (eq_attr "sync_mem" "none"))
557 (symbol_ref "mips_sync_loop_insns (insn, operands)")]
560 ;; Length of instruction in bytes. The default is derived from "insn_count",
561 ;; but there are special cases for branches (which must be handled here)
562 ;; and for compressed single instructions.
563 (define_attr "length" ""
564 (cond [(and (ior (eq_attr "compression" "micromips,all")
565 (and (eq_attr "compression" "micromips32")
566 (eq_attr "mode" "SI,SF")))
567 (eq_attr "dword_mode" "no")
568 (match_test "TARGET_MICROMIPS"))
571 ;; Direct microMIPS branch instructions have a range of
572 ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc].
573 ;; If a branch is outside this range, we have a choice of two
576 ;; For PIC, an out-of-range branch like:
581 ;; becomes the equivalent of:
590 ;; The non-PIC case is similar except that we use a direct
591 ;; jump instead of an la/jr pair. Since the target of this
592 ;; jump is an absolute 28-bit bit address (the other bits
593 ;; coming from the address of the delay slot) this form cannot
594 ;; cross a 256MB boundary. We could provide the option of
595 ;; using la/jr in this case too, but we do not do so at
598 ;; The value we specify here does not account for the delay slot
599 ;; instruction, whose length is added separately. If the RTL
600 ;; pattern has no explicit delay slot, mips_adjust_insn_length
601 ;; will add the length of the implicit nop. The range of
602 ;; [-0x20000, 0x1fffc] from the address of the delay slot
603 ;; therefore translates to a range of:
605 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
606 ;; == [-0x1fffc, 0x1fff8]
608 ;; from the shorten_branches reference address.
609 (and (eq_attr "type" "branch")
610 (not (match_test "TARGET_MIPS16")))
611 (cond [;; Any variant can handle the 17-bit range.
612 (and (le (minus (match_dup 0) (pc)) (const_int 65532))
613 (le (minus (pc) (match_dup 0)) (const_int 65534)))
616 ;; The 18-bit range is OK other than for microMIPS.
617 (and (not (match_test "TARGET_MICROMIPS"))
618 (and (le (minus (match_dup 0) (pc)) (const_int 131064))
619 (le (minus (pc) (match_dup 0)) (const_int 131068))))
622 ;; The non-PIC case: branch, first delay slot, and J.
623 (match_test "TARGET_ABSOLUTE_JUMPS")
626 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
627 ;; mips_adjust_insn_length substitutes the correct length.
629 ;; Note that we can't simply use (symbol_ref ...) here
630 ;; because genattrtab needs to know the maximum length
632 (const_int MAX_PIC_BRANCH_LENGTH))
634 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
635 ;; from the address of the following instruction, which leads
638 ;; [-(0x100 - sizeof (branch)), 0xfe]
641 ;; from the shorten_branches reference address. Extended branches
642 ;; likewise have a range of [-0x10000, 0xfffe] from the address
643 ;; of the following instruction, which leads to a range of:
645 ;; [-(0x10000 - sizeof (branch)), 0xfffe]
646 ;; == [-0xfffc, 0xfffe]
648 ;; from the reference address.
650 ;; When a branch is out of range, mips_reorg splits it into a form
651 ;; that uses in-range branches. There are four basic sequences:
653 ;; (1) Absolute addressing with a readable text segment
654 ;; (32-bit addresses):
657 ;; move $1,$2 2 bytes
658 ;; lw $2,label 2 bytes
660 ;; move $2,$1 2 bytes
661 ;; .align 2 0 or 2 bytes
663 ;; .word target 4 bytes
665 ;; (16 bytes in the worst case)
667 ;; (2) Absolute addressing with a readable text segment
668 ;; (64-bit addresses):
671 ;; move $1,$2 2 bytes
672 ;; ld $2,label 2 bytes
674 ;; move $2,$1 2 bytes
675 ;; .align 3 0 to 6 bytes
677 ;; .dword target 8 bytes
679 ;; (24 bytes in the worst case)
681 ;; (3) Absolute addressing without a readable text segment
682 ;; (which requires 32-bit addresses at present):
685 ;; move $1,$2 2 bytes
686 ;; lui $2,%hi(target) 4 bytes
689 ;; addiu $2,%lo(target) 4 bytes
691 ;; move $2,$1 2 bytes
695 ;; (4) PIC addressing (which requires 32-bit addresses at present):
698 ;; move $1,$2 2 bytes
699 ;; lw $2,cprestore 0, 2 or 4 bytes
700 ;; lw $2,%got(target)($2) 4 bytes
701 ;; addiu $2,%lo(target) 4 bytes
703 ;; move $2,$1 2 bytes
705 ;; (20 bytes in the worst case)
706 (and (eq_attr "type" "branch")
707 (match_test "TARGET_MIPS16"))
708 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
709 (le (minus (pc) (match_dup 0)) (const_int 254)))
711 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
712 (le (minus (pc) (match_dup 0)) (const_int 65532)))
714 (and (match_test "TARGET_ABICALLS")
715 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
717 (match_test "Pmode == SImode")
720 (symbol_ref "get_attr_insn_count (insn) * BASE_INSN_LENGTH")))
722 ;; Attribute describing the processor.
723 (define_enum_attr "cpu" "processor"
724 (const (symbol_ref "mips_tune")))
726 ;; The type of hardware hazard associated with this instruction.
727 ;; DELAY means that the next instruction cannot read the result
728 ;; of this one. HILO means that the next two instructions cannot
729 ;; write to HI or LO.
730 (define_attr "hazard" "none,delay,hilo,forbidden_slot"
731 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
732 (match_test "ISA_HAS_LOAD_DELAY"))
733 (const_string "delay")
735 (and (eq_attr "type" "mfc,mtc")
736 (match_test "ISA_HAS_XFER_DELAY"))
737 (const_string "delay")
739 (and (eq_attr "type" "fcmp")
740 (match_test "ISA_HAS_FCMP_DELAY"))
741 (const_string "delay")
743 ;; The r4000 multiplication patterns include an mflo instruction.
744 (and (eq_attr "type" "imul")
745 (match_test "TARGET_FIX_R4000"))
746 (const_string "hilo")
748 (and (eq_attr "type" "mfhi,mflo")
749 (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
750 (const_string "hilo")]
751 (const_string "none")))
753 ;; Can the instruction be put into a delay slot?
754 (define_attr "can_delay" "no,yes"
755 (if_then_else (and (eq_attr "type" "!branch,call,jump")
756 (eq_attr "hazard" "none")
757 (match_test "get_attr_insn_count (insn) == 1"))
759 (const_string "no")))
761 ;; Attribute defining whether or not we can use the branch-likely
763 (define_attr "branch_likely" "no,yes"
764 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
766 (const_string "no")))
768 ;; True if an instruction might assign to hi or lo when reloaded.
769 ;; This is used by the TUNE_MACC_CHAINS code.
770 (define_attr "may_clobber_hilo" "no,yes"
771 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
773 (const_string "no")))
775 ;; Describe a user's asm statement.
776 (define_asm_attributes
777 [(set_attr "type" "multi")
778 (set_attr "can_delay" "no")])
780 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
781 ;; from the same template.
782 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
784 ;; A copy of GPR that can be used when a pattern has two independent
786 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
788 (define_mode_iterator MOVEP1 [SI SF])
789 (define_mode_iterator MOVEP2 [SI SF])
790 (define_mode_iterator JOIN_MODE [HI
792 (SF "TARGET_HARD_FLOAT")
793 (DF "TARGET_HARD_FLOAT
794 && TARGET_DOUBLE_FLOAT")])
796 ;; This mode iterator allows :HILO to be used as the mode of the
797 ;; concatenated HI and LO registers.
798 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
800 ;; This mode iterator allows :P to be used for patterns that operate on
801 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
802 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
804 ;; This mode iterator allows :MOVECC to be used anywhere that a
805 ;; conditional-move-type condition is needed.
806 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
807 (CC "TARGET_HARD_FLOAT
808 && !TARGET_LOONGSON_2EF
809 && !TARGET_MIPS5900")])
811 ;; This mode iterator allows :FPCC to be used anywhere that an FP condition
813 (define_mode_iterator FPCC [(CC "!ISA_HAS_CCF")
814 (CCF "ISA_HAS_CCF")])
816 ;; 32-bit integer moves for which we provide move patterns.
817 (define_mode_iterator IMOVE32
826 (V4UQQ "TARGET_DSP")])
828 ;; 64-bit modes for which we provide move patterns.
829 (define_mode_iterator MOVE64
831 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
832 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
833 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
834 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
836 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
837 (define_mode_iterator MOVE128 [TI TF])
839 ;; This mode iterator allows the QI and HI extension patterns to be
840 ;; defined from the same template.
841 (define_mode_iterator SHORT [QI HI])
843 ;; Likewise the 64-bit truncate-and-shift patterns.
844 (define_mode_iterator SUBDI [QI HI SI])
846 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
847 ;; floating-point mode is allowed.
848 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
849 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
850 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
852 ;; Like ANYF, but only applies to scalar modes.
853 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
854 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
856 ;; A floating-point mode for which moves involving FPRs may need to be split.
857 (define_mode_iterator SPLITF
858 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
859 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
860 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
861 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
862 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
863 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
864 (TF "TARGET_64BIT && TARGET_FLOAT64")])
866 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
867 ;; 32-bit version and "dsubu" in the 64-bit version.
868 (define_mode_attr d [(SI "") (DI "d")
869 (QQ "") (HQ "") (SQ "") (DQ "d")
870 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
871 (HA "") (SA "") (DA "d")
872 (UHA "") (USA "") (UDA "d")])
874 ;; Same as d but upper-case.
875 (define_mode_attr D [(SI "") (DI "D")
876 (QQ "") (HQ "") (SQ "") (DQ "D")
877 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
878 (HA "") (SA "") (DA "D")
879 (UHA "") (USA "") (UDA "D")])
881 ;; This attribute gives the length suffix for a load or store instruction.
882 ;; The same suffixes work for zero and sign extensions.
883 (define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
884 (define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
886 ;; This attributes gives the mode mask of a SHORT.
887 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
889 ;; Mode attributes for GPR loads.
890 (define_mode_attr load [(SI "lw") (DI "ld")])
891 ;; Instruction names for stores.
892 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
894 ;; Similarly for MIPS IV indexed FPR loads and stores.
895 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
896 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
898 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
899 ;; are different. Some forms of unextended addiu have an 8-bit immediate
900 ;; field but the equivalent daddiu has only a 5-bit field.
901 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
903 ;; This attribute gives the best constraint to use for registers of
905 (define_mode_attr reg [(SI "d") (DI "d") (CC "z") (CCF "f")])
907 ;; This attribute gives the format suffix for floating-point operations.
908 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
910 ;; This attribute gives the upper-case mode name for one unit of a
911 ;; floating-point mode or vector mode.
912 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF") (V4SF "SF")
913 (V16QI "QI") (V8HI "HI") (V4SI "SI") (V2DI "DI")
916 ;; This attribute gives the integer mode that has the same size as a
918 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
919 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
920 (HA "HI") (SA "SI") (DA "DI")
921 (UHA "HI") (USA "SI") (UDA "DI")
922 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
923 (V2HQ "SI") (V2HA "SI")])
925 ;; This attribute gives the integer mode that has half the size of
926 ;; the controlling mode.
927 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
928 (V2SI "SI") (V4HI "SI") (V8QI "SI")
931 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
933 ;; In certain cases, div.s and div.ps may have a rounding error
934 ;; and/or wrong inexact flag.
936 ;; Therefore, we only allow div.s if not working around SB-1 rev2
937 ;; errata or if a slight loss of precision is OK.
938 (define_mode_attr divide_condition
939 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
940 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
942 ;; This attribute gives the conditions under which SQRT.fmt instructions
944 (define_mode_attr sqrt_condition
945 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
947 ;; This attribute provides the correct mnemonic for each FP condition mode.
948 (define_mode_attr fpcmp [(CC "c") (CCF "cmp")])
950 ;; This code iterator allows signed and unsigned widening multiplications
951 ;; to use the same template.
952 (define_code_iterator any_extend [sign_extend zero_extend])
954 ;; This code iterator allows the two right shift instructions to be
955 ;; generated from the same template.
956 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
958 ;; This code iterator allows the three shift instructions to be generated
959 ;; from the same template.
960 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
962 ;; This code iterator allows unsigned and signed division to be generated
963 ;; from the same template.
964 (define_code_iterator any_div [div udiv])
966 ;; This code iterator allows unsigned and signed modulus to be generated
967 ;; from the same template.
968 (define_code_iterator any_mod [mod umod])
970 ;; This code iterator allows addition and subtraction to be generated
971 ;; from the same template.
972 (define_code_iterator addsub [plus minus])
974 ;; This code iterator allows all native floating-point comparisons to be
975 ;; generated from the same template.
976 (define_code_iterator fcond [unordered uneq unlt unle eq lt le
977 (ordered "ISA_HAS_CCF")
981 ;; This code iterator is used for comparisons that can be implemented
982 ;; by swapping the operands.
983 (define_code_iterator swapped_fcond [ge gt unge ungt])
985 ;; Equality operators.
986 (define_code_iterator equality_op [eq ne])
988 ;; These code iterators allow the signed and unsigned scc operations to use
989 ;; the same template.
990 (define_code_iterator any_gt [gt gtu])
991 (define_code_iterator any_ge [ge geu])
992 (define_code_iterator any_lt [lt ltu])
993 (define_code_iterator any_le [le leu])
995 (define_code_iterator any_return [return simple_return])
997 ;; <u> expands to an empty string when doing a signed operation and
998 ;; "u" when doing an unsigned operation.
999 (define_code_attr u [(sign_extend "") (zero_extend "u")
1007 ;; <U> is like <u> except uppercase.
1008 (define_code_attr U [(sign_extend "") (zero_extend "U")])
1010 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
1011 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
1013 ;; <optab> expands to the name of the optab for a particular code.
1014 (define_code_attr optab [(ashift "ashl")
1023 (simple_return "simple_return")])
1025 ;; <insn> expands to the name of the insn that implements a particular code.
1026 (define_code_attr insn [(ashift "sll")
1035 ;; <immediate_insn> expands to the name of the insn that implements
1036 ;; a particular code to operate on immediate values.
1037 (define_code_attr immediate_insn [(ior "ori")
1041 (define_code_attr shift_compression [(ashift "micromips32")
1042 (lshiftrt "micromips32")
1045 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
1046 (define_code_attr fcond [(unordered "un")
1057 ;; Similar, but for swapped conditions.
1058 (define_code_attr swapped_fcond [(ge "le")
1063 ;; The value of the bit when the branch is taken for branch_bit patterns.
1064 ;; Comparison is always against zero so this depends on the operator.
1065 (define_code_attr bbv [(eq "0") (ne "1")])
1067 ;; This is the inverse value of bbv.
1068 (define_code_attr bbinv [(eq "1") (ne "0")])
1070 ;; The sel mnemonic to use depending on the condition test.
1071 (define_code_attr sel [(eq "seleqz") (ne "selnez")])
1072 (define_code_attr selinv [(eq "selnez") (ne "seleqz")])
1074 ;; .........................
1076 ;; Branch, call and jump delay slots
1078 ;; .........................
1080 (define_delay (and (eq_attr "type" "branch")
1081 (not (match_test "TARGET_MIPS16"))
1082 (eq_attr "branch_likely" "yes"))
1083 [(eq_attr "can_delay" "yes")
1085 (eq_attr "can_delay" "yes")])
1087 ;; Branches that have delay slots and don't have likely variants do
1088 ;; not annul on false.
1089 (define_delay (and (eq_attr "type" "branch")
1090 (not (match_test "TARGET_MIPS16"))
1091 (ior (match_test "TARGET_CB_NEVER")
1092 (and (eq_attr "compact_form" "maybe")
1093 (not (match_test "TARGET_CB_ALWAYS")))
1094 (eq_attr "compact_form" "never"))
1095 (eq_attr "branch_likely" "no"))
1096 [(eq_attr "can_delay" "yes")
1100 (define_delay (and (eq_attr "type" "jump")
1101 (ior (match_test "TARGET_CB_NEVER")
1102 (and (eq_attr "compact_form" "maybe")
1103 (not (match_test "TARGET_CB_ALWAYS")))
1104 (eq_attr "compact_form" "never")))
1105 [(eq_attr "can_delay" "yes")
1109 ;; Call type instructions should never have a compact form as the
1110 ;; type is only used for MIPS16 patterns. For safety put the compact
1111 ;; branch detection condition in anyway.
1112 (define_delay (and (eq_attr "type" "call")
1113 (eq_attr "jal_macro" "no")
1114 (ior (match_test "TARGET_CB_NEVER")
1115 (and (eq_attr "compact_form" "maybe")
1116 (not (match_test "TARGET_CB_ALWAYS")))
1117 (eq_attr "compact_form" "never")))
1118 [(eq_attr "can_delay" "yes")
1122 ;; Pipeline descriptions.
1124 ;; generic.md provides a fallback for processors without a specific
1125 ;; pipeline description. It is derived from the old define_function_unit
1126 ;; version and uses the "alu" and "imuldiv" units declared below.
1128 ;; Some of the processor-specific files are also derived from old
1129 ;; define_function_unit descriptions and simply override the parts of
1130 ;; generic.md that don't apply. The other processor-specific files
1131 ;; are self-contained.
1132 (define_automaton "alu,imuldiv")
1134 (define_cpu_unit "alu" "alu")
1135 (define_cpu_unit "imuldiv" "imuldiv")
1137 ;; Ghost instructions produce no real code and introduce no hazards.
1138 ;; They exist purely to express an effect on dataflow.
1139 (define_insn_reservation "ghost" 0
1140 (eq_attr "type" "ghost")
1143 (include "i6400.md")
1144 (include "p5600.md")
1145 (include "m5100.md")
1163 (include "10000.md")
1164 (include "loongson2ef.md")
1165 (include "loongson3a.md")
1166 (include "octeon.md")
1168 (include "sr71k.md")
1171 (include "generic.md")
1174 ;; ....................
1176 ;; CONDITIONAL TRAPS
1178 ;; ....................
1182 [(trap_if (const_int 1) (const_int 0))]
1185 if (ISA_HAS_COND_TRAP)
1186 return "teq\t$0,$0";
1187 else if (TARGET_MIPS16)
1192 [(set_attr "type" "trap")])
1194 (define_expand "ctrap<mode>4"
1195 [(trap_if (match_operator 0 "comparison_operator"
1196 [(match_operand:GPR 1 "reg_or_0_operand")
1197 (match_operand:GPR 2 "arith_operand")])
1198 (match_operand 3 "const_0_operand"))]
1199 "ISA_HAS_COND_TRAPI || ISA_HAS_COND_TRAP"
1201 mips_expand_conditional_trap (operands[0]);
1205 (define_insn "*conditional_trap_reg<mode>"
1206 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1207 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1208 (match_operand:GPR 2 "reg_or_0_operand" "dJ")])
1210 "ISA_HAS_COND_TRAP && !ISA_HAS_COND_TRAPI"
1212 [(set_attr "type" "trap")])
1214 (define_insn "*conditional_trap<mode>"
1215 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1216 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1217 (match_operand:GPR 2 "arith_operand" "dI")])
1219 "ISA_HAS_COND_TRAPI"
1221 [(set_attr "type" "trap")])
1224 ;; ....................
1228 ;; ....................
1231 (define_insn "add<mode>3"
1232 [(set (match_operand:ANYF 0 "register_operand" "=f")
1233 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1234 (match_operand:ANYF 2 "register_operand" "f")))]
1236 "add.<fmt>\t%0,%1,%2"
1237 [(set_attr "type" "fadd")
1238 (set_attr "mode" "<UNITMODE>")])
1240 (define_expand "add<mode>3"
1241 [(set (match_operand:GPR 0 "register_operand")
1242 (plus:GPR (match_operand:GPR 1 "register_operand")
1243 (match_operand:GPR 2 "arith_operand")))]
1246 (define_insn "*add<mode>3"
1247 [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!u,!ks,!d,d")
1248 (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,!ks,!ks,0,d")
1249 (match_operand:GPR 2 "arith_operand" "!u,d,Uead,Uuw6,Uesp,Usb4,Q")))]
1252 if (which_alternative == 0
1253 || which_alternative == 1)
1254 return "<d>addu\t%0,%1,%2";
1256 return "<d>addiu\t%0,%1,%2";
1258 [(set_attr "alu_type" "add")
1259 (set_attr "compression" "micromips32,*,micromips32,micromips32,micromips32,micromips32,*")
1260 (set_attr "mode" "<MODE>")])
1262 (define_insn "*add<mode>3_mips16"
1263 [(set (match_operand:GPR 0 "register_operand" "=ks,ks,d,d,d,d,d,d,d")
1264 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,ks,ks,0,0,d,d,d")
1265 (match_operand:GPR 2 "arith_operand" "Usd8,Q,Uuw<si8_di5>,Q,Usb<si8_di5>,Q,Usb4,O,d")))]
1277 [(set_attr "alu_type" "add")
1278 (set_attr "mode" "<MODE>")
1279 (set_attr "extended_mips16" "no,yes,no,yes,no,yes,no,yes,no")])
1281 ;; On the mips16, we can sometimes split an add of a constant which is
1282 ;; a 4 byte instruction into two adds which are both 2 byte
1283 ;; instructions. There are two cases: one where we are adding a
1284 ;; constant plus a register to another register, and one where we are
1285 ;; simply adding a constant to a register.
1288 [(set (match_operand:SI 0 "d_operand")
1289 (plus:SI (match_dup 0)
1290 (match_operand:SI 1 "const_int_operand")))]
1291 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1292 && ((INTVAL (operands[1]) > 0x7f
1293 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1294 || (INTVAL (operands[1]) < - 0x80
1295 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1296 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1297 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1299 HOST_WIDE_INT val = INTVAL (operands[1]);
1303 operands[1] = GEN_INT (0x7f);
1304 operands[2] = GEN_INT (val - 0x7f);
1308 operands[1] = GEN_INT (- 0x80);
1309 operands[2] = GEN_INT (val + 0x80);
1314 [(set (match_operand:SI 0 "d_operand")
1315 (plus:SI (match_operand:SI 1 "d_operand")
1316 (match_operand:SI 2 "const_int_operand")))]
1317 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1318 && REGNO (operands[0]) != REGNO (operands[1])
1319 && ((INTVAL (operands[2]) > 0x7
1320 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1321 || (INTVAL (operands[2]) < - 0x8
1322 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1323 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1324 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1326 HOST_WIDE_INT val = INTVAL (operands[2]);
1330 operands[2] = GEN_INT (0x7);
1331 operands[3] = GEN_INT (val - 0x7);
1335 operands[2] = GEN_INT (- 0x8);
1336 operands[3] = GEN_INT (val + 0x8);
1341 [(set (match_operand:DI 0 "d_operand")
1342 (plus:DI (match_dup 0)
1343 (match_operand:DI 1 "const_int_operand")))]
1344 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1345 && ((INTVAL (operands[1]) > 0xf
1346 && INTVAL (operands[1]) <= 0xf + 0xf)
1347 || (INTVAL (operands[1]) < - 0x10
1348 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1349 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1350 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1352 HOST_WIDE_INT val = INTVAL (operands[1]);
1356 operands[1] = GEN_INT (0xf);
1357 operands[2] = GEN_INT (val - 0xf);
1361 operands[1] = GEN_INT (- 0x10);
1362 operands[2] = GEN_INT (val + 0x10);
1367 [(set (match_operand:DI 0 "d_operand")
1368 (plus:DI (match_operand:DI 1 "d_operand")
1369 (match_operand:DI 2 "const_int_operand")))]
1370 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1371 && REGNO (operands[0]) != REGNO (operands[1])
1372 && ((INTVAL (operands[2]) > 0x7
1373 && INTVAL (operands[2]) <= 0x7 + 0xf)
1374 || (INTVAL (operands[2]) < - 0x8
1375 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1376 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1377 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1379 HOST_WIDE_INT val = INTVAL (operands[2]);
1383 operands[2] = GEN_INT (0x7);
1384 operands[3] = GEN_INT (val - 0x7);
1388 operands[2] = GEN_INT (- 0x8);
1389 operands[3] = GEN_INT (val + 0x8);
1393 (define_insn "*addsi3_extended"
1394 [(set (match_operand:DI 0 "register_operand" "=d,d")
1396 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1397 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1398 "TARGET_64BIT && !TARGET_MIPS16"
1402 [(set_attr "alu_type" "add")
1403 (set_attr "mode" "SI")])
1405 ;; Split this insn so that the addiu splitters can have a crack at it.
1406 ;; Use a conservative length estimate until the split.
1407 (define_insn_and_split "*addsi3_extended_mips16"
1408 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1410 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1411 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1412 "TARGET_64BIT && TARGET_MIPS16"
1414 "&& reload_completed"
1415 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1416 { operands[3] = gen_lowpart (SImode, operands[0]); }
1417 [(set_attr "alu_type" "add")
1418 (set_attr "mode" "SI")
1419 (set_attr "extended_mips16" "yes")])
1421 ;; Combiner patterns for unsigned byte-add.
1423 (define_insn "*baddu_si_eb"
1424 [(set (match_operand:SI 0 "register_operand" "=d")
1427 (plus:SI (match_operand:SI 1 "register_operand" "d")
1428 (match_operand:SI 2 "register_operand" "d")) 3)))]
1429 "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
1431 [(set_attr "alu_type" "add")])
1433 (define_insn "*baddu_si_el"
1434 [(set (match_operand:SI 0 "register_operand" "=d")
1437 (plus:SI (match_operand:SI 1 "register_operand" "d")
1438 (match_operand:SI 2 "register_operand" "d")) 0)))]
1439 "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
1441 [(set_attr "alu_type" "add")])
1443 (define_insn "*baddu_di<mode>"
1444 [(set (match_operand:GPR 0 "register_operand" "=d")
1447 (plus:DI (match_operand:DI 1 "register_operand" "d")
1448 (match_operand:DI 2 "register_operand" "d")))))]
1449 "ISA_HAS_BADDU && TARGET_64BIT"
1451 [(set_attr "alu_type" "add")])
1454 ;; ....................
1458 ;; ....................
1461 (define_insn "sub<mode>3"
1462 [(set (match_operand:ANYF 0 "register_operand" "=f")
1463 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1464 (match_operand:ANYF 2 "register_operand" "f")))]
1466 "sub.<fmt>\t%0,%1,%2"
1467 [(set_attr "type" "fadd")
1468 (set_attr "mode" "<UNITMODE>")])
1470 (define_insn "sub<mode>3"
1471 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
1472 (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d")
1473 (match_operand:GPR 2 "register_operand" "!u,d")))]
1476 [(set_attr "alu_type" "sub")
1477 (set_attr "compression" "micromips32,*")
1478 (set_attr "mode" "<MODE>")])
1480 (define_insn "*subsi3_extended"
1481 [(set (match_operand:DI 0 "register_operand" "=d")
1483 (minus:SI (match_operand:SI 1 "register_operand" "d")
1484 (match_operand:SI 2 "register_operand" "d"))))]
1487 [(set_attr "alu_type" "sub")
1488 (set_attr "mode" "DI")])
1491 ;; ....................
1495 ;; ....................
1498 (define_expand "mul<mode>3"
1499 [(set (match_operand:SCALARF 0 "register_operand")
1500 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1501 (match_operand:SCALARF 2 "register_operand")))]
1505 (define_insn "*mul<mode>3"
1506 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1507 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1508 (match_operand:SCALARF 2 "register_operand" "f")))]
1509 "!TARGET_4300_MUL_FIX"
1510 "mul.<fmt>\t%0,%1,%2"
1511 [(set_attr "type" "fmul")
1512 (set_attr "mode" "<MODE>")])
1514 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1515 ;; operands may corrupt immediately following multiplies. This is a
1516 ;; simple fix to insert NOPs.
1518 (define_insn "*mul<mode>3_r4300"
1519 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1520 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1521 (match_operand:SCALARF 2 "register_operand" "f")))]
1522 "TARGET_4300_MUL_FIX"
1523 "mul.<fmt>\t%0,%1,%2\;nop"
1524 [(set_attr "type" "fmul")
1525 (set_attr "mode" "<MODE>")
1526 (set_attr "insn_count" "2")])
1528 (define_insn "mulv2sf3"
1529 [(set (match_operand:V2SF 0 "register_operand" "=f")
1530 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1531 (match_operand:V2SF 2 "register_operand" "f")))]
1532 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1534 [(set_attr "type" "fmul")
1535 (set_attr "mode" "SF")])
1537 ;; The original R4000 has a cpu bug. If a double-word or a variable
1538 ;; shift executes while an integer multiplication is in progress, the
1539 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1540 ;; with the mult on the R4000.
1542 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1543 ;; (also valid for MIPS R4000MC processors):
1545 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1546 ;; this errata description.
1547 ;; The following code sequence causes the R4000 to incorrectly
1548 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1549 ;; instruction. If the dsra32 instruction is executed during an
1550 ;; integer multiply, the dsra32 will only shift by the amount in
1551 ;; specified in the instruction rather than the amount plus 32
1553 ;; instruction 1: mult rs,rt integer multiply
1554 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1555 ;; right arithmetic + 32
1556 ;; Workaround: A dsra32 instruction placed after an integer
1557 ;; multiply should not be one of the 11 instructions after the
1558 ;; multiply instruction."
1562 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1563 ;; the following description.
1564 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1565 ;; 64-bit versions) may produce incorrect results under the
1566 ;; following conditions:
1567 ;; 1) An integer multiply is currently executing
1568 ;; 2) These types of shift instructions are executed immediately
1569 ;; following an integer divide instruction.
1571 ;; 1) Make sure no integer multiply is running wihen these
1572 ;; instruction are executed. If this cannot be predicted at
1573 ;; compile time, then insert a "mfhi" to R0 instruction
1574 ;; immediately after the integer multiply instruction. This
1575 ;; will cause the integer multiply to complete before the shift
1577 ;; 2) Separate integer divide and these two classes of shift
1578 ;; instructions by another instruction or a noop."
1580 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1583 (define_expand "mul<mode>3"
1584 [(set (match_operand:GPR 0 "register_operand")
1585 (mult:GPR (match_operand:GPR 1 "register_operand")
1586 (match_operand:GPR 2 "register_operand")))]
1587 "ISA_HAS_<D>MULT || ISA_HAS_R6<D>MUL"
1591 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>MUL)
1592 emit_insn (gen_mul<mode>3_mul3_nohilo (operands[0], operands[1],
1594 else if (ISA_HAS_<D>MUL3)
1595 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1596 else if (TARGET_MIPS16)
1598 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
1599 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2]));
1600 emit_move_insn (operands[0], lo);
1602 else if (TARGET_FIX_R4000)
1603 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1606 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1610 (define_insn "mul<mode>3_mul3_nohilo"
1611 [(set (match_operand:GPR 0 "register_operand" "=d")
1612 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1613 (match_operand:GPR 2 "register_operand" "d")))]
1614 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>MUL"
1616 if (TARGET_LOONGSON_2EF)
1617 return "<d>multu.g\t%0,%1,%2";
1618 else if (TARGET_LOONGSON_3A)
1619 return "gs<d>multu\t%0,%1,%2";
1621 return "<d>mul\t%0,%1,%2";
1623 [(set_attr "type" "imul3nc")
1624 (set_attr "mode" "<MODE>")])
1626 (define_insn "mul<mode>3_mul3"
1627 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1628 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1629 (match_operand:GPR 2 "register_operand" "d,d")))
1630 (clobber (match_scratch:GPR 3 "=l,X"))]
1633 if (which_alternative == 1)
1634 return "<d>mult\t%1,%2";
1635 if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900))
1636 return "mult\t%0,%1,%2";
1637 return "<d>mul\t%0,%1,%2";
1639 [(set_attr "type" "imul3,imul")
1640 (set_attr "mode" "<MODE>")])
1642 ;; If a register gets allocated to LO, and we spill to memory, the reload
1643 ;; will include a move from LO to a GPR. Merge it into the multiplication
1644 ;; if it can set the GPR directly.
1647 ;; Operand 1: GPR (1st multiplication operand)
1648 ;; Operand 2: GPR (2nd multiplication operand)
1649 ;; Operand 3: GPR (destination)
1652 [(set (match_operand:SI 0 "lo_operand")
1653 (mult:SI (match_operand:SI 1 "d_operand")
1654 (match_operand:SI 2 "d_operand")))
1655 (clobber (scratch:SI))])
1656 (set (match_operand:SI 3 "d_operand")
1658 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1661 (mult:SI (match_dup 1)
1663 (clobber (match_dup 0))])])
1665 (define_insn "mul<mode>3_internal"
1666 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
1667 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1668 (match_operand:GPR 2 "register_operand" "d")))]
1669 "ISA_HAS_<D>MULT && !TARGET_FIX_R4000"
1671 [(set_attr "type" "imul")
1672 (set_attr "mode" "<MODE>")])
1674 (define_insn "mul<mode>3_r4000"
1675 [(set (match_operand:GPR 0 "register_operand" "=d")
1676 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1677 (match_operand:GPR 2 "register_operand" "d")))
1678 (clobber (match_scratch:GPR 3 "=l"))]
1679 "ISA_HAS_<D>MULT && TARGET_FIX_R4000"
1680 "<d>mult\t%1,%2\;mflo\t%0"
1681 [(set_attr "type" "imul")
1682 (set_attr "mode" "<MODE>")
1683 (set_attr "insn_count" "2")])
1685 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1686 ;; of "mult; mflo". They have the same latency, but the first form gives
1687 ;; us an extra cycle to compute the operands.
1690 ;; Operand 1: GPR (1st multiplication operand)
1691 ;; Operand 2: GPR (2nd multiplication operand)
1692 ;; Operand 3: GPR (destination)
1694 [(set (match_operand:SI 0 "lo_operand")
1695 (mult:SI (match_operand:SI 1 "d_operand")
1696 (match_operand:SI 2 "d_operand")))
1697 (set (match_operand:SI 3 "d_operand")
1699 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1704 (plus:SI (mult:SI (match_dup 1)
1708 (plus:SI (mult:SI (match_dup 1)
1712 ;; Multiply-accumulate patterns
1714 ;; This pattern is first matched by combine, which tries to use the
1715 ;; pattern wherever it can. We don't know until later whether it
1716 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1717 ;; so we need to keep both options open.
1719 ;; The second alternative has a "?" marker because it is generally
1720 ;; one instruction more costly than the first alternative. This "?"
1721 ;; marker is enough to convey the relative costs to the register
1724 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1725 ;; reloads of the other operands, even though operands 4 and 5 need no
1726 ;; copy instructions. Reload therefore thinks that the second alternative
1727 ;; is two reloads more costly than the first. We add "*?*?" to the first
1728 ;; alternative as a counterweight.
1730 ;; LRA simulates reload but the cost of reloading scratches is lower
1731 ;; than of the classic reload. For the time being, removing the counterweight
1732 ;; for LRA is more profitable.
1733 (define_insn "*mul_acc_si"
1734 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?")
1735 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1736 (match_operand:SI 2 "register_operand" "d,d,d"))
1737 (match_operand:SI 3 "register_operand" "0,0,d")))
1738 (clobber (match_scratch:SI 4 "=X,X,l"))
1739 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1740 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1745 [(set_attr "type" "imadd")
1746 (set_attr "accum_in" "3")
1747 (set_attr "mode" "SI")
1748 (set_attr "insn_count" "1,1,2")
1749 (set (attr "enabled")
1750 (cond [(and (eq_attr "alternative" "0")
1751 (match_test "!mips_lra_flag"))
1752 (const_string "yes")
1753 (and (eq_attr "alternative" "1")
1754 (match_test "mips_lra_flag"))
1755 (const_string "yes")
1756 (eq_attr "alternative" "2")
1757 (const_string "yes")]
1758 (const_string "no")))])
1760 ;; The same idea applies here. The middle alternative needs one less
1761 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1762 (define_insn "*mul_acc_si_r3900"
1763 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d*?,d?")
1764 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d,d")
1765 (match_operand:SI 2 "register_operand" "d,d,d,d"))
1766 (match_operand:SI 3 "register_operand" "0,0,l,d")))
1767 (clobber (match_scratch:SI 4 "=X,X,3,l"))
1768 (clobber (match_scratch:SI 5 "=X,X,X,&d"))]
1769 "TARGET_MIPS3900 && !TARGET_MIPS16"
1775 [(set_attr "type" "imadd")
1776 (set_attr "accum_in" "3")
1777 (set_attr "mode" "SI")
1778 (set_attr "insn_count" "1,1,1,2")
1779 (set (attr "enabled")
1780 (cond [(and (eq_attr "alternative" "0")
1781 (match_test "!mips_lra_flag"))
1782 (const_string "yes")
1783 (and (eq_attr "alternative" "1")
1784 (match_test "mips_lra_flag"))
1785 (const_string "yes")
1786 (eq_attr "alternative" "2,3")
1787 (const_string "yes")]
1788 (const_string "no")))])
1790 ;; Split *mul_acc_si if both the source and destination accumulator
1793 [(set (match_operand:SI 0 "d_operand")
1794 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1795 (match_operand:SI 2 "d_operand"))
1796 (match_operand:SI 3 "d_operand")))
1797 (clobber (match_operand:SI 4 "lo_operand"))
1798 (clobber (match_operand:SI 5 "d_operand"))]
1800 [(parallel [(set (match_dup 5)
1801 (mult:SI (match_dup 1) (match_dup 2)))
1802 (clobber (match_dup 4))])
1803 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1806 (define_insn "*macc"
1807 [(set (match_operand:SI 0 "register_operand" "=l,d")
1808 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1809 (match_operand:SI 2 "register_operand" "d,d"))
1810 (match_operand:SI 3 "register_operand" "0,l")))
1811 (clobber (match_scratch:SI 4 "=X,3"))]
1814 if (which_alternative == 1)
1815 return "macc\t%0,%1,%2";
1816 else if (TARGET_MIPS5500)
1817 return "madd\t%1,%2";
1819 /* The VR4130 assumes that there is a two-cycle latency between a macc
1820 that "writes" to $0 and an instruction that reads from it. We avoid
1821 this by assigning to $1 instead. */
1822 return "%[macc\t%@,%1,%2%]";
1824 [(set_attr "type" "imadd")
1825 (set_attr "accum_in" "3")
1826 (set_attr "mode" "SI")])
1828 (define_insn "*msac"
1829 [(set (match_operand:SI 0 "register_operand" "=l,d")
1830 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1831 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1832 (match_operand:SI 3 "register_operand" "d,d"))))
1833 (clobber (match_scratch:SI 4 "=X,1"))]
1836 if (which_alternative == 1)
1837 return "msac\t%0,%2,%3";
1838 else if (TARGET_MIPS5500)
1839 return "msub\t%2,%3";
1841 return "msac\t$0,%2,%3";
1843 [(set_attr "type" "imadd")
1844 (set_attr "accum_in" "1")
1845 (set_attr "mode" "SI")])
1847 ;; An msac-like instruction implemented using negation and a macc.
1848 (define_insn_and_split "*msac_using_macc"
1849 [(set (match_operand:SI 0 "register_operand" "=l,d")
1850 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1851 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1852 (match_operand:SI 3 "register_operand" "d,d"))))
1853 (clobber (match_scratch:SI 4 "=X,1"))
1854 (clobber (match_scratch:SI 5 "=d,d"))]
1855 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1857 "&& reload_completed"
1859 (neg:SI (match_dup 3)))
1862 (plus:SI (mult:SI (match_dup 2)
1865 (clobber (match_dup 4))])]
1867 [(set_attr "type" "imadd")
1868 (set_attr "accum_in" "1")
1869 (set_attr "insn_count" "2")])
1871 ;; Patterns generated by the define_peephole2 below.
1873 (define_insn "*macc2"
1874 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1875 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1876 (match_operand:SI 2 "register_operand" "d"))
1878 (set (match_operand:SI 3 "register_operand" "=d")
1879 (plus:SI (mult:SI (match_dup 1)
1882 "ISA_HAS_MACC && reload_completed"
1884 [(set_attr "type" "imadd")
1885 (set_attr "accum_in" "0")
1886 (set_attr "mode" "SI")])
1888 (define_insn "*msac2"
1889 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1890 (minus:SI (match_dup 0)
1891 (mult:SI (match_operand:SI 1 "register_operand" "d")
1892 (match_operand:SI 2 "register_operand" "d"))))
1893 (set (match_operand:SI 3 "register_operand" "=d")
1894 (minus:SI (match_dup 0)
1895 (mult:SI (match_dup 1)
1897 "ISA_HAS_MSAC && reload_completed"
1899 [(set_attr "type" "imadd")
1900 (set_attr "accum_in" "0")
1901 (set_attr "mode" "SI")])
1903 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1907 ;; Operand 1: macc/msac
1908 ;; Operand 2: GPR (destination)
1911 [(set (match_operand:SI 0 "lo_operand")
1912 (match_operand:SI 1 "macc_msac_operand"))
1913 (clobber (scratch:SI))])
1914 (set (match_operand:SI 2 "d_operand")
1917 [(parallel [(set (match_dup 0)
1922 ;; When we have a three-address multiplication instruction, it should
1923 ;; be faster to do a separate multiply and add, rather than moving
1924 ;; something into LO in order to use a macc instruction.
1926 ;; This peephole needs a scratch register to cater for the case when one
1927 ;; of the multiplication operands is the same as the destination.
1929 ;; Operand 0: GPR (scratch)
1931 ;; Operand 2: GPR (addend)
1932 ;; Operand 3: GPR (destination)
1933 ;; Operand 4: macc/msac
1934 ;; Operand 5: new multiplication
1935 ;; Operand 6: new addition/subtraction
1937 [(match_scratch:SI 0 "d")
1938 (set (match_operand:SI 1 "lo_operand")
1939 (match_operand:SI 2 "d_operand"))
1942 [(set (match_operand:SI 3 "d_operand")
1943 (match_operand:SI 4 "macc_msac_operand"))
1944 (clobber (match_dup 1))])]
1945 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1946 [(parallel [(set (match_dup 0)
1948 (clobber (match_dup 1))])
1952 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1953 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1954 operands[2], operands[0]);
1957 ;; Same as above, except LO is the initial target of the macc.
1959 ;; Operand 0: GPR (scratch)
1961 ;; Operand 2: GPR (addend)
1962 ;; Operand 3: macc/msac
1963 ;; Operand 4: GPR (destination)
1964 ;; Operand 5: new multiplication
1965 ;; Operand 6: new addition/subtraction
1967 [(match_scratch:SI 0 "d")
1968 (set (match_operand:SI 1 "lo_operand")
1969 (match_operand:SI 2 "d_operand"))
1973 (match_operand:SI 3 "macc_msac_operand"))
1974 (clobber (scratch:SI))])
1976 (set (match_operand:SI 4 "d_operand")
1978 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1979 [(parallel [(set (match_dup 0)
1981 (clobber (match_dup 1))])
1985 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1986 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1987 operands[2], operands[0]);
1990 ;; See the comment above *mul_add_si for details.
1991 (define_insn "*mul_sub_si"
1992 [(set (match_operand:SI 0 "register_operand" "=l*?*?,l,d?")
1993 (minus:SI (match_operand:SI 1 "register_operand" "0,0,d")
1994 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1995 (match_operand:SI 3 "register_operand" "d,d,d"))))
1996 (clobber (match_scratch:SI 4 "=X,X,l"))
1997 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1998 "GENERATE_MADD_MSUB"
2003 [(set_attr "type" "imadd")
2004 (set_attr "accum_in" "1")
2005 (set_attr "mode" "SI")
2006 (set_attr "insn_count" "1,1,2")
2007 (set (attr "enabled")
2008 (cond [(and (eq_attr "alternative" "0")
2009 (match_test "!mips_lra_flag"))
2010 (const_string "yes")
2011 (and (eq_attr "alternative" "1")
2012 (match_test "mips_lra_flag"))
2013 (const_string "yes")
2014 (eq_attr "alternative" "2")
2015 (const_string "yes")]
2016 (const_string "no")))])
2018 ;; Split *mul_sub_si if both the source and destination accumulator
2021 [(set (match_operand:SI 0 "d_operand")
2022 (minus:SI (match_operand:SI 1 "d_operand")
2023 (mult:SI (match_operand:SI 2 "d_operand")
2024 (match_operand:SI 3 "d_operand"))))
2025 (clobber (match_operand:SI 4 "lo_operand"))
2026 (clobber (match_operand:SI 5 "d_operand"))]
2028 [(parallel [(set (match_dup 5)
2029 (mult:SI (match_dup 2) (match_dup 3)))
2030 (clobber (match_dup 4))])
2031 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
2034 (define_insn "*muls"
2035 [(set (match_operand:SI 0 "register_operand" "=l,d")
2036 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
2037 (match_operand:SI 2 "register_operand" "d,d"))))
2038 (clobber (match_scratch:SI 3 "=X,l"))]
2043 [(set_attr "type" "imul,imul3")
2044 (set_attr "mode" "SI")])
2046 (define_expand "<u>mulsidi3"
2047 [(set (match_operand:DI 0 "register_operand")
2048 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2049 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2050 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
2052 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
2053 emit_insn (fn (operands[0], operands[1], operands[2]));
2057 (define_expand "<u>mulsidi3_32bit_r6"
2058 [(set (match_operand:DI 0 "register_operand")
2059 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2060 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2061 "!TARGET_64BIT && ISA_HAS_R6MUL"
2063 rtx dest = gen_reg_rtx (DImode);
2064 rtx low = mips_subword (dest, 0);
2065 rtx high = mips_subword (dest, 1);
2067 emit_insn (gen_mulsi3_mul3_nohilo (low, operands[1], operands[2]));
2068 emit_insn (gen_<su>mulsi3_highpart_r6 (high, operands[1], operands[2]));
2070 emit_move_insn (mips_subword (operands[0], 0), low);
2071 emit_move_insn (mips_subword (operands[0], 1), high);
2075 (define_expand "<u>mulsidi3_32bit_mips16"
2076 [(set (match_operand:DI 0 "register_operand")
2077 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2078 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2079 "!TARGET_64BIT && TARGET_MIPS16"
2083 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2084 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2085 emit_move_insn (operands[0], hilo);
2089 ;; As well as being named patterns, these instructions are used by the
2090 ;; __builtin_mips_mult<u>() functions. We must always make those functions
2091 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2092 (define_insn "<u>mulsidi3_32bit"
2093 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2094 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2095 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
2096 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP) && ISA_HAS_MULT"
2098 if (ISA_HAS_DSP_MULT)
2099 return "mult<u>\t%q0,%1,%2";
2101 return "mult<u>\t%1,%2";
2103 [(set_attr "type" "imul")
2104 (set_attr "mode" "SI")])
2106 (define_insn "<u>mulsidi3_32bit_r4000"
2107 [(set (match_operand:DI 0 "register_operand" "=d")
2108 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2109 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2110 (clobber (match_scratch:DI 3 "=x"))]
2111 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP && ISA_HAS_MULT"
2112 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2113 [(set_attr "type" "imul")
2114 (set_attr "mode" "SI")
2115 (set_attr "insn_count" "3")])
2117 (define_insn_and_split "<u>mulsidi3_64bit"
2118 [(set (match_operand:DI 0 "register_operand" "=d")
2119 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2120 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2121 (clobber (match_scratch:TI 3 "=x"))
2122 (clobber (match_scratch:DI 4 "=d"))]
2123 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3
2124 && !TARGET_MIPS16 && ISA_HAS_MULT"
2126 "&& reload_completed"
2129 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
2130 operands[2], operands[4]));
2133 [(set_attr "type" "imul")
2134 (set_attr "mode" "SI")
2135 (set (attr "insn_count")
2136 (if_then_else (match_test "ISA_HAS_EXT_INS")
2140 (define_expand "<u>mulsidi3_64bit_mips16"
2141 [(set (match_operand:DI 0 "register_operand")
2142 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2143 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
2144 "TARGET_64BIT && TARGET_MIPS16"
2146 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
2147 operands[2], gen_reg_rtx (DImode)));
2151 (define_expand "<u>mulsidi3_64bit_split"
2152 [(set (match_operand:DI 0 "register_operand")
2153 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2154 (any_extend:DI (match_operand:SI 2 "register_operand"))))
2155 (clobber (match_operand:DI 3 "register_operand"))]
2160 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2161 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2163 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM));
2164 emit_insn (gen_mfhidi_ti (operands[3], hilo));
2166 if (ISA_HAS_EXT_INS)
2167 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32),
2171 /* Zero-extend the low part. */
2172 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32));
2173 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32));
2175 /* Shift the high part into place. */
2176 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32));
2178 /* OR the two halves together. */
2179 mips_emit_binary (IOR, operands[0], operands[0], operands[3]);
2184 (define_insn "<u>mulsidi3_64bit_hilo"
2185 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2188 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2189 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
2191 "TARGET_64BIT && !TARGET_FIX_R4000"
2193 [(set_attr "type" "imul")
2194 (set_attr "mode" "SI")])
2196 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
2197 (define_insn "mulsidi3_64bit_dmul"
2198 [(set (match_operand:DI 0 "register_operand" "=d")
2199 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2200 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2201 (clobber (match_scratch:DI 3 "=l"))]
2204 [(set_attr "type" "imul3")
2205 (set_attr "mode" "DI")])
2207 (define_insn "mulsidi3_64bit_r6dmul"
2208 [(set (match_operand:DI 0 "register_operand" "=d")
2209 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2210 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
2213 [(set_attr "type" "imul3nc")
2214 (set_attr "mode" "DI")])
2216 ;; Widening multiply with negation.
2217 (define_insn "*muls<u>_di"
2218 [(set (match_operand:DI 0 "muldiv_target_operand" "=x")
2221 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2222 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2223 "!TARGET_64BIT && ISA_HAS_MULS"
2225 [(set_attr "type" "imul")
2226 (set_attr "mode" "SI")])
2228 ;; As well as being named patterns, these instructions are used by the
2229 ;; __builtin_mips_msub<u>() functions. We must always make those functions
2230 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2232 ;; This leads to a slight inconsistency. We honor any tuning overrides
2233 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
2234 ;; even if !ISA_HAS_DSP_MULT.
2235 (define_insn "<u>msubsidi4"
2236 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2238 (match_operand:DI 3 "muldiv_target_operand" "0")
2240 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2241 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2242 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
2244 if (ISA_HAS_DSP_MULT)
2245 return "msub<u>\t%q0,%1,%2";
2246 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
2247 return "msub<u>\t%1,%2";
2249 return "msac<u>\t$0,%1,%2";
2251 [(set_attr "type" "imadd")
2252 (set_attr "accum_in" "3")
2253 (set_attr "mode" "SI")])
2255 ;; _highpart patterns
2257 (define_expand "<su>mulsi3_highpart"
2258 [(set (match_operand:SI 0 "register_operand")
2261 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2262 (any_extend:DI (match_operand:SI 2 "register_operand")))
2267 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
2270 else if (TARGET_MIPS16)
2271 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2273 else if (ISA_HAS_R6MUL)
2274 emit_insn (gen_<su>mulsi3_highpart_r6 (operands[0], operands[1],
2277 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
2282 (define_insn "<su>mulsi3_highpart_r6"
2283 [(set (match_operand:SI 0 "register_operand" "=d")
2286 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2287 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2291 [(set_attr "type" "imul3nc")
2292 (set_attr "mode" "SI")])
2294 (define_insn_and_split "<su>mulsi3_highpart_internal"
2295 [(set (match_operand:SI 0 "register_operand" "=d")
2298 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2299 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2301 (clobber (match_scratch:SI 3 "=l"))]
2302 "ISA_HAS_MULT && !ISA_HAS_MULHI && !TARGET_MIPS16"
2303 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2304 "&& reload_completed && !TARGET_FIX_R4000"
2307 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2311 [(set_attr "type" "imul")
2312 (set_attr "mode" "SI")
2313 (set_attr "insn_count" "2")])
2315 (define_expand "<su>mulsi3_highpart_split"
2316 [(set (match_operand:SI 0 "register_operand")
2319 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2320 (any_extend:DI (match_operand:SI 2 "register_operand")))
2328 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2329 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2330 emit_insn (gen_mfhisi_ti (operands[0], hilo));
2334 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2335 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2336 emit_insn (gen_mfhisi_di (operands[0], hilo));
2341 (define_insn "<su>mulsi3_highpart_mulhi_internal"
2342 [(set (match_operand:SI 0 "register_operand" "=d")
2346 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2347 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2349 (clobber (match_scratch:SI 3 "=l"))]
2351 "mulhi<u>\t%0,%1,%2"
2352 [(set_attr "type" "imul3")
2353 (set_attr "mode" "SI")])
2355 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
2356 [(set (match_operand:SI 0 "register_operand" "=d")
2361 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2362 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2364 (clobber (match_scratch:SI 3 "=l"))]
2366 "mulshi<u>\t%0,%1,%2"
2367 [(set_attr "type" "imul3")
2368 (set_attr "mode" "SI")])
2370 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
2371 ;; errata MD(0), which says that dmultu does not always produce the
2373 (define_expand "<su>muldi3_highpart"
2374 [(set (match_operand:DI 0 "register_operand")
2377 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2378 (any_extend:TI (match_operand:DI 2 "register_operand")))
2382 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120))"
2385 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2387 else if (ISA_HAS_R6DMUL)
2388 emit_insn (gen_<su>muldi3_highpart_r6 (operands[0], operands[1],
2391 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1],
2396 (define_insn "<su>muldi3_highpart_r6"
2397 [(set (match_operand:DI 0 "register_operand" "=d")
2400 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2401 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2405 [(set_attr "type" "imul3nc")
2406 (set_attr "mode" "DI")])
2408 (define_insn_and_split "<su>muldi3_highpart_internal"
2409 [(set (match_operand:DI 0 "register_operand" "=d")
2412 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2413 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2415 (clobber (match_scratch:DI 3 "=l"))]
2418 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2419 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2420 "&& reload_completed && !TARGET_FIX_R4000"
2423 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2427 [(set_attr "type" "imul")
2428 (set_attr "mode" "DI")
2429 (set_attr "insn_count" "2")])
2431 (define_expand "<su>muldi3_highpart_split"
2432 [(set (match_operand:DI 0 "register_operand")
2435 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2436 (any_extend:TI (match_operand:DI 2 "register_operand")))
2442 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2443 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2444 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2448 (define_expand "<u>mulditi3"
2449 [(set (match_operand:TI 0 "register_operand")
2450 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2451 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2452 "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2458 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2459 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2460 emit_move_insn (operands[0], hilo);
2462 else if (TARGET_FIX_R4000)
2463 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2465 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2470 (define_insn "<u>mulditi3_internal"
2471 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2472 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2473 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2475 && !TARGET_FIX_R4000
2476 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2478 [(set_attr "type" "imul")
2479 (set_attr "mode" "DI")])
2481 (define_insn "<u>mulditi3_r4000"
2482 [(set (match_operand:TI 0 "register_operand" "=d")
2483 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2484 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2485 (clobber (match_scratch:TI 3 "=x"))]
2488 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2489 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2490 [(set_attr "type" "imul")
2491 (set_attr "mode" "DI")
2492 (set_attr "insn_count" "3")])
2494 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2495 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2497 (define_insn "madsi"
2498 [(set (match_operand:SI 0 "register_operand" "+l")
2499 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2500 (match_operand:SI 2 "register_operand" "d"))
2504 [(set_attr "type" "imadd")
2505 (set_attr "accum_in" "0")
2506 (set_attr "mode" "SI")])
2508 ;; See the comment above <u>msubsidi4 for the relationship between
2509 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2510 (define_insn "<u>maddsidi4"
2511 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2513 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2514 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2515 (match_operand:DI 3 "muldiv_target_operand" "0")))]
2516 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2520 return "mad<u>\t%1,%2";
2521 else if (ISA_HAS_DSP_MULT)
2522 return "madd<u>\t%q0,%1,%2";
2523 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2524 return "madd<u>\t%1,%2";
2526 /* See comment in *macc. */
2527 return "%[macc<u>\t%@,%1,%2%]";
2529 [(set_attr "type" "imadd")
2530 (set_attr "accum_in" "3")
2531 (set_attr "mode" "SI")])
2533 ;; Floating point multiply accumulate instructions.
2535 (define_expand "fma<mode>4"
2536 [(set (match_operand:ANYF 0 "register_operand")
2537 (fma:ANYF (match_operand:ANYF 1 "register_operand")
2538 (match_operand:ANYF 2 "register_operand")
2539 (match_operand:ANYF 3 "register_operand")))]
2540 "ISA_HAS_FUSED_MADDF || ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4")
2542 (define_insn "*fma<mode>4_madd3"
2543 [(set (match_operand:ANYF 0 "register_operand" "=f")
2544 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2545 (match_operand:ANYF 2 "register_operand" "f")
2546 (match_operand:ANYF 3 "register_operand" "0")))]
2547 "ISA_HAS_FUSED_MADD3"
2548 "madd.<fmt>\t%0,%1,%2"
2549 [(set_attr "type" "fmadd")
2550 (set_attr "mode" "<UNITMODE>")])
2552 (define_insn "*fma<mode>4_madd4"
2553 [(set (match_operand:ANYF 0 "register_operand" "=f")
2554 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2555 (match_operand:ANYF 2 "register_operand" "f")
2556 (match_operand:ANYF 3 "register_operand" "f")))]
2557 "ISA_HAS_FUSED_MADD4"
2558 "madd.<fmt>\t%0,%3,%1,%2"
2559 [(set_attr "type" "fmadd")
2560 (set_attr "mode" "<UNITMODE>")])
2562 (define_insn "*fma<mode>4_maddf"
2563 [(set (match_operand:ANYF 0 "register_operand" "=f")
2564 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2565 (match_operand:ANYF 2 "register_operand" "f")
2566 (match_operand:ANYF 3 "register_operand" "0")))]
2567 "ISA_HAS_FUSED_MADDF"
2568 "maddf.<fmt>\t%0,%1,%2"
2569 [(set_attr "type" "fmadd")
2570 (set_attr "mode" "<UNITMODE>")])
2572 ;; The fms, fnma, and fnms instructions can be used even when HONOR_NANS
2573 ;; is true because while IEEE 754-2008 requires the negate operation to
2574 ;; negate the sign of a NAN and the MIPS neg instruction does not do this,
2575 ;; the fma part of the instruction has no requirement on how the sign of
2576 ;; a NAN is handled and so the final sign bit of the entire operation is
2579 (define_expand "fms<mode>4"
2580 [(set (match_operand:ANYF 0 "register_operand")
2581 (fma:ANYF (match_operand:ANYF 1 "register_operand")
2582 (match_operand:ANYF 2 "register_operand")
2583 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))]
2584 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)")
2586 (define_insn "*fms<mode>4_msub3"
2587 [(set (match_operand:ANYF 0 "register_operand" "=f")
2588 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2589 (match_operand:ANYF 2 "register_operand" "f")
2590 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))]
2591 "ISA_HAS_FUSED_MADD3"
2592 "msub.<fmt>\t%0,%1,%2"
2593 [(set_attr "type" "fmadd")
2594 (set_attr "mode" "<UNITMODE>")])
2596 (define_insn "*fms<mode>4_msub4"
2597 [(set (match_operand:ANYF 0 "register_operand" "=f")
2598 (fma:ANYF (match_operand:ANYF 1 "register_operand" "f")
2599 (match_operand:ANYF 2 "register_operand" "f")
2600 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))]
2601 "ISA_HAS_FUSED_MADD4"
2602 "msub.<fmt>\t%0,%3,%1,%2"
2603 [(set_attr "type" "fmadd")
2604 (set_attr "mode" "<UNITMODE>")])
2606 ;; fnma is defined in GCC as (fma (neg op1) op2 op3)
2607 ;; (-op1 * op2) + op3 ==> -(op1 * op2) + op3 ==> -((op1 * op2) - op3)
2608 ;; The mips nmsub instructions implement -((op1 * op2) - op3)
2609 ;; This transformation means we may return the wrong signed zero
2610 ;; so we check HONOR_SIGNED_ZEROS.
2612 (define_expand "fnma<mode>4"
2613 [(set (match_operand:ANYF 0 "register_operand")
2614 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand"))
2615 (match_operand:ANYF 2 "register_operand")
2616 (match_operand:ANYF 3 "register_operand")))]
2617 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)
2618 && !HONOR_SIGNED_ZEROS (<MODE>mode)")
2620 (define_insn "*fnma<mode>4_nmsub3"
2621 [(set (match_operand:ANYF 0 "register_operand" "=f")
2622 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2623 (match_operand:ANYF 2 "register_operand" "f")
2624 (match_operand:ANYF 3 "register_operand" "0")))]
2625 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2626 "nmsub.<fmt>\t%0,%1,%2"
2627 [(set_attr "type" "fmadd")
2628 (set_attr "mode" "<UNITMODE>")])
2630 (define_insn "*fnma<mode>4_nmsub4"
2631 [(set (match_operand:ANYF 0 "register_operand" "=f")
2632 (fma:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2633 (match_operand:ANYF 2 "register_operand" "f")
2634 (match_operand:ANYF 3 "register_operand" "f")))]
2635 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2636 "nmsub.<fmt>\t%0,%3,%1,%2"
2637 [(set_attr "type" "fmadd")
2638 (set_attr "mode" "<UNITMODE>")])
2640 ;; fnms is defined as: (fma (neg op1) op2 (neg op3))
2641 ;; ((-op1) * op2) - op3 ==> -(op1 * op2) - op3 ==> -((op1 * op2) + op3)
2642 ;; The mips nmadd instructions implement -((op1 * op2) + op3)
2643 ;; This transformation means we may return the wrong signed zero
2644 ;; so we check HONOR_SIGNED_ZEROS.
2646 (define_expand "fnms<mode>4"
2647 [(set (match_operand:ANYF 0 "register_operand")
2649 (neg:ANYF (match_operand:ANYF 1 "register_operand"))
2650 (match_operand:ANYF 2 "register_operand")
2651 (neg:ANYF (match_operand:ANYF 3 "register_operand"))))]
2652 "(ISA_HAS_FUSED_MADD3 || ISA_HAS_FUSED_MADD4)
2653 && !HONOR_SIGNED_ZEROS (<MODE>mode)")
2655 (define_insn "*fnms<mode>4_nmadd3"
2656 [(set (match_operand:ANYF 0 "register_operand" "=f")
2658 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2659 (match_operand:ANYF 2 "register_operand" "f")
2660 (neg:ANYF (match_operand:ANYF 3 "register_operand" "0"))))]
2661 "ISA_HAS_FUSED_MADD3 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2662 "nmadd.<fmt>\t%0,%1,%2"
2663 [(set_attr "type" "fmadd")
2664 (set_attr "mode" "<UNITMODE>")])
2666 (define_insn "*fnms<mode>4_nmadd4"
2667 [(set (match_operand:ANYF 0 "register_operand" "=f")
2669 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2670 (match_operand:ANYF 2 "register_operand" "f")
2671 (neg:ANYF (match_operand:ANYF 3 "register_operand" "f"))))]
2672 "ISA_HAS_FUSED_MADD4 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2673 "nmadd.<fmt>\t%0,%3,%1,%2"
2674 [(set_attr "type" "fmadd")
2675 (set_attr "mode" "<UNITMODE>")])
2677 ;; Non-fused Floating point multiply accumulate instructions.
2679 ;; These instructions are not fused and round in between the multiply
2680 ;; and the add (or subtract) so they are equivalent to the separate
2681 ;; multiply and add/sub instructions.
2683 (define_insn "*madd4<mode>"
2684 [(set (match_operand:ANYF 0 "register_operand" "=f")
2685 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2686 (match_operand:ANYF 2 "register_operand" "f"))
2687 (match_operand:ANYF 3 "register_operand" "f")))]
2688 "ISA_HAS_UNFUSED_MADD4"
2689 "madd.<fmt>\t%0,%3,%1,%2"
2690 [(set_attr "type" "fmadd")
2691 (set_attr "mode" "<UNITMODE>")])
2693 (define_insn "*msub4<mode>"
2694 [(set (match_operand:ANYF 0 "register_operand" "=f")
2695 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2696 (match_operand:ANYF 2 "register_operand" "f"))
2697 (match_operand:ANYF 3 "register_operand" "f")))]
2698 "ISA_HAS_UNFUSED_MADD4"
2699 "msub.<fmt>\t%0,%3,%1,%2"
2700 [(set_attr "type" "fmadd")
2701 (set_attr "mode" "<UNITMODE>")])
2703 ;; Like with the fused fms, fnma, and fnms instructions, these unfused
2704 ;; instructions can be used even if HONOR_NANS is set because while
2705 ;; IEEE 754-2008 requires the negate operation to negate the sign of a
2706 ;; NAN and the MIPS neg instruction does not do this, the multiply and
2707 ;; add (or subtract) part of the instruction has no requirement on how
2708 ;; the sign of a NAN is handled and so the final sign bit of the entire
2709 ;; operation is undefined.
2711 (define_insn "*nmadd4<mode>"
2712 [(set (match_operand:ANYF 0 "register_operand" "=f")
2713 (neg:ANYF (plus:ANYF
2714 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2715 (match_operand:ANYF 2 "register_operand" "f"))
2716 (match_operand:ANYF 3 "register_operand" "f"))))]
2717 "ISA_HAS_UNFUSED_MADD4"
2718 "nmadd.<fmt>\t%0,%3,%1,%2"
2719 [(set_attr "type" "fmadd")
2720 (set_attr "mode" "<UNITMODE>")])
2722 (define_insn "*nmsub4<mode>"
2723 [(set (match_operand:ANYF 0 "register_operand" "=f")
2724 (neg:ANYF (minus:ANYF
2725 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2726 (match_operand:ANYF 2 "register_operand" "f"))
2727 (match_operand:ANYF 3 "register_operand" "f"))))]
2728 "ISA_HAS_UNFUSED_MADD4"
2729 "nmsub.<fmt>\t%0,%3,%1,%2"
2730 [(set_attr "type" "fmadd")
2731 (set_attr "mode" "<UNITMODE>")])
2733 ;; Fast-math Non-fused Floating point multiply accumulate instructions.
2735 ;; These instructions are not fused but the expressions they match are
2736 ;; not exactly what the instruction implements in the sense that they
2737 ;; may not generate the properly signed zeros.
2739 ;; This instruction recognizes ((-op1) * op2) - op3 and generates an
2740 ;; nmadd which is really -((op1 * op2) + op3). They are equivalent
2741 ;; except for the sign bit when the result is zero or NaN.
2743 (define_insn "*nmadd4<mode>_fastmath"
2744 [(set (match_operand:ANYF 0 "register_operand" "=f")
2746 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2747 (match_operand:ANYF 2 "register_operand" "f"))
2748 (match_operand:ANYF 3 "register_operand" "f")))]
2749 "ISA_HAS_UNFUSED_MADD4
2750 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2751 "nmadd.<fmt>\t%0,%3,%1,%2"
2752 [(set_attr "type" "fmadd")
2753 (set_attr "mode" "<UNITMODE>")])
2755 ;; This instruction recognizes (op1 - (op2 * op3) and generates an
2756 ;; nmsub which is really -((op2 * op3) - op1). They are equivalent
2757 ;; except for the sign bit when the result is zero or NaN.
2759 (define_insn "*nmsub4<mode>_fastmath"
2760 [(set (match_operand:ANYF 0 "register_operand" "=f")
2762 (match_operand:ANYF 1 "register_operand" "f")
2763 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2764 (match_operand:ANYF 3 "register_operand" "f"))))]
2765 "ISA_HAS_UNFUSED_MADD4
2766 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
2767 "nmsub.<fmt>\t%0,%1,%2,%3"
2768 [(set_attr "type" "fmadd")
2769 (set_attr "mode" "<UNITMODE>")])
2772 ;; ....................
2774 ;; DIVISION and REMAINDER
2776 ;; ....................
2779 (define_expand "div<mode>3"
2780 [(set (match_operand:ANYF 0 "register_operand")
2781 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2782 (match_operand:ANYF 2 "register_operand")))]
2783 "<divide_condition>"
2785 if (const_1_operand (operands[1], <MODE>mode))
2786 if (!(ISA_HAS_FP_RECIP_RSQRT (<MODE>mode)
2787 && flag_unsafe_math_optimizations))
2788 operands[1] = force_reg (<MODE>mode, operands[1]);
2791 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2793 ;; If an mfc1 or dmfc1 happens to access the floating point register
2794 ;; file at the same time a long latency operation (div, sqrt, recip,
2795 ;; sqrt) iterates an intermediate result back through the floating
2796 ;; point register file bypass, then instead returning the correct
2797 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2798 ;; result of the long latency operation.
2800 ;; The workaround is to insert an unconditional 'mov' from/to the
2801 ;; long latency op destination register.
2803 (define_insn "*div<mode>3"
2804 [(set (match_operand:ANYF 0 "register_operand" "=f")
2805 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2806 (match_operand:ANYF 2 "register_operand" "f")))]
2807 "<divide_condition>"
2810 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2812 return "div.<fmt>\t%0,%1,%2";
2814 [(set_attr "type" "fdiv")
2815 (set_attr "mode" "<UNITMODE>")
2816 (set (attr "insn_count")
2817 (if_then_else (match_test "TARGET_FIX_SB1")
2821 (define_insn "*recip<mode>3"
2822 [(set (match_operand:ANYF 0 "register_operand" "=f")
2823 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2824 (match_operand:ANYF 2 "register_operand" "f")))]
2825 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
2828 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2830 return "recip.<fmt>\t%0,%2";
2832 [(set_attr "type" "frdiv")
2833 (set_attr "mode" "<UNITMODE>")
2834 (set (attr "insn_count")
2835 (if_then_else (match_test "TARGET_FIX_SB1")
2839 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2840 ;; with negative operands. We use special libgcc functions instead.
2841 (define_expand "divmod<mode>4"
2843 [(set (match_operand:GPR 0 "register_operand")
2844 (div:GPR (match_operand:GPR 1 "register_operand")
2845 (match_operand:GPR 2 "register_operand")))
2846 (set (match_operand:GPR 3 "register_operand")
2847 (mod:GPR (match_dup 1)
2849 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
2853 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
2854 emit_insn (gen_divmod<mode>4_mips16 (operands[0], operands[1],
2855 operands[2], operands[3], lo));
2860 (define_insn_and_split "*divmod<mode>4"
2861 [(set (match_operand:GPR 0 "register_operand" "=l")
2862 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2863 (match_operand:GPR 2 "register_operand" "d")))
2864 (set (match_operand:GPR 3 "register_operand" "=d")
2865 (mod:GPR (match_dup 1)
2867 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && !TARGET_MIPS16"
2869 "&& reload_completed"
2872 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2875 [(set_attr "type" "idiv")
2876 (set_attr "mode" "<MODE>")
2877 (set_attr "insn_count" "2")])
2879 ;; Expand generates divmod instructions for individual division and modulus
2880 ;; operations. We then rely on CSE to reuse earlier divmods where possible.
2881 ;; This means that, when generating MIPS16 code, it is better not to expose
2882 ;; the fixed LO register until after CSE has finished. However, it's still
2883 ;; better to split before register allocation, so that we don't allocate
2884 ;; one of the scarce MIPS16 registers to an unused result.
2885 (define_insn_and_split "divmod<mode>4_mips16"
2886 [(set (match_operand:GPR 0 "register_operand" "=d")
2887 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2888 (match_operand:GPR 2 "register_operand" "d")))
2889 (set (match_operand:GPR 3 "register_operand" "=d")
2890 (mod:GPR (match_dup 1)
2892 (clobber (match_operand:GPR 4 "lo_operand" "=l"))]
2893 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && TARGET_MIPS16"
2895 "&& cse_not_expected"
2898 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2899 emit_move_insn (operands[0], operands[4]);
2902 [(set_attr "type" "idiv")
2903 (set_attr "mode" "<MODE>")
2904 (set_attr "insn_count" "3")])
2906 (define_expand "udivmod<mode>4"
2908 [(set (match_operand:GPR 0 "register_operand")
2909 (udiv:GPR (match_operand:GPR 1 "register_operand")
2910 (match_operand:GPR 2 "register_operand")))
2911 (set (match_operand:GPR 3 "register_operand")
2912 (umod:GPR (match_dup 1)
2914 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
2918 rtx lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
2919 emit_insn (gen_udivmod<mode>4_mips16 (operands[0], operands[1],
2920 operands[2], operands[3], lo));
2925 (define_insn_and_split "*udivmod<mode>4"
2926 [(set (match_operand:GPR 0 "register_operand" "=l")
2927 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2928 (match_operand:GPR 2 "register_operand" "d")))
2929 (set (match_operand:GPR 3 "register_operand" "=d")
2930 (umod:GPR (match_dup 1)
2932 "ISA_HAS_<D>DIV && !TARGET_MIPS16"
2937 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2940 [(set_attr "type" "idiv")
2941 (set_attr "mode" "<MODE>")
2942 (set_attr "insn_count" "2")])
2944 ;; See the comment above "divmod<mode>4_mips16" for the split timing.
2945 (define_insn_and_split "udivmod<mode>4_mips16"
2946 [(set (match_operand:GPR 0 "register_operand" "=d")
2947 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2948 (match_operand:GPR 2 "register_operand" "d")))
2949 (set (match_operand:GPR 3 "register_operand" "=d")
2950 (umod:GPR (match_dup 1)
2952 (clobber (match_operand:GPR 4 "lo_operand" "=l"))]
2953 "ISA_HAS_<D>DIV && TARGET_MIPS16"
2958 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2959 emit_move_insn (operands[0], operands[4]);
2962 [(set_attr "type" "idiv")
2963 (set_attr "mode" "<MODE>")
2964 (set_attr "insn_count" "3")])
2966 (define_expand "<u>divmod<mode>4_split"
2967 [(set (match_operand:GPR 0 "register_operand")
2968 (any_mod:GPR (match_operand:GPR 1 "register_operand")
2969 (match_operand:GPR 2 "register_operand")))]
2976 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2977 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1],
2979 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo));
2983 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2984 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1],
2986 emit_insn (gen_mfhi<mode>_di (operands[0], hilo));
2991 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2992 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x")
2994 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2995 (match_operand:GPR 2 "register_operand" "d"))]
2997 "ISA_HAS_<GPR:D>DIV"
2998 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2999 [(set_attr "type" "idiv")
3000 (set_attr "mode" "<GPR:MODE>")])
3002 ;; Integer division and modulus.
3004 (define_insn "<u>div<mode>3"
3005 [(set (match_operand:GPR 0 "register_operand" "=&d")
3006 (any_div:GPR (match_operand:GPR 1 "register_operand" "d")
3007 (match_operand:GPR 2 "register_operand" "d")))]
3008 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>DIV"
3010 if (TARGET_LOONGSON_2EF)
3011 return mips_output_division ("<d>div<u>.g\t%0,%1,%2", operands);
3012 else if (TARGET_LOONGSON_3A)
3013 return mips_output_division ("gs<d>div<u>\t%0,%1,%2", operands);
3015 return mips_output_division ("<d>div<u>\t%0,%1,%2", operands);
3017 [(set_attr "type" "idiv3")
3018 (set_attr "mode" "<MODE>")])
3020 (define_insn "<u>mod<mode>3"
3021 [(set (match_operand:GPR 0 "register_operand" "=&d")
3022 (any_mod:GPR (match_operand:GPR 1 "register_operand" "d")
3023 (match_operand:GPR 2 "register_operand" "d")))]
3024 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A || ISA_HAS_R6<D>DIV"
3026 if (TARGET_LOONGSON_2EF)
3027 return mips_output_division ("<d>mod<u>.g\t%0,%1,%2", operands);
3028 else if (TARGET_LOONGSON_3A)
3029 return mips_output_division ("gs<d>mod<u>\t%0,%1,%2", operands);
3031 return mips_output_division ("<d>mod<u>\t%0,%1,%2", operands);
3033 [(set_attr "type" "idiv3")
3034 (set_attr "mode" "<MODE>")])
3037 ;; ....................
3041 ;; ....................
3043 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
3044 ;; "*div[sd]f3" comment for details).
3046 (define_insn "sqrt<mode>2"
3047 [(set (match_operand:ANYF 0 "register_operand" "=f")
3048 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
3052 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
3054 return "sqrt.<fmt>\t%0,%1";
3056 [(set_attr "type" "fsqrt")
3057 (set_attr "mode" "<UNITMODE>")
3058 (set (attr "insn_count")
3059 (if_then_else (match_test "TARGET_FIX_SB1")
3063 (define_insn "*rsqrt<mode>a"
3064 [(set (match_operand:ANYF 0 "register_operand" "=f")
3065 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
3066 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
3067 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
3070 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
3072 return "rsqrt.<fmt>\t%0,%2";
3074 [(set_attr "type" "frsqrt")
3075 (set_attr "mode" "<UNITMODE>")
3076 (set (attr "insn_count")
3077 (if_then_else (match_test "TARGET_FIX_SB1")
3081 (define_insn "*rsqrt<mode>b"
3082 [(set (match_operand:ANYF 0 "register_operand" "=f")
3083 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
3084 (match_operand:ANYF 2 "register_operand" "f"))))]
3085 "ISA_HAS_FP_RECIP_RSQRT (<MODE>mode) && flag_unsafe_math_optimizations"
3088 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
3090 return "rsqrt.<fmt>\t%0,%2";
3092 [(set_attr "type" "frsqrt")
3093 (set_attr "mode" "<UNITMODE>")
3094 (set (attr "insn_count")
3095 (if_then_else (match_test "TARGET_FIX_SB1")
3100 ;; ....................
3104 ;; ....................
3106 ;; Do not use the integer abs macro instruction, since that signals an
3107 ;; exception on -2147483648 (sigh).
3109 ;; The "legacy" (as opposed to "2008") form of ABS.fmt is an arithmetic
3110 ;; instruction that treats all NaN inputs as invalid; it does not clear
3111 ;; their sign bit. We therefore can't use that form if the signs of
3114 (define_insn "abs<mode>2"
3115 [(set (match_operand:ANYF 0 "register_operand" "=f")
3116 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
3117 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)"
3119 [(set_attr "type" "fabs")
3120 (set_attr "mode" "<UNITMODE>")])
3123 ;; ...................
3125 ;; Count leading zeroes.
3127 ;; ...................
3130 (define_insn "clz<mode>2"
3131 [(set (match_operand:GPR 0 "register_operand" "=d")
3132 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
3135 [(set_attr "type" "clz")
3136 (set_attr "mode" "<MODE>")])
3139 ;; ...................
3141 ;; Count number of set bits.
3143 ;; ...................
3146 (define_insn "popcount<mode>2"
3147 [(set (match_operand:GPR 0 "register_operand" "=d")
3148 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
3151 [(set_attr "type" "pop")
3152 (set_attr "mode" "<MODE>")])
3154 ;; The POP instruction is special as it does not take into account the upper
3155 ;; 32bits and is documented that way.
3156 (define_insn "*popcountdi2_trunc"
3157 [(set (match_operand:SI 0 "register_operand" "=d")
3158 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))]
3159 "ISA_HAS_POP && TARGET_64BIT"
3161 [(set_attr "type" "pop")
3162 (set_attr "mode" "SI")])
3165 ;; ....................
3167 ;; NEGATION and ONE'S COMPLEMENT
3169 ;; ....................
3171 (define_insn "negsi2"
3172 [(set (match_operand:SI 0 "register_operand" "=d")
3173 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
3177 return "neg\t%0,%1";
3179 return "subu\t%0,%.,%1";
3181 [(set_attr "alu_type" "sub")
3182 (set_attr "mode" "SI")])
3184 (define_insn "negdi2"
3185 [(set (match_operand:DI 0 "register_operand" "=d")
3186 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
3187 "TARGET_64BIT && !TARGET_MIPS16"
3189 [(set_attr "alu_type" "sub")
3190 (set_attr "mode" "DI")])
3192 ;; The "legacy" (as opposed to "2008") form of NEG.fmt is an arithmetic
3193 ;; instruction that treats all NaN inputs as invalid; it does not flip
3194 ;; their sign bit. We therefore can't use that form if the signs of
3197 (define_insn "neg<mode>2"
3198 [(set (match_operand:ANYF 0 "register_operand" "=f")
3199 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
3200 "mips_abs == MIPS_IEEE_754_2008 || !HONOR_NANS (<MODE>mode)"
3202 [(set_attr "type" "fneg")
3203 (set_attr "mode" "<UNITMODE>")])
3205 (define_insn "one_cmpl<mode>2"
3206 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
3207 (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))]
3211 return "not\t%0,%1";
3213 return "nor\t%0,%.,%1";
3215 [(set_attr "alu_type" "not")
3216 (set_attr "compression" "micromips,*")
3217 (set_attr "mode" "<MODE>")])
3220 ;; ....................
3224 ;; ....................
3227 ;; Many of these instructions use trivial define_expands, because we
3228 ;; want to use a different set of constraints when TARGET_MIPS16.
3230 (define_expand "and<mode>3"
3231 [(set (match_operand:GPR 0 "register_operand")
3232 (and:GPR (match_operand:GPR 1 "register_operand")
3233 (match_operand:GPR 2 "and_reg_operand")))])
3235 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
3236 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
3237 ;; Note that this variant does not trigger for SI mode because we require
3238 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
3239 ;; sign-extended SImode value.
3241 ;; These are possible combinations for operand 1 and 2. The table
3242 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
3243 ;; 16=MIPS16, x=match, S=split):
3245 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
3251 ;; 0xffff_ffff x S x S x
3256 (define_insn "*and<mode>3"
3257 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d")
3258 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d")
3259 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))]
3260 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
3264 switch (which_alternative)
3267 operands[1] = gen_lowpart (QImode, operands[1]);
3268 return "lbu\t%0,%1";
3270 operands[1] = gen_lowpart (HImode, operands[1]);
3271 return "lhu\t%0,%1";
3273 operands[1] = gen_lowpart (SImode, operands[1]);
3274 return "lwu\t%0,%1";
3277 return "andi\t%0,%1,%x2";
3279 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
3280 operands[2] = GEN_INT (len);
3281 return "<d>ext\t%0,%1,0,%2";
3286 return "and\t%0,%1,%2";
3291 [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical")
3292 (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*")
3293 (set_attr "mode" "<MODE>")])
3295 (define_insn "*and<mode>3_mips16"
3296 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
3297 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0")
3298 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
3299 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
3301 switch (which_alternative)
3304 operands[1] = gen_lowpart (QImode, operands[1]);
3305 return "lbu\t%0,%1";
3307 operands[1] = gen_lowpart (HImode, operands[1]);
3308 return "lhu\t%0,%1";
3310 operands[1] = gen_lowpart (SImode, operands[1]);
3311 return "lwu\t%0,%1";
3315 return "and\t%0,%2";
3320 [(set_attr "move_type" "load,load,load,shift_shift,logical")
3321 (set_attr "mode" "<MODE>")])
3323 (define_expand "ior<mode>3"
3324 [(set (match_operand:GPR 0 "register_operand")
3325 (ior:GPR (match_operand:GPR 1 "register_operand")
3326 (match_operand:GPR 2 "uns_arith_operand")))]
3330 operands[2] = force_reg (<MODE>mode, operands[2]);
3333 (define_insn "*ior<mode>3"
3334 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3335 (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
3336 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
3342 [(set_attr "alu_type" "or")
3343 (set_attr "compression" "micromips,*,*")
3344 (set_attr "mode" "<MODE>")])
3346 (define_insn "*ior<mode>3_mips16"
3347 [(set (match_operand:GPR 0 "register_operand" "=d")
3348 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
3349 (match_operand:GPR 2 "register_operand" "d")))]
3352 [(set_attr "alu_type" "or")
3353 (set_attr "mode" "<MODE>")])
3355 (define_expand "xor<mode>3"
3356 [(set (match_operand:GPR 0 "register_operand")
3357 (xor:GPR (match_operand:GPR 1 "register_operand")
3358 (match_operand:GPR 2 "uns_arith_operand")))]
3362 (define_insn "*xor<mode>3"
3363 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3364 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
3365 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
3371 [(set_attr "alu_type" "xor")
3372 (set_attr "compression" "micromips,*,*")
3373 (set_attr "mode" "<MODE>")])
3375 (define_insn "*xor<mode>3_mips16"
3376 [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t")
3377 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d")
3378 (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))]
3385 [(set_attr "alu_type" "xor")
3386 (set_attr "mode" "<MODE>")
3387 (set_attr "extended_mips16" "no,no,yes,no")])
3389 (define_insn "*nor<mode>3"
3390 [(set (match_operand:GPR 0 "register_operand" "=d")
3391 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
3392 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
3395 [(set_attr "alu_type" "nor")
3396 (set_attr "mode" "<MODE>")])
3399 ;; ....................
3403 ;; ....................
3407 (define_insn "truncdfsf2"
3408 [(set (match_operand:SF 0 "register_operand" "=f")
3409 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3410 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3412 [(set_attr "type" "fcvt")
3413 (set_attr "cnv_mode" "D2S")
3414 (set_attr "mode" "SF")])
3416 ;; Integer truncation patterns. Truncating SImode values to smaller
3417 ;; modes is a no-op, as it is for most other GCC ports. Truncating
3418 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
3419 ;; need to make sure that the lower 32 bits are properly sign-extended
3420 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
3421 ;; smaller than SImode is equivalent to two separate truncations:
3424 ;; DI ---> HI == DI ---> SI ---> HI
3425 ;; DI ---> QI == DI ---> SI ---> QI
3427 ;; Step A needs a real instruction but step B does not.
3429 (define_insn "truncdi<mode>2"
3430 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
3431 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
3436 [(set_attr "move_type" "sll0,store")
3437 (set_attr "mode" "SI")])
3439 ;; Combiner patterns to optimize shift/truncate combinations.
3441 (define_insn "*ashr_trunc<mode>"
3442 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3444 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3445 (match_operand:DI 2 "const_arith_operand" ""))))]
3446 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3448 [(set_attr "type" "shift")
3449 (set_attr "mode" "<MODE>")])
3451 (define_insn "*lshr32_trunc<mode>"
3452 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3454 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3456 "TARGET_64BIT && !TARGET_MIPS16"
3458 [(set_attr "type" "shift")
3459 (set_attr "mode" "<MODE>")])
3461 ;; Logical shift by more than 32 results in proper SI values so truncation is
3462 ;; removed by the middle end. Note that a logical shift by 32 is handled by
3463 ;; the previous pattern.
3464 (define_insn "*<optab>_trunc<mode>_exts"
3465 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3467 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
3468 (match_operand:DI 2 "const_arith_operand" ""))))]
3469 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
3471 [(set_attr "type" "arith")
3472 (set_attr "mode" "<MODE>")])
3475 ;; ....................
3479 ;; ....................
3483 (define_expand "zero_extendsidi2"
3484 [(set (match_operand:DI 0 "register_operand")
3485 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
3488 (define_insn_and_split "*zero_extendsidi2"
3489 [(set (match_operand:DI 0 "register_operand" "=d,d")
3490 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3491 "TARGET_64BIT && !ISA_HAS_EXT_INS"
3495 "&& reload_completed && REG_P (operands[1])"
3497 (ashift:DI (match_dup 1) (const_int 32)))
3499 (lshiftrt:DI (match_dup 0) (const_int 32)))]
3500 { operands[1] = gen_lowpart (DImode, operands[1]); }
3501 [(set_attr "move_type" "shift_shift,load")
3502 (set_attr "mode" "DI")])
3504 (define_insn "*zero_extendsidi2_dext"
3505 [(set (match_operand:DI 0 "register_operand" "=d,d")
3506 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3507 "TARGET_64BIT && ISA_HAS_EXT_INS"
3511 [(set_attr "move_type" "arith,load")
3512 (set_attr "mode" "DI")])
3514 ;; See the comment before the *and<mode>3 pattern why this is generated by
3518 [(set (match_operand:DI 0 "register_operand")
3519 (and:DI (match_operand:DI 1 "register_operand")
3520 (const_int 4294967295)))]
3521 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
3523 (ashift:DI (match_dup 1) (const_int 32)))
3525 (lshiftrt:DI (match_dup 0) (const_int 32)))])
3527 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
3528 [(set (match_operand:GPR 0 "register_operand")
3529 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3532 if (TARGET_MIPS16 && !GENERATE_MIPS16E
3533 && !memory_operand (operands[1], <SHORT:MODE>mode))
3535 emit_insn (gen_and<GPR:mode>3 (operands[0],
3536 gen_lowpart (<GPR:MODE>mode, operands[1]),
3537 force_reg (<GPR:MODE>mode,
3538 GEN_INT (<SHORT:mask>))));
3543 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
3544 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3546 (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))]
3549 andi\t%0,%1,<SHORT:mask>
3550 andi\t%0,%1,<SHORT:mask>
3551 l<SHORT:size>u\t%0,%1"
3552 [(set_attr "move_type" "andi,andi,load")
3553 (set_attr "compression" "micromips,*,*")
3554 (set_attr "mode" "<GPR:MODE>")])
3556 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
3557 [(set (match_operand:GPR 0 "register_operand" "=d")
3558 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
3560 "ze<SHORT:size>\t%0"
3561 ;; This instruction is effectively a special encoding of ANDI.
3562 [(set_attr "move_type" "andi")
3563 (set_attr "mode" "<GPR:MODE>")])
3565 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
3566 [(set (match_operand:GPR 0 "register_operand" "=d")
3567 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
3569 "l<SHORT:size>u\t%0,%1"
3570 [(set_attr "move_type" "load")
3571 (set_attr "mode" "<GPR:MODE>")])
3573 (define_expand "zero_extendqihi2"
3574 [(set (match_operand:HI 0 "register_operand")
3575 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3578 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
3580 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
3586 (define_insn "*zero_extendqihi2"
3587 [(set (match_operand:HI 0 "register_operand" "=d,d")
3588 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3593 [(set_attr "move_type" "andi,load")
3594 (set_attr "mode" "HI")])
3596 (define_insn "*zero_extendqihi2_mips16"
3597 [(set (match_operand:HI 0 "register_operand" "=d")
3598 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3601 [(set_attr "move_type" "load")
3602 (set_attr "mode" "HI")])
3604 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3606 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
3607 [(set (match_operand:GPR 0 "register_operand" "=d")
3609 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3610 "TARGET_64BIT && !TARGET_MIPS16"
3612 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3613 return "andi\t%0,%1,%x2";
3615 [(set_attr "alu_type" "and")
3616 (set_attr "mode" "<GPR:MODE>")])
3618 (define_insn "*zero_extendhi_truncqi"
3619 [(set (match_operand:HI 0 "register_operand" "=d")
3621 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3622 "TARGET_64BIT && !TARGET_MIPS16"
3624 [(set_attr "alu_type" "and")
3625 (set_attr "mode" "HI")])
3628 ;; ....................
3632 ;; ....................
3635 ;; Those for integer source operand are ordered widest source type first.
3637 ;; When TARGET_64BIT, all SImode integer and accumulator registers
3638 ;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
3639 ;; and truncdisi2). We can therefore get rid of register->register
3640 ;; instructions if we constrain the source to be in the same register as
3643 ;; Only the pre-reload scheduler sees the type of the register alternatives;
3644 ;; we split them into nothing before the post-reload scheduler runs.
3645 ;; These alternatives therefore have type "move" in order to reflect
3646 ;; what happens if the two pre-reload operands cannot be tied, and are
3647 ;; instead allocated two separate GPRs. We don't distinguish between
3648 ;; the GPR and LO cases because we don't usually know during pre-reload
3649 ;; scheduling whether an operand will be LO or not.
3650 (define_insn_and_split "extendsidi2"
3651 [(set (match_operand:DI 0 "register_operand" "=d,l,d")
3652 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
3658 "&& reload_completed && register_operand (operands[1], VOIDmode)"
3661 emit_note (NOTE_INSN_DELETED);
3664 [(set_attr "move_type" "move,move,load")
3665 (set_attr "mode" "DI")])
3667 (define_expand "extend<SHORT:mode><GPR:mode>2"
3668 [(set (match_operand:GPR 0 "register_operand")
3669 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3672 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
3673 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3674 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3678 l<SHORT:size>\t%0,%1"
3679 [(set_attr "move_type" "signext,load")
3680 (set_attr "mode" "<GPR:MODE>")])
3682 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3683 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3685 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3686 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3689 l<SHORT:size>\t%0,%1"
3690 "&& reload_completed && REG_P (operands[1])"
3691 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3692 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3694 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3695 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3696 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3698 [(set_attr "move_type" "shift_shift,load")
3699 (set_attr "mode" "<GPR:MODE>")])
3701 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3702 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3704 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3707 se<SHORT:size>\t%0,%1
3708 l<SHORT:size>\t%0,%1"
3709 [(set_attr "move_type" "signext,load")
3710 (set_attr "mode" "<GPR:MODE>")])
3712 (define_expand "extendqihi2"
3713 [(set (match_operand:HI 0 "register_operand")
3714 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3717 (define_insn "*extendqihi2_mips16e"
3718 [(set (match_operand:HI 0 "register_operand" "=d,d")
3719 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3724 [(set_attr "move_type" "signext,load")
3725 (set_attr "mode" "SI")])
3727 (define_insn_and_split "*extendqihi2"
3728 [(set (match_operand:HI 0 "register_operand" "=d,d")
3730 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3731 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3735 "&& reload_completed && REG_P (operands[1])"
3736 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3737 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3739 operands[0] = gen_lowpart (SImode, operands[0]);
3740 operands[1] = gen_lowpart (SImode, operands[1]);
3741 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3742 - GET_MODE_BITSIZE (QImode));
3744 [(set_attr "move_type" "shift_shift,load")
3745 (set_attr "mode" "SI")])
3747 (define_insn "*extendqihi2_seb"
3748 [(set (match_operand:HI 0 "register_operand" "=d,d")
3750 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3755 [(set_attr "move_type" "signext,load")
3756 (set_attr "mode" "SI")])
3758 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3759 ;; use the shift/truncate patterns.
3761 (define_insn_and_split "*extenddi_truncate<mode>"
3762 [(set (match_operand:DI 0 "register_operand" "=d")
3764 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3765 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3767 "&& reload_completed"
3769 (ashift:DI (match_dup 1)
3772 (ashiftrt:DI (match_dup 2)
3775 operands[2] = gen_lowpart (DImode, operands[0]);
3776 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3778 [(set_attr "move_type" "shift_shift")
3779 (set_attr "mode" "DI")])
3781 (define_insn_and_split "*extendsi_truncate<mode>"
3782 [(set (match_operand:SI 0 "register_operand" "=d")
3784 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3785 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3787 "&& reload_completed"
3789 (ashift:DI (match_dup 1)
3792 (truncate:SI (ashiftrt:DI (match_dup 2)
3795 operands[2] = gen_lowpart (DImode, operands[0]);
3796 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3798 [(set_attr "move_type" "shift_shift")
3799 (set_attr "mode" "SI")])
3801 (define_insn_and_split "*extendhi_truncateqi"
3802 [(set (match_operand:HI 0 "register_operand" "=d")
3804 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3805 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3807 "&& reload_completed"
3809 (ashift:DI (match_dup 1)
3812 (truncate:HI (ashiftrt:DI (match_dup 2)
3815 operands[2] = gen_lowpart (DImode, operands[0]);
3817 [(set_attr "move_type" "shift_shift")
3818 (set_attr "mode" "SI")])
3820 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3821 [(set (match_operand:GPR 0 "register_operand" "=d")
3823 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3824 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3826 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3827 return "exts\t%0,%1,0,%m2";
3829 [(set_attr "type" "arith")
3830 (set_attr "mode" "<GPR:MODE>")])
3832 (define_insn "*extendhi_truncateqi_exts"
3833 [(set (match_operand:HI 0 "register_operand" "=d")
3835 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3836 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3838 [(set_attr "type" "arith")
3839 (set_attr "mode" "SI")])
3841 (define_insn "extendsfdf2"
3842 [(set (match_operand:DF 0 "register_operand" "=f")
3843 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3844 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3846 [(set_attr "type" "fcvt")
3847 (set_attr "cnv_mode" "S2D")
3848 (set_attr "mode" "DF")])
3851 ;; ....................
3855 ;; ....................
3857 (define_expand "fix_truncdfsi2"
3858 [(set (match_operand:SI 0 "register_operand")
3859 (fix:SI (match_operand:DF 1 "register_operand")))]
3860 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3862 if (!ISA_HAS_TRUNC_W)
3864 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3869 (define_insn "fix_truncdfsi2_insn"
3870 [(set (match_operand:SI 0 "register_operand" "=f")
3871 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3872 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3874 [(set_attr "type" "fcvt")
3875 (set_attr "mode" "DF")
3876 (set_attr "cnv_mode" "D2I")])
3878 (define_insn "fix_truncdfsi2_macro"
3879 [(set (match_operand:SI 0 "register_operand" "=f")
3880 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3881 (clobber (match_scratch:DF 2 "=d"))]
3882 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3884 if (mips_nomacro.nesting_level > 0)
3885 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3887 return "trunc.w.d %0,%1,%2";
3889 [(set_attr "type" "fcvt")
3890 (set_attr "mode" "DF")
3891 (set_attr "cnv_mode" "D2I")
3892 (set_attr "insn_count" "9")])
3894 (define_expand "fix_truncsfsi2"
3895 [(set (match_operand:SI 0 "register_operand")
3896 (fix:SI (match_operand:SF 1 "register_operand")))]
3899 if (!ISA_HAS_TRUNC_W)
3901 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3906 (define_insn "fix_truncsfsi2_insn"
3907 [(set (match_operand:SI 0 "register_operand" "=f")
3908 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3909 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3911 [(set_attr "type" "fcvt")
3912 (set_attr "mode" "SF")
3913 (set_attr "cnv_mode" "S2I")])
3915 (define_insn "fix_truncsfsi2_macro"
3916 [(set (match_operand:SI 0 "register_operand" "=f")
3917 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3918 (clobber (match_scratch:SF 2 "=d"))]
3919 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3921 if (mips_nomacro.nesting_level > 0)
3922 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3924 return "trunc.w.s %0,%1,%2";
3926 [(set_attr "type" "fcvt")
3927 (set_attr "mode" "SF")
3928 (set_attr "cnv_mode" "S2I")
3929 (set_attr "insn_count" "9")])
3932 (define_insn "fix_truncdfdi2"
3933 [(set (match_operand:DI 0 "register_operand" "=f")
3934 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3935 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3937 [(set_attr "type" "fcvt")
3938 (set_attr "mode" "DF")
3939 (set_attr "cnv_mode" "D2I")])
3942 (define_insn "fix_truncsfdi2"
3943 [(set (match_operand:DI 0 "register_operand" "=f")
3944 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3945 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3947 [(set_attr "type" "fcvt")
3948 (set_attr "mode" "SF")
3949 (set_attr "cnv_mode" "S2I")])
3952 (define_insn "floatsidf2"
3953 [(set (match_operand:DF 0 "register_operand" "=f")
3954 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3955 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3957 [(set_attr "type" "fcvt")
3958 (set_attr "mode" "DF")
3959 (set_attr "cnv_mode" "I2D")])
3962 (define_insn "floatdidf2"
3963 [(set (match_operand:DF 0 "register_operand" "=f")
3964 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3965 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3967 [(set_attr "type" "fcvt")
3968 (set_attr "mode" "DF")
3969 (set_attr "cnv_mode" "I2D")])
3972 (define_insn "floatsisf2"
3973 [(set (match_operand:SF 0 "register_operand" "=f")
3974 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3977 [(set_attr "type" "fcvt")
3978 (set_attr "mode" "SF")
3979 (set_attr "cnv_mode" "I2S")])
3982 (define_insn "floatdisf2"
3983 [(set (match_operand:SF 0 "register_operand" "=f")
3984 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3985 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3987 [(set_attr "type" "fcvt")
3988 (set_attr "mode" "SF")
3989 (set_attr "cnv_mode" "I2S")])
3992 (define_expand "fixuns_truncdfsi2"
3993 [(set (match_operand:SI 0 "register_operand")
3994 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3995 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3997 rtx reg1 = gen_reg_rtx (DFmode);
3998 rtx reg2 = gen_reg_rtx (DFmode);
3999 rtx reg3 = gen_reg_rtx (SImode);
4000 rtx_code_label *label1 = gen_label_rtx ();
4001 rtx_code_label *label2 = gen_label_rtx ();
4003 REAL_VALUE_TYPE offset;
4005 real_2expN (&offset, 31, DFmode);
4007 if (reg1) /* Turn off complaints about unreached code. */
4009 mips_emit_move (reg1, const_double_from_real_value (offset, DFmode));
4010 do_pending_stack_adjust ();
4012 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4013 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
4015 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
4016 emit_jump_insn (gen_rtx_SET (pc_rtx,
4017 gen_rtx_LABEL_REF (VOIDmode, label2)));
4020 emit_label (label1);
4021 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4022 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
4023 (BITMASK_HIGH, SImode)));
4025 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
4026 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4028 emit_label (label2);
4030 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4031 fields, and can't be used for REG_NOTES anyway). */
4032 emit_use (stack_pointer_rtx);
4038 (define_expand "fixuns_truncdfdi2"
4039 [(set (match_operand:DI 0 "register_operand")
4040 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
4041 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4043 rtx reg1 = gen_reg_rtx (DFmode);
4044 rtx reg2 = gen_reg_rtx (DFmode);
4045 rtx reg3 = gen_reg_rtx (DImode);
4046 rtx_code_label *label1 = gen_label_rtx ();
4047 rtx_code_label *label2 = gen_label_rtx ();
4049 REAL_VALUE_TYPE offset;
4051 real_2expN (&offset, 63, DFmode);
4053 mips_emit_move (reg1, const_double_from_real_value (offset, DFmode));
4054 do_pending_stack_adjust ();
4056 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4057 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
4059 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
4060 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4063 emit_label (label1);
4064 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4065 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
4066 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4068 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
4069 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4071 emit_label (label2);
4073 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4074 fields, and can't be used for REG_NOTES anyway). */
4075 emit_use (stack_pointer_rtx);
4080 (define_expand "fixuns_truncsfsi2"
4081 [(set (match_operand:SI 0 "register_operand")
4082 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
4085 rtx reg1 = gen_reg_rtx (SFmode);
4086 rtx reg2 = gen_reg_rtx (SFmode);
4087 rtx reg3 = gen_reg_rtx (SImode);
4088 rtx_code_label *label1 = gen_label_rtx ();
4089 rtx_code_label *label2 = gen_label_rtx ();
4091 REAL_VALUE_TYPE offset;
4093 real_2expN (&offset, 31, SFmode);
4095 mips_emit_move (reg1, const_double_from_real_value (offset, SFmode));
4096 do_pending_stack_adjust ();
4098 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4099 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
4101 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
4102 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4105 emit_label (label1);
4106 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4107 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
4108 (BITMASK_HIGH, SImode)));
4110 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
4111 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4113 emit_label (label2);
4115 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4116 fields, and can't be used for REG_NOTES anyway). */
4117 emit_use (stack_pointer_rtx);
4122 (define_expand "fixuns_truncsfdi2"
4123 [(set (match_operand:DI 0 "register_operand")
4124 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
4125 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4127 rtx reg1 = gen_reg_rtx (SFmode);
4128 rtx reg2 = gen_reg_rtx (SFmode);
4129 rtx reg3 = gen_reg_rtx (DImode);
4130 rtx_code_label *label1 = gen_label_rtx ();
4131 rtx_code_label *label2 = gen_label_rtx ();
4133 REAL_VALUE_TYPE offset;
4135 real_2expN (&offset, 63, SFmode);
4137 mips_emit_move (reg1, const_double_from_real_value (offset, SFmode));
4138 do_pending_stack_adjust ();
4140 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
4141 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
4143 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
4144 emit_jump_insn (gen_rtx_SET (pc_rtx, gen_rtx_LABEL_REF (VOIDmode, label2)));
4147 emit_label (label1);
4148 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4149 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
4150 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4152 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
4153 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4155 emit_label (label2);
4157 /* Allow REG_NOTES to be set on last insn (labels don't have enough
4158 fields, and can't be used for REG_NOTES anyway). */
4159 emit_use (stack_pointer_rtx);
4164 ;; ....................
4168 ;; ....................
4170 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
4172 (define_expand "extvmisalign<mode>"
4173 [(set (match_operand:GPR 0 "register_operand")
4174 (sign_extract:GPR (match_operand:BLK 1 "memory_operand")
4175 (match_operand 2 "const_int_operand")
4176 (match_operand 3 "const_int_operand")))]
4179 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
4180 INTVAL (operands[2]),
4181 INTVAL (operands[3]),
4182 /*unsigned=*/ false))
4188 (define_expand "extv<mode>"
4189 [(set (match_operand:GPR 0 "register_operand")
4190 (sign_extract:GPR (match_operand:GPR 1 "register_operand")
4191 (match_operand 2 "const_int_operand")
4192 (match_operand 3 "const_int_operand")))]
4195 if (UINTVAL (operands[2]) > 32)
4199 (define_insn "*extv<mode>"
4200 [(set (match_operand:GPR 0 "register_operand" "=d")
4201 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
4202 (match_operand 2 "const_int_operand" "")
4203 (match_operand 3 "const_int_operand" "")))]
4204 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
4205 "exts\t%0,%1,%3,%m2"
4206 [(set_attr "type" "arith")
4207 (set_attr "mode" "<MODE>")])
4209 (define_expand "extzvmisalign<mode>"
4210 [(set (match_operand:GPR 0 "register_operand")
4211 (zero_extract:GPR (match_operand:BLK 1 "memory_operand")
4212 (match_operand 2 "const_int_operand")
4213 (match_operand 3 "const_int_operand")))]
4216 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
4217 INTVAL (operands[2]),
4218 INTVAL (operands[3]),
4219 /*unsigned=*/ true))
4225 (define_expand "extzv<mode>"
4226 [(set (match_operand:GPR 0 "register_operand")
4227 (zero_extract:GPR (match_operand:GPR 1 "register_operand")
4228 (match_operand 2 "const_int_operand")
4229 (match_operand 3 "const_int_operand")))]
4232 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
4233 INTVAL (operands[3])))
4237 (define_insn "*extzv<mode>"
4238 [(set (match_operand:GPR 0 "register_operand" "=d")
4239 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
4240 (match_operand 2 "const_int_operand" "")
4241 (match_operand 3 "const_int_operand" "")))]
4242 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
4243 INTVAL (operands[3]))"
4244 "<d>ext\t%0,%1,%3,%2"
4245 [(set_attr "type" "arith")
4246 (set_attr "mode" "<MODE>")])
4248 (define_insn "*extzv_truncsi_exts"
4249 [(set (match_operand:SI 0 "register_operand" "=d")
4251 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
4252 (match_operand 2 "const_int_operand" "")
4253 (match_operand 3 "const_int_operand" ""))))]
4254 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
4256 [(set_attr "type" "arith")
4257 (set_attr "mode" "SI")])
4260 (define_expand "insvmisalign<mode>"
4261 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")
4262 (match_operand 1 "const_int_operand")
4263 (match_operand 2 "const_int_operand"))
4264 (match_operand:GPR 3 "reg_or_0_operand"))]
4267 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
4268 INTVAL (operands[1]),
4269 INTVAL (operands[2])))
4275 (define_expand "insv<mode>"
4276 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand")
4277 (match_operand 1 "const_int_operand")
4278 (match_operand 2 "const_int_operand"))
4279 (match_operand:GPR 3 "reg_or_0_operand"))]
4282 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
4283 INTVAL (operands[2])))
4287 (define_insn "*insv<mode>"
4288 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
4289 (match_operand:SI 1 "const_int_operand" "")
4290 (match_operand:SI 2 "const_int_operand" ""))
4291 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
4292 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
4293 INTVAL (operands[2]))"
4294 "<d>ins\t%0,%z3,%2,%1"
4295 [(set_attr "type" "arith")
4296 (set_attr "mode" "<MODE>")])
4298 ;; Combiner pattern for cins (clear and insert bit field). We can
4299 ;; implement mask-and-shift-left operation with this. Note that if
4300 ;; the upper bit of the mask is set in an SImode operation, the mask
4301 ;; itself will be sign-extended. mask_low_and_shift_len will
4302 ;; therefore be greater than our threshold of 32.
4304 (define_insn "*cins<mode>"
4305 [(set (match_operand:GPR 0 "register_operand" "=d")
4307 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
4308 (match_operand:GPR 2 "const_int_operand" ""))
4309 (match_operand:GPR 3 "const_int_operand" "")))]
4311 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
4314 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
4315 return "cins\t%0,%1,%2,%m3";
4317 [(set_attr "type" "shift")
4318 (set_attr "mode" "<MODE>")])
4320 ;; Unaligned word moves generated by the bit field patterns.
4322 ;; As far as the rtl is concerned, both the left-part and right-part
4323 ;; instructions can access the whole field. However, the real operand
4324 ;; refers to just the first or the last byte (depending on endianness).
4325 ;; We therefore use two memory operands to each instruction, one to
4326 ;; describe the rtl effect and one to use in the assembly output.
4328 ;; Operands 0 and 1 are the rtl-level target and source respectively.
4329 ;; This allows us to use the standard length calculations for the "load"
4330 ;; and "store" type attributes.
4332 (define_insn "mov_<load>l"
4333 [(set (match_operand:GPR 0 "register_operand" "=d")
4334 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
4335 (match_operand:QI 2 "memory_operand" "ZC")]
4337 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
4339 [(set_attr "move_type" "load")
4340 (set_attr "mode" "<MODE>")])
4342 (define_insn "mov_<load>r"
4343 [(set (match_operand:GPR 0 "register_operand" "=d")
4344 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
4345 (match_operand:QI 2 "memory_operand" "ZC")
4346 (match_operand:GPR 3 "register_operand" "0")]
4347 UNSPEC_LOAD_RIGHT))]
4348 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
4350 [(set_attr "move_type" "load")
4351 (set_attr "mode" "<MODE>")])
4353 (define_insn "mov_<store>l"
4354 [(set (match_operand:BLK 0 "memory_operand" "=m")
4355 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4356 (match_operand:QI 2 "memory_operand" "ZC")]
4357 UNSPEC_STORE_LEFT))]
4358 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
4360 [(set_attr "move_type" "store")
4361 (set_attr "mode" "<MODE>")])
4363 (define_insn "mov_<store>r"
4364 [(set (match_operand:BLK 0 "memory_operand" "+m")
4365 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4366 (match_operand:QI 2 "memory_operand" "ZC")
4368 UNSPEC_STORE_RIGHT))]
4369 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
4371 [(set_attr "move_type" "store")
4372 (set_attr "mode" "<MODE>")])
4374 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
4375 ;; The required value is:
4377 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
4379 ;; which translates to:
4381 ;; lui op0,%highest(op1)
4382 ;; daddiu op0,op0,%higher(op1)
4384 ;; daddiu op0,op0,%hi(op1)
4387 ;; The split is deferred until after flow2 to allow the peephole2 below
4389 (define_insn_and_split "*lea_high64"
4390 [(set (match_operand:DI 0 "register_operand" "=d")
4391 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
4392 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4394 "&& epilogue_completed"
4395 [(set (match_dup 0) (high:DI (match_dup 2)))
4396 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
4397 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
4398 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4399 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
4401 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4402 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
4404 [(set_attr "insn_count" "5")])
4406 ;; Use a scratch register to reduce the latency of the above pattern
4407 ;; on superscalar machines. The optimized sequence is:
4409 ;; lui op1,%highest(op2)
4411 ;; daddiu op1,op1,%higher(op2)
4413 ;; daddu op1,op1,op0
4415 [(set (match_operand:DI 1 "d_operand")
4416 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
4417 (match_scratch:DI 0 "d")]
4418 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4419 [(set (match_dup 1) (high:DI (match_dup 3)))
4420 (set (match_dup 0) (high:DI (match_dup 4)))
4421 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
4422 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
4423 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
4425 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
4426 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
4429 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
4430 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
4431 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
4432 ;; used once. We can then use the sequence:
4434 ;; lui op0,%highest(op1)
4436 ;; daddiu op0,op0,%higher(op1)
4437 ;; daddiu op2,op2,%lo(op1)
4439 ;; daddu op0,op0,op2
4441 ;; which takes 4 cycles on most superscalar targets.
4442 (define_insn_and_split "*lea64"
4443 [(set (match_operand:DI 0 "register_operand" "=d")
4444 (match_operand:DI 1 "absolute_symbolic_operand" ""))
4445 (clobber (match_scratch:DI 2 "=&d"))]
4447 && TARGET_EXPLICIT_RELOCS
4448 && ABI_HAS_64BIT_SYMBOLS
4449 && cse_not_expected"
4451 "&& reload_completed"
4452 [(set (match_dup 0) (high:DI (match_dup 3)))
4453 (set (match_dup 2) (high:DI (match_dup 4)))
4454 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4455 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
4456 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
4457 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
4459 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4460 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
4462 [(set_attr "insn_count" "6")])
4464 ;; Split HIGHs into:
4469 ;; on MIPS16 targets.
4471 [(set (match_operand:P 0 "d_operand")
4472 (high:P (match_operand:P 1 "symbolic_operand_with_high")))]
4473 "TARGET_MIPS16 && reload_completed"
4474 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH))
4475 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))])
4477 (define_insn "*unshifted_high"
4478 [(set (match_operand:P 0 "d_operand" "=d")
4479 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")]
4480 UNSPEC_UNSHIFTED_HIGH))]
4483 [(set_attr "extended_mips16" "yes")])
4485 ;; Insns to fetch a symbol from a big GOT.
4487 (define_insn_and_split "*xgot_hi<mode>"
4488 [(set (match_operand:P 0 "register_operand" "=d")
4489 (high:P (match_operand:P 1 "got_disp_operand" "")))]
4490 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4492 "&& reload_completed"
4493 [(set (match_dup 0) (high:P (match_dup 2)))
4494 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
4496 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
4497 operands[3] = pic_offset_table_rtx;
4499 [(set_attr "got" "xgot_high")
4500 (set_attr "mode" "<MODE>")])
4502 (define_insn_and_split "*xgot_lo<mode>"
4503 [(set (match_operand:P 0 "register_operand" "=d")
4504 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4505 (match_operand:P 2 "got_disp_operand" "")))]
4506 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4508 "&& reload_completed"
4510 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
4511 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
4512 [(set_attr "got" "load")
4513 (set_attr "mode" "<MODE>")])
4515 ;; Insns to fetch a symbol from a normal GOT.
4517 (define_insn_and_split "*got_disp<mode>"
4518 [(set (match_operand:P 0 "register_operand" "=d")
4519 (match_operand:P 1 "got_disp_operand" ""))]
4520 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
4522 "&& reload_completed"
4523 [(set (match_dup 0) (match_dup 2))]
4524 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
4525 [(set_attr "got" "load")
4526 (set_attr "mode" "<MODE>")])
4528 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
4530 (define_insn_and_split "*got_page<mode>"
4531 [(set (match_operand:P 0 "register_operand" "=d")
4532 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
4533 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
4535 "&& reload_completed"
4536 [(set (match_dup 0) (match_dup 2))]
4537 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
4538 [(set_attr "got" "load")
4539 (set_attr "mode" "<MODE>")])
4541 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
4542 (define_expand "unspec_got_<mode>"
4543 [(unspec:P [(match_operand:P 0)
4544 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
4546 ;; Lower-level instructions for loading an address from the GOT.
4547 ;; We could use MEMs, but an unspec gives more optimization
4550 (define_insn "load_got<mode>"
4551 [(set (match_operand:P 0 "register_operand" "=d")
4552 (unspec:P [(match_operand:P 1 "register_operand" "d")
4553 (match_operand:P 2 "immediate_operand" "")]
4556 "<load>\t%0,%R2(%1)"
4557 [(set_attr "got" "load")
4558 (set_attr "mode" "<MODE>")])
4560 ;; Instructions for adding the low 16 bits of an address to a register.
4561 ;; Operand 2 is the address: mips_print_operand works out which relocation
4562 ;; should be applied.
4564 (define_insn "*low<mode>"
4565 [(set (match_operand:P 0 "register_operand" "=d")
4566 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4567 (match_operand:P 2 "immediate_operand" "")))]
4569 "<d>addiu\t%0,%1,%R2"
4570 [(set_attr "alu_type" "add")
4571 (set_attr "mode" "<MODE>")])
4573 (define_insn "*low<mode>_mips16"
4574 [(set (match_operand:P 0 "register_operand" "=d")
4575 (lo_sum:P (match_operand:P 1 "register_operand" "0")
4576 (match_operand:P 2 "immediate_operand" "")))]
4579 [(set_attr "alu_type" "add")
4580 (set_attr "mode" "<MODE>")
4581 (set_attr "extended_mips16" "yes")])
4583 ;; Expose MIPS16 uses of the global pointer after reload if the function
4584 ;; is responsible for setting up the register itself.
4586 [(set (match_operand:GPR 0 "d_operand")
4587 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
4588 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
4589 [(set (match_dup 0) (match_dup 1))]
4590 { operands[1] = pic_offset_table_rtx; })
4592 ;; Allow combine to split complex const_int load sequences, using operand 2
4593 ;; to store the intermediate results. See move_operand for details.
4595 [(set (match_operand:GPR 0 "register_operand")
4596 (match_operand:GPR 1 "splittable_const_int_operand"))
4597 (clobber (match_operand:GPR 2 "register_operand"))]
4601 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
4605 ;; Likewise, for symbolic operands.
4607 [(set (match_operand:P 0 "register_operand")
4608 (match_operand:P 1))
4609 (clobber (match_operand:P 2 "register_operand"))]
4610 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
4611 [(set (match_dup 0) (match_dup 3))]
4613 mips_split_symbol (operands[2], operands[1],
4614 MAX_MACHINE_MODE, &operands[3]);
4617 ;; 64-bit integer moves
4619 ;; Unlike most other insns, the move insns can't be split with
4620 ;; different predicates, because register spilling and other parts of
4621 ;; the compiler, have memoized the insn number already.
4623 (define_expand "movdi"
4624 [(set (match_operand:DI 0 "")
4625 (match_operand:DI 1 ""))]
4628 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4632 ;; For mips16, we need a special case to handle storing $31 into
4633 ;; memory, since we don't have a constraint to match $31. This
4634 ;; instruction can be generated by save_restore_insns.
4636 (define_insn "*mov<mode>_ra"
4637 [(set (match_operand:GPR 0 "stack_operand" "=m")
4638 (reg:GPR RETURN_ADDR_REGNUM))]
4641 [(set_attr "move_type" "store")
4642 (set_attr "mode" "<MODE>")])
4644 (define_insn "*movdi_32bit"
4645 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
4646 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
4647 "!TARGET_64BIT && !TARGET_MIPS16
4648 && (register_operand (operands[0], DImode)
4649 || reg_or_0_operand (operands[1], DImode))"
4650 { return mips_output_move (operands[0], operands[1]); }
4651 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
4653 (if_then_else (eq_attr "move_type" "imul")
4655 (const_string "DI")))])
4657 (define_insn "*movdi_32bit_mips16"
4658 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4659 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
4660 "!TARGET_64BIT && TARGET_MIPS16
4661 && (register_operand (operands[0], DImode)
4662 || register_operand (operands[1], DImode))"
4663 { return mips_output_move (operands[0], operands[1]); }
4664 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4665 (set_attr "mode" "DI")])
4667 (define_insn "*movdi_64bit"
4668 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
4669 (match_operand:DI 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4670 "TARGET_64BIT && !TARGET_MIPS16
4671 && (register_operand (operands[0], DImode)
4672 || reg_or_0_operand (operands[1], DImode))"
4673 { return mips_output_move (operands[0], operands[1]); }
4674 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore")
4675 (set_attr "mode" "DI")])
4677 (define_insn "*movdi_64bit_mips16"
4678 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4679 (match_operand:DI 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4680 "TARGET_64BIT && TARGET_MIPS16
4681 && (register_operand (operands[0], DImode)
4682 || register_operand (operands[1], DImode))"
4683 { return mips_output_move (operands[0], operands[1]); }
4684 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4685 (set_attr "mode" "DI")])
4687 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4688 ;; when the original load is a 4 byte instruction but the add and the
4689 ;; load are 2 2 byte instructions.
4692 [(set (match_operand:DI 0 "d_operand")
4693 (mem:DI (plus:DI (match_dup 0)
4694 (match_operand:DI 1 "const_int_operand"))))]
4695 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4696 && !TARGET_DEBUG_D_MODE
4697 && ((INTVAL (operands[1]) < 0
4698 && INTVAL (operands[1]) >= -0x10)
4699 || (INTVAL (operands[1]) >= 32 * 8
4700 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4701 || (INTVAL (operands[1]) >= 0
4702 && INTVAL (operands[1]) < 32 * 8
4703 && (INTVAL (operands[1]) & 7) != 0))"
4704 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4705 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4707 HOST_WIDE_INT val = INTVAL (operands[1]);
4710 operands[2] = const0_rtx;
4711 else if (val >= 32 * 8)
4715 operands[1] = GEN_INT (0x8 + off);
4716 operands[2] = GEN_INT (val - off - 0x8);
4722 operands[1] = GEN_INT (off);
4723 operands[2] = GEN_INT (val - off);
4727 ;; 32-bit Integer moves
4729 ;; Unlike most other insns, the move insns can't be split with
4730 ;; different predicates, because register spilling and other parts of
4731 ;; the compiler, have memoized the insn number already.
4733 (define_expand "mov<mode>"
4734 [(set (match_operand:IMOVE32 0 "")
4735 (match_operand:IMOVE32 1 ""))]
4738 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4742 ;; The difference between these two is whether or not ints are allowed
4743 ;; in FP registers (off by default, use -mdebugh to enable).
4745 (define_insn "*mov<mode>_internal"
4746 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4747 (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!kbJ,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4749 && (register_operand (operands[0], <MODE>mode)
4750 || reg_or_0_operand (operands[1], <MODE>mode))"
4751 { return mips_output_move (operands[0], operands[1]); }
4752 [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore")
4753 (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*")
4754 (set_attr "mode" "SI")])
4756 (define_insn "*mov<mode>_mips16"
4757 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4758 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4760 && (register_operand (operands[0], <MODE>mode)
4761 || register_operand (operands[1], <MODE>mode))"
4762 { return mips_output_move (operands[0], operands[1]); }
4763 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4764 (set_attr "mode" "SI")])
4766 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4767 ;; when the original load is a 4 byte instruction but the add and the
4768 ;; load are 2 2 byte instructions.
4771 [(set (match_operand:SI 0 "d_operand")
4772 (mem:SI (plus:SI (match_dup 0)
4773 (match_operand:SI 1 "const_int_operand"))))]
4774 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4775 && ((INTVAL (operands[1]) < 0
4776 && INTVAL (operands[1]) >= -0x80)
4777 || (INTVAL (operands[1]) >= 32 * 4
4778 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4779 || (INTVAL (operands[1]) >= 0
4780 && INTVAL (operands[1]) < 32 * 4
4781 && (INTVAL (operands[1]) & 3) != 0))"
4782 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4783 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4785 HOST_WIDE_INT val = INTVAL (operands[1]);
4788 operands[2] = const0_rtx;
4789 else if (val >= 32 * 4)
4793 operands[1] = GEN_INT (0x7c + off);
4794 operands[2] = GEN_INT (val - off - 0x7c);
4800 operands[1] = GEN_INT (off);
4801 operands[2] = GEN_INT (val - off);
4805 ;; On the mips16, we can split a load of certain constants into a load
4806 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4810 [(set (match_operand:SI 0 "d_operand")
4811 (match_operand:SI 1 "const_int_operand"))]
4812 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4813 && INTVAL (operands[1]) >= 0x100
4814 && INTVAL (operands[1]) <= 0xff + 0x7f"
4815 [(set (match_dup 0) (match_dup 1))
4816 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4818 int val = INTVAL (operands[1]);
4820 operands[1] = GEN_INT (0xff);
4821 operands[2] = GEN_INT (val - 0xff);
4824 ;; MIPS4 supports loading and storing a floating point register from
4825 ;; the sum of two general registers. We use two versions for each of
4826 ;; these four instructions: one where the two general registers are
4827 ;; SImode, and one where they are DImode. This is because general
4828 ;; registers will be in SImode when they hold 32-bit values, but,
4829 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4830 ;; instructions will still work correctly.
4832 ;; ??? Perhaps it would be better to support these instructions by
4833 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4834 ;; these instructions can only be used to load and store floating
4835 ;; point registers, that would probably cause trouble in reload.
4837 (define_insn "*<ANYF:loadx>_<P:mode>"
4838 [(set (match_operand:ANYF 0 "register_operand" "=f")
4839 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4840 (match_operand:P 2 "register_operand" "d"))))]
4842 "<ANYF:loadx>\t%0,%1(%2)"
4843 [(set_attr "type" "fpidxload")
4844 (set_attr "mode" "<ANYF:UNITMODE>")])
4846 (define_insn "*<ANYF:storex>_<P:mode>"
4847 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4848 (match_operand:P 2 "register_operand" "d")))
4849 (match_operand:ANYF 0 "register_operand" "f"))]
4851 "<ANYF:storex>\t%0,%1(%2)"
4852 [(set_attr "type" "fpidxstore")
4853 (set_attr "mode" "<ANYF:UNITMODE>")])
4855 ;; Scaled indexed address load.
4856 ;; Per md.texi, we only need to look for a pattern with multiply in the
4857 ;; address expression, not shift.
4859 (define_insn "*lwxs"
4860 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4862 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4864 (match_operand:P 2 "register_operand" "d"))))]
4867 [(set_attr "type" "load")
4868 (set_attr "mode" "SI")])
4870 ;; 16-bit Integer moves
4872 ;; Unlike most other insns, the move insns can't be split with
4873 ;; different predicates, because register spilling and other parts of
4874 ;; the compiler, have memoized the insn number already.
4875 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4877 (define_expand "movhi"
4878 [(set (match_operand:HI 0 "")
4879 (match_operand:HI 1 ""))]
4882 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4886 (define_insn "*movhi_internal"
4887 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d")
4888 (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!kbJ,dJ,*d*J,*a"))]
4890 && (register_operand (operands[0], HImode)
4891 || reg_or_0_operand (operands[1], HImode))"
4892 { return mips_output_move (operands[0], operands[1]); }
4893 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4894 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4895 (set_attr "mode" "HI")])
4897 (define_insn "*movhi_mips16"
4898 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4899 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4901 && (register_operand (operands[0], HImode)
4902 || register_operand (operands[1], HImode))"
4903 { return mips_output_move (operands[0], operands[1]); }
4904 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4905 (set_attr "mode" "HI")])
4907 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4908 ;; when the original load is a 4 byte instruction but the add and the
4909 ;; load are 2 2 byte instructions.
4912 [(set (match_operand:HI 0 "d_operand")
4913 (mem:HI (plus:SI (match_dup 0)
4914 (match_operand:SI 1 "const_int_operand"))))]
4915 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4916 && ((INTVAL (operands[1]) < 0
4917 && INTVAL (operands[1]) >= -0x80)
4918 || (INTVAL (operands[1]) >= 32 * 2
4919 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4920 || (INTVAL (operands[1]) >= 0
4921 && INTVAL (operands[1]) < 32 * 2
4922 && (INTVAL (operands[1]) & 1) != 0))"
4923 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4924 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4926 HOST_WIDE_INT val = INTVAL (operands[1]);
4929 operands[2] = const0_rtx;
4930 else if (val >= 32 * 2)
4934 operands[1] = GEN_INT (0x7e + off);
4935 operands[2] = GEN_INT (val - off - 0x7e);
4941 operands[1] = GEN_INT (off);
4942 operands[2] = GEN_INT (val - off);
4946 ;; 8-bit Integer moves
4948 ;; Unlike most other insns, the move insns can't be split with
4949 ;; different predicates, because register spilling and other parts of
4950 ;; the compiler, have memoized the insn number already.
4951 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4953 (define_expand "movqi"
4954 [(set (match_operand:QI 0 "")
4955 (match_operand:QI 1 ""))]
4958 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4962 (define_insn "*movqi_internal"
4963 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d")
4964 (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!kbJ,dJ,*d*J,*a"))]
4966 && (register_operand (operands[0], QImode)
4967 || reg_or_0_operand (operands[1], QImode))"
4968 { return mips_output_move (operands[0], operands[1]); }
4969 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4970 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4971 (set_attr "mode" "QI")])
4973 (define_insn "*movqi_mips16"
4974 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4975 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4977 && (register_operand (operands[0], QImode)
4978 || register_operand (operands[1], QImode))"
4979 { return mips_output_move (operands[0], operands[1]); }
4980 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4981 (set_attr "mode" "QI")])
4983 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4984 ;; when the original load is a 4 byte instruction but the add and the
4985 ;; load are 2 2 byte instructions.
4988 [(set (match_operand:QI 0 "d_operand")
4989 (mem:QI (plus:SI (match_dup 0)
4990 (match_operand:SI 1 "const_int_operand"))))]
4991 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4992 && ((INTVAL (operands[1]) < 0
4993 && INTVAL (operands[1]) >= -0x80)
4994 || (INTVAL (operands[1]) >= 32
4995 && INTVAL (operands[1]) <= 31 + 0x7f))"
4996 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4997 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4999 HOST_WIDE_INT val = INTVAL (operands[1]);
5002 operands[2] = const0_rtx;
5005 operands[1] = GEN_INT (0x7f);
5006 operands[2] = GEN_INT (val - 0x7f);
5010 ;; 32-bit floating point moves
5012 (define_expand "movsf"
5013 [(set (match_operand:SF 0 "")
5014 (match_operand:SF 1 ""))]
5017 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
5021 (define_insn "movccf"
5022 [(set (match_operand:CCF 0 "nonimmediate_operand" "=f,f,m")
5023 (match_operand:CCF 1 "nonimmediate_operand" "f,m,f"))]
5025 { return mips_output_move (operands[0], operands[1]); }
5026 [(set_attr "move_type" "fmove,fpload,fpstore")])
5028 (define_insn "*movsf_hardfloat"
5029 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
5030 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
5032 && (register_operand (operands[0], SFmode)
5033 || reg_or_0_operand (operands[1], SFmode))"
5034 { return mips_output_move (operands[0], operands[1]); }
5035 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
5036 (set_attr "mode" "SF")])
5038 (define_insn "*movsf_softfloat"
5039 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
5040 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
5041 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
5042 && (register_operand (operands[0], SFmode)
5043 || reg_or_0_operand (operands[1], SFmode))"
5044 { return mips_output_move (operands[0], operands[1]); }
5045 [(set_attr "move_type" "move,load,store")
5046 (set_attr "mode" "SF")])
5048 (define_insn "*movsf_mips16"
5049 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
5050 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
5052 && (register_operand (operands[0], SFmode)
5053 || register_operand (operands[1], SFmode))"
5054 { return mips_output_move (operands[0], operands[1]); }
5055 [(set_attr "move_type" "move,move,move,load,store")
5056 (set_attr "mode" "SF")])
5058 ;; 64-bit floating point moves
5060 (define_expand "movdf"
5061 [(set (match_operand:DF 0 "")
5062 (match_operand:DF 1 ""))]
5065 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
5069 (define_insn "*movdf_hardfloat"
5070 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
5071 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
5072 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
5073 && (register_operand (operands[0], DFmode)
5074 || reg_or_0_operand (operands[1], DFmode))"
5075 { return mips_output_move (operands[0], operands[1]); }
5076 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
5077 (set_attr "mode" "DF")])
5079 (define_insn "*movdf_softfloat"
5080 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
5081 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
5082 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
5083 && (register_operand (operands[0], DFmode)
5084 || reg_or_0_operand (operands[1], DFmode))"
5085 { return mips_output_move (operands[0], operands[1]); }
5086 [(set_attr "move_type" "move,load,store")
5087 (set_attr "mode" "DF")])
5089 (define_insn "*movdf_mips16"
5090 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
5091 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
5093 && (register_operand (operands[0], DFmode)
5094 || register_operand (operands[1], DFmode))"
5095 { return mips_output_move (operands[0], operands[1]); }
5096 [(set_attr "move_type" "move,move,move,load,store")
5097 (set_attr "mode" "DF")])
5099 ;; 128-bit integer moves
5101 (define_expand "movti"
5102 [(set (match_operand:TI 0)
5103 (match_operand:TI 1))]
5106 if (mips_legitimize_move (TImode, operands[0], operands[1]))
5110 (define_insn "*movti"
5111 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d")
5112 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))]
5115 && (register_operand (operands[0], TImode)
5116 || reg_or_0_operand (operands[1], TImode))"
5117 { return mips_output_move (operands[0], operands[1]); }
5118 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo")
5120 (if_then_else (eq_attr "move_type" "imul")
5122 (const_string "TI")))])
5124 (define_insn "*movti_mips16"
5125 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
5126 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
5129 && (register_operand (operands[0], TImode)
5130 || register_operand (operands[1], TImode))"
5132 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
5133 (set_attr "mode" "TI")])
5135 ;; 128-bit floating point moves
5137 (define_expand "movtf"
5138 [(set (match_operand:TF 0)
5139 (match_operand:TF 1))]
5142 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
5146 ;; This pattern handles both hard- and soft-float cases.
5147 (define_insn "*movtf"
5148 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
5149 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
5152 && (register_operand (operands[0], TFmode)
5153 || reg_or_0_operand (operands[1], TFmode))"
5155 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
5156 (set_attr "mode" "TF")])
5158 (define_insn "*movtf_mips16"
5159 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
5160 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
5163 && (register_operand (operands[0], TFmode)
5164 || register_operand (operands[1], TFmode))"
5166 [(set_attr "move_type" "move,move,move,load,store")
5167 (set_attr "mode" "TF")])
5170 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
5171 (match_operand:MOVE64 1 "move_operand"))]
5172 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
5175 mips_split_move_insn (operands[0], operands[1], curr_insn);
5180 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
5181 (match_operand:MOVE128 1 "move_operand"))]
5182 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
5185 mips_split_move_insn (operands[0], operands[1], curr_insn);
5189 ;; When generating mips16 code, split moves of negative constants into
5190 ;; a positive "li" followed by a negation.
5192 [(set (match_operand 0 "d_operand")
5193 (match_operand 1 "const_int_operand"))]
5194 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
5198 (neg:SI (match_dup 2)))]
5200 operands[2] = gen_lowpart (SImode, operands[0]);
5201 operands[3] = GEN_INT (-INTVAL (operands[1]));
5204 ;; 64-bit paired-single floating point moves
5206 (define_expand "movv2sf"
5207 [(set (match_operand:V2SF 0)
5208 (match_operand:V2SF 1))]
5209 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
5211 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
5215 (define_insn "*movv2sf"
5216 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
5217 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
5219 && TARGET_PAIRED_SINGLE_FLOAT
5220 && (register_operand (operands[0], V2SFmode)
5221 || reg_or_0_operand (operands[1], V2SFmode))"
5222 { return mips_output_move (operands[0], operands[1]); }
5223 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
5224 (set_attr "mode" "DF")])
5226 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
5227 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
5229 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
5230 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
5231 ;; and the errata related to -mfix-vr4130.
5232 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
5233 [(set (match_operand:GPR 0 "register_operand" "=d")
5234 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")]
5237 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
5238 [(set_attr "type" "mfhi")
5239 (set_attr "mode" "<GPR:MODE>")])
5241 ;; Set the high part of a HI/LO value, given that the low part has
5242 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
5243 ;; why we can't just use (reg:GPR HI_REGNUM).
5244 (define_insn "mthi<GPR:mode>_<HILO:mode>"
5245 [(set (match_operand:HILO 0 "register_operand" "=x")
5246 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
5247 (match_operand:GPR 2 "register_operand" "l")]
5251 [(set_attr "type" "mthi")
5252 (set_attr "mode" "SI")])
5254 ;; Emit a doubleword move in which exactly one of the operands is
5255 ;; a floating-point register. We can't just emit two normal moves
5256 ;; because of the constraints imposed by the FPU register model;
5257 ;; see mips_cannot_change_mode_class for details. Instead, we keep
5258 ;; the FPR whole and use special patterns to refer to each word of
5259 ;; the other operand.
5261 (define_expand "move_doubleword_fpr<mode>"
5262 [(set (match_operand:SPLITF 0)
5263 (match_operand:SPLITF 1))]
5266 if (FP_REG_RTX_P (operands[0]))
5268 rtx low = mips_subword (operands[1], 0);
5269 rtx high = mips_subword (operands[1], 1);
5270 emit_insn (gen_load_low<mode> (operands[0], low));
5271 if (ISA_HAS_MXHC1 && !TARGET_64BIT)
5272 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
5274 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
5278 rtx low = mips_subword (operands[0], 0);
5279 rtx high = mips_subword (operands[0], 1);
5280 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
5281 if (ISA_HAS_MXHC1 && !TARGET_64BIT)
5282 emit_insn (gen_mfhc1<mode> (high, operands[1]));
5284 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
5289 ;; Load the low word of operand 0 with operand 1.
5290 (define_insn "load_low<mode>"
5291 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
5292 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
5296 operands[0] = mips_subword (operands[0], 0);
5297 return mips_output_move (operands[0], operands[1]);
5299 [(set_attr "move_type" "mtc,fpload")
5300 (set_attr "mode" "<HALFMODE>")])
5302 ;; Load the high word of operand 0 from operand 1, preserving the value
5304 (define_insn "load_high<mode>"
5305 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
5306 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
5307 (match_operand:SPLITF 2 "register_operand" "0,0")]
5311 operands[0] = mips_subword (operands[0], 1);
5312 return mips_output_move (operands[0], operands[1]);
5314 [(set_attr "move_type" "mtc,fpload")
5315 (set_attr "mode" "<HALFMODE>")])
5317 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
5318 ;; high word and 0 to store the low word.
5319 (define_insn "store_word<mode>"
5320 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
5321 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
5322 (match_operand 2 "const_int_operand")]
5323 UNSPEC_STORE_WORD))]
5326 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
5327 return mips_output_move (operands[0], operands[1]);
5329 [(set_attr "move_type" "mfc,fpstore")
5330 (set_attr "mode" "<HALFMODE>")])
5332 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
5333 ;; value in the low word.
5334 (define_insn "mthc1<mode>"
5335 [(set (match_operand:SPLITF 0 "register_operand" "=f")
5336 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
5337 (match_operand:SPLITF 2 "register_operand" "0")]
5339 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
5341 [(set_attr "move_type" "mtc")
5342 (set_attr "mode" "<HALFMODE>")])
5344 ;; Move high word of operand 1 to operand 0 using mfhc1.
5345 (define_insn "mfhc1<mode>"
5346 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
5347 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
5349 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
5351 [(set_attr "move_type" "mfc")
5352 (set_attr "mode" "<HALFMODE>")])
5354 ;; Move a constant that satisfies CONST_GP_P into operand 0.
5355 (define_expand "load_const_gp_<mode>"
5356 [(set (match_operand:P 0 "register_operand" "=d")
5357 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
5359 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
5360 ;; of _gp from the start of this function. Operand 1 is the incoming
5361 ;; function address.
5362 (define_insn_and_split "loadgp_newabi_<mode>"
5363 [(set (match_operand:P 0 "register_operand" "=&d")
5364 (unspec:P [(match_operand:P 1)
5365 (match_operand:P 2 "register_operand" "d")]
5367 "mips_current_loadgp_style () == LOADGP_NEWABI"
5368 { return mips_must_initialize_gp_p () ? "#" : ""; }
5369 "&& mips_must_initialize_gp_p ()"
5370 [(set (match_dup 0) (match_dup 3))
5371 (set (match_dup 0) (match_dup 4))
5372 (set (match_dup 0) (match_dup 5))]
5374 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
5375 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
5376 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
5378 [(set_attr "type" "ghost")])
5380 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
5381 (define_insn_and_split "loadgp_absolute_<mode>"
5382 [(set (match_operand:P 0 "register_operand" "=d")
5383 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
5384 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
5385 { return mips_must_initialize_gp_p () ? "#" : ""; }
5386 "&& mips_must_initialize_gp_p ()"
5389 mips_emit_move (operands[0], operands[1]);
5392 [(set_attr "type" "ghost")])
5394 ;; This blockage instruction prevents the gp load from being
5395 ;; scheduled after an implicit use of gp. It also prevents
5396 ;; the load from being deleted as dead.
5397 (define_insn "loadgp_blockage"
5398 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
5401 [(set_attr "type" "ghost")])
5403 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
5404 ;; and operand 1 is the __GOTT_INDEX__ symbol.
5405 (define_insn_and_split "loadgp_rtp_<mode>"
5406 [(set (match_operand:P 0 "register_operand" "=d")
5407 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
5408 (match_operand:P 2 "symbol_ref_operand")]
5410 "mips_current_loadgp_style () == LOADGP_RTP"
5411 { return mips_must_initialize_gp_p () ? "#" : ""; }
5412 "&& mips_must_initialize_gp_p ()"
5413 [(set (match_dup 0) (high:P (match_dup 3)))
5414 (set (match_dup 0) (unspec:P [(match_dup 0)
5415 (match_dup 3)] UNSPEC_LOAD_GOT))
5416 (set (match_dup 0) (unspec:P [(match_dup 0)
5417 (match_dup 4)] UNSPEC_LOAD_GOT))]
5419 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
5420 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
5422 [(set_attr "type" "ghost")])
5424 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
5425 ;; global pointer and operand 1 is the MIPS16 register that holds
5426 ;; the required value.
5427 (define_insn_and_split "copygp_mips16_<mode>"
5428 [(set (match_operand:P 0 "register_operand" "=y")
5429 (unspec:P [(match_operand:P 1 "register_operand" "d")]
5432 { return mips_must_initialize_gp_p () ? "#" : ""; }
5433 "&& mips_must_initialize_gp_p ()"
5434 [(set (match_dup 0) (match_dup 1))]
5436 [(set_attr "type" "ghost")])
5438 ;; A placeholder for where the cprestore instruction should go,
5439 ;; if we decide we need one. Operand 0 and operand 1 are as for
5440 ;; "cprestore". Operand 2 is a register that holds the gp value.
5442 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
5443 ;; otherwise any register that holds the correct value will do.
5444 (define_insn_and_split "potential_cprestore_<mode>"
5445 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5446 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5447 (match_operand:P 2 "register_operand" "d,d")]
5448 UNSPEC_POTENTIAL_CPRESTORE))
5449 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))]
5450 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
5451 { return mips_must_initialize_gp_p () ? "#" : ""; }
5452 "mips_must_initialize_gp_p ()"
5455 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
5456 operands[2], operands[3]);
5459 [(set_attr "type" "ghost")])
5461 ;; Emit a .cprestore directive, which normally expands to a single store
5462 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
5463 ;; for the cprestore slot. Operand 1 is the offset of the slot from
5464 ;; the stack pointer. (This is redundant with operand 0, but it makes
5465 ;; things a little simpler.)
5466 (define_insn "cprestore_<mode>"
5467 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5468 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5471 "TARGET_CPRESTORE_DIRECTIVE"
5473 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
5474 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
5476 return ".cprestore\t%1";
5478 [(set_attr "type" "store")
5479 (set_attr "insn_count" "1,3")])
5481 (define_insn "use_cprestore_<mode>"
5482 [(set (reg:P CPRESTORE_SLOT_REGNUM)
5483 (match_operand:P 0 "cprestore_load_slot_operand"))]
5486 [(set_attr "type" "ghost")])
5488 ;; Expand in-line code to clear the instruction cache between operand[0] and
5490 (define_expand "clear_cache"
5491 [(match_operand 0 "pmode_register_operand")
5492 (match_operand 1 "pmode_register_operand")]
5498 mips_expand_synci_loop (operands[0], operands[1]);
5499 emit_insn (gen_sync ());
5500 emit_insn (PMODE_INSN (gen_clear_hazard, ()));
5502 else if (mips_cache_flush_func && mips_cache_flush_func[0])
5504 rtx len = gen_reg_rtx (Pmode);
5505 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
5506 MIPS_ICACHE_SYNC (operands[0], len);
5512 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
5514 { return mips_output_sync (); })
5516 (define_insn "synci"
5517 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
5522 (define_insn "rdhwr_synci_step_<mode>"
5523 [(set (match_operand:P 0 "register_operand" "=d")
5524 (unspec_volatile [(const_int 1)]
5529 (define_insn "clear_hazard_<mode>"
5530 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
5531 (clobber (reg:P RETURN_ADDR_REGNUM))]
5534 return "%(%<bal\t1f\n"
5536 "1:\t<d>addiu\t$31,$31,12\n"
5540 [(set_attr "insn_count" "5")])
5542 ;; Cache operations for R4000-style caches.
5543 (define_insn "mips_cache"
5544 [(set (mem:BLK (scratch))
5545 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
5546 (match_operand:QI 1 "address_operand" "ZD")]
5547 UNSPEC_MIPS_CACHE))]
5551 ;; Similar, but with the operands hard-coded to an R10K cache barrier
5552 ;; operation. We keep the pattern distinct so that we can identify
5553 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
5554 ;; the operation is never inserted into a delay slot.
5555 (define_insn "r10k_cache_barrier"
5556 [(set (mem:BLK (scratch))
5557 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
5560 [(set_attr "can_delay" "no")])
5562 ;; Block moves, see mips.c for more details.
5563 ;; Argument 0 is the destination
5564 ;; Argument 1 is the source
5565 ;; Argument 2 is the length
5566 ;; Argument 3 is the alignment
5568 (define_expand "movmemsi"
5569 [(parallel [(set (match_operand:BLK 0 "general_operand")
5570 (match_operand:BLK 1 "general_operand"))
5571 (use (match_operand:SI 2 ""))
5572 (use (match_operand:SI 3 "const_int_operand"))])]
5573 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5575 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5582 ;; ....................
5586 ;; ....................
5588 (define_expand "<optab><mode>3"
5589 [(set (match_operand:GPR 0 "register_operand")
5590 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5591 (match_operand:SI 2 "arith_operand")))]
5594 /* On the mips16, a shift of more than 8 is a four byte instruction,
5595 so, for a shift between 8 and 16, it is just as fast to do two
5596 shifts of 8 or less. If there is a lot of shifting going on, we
5597 may win in CSE. Otherwise combine will put the shifts back
5598 together again. This can be called by mips_function_arg, so we must
5599 be careful not to allocate a new register if we've reached the
5603 && CONST_INT_P (operands[2])
5604 && INTVAL (operands[2]) > 8
5605 && INTVAL (operands[2]) <= 16
5606 && !reload_in_progress
5607 && !reload_completed)
5609 rtx temp = gen_reg_rtx (<MODE>mode);
5611 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5612 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5613 GEN_INT (INTVAL (operands[2]) - 8)));
5618 (define_insn "*<optab><mode>3"
5619 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
5620 (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d")
5621 (match_operand:SI 2 "arith_operand" "Uib3,dI")))]
5624 if (CONST_INT_P (operands[2]))
5625 operands[2] = GEN_INT (INTVAL (operands[2])
5626 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5628 return "<d><insn>\t%0,%1,%2";
5630 [(set_attr "type" "shift")
5631 (set_attr "compression" "<shift_compression>,none")
5632 (set_attr "mode" "<MODE>")])
5634 (define_insn "*<optab>si3_extend"
5635 [(set (match_operand:DI 0 "register_operand" "=d")
5637 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5638 (match_operand:SI 2 "arith_operand" "dI"))))]
5639 "TARGET_64BIT && !TARGET_MIPS16"
5641 if (CONST_INT_P (operands[2]))
5642 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5644 return "<insn>\t%0,%1,%2";
5646 [(set_attr "type" "shift")
5647 (set_attr "mode" "SI")])
5649 (define_insn "*<optab>si3_mips16"
5650 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
5651 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d,d")
5652 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5655 if (which_alternative == 0)
5656 return "<insn>\t%0,%2";
5658 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5659 return "<insn>\t%0,%1,%2";
5661 [(set_attr "type" "shift")
5662 (set_attr "mode" "SI")
5663 (set_attr "extended_mips16" "no,no,yes")])
5665 (define_insn "<GPR:d>lsa"
5666 [(set (match_operand:GPR 0 "register_operand" "=d")
5667 (plus:GPR (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
5668 (match_operand 2 "const_immlsa_operand" ""))
5669 (match_operand:GPR 3 "register_operand" "d")))]
5670 "ISA_HAS_<GPR:D>LSA"
5671 "<GPR:d>lsa\t%0,%1,%3,%2"
5672 [(set_attr "type" "arith")
5673 (set_attr "mode" "<GPR:MODE>")])
5675 ;; We need separate DImode MIPS16 patterns because of the irregularity
5677 (define_insn "*ashldi3_mips16"
5678 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5679 (ashift:DI (match_operand:DI 1 "register_operand" "0,d,d")
5680 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5681 "TARGET_64BIT && TARGET_MIPS16"
5683 if (which_alternative == 0)
5684 return "dsll\t%0,%2";
5686 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5687 return "dsll\t%0,%1,%2";
5689 [(set_attr "type" "shift")
5690 (set_attr "mode" "DI")
5691 (set_attr "extended_mips16" "no,no,yes")])
5693 (define_insn "*ashrdi3_mips16"
5694 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5695 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5696 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5697 "TARGET_64BIT && TARGET_MIPS16"
5699 if (CONST_INT_P (operands[2]))
5700 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5702 return "dsra\t%0,%2";
5704 [(set_attr "type" "shift")
5705 (set_attr "mode" "DI")
5706 (set_attr "extended_mips16" "no,no,yes")])
5708 (define_insn "*lshrdi3_mips16"
5709 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5710 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5711 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5712 "TARGET_64BIT && TARGET_MIPS16"
5714 if (CONST_INT_P (operands[2]))
5715 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5717 return "dsrl\t%0,%2";
5719 [(set_attr "type" "shift")
5720 (set_attr "mode" "DI")
5721 (set_attr "extended_mips16" "no,no,yes")])
5723 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5726 [(set (match_operand:GPR 0 "d_operand")
5727 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5728 (match_operand:GPR 2 "const_int_operand")))]
5729 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5730 && INTVAL (operands[2]) > 8
5731 && INTVAL (operands[2]) <= 16"
5732 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5733 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5734 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5736 ;; If we load a byte on the mips16 as a bitfield, the resulting
5737 ;; sequence of instructions is too complicated for combine, because it
5738 ;; involves four instructions: a load, a shift, a constant load into a
5739 ;; register, and an and (the key problem here is that the mips16 does
5740 ;; not have and immediate). We recognize a shift of a load in order
5741 ;; to make it simple enough for combine to understand.
5743 ;; The instruction count here is the worst case.
5744 (define_insn_and_split ""
5745 [(set (match_operand:SI 0 "register_operand" "=d")
5746 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5747 (match_operand:SI 2 "immediate_operand" "I")))]
5751 [(set (match_dup 0) (match_dup 1))
5752 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5754 [(set_attr "type" "load")
5755 (set_attr "mode" "SI")
5756 (set (attr "insn_count")
5757 (symbol_ref "mips_load_store_insns (operands[1], insn) + 2"))])
5759 (define_insn "rotr<mode>3"
5760 [(set (match_operand:GPR 0 "register_operand" "=d")
5761 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5762 (match_operand:SI 2 "arith_operand" "dI")))]
5765 if (CONST_INT_P (operands[2]))
5766 gcc_assert (INTVAL (operands[2]) >= 0
5767 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5769 return "<d>ror\t%0,%1,%2";
5771 [(set_attr "type" "shift")
5772 (set_attr "mode" "<MODE>")])
5774 (define_insn "bswaphi2"
5775 [(set (match_operand:HI 0 "register_operand" "=d")
5776 (bswap:HI (match_operand:HI 1 "register_operand" "d")))]
5779 [(set_attr "type" "shift")])
5781 (define_insn_and_split "bswapsi2"
5782 [(set (match_operand:SI 0 "register_operand" "=d")
5783 (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
5784 "ISA_HAS_WSBH && ISA_HAS_ROR"
5787 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_WSBH))
5788 (set (match_dup 0) (rotatert:SI (match_dup 0) (const_int 16)))]
5790 [(set_attr "insn_count" "2")])
5792 (define_insn_and_split "bswapdi2"
5793 [(set (match_operand:DI 0 "register_operand" "=d")
5794 (bswap:DI (match_operand:DI 1 "register_operand" "d")))]
5795 "TARGET_64BIT && ISA_HAS_WSBH"
5798 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_DSBH))
5799 (set (match_dup 0) (unspec:DI [(match_dup 0)] UNSPEC_DSHD))]
5801 [(set_attr "insn_count" "2")])
5804 [(set (match_operand:SI 0 "register_operand" "=d")
5805 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] UNSPEC_WSBH))]
5808 [(set_attr "type" "shift")])
5811 [(set (match_operand:DI 0 "register_operand" "=d")
5812 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSBH))]
5813 "TARGET_64BIT && ISA_HAS_WSBH"
5815 [(set_attr "type" "shift")])
5818 [(set (match_operand:DI 0 "register_operand" "=d")
5819 (unspec:DI [(match_operand:DI 1 "register_operand" "d")] UNSPEC_DSHD))]
5820 "TARGET_64BIT && ISA_HAS_WSBH"
5822 [(set_attr "type" "shift")])
5825 ;; ....................
5827 ;; CONDITIONAL BRANCHES
5829 ;; ....................
5831 ;; Conditional branches on floating-point equality tests.
5833 (define_insn "*branch_fp_<mode>"
5836 (match_operator 1 "equality_operator"
5837 [(match_operand:FPCC 2 "register_operand" "<reg>")
5839 (label_ref (match_operand 0 "" ""))
5843 return mips_output_conditional_branch (insn, operands,
5844 MIPS_BRANCH ("b%F1", "%Z2%0"),
5845 MIPS_BRANCH ("b%W1", "%Z2%0"));
5847 [(set_attr "type" "branch")])
5849 (define_insn "*branch_fp_inverted_<mode>"
5852 (match_operator 1 "equality_operator"
5853 [(match_operand:FPCC 2 "register_operand" "<reg>")
5856 (label_ref (match_operand 0 "" ""))))]
5859 return mips_output_conditional_branch (insn, operands,
5860 MIPS_BRANCH ("b%W1", "%Z2%0"),
5861 MIPS_BRANCH ("b%F1", "%Z2%0"));
5863 [(set_attr "type" "branch")])
5865 ;; Conditional branches on ordered comparisons with zero.
5867 (define_insn "*branch_order<mode>"
5870 (match_operator 1 "order_operator"
5871 [(match_operand:GPR 2 "register_operand" "d,d")
5872 (match_operand:GPR 3 "reg_or_0_operand" "J,d")])
5873 (label_ref (match_operand 0 "" ""))
5876 { return mips_output_order_conditional_branch (insn, operands, false); }
5877 [(set_attr "type" "branch")
5878 (set_attr "compact_form" "maybe,always")
5879 (set_attr "hazard" "forbidden_slot")])
5881 (define_insn "*branch_order<mode>_inverted"
5884 (match_operator 1 "order_operator"
5885 [(match_operand:GPR 2 "register_operand" "d,d")
5886 (match_operand:GPR 3 "reg_or_0_operand" "J,d")])
5888 (label_ref (match_operand 0 "" ""))))]
5890 { return mips_output_order_conditional_branch (insn, operands, true); }
5891 [(set_attr "type" "branch")
5892 (set_attr "compact_form" "maybe,always")
5893 (set_attr "hazard" "forbidden_slot")])
5895 ;; Conditional branch on equality comparison.
5897 (define_insn "*branch_equality<mode>"
5900 (match_operator 1 "equality_operator"
5901 [(match_operand:GPR 2 "register_operand" "d")
5902 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5903 (label_ref (match_operand 0 "" ""))
5906 { return mips_output_equal_conditional_branch (insn, operands, false); }
5907 [(set_attr "type" "branch")
5908 (set_attr "compact_form" "maybe")
5909 (set_attr "hazard" "forbidden_slot")])
5911 (define_insn "*branch_equality<mode>_inverted"
5914 (match_operator 1 "equality_operator"
5915 [(match_operand:GPR 2 "register_operand" "d")
5916 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5918 (label_ref (match_operand 0 "" ""))))]
5920 { return mips_output_equal_conditional_branch (insn, operands, true); }
5921 [(set_attr "type" "branch")
5922 (set_attr "compact_form" "maybe")
5923 (set_attr "hazard" "forbidden_slot")])
5927 (define_insn "*branch_equality<mode>_mips16"
5930 (match_operator 1 "equality_operator"
5931 [(match_operand:GPR 2 "register_operand" "d,t")
5933 (label_ref (match_operand 0 "" ""))
5939 [(set_attr "type" "branch")])
5941 (define_insn "*branch_equality<mode>_mips16_inverted"
5944 (match_operator 1 "equality_operator"
5945 [(match_operand:GPR 2 "register_operand" "d,t")
5948 (label_ref (match_operand 0 "" ""))))]
5953 [(set_attr "type" "branch")])
5955 (define_expand "cbranch<mode>4"
5957 (if_then_else (match_operator 0 "comparison_operator"
5958 [(match_operand:GPR 1 "register_operand")
5959 (match_operand:GPR 2 "nonmemory_operand")])
5960 (label_ref (match_operand 3 ""))
5964 mips_expand_conditional_branch (operands);
5968 (define_expand "cbranch<mode>4"
5970 (if_then_else (match_operator 0 "comparison_operator"
5971 [(match_operand:SCALARF 1 "register_operand")
5972 (match_operand:SCALARF 2 "register_operand")])
5973 (label_ref (match_operand 3 ""))
5977 mips_expand_conditional_branch (operands);
5981 ;; Used to implement built-in functions.
5982 (define_expand "condjump"
5984 (if_then_else (match_operand 0)
5985 (label_ref (match_operand 1))
5988 ;; Branch if bit is set/clear.
5990 (define_insn "*branch_bit<bbv><mode>"
5993 (equality_op (zero_extract:GPR
5994 (match_operand:GPR 1 "register_operand" "d")
5996 (match_operand 2 "const_int_operand" ""))
5998 (label_ref (match_operand 0 ""))
6000 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
6003 mips_output_conditional_branch (insn, operands,
6004 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
6005 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
6007 [(set_attr "type" "branch")
6008 (set_attr "branch_likely" "no")])
6010 (define_insn "*branch_bit<bbv><mode>_inverted"
6013 (equality_op (zero_extract:GPR
6014 (match_operand:GPR 1 "register_operand" "d")
6016 (match_operand 2 "const_int_operand" ""))
6019 (label_ref (match_operand 0 ""))))]
6020 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
6023 mips_output_conditional_branch (insn, operands,
6024 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
6025 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
6027 [(set_attr "type" "branch")
6028 (set_attr "branch_likely" "no")])
6031 ;; ....................
6033 ;; SETTING A REGISTER FROM A COMPARISON
6035 ;; ....................
6037 ;; Destination is always set in SI mode.
6039 (define_expand "cstore<mode>4"
6040 [(set (match_operand:SI 0 "register_operand")
6041 (match_operator:SI 1 "mips_cstore_operator"
6042 [(match_operand:GPR 2 "register_operand")
6043 (match_operand:GPR 3 "nonmemory_operand")]))]
6046 mips_expand_scc (operands);
6050 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
6051 [(set (match_operand:GPR2 0 "register_operand" "=d")
6052 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
6054 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6056 [(set_attr "type" "slt")
6057 (set_attr "mode" "<GPR:MODE>")])
6059 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
6060 [(set (match_operand:GPR2 0 "register_operand" "=t")
6061 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
6063 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6065 [(set_attr "type" "slt")
6066 (set_attr "mode" "<GPR:MODE>")])
6068 ;; Generate sltiu unless using seq results in better code.
6069 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
6070 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
6071 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
6072 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
6078 [(set_attr "type" "slt")
6079 (set_attr "mode" "<GPR:MODE>")])
6081 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
6082 [(set (match_operand:GPR2 0 "register_operand" "=d")
6083 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
6085 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
6087 [(set_attr "type" "slt")
6088 (set_attr "mode" "<GPR:MODE>")])
6090 ;; Generate sltu unless using sne results in better code.
6091 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
6092 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
6093 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
6094 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
6100 [(set_attr "type" "slt")
6101 (set_attr "mode" "<GPR:MODE>")])
6103 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
6104 [(set (match_operand:GPR2 0 "register_operand" "=d")
6105 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6106 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
6109 [(set_attr "type" "slt")
6110 (set_attr "mode" "<GPR:MODE>")])
6112 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
6113 [(set (match_operand:GPR2 0 "register_operand" "=t")
6114 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6115 (match_operand:GPR 2 "register_operand" "d")))]
6118 [(set_attr "type" "slt")
6119 (set_attr "mode" "<GPR:MODE>")])
6121 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
6122 [(set (match_operand:GPR2 0 "register_operand" "=d")
6123 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
6127 [(set_attr "type" "slt")
6128 (set_attr "mode" "<GPR:MODE>")])
6130 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
6131 [(set (match_operand:GPR2 0 "register_operand" "=d")
6132 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
6133 (match_operand:GPR 2 "arith_operand" "dI")))]
6136 [(set_attr "type" "slt")
6137 (set_attr "mode" "<GPR:MODE>")])
6139 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
6140 [(set (match_operand:GPR2 0 "register_operand" "=t,t,t")
6141 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d,d")
6142 (match_operand:GPR 2 "arith_operand" "d,Uub8,I")))]
6145 [(set_attr "type" "slt")
6146 (set_attr "mode" "<GPR:MODE>")
6147 (set_attr "extended_mips16" "no,no,yes")])
6149 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
6150 [(set (match_operand:GPR2 0 "register_operand" "=d")
6151 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
6152 (match_operand:GPR 2 "sle_operand" "")))]
6155 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
6156 return "slt<u>\t%0,%1,%2";
6158 [(set_attr "type" "slt")
6159 (set_attr "mode" "<GPR:MODE>")])
6161 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
6162 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
6163 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
6164 (match_operand:GPR 2 "sle_operand" "Udb8,i")))]
6167 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
6168 return "slt<u>\t%1,%2";
6170 [(set_attr "type" "slt")
6171 (set_attr "mode" "<GPR:MODE>")
6172 (set_attr "extended_mips16" "no,yes")])
6175 ;; ....................
6177 ;; FLOATING POINT COMPARISONS
6179 ;; ....................
6181 (define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>"
6182 [(set (match_operand:FPCC 0 "register_operand" "=<reg>")
6183 (fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f")
6184 (match_operand:SCALARF 2 "register_operand" "f")))]
6186 "<fpcmp>.<fcond>.<fmt>\t%Z0%1,%2"
6187 [(set_attr "type" "fcmp")
6188 (set_attr "mode" "FPSW")])
6190 (define_insn "s<code>_<SCALARF:mode>_using_<FPCC:mode>"
6191 [(set (match_operand:FPCC 0 "register_operand" "=<reg>")
6192 (swapped_fcond:FPCC (match_operand:SCALARF 1 "register_operand" "f")
6193 (match_operand:SCALARF 2 "register_operand" "f")))]
6195 "<fpcmp>.<swapped_fcond>.<fmt>\t%Z0%2,%1"
6196 [(set_attr "type" "fcmp")
6197 (set_attr "mode" "FPSW")])
6200 ;; ....................
6202 ;; UNCONDITIONAL BRANCHES
6204 ;; ....................
6206 ;; Unconditional branches.
6208 (define_expand "jump"
6210 (label_ref (match_operand 0)))])
6212 (define_insn "*jump_absolute"
6214 (label_ref (match_operand 0)))]
6215 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
6217 if (get_attr_length (insn) <= 8)
6219 if (TARGET_CB_MAYBE)
6220 return MIPS_ABSOLUTE_JUMP ("%*b%:\t%l0");
6222 return MIPS_ABSOLUTE_JUMP ("%*b\t%l0%/");
6226 if (TARGET_CB_MAYBE && !final_sequence)
6227 return MIPS_ABSOLUTE_JUMP ("%*bc\t%l0");
6229 return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/");
6232 [(set_attr "type" "branch")
6233 (set_attr "compact_form" "maybe")])
6235 (define_insn "*jump_pic"
6237 (label_ref (match_operand 0)))]
6238 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
6240 if (get_attr_length (insn) <= 8)
6242 if (TARGET_CB_MAYBE)
6243 return "%*b%:\t%l0";
6245 return "%*b\t%l0%/";
6249 mips_output_load_label (operands[0]);
6250 if (TARGET_CB_MAYBE)
6251 return "%*jr%:\t%@%]";
6253 return "%*jr\t%@%/%]";
6256 [(set_attr "type" "branch")
6257 (set_attr "compact_form" "maybe")])
6259 ;; We need a different insn for the mips16, because a mips16 branch
6260 ;; does not have a delay slot.
6262 (define_insn "*jump_mips16"
6264 (label_ref (match_operand 0 "" "")))]
6267 [(set_attr "type" "branch")
6268 (set (attr "length")
6269 ;; This calculation is like the normal branch one, but the
6270 ;; range of the unextended instruction is [-0x800, 0x7fe] rather
6271 ;; than [-0x100, 0xfe]. This translates to a range of:
6273 ;; [-(0x800 - sizeof (branch)), 0x7fe]
6274 ;; == [-0x7fe, 0x7fe]
6276 ;; from the shorten_branches reference address. Long-branch
6277 ;; sequences will replace this one, so the minimum length
6278 ;; is one instruction shorter than for conditional branches.
6279 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
6280 (le (minus (pc) (match_dup 0)) (const_int 2046)))
6282 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
6283 (le (minus (pc) (match_dup 0)) (const_int 65532)))
6285 (and (match_test "TARGET_ABICALLS")
6286 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
6288 (match_test "Pmode == SImode")
6290 ] (const_int 22)))])
6292 (define_expand "indirect_jump"
6293 [(set (pc) (match_operand 0 "register_operand"))]
6296 operands[0] = force_reg (Pmode, operands[0]);
6297 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0])));
6301 (define_insn "indirect_jump_<mode>"
6302 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
6305 return mips_output_jump (operands, 0, -1, false);
6307 [(set_attr "type" "jump")
6308 (set_attr "mode" "none")])
6310 ;; A combined jump-and-move instruction, used for MIPS16 long-branch
6311 ;; sequences. Having a dedicated pattern is more convenient than
6312 ;; creating a SEQUENCE for this special case.
6313 (define_insn "indirect_jump_and_restore_<mode>"
6314 [(set (pc) (match_operand:P 1 "register_operand" "d"))
6315 (set (match_operand:P 0 "register_operand" "=d")
6316 (match_operand:P 2 "register_operand" "y"))]
6318 "%(%<jr\t%1\;move\t%0,%2%>%)"
6319 [(set_attr "type" "multi")
6320 (set_attr "extended_mips16" "yes")])
6322 (define_expand "tablejump"
6324 (match_operand 0 "register_operand"))
6325 (use (label_ref (match_operand 1 "")))]
6326 "!TARGET_MIPS16_SHORT_JUMP_TABLES"
6329 operands[0] = expand_binop (Pmode, add_optab, operands[0],
6330 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
6331 else if (TARGET_RTP_PIC)
6333 /* When generating RTP PIC, we use case table entries that are relative
6334 to the start of the function. Add the function's address to the
6336 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6337 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
6338 start, 0, 0, OPTAB_WIDEN);
6341 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1])));
6345 (define_insn "tablejump_<mode>"
6347 (match_operand:P 0 "register_operand" "d"))
6348 (use (label_ref (match_operand 1 "" "")))]
6351 return mips_output_jump (operands, 0, -1, false);
6353 [(set_attr "type" "jump")
6354 (set_attr "mode" "none")])
6356 ;; For MIPS16, we don't know whether a given jump table will use short or
6357 ;; word-sized offsets until late in compilation, when we are able to determine
6358 ;; the sizes of the insns which comprise the containing function. This
6359 ;; necessitates the use of the casesi rather than the tablejump pattern, since
6360 ;; the latter tries to calculate the index of the offset to jump through early
6361 ;; in compilation, i.e. at expand time, when nothing is known about the
6362 ;; eventual function layout.
6364 (define_expand "casesi"
6365 [(match_operand:SI 0 "register_operand" "") ; index to jump on
6366 (match_operand:SI 1 "const_int_operand" "") ; lower bound
6367 (match_operand:SI 2 "const_int_operand" "") ; total range
6368 (match_operand 3 "" "") ; table label
6369 (match_operand 4 "" "")] ; out of range label
6370 "TARGET_MIPS16_SHORT_JUMP_TABLES"
6372 if (operands[1] != const0_rtx)
6374 rtx reg = gen_reg_rtx (SImode);
6375 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode);
6377 if (!arith_operand (offset, SImode))
6378 offset = force_reg (SImode, offset);
6380 emit_insn (gen_addsi3 (reg, operands[0], offset));
6384 if (!arith_operand (operands[0], SImode))
6385 operands[0] = force_reg (SImode, operands[0]);
6387 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
6389 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16,
6390 (operands[0], operands[2],
6391 operands[3], operands[4])));
6396 (define_insn "casesi_internal_mips16_<mode>"
6399 (leu (match_operand:SI 0 "register_operand" "d")
6400 (match_operand:SI 1 "arith_operand" "dI"))
6403 (label_ref (match_operand 2 "" ""))]
6404 UNSPEC_CASESI_DISPATCH)
6405 (label_ref (match_operand 3 "" ""))))
6406 (clobber (match_scratch:P 4 "=d"))
6407 (clobber (match_scratch:P 5 "=d"))
6408 (clobber (reg:SI MIPS16_T_REGNUM))]
6409 "TARGET_MIPS16_SHORT_JUMP_TABLES"
6411 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
6413 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
6415 output_asm_insn ("sltu\t%0, %1", operands);
6416 output_asm_insn ("bteqz\t%3", operands);
6418 switch (GET_MODE (diff_vec))
6421 output_asm_insn ("sll\t%5, %0, 1", operands);
6422 output_asm_insn ("la\t%4, %2", operands);
6423 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
6424 output_asm_insn ("lh\t%5, 0(%5)", operands);
6428 output_asm_insn ("sll\t%5, %0, 2", operands);
6429 output_asm_insn ("la\t%4, %2", operands);
6430 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
6431 output_asm_insn ("lw\t%5, 0(%5)", operands);
6438 output_asm_insn ("addu\t%4, %4, %5", operands);
6442 [(set_attr "insn_count" "16")])
6444 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
6445 ;; While it is possible to either pull it off the stack (in the
6446 ;; o32 case) or recalculate it given t9 and our target label,
6447 ;; it takes 3 or 4 insns to do so.
6449 (define_expand "builtin_setjmp_setup"
6450 [(use (match_operand 0 "register_operand"))]
6455 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3);
6456 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
6460 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
6461 ;; that older code did recalculate the gp from $25. Continue to jump through
6462 ;; $25 for compatibility (we lose nothing by doing so).
6464 (define_expand "builtin_longjmp"
6465 [(use (match_operand 0 "register_operand"))]
6468 /* The elements of the buffer are, in order: */
6469 int W = GET_MODE_SIZE (Pmode);
6470 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6471 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W));
6472 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W));
6473 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W));
6474 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6475 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
6476 The target is bound to be using $28 as the global pointer
6477 but the current function might not be. */
6478 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
6480 /* This bit is similar to expand_builtin_longjmp except that it
6481 restores $gp as well. */
6482 mips_emit_move (hard_frame_pointer_rtx, fp);
6483 mips_emit_move (pv, lab);
6484 emit_stack_restore (SAVE_NONLOCAL, stack);
6485 mips_emit_move (gp, gpv);
6486 emit_use (hard_frame_pointer_rtx);
6487 emit_use (stack_pointer_rtx);
6489 emit_indirect_jump (pv);
6494 ;; ....................
6496 ;; Function prologue/epilogue
6498 ;; ....................
6501 (define_expand "prologue"
6505 mips_expand_prologue ();
6509 ;; Block any insns from being moved before this point, since the
6510 ;; profiling call to mcount can use various registers that aren't
6511 ;; saved or used to pass arguments.
6513 (define_insn "blockage"
6514 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
6517 [(set_attr "type" "ghost")
6518 (set_attr "mode" "none")])
6520 (define_insn "probe_stack_range_<P:mode>"
6521 [(set (match_operand:P 0 "register_operand" "=d")
6522 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
6523 (match_operand:P 2 "register_operand" "d")]
6524 UNSPEC_PROBE_STACK_RANGE))]
6526 { return mips_output_probe_stack_range (operands[0], operands[2]); }
6527 [(set_attr "type" "unknown")
6528 (set_attr "can_delay" "no")
6529 (set_attr "mode" "<MODE>")])
6531 (define_expand "epilogue"
6535 mips_expand_epilogue (false);
6539 (define_expand "sibcall_epilogue"
6543 mips_expand_epilogue (true);
6547 ;; Trivial return. Make it look like a normal return insn as that
6548 ;; allows jump optimizations to work better.
6550 (define_expand "return"
6552 "mips_can_use_return_insn ()"
6553 { mips_expand_before_return (); })
6555 (define_expand "simple_return"
6558 { mips_expand_before_return (); })
6560 (define_insn "*<optab>"
6564 operands[0] = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
6565 return mips_output_jump (operands, 0, -1, false);
6567 [(set_attr "type" "jump")
6568 (set_attr "mode" "none")])
6572 (define_insn "<optab>_internal"
6574 (use (match_operand 0 "pmode_register_operand" ""))]
6577 operands[0] = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
6578 return mips_output_jump (operands, 0, -1, false);
6580 [(set_attr "type" "jump")
6581 (set_attr "mode" "none")])
6583 ;; Exception return.
6584 (define_insn "mips_eret"
6586 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
6589 [(set_attr "type" "trap")
6590 (set_attr "mode" "none")])
6592 ;; Debug exception return.
6593 (define_insn "mips_deret"
6595 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
6598 [(set_attr "type" "trap")
6599 (set_attr "mode" "none")])
6601 ;; Disable interrupts.
6602 (define_insn "mips_di"
6603 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
6606 [(set_attr "type" "trap")
6607 (set_attr "mode" "none")])
6609 ;; Execution hazard barrier.
6610 (define_insn "mips_ehb"
6611 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
6614 [(set_attr "type" "trap")
6615 (set_attr "mode" "none")])
6617 ;; Read GPR from previous shadow register set.
6618 (define_insn "mips_rdpgpr_<mode>"
6619 [(set (match_operand:P 0 "register_operand" "=d")
6620 (unspec_volatile:P [(match_operand:P 1 "register_operand" "d")]
6624 [(set_attr "type" "move")
6625 (set_attr "mode" "<MODE>")])
6627 ;; Move involving COP0 registers.
6628 (define_insn "cop0_move"
6629 [(set (match_operand:SI 0 "register_operand" "=B,d")
6630 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
6633 { return mips_output_move (operands[0], operands[1]); }
6634 [(set_attr "type" "mtc,mfc")
6635 (set_attr "mode" "SI")])
6637 ;; This is used in compiling the unwind routines.
6638 (define_expand "eh_return"
6639 [(use (match_operand 0 "general_operand"))]
6642 if (GET_MODE (operands[0]) != word_mode)
6643 operands[0] = convert_to_mode (word_mode, operands[0], 0);
6645 emit_insn (gen_eh_set_lr_di (operands[0]));
6647 emit_insn (gen_eh_set_lr_si (operands[0]));
6651 ;; Clobber the return address on the stack. We can't expand this
6652 ;; until we know where it will be put in the stack frame.
6654 (define_insn "eh_set_lr_si"
6655 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6656 (clobber (match_scratch:SI 1 "=&d"))]
6660 (define_insn "eh_set_lr_di"
6661 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6662 (clobber (match_scratch:DI 1 "=&d"))]
6667 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
6668 (clobber (match_scratch 1))]
6672 mips_set_return_address (operands[0], operands[1]);
6676 (define_expand "exception_receiver"
6680 /* See the comment above load_call<mode> for details. */
6681 emit_insn (gen_set_got_version ());
6683 /* If we have a call-clobbered $gp, restore it from its save slot. */
6684 if (HAVE_restore_gp_si)
6685 emit_insn (gen_restore_gp_si ());
6686 else if (HAVE_restore_gp_di)
6687 emit_insn (gen_restore_gp_di ());
6691 (define_expand "nonlocal_goto_receiver"
6695 /* See the comment above load_call<mode> for details. */
6696 emit_insn (gen_set_got_version ());
6700 ;; Restore $gp from its .cprestore stack slot. The instruction remains
6701 ;; volatile until all uses of $28 are exposed.
6702 (define_insn_and_split "restore_gp_<mode>"
6704 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP))
6705 (clobber (match_scratch:P 0 "=&d"))]
6706 "TARGET_CALL_CLOBBERED_GP"
6708 "&& epilogue_completed"
6711 mips_restore_gp_from_cprestore_slot (operands[0]);
6714 [(set_attr "type" "ghost")])
6716 ;; Move between $gp and its register save slot.
6717 (define_insn_and_split "move_gp<mode>"
6718 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
6719 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
6722 { return mips_must_initialize_gp_p () ? "#" : ""; }
6723 "mips_must_initialize_gp_p ()"
6726 mips_emit_move (operands[0], operands[1]);
6729 [(set_attr "type" "ghost")])
6732 ;; ....................
6736 ;; ....................
6738 ;; Instructions to load a call address from the GOT. The address might
6739 ;; point to a function or to a lazy binding stub. In the latter case,
6740 ;; the stub will use the dynamic linker to resolve the function, which
6741 ;; in turn will change the GOT entry to point to the function's real
6744 ;; This means that every call, even pure and constant ones, can
6745 ;; potentially modify the GOT entry. And once a stub has been called,
6746 ;; we must not call it again.
6748 ;; We represent this restriction using an imaginary, fixed, call-saved
6749 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
6750 ;; live throughout the function and to change its value after every
6751 ;; potential call site. This stops any rtx value that uses the register
6752 ;; from being computed before an earlier call. To do this, we:
6754 ;; - Ensure that the register is live on entry to the function,
6755 ;; so that it is never thought to be used uninitalized.
6757 ;; - Ensure that the register is live on exit from the function,
6758 ;; so that it is live throughout.
6760 ;; - Make each call (lazily-bound or not) use the current value
6761 ;; of GOT_VERSION_REGNUM, so that updates of the register are
6762 ;; not moved across call boundaries.
6764 ;; - Add "ghost" definitions of the register to the beginning of
6765 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
6766 ;; edges may involve calls that normal paths don't. (E.g. the
6767 ;; unwinding code that handles a non-call exception may change
6768 ;; lazily-bound GOT entries.) We do this by making the
6769 ;; exception_receiver and nonlocal_goto_receiver expanders emit
6770 ;; a set_got_version instruction.
6772 ;; - After each call (lazily-bound or not), use a "ghost"
6773 ;; update_got_version instruction to change the register's value.
6774 ;; This instruction mimics the _possible_ effect of the dynamic
6775 ;; resolver during the call and it remains live even if the call
6776 ;; itself becomes dead.
6778 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
6779 ;; The register is therefore not a valid register_operand
6780 ;; and cannot be moved to or from other registers.
6782 (define_insn "load_call<mode>"
6783 [(set (match_operand:P 0 "register_operand" "=d")
6784 (unspec:P [(match_operand:P 1 "register_operand" "d")
6785 (match_operand:P 2 "immediate_operand" "")
6786 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
6788 "<load>\t%0,%R2(%1)"
6789 [(set_attr "got" "load")
6790 (set_attr "mode" "<MODE>")])
6792 (define_insn "set_got_version"
6793 [(set (reg:SI GOT_VERSION_REGNUM)
6794 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
6797 [(set_attr "type" "ghost")])
6799 (define_insn "update_got_version"
6800 [(set (reg:SI GOT_VERSION_REGNUM)
6801 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
6804 [(set_attr "type" "ghost")])
6806 ;; Sibling calls. All these patterns use jump instructions.
6808 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
6809 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
6810 ;; is defined in terms of call_insn_operand, the same is true of the
6813 ;; When we use an indirect jump, we need a register that will be
6814 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
6815 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
6816 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
6819 (define_expand "sibcall"
6820 [(parallel [(call (match_operand 0 "")
6821 (match_operand 1 ""))
6822 (use (match_operand 2 "")) ;; next_arg_reg
6823 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6826 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
6827 operands[1], operands[2], false);
6831 (define_insn "sibcall_internal"
6832 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
6833 (match_operand 1 "" ""))]
6834 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6835 { return mips_output_jump (operands, 0, 1, false); }
6836 [(set_attr "jal" "indirect,direct")
6837 (set_attr "jal_macro" "no")])
6839 (define_expand "sibcall_value"
6840 [(parallel [(set (match_operand 0 "")
6841 (call (match_operand 1 "")
6842 (match_operand 2 "")))
6843 (use (match_operand 3 ""))])] ;; next_arg_reg
6846 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
6847 operands[2], operands[3], false);
6851 (define_insn "sibcall_value_internal"
6852 [(set (match_operand 0 "register_operand" "")
6853 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6854 (match_operand 2 "" "")))]
6855 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6856 { return mips_output_jump (operands, 1, 2, false); }
6857 [(set_attr "jal" "indirect,direct")
6858 (set_attr "jal_macro" "no")])
6860 (define_insn "sibcall_value_multiple_internal"
6861 [(set (match_operand 0 "register_operand" "")
6862 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6863 (match_operand 2 "" "")))
6864 (set (match_operand 3 "register_operand" "")
6865 (call (mem:SI (match_dup 1))
6867 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6868 { return mips_output_jump (operands, 1, 2, false); }
6869 [(set_attr "jal" "indirect,direct")
6870 (set_attr "jal_macro" "no")])
6872 (define_expand "call"
6873 [(parallel [(call (match_operand 0 "")
6874 (match_operand 1 ""))
6875 (use (match_operand 2 "")) ;; next_arg_reg
6876 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6879 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6880 operands[1], operands[2], false);
6884 ;; This instruction directly corresponds to an assembly-language "jal".
6885 ;; There are four cases:
6888 ;; Both symbolic and register destinations are OK. The pattern
6889 ;; always expands to a single mips instruction.
6891 ;; - -mabicalls/-mno-explicit-relocs:
6892 ;; Again, both symbolic and register destinations are OK.
6893 ;; The call is treated as a multi-instruction black box.
6895 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6896 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6899 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6900 ;; Only "jal $25" is allowed. The call is actually two instructions:
6901 ;; "jalr $25" followed by an insn to reload $gp.
6903 ;; In the last case, we can generate the individual instructions with
6904 ;; a define_split. There are several things to be wary of:
6906 ;; - We can't expose the load of $gp before reload. If we did,
6907 ;; it might get removed as dead, but reload can introduce new
6908 ;; uses of $gp by rematerializing constants.
6910 ;; - We shouldn't restore $gp after calls that never return.
6911 ;; It isn't valid to insert instructions between a noreturn
6912 ;; call and the following barrier.
6914 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6915 ;; instruction preserves $gp and so have no effect on its liveness.
6916 ;; But once we generate the separate insns, it becomes obvious that
6917 ;; $gp is not live on entry to the call.
6919 (define_insn_and_split "call_internal"
6920 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6921 (match_operand 1 "" ""))
6922 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6925 return (TARGET_SPLIT_CALLS ? "#"
6926 : mips_output_jump (operands, 0, 1, true));
6928 "reload_completed && TARGET_SPLIT_CALLS"
6931 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6934 [(set_attr "jal" "indirect,direct")])
6936 (define_insn "call_split"
6937 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6938 (match_operand 1 "" ""))
6939 (clobber (reg:SI RETURN_ADDR_REGNUM))
6940 (clobber (reg:SI 28))]
6941 "TARGET_SPLIT_CALLS"
6942 { return mips_output_jump (operands, 0, 1, true); }
6943 [(set_attr "jal" "indirect,direct")
6944 (set_attr "jal_macro" "no")])
6946 ;; A pattern for calls that must be made directly. It is used for
6947 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6948 ;; stub; the linker relies on the call relocation type to detect when
6949 ;; such redirection is needed.
6950 (define_insn_and_split "call_internal_direct"
6951 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6954 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6957 return (TARGET_SPLIT_CALLS ? "#"
6958 : mips_output_jump (operands, 0, -1, true));
6960 "reload_completed && TARGET_SPLIT_CALLS"
6963 mips_split_call (curr_insn,
6964 gen_call_direct_split (operands[0], operands[1]));
6967 [(set_attr "jal" "direct")])
6969 (define_insn "call_direct_split"
6970 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6973 (clobber (reg:SI RETURN_ADDR_REGNUM))
6974 (clobber (reg:SI 28))]
6975 "TARGET_SPLIT_CALLS"
6976 { return mips_output_jump (operands, 0, -1, true); }
6977 [(set_attr "jal" "direct")
6978 (set_attr "jal_macro" "no")])
6980 (define_expand "call_value"
6981 [(parallel [(set (match_operand 0 "")
6982 (call (match_operand 1 "")
6983 (match_operand 2 "")))
6984 (use (match_operand 3 ""))])] ;; next_arg_reg
6987 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6988 operands[2], operands[3], false);
6992 ;; See comment for call_internal.
6993 (define_insn_and_split "call_value_internal"
6994 [(set (match_operand 0 "register_operand" "")
6995 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6996 (match_operand 2 "" "")))
6997 (clobber (reg:SI RETURN_ADDR_REGNUM))]
7000 return (TARGET_SPLIT_CALLS ? "#"
7001 : mips_output_jump (operands, 1, 2, true));
7003 "reload_completed && TARGET_SPLIT_CALLS"
7006 mips_split_call (curr_insn,
7007 gen_call_value_split (operands[0], operands[1],
7011 [(set_attr "jal" "indirect,direct")])
7013 (define_insn "call_value_split"
7014 [(set (match_operand 0 "register_operand" "")
7015 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7016 (match_operand 2 "" "")))
7017 (clobber (reg:SI RETURN_ADDR_REGNUM))
7018 (clobber (reg:SI 28))]
7019 "TARGET_SPLIT_CALLS"
7020 { return mips_output_jump (operands, 1, 2, true); }
7021 [(set_attr "jal" "indirect,direct")
7022 (set_attr "jal_macro" "no")])
7024 ;; See call_internal_direct.
7025 (define_insn_and_split "call_value_internal_direct"
7026 [(set (match_operand 0 "register_operand")
7027 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
7030 (clobber (reg:SI RETURN_ADDR_REGNUM))]
7033 return (TARGET_SPLIT_CALLS ? "#"
7034 : mips_output_jump (operands, 1, -1, true));
7036 "reload_completed && TARGET_SPLIT_CALLS"
7039 mips_split_call (curr_insn,
7040 gen_call_value_direct_split (operands[0], operands[1],
7044 [(set_attr "jal" "direct")])
7046 (define_insn "call_value_direct_split"
7047 [(set (match_operand 0 "register_operand")
7048 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
7051 (clobber (reg:SI RETURN_ADDR_REGNUM))
7052 (clobber (reg:SI 28))]
7053 "TARGET_SPLIT_CALLS"
7054 { return mips_output_jump (operands, 1, -1, true); }
7055 [(set_attr "jal" "direct")
7056 (set_attr "jal_macro" "no")])
7058 ;; See comment for call_internal.
7059 (define_insn_and_split "call_value_multiple_internal"
7060 [(set (match_operand 0 "register_operand" "")
7061 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7062 (match_operand 2 "" "")))
7063 (set (match_operand 3 "register_operand" "")
7064 (call (mem:SI (match_dup 1))
7066 (clobber (reg:SI RETURN_ADDR_REGNUM))]
7069 return (TARGET_SPLIT_CALLS ? "#"
7070 : mips_output_jump (operands, 1, 2, true));
7072 "reload_completed && TARGET_SPLIT_CALLS"
7075 mips_split_call (curr_insn,
7076 gen_call_value_multiple_split (operands[0], operands[1],
7077 operands[2], operands[3]));
7080 [(set_attr "jal" "indirect,direct")])
7082 (define_insn "call_value_multiple_split"
7083 [(set (match_operand 0 "register_operand" "")
7084 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
7085 (match_operand 2 "" "")))
7086 (set (match_operand 3 "register_operand" "")
7087 (call (mem:SI (match_dup 1))
7089 (clobber (reg:SI RETURN_ADDR_REGNUM))
7090 (clobber (reg:SI 28))]
7091 "TARGET_SPLIT_CALLS"
7092 { return mips_output_jump (operands, 1, 2, true); }
7093 [(set_attr "jal" "indirect,direct")
7094 (set_attr "jal_macro" "no")])
7096 ;; Call subroutine returning any type.
7098 (define_expand "untyped_call"
7099 [(parallel [(call (match_operand 0 "")
7101 (match_operand 1 "")
7102 (match_operand 2 "")])]
7107 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
7109 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7111 rtx set = XVECEXP (operands[2], 0, i);
7112 mips_emit_move (SET_DEST (set), SET_SRC (set));
7115 emit_insn (gen_blockage ());
7120 ;; ....................
7124 ;; ....................
7128 (define_insn "prefetch"
7129 [(prefetch (match_operand:QI 0 "address_operand" "ZD")
7130 (match_operand 1 "const_int_operand" "n")
7131 (match_operand 2 "const_int_operand" "n"))]
7132 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
7134 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
7136 /* Loongson 2[ef] and Loongson 3a use load to $0 for prefetching. */
7138 return "ld\t$0,%a0";
7140 return "lw\t$0,%a0";
7142 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
7143 return "pref\t%1,%a0";
7145 [(set_attr "type" "prefetch")])
7147 (define_insn "*prefetch_indexed_<mode>"
7148 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
7149 (match_operand:P 1 "register_operand" "d"))
7150 (match_operand 2 "const_int_operand" "n")
7151 (match_operand 3 "const_int_operand" "n"))]
7152 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7154 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
7155 return "prefx\t%2,%1(%0)";
7157 [(set_attr "type" "prefetchx")])
7163 [(set_attr "type" "nop")
7164 (set_attr "mode" "none")])
7166 ;; Like nop, but commented out when outside a .set noreorder block.
7167 (define_insn "hazard_nop"
7171 if (mips_noreorder.nesting_level > 0)
7176 [(set_attr "type" "nop")])
7178 ;; MIPS4 Conditional move instructions.
7180 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
7181 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7183 (match_operator 4 "equality_operator"
7184 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
7186 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
7187 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
7192 [(set_attr "type" "condmove")
7193 (set_attr "mode" "<GPR:MODE>")])
7195 (define_insn "*mov<GPR:mode>_on_<GPR2:mode>_ne"
7196 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7198 (match_operand:GPR2 1 "register_operand" "<GPR2:reg>,<GPR2:reg>")
7199 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
7200 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
7205 [(set_attr "type" "condmove")
7206 (set_attr "mode" "<GPR:MODE>")])
7208 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
7209 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
7210 (if_then_else:SCALARF
7211 (match_operator 4 "equality_operator"
7212 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
7214 (match_operand:SCALARF 2 "register_operand" "f,0")
7215 (match_operand:SCALARF 3 "register_operand" "0,f")))]
7216 "ISA_HAS_FP_CONDMOVE"
7218 mov%T4.<fmt>\t%0,%2,%1
7219 mov%t4.<fmt>\t%0,%3,%1"
7220 [(set_attr "type" "condmove")
7221 (set_attr "mode" "<SCALARF:MODE>")])
7223 (define_insn "*sel<code><GPR:mode>_using_<GPR2:mode>"
7224 [(set (match_operand:GPR 0 "register_operand" "=d,d")
7226 (equality_op:GPR2 (match_operand:GPR2 1 "register_operand" "d,d")
7228 (match_operand:GPR 2 "reg_or_0_operand" "d,J")
7229 (match_operand:GPR 3 "reg_or_0_operand" "J,d")))]
7231 && (register_operand (operands[2], <GPR:MODE>mode)
7232 != register_operand (operands[3], <GPR:MODE>mode))"
7236 [(set_attr "type" "condmove")
7237 (set_attr "mode" "<GPR:MODE>")])
7239 ;; sel.fmt copies the 3rd argument when the 1st is non-zero and the 2nd
7240 ;; argument if the 1st is zero. This means operand 2 and 3 are
7241 ;; inverted in the instruction.
7243 (define_insn "*sel<mode>"
7244 [(set (match_operand:SCALARF 0 "register_operand" "=f,f,f")
7245 (if_then_else:SCALARF
7246 (ne:CCF (match_operand:CCF 1 "register_operand" "0,f,f")
7248 (match_operand:SCALARF 2 "reg_or_0_operand" "f,G,f")
7249 (match_operand:SCALARF 3 "reg_or_0_operand" "f,f,G")))]
7250 "ISA_HAS_SEL && ISA_HAS_CCF"
7253 seleqz.<fmt>\t%0,%3,%1
7254 selnez.<fmt>\t%0,%2,%1"
7255 [(set_attr "type" "condmove")
7256 (set_attr "mode" "<SCALARF:MODE>")])
7258 ;; These are the main define_expand's used to make conditional moves.
7260 (define_expand "mov<mode>cc"
7261 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
7262 (set (match_operand:GPR 0 "register_operand")
7263 (if_then_else:GPR (match_dup 5)
7264 (match_operand:GPR 2 "reg_or_0_operand")
7265 (match_operand:GPR 3 "reg_or_0_operand")))]
7266 "ISA_HAS_CONDMOVE || ISA_HAS_SEL"
7268 if (!ISA_HAS_FP_CONDMOVE
7269 && !INTEGRAL_MODE_P (GET_MODE (XEXP (operands[1], 0))))
7272 mips_expand_conditional_move (operands);
7276 (define_expand "mov<mode>cc"
7277 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
7278 (set (match_operand:SCALARF 0 "register_operand")
7279 (if_then_else:SCALARF (match_dup 5)
7280 (match_operand:SCALARF 2 "reg_or_0_operand")
7281 (match_operand:SCALARF 3 "reg_or_0_operand")))]
7282 "ISA_HAS_FP_CONDMOVE
7283 || (ISA_HAS_SEL && ISA_HAS_CCF)"
7285 if (ISA_HAS_SEL && !FLOAT_MODE_P (GET_MODE (XEXP (operands[1], 0))))
7288 /* Workaround an LRA bug which means that tied operands in the sel.fmt
7289 pattern lead to the double precision destination of sel.d getting
7290 reloaded with the full register file usable and the restrictions on
7291 whether the CCFmode input can be used in odd-numbered single-precision
7292 registers are ignored. For consistency reasons the CCF mode values
7293 must be guaranteed to only exist in the even-registers because of
7294 the unusual duality between single and double precision values. */
7295 if (ISA_HAS_SEL && <MODE>mode == DFmode
7296 && (!TARGET_ODD_SPREG || TARGET_FLOATXX))
7299 mips_expand_conditional_move (operands);
7304 ;; ....................
7306 ;; mips16 inline constant tables
7308 ;; ....................
7311 (define_insn "consttable_tls_reloc"
7312 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "")
7313 (match_operand 1 "const_int_operand" "")]
7314 UNSPEC_CONSTTABLE_INT)]
7315 "TARGET_MIPS16_PCREL_LOADS"
7316 { return mips_output_tls_reloc_directive (&operands[0]); }
7317 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
7319 (define_insn "consttable_int"
7320 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
7321 (match_operand 1 "const_int_operand" "")]
7322 UNSPEC_CONSTTABLE_INT)]
7325 assemble_integer (mips_strip_unspec_address (operands[0]),
7326 INTVAL (operands[1]),
7327 BITS_PER_UNIT * INTVAL (operands[1]), 1);
7330 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
7332 (define_insn "consttable_float"
7333 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
7334 UNSPEC_CONSTTABLE_FLOAT)]
7337 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
7338 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
7339 GET_MODE (operands[0]),
7340 GET_MODE_BITSIZE (GET_MODE (operands[0])));
7343 [(set (attr "length")
7344 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
7346 (define_insn "align"
7347 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
7350 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
7353 [(match_operand 0 "small_data_pattern")]
7356 { operands[0] = mips_rewrite_small_data (operands[0]); })
7359 ;; ....................
7361 ;; MIPS16e Save/Restore
7363 ;; ....................
7366 (define_insn "*mips16e_save_restore"
7367 [(match_parallel 0 ""
7368 [(set (match_operand:SI 1 "register_operand")
7369 (plus:SI (match_dup 1)
7370 (match_operand:SI 2 "const_int_operand")))])]
7371 "operands[1] == stack_pointer_rtx
7372 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
7373 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
7374 [(set_attr "type" "arith")
7375 (set_attr "extended_mips16" "yes")])
7377 ;; Thread-Local Storage
7379 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
7380 ;; MIPS architecture defines this register, and no current
7381 ;; implementation provides it; instead, any OS which supports TLS is
7382 ;; expected to trap and emulate this instruction. rdhwr is part of the
7383 ;; MIPS 32r2 specification, but we use it on any architecture because
7384 ;; we expect it to be emulated. Use .set to force the assembler to
7387 ;; We do not use a constraint to force the destination to be $3
7388 ;; because $3 can appear explicitly as a function return value.
7389 ;; If we leave the use of $3 implicit in the constraints until
7390 ;; reload, we may end up making a $3 return value live across
7391 ;; the instruction, leading to a spill failure when reloading it.
7392 (define_insn_and_split "tls_get_tp_<mode>"
7393 [(set (match_operand:P 0 "register_operand" "=d")
7394 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
7395 (clobber (reg:P TLS_GET_TP_REGNUM))]
7396 "HAVE_AS_TLS && !TARGET_MIPS16"
7398 "&& reload_completed"
7399 [(set (reg:P TLS_GET_TP_REGNUM)
7400 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
7401 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
7403 [(set_attr "type" "unknown")
7404 (set_attr "mode" "<MODE>")
7405 (set_attr "insn_count" "2")])
7407 (define_insn "*tls_get_tp_<mode>_split"
7408 [(set (reg:P TLS_GET_TP_REGNUM)
7409 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
7410 "HAVE_AS_TLS && !TARGET_MIPS16"
7412 if (mips_isa_rev >= 2)
7413 return "rdhwr\t$3,$29";
7415 return ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop";
7417 [(set_attr "type" "unknown")
7418 ; Since rdhwr always generates a trap for now, putting it in a delay
7419 ; slot would make the kernel's emulation of it much slower.
7420 (set_attr "can_delay" "no")
7421 (set_attr "mode" "<MODE>")])
7423 ;; In MIPS16 mode, the TLS base pointer is accessed by a
7424 ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not
7425 ;; accessible in MIPS16.
7427 ;; This is not represented as a call insn, to avoid the
7428 ;; unnecesarry clobbering of caller-save registers by a
7429 ;; function consisting only of: "rdhwr $3,$29; j $31; nop;"
7431 ;; A $25 clobber is added to cater for a $25 load stub added by the
7432 ;; linker to __mips16_rdhwr when the call is made from non-PIC code.
7434 (define_insn_and_split "tls_get_tp_mips16_<mode>"
7435 [(set (match_operand:P 0 "register_operand" "=d")
7436 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")]
7438 (clobber (reg:P TLS_GET_TP_REGNUM))
7439 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7440 (clobber (reg:P RETURN_ADDR_REGNUM))]
7441 "HAVE_AS_TLS && TARGET_MIPS16"
7443 "&& reload_completed"
7444 [(parallel [(set (reg:P TLS_GET_TP_REGNUM)
7445 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP))
7446 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7447 (clobber (reg:P RETURN_ADDR_REGNUM))])
7448 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
7450 [(set_attr "type" "multi")
7451 (set_attr "insn_count" "4")
7452 (set_attr "mode" "<MODE>")])
7454 (define_insn "*tls_get_tp_mips16_call_<mode>"
7455 [(set (reg:P TLS_GET_TP_REGNUM)
7456 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")]
7458 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7459 (clobber (reg:P RETURN_ADDR_REGNUM))]
7460 "HAVE_AS_TLS && TARGET_MIPS16"
7461 { return mips_output_jump (operands, 0, -1, true); }
7462 [(set_attr "type" "call")
7463 (set_attr "insn_count" "3")
7464 (set_attr "mode" "<MODE>")])
7466 ;; Named pattern for expanding thread pointer reference.
7467 (define_expand "get_thread_pointer<mode>"
7468 [(match_operand:P 0 "register_operand" "=d")]
7471 mips_expand_thread_pointer (operands[0]);
7475 ;; __builtin_mips_get_fcsr: move the FCSR into operand 0.
7476 (define_expand "mips_get_fcsr"
7477 [(set (match_operand:SI 0 "register_operand")
7478 (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
7479 "TARGET_HARD_FLOAT_ABI"
7483 mips16_expand_get_fcsr (operands[0]);
7488 (define_insn "*mips_get_fcsr"
7489 [(set (match_operand:SI 0 "register_operand" "=d")
7490 (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))]
7494 ;; See tls_get_tp_mips16_<mode> for why this form is used.
7495 (define_insn "mips_get_fcsr_mips16_<mode>"
7496 [(set (reg:SI GET_FCSR_REGNUM)
7497 (unspec:SI [(match_operand:P 0 "call_insn_operand" "dS")]
7499 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7500 (clobber (reg:P RETURN_ADDR_REGNUM))]
7501 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16"
7502 { return mips_output_jump (operands, 0, -1, true); }
7503 [(set_attr "type" "call")
7504 (set_attr "insn_count" "3")])
7506 ;; __builtin_mips_set_fcsr: move operand 0 into the FCSR.
7507 (define_expand "mips_set_fcsr"
7508 [(unspec_volatile [(match_operand:SI 0 "register_operand")]
7510 "TARGET_HARD_FLOAT_ABI"
7514 mips16_expand_set_fcsr (operands[0]);
7519 (define_insn "*mips_set_fcsr"
7520 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")]
7525 ;; See tls_get_tp_mips16_<mode> for why this form is used.
7526 (define_insn "mips_set_fcsr_mips16_<mode>"
7527 [(unspec_volatile:SI [(match_operand:P 0 "call_insn_operand" "dS")
7528 (reg:SI SET_FCSR_REGNUM)] UNSPEC_SET_FCSR)
7529 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
7530 (clobber (reg:P RETURN_ADDR_REGNUM))]
7531 "TARGET_HARD_FLOAT_ABI && TARGET_MIPS16"
7532 { return mips_output_jump (operands, 0, -1, true); }
7533 [(set_attr "type" "call")
7534 (set_attr "insn_count" "3")])
7536 ;; Match paired HI/SI/SF/DFmode load/stores.
7537 (define_insn "*join2_load_store<JOIN_MODE:mode>"
7538 [(set (match_operand:JOIN_MODE 0 "nonimmediate_operand" "=d,f,m,m")
7539 (match_operand:JOIN_MODE 1 "nonimmediate_operand" "m,m,d,f"))
7540 (set (match_operand:JOIN_MODE 2 "nonimmediate_operand" "=d,f,m,m")
7541 (match_operand:JOIN_MODE 3 "nonimmediate_operand" "m,m,d,f"))]
7542 "ENABLE_LD_ST_PAIRS && reload_completed"
7544 bool load_p = (which_alternative == 0 || which_alternative == 1);
7545 /* Reg-renaming pass reuses base register if it is dead after bonded loads.
7546 Hardware does not bond those loads, even when they are consecutive.
7547 However, order of the loads need to be checked for correctness. */
7548 if (!load_p || !reg_overlap_mentioned_p (operands[0], operands[1]))
7550 output_asm_insn (mips_output_move (operands[0], operands[1]),
7552 output_asm_insn (mips_output_move (operands[2], operands[3]),
7557 output_asm_insn (mips_output_move (operands[2], operands[3]),
7559 output_asm_insn (mips_output_move (operands[0], operands[1]),
7564 [(set_attr "move_type" "load,fpload,store,fpstore")
7565 (set_attr "insn_count" "2,2,2,2")])
7567 ;; 2 HI/SI/SF/DF loads are joined.
7568 ;; P5600 does not support bonding of two LBs, hence QI mode is not included.
7569 ;; The loads must be non-volatile as they might be reordered at the time of asm
7572 [(set (match_operand:JOIN_MODE 0 "register_operand")
7573 (match_operand:JOIN_MODE 1 "non_volatile_mem_operand"))
7574 (set (match_operand:JOIN_MODE 2 "register_operand")
7575 (match_operand:JOIN_MODE 3 "non_volatile_mem_operand"))]
7577 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, true)"
7578 [(parallel [(set (match_dup 0)
7584 ;; 2 HI/SI/SF/DF stores are joined.
7585 ;; P5600 does not support bonding of two SBs, hence QI mode is not included.
7587 [(set (match_operand:JOIN_MODE 0 "memory_operand")
7588 (match_operand:JOIN_MODE 1 "register_operand"))
7589 (set (match_operand:JOIN_MODE 2 "memory_operand")
7590 (match_operand:JOIN_MODE 3 "register_operand"))]
7592 && mips_load_store_bonding_p (operands, <JOIN_MODE:MODE>mode, false)"
7593 [(parallel [(set (match_dup 0)
7599 ;; Match paired HImode loads.
7600 (define_insn "*join2_loadhi"
7601 [(set (match_operand:SI 0 "register_operand" "=r")
7602 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand" "m")))
7603 (set (match_operand:SI 2 "register_operand" "=r")
7604 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand" "m")))]
7605 "ENABLE_LD_ST_PAIRS && reload_completed"
7607 /* Reg-renaming pass reuses base register if it is dead after bonded loads.
7608 Hardware does not bond those loads, even when they are consecutive.
7609 However, order of the loads need to be checked for correctness. */
7610 if (!reg_overlap_mentioned_p (operands[0], operands[1]))
7612 output_asm_insn ("lh<u>\t%0,%1", operands);
7613 output_asm_insn ("lh<u>\t%2,%3", operands);
7617 output_asm_insn ("lh<u>\t%2,%3", operands);
7618 output_asm_insn ("lh<u>\t%0,%1", operands);
7623 [(set_attr "move_type" "load")
7624 (set_attr "insn_count" "2")])
7627 ;; 2 HI loads are joined.
7629 [(set (match_operand:SI 0 "register_operand")
7630 (any_extend:SI (match_operand:HI 1 "non_volatile_mem_operand")))
7631 (set (match_operand:SI 2 "register_operand")
7632 (any_extend:SI (match_operand:HI 3 "non_volatile_mem_operand")))]
7634 && mips_load_store_bonding_p (operands, HImode, true)"
7635 [(parallel [(set (match_dup 0)
7636 (any_extend:SI (match_dup 1)))
7638 (any_extend:SI (match_dup 3)))])]
7642 ;; Synchronization instructions.
7646 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
7648 (include "mips-ps-3d.md")
7650 ; The MIPS DSP Instructions.
7652 (include "mips-dsp.md")
7654 ; The MIPS DSP REV 2 Instructions.
7656 (include "mips-dspr2.md")
7658 ; MIPS fixed-point instructions.
7659 (include "mips-fixed.md")
7661 ; microMIPS patterns.
7662 (include "micromips.md")
7664 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
7665 (include "loongson.md")
7667 ; The MIPS MSA Instructions.
7668 (include "mips-msa.md")
7670 (define_c_enum "unspec" [
7671 UNSPEC_ADDRESS_FIRST