1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
4 ;; Changes by Michael Meissner, meissner@osf.org
5 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 ;; Brendan Eich, brendan@microunity.com.
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 (define_enum "processor" [
69 (define_c_enum "unspec" [
70 ;; Unaligned accesses.
76 ;; Floating-point moves.
92 UNSPEC_POTENTIAL_CPRESTORE
97 UNSPEC_SET_GOT_VERSION
98 UNSPEC_UPDATE_GOT_VERSION
100 ;; Symbolic accesses.
105 UNSPEC_UNSHIFTED_HIGH
107 ;; MIPS16 constant pools.
109 UNSPEC_CONSTTABLE_INT
110 UNSPEC_CONSTTABLE_FLOAT
112 ;; Blockage and synchronisation.
119 ;; Cache manipulation.
121 UNSPEC_R10K_CACHE_BARRIER
123 ;; Interrupt handling.
131 ;; Used in a call expression in place of args_size. It's present for PIC
132 ;; indirect calls where it contains args_size and the function symbol.
135 ;; MIPS16 casesi jump table dispatch.
136 UNSPEC_CASESI_DISPATCH
139 UNSPEC_PROBE_STACK_RANGE
143 [(TLS_GET_TP_REGNUM 3)
145 (PIC_FUNCTION_ADDR_REGNUM 25)
146 (RETURN_ADDR_REGNUM 31)
147 (CPRESTORE_SLOT_REGNUM 76)
148 (GOT_VERSION_REGNUM 79)
150 ;; PIC long branch sequences are never longer than 100 bytes.
151 (MAX_PIC_BRANCH_LENGTH 100)
155 (include "predicates.md")
156 (include "constraints.md")
158 ;; ....................
162 ;; ....................
164 (define_attr "got" "unset,xgot_high,load"
165 (const_string "unset"))
167 ;; For jal instructions, this attribute is DIRECT when the target address
168 ;; is symbolic and INDIRECT when it is a register.
169 (define_attr "jal" "unset,direct,indirect"
170 (const_string "unset"))
172 ;; This attribute is YES if the instruction is a jal macro (not a
173 ;; real jal instruction).
175 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
176 ;; an instruction to restore $gp. Direct jals are also macros for
177 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
179 (define_attr "jal_macro" "no,yes"
180 (cond [(eq_attr "jal" "direct")
181 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
182 ? JAL_MACRO_YES : JAL_MACRO_NO)")
183 (eq_attr "jal" "indirect")
184 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
185 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
186 (const_string "no")))
188 ;; Classification of moves, extensions and truncations. Most values
189 ;; are as for "type" (see below) but there are also the following
190 ;; move-specific values:
192 ;; constN move an N-constraint integer into a MIPS16 register
193 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
194 ;; to produce a sign-extended DEST, even if SRC is not
195 ;; properly sign-extended
196 ;; ext_ins EXT, DEXT, INS or DINS instruction
197 ;; andi a single ANDI instruction
198 ;; loadpool move a constant into a MIPS16 register by loading it
200 ;; shift_shift a shift left followed by a shift right
202 ;; This attribute is used to determine the instruction's length and
203 ;; scheduling type. For doubleword moves, the attribute always describes
204 ;; the split instructions; in some cases, it is more appropriate for the
205 ;; scheduling type to be "multi" instead.
206 (define_attr "move_type"
207 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove,
208 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
210 (const_string "unknown"))
212 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
213 (const_string "unknown"))
215 ;; Main data type used by the insn
216 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
217 (const_string "unknown"))
219 ;; True if the main data type is twice the size of a word.
220 (define_attr "dword_mode" "no,yes"
221 (cond [(and (eq_attr "mode" "DI,DF")
222 (not (match_test "TARGET_64BIT")))
225 (and (eq_attr "mode" "TI,TF")
226 (match_test "TARGET_64BIT"))
227 (const_string "yes")]
228 (const_string "no")))
230 ;; Attributes describing a sync loop. These loops have the form:
232 ;; if (RELEASE_BARRIER == YES) sync
234 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
235 ;; CMP = 0 [delay slot]
236 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
237 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
238 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
239 ;; $AT |= $TMP1 | $TMP3
240 ;; if (!commit (*MEM = $AT)) goto 1.
241 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
243 ;; if (ACQUIRE_BARRIER == YES) sync
246 ;; where "$" values are temporaries and where the other values are
247 ;; specified by the attributes below. Values are specified as operand
248 ;; numbers and insns are specified as enums. If no operand number is
249 ;; specified, the following values are used instead:
254 ;; - INCLUSIVE_MASK: -1
255 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
256 ;; - EXCLUSIVE_MASK: 0
258 ;; MEM and INSN1_OP2 are required.
260 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
261 ;; but the gen* programs don't yet support that.
262 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
263 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
264 (define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
265 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
266 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
267 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
268 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
269 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
270 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
271 (const_string "move"))
272 (define_attr "sync_insn2" "nop,and,xor,not"
273 (const_string "nop"))
274 ;; Memory model specifier.
275 ;; "0"-"9" values specify the operand that stores the memory model value.
276 ;; "10" specifies MEMMODEL_ACQ_REL,
277 ;; "11" specifies MEMMODEL_ACQUIRE.
278 (define_attr "sync_memmodel" "" (const_int 10))
280 ;; Accumulator operand for madd patterns.
281 (define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
283 ;; Classification of each insn.
284 ;; branch conditional branch
285 ;; jump unconditional jump
286 ;; call unconditional call
287 ;; load load instruction(s)
288 ;; fpload floating point load
289 ;; fpidxload floating point indexed load
290 ;; store store instruction(s)
291 ;; fpstore floating point store
292 ;; fpidxstore floating point indexed store
293 ;; prefetch memory prefetch (register + offset)
294 ;; prefetchx memory indexed prefetch (register + register)
295 ;; condmove conditional moves
296 ;; mtc transfer to coprocessor
297 ;; mfc transfer from coprocessor
298 ;; mthi transfer to a hi register
299 ;; mtlo transfer to a lo register
300 ;; mfhi transfer from a hi register
301 ;; mflo transfer from a lo register
302 ;; const load constant
303 ;; arith integer arithmetic instructions
304 ;; logical integer logical instructions
305 ;; shift integer shift instructions
306 ;; slt set less than instructions
307 ;; signext sign extend instructions
308 ;; clz the clz and clo instructions
309 ;; pop the pop instruction
310 ;; trap trap if instructions
311 ;; imul integer multiply 2 operands
312 ;; imul3 integer multiply 3 operands
313 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
314 ;; imadd integer multiply-add
315 ;; idiv integer divide 2 operands
316 ;; idiv3 integer divide 3 operands
317 ;; move integer register move ({,D}ADD{,U} with rt = 0)
318 ;; fmove floating point register move
319 ;; fadd floating point add/subtract
320 ;; fmul floating point multiply
321 ;; fmadd floating point multiply-add
322 ;; fdiv floating point divide
323 ;; frdiv floating point reciprocal divide
324 ;; frdiv1 floating point reciprocal divide step 1
325 ;; frdiv2 floating point reciprocal divide step 2
326 ;; fabs floating point absolute value
327 ;; fneg floating point negation
328 ;; fcmp floating point compare
329 ;; fcvt floating point convert
330 ;; fsqrt floating point square root
331 ;; frsqrt floating point reciprocal square root
332 ;; frsqrt1 floating point reciprocal square root step1
333 ;; frsqrt2 floating point reciprocal square root step2
334 ;; dspmac DSP MAC instructions not saturating the accumulator
335 ;; dspmacsat DSP MAC instructions that saturate the accumulator
336 ;; accext DSP accumulator extract instructions
337 ;; accmod DSP accumulator modify instructions
338 ;; dspalu DSP ALU instructions not saturating the result
339 ;; dspalusat DSP ALU instructions that saturate the result
340 ;; multi multiword sequence (or user asm statements)
341 ;; atomic atomic memory update instruction
342 ;; syncloop memory atomic operation implemented as a sync loop
344 ;; ghost an instruction that produces no real code
346 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
347 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
348 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
349 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
350 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
351 multi,atomic,syncloop,nop,ghost"
352 (cond [(eq_attr "jal" "!unset") (const_string "call")
353 (eq_attr "got" "load") (const_string "load")
355 (eq_attr "alu_type" "add,sub") (const_string "arith")
357 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
359 ;; If a doubleword move uses these expensive instructions,
360 ;; it is usually better to schedule them in the same way
361 ;; as the singleword form, rather than as "multi".
362 (eq_attr "move_type" "load") (const_string "load")
363 (eq_attr "move_type" "fpload") (const_string "fpload")
364 (eq_attr "move_type" "store") (const_string "store")
365 (eq_attr "move_type" "fpstore") (const_string "fpstore")
366 (eq_attr "move_type" "mtc") (const_string "mtc")
367 (eq_attr "move_type" "mfc") (const_string "mfc")
368 (eq_attr "move_type" "mtlo") (const_string "mtlo")
369 (eq_attr "move_type" "mflo") (const_string "mflo")
371 ;; These types of move are always single insns.
372 (eq_attr "move_type" "imul") (const_string "imul")
373 (eq_attr "move_type" "fmove") (const_string "fmove")
374 (eq_attr "move_type" "loadpool") (const_string "load")
375 (eq_attr "move_type" "signext") (const_string "signext")
376 (eq_attr "move_type" "ext_ins") (const_string "arith")
377 (eq_attr "move_type" "arith") (const_string "arith")
378 (eq_attr "move_type" "logical") (const_string "logical")
379 (eq_attr "move_type" "sll0") (const_string "shift")
380 (eq_attr "move_type" "andi") (const_string "logical")
382 ;; These types of move are always split.
383 (eq_attr "move_type" "constN,shift_shift")
384 (const_string "multi")
386 ;; These types of move are split for doubleword modes only.
387 (and (eq_attr "move_type" "move,const")
388 (eq_attr "dword_mode" "yes"))
389 (const_string "multi")
390 (eq_attr "move_type" "move") (const_string "move")
391 (eq_attr "move_type" "const") (const_string "const")
392 (eq_attr "sync_mem" "!none") (const_string "syncloop")]
393 (const_string "unknown")))
395 ;; Mode for conversion types (fcvt)
396 ;; I2S integer to float single (SI/DI to SF)
397 ;; I2D integer to float double (SI/DI to DF)
398 ;; S2I float to integer (SF to SI/DI)
399 ;; D2I float to integer (DF to SI/DI)
400 ;; D2S double to float single
401 ;; S2D float single to double
403 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
404 (const_string "unknown"))
406 ;; Is this an extended instruction in mips16 mode?
407 (define_attr "extended_mips16" "no,yes"
408 (if_then_else (ior (eq_attr "move_type" "sll0")
409 (eq_attr "type" "branch")
410 (eq_attr "jal" "direct"))
412 (const_string "no")))
414 ;; Length of instruction in bytes.
415 (define_attr "length" ""
416 (cond [;; Direct branch instructions have a range of [-0x20000,0x1fffc],
417 ;; relative to the address of the delay slot. If a branch is
418 ;; outside this range, we have a choice of two sequences.
419 ;; For PIC, an out-of-range branch like:
424 ;; becomes the equivalent of:
433 ;; The non-PIC case is similar except that we use a direct
434 ;; jump instead of an la/jr pair. Since the target of this
435 ;; jump is an absolute 28-bit bit address (the other bits
436 ;; coming from the address of the delay slot) this form cannot
437 ;; cross a 256MB boundary. We could provide the option of
438 ;; using la/jr in this case too, but we do not do so at
441 ;; The value we specify here does not account for the delay slot
442 ;; instruction, whose length is added separately. If the RTL
443 ;; pattern has no explicit delay slot, mips_adjust_insn_length
444 ;; will add the length of the implicit nop. The range of
445 ;; [-0x20000, 0x1fffc] from the address of the delay slot
446 ;; therefore translates to a range of:
448 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
449 ;; == [-0x1fffc, 0x1fff8]
451 ;; from the shorten_branches reference address.
452 (and (eq_attr "type" "branch")
453 (not (match_test "TARGET_MIPS16")))
454 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 131064))
455 (le (minus (pc) (match_dup 0)) (const_int 131068)))
458 ;; The non-PIC case: branch, first delay slot, and J.
459 (match_test "TARGET_ABSOLUTE_JUMPS")
462 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
463 ;; mips_adjust_insn_length substitutes the correct length.
465 ;; Note that we can't simply use (symbol_ref ...) here
466 ;; because genattrtab needs to know the maximum length
468 (const_int MAX_PIC_BRANCH_LENGTH))
470 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
471 ;; from the address of the following instruction, which leads
474 ;; [-(0x100 - sizeof (branch)), 0xfe]
477 ;; from the shorten_branches reference address. Extended branches
478 ;; likewise have a range of [-0x10000, 0xfffe] from the address
479 ;; of the following instruction, which leads to a range of:
481 ;; [-(0x10000 - sizeof (branch)), 0xfffe]
482 ;; == [-0xfffc, 0xfffe]
484 ;; from the reference address.
486 ;; When a branch is out of range, mips_reorg splits it into a form
487 ;; that uses in-range branches. There are four basic sequences:
489 ;; (1) Absolute addressing with a readable text segment
490 ;; (32-bit addresses):
493 ;; move $1,$2 2 bytes
494 ;; lw $2,label 2 bytes
496 ;; move $2,$1 2 bytes
497 ;; .align 2 0 or 2 bytes
499 ;; .word target 4 bytes
501 ;; (16 bytes in the worst case)
503 ;; (2) Absolute addressing with a readable text segment
504 ;; (64-bit addresses):
507 ;; move $1,$2 2 bytes
508 ;; ld $2,label 2 bytes
510 ;; move $2,$1 2 bytes
511 ;; .align 3 0 to 6 bytes
513 ;; .dword target 8 bytes
515 ;; (24 bytes in the worst case)
517 ;; (3) Absolute addressing without a readable text segment
518 ;; (which requires 32-bit addresses at present):
521 ;; move $1,$2 2 bytes
522 ;; lui $2,%hi(target) 4 bytes
525 ;; addiu $2,%lo(target) 4 bytes
527 ;; move $2,$1 2 bytes
531 ;; (4) PIC addressing (which requires 32-bit addresses at present):
534 ;; move $1,$2 2 bytes
535 ;; lw $2,cprestore 0, 2 or 4 bytes
536 ;; lw $2,%got(target)($2) 4 bytes
537 ;; addiu $2,%lo(target) 4 bytes
539 ;; move $2,$1 2 bytes
541 ;; (20 bytes in the worst case)
543 ;; Note that the conditions test adjusted lengths, whereas the
544 ;; result is an unadjusted length, and is thus twice the true value.
545 (and (eq_attr "type" "branch")
546 (match_test "TARGET_MIPS16"))
547 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
548 (le (minus (pc) (match_dup 0)) (const_int 254)))
550 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
551 (le (minus (pc) (match_dup 0)) (const_int 65532)))
553 (and (match_test "TARGET_ABICALLS")
554 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
556 (match_test "Pmode == SImode")
560 (and (eq_attr "extended_mips16" "yes")
561 (match_test "TARGET_MIPS16"))
564 ;; "Ghost" instructions occupy no space.
565 (eq_attr "type" "ghost")
568 (eq_attr "got" "load")
569 (if_then_else (match_test "TARGET_MIPS16")
572 (eq_attr "got" "xgot_high")
575 ;; In general, constant-pool loads are extended instructions.
576 (eq_attr "move_type" "loadpool")
579 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
580 ;; They are extended instructions on MIPS16 targets.
581 (eq_attr "move_type" "shift_shift")
582 (if_then_else (match_test "TARGET_MIPS16")
586 ;; Check for doubleword moves that are decomposed into two
588 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
589 (eq_attr "dword_mode" "yes"))
592 ;; Doubleword CONST{,N} moves are split into two word
594 (and (eq_attr "move_type" "const,constN")
595 (eq_attr "dword_mode" "yes"))
596 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
598 ;; Otherwise, constants, loads and stores are handled by external
600 (eq_attr "move_type" "const,constN")
601 (symbol_ref "mips_const_insns (operands[1]) * 4")
602 (eq_attr "move_type" "load,fpload")
603 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
604 (eq_attr "move_type" "store,fpstore")
605 (cond [(not (match_test "TARGET_FIX_24K"))
606 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")]
607 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4 + 4"))
609 ;; In the worst case, a call macro will take 8 instructions:
611 ;; lui $25,%call_hi(FOO)
613 ;; lw $25,%call_lo(FOO)($25)
619 (eq_attr "jal_macro" "yes")
622 ;; Various VR4120 errata require a nop to be inserted after a macc
623 ;; instruction. The assembler does this for us, so account for
624 ;; the worst-case length here.
625 (and (eq_attr "type" "imadd")
626 (match_test "TARGET_FIX_VR4120"))
629 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
630 ;; the result of the second one is missed. The assembler should work
631 ;; around this by inserting a nop after the first dmult.
632 (and (eq_attr "type" "imul,imul3")
633 (and (eq_attr "mode" "DI")
634 (match_test "TARGET_FIX_VR4120")))
637 (eq_attr "type" "idiv,idiv3")
638 (symbol_ref "mips_idiv_insns () * 4")
640 (not (eq_attr "sync_mem" "none"))
641 (symbol_ref "mips_sync_loop_insns (insn, operands) * 4")
644 ;; Attribute describing the processor.
645 (define_enum_attr "cpu" "processor"
646 (const (symbol_ref "mips_tune")))
648 ;; The type of hardware hazard associated with this instruction.
649 ;; DELAY means that the next instruction cannot read the result
650 ;; of this one. HILO means that the next two instructions cannot
651 ;; write to HI or LO.
652 (define_attr "hazard" "none,delay,hilo"
653 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
654 (match_test "ISA_HAS_LOAD_DELAY"))
655 (const_string "delay")
657 (and (eq_attr "type" "mfc,mtc")
658 (match_test "ISA_HAS_XFER_DELAY"))
659 (const_string "delay")
661 (and (eq_attr "type" "fcmp")
662 (match_test "ISA_HAS_FCMP_DELAY"))
663 (const_string "delay")
665 ;; The r4000 multiplication patterns include an mflo instruction.
666 (and (eq_attr "type" "imul")
667 (match_test "TARGET_FIX_R4000"))
668 (const_string "hilo")
670 (and (eq_attr "type" "mfhi,mflo")
671 (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
672 (const_string "hilo")]
673 (const_string "none")))
675 ;; Is it a single instruction?
676 (define_attr "single_insn" "no,yes"
677 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
678 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
680 ;; Can the instruction be put into a delay slot?
681 (define_attr "can_delay" "no,yes"
682 (if_then_else (and (eq_attr "type" "!branch,call,jump")
683 (and (eq_attr "hazard" "none")
684 (eq_attr "single_insn" "yes")))
686 (const_string "no")))
688 ;; Attribute defining whether or not we can use the branch-likely
690 (define_attr "branch_likely" "no,yes"
691 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
693 (const_string "no")))
695 ;; True if an instruction might assign to hi or lo when reloaded.
696 ;; This is used by the TUNE_MACC_CHAINS code.
697 (define_attr "may_clobber_hilo" "no,yes"
698 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
700 (const_string "no")))
702 ;; Describe a user's asm statement.
703 (define_asm_attributes
704 [(set_attr "type" "multi")
705 (set_attr "can_delay" "no")])
707 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
708 ;; from the same template.
709 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
711 ;; A copy of GPR that can be used when a pattern has two independent
713 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
715 ;; This mode iterator allows :HILO to be used as the mode of the
716 ;; concatenated HI and LO registers.
717 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
719 ;; This mode iterator allows :P to be used for patterns that operate on
720 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
721 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
723 ;; This mode iterator allows :MOVECC to be used anywhere that a
724 ;; conditional-move-type condition is needed.
725 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
726 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
728 ;; 32-bit integer moves for which we provide move patterns.
729 (define_mode_iterator IMOVE32
738 (V4UQQ "TARGET_DSP")])
740 ;; 64-bit modes for which we provide move patterns.
741 (define_mode_iterator MOVE64
743 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
744 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
745 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
746 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
748 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
749 (define_mode_iterator MOVE128 [TI TF])
751 ;; This mode iterator allows the QI and HI extension patterns to be
752 ;; defined from the same template.
753 (define_mode_iterator SHORT [QI HI])
755 ;; Likewise the 64-bit truncate-and-shift patterns.
756 (define_mode_iterator SUBDI [QI HI SI])
758 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
759 ;; floating-point mode is allowed.
760 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
761 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
762 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
764 ;; Like ANYF, but only applies to scalar modes.
765 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
766 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
768 ;; A floating-point mode for which moves involving FPRs may need to be split.
769 (define_mode_iterator SPLITF
770 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
771 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
772 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
773 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
774 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
775 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
776 (TF "TARGET_64BIT && TARGET_FLOAT64")])
778 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
779 ;; 32-bit version and "dsubu" in the 64-bit version.
780 (define_mode_attr d [(SI "") (DI "d")
781 (QQ "") (HQ "") (SQ "") (DQ "d")
782 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
783 (HA "") (SA "") (DA "d")
784 (UHA "") (USA "") (UDA "d")])
786 ;; Same as d but upper-case.
787 (define_mode_attr D [(SI "") (DI "D")
788 (QQ "") (HQ "") (SQ "") (DQ "D")
789 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
790 (HA "") (SA "") (DA "D")
791 (UHA "") (USA "") (UDA "D")])
793 ;; This attribute gives the length suffix for a load or store instruction.
794 ;; The same suffixes work for zero and sign extensions.
795 (define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
796 (define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
798 ;; This attributes gives the mode mask of a SHORT.
799 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
801 ;; Mode attributes for GPR loads.
802 (define_mode_attr load [(SI "lw") (DI "ld")])
803 ;; Instruction names for stores.
804 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
806 ;; Similarly for MIPS IV indexed FPR loads and stores.
807 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
808 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
810 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
811 ;; are different. Some forms of unextended addiu have an 8-bit immediate
812 ;; field but the equivalent daddiu has only a 5-bit field.
813 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
815 ;; This attribute gives the best constraint to use for registers of
817 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
819 ;; This attribute gives the format suffix for floating-point operations.
820 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
822 ;; This attribute gives the upper-case mode name for one unit of a
823 ;; floating-point mode.
824 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
826 ;; This attribute gives the integer mode that has the same size as a
828 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
829 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
830 (HA "HI") (SA "SI") (DA "DI")
831 (UHA "HI") (USA "SI") (UDA "DI")
832 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
833 (V2HQ "SI") (V2HA "SI")])
835 ;; This attribute gives the integer mode that has half the size of
836 ;; the controlling mode.
837 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
838 (V2SI "SI") (V4HI "SI") (V8QI "SI")
841 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
843 ;; In certain cases, div.s and div.ps may have a rounding error
844 ;; and/or wrong inexact flag.
846 ;; Therefore, we only allow div.s if not working around SB-1 rev2
847 ;; errata or if a slight loss of precision is OK.
848 (define_mode_attr divide_condition
849 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
850 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
852 ;; This attribute gives the conditions under which SQRT.fmt instructions
854 (define_mode_attr sqrt_condition
855 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
857 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
858 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
859 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
860 ;; so for safety's sake, we apply this restriction to all targets.
861 (define_mode_attr recip_condition
863 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
864 (V2SF "TARGET_SB1")])
866 ;; This code iterator allows signed and unsigned widening multiplications
867 ;; to use the same template.
868 (define_code_iterator any_extend [sign_extend zero_extend])
870 ;; This code iterator allows the two right shift instructions to be
871 ;; generated from the same template.
872 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
874 ;; This code iterator allows the three shift instructions to be generated
875 ;; from the same template.
876 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
878 ;; This code iterator allows unsigned and signed division to be generated
879 ;; from the same template.
880 (define_code_iterator any_div [div udiv])
882 ;; This code iterator allows unsigned and signed modulus to be generated
883 ;; from the same template.
884 (define_code_iterator any_mod [mod umod])
886 ;; This code iterator allows all native floating-point comparisons to be
887 ;; generated from the same template.
888 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
890 ;; This code iterator is used for comparisons that can be implemented
891 ;; by swapping the operands.
892 (define_code_iterator swapped_fcond [ge gt unge ungt])
894 ;; Equality operators.
895 (define_code_iterator equality_op [eq ne])
897 ;; These code iterators allow the signed and unsigned scc operations to use
898 ;; the same template.
899 (define_code_iterator any_gt [gt gtu])
900 (define_code_iterator any_ge [ge geu])
901 (define_code_iterator any_lt [lt ltu])
902 (define_code_iterator any_le [le leu])
904 (define_code_iterator any_return [return simple_return])
906 ;; <u> expands to an empty string when doing a signed operation and
907 ;; "u" when doing an unsigned operation.
908 (define_code_attr u [(sign_extend "") (zero_extend "u")
916 ;; <U> is like <u> except uppercase.
917 (define_code_attr U [(sign_extend "") (zero_extend "U")])
919 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
920 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
922 ;; <optab> expands to the name of the optab for a particular code.
923 (define_code_attr optab [(ashift "ashl")
932 (simple_return "simple_return")])
934 ;; <insn> expands to the name of the insn that implements a particular code.
935 (define_code_attr insn [(ashift "sll")
944 ;; <immediate_insn> expands to the name of the insn that implements
945 ;; a particular code to operate on immediate values.
946 (define_code_attr immediate_insn [(ior "ori")
950 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
951 (define_code_attr fcond [(unordered "un")
959 ;; Similar, but for swapped conditions.
960 (define_code_attr swapped_fcond [(ge "le")
965 ;; The value of the bit when the branch is taken for branch_bit patterns.
966 ;; Comparison is always against zero so this depends on the operator.
967 (define_code_attr bbv [(eq "0") (ne "1")])
969 ;; This is the inverse value of bbv.
970 (define_code_attr bbinv [(eq "1") (ne "0")])
972 ;; .........................
974 ;; Branch, call and jump delay slots
976 ;; .........................
978 (define_delay (and (eq_attr "type" "branch")
979 (not (match_test "TARGET_MIPS16"))
980 (eq_attr "branch_likely" "yes"))
981 [(eq_attr "can_delay" "yes")
983 (eq_attr "can_delay" "yes")])
985 ;; Branches that don't have likely variants do not annul on false.
986 (define_delay (and (eq_attr "type" "branch")
987 (not (match_test "TARGET_MIPS16"))
988 (eq_attr "branch_likely" "no"))
989 [(eq_attr "can_delay" "yes")
993 (define_delay (eq_attr "type" "jump")
994 [(eq_attr "can_delay" "yes")
998 (define_delay (and (eq_attr "type" "call")
999 (eq_attr "jal_macro" "no"))
1000 [(eq_attr "can_delay" "yes")
1004 ;; Pipeline descriptions.
1006 ;; generic.md provides a fallback for processors without a specific
1007 ;; pipeline description. It is derived from the old define_function_unit
1008 ;; version and uses the "alu" and "imuldiv" units declared below.
1010 ;; Some of the processor-specific files are also derived from old
1011 ;; define_function_unit descriptions and simply override the parts of
1012 ;; generic.md that don't apply. The other processor-specific files
1013 ;; are self-contained.
1014 (define_automaton "alu,imuldiv")
1016 (define_cpu_unit "alu" "alu")
1017 (define_cpu_unit "imuldiv" "imuldiv")
1019 ;; Ghost instructions produce no real code and introduce no hazards.
1020 ;; They exist purely to express an effect on dataflow.
1021 (define_insn_reservation "ghost" 0
1022 (eq_attr "type" "ghost")
1042 (include "10000.md")
1043 (include "loongson2ef.md")
1044 (include "loongson3a.md")
1045 (include "octeon.md")
1047 (include "sr71k.md")
1050 (include "generic.md")
1053 ;; ....................
1055 ;; CONDITIONAL TRAPS
1057 ;; ....................
1061 [(trap_if (const_int 1) (const_int 0))]
1064 if (ISA_HAS_COND_TRAP)
1065 return "teq\t$0,$0";
1066 else if (TARGET_MIPS16)
1071 [(set_attr "type" "trap")])
1073 (define_expand "ctrap<mode>4"
1074 [(trap_if (match_operator 0 "comparison_operator"
1075 [(match_operand:GPR 1 "reg_or_0_operand")
1076 (match_operand:GPR 2 "arith_operand")])
1077 (match_operand 3 "const_0_operand"))]
1080 mips_expand_conditional_trap (operands[0]);
1084 (define_insn "*conditional_trap<mode>"
1085 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1086 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1087 (match_operand:GPR 2 "arith_operand" "dI")])
1091 [(set_attr "type" "trap")])
1094 ;; ....................
1098 ;; ....................
1101 (define_insn "add<mode>3"
1102 [(set (match_operand:ANYF 0 "register_operand" "=f")
1103 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1104 (match_operand:ANYF 2 "register_operand" "f")))]
1106 "add.<fmt>\t%0,%1,%2"
1107 [(set_attr "type" "fadd")
1108 (set_attr "mode" "<UNITMODE>")])
1110 (define_expand "add<mode>3"
1111 [(set (match_operand:GPR 0 "register_operand")
1112 (plus:GPR (match_operand:GPR 1 "register_operand")
1113 (match_operand:GPR 2 "arith_operand")))]
1116 (define_insn "*add<mode>3"
1117 [(set (match_operand:GPR 0 "register_operand" "=d,d")
1118 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
1119 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1124 [(set_attr "alu_type" "add")
1125 (set_attr "mode" "<MODE>")])
1127 (define_insn "*add<mode>3_mips16"
1128 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1129 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1130 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1138 [(set_attr "alu_type" "add")
1139 (set_attr "mode" "<MODE>")
1140 (set_attr_alternative "length"
1141 [(if_then_else (match_operand 2 "m16_simm8_8")
1144 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1147 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1150 (if_then_else (match_operand 2 "m16_simm4_1")
1155 ;; On the mips16, we can sometimes split an add of a constant which is
1156 ;; a 4 byte instruction into two adds which are both 2 byte
1157 ;; instructions. There are two cases: one where we are adding a
1158 ;; constant plus a register to another register, and one where we are
1159 ;; simply adding a constant to a register.
1162 [(set (match_operand:SI 0 "d_operand")
1163 (plus:SI (match_dup 0)
1164 (match_operand:SI 1 "const_int_operand")))]
1165 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1166 && ((INTVAL (operands[1]) > 0x7f
1167 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1168 || (INTVAL (operands[1]) < - 0x80
1169 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1170 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1171 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1173 HOST_WIDE_INT val = INTVAL (operands[1]);
1177 operands[1] = GEN_INT (0x7f);
1178 operands[2] = GEN_INT (val - 0x7f);
1182 operands[1] = GEN_INT (- 0x80);
1183 operands[2] = GEN_INT (val + 0x80);
1188 [(set (match_operand:SI 0 "d_operand")
1189 (plus:SI (match_operand:SI 1 "d_operand")
1190 (match_operand:SI 2 "const_int_operand")))]
1191 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1192 && REGNO (operands[0]) != REGNO (operands[1])
1193 && ((INTVAL (operands[2]) > 0x7
1194 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1195 || (INTVAL (operands[2]) < - 0x8
1196 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1197 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1198 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1200 HOST_WIDE_INT val = INTVAL (operands[2]);
1204 operands[2] = GEN_INT (0x7);
1205 operands[3] = GEN_INT (val - 0x7);
1209 operands[2] = GEN_INT (- 0x8);
1210 operands[3] = GEN_INT (val + 0x8);
1215 [(set (match_operand:DI 0 "d_operand")
1216 (plus:DI (match_dup 0)
1217 (match_operand:DI 1 "const_int_operand")))]
1218 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1219 && ((INTVAL (operands[1]) > 0xf
1220 && INTVAL (operands[1]) <= 0xf + 0xf)
1221 || (INTVAL (operands[1]) < - 0x10
1222 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1223 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1224 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1226 HOST_WIDE_INT val = INTVAL (operands[1]);
1230 operands[1] = GEN_INT (0xf);
1231 operands[2] = GEN_INT (val - 0xf);
1235 operands[1] = GEN_INT (- 0x10);
1236 operands[2] = GEN_INT (val + 0x10);
1241 [(set (match_operand:DI 0 "d_operand")
1242 (plus:DI (match_operand:DI 1 "d_operand")
1243 (match_operand:DI 2 "const_int_operand")))]
1244 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1245 && REGNO (operands[0]) != REGNO (operands[1])
1246 && ((INTVAL (operands[2]) > 0x7
1247 && INTVAL (operands[2]) <= 0x7 + 0xf)
1248 || (INTVAL (operands[2]) < - 0x8
1249 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1250 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1251 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1253 HOST_WIDE_INT val = INTVAL (operands[2]);
1257 operands[2] = GEN_INT (0x7);
1258 operands[3] = GEN_INT (val - 0x7);
1262 operands[2] = GEN_INT (- 0x8);
1263 operands[3] = GEN_INT (val + 0x8);
1267 (define_insn "*addsi3_extended"
1268 [(set (match_operand:DI 0 "register_operand" "=d,d")
1270 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1271 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1272 "TARGET_64BIT && !TARGET_MIPS16"
1276 [(set_attr "alu_type" "add")
1277 (set_attr "mode" "SI")])
1279 ;; Split this insn so that the addiu splitters can have a crack at it.
1280 ;; Use a conservative length estimate until the split.
1281 (define_insn_and_split "*addsi3_extended_mips16"
1282 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1284 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1285 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1286 "TARGET_64BIT && TARGET_MIPS16"
1288 "&& reload_completed"
1289 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1290 { operands[3] = gen_lowpart (SImode, operands[0]); }
1291 [(set_attr "alu_type" "add")
1292 (set_attr "mode" "SI")
1293 (set_attr "extended_mips16" "yes")])
1295 ;; Combiner patterns for unsigned byte-add.
1297 (define_insn "*baddu_si"
1298 [(set (match_operand:SI 0 "register_operand" "=d")
1300 (plus:QI (match_operand:QI 1 "register_operand" "d")
1301 (match_operand:QI 2 "register_operand" "d"))))]
1304 [(set_attr "alu_type" "add")])
1306 (define_insn "*baddu_di<mode>"
1307 [(set (match_operand:GPR 0 "register_operand" "=d")
1309 (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d"))
1310 (truncate:QI (match_operand:DI 2 "register_operand" "d")))))]
1311 "ISA_HAS_BADDU && TARGET_64BIT"
1313 [(set_attr "alu_type" "add")])
1316 ;; ....................
1320 ;; ....................
1323 (define_insn "sub<mode>3"
1324 [(set (match_operand:ANYF 0 "register_operand" "=f")
1325 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1326 (match_operand:ANYF 2 "register_operand" "f")))]
1328 "sub.<fmt>\t%0,%1,%2"
1329 [(set_attr "type" "fadd")
1330 (set_attr "mode" "<UNITMODE>")])
1332 (define_insn "sub<mode>3"
1333 [(set (match_operand:GPR 0 "register_operand" "=d")
1334 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1335 (match_operand:GPR 2 "register_operand" "d")))]
1338 [(set_attr "alu_type" "sub")
1339 (set_attr "mode" "<MODE>")])
1341 (define_insn "*subsi3_extended"
1342 [(set (match_operand:DI 0 "register_operand" "=d")
1344 (minus:SI (match_operand:SI 1 "register_operand" "d")
1345 (match_operand:SI 2 "register_operand" "d"))))]
1348 [(set_attr "alu_type" "sub")
1349 (set_attr "mode" "DI")])
1352 ;; ....................
1356 ;; ....................
1359 (define_expand "mul<mode>3"
1360 [(set (match_operand:SCALARF 0 "register_operand")
1361 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1362 (match_operand:SCALARF 2 "register_operand")))]
1366 (define_insn "*mul<mode>3"
1367 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1368 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1369 (match_operand:SCALARF 2 "register_operand" "f")))]
1370 "!TARGET_4300_MUL_FIX"
1371 "mul.<fmt>\t%0,%1,%2"
1372 [(set_attr "type" "fmul")
1373 (set_attr "mode" "<MODE>")])
1375 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1376 ;; operands may corrupt immediately following multiplies. This is a
1377 ;; simple fix to insert NOPs.
1379 (define_insn "*mul<mode>3_r4300"
1380 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1381 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1382 (match_operand:SCALARF 2 "register_operand" "f")))]
1383 "TARGET_4300_MUL_FIX"
1384 "mul.<fmt>\t%0,%1,%2\;nop"
1385 [(set_attr "type" "fmul")
1386 (set_attr "mode" "<MODE>")
1387 (set_attr "length" "8")])
1389 (define_insn "mulv2sf3"
1390 [(set (match_operand:V2SF 0 "register_operand" "=f")
1391 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1392 (match_operand:V2SF 2 "register_operand" "f")))]
1393 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1395 [(set_attr "type" "fmul")
1396 (set_attr "mode" "SF")])
1398 ;; The original R4000 has a cpu bug. If a double-word or a variable
1399 ;; shift executes while an integer multiplication is in progress, the
1400 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1401 ;; with the mult on the R4000.
1403 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1404 ;; (also valid for MIPS R4000MC processors):
1406 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1407 ;; this errata description.
1408 ;; The following code sequence causes the R4000 to incorrectly
1409 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1410 ;; instruction. If the dsra32 instruction is executed during an
1411 ;; integer multiply, the dsra32 will only shift by the amount in
1412 ;; specified in the instruction rather than the amount plus 32
1414 ;; instruction 1: mult rs,rt integer multiply
1415 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1416 ;; right arithmetic + 32
1417 ;; Workaround: A dsra32 instruction placed after an integer
1418 ;; multiply should not be one of the 11 instructions after the
1419 ;; multiply instruction."
1423 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1424 ;; the following description.
1425 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1426 ;; 64-bit versions) may produce incorrect results under the
1427 ;; following conditions:
1428 ;; 1) An integer multiply is currently executing
1429 ;; 2) These types of shift instructions are executed immediately
1430 ;; following an integer divide instruction.
1432 ;; 1) Make sure no integer multiply is running wihen these
1433 ;; instruction are executed. If this cannot be predicted at
1434 ;; compile time, then insert a "mfhi" to R0 instruction
1435 ;; immediately after the integer multiply instruction. This
1436 ;; will cause the integer multiply to complete before the shift
1438 ;; 2) Separate integer divide and these two classes of shift
1439 ;; instructions by another instruction or a noop."
1441 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1444 (define_expand "mul<mode>3"
1445 [(set (match_operand:GPR 0 "register_operand")
1446 (mult:GPR (match_operand:GPR 1 "register_operand")
1447 (match_operand:GPR 2 "register_operand")))]
1452 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
1453 emit_insn (gen_mul<mode>3_mul3_loongson (operands[0], operands[1],
1455 else if (ISA_HAS_<D>MUL3)
1456 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1457 else if (TARGET_MIPS16)
1459 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
1460 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2]));
1461 emit_move_insn (operands[0], lo);
1463 else if (TARGET_FIX_R4000)
1464 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1467 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1471 (define_insn "mul<mode>3_mul3_loongson"
1472 [(set (match_operand:GPR 0 "register_operand" "=d")
1473 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1474 (match_operand:GPR 2 "register_operand" "d")))]
1475 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A"
1477 if (TARGET_LOONGSON_2EF)
1478 return "<d>multu.g\t%0,%1,%2";
1480 return "gs<d>multu\t%0,%1,%2";
1482 [(set_attr "type" "imul3nc")
1483 (set_attr "mode" "<MODE>")])
1485 (define_insn "mul<mode>3_mul3"
1486 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1487 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1488 (match_operand:GPR 2 "register_operand" "d,d")))
1489 (clobber (match_scratch:GPR 3 "=l,X"))]
1492 if (which_alternative == 1)
1493 return "<d>mult\t%1,%2";
1494 if (<MODE>mode == SImode && TARGET_MIPS3900)
1495 return "mult\t%0,%1,%2";
1496 return "<d>mul\t%0,%1,%2";
1498 [(set_attr "type" "imul3,imul")
1499 (set_attr "mode" "<MODE>")])
1501 ;; If a register gets allocated to LO, and we spill to memory, the reload
1502 ;; will include a move from LO to a GPR. Merge it into the multiplication
1503 ;; if it can set the GPR directly.
1506 ;; Operand 1: GPR (1st multiplication operand)
1507 ;; Operand 2: GPR (2nd multiplication operand)
1508 ;; Operand 3: GPR (destination)
1511 [(set (match_operand:SI 0 "lo_operand")
1512 (mult:SI (match_operand:SI 1 "d_operand")
1513 (match_operand:SI 2 "d_operand")))
1514 (clobber (scratch:SI))])
1515 (set (match_operand:SI 3 "d_operand")
1517 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1520 (mult:SI (match_dup 1)
1522 (clobber (match_dup 0))])])
1524 (define_insn "mul<mode>3_internal"
1525 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
1526 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1527 (match_operand:GPR 2 "register_operand" "d")))]
1530 [(set_attr "type" "imul")
1531 (set_attr "mode" "<MODE>")])
1533 (define_insn "mul<mode>3_r4000"
1534 [(set (match_operand:GPR 0 "register_operand" "=d")
1535 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1536 (match_operand:GPR 2 "register_operand" "d")))
1537 (clobber (match_scratch:GPR 3 "=l"))]
1539 "<d>mult\t%1,%2\;mflo\t%0"
1540 [(set_attr "type" "imul")
1541 (set_attr "mode" "<MODE>")
1542 (set_attr "length" "8")])
1544 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1545 ;; of "mult; mflo". They have the same latency, but the first form gives
1546 ;; us an extra cycle to compute the operands.
1549 ;; Operand 1: GPR (1st multiplication operand)
1550 ;; Operand 2: GPR (2nd multiplication operand)
1551 ;; Operand 3: GPR (destination)
1553 [(set (match_operand:SI 0 "lo_operand")
1554 (mult:SI (match_operand:SI 1 "d_operand")
1555 (match_operand:SI 2 "d_operand")))
1556 (set (match_operand:SI 3 "d_operand")
1558 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1563 (plus:SI (mult:SI (match_dup 1)
1567 (plus:SI (mult:SI (match_dup 1)
1571 ;; Multiply-accumulate patterns
1573 ;; This pattern is first matched by combine, which tries to use the
1574 ;; pattern wherever it can. We don't know until later whether it
1575 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1576 ;; so we need to keep both options open.
1578 ;; The second alternative has a "?" marker because it is generally
1579 ;; one instruction more costly than the first alternative. This "?"
1580 ;; marker is enough to convey the relative costs to the register
1583 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1584 ;; reloads of the other operands, even though operands 4 and 5 need no
1585 ;; copy instructions. Reload therefore thinks that the second alternative
1586 ;; is two reloads more costly than the first. We add "*?*?" to the first
1587 ;; alternative as a counterweight.
1588 (define_insn "*mul_acc_si"
1589 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1590 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1591 (match_operand:SI 2 "register_operand" "d,d"))
1592 (match_operand:SI 3 "register_operand" "0,d")))
1593 (clobber (match_scratch:SI 4 "=X,l"))
1594 (clobber (match_scratch:SI 5 "=X,&d"))]
1595 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1599 [(set_attr "type" "imadd")
1600 (set_attr "accum_in" "3")
1601 (set_attr "mode" "SI")
1602 (set_attr "length" "4,8")])
1604 ;; The same idea applies here. The middle alternative needs one less
1605 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1606 (define_insn "*mul_acc_si_r3900"
1607 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1608 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1609 (match_operand:SI 2 "register_operand" "d,d,d"))
1610 (match_operand:SI 3 "register_operand" "0,l,d")))
1611 (clobber (match_scratch:SI 4 "=X,3,l"))
1612 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1613 "TARGET_MIPS3900 && !TARGET_MIPS16"
1618 [(set_attr "type" "imadd")
1619 (set_attr "accum_in" "3")
1620 (set_attr "mode" "SI")
1621 (set_attr "length" "4,4,8")])
1623 ;; Split *mul_acc_si if both the source and destination accumulator
1626 [(set (match_operand:SI 0 "d_operand")
1627 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1628 (match_operand:SI 2 "d_operand"))
1629 (match_operand:SI 3 "d_operand")))
1630 (clobber (match_operand:SI 4 "lo_operand"))
1631 (clobber (match_operand:SI 5 "d_operand"))]
1633 [(parallel [(set (match_dup 5)
1634 (mult:SI (match_dup 1) (match_dup 2)))
1635 (clobber (match_dup 4))])
1636 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1639 (define_insn "*macc"
1640 [(set (match_operand:SI 0 "register_operand" "=l,d")
1641 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1642 (match_operand:SI 2 "register_operand" "d,d"))
1643 (match_operand:SI 3 "register_operand" "0,l")))
1644 (clobber (match_scratch:SI 4 "=X,3"))]
1647 if (which_alternative == 1)
1648 return "macc\t%0,%1,%2";
1649 else if (TARGET_MIPS5500)
1650 return "madd\t%1,%2";
1652 /* The VR4130 assumes that there is a two-cycle latency between a macc
1653 that "writes" to $0 and an instruction that reads from it. We avoid
1654 this by assigning to $1 instead. */
1655 return "%[macc\t%@,%1,%2%]";
1657 [(set_attr "type" "imadd")
1658 (set_attr "accum_in" "3")
1659 (set_attr "mode" "SI")])
1661 (define_insn "*msac"
1662 [(set (match_operand:SI 0 "register_operand" "=l,d")
1663 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1664 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1665 (match_operand:SI 3 "register_operand" "d,d"))))
1666 (clobber (match_scratch:SI 4 "=X,1"))]
1669 if (which_alternative == 1)
1670 return "msac\t%0,%2,%3";
1671 else if (TARGET_MIPS5500)
1672 return "msub\t%2,%3";
1674 return "msac\t$0,%2,%3";
1676 [(set_attr "type" "imadd")
1677 (set_attr "accum_in" "1")
1678 (set_attr "mode" "SI")])
1680 ;; An msac-like instruction implemented using negation and a macc.
1681 (define_insn_and_split "*msac_using_macc"
1682 [(set (match_operand:SI 0 "register_operand" "=l,d")
1683 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1684 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1685 (match_operand:SI 3 "register_operand" "d,d"))))
1686 (clobber (match_scratch:SI 4 "=X,1"))
1687 (clobber (match_scratch:SI 5 "=d,d"))]
1688 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1690 "&& reload_completed"
1692 (neg:SI (match_dup 3)))
1695 (plus:SI (mult:SI (match_dup 2)
1698 (clobber (match_dup 4))])]
1700 [(set_attr "type" "imadd")
1701 (set_attr "accum_in" "1")
1702 (set_attr "length" "8")])
1704 ;; Patterns generated by the define_peephole2 below.
1706 (define_insn "*macc2"
1707 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1708 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1709 (match_operand:SI 2 "register_operand" "d"))
1711 (set (match_operand:SI 3 "register_operand" "=d")
1712 (plus:SI (mult:SI (match_dup 1)
1715 "ISA_HAS_MACC && reload_completed"
1717 [(set_attr "type" "imadd")
1718 (set_attr "accum_in" "0")
1719 (set_attr "mode" "SI")])
1721 (define_insn "*msac2"
1722 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1723 (minus:SI (match_dup 0)
1724 (mult:SI (match_operand:SI 1 "register_operand" "d")
1725 (match_operand:SI 2 "register_operand" "d"))))
1726 (set (match_operand:SI 3 "register_operand" "=d")
1727 (minus:SI (match_dup 0)
1728 (mult:SI (match_dup 1)
1730 "ISA_HAS_MSAC && reload_completed"
1732 [(set_attr "type" "imadd")
1733 (set_attr "accum_in" "0")
1734 (set_attr "mode" "SI")])
1736 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1740 ;; Operand 1: macc/msac
1741 ;; Operand 2: GPR (destination)
1744 [(set (match_operand:SI 0 "lo_operand")
1745 (match_operand:SI 1 "macc_msac_operand"))
1746 (clobber (scratch:SI))])
1747 (set (match_operand:SI 2 "d_operand")
1750 [(parallel [(set (match_dup 0)
1755 ;; When we have a three-address multiplication instruction, it should
1756 ;; be faster to do a separate multiply and add, rather than moving
1757 ;; something into LO in order to use a macc instruction.
1759 ;; This peephole needs a scratch register to cater for the case when one
1760 ;; of the multiplication operands is the same as the destination.
1762 ;; Operand 0: GPR (scratch)
1764 ;; Operand 2: GPR (addend)
1765 ;; Operand 3: GPR (destination)
1766 ;; Operand 4: macc/msac
1767 ;; Operand 5: new multiplication
1768 ;; Operand 6: new addition/subtraction
1770 [(match_scratch:SI 0 "d")
1771 (set (match_operand:SI 1 "lo_operand")
1772 (match_operand:SI 2 "d_operand"))
1775 [(set (match_operand:SI 3 "d_operand")
1776 (match_operand:SI 4 "macc_msac_operand"))
1777 (clobber (match_dup 1))])]
1778 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1779 [(parallel [(set (match_dup 0)
1781 (clobber (match_dup 1))])
1785 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1786 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1787 operands[2], operands[0]);
1790 ;; Same as above, except LO is the initial target of the macc.
1792 ;; Operand 0: GPR (scratch)
1794 ;; Operand 2: GPR (addend)
1795 ;; Operand 3: macc/msac
1796 ;; Operand 4: GPR (destination)
1797 ;; Operand 5: new multiplication
1798 ;; Operand 6: new addition/subtraction
1800 [(match_scratch:SI 0 "d")
1801 (set (match_operand:SI 1 "lo_operand")
1802 (match_operand:SI 2 "d_operand"))
1806 (match_operand:SI 3 "macc_msac_operand"))
1807 (clobber (scratch:SI))])
1809 (set (match_operand:SI 4 "d_operand")
1811 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1812 [(parallel [(set (match_dup 0)
1814 (clobber (match_dup 1))])
1818 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1819 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1820 operands[2], operands[0]);
1823 ;; See the comment above *mul_add_si for details.
1824 (define_insn "*mul_sub_si"
1825 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1826 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1827 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1828 (match_operand:SI 3 "register_operand" "d,d"))))
1829 (clobber (match_scratch:SI 4 "=X,l"))
1830 (clobber (match_scratch:SI 5 "=X,&d"))]
1831 "GENERATE_MADD_MSUB"
1835 [(set_attr "type" "imadd")
1836 (set_attr "accum_in" "1")
1837 (set_attr "mode" "SI")
1838 (set_attr "length" "4,8")])
1840 ;; Split *mul_sub_si if both the source and destination accumulator
1843 [(set (match_operand:SI 0 "d_operand")
1844 (minus:SI (match_operand:SI 1 "d_operand")
1845 (mult:SI (match_operand:SI 2 "d_operand")
1846 (match_operand:SI 3 "d_operand"))))
1847 (clobber (match_operand:SI 4 "lo_operand"))
1848 (clobber (match_operand:SI 5 "d_operand"))]
1850 [(parallel [(set (match_dup 5)
1851 (mult:SI (match_dup 2) (match_dup 3)))
1852 (clobber (match_dup 4))])
1853 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1856 (define_insn "*muls"
1857 [(set (match_operand:SI 0 "register_operand" "=l,d")
1858 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1859 (match_operand:SI 2 "register_operand" "d,d"))))
1860 (clobber (match_scratch:SI 3 "=X,l"))]
1865 [(set_attr "type" "imul,imul3")
1866 (set_attr "mode" "SI")])
1868 (define_expand "<u>mulsidi3"
1869 [(set (match_operand:DI 0 "register_operand")
1870 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1871 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1872 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
1874 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1875 emit_insn (fn (operands[0], operands[1], operands[2]));
1879 (define_expand "<u>mulsidi3_32bit_mips16"
1880 [(set (match_operand:DI 0 "register_operand")
1881 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1882 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1883 "!TARGET_64BIT && TARGET_MIPS16"
1887 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1888 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1889 emit_move_insn (operands[0], hilo);
1893 ;; As well as being named patterns, these instructions are used by the
1894 ;; __builtin_mips_mult<u>() functions. We must always make those functions
1895 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1896 (define_insn "<u>mulsidi3_32bit"
1897 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
1898 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1899 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1900 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP)"
1902 if (ISA_HAS_DSP_MULT)
1903 return "mult<u>\t%q0,%1,%2";
1905 return "mult<u>\t%1,%2";
1907 [(set_attr "type" "imul")
1908 (set_attr "mode" "SI")])
1910 (define_insn "<u>mulsidi3_32bit_r4000"
1911 [(set (match_operand:DI 0 "register_operand" "=d")
1912 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1913 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1914 (clobber (match_scratch:DI 3 "=x"))]
1915 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP"
1916 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1917 [(set_attr "type" "imul")
1918 (set_attr "mode" "SI")
1919 (set_attr "length" "12")])
1921 (define_insn_and_split "<u>mulsidi3_64bit"
1922 [(set (match_operand:DI 0 "register_operand" "=d")
1923 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1924 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1925 (clobber (match_scratch:TI 3 "=x"))
1926 (clobber (match_scratch:DI 4 "=d"))]
1927 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3 && !TARGET_MIPS16"
1929 "&& reload_completed"
1932 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1933 operands[2], operands[4]));
1936 [(set_attr "type" "imul")
1937 (set_attr "mode" "SI")
1938 (set (attr "length")
1939 (if_then_else (match_test "ISA_HAS_EXT_INS")
1943 (define_expand "<u>mulsidi3_64bit_mips16"
1944 [(set (match_operand:DI 0 "register_operand")
1945 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1946 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1947 "TARGET_64BIT && TARGET_MIPS16"
1949 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1950 operands[2], gen_reg_rtx (DImode)));
1954 (define_expand "<u>mulsidi3_64bit_split"
1955 [(set (match_operand:DI 0 "register_operand")
1956 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1957 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1958 (clobber (match_operand:DI 3 "register_operand"))]
1963 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1964 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1966 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM));
1967 emit_insn (gen_mfhidi_ti (operands[3], hilo));
1969 if (ISA_HAS_EXT_INS)
1970 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32),
1974 /* Zero-extend the low part. */
1975 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32));
1976 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32));
1978 /* Shift the high part into place. */
1979 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32));
1981 /* OR the two halves together. */
1982 mips_emit_binary (IOR, operands[0], operands[0], operands[3]);
1987 (define_insn "<u>mulsidi3_64bit_hilo"
1988 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
1991 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1992 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1994 "TARGET_64BIT && !TARGET_FIX_R4000"
1996 [(set_attr "type" "imul")
1997 (set_attr "mode" "SI")])
1999 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
2000 (define_insn "mulsidi3_64bit_dmul"
2001 [(set (match_operand:DI 0 "register_operand" "=d")
2002 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2003 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2004 (clobber (match_scratch:DI 3 "=l"))]
2005 "TARGET_64BIT && ISA_HAS_DMUL3"
2007 [(set_attr "type" "imul3")
2008 (set_attr "mode" "DI")])
2010 ;; Widening multiply with negation.
2011 (define_insn "*muls<u>_di"
2012 [(set (match_operand:DI 0 "muldiv_target_operand" "=x")
2015 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2016 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2017 "!TARGET_64BIT && ISA_HAS_MULS"
2019 [(set_attr "type" "imul")
2020 (set_attr "mode" "SI")])
2022 ;; As well as being named patterns, these instructions are used by the
2023 ;; __builtin_mips_msub<u>() functions. We must always make those functions
2024 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2026 ;; This leads to a slight inconsistency. We honor any tuning overrides
2027 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
2028 ;; even if !ISA_HAS_DSP_MULT.
2029 (define_insn "<u>msubsidi4"
2030 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2032 (match_operand:DI 3 "muldiv_target_operand" "0")
2034 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2035 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2036 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
2038 if (ISA_HAS_DSP_MULT)
2039 return "msub<u>\t%q0,%1,%2";
2040 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
2041 return "msub<u>\t%1,%2";
2043 return "msac<u>\t$0,%1,%2";
2045 [(set_attr "type" "imadd")
2046 (set_attr "accum_in" "3")
2047 (set_attr "mode" "SI")])
2049 ;; _highpart patterns
2051 (define_expand "<su>mulsi3_highpart"
2052 [(set (match_operand:SI 0 "register_operand")
2055 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2056 (any_extend:DI (match_operand:SI 2 "register_operand")))
2061 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
2064 else if (TARGET_MIPS16)
2065 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2068 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
2073 (define_insn_and_split "<su>mulsi3_highpart_internal"
2074 [(set (match_operand:SI 0 "register_operand" "=d")
2077 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2078 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2080 (clobber (match_scratch:SI 3 "=l"))]
2081 "!ISA_HAS_MULHI && !TARGET_MIPS16"
2082 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2083 "&& reload_completed && !TARGET_FIX_R4000"
2086 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2090 [(set_attr "type" "imul")
2091 (set_attr "mode" "SI")
2092 (set_attr "length" "8")])
2094 (define_expand "<su>mulsi3_highpart_split"
2095 [(set (match_operand:SI 0 "register_operand")
2098 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2099 (any_extend:DI (match_operand:SI 2 "register_operand")))
2107 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2108 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2109 emit_insn (gen_mfhisi_ti (operands[0], hilo));
2113 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2114 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2115 emit_insn (gen_mfhisi_di (operands[0], hilo));
2120 (define_insn "<su>mulsi3_highpart_mulhi_internal"
2121 [(set (match_operand:SI 0 "register_operand" "=d")
2125 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2126 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2128 (clobber (match_scratch:SI 3 "=l"))]
2130 "mulhi<u>\t%0,%1,%2"
2131 [(set_attr "type" "imul3")
2132 (set_attr "mode" "SI")])
2134 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
2135 [(set (match_operand:SI 0 "register_operand" "=d")
2140 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2141 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2143 (clobber (match_scratch:SI 3 "=l"))]
2145 "mulshi<u>\t%0,%1,%2"
2146 [(set_attr "type" "imul3")
2147 (set_attr "mode" "SI")])
2149 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
2150 ;; errata MD(0), which says that dmultu does not always produce the
2152 (define_expand "<su>muldi3_highpart"
2153 [(set (match_operand:DI 0 "register_operand")
2156 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2157 (any_extend:TI (match_operand:DI 2 "register_operand")))
2159 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2162 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2165 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1],
2170 (define_insn_and_split "<su>muldi3_highpart_internal"
2171 [(set (match_operand:DI 0 "register_operand" "=d")
2174 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2175 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2177 (clobber (match_scratch:DI 3 "=l"))]
2180 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2181 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2182 "&& reload_completed && !TARGET_FIX_R4000"
2185 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2189 [(set_attr "type" "imul")
2190 (set_attr "mode" "DI")
2191 (set_attr "length" "8")])
2193 (define_expand "<su>muldi3_highpart_split"
2194 [(set (match_operand:DI 0 "register_operand")
2197 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2198 (any_extend:TI (match_operand:DI 2 "register_operand")))
2204 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2205 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2206 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2210 (define_expand "<u>mulditi3"
2211 [(set (match_operand:TI 0 "register_operand")
2212 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2213 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2214 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2220 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2221 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2222 emit_move_insn (operands[0], hilo);
2224 else if (TARGET_FIX_R4000)
2225 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2227 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2232 (define_insn "<u>mulditi3_internal"
2233 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2234 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2235 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2237 && !TARGET_FIX_R4000
2238 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2240 [(set_attr "type" "imul")
2241 (set_attr "mode" "DI")])
2243 (define_insn "<u>mulditi3_r4000"
2244 [(set (match_operand:TI 0 "register_operand" "=d")
2245 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2246 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2247 (clobber (match_scratch:TI 3 "=x"))]
2250 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2251 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2252 [(set_attr "type" "imul")
2253 (set_attr "mode" "DI")
2254 (set_attr "length" "12")])
2256 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2257 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2259 (define_insn "madsi"
2260 [(set (match_operand:SI 0 "register_operand" "+l")
2261 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2262 (match_operand:SI 2 "register_operand" "d"))
2266 [(set_attr "type" "imadd")
2267 (set_attr "accum_in" "0")
2268 (set_attr "mode" "SI")])
2270 ;; See the comment above <u>msubsidi4 for the relationship between
2271 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2272 (define_insn "<u>maddsidi4"
2273 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2275 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2276 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2277 (match_operand:DI 3 "muldiv_target_operand" "0")))]
2278 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2282 return "mad<u>\t%1,%2";
2283 else if (ISA_HAS_DSP_MULT)
2284 return "madd<u>\t%q0,%1,%2";
2285 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2286 return "madd<u>\t%1,%2";
2288 /* See comment in *macc. */
2289 return "%[macc<u>\t%@,%1,%2%]";
2291 [(set_attr "type" "imadd")
2292 (set_attr "accum_in" "3")
2293 (set_attr "mode" "SI")])
2295 ;; Floating point multiply accumulate instructions.
2297 (define_insn "*madd4<mode>"
2298 [(set (match_operand:ANYF 0 "register_operand" "=f")
2299 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2300 (match_operand:ANYF 2 "register_operand" "f"))
2301 (match_operand:ANYF 3 "register_operand" "f")))]
2302 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2303 "madd.<fmt>\t%0,%3,%1,%2"
2304 [(set_attr "type" "fmadd")
2305 (set_attr "accum_in" "3")
2306 (set_attr "mode" "<UNITMODE>")])
2308 (define_insn "*madd3<mode>"
2309 [(set (match_operand:ANYF 0 "register_operand" "=f")
2310 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2311 (match_operand:ANYF 2 "register_operand" "f"))
2312 (match_operand:ANYF 3 "register_operand" "0")))]
2313 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2314 "madd.<fmt>\t%0,%1,%2"
2315 [(set_attr "type" "fmadd")
2316 (set_attr "accum_in" "3")
2317 (set_attr "mode" "<UNITMODE>")])
2319 (define_insn "*msub4<mode>"
2320 [(set (match_operand:ANYF 0 "register_operand" "=f")
2321 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2322 (match_operand:ANYF 2 "register_operand" "f"))
2323 (match_operand:ANYF 3 "register_operand" "f")))]
2324 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2325 "msub.<fmt>\t%0,%3,%1,%2"
2326 [(set_attr "type" "fmadd")
2327 (set_attr "accum_in" "3")
2328 (set_attr "mode" "<UNITMODE>")])
2330 (define_insn "*msub3<mode>"
2331 [(set (match_operand:ANYF 0 "register_operand" "=f")
2332 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2333 (match_operand:ANYF 2 "register_operand" "f"))
2334 (match_operand:ANYF 3 "register_operand" "0")))]
2335 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2336 "msub.<fmt>\t%0,%1,%2"
2337 [(set_attr "type" "fmadd")
2338 (set_attr "accum_in" "3")
2339 (set_attr "mode" "<UNITMODE>")])
2341 (define_insn "*nmadd4<mode>"
2342 [(set (match_operand:ANYF 0 "register_operand" "=f")
2343 (neg:ANYF (plus:ANYF
2344 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2345 (match_operand:ANYF 2 "register_operand" "f"))
2346 (match_operand:ANYF 3 "register_operand" "f"))))]
2347 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2348 && TARGET_FUSED_MADD
2349 && HONOR_SIGNED_ZEROS (<MODE>mode)
2350 && !HONOR_NANS (<MODE>mode)"
2351 "nmadd.<fmt>\t%0,%3,%1,%2"
2352 [(set_attr "type" "fmadd")
2353 (set_attr "accum_in" "3")
2354 (set_attr "mode" "<UNITMODE>")])
2356 (define_insn "*nmadd3<mode>"
2357 [(set (match_operand:ANYF 0 "register_operand" "=f")
2358 (neg:ANYF (plus:ANYF
2359 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2360 (match_operand:ANYF 2 "register_operand" "f"))
2361 (match_operand:ANYF 3 "register_operand" "0"))))]
2362 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2363 && TARGET_FUSED_MADD
2364 && HONOR_SIGNED_ZEROS (<MODE>mode)
2365 && !HONOR_NANS (<MODE>mode)"
2366 "nmadd.<fmt>\t%0,%1,%2"
2367 [(set_attr "type" "fmadd")
2368 (set_attr "accum_in" "3")
2369 (set_attr "mode" "<UNITMODE>")])
2371 (define_insn "*nmadd4<mode>_fastmath"
2372 [(set (match_operand:ANYF 0 "register_operand" "=f")
2374 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2375 (match_operand:ANYF 2 "register_operand" "f"))
2376 (match_operand:ANYF 3 "register_operand" "f")))]
2377 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2378 && TARGET_FUSED_MADD
2379 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2380 && !HONOR_NANS (<MODE>mode)"
2381 "nmadd.<fmt>\t%0,%3,%1,%2"
2382 [(set_attr "type" "fmadd")
2383 (set_attr "accum_in" "3")
2384 (set_attr "mode" "<UNITMODE>")])
2386 (define_insn "*nmadd3<mode>_fastmath"
2387 [(set (match_operand:ANYF 0 "register_operand" "=f")
2389 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2390 (match_operand:ANYF 2 "register_operand" "f"))
2391 (match_operand:ANYF 3 "register_operand" "0")))]
2392 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2393 && TARGET_FUSED_MADD
2394 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2395 && !HONOR_NANS (<MODE>mode)"
2396 "nmadd.<fmt>\t%0,%1,%2"
2397 [(set_attr "type" "fmadd")
2398 (set_attr "accum_in" "3")
2399 (set_attr "mode" "<UNITMODE>")])
2401 (define_insn "*nmsub4<mode>"
2402 [(set (match_operand:ANYF 0 "register_operand" "=f")
2403 (neg:ANYF (minus:ANYF
2404 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2405 (match_operand:ANYF 3 "register_operand" "f"))
2406 (match_operand:ANYF 1 "register_operand" "f"))))]
2407 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2408 && TARGET_FUSED_MADD
2409 && HONOR_SIGNED_ZEROS (<MODE>mode)
2410 && !HONOR_NANS (<MODE>mode)"
2411 "nmsub.<fmt>\t%0,%1,%2,%3"
2412 [(set_attr "type" "fmadd")
2413 (set_attr "accum_in" "1")
2414 (set_attr "mode" "<UNITMODE>")])
2416 (define_insn "*nmsub3<mode>"
2417 [(set (match_operand:ANYF 0 "register_operand" "=f")
2418 (neg:ANYF (minus:ANYF
2419 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2420 (match_operand:ANYF 3 "register_operand" "f"))
2421 (match_operand:ANYF 1 "register_operand" "0"))))]
2422 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2423 && TARGET_FUSED_MADD
2424 && HONOR_SIGNED_ZEROS (<MODE>mode)
2425 && !HONOR_NANS (<MODE>mode)"
2426 "nmsub.<fmt>\t%0,%1,%2"
2427 [(set_attr "type" "fmadd")
2428 (set_attr "accum_in" "1")
2429 (set_attr "mode" "<UNITMODE>")])
2431 (define_insn "*nmsub4<mode>_fastmath"
2432 [(set (match_operand:ANYF 0 "register_operand" "=f")
2434 (match_operand:ANYF 1 "register_operand" "f")
2435 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2436 (match_operand:ANYF 3 "register_operand" "f"))))]
2437 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2438 && TARGET_FUSED_MADD
2439 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2440 && !HONOR_NANS (<MODE>mode)"
2441 "nmsub.<fmt>\t%0,%1,%2,%3"
2442 [(set_attr "type" "fmadd")
2443 (set_attr "accum_in" "1")
2444 (set_attr "mode" "<UNITMODE>")])
2446 (define_insn "*nmsub3<mode>_fastmath"
2447 [(set (match_operand:ANYF 0 "register_operand" "=f")
2449 (match_operand:ANYF 1 "register_operand" "f")
2450 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2451 (match_operand:ANYF 3 "register_operand" "0"))))]
2452 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2453 && TARGET_FUSED_MADD
2454 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2455 && !HONOR_NANS (<MODE>mode)"
2456 "nmsub.<fmt>\t%0,%1,%2"
2457 [(set_attr "type" "fmadd")
2458 (set_attr "accum_in" "1")
2459 (set_attr "mode" "<UNITMODE>")])
2462 ;; ....................
2464 ;; DIVISION and REMAINDER
2466 ;; ....................
2469 (define_expand "div<mode>3"
2470 [(set (match_operand:ANYF 0 "register_operand")
2471 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2472 (match_operand:ANYF 2 "register_operand")))]
2473 "<divide_condition>"
2475 if (const_1_operand (operands[1], <MODE>mode))
2476 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2477 operands[1] = force_reg (<MODE>mode, operands[1]);
2480 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2482 ;; If an mfc1 or dmfc1 happens to access the floating point register
2483 ;; file at the same time a long latency operation (div, sqrt, recip,
2484 ;; sqrt) iterates an intermediate result back through the floating
2485 ;; point register file bypass, then instead returning the correct
2486 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2487 ;; result of the long latency operation.
2489 ;; The workaround is to insert an unconditional 'mov' from/to the
2490 ;; long latency op destination register.
2492 (define_insn "*div<mode>3"
2493 [(set (match_operand:ANYF 0 "register_operand" "=f")
2494 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2495 (match_operand:ANYF 2 "register_operand" "f")))]
2496 "<divide_condition>"
2499 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2501 return "div.<fmt>\t%0,%1,%2";
2503 [(set_attr "type" "fdiv")
2504 (set_attr "mode" "<UNITMODE>")
2505 (set (attr "length")
2506 (if_then_else (match_test "TARGET_FIX_SB1")
2510 (define_insn "*recip<mode>3"
2511 [(set (match_operand:ANYF 0 "register_operand" "=f")
2512 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2513 (match_operand:ANYF 2 "register_operand" "f")))]
2514 "<recip_condition> && flag_unsafe_math_optimizations"
2517 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2519 return "recip.<fmt>\t%0,%2";
2521 [(set_attr "type" "frdiv")
2522 (set_attr "mode" "<UNITMODE>")
2523 (set (attr "length")
2524 (if_then_else (match_test "TARGET_FIX_SB1")
2528 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2529 ;; with negative operands. We use special libgcc functions instead.
2530 (define_expand "divmod<mode>4"
2531 [(set (match_operand:GPR 0 "register_operand")
2532 (div:GPR (match_operand:GPR 1 "register_operand")
2533 (match_operand:GPR 2 "register_operand")))
2534 (set (match_operand:GPR 3 "register_operand")
2535 (mod:GPR (match_dup 1)
2537 "!TARGET_FIX_VR4120"
2541 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1],
2543 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2546 emit_insn (gen_divmod<mode>4_internal (operands[0], operands[1],
2547 operands[2], operands[3]));
2551 (define_insn_and_split "divmod<mode>4_internal"
2552 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
2553 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2554 (match_operand:GPR 2 "register_operand" "d")))
2555 (set (match_operand:GPR 3 "register_operand" "=d")
2556 (mod:GPR (match_dup 1)
2558 "!TARGET_FIX_VR4120 && !TARGET_MIPS16"
2560 "&& reload_completed"
2563 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2566 [(set_attr "type" "idiv")
2567 (set_attr "mode" "<MODE>")
2568 (set_attr "length" "8")])
2570 (define_expand "udivmod<mode>4"
2571 [(set (match_operand:GPR 0 "register_operand")
2572 (udiv:GPR (match_operand:GPR 1 "register_operand")
2573 (match_operand:GPR 2 "register_operand")))
2574 (set (match_operand:GPR 3 "register_operand")
2575 (umod:GPR (match_dup 1)
2581 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1],
2583 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2586 emit_insn (gen_udivmod<mode>4_internal (operands[0], operands[1],
2587 operands[2], operands[3]));
2591 (define_insn_and_split "udivmod<mode>4_internal"
2592 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
2593 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2594 (match_operand:GPR 2 "register_operand" "d")))
2595 (set (match_operand:GPR 3 "register_operand" "=d")
2596 (umod:GPR (match_dup 1)
2603 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2606 [(set_attr "type" "idiv")
2607 (set_attr "mode" "<MODE>")
2608 (set_attr "length" "8")])
2610 (define_expand "<u>divmod<mode>4_split"
2611 [(set (match_operand:GPR 0 "register_operand")
2612 (any_mod:GPR (match_operand:GPR 1 "register_operand")
2613 (match_operand:GPR 2 "register_operand")))]
2620 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2621 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1],
2623 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo));
2627 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2628 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1],
2630 emit_insn (gen_mfhi<mode>_di (operands[0], hilo));
2635 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2636 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x")
2638 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2639 (match_operand:GPR 2 "register_operand" "d"))]
2642 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2643 [(set_attr "type" "idiv")
2644 (set_attr "mode" "<GPR:MODE>")])
2647 ;; ....................
2651 ;; ....................
2653 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2654 ;; "*div[sd]f3" comment for details).
2656 (define_insn "sqrt<mode>2"
2657 [(set (match_operand:ANYF 0 "register_operand" "=f")
2658 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2662 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2664 return "sqrt.<fmt>\t%0,%1";
2666 [(set_attr "type" "fsqrt")
2667 (set_attr "mode" "<UNITMODE>")
2668 (set (attr "length")
2669 (if_then_else (match_test "TARGET_FIX_SB1")
2673 (define_insn "*rsqrt<mode>a"
2674 [(set (match_operand:ANYF 0 "register_operand" "=f")
2675 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2676 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2677 "<recip_condition> && flag_unsafe_math_optimizations"
2680 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2682 return "rsqrt.<fmt>\t%0,%2";
2684 [(set_attr "type" "frsqrt")
2685 (set_attr "mode" "<UNITMODE>")
2686 (set (attr "length")
2687 (if_then_else (match_test "TARGET_FIX_SB1")
2691 (define_insn "*rsqrt<mode>b"
2692 [(set (match_operand:ANYF 0 "register_operand" "=f")
2693 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2694 (match_operand:ANYF 2 "register_operand" "f"))))]
2695 "<recip_condition> && flag_unsafe_math_optimizations"
2698 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2700 return "rsqrt.<fmt>\t%0,%2";
2702 [(set_attr "type" "frsqrt")
2703 (set_attr "mode" "<UNITMODE>")
2704 (set (attr "length")
2705 (if_then_else (match_test "TARGET_FIX_SB1")
2710 ;; ....................
2714 ;; ....................
2716 ;; Do not use the integer abs macro instruction, since that signals an
2717 ;; exception on -2147483648 (sigh).
2719 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2720 ;; invalid; it does not clear their sign bits. We therefore can't use
2721 ;; abs.fmt if the signs of NaNs matter.
2723 (define_insn "abs<mode>2"
2724 [(set (match_operand:ANYF 0 "register_operand" "=f")
2725 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2726 "!HONOR_NANS (<MODE>mode)"
2728 [(set_attr "type" "fabs")
2729 (set_attr "mode" "<UNITMODE>")])
2732 ;; ...................
2734 ;; Count leading zeroes.
2736 ;; ...................
2739 (define_insn "clz<mode>2"
2740 [(set (match_operand:GPR 0 "register_operand" "=d")
2741 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2744 [(set_attr "type" "clz")
2745 (set_attr "mode" "<MODE>")])
2748 ;; ...................
2750 ;; Count number of set bits.
2752 ;; ...................
2755 (define_insn "popcount<mode>2"
2756 [(set (match_operand:GPR 0 "register_operand" "=d")
2757 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2760 [(set_attr "type" "pop")
2761 (set_attr "mode" "<MODE>")])
2763 ;; The POP instruction is special as it does not take into account the upper
2764 ;; 32bits and is documented that way.
2765 (define_insn "*popcountdi2_trunc"
2766 [(set (match_operand:SI 0 "register_operand" "=d")
2767 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))]
2768 "ISA_HAS_POP && TARGET_64BIT"
2770 [(set_attr "type" "pop")
2771 (set_attr "mode" "SI")])
2774 ;; ....................
2776 ;; NEGATION and ONE'S COMPLEMENT
2778 ;; ....................
2780 (define_insn "negsi2"
2781 [(set (match_operand:SI 0 "register_operand" "=d")
2782 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2786 return "neg\t%0,%1";
2788 return "subu\t%0,%.,%1";
2790 [(set_attr "alu_type" "sub")
2791 (set_attr "mode" "SI")])
2793 (define_insn "negdi2"
2794 [(set (match_operand:DI 0 "register_operand" "=d")
2795 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2796 "TARGET_64BIT && !TARGET_MIPS16"
2798 [(set_attr "alu_type" "sub")
2799 (set_attr "mode" "DI")])
2801 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2802 ;; invalid; it does not flip their sign bit. We therefore can't use
2803 ;; neg.fmt if the signs of NaNs matter.
2805 (define_insn "neg<mode>2"
2806 [(set (match_operand:ANYF 0 "register_operand" "=f")
2807 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2808 "!HONOR_NANS (<MODE>mode)"
2810 [(set_attr "type" "fneg")
2811 (set_attr "mode" "<UNITMODE>")])
2813 (define_insn "one_cmpl<mode>2"
2814 [(set (match_operand:GPR 0 "register_operand" "=d")
2815 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2819 return "not\t%0,%1";
2821 return "nor\t%0,%.,%1";
2823 [(set_attr "alu_type" "not")
2824 (set_attr "mode" "<MODE>")])
2827 ;; ....................
2831 ;; ....................
2834 ;; Many of these instructions use trivial define_expands, because we
2835 ;; want to use a different set of constraints when TARGET_MIPS16.
2837 (define_expand "and<mode>3"
2838 [(set (match_operand:GPR 0 "register_operand")
2839 (and:GPR (match_operand:GPR 1 "register_operand")
2840 (match_operand:GPR 2 "and_reg_operand")))])
2842 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
2843 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
2844 ;; Note that this variant does not trigger for SI mode because we require
2845 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
2846 ;; sign-extended SImode value.
2848 ;; These are possible combinations for operand 1 and 2. The table
2849 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
2850 ;; 16=MIPS16, x=match, S=split):
2852 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
2858 ;; 0xffff_ffff x S x S x
2863 (define_insn "*and<mode>3"
2864 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d")
2865 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,d,d,d,d")
2866 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,K,Yx,Yw,d")))]
2867 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2871 switch (which_alternative)
2874 operands[1] = gen_lowpart (QImode, operands[1]);
2875 return "lbu\t%0,%1";
2877 operands[1] = gen_lowpart (HImode, operands[1]);
2878 return "lhu\t%0,%1";
2880 operands[1] = gen_lowpart (SImode, operands[1]);
2881 return "lwu\t%0,%1";
2883 return "andi\t%0,%1,%x2";
2885 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
2886 operands[2] = GEN_INT (len);
2887 return "<d>ext\t%0,%1,0,%2";
2891 return "and\t%0,%1,%2";
2896 [(set_attr "move_type" "load,load,load,andi,ext_ins,shift_shift,logical")
2897 (set_attr "mode" "<MODE>")])
2899 (define_insn "*and<mode>3_mips16"
2900 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
2901 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%o,o,W,d,0")
2902 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
2903 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2905 switch (which_alternative)
2908 operands[1] = gen_lowpart (QImode, operands[1]);
2909 return "lbu\t%0,%1";
2911 operands[1] = gen_lowpart (HImode, operands[1]);
2912 return "lhu\t%0,%1";
2914 operands[1] = gen_lowpart (SImode, operands[1]);
2915 return "lwu\t%0,%1";
2919 return "and\t%0,%2";
2924 [(set_attr "move_type" "load,load,load,shift_shift,logical")
2925 (set_attr "mode" "<MODE>")])
2927 (define_expand "ior<mode>3"
2928 [(set (match_operand:GPR 0 "register_operand")
2929 (ior:GPR (match_operand:GPR 1 "register_operand")
2930 (match_operand:GPR 2 "uns_arith_operand")))]
2934 operands[2] = force_reg (<MODE>mode, operands[2]);
2937 (define_insn "*ior<mode>3"
2938 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2939 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2940 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2945 [(set_attr "alu_type" "or")
2946 (set_attr "mode" "<MODE>")])
2948 (define_insn "*ior<mode>3_mips16"
2949 [(set (match_operand:GPR 0 "register_operand" "=d")
2950 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2951 (match_operand:GPR 2 "register_operand" "d")))]
2954 [(set_attr "alu_type" "or")
2955 (set_attr "mode" "<MODE>")])
2957 (define_expand "xor<mode>3"
2958 [(set (match_operand:GPR 0 "register_operand")
2959 (xor:GPR (match_operand:GPR 1 "register_operand")
2960 (match_operand:GPR 2 "uns_arith_operand")))]
2965 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2966 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2967 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2972 [(set_attr "alu_type" "xor")
2973 (set_attr "mode" "<MODE>")])
2976 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2977 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2978 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2984 [(set_attr "alu_type" "xor")
2985 (set_attr "mode" "<MODE>")
2986 (set_attr_alternative "length"
2988 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2993 (define_insn "*nor<mode>3"
2994 [(set (match_operand:GPR 0 "register_operand" "=d")
2995 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2996 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2999 [(set_attr "alu_type" "nor")
3000 (set_attr "mode" "<MODE>")])
3003 ;; ....................
3007 ;; ....................
3011 (define_insn "truncdfsf2"
3012 [(set (match_operand:SF 0 "register_operand" "=f")
3013 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3014 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3016 [(set_attr "type" "fcvt")
3017 (set_attr "cnv_mode" "D2S")
3018 (set_attr "mode" "SF")])
3020 ;; Integer truncation patterns. Truncating SImode values to smaller
3021 ;; modes is a no-op, as it is for most other GCC ports. Truncating
3022 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
3023 ;; need to make sure that the lower 32 bits are properly sign-extended
3024 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
3025 ;; smaller than SImode is equivalent to two separate truncations:
3028 ;; DI ---> HI == DI ---> SI ---> HI
3029 ;; DI ---> QI == DI ---> SI ---> QI
3031 ;; Step A needs a real instruction but step B does not.
3033 (define_insn "truncdi<mode>2"
3034 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
3035 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
3040 [(set_attr "move_type" "sll0,store")
3041 (set_attr "mode" "SI")])
3043 ;; Combiner patterns to optimize shift/truncate combinations.
3045 (define_insn "*ashr_trunc<mode>"
3046 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3048 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3049 (match_operand:DI 2 "const_arith_operand" ""))))]
3050 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3052 [(set_attr "type" "shift")
3053 (set_attr "mode" "<MODE>")])
3055 (define_insn "*lshr32_trunc<mode>"
3056 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3058 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3060 "TARGET_64BIT && !TARGET_MIPS16"
3062 [(set_attr "type" "shift")
3063 (set_attr "mode" "<MODE>")])
3065 ;; Logical shift by more than 32 results in proper SI values so truncation is
3066 ;; removed by the middle end. Note that a logical shift by 32 is handled by
3067 ;; the previous pattern.
3068 (define_insn "*<optab>_trunc<mode>_exts"
3069 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3071 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
3072 (match_operand:DI 2 "const_arith_operand" ""))))]
3073 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
3075 [(set_attr "type" "arith")
3076 (set_attr "mode" "<MODE>")])
3079 ;; ....................
3083 ;; ....................
3087 (define_expand "zero_extendsidi2"
3088 [(set (match_operand:DI 0 "register_operand")
3089 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
3092 (define_insn_and_split "*zero_extendsidi2"
3093 [(set (match_operand:DI 0 "register_operand" "=d,d")
3094 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3095 "TARGET_64BIT && !ISA_HAS_EXT_INS"
3099 "&& reload_completed && REG_P (operands[1])"
3101 (ashift:DI (match_dup 1) (const_int 32)))
3103 (lshiftrt:DI (match_dup 0) (const_int 32)))]
3104 { operands[1] = gen_lowpart (DImode, operands[1]); }
3105 [(set_attr "move_type" "shift_shift,load")
3106 (set_attr "mode" "DI")])
3108 (define_insn "*zero_extendsidi2_dext"
3109 [(set (match_operand:DI 0 "register_operand" "=d,d")
3110 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3111 "TARGET_64BIT && ISA_HAS_EXT_INS"
3115 [(set_attr "move_type" "arith,load")
3116 (set_attr "mode" "DI")])
3118 ;; See the comment before the *and<mode>3 pattern why this is generated by
3122 [(set (match_operand:DI 0 "register_operand")
3123 (and:DI (match_operand:DI 1 "register_operand")
3124 (const_int 4294967295)))]
3125 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
3127 (ashift:DI (match_dup 1) (const_int 32)))
3129 (lshiftrt:DI (match_dup 0) (const_int 32)))])
3131 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
3132 [(set (match_operand:GPR 0 "register_operand")
3133 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3136 if (TARGET_MIPS16 && !GENERATE_MIPS16E
3137 && !memory_operand (operands[1], <SHORT:MODE>mode))
3139 emit_insn (gen_and<GPR:mode>3 (operands[0],
3140 gen_lowpart (<GPR:MODE>mode, operands[1]),
3141 force_reg (<GPR:MODE>mode,
3142 GEN_INT (<SHORT:mask>))));
3147 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
3148 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3150 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3153 andi\t%0,%1,<SHORT:mask>
3154 l<SHORT:size>u\t%0,%1"
3155 [(set_attr "move_type" "andi,load")
3156 (set_attr "mode" "<GPR:MODE>")])
3158 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
3159 [(set (match_operand:GPR 0 "register_operand" "=d")
3160 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
3162 "ze<SHORT:size>\t%0"
3163 ;; This instruction is effectively a special encoding of ANDI.
3164 [(set_attr "move_type" "andi")
3165 (set_attr "mode" "<GPR:MODE>")])
3167 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
3168 [(set (match_operand:GPR 0 "register_operand" "=d")
3169 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
3171 "l<SHORT:size>u\t%0,%1"
3172 [(set_attr "move_type" "load")
3173 (set_attr "mode" "<GPR:MODE>")])
3175 (define_expand "zero_extendqihi2"
3176 [(set (match_operand:HI 0 "register_operand")
3177 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3180 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
3182 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
3188 (define_insn "*zero_extendqihi2"
3189 [(set (match_operand:HI 0 "register_operand" "=d,d")
3190 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3195 [(set_attr "move_type" "andi,load")
3196 (set_attr "mode" "HI")])
3198 (define_insn "*zero_extendqihi2_mips16"
3199 [(set (match_operand:HI 0 "register_operand" "=d")
3200 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3203 [(set_attr "move_type" "load")
3204 (set_attr "mode" "HI")])
3206 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3208 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
3209 [(set (match_operand:GPR 0 "register_operand" "=d")
3211 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3212 "TARGET_64BIT && !TARGET_MIPS16"
3214 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3215 return "andi\t%0,%1,%x2";
3217 [(set_attr "alu_type" "and")
3218 (set_attr "mode" "<GPR:MODE>")])
3220 (define_insn "*zero_extendhi_truncqi"
3221 [(set (match_operand:HI 0 "register_operand" "=d")
3223 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3224 "TARGET_64BIT && !TARGET_MIPS16"
3226 [(set_attr "alu_type" "and")
3227 (set_attr "mode" "HI")])
3230 ;; ....................
3234 ;; ....................
3237 ;; Those for integer source operand are ordered widest source type first.
3239 ;; When TARGET_64BIT, all SImode integer and accumulator registers
3240 ;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
3241 ;; and truncdisi2). We can therefore get rid of register->register
3242 ;; instructions if we constrain the source to be in the same register as
3245 ;; Only the pre-reload scheduler sees the type of the register alternatives;
3246 ;; we split them into nothing before the post-reload scheduler runs.
3247 ;; These alternatives therefore have type "move" in order to reflect
3248 ;; what happens if the two pre-reload operands cannot be tied, and are
3249 ;; instead allocated two separate GPRs. We don't distinguish between
3250 ;; the GPR and LO cases because we don't usually know during pre-reload
3251 ;; scheduling whether an operand will be LO or not.
3252 (define_insn_and_split "extendsidi2"
3253 [(set (match_operand:DI 0 "register_operand" "=d,l,d")
3254 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
3260 "&& reload_completed && register_operand (operands[1], VOIDmode)"
3263 emit_note (NOTE_INSN_DELETED);
3266 [(set_attr "move_type" "move,move,load")
3267 (set_attr "mode" "DI")])
3269 (define_expand "extend<SHORT:mode><GPR:mode>2"
3270 [(set (match_operand:GPR 0 "register_operand")
3271 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3274 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
3275 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3276 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3280 l<SHORT:size>\t%0,%1"
3281 [(set_attr "move_type" "signext,load")
3282 (set_attr "mode" "<GPR:MODE>")])
3284 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3285 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3287 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3288 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3291 l<SHORT:size>\t%0,%1"
3292 "&& reload_completed && REG_P (operands[1])"
3293 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3294 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3296 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3297 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3298 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3300 [(set_attr "move_type" "shift_shift,load")
3301 (set_attr "mode" "<GPR:MODE>")])
3303 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3304 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3306 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3309 se<SHORT:size>\t%0,%1
3310 l<SHORT:size>\t%0,%1"
3311 [(set_attr "move_type" "signext,load")
3312 (set_attr "mode" "<GPR:MODE>")])
3314 (define_expand "extendqihi2"
3315 [(set (match_operand:HI 0 "register_operand")
3316 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3319 (define_insn "*extendqihi2_mips16e"
3320 [(set (match_operand:HI 0 "register_operand" "=d,d")
3321 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3326 [(set_attr "move_type" "signext,load")
3327 (set_attr "mode" "SI")])
3329 (define_insn_and_split "*extendqihi2"
3330 [(set (match_operand:HI 0 "register_operand" "=d,d")
3332 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3333 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3337 "&& reload_completed && REG_P (operands[1])"
3338 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3339 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3341 operands[0] = gen_lowpart (SImode, operands[0]);
3342 operands[1] = gen_lowpart (SImode, operands[1]);
3343 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3344 - GET_MODE_BITSIZE (QImode));
3346 [(set_attr "move_type" "shift_shift,load")
3347 (set_attr "mode" "SI")])
3349 (define_insn "*extendqihi2_seb"
3350 [(set (match_operand:HI 0 "register_operand" "=d,d")
3352 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3357 [(set_attr "move_type" "signext,load")
3358 (set_attr "mode" "SI")])
3360 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3361 ;; use the shift/truncate patterns.
3363 (define_insn_and_split "*extenddi_truncate<mode>"
3364 [(set (match_operand:DI 0 "register_operand" "=d")
3366 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3367 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3369 "&& reload_completed"
3371 (ashift:DI (match_dup 1)
3374 (ashiftrt:DI (match_dup 2)
3377 operands[2] = gen_lowpart (DImode, operands[0]);
3378 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3380 [(set_attr "move_type" "shift_shift")
3381 (set_attr "mode" "DI")])
3383 (define_insn_and_split "*extendsi_truncate<mode>"
3384 [(set (match_operand:SI 0 "register_operand" "=d")
3386 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3387 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3389 "&& reload_completed"
3391 (ashift:DI (match_dup 1)
3394 (truncate:SI (ashiftrt:DI (match_dup 2)
3397 operands[2] = gen_lowpart (DImode, operands[0]);
3398 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3400 [(set_attr "move_type" "shift_shift")
3401 (set_attr "mode" "SI")])
3403 (define_insn_and_split "*extendhi_truncateqi"
3404 [(set (match_operand:HI 0 "register_operand" "=d")
3406 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3407 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3409 "&& reload_completed"
3411 (ashift:DI (match_dup 1)
3414 (truncate:HI (ashiftrt:DI (match_dup 2)
3417 operands[2] = gen_lowpart (DImode, operands[0]);
3419 [(set_attr "move_type" "shift_shift")
3420 (set_attr "mode" "SI")])
3422 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3423 [(set (match_operand:GPR 0 "register_operand" "=d")
3425 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3426 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3428 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3429 return "exts\t%0,%1,0,%m2";
3431 [(set_attr "type" "arith")
3432 (set_attr "mode" "<GPR:MODE>")])
3434 (define_insn "*extendhi_truncateqi_exts"
3435 [(set (match_operand:HI 0 "register_operand" "=d")
3437 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3438 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3440 [(set_attr "type" "arith")
3441 (set_attr "mode" "SI")])
3443 (define_insn "extendsfdf2"
3444 [(set (match_operand:DF 0 "register_operand" "=f")
3445 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3446 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3448 [(set_attr "type" "fcvt")
3449 (set_attr "cnv_mode" "S2D")
3450 (set_attr "mode" "DF")])
3453 ;; ....................
3457 ;; ....................
3459 (define_expand "fix_truncdfsi2"
3460 [(set (match_operand:SI 0 "register_operand")
3461 (fix:SI (match_operand:DF 1 "register_operand")))]
3462 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3464 if (!ISA_HAS_TRUNC_W)
3466 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3471 (define_insn "fix_truncdfsi2_insn"
3472 [(set (match_operand:SI 0 "register_operand" "=f")
3473 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3474 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3476 [(set_attr "type" "fcvt")
3477 (set_attr "mode" "DF")
3478 (set_attr "cnv_mode" "D2I")])
3480 (define_insn "fix_truncdfsi2_macro"
3481 [(set (match_operand:SI 0 "register_operand" "=f")
3482 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3483 (clobber (match_scratch:DF 2 "=d"))]
3484 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3486 if (mips_nomacro.nesting_level > 0)
3487 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3489 return "trunc.w.d %0,%1,%2";
3491 [(set_attr "type" "fcvt")
3492 (set_attr "mode" "DF")
3493 (set_attr "cnv_mode" "D2I")
3494 (set_attr "length" "36")])
3496 (define_expand "fix_truncsfsi2"
3497 [(set (match_operand:SI 0 "register_operand")
3498 (fix:SI (match_operand:SF 1 "register_operand")))]
3501 if (!ISA_HAS_TRUNC_W)
3503 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3508 (define_insn "fix_truncsfsi2_insn"
3509 [(set (match_operand:SI 0 "register_operand" "=f")
3510 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3511 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3513 [(set_attr "type" "fcvt")
3514 (set_attr "mode" "SF")
3515 (set_attr "cnv_mode" "S2I")])
3517 (define_insn "fix_truncsfsi2_macro"
3518 [(set (match_operand:SI 0 "register_operand" "=f")
3519 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3520 (clobber (match_scratch:SF 2 "=d"))]
3521 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3523 if (mips_nomacro.nesting_level > 0)
3524 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3526 return "trunc.w.s %0,%1,%2";
3528 [(set_attr "type" "fcvt")
3529 (set_attr "mode" "SF")
3530 (set_attr "cnv_mode" "S2I")
3531 (set_attr "length" "36")])
3534 (define_insn "fix_truncdfdi2"
3535 [(set (match_operand:DI 0 "register_operand" "=f")
3536 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3537 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3539 [(set_attr "type" "fcvt")
3540 (set_attr "mode" "DF")
3541 (set_attr "cnv_mode" "D2I")])
3544 (define_insn "fix_truncsfdi2"
3545 [(set (match_operand:DI 0 "register_operand" "=f")
3546 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3547 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3549 [(set_attr "type" "fcvt")
3550 (set_attr "mode" "SF")
3551 (set_attr "cnv_mode" "S2I")])
3554 (define_insn "floatsidf2"
3555 [(set (match_operand:DF 0 "register_operand" "=f")
3556 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3557 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3559 [(set_attr "type" "fcvt")
3560 (set_attr "mode" "DF")
3561 (set_attr "cnv_mode" "I2D")])
3564 (define_insn "floatdidf2"
3565 [(set (match_operand:DF 0 "register_operand" "=f")
3566 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3567 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3569 [(set_attr "type" "fcvt")
3570 (set_attr "mode" "DF")
3571 (set_attr "cnv_mode" "I2D")])
3574 (define_insn "floatsisf2"
3575 [(set (match_operand:SF 0 "register_operand" "=f")
3576 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3579 [(set_attr "type" "fcvt")
3580 (set_attr "mode" "SF")
3581 (set_attr "cnv_mode" "I2S")])
3584 (define_insn "floatdisf2"
3585 [(set (match_operand:SF 0 "register_operand" "=f")
3586 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3587 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3589 [(set_attr "type" "fcvt")
3590 (set_attr "mode" "SF")
3591 (set_attr "cnv_mode" "I2S")])
3594 (define_expand "fixuns_truncdfsi2"
3595 [(set (match_operand:SI 0 "register_operand")
3596 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3597 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3599 rtx reg1 = gen_reg_rtx (DFmode);
3600 rtx reg2 = gen_reg_rtx (DFmode);
3601 rtx reg3 = gen_reg_rtx (SImode);
3602 rtx label1 = gen_label_rtx ();
3603 rtx label2 = gen_label_rtx ();
3605 REAL_VALUE_TYPE offset;
3607 real_2expN (&offset, 31, DFmode);
3609 if (reg1) /* Turn off complaints about unreached code. */
3611 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3612 do_pending_stack_adjust ();
3614 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3615 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3617 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3618 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3619 gen_rtx_LABEL_REF (VOIDmode, label2)));
3622 emit_label (label1);
3623 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3624 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3625 (BITMASK_HIGH, SImode)));
3627 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3628 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3630 emit_label (label2);
3632 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3633 fields, and can't be used for REG_NOTES anyway). */
3634 emit_use (stack_pointer_rtx);
3640 (define_expand "fixuns_truncdfdi2"
3641 [(set (match_operand:DI 0 "register_operand")
3642 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3643 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3645 rtx reg1 = gen_reg_rtx (DFmode);
3646 rtx reg2 = gen_reg_rtx (DFmode);
3647 rtx reg3 = gen_reg_rtx (DImode);
3648 rtx label1 = gen_label_rtx ();
3649 rtx label2 = gen_label_rtx ();
3651 REAL_VALUE_TYPE offset;
3653 real_2expN (&offset, 63, DFmode);
3655 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3656 do_pending_stack_adjust ();
3658 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3659 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3661 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3662 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3663 gen_rtx_LABEL_REF (VOIDmode, label2)));
3666 emit_label (label1);
3667 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3668 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3669 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3671 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3672 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3674 emit_label (label2);
3676 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3677 fields, and can't be used for REG_NOTES anyway). */
3678 emit_use (stack_pointer_rtx);
3683 (define_expand "fixuns_truncsfsi2"
3684 [(set (match_operand:SI 0 "register_operand")
3685 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3688 rtx reg1 = gen_reg_rtx (SFmode);
3689 rtx reg2 = gen_reg_rtx (SFmode);
3690 rtx reg3 = gen_reg_rtx (SImode);
3691 rtx label1 = gen_label_rtx ();
3692 rtx label2 = gen_label_rtx ();
3694 REAL_VALUE_TYPE offset;
3696 real_2expN (&offset, 31, SFmode);
3698 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3699 do_pending_stack_adjust ();
3701 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3702 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3704 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3705 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3706 gen_rtx_LABEL_REF (VOIDmode, label2)));
3709 emit_label (label1);
3710 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3711 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3712 (BITMASK_HIGH, SImode)));
3714 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3715 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3717 emit_label (label2);
3719 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3720 fields, and can't be used for REG_NOTES anyway). */
3721 emit_use (stack_pointer_rtx);
3726 (define_expand "fixuns_truncsfdi2"
3727 [(set (match_operand:DI 0 "register_operand")
3728 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3729 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3731 rtx reg1 = gen_reg_rtx (SFmode);
3732 rtx reg2 = gen_reg_rtx (SFmode);
3733 rtx reg3 = gen_reg_rtx (DImode);
3734 rtx label1 = gen_label_rtx ();
3735 rtx label2 = gen_label_rtx ();
3737 REAL_VALUE_TYPE offset;
3739 real_2expN (&offset, 63, SFmode);
3741 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3742 do_pending_stack_adjust ();
3744 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3745 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3747 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3748 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3749 gen_rtx_LABEL_REF (VOIDmode, label2)));
3752 emit_label (label1);
3753 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3754 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3755 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3757 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3758 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3760 emit_label (label2);
3762 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3763 fields, and can't be used for REG_NOTES anyway). */
3764 emit_use (stack_pointer_rtx);
3769 ;; ....................
3773 ;; ....................
3775 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3777 (define_expand "extvmisalign<mode>"
3778 [(set (match_operand:GPR 0 "register_operand")
3779 (sign_extract:GPR (match_operand:BLK 1 "memory_operand")
3780 (match_operand 2 "const_int_operand")
3781 (match_operand 3 "const_int_operand")))]
3784 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3785 INTVAL (operands[2]),
3786 INTVAL (operands[3]),
3787 /*unsigned=*/ false))
3793 (define_expand "extv<mode>"
3794 [(set (match_operand:GPR 0 "register_operand")
3795 (sign_extract:GPR (match_operand:GPR 1 "register_operand")
3796 (match_operand 2 "const_int_operand")
3797 (match_operand 3 "const_int_operand")))]
3800 if (UINTVAL (operands[2]) > 32)
3804 (define_insn "*extv<mode>"
3805 [(set (match_operand:GPR 0 "register_operand" "=d")
3806 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3807 (match_operand 2 "const_int_operand" "")
3808 (match_operand 3 "const_int_operand" "")))]
3809 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3810 "exts\t%0,%1,%3,%m2"
3811 [(set_attr "type" "arith")
3812 (set_attr "mode" "<MODE>")])
3814 (define_expand "extzvmisalign<mode>"
3815 [(set (match_operand:GPR 0 "register_operand")
3816 (zero_extract:GPR (match_operand:BLK 1 "memory_operand")
3817 (match_operand 2 "const_int_operand")
3818 (match_operand 3 "const_int_operand")))]
3821 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3822 INTVAL (operands[2]),
3823 INTVAL (operands[3]),
3824 /*unsigned=*/ true))
3830 (define_expand "extzv<mode>"
3831 [(set (match_operand:GPR 0 "register_operand")
3832 (zero_extract:GPR (match_operand:GPR 1 "register_operand")
3833 (match_operand 2 "const_int_operand")
3834 (match_operand 3 "const_int_operand")))]
3837 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3838 INTVAL (operands[3])))
3842 (define_insn "*extzv<mode>"
3843 [(set (match_operand:GPR 0 "register_operand" "=d")
3844 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3845 (match_operand 2 "const_int_operand" "")
3846 (match_operand 3 "const_int_operand" "")))]
3847 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3848 INTVAL (operands[3]))"
3849 "<d>ext\t%0,%1,%3,%2"
3850 [(set_attr "type" "arith")
3851 (set_attr "mode" "<MODE>")])
3853 (define_insn "*extzv_truncsi_exts"
3854 [(set (match_operand:SI 0 "register_operand" "=d")
3856 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3857 (match_operand 2 "const_int_operand" "")
3858 (match_operand 3 "const_int_operand" ""))))]
3859 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3861 [(set_attr "type" "arith")
3862 (set_attr "mode" "SI")])
3865 (define_expand "insvmisalign<mode>"
3866 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")
3867 (match_operand 1 "const_int_operand")
3868 (match_operand 2 "const_int_operand"))
3869 (match_operand:GPR 3 "reg_or_0_operand"))]
3872 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3873 INTVAL (operands[1]),
3874 INTVAL (operands[2])))
3880 (define_expand "insv<mode>"
3881 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand")
3882 (match_operand 1 "const_int_operand")
3883 (match_operand 2 "const_int_operand"))
3884 (match_operand:GPR 3 "reg_or_0_operand"))]
3887 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3888 INTVAL (operands[2])))
3892 (define_insn "*insv<mode>"
3893 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3894 (match_operand:SI 1 "const_int_operand" "")
3895 (match_operand:SI 2 "const_int_operand" ""))
3896 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3897 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3898 INTVAL (operands[2]))"
3899 "<d>ins\t%0,%z3,%2,%1"
3900 [(set_attr "type" "arith")
3901 (set_attr "mode" "<MODE>")])
3903 ;; Combiner pattern for cins (clear and insert bit field). We can
3904 ;; implement mask-and-shift-left operation with this. Note that if
3905 ;; the upper bit of the mask is set in an SImode operation, the mask
3906 ;; itself will be sign-extended. mask_low_and_shift_len will
3907 ;; therefore be greater than our threshold of 32.
3909 (define_insn "*cins<mode>"
3910 [(set (match_operand:GPR 0 "register_operand" "=d")
3912 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3913 (match_operand:GPR 2 "const_int_operand" ""))
3914 (match_operand:GPR 3 "const_int_operand" "")))]
3916 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3919 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3920 return "cins\t%0,%1,%2,%m3";
3922 [(set_attr "type" "shift")
3923 (set_attr "mode" "<MODE>")])
3925 ;; Unaligned word moves generated by the bit field patterns.
3927 ;; As far as the rtl is concerned, both the left-part and right-part
3928 ;; instructions can access the whole field. However, the real operand
3929 ;; refers to just the first or the last byte (depending on endianness).
3930 ;; We therefore use two memory operands to each instruction, one to
3931 ;; describe the rtl effect and one to use in the assembly output.
3933 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3934 ;; This allows us to use the standard length calculations for the "load"
3935 ;; and "store" type attributes.
3937 (define_insn "mov_<load>l"
3938 [(set (match_operand:GPR 0 "register_operand" "=d")
3939 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3940 (match_operand:QI 2 "memory_operand" "m")]
3942 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3944 [(set_attr "move_type" "load")
3945 (set_attr "mode" "<MODE>")])
3947 (define_insn "mov_<load>r"
3948 [(set (match_operand:GPR 0 "register_operand" "=d")
3949 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3950 (match_operand:QI 2 "memory_operand" "m")
3951 (match_operand:GPR 3 "register_operand" "0")]
3952 UNSPEC_LOAD_RIGHT))]
3953 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3955 [(set_attr "move_type" "load")
3956 (set_attr "mode" "<MODE>")])
3958 (define_insn "mov_<store>l"
3959 [(set (match_operand:BLK 0 "memory_operand" "=m")
3960 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3961 (match_operand:QI 2 "memory_operand" "m")]
3962 UNSPEC_STORE_LEFT))]
3963 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3965 [(set_attr "move_type" "store")
3966 (set_attr "mode" "<MODE>")])
3968 (define_insn "mov_<store>r"
3969 [(set (match_operand:BLK 0 "memory_operand" "+m")
3970 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3971 (match_operand:QI 2 "memory_operand" "m")
3973 UNSPEC_STORE_RIGHT))]
3974 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3976 [(set_attr "move_type" "store")
3977 (set_attr "mode" "<MODE>")])
3979 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3980 ;; The required value is:
3982 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3984 ;; which translates to:
3986 ;; lui op0,%highest(op1)
3987 ;; daddiu op0,op0,%higher(op1)
3989 ;; daddiu op0,op0,%hi(op1)
3992 ;; The split is deferred until after flow2 to allow the peephole2 below
3994 (define_insn_and_split "*lea_high64"
3995 [(set (match_operand:DI 0 "register_operand" "=d")
3996 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3997 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3999 "&& epilogue_completed"
4000 [(set (match_dup 0) (high:DI (match_dup 2)))
4001 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
4002 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
4003 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4004 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
4006 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4007 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
4009 [(set_attr "length" "20")])
4011 ;; Use a scratch register to reduce the latency of the above pattern
4012 ;; on superscalar machines. The optimized sequence is:
4014 ;; lui op1,%highest(op2)
4016 ;; daddiu op1,op1,%higher(op2)
4018 ;; daddu op1,op1,op0
4020 [(set (match_operand:DI 1 "d_operand")
4021 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
4022 (match_scratch:DI 0 "d")]
4023 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4024 [(set (match_dup 1) (high:DI (match_dup 3)))
4025 (set (match_dup 0) (high:DI (match_dup 4)))
4026 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
4027 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
4028 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
4030 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
4031 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
4034 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
4035 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
4036 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
4037 ;; used once. We can then use the sequence:
4039 ;; lui op0,%highest(op1)
4041 ;; daddiu op0,op0,%higher(op1)
4042 ;; daddiu op2,op2,%lo(op1)
4044 ;; daddu op0,op0,op2
4046 ;; which takes 4 cycles on most superscalar targets.
4047 (define_insn_and_split "*lea64"
4048 [(set (match_operand:DI 0 "register_operand" "=d")
4049 (match_operand:DI 1 "absolute_symbolic_operand" ""))
4050 (clobber (match_scratch:DI 2 "=&d"))]
4051 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
4053 "&& reload_completed"
4054 [(set (match_dup 0) (high:DI (match_dup 3)))
4055 (set (match_dup 2) (high:DI (match_dup 4)))
4056 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4057 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
4058 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
4059 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
4061 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4062 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
4064 [(set_attr "length" "24")])
4066 ;; Split HIGHs into:
4071 ;; on MIPS16 targets.
4073 [(set (match_operand:P 0 "d_operand")
4074 (high:P (match_operand:P 1 "symbolic_operand_with_high")))]
4075 "TARGET_MIPS16 && reload_completed"
4076 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH))
4077 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))])
4079 (define_insn "*unshifted_high"
4080 [(set (match_operand:P 0 "d_operand" "=d")
4081 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")]
4082 UNSPEC_UNSHIFTED_HIGH))]
4085 [(set_attr "extended_mips16" "yes")])
4087 ;; Insns to fetch a symbol from a big GOT.
4089 (define_insn_and_split "*xgot_hi<mode>"
4090 [(set (match_operand:P 0 "register_operand" "=d")
4091 (high:P (match_operand:P 1 "got_disp_operand" "")))]
4092 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4094 "&& reload_completed"
4095 [(set (match_dup 0) (high:P (match_dup 2)))
4096 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
4098 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
4099 operands[3] = pic_offset_table_rtx;
4101 [(set_attr "got" "xgot_high")
4102 (set_attr "mode" "<MODE>")])
4104 (define_insn_and_split "*xgot_lo<mode>"
4105 [(set (match_operand:P 0 "register_operand" "=d")
4106 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4107 (match_operand:P 2 "got_disp_operand" "")))]
4108 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4110 "&& reload_completed"
4112 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
4113 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
4114 [(set_attr "got" "load")
4115 (set_attr "mode" "<MODE>")])
4117 ;; Insns to fetch a symbol from a normal GOT.
4119 (define_insn_and_split "*got_disp<mode>"
4120 [(set (match_operand:P 0 "register_operand" "=d")
4121 (match_operand:P 1 "got_disp_operand" ""))]
4122 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
4124 "&& reload_completed"
4125 [(set (match_dup 0) (match_dup 2))]
4126 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
4127 [(set_attr "got" "load")
4128 (set_attr "mode" "<MODE>")])
4130 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
4132 (define_insn_and_split "*got_page<mode>"
4133 [(set (match_operand:P 0 "register_operand" "=d")
4134 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
4135 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
4137 "&& reload_completed"
4138 [(set (match_dup 0) (match_dup 2))]
4139 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
4140 [(set_attr "got" "load")
4141 (set_attr "mode" "<MODE>")])
4143 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
4144 (define_expand "unspec_got_<mode>"
4145 [(unspec:P [(match_operand:P 0)
4146 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
4148 ;; Lower-level instructions for loading an address from the GOT.
4149 ;; We could use MEMs, but an unspec gives more optimization
4152 (define_insn "load_got<mode>"
4153 [(set (match_operand:P 0 "register_operand" "=d")
4154 (unspec:P [(match_operand:P 1 "register_operand" "d")
4155 (match_operand:P 2 "immediate_operand" "")]
4158 "<load>\t%0,%R2(%1)"
4159 [(set_attr "got" "load")
4160 (set_attr "mode" "<MODE>")])
4162 ;; Instructions for adding the low 16 bits of an address to a register.
4163 ;; Operand 2 is the address: mips_print_operand works out which relocation
4164 ;; should be applied.
4166 (define_insn "*low<mode>"
4167 [(set (match_operand:P 0 "register_operand" "=d")
4168 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4169 (match_operand:P 2 "immediate_operand" "")))]
4171 "<d>addiu\t%0,%1,%R2"
4172 [(set_attr "alu_type" "add")
4173 (set_attr "mode" "<MODE>")])
4175 (define_insn "*low<mode>_mips16"
4176 [(set (match_operand:P 0 "register_operand" "=d")
4177 (lo_sum:P (match_operand:P 1 "register_operand" "0")
4178 (match_operand:P 2 "immediate_operand" "")))]
4181 [(set_attr "alu_type" "add")
4182 (set_attr "mode" "<MODE>")
4183 (set_attr "extended_mips16" "yes")])
4185 ;; Expose MIPS16 uses of the global pointer after reload if the function
4186 ;; is responsible for setting up the register itself.
4188 [(set (match_operand:GPR 0 "d_operand")
4189 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
4190 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
4191 [(set (match_dup 0) (match_dup 1))]
4192 { operands[1] = pic_offset_table_rtx; })
4194 ;; Allow combine to split complex const_int load sequences, using operand 2
4195 ;; to store the intermediate results. See move_operand for details.
4197 [(set (match_operand:GPR 0 "register_operand")
4198 (match_operand:GPR 1 "splittable_const_int_operand"))
4199 (clobber (match_operand:GPR 2 "register_operand"))]
4203 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
4207 ;; Likewise, for symbolic operands.
4209 [(set (match_operand:P 0 "register_operand")
4210 (match_operand:P 1))
4211 (clobber (match_operand:P 2 "register_operand"))]
4212 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
4213 [(set (match_dup 0) (match_dup 3))]
4215 mips_split_symbol (operands[2], operands[1],
4216 MAX_MACHINE_MODE, &operands[3]);
4219 ;; 64-bit integer moves
4221 ;; Unlike most other insns, the move insns can't be split with
4222 ;; different predicates, because register spilling and other parts of
4223 ;; the compiler, have memoized the insn number already.
4225 (define_expand "movdi"
4226 [(set (match_operand:DI 0 "")
4227 (match_operand:DI 1 ""))]
4230 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4234 ;; For mips16, we need a special case to handle storing $31 into
4235 ;; memory, since we don't have a constraint to match $31. This
4236 ;; instruction can be generated by save_restore_insns.
4238 (define_insn "*mov<mode>_ra"
4239 [(set (match_operand:GPR 0 "stack_operand" "=m")
4240 (reg:GPR RETURN_ADDR_REGNUM))]
4243 [(set_attr "move_type" "store")
4244 (set_attr "mode" "<MODE>")])
4246 (define_insn "*movdi_32bit"
4247 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
4248 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
4249 "!TARGET_64BIT && !TARGET_MIPS16
4250 && (register_operand (operands[0], DImode)
4251 || reg_or_0_operand (operands[1], DImode))"
4252 { return mips_output_move (operands[0], operands[1]); }
4253 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
4255 (if_then_else (eq_attr "move_type" "imul")
4257 (const_string "DI")))])
4259 (define_insn "*movdi_32bit_mips16"
4260 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4261 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
4262 "!TARGET_64BIT && TARGET_MIPS16
4263 && (register_operand (operands[0], DImode)
4264 || register_operand (operands[1], DImode))"
4265 { return mips_output_move (operands[0], operands[1]); }
4266 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4267 (set_attr "mode" "DI")])
4269 (define_insn "*movdi_64bit"
4270 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
4271 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4272 "TARGET_64BIT && !TARGET_MIPS16
4273 && (register_operand (operands[0], DImode)
4274 || reg_or_0_operand (operands[1], DImode))"
4275 { return mips_output_move (operands[0], operands[1]); }
4276 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore")
4277 (set_attr "mode" "DI")])
4279 (define_insn "*movdi_64bit_mips16"
4280 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4281 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4282 "TARGET_64BIT && TARGET_MIPS16
4283 && (register_operand (operands[0], DImode)
4284 || register_operand (operands[1], DImode))"
4285 { return mips_output_move (operands[0], operands[1]); }
4286 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4287 (set_attr "mode" "DI")])
4289 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4290 ;; when the original load is a 4 byte instruction but the add and the
4291 ;; load are 2 2 byte instructions.
4294 [(set (match_operand:DI 0 "d_operand")
4295 (mem:DI (plus:DI (match_dup 0)
4296 (match_operand:DI 1 "const_int_operand"))))]
4297 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4298 && !TARGET_DEBUG_D_MODE
4299 && ((INTVAL (operands[1]) < 0
4300 && INTVAL (operands[1]) >= -0x10)
4301 || (INTVAL (operands[1]) >= 32 * 8
4302 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4303 || (INTVAL (operands[1]) >= 0
4304 && INTVAL (operands[1]) < 32 * 8
4305 && (INTVAL (operands[1]) & 7) != 0))"
4306 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4307 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4309 HOST_WIDE_INT val = INTVAL (operands[1]);
4312 operands[2] = const0_rtx;
4313 else if (val >= 32 * 8)
4317 operands[1] = GEN_INT (0x8 + off);
4318 operands[2] = GEN_INT (val - off - 0x8);
4324 operands[1] = GEN_INT (off);
4325 operands[2] = GEN_INT (val - off);
4329 ;; 32-bit Integer moves
4331 ;; Unlike most other insns, the move insns can't be split with
4332 ;; different predicates, because register spilling and other parts of
4333 ;; the compiler, have memoized the insn number already.
4335 (define_expand "mov<mode>"
4336 [(set (match_operand:IMOVE32 0 "")
4337 (match_operand:IMOVE32 1 ""))]
4340 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4344 ;; The difference between these two is whether or not ints are allowed
4345 ;; in FP registers (off by default, use -mdebugh to enable).
4347 (define_insn "*mov<mode>_internal"
4348 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4349 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4351 && (register_operand (operands[0], <MODE>mode)
4352 || reg_or_0_operand (operands[1], <MODE>mode))"
4353 { return mips_output_move (operands[0], operands[1]); }
4354 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore")
4355 (set_attr "mode" "SI")])
4357 (define_insn "*mov<mode>_mips16"
4358 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4359 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4361 && (register_operand (operands[0], <MODE>mode)
4362 || register_operand (operands[1], <MODE>mode))"
4363 { return mips_output_move (operands[0], operands[1]); }
4364 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4365 (set_attr "mode" "SI")])
4367 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4368 ;; when the original load is a 4 byte instruction but the add and the
4369 ;; load are 2 2 byte instructions.
4372 [(set (match_operand:SI 0 "d_operand")
4373 (mem:SI (plus:SI (match_dup 0)
4374 (match_operand:SI 1 "const_int_operand"))))]
4375 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4376 && ((INTVAL (operands[1]) < 0
4377 && INTVAL (operands[1]) >= -0x80)
4378 || (INTVAL (operands[1]) >= 32 * 4
4379 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4380 || (INTVAL (operands[1]) >= 0
4381 && INTVAL (operands[1]) < 32 * 4
4382 && (INTVAL (operands[1]) & 3) != 0))"
4383 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4384 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4386 HOST_WIDE_INT val = INTVAL (operands[1]);
4389 operands[2] = const0_rtx;
4390 else if (val >= 32 * 4)
4394 operands[1] = GEN_INT (0x7c + off);
4395 operands[2] = GEN_INT (val - off - 0x7c);
4401 operands[1] = GEN_INT (off);
4402 operands[2] = GEN_INT (val - off);
4406 ;; On the mips16, we can split a load of certain constants into a load
4407 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4411 [(set (match_operand:SI 0 "d_operand")
4412 (match_operand:SI 1 "const_int_operand"))]
4413 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4414 && INTVAL (operands[1]) >= 0x100
4415 && INTVAL (operands[1]) <= 0xff + 0x7f"
4416 [(set (match_dup 0) (match_dup 1))
4417 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4419 int val = INTVAL (operands[1]);
4421 operands[1] = GEN_INT (0xff);
4422 operands[2] = GEN_INT (val - 0xff);
4425 ;; MIPS4 supports loading and storing a floating point register from
4426 ;; the sum of two general registers. We use two versions for each of
4427 ;; these four instructions: one where the two general registers are
4428 ;; SImode, and one where they are DImode. This is because general
4429 ;; registers will be in SImode when they hold 32-bit values, but,
4430 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4431 ;; instructions will still work correctly.
4433 ;; ??? Perhaps it would be better to support these instructions by
4434 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4435 ;; these instructions can only be used to load and store floating
4436 ;; point registers, that would probably cause trouble in reload.
4438 (define_insn "*<ANYF:loadx>_<P:mode>"
4439 [(set (match_operand:ANYF 0 "register_operand" "=f")
4440 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4441 (match_operand:P 2 "register_operand" "d"))))]
4443 "<ANYF:loadx>\t%0,%1(%2)"
4444 [(set_attr "type" "fpidxload")
4445 (set_attr "mode" "<ANYF:UNITMODE>")])
4447 (define_insn "*<ANYF:storex>_<P:mode>"
4448 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4449 (match_operand:P 2 "register_operand" "d")))
4450 (match_operand:ANYF 0 "register_operand" "f"))]
4452 "<ANYF:storex>\t%0,%1(%2)"
4453 [(set_attr "type" "fpidxstore")
4454 (set_attr "mode" "<ANYF:UNITMODE>")])
4456 ;; Scaled indexed address load.
4457 ;; Per md.texi, we only need to look for a pattern with multiply in the
4458 ;; address expression, not shift.
4460 (define_insn "*lwxs"
4461 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4463 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4465 (match_operand:P 2 "register_operand" "d"))))]
4468 [(set_attr "type" "load")
4469 (set_attr "mode" "SI")])
4471 ;; 16-bit Integer moves
4473 ;; Unlike most other insns, the move insns can't be split with
4474 ;; different predicates, because register spilling and other parts of
4475 ;; the compiler, have memoized the insn number already.
4476 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4478 (define_expand "movhi"
4479 [(set (match_operand:HI 0 "")
4480 (match_operand:HI 1 ""))]
4483 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4487 (define_insn "*movhi_internal"
4488 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4489 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4491 && (register_operand (operands[0], HImode)
4492 || reg_or_0_operand (operands[1], HImode))"
4493 { return mips_output_move (operands[0], operands[1]); }
4494 [(set_attr "move_type" "move,const,load,store,mtlo,mflo")
4495 (set_attr "mode" "HI")])
4497 (define_insn "*movhi_mips16"
4498 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4499 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4501 && (register_operand (operands[0], HImode)
4502 || register_operand (operands[1], HImode))"
4503 { return mips_output_move (operands[0], operands[1]); }
4504 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4505 (set_attr "mode" "HI")])
4507 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4508 ;; when the original load is a 4 byte instruction but the add and the
4509 ;; load are 2 2 byte instructions.
4512 [(set (match_operand:HI 0 "d_operand")
4513 (mem:HI (plus:SI (match_dup 0)
4514 (match_operand:SI 1 "const_int_operand"))))]
4515 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4516 && ((INTVAL (operands[1]) < 0
4517 && INTVAL (operands[1]) >= -0x80)
4518 || (INTVAL (operands[1]) >= 32 * 2
4519 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4520 || (INTVAL (operands[1]) >= 0
4521 && INTVAL (operands[1]) < 32 * 2
4522 && (INTVAL (operands[1]) & 1) != 0))"
4523 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4524 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4526 HOST_WIDE_INT val = INTVAL (operands[1]);
4529 operands[2] = const0_rtx;
4530 else if (val >= 32 * 2)
4534 operands[1] = GEN_INT (0x7e + off);
4535 operands[2] = GEN_INT (val - off - 0x7e);
4541 operands[1] = GEN_INT (off);
4542 operands[2] = GEN_INT (val - off);
4546 ;; 8-bit Integer moves
4548 ;; Unlike most other insns, the move insns can't be split with
4549 ;; different predicates, because register spilling and other parts of
4550 ;; the compiler, have memoized the insn number already.
4551 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4553 (define_expand "movqi"
4554 [(set (match_operand:QI 0 "")
4555 (match_operand:QI 1 ""))]
4558 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4562 (define_insn "*movqi_internal"
4563 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4564 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4566 && (register_operand (operands[0], QImode)
4567 || reg_or_0_operand (operands[1], QImode))"
4568 { return mips_output_move (operands[0], operands[1]); }
4569 [(set_attr "move_type" "move,const,load,store,mtlo,mflo")
4570 (set_attr "mode" "QI")])
4572 (define_insn "*movqi_mips16"
4573 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4574 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4576 && (register_operand (operands[0], QImode)
4577 || register_operand (operands[1], QImode))"
4578 { return mips_output_move (operands[0], operands[1]); }
4579 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4580 (set_attr "mode" "QI")])
4582 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4583 ;; when the original load is a 4 byte instruction but the add and the
4584 ;; load are 2 2 byte instructions.
4587 [(set (match_operand:QI 0 "d_operand")
4588 (mem:QI (plus:SI (match_dup 0)
4589 (match_operand:SI 1 "const_int_operand"))))]
4590 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4591 && ((INTVAL (operands[1]) < 0
4592 && INTVAL (operands[1]) >= -0x80)
4593 || (INTVAL (operands[1]) >= 32
4594 && INTVAL (operands[1]) <= 31 + 0x7f))"
4595 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4596 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4598 HOST_WIDE_INT val = INTVAL (operands[1]);
4601 operands[2] = const0_rtx;
4604 operands[1] = GEN_INT (0x7f);
4605 operands[2] = GEN_INT (val - 0x7f);
4609 ;; 32-bit floating point moves
4611 (define_expand "movsf"
4612 [(set (match_operand:SF 0 "")
4613 (match_operand:SF 1 ""))]
4616 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4620 (define_insn "*movsf_hardfloat"
4621 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4622 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4624 && (register_operand (operands[0], SFmode)
4625 || reg_or_0_operand (operands[1], SFmode))"
4626 { return mips_output_move (operands[0], operands[1]); }
4627 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4628 (set_attr "mode" "SF")])
4630 (define_insn "*movsf_softfloat"
4631 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4632 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4633 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4634 && (register_operand (operands[0], SFmode)
4635 || reg_or_0_operand (operands[1], SFmode))"
4636 { return mips_output_move (operands[0], operands[1]); }
4637 [(set_attr "move_type" "move,load,store")
4638 (set_attr "mode" "SF")])
4640 (define_insn "*movsf_mips16"
4641 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4642 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4644 && (register_operand (operands[0], SFmode)
4645 || register_operand (operands[1], SFmode))"
4646 { return mips_output_move (operands[0], operands[1]); }
4647 [(set_attr "move_type" "move,move,move,load,store")
4648 (set_attr "mode" "SF")])
4650 ;; 64-bit floating point moves
4652 (define_expand "movdf"
4653 [(set (match_operand:DF 0 "")
4654 (match_operand:DF 1 ""))]
4657 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4661 (define_insn "*movdf_hardfloat"
4662 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4663 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4664 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4665 && (register_operand (operands[0], DFmode)
4666 || reg_or_0_operand (operands[1], DFmode))"
4667 { return mips_output_move (operands[0], operands[1]); }
4668 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4669 (set_attr "mode" "DF")])
4671 (define_insn "*movdf_softfloat"
4672 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4673 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4674 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4675 && (register_operand (operands[0], DFmode)
4676 || reg_or_0_operand (operands[1], DFmode))"
4677 { return mips_output_move (operands[0], operands[1]); }
4678 [(set_attr "move_type" "move,load,store")
4679 (set_attr "mode" "DF")])
4681 (define_insn "*movdf_mips16"
4682 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4683 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4685 && (register_operand (operands[0], DFmode)
4686 || register_operand (operands[1], DFmode))"
4687 { return mips_output_move (operands[0], operands[1]); }
4688 [(set_attr "move_type" "move,move,move,load,store")
4689 (set_attr "mode" "DF")])
4691 ;; 128-bit integer moves
4693 (define_expand "movti"
4694 [(set (match_operand:TI 0)
4695 (match_operand:TI 1))]
4698 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4702 (define_insn "*movti"
4703 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d")
4704 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))]
4707 && (register_operand (operands[0], TImode)
4708 || reg_or_0_operand (operands[1], TImode))"
4709 { return mips_output_move (operands[0], operands[1]); }
4710 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo")
4712 (if_then_else (eq_attr "move_type" "imul")
4714 (const_string "TI")))])
4716 (define_insn "*movti_mips16"
4717 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4718 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4721 && (register_operand (operands[0], TImode)
4722 || register_operand (operands[1], TImode))"
4724 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4725 (set_attr "mode" "TI")])
4727 ;; 128-bit floating point moves
4729 (define_expand "movtf"
4730 [(set (match_operand:TF 0)
4731 (match_operand:TF 1))]
4734 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4738 ;; This pattern handles both hard- and soft-float cases.
4739 (define_insn "*movtf"
4740 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4741 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4744 && (register_operand (operands[0], TFmode)
4745 || reg_or_0_operand (operands[1], TFmode))"
4747 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4748 (set_attr "mode" "TF")])
4750 (define_insn "*movtf_mips16"
4751 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4752 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4755 && (register_operand (operands[0], TFmode)
4756 || register_operand (operands[1], TFmode))"
4758 [(set_attr "move_type" "move,move,move,load,store")
4759 (set_attr "mode" "TF")])
4762 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4763 (match_operand:MOVE64 1 "move_operand"))]
4764 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
4767 mips_split_move_insn (operands[0], operands[1], curr_insn);
4772 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4773 (match_operand:MOVE128 1 "move_operand"))]
4774 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
4777 mips_split_move_insn (operands[0], operands[1], curr_insn);
4781 ;; When generating mips16 code, split moves of negative constants into
4782 ;; a positive "li" followed by a negation.
4784 [(set (match_operand 0 "d_operand")
4785 (match_operand 1 "const_int_operand"))]
4786 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4790 (neg:SI (match_dup 2)))]
4792 operands[2] = gen_lowpart (SImode, operands[0]);
4793 operands[3] = GEN_INT (-INTVAL (operands[1]));
4796 ;; 64-bit paired-single floating point moves
4798 (define_expand "movv2sf"
4799 [(set (match_operand:V2SF 0)
4800 (match_operand:V2SF 1))]
4801 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4803 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4807 (define_insn "*movv2sf"
4808 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4809 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4811 && TARGET_PAIRED_SINGLE_FLOAT
4812 && (register_operand (operands[0], V2SFmode)
4813 || reg_or_0_operand (operands[1], V2SFmode))"
4814 { return mips_output_move (operands[0], operands[1]); }
4815 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4816 (set_attr "mode" "DF")])
4818 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4819 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4821 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4822 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4823 ;; and the errata related to -mfix-vr4130.
4824 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4825 [(set (match_operand:GPR 0 "register_operand" "=d")
4826 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")]
4829 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4830 [(set_attr "type" "mfhi")
4831 (set_attr "mode" "<GPR:MODE>")])
4833 ;; Set the high part of a HI/LO value, given that the low part has
4834 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4835 ;; why we can't just use (reg:GPR HI_REGNUM).
4836 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4837 [(set (match_operand:HILO 0 "register_operand" "=x")
4838 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4839 (match_operand:GPR 2 "register_operand" "l")]
4843 [(set_attr "type" "mthi")
4844 (set_attr "mode" "SI")])
4846 ;; Emit a doubleword move in which exactly one of the operands is
4847 ;; a floating-point register. We can't just emit two normal moves
4848 ;; because of the constraints imposed by the FPU register model;
4849 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4850 ;; the FPR whole and use special patterns to refer to each word of
4851 ;; the other operand.
4853 (define_expand "move_doubleword_fpr<mode>"
4854 [(set (match_operand:SPLITF 0)
4855 (match_operand:SPLITF 1))]
4858 if (FP_REG_RTX_P (operands[0]))
4860 rtx low = mips_subword (operands[1], 0);
4861 rtx high = mips_subword (operands[1], 1);
4862 emit_insn (gen_load_low<mode> (operands[0], low));
4863 if (TARGET_FLOAT64 && !TARGET_64BIT)
4864 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4866 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4870 rtx low = mips_subword (operands[0], 0);
4871 rtx high = mips_subword (operands[0], 1);
4872 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4873 if (TARGET_FLOAT64 && !TARGET_64BIT)
4874 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4876 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4881 ;; Load the low word of operand 0 with operand 1.
4882 (define_insn "load_low<mode>"
4883 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4884 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4888 operands[0] = mips_subword (operands[0], 0);
4889 return mips_output_move (operands[0], operands[1]);
4891 [(set_attr "move_type" "mtc,fpload")
4892 (set_attr "mode" "<HALFMODE>")])
4894 ;; Load the high word of operand 0 from operand 1, preserving the value
4896 (define_insn "load_high<mode>"
4897 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4898 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4899 (match_operand:SPLITF 2 "register_operand" "0,0")]
4903 operands[0] = mips_subword (operands[0], 1);
4904 return mips_output_move (operands[0], operands[1]);
4906 [(set_attr "move_type" "mtc,fpload")
4907 (set_attr "mode" "<HALFMODE>")])
4909 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4910 ;; high word and 0 to store the low word.
4911 (define_insn "store_word<mode>"
4912 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4913 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4914 (match_operand 2 "const_int_operand")]
4915 UNSPEC_STORE_WORD))]
4918 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4919 return mips_output_move (operands[0], operands[1]);
4921 [(set_attr "move_type" "mfc,fpstore")
4922 (set_attr "mode" "<HALFMODE>")])
4924 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4925 ;; value in the low word.
4926 (define_insn "mthc1<mode>"
4927 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4928 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4929 (match_operand:SPLITF 2 "register_operand" "0")]
4931 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4933 [(set_attr "move_type" "mtc")
4934 (set_attr "mode" "<HALFMODE>")])
4936 ;; Move high word of operand 1 to operand 0 using mfhc1.
4937 (define_insn "mfhc1<mode>"
4938 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4939 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4941 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4943 [(set_attr "move_type" "mfc")
4944 (set_attr "mode" "<HALFMODE>")])
4946 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4947 (define_expand "load_const_gp_<mode>"
4948 [(set (match_operand:P 0 "register_operand" "=d")
4949 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4951 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4952 ;; of _gp from the start of this function. Operand 1 is the incoming
4953 ;; function address.
4954 (define_insn_and_split "loadgp_newabi_<mode>"
4955 [(set (match_operand:P 0 "register_operand" "=&d")
4956 (unspec:P [(match_operand:P 1)
4957 (match_operand:P 2 "register_operand" "d")]
4959 "mips_current_loadgp_style () == LOADGP_NEWABI"
4960 { return mips_must_initialize_gp_p () ? "#" : ""; }
4961 "&& mips_must_initialize_gp_p ()"
4962 [(set (match_dup 0) (match_dup 3))
4963 (set (match_dup 0) (match_dup 4))
4964 (set (match_dup 0) (match_dup 5))]
4966 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4967 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4968 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4970 [(set_attr "type" "ghost")])
4972 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4973 (define_insn_and_split "loadgp_absolute_<mode>"
4974 [(set (match_operand:P 0 "register_operand" "=d")
4975 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4976 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4977 { return mips_must_initialize_gp_p () ? "#" : ""; }
4978 "&& mips_must_initialize_gp_p ()"
4981 mips_emit_move (operands[0], operands[1]);
4984 [(set_attr "type" "ghost")])
4986 ;; This blockage instruction prevents the gp load from being
4987 ;; scheduled after an implicit use of gp. It also prevents
4988 ;; the load from being deleted as dead.
4989 (define_insn "loadgp_blockage"
4990 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4993 [(set_attr "type" "ghost")])
4995 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4996 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4997 (define_insn_and_split "loadgp_rtp_<mode>"
4998 [(set (match_operand:P 0 "register_operand" "=d")
4999 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
5000 (match_operand:P 2 "symbol_ref_operand")]
5002 "mips_current_loadgp_style () == LOADGP_RTP"
5003 { return mips_must_initialize_gp_p () ? "#" : ""; }
5004 "&& mips_must_initialize_gp_p ()"
5005 [(set (match_dup 0) (high:P (match_dup 3)))
5006 (set (match_dup 0) (unspec:P [(match_dup 0)
5007 (match_dup 3)] UNSPEC_LOAD_GOT))
5008 (set (match_dup 0) (unspec:P [(match_dup 0)
5009 (match_dup 4)] UNSPEC_LOAD_GOT))]
5011 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
5012 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
5014 [(set_attr "type" "ghost")])
5016 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
5017 ;; global pointer and operand 1 is the MIPS16 register that holds
5018 ;; the required value.
5019 (define_insn_and_split "copygp_mips16_<mode>"
5020 [(set (match_operand:P 0 "register_operand" "=y")
5021 (unspec:P [(match_operand:P 1 "register_operand" "d")]
5024 { return mips_must_initialize_gp_p () ? "#" : ""; }
5025 "&& mips_must_initialize_gp_p ()"
5026 [(set (match_dup 0) (match_dup 1))]
5028 [(set_attr "type" "ghost")])
5030 ;; A placeholder for where the cprestore instruction should go,
5031 ;; if we decide we need one. Operand 0 and operand 1 are as for
5032 ;; "cprestore". Operand 2 is a register that holds the gp value.
5034 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
5035 ;; otherwise any register that holds the correct value will do.
5036 (define_insn_and_split "potential_cprestore_<mode>"
5037 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5038 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5039 (match_operand:P 2 "register_operand" "d,d")]
5040 UNSPEC_POTENTIAL_CPRESTORE))
5041 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))]
5042 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
5043 { return mips_must_initialize_gp_p () ? "#" : ""; }
5044 "mips_must_initialize_gp_p ()"
5047 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
5048 operands[2], operands[3]);
5051 [(set_attr "type" "ghost")])
5053 ;; Emit a .cprestore directive, which normally expands to a single store
5054 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
5055 ;; for the cprestore slot. Operand 1 is the offset of the slot from
5056 ;; the stack pointer. (This is redundant with operand 0, but it makes
5057 ;; things a little simpler.)
5058 (define_insn "cprestore_<mode>"
5059 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5060 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5063 "TARGET_CPRESTORE_DIRECTIVE"
5065 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
5066 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
5068 return ".cprestore\t%1";
5070 [(set_attr "type" "store")
5071 (set_attr "length" "4,12")])
5073 (define_insn "use_cprestore_<mode>"
5074 [(set (reg:P CPRESTORE_SLOT_REGNUM)
5075 (match_operand:P 0 "cprestore_load_slot_operand"))]
5078 [(set_attr "type" "ghost")])
5080 ;; Expand in-line code to clear the instruction cache between operand[0] and
5082 (define_expand "clear_cache"
5083 [(match_operand 0 "pmode_register_operand")
5084 (match_operand 1 "pmode_register_operand")]
5090 mips_expand_synci_loop (operands[0], operands[1]);
5091 emit_insn (gen_sync ());
5092 emit_insn (PMODE_INSN (gen_clear_hazard, ()));
5094 else if (mips_cache_flush_func && mips_cache_flush_func[0])
5096 rtx len = gen_reg_rtx (Pmode);
5097 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
5098 MIPS_ICACHE_SYNC (operands[0], len);
5104 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
5106 { return mips_output_sync (); })
5108 (define_insn "synci"
5109 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
5114 (define_insn "rdhwr_synci_step_<mode>"
5115 [(set (match_operand:P 0 "register_operand" "=d")
5116 (unspec_volatile [(const_int 1)]
5121 (define_insn "clear_hazard_<mode>"
5122 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
5123 (clobber (reg:P RETURN_ADDR_REGNUM))]
5126 return "%(%<bal\t1f\n"
5128 "1:\t<d>addiu\t$31,$31,12\n"
5132 [(set_attr "length" "20")])
5134 ;; Cache operations for R4000-style caches.
5135 (define_insn "mips_cache"
5136 [(set (mem:BLK (scratch))
5137 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
5138 (match_operand:QI 1 "address_operand" "p")]
5139 UNSPEC_MIPS_CACHE))]
5143 ;; Similar, but with the operands hard-coded to an R10K cache barrier
5144 ;; operation. We keep the pattern distinct so that we can identify
5145 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
5146 ;; the operation is never inserted into a delay slot.
5147 (define_insn "r10k_cache_barrier"
5148 [(set (mem:BLK (scratch))
5149 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
5152 [(set_attr "can_delay" "no")])
5154 ;; Block moves, see mips.c for more details.
5155 ;; Argument 0 is the destination
5156 ;; Argument 1 is the source
5157 ;; Argument 2 is the length
5158 ;; Argument 3 is the alignment
5160 (define_expand "movmemsi"
5161 [(parallel [(set (match_operand:BLK 0 "general_operand")
5162 (match_operand:BLK 1 "general_operand"))
5163 (use (match_operand:SI 2 ""))
5164 (use (match_operand:SI 3 "const_int_operand"))])]
5165 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5167 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5174 ;; ....................
5178 ;; ....................
5180 (define_expand "<optab><mode>3"
5181 [(set (match_operand:GPR 0 "register_operand")
5182 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5183 (match_operand:SI 2 "arith_operand")))]
5186 /* On the mips16, a shift of more than 8 is a four byte instruction,
5187 so, for a shift between 8 and 16, it is just as fast to do two
5188 shifts of 8 or less. If there is a lot of shifting going on, we
5189 may win in CSE. Otherwise combine will put the shifts back
5190 together again. This can be called by mips_function_arg, so we must
5191 be careful not to allocate a new register if we've reached the
5195 && CONST_INT_P (operands[2])
5196 && INTVAL (operands[2]) > 8
5197 && INTVAL (operands[2]) <= 16
5198 && !reload_in_progress
5199 && !reload_completed)
5201 rtx temp = gen_reg_rtx (<MODE>mode);
5203 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5204 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5205 GEN_INT (INTVAL (operands[2]) - 8)));
5210 (define_insn "*<optab><mode>3"
5211 [(set (match_operand:GPR 0 "register_operand" "=d")
5212 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
5213 (match_operand:SI 2 "arith_operand" "dI")))]
5216 if (CONST_INT_P (operands[2]))
5217 operands[2] = GEN_INT (INTVAL (operands[2])
5218 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5220 return "<d><insn>\t%0,%1,%2";
5222 [(set_attr "type" "shift")
5223 (set_attr "mode" "<MODE>")])
5225 (define_insn "*<optab>si3_extend"
5226 [(set (match_operand:DI 0 "register_operand" "=d")
5228 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5229 (match_operand:SI 2 "arith_operand" "dI"))))]
5230 "TARGET_64BIT && !TARGET_MIPS16"
5232 if (CONST_INT_P (operands[2]))
5233 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5235 return "<insn>\t%0,%1,%2";
5237 [(set_attr "type" "shift")
5238 (set_attr "mode" "SI")])
5240 (define_insn "*<optab>si3_mips16"
5241 [(set (match_operand:SI 0 "register_operand" "=d,d")
5242 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
5243 (match_operand:SI 2 "arith_operand" "d,I")))]
5246 if (which_alternative == 0)
5247 return "<insn>\t%0,%2";
5249 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5250 return "<insn>\t%0,%1,%2";
5252 [(set_attr "type" "shift")
5253 (set_attr "mode" "SI")
5254 (set_attr_alternative "length"
5256 (if_then_else (match_operand 2 "m16_uimm3_b")
5260 ;; We need separate DImode MIPS16 patterns because of the irregularity
5262 (define_insn "*ashldi3_mips16"
5263 [(set (match_operand:DI 0 "register_operand" "=d,d")
5264 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
5265 (match_operand:SI 2 "arith_operand" "d,I")))]
5266 "TARGET_64BIT && TARGET_MIPS16"
5268 if (which_alternative == 0)
5269 return "dsll\t%0,%2";
5271 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5272 return "dsll\t%0,%1,%2";
5274 [(set_attr "type" "shift")
5275 (set_attr "mode" "DI")
5276 (set_attr_alternative "length"
5278 (if_then_else (match_operand 2 "m16_uimm3_b")
5282 (define_insn "*ashrdi3_mips16"
5283 [(set (match_operand:DI 0 "register_operand" "=d,d")
5284 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5285 (match_operand:SI 2 "arith_operand" "d,I")))]
5286 "TARGET_64BIT && TARGET_MIPS16"
5288 if (CONST_INT_P (operands[2]))
5289 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5291 return "dsra\t%0,%2";
5293 [(set_attr "type" "shift")
5294 (set_attr "mode" "DI")
5295 (set_attr_alternative "length"
5297 (if_then_else (match_operand 2 "m16_uimm3_b")
5301 (define_insn "*lshrdi3_mips16"
5302 [(set (match_operand:DI 0 "register_operand" "=d,d")
5303 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5304 (match_operand:SI 2 "arith_operand" "d,I")))]
5305 "TARGET_64BIT && TARGET_MIPS16"
5307 if (CONST_INT_P (operands[2]))
5308 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5310 return "dsrl\t%0,%2";
5312 [(set_attr "type" "shift")
5313 (set_attr "mode" "DI")
5314 (set_attr_alternative "length"
5316 (if_then_else (match_operand 2 "m16_uimm3_b")
5320 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5323 [(set (match_operand:GPR 0 "d_operand")
5324 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5325 (match_operand:GPR 2 "const_int_operand")))]
5326 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5327 && INTVAL (operands[2]) > 8
5328 && INTVAL (operands[2]) <= 16"
5329 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5330 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5331 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5333 ;; If we load a byte on the mips16 as a bitfield, the resulting
5334 ;; sequence of instructions is too complicated for combine, because it
5335 ;; involves four instructions: a load, a shift, a constant load into a
5336 ;; register, and an and (the key problem here is that the mips16 does
5337 ;; not have and immediate). We recognize a shift of a load in order
5338 ;; to make it simple enough for combine to understand.
5340 ;; The length here is the worst case: the length of the split version
5341 ;; will be more accurate.
5342 (define_insn_and_split ""
5343 [(set (match_operand:SI 0 "register_operand" "=d")
5344 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5345 (match_operand:SI 2 "immediate_operand" "I")))]
5349 [(set (match_dup 0) (match_dup 1))
5350 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5352 [(set_attr "type" "load")
5353 (set_attr "mode" "SI")
5354 (set_attr "length" "16")])
5356 (define_insn "rotr<mode>3"
5357 [(set (match_operand:GPR 0 "register_operand" "=d")
5358 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5359 (match_operand:SI 2 "arith_operand" "dI")))]
5362 if (CONST_INT_P (operands[2]))
5363 gcc_assert (INTVAL (operands[2]) >= 0
5364 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5366 return "<d>ror\t%0,%1,%2";
5368 [(set_attr "type" "shift")
5369 (set_attr "mode" "<MODE>")])
5372 ;; ....................
5374 ;; CONDITIONAL BRANCHES
5376 ;; ....................
5378 ;; Conditional branches on floating-point equality tests.
5380 (define_insn "*branch_fp"
5383 (match_operator 1 "equality_operator"
5384 [(match_operand:CC 2 "register_operand" "z")
5386 (label_ref (match_operand 0 "" ""))
5390 return mips_output_conditional_branch (insn, operands,
5391 MIPS_BRANCH ("b%F1", "%Z2%0"),
5392 MIPS_BRANCH ("b%W1", "%Z2%0"));
5394 [(set_attr "type" "branch")])
5396 (define_insn "*branch_fp_inverted"
5399 (match_operator 1 "equality_operator"
5400 [(match_operand:CC 2 "register_operand" "z")
5403 (label_ref (match_operand 0 "" ""))))]
5406 return mips_output_conditional_branch (insn, operands,
5407 MIPS_BRANCH ("b%W1", "%Z2%0"),
5408 MIPS_BRANCH ("b%F1", "%Z2%0"));
5410 [(set_attr "type" "branch")])
5412 ;; Conditional branches on ordered comparisons with zero.
5414 (define_insn "*branch_order<mode>"
5417 (match_operator 1 "order_operator"
5418 [(match_operand:GPR 2 "register_operand" "d")
5420 (label_ref (match_operand 0 "" ""))
5423 { return mips_output_order_conditional_branch (insn, operands, false); }
5424 [(set_attr "type" "branch")])
5426 (define_insn "*branch_order<mode>_inverted"
5429 (match_operator 1 "order_operator"
5430 [(match_operand:GPR 2 "register_operand" "d")
5433 (label_ref (match_operand 0 "" ""))))]
5435 { return mips_output_order_conditional_branch (insn, operands, true); }
5436 [(set_attr "type" "branch")])
5438 ;; Conditional branch on equality comparison.
5440 (define_insn "*branch_equality<mode>"
5443 (match_operator 1 "equality_operator"
5444 [(match_operand:GPR 2 "register_operand" "d")
5445 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5446 (label_ref (match_operand 0 "" ""))
5450 return mips_output_conditional_branch (insn, operands,
5451 MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
5452 MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
5454 [(set_attr "type" "branch")])
5456 (define_insn "*branch_equality<mode>_inverted"
5459 (match_operator 1 "equality_operator"
5460 [(match_operand:GPR 2 "register_operand" "d")
5461 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5463 (label_ref (match_operand 0 "" ""))))]
5466 return mips_output_conditional_branch (insn, operands,
5467 MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
5468 MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
5470 [(set_attr "type" "branch")])
5474 (define_insn "*branch_equality<mode>_mips16"
5477 (match_operator 1 "equality_operator"
5478 [(match_operand:GPR 2 "register_operand" "d,t")
5480 (label_ref (match_operand 0 "" ""))
5486 [(set_attr "type" "branch")])
5488 (define_insn "*branch_equality<mode>_mips16_inverted"
5491 (match_operator 1 "equality_operator"
5492 [(match_operand:GPR 2 "register_operand" "d,t")
5495 (label_ref (match_operand 0 "" ""))))]
5500 [(set_attr "type" "branch")])
5502 (define_expand "cbranch<mode>4"
5504 (if_then_else (match_operator 0 "comparison_operator"
5505 [(match_operand:GPR 1 "register_operand")
5506 (match_operand:GPR 2 "nonmemory_operand")])
5507 (label_ref (match_operand 3 ""))
5511 mips_expand_conditional_branch (operands);
5515 (define_expand "cbranch<mode>4"
5517 (if_then_else (match_operator 0 "comparison_operator"
5518 [(match_operand:SCALARF 1 "register_operand")
5519 (match_operand:SCALARF 2 "register_operand")])
5520 (label_ref (match_operand 3 ""))
5524 mips_expand_conditional_branch (operands);
5528 ;; Used to implement built-in functions.
5529 (define_expand "condjump"
5531 (if_then_else (match_operand 0)
5532 (label_ref (match_operand 1))
5535 ;; Branch if bit is set/clear.
5537 (define_insn "*branch_bit<bbv><mode>"
5540 (equality_op (zero_extract:GPR
5541 (match_operand:GPR 1 "register_operand" "d")
5543 (match_operand 2 "const_int_operand" ""))
5545 (label_ref (match_operand 0 ""))
5547 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5550 mips_output_conditional_branch (insn, operands,
5551 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5552 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5554 [(set_attr "type" "branch")
5555 (set_attr "branch_likely" "no")])
5557 (define_insn "*branch_bit<bbv><mode>_inverted"
5560 (equality_op (zero_extract:GPR
5561 (match_operand:GPR 1 "register_operand" "d")
5563 (match_operand 2 "const_int_operand" ""))
5566 (label_ref (match_operand 0 ""))))]
5567 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5570 mips_output_conditional_branch (insn, operands,
5571 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5572 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5574 [(set_attr "type" "branch")
5575 (set_attr "branch_likely" "no")])
5578 ;; ....................
5580 ;; SETTING A REGISTER FROM A COMPARISON
5582 ;; ....................
5584 ;; Destination is always set in SI mode.
5586 (define_expand "cstore<mode>4"
5587 [(set (match_operand:SI 0 "register_operand")
5588 (match_operator:SI 1 "mips_cstore_operator"
5589 [(match_operand:GPR 2 "register_operand")
5590 (match_operand:GPR 3 "nonmemory_operand")]))]
5593 mips_expand_scc (operands);
5597 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5598 [(set (match_operand:GPR2 0 "register_operand" "=d")
5599 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5601 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5603 [(set_attr "type" "slt")
5604 (set_attr "mode" "<GPR:MODE>")])
5606 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5607 [(set (match_operand:GPR2 0 "register_operand" "=t")
5608 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5610 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5612 [(set_attr "type" "slt")
5613 (set_attr "mode" "<GPR:MODE>")])
5615 ;; Generate sltiu unless using seq results in better code.
5616 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5617 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5618 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5619 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5625 [(set_attr "type" "slt")
5626 (set_attr "mode" "<GPR:MODE>")])
5628 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5629 [(set (match_operand:GPR2 0 "register_operand" "=d")
5630 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5632 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5634 [(set_attr "type" "slt")
5635 (set_attr "mode" "<GPR:MODE>")])
5637 ;; Generate sltu unless using sne results in better code.
5638 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5639 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5640 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5641 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5647 [(set_attr "type" "slt")
5648 (set_attr "mode" "<GPR:MODE>")])
5650 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5651 [(set (match_operand:GPR2 0 "register_operand" "=d")
5652 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5653 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5656 [(set_attr "type" "slt")
5657 (set_attr "mode" "<GPR:MODE>")])
5659 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5660 [(set (match_operand:GPR2 0 "register_operand" "=t")
5661 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5662 (match_operand:GPR 2 "register_operand" "d")))]
5665 [(set_attr "type" "slt")
5666 (set_attr "mode" "<GPR:MODE>")])
5668 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5669 [(set (match_operand:GPR2 0 "register_operand" "=d")
5670 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5674 [(set_attr "type" "slt")
5675 (set_attr "mode" "<GPR:MODE>")])
5677 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5678 [(set (match_operand:GPR2 0 "register_operand" "=d")
5679 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5680 (match_operand:GPR 2 "arith_operand" "dI")))]
5683 [(set_attr "type" "slt")
5684 (set_attr "mode" "<GPR:MODE>")])
5686 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5687 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5688 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5689 (match_operand:GPR 2 "arith_operand" "d,I")))]
5692 [(set_attr "type" "slt")
5693 (set_attr "mode" "<GPR:MODE>")
5694 (set_attr_alternative "length"
5696 (if_then_else (match_operand 2 "m16_uimm8_1")
5700 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5701 [(set (match_operand:GPR2 0 "register_operand" "=d")
5702 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5703 (match_operand:GPR 2 "sle_operand" "")))]
5706 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5707 return "slt<u>\t%0,%1,%2";
5709 [(set_attr "type" "slt")
5710 (set_attr "mode" "<GPR:MODE>")])
5712 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5713 [(set (match_operand:GPR2 0 "register_operand" "=t")
5714 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5715 (match_operand:GPR 2 "sle_operand" "")))]
5718 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5719 return "slt<u>\t%1,%2";
5721 [(set_attr "type" "slt")
5722 (set_attr "mode" "<GPR:MODE>")
5723 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5728 ;; ....................
5730 ;; FLOATING POINT COMPARISONS
5732 ;; ....................
5734 (define_insn "s<code>_<mode>"
5735 [(set (match_operand:CC 0 "register_operand" "=z")
5736 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5737 (match_operand:SCALARF 2 "register_operand" "f")))]
5739 "c.<fcond>.<fmt>\t%Z0%1,%2"
5740 [(set_attr "type" "fcmp")
5741 (set_attr "mode" "FPSW")])
5743 (define_insn "s<code>_<mode>"
5744 [(set (match_operand:CC 0 "register_operand" "=z")
5745 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5746 (match_operand:SCALARF 2 "register_operand" "f")))]
5748 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5749 [(set_attr "type" "fcmp")
5750 (set_attr "mode" "FPSW")])
5753 ;; ....................
5755 ;; UNCONDITIONAL BRANCHES
5757 ;; ....................
5759 ;; Unconditional branches.
5761 (define_expand "jump"
5763 (label_ref (match_operand 0)))])
5765 (define_insn "*jump_absolute"
5767 (label_ref (match_operand 0)))]
5768 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
5769 { return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); }
5770 [(set_attr "type" "jump")])
5772 (define_insn "*jump_pic"
5774 (label_ref (match_operand 0)))]
5775 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
5777 if (get_attr_length (insn) <= 8)
5778 return "%*b\t%l0%/";
5781 mips_output_load_label (operands[0]);
5782 return "%*jr\t%@%/%]";
5785 [(set_attr "type" "branch")])
5787 ;; We need a different insn for the mips16, because a mips16 branch
5788 ;; does not have a delay slot.
5790 (define_insn "*jump_mips16"
5792 (label_ref (match_operand 0 "" "")))]
5795 [(set_attr "type" "branch")
5796 (set (attr "length")
5797 ;; This calculation is like the normal branch one, but the
5798 ;; range of the unextended instruction is [-0x800, 0x7fe] rather
5799 ;; than [-0x100, 0xfe]. This translates to a range of:
5801 ;; [-(0x800 - sizeof (branch)), 0x7fe]
5802 ;; == [-0x7fe, 0x7fe]
5804 ;; from the shorten_branches reference address. Long-branch
5805 ;; sequences will replace this one, so the minimum length
5806 ;; is one instruction shorter than for conditional branches.
5807 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
5808 (le (minus (pc) (match_dup 0)) (const_int 2046)))
5810 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
5811 (le (minus (pc) (match_dup 0)) (const_int 65532)))
5813 (and (match_test "TARGET_ABICALLS")
5814 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
5816 (match_test "Pmode == SImode")
5818 ] (const_int 44)))])
5820 (define_expand "indirect_jump"
5821 [(set (pc) (match_operand 0 "register_operand"))]
5824 operands[0] = force_reg (Pmode, operands[0]);
5825 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0])));
5829 (define_insn "indirect_jump_<mode>"
5830 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5833 [(set_attr "type" "jump")
5834 (set_attr "mode" "none")])
5836 ;; A combined jump-and-move instruction, used for MIPS16 long-branch
5837 ;; sequences. Having a dedicated pattern is more convenient than
5838 ;; creating a SEQUENCE for this special case.
5839 (define_insn "indirect_jump_and_restore_<mode>"
5840 [(set (pc) (match_operand:P 1 "register_operand" "d"))
5841 (set (match_operand:P 0 "register_operand" "=d")
5842 (match_operand:P 2 "register_operand" "y"))]
5844 "%(%<jr\t%1\;move\t%0,%2%>%)"
5845 [(set_attr "type" "multi")
5846 (set_attr "extended_mips16" "yes")])
5848 (define_expand "tablejump"
5850 (match_operand 0 "register_operand"))
5851 (use (label_ref (match_operand 1 "")))]
5852 "!TARGET_MIPS16_SHORT_JUMP_TABLES"
5855 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5856 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5857 else if (TARGET_RTP_PIC)
5859 /* When generating RTP PIC, we use case table entries that are relative
5860 to the start of the function. Add the function's address to the
5862 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5863 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5864 start, 0, 0, OPTAB_WIDEN);
5867 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1])));
5871 (define_insn "tablejump_<mode>"
5873 (match_operand:P 0 "register_operand" "d"))
5874 (use (label_ref (match_operand 1 "" "")))]
5877 [(set_attr "type" "jump")
5878 (set_attr "mode" "none")])
5880 ;; For MIPS16, we don't know whether a given jump table will use short or
5881 ;; word-sized offsets until late in compilation, when we are able to determine
5882 ;; the sizes of the insns which comprise the containing function. This
5883 ;; necessitates the use of the casesi rather than the tablejump pattern, since
5884 ;; the latter tries to calculate the index of the offset to jump through early
5885 ;; in compilation, i.e. at expand time, when nothing is known about the
5886 ;; eventual function layout.
5888 (define_expand "casesi"
5889 [(match_operand:SI 0 "register_operand" "") ; index to jump on
5890 (match_operand:SI 1 "const_int_operand" "") ; lower bound
5891 (match_operand:SI 2 "const_int_operand" "") ; total range
5892 (match_operand 3 "" "") ; table label
5893 (match_operand 4 "" "")] ; out of range label
5894 "TARGET_MIPS16_SHORT_JUMP_TABLES"
5896 if (operands[1] != const0_rtx)
5898 rtx reg = gen_reg_rtx (SImode);
5899 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode);
5901 if (!arith_operand (offset, SImode))
5902 offset = force_reg (SImode, offset);
5904 emit_insn (gen_addsi3 (reg, operands[0], offset));
5908 if (!arith_operand (operands[0], SImode))
5909 operands[0] = force_reg (SImode, operands[0]);
5911 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5913 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16,
5914 (operands[0], operands[2],
5915 operands[3], operands[4])));
5920 (define_insn "casesi_internal_mips16_<mode>"
5923 (leu (match_operand:SI 0 "register_operand" "d")
5924 (match_operand:SI 1 "arith_operand" "dI"))
5927 (label_ref (match_operand 2 "" ""))]
5928 UNSPEC_CASESI_DISPATCH)
5929 (label_ref (match_operand 3 "" ""))))
5930 (clobber (match_scratch:P 4 "=d"))
5931 (clobber (match_scratch:P 5 "=d"))
5932 (clobber (reg:SI MIPS16_T_REGNUM))]
5933 "TARGET_MIPS16_SHORT_JUMP_TABLES"
5935 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
5937 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
5939 output_asm_insn ("sltu\t%0, %1", operands);
5940 output_asm_insn ("bteqz\t%3", operands);
5942 switch (GET_MODE (diff_vec))
5945 output_asm_insn ("sll\t%5, %0, 1", operands);
5946 output_asm_insn ("la\t%4, %2", operands);
5947 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
5948 output_asm_insn ("lh\t%5, 0(%5)", operands);
5952 output_asm_insn ("sll\t%5, %0, 2", operands);
5953 output_asm_insn ("la\t%4, %2", operands);
5954 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
5955 output_asm_insn ("lw\t%5, 0(%5)", operands);
5962 output_asm_insn ("addu\t%4, %4, %5", operands);
5966 [(set_attr "length" "32")])
5968 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5969 ;; While it is possible to either pull it off the stack (in the
5970 ;; o32 case) or recalculate it given t9 and our target label,
5971 ;; it takes 3 or 4 insns to do so.
5973 (define_expand "builtin_setjmp_setup"
5974 [(use (match_operand 0 "register_operand"))]
5979 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3);
5980 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5984 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5985 ;; that older code did recalculate the gp from $25. Continue to jump through
5986 ;; $25 for compatibility (we lose nothing by doing so).
5988 (define_expand "builtin_longjmp"
5989 [(use (match_operand 0 "register_operand"))]
5992 /* The elements of the buffer are, in order: */
5993 int W = GET_MODE_SIZE (Pmode);
5994 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5995 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W));
5996 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W));
5997 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W));
5998 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5999 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
6000 The target is bound to be using $28 as the global pointer
6001 but the current function might not be. */
6002 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
6004 /* This bit is similar to expand_builtin_longjmp except that it
6005 restores $gp as well. */
6006 mips_emit_move (hard_frame_pointer_rtx, fp);
6007 mips_emit_move (pv, lab);
6008 emit_stack_restore (SAVE_NONLOCAL, stack);
6009 mips_emit_move (gp, gpv);
6010 emit_use (hard_frame_pointer_rtx);
6011 emit_use (stack_pointer_rtx);
6013 emit_indirect_jump (pv);
6018 ;; ....................
6020 ;; Function prologue/epilogue
6022 ;; ....................
6025 (define_expand "prologue"
6029 mips_expand_prologue ();
6033 ;; Block any insns from being moved before this point, since the
6034 ;; profiling call to mcount can use various registers that aren't
6035 ;; saved or used to pass arguments.
6037 (define_insn "blockage"
6038 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
6041 [(set_attr "type" "ghost")
6042 (set_attr "mode" "none")])
6044 (define_insn "probe_stack_range_<P:mode>"
6045 [(set (match_operand:P 0 "register_operand" "=d")
6046 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
6047 (match_operand:P 2 "register_operand" "d")]
6048 UNSPEC_PROBE_STACK_RANGE))]
6050 { return mips_output_probe_stack_range (operands[0], operands[2]); }
6051 [(set_attr "type" "unknown")
6052 (set_attr "can_delay" "no")
6053 (set_attr "mode" "<MODE>")])
6055 (define_expand "epilogue"
6059 mips_expand_epilogue (false);
6063 (define_expand "sibcall_epilogue"
6067 mips_expand_epilogue (true);
6071 ;; Trivial return. Make it look like a normal return insn as that
6072 ;; allows jump optimizations to work better.
6074 (define_expand "return"
6076 "mips_can_use_return_insn ()"
6077 { mips_expand_before_return (); })
6079 (define_expand "simple_return"
6082 { mips_expand_before_return (); })
6084 (define_insn "*<optab>"
6088 [(set_attr "type" "jump")
6089 (set_attr "mode" "none")])
6093 (define_insn "<optab>_internal"
6095 (use (match_operand 0 "pmode_register_operand" ""))]
6098 [(set_attr "type" "jump")
6099 (set_attr "mode" "none")])
6101 ;; Exception return.
6102 (define_insn "mips_eret"
6104 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
6107 [(set_attr "type" "trap")
6108 (set_attr "mode" "none")])
6110 ;; Debug exception return.
6111 (define_insn "mips_deret"
6113 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
6116 [(set_attr "type" "trap")
6117 (set_attr "mode" "none")])
6119 ;; Disable interrupts.
6120 (define_insn "mips_di"
6121 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
6124 [(set_attr "type" "trap")
6125 (set_attr "mode" "none")])
6127 ;; Execution hazard barrier.
6128 (define_insn "mips_ehb"
6129 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
6132 [(set_attr "type" "trap")
6133 (set_attr "mode" "none")])
6135 ;; Read GPR from previous shadow register set.
6136 (define_insn "mips_rdpgpr"
6137 [(set (match_operand:SI 0 "register_operand" "=d")
6138 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
6142 [(set_attr "type" "move")
6143 (set_attr "mode" "SI")])
6145 ;; Move involving COP0 registers.
6146 (define_insn "cop0_move"
6147 [(set (match_operand:SI 0 "register_operand" "=B,d")
6148 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
6151 { return mips_output_move (operands[0], operands[1]); }
6152 [(set_attr "type" "mtc,mfc")
6153 (set_attr "mode" "SI")])
6155 ;; This is used in compiling the unwind routines.
6156 (define_expand "eh_return"
6157 [(use (match_operand 0 "general_operand"))]
6160 if (GET_MODE (operands[0]) != word_mode)
6161 operands[0] = convert_to_mode (word_mode, operands[0], 0);
6163 emit_insn (gen_eh_set_lr_di (operands[0]));
6165 emit_insn (gen_eh_set_lr_si (operands[0]));
6169 ;; Clobber the return address on the stack. We can't expand this
6170 ;; until we know where it will be put in the stack frame.
6172 (define_insn "eh_set_lr_si"
6173 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6174 (clobber (match_scratch:SI 1 "=&d"))]
6178 (define_insn "eh_set_lr_di"
6179 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6180 (clobber (match_scratch:DI 1 "=&d"))]
6185 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
6186 (clobber (match_scratch 1))]
6190 mips_set_return_address (operands[0], operands[1]);
6194 (define_expand "exception_receiver"
6198 /* See the comment above load_call<mode> for details. */
6199 emit_insn (gen_set_got_version ());
6201 /* If we have a call-clobbered $gp, restore it from its save slot. */
6202 if (HAVE_restore_gp_si)
6203 emit_insn (gen_restore_gp_si ());
6204 else if (HAVE_restore_gp_di)
6205 emit_insn (gen_restore_gp_di ());
6209 (define_expand "nonlocal_goto_receiver"
6213 /* See the comment above load_call<mode> for details. */
6214 emit_insn (gen_set_got_version ());
6218 ;; Restore $gp from its .cprestore stack slot. The instruction remains
6219 ;; volatile until all uses of $28 are exposed.
6220 (define_insn_and_split "restore_gp_<mode>"
6222 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP))
6223 (clobber (match_scratch:P 0 "=&d"))]
6224 "TARGET_CALL_CLOBBERED_GP"
6226 "&& epilogue_completed"
6229 mips_restore_gp_from_cprestore_slot (operands[0]);
6232 [(set_attr "type" "ghost")])
6234 ;; Move between $gp and its register save slot.
6235 (define_insn_and_split "move_gp<mode>"
6236 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
6237 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
6240 { return mips_must_initialize_gp_p () ? "#" : ""; }
6241 "mips_must_initialize_gp_p ()"
6244 mips_emit_move (operands[0], operands[1]);
6247 [(set_attr "type" "ghost")])
6250 ;; ....................
6254 ;; ....................
6256 ;; Instructions to load a call address from the GOT. The address might
6257 ;; point to a function or to a lazy binding stub. In the latter case,
6258 ;; the stub will use the dynamic linker to resolve the function, which
6259 ;; in turn will change the GOT entry to point to the function's real
6262 ;; This means that every call, even pure and constant ones, can
6263 ;; potentially modify the GOT entry. And once a stub has been called,
6264 ;; we must not call it again.
6266 ;; We represent this restriction using an imaginary, fixed, call-saved
6267 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
6268 ;; live throughout the function and to change its value after every
6269 ;; potential call site. This stops any rtx value that uses the register
6270 ;; from being computed before an earlier call. To do this, we:
6272 ;; - Ensure that the register is live on entry to the function,
6273 ;; so that it is never thought to be used uninitalized.
6275 ;; - Ensure that the register is live on exit from the function,
6276 ;; so that it is live throughout.
6278 ;; - Make each call (lazily-bound or not) use the current value
6279 ;; of GOT_VERSION_REGNUM, so that updates of the register are
6280 ;; not moved across call boundaries.
6282 ;; - Add "ghost" definitions of the register to the beginning of
6283 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
6284 ;; edges may involve calls that normal paths don't. (E.g. the
6285 ;; unwinding code that handles a non-call exception may change
6286 ;; lazily-bound GOT entries.) We do this by making the
6287 ;; exception_receiver and nonlocal_goto_receiver expanders emit
6288 ;; a set_got_version instruction.
6290 ;; - After each call (lazily-bound or not), use a "ghost"
6291 ;; update_got_version instruction to change the register's value.
6292 ;; This instruction mimics the _possible_ effect of the dynamic
6293 ;; resolver during the call and it remains live even if the call
6294 ;; itself becomes dead.
6296 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
6297 ;; The register is therefore not a valid register_operand
6298 ;; and cannot be moved to or from other registers.
6300 (define_insn "load_call<mode>"
6301 [(set (match_operand:P 0 "register_operand" "=d")
6302 (unspec:P [(match_operand:P 1 "register_operand" "d")
6303 (match_operand:P 2 "immediate_operand" "")
6304 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
6306 "<load>\t%0,%R2(%1)"
6307 [(set_attr "got" "load")
6308 (set_attr "mode" "<MODE>")])
6310 (define_insn "set_got_version"
6311 [(set (reg:SI GOT_VERSION_REGNUM)
6312 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
6315 [(set_attr "type" "ghost")])
6317 (define_insn "update_got_version"
6318 [(set (reg:SI GOT_VERSION_REGNUM)
6319 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
6322 [(set_attr "type" "ghost")])
6324 ;; Sibling calls. All these patterns use jump instructions.
6326 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
6327 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
6328 ;; is defined in terms of call_insn_operand, the same is true of the
6331 ;; When we use an indirect jump, we need a register that will be
6332 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
6333 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
6334 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
6337 (define_expand "sibcall"
6338 [(parallel [(call (match_operand 0 "")
6339 (match_operand 1 ""))
6340 (use (match_operand 2 "")) ;; next_arg_reg
6341 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6344 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
6345 operands[1], operands[2], false);
6349 (define_insn "sibcall_internal"
6350 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
6351 (match_operand 1 "" ""))]
6352 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6353 { return MIPS_CALL ("j", operands, 0, 1); }
6354 [(set_attr "jal" "indirect,direct")
6355 (set_attr "jal_macro" "no")])
6357 (define_expand "sibcall_value"
6358 [(parallel [(set (match_operand 0 "")
6359 (call (match_operand 1 "")
6360 (match_operand 2 "")))
6361 (use (match_operand 3 ""))])] ;; next_arg_reg
6364 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
6365 operands[2], operands[3], false);
6369 (define_insn "sibcall_value_internal"
6370 [(set (match_operand 0 "register_operand" "")
6371 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6372 (match_operand 2 "" "")))]
6373 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6374 { return MIPS_CALL ("j", operands, 1, 2); }
6375 [(set_attr "jal" "indirect,direct")
6376 (set_attr "jal_macro" "no")])
6378 (define_insn "sibcall_value_multiple_internal"
6379 [(set (match_operand 0 "register_operand" "")
6380 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6381 (match_operand 2 "" "")))
6382 (set (match_operand 3 "register_operand" "")
6383 (call (mem:SI (match_dup 1))
6385 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6386 { return MIPS_CALL ("j", operands, 1, 2); }
6387 [(set_attr "jal" "indirect,direct")
6388 (set_attr "jal_macro" "no")])
6390 (define_expand "call"
6391 [(parallel [(call (match_operand 0 "")
6392 (match_operand 1 ""))
6393 (use (match_operand 2 "")) ;; next_arg_reg
6394 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6397 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6398 operands[1], operands[2], false);
6402 ;; This instruction directly corresponds to an assembly-language "jal".
6403 ;; There are four cases:
6406 ;; Both symbolic and register destinations are OK. The pattern
6407 ;; always expands to a single mips instruction.
6409 ;; - -mabicalls/-mno-explicit-relocs:
6410 ;; Again, both symbolic and register destinations are OK.
6411 ;; The call is treated as a multi-instruction black box.
6413 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6414 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6417 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6418 ;; Only "jal $25" is allowed. The call is actually two instructions:
6419 ;; "jalr $25" followed by an insn to reload $gp.
6421 ;; In the last case, we can generate the individual instructions with
6422 ;; a define_split. There are several things to be wary of:
6424 ;; - We can't expose the load of $gp before reload. If we did,
6425 ;; it might get removed as dead, but reload can introduce new
6426 ;; uses of $gp by rematerializing constants.
6428 ;; - We shouldn't restore $gp after calls that never return.
6429 ;; It isn't valid to insert instructions between a noreturn
6430 ;; call and the following barrier.
6432 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6433 ;; instruction preserves $gp and so have no effect on its liveness.
6434 ;; But once we generate the separate insns, it becomes obvious that
6435 ;; $gp is not live on entry to the call.
6437 (define_insn_and_split "call_internal"
6438 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6439 (match_operand 1 "" ""))
6440 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6442 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6443 "reload_completed && TARGET_SPLIT_CALLS"
6446 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6449 [(set_attr "jal" "indirect,direct")])
6451 (define_insn "call_split"
6452 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6453 (match_operand 1 "" ""))
6454 (clobber (reg:SI RETURN_ADDR_REGNUM))
6455 (clobber (reg:SI 28))]
6456 "TARGET_SPLIT_CALLS"
6457 { return MIPS_CALL ("jal", operands, 0, 1); }
6458 [(set_attr "jal" "indirect,direct")
6459 (set_attr "jal_macro" "no")])
6461 ;; A pattern for calls that must be made directly. It is used for
6462 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6463 ;; stub; the linker relies on the call relocation type to detect when
6464 ;; such redirection is needed.
6465 (define_insn_and_split "call_internal_direct"
6466 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6469 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6471 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6472 "reload_completed && TARGET_SPLIT_CALLS"
6475 mips_split_call (curr_insn,
6476 gen_call_direct_split (operands[0], operands[1]));
6479 [(set_attr "jal" "direct")])
6481 (define_insn "call_direct_split"
6482 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6485 (clobber (reg:SI RETURN_ADDR_REGNUM))
6486 (clobber (reg:SI 28))]
6487 "TARGET_SPLIT_CALLS"
6488 { return MIPS_CALL ("jal", operands, 0, -1); }
6489 [(set_attr "jal" "direct")
6490 (set_attr "jal_macro" "no")])
6492 (define_expand "call_value"
6493 [(parallel [(set (match_operand 0 "")
6494 (call (match_operand 1 "")
6495 (match_operand 2 "")))
6496 (use (match_operand 3 ""))])] ;; next_arg_reg
6499 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6500 operands[2], operands[3], false);
6504 ;; See comment for call_internal.
6505 (define_insn_and_split "call_value_internal"
6506 [(set (match_operand 0 "register_operand" "")
6507 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6508 (match_operand 2 "" "")))
6509 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6511 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6512 "reload_completed && TARGET_SPLIT_CALLS"
6515 mips_split_call (curr_insn,
6516 gen_call_value_split (operands[0], operands[1],
6520 [(set_attr "jal" "indirect,direct")])
6522 (define_insn "call_value_split"
6523 [(set (match_operand 0 "register_operand" "")
6524 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6525 (match_operand 2 "" "")))
6526 (clobber (reg:SI RETURN_ADDR_REGNUM))
6527 (clobber (reg:SI 28))]
6528 "TARGET_SPLIT_CALLS"
6529 { return MIPS_CALL ("jal", operands, 1, 2); }
6530 [(set_attr "jal" "indirect,direct")
6531 (set_attr "jal_macro" "no")])
6533 ;; See call_internal_direct.
6534 (define_insn_and_split "call_value_internal_direct"
6535 [(set (match_operand 0 "register_operand")
6536 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6539 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6541 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6542 "reload_completed && TARGET_SPLIT_CALLS"
6545 mips_split_call (curr_insn,
6546 gen_call_value_direct_split (operands[0], operands[1],
6550 [(set_attr "jal" "direct")])
6552 (define_insn "call_value_direct_split"
6553 [(set (match_operand 0 "register_operand")
6554 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6557 (clobber (reg:SI RETURN_ADDR_REGNUM))
6558 (clobber (reg:SI 28))]
6559 "TARGET_SPLIT_CALLS"
6560 { return MIPS_CALL ("jal", operands, 1, -1); }
6561 [(set_attr "jal" "direct")
6562 (set_attr "jal_macro" "no")])
6564 ;; See comment for call_internal.
6565 (define_insn_and_split "call_value_multiple_internal"
6566 [(set (match_operand 0 "register_operand" "")
6567 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6568 (match_operand 2 "" "")))
6569 (set (match_operand 3 "register_operand" "")
6570 (call (mem:SI (match_dup 1))
6572 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6574 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6575 "reload_completed && TARGET_SPLIT_CALLS"
6578 mips_split_call (curr_insn,
6579 gen_call_value_multiple_split (operands[0], operands[1],
6580 operands[2], operands[3]));
6583 [(set_attr "jal" "indirect,direct")])
6585 (define_insn "call_value_multiple_split"
6586 [(set (match_operand 0 "register_operand" "")
6587 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6588 (match_operand 2 "" "")))
6589 (set (match_operand 3 "register_operand" "")
6590 (call (mem:SI (match_dup 1))
6592 (clobber (reg:SI RETURN_ADDR_REGNUM))
6593 (clobber (reg:SI 28))]
6594 "TARGET_SPLIT_CALLS"
6595 { return MIPS_CALL ("jal", operands, 1, 2); }
6596 [(set_attr "jal" "indirect,direct")
6597 (set_attr "jal_macro" "no")])
6599 ;; Call subroutine returning any type.
6601 (define_expand "untyped_call"
6602 [(parallel [(call (match_operand 0 "")
6604 (match_operand 1 "")
6605 (match_operand 2 "")])]
6610 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6612 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6614 rtx set = XVECEXP (operands[2], 0, i);
6615 mips_emit_move (SET_DEST (set), SET_SRC (set));
6618 emit_insn (gen_blockage ());
6623 ;; ....................
6627 ;; ....................
6631 (define_insn "prefetch"
6632 [(prefetch (match_operand:QI 0 "address_operand" "p")
6633 (match_operand 1 "const_int_operand" "n")
6634 (match_operand 2 "const_int_operand" "n"))]
6635 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6637 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
6638 /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching. */
6639 return "ld\t$0,%a0";
6640 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6641 return "pref\t%1,%a0";
6643 [(set_attr "type" "prefetch")])
6645 (define_insn "*prefetch_indexed_<mode>"
6646 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6647 (match_operand:P 1 "register_operand" "d"))
6648 (match_operand 2 "const_int_operand" "n")
6649 (match_operand 3 "const_int_operand" "n"))]
6650 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6652 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6653 return "prefx\t%2,%1(%0)";
6655 [(set_attr "type" "prefetchx")])
6661 [(set_attr "type" "nop")
6662 (set_attr "mode" "none")])
6664 ;; Like nop, but commented out when outside a .set noreorder block.
6665 (define_insn "hazard_nop"
6669 if (mips_noreorder.nesting_level > 0)
6674 [(set_attr "type" "nop")])
6676 ;; MIPS4 Conditional move instructions.
6678 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6679 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6681 (match_operator:MOVECC 4 "equality_operator"
6682 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6684 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6685 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6690 [(set_attr "type" "condmove")
6691 (set_attr "mode" "<GPR:MODE>")])
6693 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6694 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6695 (if_then_else:SCALARF
6696 (match_operator:MOVECC 4 "equality_operator"
6697 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6699 (match_operand:SCALARF 2 "register_operand" "f,0")
6700 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6701 "ISA_HAS_FP_CONDMOVE"
6703 mov%T4.<fmt>\t%0,%2,%1
6704 mov%t4.<fmt>\t%0,%3,%1"
6705 [(set_attr "type" "condmove")
6706 (set_attr "mode" "<SCALARF:MODE>")])
6708 ;; These are the main define_expand's used to make conditional moves.
6710 (define_expand "mov<mode>cc"
6711 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6712 (set (match_operand:GPR 0 "register_operand")
6713 (if_then_else:GPR (match_dup 5)
6714 (match_operand:GPR 2 "reg_or_0_operand")
6715 (match_operand:GPR 3 "reg_or_0_operand")))]
6718 mips_expand_conditional_move (operands);
6722 (define_expand "mov<mode>cc"
6723 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6724 (set (match_operand:SCALARF 0 "register_operand")
6725 (if_then_else:SCALARF (match_dup 5)
6726 (match_operand:SCALARF 2 "register_operand")
6727 (match_operand:SCALARF 3 "register_operand")))]
6728 "ISA_HAS_FP_CONDMOVE"
6730 mips_expand_conditional_move (operands);
6735 ;; ....................
6737 ;; mips16 inline constant tables
6739 ;; ....................
6742 (define_insn "consttable_tls_reloc"
6743 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "")
6744 (match_operand 1 "const_int_operand" "")]
6745 UNSPEC_CONSTTABLE_INT)]
6746 "TARGET_MIPS16_PCREL_LOADS"
6747 { return mips_output_tls_reloc_directive (&operands[0]); }
6748 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6750 (define_insn "consttable_int"
6751 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6752 (match_operand 1 "const_int_operand" "")]
6753 UNSPEC_CONSTTABLE_INT)]
6756 assemble_integer (mips_strip_unspec_address (operands[0]),
6757 INTVAL (operands[1]),
6758 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6761 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6763 (define_insn "consttable_float"
6764 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6765 UNSPEC_CONSTTABLE_FLOAT)]
6770 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6771 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6772 assemble_real (d, GET_MODE (operands[0]),
6773 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6776 [(set (attr "length")
6777 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6779 (define_insn "align"
6780 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6783 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6786 [(match_operand 0 "small_data_pattern")]
6789 { operands[0] = mips_rewrite_small_data (operands[0]); })
6792 ;; ....................
6794 ;; MIPS16e Save/Restore
6796 ;; ....................
6799 (define_insn "*mips16e_save_restore"
6800 [(match_parallel 0 ""
6801 [(set (match_operand:SI 1 "register_operand")
6802 (plus:SI (match_dup 1)
6803 (match_operand:SI 2 "const_int_operand")))])]
6804 "operands[1] == stack_pointer_rtx
6805 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6806 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6807 [(set_attr "type" "arith")
6808 (set_attr "extended_mips16" "yes")])
6810 ;; Thread-Local Storage
6812 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6813 ;; MIPS architecture defines this register, and no current
6814 ;; implementation provides it; instead, any OS which supports TLS is
6815 ;; expected to trap and emulate this instruction. rdhwr is part of the
6816 ;; MIPS 32r2 specification, but we use it on any architecture because
6817 ;; we expect it to be emulated. Use .set to force the assembler to
6820 ;; We do not use a constraint to force the destination to be $3
6821 ;; because $3 can appear explicitly as a function return value.
6822 ;; If we leave the use of $3 implicit in the constraints until
6823 ;; reload, we may end up making a $3 return value live across
6824 ;; the instruction, leading to a spill failure when reloading it.
6825 (define_insn_and_split "tls_get_tp_<mode>"
6826 [(set (match_operand:P 0 "register_operand" "=d")
6827 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6828 (clobber (reg:P TLS_GET_TP_REGNUM))]
6829 "HAVE_AS_TLS && !TARGET_MIPS16"
6831 "&& reload_completed"
6832 [(set (reg:P TLS_GET_TP_REGNUM)
6833 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6834 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6836 [(set_attr "type" "unknown")
6837 ; Since rdhwr always generates a trap for now, putting it in a delay
6838 ; slot would make the kernel's emulation of it much slower.
6839 (set_attr "can_delay" "no")
6840 (set_attr "mode" "<MODE>")
6841 (set_attr "length" "8")])
6843 (define_insn "*tls_get_tp_<mode>_split"
6844 [(set (reg:P TLS_GET_TP_REGNUM)
6845 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6846 "HAVE_AS_TLS && !TARGET_MIPS16"
6847 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6848 [(set_attr "type" "unknown")
6849 ; See tls_get_tp_<mode>
6850 (set_attr "can_delay" "no")
6851 (set_attr "mode" "<MODE>")])
6853 ;; In MIPS16 mode, the TLS base pointer is accessed by a
6854 ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not
6855 ;; accessible in MIPS16.
6857 ;; This is not represented as a call insn, to avoid the
6858 ;; unnecesarry clobbering of caller-save registers by a
6859 ;; function consisting only of: "rdhwr $3,$29; j $31; nop;"
6861 ;; A $25 clobber is added to cater for a $25 load stub added by the
6862 ;; linker to __mips16_rdhwr when the call is made from non-PIC code.
6864 (define_insn_and_split "tls_get_tp_mips16_<mode>"
6865 [(set (match_operand:P 0 "register_operand" "=d")
6866 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")]
6868 (clobber (reg:P TLS_GET_TP_REGNUM))
6869 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6870 (clobber (reg:P RETURN_ADDR_REGNUM))]
6871 "HAVE_AS_TLS && TARGET_MIPS16"
6873 "&& reload_completed"
6874 [(parallel [(set (reg:P TLS_GET_TP_REGNUM)
6875 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP))
6876 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6877 (clobber (reg:P RETURN_ADDR_REGNUM))])
6878 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6880 [(set_attr "type" "multi")
6881 (set_attr "length" "16")
6882 (set_attr "mode" "<MODE>")])
6884 (define_insn "*tls_get_tp_mips16_call_<mode>"
6885 [(set (reg:P TLS_GET_TP_REGNUM)
6886 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")]
6888 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6889 (clobber (reg:P RETURN_ADDR_REGNUM))]
6890 "HAVE_AS_TLS && TARGET_MIPS16"
6891 { return MIPS_CALL ("jal", operands, 0, -1); }
6892 [(set_attr "type" "call")
6893 (set_attr "length" "12")
6894 (set_attr "mode" "<MODE>")])
6896 ;; Named pattern for expanding thread pointer reference.
6897 (define_expand "get_thread_pointer<mode>"
6898 [(match_operand:P 0 "register_operand" "=d")]
6901 mips_expand_thread_pointer (operands[0]);
6906 ;; Synchronization instructions.
6910 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6912 (include "mips-ps-3d.md")
6914 ; The MIPS DSP Instructions.
6916 (include "mips-dsp.md")
6918 ; The MIPS DSP REV 2 Instructions.
6920 (include "mips-dspr2.md")
6922 ; MIPS fixed-point instructions.
6923 (include "mips-fixed.md")
6925 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6926 (include "loongson.md")
6928 (define_c_enum "unspec" [
6929 UNSPEC_ADDRESS_FIRST