1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 ;; Free Software Foundation, Inc.
6 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
7 ;; Changes by Michael Meissner, meissner@osf.org
8 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 ;; Brendan Eich, brendan@microunity.com.
11 ;; This file is part of GCC.
13 ;; GCC is free software; you can redistribute it and/or modify
14 ;; it under the terms of the GNU General Public License as published by
15 ;; the Free Software Foundation; either version 3, or (at your option)
18 ;; GCC is distributed in the hope that it will be useful,
19 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
20 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 ;; GNU General Public License for more details.
23 ;; You should have received a copy of the GNU General Public License
24 ;; along with GCC; see the file COPYING3. If not see
25 ;; <http://www.gnu.org/licenses/>.
27 (define_enum "processor" [
72 (define_c_enum "unspec" [
73 ;; Unaligned accesses.
79 ;; Floating-point moves.
95 UNSPEC_POTENTIAL_CPRESTORE
100 UNSPEC_SET_GOT_VERSION
101 UNSPEC_UPDATE_GOT_VERSION
103 ;; Symbolic accesses.
108 UNSPEC_UNSHIFTED_HIGH
110 ;; MIPS16 constant pools.
112 UNSPEC_CONSTTABLE_INT
113 UNSPEC_CONSTTABLE_FLOAT
115 ;; Blockage and synchronisation.
122 ;; Cache manipulation.
124 UNSPEC_R10K_CACHE_BARRIER
126 ;; Interrupt handling.
134 ;; Used in a call expression in place of args_size. It's present for PIC
135 ;; indirect calls where it contains args_size and the function symbol.
138 ;; MIPS16 casesi jump table dispatch.
139 UNSPEC_CASESI_DISPATCH
143 [(TLS_GET_TP_REGNUM 3)
145 (PIC_FUNCTION_ADDR_REGNUM 25)
146 (RETURN_ADDR_REGNUM 31)
147 (CPRESTORE_SLOT_REGNUM 76)
148 (GOT_VERSION_REGNUM 79)
150 ;; PIC long branch sequences are never longer than 100 bytes.
151 (MAX_PIC_BRANCH_LENGTH 100)
155 (include "predicates.md")
156 (include "constraints.md")
158 ;; ....................
162 ;; ....................
164 (define_attr "got" "unset,xgot_high,load"
165 (const_string "unset"))
167 ;; For jal instructions, this attribute is DIRECT when the target address
168 ;; is symbolic and INDIRECT when it is a register.
169 (define_attr "jal" "unset,direct,indirect"
170 (const_string "unset"))
172 ;; This attribute is YES if the instruction is a jal macro (not a
173 ;; real jal instruction).
175 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
176 ;; an instruction to restore $gp. Direct jals are also macros for
177 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
179 (define_attr "jal_macro" "no,yes"
180 (cond [(eq_attr "jal" "direct")
181 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
182 ? JAL_MACRO_YES : JAL_MACRO_NO)")
183 (eq_attr "jal" "indirect")
184 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
185 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
186 (const_string "no")))
188 ;; Classification of moves, extensions and truncations. Most values
189 ;; are as for "type" (see below) but there are also the following
190 ;; move-specific values:
192 ;; constN move an N-constraint integer into a MIPS16 register
193 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
194 ;; to produce a sign-extended DEST, even if SRC is not
195 ;; properly sign-extended
196 ;; ext_ins EXT, DEXT, INS or DINS instruction
197 ;; andi a single ANDI instruction
198 ;; loadpool move a constant into a MIPS16 register by loading it
200 ;; shift_shift a shift left followed by a shift right
202 ;; This attribute is used to determine the instruction's length and
203 ;; scheduling type. For doubleword moves, the attribute always describes
204 ;; the split instructions; in some cases, it is more appropriate for the
205 ;; scheduling type to be "multi" instead.
206 (define_attr "move_type"
207 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,move,fmove,
208 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
210 (const_string "unknown"))
212 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
213 (const_string "unknown"))
215 ;; Main data type used by the insn
216 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
217 (const_string "unknown"))
219 ;; True if the main data type is twice the size of a word.
220 (define_attr "dword_mode" "no,yes"
221 (cond [(and (eq_attr "mode" "DI,DF")
222 (not (match_test "TARGET_64BIT")))
225 (and (eq_attr "mode" "TI,TF")
226 (match_test "TARGET_64BIT"))
227 (const_string "yes")]
228 (const_string "no")))
230 ;; Attributes describing a sync loop. These loops have the form:
232 ;; if (RELEASE_BARRIER == YES) sync
234 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
235 ;; CMP = 0 [delay slot]
236 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
237 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
238 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
239 ;; $AT |= $TMP1 | $TMP3
240 ;; if (!commit (*MEM = $AT)) goto 1.
241 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
243 ;; if (ACQUIRE_BARRIER == YES) sync
246 ;; where "$" values are temporaries and where the other values are
247 ;; specified by the attributes below. Values are specified as operand
248 ;; numbers and insns are specified as enums. If no operand number is
249 ;; specified, the following values are used instead:
254 ;; - INCLUSIVE_MASK: -1
255 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
256 ;; - EXCLUSIVE_MASK: 0
258 ;; MEM and INSN1_OP2 are required.
260 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
261 ;; but the gen* programs don't yet support that.
262 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
263 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
264 (define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
265 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
266 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
267 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
268 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
269 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
270 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
271 (const_string "move"))
272 (define_attr "sync_insn2" "nop,and,xor,not"
273 (const_string "nop"))
274 ;; Memory model specifier.
275 ;; "0"-"9" values specify the operand that stores the memory model value.
276 ;; "10" specifies MEMMODEL_ACQ_REL,
277 ;; "11" specifies MEMMODEL_ACQUIRE.
278 (define_attr "sync_memmodel" "" (const_int 10))
280 ;; Accumulator operand for madd patterns.
281 (define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
283 ;; Classification of each insn.
284 ;; branch conditional branch
285 ;; jump unconditional jump
286 ;; call unconditional call
287 ;; load load instruction(s)
288 ;; fpload floating point load
289 ;; fpidxload floating point indexed load
290 ;; store store instruction(s)
291 ;; fpstore floating point store
292 ;; fpidxstore floating point indexed store
293 ;; prefetch memory prefetch (register + offset)
294 ;; prefetchx memory indexed prefetch (register + register)
295 ;; condmove conditional moves
296 ;; mtc transfer to coprocessor
297 ;; mfc transfer from coprocessor
298 ;; mthi transfer to a hi register
299 ;; mtlo transfer to a lo register
300 ;; mfhi transfer from a hi register
301 ;; mflo transfer from a lo register
302 ;; const load constant
303 ;; arith integer arithmetic instructions
304 ;; logical integer logical instructions
305 ;; shift integer shift instructions
306 ;; slt set less than instructions
307 ;; signext sign extend instructions
308 ;; clz the clz and clo instructions
309 ;; pop the pop instruction
310 ;; trap trap if instructions
311 ;; imul integer multiply 2 operands
312 ;; imul3 integer multiply 3 operands
313 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
314 ;; imadd integer multiply-add
315 ;; idiv integer divide 2 operands
316 ;; idiv3 integer divide 3 operands
317 ;; move integer register move ({,D}ADD{,U} with rt = 0)
318 ;; fmove floating point register move
319 ;; fadd floating point add/subtract
320 ;; fmul floating point multiply
321 ;; fmadd floating point multiply-add
322 ;; fdiv floating point divide
323 ;; frdiv floating point reciprocal divide
324 ;; frdiv1 floating point reciprocal divide step 1
325 ;; frdiv2 floating point reciprocal divide step 2
326 ;; fabs floating point absolute value
327 ;; fneg floating point negation
328 ;; fcmp floating point compare
329 ;; fcvt floating point convert
330 ;; fsqrt floating point square root
331 ;; frsqrt floating point reciprocal square root
332 ;; frsqrt1 floating point reciprocal square root step1
333 ;; frsqrt2 floating point reciprocal square root step2
334 ;; dspmac DSP MAC instructions not saturating the accumulator
335 ;; dspmacsat DSP MAC instructions that saturate the accumulator
336 ;; accext DSP accumulator extract instructions
337 ;; accmod DSP accumulator modify instructions
338 ;; dspalu DSP ALU instructions not saturating the result
339 ;; dspalusat DSP ALU instructions that saturate the result
340 ;; multi multiword sequence (or user asm statements)
341 ;; atomic atomic memory update instruction
342 ;; syncloop memory atomic operation implemented as a sync loop
344 ;; ghost an instruction that produces no real code
346 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
347 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
348 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
349 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
350 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
351 multi,atomic,syncloop,nop,ghost"
352 (cond [(eq_attr "jal" "!unset") (const_string "call")
353 (eq_attr "got" "load") (const_string "load")
355 (eq_attr "alu_type" "add,sub") (const_string "arith")
357 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
359 ;; If a doubleword move uses these expensive instructions,
360 ;; it is usually better to schedule them in the same way
361 ;; as the singleword form, rather than as "multi".
362 (eq_attr "move_type" "load") (const_string "load")
363 (eq_attr "move_type" "fpload") (const_string "fpload")
364 (eq_attr "move_type" "store") (const_string "store")
365 (eq_attr "move_type" "fpstore") (const_string "fpstore")
366 (eq_attr "move_type" "mtc") (const_string "mtc")
367 (eq_attr "move_type" "mfc") (const_string "mfc")
368 (eq_attr "move_type" "mtlo") (const_string "mtlo")
369 (eq_attr "move_type" "mflo") (const_string "mflo")
371 ;; These types of move are always single insns.
372 (eq_attr "move_type" "fmove") (const_string "fmove")
373 (eq_attr "move_type" "loadpool") (const_string "load")
374 (eq_attr "move_type" "signext") (const_string "signext")
375 (eq_attr "move_type" "ext_ins") (const_string "arith")
376 (eq_attr "move_type" "arith") (const_string "arith")
377 (eq_attr "move_type" "logical") (const_string "logical")
378 (eq_attr "move_type" "sll0") (const_string "shift")
379 (eq_attr "move_type" "andi") (const_string "logical")
381 ;; These types of move are always split.
382 (eq_attr "move_type" "constN,shift_shift")
383 (const_string "multi")
385 ;; These types of move are split for doubleword modes only.
386 (and (eq_attr "move_type" "move,const")
387 (eq_attr "dword_mode" "yes"))
388 (const_string "multi")
389 (eq_attr "move_type" "move") (const_string "move")
390 (eq_attr "move_type" "const") (const_string "const")
391 (eq_attr "sync_mem" "!none") (const_string "syncloop")]
392 (const_string "unknown")))
394 ;; Mode for conversion types (fcvt)
395 ;; I2S integer to float single (SI/DI to SF)
396 ;; I2D integer to float double (SI/DI to DF)
397 ;; S2I float to integer (SF to SI/DI)
398 ;; D2I float to integer (DF to SI/DI)
399 ;; D2S double to float single
400 ;; S2D float single to double
402 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
403 (const_string "unknown"))
405 ;; Is this an extended instruction in mips16 mode?
406 (define_attr "extended_mips16" "no,yes"
407 (if_then_else (ior (eq_attr "move_type" "sll0")
408 (eq_attr "type" "branch")
409 (eq_attr "jal" "direct"))
411 (const_string "no")))
413 ;; Length of instruction in bytes.
414 (define_attr "length" ""
415 (cond [;; Direct branch instructions have a range of [-0x20000,0x1fffc],
416 ;; relative to the address of the delay slot. If a branch is
417 ;; outside this range, we have a choice of two sequences.
418 ;; For PIC, an out-of-range branch like:
423 ;; becomes the equivalent of:
432 ;; The non-PIC case is similar except that we use a direct
433 ;; jump instead of an la/jr pair. Since the target of this
434 ;; jump is an absolute 28-bit bit address (the other bits
435 ;; coming from the address of the delay slot) this form cannot
436 ;; cross a 256MB boundary. We could provide the option of
437 ;; using la/jr in this case too, but we do not do so at
440 ;; The value we specify here does not account for the delay slot
441 ;; instruction, whose length is added separately. If the RTL
442 ;; pattern has no explicit delay slot, mips_adjust_insn_length
443 ;; will add the length of the implicit nop. The range of
444 ;; [-0x20000, 0x1fffc] from the address of the delay slot
445 ;; therefore translates to a range of:
447 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
448 ;; == [-0x1fffc, 0x1fff8]
450 ;; from the shorten_branches reference address.
451 (and (eq_attr "type" "branch")
452 (not (match_test "TARGET_MIPS16")))
453 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 131064))
454 (le (minus (pc) (match_dup 0)) (const_int 131068)))
457 ;; The non-PIC case: branch, first delay slot, and J.
458 (match_test "TARGET_ABSOLUTE_JUMPS")
461 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
462 ;; mips_adjust_insn_length substitutes the correct length.
464 ;; Note that we can't simply use (symbol_ref ...) here
465 ;; because genattrtab needs to know the maximum length
467 (const_int MAX_PIC_BRANCH_LENGTH))
469 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
470 ;; from the address of the following instruction, which leads
473 ;; [-(0x100 - sizeof (branch)), 0xfe]
476 ;; from the shorten_branches reference address. Extended branches
477 ;; likewise have a range of [-0x10000, 0xfffe] from the address
478 ;; of the following instruction, which leads to a range of:
480 ;; [-(0x10000 - sizeof (branch)), 0xfffe]
481 ;; == [-0xfffc, 0xfffe]
483 ;; from the reference address.
485 ;; When a branch is out of range, mips_reorg splits it into a form
486 ;; that uses in-range branches. There are four basic sequences:
488 ;; (1) Absolute addressing with a readable text segment
489 ;; (32-bit addresses):
492 ;; move $1,$2 2 bytes
493 ;; lw $2,label 2 bytes
495 ;; move $2,$1 2 bytes
496 ;; .align 2 0 or 2 bytes
498 ;; .word target 4 bytes
500 ;; (16 bytes in the worst case)
502 ;; (2) Absolute addressing with a readable text segment
503 ;; (64-bit addresses):
506 ;; move $1,$2 2 bytes
507 ;; ld $2,label 2 bytes
509 ;; move $2,$1 2 bytes
510 ;; .align 3 0 to 6 bytes
512 ;; .dword target 8 bytes
514 ;; (24 bytes in the worst case)
516 ;; (3) Absolute addressing without a readable text segment
517 ;; (which requires 32-bit addresses at present):
520 ;; move $1,$2 2 bytes
521 ;; lui $2,%hi(target) 4 bytes
524 ;; addiu $2,%lo(target) 4 bytes
526 ;; move $2,$1 2 bytes
530 ;; (4) PIC addressing (which requires 32-bit addresses at present):
533 ;; move $1,$2 2 bytes
534 ;; lw $2,cprestore 0, 2 or 4 bytes
535 ;; lw $2,%got(target)($2) 4 bytes
536 ;; addiu $2,%lo(target) 4 bytes
538 ;; move $2,$1 2 bytes
540 ;; (20 bytes in the worst case)
542 ;; Note that the conditions test adjusted lengths, whereas the
543 ;; result is an unadjusted length, and is thus twice the true value.
544 (and (eq_attr "type" "branch")
545 (match_test "TARGET_MIPS16"))
546 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
547 (le (minus (pc) (match_dup 0)) (const_int 254)))
549 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
550 (le (minus (pc) (match_dup 0)) (const_int 65532)))
552 (and (match_test "TARGET_ABICALLS")
553 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
555 (match_test "Pmode == SImode")
559 (and (eq_attr "extended_mips16" "yes")
560 (match_test "TARGET_MIPS16"))
563 ;; "Ghost" instructions occupy no space.
564 (eq_attr "type" "ghost")
567 (eq_attr "got" "load")
568 (if_then_else (match_test "TARGET_MIPS16")
571 (eq_attr "got" "xgot_high")
574 ;; In general, constant-pool loads are extended instructions.
575 (eq_attr "move_type" "loadpool")
578 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
579 ;; They are extended instructions on MIPS16 targets.
580 (eq_attr "move_type" "shift_shift")
581 (if_then_else (match_test "TARGET_MIPS16")
585 ;; Check for doubleword moves that are decomposed into two
587 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
588 (eq_attr "dword_mode" "yes"))
591 ;; Doubleword CONST{,N} moves are split into two word
593 (and (eq_attr "move_type" "const,constN")
594 (eq_attr "dword_mode" "yes"))
595 (symbol_ref "mips_split_const_insns (operands[1]) * 4")
597 ;; Otherwise, constants, loads and stores are handled by external
599 (eq_attr "move_type" "const,constN")
600 (symbol_ref "mips_const_insns (operands[1]) * 4")
601 (eq_attr "move_type" "load,fpload")
602 (symbol_ref "mips_load_store_insns (operands[1], insn) * 4")
603 (eq_attr "move_type" "store,fpstore")
604 (cond [(not (match_test "TARGET_FIX_24K"))
605 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4")]
606 (symbol_ref "mips_load_store_insns (operands[0], insn) * 4 + 4"))
608 ;; In the worst case, a call macro will take 8 instructions:
610 ;; lui $25,%call_hi(FOO)
612 ;; lw $25,%call_lo(FOO)($25)
618 (eq_attr "jal_macro" "yes")
621 ;; Various VR4120 errata require a nop to be inserted after a macc
622 ;; instruction. The assembler does this for us, so account for
623 ;; the worst-case length here.
624 (and (eq_attr "type" "imadd")
625 (match_test "TARGET_FIX_VR4120"))
628 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
629 ;; the result of the second one is missed. The assembler should work
630 ;; around this by inserting a nop after the first dmult.
631 (and (eq_attr "type" "imul,imul3")
632 (and (eq_attr "mode" "DI")
633 (match_test "TARGET_FIX_VR4120")))
636 (eq_attr "type" "idiv,idiv3")
637 (symbol_ref "mips_idiv_insns () * 4")
639 (not (eq_attr "sync_mem" "none"))
640 (symbol_ref "mips_sync_loop_insns (insn, operands) * 4")
643 ;; Attribute describing the processor.
644 (define_enum_attr "cpu" "processor"
645 (const (symbol_ref "mips_tune")))
647 ;; The type of hardware hazard associated with this instruction.
648 ;; DELAY means that the next instruction cannot read the result
649 ;; of this one. HILO means that the next two instructions cannot
650 ;; write to HI or LO.
651 (define_attr "hazard" "none,delay,hilo"
652 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
653 (match_test "ISA_HAS_LOAD_DELAY"))
654 (const_string "delay")
656 (and (eq_attr "type" "mfc,mtc")
657 (match_test "ISA_HAS_XFER_DELAY"))
658 (const_string "delay")
660 (and (eq_attr "type" "fcmp")
661 (match_test "ISA_HAS_FCMP_DELAY"))
662 (const_string "delay")
664 ;; The r4000 multiplication patterns include an mflo instruction.
665 (and (eq_attr "type" "imul")
666 (match_test "TARGET_FIX_R4000"))
667 (const_string "hilo")
669 (and (eq_attr "type" "mfhi,mflo")
670 (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
671 (const_string "hilo")]
672 (const_string "none")))
674 ;; Is it a single instruction?
675 (define_attr "single_insn" "no,yes"
676 (symbol_ref "(get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)
677 ? SINGLE_INSN_YES : SINGLE_INSN_NO)"))
679 ;; Can the instruction be put into a delay slot?
680 (define_attr "can_delay" "no,yes"
681 (if_then_else (and (eq_attr "type" "!branch,call,jump")
682 (and (eq_attr "hazard" "none")
683 (eq_attr "single_insn" "yes")))
685 (const_string "no")))
687 ;; Attribute defining whether or not we can use the branch-likely
689 (define_attr "branch_likely" "no,yes"
690 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
692 (const_string "no")))
694 ;; True if an instruction might assign to hi or lo when reloaded.
695 ;; This is used by the TUNE_MACC_CHAINS code.
696 (define_attr "may_clobber_hilo" "no,yes"
697 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
699 (const_string "no")))
701 ;; Describe a user's asm statement.
702 (define_asm_attributes
703 [(set_attr "type" "multi")
704 (set_attr "can_delay" "no")])
706 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
707 ;; from the same template.
708 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
710 ;; A copy of GPR that can be used when a pattern has two independent
712 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
714 ;; This mode iterator allows :HILO to be used as the mode of the
715 ;; concatenated HI and LO registers.
716 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
718 ;; This mode iterator allows :P to be used for patterns that operate on
719 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
720 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
722 ;; This mode iterator allows :MOVECC to be used anywhere that a
723 ;; conditional-move-type condition is needed.
724 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
725 (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
727 ;; 32-bit integer moves for which we provide move patterns.
728 (define_mode_iterator IMOVE32
737 (V4UQQ "TARGET_DSP")])
739 ;; 64-bit modes for which we provide move patterns.
740 (define_mode_iterator MOVE64
742 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
743 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
744 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
745 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
747 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
748 (define_mode_iterator MOVE128 [TI TF])
750 ;; This mode iterator allows the QI and HI extension patterns to be
751 ;; defined from the same template.
752 (define_mode_iterator SHORT [QI HI])
754 ;; Likewise the 64-bit truncate-and-shift patterns.
755 (define_mode_iterator SUBDI [QI HI SI])
757 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
758 ;; floating-point mode is allowed.
759 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
760 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
761 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
763 ;; Like ANYF, but only applies to scalar modes.
764 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
765 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
767 ;; A floating-point mode for which moves involving FPRs may need to be split.
768 (define_mode_iterator SPLITF
769 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
770 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
771 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
772 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
773 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
774 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
775 (TF "TARGET_64BIT && TARGET_FLOAT64")])
777 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
778 ;; 32-bit version and "dsubu" in the 64-bit version.
779 (define_mode_attr d [(SI "") (DI "d")
780 (QQ "") (HQ "") (SQ "") (DQ "d")
781 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
782 (HA "") (SA "") (DA "d")
783 (UHA "") (USA "") (UDA "d")])
785 ;; Same as d but upper-case.
786 (define_mode_attr D [(SI "") (DI "D")
787 (QQ "") (HQ "") (SQ "") (DQ "D")
788 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
789 (HA "") (SA "") (DA "D")
790 (UHA "") (USA "") (UDA "D")])
792 ;; This attribute gives the length suffix for a load or store instruction.
793 ;; The same suffixes work for zero and sign extensions.
794 (define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
795 (define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
797 ;; This attributes gives the mode mask of a SHORT.
798 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
800 ;; Mode attributes for GPR loads.
801 (define_mode_attr load [(SI "lw") (DI "ld")])
802 ;; Instruction names for stores.
803 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
805 ;; Similarly for MIPS IV indexed FPR loads and stores.
806 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
807 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
809 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
810 ;; are different. Some forms of unextended addiu have an 8-bit immediate
811 ;; field but the equivalent daddiu has only a 5-bit field.
812 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
814 ;; This attribute gives the best constraint to use for registers of
816 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
818 ;; This attribute gives the format suffix for floating-point operations.
819 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
821 ;; This attribute gives the upper-case mode name for one unit of a
822 ;; floating-point mode.
823 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
825 ;; This attribute gives the integer mode that has the same size as a
827 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
828 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
829 (HA "HI") (SA "SI") (DA "DI")
830 (UHA "HI") (USA "SI") (UDA "DI")
831 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
832 (V2HQ "SI") (V2HA "SI")])
834 ;; This attribute gives the integer mode that has half the size of
835 ;; the controlling mode.
836 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
837 (V2SI "SI") (V4HI "SI") (V8QI "SI")
840 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
842 ;; In certain cases, div.s and div.ps may have a rounding error
843 ;; and/or wrong inexact flag.
845 ;; Therefore, we only allow div.s if not working around SB-1 rev2
846 ;; errata or if a slight loss of precision is OK.
847 (define_mode_attr divide_condition
848 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
849 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
851 ;; This attribute gives the conditions under which SQRT.fmt instructions
853 (define_mode_attr sqrt_condition
854 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
856 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
857 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
858 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
859 ;; so for safety's sake, we apply this restriction to all targets.
860 (define_mode_attr recip_condition
862 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
863 (V2SF "TARGET_SB1")])
865 ;; This code iterator allows signed and unsigned widening multiplications
866 ;; to use the same template.
867 (define_code_iterator any_extend [sign_extend zero_extend])
869 ;; This code iterator allows the two right shift instructions to be
870 ;; generated from the same template.
871 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
873 ;; This code iterator allows the three shift instructions to be generated
874 ;; from the same template.
875 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
877 ;; This code iterator allows unsigned and signed division to be generated
878 ;; from the same template.
879 (define_code_iterator any_div [div udiv])
881 ;; This code iterator allows unsigned and signed modulus to be generated
882 ;; from the same template.
883 (define_code_iterator any_mod [mod umod])
885 ;; This code iterator allows all native floating-point comparisons to be
886 ;; generated from the same template.
887 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
889 ;; This code iterator is used for comparisons that can be implemented
890 ;; by swapping the operands.
891 (define_code_iterator swapped_fcond [ge gt unge ungt])
893 ;; Equality operators.
894 (define_code_iterator equality_op [eq ne])
896 ;; These code iterators allow the signed and unsigned scc operations to use
897 ;; the same template.
898 (define_code_iterator any_gt [gt gtu])
899 (define_code_iterator any_ge [ge geu])
900 (define_code_iterator any_lt [lt ltu])
901 (define_code_iterator any_le [le leu])
903 (define_code_iterator any_return [return simple_return])
905 ;; <u> expands to an empty string when doing a signed operation and
906 ;; "u" when doing an unsigned operation.
907 (define_code_attr u [(sign_extend "") (zero_extend "u")
915 ;; <U> is like <u> except uppercase.
916 (define_code_attr U [(sign_extend "") (zero_extend "U")])
918 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
919 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
921 ;; <optab> expands to the name of the optab for a particular code.
922 (define_code_attr optab [(ashift "ashl")
931 (simple_return "simple_return")])
933 ;; <insn> expands to the name of the insn that implements a particular code.
934 (define_code_attr insn [(ashift "sll")
943 ;; <immediate_insn> expands to the name of the insn that implements
944 ;; a particular code to operate on immediate values.
945 (define_code_attr immediate_insn [(ior "ori")
949 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
950 (define_code_attr fcond [(unordered "un")
958 ;; Similar, but for swapped conditions.
959 (define_code_attr swapped_fcond [(ge "le")
964 ;; The value of the bit when the branch is taken for branch_bit patterns.
965 ;; Comparison is always against zero so this depends on the operator.
966 (define_code_attr bbv [(eq "0") (ne "1")])
968 ;; This is the inverse value of bbv.
969 (define_code_attr bbinv [(eq "1") (ne "0")])
971 ;; .........................
973 ;; Branch, call and jump delay slots
975 ;; .........................
977 (define_delay (and (eq_attr "type" "branch")
978 (not (match_test "TARGET_MIPS16"))
979 (eq_attr "branch_likely" "yes"))
980 [(eq_attr "can_delay" "yes")
982 (eq_attr "can_delay" "yes")])
984 ;; Branches that don't have likely variants do not annul on false.
985 (define_delay (and (eq_attr "type" "branch")
986 (not (match_test "TARGET_MIPS16"))
987 (eq_attr "branch_likely" "no"))
988 [(eq_attr "can_delay" "yes")
992 (define_delay (eq_attr "type" "jump")
993 [(eq_attr "can_delay" "yes")
997 (define_delay (and (eq_attr "type" "call")
998 (eq_attr "jal_macro" "no"))
999 [(eq_attr "can_delay" "yes")
1003 ;; Pipeline descriptions.
1005 ;; generic.md provides a fallback for processors without a specific
1006 ;; pipeline description. It is derived from the old define_function_unit
1007 ;; version and uses the "alu" and "imuldiv" units declared below.
1009 ;; Some of the processor-specific files are also derived from old
1010 ;; define_function_unit descriptions and simply override the parts of
1011 ;; generic.md that don't apply. The other processor-specific files
1012 ;; are self-contained.
1013 (define_automaton "alu,imuldiv")
1015 (define_cpu_unit "alu" "alu")
1016 (define_cpu_unit "imuldiv" "imuldiv")
1018 ;; Ghost instructions produce no real code and introduce no hazards.
1019 ;; They exist purely to express an effect on dataflow.
1020 (define_insn_reservation "ghost" 0
1021 (eq_attr "type" "ghost")
1041 (include "10000.md")
1042 (include "loongson2ef.md")
1043 (include "loongson3a.md")
1044 (include "octeon.md")
1046 (include "sr71k.md")
1049 (include "generic.md")
1052 ;; ....................
1054 ;; CONDITIONAL TRAPS
1056 ;; ....................
1060 [(trap_if (const_int 1) (const_int 0))]
1063 if (ISA_HAS_COND_TRAP)
1064 return "teq\t$0,$0";
1065 else if (TARGET_MIPS16)
1070 [(set_attr "type" "trap")])
1072 (define_expand "ctrap<mode>4"
1073 [(trap_if (match_operator 0 "comparison_operator"
1074 [(match_operand:GPR 1 "reg_or_0_operand")
1075 (match_operand:GPR 2 "arith_operand")])
1076 (match_operand 3 "const_0_operand"))]
1079 mips_expand_conditional_trap (operands[0]);
1083 (define_insn "*conditional_trap<mode>"
1084 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1085 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1086 (match_operand:GPR 2 "arith_operand" "dI")])
1090 [(set_attr "type" "trap")])
1093 ;; ....................
1097 ;; ....................
1100 (define_insn "add<mode>3"
1101 [(set (match_operand:ANYF 0 "register_operand" "=f")
1102 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1103 (match_operand:ANYF 2 "register_operand" "f")))]
1105 "add.<fmt>\t%0,%1,%2"
1106 [(set_attr "type" "fadd")
1107 (set_attr "mode" "<UNITMODE>")])
1109 (define_expand "add<mode>3"
1110 [(set (match_operand:GPR 0 "register_operand")
1111 (plus:GPR (match_operand:GPR 1 "register_operand")
1112 (match_operand:GPR 2 "arith_operand")))]
1115 (define_insn "*add<mode>3"
1116 [(set (match_operand:GPR 0 "register_operand" "=d,d")
1117 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
1118 (match_operand:GPR 2 "arith_operand" "d,Q")))]
1123 [(set_attr "alu_type" "add")
1124 (set_attr "mode" "<MODE>")])
1126 (define_insn "*add<mode>3_mips16"
1127 [(set (match_operand:GPR 0 "register_operand" "=ks,d,d,d,d")
1128 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,0,d,d")
1129 (match_operand:GPR 2 "arith_operand" "Q,Q,Q,O,d")))]
1137 [(set_attr "alu_type" "add")
1138 (set_attr "mode" "<MODE>")
1139 (set_attr_alternative "length"
1140 [(if_then_else (match_operand 2 "m16_simm8_8")
1143 (if_then_else (match_operand 2 "m16_uimm<si8_di5>_4")
1146 (if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
1149 (if_then_else (match_operand 2 "m16_simm4_1")
1154 ;; On the mips16, we can sometimes split an add of a constant which is
1155 ;; a 4 byte instruction into two adds which are both 2 byte
1156 ;; instructions. There are two cases: one where we are adding a
1157 ;; constant plus a register to another register, and one where we are
1158 ;; simply adding a constant to a register.
1161 [(set (match_operand:SI 0 "d_operand")
1162 (plus:SI (match_dup 0)
1163 (match_operand:SI 1 "const_int_operand")))]
1164 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1165 && ((INTVAL (operands[1]) > 0x7f
1166 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1167 || (INTVAL (operands[1]) < - 0x80
1168 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1169 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1170 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1172 HOST_WIDE_INT val = INTVAL (operands[1]);
1176 operands[1] = GEN_INT (0x7f);
1177 operands[2] = GEN_INT (val - 0x7f);
1181 operands[1] = GEN_INT (- 0x80);
1182 operands[2] = GEN_INT (val + 0x80);
1187 [(set (match_operand:SI 0 "d_operand")
1188 (plus:SI (match_operand:SI 1 "d_operand")
1189 (match_operand:SI 2 "const_int_operand")))]
1190 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1191 && REGNO (operands[0]) != REGNO (operands[1])
1192 && ((INTVAL (operands[2]) > 0x7
1193 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1194 || (INTVAL (operands[2]) < - 0x8
1195 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1196 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1197 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1199 HOST_WIDE_INT val = INTVAL (operands[2]);
1203 operands[2] = GEN_INT (0x7);
1204 operands[3] = GEN_INT (val - 0x7);
1208 operands[2] = GEN_INT (- 0x8);
1209 operands[3] = GEN_INT (val + 0x8);
1214 [(set (match_operand:DI 0 "d_operand")
1215 (plus:DI (match_dup 0)
1216 (match_operand:DI 1 "const_int_operand")))]
1217 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1218 && ((INTVAL (operands[1]) > 0xf
1219 && INTVAL (operands[1]) <= 0xf + 0xf)
1220 || (INTVAL (operands[1]) < - 0x10
1221 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1222 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1223 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1225 HOST_WIDE_INT val = INTVAL (operands[1]);
1229 operands[1] = GEN_INT (0xf);
1230 operands[2] = GEN_INT (val - 0xf);
1234 operands[1] = GEN_INT (- 0x10);
1235 operands[2] = GEN_INT (val + 0x10);
1240 [(set (match_operand:DI 0 "d_operand")
1241 (plus:DI (match_operand:DI 1 "d_operand")
1242 (match_operand:DI 2 "const_int_operand")))]
1243 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1244 && REGNO (operands[0]) != REGNO (operands[1])
1245 && ((INTVAL (operands[2]) > 0x7
1246 && INTVAL (operands[2]) <= 0x7 + 0xf)
1247 || (INTVAL (operands[2]) < - 0x8
1248 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1249 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1250 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1252 HOST_WIDE_INT val = INTVAL (operands[2]);
1256 operands[2] = GEN_INT (0x7);
1257 operands[3] = GEN_INT (val - 0x7);
1261 operands[2] = GEN_INT (- 0x8);
1262 operands[3] = GEN_INT (val + 0x8);
1266 (define_insn "*addsi3_extended"
1267 [(set (match_operand:DI 0 "register_operand" "=d,d")
1269 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1270 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1271 "TARGET_64BIT && !TARGET_MIPS16"
1275 [(set_attr "alu_type" "add")
1276 (set_attr "mode" "SI")])
1278 ;; Split this insn so that the addiu splitters can have a crack at it.
1279 ;; Use a conservative length estimate until the split.
1280 (define_insn_and_split "*addsi3_extended_mips16"
1281 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1283 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1284 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1285 "TARGET_64BIT && TARGET_MIPS16"
1287 "&& reload_completed"
1288 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1289 { operands[3] = gen_lowpart (SImode, operands[0]); }
1290 [(set_attr "alu_type" "add")
1291 (set_attr "mode" "SI")
1292 (set_attr "extended_mips16" "yes")])
1294 ;; Combiner patterns for unsigned byte-add.
1296 (define_insn "*baddu_si"
1297 [(set (match_operand:SI 0 "register_operand" "=d")
1299 (plus:QI (match_operand:QI 1 "register_operand" "d")
1300 (match_operand:QI 2 "register_operand" "d"))))]
1303 [(set_attr "alu_type" "add")])
1305 (define_insn "*baddu_di<mode>"
1306 [(set (match_operand:GPR 0 "register_operand" "=d")
1309 (plus:DI (match_operand:DI 1 "register_operand" "d")
1310 (match_operand:DI 2 "register_operand" "d")))))]
1311 "ISA_HAS_BADDU && TARGET_64BIT"
1313 [(set_attr "alu_type" "add")])
1316 ;; ....................
1320 ;; ....................
1323 (define_insn "sub<mode>3"
1324 [(set (match_operand:ANYF 0 "register_operand" "=f")
1325 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1326 (match_operand:ANYF 2 "register_operand" "f")))]
1328 "sub.<fmt>\t%0,%1,%2"
1329 [(set_attr "type" "fadd")
1330 (set_attr "mode" "<UNITMODE>")])
1332 (define_insn "sub<mode>3"
1333 [(set (match_operand:GPR 0 "register_operand" "=d")
1334 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
1335 (match_operand:GPR 2 "register_operand" "d")))]
1338 [(set_attr "alu_type" "sub")
1339 (set_attr "mode" "<MODE>")])
1341 (define_insn "*subsi3_extended"
1342 [(set (match_operand:DI 0 "register_operand" "=d")
1344 (minus:SI (match_operand:SI 1 "register_operand" "d")
1345 (match_operand:SI 2 "register_operand" "d"))))]
1348 [(set_attr "alu_type" "sub")
1349 (set_attr "mode" "DI")])
1352 ;; ....................
1356 ;; ....................
1359 (define_expand "mul<mode>3"
1360 [(set (match_operand:SCALARF 0 "register_operand")
1361 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1362 (match_operand:SCALARF 2 "register_operand")))]
1366 (define_insn "*mul<mode>3"
1367 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1368 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1369 (match_operand:SCALARF 2 "register_operand" "f")))]
1370 "!TARGET_4300_MUL_FIX"
1371 "mul.<fmt>\t%0,%1,%2"
1372 [(set_attr "type" "fmul")
1373 (set_attr "mode" "<MODE>")])
1375 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1376 ;; operands may corrupt immediately following multiplies. This is a
1377 ;; simple fix to insert NOPs.
1379 (define_insn "*mul<mode>3_r4300"
1380 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1381 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1382 (match_operand:SCALARF 2 "register_operand" "f")))]
1383 "TARGET_4300_MUL_FIX"
1384 "mul.<fmt>\t%0,%1,%2\;nop"
1385 [(set_attr "type" "fmul")
1386 (set_attr "mode" "<MODE>")
1387 (set_attr "length" "8")])
1389 (define_insn "mulv2sf3"
1390 [(set (match_operand:V2SF 0 "register_operand" "=f")
1391 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1392 (match_operand:V2SF 2 "register_operand" "f")))]
1393 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1395 [(set_attr "type" "fmul")
1396 (set_attr "mode" "SF")])
1398 ;; The original R4000 has a cpu bug. If a double-word or a variable
1399 ;; shift executes while an integer multiplication is in progress, the
1400 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1401 ;; with the mult on the R4000.
1403 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1404 ;; (also valid for MIPS R4000MC processors):
1406 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1407 ;; this errata description.
1408 ;; The following code sequence causes the R4000 to incorrectly
1409 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1410 ;; instruction. If the dsra32 instruction is executed during an
1411 ;; integer multiply, the dsra32 will only shift by the amount in
1412 ;; specified in the instruction rather than the amount plus 32
1414 ;; instruction 1: mult rs,rt integer multiply
1415 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1416 ;; right arithmetic + 32
1417 ;; Workaround: A dsra32 instruction placed after an integer
1418 ;; multiply should not be one of the 11 instructions after the
1419 ;; multiply instruction."
1423 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1424 ;; the following description.
1425 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1426 ;; 64-bit versions) may produce incorrect results under the
1427 ;; following conditions:
1428 ;; 1) An integer multiply is currently executing
1429 ;; 2) These types of shift instructions are executed immediately
1430 ;; following an integer divide instruction.
1432 ;; 1) Make sure no integer multiply is running wihen these
1433 ;; instruction are executed. If this cannot be predicted at
1434 ;; compile time, then insert a "mfhi" to R0 instruction
1435 ;; immediately after the integer multiply instruction. This
1436 ;; will cause the integer multiply to complete before the shift
1438 ;; 2) Separate integer divide and these two classes of shift
1439 ;; instructions by another instruction or a noop."
1441 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1444 (define_expand "mul<mode>3"
1445 [(set (match_operand:GPR 0 "register_operand")
1446 (mult:GPR (match_operand:GPR 1 "register_operand")
1447 (match_operand:GPR 2 "register_operand")))]
1452 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
1453 emit_insn (gen_mul<mode>3_mul3_loongson (operands[0], operands[1],
1455 else if (ISA_HAS_<D>MUL3)
1456 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1457 else if (TARGET_MIPS16)
1459 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
1460 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2]));
1461 emit_move_insn (operands[0], lo);
1463 else if (TARGET_FIX_R4000)
1464 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1467 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1471 (define_insn "mul<mode>3_mul3_loongson"
1472 [(set (match_operand:GPR 0 "register_operand" "=d")
1473 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1474 (match_operand:GPR 2 "register_operand" "d")))]
1475 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A"
1477 if (TARGET_LOONGSON_2EF)
1478 return "<d>multu.g\t%0,%1,%2";
1480 return "gs<d>multu\t%0,%1,%2";
1482 [(set_attr "type" "imul3nc")
1483 (set_attr "mode" "<MODE>")])
1485 (define_insn "mul<mode>3_mul3"
1486 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1487 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1488 (match_operand:GPR 2 "register_operand" "d,d")))
1489 (clobber (match_scratch:GPR 3 "=l,X"))]
1492 if (which_alternative == 1)
1493 return "<d>mult\t%1,%2";
1494 if (<MODE>mode == SImode && TARGET_MIPS3900)
1495 return "mult\t%0,%1,%2";
1496 return "<d>mul\t%0,%1,%2";
1498 [(set_attr "type" "imul3,imul")
1499 (set_attr "mode" "<MODE>")])
1501 ;; If a register gets allocated to LO, and we spill to memory, the reload
1502 ;; will include a move from LO to a GPR. Merge it into the multiplication
1503 ;; if it can set the GPR directly.
1506 ;; Operand 1: GPR (1st multiplication operand)
1507 ;; Operand 2: GPR (2nd multiplication operand)
1508 ;; Operand 3: GPR (destination)
1511 [(set (match_operand:SI 0 "lo_operand")
1512 (mult:SI (match_operand:SI 1 "d_operand")
1513 (match_operand:SI 2 "d_operand")))
1514 (clobber (scratch:SI))])
1515 (set (match_operand:SI 3 "d_operand")
1517 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1520 (mult:SI (match_dup 1)
1522 (clobber (match_dup 0))])])
1524 (define_insn "mul<mode>3_internal"
1525 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
1526 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1527 (match_operand:GPR 2 "register_operand" "d")))]
1530 [(set_attr "type" "imul")
1531 (set_attr "mode" "<MODE>")])
1533 (define_insn "mul<mode>3_r4000"
1534 [(set (match_operand:GPR 0 "register_operand" "=d")
1535 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1536 (match_operand:GPR 2 "register_operand" "d")))
1537 (clobber (match_scratch:GPR 3 "=l"))]
1539 "<d>mult\t%1,%2\;mflo\t%0"
1540 [(set_attr "type" "imul")
1541 (set_attr "mode" "<MODE>")
1542 (set_attr "length" "8")])
1544 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1545 ;; of "mult; mflo". They have the same latency, but the first form gives
1546 ;; us an extra cycle to compute the operands.
1549 ;; Operand 1: GPR (1st multiplication operand)
1550 ;; Operand 2: GPR (2nd multiplication operand)
1551 ;; Operand 3: GPR (destination)
1553 [(set (match_operand:SI 0 "lo_operand")
1554 (mult:SI (match_operand:SI 1 "d_operand")
1555 (match_operand:SI 2 "d_operand")))
1556 (set (match_operand:SI 3 "d_operand")
1558 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1563 (plus:SI (mult:SI (match_dup 1)
1567 (plus:SI (mult:SI (match_dup 1)
1571 ;; Multiply-accumulate patterns
1573 ;; This pattern is first matched by combine, which tries to use the
1574 ;; pattern wherever it can. We don't know until later whether it
1575 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1576 ;; so we need to keep both options open.
1578 ;; The second alternative has a "?" marker because it is generally
1579 ;; one instruction more costly than the first alternative. This "?"
1580 ;; marker is enough to convey the relative costs to the register
1583 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1584 ;; reloads of the other operands, even though operands 4 and 5 need no
1585 ;; copy instructions. Reload therefore thinks that the second alternative
1586 ;; is two reloads more costly than the first. We add "*?*?" to the first
1587 ;; alternative as a counterweight.
1588 (define_insn "*mul_acc_si"
1589 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1590 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1591 (match_operand:SI 2 "register_operand" "d,d"))
1592 (match_operand:SI 3 "register_operand" "0,d")))
1593 (clobber (match_scratch:SI 4 "=X,l"))
1594 (clobber (match_scratch:SI 5 "=X,&d"))]
1595 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1599 [(set_attr "type" "imadd")
1600 (set_attr "accum_in" "3")
1601 (set_attr "mode" "SI")
1602 (set_attr "length" "4,8")])
1604 ;; The same idea applies here. The middle alternative needs one less
1605 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1606 (define_insn "*mul_acc_si_r3900"
1607 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1608 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1609 (match_operand:SI 2 "register_operand" "d,d,d"))
1610 (match_operand:SI 3 "register_operand" "0,l,d")))
1611 (clobber (match_scratch:SI 4 "=X,3,l"))
1612 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1613 "TARGET_MIPS3900 && !TARGET_MIPS16"
1618 [(set_attr "type" "imadd")
1619 (set_attr "accum_in" "3")
1620 (set_attr "mode" "SI")
1621 (set_attr "length" "4,4,8")])
1623 ;; Split *mul_acc_si if both the source and destination accumulator
1626 [(set (match_operand:SI 0 "d_operand")
1627 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1628 (match_operand:SI 2 "d_operand"))
1629 (match_operand:SI 3 "d_operand")))
1630 (clobber (match_operand:SI 4 "lo_operand"))
1631 (clobber (match_operand:SI 5 "d_operand"))]
1633 [(parallel [(set (match_dup 5)
1634 (mult:SI (match_dup 1) (match_dup 2)))
1635 (clobber (match_dup 4))])
1636 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1639 (define_insn "*macc"
1640 [(set (match_operand:SI 0 "register_operand" "=l,d")
1641 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1642 (match_operand:SI 2 "register_operand" "d,d"))
1643 (match_operand:SI 3 "register_operand" "0,l")))
1644 (clobber (match_scratch:SI 4 "=X,3"))]
1647 if (which_alternative == 1)
1648 return "macc\t%0,%1,%2";
1649 else if (TARGET_MIPS5500)
1650 return "madd\t%1,%2";
1652 /* The VR4130 assumes that there is a two-cycle latency between a macc
1653 that "writes" to $0 and an instruction that reads from it. We avoid
1654 this by assigning to $1 instead. */
1655 return "%[macc\t%@,%1,%2%]";
1657 [(set_attr "type" "imadd")
1658 (set_attr "accum_in" "3")
1659 (set_attr "mode" "SI")])
1661 (define_insn "*msac"
1662 [(set (match_operand:SI 0 "register_operand" "=l,d")
1663 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1664 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1665 (match_operand:SI 3 "register_operand" "d,d"))))
1666 (clobber (match_scratch:SI 4 "=X,1"))]
1669 if (which_alternative == 1)
1670 return "msac\t%0,%2,%3";
1671 else if (TARGET_MIPS5500)
1672 return "msub\t%2,%3";
1674 return "msac\t$0,%2,%3";
1676 [(set_attr "type" "imadd")
1677 (set_attr "accum_in" "1")
1678 (set_attr "mode" "SI")])
1680 ;; An msac-like instruction implemented using negation and a macc.
1681 (define_insn_and_split "*msac_using_macc"
1682 [(set (match_operand:SI 0 "register_operand" "=l,d")
1683 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1684 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1685 (match_operand:SI 3 "register_operand" "d,d"))))
1686 (clobber (match_scratch:SI 4 "=X,1"))
1687 (clobber (match_scratch:SI 5 "=d,d"))]
1688 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1690 "&& reload_completed"
1692 (neg:SI (match_dup 3)))
1695 (plus:SI (mult:SI (match_dup 2)
1698 (clobber (match_dup 4))])]
1700 [(set_attr "type" "imadd")
1701 (set_attr "accum_in" "1")
1702 (set_attr "length" "8")])
1704 ;; Patterns generated by the define_peephole2 below.
1706 (define_insn "*macc2"
1707 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1708 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1709 (match_operand:SI 2 "register_operand" "d"))
1711 (set (match_operand:SI 3 "register_operand" "=d")
1712 (plus:SI (mult:SI (match_dup 1)
1715 "ISA_HAS_MACC && reload_completed"
1717 [(set_attr "type" "imadd")
1718 (set_attr "accum_in" "0")
1719 (set_attr "mode" "SI")])
1721 (define_insn "*msac2"
1722 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1723 (minus:SI (match_dup 0)
1724 (mult:SI (match_operand:SI 1 "register_operand" "d")
1725 (match_operand:SI 2 "register_operand" "d"))))
1726 (set (match_operand:SI 3 "register_operand" "=d")
1727 (minus:SI (match_dup 0)
1728 (mult:SI (match_dup 1)
1730 "ISA_HAS_MSAC && reload_completed"
1732 [(set_attr "type" "imadd")
1733 (set_attr "accum_in" "0")
1734 (set_attr "mode" "SI")])
1736 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1740 ;; Operand 1: macc/msac
1741 ;; Operand 2: GPR (destination)
1744 [(set (match_operand:SI 0 "lo_operand")
1745 (match_operand:SI 1 "macc_msac_operand"))
1746 (clobber (scratch:SI))])
1747 (set (match_operand:SI 2 "d_operand")
1750 [(parallel [(set (match_dup 0)
1755 ;; When we have a three-address multiplication instruction, it should
1756 ;; be faster to do a separate multiply and add, rather than moving
1757 ;; something into LO in order to use a macc instruction.
1759 ;; This peephole needs a scratch register to cater for the case when one
1760 ;; of the multiplication operands is the same as the destination.
1762 ;; Operand 0: GPR (scratch)
1764 ;; Operand 2: GPR (addend)
1765 ;; Operand 3: GPR (destination)
1766 ;; Operand 4: macc/msac
1767 ;; Operand 5: new multiplication
1768 ;; Operand 6: new addition/subtraction
1770 [(match_scratch:SI 0 "d")
1771 (set (match_operand:SI 1 "lo_operand")
1772 (match_operand:SI 2 "d_operand"))
1775 [(set (match_operand:SI 3 "d_operand")
1776 (match_operand:SI 4 "macc_msac_operand"))
1777 (clobber (match_dup 1))])]
1778 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1779 [(parallel [(set (match_dup 0)
1781 (clobber (match_dup 1))])
1785 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1786 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1787 operands[2], operands[0]);
1790 ;; Same as above, except LO is the initial target of the macc.
1792 ;; Operand 0: GPR (scratch)
1794 ;; Operand 2: GPR (addend)
1795 ;; Operand 3: macc/msac
1796 ;; Operand 4: GPR (destination)
1797 ;; Operand 5: new multiplication
1798 ;; Operand 6: new addition/subtraction
1800 [(match_scratch:SI 0 "d")
1801 (set (match_operand:SI 1 "lo_operand")
1802 (match_operand:SI 2 "d_operand"))
1806 (match_operand:SI 3 "macc_msac_operand"))
1807 (clobber (scratch:SI))])
1809 (set (match_operand:SI 4 "d_operand")
1811 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1812 [(parallel [(set (match_dup 0)
1814 (clobber (match_dup 1))])
1818 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1819 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1820 operands[2], operands[0]);
1823 ;; See the comment above *mul_add_si for details.
1824 (define_insn "*mul_sub_si"
1825 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1826 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1827 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1828 (match_operand:SI 3 "register_operand" "d,d"))))
1829 (clobber (match_scratch:SI 4 "=X,l"))
1830 (clobber (match_scratch:SI 5 "=X,&d"))]
1831 "GENERATE_MADD_MSUB"
1835 [(set_attr "type" "imadd")
1836 (set_attr "accum_in" "1")
1837 (set_attr "mode" "SI")
1838 (set_attr "length" "4,8")])
1840 ;; Split *mul_sub_si if both the source and destination accumulator
1843 [(set (match_operand:SI 0 "d_operand")
1844 (minus:SI (match_operand:SI 1 "d_operand")
1845 (mult:SI (match_operand:SI 2 "d_operand")
1846 (match_operand:SI 3 "d_operand"))))
1847 (clobber (match_operand:SI 4 "lo_operand"))
1848 (clobber (match_operand:SI 5 "d_operand"))]
1850 [(parallel [(set (match_dup 5)
1851 (mult:SI (match_dup 2) (match_dup 3)))
1852 (clobber (match_dup 4))])
1853 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1856 (define_insn "*muls"
1857 [(set (match_operand:SI 0 "register_operand" "=l,d")
1858 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1859 (match_operand:SI 2 "register_operand" "d,d"))))
1860 (clobber (match_scratch:SI 3 "=X,l"))]
1865 [(set_attr "type" "imul,imul3")
1866 (set_attr "mode" "SI")])
1868 (define_expand "<u>mulsidi3"
1869 [(set (match_operand:DI 0 "register_operand")
1870 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1871 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1872 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
1874 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1875 emit_insn (fn (operands[0], operands[1], operands[2]));
1879 (define_expand "<u>mulsidi3_32bit_mips16"
1880 [(set (match_operand:DI 0 "register_operand")
1881 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1882 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1883 "!TARGET_64BIT && TARGET_MIPS16"
1887 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1888 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1889 emit_move_insn (operands[0], hilo);
1893 ;; As well as being named patterns, these instructions are used by the
1894 ;; __builtin_mips_mult<u>() functions. We must always make those functions
1895 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1896 (define_insn "<u>mulsidi3_32bit"
1897 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
1898 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1899 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1900 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP)"
1902 if (ISA_HAS_DSP_MULT)
1903 return "mult<u>\t%q0,%1,%2";
1905 return "mult<u>\t%1,%2";
1907 [(set_attr "type" "imul")
1908 (set_attr "mode" "SI")])
1910 (define_insn "<u>mulsidi3_32bit_r4000"
1911 [(set (match_operand:DI 0 "register_operand" "=d")
1912 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1913 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1914 (clobber (match_scratch:DI 3 "=x"))]
1915 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP"
1916 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1917 [(set_attr "type" "imul")
1918 (set_attr "mode" "SI")
1919 (set_attr "length" "12")])
1921 (define_insn_and_split "<u>mulsidi3_64bit"
1922 [(set (match_operand:DI 0 "register_operand" "=d")
1923 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1924 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1925 (clobber (match_scratch:TI 3 "=x"))
1926 (clobber (match_scratch:DI 4 "=d"))]
1927 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3 && !TARGET_MIPS16"
1929 "&& reload_completed"
1932 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1933 operands[2], operands[4]));
1936 [(set_attr "type" "imul")
1937 (set_attr "mode" "SI")
1938 (set (attr "length")
1939 (if_then_else (match_test "ISA_HAS_EXT_INS")
1943 (define_expand "<u>mulsidi3_64bit_mips16"
1944 [(set (match_operand:DI 0 "register_operand")
1945 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1946 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1947 "TARGET_64BIT && TARGET_MIPS16"
1949 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1950 operands[2], gen_reg_rtx (DImode)));
1954 (define_expand "<u>mulsidi3_64bit_split"
1955 [(set (match_operand:DI 0 "register_operand")
1956 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1957 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1958 (clobber (match_operand:DI 3 "register_operand"))]
1963 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1964 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1966 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM));
1967 emit_insn (gen_mfhidi_ti (operands[3], hilo));
1969 if (ISA_HAS_EXT_INS)
1970 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32),
1974 /* Zero-extend the low part. */
1975 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32));
1976 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32));
1978 /* Shift the high part into place. */
1979 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32));
1981 /* OR the two halves together. */
1982 mips_emit_binary (IOR, operands[0], operands[0], operands[3]);
1987 (define_insn "<u>mulsidi3_64bit_hilo"
1988 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
1991 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1992 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
1994 "TARGET_64BIT && !TARGET_FIX_R4000"
1996 [(set_attr "type" "imul")
1997 (set_attr "mode" "SI")])
1999 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
2000 (define_insn "mulsidi3_64bit_dmul"
2001 [(set (match_operand:DI 0 "register_operand" "=d")
2002 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2003 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2004 (clobber (match_scratch:DI 3 "=l"))]
2005 "TARGET_64BIT && ISA_HAS_DMUL3"
2007 [(set_attr "type" "imul3")
2008 (set_attr "mode" "DI")])
2010 ;; Widening multiply with negation.
2011 (define_insn "*muls<u>_di"
2012 [(set (match_operand:DI 0 "muldiv_target_operand" "=x")
2015 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2016 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2017 "!TARGET_64BIT && ISA_HAS_MULS"
2019 [(set_attr "type" "imul")
2020 (set_attr "mode" "SI")])
2022 ;; As well as being named patterns, these instructions are used by the
2023 ;; __builtin_mips_msub<u>() functions. We must always make those functions
2024 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2026 ;; This leads to a slight inconsistency. We honor any tuning overrides
2027 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
2028 ;; even if !ISA_HAS_DSP_MULT.
2029 (define_insn "<u>msubsidi4"
2030 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2032 (match_operand:DI 3 "muldiv_target_operand" "0")
2034 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2035 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2036 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
2038 if (ISA_HAS_DSP_MULT)
2039 return "msub<u>\t%q0,%1,%2";
2040 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
2041 return "msub<u>\t%1,%2";
2043 return "msac<u>\t$0,%1,%2";
2045 [(set_attr "type" "imadd")
2046 (set_attr "accum_in" "3")
2047 (set_attr "mode" "SI")])
2049 ;; _highpart patterns
2051 (define_expand "<su>mulsi3_highpart"
2052 [(set (match_operand:SI 0 "register_operand")
2055 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2056 (any_extend:DI (match_operand:SI 2 "register_operand")))
2061 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
2064 else if (TARGET_MIPS16)
2065 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2068 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
2073 (define_insn_and_split "<su>mulsi3_highpart_internal"
2074 [(set (match_operand:SI 0 "register_operand" "=d")
2077 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2078 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2080 (clobber (match_scratch:SI 3 "=l"))]
2081 "!ISA_HAS_MULHI && !TARGET_MIPS16"
2082 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2083 "&& reload_completed && !TARGET_FIX_R4000"
2086 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2090 [(set_attr "type" "imul")
2091 (set_attr "mode" "SI")
2092 (set_attr "length" "8")])
2094 (define_expand "<su>mulsi3_highpart_split"
2095 [(set (match_operand:SI 0 "register_operand")
2098 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2099 (any_extend:DI (match_operand:SI 2 "register_operand")))
2107 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2108 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2109 emit_insn (gen_mfhisi_ti (operands[0], hilo));
2113 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2114 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2115 emit_insn (gen_mfhisi_di (operands[0], hilo));
2120 (define_insn "<su>mulsi3_highpart_mulhi_internal"
2121 [(set (match_operand:SI 0 "register_operand" "=d")
2125 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2126 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2128 (clobber (match_scratch:SI 3 "=l"))]
2130 "mulhi<u>\t%0,%1,%2"
2131 [(set_attr "type" "imul3")
2132 (set_attr "mode" "SI")])
2134 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
2135 [(set (match_operand:SI 0 "register_operand" "=d")
2140 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2141 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2143 (clobber (match_scratch:SI 3 "=l"))]
2145 "mulshi<u>\t%0,%1,%2"
2146 [(set_attr "type" "imul3")
2147 (set_attr "mode" "SI")])
2149 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
2150 ;; errata MD(0), which says that dmultu does not always produce the
2152 (define_expand "<su>muldi3_highpart"
2153 [(set (match_operand:DI 0 "register_operand")
2156 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2157 (any_extend:TI (match_operand:DI 2 "register_operand")))
2159 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2162 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2165 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1],
2170 (define_insn_and_split "<su>muldi3_highpart_internal"
2171 [(set (match_operand:DI 0 "register_operand" "=d")
2174 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2175 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2177 (clobber (match_scratch:DI 3 "=l"))]
2180 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2181 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2182 "&& reload_completed && !TARGET_FIX_R4000"
2185 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2189 [(set_attr "type" "imul")
2190 (set_attr "mode" "DI")
2191 (set_attr "length" "8")])
2193 (define_expand "<su>muldi3_highpart_split"
2194 [(set (match_operand:DI 0 "register_operand")
2197 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2198 (any_extend:TI (match_operand:DI 2 "register_operand")))
2204 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2205 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2206 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2210 (define_expand "<u>mulditi3"
2211 [(set (match_operand:TI 0 "register_operand")
2212 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2213 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2214 "TARGET_64BIT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2220 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2221 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2222 emit_move_insn (operands[0], hilo);
2224 else if (TARGET_FIX_R4000)
2225 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2227 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2232 (define_insn "<u>mulditi3_internal"
2233 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2234 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2235 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2237 && !TARGET_FIX_R4000
2238 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2240 [(set_attr "type" "imul")
2241 (set_attr "mode" "DI")])
2243 (define_insn "<u>mulditi3_r4000"
2244 [(set (match_operand:TI 0 "register_operand" "=d")
2245 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2246 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2247 (clobber (match_scratch:TI 3 "=x"))]
2250 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2251 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2252 [(set_attr "type" "imul")
2253 (set_attr "mode" "DI")
2254 (set_attr "length" "12")])
2256 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2257 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2259 (define_insn "madsi"
2260 [(set (match_operand:SI 0 "register_operand" "+l")
2261 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2262 (match_operand:SI 2 "register_operand" "d"))
2266 [(set_attr "type" "imadd")
2267 (set_attr "accum_in" "0")
2268 (set_attr "mode" "SI")])
2270 ;; See the comment above <u>msubsidi4 for the relationship between
2271 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2272 (define_insn "<u>maddsidi4"
2273 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2275 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2276 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2277 (match_operand:DI 3 "muldiv_target_operand" "0")))]
2278 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2282 return "mad<u>\t%1,%2";
2283 else if (ISA_HAS_DSP_MULT)
2284 return "madd<u>\t%q0,%1,%2";
2285 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2286 return "madd<u>\t%1,%2";
2288 /* See comment in *macc. */
2289 return "%[macc<u>\t%@,%1,%2%]";
2291 [(set_attr "type" "imadd")
2292 (set_attr "accum_in" "3")
2293 (set_attr "mode" "SI")])
2295 ;; Floating point multiply accumulate instructions.
2297 (define_insn "*madd4<mode>"
2298 [(set (match_operand:ANYF 0 "register_operand" "=f")
2299 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2300 (match_operand:ANYF 2 "register_operand" "f"))
2301 (match_operand:ANYF 3 "register_operand" "f")))]
2302 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2303 "madd.<fmt>\t%0,%3,%1,%2"
2304 [(set_attr "type" "fmadd")
2305 (set_attr "accum_in" "3")
2306 (set_attr "mode" "<UNITMODE>")])
2308 (define_insn "*madd3<mode>"
2309 [(set (match_operand:ANYF 0 "register_operand" "=f")
2310 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2311 (match_operand:ANYF 2 "register_operand" "f"))
2312 (match_operand:ANYF 3 "register_operand" "0")))]
2313 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2314 "madd.<fmt>\t%0,%1,%2"
2315 [(set_attr "type" "fmadd")
2316 (set_attr "accum_in" "3")
2317 (set_attr "mode" "<UNITMODE>")])
2319 (define_insn "*msub4<mode>"
2320 [(set (match_operand:ANYF 0 "register_operand" "=f")
2321 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2322 (match_operand:ANYF 2 "register_operand" "f"))
2323 (match_operand:ANYF 3 "register_operand" "f")))]
2324 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2325 "msub.<fmt>\t%0,%3,%1,%2"
2326 [(set_attr "type" "fmadd")
2327 (set_attr "accum_in" "3")
2328 (set_attr "mode" "<UNITMODE>")])
2330 (define_insn "*msub3<mode>"
2331 [(set (match_operand:ANYF 0 "register_operand" "=f")
2332 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2333 (match_operand:ANYF 2 "register_operand" "f"))
2334 (match_operand:ANYF 3 "register_operand" "0")))]
2335 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2336 "msub.<fmt>\t%0,%1,%2"
2337 [(set_attr "type" "fmadd")
2338 (set_attr "accum_in" "3")
2339 (set_attr "mode" "<UNITMODE>")])
2341 (define_insn "*nmadd4<mode>"
2342 [(set (match_operand:ANYF 0 "register_operand" "=f")
2343 (neg:ANYF (plus:ANYF
2344 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2345 (match_operand:ANYF 2 "register_operand" "f"))
2346 (match_operand:ANYF 3 "register_operand" "f"))))]
2347 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2348 && TARGET_FUSED_MADD
2349 && HONOR_SIGNED_ZEROS (<MODE>mode)
2350 && !HONOR_NANS (<MODE>mode)"
2351 "nmadd.<fmt>\t%0,%3,%1,%2"
2352 [(set_attr "type" "fmadd")
2353 (set_attr "accum_in" "3")
2354 (set_attr "mode" "<UNITMODE>")])
2356 (define_insn "*nmadd3<mode>"
2357 [(set (match_operand:ANYF 0 "register_operand" "=f")
2358 (neg:ANYF (plus:ANYF
2359 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2360 (match_operand:ANYF 2 "register_operand" "f"))
2361 (match_operand:ANYF 3 "register_operand" "0"))))]
2362 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2363 && TARGET_FUSED_MADD
2364 && HONOR_SIGNED_ZEROS (<MODE>mode)
2365 && !HONOR_NANS (<MODE>mode)"
2366 "nmadd.<fmt>\t%0,%1,%2"
2367 [(set_attr "type" "fmadd")
2368 (set_attr "accum_in" "3")
2369 (set_attr "mode" "<UNITMODE>")])
2371 (define_insn "*nmadd4<mode>_fastmath"
2372 [(set (match_operand:ANYF 0 "register_operand" "=f")
2374 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2375 (match_operand:ANYF 2 "register_operand" "f"))
2376 (match_operand:ANYF 3 "register_operand" "f")))]
2377 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2378 && TARGET_FUSED_MADD
2379 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2380 && !HONOR_NANS (<MODE>mode)"
2381 "nmadd.<fmt>\t%0,%3,%1,%2"
2382 [(set_attr "type" "fmadd")
2383 (set_attr "accum_in" "3")
2384 (set_attr "mode" "<UNITMODE>")])
2386 (define_insn "*nmadd3<mode>_fastmath"
2387 [(set (match_operand:ANYF 0 "register_operand" "=f")
2389 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2390 (match_operand:ANYF 2 "register_operand" "f"))
2391 (match_operand:ANYF 3 "register_operand" "0")))]
2392 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2393 && TARGET_FUSED_MADD
2394 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2395 && !HONOR_NANS (<MODE>mode)"
2396 "nmadd.<fmt>\t%0,%1,%2"
2397 [(set_attr "type" "fmadd")
2398 (set_attr "accum_in" "3")
2399 (set_attr "mode" "<UNITMODE>")])
2401 (define_insn "*nmsub4<mode>"
2402 [(set (match_operand:ANYF 0 "register_operand" "=f")
2403 (neg:ANYF (minus:ANYF
2404 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2405 (match_operand:ANYF 3 "register_operand" "f"))
2406 (match_operand:ANYF 1 "register_operand" "f"))))]
2407 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2408 && TARGET_FUSED_MADD
2409 && HONOR_SIGNED_ZEROS (<MODE>mode)
2410 && !HONOR_NANS (<MODE>mode)"
2411 "nmsub.<fmt>\t%0,%1,%2,%3"
2412 [(set_attr "type" "fmadd")
2413 (set_attr "accum_in" "1")
2414 (set_attr "mode" "<UNITMODE>")])
2416 (define_insn "*nmsub3<mode>"
2417 [(set (match_operand:ANYF 0 "register_operand" "=f")
2418 (neg:ANYF (minus:ANYF
2419 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2420 (match_operand:ANYF 3 "register_operand" "f"))
2421 (match_operand:ANYF 1 "register_operand" "0"))))]
2422 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2423 && TARGET_FUSED_MADD
2424 && HONOR_SIGNED_ZEROS (<MODE>mode)
2425 && !HONOR_NANS (<MODE>mode)"
2426 "nmsub.<fmt>\t%0,%1,%2"
2427 [(set_attr "type" "fmadd")
2428 (set_attr "accum_in" "1")
2429 (set_attr "mode" "<UNITMODE>")])
2431 (define_insn "*nmsub4<mode>_fastmath"
2432 [(set (match_operand:ANYF 0 "register_operand" "=f")
2434 (match_operand:ANYF 1 "register_operand" "f")
2435 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2436 (match_operand:ANYF 3 "register_operand" "f"))))]
2437 "ISA_HAS_NMADD4_NMSUB4 (<MODE>mode)
2438 && TARGET_FUSED_MADD
2439 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2440 && !HONOR_NANS (<MODE>mode)"
2441 "nmsub.<fmt>\t%0,%1,%2,%3"
2442 [(set_attr "type" "fmadd")
2443 (set_attr "accum_in" "1")
2444 (set_attr "mode" "<UNITMODE>")])
2446 (define_insn "*nmsub3<mode>_fastmath"
2447 [(set (match_operand:ANYF 0 "register_operand" "=f")
2449 (match_operand:ANYF 1 "register_operand" "f")
2450 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2451 (match_operand:ANYF 3 "register_operand" "0"))))]
2452 "ISA_HAS_NMADD3_NMSUB3 (<MODE>mode)
2453 && TARGET_FUSED_MADD
2454 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2455 && !HONOR_NANS (<MODE>mode)"
2456 "nmsub.<fmt>\t%0,%1,%2"
2457 [(set_attr "type" "fmadd")
2458 (set_attr "accum_in" "1")
2459 (set_attr "mode" "<UNITMODE>")])
2462 ;; ....................
2464 ;; DIVISION and REMAINDER
2466 ;; ....................
2469 (define_expand "div<mode>3"
2470 [(set (match_operand:ANYF 0 "register_operand")
2471 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2472 (match_operand:ANYF 2 "register_operand")))]
2473 "<divide_condition>"
2475 if (const_1_operand (operands[1], <MODE>mode))
2476 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2477 operands[1] = force_reg (<MODE>mode, operands[1]);
2480 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2482 ;; If an mfc1 or dmfc1 happens to access the floating point register
2483 ;; file at the same time a long latency operation (div, sqrt, recip,
2484 ;; sqrt) iterates an intermediate result back through the floating
2485 ;; point register file bypass, then instead returning the correct
2486 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2487 ;; result of the long latency operation.
2489 ;; The workaround is to insert an unconditional 'mov' from/to the
2490 ;; long latency op destination register.
2492 (define_insn "*div<mode>3"
2493 [(set (match_operand:ANYF 0 "register_operand" "=f")
2494 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2495 (match_operand:ANYF 2 "register_operand" "f")))]
2496 "<divide_condition>"
2499 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2501 return "div.<fmt>\t%0,%1,%2";
2503 [(set_attr "type" "fdiv")
2504 (set_attr "mode" "<UNITMODE>")
2505 (set (attr "length")
2506 (if_then_else (match_test "TARGET_FIX_SB1")
2510 (define_insn "*recip<mode>3"
2511 [(set (match_operand:ANYF 0 "register_operand" "=f")
2512 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2513 (match_operand:ANYF 2 "register_operand" "f")))]
2514 "<recip_condition> && flag_unsafe_math_optimizations"
2517 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2519 return "recip.<fmt>\t%0,%2";
2521 [(set_attr "type" "frdiv")
2522 (set_attr "mode" "<UNITMODE>")
2523 (set (attr "length")
2524 (if_then_else (match_test "TARGET_FIX_SB1")
2528 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2529 ;; with negative operands. We use special libgcc functions instead.
2530 (define_expand "divmod<mode>4"
2531 [(set (match_operand:GPR 0 "register_operand")
2532 (div:GPR (match_operand:GPR 1 "register_operand")
2533 (match_operand:GPR 2 "register_operand")))
2534 (set (match_operand:GPR 3 "register_operand")
2535 (mod:GPR (match_dup 1)
2537 "!TARGET_FIX_VR4120"
2541 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1],
2543 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2546 emit_insn (gen_divmod<mode>4_internal (operands[0], operands[1],
2547 operands[2], operands[3]));
2551 (define_insn_and_split "divmod<mode>4_internal"
2552 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
2553 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2554 (match_operand:GPR 2 "register_operand" "d")))
2555 (set (match_operand:GPR 3 "register_operand" "=d")
2556 (mod:GPR (match_dup 1)
2558 "!TARGET_FIX_VR4120 && !TARGET_MIPS16"
2560 "&& reload_completed"
2563 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2566 [(set_attr "type" "idiv")
2567 (set_attr "mode" "<MODE>")
2568 (set_attr "length" "8")])
2570 (define_expand "udivmod<mode>4"
2571 [(set (match_operand:GPR 0 "register_operand")
2572 (udiv:GPR (match_operand:GPR 1 "register_operand")
2573 (match_operand:GPR 2 "register_operand")))
2574 (set (match_operand:GPR 3 "register_operand")
2575 (umod:GPR (match_dup 1)
2581 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1],
2583 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2586 emit_insn (gen_udivmod<mode>4_internal (operands[0], operands[1],
2587 operands[2], operands[3]));
2591 (define_insn_and_split "udivmod<mode>4_internal"
2592 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
2593 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2594 (match_operand:GPR 2 "register_operand" "d")))
2595 (set (match_operand:GPR 3 "register_operand" "=d")
2596 (umod:GPR (match_dup 1)
2603 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2606 [(set_attr "type" "idiv")
2607 (set_attr "mode" "<MODE>")
2608 (set_attr "length" "8")])
2610 (define_expand "<u>divmod<mode>4_split"
2611 [(set (match_operand:GPR 0 "register_operand")
2612 (any_mod:GPR (match_operand:GPR 1 "register_operand")
2613 (match_operand:GPR 2 "register_operand")))]
2620 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2621 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1],
2623 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo));
2627 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2628 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1],
2630 emit_insn (gen_mfhi<mode>_di (operands[0], hilo));
2635 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2636 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x")
2638 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2639 (match_operand:GPR 2 "register_operand" "d"))]
2642 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2643 [(set_attr "type" "idiv")
2644 (set_attr "mode" "<GPR:MODE>")])
2647 ;; ....................
2651 ;; ....................
2653 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2654 ;; "*div[sd]f3" comment for details).
2656 (define_insn "sqrt<mode>2"
2657 [(set (match_operand:ANYF 0 "register_operand" "=f")
2658 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2662 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2664 return "sqrt.<fmt>\t%0,%1";
2666 [(set_attr "type" "fsqrt")
2667 (set_attr "mode" "<UNITMODE>")
2668 (set (attr "length")
2669 (if_then_else (match_test "TARGET_FIX_SB1")
2673 (define_insn "*rsqrt<mode>a"
2674 [(set (match_operand:ANYF 0 "register_operand" "=f")
2675 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2676 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2677 "<recip_condition> && flag_unsafe_math_optimizations"
2680 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2682 return "rsqrt.<fmt>\t%0,%2";
2684 [(set_attr "type" "frsqrt")
2685 (set_attr "mode" "<UNITMODE>")
2686 (set (attr "length")
2687 (if_then_else (match_test "TARGET_FIX_SB1")
2691 (define_insn "*rsqrt<mode>b"
2692 [(set (match_operand:ANYF 0 "register_operand" "=f")
2693 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2694 (match_operand:ANYF 2 "register_operand" "f"))))]
2695 "<recip_condition> && flag_unsafe_math_optimizations"
2698 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2700 return "rsqrt.<fmt>\t%0,%2";
2702 [(set_attr "type" "frsqrt")
2703 (set_attr "mode" "<UNITMODE>")
2704 (set (attr "length")
2705 (if_then_else (match_test "TARGET_FIX_SB1")
2710 ;; ....................
2714 ;; ....................
2716 ;; Do not use the integer abs macro instruction, since that signals an
2717 ;; exception on -2147483648 (sigh).
2719 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2720 ;; invalid; it does not clear their sign bits. We therefore can't use
2721 ;; abs.fmt if the signs of NaNs matter.
2723 (define_insn "abs<mode>2"
2724 [(set (match_operand:ANYF 0 "register_operand" "=f")
2725 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2726 "!HONOR_NANS (<MODE>mode)"
2728 [(set_attr "type" "fabs")
2729 (set_attr "mode" "<UNITMODE>")])
2732 ;; ...................
2734 ;; Count leading zeroes.
2736 ;; ...................
2739 (define_insn "clz<mode>2"
2740 [(set (match_operand:GPR 0 "register_operand" "=d")
2741 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2744 [(set_attr "type" "clz")
2745 (set_attr "mode" "<MODE>")])
2748 ;; ...................
2750 ;; Count number of set bits.
2752 ;; ...................
2755 (define_insn "popcount<mode>2"
2756 [(set (match_operand:GPR 0 "register_operand" "=d")
2757 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2760 [(set_attr "type" "pop")
2761 (set_attr "mode" "<MODE>")])
2763 ;; The POP instruction is special as it does not take into account the upper
2764 ;; 32bits and is documented that way.
2765 (define_insn "*popcountdi2_trunc"
2766 [(set (match_operand:SI 0 "register_operand" "=d")
2767 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))]
2768 "ISA_HAS_POP && TARGET_64BIT"
2770 [(set_attr "type" "pop")
2771 (set_attr "mode" "SI")])
2774 ;; ....................
2776 ;; NEGATION and ONE'S COMPLEMENT
2778 ;; ....................
2780 (define_insn "negsi2"
2781 [(set (match_operand:SI 0 "register_operand" "=d")
2782 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2786 return "neg\t%0,%1";
2788 return "subu\t%0,%.,%1";
2790 [(set_attr "alu_type" "sub")
2791 (set_attr "mode" "SI")])
2793 (define_insn "negdi2"
2794 [(set (match_operand:DI 0 "register_operand" "=d")
2795 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2796 "TARGET_64BIT && !TARGET_MIPS16"
2798 [(set_attr "alu_type" "sub")
2799 (set_attr "mode" "DI")])
2801 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2802 ;; invalid; it does not flip their sign bit. We therefore can't use
2803 ;; neg.fmt if the signs of NaNs matter.
2805 (define_insn "neg<mode>2"
2806 [(set (match_operand:ANYF 0 "register_operand" "=f")
2807 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2808 "!HONOR_NANS (<MODE>mode)"
2810 [(set_attr "type" "fneg")
2811 (set_attr "mode" "<UNITMODE>")])
2813 (define_insn "one_cmpl<mode>2"
2814 [(set (match_operand:GPR 0 "register_operand" "=d")
2815 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2819 return "not\t%0,%1";
2821 return "nor\t%0,%.,%1";
2823 [(set_attr "alu_type" "not")
2824 (set_attr "mode" "<MODE>")])
2827 ;; ....................
2831 ;; ....................
2834 ;; Many of these instructions use trivial define_expands, because we
2835 ;; want to use a different set of constraints when TARGET_MIPS16.
2837 (define_expand "and<mode>3"
2838 [(set (match_operand:GPR 0 "register_operand")
2839 (and:GPR (match_operand:GPR 1 "register_operand")
2840 (match_operand:GPR 2 "and_reg_operand")))])
2842 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
2843 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
2844 ;; Note that this variant does not trigger for SI mode because we require
2845 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
2846 ;; sign-extended SImode value.
2848 ;; These are possible combinations for operand 1 and 2. The table
2849 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
2850 ;; 16=MIPS16, x=match, S=split):
2852 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
2858 ;; 0xffff_ffff x S x S x
2863 (define_insn "*and<mode>3"
2864 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d,d,d")
2865 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,d,d,d,d")
2866 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,K,Yx,Yw,d")))]
2867 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2871 switch (which_alternative)
2874 operands[1] = gen_lowpart (QImode, operands[1]);
2875 return "lbu\t%0,%1";
2877 operands[1] = gen_lowpart (HImode, operands[1]);
2878 return "lhu\t%0,%1";
2880 operands[1] = gen_lowpart (SImode, operands[1]);
2881 return "lwu\t%0,%1";
2883 return "andi\t%0,%1,%x2";
2885 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
2886 operands[2] = GEN_INT (len);
2887 return "<d>ext\t%0,%1,0,%2";
2891 return "and\t%0,%1,%2";
2896 [(set_attr "move_type" "load,load,load,andi,ext_ins,shift_shift,logical")
2897 (set_attr "mode" "<MODE>")])
2899 (define_insn "*and<mode>3_mips16"
2900 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
2901 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%o,o,W,d,0")
2902 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
2903 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2905 switch (which_alternative)
2908 operands[1] = gen_lowpart (QImode, operands[1]);
2909 return "lbu\t%0,%1";
2911 operands[1] = gen_lowpart (HImode, operands[1]);
2912 return "lhu\t%0,%1";
2914 operands[1] = gen_lowpart (SImode, operands[1]);
2915 return "lwu\t%0,%1";
2919 return "and\t%0,%2";
2924 [(set_attr "move_type" "load,load,load,shift_shift,logical")
2925 (set_attr "mode" "<MODE>")])
2927 (define_expand "ior<mode>3"
2928 [(set (match_operand:GPR 0 "register_operand")
2929 (ior:GPR (match_operand:GPR 1 "register_operand")
2930 (match_operand:GPR 2 "uns_arith_operand")))]
2934 operands[2] = force_reg (<MODE>mode, operands[2]);
2937 (define_insn "*ior<mode>3"
2938 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2939 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2940 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2945 [(set_attr "alu_type" "or")
2946 (set_attr "mode" "<MODE>")])
2948 (define_insn "*ior<mode>3_mips16"
2949 [(set (match_operand:GPR 0 "register_operand" "=d")
2950 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2951 (match_operand:GPR 2 "register_operand" "d")))]
2954 [(set_attr "alu_type" "or")
2955 (set_attr "mode" "<MODE>")])
2957 (define_expand "xor<mode>3"
2958 [(set (match_operand:GPR 0 "register_operand")
2959 (xor:GPR (match_operand:GPR 1 "register_operand")
2960 (match_operand:GPR 2 "uns_arith_operand")))]
2965 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2966 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2967 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2972 [(set_attr "alu_type" "xor")
2973 (set_attr "mode" "<MODE>")])
2976 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2977 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2978 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2984 [(set_attr "alu_type" "xor")
2985 (set_attr "mode" "<MODE>")
2986 (set_attr_alternative "length"
2988 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2993 (define_insn "*nor<mode>3"
2994 [(set (match_operand:GPR 0 "register_operand" "=d")
2995 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2996 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2999 [(set_attr "alu_type" "nor")
3000 (set_attr "mode" "<MODE>")])
3003 ;; ....................
3007 ;; ....................
3011 (define_insn "truncdfsf2"
3012 [(set (match_operand:SF 0 "register_operand" "=f")
3013 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3014 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3016 [(set_attr "type" "fcvt")
3017 (set_attr "cnv_mode" "D2S")
3018 (set_attr "mode" "SF")])
3020 ;; Integer truncation patterns. Truncating SImode values to smaller
3021 ;; modes is a no-op, as it is for most other GCC ports. Truncating
3022 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
3023 ;; need to make sure that the lower 32 bits are properly sign-extended
3024 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
3025 ;; smaller than SImode is equivalent to two separate truncations:
3028 ;; DI ---> HI == DI ---> SI ---> HI
3029 ;; DI ---> QI == DI ---> SI ---> QI
3031 ;; Step A needs a real instruction but step B does not.
3033 (define_insn "truncdi<mode>2"
3034 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
3035 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
3040 [(set_attr "move_type" "sll0,store")
3041 (set_attr "mode" "SI")])
3043 ;; Combiner patterns to optimize shift/truncate combinations.
3045 (define_insn "*ashr_trunc<mode>"
3046 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3048 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3049 (match_operand:DI 2 "const_arith_operand" ""))))]
3050 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3052 [(set_attr "type" "shift")
3053 (set_attr "mode" "<MODE>")])
3055 (define_insn "*lshr32_trunc<mode>"
3056 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3058 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3060 "TARGET_64BIT && !TARGET_MIPS16"
3062 [(set_attr "type" "shift")
3063 (set_attr "mode" "<MODE>")])
3065 ;; Logical shift by more than 32 results in proper SI values so truncation is
3066 ;; removed by the middle end. Note that a logical shift by 32 is handled by
3067 ;; the previous pattern.
3068 (define_insn "*<optab>_trunc<mode>_exts"
3069 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3071 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
3072 (match_operand:DI 2 "const_arith_operand" ""))))]
3073 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
3075 [(set_attr "type" "arith")
3076 (set_attr "mode" "<MODE>")])
3079 ;; ....................
3083 ;; ....................
3087 (define_expand "zero_extendsidi2"
3088 [(set (match_operand:DI 0 "register_operand")
3089 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
3092 (define_insn_and_split "*zero_extendsidi2"
3093 [(set (match_operand:DI 0 "register_operand" "=d,d")
3094 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3095 "TARGET_64BIT && !ISA_HAS_EXT_INS"
3099 "&& reload_completed && REG_P (operands[1])"
3101 (ashift:DI (match_dup 1) (const_int 32)))
3103 (lshiftrt:DI (match_dup 0) (const_int 32)))]
3104 { operands[1] = gen_lowpart (DImode, operands[1]); }
3105 [(set_attr "move_type" "shift_shift,load")
3106 (set_attr "mode" "DI")])
3108 (define_insn "*zero_extendsidi2_dext"
3109 [(set (match_operand:DI 0 "register_operand" "=d,d")
3110 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3111 "TARGET_64BIT && ISA_HAS_EXT_INS"
3115 [(set_attr "move_type" "arith,load")
3116 (set_attr "mode" "DI")])
3118 ;; See the comment before the *and<mode>3 pattern why this is generated by
3122 [(set (match_operand:DI 0 "register_operand")
3123 (and:DI (match_operand:DI 1 "register_operand")
3124 (const_int 4294967295)))]
3125 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
3127 (ashift:DI (match_dup 1) (const_int 32)))
3129 (lshiftrt:DI (match_dup 0) (const_int 32)))])
3131 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
3132 [(set (match_operand:GPR 0 "register_operand")
3133 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3136 if (TARGET_MIPS16 && !GENERATE_MIPS16E
3137 && !memory_operand (operands[1], <SHORT:MODE>mode))
3139 emit_insn (gen_and<GPR:mode>3 (operands[0],
3140 gen_lowpart (<GPR:MODE>mode, operands[1]),
3141 force_reg (<GPR:MODE>mode,
3142 GEN_INT (<SHORT:mask>))));
3147 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
3148 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3150 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3153 andi\t%0,%1,<SHORT:mask>
3154 l<SHORT:size>u\t%0,%1"
3155 [(set_attr "move_type" "andi,load")
3156 (set_attr "mode" "<GPR:MODE>")])
3158 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
3159 [(set (match_operand:GPR 0 "register_operand" "=d")
3160 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
3162 "ze<SHORT:size>\t%0"
3163 ;; This instruction is effectively a special encoding of ANDI.
3164 [(set_attr "move_type" "andi")
3165 (set_attr "mode" "<GPR:MODE>")])
3167 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
3168 [(set (match_operand:GPR 0 "register_operand" "=d")
3169 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
3171 "l<SHORT:size>u\t%0,%1"
3172 [(set_attr "move_type" "load")
3173 (set_attr "mode" "<GPR:MODE>")])
3175 (define_expand "zero_extendqihi2"
3176 [(set (match_operand:HI 0 "register_operand")
3177 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3180 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
3182 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
3188 (define_insn "*zero_extendqihi2"
3189 [(set (match_operand:HI 0 "register_operand" "=d,d")
3190 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3195 [(set_attr "move_type" "andi,load")
3196 (set_attr "mode" "HI")])
3198 (define_insn "*zero_extendqihi2_mips16"
3199 [(set (match_operand:HI 0 "register_operand" "=d")
3200 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3203 [(set_attr "move_type" "load")
3204 (set_attr "mode" "HI")])
3206 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3208 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
3209 [(set (match_operand:GPR 0 "register_operand" "=d")
3211 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3212 "TARGET_64BIT && !TARGET_MIPS16"
3214 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3215 return "andi\t%0,%1,%x2";
3217 [(set_attr "alu_type" "and")
3218 (set_attr "mode" "<GPR:MODE>")])
3220 (define_insn "*zero_extendhi_truncqi"
3221 [(set (match_operand:HI 0 "register_operand" "=d")
3223 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3224 "TARGET_64BIT && !TARGET_MIPS16"
3226 [(set_attr "alu_type" "and")
3227 (set_attr "mode" "HI")])
3230 ;; ....................
3234 ;; ....................
3237 ;; Those for integer source operand are ordered widest source type first.
3239 ;; When TARGET_64BIT, all SImode integer and accumulator registers
3240 ;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
3241 ;; and truncdisi2). We can therefore get rid of register->register
3242 ;; instructions if we constrain the source to be in the same register as
3245 ;; Only the pre-reload scheduler sees the type of the register alternatives;
3246 ;; we split them into nothing before the post-reload scheduler runs.
3247 ;; These alternatives therefore have type "move" in order to reflect
3248 ;; what happens if the two pre-reload operands cannot be tied, and are
3249 ;; instead allocated two separate GPRs. We don't distinguish between
3250 ;; the GPR and LO cases because we don't usually know during pre-reload
3251 ;; scheduling whether an operand will be LO or not.
3252 (define_insn_and_split "extendsidi2"
3253 [(set (match_operand:DI 0 "register_operand" "=d,l,d")
3254 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
3260 "&& reload_completed && register_operand (operands[1], VOIDmode)"
3263 emit_note (NOTE_INSN_DELETED);
3266 [(set_attr "move_type" "move,move,load")
3267 (set_attr "mode" "DI")])
3269 (define_expand "extend<SHORT:mode><GPR:mode>2"
3270 [(set (match_operand:GPR 0 "register_operand")
3271 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3274 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
3275 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3276 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3280 l<SHORT:size>\t%0,%1"
3281 [(set_attr "move_type" "signext,load")
3282 (set_attr "mode" "<GPR:MODE>")])
3284 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3285 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3287 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3288 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3291 l<SHORT:size>\t%0,%1"
3292 "&& reload_completed && REG_P (operands[1])"
3293 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3294 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3296 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3297 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3298 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3300 [(set_attr "move_type" "shift_shift,load")
3301 (set_attr "mode" "<GPR:MODE>")])
3303 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3304 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3306 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3309 se<SHORT:size>\t%0,%1
3310 l<SHORT:size>\t%0,%1"
3311 [(set_attr "move_type" "signext,load")
3312 (set_attr "mode" "<GPR:MODE>")])
3314 (define_expand "extendqihi2"
3315 [(set (match_operand:HI 0 "register_operand")
3316 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3319 (define_insn "*extendqihi2_mips16e"
3320 [(set (match_operand:HI 0 "register_operand" "=d,d")
3321 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3326 [(set_attr "move_type" "signext,load")
3327 (set_attr "mode" "SI")])
3329 (define_insn_and_split "*extendqihi2"
3330 [(set (match_operand:HI 0 "register_operand" "=d,d")
3332 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3333 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3337 "&& reload_completed && REG_P (operands[1])"
3338 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3339 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3341 operands[0] = gen_lowpart (SImode, operands[0]);
3342 operands[1] = gen_lowpart (SImode, operands[1]);
3343 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3344 - GET_MODE_BITSIZE (QImode));
3346 [(set_attr "move_type" "shift_shift,load")
3347 (set_attr "mode" "SI")])
3349 (define_insn "*extendqihi2_seb"
3350 [(set (match_operand:HI 0 "register_operand" "=d,d")
3352 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3357 [(set_attr "move_type" "signext,load")
3358 (set_attr "mode" "SI")])
3360 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3361 ;; use the shift/truncate patterns.
3363 (define_insn_and_split "*extenddi_truncate<mode>"
3364 [(set (match_operand:DI 0 "register_operand" "=d")
3366 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3367 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3369 "&& reload_completed"
3371 (ashift:DI (match_dup 1)
3374 (ashiftrt:DI (match_dup 2)
3377 operands[2] = gen_lowpart (DImode, operands[0]);
3378 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3380 [(set_attr "move_type" "shift_shift")
3381 (set_attr "mode" "DI")])
3383 (define_insn_and_split "*extendsi_truncate<mode>"
3384 [(set (match_operand:SI 0 "register_operand" "=d")
3386 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3387 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3389 "&& reload_completed"
3391 (ashift:DI (match_dup 1)
3394 (truncate:SI (ashiftrt:DI (match_dup 2)
3397 operands[2] = gen_lowpart (DImode, operands[0]);
3398 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3400 [(set_attr "move_type" "shift_shift")
3401 (set_attr "mode" "SI")])
3403 (define_insn_and_split "*extendhi_truncateqi"
3404 [(set (match_operand:HI 0 "register_operand" "=d")
3406 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3407 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3409 "&& reload_completed"
3411 (ashift:DI (match_dup 1)
3414 (truncate:HI (ashiftrt:DI (match_dup 2)
3417 operands[2] = gen_lowpart (DImode, operands[0]);
3419 [(set_attr "move_type" "shift_shift")
3420 (set_attr "mode" "SI")])
3422 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3423 [(set (match_operand:GPR 0 "register_operand" "=d")
3425 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3426 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3428 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3429 return "exts\t%0,%1,0,%m2";
3431 [(set_attr "type" "arith")
3432 (set_attr "mode" "<GPR:MODE>")])
3434 (define_insn "*extendhi_truncateqi_exts"
3435 [(set (match_operand:HI 0 "register_operand" "=d")
3437 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3438 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3440 [(set_attr "type" "arith")
3441 (set_attr "mode" "SI")])
3443 (define_insn "extendsfdf2"
3444 [(set (match_operand:DF 0 "register_operand" "=f")
3445 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3446 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3448 [(set_attr "type" "fcvt")
3449 (set_attr "cnv_mode" "S2D")
3450 (set_attr "mode" "DF")])
3453 ;; ....................
3457 ;; ....................
3459 (define_expand "fix_truncdfsi2"
3460 [(set (match_operand:SI 0 "register_operand")
3461 (fix:SI (match_operand:DF 1 "register_operand")))]
3462 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3464 if (!ISA_HAS_TRUNC_W)
3466 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3471 (define_insn "fix_truncdfsi2_insn"
3472 [(set (match_operand:SI 0 "register_operand" "=f")
3473 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3474 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3476 [(set_attr "type" "fcvt")
3477 (set_attr "mode" "DF")
3478 (set_attr "cnv_mode" "D2I")])
3480 (define_insn "fix_truncdfsi2_macro"
3481 [(set (match_operand:SI 0 "register_operand" "=f")
3482 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3483 (clobber (match_scratch:DF 2 "=d"))]
3484 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3486 if (mips_nomacro.nesting_level > 0)
3487 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3489 return "trunc.w.d %0,%1,%2";
3491 [(set_attr "type" "fcvt")
3492 (set_attr "mode" "DF")
3493 (set_attr "cnv_mode" "D2I")
3494 (set_attr "length" "36")])
3496 (define_expand "fix_truncsfsi2"
3497 [(set (match_operand:SI 0 "register_operand")
3498 (fix:SI (match_operand:SF 1 "register_operand")))]
3501 if (!ISA_HAS_TRUNC_W)
3503 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3508 (define_insn "fix_truncsfsi2_insn"
3509 [(set (match_operand:SI 0 "register_operand" "=f")
3510 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3511 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3513 [(set_attr "type" "fcvt")
3514 (set_attr "mode" "SF")
3515 (set_attr "cnv_mode" "S2I")])
3517 (define_insn "fix_truncsfsi2_macro"
3518 [(set (match_operand:SI 0 "register_operand" "=f")
3519 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3520 (clobber (match_scratch:SF 2 "=d"))]
3521 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3523 if (mips_nomacro.nesting_level > 0)
3524 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3526 return "trunc.w.s %0,%1,%2";
3528 [(set_attr "type" "fcvt")
3529 (set_attr "mode" "SF")
3530 (set_attr "cnv_mode" "S2I")
3531 (set_attr "length" "36")])
3534 (define_insn "fix_truncdfdi2"
3535 [(set (match_operand:DI 0 "register_operand" "=f")
3536 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3537 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3539 [(set_attr "type" "fcvt")
3540 (set_attr "mode" "DF")
3541 (set_attr "cnv_mode" "D2I")])
3544 (define_insn "fix_truncsfdi2"
3545 [(set (match_operand:DI 0 "register_operand" "=f")
3546 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3547 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3549 [(set_attr "type" "fcvt")
3550 (set_attr "mode" "SF")
3551 (set_attr "cnv_mode" "S2I")])
3554 (define_insn "floatsidf2"
3555 [(set (match_operand:DF 0 "register_operand" "=f")
3556 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3557 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3559 [(set_attr "type" "fcvt")
3560 (set_attr "mode" "DF")
3561 (set_attr "cnv_mode" "I2D")])
3564 (define_insn "floatdidf2"
3565 [(set (match_operand:DF 0 "register_operand" "=f")
3566 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3567 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3569 [(set_attr "type" "fcvt")
3570 (set_attr "mode" "DF")
3571 (set_attr "cnv_mode" "I2D")])
3574 (define_insn "floatsisf2"
3575 [(set (match_operand:SF 0 "register_operand" "=f")
3576 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3579 [(set_attr "type" "fcvt")
3580 (set_attr "mode" "SF")
3581 (set_attr "cnv_mode" "I2S")])
3584 (define_insn "floatdisf2"
3585 [(set (match_operand:SF 0 "register_operand" "=f")
3586 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3587 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3589 [(set_attr "type" "fcvt")
3590 (set_attr "mode" "SF")
3591 (set_attr "cnv_mode" "I2S")])
3594 (define_expand "fixuns_truncdfsi2"
3595 [(set (match_operand:SI 0 "register_operand")
3596 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3597 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3599 rtx reg1 = gen_reg_rtx (DFmode);
3600 rtx reg2 = gen_reg_rtx (DFmode);
3601 rtx reg3 = gen_reg_rtx (SImode);
3602 rtx label1 = gen_label_rtx ();
3603 rtx label2 = gen_label_rtx ();
3605 REAL_VALUE_TYPE offset;
3607 real_2expN (&offset, 31, DFmode);
3609 if (reg1) /* Turn off complaints about unreached code. */
3611 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3612 do_pending_stack_adjust ();
3614 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3615 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3617 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3618 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3619 gen_rtx_LABEL_REF (VOIDmode, label2)));
3622 emit_label (label1);
3623 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3624 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3625 (BITMASK_HIGH, SImode)));
3627 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3628 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3630 emit_label (label2);
3632 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3633 fields, and can't be used for REG_NOTES anyway). */
3634 emit_use (stack_pointer_rtx);
3640 (define_expand "fixuns_truncdfdi2"
3641 [(set (match_operand:DI 0 "register_operand")
3642 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3643 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3645 rtx reg1 = gen_reg_rtx (DFmode);
3646 rtx reg2 = gen_reg_rtx (DFmode);
3647 rtx reg3 = gen_reg_rtx (DImode);
3648 rtx label1 = gen_label_rtx ();
3649 rtx label2 = gen_label_rtx ();
3651 REAL_VALUE_TYPE offset;
3653 real_2expN (&offset, 63, DFmode);
3655 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3656 do_pending_stack_adjust ();
3658 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3659 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3661 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3662 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3663 gen_rtx_LABEL_REF (VOIDmode, label2)));
3666 emit_label (label1);
3667 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3668 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3669 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3671 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3672 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3674 emit_label (label2);
3676 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3677 fields, and can't be used for REG_NOTES anyway). */
3678 emit_use (stack_pointer_rtx);
3683 (define_expand "fixuns_truncsfsi2"
3684 [(set (match_operand:SI 0 "register_operand")
3685 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3688 rtx reg1 = gen_reg_rtx (SFmode);
3689 rtx reg2 = gen_reg_rtx (SFmode);
3690 rtx reg3 = gen_reg_rtx (SImode);
3691 rtx label1 = gen_label_rtx ();
3692 rtx label2 = gen_label_rtx ();
3694 REAL_VALUE_TYPE offset;
3696 real_2expN (&offset, 31, SFmode);
3698 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3699 do_pending_stack_adjust ();
3701 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3702 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3704 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3705 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3706 gen_rtx_LABEL_REF (VOIDmode, label2)));
3709 emit_label (label1);
3710 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3711 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3712 (BITMASK_HIGH, SImode)));
3714 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3715 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3717 emit_label (label2);
3719 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3720 fields, and can't be used for REG_NOTES anyway). */
3721 emit_use (stack_pointer_rtx);
3726 (define_expand "fixuns_truncsfdi2"
3727 [(set (match_operand:DI 0 "register_operand")
3728 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3729 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3731 rtx reg1 = gen_reg_rtx (SFmode);
3732 rtx reg2 = gen_reg_rtx (SFmode);
3733 rtx reg3 = gen_reg_rtx (DImode);
3734 rtx label1 = gen_label_rtx ();
3735 rtx label2 = gen_label_rtx ();
3737 REAL_VALUE_TYPE offset;
3739 real_2expN (&offset, 63, SFmode);
3741 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3742 do_pending_stack_adjust ();
3744 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3745 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3747 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3748 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3749 gen_rtx_LABEL_REF (VOIDmode, label2)));
3752 emit_label (label1);
3753 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3754 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3755 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3757 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3758 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3760 emit_label (label2);
3762 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3763 fields, and can't be used for REG_NOTES anyway). */
3764 emit_use (stack_pointer_rtx);
3769 ;; ....................
3773 ;; ....................
3775 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3777 (define_expand "extv"
3778 [(set (match_operand 0 "register_operand")
3779 (sign_extract (match_operand 1 "nonimmediate_operand")
3780 (match_operand 2 "const_int_operand")
3781 (match_operand 3 "const_int_operand")))]
3784 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3785 INTVAL (operands[2]),
3786 INTVAL (operands[3]),
3787 /*unsigned=*/ false))
3789 else if (register_operand (operands[1], GET_MODE (operands[0]))
3790 && ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
3792 if (GET_MODE (operands[0]) == DImode)
3793 emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
3796 emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
3804 (define_insn "extv<mode>"
3805 [(set (match_operand:GPR 0 "register_operand" "=d")
3806 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3807 (match_operand 2 "const_int_operand" "")
3808 (match_operand 3 "const_int_operand" "")))]
3809 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3810 "exts\t%0,%1,%3,%m2"
3811 [(set_attr "type" "arith")
3812 (set_attr "mode" "<MODE>")])
3815 (define_expand "extzv"
3816 [(set (match_operand 0 "register_operand")
3817 (zero_extract (match_operand 1 "nonimmediate_operand")
3818 (match_operand 2 "const_int_operand")
3819 (match_operand 3 "const_int_operand")))]
3822 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3823 INTVAL (operands[2]),
3824 INTVAL (operands[3]),
3827 else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3828 INTVAL (operands[3])))
3830 if (GET_MODE (operands[0]) == DImode)
3831 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
3834 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
3842 (define_insn "extzv<mode>"
3843 [(set (match_operand:GPR 0 "register_operand" "=d")
3844 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3845 (match_operand 2 "const_int_operand" "")
3846 (match_operand 3 "const_int_operand" "")))]
3847 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3848 INTVAL (operands[3]))"
3849 "<d>ext\t%0,%1,%3,%2"
3850 [(set_attr "type" "arith")
3851 (set_attr "mode" "<MODE>")])
3853 (define_insn "*extzv_truncsi_exts"
3854 [(set (match_operand:SI 0 "register_operand" "=d")
3856 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3857 (match_operand 2 "const_int_operand" "")
3858 (match_operand 3 "const_int_operand" ""))))]
3859 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3861 [(set_attr "type" "arith")
3862 (set_attr "mode" "SI")])
3865 (define_expand "insv"
3866 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
3867 (match_operand 1 "immediate_operand")
3868 (match_operand 2 "immediate_operand"))
3869 (match_operand 3 "reg_or_0_operand"))]
3872 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3873 INTVAL (operands[1]),
3874 INTVAL (operands[2])))
3876 else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3877 INTVAL (operands[2])))
3879 if (GET_MODE (operands[0]) == DImode)
3880 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3883 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3891 (define_insn "insv<mode>"
3892 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3893 (match_operand:SI 1 "immediate_operand" "I")
3894 (match_operand:SI 2 "immediate_operand" "I"))
3895 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3896 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3897 INTVAL (operands[2]))"
3898 "<d>ins\t%0,%z3,%2,%1"
3899 [(set_attr "type" "arith")
3900 (set_attr "mode" "<MODE>")])
3902 ;; Combiner pattern for cins (clear and insert bit field). We can
3903 ;; implement mask-and-shift-left operation with this. Note that if
3904 ;; the upper bit of the mask is set in an SImode operation, the mask
3905 ;; itself will be sign-extended. mask_low_and_shift_len will
3906 ;; therefore be greater than our threshold of 32.
3908 (define_insn "*cins<mode>"
3909 [(set (match_operand:GPR 0 "register_operand" "=d")
3911 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3912 (match_operand:GPR 2 "const_int_operand" ""))
3913 (match_operand:GPR 3 "const_int_operand" "")))]
3915 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3918 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3919 return "cins\t%0,%1,%2,%m3";
3921 [(set_attr "type" "shift")
3922 (set_attr "mode" "<MODE>")])
3924 ;; Unaligned word moves generated by the bit field patterns.
3926 ;; As far as the rtl is concerned, both the left-part and right-part
3927 ;; instructions can access the whole field. However, the real operand
3928 ;; refers to just the first or the last byte (depending on endianness).
3929 ;; We therefore use two memory operands to each instruction, one to
3930 ;; describe the rtl effect and one to use in the assembly output.
3932 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3933 ;; This allows us to use the standard length calculations for the "load"
3934 ;; and "store" type attributes.
3936 (define_insn "mov_<load>l"
3937 [(set (match_operand:GPR 0 "register_operand" "=d")
3938 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3939 (match_operand:QI 2 "memory_operand" "m")]
3941 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3943 [(set_attr "move_type" "load")
3944 (set_attr "mode" "<MODE>")])
3946 (define_insn "mov_<load>r"
3947 [(set (match_operand:GPR 0 "register_operand" "=d")
3948 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3949 (match_operand:QI 2 "memory_operand" "m")
3950 (match_operand:GPR 3 "register_operand" "0")]
3951 UNSPEC_LOAD_RIGHT))]
3952 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3954 [(set_attr "move_type" "load")
3955 (set_attr "mode" "<MODE>")])
3957 (define_insn "mov_<store>l"
3958 [(set (match_operand:BLK 0 "memory_operand" "=m")
3959 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3960 (match_operand:QI 2 "memory_operand" "m")]
3961 UNSPEC_STORE_LEFT))]
3962 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3964 [(set_attr "move_type" "store")
3965 (set_attr "mode" "<MODE>")])
3967 (define_insn "mov_<store>r"
3968 [(set (match_operand:BLK 0 "memory_operand" "+m")
3969 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3970 (match_operand:QI 2 "memory_operand" "m")
3972 UNSPEC_STORE_RIGHT))]
3973 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3975 [(set_attr "move_type" "store")
3976 (set_attr "mode" "<MODE>")])
3978 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3979 ;; The required value is:
3981 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3983 ;; which translates to:
3985 ;; lui op0,%highest(op1)
3986 ;; daddiu op0,op0,%higher(op1)
3988 ;; daddiu op0,op0,%hi(op1)
3991 ;; The split is deferred until after flow2 to allow the peephole2 below
3993 (define_insn_and_split "*lea_high64"
3994 [(set (match_operand:DI 0 "register_operand" "=d")
3995 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3996 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3998 "&& epilogue_completed"
3999 [(set (match_dup 0) (high:DI (match_dup 2)))
4000 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
4001 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
4002 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4003 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
4005 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4006 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
4008 [(set_attr "length" "20")])
4010 ;; Use a scratch register to reduce the latency of the above pattern
4011 ;; on superscalar machines. The optimized sequence is:
4013 ;; lui op1,%highest(op2)
4015 ;; daddiu op1,op1,%higher(op2)
4017 ;; daddu op1,op1,op0
4019 [(set (match_operand:DI 1 "d_operand")
4020 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
4021 (match_scratch:DI 0 "d")]
4022 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4023 [(set (match_dup 1) (high:DI (match_dup 3)))
4024 (set (match_dup 0) (high:DI (match_dup 4)))
4025 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
4026 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
4027 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
4029 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
4030 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
4033 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
4034 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
4035 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
4036 ;; used once. We can then use the sequence:
4038 ;; lui op0,%highest(op1)
4040 ;; daddiu op0,op0,%higher(op1)
4041 ;; daddiu op2,op2,%lo(op1)
4043 ;; daddu op0,op0,op2
4045 ;; which takes 4 cycles on most superscalar targets.
4046 (define_insn_and_split "*lea64"
4047 [(set (match_operand:DI 0 "register_operand" "=d")
4048 (match_operand:DI 1 "absolute_symbolic_operand" ""))
4049 (clobber (match_scratch:DI 2 "=&d"))]
4050 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
4052 "&& reload_completed"
4053 [(set (match_dup 0) (high:DI (match_dup 3)))
4054 (set (match_dup 2) (high:DI (match_dup 4)))
4055 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4056 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
4057 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
4058 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
4060 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4061 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
4063 [(set_attr "length" "24")])
4065 ;; Split HIGHs into:
4070 ;; on MIPS16 targets.
4072 [(set (match_operand:P 0 "d_operand")
4073 (high:P (match_operand:P 1 "symbolic_operand_with_high")))]
4074 "TARGET_MIPS16 && reload_completed"
4075 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH))
4076 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))])
4078 (define_insn "*unshifted_high"
4079 [(set (match_operand:P 0 "d_operand" "=d")
4080 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")]
4081 UNSPEC_UNSHIFTED_HIGH))]
4084 [(set_attr "extended_mips16" "yes")])
4086 ;; Insns to fetch a symbol from a big GOT.
4088 (define_insn_and_split "*xgot_hi<mode>"
4089 [(set (match_operand:P 0 "register_operand" "=d")
4090 (high:P (match_operand:P 1 "got_disp_operand" "")))]
4091 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4093 "&& reload_completed"
4094 [(set (match_dup 0) (high:P (match_dup 2)))
4095 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
4097 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
4098 operands[3] = pic_offset_table_rtx;
4100 [(set_attr "got" "xgot_high")
4101 (set_attr "mode" "<MODE>")])
4103 (define_insn_and_split "*xgot_lo<mode>"
4104 [(set (match_operand:P 0 "register_operand" "=d")
4105 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4106 (match_operand:P 2 "got_disp_operand" "")))]
4107 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4109 "&& reload_completed"
4111 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
4112 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
4113 [(set_attr "got" "load")
4114 (set_attr "mode" "<MODE>")])
4116 ;; Insns to fetch a symbol from a normal GOT.
4118 (define_insn_and_split "*got_disp<mode>"
4119 [(set (match_operand:P 0 "register_operand" "=d")
4120 (match_operand:P 1 "got_disp_operand" ""))]
4121 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
4123 "&& reload_completed"
4124 [(set (match_dup 0) (match_dup 2))]
4125 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
4126 [(set_attr "got" "load")
4127 (set_attr "mode" "<MODE>")])
4129 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
4131 (define_insn_and_split "*got_page<mode>"
4132 [(set (match_operand:P 0 "register_operand" "=d")
4133 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
4134 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
4136 "&& reload_completed"
4137 [(set (match_dup 0) (match_dup 2))]
4138 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
4139 [(set_attr "got" "load")
4140 (set_attr "mode" "<MODE>")])
4142 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
4143 (define_expand "unspec_got_<mode>"
4144 [(unspec:P [(match_operand:P 0)
4145 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
4147 ;; Lower-level instructions for loading an address from the GOT.
4148 ;; We could use MEMs, but an unspec gives more optimization
4151 (define_insn "load_got<mode>"
4152 [(set (match_operand:P 0 "register_operand" "=d")
4153 (unspec:P [(match_operand:P 1 "register_operand" "d")
4154 (match_operand:P 2 "immediate_operand" "")]
4157 "<load>\t%0,%R2(%1)"
4158 [(set_attr "got" "load")
4159 (set_attr "mode" "<MODE>")])
4161 ;; Instructions for adding the low 16 bits of an address to a register.
4162 ;; Operand 2 is the address: mips_print_operand works out which relocation
4163 ;; should be applied.
4165 (define_insn "*low<mode>"
4166 [(set (match_operand:P 0 "register_operand" "=d")
4167 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4168 (match_operand:P 2 "immediate_operand" "")))]
4170 "<d>addiu\t%0,%1,%R2"
4171 [(set_attr "alu_type" "add")
4172 (set_attr "mode" "<MODE>")])
4174 (define_insn "*low<mode>_mips16"
4175 [(set (match_operand:P 0 "register_operand" "=d")
4176 (lo_sum:P (match_operand:P 1 "register_operand" "0")
4177 (match_operand:P 2 "immediate_operand" "")))]
4180 [(set_attr "alu_type" "add")
4181 (set_attr "mode" "<MODE>")
4182 (set_attr "extended_mips16" "yes")])
4184 ;; Expose MIPS16 uses of the global pointer after reload if the function
4185 ;; is responsible for setting up the register itself.
4187 [(set (match_operand:GPR 0 "d_operand")
4188 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
4189 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
4190 [(set (match_dup 0) (match_dup 1))]
4191 { operands[1] = pic_offset_table_rtx; })
4193 ;; Allow combine to split complex const_int load sequences, using operand 2
4194 ;; to store the intermediate results. See move_operand for details.
4196 [(set (match_operand:GPR 0 "register_operand")
4197 (match_operand:GPR 1 "splittable_const_int_operand"))
4198 (clobber (match_operand:GPR 2 "register_operand"))]
4202 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
4206 ;; Likewise, for symbolic operands.
4208 [(set (match_operand:P 0 "register_operand")
4209 (match_operand:P 1))
4210 (clobber (match_operand:P 2 "register_operand"))]
4211 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
4212 [(set (match_dup 0) (match_dup 3))]
4214 mips_split_symbol (operands[2], operands[1],
4215 MAX_MACHINE_MODE, &operands[3]);
4218 ;; 64-bit integer moves
4220 ;; Unlike most other insns, the move insns can't be split with
4221 ;; different predicates, because register spilling and other parts of
4222 ;; the compiler, have memoized the insn number already.
4224 (define_expand "movdi"
4225 [(set (match_operand:DI 0 "")
4226 (match_operand:DI 1 ""))]
4229 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4233 ;; For mips16, we need a special case to handle storing $31 into
4234 ;; memory, since we don't have a constraint to match $31. This
4235 ;; instruction can be generated by save_restore_insns.
4237 (define_insn "*mov<mode>_ra"
4238 [(set (match_operand:GPR 0 "stack_operand" "=m")
4239 (reg:GPR RETURN_ADDR_REGNUM))]
4242 [(set_attr "move_type" "store")
4243 (set_attr "mode" "<MODE>")])
4245 (define_insn "*movdi_32bit"
4246 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
4247 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
4248 "!TARGET_64BIT && !TARGET_MIPS16
4249 && (register_operand (operands[0], DImode)
4250 || reg_or_0_operand (operands[1], DImode))"
4251 { return mips_output_move (operands[0], operands[1]); }
4252 [(set_attr "move_type" "move,const,load,store,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
4253 (set_attr "mode" "DI")])
4255 (define_insn "*movdi_32bit_mips16"
4256 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4257 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
4258 "!TARGET_64BIT && TARGET_MIPS16
4259 && (register_operand (operands[0], DImode)
4260 || register_operand (operands[1], DImode))"
4261 { return mips_output_move (operands[0], operands[1]); }
4262 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4263 (set_attr "mode" "DI")])
4265 (define_insn "*movdi_64bit"
4266 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
4267 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4268 "TARGET_64BIT && !TARGET_MIPS16
4269 && (register_operand (operands[0], DImode)
4270 || reg_or_0_operand (operands[1], DImode))"
4271 { return mips_output_move (operands[0], operands[1]); }
4272 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore")
4273 (set_attr "mode" "DI")])
4275 (define_insn "*movdi_64bit_mips16"
4276 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4277 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4278 "TARGET_64BIT && TARGET_MIPS16
4279 && (register_operand (operands[0], DImode)
4280 || register_operand (operands[1], DImode))"
4281 { return mips_output_move (operands[0], operands[1]); }
4282 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4283 (set_attr "mode" "DI")])
4285 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4286 ;; when the original load is a 4 byte instruction but the add and the
4287 ;; load are 2 2 byte instructions.
4290 [(set (match_operand:DI 0 "d_operand")
4291 (mem:DI (plus:DI (match_dup 0)
4292 (match_operand:DI 1 "const_int_operand"))))]
4293 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4294 && !TARGET_DEBUG_D_MODE
4295 && ((INTVAL (operands[1]) < 0
4296 && INTVAL (operands[1]) >= -0x10)
4297 || (INTVAL (operands[1]) >= 32 * 8
4298 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4299 || (INTVAL (operands[1]) >= 0
4300 && INTVAL (operands[1]) < 32 * 8
4301 && (INTVAL (operands[1]) & 7) != 0))"
4302 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4303 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4305 HOST_WIDE_INT val = INTVAL (operands[1]);
4308 operands[2] = const0_rtx;
4309 else if (val >= 32 * 8)
4313 operands[1] = GEN_INT (0x8 + off);
4314 operands[2] = GEN_INT (val - off - 0x8);
4320 operands[1] = GEN_INT (off);
4321 operands[2] = GEN_INT (val - off);
4325 ;; 32-bit Integer moves
4327 ;; Unlike most other insns, the move insns can't be split with
4328 ;; different predicates, because register spilling and other parts of
4329 ;; the compiler, have memoized the insn number already.
4331 (define_expand "mov<mode>"
4332 [(set (match_operand:IMOVE32 0 "")
4333 (match_operand:IMOVE32 1 ""))]
4336 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4340 ;; The difference between these two is whether or not ints are allowed
4341 ;; in FP registers (off by default, use -mdebugh to enable).
4343 (define_insn "*mov<mode>_internal"
4344 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4345 (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4347 && (register_operand (operands[0], <MODE>mode)
4348 || reg_or_0_operand (operands[1], <MODE>mode))"
4349 { return mips_output_move (operands[0], operands[1]); }
4350 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore")
4351 (set_attr "mode" "SI")])
4353 (define_insn "*mov<mode>_mips16"
4354 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4355 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))]
4357 && (register_operand (operands[0], <MODE>mode)
4358 || register_operand (operands[1], <MODE>mode))"
4359 { return mips_output_move (operands[0], operands[1]); }
4360 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4361 (set_attr "mode" "SI")])
4363 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4364 ;; when the original load is a 4 byte instruction but the add and the
4365 ;; load are 2 2 byte instructions.
4368 [(set (match_operand:SI 0 "d_operand")
4369 (mem:SI (plus:SI (match_dup 0)
4370 (match_operand:SI 1 "const_int_operand"))))]
4371 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4372 && ((INTVAL (operands[1]) < 0
4373 && INTVAL (operands[1]) >= -0x80)
4374 || (INTVAL (operands[1]) >= 32 * 4
4375 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4376 || (INTVAL (operands[1]) >= 0
4377 && INTVAL (operands[1]) < 32 * 4
4378 && (INTVAL (operands[1]) & 3) != 0))"
4379 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4380 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4382 HOST_WIDE_INT val = INTVAL (operands[1]);
4385 operands[2] = const0_rtx;
4386 else if (val >= 32 * 4)
4390 operands[1] = GEN_INT (0x7c + off);
4391 operands[2] = GEN_INT (val - off - 0x7c);
4397 operands[1] = GEN_INT (off);
4398 operands[2] = GEN_INT (val - off);
4402 ;; On the mips16, we can split a load of certain constants into a load
4403 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4407 [(set (match_operand:SI 0 "d_operand")
4408 (match_operand:SI 1 "const_int_operand"))]
4409 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4410 && INTVAL (operands[1]) >= 0x100
4411 && INTVAL (operands[1]) <= 0xff + 0x7f"
4412 [(set (match_dup 0) (match_dup 1))
4413 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4415 int val = INTVAL (operands[1]);
4417 operands[1] = GEN_INT (0xff);
4418 operands[2] = GEN_INT (val - 0xff);
4421 ;; MIPS4 supports loading and storing a floating point register from
4422 ;; the sum of two general registers. We use two versions for each of
4423 ;; these four instructions: one where the two general registers are
4424 ;; SImode, and one where they are DImode. This is because general
4425 ;; registers will be in SImode when they hold 32-bit values, but,
4426 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4427 ;; instructions will still work correctly.
4429 ;; ??? Perhaps it would be better to support these instructions by
4430 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4431 ;; these instructions can only be used to load and store floating
4432 ;; point registers, that would probably cause trouble in reload.
4434 (define_insn "*<ANYF:loadx>_<P:mode>"
4435 [(set (match_operand:ANYF 0 "register_operand" "=f")
4436 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4437 (match_operand:P 2 "register_operand" "d"))))]
4439 "<ANYF:loadx>\t%0,%1(%2)"
4440 [(set_attr "type" "fpidxload")
4441 (set_attr "mode" "<ANYF:UNITMODE>")])
4443 (define_insn "*<ANYF:storex>_<P:mode>"
4444 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4445 (match_operand:P 2 "register_operand" "d")))
4446 (match_operand:ANYF 0 "register_operand" "f"))]
4448 "<ANYF:storex>\t%0,%1(%2)"
4449 [(set_attr "type" "fpidxstore")
4450 (set_attr "mode" "<ANYF:UNITMODE>")])
4452 ;; Scaled indexed address load.
4453 ;; Per md.texi, we only need to look for a pattern with multiply in the
4454 ;; address expression, not shift.
4456 (define_insn "*lwxs"
4457 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4459 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4461 (match_operand:P 2 "register_operand" "d"))))]
4464 [(set_attr "type" "load")
4465 (set_attr "mode" "SI")])
4467 ;; 16-bit Integer moves
4469 ;; Unlike most other insns, the move insns can't be split with
4470 ;; different predicates, because register spilling and other parts of
4471 ;; the compiler, have memoized the insn number already.
4472 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4474 (define_expand "movhi"
4475 [(set (match_operand:HI 0 "")
4476 (match_operand:HI 1 ""))]
4479 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4483 (define_insn "*movhi_internal"
4484 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4485 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4487 && (register_operand (operands[0], HImode)
4488 || reg_or_0_operand (operands[1], HImode))"
4489 { return mips_output_move (operands[0], operands[1]); }
4490 [(set_attr "move_type" "move,const,load,store,mtlo,mflo")
4491 (set_attr "mode" "HI")])
4493 (define_insn "*movhi_mips16"
4494 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4495 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4497 && (register_operand (operands[0], HImode)
4498 || register_operand (operands[1], HImode))"
4499 { return mips_output_move (operands[0], operands[1]); }
4500 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4501 (set_attr "mode" "HI")])
4503 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4504 ;; when the original load is a 4 byte instruction but the add and the
4505 ;; load are 2 2 byte instructions.
4508 [(set (match_operand:HI 0 "d_operand")
4509 (mem:HI (plus:SI (match_dup 0)
4510 (match_operand:SI 1 "const_int_operand"))))]
4511 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4512 && ((INTVAL (operands[1]) < 0
4513 && INTVAL (operands[1]) >= -0x80)
4514 || (INTVAL (operands[1]) >= 32 * 2
4515 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4516 || (INTVAL (operands[1]) >= 0
4517 && INTVAL (operands[1]) < 32 * 2
4518 && (INTVAL (operands[1]) & 1) != 0))"
4519 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4520 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4522 HOST_WIDE_INT val = INTVAL (operands[1]);
4525 operands[2] = const0_rtx;
4526 else if (val >= 32 * 2)
4530 operands[1] = GEN_INT (0x7e + off);
4531 operands[2] = GEN_INT (val - off - 0x7e);
4537 operands[1] = GEN_INT (off);
4538 operands[2] = GEN_INT (val - off);
4542 ;; 8-bit Integer moves
4544 ;; Unlike most other insns, the move insns can't be split with
4545 ;; different predicates, because register spilling and other parts of
4546 ;; the compiler, have memoized the insn number already.
4547 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4549 (define_expand "movqi"
4550 [(set (match_operand:QI 0 "")
4551 (match_operand:QI 1 ""))]
4554 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4558 (define_insn "*movqi_internal"
4559 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4560 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*d*J,*a"))]
4562 && (register_operand (operands[0], QImode)
4563 || reg_or_0_operand (operands[1], QImode))"
4564 { return mips_output_move (operands[0], operands[1]); }
4565 [(set_attr "move_type" "move,const,load,store,mtlo,mflo")
4566 (set_attr "mode" "QI")])
4568 (define_insn "*movqi_mips16"
4569 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4570 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4572 && (register_operand (operands[0], QImode)
4573 || register_operand (operands[1], QImode))"
4574 { return mips_output_move (operands[0], operands[1]); }
4575 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4576 (set_attr "mode" "QI")])
4578 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4579 ;; when the original load is a 4 byte instruction but the add and the
4580 ;; load are 2 2 byte instructions.
4583 [(set (match_operand:QI 0 "d_operand")
4584 (mem:QI (plus:SI (match_dup 0)
4585 (match_operand:SI 1 "const_int_operand"))))]
4586 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4587 && ((INTVAL (operands[1]) < 0
4588 && INTVAL (operands[1]) >= -0x80)
4589 || (INTVAL (operands[1]) >= 32
4590 && INTVAL (operands[1]) <= 31 + 0x7f))"
4591 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4592 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4594 HOST_WIDE_INT val = INTVAL (operands[1]);
4597 operands[2] = const0_rtx;
4600 operands[1] = GEN_INT (0x7f);
4601 operands[2] = GEN_INT (val - 0x7f);
4605 ;; 32-bit floating point moves
4607 (define_expand "movsf"
4608 [(set (match_operand:SF 0 "")
4609 (match_operand:SF 1 ""))]
4612 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4616 (define_insn "*movsf_hardfloat"
4617 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4618 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4620 && (register_operand (operands[0], SFmode)
4621 || reg_or_0_operand (operands[1], SFmode))"
4622 { return mips_output_move (operands[0], operands[1]); }
4623 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4624 (set_attr "mode" "SF")])
4626 (define_insn "*movsf_softfloat"
4627 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4628 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4629 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4630 && (register_operand (operands[0], SFmode)
4631 || reg_or_0_operand (operands[1], SFmode))"
4632 { return mips_output_move (operands[0], operands[1]); }
4633 [(set_attr "move_type" "move,load,store")
4634 (set_attr "mode" "SF")])
4636 (define_insn "*movsf_mips16"
4637 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4638 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4640 && (register_operand (operands[0], SFmode)
4641 || register_operand (operands[1], SFmode))"
4642 { return mips_output_move (operands[0], operands[1]); }
4643 [(set_attr "move_type" "move,move,move,load,store")
4644 (set_attr "mode" "SF")])
4646 ;; 64-bit floating point moves
4648 (define_expand "movdf"
4649 [(set (match_operand:DF 0 "")
4650 (match_operand:DF 1 ""))]
4653 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4657 (define_insn "*movdf_hardfloat"
4658 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4659 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4660 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4661 && (register_operand (operands[0], DFmode)
4662 || reg_or_0_operand (operands[1], DFmode))"
4663 { return mips_output_move (operands[0], operands[1]); }
4664 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4665 (set_attr "mode" "DF")])
4667 (define_insn "*movdf_softfloat"
4668 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4669 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4670 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4671 && (register_operand (operands[0], DFmode)
4672 || reg_or_0_operand (operands[1], DFmode))"
4673 { return mips_output_move (operands[0], operands[1]); }
4674 [(set_attr "move_type" "move,load,store")
4675 (set_attr "mode" "DF")])
4677 (define_insn "*movdf_mips16"
4678 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4679 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4681 && (register_operand (operands[0], DFmode)
4682 || register_operand (operands[1], DFmode))"
4683 { return mips_output_move (operands[0], operands[1]); }
4684 [(set_attr "move_type" "move,move,move,load,store")
4685 (set_attr "mode" "DF")])
4687 ;; 128-bit integer moves
4689 (define_expand "movti"
4690 [(set (match_operand:TI 0)
4691 (match_operand:TI 1))]
4694 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4698 (define_insn "*movti"
4699 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d")
4700 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*d*J,*a"))]
4703 && (register_operand (operands[0], TImode)
4704 || reg_or_0_operand (operands[1], TImode))"
4706 [(set_attr "move_type" "move,const,load,store,mtlo,mflo")
4707 (set_attr "mode" "TI")])
4709 (define_insn "*movti_mips16"
4710 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4711 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4714 && (register_operand (operands[0], TImode)
4715 || register_operand (operands[1], TImode))"
4717 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4718 (set_attr "mode" "TI")])
4720 ;; 128-bit floating point moves
4722 (define_expand "movtf"
4723 [(set (match_operand:TF 0)
4724 (match_operand:TF 1))]
4727 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4731 ;; This pattern handles both hard- and soft-float cases.
4732 (define_insn "*movtf"
4733 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4734 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4737 && (register_operand (operands[0], TFmode)
4738 || reg_or_0_operand (operands[1], TFmode))"
4740 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4741 (set_attr "mode" "TF")])
4743 (define_insn "*movtf_mips16"
4744 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4745 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4748 && (register_operand (operands[0], TFmode)
4749 || register_operand (operands[1], TFmode))"
4751 [(set_attr "move_type" "move,move,move,load,store")
4752 (set_attr "mode" "TF")])
4755 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4756 (match_operand:MOVE64 1 "move_operand"))]
4757 "reload_completed && !TARGET_64BIT
4758 && mips_split_64bit_move_p (operands[0], operands[1])"
4761 mips_split_doubleword_move (operands[0], operands[1]);
4766 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4767 (match_operand:MOVE128 1 "move_operand"))]
4768 "TARGET_64BIT && reload_completed"
4771 mips_split_doubleword_move (operands[0], operands[1]);
4775 ;; When generating mips16 code, split moves of negative constants into
4776 ;; a positive "li" followed by a negation.
4778 [(set (match_operand 0 "d_operand")
4779 (match_operand 1 "const_int_operand"))]
4780 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4784 (neg:SI (match_dup 2)))]
4786 operands[2] = gen_lowpart (SImode, operands[0]);
4787 operands[3] = GEN_INT (-INTVAL (operands[1]));
4790 ;; 64-bit paired-single floating point moves
4792 (define_expand "movv2sf"
4793 [(set (match_operand:V2SF 0)
4794 (match_operand:V2SF 1))]
4795 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4797 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4801 (define_insn "*movv2sf"
4802 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4803 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4805 && TARGET_PAIRED_SINGLE_FLOAT
4806 && (register_operand (operands[0], V2SFmode)
4807 || reg_or_0_operand (operands[1], V2SFmode))"
4808 { return mips_output_move (operands[0], operands[1]); }
4809 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4810 (set_attr "mode" "DF")])
4812 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4813 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4815 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4816 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4817 ;; and the errata related to -mfix-vr4130.
4818 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4819 [(set (match_operand:GPR 0 "register_operand" "=d")
4820 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")]
4823 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4824 [(set_attr "type" "mfhi")
4825 (set_attr "mode" "<GPR:MODE>")])
4827 ;; Set the high part of a HI/LO value, given that the low part has
4828 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4829 ;; why we can't just use (reg:GPR HI_REGNUM).
4830 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4831 [(set (match_operand:HILO 0 "register_operand" "=x")
4832 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4833 (match_operand:GPR 2 "register_operand" "l")]
4837 [(set_attr "type" "mthi")
4838 (set_attr "mode" "SI")])
4840 ;; Emit a doubleword move in which exactly one of the operands is
4841 ;; a floating-point register. We can't just emit two normal moves
4842 ;; because of the constraints imposed by the FPU register model;
4843 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4844 ;; the FPR whole and use special patterns to refer to each word of
4845 ;; the other operand.
4847 (define_expand "move_doubleword_fpr<mode>"
4848 [(set (match_operand:SPLITF 0)
4849 (match_operand:SPLITF 1))]
4852 if (FP_REG_RTX_P (operands[0]))
4854 rtx low = mips_subword (operands[1], 0);
4855 rtx high = mips_subword (operands[1], 1);
4856 emit_insn (gen_load_low<mode> (operands[0], low));
4857 if (TARGET_FLOAT64 && !TARGET_64BIT)
4858 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4860 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4864 rtx low = mips_subword (operands[0], 0);
4865 rtx high = mips_subword (operands[0], 1);
4866 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4867 if (TARGET_FLOAT64 && !TARGET_64BIT)
4868 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4870 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4875 ;; Load the low word of operand 0 with operand 1.
4876 (define_insn "load_low<mode>"
4877 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4878 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4882 operands[0] = mips_subword (operands[0], 0);
4883 return mips_output_move (operands[0], operands[1]);
4885 [(set_attr "move_type" "mtc,fpload")
4886 (set_attr "mode" "<HALFMODE>")])
4888 ;; Load the high word of operand 0 from operand 1, preserving the value
4890 (define_insn "load_high<mode>"
4891 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4892 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4893 (match_operand:SPLITF 2 "register_operand" "0,0")]
4897 operands[0] = mips_subword (operands[0], 1);
4898 return mips_output_move (operands[0], operands[1]);
4900 [(set_attr "move_type" "mtc,fpload")
4901 (set_attr "mode" "<HALFMODE>")])
4903 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4904 ;; high word and 0 to store the low word.
4905 (define_insn "store_word<mode>"
4906 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4907 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4908 (match_operand 2 "const_int_operand")]
4909 UNSPEC_STORE_WORD))]
4912 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4913 return mips_output_move (operands[0], operands[1]);
4915 [(set_attr "move_type" "mfc,fpstore")
4916 (set_attr "mode" "<HALFMODE>")])
4918 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4919 ;; value in the low word.
4920 (define_insn "mthc1<mode>"
4921 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4922 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4923 (match_operand:SPLITF 2 "register_operand" "0")]
4925 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4927 [(set_attr "move_type" "mtc")
4928 (set_attr "mode" "<HALFMODE>")])
4930 ;; Move high word of operand 1 to operand 0 using mfhc1.
4931 (define_insn "mfhc1<mode>"
4932 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4933 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4935 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4937 [(set_attr "move_type" "mfc")
4938 (set_attr "mode" "<HALFMODE>")])
4940 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4941 (define_expand "load_const_gp_<mode>"
4942 [(set (match_operand:P 0 "register_operand" "=d")
4943 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4945 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4946 ;; of _gp from the start of this function. Operand 1 is the incoming
4947 ;; function address.
4948 (define_insn_and_split "loadgp_newabi_<mode>"
4949 [(set (match_operand:P 0 "register_operand" "=&d")
4950 (unspec:P [(match_operand:P 1)
4951 (match_operand:P 2 "register_operand" "d")]
4953 "mips_current_loadgp_style () == LOADGP_NEWABI"
4954 { return mips_must_initialize_gp_p () ? "#" : ""; }
4955 "&& mips_must_initialize_gp_p ()"
4956 [(set (match_dup 0) (match_dup 3))
4957 (set (match_dup 0) (match_dup 4))
4958 (set (match_dup 0) (match_dup 5))]
4960 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4961 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4962 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4964 [(set_attr "type" "ghost")])
4966 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4967 (define_insn_and_split "loadgp_absolute_<mode>"
4968 [(set (match_operand:P 0 "register_operand" "=d")
4969 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4970 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4971 { return mips_must_initialize_gp_p () ? "#" : ""; }
4972 "&& mips_must_initialize_gp_p ()"
4975 mips_emit_move (operands[0], operands[1]);
4978 [(set_attr "type" "ghost")])
4980 ;; This blockage instruction prevents the gp load from being
4981 ;; scheduled after an implicit use of gp. It also prevents
4982 ;; the load from being deleted as dead.
4983 (define_insn "loadgp_blockage"
4984 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4987 [(set_attr "type" "ghost")])
4989 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4990 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4991 (define_insn_and_split "loadgp_rtp_<mode>"
4992 [(set (match_operand:P 0 "register_operand" "=d")
4993 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
4994 (match_operand:P 2 "symbol_ref_operand")]
4996 "mips_current_loadgp_style () == LOADGP_RTP"
4997 { return mips_must_initialize_gp_p () ? "#" : ""; }
4998 "&& mips_must_initialize_gp_p ()"
4999 [(set (match_dup 0) (high:P (match_dup 3)))
5000 (set (match_dup 0) (unspec:P [(match_dup 0)
5001 (match_dup 3)] UNSPEC_LOAD_GOT))
5002 (set (match_dup 0) (unspec:P [(match_dup 0)
5003 (match_dup 4)] UNSPEC_LOAD_GOT))]
5005 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
5006 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
5008 [(set_attr "type" "ghost")])
5010 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
5011 ;; global pointer and operand 1 is the MIPS16 register that holds
5012 ;; the required value.
5013 (define_insn_and_split "copygp_mips16_<mode>"
5014 [(set (match_operand:P 0 "register_operand" "=y")
5015 (unspec:P [(match_operand:P 1 "register_operand" "d")]
5018 { return mips_must_initialize_gp_p () ? "#" : ""; }
5019 "&& mips_must_initialize_gp_p ()"
5020 [(set (match_dup 0) (match_dup 1))]
5022 [(set_attr "type" "ghost")])
5024 ;; A placeholder for where the cprestore instruction should go,
5025 ;; if we decide we need one. Operand 0 and operand 1 are as for
5026 ;; "cprestore". Operand 2 is a register that holds the gp value.
5028 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
5029 ;; otherwise any register that holds the correct value will do.
5030 (define_insn_and_split "potential_cprestore_<mode>"
5031 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5032 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5033 (match_operand:P 2 "register_operand" "d,d")]
5034 UNSPEC_POTENTIAL_CPRESTORE))
5035 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))]
5036 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
5037 { return mips_must_initialize_gp_p () ? "#" : ""; }
5038 "mips_must_initialize_gp_p ()"
5041 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
5042 operands[2], operands[3]);
5045 [(set_attr "type" "ghost")])
5047 ;; Emit a .cprestore directive, which normally expands to a single store
5048 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
5049 ;; for the cprestore slot. Operand 1 is the offset of the slot from
5050 ;; the stack pointer. (This is redundant with operand 0, but it makes
5051 ;; things a little simpler.)
5052 (define_insn "cprestore_<mode>"
5053 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5054 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5057 "TARGET_CPRESTORE_DIRECTIVE"
5059 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
5060 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
5062 return ".cprestore\t%1";
5064 [(set_attr "type" "store")
5065 (set_attr "length" "4,12")])
5067 (define_insn "use_cprestore_<mode>"
5068 [(set (reg:P CPRESTORE_SLOT_REGNUM)
5069 (match_operand:P 0 "cprestore_load_slot_operand"))]
5072 [(set_attr "type" "ghost")])
5074 ;; Expand in-line code to clear the instruction cache between operand[0] and
5076 (define_expand "clear_cache"
5077 [(match_operand 0 "pmode_register_operand")
5078 (match_operand 1 "pmode_register_operand")]
5084 mips_expand_synci_loop (operands[0], operands[1]);
5085 emit_insn (gen_sync ());
5086 emit_insn (PMODE_INSN (gen_clear_hazard, ()));
5088 else if (mips_cache_flush_func && mips_cache_flush_func[0])
5090 rtx len = gen_reg_rtx (Pmode);
5091 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
5092 MIPS_ICACHE_SYNC (operands[0], len);
5098 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
5100 { return mips_output_sync (); })
5102 (define_insn "synci"
5103 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
5108 (define_insn "rdhwr_synci_step_<mode>"
5109 [(set (match_operand:P 0 "register_operand" "=d")
5110 (unspec_volatile [(const_int 1)]
5115 (define_insn "clear_hazard_<mode>"
5116 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
5117 (clobber (reg:P RETURN_ADDR_REGNUM))]
5120 return "%(%<bal\t1f\n"
5122 "1:\t<d>addiu\t$31,$31,12\n"
5126 [(set_attr "length" "20")])
5128 ;; Cache operations for R4000-style caches.
5129 (define_insn "mips_cache"
5130 [(set (mem:BLK (scratch))
5131 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
5132 (match_operand:QI 1 "address_operand" "p")]
5133 UNSPEC_MIPS_CACHE))]
5137 ;; Similar, but with the operands hard-coded to an R10K cache barrier
5138 ;; operation. We keep the pattern distinct so that we can identify
5139 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
5140 ;; the operation is never inserted into a delay slot.
5141 (define_insn "r10k_cache_barrier"
5142 [(set (mem:BLK (scratch))
5143 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
5146 [(set_attr "can_delay" "no")])
5148 ;; Block moves, see mips.c for more details.
5149 ;; Argument 0 is the destination
5150 ;; Argument 1 is the source
5151 ;; Argument 2 is the length
5152 ;; Argument 3 is the alignment
5154 (define_expand "movmemsi"
5155 [(parallel [(set (match_operand:BLK 0 "general_operand")
5156 (match_operand:BLK 1 "general_operand"))
5157 (use (match_operand:SI 2 ""))
5158 (use (match_operand:SI 3 "const_int_operand"))])]
5159 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5161 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5168 ;; ....................
5172 ;; ....................
5174 (define_expand "<optab><mode>3"
5175 [(set (match_operand:GPR 0 "register_operand")
5176 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5177 (match_operand:SI 2 "arith_operand")))]
5180 /* On the mips16, a shift of more than 8 is a four byte instruction,
5181 so, for a shift between 8 and 16, it is just as fast to do two
5182 shifts of 8 or less. If there is a lot of shifting going on, we
5183 may win in CSE. Otherwise combine will put the shifts back
5184 together again. This can be called by mips_function_arg, so we must
5185 be careful not to allocate a new register if we've reached the
5189 && CONST_INT_P (operands[2])
5190 && INTVAL (operands[2]) > 8
5191 && INTVAL (operands[2]) <= 16
5192 && !reload_in_progress
5193 && !reload_completed)
5195 rtx temp = gen_reg_rtx (<MODE>mode);
5197 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5198 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5199 GEN_INT (INTVAL (operands[2]) - 8)));
5204 (define_insn "*<optab><mode>3"
5205 [(set (match_operand:GPR 0 "register_operand" "=d")
5206 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
5207 (match_operand:SI 2 "arith_operand" "dI")))]
5210 if (CONST_INT_P (operands[2]))
5211 operands[2] = GEN_INT (INTVAL (operands[2])
5212 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5214 return "<d><insn>\t%0,%1,%2";
5216 [(set_attr "type" "shift")
5217 (set_attr "mode" "<MODE>")])
5219 (define_insn "*<optab>si3_extend"
5220 [(set (match_operand:DI 0 "register_operand" "=d")
5222 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5223 (match_operand:SI 2 "arith_operand" "dI"))))]
5224 "TARGET_64BIT && !TARGET_MIPS16"
5226 if (CONST_INT_P (operands[2]))
5227 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5229 return "<insn>\t%0,%1,%2";
5231 [(set_attr "type" "shift")
5232 (set_attr "mode" "SI")])
5234 (define_insn "*<optab>si3_mips16"
5235 [(set (match_operand:SI 0 "register_operand" "=d,d")
5236 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
5237 (match_operand:SI 2 "arith_operand" "d,I")))]
5240 if (which_alternative == 0)
5241 return "<insn>\t%0,%2";
5243 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5244 return "<insn>\t%0,%1,%2";
5246 [(set_attr "type" "shift")
5247 (set_attr "mode" "SI")
5248 (set_attr_alternative "length"
5250 (if_then_else (match_operand 2 "m16_uimm3_b")
5254 ;; We need separate DImode MIPS16 patterns because of the irregularity
5256 (define_insn "*ashldi3_mips16"
5257 [(set (match_operand:DI 0 "register_operand" "=d,d")
5258 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
5259 (match_operand:SI 2 "arith_operand" "d,I")))]
5260 "TARGET_64BIT && TARGET_MIPS16"
5262 if (which_alternative == 0)
5263 return "dsll\t%0,%2";
5265 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5266 return "dsll\t%0,%1,%2";
5268 [(set_attr "type" "shift")
5269 (set_attr "mode" "DI")
5270 (set_attr_alternative "length"
5272 (if_then_else (match_operand 2 "m16_uimm3_b")
5276 (define_insn "*ashrdi3_mips16"
5277 [(set (match_operand:DI 0 "register_operand" "=d,d")
5278 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5279 (match_operand:SI 2 "arith_operand" "d,I")))]
5280 "TARGET_64BIT && TARGET_MIPS16"
5282 if (CONST_INT_P (operands[2]))
5283 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5285 return "dsra\t%0,%2";
5287 [(set_attr "type" "shift")
5288 (set_attr "mode" "DI")
5289 (set_attr_alternative "length"
5291 (if_then_else (match_operand 2 "m16_uimm3_b")
5295 (define_insn "*lshrdi3_mips16"
5296 [(set (match_operand:DI 0 "register_operand" "=d,d")
5297 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
5298 (match_operand:SI 2 "arith_operand" "d,I")))]
5299 "TARGET_64BIT && TARGET_MIPS16"
5301 if (CONST_INT_P (operands[2]))
5302 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5304 return "dsrl\t%0,%2";
5306 [(set_attr "type" "shift")
5307 (set_attr "mode" "DI")
5308 (set_attr_alternative "length"
5310 (if_then_else (match_operand 2 "m16_uimm3_b")
5314 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5317 [(set (match_operand:GPR 0 "d_operand")
5318 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5319 (match_operand:GPR 2 "const_int_operand")))]
5320 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5321 && INTVAL (operands[2]) > 8
5322 && INTVAL (operands[2]) <= 16"
5323 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5324 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5325 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5327 ;; If we load a byte on the mips16 as a bitfield, the resulting
5328 ;; sequence of instructions is too complicated for combine, because it
5329 ;; involves four instructions: a load, a shift, a constant load into a
5330 ;; register, and an and (the key problem here is that the mips16 does
5331 ;; not have and immediate). We recognize a shift of a load in order
5332 ;; to make it simple enough for combine to understand.
5334 ;; The length here is the worst case: the length of the split version
5335 ;; will be more accurate.
5336 (define_insn_and_split ""
5337 [(set (match_operand:SI 0 "register_operand" "=d")
5338 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5339 (match_operand:SI 2 "immediate_operand" "I")))]
5343 [(set (match_dup 0) (match_dup 1))
5344 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5346 [(set_attr "type" "load")
5347 (set_attr "mode" "SI")
5348 (set_attr "length" "16")])
5350 (define_insn "rotr<mode>3"
5351 [(set (match_operand:GPR 0 "register_operand" "=d")
5352 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5353 (match_operand:SI 2 "arith_operand" "dI")))]
5356 if (CONST_INT_P (operands[2]))
5357 gcc_assert (INTVAL (operands[2]) >= 0
5358 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5360 return "<d>ror\t%0,%1,%2";
5362 [(set_attr "type" "shift")
5363 (set_attr "mode" "<MODE>")])
5366 ;; ....................
5368 ;; CONDITIONAL BRANCHES
5370 ;; ....................
5372 ;; Conditional branches on floating-point equality tests.
5374 (define_insn "*branch_fp"
5377 (match_operator 1 "equality_operator"
5378 [(match_operand:CC 2 "register_operand" "z")
5380 (label_ref (match_operand 0 "" ""))
5384 return mips_output_conditional_branch (insn, operands,
5385 MIPS_BRANCH ("b%F1", "%Z2%0"),
5386 MIPS_BRANCH ("b%W1", "%Z2%0"));
5388 [(set_attr "type" "branch")])
5390 (define_insn "*branch_fp_inverted"
5393 (match_operator 1 "equality_operator"
5394 [(match_operand:CC 2 "register_operand" "z")
5397 (label_ref (match_operand 0 "" ""))))]
5400 return mips_output_conditional_branch (insn, operands,
5401 MIPS_BRANCH ("b%W1", "%Z2%0"),
5402 MIPS_BRANCH ("b%F1", "%Z2%0"));
5404 [(set_attr "type" "branch")])
5406 ;; Conditional branches on ordered comparisons with zero.
5408 (define_insn "*branch_order<mode>"
5411 (match_operator 1 "order_operator"
5412 [(match_operand:GPR 2 "register_operand" "d")
5414 (label_ref (match_operand 0 "" ""))
5417 { return mips_output_order_conditional_branch (insn, operands, false); }
5418 [(set_attr "type" "branch")])
5420 (define_insn "*branch_order<mode>_inverted"
5423 (match_operator 1 "order_operator"
5424 [(match_operand:GPR 2 "register_operand" "d")
5427 (label_ref (match_operand 0 "" ""))))]
5429 { return mips_output_order_conditional_branch (insn, operands, true); }
5430 [(set_attr "type" "branch")])
5432 ;; Conditional branch on equality comparison.
5434 (define_insn "*branch_equality<mode>"
5437 (match_operator 1 "equality_operator"
5438 [(match_operand:GPR 2 "register_operand" "d")
5439 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5440 (label_ref (match_operand 0 "" ""))
5444 return mips_output_conditional_branch (insn, operands,
5445 MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
5446 MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
5448 [(set_attr "type" "branch")])
5450 (define_insn "*branch_equality<mode>_inverted"
5453 (match_operator 1 "equality_operator"
5454 [(match_operand:GPR 2 "register_operand" "d")
5455 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5457 (label_ref (match_operand 0 "" ""))))]
5460 return mips_output_conditional_branch (insn, operands,
5461 MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
5462 MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
5464 [(set_attr "type" "branch")])
5468 (define_insn "*branch_equality<mode>_mips16"
5471 (match_operator 1 "equality_operator"
5472 [(match_operand:GPR 2 "register_operand" "d,t")
5474 (label_ref (match_operand 0 "" ""))
5480 [(set_attr "type" "branch")])
5482 (define_insn "*branch_equality<mode>_mips16_inverted"
5485 (match_operator 1 "equality_operator"
5486 [(match_operand:GPR 2 "register_operand" "d,t")
5489 (label_ref (match_operand 0 "" ""))))]
5494 [(set_attr "type" "branch")])
5496 (define_expand "cbranch<mode>4"
5498 (if_then_else (match_operator 0 "comparison_operator"
5499 [(match_operand:GPR 1 "register_operand")
5500 (match_operand:GPR 2 "nonmemory_operand")])
5501 (label_ref (match_operand 3 ""))
5505 mips_expand_conditional_branch (operands);
5509 (define_expand "cbranch<mode>4"
5511 (if_then_else (match_operator 0 "comparison_operator"
5512 [(match_operand:SCALARF 1 "register_operand")
5513 (match_operand:SCALARF 2 "register_operand")])
5514 (label_ref (match_operand 3 ""))
5518 mips_expand_conditional_branch (operands);
5522 ;; Used to implement built-in functions.
5523 (define_expand "condjump"
5525 (if_then_else (match_operand 0)
5526 (label_ref (match_operand 1))
5529 ;; Branch if bit is set/clear.
5531 (define_insn "*branch_bit<bbv><mode>"
5534 (equality_op (zero_extract:GPR
5535 (match_operand:GPR 1 "register_operand" "d")
5537 (match_operand 2 "const_int_operand" ""))
5539 (label_ref (match_operand 0 ""))
5541 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5544 mips_output_conditional_branch (insn, operands,
5545 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5546 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5548 [(set_attr "type" "branch")
5549 (set_attr "branch_likely" "no")])
5551 (define_insn "*branch_bit<bbv><mode>_inverted"
5554 (equality_op (zero_extract:GPR
5555 (match_operand:GPR 1 "register_operand" "d")
5557 (match_operand 2 "const_int_operand" ""))
5560 (label_ref (match_operand 0 ""))))]
5561 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5564 mips_output_conditional_branch (insn, operands,
5565 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5566 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5568 [(set_attr "type" "branch")
5569 (set_attr "branch_likely" "no")])
5572 ;; ....................
5574 ;; SETTING A REGISTER FROM A COMPARISON
5576 ;; ....................
5578 ;; Destination is always set in SI mode.
5580 (define_expand "cstore<mode>4"
5581 [(set (match_operand:SI 0 "register_operand")
5582 (match_operator:SI 1 "mips_cstore_operator"
5583 [(match_operand:GPR 2 "register_operand")
5584 (match_operand:GPR 3 "nonmemory_operand")]))]
5587 mips_expand_scc (operands);
5591 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5592 [(set (match_operand:GPR2 0 "register_operand" "=d")
5593 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5595 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5597 [(set_attr "type" "slt")
5598 (set_attr "mode" "<GPR:MODE>")])
5600 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5601 [(set (match_operand:GPR2 0 "register_operand" "=t")
5602 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5604 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5606 [(set_attr "type" "slt")
5607 (set_attr "mode" "<GPR:MODE>")])
5609 ;; Generate sltiu unless using seq results in better code.
5610 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5611 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5612 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5613 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5619 [(set_attr "type" "slt")
5620 (set_attr "mode" "<GPR:MODE>")])
5622 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5623 [(set (match_operand:GPR2 0 "register_operand" "=d")
5624 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5626 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5628 [(set_attr "type" "slt")
5629 (set_attr "mode" "<GPR:MODE>")])
5631 ;; Generate sltu unless using sne results in better code.
5632 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5633 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5634 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5635 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5641 [(set_attr "type" "slt")
5642 (set_attr "mode" "<GPR:MODE>")])
5644 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5645 [(set (match_operand:GPR2 0 "register_operand" "=d")
5646 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5647 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5650 [(set_attr "type" "slt")
5651 (set_attr "mode" "<GPR:MODE>")])
5653 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5654 [(set (match_operand:GPR2 0 "register_operand" "=t")
5655 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5656 (match_operand:GPR 2 "register_operand" "d")))]
5659 [(set_attr "type" "slt")
5660 (set_attr "mode" "<GPR:MODE>")])
5662 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5663 [(set (match_operand:GPR2 0 "register_operand" "=d")
5664 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5668 [(set_attr "type" "slt")
5669 (set_attr "mode" "<GPR:MODE>")])
5671 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5672 [(set (match_operand:GPR2 0 "register_operand" "=d")
5673 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5674 (match_operand:GPR 2 "arith_operand" "dI")))]
5677 [(set_attr "type" "slt")
5678 (set_attr "mode" "<GPR:MODE>")])
5680 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5681 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5682 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5683 (match_operand:GPR 2 "arith_operand" "d,I")))]
5686 [(set_attr "type" "slt")
5687 (set_attr "mode" "<GPR:MODE>")
5688 (set_attr_alternative "length"
5690 (if_then_else (match_operand 2 "m16_uimm8_1")
5694 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5695 [(set (match_operand:GPR2 0 "register_operand" "=d")
5696 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5697 (match_operand:GPR 2 "sle_operand" "")))]
5700 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5701 return "slt<u>\t%0,%1,%2";
5703 [(set_attr "type" "slt")
5704 (set_attr "mode" "<GPR:MODE>")])
5706 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5707 [(set (match_operand:GPR2 0 "register_operand" "=t")
5708 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5709 (match_operand:GPR 2 "sle_operand" "")))]
5712 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5713 return "slt<u>\t%1,%2";
5715 [(set_attr "type" "slt")
5716 (set_attr "mode" "<GPR:MODE>")
5717 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
5722 ;; ....................
5724 ;; FLOATING POINT COMPARISONS
5726 ;; ....................
5728 (define_insn "s<code>_<mode>"
5729 [(set (match_operand:CC 0 "register_operand" "=z")
5730 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5731 (match_operand:SCALARF 2 "register_operand" "f")))]
5733 "c.<fcond>.<fmt>\t%Z0%1,%2"
5734 [(set_attr "type" "fcmp")
5735 (set_attr "mode" "FPSW")])
5737 (define_insn "s<code>_<mode>"
5738 [(set (match_operand:CC 0 "register_operand" "=z")
5739 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5740 (match_operand:SCALARF 2 "register_operand" "f")))]
5742 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5743 [(set_attr "type" "fcmp")
5744 (set_attr "mode" "FPSW")])
5747 ;; ....................
5749 ;; UNCONDITIONAL BRANCHES
5751 ;; ....................
5753 ;; Unconditional branches.
5755 (define_expand "jump"
5757 (label_ref (match_operand 0)))])
5759 (define_insn "*jump_absolute"
5761 (label_ref (match_operand 0)))]
5762 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
5763 { return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/"); }
5764 [(set_attr "type" "jump")])
5766 (define_insn "*jump_pic"
5768 (label_ref (match_operand 0)))]
5769 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
5771 if (get_attr_length (insn) <= 8)
5772 return "%*b\t%l0%/";
5775 mips_output_load_label (operands[0]);
5776 return "%*jr\t%@%/%]";
5779 [(set_attr "type" "branch")])
5781 ;; We need a different insn for the mips16, because a mips16 branch
5782 ;; does not have a delay slot.
5784 (define_insn "*jump_mips16"
5786 (label_ref (match_operand 0 "" "")))]
5789 [(set_attr "type" "branch")
5790 (set (attr "length")
5791 ;; This calculation is like the normal branch one, but the
5792 ;; range of the unextended instruction is [-0x800, 0x7fe] rather
5793 ;; than [-0x100, 0xfe]. This translates to a range of:
5795 ;; [-(0x800 - sizeof (branch)), 0x7fe]
5796 ;; == [-0x7fe, 0x7fe]
5798 ;; from the shorten_branches reference address. Long-branch
5799 ;; sequences will replace this one, so the minimum length
5800 ;; is one instruction shorter than for conditional branches.
5801 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
5802 (le (minus (pc) (match_dup 0)) (const_int 2046)))
5804 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
5805 (le (minus (pc) (match_dup 0)) (const_int 65532)))
5807 (and (match_test "TARGET_ABICALLS")
5808 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
5810 (match_test "Pmode == SImode")
5812 ] (const_int 44)))])
5814 (define_expand "indirect_jump"
5815 [(set (pc) (match_operand 0 "register_operand"))]
5818 operands[0] = force_reg (Pmode, operands[0]);
5819 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0])));
5823 (define_insn "indirect_jump_<mode>"
5824 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5827 [(set_attr "type" "jump")
5828 (set_attr "mode" "none")])
5830 ;; A combined jump-and-move instruction, used for MIPS16 long-branch
5831 ;; sequences. Having a dedicated pattern is more convenient than
5832 ;; creating a SEQUENCE for this special case.
5833 (define_insn "indirect_jump_and_restore_<mode>"
5834 [(set (pc) (match_operand:P 1 "register_operand" "d"))
5835 (set (match_operand:P 0 "register_operand" "=d")
5836 (match_operand:P 2 "register_operand" "y"))]
5838 "%(%<jr\t%1\;move\t%0,%2%>%)"
5839 [(set_attr "type" "multi")
5840 (set_attr "extended_mips16" "yes")])
5842 (define_expand "tablejump"
5844 (match_operand 0 "register_operand"))
5845 (use (label_ref (match_operand 1 "")))]
5846 "!TARGET_MIPS16_SHORT_JUMP_TABLES"
5849 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5850 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5851 else if (TARGET_RTP_PIC)
5853 /* When generating RTP PIC, we use case table entries that are relative
5854 to the start of the function. Add the function's address to the
5856 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5857 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5858 start, 0, 0, OPTAB_WIDEN);
5861 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1])));
5865 (define_insn "tablejump_<mode>"
5867 (match_operand:P 0 "register_operand" "d"))
5868 (use (label_ref (match_operand 1 "" "")))]
5871 [(set_attr "type" "jump")
5872 (set_attr "mode" "none")])
5874 ;; For MIPS16, we don't know whether a given jump table will use short or
5875 ;; word-sized offsets until late in compilation, when we are able to determine
5876 ;; the sizes of the insns which comprise the containing function. This
5877 ;; necessitates the use of the casesi rather than the tablejump pattern, since
5878 ;; the latter tries to calculate the index of the offset to jump through early
5879 ;; in compilation, i.e. at expand time, when nothing is known about the
5880 ;; eventual function layout.
5882 (define_expand "casesi"
5883 [(match_operand:SI 0 "register_operand" "") ; index to jump on
5884 (match_operand:SI 1 "const_int_operand" "") ; lower bound
5885 (match_operand:SI 2 "const_int_operand" "") ; total range
5886 (match_operand 3 "" "") ; table label
5887 (match_operand 4 "" "")] ; out of range label
5888 "TARGET_MIPS16_SHORT_JUMP_TABLES"
5890 if (operands[1] != const0_rtx)
5892 rtx reg = gen_reg_rtx (SImode);
5893 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode);
5895 if (!arith_operand (offset, SImode))
5896 offset = force_reg (SImode, offset);
5898 emit_insn (gen_addsi3 (reg, operands[0], offset));
5902 if (!arith_operand (operands[0], SImode))
5903 operands[0] = force_reg (SImode, operands[0]);
5905 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5907 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16,
5908 (operands[0], operands[2],
5909 operands[3], operands[4])));
5914 (define_insn "casesi_internal_mips16_<mode>"
5917 (leu (match_operand:SI 0 "register_operand" "d")
5918 (match_operand:SI 1 "arith_operand" "dI"))
5921 (label_ref (match_operand 2 "" ""))]
5922 UNSPEC_CASESI_DISPATCH)
5923 (label_ref (match_operand 3 "" ""))))
5924 (clobber (match_scratch:P 4 "=d"))
5925 (clobber (match_scratch:P 5 "=d"))
5926 (clobber (reg:SI MIPS16_T_REGNUM))]
5927 "TARGET_MIPS16_SHORT_JUMP_TABLES"
5929 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
5931 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
5933 output_asm_insn ("sltu\t%0, %1", operands);
5934 output_asm_insn ("bteqz\t%3", operands);
5936 switch (GET_MODE (diff_vec))
5939 output_asm_insn ("sll\t%5, %0, 1", operands);
5940 output_asm_insn ("la\t%4, %2", operands);
5941 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
5942 output_asm_insn ("lh\t%5, 0(%5)", operands);
5946 output_asm_insn ("sll\t%5, %0, 2", operands);
5947 output_asm_insn ("la\t%4, %2", operands);
5948 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
5949 output_asm_insn ("lw\t%5, 0(%5)", operands);
5956 output_asm_insn ("addu\t%4, %4, %5", operands);
5960 [(set_attr "length" "32")])
5962 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5963 ;; While it is possible to either pull it off the stack (in the
5964 ;; o32 case) or recalculate it given t9 and our target label,
5965 ;; it takes 3 or 4 insns to do so.
5967 (define_expand "builtin_setjmp_setup"
5968 [(use (match_operand 0 "register_operand"))]
5973 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3);
5974 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5978 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5979 ;; that older code did recalculate the gp from $25. Continue to jump through
5980 ;; $25 for compatibility (we lose nothing by doing so).
5982 (define_expand "builtin_longjmp"
5983 [(use (match_operand 0 "register_operand"))]
5986 /* The elements of the buffer are, in order: */
5987 int W = GET_MODE_SIZE (Pmode);
5988 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5989 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W));
5990 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W));
5991 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W));
5992 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5993 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5994 The target is bound to be using $28 as the global pointer
5995 but the current function might not be. */
5996 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5998 /* This bit is similar to expand_builtin_longjmp except that it
5999 restores $gp as well. */
6000 mips_emit_move (hard_frame_pointer_rtx, fp);
6001 mips_emit_move (pv, lab);
6002 emit_stack_restore (SAVE_NONLOCAL, stack);
6003 mips_emit_move (gp, gpv);
6004 emit_use (hard_frame_pointer_rtx);
6005 emit_use (stack_pointer_rtx);
6007 emit_indirect_jump (pv);
6012 ;; ....................
6014 ;; Function prologue/epilogue
6016 ;; ....................
6019 (define_expand "prologue"
6023 mips_expand_prologue ();
6027 ;; Block any insns from being moved before this point, since the
6028 ;; profiling call to mcount can use various registers that aren't
6029 ;; saved or used to pass arguments.
6031 (define_insn "blockage"
6032 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
6035 [(set_attr "type" "ghost")
6036 (set_attr "mode" "none")])
6038 (define_expand "epilogue"
6042 mips_expand_epilogue (false);
6046 (define_expand "sibcall_epilogue"
6050 mips_expand_epilogue (true);
6054 ;; Trivial return. Make it look like a normal return insn as that
6055 ;; allows jump optimizations to work better.
6057 (define_expand "return"
6059 "mips_can_use_return_insn ()"
6060 { mips_expand_before_return (); })
6062 (define_expand "simple_return"
6065 { mips_expand_before_return (); })
6067 (define_insn "*<optab>"
6071 [(set_attr "type" "jump")
6072 (set_attr "mode" "none")])
6076 (define_insn "<optab>_internal"
6078 (use (match_operand 0 "pmode_register_operand" ""))]
6081 [(set_attr "type" "jump")
6082 (set_attr "mode" "none")])
6084 ;; Exception return.
6085 (define_insn "mips_eret"
6087 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
6090 [(set_attr "type" "trap")
6091 (set_attr "mode" "none")])
6093 ;; Debug exception return.
6094 (define_insn "mips_deret"
6096 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
6099 [(set_attr "type" "trap")
6100 (set_attr "mode" "none")])
6102 ;; Disable interrupts.
6103 (define_insn "mips_di"
6104 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
6107 [(set_attr "type" "trap")
6108 (set_attr "mode" "none")])
6110 ;; Execution hazard barrier.
6111 (define_insn "mips_ehb"
6112 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
6115 [(set_attr "type" "trap")
6116 (set_attr "mode" "none")])
6118 ;; Read GPR from previous shadow register set.
6119 (define_insn "mips_rdpgpr"
6120 [(set (match_operand:SI 0 "register_operand" "=d")
6121 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
6125 [(set_attr "type" "move")
6126 (set_attr "mode" "SI")])
6128 ;; Move involving COP0 registers.
6129 (define_insn "cop0_move"
6130 [(set (match_operand:SI 0 "register_operand" "=B,d")
6131 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
6134 { return mips_output_move (operands[0], operands[1]); }
6135 [(set_attr "type" "mtc,mfc")
6136 (set_attr "mode" "SI")])
6138 ;; This is used in compiling the unwind routines.
6139 (define_expand "eh_return"
6140 [(use (match_operand 0 "general_operand"))]
6143 if (GET_MODE (operands[0]) != word_mode)
6144 operands[0] = convert_to_mode (word_mode, operands[0], 0);
6146 emit_insn (gen_eh_set_lr_di (operands[0]));
6148 emit_insn (gen_eh_set_lr_si (operands[0]));
6152 ;; Clobber the return address on the stack. We can't expand this
6153 ;; until we know where it will be put in the stack frame.
6155 (define_insn "eh_set_lr_si"
6156 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6157 (clobber (match_scratch:SI 1 "=&d"))]
6161 (define_insn "eh_set_lr_di"
6162 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6163 (clobber (match_scratch:DI 1 "=&d"))]
6168 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
6169 (clobber (match_scratch 1))]
6173 mips_set_return_address (operands[0], operands[1]);
6177 (define_expand "exception_receiver"
6181 /* See the comment above load_call<mode> for details. */
6182 emit_insn (gen_set_got_version ());
6184 /* If we have a call-clobbered $gp, restore it from its save slot. */
6185 if (HAVE_restore_gp_si)
6186 emit_insn (gen_restore_gp_si ());
6187 else if (HAVE_restore_gp_di)
6188 emit_insn (gen_restore_gp_di ());
6192 (define_expand "nonlocal_goto_receiver"
6196 /* See the comment above load_call<mode> for details. */
6197 emit_insn (gen_set_got_version ());
6201 ;; Restore $gp from its .cprestore stack slot. The instruction remains
6202 ;; volatile until all uses of $28 are exposed.
6203 (define_insn_and_split "restore_gp_<mode>"
6205 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP))
6206 (clobber (match_scratch:P 0 "=&d"))]
6207 "TARGET_CALL_CLOBBERED_GP"
6209 "&& epilogue_completed"
6212 mips_restore_gp_from_cprestore_slot (operands[0]);
6215 [(set_attr "type" "ghost")])
6217 ;; Move between $gp and its register save slot.
6218 (define_insn_and_split "move_gp<mode>"
6219 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
6220 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
6223 { return mips_must_initialize_gp_p () ? "#" : ""; }
6224 "mips_must_initialize_gp_p ()"
6227 mips_emit_move (operands[0], operands[1]);
6230 [(set_attr "type" "ghost")])
6233 ;; ....................
6237 ;; ....................
6239 ;; Instructions to load a call address from the GOT. The address might
6240 ;; point to a function or to a lazy binding stub. In the latter case,
6241 ;; the stub will use the dynamic linker to resolve the function, which
6242 ;; in turn will change the GOT entry to point to the function's real
6245 ;; This means that every call, even pure and constant ones, can
6246 ;; potentially modify the GOT entry. And once a stub has been called,
6247 ;; we must not call it again.
6249 ;; We represent this restriction using an imaginary, fixed, call-saved
6250 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
6251 ;; live throughout the function and to change its value after every
6252 ;; potential call site. This stops any rtx value that uses the register
6253 ;; from being computed before an earlier call. To do this, we:
6255 ;; - Ensure that the register is live on entry to the function,
6256 ;; so that it is never thought to be used uninitalized.
6258 ;; - Ensure that the register is live on exit from the function,
6259 ;; so that it is live throughout.
6261 ;; - Make each call (lazily-bound or not) use the current value
6262 ;; of GOT_VERSION_REGNUM, so that updates of the register are
6263 ;; not moved across call boundaries.
6265 ;; - Add "ghost" definitions of the register to the beginning of
6266 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
6267 ;; edges may involve calls that normal paths don't. (E.g. the
6268 ;; unwinding code that handles a non-call exception may change
6269 ;; lazily-bound GOT entries.) We do this by making the
6270 ;; exception_receiver and nonlocal_goto_receiver expanders emit
6271 ;; a set_got_version instruction.
6273 ;; - After each call (lazily-bound or not), use a "ghost"
6274 ;; update_got_version instruction to change the register's value.
6275 ;; This instruction mimics the _possible_ effect of the dynamic
6276 ;; resolver during the call and it remains live even if the call
6277 ;; itself becomes dead.
6279 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
6280 ;; The register is therefore not a valid register_operand
6281 ;; and cannot be moved to or from other registers.
6283 (define_insn "load_call<mode>"
6284 [(set (match_operand:P 0 "register_operand" "=d")
6285 (unspec:P [(match_operand:P 1 "register_operand" "d")
6286 (match_operand:P 2 "immediate_operand" "")
6287 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
6289 "<load>\t%0,%R2(%1)"
6290 [(set_attr "got" "load")
6291 (set_attr "mode" "<MODE>")])
6293 (define_insn "set_got_version"
6294 [(set (reg:SI GOT_VERSION_REGNUM)
6295 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
6298 [(set_attr "type" "ghost")])
6300 (define_insn "update_got_version"
6301 [(set (reg:SI GOT_VERSION_REGNUM)
6302 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
6305 [(set_attr "type" "ghost")])
6307 ;; Sibling calls. All these patterns use jump instructions.
6309 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
6310 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
6311 ;; is defined in terms of call_insn_operand, the same is true of the
6314 ;; When we use an indirect jump, we need a register that will be
6315 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
6316 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
6317 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
6320 (define_expand "sibcall"
6321 [(parallel [(call (match_operand 0 "")
6322 (match_operand 1 ""))
6323 (use (match_operand 2 "")) ;; next_arg_reg
6324 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6327 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
6328 operands[1], operands[2], false);
6332 (define_insn "sibcall_internal"
6333 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
6334 (match_operand 1 "" ""))]
6335 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6336 { return MIPS_CALL ("j", operands, 0, 1); }
6337 [(set_attr "jal" "indirect,direct")
6338 (set_attr "jal_macro" "no")])
6340 (define_expand "sibcall_value"
6341 [(parallel [(set (match_operand 0 "")
6342 (call (match_operand 1 "")
6343 (match_operand 2 "")))
6344 (use (match_operand 3 ""))])] ;; next_arg_reg
6347 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
6348 operands[2], operands[3], false);
6352 (define_insn "sibcall_value_internal"
6353 [(set (match_operand 0 "register_operand" "")
6354 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6355 (match_operand 2 "" "")))]
6356 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6357 { return MIPS_CALL ("j", operands, 1, 2); }
6358 [(set_attr "jal" "indirect,direct")
6359 (set_attr "jal_macro" "no")])
6361 (define_insn "sibcall_value_multiple_internal"
6362 [(set (match_operand 0 "register_operand" "")
6363 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6364 (match_operand 2 "" "")))
6365 (set (match_operand 3 "register_operand" "")
6366 (call (mem:SI (match_dup 1))
6368 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6369 { return MIPS_CALL ("j", operands, 1, 2); }
6370 [(set_attr "jal" "indirect,direct")
6371 (set_attr "jal_macro" "no")])
6373 (define_expand "call"
6374 [(parallel [(call (match_operand 0 "")
6375 (match_operand 1 ""))
6376 (use (match_operand 2 "")) ;; next_arg_reg
6377 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6380 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6381 operands[1], operands[2], false);
6385 ;; This instruction directly corresponds to an assembly-language "jal".
6386 ;; There are four cases:
6389 ;; Both symbolic and register destinations are OK. The pattern
6390 ;; always expands to a single mips instruction.
6392 ;; - -mabicalls/-mno-explicit-relocs:
6393 ;; Again, both symbolic and register destinations are OK.
6394 ;; The call is treated as a multi-instruction black box.
6396 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6397 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6400 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6401 ;; Only "jal $25" is allowed. The call is actually two instructions:
6402 ;; "jalr $25" followed by an insn to reload $gp.
6404 ;; In the last case, we can generate the individual instructions with
6405 ;; a define_split. There are several things to be wary of:
6407 ;; - We can't expose the load of $gp before reload. If we did,
6408 ;; it might get removed as dead, but reload can introduce new
6409 ;; uses of $gp by rematerializing constants.
6411 ;; - We shouldn't restore $gp after calls that never return.
6412 ;; It isn't valid to insert instructions between a noreturn
6413 ;; call and the following barrier.
6415 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6416 ;; instruction preserves $gp and so have no effect on its liveness.
6417 ;; But once we generate the separate insns, it becomes obvious that
6418 ;; $gp is not live on entry to the call.
6420 (define_insn_and_split "call_internal"
6421 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6422 (match_operand 1 "" ""))
6423 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6425 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6426 "reload_completed && TARGET_SPLIT_CALLS"
6429 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6432 [(set_attr "jal" "indirect,direct")])
6434 (define_insn "call_split"
6435 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6436 (match_operand 1 "" ""))
6437 (clobber (reg:SI RETURN_ADDR_REGNUM))
6438 (clobber (reg:SI 28))]
6439 "TARGET_SPLIT_CALLS"
6440 { return MIPS_CALL ("jal", operands, 0, 1); }
6441 [(set_attr "jal" "indirect,direct")
6442 (set_attr "jal_macro" "no")])
6444 ;; A pattern for calls that must be made directly. It is used for
6445 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6446 ;; stub; the linker relies on the call relocation type to detect when
6447 ;; such redirection is needed.
6448 (define_insn_and_split "call_internal_direct"
6449 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6452 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6454 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6455 "reload_completed && TARGET_SPLIT_CALLS"
6458 mips_split_call (curr_insn,
6459 gen_call_direct_split (operands[0], operands[1]));
6462 [(set_attr "jal" "direct")])
6464 (define_insn "call_direct_split"
6465 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6468 (clobber (reg:SI RETURN_ADDR_REGNUM))
6469 (clobber (reg:SI 28))]
6470 "TARGET_SPLIT_CALLS"
6471 { return MIPS_CALL ("jal", operands, 0, -1); }
6472 [(set_attr "jal" "direct")
6473 (set_attr "jal_macro" "no")])
6475 (define_expand "call_value"
6476 [(parallel [(set (match_operand 0 "")
6477 (call (match_operand 1 "")
6478 (match_operand 2 "")))
6479 (use (match_operand 3 ""))])] ;; next_arg_reg
6482 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6483 operands[2], operands[3], false);
6487 ;; See comment for call_internal.
6488 (define_insn_and_split "call_value_internal"
6489 [(set (match_operand 0 "register_operand" "")
6490 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6491 (match_operand 2 "" "")))
6492 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6494 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6495 "reload_completed && TARGET_SPLIT_CALLS"
6498 mips_split_call (curr_insn,
6499 gen_call_value_split (operands[0], operands[1],
6503 [(set_attr "jal" "indirect,direct")])
6505 (define_insn "call_value_split"
6506 [(set (match_operand 0 "register_operand" "")
6507 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6508 (match_operand 2 "" "")))
6509 (clobber (reg:SI RETURN_ADDR_REGNUM))
6510 (clobber (reg:SI 28))]
6511 "TARGET_SPLIT_CALLS"
6512 { return MIPS_CALL ("jal", operands, 1, 2); }
6513 [(set_attr "jal" "indirect,direct")
6514 (set_attr "jal_macro" "no")])
6516 ;; See call_internal_direct.
6517 (define_insn_and_split "call_value_internal_direct"
6518 [(set (match_operand 0 "register_operand")
6519 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6522 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6524 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6525 "reload_completed && TARGET_SPLIT_CALLS"
6528 mips_split_call (curr_insn,
6529 gen_call_value_direct_split (operands[0], operands[1],
6533 [(set_attr "jal" "direct")])
6535 (define_insn "call_value_direct_split"
6536 [(set (match_operand 0 "register_operand")
6537 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6540 (clobber (reg:SI RETURN_ADDR_REGNUM))
6541 (clobber (reg:SI 28))]
6542 "TARGET_SPLIT_CALLS"
6543 { return MIPS_CALL ("jal", operands, 1, -1); }
6544 [(set_attr "jal" "direct")
6545 (set_attr "jal_macro" "no")])
6547 ;; See comment for call_internal.
6548 (define_insn_and_split "call_value_multiple_internal"
6549 [(set (match_operand 0 "register_operand" "")
6550 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6551 (match_operand 2 "" "")))
6552 (set (match_operand 3 "register_operand" "")
6553 (call (mem:SI (match_dup 1))
6555 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6557 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6558 "reload_completed && TARGET_SPLIT_CALLS"
6561 mips_split_call (curr_insn,
6562 gen_call_value_multiple_split (operands[0], operands[1],
6563 operands[2], operands[3]));
6566 [(set_attr "jal" "indirect,direct")])
6568 (define_insn "call_value_multiple_split"
6569 [(set (match_operand 0 "register_operand" "")
6570 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6571 (match_operand 2 "" "")))
6572 (set (match_operand 3 "register_operand" "")
6573 (call (mem:SI (match_dup 1))
6575 (clobber (reg:SI RETURN_ADDR_REGNUM))
6576 (clobber (reg:SI 28))]
6577 "TARGET_SPLIT_CALLS"
6578 { return MIPS_CALL ("jal", operands, 1, 2); }
6579 [(set_attr "jal" "indirect,direct")
6580 (set_attr "jal_macro" "no")])
6582 ;; Call subroutine returning any type.
6584 (define_expand "untyped_call"
6585 [(parallel [(call (match_operand 0 "")
6587 (match_operand 1 "")
6588 (match_operand 2 "")])]
6593 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6595 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6597 rtx set = XVECEXP (operands[2], 0, i);
6598 mips_emit_move (SET_DEST (set), SET_SRC (set));
6601 emit_insn (gen_blockage ());
6606 ;; ....................
6610 ;; ....................
6614 (define_insn "prefetch"
6615 [(prefetch (match_operand:QI 0 "address_operand" "p")
6616 (match_operand 1 "const_int_operand" "n")
6617 (match_operand 2 "const_int_operand" "n"))]
6618 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6620 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
6621 /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching. */
6622 return "ld\t$0,%a0";
6623 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6624 return "pref\t%1,%a0";
6626 [(set_attr "type" "prefetch")])
6628 (define_insn "*prefetch_indexed_<mode>"
6629 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6630 (match_operand:P 1 "register_operand" "d"))
6631 (match_operand 2 "const_int_operand" "n")
6632 (match_operand 3 "const_int_operand" "n"))]
6633 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6635 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6636 return "prefx\t%2,%1(%0)";
6638 [(set_attr "type" "prefetchx")])
6644 [(set_attr "type" "nop")
6645 (set_attr "mode" "none")])
6647 ;; Like nop, but commented out when outside a .set noreorder block.
6648 (define_insn "hazard_nop"
6652 if (mips_noreorder.nesting_level > 0)
6657 [(set_attr "type" "nop")])
6659 ;; MIPS4 Conditional move instructions.
6661 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6662 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6664 (match_operator:MOVECC 4 "equality_operator"
6665 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6667 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6668 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6673 [(set_attr "type" "condmove")
6674 (set_attr "mode" "<GPR:MODE>")])
6676 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6677 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6678 (if_then_else:SCALARF
6679 (match_operator:MOVECC 4 "equality_operator"
6680 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6682 (match_operand:SCALARF 2 "register_operand" "f,0")
6683 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6684 "ISA_HAS_FP_CONDMOVE"
6686 mov%T4.<fmt>\t%0,%2,%1
6687 mov%t4.<fmt>\t%0,%3,%1"
6688 [(set_attr "type" "condmove")
6689 (set_attr "mode" "<SCALARF:MODE>")])
6691 ;; These are the main define_expand's used to make conditional moves.
6693 (define_expand "mov<mode>cc"
6694 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6695 (set (match_operand:GPR 0 "register_operand")
6696 (if_then_else:GPR (match_dup 5)
6697 (match_operand:GPR 2 "reg_or_0_operand")
6698 (match_operand:GPR 3 "reg_or_0_operand")))]
6701 mips_expand_conditional_move (operands);
6705 (define_expand "mov<mode>cc"
6706 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6707 (set (match_operand:SCALARF 0 "register_operand")
6708 (if_then_else:SCALARF (match_dup 5)
6709 (match_operand:SCALARF 2 "register_operand")
6710 (match_operand:SCALARF 3 "register_operand")))]
6711 "ISA_HAS_FP_CONDMOVE"
6713 mips_expand_conditional_move (operands);
6718 ;; ....................
6720 ;; mips16 inline constant tables
6722 ;; ....................
6725 (define_insn "consttable_tls_reloc"
6726 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "")
6727 (match_operand 1 "const_int_operand" "")]
6728 UNSPEC_CONSTTABLE_INT)]
6729 "TARGET_MIPS16_PCREL_LOADS"
6730 { return mips_output_tls_reloc_directive (&operands[0]); }
6731 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6733 (define_insn "consttable_int"
6734 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6735 (match_operand 1 "const_int_operand" "")]
6736 UNSPEC_CONSTTABLE_INT)]
6739 assemble_integer (mips_strip_unspec_address (operands[0]),
6740 INTVAL (operands[1]),
6741 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6744 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6746 (define_insn "consttable_float"
6747 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6748 UNSPEC_CONSTTABLE_FLOAT)]
6753 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6754 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6755 assemble_real (d, GET_MODE (operands[0]),
6756 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6759 [(set (attr "length")
6760 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6762 (define_insn "align"
6763 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6766 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6769 [(match_operand 0 "small_data_pattern")]
6772 { operands[0] = mips_rewrite_small_data (operands[0]); })
6775 ;; ....................
6777 ;; MIPS16e Save/Restore
6779 ;; ....................
6782 (define_insn "*mips16e_save_restore"
6783 [(match_parallel 0 ""
6784 [(set (match_operand:SI 1 "register_operand")
6785 (plus:SI (match_dup 1)
6786 (match_operand:SI 2 "const_int_operand")))])]
6787 "operands[1] == stack_pointer_rtx
6788 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6789 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6790 [(set_attr "type" "arith")
6791 (set_attr "extended_mips16" "yes")])
6793 ;; Thread-Local Storage
6795 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6796 ;; MIPS architecture defines this register, and no current
6797 ;; implementation provides it; instead, any OS which supports TLS is
6798 ;; expected to trap and emulate this instruction. rdhwr is part of the
6799 ;; MIPS 32r2 specification, but we use it on any architecture because
6800 ;; we expect it to be emulated. Use .set to force the assembler to
6803 ;; We do not use a constraint to force the destination to be $3
6804 ;; because $3 can appear explicitly as a function return value.
6805 ;; If we leave the use of $3 implicit in the constraints until
6806 ;; reload, we may end up making a $3 return value live across
6807 ;; the instruction, leading to a spill failure when reloading it.
6808 (define_insn_and_split "tls_get_tp_<mode>"
6809 [(set (match_operand:P 0 "register_operand" "=d")
6810 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6811 (clobber (reg:P TLS_GET_TP_REGNUM))]
6812 "HAVE_AS_TLS && !TARGET_MIPS16"
6814 "&& reload_completed"
6815 [(set (reg:P TLS_GET_TP_REGNUM)
6816 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6817 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6819 [(set_attr "type" "unknown")
6820 ; Since rdhwr always generates a trap for now, putting it in a delay
6821 ; slot would make the kernel's emulation of it much slower.
6822 (set_attr "can_delay" "no")
6823 (set_attr "mode" "<MODE>")
6824 (set_attr "length" "8")])
6826 (define_insn "*tls_get_tp_<mode>_split"
6827 [(set (reg:P TLS_GET_TP_REGNUM)
6828 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6829 "HAVE_AS_TLS && !TARGET_MIPS16"
6830 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6831 [(set_attr "type" "unknown")
6832 ; See tls_get_tp_<mode>
6833 (set_attr "can_delay" "no")
6834 (set_attr "mode" "<MODE>")])
6836 ;; In MIPS16 mode, the TLS base pointer is accessed by a
6837 ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not
6838 ;; accessible in MIPS16.
6840 ;; This is not represented as a call insn, to avoid the
6841 ;; unnecesarry clobbering of caller-save registers by a
6842 ;; function consisting only of: "rdhwr $3,$29; j $31; nop;"
6844 ;; A $25 clobber is added to cater for a $25 load stub added by the
6845 ;; linker to __mips16_rdhwr when the call is made from non-PIC code.
6847 (define_insn_and_split "tls_get_tp_mips16_<mode>"
6848 [(set (match_operand:P 0 "register_operand" "=d")
6849 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")]
6851 (clobber (reg:P TLS_GET_TP_REGNUM))
6852 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6853 (clobber (reg:P RETURN_ADDR_REGNUM))]
6854 "HAVE_AS_TLS && TARGET_MIPS16"
6856 "&& reload_completed"
6857 [(parallel [(set (reg:P TLS_GET_TP_REGNUM)
6858 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP))
6859 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6860 (clobber (reg:P RETURN_ADDR_REGNUM))])
6861 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6863 [(set_attr "type" "multi")
6864 (set_attr "length" "16")
6865 (set_attr "mode" "<MODE>")])
6867 (define_insn "*tls_get_tp_mips16_call_<mode>"
6868 [(set (reg:P TLS_GET_TP_REGNUM)
6869 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")]
6871 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6872 (clobber (reg:P RETURN_ADDR_REGNUM))]
6873 "HAVE_AS_TLS && TARGET_MIPS16"
6874 { return MIPS_CALL ("jal", operands, 0, -1); }
6875 [(set_attr "type" "call")
6876 (set_attr "length" "12")
6877 (set_attr "mode" "<MODE>")])
6879 ;; Synchronization instructions.
6883 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6885 (include "mips-ps-3d.md")
6887 ; The MIPS DSP Instructions.
6889 (include "mips-dsp.md")
6891 ; The MIPS DSP REV 2 Instructions.
6893 (include "mips-dspr2.md")
6895 ; MIPS fixed-point instructions.
6896 (include "mips-fixed.md")
6898 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6899 (include "loongson.md")
6901 (define_c_enum "unspec" [
6902 UNSPEC_ADDRESS_FIRST