1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989-2013 Free Software Foundation, Inc.
3 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
4 ;; Changes by Michael Meissner, meissner@osf.org
5 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 ;; Brendan Eich, brendan@microunity.com.
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 (define_enum "processor" [
70 (define_c_enum "unspec" [
71 ;; Unaligned accesses.
77 ;; Floating-point moves.
93 UNSPEC_POTENTIAL_CPRESTORE
98 UNSPEC_SET_GOT_VERSION
99 UNSPEC_UPDATE_GOT_VERSION
101 ;; Symbolic accesses.
106 UNSPEC_UNSHIFTED_HIGH
108 ;; MIPS16 constant pools.
110 UNSPEC_CONSTTABLE_INT
111 UNSPEC_CONSTTABLE_FLOAT
113 ;; Blockage and synchronisation.
120 ;; Cache manipulation.
122 UNSPEC_R10K_CACHE_BARRIER
124 ;; Interrupt handling.
132 ;; Used in a call expression in place of args_size. It's present for PIC
133 ;; indirect calls where it contains args_size and the function symbol.
136 ;; MIPS16 casesi jump table dispatch.
137 UNSPEC_CASESI_DISPATCH
140 UNSPEC_PROBE_STACK_RANGE
144 [(TLS_GET_TP_REGNUM 3)
146 (PIC_FUNCTION_ADDR_REGNUM 25)
147 (RETURN_ADDR_REGNUM 31)
148 (CPRESTORE_SLOT_REGNUM 76)
149 (GOT_VERSION_REGNUM 79)
151 ;; PIC long branch sequences are never longer than 100 bytes.
152 (MAX_PIC_BRANCH_LENGTH 100)
156 (include "predicates.md")
157 (include "constraints.md")
159 ;; ....................
163 ;; ....................
165 (define_attr "got" "unset,xgot_high,load"
166 (const_string "unset"))
168 ;; For jal instructions, this attribute is DIRECT when the target address
169 ;; is symbolic and INDIRECT when it is a register.
170 (define_attr "jal" "unset,direct,indirect"
171 (const_string "unset"))
173 ;; This attribute is YES if the instruction is a jal macro (not a
174 ;; real jal instruction).
176 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
177 ;; an instruction to restore $gp. Direct jals are also macros for
178 ;; !TARGET_ABSOLUTE_JUMPS because they first load the target address
180 (define_attr "jal_macro" "no,yes"
181 (cond [(eq_attr "jal" "direct")
182 (symbol_ref "(TARGET_CALL_CLOBBERED_GP || !TARGET_ABSOLUTE_JUMPS
183 ? JAL_MACRO_YES : JAL_MACRO_NO)")
184 (eq_attr "jal" "indirect")
185 (symbol_ref "(TARGET_CALL_CLOBBERED_GP
186 ? JAL_MACRO_YES : JAL_MACRO_NO)")]
187 (const_string "no")))
189 ;; Classification of moves, extensions and truncations. Most values
190 ;; are as for "type" (see below) but there are also the following
191 ;; move-specific values:
193 ;; constN move an N-constraint integer into a MIPS16 register
194 ;; sll0 "sll DEST,SRC,0", which on 64-bit targets is guaranteed
195 ;; to produce a sign-extended DEST, even if SRC is not
196 ;; properly sign-extended
197 ;; ext_ins EXT, DEXT, INS or DINS instruction
198 ;; andi a single ANDI instruction
199 ;; loadpool move a constant into a MIPS16 register by loading it
201 ;; shift_shift a shift left followed by a shift right
203 ;; This attribute is used to determine the instruction's length and
204 ;; scheduling type. For doubleword moves, the attribute always describes
205 ;; the split instructions; in some cases, it is more appropriate for the
206 ;; scheduling type to be "multi" instead.
207 (define_attr "move_type"
208 "unknown,load,fpload,store,fpstore,mtc,mfc,mtlo,mflo,imul,move,fmove,
209 const,constN,signext,ext_ins,logical,arith,sll0,andi,loadpool,
211 (const_string "unknown"))
213 (define_attr "alu_type" "unknown,add,sub,not,nor,and,or,xor"
214 (const_string "unknown"))
216 ;; Main data type used by the insn
217 (define_attr "mode" "unknown,none,QI,HI,SI,DI,TI,SF,DF,TF,FPSW"
218 (const_string "unknown"))
220 ;; True if the main data type is twice the size of a word.
221 (define_attr "dword_mode" "no,yes"
222 (cond [(and (eq_attr "mode" "DI,DF")
223 (not (match_test "TARGET_64BIT")))
226 (and (eq_attr "mode" "TI,TF")
227 (match_test "TARGET_64BIT"))
228 (const_string "yes")]
229 (const_string "no")))
231 ;; Attributes describing a sync loop. These loops have the form:
233 ;; if (RELEASE_BARRIER == YES) sync
235 ;; if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2
236 ;; CMP = 0 [delay slot]
237 ;; $TMP1 = OLDVAL & EXCLUSIVE_MASK
238 ;; $TMP2 = INSN1 (OLDVAL, INSN1_OP2)
239 ;; $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK)
240 ;; $AT |= $TMP1 | $TMP3
241 ;; if (!commit (*MEM = $AT)) goto 1.
242 ;; if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]
244 ;; if (ACQUIRE_BARRIER == YES) sync
247 ;; where "$" values are temporaries and where the other values are
248 ;; specified by the attributes below. Values are specified as operand
249 ;; numbers and insns are specified as enums. If no operand number is
250 ;; specified, the following values are used instead:
255 ;; - INCLUSIVE_MASK: -1
256 ;; - REQUIRED_OLDVAL: OLDVAL & INCLUSIVE_MASK
257 ;; - EXCLUSIVE_MASK: 0
259 ;; MEM and INSN1_OP2 are required.
261 ;; Ideally, the operand attributes would be integers, with -1 meaning "none",
262 ;; but the gen* programs don't yet support that.
263 (define_attr "sync_mem" "none,0,1,2,3,4,5" (const_string "none"))
264 (define_attr "sync_oldval" "none,0,1,2,3,4,5" (const_string "none"))
265 (define_attr "sync_cmp" "none,0,1,2,3,4,5" (const_string "none"))
266 (define_attr "sync_newval" "none,0,1,2,3,4,5" (const_string "none"))
267 (define_attr "sync_inclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
268 (define_attr "sync_exclusive_mask" "none,0,1,2,3,4,5" (const_string "none"))
269 (define_attr "sync_required_oldval" "none,0,1,2,3,4,5" (const_string "none"))
270 (define_attr "sync_insn1_op2" "none,0,1,2,3,4,5" (const_string "none"))
271 (define_attr "sync_insn1" "move,li,addu,addiu,subu,and,andi,or,ori,xor,xori"
272 (const_string "move"))
273 (define_attr "sync_insn2" "nop,and,xor,not"
274 (const_string "nop"))
275 ;; Memory model specifier.
276 ;; "0"-"9" values specify the operand that stores the memory model value.
277 ;; "10" specifies MEMMODEL_ACQ_REL,
278 ;; "11" specifies MEMMODEL_ACQUIRE.
279 (define_attr "sync_memmodel" "" (const_int 10))
281 ;; Accumulator operand for madd patterns.
282 (define_attr "accum_in" "none,0,1,2,3,4,5" (const_string "none"))
284 ;; Classification of each insn.
285 ;; branch conditional branch
286 ;; jump unconditional jump
287 ;; call unconditional call
288 ;; load load instruction(s)
289 ;; fpload floating point load
290 ;; fpidxload floating point indexed load
291 ;; store store instruction(s)
292 ;; fpstore floating point store
293 ;; fpidxstore floating point indexed store
294 ;; prefetch memory prefetch (register + offset)
295 ;; prefetchx memory indexed prefetch (register + register)
296 ;; condmove conditional moves
297 ;; mtc transfer to coprocessor
298 ;; mfc transfer from coprocessor
299 ;; mthi transfer to a hi register
300 ;; mtlo transfer to a lo register
301 ;; mfhi transfer from a hi register
302 ;; mflo transfer from a lo register
303 ;; const load constant
304 ;; arith integer arithmetic instructions
305 ;; logical integer logical instructions
306 ;; shift integer shift instructions
307 ;; slt set less than instructions
308 ;; signext sign extend instructions
309 ;; clz the clz and clo instructions
310 ;; pop the pop instruction
311 ;; trap trap if instructions
312 ;; imul integer multiply 2 operands
313 ;; imul3 integer multiply 3 operands
314 ;; imul3nc integer multiply 3 operands without clobbering HI/LO
315 ;; imadd integer multiply-add
316 ;; idiv integer divide 2 operands
317 ;; idiv3 integer divide 3 operands
318 ;; move integer register move ({,D}ADD{,U} with rt = 0)
319 ;; fmove floating point register move
320 ;; fadd floating point add/subtract
321 ;; fmul floating point multiply
322 ;; fmadd floating point multiply-add
323 ;; fdiv floating point divide
324 ;; frdiv floating point reciprocal divide
325 ;; frdiv1 floating point reciprocal divide step 1
326 ;; frdiv2 floating point reciprocal divide step 2
327 ;; fabs floating point absolute value
328 ;; fneg floating point negation
329 ;; fcmp floating point compare
330 ;; fcvt floating point convert
331 ;; fsqrt floating point square root
332 ;; frsqrt floating point reciprocal square root
333 ;; frsqrt1 floating point reciprocal square root step1
334 ;; frsqrt2 floating point reciprocal square root step2
335 ;; dspmac DSP MAC instructions not saturating the accumulator
336 ;; dspmacsat DSP MAC instructions that saturate the accumulator
337 ;; accext DSP accumulator extract instructions
338 ;; accmod DSP accumulator modify instructions
339 ;; dspalu DSP ALU instructions not saturating the result
340 ;; dspalusat DSP ALU instructions that saturate the result
341 ;; multi multiword sequence (or user asm statements)
342 ;; atomic atomic memory update instruction
343 ;; syncloop memory atomic operation implemented as a sync loop
345 ;; ghost an instruction that produces no real code
346 ;; multimem microMIPS multiword load and store
348 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
349 prefetch,prefetchx,condmove,mtc,mfc,mthi,mtlo,mfhi,mflo,const,arith,logical,
350 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
351 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
352 frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,
353 multi,atomic,syncloop,nop,ghost,multimem"
354 (cond [(eq_attr "jal" "!unset") (const_string "call")
355 (eq_attr "got" "load") (const_string "load")
357 (eq_attr "alu_type" "add,sub") (const_string "arith")
359 (eq_attr "alu_type" "not,nor,and,or,xor") (const_string "logical")
361 ;; If a doubleword move uses these expensive instructions,
362 ;; it is usually better to schedule them in the same way
363 ;; as the singleword form, rather than as "multi".
364 (eq_attr "move_type" "load") (const_string "load")
365 (eq_attr "move_type" "fpload") (const_string "fpload")
366 (eq_attr "move_type" "store") (const_string "store")
367 (eq_attr "move_type" "fpstore") (const_string "fpstore")
368 (eq_attr "move_type" "mtc") (const_string "mtc")
369 (eq_attr "move_type" "mfc") (const_string "mfc")
370 (eq_attr "move_type" "mtlo") (const_string "mtlo")
371 (eq_attr "move_type" "mflo") (const_string "mflo")
373 ;; These types of move are always single insns.
374 (eq_attr "move_type" "imul") (const_string "imul")
375 (eq_attr "move_type" "fmove") (const_string "fmove")
376 (eq_attr "move_type" "loadpool") (const_string "load")
377 (eq_attr "move_type" "signext") (const_string "signext")
378 (eq_attr "move_type" "ext_ins") (const_string "arith")
379 (eq_attr "move_type" "arith") (const_string "arith")
380 (eq_attr "move_type" "logical") (const_string "logical")
381 (eq_attr "move_type" "sll0") (const_string "shift")
382 (eq_attr "move_type" "andi") (const_string "logical")
384 ;; These types of move are always split.
385 (eq_attr "move_type" "constN,shift_shift")
386 (const_string "multi")
388 ;; These types of move are split for doubleword modes only.
389 (and (eq_attr "move_type" "move,const")
390 (eq_attr "dword_mode" "yes"))
391 (const_string "multi")
392 (eq_attr "move_type" "move") (const_string "move")
393 (eq_attr "move_type" "const") (const_string "const")
394 (eq_attr "sync_mem" "!none") (const_string "syncloop")]
395 (const_string "unknown")))
397 ;; Mode for conversion types (fcvt)
398 ;; I2S integer to float single (SI/DI to SF)
399 ;; I2D integer to float double (SI/DI to DF)
400 ;; S2I float to integer (SF to SI/DI)
401 ;; D2I float to integer (DF to SI/DI)
402 ;; D2S double to float single
403 ;; S2D float single to double
405 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
406 (const_string "unknown"))
408 ;; Is this an extended instruction in mips16 mode?
409 (define_attr "extended_mips16" "no,yes"
410 (if_then_else (ior ;; In general, constant-pool loads are extended
411 ;; instructions. We don't yet optimize for 16-bit
412 ;; PC-relative references.
413 (eq_attr "move_type" "sll0,loadpool")
414 (eq_attr "jal" "direct")
415 (eq_attr "got" "load"))
417 (const_string "no")))
419 (define_attr "compression" "none,all,micromips"
420 (const_string "none"))
422 (define_attr "enabled" "no,yes"
423 (if_then_else (ior (eq_attr "compression" "all,none")
424 (and (eq_attr "compression" "micromips")
425 (match_test "TARGET_MICROMIPS")))
427 (const_string "no")))
429 ;; The number of individual instructions that a non-branch pattern generates,
430 ;; using units of BASE_INSN_LENGTH.
431 (define_attr "insn_count" ""
432 (cond [;; "Ghost" instructions occupy no space.
433 (eq_attr "type" "ghost")
436 ;; Extended instructions count as 2.
437 (and (eq_attr "extended_mips16" "yes")
438 (match_test "TARGET_MIPS16"))
441 ;; A GOT load followed by an add of $gp. This is not used for MIPS16.
442 (eq_attr "got" "xgot_high")
445 ;; SHIFT_SHIFTs are decomposed into two separate instructions.
446 ;; They are extended instructions on MIPS16 targets.
447 (eq_attr "move_type" "shift_shift")
448 (if_then_else (match_test "TARGET_MIPS16")
452 ;; Check for doubleword moves that are decomposed into two
453 ;; instructions. The individual instructions are unextended
455 (and (eq_attr "move_type" "mtc,mfc,mtlo,mflo,move")
456 (eq_attr "dword_mode" "yes"))
459 ;; Constants, loads and stores are handled by external routines.
460 (and (eq_attr "move_type" "const,constN")
461 (eq_attr "dword_mode" "yes"))
462 (symbol_ref "mips_split_const_insns (operands[1])")
463 (eq_attr "move_type" "const,constN")
464 (symbol_ref "mips_const_insns (operands[1])")
465 (eq_attr "move_type" "load,fpload")
466 (symbol_ref "mips_load_store_insns (operands[1], insn)")
467 (eq_attr "move_type" "store,fpstore")
468 (symbol_ref "mips_load_store_insns (operands[0], insn)
469 + (TARGET_FIX_24K ? 1 : 0)")
471 ;; In the worst case, a call macro will take 8 instructions:
473 ;; lui $25,%call_hi(FOO)
475 ;; lw $25,%call_lo(FOO)($25)
481 (eq_attr "jal_macro" "yes")
484 ;; Various VR4120 errata require a nop to be inserted after a macc
485 ;; instruction. The assembler does this for us, so account for
486 ;; the worst-case length here.
487 (and (eq_attr "type" "imadd")
488 (match_test "TARGET_FIX_VR4120"))
491 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
492 ;; the result of the second one is missed. The assembler should work
493 ;; around this by inserting a nop after the first dmult.
494 (and (eq_attr "type" "imul,imul3")
495 (eq_attr "mode" "DI")
496 (match_test "TARGET_FIX_VR4120"))
499 (eq_attr "type" "idiv,idiv3")
500 (symbol_ref "mips_idiv_insns ()")
502 (not (eq_attr "sync_mem" "none"))
503 (symbol_ref "mips_sync_loop_insns (insn, operands)")]
506 ;; Length of instruction in bytes. The default is derived from "insn_count",
507 ;; but there are special cases for branches (which must be handled here)
508 ;; and for compressed single instructions.
509 (define_attr "length" ""
510 (cond [(and (eq_attr "compression" "micromips,all")
511 (eq_attr "dword_mode" "no")
512 (match_test "TARGET_MICROMIPS"))
515 ;; Direct microMIPS branch instructions have a range of
516 ;; [-0x10000,0xfffe], otherwise the range is [-0x20000,0x1fffc].
517 ;; If a branch is outside this range, we have a choice of two
520 ;; For PIC, an out-of-range branch like:
525 ;; becomes the equivalent of:
534 ;; The non-PIC case is similar except that we use a direct
535 ;; jump instead of an la/jr pair. Since the target of this
536 ;; jump is an absolute 28-bit bit address (the other bits
537 ;; coming from the address of the delay slot) this form cannot
538 ;; cross a 256MB boundary. We could provide the option of
539 ;; using la/jr in this case too, but we do not do so at
542 ;; The value we specify here does not account for the delay slot
543 ;; instruction, whose length is added separately. If the RTL
544 ;; pattern has no explicit delay slot, mips_adjust_insn_length
545 ;; will add the length of the implicit nop. The range of
546 ;; [-0x20000, 0x1fffc] from the address of the delay slot
547 ;; therefore translates to a range of:
549 ;; [-(0x20000 - sizeof (branch)), 0x1fffc - sizeof (slot)]
550 ;; == [-0x1fffc, 0x1fff8]
552 ;; from the shorten_branches reference address.
553 (and (eq_attr "type" "branch")
554 (not (match_test "TARGET_MIPS16")))
555 (cond [;; Any variant can handle the 17-bit range.
556 (and (le (minus (match_dup 0) (pc)) (const_int 65532))
557 (le (minus (pc) (match_dup 0)) (const_int 65534)))
560 ;; The 18-bit range is OK other than for microMIPS.
561 (and (not (match_test "TARGET_MICROMIPS"))
562 (and (le (minus (match_dup 0) (pc)) (const_int 131064))
563 (le (minus (pc) (match_dup 0)) (const_int 131068))))
566 ;; The non-PIC case: branch, first delay slot, and J.
567 (match_test "TARGET_ABSOLUTE_JUMPS")
570 ;; Use MAX_PIC_BRANCH_LENGTH as a (gross) overestimate.
571 ;; mips_adjust_insn_length substitutes the correct length.
573 ;; Note that we can't simply use (symbol_ref ...) here
574 ;; because genattrtab needs to know the maximum length
576 (const_int MAX_PIC_BRANCH_LENGTH))
578 ;; An unextended MIPS16 branch has a range of [-0x100, 0xfe]
579 ;; from the address of the following instruction, which leads
582 ;; [-(0x100 - sizeof (branch)), 0xfe]
585 ;; from the shorten_branches reference address. Extended branches
586 ;; likewise have a range of [-0x10000, 0xfffe] from the address
587 ;; of the following instruction, which leads to a range of:
589 ;; [-(0x10000 - sizeof (branch)), 0xfffe]
590 ;; == [-0xfffc, 0xfffe]
592 ;; from the reference address.
594 ;; When a branch is out of range, mips_reorg splits it into a form
595 ;; that uses in-range branches. There are four basic sequences:
597 ;; (1) Absolute addressing with a readable text segment
598 ;; (32-bit addresses):
601 ;; move $1,$2 2 bytes
602 ;; lw $2,label 2 bytes
604 ;; move $2,$1 2 bytes
605 ;; .align 2 0 or 2 bytes
607 ;; .word target 4 bytes
609 ;; (16 bytes in the worst case)
611 ;; (2) Absolute addressing with a readable text segment
612 ;; (64-bit addresses):
615 ;; move $1,$2 2 bytes
616 ;; ld $2,label 2 bytes
618 ;; move $2,$1 2 bytes
619 ;; .align 3 0 to 6 bytes
621 ;; .dword target 8 bytes
623 ;; (24 bytes in the worst case)
625 ;; (3) Absolute addressing without a readable text segment
626 ;; (which requires 32-bit addresses at present):
629 ;; move $1,$2 2 bytes
630 ;; lui $2,%hi(target) 4 bytes
633 ;; addiu $2,%lo(target) 4 bytes
635 ;; move $2,$1 2 bytes
639 ;; (4) PIC addressing (which requires 32-bit addresses at present):
642 ;; move $1,$2 2 bytes
643 ;; lw $2,cprestore 0, 2 or 4 bytes
644 ;; lw $2,%got(target)($2) 4 bytes
645 ;; addiu $2,%lo(target) 4 bytes
647 ;; move $2,$1 2 bytes
649 ;; (20 bytes in the worst case)
650 (and (eq_attr "type" "branch")
651 (match_test "TARGET_MIPS16"))
652 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
653 (le (minus (pc) (match_dup 0)) (const_int 254)))
655 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
656 (le (minus (pc) (match_dup 0)) (const_int 65532)))
658 (and (match_test "TARGET_ABICALLS")
659 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
661 (match_test "Pmode == SImode")
664 (symbol_ref "get_attr_insn_count (insn) * BASE_INSN_LENGTH")))
666 ;; Attribute describing the processor.
667 (define_enum_attr "cpu" "processor"
668 (const (symbol_ref "mips_tune")))
670 ;; The type of hardware hazard associated with this instruction.
671 ;; DELAY means that the next instruction cannot read the result
672 ;; of this one. HILO means that the next two instructions cannot
673 ;; write to HI or LO.
674 (define_attr "hazard" "none,delay,hilo"
675 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
676 (match_test "ISA_HAS_LOAD_DELAY"))
677 (const_string "delay")
679 (and (eq_attr "type" "mfc,mtc")
680 (match_test "ISA_HAS_XFER_DELAY"))
681 (const_string "delay")
683 (and (eq_attr "type" "fcmp")
684 (match_test "ISA_HAS_FCMP_DELAY"))
685 (const_string "delay")
687 ;; The r4000 multiplication patterns include an mflo instruction.
688 (and (eq_attr "type" "imul")
689 (match_test "TARGET_FIX_R4000"))
690 (const_string "hilo")
692 (and (eq_attr "type" "mfhi,mflo")
693 (not (match_test "ISA_HAS_HILO_INTERLOCKS")))
694 (const_string "hilo")]
695 (const_string "none")))
697 ;; Can the instruction be put into a delay slot?
698 (define_attr "can_delay" "no,yes"
699 (if_then_else (and (eq_attr "type" "!branch,call,jump")
700 (eq_attr "hazard" "none")
701 (match_test "get_attr_insn_count (insn) == 1"))
703 (const_string "no")))
705 ;; Attribute defining whether or not we can use the branch-likely
707 (define_attr "branch_likely" "no,yes"
708 (if_then_else (match_test "GENERATE_BRANCHLIKELY")
710 (const_string "no")))
712 ;; True if an instruction might assign to hi or lo when reloaded.
713 ;; This is used by the TUNE_MACC_CHAINS code.
714 (define_attr "may_clobber_hilo" "no,yes"
715 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthi,mtlo")
717 (const_string "no")))
719 ;; Describe a user's asm statement.
720 (define_asm_attributes
721 [(set_attr "type" "multi")
722 (set_attr "can_delay" "no")])
724 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
725 ;; from the same template.
726 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
728 ;; A copy of GPR that can be used when a pattern has two independent
730 (define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")])
732 (define_mode_iterator MOVEP1 [SI SF])
733 (define_mode_iterator MOVEP2 [SI SF])
735 ;; This mode iterator allows :HILO to be used as the mode of the
736 ;; concatenated HI and LO registers.
737 (define_mode_iterator HILO [(DI "!TARGET_64BIT") (TI "TARGET_64BIT")])
739 ;; This mode iterator allows :P to be used for patterns that operate on
740 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
741 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
743 ;; This mode iterator allows :MOVECC to be used anywhere that a
744 ;; conditional-move-type condition is needed.
745 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
746 (CC "TARGET_HARD_FLOAT
747 && !TARGET_LOONGSON_2EF
748 && !TARGET_MIPS5900")])
750 ;; 32-bit integer moves for which we provide move patterns.
751 (define_mode_iterator IMOVE32
760 (V4UQQ "TARGET_DSP")])
762 ;; 64-bit modes for which we provide move patterns.
763 (define_mode_iterator MOVE64
765 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")
766 (V2SI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
767 (V4HI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")
768 (V8QI "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS")])
770 ;; 128-bit modes for which we provide move patterns on 64-bit targets.
771 (define_mode_iterator MOVE128 [TI TF])
773 ;; This mode iterator allows the QI and HI extension patterns to be
774 ;; defined from the same template.
775 (define_mode_iterator SHORT [QI HI])
777 ;; Likewise the 64-bit truncate-and-shift patterns.
778 (define_mode_iterator SUBDI [QI HI SI])
780 ;; This mode iterator allows :ANYF to be used wherever a scalar or vector
781 ;; floating-point mode is allowed.
782 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
783 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
784 (V2SF "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT")])
786 ;; Like ANYF, but only applies to scalar modes.
787 (define_mode_iterator SCALARF [(SF "TARGET_HARD_FLOAT")
788 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
790 ;; A floating-point mode for which moves involving FPRs may need to be split.
791 (define_mode_iterator SPLITF
792 [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
793 (DI "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
794 (V2SF "!TARGET_64BIT && TARGET_PAIRED_SINGLE_FLOAT")
795 (V2SI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
796 (V4HI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
797 (V8QI "!TARGET_64BIT && TARGET_LOONGSON_VECTORS")
798 (TF "TARGET_64BIT && TARGET_FLOAT64")])
800 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
801 ;; 32-bit version and "dsubu" in the 64-bit version.
802 (define_mode_attr d [(SI "") (DI "d")
803 (QQ "") (HQ "") (SQ "") (DQ "d")
804 (UQQ "") (UHQ "") (USQ "") (UDQ "d")
805 (HA "") (SA "") (DA "d")
806 (UHA "") (USA "") (UDA "d")])
808 ;; Same as d but upper-case.
809 (define_mode_attr D [(SI "") (DI "D")
810 (QQ "") (HQ "") (SQ "") (DQ "D")
811 (UQQ "") (UHQ "") (USQ "") (UDQ "D")
812 (HA "") (SA "") (DA "D")
813 (UHA "") (USA "") (UDA "D")])
815 ;; This attribute gives the length suffix for a load or store instruction.
816 ;; The same suffixes work for zero and sign extensions.
817 (define_mode_attr size [(QI "b") (HI "h") (SI "w") (DI "d")])
818 (define_mode_attr SIZE [(QI "B") (HI "H") (SI "W") (DI "D")])
820 ;; This attributes gives the mode mask of a SHORT.
821 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
823 ;; Mode attributes for GPR loads.
824 (define_mode_attr load [(SI "lw") (DI "ld")])
825 ;; Instruction names for stores.
826 (define_mode_attr store [(QI "sb") (HI "sh") (SI "sw") (DI "sd")])
828 ;; Similarly for MIPS IV indexed FPR loads and stores.
829 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
830 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
832 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
833 ;; are different. Some forms of unextended addiu have an 8-bit immediate
834 ;; field but the equivalent daddiu has only a 5-bit field.
835 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
837 ;; This attribute gives the best constraint to use for registers of
839 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
841 ;; This attribute gives the format suffix for floating-point operations.
842 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
844 ;; This attribute gives the upper-case mode name for one unit of a
845 ;; floating-point mode.
846 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
848 ;; This attribute gives the integer mode that has the same size as a
850 (define_mode_attr IMODE [(QQ "QI") (HQ "HI") (SQ "SI") (DQ "DI")
851 (UQQ "QI") (UHQ "HI") (USQ "SI") (UDQ "DI")
852 (HA "HI") (SA "SI") (DA "DI")
853 (UHA "HI") (USA "SI") (UDA "DI")
854 (V4UQQ "SI") (V2UHQ "SI") (V2UHA "SI")
855 (V2HQ "SI") (V2HA "SI")])
857 ;; This attribute gives the integer mode that has half the size of
858 ;; the controlling mode.
859 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (V2SF "SI")
860 (V2SI "SI") (V4HI "SI") (V8QI "SI")
863 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
865 ;; In certain cases, div.s and div.ps may have a rounding error
866 ;; and/or wrong inexact flag.
868 ;; Therefore, we only allow div.s if not working around SB-1 rev2
869 ;; errata or if a slight loss of precision is OK.
870 (define_mode_attr divide_condition
871 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
872 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
874 ;; This attribute gives the conditions under which SQRT.fmt instructions
876 (define_mode_attr sqrt_condition
877 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
879 ;; This attribute gives the conditions under which RECIP.fmt and RSQRT.fmt
880 ;; instructions can be used. The MIPS32 and MIPS64 ISAs say that RECIP.D
881 ;; and RSQRT.D are unpredictable when doubles are stored in pairs of FPRs,
882 ;; so for safety's sake, we apply this restriction to all targets.
883 (define_mode_attr recip_condition
885 (DF "ISA_HAS_FP4 && TARGET_FLOAT64")
886 (V2SF "TARGET_SB1")])
888 ;; This code iterator allows signed and unsigned widening multiplications
889 ;; to use the same template.
890 (define_code_iterator any_extend [sign_extend zero_extend])
892 ;; This code iterator allows the two right shift instructions to be
893 ;; generated from the same template.
894 (define_code_iterator any_shiftrt [ashiftrt lshiftrt])
896 ;; This code iterator allows the three shift instructions to be generated
897 ;; from the same template.
898 (define_code_iterator any_shift [ashift ashiftrt lshiftrt])
900 ;; This code iterator allows unsigned and signed division to be generated
901 ;; from the same template.
902 (define_code_iterator any_div [div udiv])
904 ;; This code iterator allows unsigned and signed modulus to be generated
905 ;; from the same template.
906 (define_code_iterator any_mod [mod umod])
908 ;; This code iterator allows all native floating-point comparisons to be
909 ;; generated from the same template.
910 (define_code_iterator fcond [unordered uneq unlt unle eq lt le])
912 ;; This code iterator is used for comparisons that can be implemented
913 ;; by swapping the operands.
914 (define_code_iterator swapped_fcond [ge gt unge ungt])
916 ;; Equality operators.
917 (define_code_iterator equality_op [eq ne])
919 ;; These code iterators allow the signed and unsigned scc operations to use
920 ;; the same template.
921 (define_code_iterator any_gt [gt gtu])
922 (define_code_iterator any_ge [ge geu])
923 (define_code_iterator any_lt [lt ltu])
924 (define_code_iterator any_le [le leu])
926 (define_code_iterator any_return [return simple_return])
928 ;; <u> expands to an empty string when doing a signed operation and
929 ;; "u" when doing an unsigned operation.
930 (define_code_attr u [(sign_extend "") (zero_extend "u")
938 ;; <U> is like <u> except uppercase.
939 (define_code_attr U [(sign_extend "") (zero_extend "U")])
941 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
942 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
944 ;; <optab> expands to the name of the optab for a particular code.
945 (define_code_attr optab [(ashift "ashl")
954 (simple_return "simple_return")])
956 ;; <insn> expands to the name of the insn that implements a particular code.
957 (define_code_attr insn [(ashift "sll")
966 ;; <immediate_insn> expands to the name of the insn that implements
967 ;; a particular code to operate on immediate values.
968 (define_code_attr immediate_insn [(ior "ori")
972 (define_code_attr shift_compression [(ashift "micromips")
973 (lshiftrt "micromips")
976 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
977 (define_code_attr fcond [(unordered "un")
985 ;; Similar, but for swapped conditions.
986 (define_code_attr swapped_fcond [(ge "le")
991 ;; The value of the bit when the branch is taken for branch_bit patterns.
992 ;; Comparison is always against zero so this depends on the operator.
993 (define_code_attr bbv [(eq "0") (ne "1")])
995 ;; This is the inverse value of bbv.
996 (define_code_attr bbinv [(eq "1") (ne "0")])
998 ;; .........................
1000 ;; Branch, call and jump delay slots
1002 ;; .........................
1004 (define_delay (and (eq_attr "type" "branch")
1005 (not (match_test "TARGET_MIPS16"))
1006 (eq_attr "branch_likely" "yes"))
1007 [(eq_attr "can_delay" "yes")
1009 (eq_attr "can_delay" "yes")])
1011 ;; Branches that don't have likely variants do not annul on false.
1012 (define_delay (and (eq_attr "type" "branch")
1013 (not (match_test "TARGET_MIPS16"))
1014 (eq_attr "branch_likely" "no"))
1015 [(eq_attr "can_delay" "yes")
1019 (define_delay (eq_attr "type" "jump")
1020 [(eq_attr "can_delay" "yes")
1024 (define_delay (and (eq_attr "type" "call")
1025 (eq_attr "jal_macro" "no"))
1026 [(eq_attr "can_delay" "yes")
1030 ;; Pipeline descriptions.
1032 ;; generic.md provides a fallback for processors without a specific
1033 ;; pipeline description. It is derived from the old define_function_unit
1034 ;; version and uses the "alu" and "imuldiv" units declared below.
1036 ;; Some of the processor-specific files are also derived from old
1037 ;; define_function_unit descriptions and simply override the parts of
1038 ;; generic.md that don't apply. The other processor-specific files
1039 ;; are self-contained.
1040 (define_automaton "alu,imuldiv")
1042 (define_cpu_unit "alu" "alu")
1043 (define_cpu_unit "imuldiv" "imuldiv")
1045 ;; Ghost instructions produce no real code and introduce no hazards.
1046 ;; They exist purely to express an effect on dataflow.
1047 (define_insn_reservation "ghost" 0
1048 (eq_attr "type" "ghost")
1068 (include "10000.md")
1069 (include "loongson2ef.md")
1070 (include "loongson3a.md")
1071 (include "octeon.md")
1073 (include "sr71k.md")
1076 (include "generic.md")
1079 ;; ....................
1081 ;; CONDITIONAL TRAPS
1083 ;; ....................
1087 [(trap_if (const_int 1) (const_int 0))]
1090 if (ISA_HAS_COND_TRAP)
1091 return "teq\t$0,$0";
1092 else if (TARGET_MIPS16)
1097 [(set_attr "type" "trap")])
1099 (define_expand "ctrap<mode>4"
1100 [(trap_if (match_operator 0 "comparison_operator"
1101 [(match_operand:GPR 1 "reg_or_0_operand")
1102 (match_operand:GPR 2 "arith_operand")])
1103 (match_operand 3 "const_0_operand"))]
1106 mips_expand_conditional_trap (operands[0]);
1110 (define_insn "*conditional_trap<mode>"
1111 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1112 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1113 (match_operand:GPR 2 "arith_operand" "dI")])
1117 [(set_attr "type" "trap")])
1120 ;; ....................
1124 ;; ....................
1127 (define_insn "add<mode>3"
1128 [(set (match_operand:ANYF 0 "register_operand" "=f")
1129 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1130 (match_operand:ANYF 2 "register_operand" "f")))]
1132 "add.<fmt>\t%0,%1,%2"
1133 [(set_attr "type" "fadd")
1134 (set_attr "mode" "<UNITMODE>")])
1136 (define_expand "add<mode>3"
1137 [(set (match_operand:GPR 0 "register_operand")
1138 (plus:GPR (match_operand:GPR 1 "register_operand")
1139 (match_operand:GPR 2 "arith_operand")))]
1142 (define_insn "*add<mode>3"
1143 [(set (match_operand:GPR 0 "register_operand" "=!u,d,!u,!u,!ks,!d,d")
1144 (plus:GPR (match_operand:GPR 1 "register_operand" "!u,d,!u,!ks,!ks,0,d")
1145 (match_operand:GPR 2 "arith_operand" "!u,d,Uead,Uuw6,Uesp,Usb4,Q")))]
1148 if (which_alternative == 0
1149 || which_alternative == 1)
1150 return "<d>addu\t%0,%1,%2";
1152 return "<d>addiu\t%0,%1,%2";
1154 [(set_attr "alu_type" "add")
1155 (set_attr "compression" "micromips,*,micromips,micromips,micromips,micromips,*")
1156 (set_attr "mode" "<MODE>")])
1158 (define_insn "*add<mode>3_mips16"
1159 [(set (match_operand:GPR 0 "register_operand" "=ks,ks,d,d,d,d,d,d,d")
1160 (plus:GPR (match_operand:GPR 1 "register_operand" "ks,ks,ks,ks,0,0,d,d,d")
1161 (match_operand:GPR 2 "arith_operand" "Usd8,Q,Uuw<si8_di5>,Q,Usb<si8_di5>,Q,Usb4,O,d")))]
1173 [(set_attr "alu_type" "add")
1174 (set_attr "mode" "<MODE>")
1175 (set_attr "extended_mips16" "no,yes,no,yes,no,yes,no,yes,no")])
1177 ;; On the mips16, we can sometimes split an add of a constant which is
1178 ;; a 4 byte instruction into two adds which are both 2 byte
1179 ;; instructions. There are two cases: one where we are adding a
1180 ;; constant plus a register to another register, and one where we are
1181 ;; simply adding a constant to a register.
1184 [(set (match_operand:SI 0 "d_operand")
1185 (plus:SI (match_dup 0)
1186 (match_operand:SI 1 "const_int_operand")))]
1187 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1188 && ((INTVAL (operands[1]) > 0x7f
1189 && INTVAL (operands[1]) <= 0x7f + 0x7f)
1190 || (INTVAL (operands[1]) < - 0x80
1191 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
1192 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
1193 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1195 HOST_WIDE_INT val = INTVAL (operands[1]);
1199 operands[1] = GEN_INT (0x7f);
1200 operands[2] = GEN_INT (val - 0x7f);
1204 operands[1] = GEN_INT (- 0x80);
1205 operands[2] = GEN_INT (val + 0x80);
1210 [(set (match_operand:SI 0 "d_operand")
1211 (plus:SI (match_operand:SI 1 "d_operand")
1212 (match_operand:SI 2 "const_int_operand")))]
1213 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1214 && REGNO (operands[0]) != REGNO (operands[1])
1215 && ((INTVAL (operands[2]) > 0x7
1216 && INTVAL (operands[2]) <= 0x7 + 0x7f)
1217 || (INTVAL (operands[2]) < - 0x8
1218 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
1219 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
1220 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
1222 HOST_WIDE_INT val = INTVAL (operands[2]);
1226 operands[2] = GEN_INT (0x7);
1227 operands[3] = GEN_INT (val - 0x7);
1231 operands[2] = GEN_INT (- 0x8);
1232 operands[3] = GEN_INT (val + 0x8);
1237 [(set (match_operand:DI 0 "d_operand")
1238 (plus:DI (match_dup 0)
1239 (match_operand:DI 1 "const_int_operand")))]
1240 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1241 && ((INTVAL (operands[1]) > 0xf
1242 && INTVAL (operands[1]) <= 0xf + 0xf)
1243 || (INTVAL (operands[1]) < - 0x10
1244 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1245 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1246 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1248 HOST_WIDE_INT val = INTVAL (operands[1]);
1252 operands[1] = GEN_INT (0xf);
1253 operands[2] = GEN_INT (val - 0xf);
1257 operands[1] = GEN_INT (- 0x10);
1258 operands[2] = GEN_INT (val + 0x10);
1263 [(set (match_operand:DI 0 "d_operand")
1264 (plus:DI (match_operand:DI 1 "d_operand")
1265 (match_operand:DI 2 "const_int_operand")))]
1266 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1267 && REGNO (operands[0]) != REGNO (operands[1])
1268 && ((INTVAL (operands[2]) > 0x7
1269 && INTVAL (operands[2]) <= 0x7 + 0xf)
1270 || (INTVAL (operands[2]) < - 0x8
1271 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1272 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1273 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1275 HOST_WIDE_INT val = INTVAL (operands[2]);
1279 operands[2] = GEN_INT (0x7);
1280 operands[3] = GEN_INT (val - 0x7);
1284 operands[2] = GEN_INT (- 0x8);
1285 operands[3] = GEN_INT (val + 0x8);
1289 (define_insn "*addsi3_extended"
1290 [(set (match_operand:DI 0 "register_operand" "=d,d")
1292 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
1293 (match_operand:SI 2 "arith_operand" "d,Q"))))]
1294 "TARGET_64BIT && !TARGET_MIPS16"
1298 [(set_attr "alu_type" "add")
1299 (set_attr "mode" "SI")])
1301 ;; Split this insn so that the addiu splitters can have a crack at it.
1302 ;; Use a conservative length estimate until the split.
1303 (define_insn_and_split "*addsi3_extended_mips16"
1304 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1306 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1307 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
1308 "TARGET_64BIT && TARGET_MIPS16"
1310 "&& reload_completed"
1311 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
1312 { operands[3] = gen_lowpart (SImode, operands[0]); }
1313 [(set_attr "alu_type" "add")
1314 (set_attr "mode" "SI")
1315 (set_attr "extended_mips16" "yes")])
1317 ;; Combiner patterns for unsigned byte-add.
1319 (define_insn "*baddu_si"
1320 [(set (match_operand:SI 0 "register_operand" "=d")
1322 (plus:QI (match_operand:QI 1 "register_operand" "d")
1323 (match_operand:QI 2 "register_operand" "d"))))]
1326 [(set_attr "alu_type" "add")])
1328 (define_insn "*baddu_di<mode>"
1329 [(set (match_operand:GPR 0 "register_operand" "=d")
1331 (plus:QI (truncate:QI (match_operand:DI 1 "register_operand" "d"))
1332 (truncate:QI (match_operand:DI 2 "register_operand" "d")))))]
1333 "ISA_HAS_BADDU && TARGET_64BIT"
1335 [(set_attr "alu_type" "add")])
1338 ;; ....................
1342 ;; ....................
1345 (define_insn "sub<mode>3"
1346 [(set (match_operand:ANYF 0 "register_operand" "=f")
1347 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
1348 (match_operand:ANYF 2 "register_operand" "f")))]
1350 "sub.<fmt>\t%0,%1,%2"
1351 [(set_attr "type" "fadd")
1352 (set_attr "mode" "<UNITMODE>")])
1354 (define_insn "sub<mode>3"
1355 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
1356 (minus:GPR (match_operand:GPR 1 "register_operand" "!u,d")
1357 (match_operand:GPR 2 "register_operand" "!u,d")))]
1360 [(set_attr "alu_type" "sub")
1361 (set_attr "compression" "micromips,*")
1362 (set_attr "mode" "<MODE>")])
1364 (define_insn "*subsi3_extended"
1365 [(set (match_operand:DI 0 "register_operand" "=d")
1367 (minus:SI (match_operand:SI 1 "register_operand" "d")
1368 (match_operand:SI 2 "register_operand" "d"))))]
1371 [(set_attr "alu_type" "sub")
1372 (set_attr "mode" "DI")])
1375 ;; ....................
1379 ;; ....................
1382 (define_expand "mul<mode>3"
1383 [(set (match_operand:SCALARF 0 "register_operand")
1384 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
1385 (match_operand:SCALARF 2 "register_operand")))]
1389 (define_insn "*mul<mode>3"
1390 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1391 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1392 (match_operand:SCALARF 2 "register_operand" "f")))]
1393 "!TARGET_4300_MUL_FIX"
1394 "mul.<fmt>\t%0,%1,%2"
1395 [(set_attr "type" "fmul")
1396 (set_attr "mode" "<MODE>")])
1398 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
1399 ;; operands may corrupt immediately following multiplies. This is a
1400 ;; simple fix to insert NOPs.
1402 (define_insn "*mul<mode>3_r4300"
1403 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1404 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1405 (match_operand:SCALARF 2 "register_operand" "f")))]
1406 "TARGET_4300_MUL_FIX"
1407 "mul.<fmt>\t%0,%1,%2\;nop"
1408 [(set_attr "type" "fmul")
1409 (set_attr "mode" "<MODE>")
1410 (set_attr "insn_count" "2")])
1412 (define_insn "mulv2sf3"
1413 [(set (match_operand:V2SF 0 "register_operand" "=f")
1414 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1415 (match_operand:V2SF 2 "register_operand" "f")))]
1416 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
1418 [(set_attr "type" "fmul")
1419 (set_attr "mode" "SF")])
1421 ;; The original R4000 has a cpu bug. If a double-word or a variable
1422 ;; shift executes while an integer multiplication is in progress, the
1423 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1424 ;; with the mult on the R4000.
1426 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1427 ;; (also valid for MIPS R4000MC processors):
1429 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1430 ;; this errata description.
1431 ;; The following code sequence causes the R4000 to incorrectly
1432 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1433 ;; instruction. If the dsra32 instruction is executed during an
1434 ;; integer multiply, the dsra32 will only shift by the amount in
1435 ;; specified in the instruction rather than the amount plus 32
1437 ;; instruction 1: mult rs,rt integer multiply
1438 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1439 ;; right arithmetic + 32
1440 ;; Workaround: A dsra32 instruction placed after an integer
1441 ;; multiply should not be one of the 11 instructions after the
1442 ;; multiply instruction."
1446 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1447 ;; the following description.
1448 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1449 ;; 64-bit versions) may produce incorrect results under the
1450 ;; following conditions:
1451 ;; 1) An integer multiply is currently executing
1452 ;; 2) These types of shift instructions are executed immediately
1453 ;; following an integer divide instruction.
1455 ;; 1) Make sure no integer multiply is running wihen these
1456 ;; instruction are executed. If this cannot be predicted at
1457 ;; compile time, then insert a "mfhi" to R0 instruction
1458 ;; immediately after the integer multiply instruction. This
1459 ;; will cause the integer multiply to complete before the shift
1461 ;; 2) Separate integer divide and these two classes of shift
1462 ;; instructions by another instruction or a noop."
1464 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1467 (define_expand "mul<mode>3"
1468 [(set (match_operand:GPR 0 "register_operand")
1469 (mult:GPR (match_operand:GPR 1 "register_operand")
1470 (match_operand:GPR 2 "register_operand")))]
1475 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
1476 emit_insn (gen_mul<mode>3_mul3_loongson (operands[0], operands[1],
1478 else if (ISA_HAS_<D>MUL3)
1479 emit_insn (gen_mul<mode>3_mul3 (operands[0], operands[1], operands[2]));
1480 else if (TARGET_MIPS16)
1482 lo = gen_rtx_REG (<MODE>mode, LO_REGNUM);
1483 emit_insn (gen_mul<mode>3_internal (lo, operands[1], operands[2]));
1484 emit_move_insn (operands[0], lo);
1486 else if (TARGET_FIX_R4000)
1487 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
1490 (gen_mul<mode>3_internal (operands[0], operands[1], operands[2]));
1494 (define_insn "mul<mode>3_mul3_loongson"
1495 [(set (match_operand:GPR 0 "register_operand" "=d")
1496 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1497 (match_operand:GPR 2 "register_operand" "d")))]
1498 "TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A"
1500 if (TARGET_LOONGSON_2EF)
1501 return "<d>multu.g\t%0,%1,%2";
1503 return "gs<d>multu\t%0,%1,%2";
1505 [(set_attr "type" "imul3nc")
1506 (set_attr "mode" "<MODE>")])
1508 (define_insn "mul<mode>3_mul3"
1509 [(set (match_operand:GPR 0 "register_operand" "=d,l")
1510 (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
1511 (match_operand:GPR 2 "register_operand" "d,d")))
1512 (clobber (match_scratch:GPR 3 "=l,X"))]
1515 if (which_alternative == 1)
1516 return "<d>mult\t%1,%2";
1517 if (<MODE>mode == SImode && (TARGET_MIPS3900 || TARGET_MIPS5900))
1518 return "mult\t%0,%1,%2";
1519 return "<d>mul\t%0,%1,%2";
1521 [(set_attr "type" "imul3,imul")
1522 (set_attr "mode" "<MODE>")])
1524 ;; If a register gets allocated to LO, and we spill to memory, the reload
1525 ;; will include a move from LO to a GPR. Merge it into the multiplication
1526 ;; if it can set the GPR directly.
1529 ;; Operand 1: GPR (1st multiplication operand)
1530 ;; Operand 2: GPR (2nd multiplication operand)
1531 ;; Operand 3: GPR (destination)
1534 [(set (match_operand:SI 0 "lo_operand")
1535 (mult:SI (match_operand:SI 1 "d_operand")
1536 (match_operand:SI 2 "d_operand")))
1537 (clobber (scratch:SI))])
1538 (set (match_operand:SI 3 "d_operand")
1540 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1543 (mult:SI (match_dup 1)
1545 (clobber (match_dup 0))])])
1547 (define_insn "mul<mode>3_internal"
1548 [(set (match_operand:GPR 0 "muldiv_target_operand" "=l")
1549 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1550 (match_operand:GPR 2 "register_operand" "d")))]
1551 "ISA_HAS_<D>MULT && !TARGET_FIX_R4000"
1553 [(set_attr "type" "imul")
1554 (set_attr "mode" "<MODE>")])
1556 (define_insn "mul<mode>3_r4000"
1557 [(set (match_operand:GPR 0 "register_operand" "=d")
1558 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1559 (match_operand:GPR 2 "register_operand" "d")))
1560 (clobber (match_scratch:GPR 3 "=l"))]
1561 "ISA_HAS_<D>MULT && TARGET_FIX_R4000"
1562 "<d>mult\t%1,%2\;mflo\t%0"
1563 [(set_attr "type" "imul")
1564 (set_attr "mode" "<MODE>")
1565 (set_attr "insn_count" "2")])
1567 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1568 ;; of "mult; mflo". They have the same latency, but the first form gives
1569 ;; us an extra cycle to compute the operands.
1572 ;; Operand 1: GPR (1st multiplication operand)
1573 ;; Operand 2: GPR (2nd multiplication operand)
1574 ;; Operand 3: GPR (destination)
1576 [(set (match_operand:SI 0 "lo_operand")
1577 (mult:SI (match_operand:SI 1 "d_operand")
1578 (match_operand:SI 2 "d_operand")))
1579 (set (match_operand:SI 3 "d_operand")
1581 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1586 (plus:SI (mult:SI (match_dup 1)
1590 (plus:SI (mult:SI (match_dup 1)
1594 ;; Multiply-accumulate patterns
1596 ;; This pattern is first matched by combine, which tries to use the
1597 ;; pattern wherever it can. We don't know until later whether it
1598 ;; is actually profitable to use MADD over a "MUL; ADDIU" sequence,
1599 ;; so we need to keep both options open.
1601 ;; The second alternative has a "?" marker because it is generally
1602 ;; one instruction more costly than the first alternative. This "?"
1603 ;; marker is enough to convey the relative costs to the register
1606 ;; However, reload counts reloads of operands 4 and 5 in the same way as
1607 ;; reloads of the other operands, even though operands 4 and 5 need no
1608 ;; copy instructions. Reload therefore thinks that the second alternative
1609 ;; is two reloads more costly than the first. We add "*?*?" to the first
1610 ;; alternative as a counterweight.
1611 (define_insn "*mul_acc_si"
1612 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1613 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1614 (match_operand:SI 2 "register_operand" "d,d"))
1615 (match_operand:SI 3 "register_operand" "0,d")))
1616 (clobber (match_scratch:SI 4 "=X,l"))
1617 (clobber (match_scratch:SI 5 "=X,&d"))]
1618 "GENERATE_MADD_MSUB && !TARGET_MIPS16"
1622 [(set_attr "type" "imadd")
1623 (set_attr "accum_in" "3")
1624 (set_attr "mode" "SI")
1625 (set_attr "insn_count" "1,2")])
1627 ;; The same idea applies here. The middle alternative needs one less
1628 ;; clobber than the final alternative, so we add "*?" as a counterweight.
1629 (define_insn "*mul_acc_si_r3900"
1630 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d*?,d?")
1631 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1632 (match_operand:SI 2 "register_operand" "d,d,d"))
1633 (match_operand:SI 3 "register_operand" "0,l,d")))
1634 (clobber (match_scratch:SI 4 "=X,3,l"))
1635 (clobber (match_scratch:SI 5 "=X,X,&d"))]
1636 "TARGET_MIPS3900 && !TARGET_MIPS16"
1641 [(set_attr "type" "imadd")
1642 (set_attr "accum_in" "3")
1643 (set_attr "mode" "SI")
1644 (set_attr "insn_count" "1,1,2")])
1646 ;; Split *mul_acc_si if both the source and destination accumulator
1649 [(set (match_operand:SI 0 "d_operand")
1650 (plus:SI (mult:SI (match_operand:SI 1 "d_operand")
1651 (match_operand:SI 2 "d_operand"))
1652 (match_operand:SI 3 "d_operand")))
1653 (clobber (match_operand:SI 4 "lo_operand"))
1654 (clobber (match_operand:SI 5 "d_operand"))]
1656 [(parallel [(set (match_dup 5)
1657 (mult:SI (match_dup 1) (match_dup 2)))
1658 (clobber (match_dup 4))])
1659 (set (match_dup 0) (plus:SI (match_dup 5) (match_dup 3)))]
1662 (define_insn "*macc"
1663 [(set (match_operand:SI 0 "register_operand" "=l,d")
1664 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1665 (match_operand:SI 2 "register_operand" "d,d"))
1666 (match_operand:SI 3 "register_operand" "0,l")))
1667 (clobber (match_scratch:SI 4 "=X,3"))]
1670 if (which_alternative == 1)
1671 return "macc\t%0,%1,%2";
1672 else if (TARGET_MIPS5500)
1673 return "madd\t%1,%2";
1675 /* The VR4130 assumes that there is a two-cycle latency between a macc
1676 that "writes" to $0 and an instruction that reads from it. We avoid
1677 this by assigning to $1 instead. */
1678 return "%[macc\t%@,%1,%2%]";
1680 [(set_attr "type" "imadd")
1681 (set_attr "accum_in" "3")
1682 (set_attr "mode" "SI")])
1684 (define_insn "*msac"
1685 [(set (match_operand:SI 0 "register_operand" "=l,d")
1686 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1687 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1688 (match_operand:SI 3 "register_operand" "d,d"))))
1689 (clobber (match_scratch:SI 4 "=X,1"))]
1692 if (which_alternative == 1)
1693 return "msac\t%0,%2,%3";
1694 else if (TARGET_MIPS5500)
1695 return "msub\t%2,%3";
1697 return "msac\t$0,%2,%3";
1699 [(set_attr "type" "imadd")
1700 (set_attr "accum_in" "1")
1701 (set_attr "mode" "SI")])
1703 ;; An msac-like instruction implemented using negation and a macc.
1704 (define_insn_and_split "*msac_using_macc"
1705 [(set (match_operand:SI 0 "register_operand" "=l,d")
1706 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1707 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1708 (match_operand:SI 3 "register_operand" "d,d"))))
1709 (clobber (match_scratch:SI 4 "=X,1"))
1710 (clobber (match_scratch:SI 5 "=d,d"))]
1711 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1713 "&& reload_completed"
1715 (neg:SI (match_dup 3)))
1718 (plus:SI (mult:SI (match_dup 2)
1721 (clobber (match_dup 4))])]
1723 [(set_attr "type" "imadd")
1724 (set_attr "accum_in" "1")
1725 (set_attr "insn_count" "2")])
1727 ;; Patterns generated by the define_peephole2 below.
1729 (define_insn "*macc2"
1730 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1731 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1732 (match_operand:SI 2 "register_operand" "d"))
1734 (set (match_operand:SI 3 "register_operand" "=d")
1735 (plus:SI (mult:SI (match_dup 1)
1738 "ISA_HAS_MACC && reload_completed"
1740 [(set_attr "type" "imadd")
1741 (set_attr "accum_in" "0")
1742 (set_attr "mode" "SI")])
1744 (define_insn "*msac2"
1745 [(set (match_operand:SI 0 "muldiv_target_operand" "=l")
1746 (minus:SI (match_dup 0)
1747 (mult:SI (match_operand:SI 1 "register_operand" "d")
1748 (match_operand:SI 2 "register_operand" "d"))))
1749 (set (match_operand:SI 3 "register_operand" "=d")
1750 (minus:SI (match_dup 0)
1751 (mult:SI (match_dup 1)
1753 "ISA_HAS_MSAC && reload_completed"
1755 [(set_attr "type" "imadd")
1756 (set_attr "accum_in" "0")
1757 (set_attr "mode" "SI")])
1759 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1763 ;; Operand 1: macc/msac
1764 ;; Operand 2: GPR (destination)
1767 [(set (match_operand:SI 0 "lo_operand")
1768 (match_operand:SI 1 "macc_msac_operand"))
1769 (clobber (scratch:SI))])
1770 (set (match_operand:SI 2 "d_operand")
1773 [(parallel [(set (match_dup 0)
1778 ;; When we have a three-address multiplication instruction, it should
1779 ;; be faster to do a separate multiply and add, rather than moving
1780 ;; something into LO in order to use a macc instruction.
1782 ;; This peephole needs a scratch register to cater for the case when one
1783 ;; of the multiplication operands is the same as the destination.
1785 ;; Operand 0: GPR (scratch)
1787 ;; Operand 2: GPR (addend)
1788 ;; Operand 3: GPR (destination)
1789 ;; Operand 4: macc/msac
1790 ;; Operand 5: new multiplication
1791 ;; Operand 6: new addition/subtraction
1793 [(match_scratch:SI 0 "d")
1794 (set (match_operand:SI 1 "lo_operand")
1795 (match_operand:SI 2 "d_operand"))
1798 [(set (match_operand:SI 3 "d_operand")
1799 (match_operand:SI 4 "macc_msac_operand"))
1800 (clobber (match_dup 1))])]
1801 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[1])"
1802 [(parallel [(set (match_dup 0)
1804 (clobber (match_dup 1))])
1808 operands[5] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1809 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1810 operands[2], operands[0]);
1813 ;; Same as above, except LO is the initial target of the macc.
1815 ;; Operand 0: GPR (scratch)
1817 ;; Operand 2: GPR (addend)
1818 ;; Operand 3: macc/msac
1819 ;; Operand 4: GPR (destination)
1820 ;; Operand 5: new multiplication
1821 ;; Operand 6: new addition/subtraction
1823 [(match_scratch:SI 0 "d")
1824 (set (match_operand:SI 1 "lo_operand")
1825 (match_operand:SI 2 "d_operand"))
1829 (match_operand:SI 3 "macc_msac_operand"))
1830 (clobber (scratch:SI))])
1832 (set (match_operand:SI 4 "d_operand")
1834 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1835 [(parallel [(set (match_dup 0)
1837 (clobber (match_dup 1))])
1841 operands[5] = XEXP (operands[3], GET_CODE (operands[3]) == PLUS ? 0 : 1);
1842 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
1843 operands[2], operands[0]);
1846 ;; See the comment above *mul_add_si for details.
1847 (define_insn "*mul_sub_si"
1848 [(set (match_operand:SI 0 "register_operand" "=l*?*?,d?")
1849 (minus:SI (match_operand:SI 1 "register_operand" "0,d")
1850 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1851 (match_operand:SI 3 "register_operand" "d,d"))))
1852 (clobber (match_scratch:SI 4 "=X,l"))
1853 (clobber (match_scratch:SI 5 "=X,&d"))]
1854 "GENERATE_MADD_MSUB"
1858 [(set_attr "type" "imadd")
1859 (set_attr "accum_in" "1")
1860 (set_attr "mode" "SI")
1861 (set_attr "insn_count" "1,2")])
1863 ;; Split *mul_sub_si if both the source and destination accumulator
1866 [(set (match_operand:SI 0 "d_operand")
1867 (minus:SI (match_operand:SI 1 "d_operand")
1868 (mult:SI (match_operand:SI 2 "d_operand")
1869 (match_operand:SI 3 "d_operand"))))
1870 (clobber (match_operand:SI 4 "lo_operand"))
1871 (clobber (match_operand:SI 5 "d_operand"))]
1873 [(parallel [(set (match_dup 5)
1874 (mult:SI (match_dup 2) (match_dup 3)))
1875 (clobber (match_dup 4))])
1876 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 5)))]
1879 (define_insn "*muls"
1880 [(set (match_operand:SI 0 "register_operand" "=l,d")
1881 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1882 (match_operand:SI 2 "register_operand" "d,d"))))
1883 (clobber (match_scratch:SI 3 "=X,l"))]
1888 [(set_attr "type" "imul,imul3")
1889 (set_attr "mode" "SI")])
1891 (define_expand "<u>mulsidi3"
1892 [(set (match_operand:DI 0 "register_operand")
1893 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1894 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1895 "mips_mulsidi3_gen_fn (<CODE>) != NULL"
1897 mulsidi3_gen_fn fn = mips_mulsidi3_gen_fn (<CODE>);
1898 emit_insn (fn (operands[0], operands[1], operands[2]));
1902 (define_expand "<u>mulsidi3_32bit_mips16"
1903 [(set (match_operand:DI 0 "register_operand")
1904 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1905 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1906 "!TARGET_64BIT && TARGET_MIPS16"
1910 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
1911 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
1912 emit_move_insn (operands[0], hilo);
1916 ;; As well as being named patterns, these instructions are used by the
1917 ;; __builtin_mips_mult<u>() functions. We must always make those functions
1918 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
1919 (define_insn "<u>mulsidi3_32bit"
1920 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
1921 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1922 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1923 "!TARGET_64BIT && (!TARGET_FIX_R4000 || ISA_HAS_DSP)"
1925 if (ISA_HAS_DSP_MULT)
1926 return "mult<u>\t%q0,%1,%2";
1928 return "mult<u>\t%1,%2";
1930 [(set_attr "type" "imul")
1931 (set_attr "mode" "SI")])
1933 (define_insn "<u>mulsidi3_32bit_r4000"
1934 [(set (match_operand:DI 0 "register_operand" "=d")
1935 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1936 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1937 (clobber (match_scratch:DI 3 "=x"))]
1938 "!TARGET_64BIT && TARGET_FIX_R4000 && !ISA_HAS_DSP"
1939 "mult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
1940 [(set_attr "type" "imul")
1941 (set_attr "mode" "SI")
1942 (set_attr "insn_count" "3")])
1944 (define_insn_and_split "<u>mulsidi3_64bit"
1945 [(set (match_operand:DI 0 "register_operand" "=d")
1946 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1947 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1948 (clobber (match_scratch:TI 3 "=x"))
1949 (clobber (match_scratch:DI 4 "=d"))]
1950 "TARGET_64BIT && !TARGET_FIX_R4000 && !ISA_HAS_DMUL3 && !TARGET_MIPS16"
1952 "&& reload_completed"
1955 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1956 operands[2], operands[4]));
1959 [(set_attr "type" "imul")
1960 (set_attr "mode" "SI")
1961 (set (attr "insn_count")
1962 (if_then_else (match_test "ISA_HAS_EXT_INS")
1966 (define_expand "<u>mulsidi3_64bit_mips16"
1967 [(set (match_operand:DI 0 "register_operand")
1968 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1969 (any_extend:DI (match_operand:SI 2 "register_operand"))))]
1970 "TARGET_64BIT && TARGET_MIPS16"
1972 emit_insn (gen_<u>mulsidi3_64bit_split (operands[0], operands[1],
1973 operands[2], gen_reg_rtx (DImode)));
1977 (define_expand "<u>mulsidi3_64bit_split"
1978 [(set (match_operand:DI 0 "register_operand")
1979 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1980 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1981 (clobber (match_operand:DI 3 "register_operand"))]
1986 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
1987 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
1989 emit_move_insn (operands[0], gen_rtx_REG (DImode, LO_REGNUM));
1990 emit_insn (gen_mfhidi_ti (operands[3], hilo));
1992 if (ISA_HAS_EXT_INS)
1993 emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32),
1997 /* Zero-extend the low part. */
1998 mips_emit_binary (ASHIFT, operands[0], operands[0], GEN_INT (32));
1999 mips_emit_binary (LSHIFTRT, operands[0], operands[0], GEN_INT (32));
2001 /* Shift the high part into place. */
2002 mips_emit_binary (ASHIFT, operands[3], operands[3], GEN_INT (32));
2004 /* OR the two halves together. */
2005 mips_emit_binary (IOR, operands[0], operands[0], operands[3]);
2010 (define_insn "<u>mulsidi3_64bit_hilo"
2011 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2014 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2015 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))]
2017 "TARGET_64BIT && !TARGET_FIX_R4000"
2019 [(set_attr "type" "imul")
2020 (set_attr "mode" "SI")])
2022 ;; See comment before the ISA_HAS_DMUL3 case in mips_mulsidi3_gen_fn.
2023 (define_insn "mulsidi3_64bit_dmul"
2024 [(set (match_operand:DI 0 "register_operand" "=d")
2025 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2026 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2027 (clobber (match_scratch:DI 3 "=l"))]
2030 [(set_attr "type" "imul3")
2031 (set_attr "mode" "DI")])
2033 ;; Widening multiply with negation.
2034 (define_insn "*muls<u>_di"
2035 [(set (match_operand:DI 0 "muldiv_target_operand" "=x")
2038 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2039 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2040 "!TARGET_64BIT && ISA_HAS_MULS"
2042 [(set_attr "type" "imul")
2043 (set_attr "mode" "SI")])
2045 ;; As well as being named patterns, these instructions are used by the
2046 ;; __builtin_mips_msub<u>() functions. We must always make those functions
2047 ;; available if !TARGET_64BIT && ISA_HAS_DSP.
2049 ;; This leads to a slight inconsistency. We honor any tuning overrides
2050 ;; in GENERATE_MADD_MSUB for -mno-dsp, but always ignore them for -mdsp,
2051 ;; even if !ISA_HAS_DSP_MULT.
2052 (define_insn "<u>msubsidi4"
2053 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2055 (match_operand:DI 3 "muldiv_target_operand" "0")
2057 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2058 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
2059 "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
2061 if (ISA_HAS_DSP_MULT)
2062 return "msub<u>\t%q0,%1,%2";
2063 else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
2064 return "msub<u>\t%1,%2";
2066 return "msac<u>\t$0,%1,%2";
2068 [(set_attr "type" "imadd")
2069 (set_attr "accum_in" "3")
2070 (set_attr "mode" "SI")])
2072 ;; _highpart patterns
2074 (define_expand "<su>mulsi3_highpart"
2075 [(set (match_operand:SI 0 "register_operand")
2078 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2079 (any_extend:DI (match_operand:SI 2 "register_operand")))
2084 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
2087 else if (TARGET_MIPS16)
2088 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2091 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
2096 (define_insn_and_split "<su>mulsi3_highpart_internal"
2097 [(set (match_operand:SI 0 "register_operand" "=d")
2100 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2101 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2103 (clobber (match_scratch:SI 3 "=l"))]
2104 "!ISA_HAS_MULHI && !TARGET_MIPS16"
2105 { return TARGET_FIX_R4000 ? "mult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2106 "&& reload_completed && !TARGET_FIX_R4000"
2109 emit_insn (gen_<su>mulsi3_highpart_split (operands[0], operands[1],
2113 [(set_attr "type" "imul")
2114 (set_attr "mode" "SI")
2115 (set_attr "insn_count" "2")])
2117 (define_expand "<su>mulsi3_highpart_split"
2118 [(set (match_operand:SI 0 "register_operand")
2121 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
2122 (any_extend:DI (match_operand:SI 2 "register_operand")))
2130 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2131 emit_insn (gen_<u>mulsidi3_64bit_hilo (hilo, operands[1], operands[2]));
2132 emit_insn (gen_mfhisi_ti (operands[0], hilo));
2136 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2137 emit_insn (gen_<u>mulsidi3_32bit (hilo, operands[1], operands[2]));
2138 emit_insn (gen_mfhisi_di (operands[0], hilo));
2143 (define_insn "<su>mulsi3_highpart_mulhi_internal"
2144 [(set (match_operand:SI 0 "register_operand" "=d")
2148 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2149 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2151 (clobber (match_scratch:SI 3 "=l"))]
2153 "mulhi<u>\t%0,%1,%2"
2154 [(set_attr "type" "imul3")
2155 (set_attr "mode" "SI")])
2157 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
2158 [(set (match_operand:SI 0 "register_operand" "=d")
2163 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2164 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
2166 (clobber (match_scratch:SI 3 "=l"))]
2168 "mulshi<u>\t%0,%1,%2"
2169 [(set_attr "type" "imul3")
2170 (set_attr "mode" "SI")])
2172 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
2173 ;; errata MD(0), which says that dmultu does not always produce the
2175 (define_expand "<su>muldi3_highpart"
2176 [(set (match_operand:DI 0 "register_operand")
2179 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2180 (any_extend:TI (match_operand:DI 2 "register_operand")))
2182 "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2185 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2188 emit_insn (gen_<su>muldi3_highpart_internal (operands[0], operands[1],
2193 (define_insn_and_split "<su>muldi3_highpart_internal"
2194 [(set (match_operand:DI 0 "register_operand" "=d")
2197 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2198 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
2200 (clobber (match_scratch:DI 3 "=l"))]
2203 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2204 { return TARGET_FIX_R4000 ? "dmult<u>\t%1,%2\n\tmfhi\t%0" : "#"; }
2205 "&& reload_completed && !TARGET_FIX_R4000"
2208 emit_insn (gen_<su>muldi3_highpart_split (operands[0], operands[1],
2212 [(set_attr "type" "imul")
2213 (set_attr "mode" "DI")
2214 (set_attr "insn_count" "2")])
2216 (define_expand "<su>muldi3_highpart_split"
2217 [(set (match_operand:DI 0 "register_operand")
2220 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2221 (any_extend:TI (match_operand:DI 2 "register_operand")))
2227 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2228 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2229 emit_insn (gen_mfhidi_ti (operands[0], hilo));
2233 (define_expand "<u>mulditi3"
2234 [(set (match_operand:TI 0 "register_operand")
2235 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand"))
2236 (any_extend:TI (match_operand:DI 2 "register_operand"))))]
2237 "ISA_HAS_DMULT && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2243 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2244 emit_insn (gen_<u>mulditi3_internal (hilo, operands[1], operands[2]));
2245 emit_move_insn (operands[0], hilo);
2247 else if (TARGET_FIX_R4000)
2248 emit_insn (gen_<u>mulditi3_r4000 (operands[0], operands[1], operands[2]));
2250 emit_insn (gen_<u>mulditi3_internal (operands[0], operands[1],
2255 (define_insn "<u>mulditi3_internal"
2256 [(set (match_operand:TI 0 "muldiv_target_operand" "=x")
2257 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2258 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))]
2260 && !TARGET_FIX_R4000
2261 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2263 [(set_attr "type" "imul")
2264 (set_attr "mode" "DI")])
2266 (define_insn "<u>mulditi3_r4000"
2267 [(set (match_operand:TI 0 "register_operand" "=d")
2268 (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
2269 (any_extend:TI (match_operand:DI 2 "register_operand" "d"))))
2270 (clobber (match_scratch:TI 3 "=x"))]
2273 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
2274 "dmult<u>\t%1,%2\;mflo\t%L0\;mfhi\t%M0"
2275 [(set_attr "type" "imul")
2276 (set_attr "mode" "DI")
2277 (set_attr "insn_count" "3")])
2279 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
2280 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
2282 (define_insn "madsi"
2283 [(set (match_operand:SI 0 "register_operand" "+l")
2284 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2285 (match_operand:SI 2 "register_operand" "d"))
2289 [(set_attr "type" "imadd")
2290 (set_attr "accum_in" "0")
2291 (set_attr "mode" "SI")])
2293 ;; See the comment above <u>msubsidi4 for the relationship between
2294 ;; ISA_HAS_DSP and ISA_HAS_DSP_MULT.
2295 (define_insn "<u>maddsidi4"
2296 [(set (match_operand:DI 0 "muldiv_target_operand" "=ka")
2298 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
2299 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
2300 (match_operand:DI 3 "muldiv_target_operand" "0")))]
2301 "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
2305 return "mad<u>\t%1,%2";
2306 else if (ISA_HAS_DSP_MULT)
2307 return "madd<u>\t%q0,%1,%2";
2308 else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
2309 return "madd<u>\t%1,%2";
2311 /* See comment in *macc. */
2312 return "%[macc<u>\t%@,%1,%2%]";
2314 [(set_attr "type" "imadd")
2315 (set_attr "accum_in" "3")
2316 (set_attr "mode" "SI")])
2318 ;; Floating point multiply accumulate instructions.
2320 (define_insn "*madd4<mode>"
2321 [(set (match_operand:ANYF 0 "register_operand" "=f")
2322 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2323 (match_operand:ANYF 2 "register_operand" "f"))
2324 (match_operand:ANYF 3 "register_operand" "f")))]
2325 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2326 "madd.<fmt>\t%0,%3,%1,%2"
2327 [(set_attr "type" "fmadd")
2328 (set_attr "accum_in" "3")
2329 (set_attr "mode" "<UNITMODE>")])
2331 (define_insn "*madd3<mode>"
2332 [(set (match_operand:ANYF 0 "register_operand" "=f")
2333 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2334 (match_operand:ANYF 2 "register_operand" "f"))
2335 (match_operand:ANYF 3 "register_operand" "0")))]
2336 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2337 "madd.<fmt>\t%0,%1,%2"
2338 [(set_attr "type" "fmadd")
2339 (set_attr "accum_in" "3")
2340 (set_attr "mode" "<UNITMODE>")])
2342 (define_insn "*msub4<mode>"
2343 [(set (match_operand:ANYF 0 "register_operand" "=f")
2344 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2345 (match_operand:ANYF 2 "register_operand" "f"))
2346 (match_operand:ANYF 3 "register_operand" "f")))]
2347 "ISA_HAS_FP_MADD4_MSUB4 && TARGET_FUSED_MADD"
2348 "msub.<fmt>\t%0,%3,%1,%2"
2349 [(set_attr "type" "fmadd")
2350 (set_attr "accum_in" "3")
2351 (set_attr "mode" "<UNITMODE>")])
2353 (define_insn "*msub3<mode>"
2354 [(set (match_operand:ANYF 0 "register_operand" "=f")
2355 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2356 (match_operand:ANYF 2 "register_operand" "f"))
2357 (match_operand:ANYF 3 "register_operand" "0")))]
2358 "ISA_HAS_FP_MADD3_MSUB3 && TARGET_FUSED_MADD"
2359 "msub.<fmt>\t%0,%1,%2"
2360 [(set_attr "type" "fmadd")
2361 (set_attr "accum_in" "3")
2362 (set_attr "mode" "<UNITMODE>")])
2364 (define_insn "*nmadd4<mode>"
2365 [(set (match_operand:ANYF 0 "register_operand" "=f")
2366 (neg:ANYF (plus:ANYF
2367 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2368 (match_operand:ANYF 2 "register_operand" "f"))
2369 (match_operand:ANYF 3 "register_operand" "f"))))]
2370 "ISA_HAS_NMADD4_NMSUB4
2371 && TARGET_FUSED_MADD
2372 && HONOR_SIGNED_ZEROS (<MODE>mode)
2373 && !HONOR_NANS (<MODE>mode)"
2374 "nmadd.<fmt>\t%0,%3,%1,%2"
2375 [(set_attr "type" "fmadd")
2376 (set_attr "accum_in" "3")
2377 (set_attr "mode" "<UNITMODE>")])
2379 (define_insn "*nmadd3<mode>"
2380 [(set (match_operand:ANYF 0 "register_operand" "=f")
2381 (neg:ANYF (plus:ANYF
2382 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
2383 (match_operand:ANYF 2 "register_operand" "f"))
2384 (match_operand:ANYF 3 "register_operand" "0"))))]
2385 "ISA_HAS_NMADD3_NMSUB3
2386 && TARGET_FUSED_MADD
2387 && HONOR_SIGNED_ZEROS (<MODE>mode)
2388 && !HONOR_NANS (<MODE>mode)"
2389 "nmadd.<fmt>\t%0,%1,%2"
2390 [(set_attr "type" "fmadd")
2391 (set_attr "accum_in" "3")
2392 (set_attr "mode" "<UNITMODE>")])
2394 (define_insn "*nmadd4<mode>_fastmath"
2395 [(set (match_operand:ANYF 0 "register_operand" "=f")
2397 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2398 (match_operand:ANYF 2 "register_operand" "f"))
2399 (match_operand:ANYF 3 "register_operand" "f")))]
2400 "ISA_HAS_NMADD4_NMSUB4
2401 && TARGET_FUSED_MADD
2402 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2403 && !HONOR_NANS (<MODE>mode)"
2404 "nmadd.<fmt>\t%0,%3,%1,%2"
2405 [(set_attr "type" "fmadd")
2406 (set_attr "accum_in" "3")
2407 (set_attr "mode" "<UNITMODE>")])
2409 (define_insn "*nmadd3<mode>_fastmath"
2410 [(set (match_operand:ANYF 0 "register_operand" "=f")
2412 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
2413 (match_operand:ANYF 2 "register_operand" "f"))
2414 (match_operand:ANYF 3 "register_operand" "0")))]
2415 "ISA_HAS_NMADD3_NMSUB3
2416 && TARGET_FUSED_MADD
2417 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2418 && !HONOR_NANS (<MODE>mode)"
2419 "nmadd.<fmt>\t%0,%1,%2"
2420 [(set_attr "type" "fmadd")
2421 (set_attr "accum_in" "3")
2422 (set_attr "mode" "<UNITMODE>")])
2424 (define_insn "*nmsub4<mode>"
2425 [(set (match_operand:ANYF 0 "register_operand" "=f")
2426 (neg:ANYF (minus:ANYF
2427 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2428 (match_operand:ANYF 3 "register_operand" "f"))
2429 (match_operand:ANYF 1 "register_operand" "f"))))]
2430 "ISA_HAS_NMADD4_NMSUB4
2431 && TARGET_FUSED_MADD
2432 && HONOR_SIGNED_ZEROS (<MODE>mode)
2433 && !HONOR_NANS (<MODE>mode)"
2434 "nmsub.<fmt>\t%0,%1,%2,%3"
2435 [(set_attr "type" "fmadd")
2436 (set_attr "accum_in" "1")
2437 (set_attr "mode" "<UNITMODE>")])
2439 (define_insn "*nmsub3<mode>"
2440 [(set (match_operand:ANYF 0 "register_operand" "=f")
2441 (neg:ANYF (minus:ANYF
2442 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2443 (match_operand:ANYF 3 "register_operand" "f"))
2444 (match_operand:ANYF 1 "register_operand" "0"))))]
2445 "ISA_HAS_NMADD3_NMSUB3
2446 && TARGET_FUSED_MADD
2447 && HONOR_SIGNED_ZEROS (<MODE>mode)
2448 && !HONOR_NANS (<MODE>mode)"
2449 "nmsub.<fmt>\t%0,%1,%2"
2450 [(set_attr "type" "fmadd")
2451 (set_attr "accum_in" "1")
2452 (set_attr "mode" "<UNITMODE>")])
2454 (define_insn "*nmsub4<mode>_fastmath"
2455 [(set (match_operand:ANYF 0 "register_operand" "=f")
2457 (match_operand:ANYF 1 "register_operand" "f")
2458 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2459 (match_operand:ANYF 3 "register_operand" "f"))))]
2460 "ISA_HAS_NMADD4_NMSUB4
2461 && TARGET_FUSED_MADD
2462 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2463 && !HONOR_NANS (<MODE>mode)"
2464 "nmsub.<fmt>\t%0,%1,%2,%3"
2465 [(set_attr "type" "fmadd")
2466 (set_attr "accum_in" "1")
2467 (set_attr "mode" "<UNITMODE>")])
2469 (define_insn "*nmsub3<mode>_fastmath"
2470 [(set (match_operand:ANYF 0 "register_operand" "=f")
2472 (match_operand:ANYF 1 "register_operand" "f")
2473 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
2474 (match_operand:ANYF 3 "register_operand" "0"))))]
2475 "ISA_HAS_NMADD3_NMSUB3
2476 && TARGET_FUSED_MADD
2477 && !HONOR_SIGNED_ZEROS (<MODE>mode)
2478 && !HONOR_NANS (<MODE>mode)"
2479 "nmsub.<fmt>\t%0,%1,%2"
2480 [(set_attr "type" "fmadd")
2481 (set_attr "accum_in" "1")
2482 (set_attr "mode" "<UNITMODE>")])
2485 ;; ....................
2487 ;; DIVISION and REMAINDER
2489 ;; ....................
2492 (define_expand "div<mode>3"
2493 [(set (match_operand:ANYF 0 "register_operand")
2494 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
2495 (match_operand:ANYF 2 "register_operand")))]
2496 "<divide_condition>"
2498 if (const_1_operand (operands[1], <MODE>mode))
2499 if (!(<recip_condition> && flag_unsafe_math_optimizations))
2500 operands[1] = force_reg (<MODE>mode, operands[1]);
2503 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
2505 ;; If an mfc1 or dmfc1 happens to access the floating point register
2506 ;; file at the same time a long latency operation (div, sqrt, recip,
2507 ;; sqrt) iterates an intermediate result back through the floating
2508 ;; point register file bypass, then instead returning the correct
2509 ;; register value the mfc1 or dmfc1 operation returns the intermediate
2510 ;; result of the long latency operation.
2512 ;; The workaround is to insert an unconditional 'mov' from/to the
2513 ;; long latency op destination register.
2515 (define_insn "*div<mode>3"
2516 [(set (match_operand:ANYF 0 "register_operand" "=f")
2517 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
2518 (match_operand:ANYF 2 "register_operand" "f")))]
2519 "<divide_condition>"
2522 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
2524 return "div.<fmt>\t%0,%1,%2";
2526 [(set_attr "type" "fdiv")
2527 (set_attr "mode" "<UNITMODE>")
2528 (set (attr "insn_count")
2529 (if_then_else (match_test "TARGET_FIX_SB1")
2533 (define_insn "*recip<mode>3"
2534 [(set (match_operand:ANYF 0 "register_operand" "=f")
2535 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2536 (match_operand:ANYF 2 "register_operand" "f")))]
2537 "<recip_condition> && flag_unsafe_math_optimizations"
2540 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2542 return "recip.<fmt>\t%0,%2";
2544 [(set_attr "type" "frdiv")
2545 (set_attr "mode" "<UNITMODE>")
2546 (set (attr "insn_count")
2547 (if_then_else (match_test "TARGET_FIX_SB1")
2551 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
2552 ;; with negative operands. We use special libgcc functions instead.
2554 ;; Expand generates divmod instructions for individual division and modulus
2555 ;; operations. We then rely on CSE to reuse earlier divmods where possible.
2556 ;; This means that, when generating MIPS16 code, it is better not to expose
2557 ;; the fixed LO register until after CSE has finished. However, it's still
2558 ;; better to split before register allocation, so that we don't allocate
2559 ;; one of the scarce MIPS16 registers to an unused result.
2560 (define_insn_and_split "divmod<mode>4"
2561 [(set (match_operand:GPR 0 "register_operand" "=kl")
2562 (div:GPR (match_operand:GPR 1 "register_operand" "d")
2563 (match_operand:GPR 2 "register_operand" "d")))
2564 (set (match_operand:GPR 3 "register_operand" "=d")
2565 (mod:GPR (match_dup 1)
2567 "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
2569 "&& ((TARGET_MIPS16 && cse_not_expected) || reload_completed)"
2572 emit_insn (gen_divmod<mode>4_split (operands[3], operands[1], operands[2]));
2574 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2577 [(set_attr "type" "idiv")
2578 (set_attr "mode" "<MODE>")
2579 ;; Worst case for MIPS16.
2580 (set_attr "insn_count" "3")])
2582 ;; See the comment above "divmod<mode>4" for the MIPS16 handling.
2583 (define_insn_and_split "udivmod<mode>4"
2584 [(set (match_operand:GPR 0 "register_operand" "=kl")
2585 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
2586 (match_operand:GPR 2 "register_operand" "d")))
2587 (set (match_operand:GPR 3 "register_operand" "=d")
2588 (umod:GPR (match_dup 1)
2592 "(TARGET_MIPS16 && cse_not_expected) || reload_completed"
2595 emit_insn (gen_udivmod<mode>4_split (operands[3], operands[1], operands[2]));
2597 emit_move_insn (operands[0], gen_rtx_REG (<MODE>mode, LO_REGNUM));
2600 [(set_attr "type" "idiv")
2601 (set_attr "mode" "<MODE>")
2602 ;; Worst case for MIPS16.
2603 (set_attr "insn_count" "3")])
2605 (define_expand "<u>divmod<mode>4_split"
2606 [(set (match_operand:GPR 0 "register_operand")
2607 (any_mod:GPR (match_operand:GPR 1 "register_operand")
2608 (match_operand:GPR 2 "register_operand")))]
2615 hilo = gen_rtx_REG (TImode, MD_REG_FIRST);
2616 emit_insn (gen_<u>divmod<mode>4_hilo_ti (hilo, operands[1],
2618 emit_insn (gen_mfhi<mode>_ti (operands[0], hilo));
2622 hilo = gen_rtx_REG (DImode, MD_REG_FIRST);
2623 emit_insn (gen_<u>divmod<mode>4_hilo_di (hilo, operands[1],
2625 emit_insn (gen_mfhi<mode>_di (operands[0], hilo));
2630 (define_insn "<u>divmod<GPR:mode>4_hilo_<HILO:mode>"
2631 [(set (match_operand:HILO 0 "muldiv_target_operand" "=x")
2633 [(any_div:GPR (match_operand:GPR 1 "register_operand" "d")
2634 (match_operand:GPR 2 "register_operand" "d"))]
2636 "ISA_HAS_<GPR:D>DIV"
2637 { return mips_output_division ("<GPR:d>div<u>\t%.,%1,%2", operands); }
2638 [(set_attr "type" "idiv")
2639 (set_attr "mode" "<GPR:MODE>")])
2642 ;; ....................
2646 ;; ....................
2648 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
2649 ;; "*div[sd]f3" comment for details).
2651 (define_insn "sqrt<mode>2"
2652 [(set (match_operand:ANYF 0 "register_operand" "=f")
2653 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2657 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
2659 return "sqrt.<fmt>\t%0,%1";
2661 [(set_attr "type" "fsqrt")
2662 (set_attr "mode" "<UNITMODE>")
2663 (set (attr "insn_count")
2664 (if_then_else (match_test "TARGET_FIX_SB1")
2668 (define_insn "*rsqrt<mode>a"
2669 [(set (match_operand:ANYF 0 "register_operand" "=f")
2670 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2671 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
2672 "<recip_condition> && flag_unsafe_math_optimizations"
2675 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2677 return "rsqrt.<fmt>\t%0,%2";
2679 [(set_attr "type" "frsqrt")
2680 (set_attr "mode" "<UNITMODE>")
2681 (set (attr "insn_count")
2682 (if_then_else (match_test "TARGET_FIX_SB1")
2686 (define_insn "*rsqrt<mode>b"
2687 [(set (match_operand:ANYF 0 "register_operand" "=f")
2688 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2689 (match_operand:ANYF 2 "register_operand" "f"))))]
2690 "<recip_condition> && flag_unsafe_math_optimizations"
2693 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2695 return "rsqrt.<fmt>\t%0,%2";
2697 [(set_attr "type" "frsqrt")
2698 (set_attr "mode" "<UNITMODE>")
2699 (set (attr "insn_count")
2700 (if_then_else (match_test "TARGET_FIX_SB1")
2705 ;; ....................
2709 ;; ....................
2711 ;; Do not use the integer abs macro instruction, since that signals an
2712 ;; exception on -2147483648 (sigh).
2714 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2715 ;; invalid; it does not clear their sign bits. We therefore can't use
2716 ;; abs.fmt if the signs of NaNs matter.
2718 (define_insn "abs<mode>2"
2719 [(set (match_operand:ANYF 0 "register_operand" "=f")
2720 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2721 "!HONOR_NANS (<MODE>mode)"
2723 [(set_attr "type" "fabs")
2724 (set_attr "mode" "<UNITMODE>")])
2727 ;; ...................
2729 ;; Count leading zeroes.
2731 ;; ...................
2734 (define_insn "clz<mode>2"
2735 [(set (match_operand:GPR 0 "register_operand" "=d")
2736 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2739 [(set_attr "type" "clz")
2740 (set_attr "mode" "<MODE>")])
2743 ;; ...................
2745 ;; Count number of set bits.
2747 ;; ...................
2750 (define_insn "popcount<mode>2"
2751 [(set (match_operand:GPR 0 "register_operand" "=d")
2752 (popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
2755 [(set_attr "type" "pop")
2756 (set_attr "mode" "<MODE>")])
2758 ;; The POP instruction is special as it does not take into account the upper
2759 ;; 32bits and is documented that way.
2760 (define_insn "*popcountdi2_trunc"
2761 [(set (match_operand:SI 0 "register_operand" "=d")
2762 (popcount:SI (truncate:SI (match_operand:DI 1 "register_operand" "d"))))]
2763 "ISA_HAS_POP && TARGET_64BIT"
2765 [(set_attr "type" "pop")
2766 (set_attr "mode" "SI")])
2769 ;; ....................
2771 ;; NEGATION and ONE'S COMPLEMENT
2773 ;; ....................
2775 (define_insn "negsi2"
2776 [(set (match_operand:SI 0 "register_operand" "=d")
2777 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2781 return "neg\t%0,%1";
2783 return "subu\t%0,%.,%1";
2785 [(set_attr "alu_type" "sub")
2786 (set_attr "mode" "SI")])
2788 (define_insn "negdi2"
2789 [(set (match_operand:DI 0 "register_operand" "=d")
2790 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2791 "TARGET_64BIT && !TARGET_MIPS16"
2793 [(set_attr "alu_type" "sub")
2794 (set_attr "mode" "DI")])
2796 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2797 ;; invalid; it does not flip their sign bit. We therefore can't use
2798 ;; neg.fmt if the signs of NaNs matter.
2800 (define_insn "neg<mode>2"
2801 [(set (match_operand:ANYF 0 "register_operand" "=f")
2802 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2803 "!HONOR_NANS (<MODE>mode)"
2805 [(set_attr "type" "fneg")
2806 (set_attr "mode" "<UNITMODE>")])
2808 (define_insn "one_cmpl<mode>2"
2809 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
2810 (not:GPR (match_operand:GPR 1 "register_operand" "!u,d")))]
2814 return "not\t%0,%1";
2816 return "nor\t%0,%.,%1";
2818 [(set_attr "alu_type" "not")
2819 (set_attr "compression" "micromips,*")
2820 (set_attr "mode" "<MODE>")])
2823 ;; ....................
2827 ;; ....................
2830 ;; Many of these instructions use trivial define_expands, because we
2831 ;; want to use a different set of constraints when TARGET_MIPS16.
2833 (define_expand "and<mode>3"
2834 [(set (match_operand:GPR 0 "register_operand")
2835 (and:GPR (match_operand:GPR 1 "register_operand")
2836 (match_operand:GPR 2 "and_reg_operand")))])
2838 ;; The middle-end is not allowed to convert ANDing with 0xffff_ffff into a
2839 ;; zero_extendsidi2 because of TRULY_NOOP_TRUNCATION, so handle these here.
2840 ;; Note that this variant does not trigger for SI mode because we require
2841 ;; a 64-bit HOST_WIDE_INT and 0xffff_ffff wouldn't be a canonical
2842 ;; sign-extended SImode value.
2844 ;; These are possible combinations for operand 1 and 2. The table
2845 ;; includes both MIPS and MIPS16 cases. (r=register, mem=memory,
2846 ;; 16=MIPS16, x=match, S=split):
2848 ;; \ op1 r/EXT r/!EXT mem r/16 mem/16
2854 ;; 0xffff_ffff x S x S x
2859 (define_insn "*and<mode>3"
2860 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,!u,d,d,d,!u,d")
2861 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "o,o,W,!u,d,d,d,0,d")
2862 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Uean,K,Yx,Yw,!u,d")))]
2863 "!TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2867 switch (which_alternative)
2870 operands[1] = gen_lowpart (QImode, operands[1]);
2871 return "lbu\t%0,%1";
2873 operands[1] = gen_lowpart (HImode, operands[1]);
2874 return "lhu\t%0,%1";
2876 operands[1] = gen_lowpart (SImode, operands[1]);
2877 return "lwu\t%0,%1";
2880 return "andi\t%0,%1,%x2";
2882 len = low_bitmask_len (<MODE>mode, INTVAL (operands[2]));
2883 operands[2] = GEN_INT (len);
2884 return "<d>ext\t%0,%1,0,%2";
2889 return "and\t%0,%1,%2";
2894 [(set_attr "move_type" "load,load,load,andi,andi,ext_ins,shift_shift,logical,logical")
2895 (set_attr "compression" "*,*,*,micromips,*,*,*,micromips,*")
2896 (set_attr "mode" "<MODE>")])
2898 (define_insn "*and<mode>3_mips16"
2899 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d,d")
2900 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "%W,W,W,d,0")
2901 (match_operand:GPR 2 "and_operand" "Yb,Yh,Yw,Yw,d")))]
2902 "TARGET_MIPS16 && and_operands_ok (<MODE>mode, operands[1], operands[2])"
2904 switch (which_alternative)
2907 operands[1] = gen_lowpart (QImode, operands[1]);
2908 return "lbu\t%0,%1";
2910 operands[1] = gen_lowpart (HImode, operands[1]);
2911 return "lhu\t%0,%1";
2913 operands[1] = gen_lowpart (SImode, operands[1]);
2914 return "lwu\t%0,%1";
2918 return "and\t%0,%2";
2923 [(set_attr "move_type" "load,load,load,shift_shift,logical")
2924 (set_attr "mode" "<MODE>")])
2926 (define_expand "ior<mode>3"
2927 [(set (match_operand:GPR 0 "register_operand")
2928 (ior:GPR (match_operand:GPR 1 "register_operand")
2929 (match_operand:GPR 2 "uns_arith_operand")))]
2933 operands[2] = force_reg (<MODE>mode, operands[2]);
2936 (define_insn "*ior<mode>3"
2937 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
2938 (ior:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2939 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
2945 [(set_attr "alu_type" "or")
2946 (set_attr "compression" "micromips,*,*")
2947 (set_attr "mode" "<MODE>")])
2949 (define_insn "*ior<mode>3_mips16"
2950 [(set (match_operand:GPR 0 "register_operand" "=d")
2951 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2952 (match_operand:GPR 2 "register_operand" "d")))]
2955 [(set_attr "alu_type" "or")
2956 (set_attr "mode" "<MODE>")])
2958 (define_expand "xor<mode>3"
2959 [(set (match_operand:GPR 0 "register_operand")
2960 (xor:GPR (match_operand:GPR 1 "register_operand")
2961 (match_operand:GPR 2 "uns_arith_operand")))]
2965 (define_insn "*xor<mode>3"
2966 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
2967 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2968 (match_operand:GPR 2 "uns_arith_operand" "!u,d,K")))]
2974 [(set_attr "alu_type" "xor")
2975 (set_attr "compression" "micromips,*,*")
2976 (set_attr "mode" "<MODE>")])
2978 (define_insn "*xor<mode>3_mips16"
2979 [(set (match_operand:GPR 0 "register_operand" "=d,t,t,t")
2980 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d,d")
2981 (match_operand:GPR 2 "uns_arith_operand" "d,Uub8,K,d")))]
2988 [(set_attr "alu_type" "xor")
2989 (set_attr "mode" "<MODE>")
2990 (set_attr "extended_mips16" "no,no,yes,no")])
2992 (define_insn "*nor<mode>3"
2993 [(set (match_operand:GPR 0 "register_operand" "=d")
2994 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2995 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2998 [(set_attr "alu_type" "nor")
2999 (set_attr "mode" "<MODE>")])
3002 ;; ....................
3006 ;; ....................
3010 (define_insn "truncdfsf2"
3011 [(set (match_operand:SF 0 "register_operand" "=f")
3012 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3013 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3015 [(set_attr "type" "fcvt")
3016 (set_attr "cnv_mode" "D2S")
3017 (set_attr "mode" "SF")])
3019 ;; Integer truncation patterns. Truncating SImode values to smaller
3020 ;; modes is a no-op, as it is for most other GCC ports. Truncating
3021 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
3022 ;; need to make sure that the lower 32 bits are properly sign-extended
3023 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
3024 ;; smaller than SImode is equivalent to two separate truncations:
3027 ;; DI ---> HI == DI ---> SI ---> HI
3028 ;; DI ---> QI == DI ---> SI ---> QI
3030 ;; Step A needs a real instruction but step B does not.
3032 (define_insn "truncdi<mode>2"
3033 [(set (match_operand:SUBDI 0 "nonimmediate_operand" "=d,m")
3034 (truncate:SUBDI (match_operand:DI 1 "register_operand" "d,d")))]
3039 [(set_attr "move_type" "sll0,store")
3040 (set_attr "mode" "SI")])
3042 ;; Combiner patterns to optimize shift/truncate combinations.
3044 (define_insn "*ashr_trunc<mode>"
3045 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3047 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3048 (match_operand:DI 2 "const_arith_operand" ""))))]
3049 "TARGET_64BIT && !TARGET_MIPS16 && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3051 [(set_attr "type" "shift")
3052 (set_attr "mode" "<MODE>")])
3054 (define_insn "*lshr32_trunc<mode>"
3055 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3057 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3059 "TARGET_64BIT && !TARGET_MIPS16"
3061 [(set_attr "type" "shift")
3062 (set_attr "mode" "<MODE>")])
3064 ;; Logical shift by more than 32 results in proper SI values so truncation is
3065 ;; removed by the middle end. Note that a logical shift by 32 is handled by
3066 ;; the previous pattern.
3067 (define_insn "*<optab>_trunc<mode>_exts"
3068 [(set (match_operand:SUBDI 0 "register_operand" "=d")
3070 (any_shiftrt:DI (match_operand:DI 1 "register_operand" "d")
3071 (match_operand:DI 2 "const_arith_operand" ""))))]
3072 "ISA_HAS_EXTS && TARGET_64BIT && UINTVAL (operands[2]) < 32"
3074 [(set_attr "type" "arith")
3075 (set_attr "mode" "<MODE>")])
3078 ;; ....................
3082 ;; ....................
3086 (define_expand "zero_extendsidi2"
3087 [(set (match_operand:DI 0 "register_operand")
3088 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
3091 (define_insn_and_split "*zero_extendsidi2"
3092 [(set (match_operand:DI 0 "register_operand" "=d,d")
3093 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3094 "TARGET_64BIT && !ISA_HAS_EXT_INS"
3098 "&& reload_completed && REG_P (operands[1])"
3100 (ashift:DI (match_dup 1) (const_int 32)))
3102 (lshiftrt:DI (match_dup 0) (const_int 32)))]
3103 { operands[1] = gen_lowpart (DImode, operands[1]); }
3104 [(set_attr "move_type" "shift_shift,load")
3105 (set_attr "mode" "DI")])
3107 (define_insn "*zero_extendsidi2_dext"
3108 [(set (match_operand:DI 0 "register_operand" "=d,d")
3109 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
3110 "TARGET_64BIT && ISA_HAS_EXT_INS"
3114 [(set_attr "move_type" "arith,load")
3115 (set_attr "mode" "DI")])
3117 ;; See the comment before the *and<mode>3 pattern why this is generated by
3121 [(set (match_operand:DI 0 "register_operand")
3122 (and:DI (match_operand:DI 1 "register_operand")
3123 (const_int 4294967295)))]
3124 "TARGET_64BIT && !ISA_HAS_EXT_INS && reload_completed"
3126 (ashift:DI (match_dup 1) (const_int 32)))
3128 (lshiftrt:DI (match_dup 0) (const_int 32)))])
3130 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
3131 [(set (match_operand:GPR 0 "register_operand")
3132 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3135 if (TARGET_MIPS16 && !GENERATE_MIPS16E
3136 && !memory_operand (operands[1], <SHORT:MODE>mode))
3138 emit_insn (gen_and<GPR:mode>3 (operands[0],
3139 gen_lowpart (<GPR:MODE>mode, operands[1]),
3140 force_reg (<GPR:MODE>mode,
3141 GEN_INT (<SHORT:mask>))));
3146 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
3147 [(set (match_operand:GPR 0 "register_operand" "=!u,d,d")
3149 (match_operand:SHORT 1 "nonimmediate_operand" "!u,d,m")))]
3152 andi\t%0,%1,<SHORT:mask>
3153 andi\t%0,%1,<SHORT:mask>
3154 l<SHORT:size>u\t%0,%1"
3155 [(set_attr "move_type" "andi,andi,load")
3156 (set_attr "compression" "micromips,*,*")
3157 (set_attr "mode" "<GPR:MODE>")])
3159 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
3160 [(set (match_operand:GPR 0 "register_operand" "=d")
3161 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
3163 "ze<SHORT:size>\t%0"
3164 ;; This instruction is effectively a special encoding of ANDI.
3165 [(set_attr "move_type" "andi")
3166 (set_attr "mode" "<GPR:MODE>")])
3168 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
3169 [(set (match_operand:GPR 0 "register_operand" "=d")
3170 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
3172 "l<SHORT:size>u\t%0,%1"
3173 [(set_attr "move_type" "load")
3174 (set_attr "mode" "<GPR:MODE>")])
3176 (define_expand "zero_extendqihi2"
3177 [(set (match_operand:HI 0 "register_operand")
3178 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3181 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
3183 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
3189 (define_insn "*zero_extendqihi2"
3190 [(set (match_operand:HI 0 "register_operand" "=d,d")
3191 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3196 [(set_attr "move_type" "andi,load")
3197 (set_attr "mode" "HI")])
3199 (define_insn "*zero_extendqihi2_mips16"
3200 [(set (match_operand:HI 0 "register_operand" "=d")
3201 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
3204 [(set_attr "move_type" "load")
3205 (set_attr "mode" "HI")])
3207 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3209 (define_insn "*zero_extend<GPR:mode>_trunc<SHORT:mode>"
3210 [(set (match_operand:GPR 0 "register_operand" "=d")
3212 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3213 "TARGET_64BIT && !TARGET_MIPS16"
3215 operands[2] = GEN_INT (GET_MODE_MASK (<SHORT:MODE>mode));
3216 return "andi\t%0,%1,%x2";
3218 [(set_attr "alu_type" "and")
3219 (set_attr "mode" "<GPR:MODE>")])
3221 (define_insn "*zero_extendhi_truncqi"
3222 [(set (match_operand:HI 0 "register_operand" "=d")
3224 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3225 "TARGET_64BIT && !TARGET_MIPS16"
3227 [(set_attr "alu_type" "and")
3228 (set_attr "mode" "HI")])
3231 ;; ....................
3235 ;; ....................
3238 ;; Those for integer source operand are ordered widest source type first.
3240 ;; When TARGET_64BIT, all SImode integer and accumulator registers
3241 ;; should already be in sign-extended form (see TRULY_NOOP_TRUNCATION
3242 ;; and truncdisi2). We can therefore get rid of register->register
3243 ;; instructions if we constrain the source to be in the same register as
3246 ;; Only the pre-reload scheduler sees the type of the register alternatives;
3247 ;; we split them into nothing before the post-reload scheduler runs.
3248 ;; These alternatives therefore have type "move" in order to reflect
3249 ;; what happens if the two pre-reload operands cannot be tied, and are
3250 ;; instead allocated two separate GPRs. We don't distinguish between
3251 ;; the GPR and LO cases because we don't usually know during pre-reload
3252 ;; scheduling whether an operand will be LO or not.
3253 (define_insn_and_split "extendsidi2"
3254 [(set (match_operand:DI 0 "register_operand" "=d,l,d")
3255 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,0,m")))]
3261 "&& reload_completed && register_operand (operands[1], VOIDmode)"
3264 emit_note (NOTE_INSN_DELETED);
3267 [(set_attr "move_type" "move,move,load")
3268 (set_attr "mode" "DI")])
3270 (define_expand "extend<SHORT:mode><GPR:mode>2"
3271 [(set (match_operand:GPR 0 "register_operand")
3272 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
3275 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
3276 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3277 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
3281 l<SHORT:size>\t%0,%1"
3282 [(set_attr "move_type" "signext,load")
3283 (set_attr "mode" "<GPR:MODE>")])
3285 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
3286 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3288 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3289 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3292 l<SHORT:size>\t%0,%1"
3293 "&& reload_completed && REG_P (operands[1])"
3294 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
3295 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
3297 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
3298 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
3299 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
3301 [(set_attr "move_type" "shift_shift,load")
3302 (set_attr "mode" "<GPR:MODE>")])
3304 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
3305 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3307 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
3310 se<SHORT:size>\t%0,%1
3311 l<SHORT:size>\t%0,%1"
3312 [(set_attr "move_type" "signext,load")
3313 (set_attr "mode" "<GPR:MODE>")])
3315 (define_expand "extendqihi2"
3316 [(set (match_operand:HI 0 "register_operand")
3317 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
3320 (define_insn "*extendqihi2_mips16e"
3321 [(set (match_operand:HI 0 "register_operand" "=d,d")
3322 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))]
3327 [(set_attr "move_type" "signext,load")
3328 (set_attr "mode" "SI")])
3330 (define_insn_and_split "*extendqihi2"
3331 [(set (match_operand:HI 0 "register_operand" "=d,d")
3333 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3334 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
3338 "&& reload_completed && REG_P (operands[1])"
3339 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
3340 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
3342 operands[0] = gen_lowpart (SImode, operands[0]);
3343 operands[1] = gen_lowpart (SImode, operands[1]);
3344 operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
3345 - GET_MODE_BITSIZE (QImode));
3347 [(set_attr "move_type" "shift_shift,load")
3348 (set_attr "mode" "SI")])
3350 (define_insn "*extendqihi2_seb"
3351 [(set (match_operand:HI 0 "register_operand" "=d,d")
3353 (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
3358 [(set_attr "move_type" "signext,load")
3359 (set_attr "mode" "SI")])
3361 ;; Combiner patterns for truncate/sign_extend combinations. The SI versions
3362 ;; use the shift/truncate patterns.
3364 (define_insn_and_split "*extenddi_truncate<mode>"
3365 [(set (match_operand:DI 0 "register_operand" "=d")
3367 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3368 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3370 "&& reload_completed"
3372 (ashift:DI (match_dup 1)
3375 (ashiftrt:DI (match_dup 2)
3378 operands[2] = gen_lowpart (DImode, operands[0]);
3379 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3381 [(set_attr "move_type" "shift_shift")
3382 (set_attr "mode" "DI")])
3384 (define_insn_and_split "*extendsi_truncate<mode>"
3385 [(set (match_operand:SI 0 "register_operand" "=d")
3387 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3388 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3390 "&& reload_completed"
3392 (ashift:DI (match_dup 1)
3395 (truncate:SI (ashiftrt:DI (match_dup 2)
3398 operands[2] = gen_lowpart (DImode, operands[0]);
3399 operands[3] = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (<MODE>mode));
3401 [(set_attr "move_type" "shift_shift")
3402 (set_attr "mode" "SI")])
3404 (define_insn_and_split "*extendhi_truncateqi"
3405 [(set (match_operand:HI 0 "register_operand" "=d")
3407 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3408 "TARGET_64BIT && !TARGET_MIPS16 && !ISA_HAS_EXTS"
3410 "&& reload_completed"
3412 (ashift:DI (match_dup 1)
3415 (truncate:HI (ashiftrt:DI (match_dup 2)
3418 operands[2] = gen_lowpart (DImode, operands[0]);
3420 [(set_attr "move_type" "shift_shift")
3421 (set_attr "mode" "SI")])
3423 (define_insn "*extend<GPR:mode>_truncate<SHORT:mode>_exts"
3424 [(set (match_operand:GPR 0 "register_operand" "=d")
3426 (truncate:SHORT (match_operand:DI 1 "register_operand" "d"))))]
3427 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3429 operands[2] = GEN_INT (GET_MODE_BITSIZE (<SHORT:MODE>mode));
3430 return "exts\t%0,%1,0,%m2";
3432 [(set_attr "type" "arith")
3433 (set_attr "mode" "<GPR:MODE>")])
3435 (define_insn "*extendhi_truncateqi_exts"
3436 [(set (match_operand:HI 0 "register_operand" "=d")
3438 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
3439 "TARGET_64BIT && !TARGET_MIPS16 && ISA_HAS_EXTS"
3441 [(set_attr "type" "arith")
3442 (set_attr "mode" "SI")])
3444 (define_insn "extendsfdf2"
3445 [(set (match_operand:DF 0 "register_operand" "=f")
3446 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
3447 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3449 [(set_attr "type" "fcvt")
3450 (set_attr "cnv_mode" "S2D")
3451 (set_attr "mode" "DF")])
3454 ;; ....................
3458 ;; ....................
3460 (define_expand "fix_truncdfsi2"
3461 [(set (match_operand:SI 0 "register_operand")
3462 (fix:SI (match_operand:DF 1 "register_operand")))]
3463 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3465 if (!ISA_HAS_TRUNC_W)
3467 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
3472 (define_insn "fix_truncdfsi2_insn"
3473 [(set (match_operand:SI 0 "register_operand" "=f")
3474 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
3475 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
3477 [(set_attr "type" "fcvt")
3478 (set_attr "mode" "DF")
3479 (set_attr "cnv_mode" "D2I")])
3481 (define_insn "fix_truncdfsi2_macro"
3482 [(set (match_operand:SI 0 "register_operand" "=f")
3483 (fix:SI (match_operand:DF 1 "register_operand" "f")))
3484 (clobber (match_scratch:DF 2 "=d"))]
3485 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
3487 if (mips_nomacro.nesting_level > 0)
3488 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
3490 return "trunc.w.d %0,%1,%2";
3492 [(set_attr "type" "fcvt")
3493 (set_attr "mode" "DF")
3494 (set_attr "cnv_mode" "D2I")
3495 (set_attr "insn_count" "9")])
3497 (define_expand "fix_truncsfsi2"
3498 [(set (match_operand:SI 0 "register_operand")
3499 (fix:SI (match_operand:SF 1 "register_operand")))]
3502 if (!ISA_HAS_TRUNC_W)
3504 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
3509 (define_insn "fix_truncsfsi2_insn"
3510 [(set (match_operand:SI 0 "register_operand" "=f")
3511 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
3512 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
3514 [(set_attr "type" "fcvt")
3515 (set_attr "mode" "SF")
3516 (set_attr "cnv_mode" "S2I")])
3518 (define_insn "fix_truncsfsi2_macro"
3519 [(set (match_operand:SI 0 "register_operand" "=f")
3520 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3521 (clobber (match_scratch:SF 2 "=d"))]
3522 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
3524 if (mips_nomacro.nesting_level > 0)
3525 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
3527 return "trunc.w.s %0,%1,%2";
3529 [(set_attr "type" "fcvt")
3530 (set_attr "mode" "SF")
3531 (set_attr "cnv_mode" "S2I")
3532 (set_attr "insn_count" "9")])
3535 (define_insn "fix_truncdfdi2"
3536 [(set (match_operand:DI 0 "register_operand" "=f")
3537 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
3538 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3540 [(set_attr "type" "fcvt")
3541 (set_attr "mode" "DF")
3542 (set_attr "cnv_mode" "D2I")])
3545 (define_insn "fix_truncsfdi2"
3546 [(set (match_operand:DI 0 "register_operand" "=f")
3547 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
3548 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3550 [(set_attr "type" "fcvt")
3551 (set_attr "mode" "SF")
3552 (set_attr "cnv_mode" "S2I")])
3555 (define_insn "floatsidf2"
3556 [(set (match_operand:DF 0 "register_operand" "=f")
3557 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3558 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3560 [(set_attr "type" "fcvt")
3561 (set_attr "mode" "DF")
3562 (set_attr "cnv_mode" "I2D")])
3565 (define_insn "floatdidf2"
3566 [(set (match_operand:DF 0 "register_operand" "=f")
3567 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3568 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3570 [(set_attr "type" "fcvt")
3571 (set_attr "mode" "DF")
3572 (set_attr "cnv_mode" "I2D")])
3575 (define_insn "floatsisf2"
3576 [(set (match_operand:SF 0 "register_operand" "=f")
3577 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3580 [(set_attr "type" "fcvt")
3581 (set_attr "mode" "SF")
3582 (set_attr "cnv_mode" "I2S")])
3585 (define_insn "floatdisf2"
3586 [(set (match_operand:SF 0 "register_operand" "=f")
3587 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3588 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
3590 [(set_attr "type" "fcvt")
3591 (set_attr "mode" "SF")
3592 (set_attr "cnv_mode" "I2S")])
3595 (define_expand "fixuns_truncdfsi2"
3596 [(set (match_operand:SI 0 "register_operand")
3597 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
3598 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3600 rtx reg1 = gen_reg_rtx (DFmode);
3601 rtx reg2 = gen_reg_rtx (DFmode);
3602 rtx reg3 = gen_reg_rtx (SImode);
3603 rtx label1 = gen_label_rtx ();
3604 rtx label2 = gen_label_rtx ();
3606 REAL_VALUE_TYPE offset;
3608 real_2expN (&offset, 31, DFmode);
3610 if (reg1) /* Turn off complaints about unreached code. */
3612 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3613 do_pending_stack_adjust ();
3615 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3616 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3618 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
3619 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3620 gen_rtx_LABEL_REF (VOIDmode, label2)));
3623 emit_label (label1);
3624 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3625 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3626 (BITMASK_HIGH, SImode)));
3628 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
3629 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3631 emit_label (label2);
3633 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3634 fields, and can't be used for REG_NOTES anyway). */
3635 emit_use (stack_pointer_rtx);
3641 (define_expand "fixuns_truncdfdi2"
3642 [(set (match_operand:DI 0 "register_operand")
3643 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
3644 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3646 rtx reg1 = gen_reg_rtx (DFmode);
3647 rtx reg2 = gen_reg_rtx (DFmode);
3648 rtx reg3 = gen_reg_rtx (DImode);
3649 rtx label1 = gen_label_rtx ();
3650 rtx label2 = gen_label_rtx ();
3652 REAL_VALUE_TYPE offset;
3654 real_2expN (&offset, 63, DFmode);
3656 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
3657 do_pending_stack_adjust ();
3659 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3660 emit_jump_insn (gen_cbranchdf4 (test, operands[1], reg1, label1));
3662 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3663 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3664 gen_rtx_LABEL_REF (VOIDmode, label2)));
3667 emit_label (label1);
3668 mips_emit_move (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
3669 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3670 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3672 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3673 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3675 emit_label (label2);
3677 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3678 fields, and can't be used for REG_NOTES anyway). */
3679 emit_use (stack_pointer_rtx);
3684 (define_expand "fixuns_truncsfsi2"
3685 [(set (match_operand:SI 0 "register_operand")
3686 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
3689 rtx reg1 = gen_reg_rtx (SFmode);
3690 rtx reg2 = gen_reg_rtx (SFmode);
3691 rtx reg3 = gen_reg_rtx (SImode);
3692 rtx label1 = gen_label_rtx ();
3693 rtx label2 = gen_label_rtx ();
3695 REAL_VALUE_TYPE offset;
3697 real_2expN (&offset, 31, SFmode);
3699 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3700 do_pending_stack_adjust ();
3702 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3703 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3705 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3706 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3707 gen_rtx_LABEL_REF (VOIDmode, label2)));
3710 emit_label (label1);
3711 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3712 mips_emit_move (reg3, GEN_INT (trunc_int_for_mode
3713 (BITMASK_HIGH, SImode)));
3715 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3716 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3718 emit_label (label2);
3720 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3721 fields, and can't be used for REG_NOTES anyway). */
3722 emit_use (stack_pointer_rtx);
3727 (define_expand "fixuns_truncsfdi2"
3728 [(set (match_operand:DI 0 "register_operand")
3729 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
3730 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3732 rtx reg1 = gen_reg_rtx (SFmode);
3733 rtx reg2 = gen_reg_rtx (SFmode);
3734 rtx reg3 = gen_reg_rtx (DImode);
3735 rtx label1 = gen_label_rtx ();
3736 rtx label2 = gen_label_rtx ();
3738 REAL_VALUE_TYPE offset;
3740 real_2expN (&offset, 63, SFmode);
3742 mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
3743 do_pending_stack_adjust ();
3745 test = gen_rtx_GE (VOIDmode, operands[1], reg1);
3746 emit_jump_insn (gen_cbranchsf4 (test, operands[1], reg1, label1));
3748 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3749 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3750 gen_rtx_LABEL_REF (VOIDmode, label2)));
3753 emit_label (label1);
3754 mips_emit_move (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
3755 mips_emit_move (reg3, GEN_INT (BITMASK_HIGH));
3756 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3758 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3759 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3761 emit_label (label2);
3763 /* Allow REG_NOTES to be set on last insn (labels don't have enough
3764 fields, and can't be used for REG_NOTES anyway). */
3765 emit_use (stack_pointer_rtx);
3770 ;; ....................
3774 ;; ....................
3776 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
3778 (define_expand "extvmisalign<mode>"
3779 [(set (match_operand:GPR 0 "register_operand")
3780 (sign_extract:GPR (match_operand:BLK 1 "memory_operand")
3781 (match_operand 2 "const_int_operand")
3782 (match_operand 3 "const_int_operand")))]
3785 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3786 INTVAL (operands[2]),
3787 INTVAL (operands[3]),
3788 /*unsigned=*/ false))
3794 (define_expand "extv<mode>"
3795 [(set (match_operand:GPR 0 "register_operand")
3796 (sign_extract:GPR (match_operand:GPR 1 "register_operand")
3797 (match_operand 2 "const_int_operand")
3798 (match_operand 3 "const_int_operand")))]
3801 if (UINTVAL (operands[2]) > 32)
3805 (define_insn "*extv<mode>"
3806 [(set (match_operand:GPR 0 "register_operand" "=d")
3807 (sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3808 (match_operand 2 "const_int_operand" "")
3809 (match_operand 3 "const_int_operand" "")))]
3810 "ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32"
3811 "exts\t%0,%1,%3,%m2"
3812 [(set_attr "type" "arith")
3813 (set_attr "mode" "<MODE>")])
3815 (define_expand "extzvmisalign<mode>"
3816 [(set (match_operand:GPR 0 "register_operand")
3817 (zero_extract:GPR (match_operand:BLK 1 "memory_operand")
3818 (match_operand 2 "const_int_operand")
3819 (match_operand 3 "const_int_operand")))]
3822 if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
3823 INTVAL (operands[2]),
3824 INTVAL (operands[3]),
3825 /*unsigned=*/ true))
3831 (define_expand "extzv<mode>"
3832 [(set (match_operand:GPR 0 "register_operand")
3833 (zero_extract:GPR (match_operand:GPR 1 "register_operand")
3834 (match_operand 2 "const_int_operand")
3835 (match_operand 3 "const_int_operand")))]
3838 if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3839 INTVAL (operands[3])))
3843 (define_insn "*extzv<mode>"
3844 [(set (match_operand:GPR 0 "register_operand" "=d")
3845 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
3846 (match_operand 2 "const_int_operand" "")
3847 (match_operand 3 "const_int_operand" "")))]
3848 "mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
3849 INTVAL (operands[3]))"
3850 "<d>ext\t%0,%1,%3,%2"
3851 [(set_attr "type" "arith")
3852 (set_attr "mode" "<MODE>")])
3854 (define_insn "*extzv_truncsi_exts"
3855 [(set (match_operand:SI 0 "register_operand" "=d")
3857 (zero_extract:DI (match_operand:DI 1 "register_operand" "d")
3858 (match_operand 2 "const_int_operand" "")
3859 (match_operand 3 "const_int_operand" ""))))]
3860 "ISA_HAS_EXTS && TARGET_64BIT && IN_RANGE (INTVAL (operands[2]), 32, 63)"
3862 [(set_attr "type" "arith")
3863 (set_attr "mode" "SI")])
3866 (define_expand "insvmisalign<mode>"
3867 [(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")
3868 (match_operand 1 "const_int_operand")
3869 (match_operand 2 "const_int_operand"))
3870 (match_operand:GPR 3 "reg_or_0_operand"))]
3873 if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
3874 INTVAL (operands[1]),
3875 INTVAL (operands[2])))
3881 (define_expand "insv<mode>"
3882 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand")
3883 (match_operand 1 "const_int_operand")
3884 (match_operand 2 "const_int_operand"))
3885 (match_operand:GPR 3 "reg_or_0_operand"))]
3888 if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3889 INTVAL (operands[2])))
3893 (define_insn "*insv<mode>"
3894 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3895 (match_operand:SI 1 "const_int_operand" "")
3896 (match_operand:SI 2 "const_int_operand" ""))
3897 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3898 "mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
3899 INTVAL (operands[2]))"
3900 "<d>ins\t%0,%z3,%2,%1"
3901 [(set_attr "type" "arith")
3902 (set_attr "mode" "<MODE>")])
3904 ;; Combiner pattern for cins (clear and insert bit field). We can
3905 ;; implement mask-and-shift-left operation with this. Note that if
3906 ;; the upper bit of the mask is set in an SImode operation, the mask
3907 ;; itself will be sign-extended. mask_low_and_shift_len will
3908 ;; therefore be greater than our threshold of 32.
3910 (define_insn "*cins<mode>"
3911 [(set (match_operand:GPR 0 "register_operand" "=d")
3913 (ashift:GPR (match_operand:GPR 1 "register_operand" "d")
3914 (match_operand:GPR 2 "const_int_operand" ""))
3915 (match_operand:GPR 3 "const_int_operand" "")))]
3917 && mask_low_and_shift_p (<MODE>mode, operands[3], operands[2], 32)"
3920 GEN_INT (mask_low_and_shift_len (<MODE>mode, operands[3], operands[2]));
3921 return "cins\t%0,%1,%2,%m3";
3923 [(set_attr "type" "shift")
3924 (set_attr "mode" "<MODE>")])
3926 ;; Unaligned word moves generated by the bit field patterns.
3928 ;; As far as the rtl is concerned, both the left-part and right-part
3929 ;; instructions can access the whole field. However, the real operand
3930 ;; refers to just the first or the last byte (depending on endianness).
3931 ;; We therefore use two memory operands to each instruction, one to
3932 ;; describe the rtl effect and one to use in the assembly output.
3934 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3935 ;; This allows us to use the standard length calculations for the "load"
3936 ;; and "store" type attributes.
3938 (define_insn "mov_<load>l"
3939 [(set (match_operand:GPR 0 "register_operand" "=d")
3940 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3941 (match_operand:QI 2 "memory_operand" "ZC")]
3943 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3945 [(set_attr "move_type" "load")
3946 (set_attr "mode" "<MODE>")])
3948 (define_insn "mov_<load>r"
3949 [(set (match_operand:GPR 0 "register_operand" "=d")
3950 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3951 (match_operand:QI 2 "memory_operand" "ZC")
3952 (match_operand:GPR 3 "register_operand" "0")]
3953 UNSPEC_LOAD_RIGHT))]
3954 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3956 [(set_attr "move_type" "load")
3957 (set_attr "mode" "<MODE>")])
3959 (define_insn "mov_<store>l"
3960 [(set (match_operand:BLK 0 "memory_operand" "=m")
3961 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3962 (match_operand:QI 2 "memory_operand" "ZC")]
3963 UNSPEC_STORE_LEFT))]
3964 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3966 [(set_attr "move_type" "store")
3967 (set_attr "mode" "<MODE>")])
3969 (define_insn "mov_<store>r"
3970 [(set (match_operand:BLK 0 "memory_operand" "+m")
3971 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3972 (match_operand:QI 2 "memory_operand" "ZC")
3974 UNSPEC_STORE_RIGHT))]
3975 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3977 [(set_attr "move_type" "store")
3978 (set_attr "mode" "<MODE>")])
3980 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
3981 ;; The required value is:
3983 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3985 ;; which translates to:
3987 ;; lui op0,%highest(op1)
3988 ;; daddiu op0,op0,%higher(op1)
3990 ;; daddiu op0,op0,%hi(op1)
3993 ;; The split is deferred until after flow2 to allow the peephole2 below
3995 (define_insn_and_split "*lea_high64"
3996 [(set (match_operand:DI 0 "register_operand" "=d")
3997 (high:DI (match_operand:DI 1 "absolute_symbolic_operand" "")))]
3998 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4000 "&& epilogue_completed"
4001 [(set (match_dup 0) (high:DI (match_dup 2)))
4002 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
4003 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
4004 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4005 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
4007 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4008 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
4010 [(set_attr "insn_count" "5")])
4012 ;; Use a scratch register to reduce the latency of the above pattern
4013 ;; on superscalar machines. The optimized sequence is:
4015 ;; lui op1,%highest(op2)
4017 ;; daddiu op1,op1,%higher(op2)
4019 ;; daddu op1,op1,op0
4021 [(set (match_operand:DI 1 "d_operand")
4022 (high:DI (match_operand:DI 2 "absolute_symbolic_operand")))
4023 (match_scratch:DI 0 "d")]
4024 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
4025 [(set (match_dup 1) (high:DI (match_dup 3)))
4026 (set (match_dup 0) (high:DI (match_dup 4)))
4027 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
4028 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
4029 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
4031 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
4032 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
4035 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
4036 ;; SYMBOL_ABSOLUTE X will take 6 cycles. This next pattern allows combine
4037 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
4038 ;; used once. We can then use the sequence:
4040 ;; lui op0,%highest(op1)
4042 ;; daddiu op0,op0,%higher(op1)
4043 ;; daddiu op2,op2,%lo(op1)
4045 ;; daddu op0,op0,op2
4047 ;; which takes 4 cycles on most superscalar targets.
4048 (define_insn_and_split "*lea64"
4049 [(set (match_operand:DI 0 "register_operand" "=d")
4050 (match_operand:DI 1 "absolute_symbolic_operand" ""))
4051 (clobber (match_scratch:DI 2 "=&d"))]
4052 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
4054 "&& reload_completed"
4055 [(set (match_dup 0) (high:DI (match_dup 3)))
4056 (set (match_dup 2) (high:DI (match_dup 4)))
4057 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
4058 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
4059 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
4060 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
4062 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
4063 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
4065 [(set_attr "insn_count" "6")])
4067 ;; Split HIGHs into:
4072 ;; on MIPS16 targets.
4074 [(set (match_operand:P 0 "d_operand")
4075 (high:P (match_operand:P 1 "symbolic_operand_with_high")))]
4076 "TARGET_MIPS16 && reload_completed"
4077 [(set (match_dup 0) (unspec:P [(match_dup 1)] UNSPEC_UNSHIFTED_HIGH))
4078 (set (match_dup 0) (ashift:P (match_dup 0) (const_int 16)))])
4080 (define_insn "*unshifted_high"
4081 [(set (match_operand:P 0 "d_operand" "=d")
4082 (unspec:P [(match_operand:P 1 "symbolic_operand_with_high")]
4083 UNSPEC_UNSHIFTED_HIGH))]
4086 [(set_attr "extended_mips16" "yes")])
4088 ;; Insns to fetch a symbol from a big GOT.
4090 (define_insn_and_split "*xgot_hi<mode>"
4091 [(set (match_operand:P 0 "register_operand" "=d")
4092 (high:P (match_operand:P 1 "got_disp_operand" "")))]
4093 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4095 "&& reload_completed"
4096 [(set (match_dup 0) (high:P (match_dup 2)))
4097 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
4099 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
4100 operands[3] = pic_offset_table_rtx;
4102 [(set_attr "got" "xgot_high")
4103 (set_attr "mode" "<MODE>")])
4105 (define_insn_and_split "*xgot_lo<mode>"
4106 [(set (match_operand:P 0 "register_operand" "=d")
4107 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4108 (match_operand:P 2 "got_disp_operand" "")))]
4109 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
4111 "&& reload_completed"
4113 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
4114 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
4115 [(set_attr "got" "load")
4116 (set_attr "mode" "<MODE>")])
4118 ;; Insns to fetch a symbol from a normal GOT.
4120 (define_insn_and_split "*got_disp<mode>"
4121 [(set (match_operand:P 0 "register_operand" "=d")
4122 (match_operand:P 1 "got_disp_operand" ""))]
4123 "TARGET_EXPLICIT_RELOCS && !mips_split_p[SYMBOL_GOT_DISP]"
4125 "&& reload_completed"
4126 [(set (match_dup 0) (match_dup 2))]
4127 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_DISP); }
4128 [(set_attr "got" "load")
4129 (set_attr "mode" "<MODE>")])
4131 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
4133 (define_insn_and_split "*got_page<mode>"
4134 [(set (match_operand:P 0 "register_operand" "=d")
4135 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
4136 "TARGET_EXPLICIT_RELOCS && !mips_split_hi_p[SYMBOL_GOT_PAGE_OFST]"
4138 "&& reload_completed"
4139 [(set (match_dup 0) (match_dup 2))]
4140 { operands[2] = mips_got_load (NULL, operands[1], SYMBOL_GOTOFF_PAGE); }
4141 [(set_attr "got" "load")
4142 (set_attr "mode" "<MODE>")])
4144 ;; Convenience expander that generates the rhs of a load_got<mode> insn.
4145 (define_expand "unspec_got_<mode>"
4146 [(unspec:P [(match_operand:P 0)
4147 (match_operand:P 1)] UNSPEC_LOAD_GOT)])
4149 ;; Lower-level instructions for loading an address from the GOT.
4150 ;; We could use MEMs, but an unspec gives more optimization
4153 (define_insn "load_got<mode>"
4154 [(set (match_operand:P 0 "register_operand" "=d")
4155 (unspec:P [(match_operand:P 1 "register_operand" "d")
4156 (match_operand:P 2 "immediate_operand" "")]
4159 "<load>\t%0,%R2(%1)"
4160 [(set_attr "got" "load")
4161 (set_attr "mode" "<MODE>")])
4163 ;; Instructions for adding the low 16 bits of an address to a register.
4164 ;; Operand 2 is the address: mips_print_operand works out which relocation
4165 ;; should be applied.
4167 (define_insn "*low<mode>"
4168 [(set (match_operand:P 0 "register_operand" "=d")
4169 (lo_sum:P (match_operand:P 1 "register_operand" "d")
4170 (match_operand:P 2 "immediate_operand" "")))]
4172 "<d>addiu\t%0,%1,%R2"
4173 [(set_attr "alu_type" "add")
4174 (set_attr "mode" "<MODE>")])
4176 (define_insn "*low<mode>_mips16"
4177 [(set (match_operand:P 0 "register_operand" "=d")
4178 (lo_sum:P (match_operand:P 1 "register_operand" "0")
4179 (match_operand:P 2 "immediate_operand" "")))]
4182 [(set_attr "alu_type" "add")
4183 (set_attr "mode" "<MODE>")
4184 (set_attr "extended_mips16" "yes")])
4186 ;; Expose MIPS16 uses of the global pointer after reload if the function
4187 ;; is responsible for setting up the register itself.
4189 [(set (match_operand:GPR 0 "d_operand")
4190 (const:GPR (unspec:GPR [(const_int 0)] UNSPEC_GP)))]
4191 "TARGET_MIPS16 && TARGET_USE_GOT && reload_completed"
4192 [(set (match_dup 0) (match_dup 1))]
4193 { operands[1] = pic_offset_table_rtx; })
4195 ;; Allow combine to split complex const_int load sequences, using operand 2
4196 ;; to store the intermediate results. See move_operand for details.
4198 [(set (match_operand:GPR 0 "register_operand")
4199 (match_operand:GPR 1 "splittable_const_int_operand"))
4200 (clobber (match_operand:GPR 2 "register_operand"))]
4204 mips_move_integer (operands[2], operands[0], INTVAL (operands[1]));
4208 ;; Likewise, for symbolic operands.
4210 [(set (match_operand:P 0 "register_operand")
4211 (match_operand:P 1))
4212 (clobber (match_operand:P 2 "register_operand"))]
4213 "mips_split_symbol (operands[2], operands[1], MAX_MACHINE_MODE, NULL)"
4214 [(set (match_dup 0) (match_dup 3))]
4216 mips_split_symbol (operands[2], operands[1],
4217 MAX_MACHINE_MODE, &operands[3]);
4220 ;; 64-bit integer moves
4222 ;; Unlike most other insns, the move insns can't be split with
4223 ;; different predicates, because register spilling and other parts of
4224 ;; the compiler, have memoized the insn number already.
4226 (define_expand "movdi"
4227 [(set (match_operand:DI 0 "")
4228 (match_operand:DI 1 ""))]
4231 if (mips_legitimize_move (DImode, operands[0], operands[1]))
4235 ;; For mips16, we need a special case to handle storing $31 into
4236 ;; memory, since we don't have a constraint to match $31. This
4237 ;; instruction can be generated by save_restore_insns.
4239 (define_insn "*mov<mode>_ra"
4240 [(set (match_operand:GPR 0 "stack_operand" "=m")
4241 (reg:GPR RETURN_ADDR_REGNUM))]
4244 [(set_attr "move_type" "store")
4245 (set_attr "mode" "<MODE>")])
4247 (define_insn "*movdi_32bit"
4248 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d,*f,*f,*d,*m,*B*C*D,*B*C*D,*d,*m")
4249 (match_operand:DI 1 "move_operand" "d,i,m,d,*J,*d,*a,*J*d,*m,*f,*f,*d,*m,*B*C*D,*B*C*D"))]
4250 "!TARGET_64BIT && !TARGET_MIPS16
4251 && (register_operand (operands[0], DImode)
4252 || reg_or_0_operand (operands[1], DImode))"
4253 { return mips_output_move (operands[0], operands[1]); }
4254 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo,mtc,fpload,mfc,fpstore,mtc,fpload,mfc,fpstore")
4256 (if_then_else (eq_attr "move_type" "imul")
4258 (const_string "DI")))])
4260 (define_insn "*movdi_32bit_mips16"
4261 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4262 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
4263 "!TARGET_64BIT && TARGET_MIPS16
4264 && (register_operand (operands[0], DImode)
4265 || register_operand (operands[1], DImode))"
4266 { return mips_output_move (operands[0], operands[1]); }
4267 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4268 (set_attr "mode" "DI")])
4270 (define_insn "*movdi_64bit"
4271 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*a,*d,*B*C*D,*B*C*D,*d,*m")
4272 (match_operand:DI 1 "move_operand" "d,Yd,Yf,m,dJ,*d*J,*m,*f,*f,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4273 "TARGET_64BIT && !TARGET_MIPS16
4274 && (register_operand (operands[0], DImode)
4275 || reg_or_0_operand (operands[1], DImode))"
4276 { return mips_output_move (operands[0], operands[1]); }
4277 [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mtlo,mflo,mtc,fpload,mfc,fpstore")
4278 (set_attr "mode" "DI")])
4280 (define_insn "*movdi_64bit_mips16"
4281 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4282 (match_operand:DI 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4283 "TARGET_64BIT && TARGET_MIPS16
4284 && (register_operand (operands[0], DImode)
4285 || register_operand (operands[1], DImode))"
4286 { return mips_output_move (operands[0], operands[1]); }
4287 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4288 (set_attr "mode" "DI")])
4290 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
4291 ;; when the original load is a 4 byte instruction but the add and the
4292 ;; load are 2 2 byte instructions.
4295 [(set (match_operand:DI 0 "d_operand")
4296 (mem:DI (plus:DI (match_dup 0)
4297 (match_operand:DI 1 "const_int_operand"))))]
4298 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
4299 && !TARGET_DEBUG_D_MODE
4300 && ((INTVAL (operands[1]) < 0
4301 && INTVAL (operands[1]) >= -0x10)
4302 || (INTVAL (operands[1]) >= 32 * 8
4303 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
4304 || (INTVAL (operands[1]) >= 0
4305 && INTVAL (operands[1]) < 32 * 8
4306 && (INTVAL (operands[1]) & 7) != 0))"
4307 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
4308 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
4310 HOST_WIDE_INT val = INTVAL (operands[1]);
4313 operands[2] = const0_rtx;
4314 else if (val >= 32 * 8)
4318 operands[1] = GEN_INT (0x8 + off);
4319 operands[2] = GEN_INT (val - off - 0x8);
4325 operands[1] = GEN_INT (off);
4326 operands[2] = GEN_INT (val - off);
4330 ;; 32-bit Integer moves
4332 ;; Unlike most other insns, the move insns can't be split with
4333 ;; different predicates, because register spilling and other parts of
4334 ;; the compiler, have memoized the insn number already.
4336 (define_expand "mov<mode>"
4337 [(set (match_operand:IMOVE32 0 "")
4338 (match_operand:IMOVE32 1 ""))]
4341 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
4345 ;; The difference between these two is whether or not ints are allowed
4346 ;; in FP registers (off by default, use -mdebugh to enable).
4348 (define_insn "*mov<mode>_internal"
4349 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,!u,!u,d,e,!u,!ks,d,ZS,ZT,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
4350 (match_operand:IMOVE32 1 "move_operand" "d,J,Udb7,Yd,Yf,ZT,ZS,m,!ks,!u,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
4352 && (register_operand (operands[0], <MODE>mode)
4353 || reg_or_0_operand (operands[1], <MODE>mode))"
4354 { return mips_output_move (operands[0], operands[1]); }
4355 [(set_attr "move_type" "move,move,const,const,const,load,load,load,store,store,store,mtc,fpload,mfc,fpstore,mfc,mtc,mtlo,mflo,mtc,fpload,mfc,fpstore")
4356 (set_attr "compression" "all,micromips,micromips,*,*,micromips,micromips,*,micromips,micromips,*,*,*,*,*,*,*,*,*,*,*,*,*")
4357 (set_attr "mode" "SI")])
4359 (define_insn "*mov<mode>_mips16"
4360 [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d")
4361 (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,Yd,kf,m,d,*a"))]
4363 && (register_operand (operands[0], <MODE>mode)
4364 || register_operand (operands[1], <MODE>mode))"
4365 { return mips_output_move (operands[0], operands[1]); }
4366 [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mflo")
4367 (set_attr "mode" "SI")])
4369 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
4370 ;; when the original load is a 4 byte instruction but the add and the
4371 ;; load are 2 2 byte instructions.
4374 [(set (match_operand:SI 0 "d_operand")
4375 (mem:SI (plus:SI (match_dup 0)
4376 (match_operand:SI 1 "const_int_operand"))))]
4377 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4378 && ((INTVAL (operands[1]) < 0
4379 && INTVAL (operands[1]) >= -0x80)
4380 || (INTVAL (operands[1]) >= 32 * 4
4381 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
4382 || (INTVAL (operands[1]) >= 0
4383 && INTVAL (operands[1]) < 32 * 4
4384 && (INTVAL (operands[1]) & 3) != 0))"
4385 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4386 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
4388 HOST_WIDE_INT val = INTVAL (operands[1]);
4391 operands[2] = const0_rtx;
4392 else if (val >= 32 * 4)
4396 operands[1] = GEN_INT (0x7c + off);
4397 operands[2] = GEN_INT (val - off - 0x7c);
4403 operands[1] = GEN_INT (off);
4404 operands[2] = GEN_INT (val - off);
4408 ;; On the mips16, we can split a load of certain constants into a load
4409 ;; and an add. This turns a 4 byte instruction into 2 2 byte
4413 [(set (match_operand:SI 0 "d_operand")
4414 (match_operand:SI 1 "const_int_operand"))]
4415 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4416 && INTVAL (operands[1]) >= 0x100
4417 && INTVAL (operands[1]) <= 0xff + 0x7f"
4418 [(set (match_dup 0) (match_dup 1))
4419 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
4421 int val = INTVAL (operands[1]);
4423 operands[1] = GEN_INT (0xff);
4424 operands[2] = GEN_INT (val - 0xff);
4427 ;; MIPS4 supports loading and storing a floating point register from
4428 ;; the sum of two general registers. We use two versions for each of
4429 ;; these four instructions: one where the two general registers are
4430 ;; SImode, and one where they are DImode. This is because general
4431 ;; registers will be in SImode when they hold 32-bit values, but,
4432 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
4433 ;; instructions will still work correctly.
4435 ;; ??? Perhaps it would be better to support these instructions by
4436 ;; modifying TARGET_LEGITIMATE_ADDRESS_P and friends. However, since
4437 ;; these instructions can only be used to load and store floating
4438 ;; point registers, that would probably cause trouble in reload.
4440 (define_insn "*<ANYF:loadx>_<P:mode>"
4441 [(set (match_operand:ANYF 0 "register_operand" "=f")
4442 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4443 (match_operand:P 2 "register_operand" "d"))))]
4445 "<ANYF:loadx>\t%0,%1(%2)"
4446 [(set_attr "type" "fpidxload")
4447 (set_attr "mode" "<ANYF:UNITMODE>")])
4449 (define_insn "*<ANYF:storex>_<P:mode>"
4450 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
4451 (match_operand:P 2 "register_operand" "d")))
4452 (match_operand:ANYF 0 "register_operand" "f"))]
4454 "<ANYF:storex>\t%0,%1(%2)"
4455 [(set_attr "type" "fpidxstore")
4456 (set_attr "mode" "<ANYF:UNITMODE>")])
4458 ;; Scaled indexed address load.
4459 ;; Per md.texi, we only need to look for a pattern with multiply in the
4460 ;; address expression, not shift.
4462 (define_insn "*lwxs"
4463 [(set (match_operand:IMOVE32 0 "register_operand" "=d")
4465 (plus:P (mult:P (match_operand:P 1 "register_operand" "d")
4467 (match_operand:P 2 "register_operand" "d"))))]
4470 [(set_attr "type" "load")
4471 (set_attr "mode" "SI")])
4473 ;; 16-bit Integer moves
4475 ;; Unlike most other insns, the move insns can't be split with
4476 ;; different predicates, because register spilling and other parts of
4477 ;; the compiler, have memoized the insn number already.
4478 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4480 (define_expand "movhi"
4481 [(set (match_operand:HI 0 "")
4482 (match_operand:HI 1 ""))]
4485 if (mips_legitimize_move (HImode, operands[0], operands[1]))
4489 (define_insn "*movhi_internal"
4490 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZU,m,*a,*d")
4491 (match_operand:HI 1 "move_operand" "d,J,I,ZU,m,!u,dJ,*d*J,*a"))]
4493 && (register_operand (operands[0], HImode)
4494 || reg_or_0_operand (operands[1], HImode))"
4495 { return mips_output_move (operands[0], operands[1]); }
4496 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4497 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4498 (set_attr "mode" "HI")])
4500 (define_insn "*movhi_mips16"
4501 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4502 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4504 && (register_operand (operands[0], HImode)
4505 || register_operand (operands[1], HImode))"
4506 { return mips_output_move (operands[0], operands[1]); }
4507 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4508 (set_attr "mode" "HI")])
4510 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
4511 ;; when the original load is a 4 byte instruction but the add and the
4512 ;; load are 2 2 byte instructions.
4515 [(set (match_operand:HI 0 "d_operand")
4516 (mem:HI (plus:SI (match_dup 0)
4517 (match_operand:SI 1 "const_int_operand"))))]
4518 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4519 && ((INTVAL (operands[1]) < 0
4520 && INTVAL (operands[1]) >= -0x80)
4521 || (INTVAL (operands[1]) >= 32 * 2
4522 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
4523 || (INTVAL (operands[1]) >= 0
4524 && INTVAL (operands[1]) < 32 * 2
4525 && (INTVAL (operands[1]) & 1) != 0))"
4526 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4527 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
4529 HOST_WIDE_INT val = INTVAL (operands[1]);
4532 operands[2] = const0_rtx;
4533 else if (val >= 32 * 2)
4537 operands[1] = GEN_INT (0x7e + off);
4538 operands[2] = GEN_INT (val - off - 0x7e);
4544 operands[1] = GEN_INT (off);
4545 operands[2] = GEN_INT (val - off);
4549 ;; 8-bit Integer moves
4551 ;; Unlike most other insns, the move insns can't be split with
4552 ;; different predicates, because register spilling and other parts of
4553 ;; the compiler, have memoized the insn number already.
4554 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
4556 (define_expand "movqi"
4557 [(set (match_operand:QI 0 "")
4558 (match_operand:QI 1 ""))]
4561 if (mips_legitimize_move (QImode, operands[0], operands[1]))
4565 (define_insn "*movqi_internal"
4566 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,!u,d,!u,d,ZV,m,*a,*d")
4567 (match_operand:QI 1 "move_operand" "d,J,I,ZW,m,!u,dJ,*d*J,*a"))]
4569 && (register_operand (operands[0], QImode)
4570 || reg_or_0_operand (operands[1], QImode))"
4571 { return mips_output_move (operands[0], operands[1]); }
4572 [(set_attr "move_type" "move,const,const,load,load,store,store,mtlo,mflo")
4573 (set_attr "compression" "all,micromips,*,micromips,*,micromips,*,*,*")
4574 (set_attr "mode" "QI")])
4576 (define_insn "*movqi_mips16"
4577 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4578 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4580 && (register_operand (operands[0], QImode)
4581 || register_operand (operands[1], QImode))"
4582 { return mips_output_move (operands[0], operands[1]); }
4583 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4584 (set_attr "mode" "QI")])
4586 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
4587 ;; when the original load is a 4 byte instruction but the add and the
4588 ;; load are 2 2 byte instructions.
4591 [(set (match_operand:QI 0 "d_operand")
4592 (mem:QI (plus:SI (match_dup 0)
4593 (match_operand:SI 1 "const_int_operand"))))]
4594 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4595 && ((INTVAL (operands[1]) < 0
4596 && INTVAL (operands[1]) >= -0x80)
4597 || (INTVAL (operands[1]) >= 32
4598 && INTVAL (operands[1]) <= 31 + 0x7f))"
4599 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
4600 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
4602 HOST_WIDE_INT val = INTVAL (operands[1]);
4605 operands[2] = const0_rtx;
4608 operands[1] = GEN_INT (0x7f);
4609 operands[2] = GEN_INT (val - 0x7f);
4613 ;; 32-bit floating point moves
4615 (define_expand "movsf"
4616 [(set (match_operand:SF 0 "")
4617 (match_operand:SF 1 ""))]
4620 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
4624 (define_insn "*movsf_hardfloat"
4625 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4626 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
4628 && (register_operand (operands[0], SFmode)
4629 || reg_or_0_operand (operands[1], SFmode))"
4630 { return mips_output_move (operands[0], operands[1]); }
4631 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4632 (set_attr "mode" "SF")])
4634 (define_insn "*movsf_softfloat"
4635 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
4636 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
4637 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
4638 && (register_operand (operands[0], SFmode)
4639 || reg_or_0_operand (operands[1], SFmode))"
4640 { return mips_output_move (operands[0], operands[1]); }
4641 [(set_attr "move_type" "move,load,store")
4642 (set_attr "mode" "SF")])
4644 (define_insn "*movsf_mips16"
4645 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
4646 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
4648 && (register_operand (operands[0], SFmode)
4649 || register_operand (operands[1], SFmode))"
4650 { return mips_output_move (operands[0], operands[1]); }
4651 [(set_attr "move_type" "move,move,move,load,store")
4652 (set_attr "mode" "SF")])
4654 ;; 64-bit floating point moves
4656 (define_expand "movdf"
4657 [(set (match_operand:DF 0 "")
4658 (match_operand:DF 1 ""))]
4661 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
4665 (define_insn "*movdf_hardfloat"
4666 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4667 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
4668 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
4669 && (register_operand (operands[0], DFmode)
4670 || reg_or_0_operand (operands[1], DFmode))"
4671 { return mips_output_move (operands[0], operands[1]); }
4672 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4673 (set_attr "mode" "DF")])
4675 (define_insn "*movdf_softfloat"
4676 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m")
4677 (match_operand:DF 1 "move_operand" "dG,m,dG"))]
4678 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
4679 && (register_operand (operands[0], DFmode)
4680 || reg_or_0_operand (operands[1], DFmode))"
4681 { return mips_output_move (operands[0], operands[1]); }
4682 [(set_attr "move_type" "move,load,store")
4683 (set_attr "mode" "DF")])
4685 (define_insn "*movdf_mips16"
4686 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
4687 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
4689 && (register_operand (operands[0], DFmode)
4690 || register_operand (operands[1], DFmode))"
4691 { return mips_output_move (operands[0], operands[1]); }
4692 [(set_attr "move_type" "move,move,move,load,store")
4693 (set_attr "mode" "DF")])
4695 ;; 128-bit integer moves
4697 (define_expand "movti"
4698 [(set (match_operand:TI 0)
4699 (match_operand:TI 1))]
4702 if (mips_legitimize_move (TImode, operands[0], operands[1]))
4706 (define_insn "*movti"
4707 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,*a,*a,*d")
4708 (match_operand:TI 1 "move_operand" "d,i,m,dJ,*J,*d,*a"))]
4711 && (register_operand (operands[0], TImode)
4712 || reg_or_0_operand (operands[1], TImode))"
4713 { return mips_output_move (operands[0], operands[1]); }
4714 [(set_attr "move_type" "move,const,load,store,imul,mtlo,mflo")
4716 (if_then_else (eq_attr "move_type" "imul")
4718 (const_string "TI")))])
4720 (define_insn "*movti_mips16"
4721 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
4722 (match_operand:TI 1 "move_operand" "d,d,y,K,N,m,d,*a"))]
4725 && (register_operand (operands[0], TImode)
4726 || register_operand (operands[1], TImode))"
4728 [(set_attr "move_type" "move,move,move,const,constN,load,store,mflo")
4729 (set_attr "mode" "TI")])
4731 ;; 128-bit floating point moves
4733 (define_expand "movtf"
4734 [(set (match_operand:TF 0)
4735 (match_operand:TF 1))]
4738 if (mips_legitimize_move (TFmode, operands[0], operands[1]))
4742 ;; This pattern handles both hard- and soft-float cases.
4743 (define_insn "*movtf"
4744 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,d,m,f,d,f,m")
4745 (match_operand:TF 1 "move_operand" "dG,m,dG,dG,f,m,f"))]
4748 && (register_operand (operands[0], TFmode)
4749 || reg_or_0_operand (operands[1], TFmode))"
4751 [(set_attr "move_type" "move,load,store,mtc,mfc,fpload,fpstore")
4752 (set_attr "mode" "TF")])
4754 (define_insn "*movtf_mips16"
4755 [(set (match_operand:TF 0 "nonimmediate_operand" "=d,y,d,d,m")
4756 (match_operand:TF 1 "move_operand" "d,d,y,m,d"))]
4759 && (register_operand (operands[0], TFmode)
4760 || register_operand (operands[1], TFmode))"
4762 [(set_attr "move_type" "move,move,move,load,store")
4763 (set_attr "mode" "TF")])
4766 [(set (match_operand:MOVE64 0 "nonimmediate_operand")
4767 (match_operand:MOVE64 1 "move_operand"))]
4768 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
4771 mips_split_move_insn (operands[0], operands[1], curr_insn);
4776 [(set (match_operand:MOVE128 0 "nonimmediate_operand")
4777 (match_operand:MOVE128 1 "move_operand"))]
4778 "reload_completed && mips_split_move_insn_p (operands[0], operands[1], insn)"
4781 mips_split_move_insn (operands[0], operands[1], curr_insn);
4785 ;; When generating mips16 code, split moves of negative constants into
4786 ;; a positive "li" followed by a negation.
4788 [(set (match_operand 0 "d_operand")
4789 (match_operand 1 "const_int_operand"))]
4790 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
4794 (neg:SI (match_dup 2)))]
4796 operands[2] = gen_lowpart (SImode, operands[0]);
4797 operands[3] = GEN_INT (-INTVAL (operands[1]));
4800 ;; 64-bit paired-single floating point moves
4802 (define_expand "movv2sf"
4803 [(set (match_operand:V2SF 0)
4804 (match_operand:V2SF 1))]
4805 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT"
4807 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
4811 (define_insn "*movv2sf"
4812 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
4813 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
4815 && TARGET_PAIRED_SINGLE_FLOAT
4816 && (register_operand (operands[0], V2SFmode)
4817 || reg_or_0_operand (operands[1], V2SFmode))"
4818 { return mips_output_move (operands[0], operands[1]); }
4819 [(set_attr "move_type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,move,load,store")
4820 (set_attr "mode" "DF")])
4822 ;; Extract the high part of a HI/LO value. See mips_hard_regno_mode_ok_p
4823 ;; for the reason why we can't just use (reg:GPR HI_REGNUM).
4825 ;; When generating VR4120 or VR4130 code, we use MACCHI and DMACCHI
4826 ;; instead of MFHI. This avoids both the normal MIPS III hi/lo hazards
4827 ;; and the errata related to -mfix-vr4130.
4828 (define_insn "mfhi<GPR:mode>_<HILO:mode>"
4829 [(set (match_operand:GPR 0 "register_operand" "=d")
4830 (unspec:GPR [(match_operand:HILO 1 "hilo_operand" "x")]
4833 { return ISA_HAS_MACCHI ? "<GPR:d>macchi\t%0,%.,%." : "mfhi\t%0"; }
4834 [(set_attr "type" "mfhi")
4835 (set_attr "mode" "<GPR:MODE>")])
4837 ;; Set the high part of a HI/LO value, given that the low part has
4838 ;; already been set. See mips_hard_regno_mode_ok_p for the reason
4839 ;; why we can't just use (reg:GPR HI_REGNUM).
4840 (define_insn "mthi<GPR:mode>_<HILO:mode>"
4841 [(set (match_operand:HILO 0 "register_operand" "=x")
4842 (unspec:HILO [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
4843 (match_operand:GPR 2 "register_operand" "l")]
4847 [(set_attr "type" "mthi")
4848 (set_attr "mode" "SI")])
4850 ;; Emit a doubleword move in which exactly one of the operands is
4851 ;; a floating-point register. We can't just emit two normal moves
4852 ;; because of the constraints imposed by the FPU register model;
4853 ;; see mips_cannot_change_mode_class for details. Instead, we keep
4854 ;; the FPR whole and use special patterns to refer to each word of
4855 ;; the other operand.
4857 (define_expand "move_doubleword_fpr<mode>"
4858 [(set (match_operand:SPLITF 0)
4859 (match_operand:SPLITF 1))]
4862 if (FP_REG_RTX_P (operands[0]))
4864 rtx low = mips_subword (operands[1], 0);
4865 rtx high = mips_subword (operands[1], 1);
4866 emit_insn (gen_load_low<mode> (operands[0], low));
4867 if (TARGET_FLOAT64 && !TARGET_64BIT)
4868 emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
4870 emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
4874 rtx low = mips_subword (operands[0], 0);
4875 rtx high = mips_subword (operands[0], 1);
4876 emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
4877 if (TARGET_FLOAT64 && !TARGET_64BIT)
4878 emit_insn (gen_mfhc1<mode> (high, operands[1]));
4880 emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
4885 ;; Load the low word of operand 0 with operand 1.
4886 (define_insn "load_low<mode>"
4887 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4888 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")]
4892 operands[0] = mips_subword (operands[0], 0);
4893 return mips_output_move (operands[0], operands[1]);
4895 [(set_attr "move_type" "mtc,fpload")
4896 (set_attr "mode" "<HALFMODE>")])
4898 ;; Load the high word of operand 0 from operand 1, preserving the value
4900 (define_insn "load_high<mode>"
4901 [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
4902 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ,m")
4903 (match_operand:SPLITF 2 "register_operand" "0,0")]
4907 operands[0] = mips_subword (operands[0], 1);
4908 return mips_output_move (operands[0], operands[1]);
4910 [(set_attr "move_type" "mtc,fpload")
4911 (set_attr "mode" "<HALFMODE>")])
4913 ;; Store one word of operand 1 in operand 0. Operand 2 is 1 to store the
4914 ;; high word and 0 to store the low word.
4915 (define_insn "store_word<mode>"
4916 [(set (match_operand:<HALFMODE> 0 "nonimmediate_operand" "=d,m")
4917 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f,f")
4918 (match_operand 2 "const_int_operand")]
4919 UNSPEC_STORE_WORD))]
4922 operands[1] = mips_subword (operands[1], INTVAL (operands[2]));
4923 return mips_output_move (operands[0], operands[1]);
4925 [(set_attr "move_type" "mfc,fpstore")
4926 (set_attr "mode" "<HALFMODE>")])
4928 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4929 ;; value in the low word.
4930 (define_insn "mthc1<mode>"
4931 [(set (match_operand:SPLITF 0 "register_operand" "=f")
4932 (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
4933 (match_operand:SPLITF 2 "register_operand" "0")]
4935 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4937 [(set_attr "move_type" "mtc")
4938 (set_attr "mode" "<HALFMODE>")])
4940 ;; Move high word of operand 1 to operand 0 using mfhc1.
4941 (define_insn "mfhc1<mode>"
4942 [(set (match_operand:<HALFMODE> 0 "register_operand" "=d")
4943 (unspec:<HALFMODE> [(match_operand:SPLITF 1 "register_operand" "f")]
4945 "TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
4947 [(set_attr "move_type" "mfc")
4948 (set_attr "mode" "<HALFMODE>")])
4950 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4951 (define_expand "load_const_gp_<mode>"
4952 [(set (match_operand:P 0 "register_operand" "=d")
4953 (const:P (unspec:P [(const_int 0)] UNSPEC_GP)))])
4955 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4956 ;; of _gp from the start of this function. Operand 1 is the incoming
4957 ;; function address.
4958 (define_insn_and_split "loadgp_newabi_<mode>"
4959 [(set (match_operand:P 0 "register_operand" "=&d")
4960 (unspec:P [(match_operand:P 1)
4961 (match_operand:P 2 "register_operand" "d")]
4963 "mips_current_loadgp_style () == LOADGP_NEWABI"
4964 { return mips_must_initialize_gp_p () ? "#" : ""; }
4965 "&& mips_must_initialize_gp_p ()"
4966 [(set (match_dup 0) (match_dup 3))
4967 (set (match_dup 0) (match_dup 4))
4968 (set (match_dup 0) (match_dup 5))]
4970 operands[3] = gen_rtx_HIGH (Pmode, operands[1]);
4971 operands[4] = gen_rtx_PLUS (Pmode, operands[0], operands[2]);
4972 operands[5] = gen_rtx_LO_SUM (Pmode, operands[0], operands[1]);
4974 [(set_attr "type" "ghost")])
4976 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4977 (define_insn_and_split "loadgp_absolute_<mode>"
4978 [(set (match_operand:P 0 "register_operand" "=d")
4979 (unspec:P [(match_operand:P 1)] UNSPEC_LOADGP))]
4980 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4981 { return mips_must_initialize_gp_p () ? "#" : ""; }
4982 "&& mips_must_initialize_gp_p ()"
4985 mips_emit_move (operands[0], operands[1]);
4988 [(set_attr "type" "ghost")])
4990 ;; This blockage instruction prevents the gp load from being
4991 ;; scheduled after an implicit use of gp. It also prevents
4992 ;; the load from being deleted as dead.
4993 (define_insn "loadgp_blockage"
4994 [(unspec_volatile [(reg:SI 28)] UNSPEC_BLOCKAGE)]
4997 [(set_attr "type" "ghost")])
4999 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
5000 ;; and operand 1 is the __GOTT_INDEX__ symbol.
5001 (define_insn_and_split "loadgp_rtp_<mode>"
5002 [(set (match_operand:P 0 "register_operand" "=d")
5003 (unspec:P [(match_operand:P 1 "symbol_ref_operand")
5004 (match_operand:P 2 "symbol_ref_operand")]
5006 "mips_current_loadgp_style () == LOADGP_RTP"
5007 { return mips_must_initialize_gp_p () ? "#" : ""; }
5008 "&& mips_must_initialize_gp_p ()"
5009 [(set (match_dup 0) (high:P (match_dup 3)))
5010 (set (match_dup 0) (unspec:P [(match_dup 0)
5011 (match_dup 3)] UNSPEC_LOAD_GOT))
5012 (set (match_dup 0) (unspec:P [(match_dup 0)
5013 (match_dup 4)] UNSPEC_LOAD_GOT))]
5015 operands[3] = mips_unspec_address (operands[1], SYMBOL_ABSOLUTE);
5016 operands[4] = mips_unspec_address (operands[2], SYMBOL_HALF);
5018 [(set_attr "type" "ghost")])
5020 ;; Initialize the global pointer for MIPS16 code. Operand 0 is the
5021 ;; global pointer and operand 1 is the MIPS16 register that holds
5022 ;; the required value.
5023 (define_insn_and_split "copygp_mips16_<mode>"
5024 [(set (match_operand:P 0 "register_operand" "=y")
5025 (unspec:P [(match_operand:P 1 "register_operand" "d")]
5028 { return mips_must_initialize_gp_p () ? "#" : ""; }
5029 "&& mips_must_initialize_gp_p ()"
5030 [(set (match_dup 0) (match_dup 1))]
5032 [(set_attr "type" "ghost")])
5034 ;; A placeholder for where the cprestore instruction should go,
5035 ;; if we decide we need one. Operand 0 and operand 1 are as for
5036 ;; "cprestore". Operand 2 is a register that holds the gp value.
5038 ;; The "cprestore" pattern requires operand 2 to be pic_offset_table_rtx,
5039 ;; otherwise any register that holds the correct value will do.
5040 (define_insn_and_split "potential_cprestore_<mode>"
5041 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5042 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5043 (match_operand:P 2 "register_operand" "d,d")]
5044 UNSPEC_POTENTIAL_CPRESTORE))
5045 (clobber (match_operand:P 3 "scratch_operand" "=X,&d"))]
5046 "!TARGET_CPRESTORE_DIRECTIVE || operands[2] == pic_offset_table_rtx"
5047 { return mips_must_initialize_gp_p () ? "#" : ""; }
5048 "mips_must_initialize_gp_p ()"
5051 mips_save_gp_to_cprestore_slot (operands[0], operands[1],
5052 operands[2], operands[3]);
5055 [(set_attr "type" "ghost")])
5057 ;; Emit a .cprestore directive, which normally expands to a single store
5058 ;; instruction. Operand 0 is a (possibly illegitimate) sp-based MEM
5059 ;; for the cprestore slot. Operand 1 is the offset of the slot from
5060 ;; the stack pointer. (This is redundant with operand 0, but it makes
5061 ;; things a little simpler.)
5062 (define_insn "cprestore_<mode>"
5063 [(set (match_operand:P 0 "cprestore_save_slot_operand" "=X,X")
5064 (unspec:P [(match_operand:P 1 "const_int_operand" "I,i")
5067 "TARGET_CPRESTORE_DIRECTIVE"
5069 if (mips_nomacro.nesting_level > 0 && which_alternative == 1)
5070 return ".set\tmacro\;.cprestore\t%1\;.set\tnomacro";
5072 return ".cprestore\t%1";
5074 [(set_attr "type" "store")
5075 (set_attr "insn_count" "1,3")])
5077 (define_insn "use_cprestore_<mode>"
5078 [(set (reg:P CPRESTORE_SLOT_REGNUM)
5079 (match_operand:P 0 "cprestore_load_slot_operand"))]
5082 [(set_attr "type" "ghost")])
5084 ;; Expand in-line code to clear the instruction cache between operand[0] and
5086 (define_expand "clear_cache"
5087 [(match_operand 0 "pmode_register_operand")
5088 (match_operand 1 "pmode_register_operand")]
5094 mips_expand_synci_loop (operands[0], operands[1]);
5095 emit_insn (gen_sync ());
5096 emit_insn (PMODE_INSN (gen_clear_hazard, ()));
5098 else if (mips_cache_flush_func && mips_cache_flush_func[0])
5100 rtx len = gen_reg_rtx (Pmode);
5101 emit_insn (gen_sub3_insn (len, operands[1], operands[0]));
5102 MIPS_ICACHE_SYNC (operands[0], len);
5108 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
5110 { return mips_output_sync (); })
5112 (define_insn "synci"
5113 [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
5118 (define_insn "rdhwr_synci_step_<mode>"
5119 [(set (match_operand:P 0 "register_operand" "=d")
5120 (unspec_volatile [(const_int 1)]
5125 (define_insn "clear_hazard_<mode>"
5126 [(unspec_volatile [(const_int 0)] UNSPEC_CLEAR_HAZARD)
5127 (clobber (reg:P RETURN_ADDR_REGNUM))]
5130 return "%(%<bal\t1f\n"
5132 "1:\t<d>addiu\t$31,$31,12\n"
5136 [(set_attr "insn_count" "5")])
5138 ;; Cache operations for R4000-style caches.
5139 (define_insn "mips_cache"
5140 [(set (mem:BLK (scratch))
5141 (unspec:BLK [(match_operand:SI 0 "const_int_operand")
5142 (match_operand:QI 1 "address_operand" "p")]
5143 UNSPEC_MIPS_CACHE))]
5147 ;; Similar, but with the operands hard-coded to an R10K cache barrier
5148 ;; operation. We keep the pattern distinct so that we can identify
5149 ;; cache operations inserted by -mr10k-cache-barrier=, and so that
5150 ;; the operation is never inserted into a delay slot.
5151 (define_insn "r10k_cache_barrier"
5152 [(set (mem:BLK (scratch))
5153 (unspec:BLK [(const_int 0)] UNSPEC_R10K_CACHE_BARRIER))]
5156 [(set_attr "can_delay" "no")])
5158 ;; Block moves, see mips.c for more details.
5159 ;; Argument 0 is the destination
5160 ;; Argument 1 is the source
5161 ;; Argument 2 is the length
5162 ;; Argument 3 is the alignment
5164 (define_expand "movmemsi"
5165 [(parallel [(set (match_operand:BLK 0 "general_operand")
5166 (match_operand:BLK 1 "general_operand"))
5167 (use (match_operand:SI 2 ""))
5168 (use (match_operand:SI 3 "const_int_operand"))])]
5169 "!TARGET_MIPS16 && !TARGET_MEMCPY"
5171 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
5178 ;; ....................
5182 ;; ....................
5184 (define_expand "<optab><mode>3"
5185 [(set (match_operand:GPR 0 "register_operand")
5186 (any_shift:GPR (match_operand:GPR 1 "register_operand")
5187 (match_operand:SI 2 "arith_operand")))]
5190 /* On the mips16, a shift of more than 8 is a four byte instruction,
5191 so, for a shift between 8 and 16, it is just as fast to do two
5192 shifts of 8 or less. If there is a lot of shifting going on, we
5193 may win in CSE. Otherwise combine will put the shifts back
5194 together again. This can be called by mips_function_arg, so we must
5195 be careful not to allocate a new register if we've reached the
5199 && CONST_INT_P (operands[2])
5200 && INTVAL (operands[2]) > 8
5201 && INTVAL (operands[2]) <= 16
5202 && !reload_in_progress
5203 && !reload_completed)
5205 rtx temp = gen_reg_rtx (<MODE>mode);
5207 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
5208 emit_insn (gen_<optab><mode>3 (operands[0], temp,
5209 GEN_INT (INTVAL (operands[2]) - 8)));
5214 (define_insn "*<optab><mode>3"
5215 [(set (match_operand:GPR 0 "register_operand" "=!u,d")
5216 (any_shift:GPR (match_operand:GPR 1 "register_operand" "!u,d")
5217 (match_operand:SI 2 "arith_operand" "Uib3,dI")))]
5220 if (CONST_INT_P (operands[2]))
5221 operands[2] = GEN_INT (INTVAL (operands[2])
5222 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
5224 return "<d><insn>\t%0,%1,%2";
5226 [(set_attr "type" "shift")
5227 (set_attr "compression" "<shift_compression>,none")
5228 (set_attr "mode" "<MODE>")])
5230 (define_insn "*<optab>si3_extend"
5231 [(set (match_operand:DI 0 "register_operand" "=d")
5233 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
5234 (match_operand:SI 2 "arith_operand" "dI"))))]
5235 "TARGET_64BIT && !TARGET_MIPS16"
5237 if (CONST_INT_P (operands[2]))
5238 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5240 return "<insn>\t%0,%1,%2";
5242 [(set_attr "type" "shift")
5243 (set_attr "mode" "SI")])
5245 (define_insn "*<optab>si3_mips16"
5246 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
5247 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d,d")
5248 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5251 if (which_alternative == 0)
5252 return "<insn>\t%0,%2";
5254 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
5255 return "<insn>\t%0,%1,%2";
5257 [(set_attr "type" "shift")
5258 (set_attr "mode" "SI")
5259 (set_attr "extended_mips16" "no,no,yes")])
5261 ;; We need separate DImode MIPS16 patterns because of the irregularity
5263 (define_insn "*ashldi3_mips16"
5264 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5265 (ashift:DI (match_operand:DI 1 "register_operand" "0,d,d")
5266 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5267 "TARGET_64BIT && TARGET_MIPS16"
5269 if (which_alternative == 0)
5270 return "dsll\t%0,%2";
5272 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5273 return "dsll\t%0,%1,%2";
5275 [(set_attr "type" "shift")
5276 (set_attr "mode" "DI")
5277 (set_attr "extended_mips16" "no,no,yes")])
5279 (define_insn "*ashrdi3_mips16"
5280 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5281 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5282 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5283 "TARGET_64BIT && TARGET_MIPS16"
5285 if (CONST_INT_P (operands[2]))
5286 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5288 return "dsra\t%0,%2";
5290 [(set_attr "type" "shift")
5291 (set_attr "mode" "DI")
5292 (set_attr "extended_mips16" "no,no,yes")])
5294 (define_insn "*lshrdi3_mips16"
5295 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
5296 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,0")
5297 (match_operand:SI 2 "arith_operand" "d,Uib3,I")))]
5298 "TARGET_64BIT && TARGET_MIPS16"
5300 if (CONST_INT_P (operands[2]))
5301 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
5303 return "dsrl\t%0,%2";
5305 [(set_attr "type" "shift")
5306 (set_attr "mode" "DI")
5307 (set_attr "extended_mips16" "no,no,yes")])
5309 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
5312 [(set (match_operand:GPR 0 "d_operand")
5313 (any_shift:GPR (match_operand:GPR 1 "d_operand")
5314 (match_operand:GPR 2 "const_int_operand")))]
5315 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5316 && INTVAL (operands[2]) > 8
5317 && INTVAL (operands[2]) <= 16"
5318 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
5319 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
5320 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
5322 ;; If we load a byte on the mips16 as a bitfield, the resulting
5323 ;; sequence of instructions is too complicated for combine, because it
5324 ;; involves four instructions: a load, a shift, a constant load into a
5325 ;; register, and an and (the key problem here is that the mips16 does
5326 ;; not have and immediate). We recognize a shift of a load in order
5327 ;; to make it simple enough for combine to understand.
5329 ;; The instruction count here is the worst case.
5330 (define_insn_and_split ""
5331 [(set (match_operand:SI 0 "register_operand" "=d")
5332 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5333 (match_operand:SI 2 "immediate_operand" "I")))]
5337 [(set (match_dup 0) (match_dup 1))
5338 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
5340 [(set_attr "type" "load")
5341 (set_attr "mode" "SI")
5342 (set (attr "insn_count")
5343 (symbol_ref "mips_load_store_insns (operands[1], insn) + 2"))])
5345 (define_insn "rotr<mode>3"
5346 [(set (match_operand:GPR 0 "register_operand" "=d")
5347 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
5348 (match_operand:SI 2 "arith_operand" "dI")))]
5351 if (CONST_INT_P (operands[2]))
5352 gcc_assert (INTVAL (operands[2]) >= 0
5353 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
5355 return "<d>ror\t%0,%1,%2";
5357 [(set_attr "type" "shift")
5358 (set_attr "mode" "<MODE>")])
5361 ;; ....................
5363 ;; CONDITIONAL BRANCHES
5365 ;; ....................
5367 ;; Conditional branches on floating-point equality tests.
5369 (define_insn "*branch_fp"
5372 (match_operator 1 "equality_operator"
5373 [(match_operand:CC 2 "register_operand" "z")
5375 (label_ref (match_operand 0 "" ""))
5379 return mips_output_conditional_branch (insn, operands,
5380 MIPS_BRANCH ("b%F1", "%Z2%0"),
5381 MIPS_BRANCH ("b%W1", "%Z2%0"));
5383 [(set_attr "type" "branch")])
5385 (define_insn "*branch_fp_inverted"
5388 (match_operator 1 "equality_operator"
5389 [(match_operand:CC 2 "register_operand" "z")
5392 (label_ref (match_operand 0 "" ""))))]
5395 return mips_output_conditional_branch (insn, operands,
5396 MIPS_BRANCH ("b%W1", "%Z2%0"),
5397 MIPS_BRANCH ("b%F1", "%Z2%0"));
5399 [(set_attr "type" "branch")])
5401 ;; Conditional branches on ordered comparisons with zero.
5403 (define_insn "*branch_order<mode>"
5406 (match_operator 1 "order_operator"
5407 [(match_operand:GPR 2 "register_operand" "d")
5409 (label_ref (match_operand 0 "" ""))
5412 { return mips_output_order_conditional_branch (insn, operands, false); }
5413 [(set_attr "type" "branch")])
5415 (define_insn "*branch_order<mode>_inverted"
5418 (match_operator 1 "order_operator"
5419 [(match_operand:GPR 2 "register_operand" "d")
5422 (label_ref (match_operand 0 "" ""))))]
5424 { return mips_output_order_conditional_branch (insn, operands, true); }
5425 [(set_attr "type" "branch")])
5427 ;; Conditional branch on equality comparison.
5429 (define_insn "*branch_equality<mode>"
5432 (match_operator 1 "equality_operator"
5433 [(match_operand:GPR 2 "register_operand" "d")
5434 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5435 (label_ref (match_operand 0 "" ""))
5439 /* For a simple BNEZ or BEQZ microMIPS branch. */
5440 if (TARGET_MICROMIPS
5441 && operands[3] == const0_rtx
5442 && get_attr_length (insn) <= 8)
5443 return mips_output_conditional_branch (insn, operands,
5445 "%*b%N1z%:\t%2,%0");
5447 return mips_output_conditional_branch (insn, operands,
5448 MIPS_BRANCH ("b%C1", "%2,%z3,%0"),
5449 MIPS_BRANCH ("b%N1", "%2,%z3,%0"));
5451 [(set_attr "type" "branch")])
5453 (define_insn "*branch_equality<mode>_inverted"
5456 (match_operator 1 "equality_operator"
5457 [(match_operand:GPR 2 "register_operand" "d")
5458 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
5460 (label_ref (match_operand 0 "" ""))))]
5463 /* For a simple BNEZ or BEQZ microMIPS branch. */
5464 if (TARGET_MICROMIPS
5465 && operands[3] == const0_rtx
5466 && get_attr_length (insn) <= 8)
5467 return mips_output_conditional_branch (insn, operands,
5469 "%*b%C0z%:\t%2,%1");
5471 return mips_output_conditional_branch (insn, operands,
5472 MIPS_BRANCH ("b%N1", "%2,%z3,%0"),
5473 MIPS_BRANCH ("b%C1", "%2,%z3,%0"));
5475 [(set_attr "type" "branch")])
5479 (define_insn "*branch_equality<mode>_mips16"
5482 (match_operator 1 "equality_operator"
5483 [(match_operand:GPR 2 "register_operand" "d,t")
5485 (label_ref (match_operand 0 "" ""))
5491 [(set_attr "type" "branch")])
5493 (define_insn "*branch_equality<mode>_mips16_inverted"
5496 (match_operator 1 "equality_operator"
5497 [(match_operand:GPR 2 "register_operand" "d,t")
5500 (label_ref (match_operand 0 "" ""))))]
5505 [(set_attr "type" "branch")])
5507 (define_expand "cbranch<mode>4"
5509 (if_then_else (match_operator 0 "comparison_operator"
5510 [(match_operand:GPR 1 "register_operand")
5511 (match_operand:GPR 2 "nonmemory_operand")])
5512 (label_ref (match_operand 3 ""))
5516 mips_expand_conditional_branch (operands);
5520 (define_expand "cbranch<mode>4"
5522 (if_then_else (match_operator 0 "comparison_operator"
5523 [(match_operand:SCALARF 1 "register_operand")
5524 (match_operand:SCALARF 2 "register_operand")])
5525 (label_ref (match_operand 3 ""))
5529 mips_expand_conditional_branch (operands);
5533 ;; Used to implement built-in functions.
5534 (define_expand "condjump"
5536 (if_then_else (match_operand 0)
5537 (label_ref (match_operand 1))
5540 ;; Branch if bit is set/clear.
5542 (define_insn "*branch_bit<bbv><mode>"
5545 (equality_op (zero_extract:GPR
5546 (match_operand:GPR 1 "register_operand" "d")
5548 (match_operand 2 "const_int_operand" ""))
5550 (label_ref (match_operand 0 ""))
5552 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5555 mips_output_conditional_branch (insn, operands,
5556 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"),
5557 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"));
5559 [(set_attr "type" "branch")
5560 (set_attr "branch_likely" "no")])
5562 (define_insn "*branch_bit<bbv><mode>_inverted"
5565 (equality_op (zero_extract:GPR
5566 (match_operand:GPR 1 "register_operand" "d")
5568 (match_operand 2 "const_int_operand" ""))
5571 (label_ref (match_operand 0 ""))))]
5572 "ISA_HAS_BBIT && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
5575 mips_output_conditional_branch (insn, operands,
5576 MIPS_BRANCH ("bbit<bbinv>", "%1,%2,%0"),
5577 MIPS_BRANCH ("bbit<bbv>", "%1,%2,%0"));
5579 [(set_attr "type" "branch")
5580 (set_attr "branch_likely" "no")])
5583 ;; ....................
5585 ;; SETTING A REGISTER FROM A COMPARISON
5587 ;; ....................
5589 ;; Destination is always set in SI mode.
5591 (define_expand "cstore<mode>4"
5592 [(set (match_operand:SI 0 "register_operand")
5593 (match_operator:SI 1 "mips_cstore_operator"
5594 [(match_operand:GPR 2 "register_operand")
5595 (match_operand:GPR 3 "nonmemory_operand")]))]
5598 mips_expand_scc (operands);
5602 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>"
5603 [(set (match_operand:GPR2 0 "register_operand" "=d")
5604 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5606 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5608 [(set_attr "type" "slt")
5609 (set_attr "mode" "<GPR:MODE>")])
5611 (define_insn "*seq_zero_<GPR:mode><GPR2:mode>_mips16"
5612 [(set (match_operand:GPR2 0 "register_operand" "=t")
5613 (eq:GPR2 (match_operand:GPR 1 "register_operand" "d")
5615 "TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5617 [(set_attr "type" "slt")
5618 (set_attr "mode" "<GPR:MODE>")])
5620 ;; Generate sltiu unless using seq results in better code.
5621 (define_insn "*seq_<GPR:mode><GPR2:mode>_seq"
5622 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5623 (eq:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5624 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5630 [(set_attr "type" "slt")
5631 (set_attr "mode" "<GPR:MODE>")])
5633 (define_insn "*sne_zero_<GPR:mode><GPR2:mode>"
5634 [(set (match_operand:GPR2 0 "register_operand" "=d")
5635 (ne:GPR2 (match_operand:GPR 1 "register_operand" "d")
5637 "!TARGET_MIPS16 && !ISA_HAS_SEQ_SNE"
5639 [(set_attr "type" "slt")
5640 (set_attr "mode" "<GPR:MODE>")])
5642 ;; Generate sltu unless using sne results in better code.
5643 (define_insn "*sne_<GPR:mode><GPR2:mode>_sne"
5644 [(set (match_operand:GPR2 0 "register_operand" "=d,d,d")
5645 (ne:GPR2 (match_operand:GPR 1 "register_operand" "%d,d,d")
5646 (match_operand:GPR 2 "reg_imm10_operand" "d,J,YB")))]
5652 [(set_attr "type" "slt")
5653 (set_attr "mode" "<GPR:MODE>")])
5655 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>"
5656 [(set (match_operand:GPR2 0 "register_operand" "=d")
5657 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5658 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
5661 [(set_attr "type" "slt")
5662 (set_attr "mode" "<GPR:MODE>")])
5664 (define_insn "*sgt<u>_<GPR:mode><GPR2:mode>_mips16"
5665 [(set (match_operand:GPR2 0 "register_operand" "=t")
5666 (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5667 (match_operand:GPR 2 "register_operand" "d")))]
5670 [(set_attr "type" "slt")
5671 (set_attr "mode" "<GPR:MODE>")])
5673 (define_insn "*sge<u>_<GPR:mode><GPR2:mode>"
5674 [(set (match_operand:GPR2 0 "register_operand" "=d")
5675 (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d")
5679 [(set_attr "type" "slt")
5680 (set_attr "mode" "<GPR:MODE>")])
5682 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>"
5683 [(set (match_operand:GPR2 0 "register_operand" "=d")
5684 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d")
5685 (match_operand:GPR 2 "arith_operand" "dI")))]
5688 [(set_attr "type" "slt")
5689 (set_attr "mode" "<GPR:MODE>")])
5691 (define_insn "*slt<u>_<GPR:mode><GPR2:mode>_mips16"
5692 [(set (match_operand:GPR2 0 "register_operand" "=t,t,t")
5693 (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d,d")
5694 (match_operand:GPR 2 "arith_operand" "d,Uub8,I")))]
5697 [(set_attr "type" "slt")
5698 (set_attr "mode" "<GPR:MODE>")
5699 (set_attr "extended_mips16" "no,no,yes")])
5701 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>"
5702 [(set (match_operand:GPR2 0 "register_operand" "=d")
5703 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d")
5704 (match_operand:GPR 2 "sle_operand" "")))]
5707 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5708 return "slt<u>\t%0,%1,%2";
5710 [(set_attr "type" "slt")
5711 (set_attr "mode" "<GPR:MODE>")])
5713 (define_insn "*sle<u>_<GPR:mode><GPR2:mode>_mips16"
5714 [(set (match_operand:GPR2 0 "register_operand" "=t,t")
5715 (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d,d")
5716 (match_operand:GPR 2 "sle_operand" "Udb8,i")))]
5719 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5720 return "slt<u>\t%1,%2";
5722 [(set_attr "type" "slt")
5723 (set_attr "mode" "<GPR:MODE>")
5724 (set_attr "extended_mips16" "no,yes")])
5727 ;; ....................
5729 ;; FLOATING POINT COMPARISONS
5731 ;; ....................
5733 (define_insn "s<code>_<mode>"
5734 [(set (match_operand:CC 0 "register_operand" "=z")
5735 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5736 (match_operand:SCALARF 2 "register_operand" "f")))]
5738 "c.<fcond>.<fmt>\t%Z0%1,%2"
5739 [(set_attr "type" "fcmp")
5740 (set_attr "mode" "FPSW")])
5742 (define_insn "s<code>_<mode>"
5743 [(set (match_operand:CC 0 "register_operand" "=z")
5744 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
5745 (match_operand:SCALARF 2 "register_operand" "f")))]
5747 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
5748 [(set_attr "type" "fcmp")
5749 (set_attr "mode" "FPSW")])
5752 ;; ....................
5754 ;; UNCONDITIONAL BRANCHES
5756 ;; ....................
5758 ;; Unconditional branches.
5760 (define_expand "jump"
5762 (label_ref (match_operand 0)))])
5764 (define_insn "*jump_absolute"
5766 (label_ref (match_operand 0)))]
5767 "!TARGET_MIPS16 && TARGET_ABSOLUTE_JUMPS"
5769 /* Use a branch for microMIPS. The assembler will choose
5770 a 16-bit branch, a 32-bit branch, or a 32-bit jump. */
5771 if (TARGET_MICROMIPS && !TARGET_ABICALLS_PIC2)
5772 return "%*b\t%l0%/";
5774 return MIPS_ABSOLUTE_JUMP ("%*j\t%l0%/");
5776 [(set_attr "type" "jump")])
5778 (define_insn "*jump_pic"
5780 (label_ref (match_operand 0)))]
5781 "!TARGET_MIPS16 && !TARGET_ABSOLUTE_JUMPS"
5783 if (get_attr_length (insn) <= 8)
5784 return "%*b\t%l0%/";
5787 mips_output_load_label (operands[0]);
5788 return "%*jr\t%@%/%]";
5791 [(set_attr "type" "branch")])
5793 ;; We need a different insn for the mips16, because a mips16 branch
5794 ;; does not have a delay slot.
5796 (define_insn "*jump_mips16"
5798 (label_ref (match_operand 0 "" "")))]
5801 [(set_attr "type" "branch")
5802 (set (attr "length")
5803 ;; This calculation is like the normal branch one, but the
5804 ;; range of the unextended instruction is [-0x800, 0x7fe] rather
5805 ;; than [-0x100, 0xfe]. This translates to a range of:
5807 ;; [-(0x800 - sizeof (branch)), 0x7fe]
5808 ;; == [-0x7fe, 0x7fe]
5810 ;; from the shorten_branches reference address. Long-branch
5811 ;; sequences will replace this one, so the minimum length
5812 ;; is one instruction shorter than for conditional branches.
5813 (cond [(and (le (minus (match_dup 0) (pc)) (const_int 2046))
5814 (le (minus (pc) (match_dup 0)) (const_int 2046)))
5816 (and (le (minus (match_dup 0) (pc)) (const_int 65534))
5817 (le (minus (pc) (match_dup 0)) (const_int 65532)))
5819 (and (match_test "TARGET_ABICALLS")
5820 (not (match_test "TARGET_ABSOLUTE_ABICALLS")))
5822 (match_test "Pmode == SImode")
5824 ] (const_int 22)))])
5826 (define_expand "indirect_jump"
5827 [(set (pc) (match_operand 0 "register_operand"))]
5830 operands[0] = force_reg (Pmode, operands[0]);
5831 emit_jump_insn (PMODE_INSN (gen_indirect_jump, (operands[0])));
5835 (define_insn "indirect_jump_<mode>"
5836 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
5839 if (TARGET_MICROMIPS)
5840 return "%*jr%:\t%0";
5844 [(set_attr "type" "jump")
5845 (set_attr "mode" "none")])
5847 ;; A combined jump-and-move instruction, used for MIPS16 long-branch
5848 ;; sequences. Having a dedicated pattern is more convenient than
5849 ;; creating a SEQUENCE for this special case.
5850 (define_insn "indirect_jump_and_restore_<mode>"
5851 [(set (pc) (match_operand:P 1 "register_operand" "d"))
5852 (set (match_operand:P 0 "register_operand" "=d")
5853 (match_operand:P 2 "register_operand" "y"))]
5855 "%(%<jr\t%1\;move\t%0,%2%>%)"
5856 [(set_attr "type" "multi")
5857 (set_attr "extended_mips16" "yes")])
5859 (define_expand "tablejump"
5861 (match_operand 0 "register_operand"))
5862 (use (label_ref (match_operand 1 "")))]
5863 "!TARGET_MIPS16_SHORT_JUMP_TABLES"
5866 operands[0] = expand_binop (Pmode, add_optab, operands[0],
5867 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
5868 else if (TARGET_RTP_PIC)
5870 /* When generating RTP PIC, we use case table entries that are relative
5871 to the start of the function. Add the function's address to the
5873 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5874 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
5875 start, 0, 0, OPTAB_WIDEN);
5878 emit_jump_insn (PMODE_INSN (gen_tablejump, (operands[0], operands[1])));
5882 (define_insn "tablejump_<mode>"
5884 (match_operand:P 0 "register_operand" "d"))
5885 (use (label_ref (match_operand 1 "" "")))]
5888 if (TARGET_MICROMIPS)
5889 return "%*jr%:\t%0";
5893 [(set_attr "type" "jump")
5894 (set_attr "mode" "none")])
5896 ;; For MIPS16, we don't know whether a given jump table will use short or
5897 ;; word-sized offsets until late in compilation, when we are able to determine
5898 ;; the sizes of the insns which comprise the containing function. This
5899 ;; necessitates the use of the casesi rather than the tablejump pattern, since
5900 ;; the latter tries to calculate the index of the offset to jump through early
5901 ;; in compilation, i.e. at expand time, when nothing is known about the
5902 ;; eventual function layout.
5904 (define_expand "casesi"
5905 [(match_operand:SI 0 "register_operand" "") ; index to jump on
5906 (match_operand:SI 1 "const_int_operand" "") ; lower bound
5907 (match_operand:SI 2 "const_int_operand" "") ; total range
5908 (match_operand 3 "" "") ; table label
5909 (match_operand 4 "" "")] ; out of range label
5910 "TARGET_MIPS16_SHORT_JUMP_TABLES"
5912 if (operands[1] != const0_rtx)
5914 rtx reg = gen_reg_rtx (SImode);
5915 rtx offset = gen_int_mode (-INTVAL (operands[1]), SImode);
5917 if (!arith_operand (offset, SImode))
5918 offset = force_reg (SImode, offset);
5920 emit_insn (gen_addsi3 (reg, operands[0], offset));
5924 if (!arith_operand (operands[0], SImode))
5925 operands[0] = force_reg (SImode, operands[0]);
5927 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
5929 emit_jump_insn (PMODE_INSN (gen_casesi_internal_mips16,
5930 (operands[0], operands[2],
5931 operands[3], operands[4])));
5936 (define_insn "casesi_internal_mips16_<mode>"
5939 (leu (match_operand:SI 0 "register_operand" "d")
5940 (match_operand:SI 1 "arith_operand" "dI"))
5943 (label_ref (match_operand 2 "" ""))]
5944 UNSPEC_CASESI_DISPATCH)
5945 (label_ref (match_operand 3 "" ""))))
5946 (clobber (match_scratch:P 4 "=d"))
5947 (clobber (match_scratch:P 5 "=d"))
5948 (clobber (reg:SI MIPS16_T_REGNUM))]
5949 "TARGET_MIPS16_SHORT_JUMP_TABLES"
5951 rtx diff_vec = PATTERN (NEXT_INSN (operands[2]));
5953 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
5955 output_asm_insn ("sltu\t%0, %1", operands);
5956 output_asm_insn ("bteqz\t%3", operands);
5958 switch (GET_MODE (diff_vec))
5961 output_asm_insn ("sll\t%5, %0, 1", operands);
5962 output_asm_insn ("la\t%4, %2", operands);
5963 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
5964 output_asm_insn ("lh\t%5, 0(%5)", operands);
5968 output_asm_insn ("sll\t%5, %0, 2", operands);
5969 output_asm_insn ("la\t%4, %2", operands);
5970 output_asm_insn ("<d>addu\t%5, %4, %5", operands);
5971 output_asm_insn ("lw\t%5, 0(%5)", operands);
5978 output_asm_insn ("addu\t%4, %4, %5", operands);
5982 [(set_attr "insn_count" "16")])
5984 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
5985 ;; While it is possible to either pull it off the stack (in the
5986 ;; o32 case) or recalculate it given t9 and our target label,
5987 ;; it takes 3 or 4 insns to do so.
5989 (define_expand "builtin_setjmp_setup"
5990 [(use (match_operand 0 "register_operand"))]
5995 addr = plus_constant (Pmode, operands[0], GET_MODE_SIZE (Pmode) * 3);
5996 mips_emit_move (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
6000 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
6001 ;; that older code did recalculate the gp from $25. Continue to jump through
6002 ;; $25 for compatibility (we lose nothing by doing so).
6004 (define_expand "builtin_longjmp"
6005 [(use (match_operand 0 "register_operand"))]
6008 /* The elements of the buffer are, in order: */
6009 int W = GET_MODE_SIZE (Pmode);
6010 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6011 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 1*W));
6012 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 2*W));
6013 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 3*W));
6014 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6015 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
6016 The target is bound to be using $28 as the global pointer
6017 but the current function might not be. */
6018 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
6020 /* This bit is similar to expand_builtin_longjmp except that it
6021 restores $gp as well. */
6022 mips_emit_move (hard_frame_pointer_rtx, fp);
6023 mips_emit_move (pv, lab);
6024 emit_stack_restore (SAVE_NONLOCAL, stack);
6025 mips_emit_move (gp, gpv);
6026 emit_use (hard_frame_pointer_rtx);
6027 emit_use (stack_pointer_rtx);
6029 emit_indirect_jump (pv);
6034 ;; ....................
6036 ;; Function prologue/epilogue
6038 ;; ....................
6041 (define_expand "prologue"
6045 mips_expand_prologue ();
6049 ;; Block any insns from being moved before this point, since the
6050 ;; profiling call to mcount can use various registers that aren't
6051 ;; saved or used to pass arguments.
6053 (define_insn "blockage"
6054 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
6057 [(set_attr "type" "ghost")
6058 (set_attr "mode" "none")])
6060 (define_insn "probe_stack_range_<P:mode>"
6061 [(set (match_operand:P 0 "register_operand" "=d")
6062 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
6063 (match_operand:P 2 "register_operand" "d")]
6064 UNSPEC_PROBE_STACK_RANGE))]
6066 { return mips_output_probe_stack_range (operands[0], operands[2]); }
6067 [(set_attr "type" "unknown")
6068 (set_attr "can_delay" "no")
6069 (set_attr "mode" "<MODE>")])
6071 (define_expand "epilogue"
6075 mips_expand_epilogue (false);
6079 (define_expand "sibcall_epilogue"
6083 mips_expand_epilogue (true);
6087 ;; Trivial return. Make it look like a normal return insn as that
6088 ;; allows jump optimizations to work better.
6090 (define_expand "return"
6092 "mips_can_use_return_insn ()"
6093 { mips_expand_before_return (); })
6095 (define_expand "simple_return"
6098 { mips_expand_before_return (); })
6100 (define_insn "*<optab>"
6104 [(set_attr "type" "jump")
6105 (set_attr "mode" "none")])
6109 (define_insn "<optab>_internal"
6111 (use (match_operand 0 "pmode_register_operand" ""))]
6114 if (TARGET_MICROMIPS)
6115 return "%*jr%:\t%0";
6119 [(set_attr "type" "jump")
6120 (set_attr "mode" "none")])
6122 ;; Exception return.
6123 (define_insn "mips_eret"
6125 (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
6128 [(set_attr "type" "trap")
6129 (set_attr "mode" "none")])
6131 ;; Debug exception return.
6132 (define_insn "mips_deret"
6134 (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
6137 [(set_attr "type" "trap")
6138 (set_attr "mode" "none")])
6140 ;; Disable interrupts.
6141 (define_insn "mips_di"
6142 [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
6145 [(set_attr "type" "trap")
6146 (set_attr "mode" "none")])
6148 ;; Execution hazard barrier.
6149 (define_insn "mips_ehb"
6150 [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
6153 [(set_attr "type" "trap")
6154 (set_attr "mode" "none")])
6156 ;; Read GPR from previous shadow register set.
6157 (define_insn "mips_rdpgpr"
6158 [(set (match_operand:SI 0 "register_operand" "=d")
6159 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
6163 [(set_attr "type" "move")
6164 (set_attr "mode" "SI")])
6166 ;; Move involving COP0 registers.
6167 (define_insn "cop0_move"
6168 [(set (match_operand:SI 0 "register_operand" "=B,d")
6169 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
6172 { return mips_output_move (operands[0], operands[1]); }
6173 [(set_attr "type" "mtc,mfc")
6174 (set_attr "mode" "SI")])
6176 ;; This is used in compiling the unwind routines.
6177 (define_expand "eh_return"
6178 [(use (match_operand 0 "general_operand"))]
6181 if (GET_MODE (operands[0]) != word_mode)
6182 operands[0] = convert_to_mode (word_mode, operands[0], 0);
6184 emit_insn (gen_eh_set_lr_di (operands[0]));
6186 emit_insn (gen_eh_set_lr_si (operands[0]));
6190 ;; Clobber the return address on the stack. We can't expand this
6191 ;; until we know where it will be put in the stack frame.
6193 (define_insn "eh_set_lr_si"
6194 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6195 (clobber (match_scratch:SI 1 "=&d"))]
6199 (define_insn "eh_set_lr_di"
6200 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
6201 (clobber (match_scratch:DI 1 "=&d"))]
6206 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
6207 (clobber (match_scratch 1))]
6211 mips_set_return_address (operands[0], operands[1]);
6215 (define_expand "exception_receiver"
6219 /* See the comment above load_call<mode> for details. */
6220 emit_insn (gen_set_got_version ());
6222 /* If we have a call-clobbered $gp, restore it from its save slot. */
6223 if (HAVE_restore_gp_si)
6224 emit_insn (gen_restore_gp_si ());
6225 else if (HAVE_restore_gp_di)
6226 emit_insn (gen_restore_gp_di ());
6230 (define_expand "nonlocal_goto_receiver"
6234 /* See the comment above load_call<mode> for details. */
6235 emit_insn (gen_set_got_version ());
6239 ;; Restore $gp from its .cprestore stack slot. The instruction remains
6240 ;; volatile until all uses of $28 are exposed.
6241 (define_insn_and_split "restore_gp_<mode>"
6243 (unspec_volatile:P [(const_int 0)] UNSPEC_RESTORE_GP))
6244 (clobber (match_scratch:P 0 "=&d"))]
6245 "TARGET_CALL_CLOBBERED_GP"
6247 "&& epilogue_completed"
6250 mips_restore_gp_from_cprestore_slot (operands[0]);
6253 [(set_attr "type" "ghost")])
6255 ;; Move between $gp and its register save slot.
6256 (define_insn_and_split "move_gp<mode>"
6257 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,m")
6258 (unspec:GPR [(match_operand:GPR 1 "move_operand" "m,d")]
6261 { return mips_must_initialize_gp_p () ? "#" : ""; }
6262 "mips_must_initialize_gp_p ()"
6265 mips_emit_move (operands[0], operands[1]);
6268 [(set_attr "type" "ghost")])
6271 ;; ....................
6275 ;; ....................
6277 ;; Instructions to load a call address from the GOT. The address might
6278 ;; point to a function or to a lazy binding stub. In the latter case,
6279 ;; the stub will use the dynamic linker to resolve the function, which
6280 ;; in turn will change the GOT entry to point to the function's real
6283 ;; This means that every call, even pure and constant ones, can
6284 ;; potentially modify the GOT entry. And once a stub has been called,
6285 ;; we must not call it again.
6287 ;; We represent this restriction using an imaginary, fixed, call-saved
6288 ;; register called GOT_VERSION_REGNUM. The idea is to make the register
6289 ;; live throughout the function and to change its value after every
6290 ;; potential call site. This stops any rtx value that uses the register
6291 ;; from being computed before an earlier call. To do this, we:
6293 ;; - Ensure that the register is live on entry to the function,
6294 ;; so that it is never thought to be used uninitalized.
6296 ;; - Ensure that the register is live on exit from the function,
6297 ;; so that it is live throughout.
6299 ;; - Make each call (lazily-bound or not) use the current value
6300 ;; of GOT_VERSION_REGNUM, so that updates of the register are
6301 ;; not moved across call boundaries.
6303 ;; - Add "ghost" definitions of the register to the beginning of
6304 ;; blocks reached by EH and ABNORMAL_CALL edges, because those
6305 ;; edges may involve calls that normal paths don't. (E.g. the
6306 ;; unwinding code that handles a non-call exception may change
6307 ;; lazily-bound GOT entries.) We do this by making the
6308 ;; exception_receiver and nonlocal_goto_receiver expanders emit
6309 ;; a set_got_version instruction.
6311 ;; - After each call (lazily-bound or not), use a "ghost"
6312 ;; update_got_version instruction to change the register's value.
6313 ;; This instruction mimics the _possible_ effect of the dynamic
6314 ;; resolver during the call and it remains live even if the call
6315 ;; itself becomes dead.
6317 ;; - Leave GOT_VERSION_REGNUM out of all register classes.
6318 ;; The register is therefore not a valid register_operand
6319 ;; and cannot be moved to or from other registers.
6321 (define_insn "load_call<mode>"
6322 [(set (match_operand:P 0 "register_operand" "=d")
6323 (unspec:P [(match_operand:P 1 "register_operand" "d")
6324 (match_operand:P 2 "immediate_operand" "")
6325 (reg:SI GOT_VERSION_REGNUM)] UNSPEC_LOAD_CALL))]
6327 "<load>\t%0,%R2(%1)"
6328 [(set_attr "got" "load")
6329 (set_attr "mode" "<MODE>")])
6331 (define_insn "set_got_version"
6332 [(set (reg:SI GOT_VERSION_REGNUM)
6333 (unspec_volatile:SI [(const_int 0)] UNSPEC_SET_GOT_VERSION))]
6336 [(set_attr "type" "ghost")])
6338 (define_insn "update_got_version"
6339 [(set (reg:SI GOT_VERSION_REGNUM)
6340 (unspec:SI [(reg:SI GOT_VERSION_REGNUM)] UNSPEC_UPDATE_GOT_VERSION))]
6343 [(set_attr "type" "ghost")])
6345 ;; Sibling calls. All these patterns use jump instructions.
6347 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
6348 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
6349 ;; is defined in terms of call_insn_operand, the same is true of the
6352 ;; When we use an indirect jump, we need a register that will be
6353 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
6354 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
6355 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
6358 (define_expand "sibcall"
6359 [(parallel [(call (match_operand 0 "")
6360 (match_operand 1 ""))
6361 (use (match_operand 2 "")) ;; next_arg_reg
6362 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6365 mips_expand_call (MIPS_CALL_SIBCALL, NULL_RTX, XEXP (operands[0], 0),
6366 operands[1], operands[2], false);
6370 (define_insn "sibcall_internal"
6371 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
6372 (match_operand 1 "" ""))]
6373 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6375 if (TARGET_MICROMIPS)
6376 return MICROMIPS_J ("j", operands, 0);
6378 return MIPS_CALL ("j", operands, 0, 1);
6380 [(set_attr "jal" "indirect,direct")
6381 (set_attr "jal_macro" "no")])
6383 (define_expand "sibcall_value"
6384 [(parallel [(set (match_operand 0 "")
6385 (call (match_operand 1 "")
6386 (match_operand 2 "")))
6387 (use (match_operand 3 ""))])] ;; next_arg_reg
6390 mips_expand_call (MIPS_CALL_SIBCALL, operands[0], XEXP (operands[1], 0),
6391 operands[2], operands[3], false);
6395 (define_insn "sibcall_value_internal"
6396 [(set (match_operand 0 "register_operand" "")
6397 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6398 (match_operand 2 "" "")))]
6399 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6401 if (TARGET_MICROMIPS)
6402 return MICROMIPS_J ("j", operands, 1);
6404 return MIPS_CALL ("j", operands, 1, 2);
6406 [(set_attr "jal" "indirect,direct")
6407 (set_attr "jal_macro" "no")])
6409 (define_insn "sibcall_value_multiple_internal"
6410 [(set (match_operand 0 "register_operand" "")
6411 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
6412 (match_operand 2 "" "")))
6413 (set (match_operand 3 "register_operand" "")
6414 (call (mem:SI (match_dup 1))
6416 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
6418 if (TARGET_MICROMIPS)
6419 return MICROMIPS_J ("j", operands, 1);
6421 return MIPS_CALL ("j", operands, 1, 2);
6423 [(set_attr "jal" "indirect,direct")
6424 (set_attr "jal_macro" "no")])
6426 (define_expand "call"
6427 [(parallel [(call (match_operand 0 "")
6428 (match_operand 1 ""))
6429 (use (match_operand 2 "")) ;; next_arg_reg
6430 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
6433 mips_expand_call (MIPS_CALL_NORMAL, NULL_RTX, XEXP (operands[0], 0),
6434 operands[1], operands[2], false);
6438 ;; This instruction directly corresponds to an assembly-language "jal".
6439 ;; There are four cases:
6442 ;; Both symbolic and register destinations are OK. The pattern
6443 ;; always expands to a single mips instruction.
6445 ;; - -mabicalls/-mno-explicit-relocs:
6446 ;; Again, both symbolic and register destinations are OK.
6447 ;; The call is treated as a multi-instruction black box.
6449 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
6450 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
6453 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
6454 ;; Only "jal $25" is allowed. The call is actually two instructions:
6455 ;; "jalr $25" followed by an insn to reload $gp.
6457 ;; In the last case, we can generate the individual instructions with
6458 ;; a define_split. There are several things to be wary of:
6460 ;; - We can't expose the load of $gp before reload. If we did,
6461 ;; it might get removed as dead, but reload can introduce new
6462 ;; uses of $gp by rematerializing constants.
6464 ;; - We shouldn't restore $gp after calls that never return.
6465 ;; It isn't valid to insert instructions between a noreturn
6466 ;; call and the following barrier.
6468 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
6469 ;; instruction preserves $gp and so have no effect on its liveness.
6470 ;; But once we generate the separate insns, it becomes obvious that
6471 ;; $gp is not live on entry to the call.
6473 (define_insn_and_split "call_internal"
6474 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6475 (match_operand 1 "" ""))
6476 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6478 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, 1); }
6479 "reload_completed && TARGET_SPLIT_CALLS"
6482 mips_split_call (curr_insn, gen_call_split (operands[0], operands[1]));
6485 [(set_attr "jal" "indirect,direct")])
6487 (define_insn "call_split"
6488 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
6489 (match_operand 1 "" ""))
6490 (clobber (reg:SI RETURN_ADDR_REGNUM))
6491 (clobber (reg:SI 28))]
6492 "TARGET_SPLIT_CALLS"
6493 { return MIPS_CALL ("jal", operands, 0, 1); }
6494 [(set_attr "jal" "indirect,direct")
6495 (set_attr "jal_macro" "no")])
6497 ;; A pattern for calls that must be made directly. It is used for
6498 ;; MIPS16 calls that the linker may need to redirect to a hard-float
6499 ;; stub; the linker relies on the call relocation type to detect when
6500 ;; such redirection is needed.
6501 (define_insn_and_split "call_internal_direct"
6502 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6505 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6507 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0, -1); }
6508 "reload_completed && TARGET_SPLIT_CALLS"
6511 mips_split_call (curr_insn,
6512 gen_call_direct_split (operands[0], operands[1]));
6515 [(set_attr "jal" "direct")])
6517 (define_insn "call_direct_split"
6518 [(call (mem:SI (match_operand 0 "const_call_insn_operand"))
6521 (clobber (reg:SI RETURN_ADDR_REGNUM))
6522 (clobber (reg:SI 28))]
6523 "TARGET_SPLIT_CALLS"
6524 { return MIPS_CALL ("jal", operands, 0, -1); }
6525 [(set_attr "jal" "direct")
6526 (set_attr "jal_macro" "no")])
6528 (define_expand "call_value"
6529 [(parallel [(set (match_operand 0 "")
6530 (call (match_operand 1 "")
6531 (match_operand 2 "")))
6532 (use (match_operand 3 ""))])] ;; next_arg_reg
6535 mips_expand_call (MIPS_CALL_NORMAL, operands[0], XEXP (operands[1], 0),
6536 operands[2], operands[3], false);
6540 ;; See comment for call_internal.
6541 (define_insn_and_split "call_value_internal"
6542 [(set (match_operand 0 "register_operand" "")
6543 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6544 (match_operand 2 "" "")))
6545 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6547 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6548 "reload_completed && TARGET_SPLIT_CALLS"
6551 mips_split_call (curr_insn,
6552 gen_call_value_split (operands[0], operands[1],
6556 [(set_attr "jal" "indirect,direct")])
6558 (define_insn "call_value_split"
6559 [(set (match_operand 0 "register_operand" "")
6560 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6561 (match_operand 2 "" "")))
6562 (clobber (reg:SI RETURN_ADDR_REGNUM))
6563 (clobber (reg:SI 28))]
6564 "TARGET_SPLIT_CALLS"
6565 { return MIPS_CALL ("jal", operands, 1, 2); }
6566 [(set_attr "jal" "indirect,direct")
6567 (set_attr "jal_macro" "no")])
6569 ;; See call_internal_direct.
6570 (define_insn_and_split "call_value_internal_direct"
6571 [(set (match_operand 0 "register_operand")
6572 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6575 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6577 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, -1); }
6578 "reload_completed && TARGET_SPLIT_CALLS"
6581 mips_split_call (curr_insn,
6582 gen_call_value_direct_split (operands[0], operands[1],
6586 [(set_attr "jal" "direct")])
6588 (define_insn "call_value_direct_split"
6589 [(set (match_operand 0 "register_operand")
6590 (call (mem:SI (match_operand 1 "const_call_insn_operand"))
6593 (clobber (reg:SI RETURN_ADDR_REGNUM))
6594 (clobber (reg:SI 28))]
6595 "TARGET_SPLIT_CALLS"
6596 { return MIPS_CALL ("jal", operands, 1, -1); }
6597 [(set_attr "jal" "direct")
6598 (set_attr "jal_macro" "no")])
6600 ;; See comment for call_internal.
6601 (define_insn_and_split "call_value_multiple_internal"
6602 [(set (match_operand 0 "register_operand" "")
6603 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6604 (match_operand 2 "" "")))
6605 (set (match_operand 3 "register_operand" "")
6606 (call (mem:SI (match_dup 1))
6608 (clobber (reg:SI RETURN_ADDR_REGNUM))]
6610 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1, 2); }
6611 "reload_completed && TARGET_SPLIT_CALLS"
6614 mips_split_call (curr_insn,
6615 gen_call_value_multiple_split (operands[0], operands[1],
6616 operands[2], operands[3]));
6619 [(set_attr "jal" "indirect,direct")])
6621 (define_insn "call_value_multiple_split"
6622 [(set (match_operand 0 "register_operand" "")
6623 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
6624 (match_operand 2 "" "")))
6625 (set (match_operand 3 "register_operand" "")
6626 (call (mem:SI (match_dup 1))
6628 (clobber (reg:SI RETURN_ADDR_REGNUM))
6629 (clobber (reg:SI 28))]
6630 "TARGET_SPLIT_CALLS"
6631 { return MIPS_CALL ("jal", operands, 1, 2); }
6632 [(set_attr "jal" "indirect,direct")
6633 (set_attr "jal_macro" "no")])
6635 ;; Call subroutine returning any type.
6637 (define_expand "untyped_call"
6638 [(parallel [(call (match_operand 0 "")
6640 (match_operand 1 "")
6641 (match_operand 2 "")])]
6646 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6648 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6650 rtx set = XVECEXP (operands[2], 0, i);
6651 mips_emit_move (SET_DEST (set), SET_SRC (set));
6654 emit_insn (gen_blockage ());
6659 ;; ....................
6663 ;; ....................
6667 (define_insn "prefetch"
6668 [(prefetch (match_operand:QI 0 "address_operand" "ZD")
6669 (match_operand 1 "const_int_operand" "n")
6670 (match_operand 2 "const_int_operand" "n"))]
6671 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
6673 if (TARGET_LOONGSON_2EF || TARGET_LOONGSON_3A)
6674 /* Loongson 2[ef] and Loongson 3a use load to $0 to perform prefetching. */
6675 return "ld\t$0,%a0";
6676 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
6677 return "pref\t%1,%a0";
6679 [(set_attr "type" "prefetch")])
6681 (define_insn "*prefetch_indexed_<mode>"
6682 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
6683 (match_operand:P 1 "register_operand" "d"))
6684 (match_operand 2 "const_int_operand" "n")
6685 (match_operand 3 "const_int_operand" "n"))]
6686 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6688 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
6689 return "prefx\t%2,%1(%0)";
6691 [(set_attr "type" "prefetchx")])
6697 [(set_attr "type" "nop")
6698 (set_attr "mode" "none")])
6700 ;; Like nop, but commented out when outside a .set noreorder block.
6701 (define_insn "hazard_nop"
6705 if (mips_noreorder.nesting_level > 0)
6710 [(set_attr "type" "nop")])
6712 ;; MIPS4 Conditional move instructions.
6714 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
6715 [(set (match_operand:GPR 0 "register_operand" "=d,d")
6717 (match_operator:MOVECC 4 "equality_operator"
6718 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6720 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
6721 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
6726 [(set_attr "type" "condmove")
6727 (set_attr "mode" "<GPR:MODE>")])
6729 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
6730 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
6731 (if_then_else:SCALARF
6732 (match_operator:MOVECC 4 "equality_operator"
6733 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
6735 (match_operand:SCALARF 2 "register_operand" "f,0")
6736 (match_operand:SCALARF 3 "register_operand" "0,f")))]
6737 "ISA_HAS_FP_CONDMOVE"
6739 mov%T4.<fmt>\t%0,%2,%1
6740 mov%t4.<fmt>\t%0,%3,%1"
6741 [(set_attr "type" "condmove")
6742 (set_attr "mode" "<SCALARF:MODE>")])
6744 ;; These are the main define_expand's used to make conditional moves.
6746 (define_expand "mov<mode>cc"
6747 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6748 (set (match_operand:GPR 0 "register_operand")
6749 (if_then_else:GPR (match_dup 5)
6750 (match_operand:GPR 2 "reg_or_0_operand")
6751 (match_operand:GPR 3 "reg_or_0_operand")))]
6754 mips_expand_conditional_move (operands);
6758 (define_expand "mov<mode>cc"
6759 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
6760 (set (match_operand:SCALARF 0 "register_operand")
6761 (if_then_else:SCALARF (match_dup 5)
6762 (match_operand:SCALARF 2 "register_operand")
6763 (match_operand:SCALARF 3 "register_operand")))]
6764 "ISA_HAS_FP_CONDMOVE"
6766 mips_expand_conditional_move (operands);
6771 ;; ....................
6773 ;; mips16 inline constant tables
6775 ;; ....................
6778 (define_insn "consttable_tls_reloc"
6779 [(unspec_volatile [(match_operand 0 "tls_reloc_operand" "")
6780 (match_operand 1 "const_int_operand" "")]
6781 UNSPEC_CONSTTABLE_INT)]
6782 "TARGET_MIPS16_PCREL_LOADS"
6783 { return mips_output_tls_reloc_directive (&operands[0]); }
6784 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6786 (define_insn "consttable_int"
6787 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
6788 (match_operand 1 "const_int_operand" "")]
6789 UNSPEC_CONSTTABLE_INT)]
6792 assemble_integer (mips_strip_unspec_address (operands[0]),
6793 INTVAL (operands[1]),
6794 BITS_PER_UNIT * INTVAL (operands[1]), 1);
6797 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
6799 (define_insn "consttable_float"
6800 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
6801 UNSPEC_CONSTTABLE_FLOAT)]
6806 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
6807 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
6808 assemble_real (d, GET_MODE (operands[0]),
6809 GET_MODE_BITSIZE (GET_MODE (operands[0])));
6812 [(set (attr "length")
6813 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
6815 (define_insn "align"
6816 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
6819 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
6822 [(match_operand 0 "small_data_pattern")]
6825 { operands[0] = mips_rewrite_small_data (operands[0]); })
6828 ;; ....................
6830 ;; MIPS16e Save/Restore
6832 ;; ....................
6835 (define_insn "*mips16e_save_restore"
6836 [(match_parallel 0 ""
6837 [(set (match_operand:SI 1 "register_operand")
6838 (plus:SI (match_dup 1)
6839 (match_operand:SI 2 "const_int_operand")))])]
6840 "operands[1] == stack_pointer_rtx
6841 && mips16e_save_restore_pattern_p (operands[0], INTVAL (operands[2]), NULL)"
6842 { return mips16e_output_save_restore (operands[0], INTVAL (operands[2])); }
6843 [(set_attr "type" "arith")
6844 (set_attr "extended_mips16" "yes")])
6846 ;; Thread-Local Storage
6848 ;; The TLS base pointer is accessed via "rdhwr $3, $29". No current
6849 ;; MIPS architecture defines this register, and no current
6850 ;; implementation provides it; instead, any OS which supports TLS is
6851 ;; expected to trap and emulate this instruction. rdhwr is part of the
6852 ;; MIPS 32r2 specification, but we use it on any architecture because
6853 ;; we expect it to be emulated. Use .set to force the assembler to
6856 ;; We do not use a constraint to force the destination to be $3
6857 ;; because $3 can appear explicitly as a function return value.
6858 ;; If we leave the use of $3 implicit in the constraints until
6859 ;; reload, we may end up making a $3 return value live across
6860 ;; the instruction, leading to a spill failure when reloading it.
6861 (define_insn_and_split "tls_get_tp_<mode>"
6862 [(set (match_operand:P 0 "register_operand" "=d")
6863 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6864 (clobber (reg:P TLS_GET_TP_REGNUM))]
6865 "HAVE_AS_TLS && !TARGET_MIPS16"
6867 "&& reload_completed"
6868 [(set (reg:P TLS_GET_TP_REGNUM)
6869 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))
6870 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6872 [(set_attr "type" "unknown")
6873 (set_attr "mode" "<MODE>")
6874 (set_attr "insn_count" "2")])
6876 (define_insn "*tls_get_tp_<mode>_split"
6877 [(set (reg:P TLS_GET_TP_REGNUM)
6878 (unspec:P [(const_int 0)] UNSPEC_TLS_GET_TP))]
6879 "HAVE_AS_TLS && !TARGET_MIPS16"
6880 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t$3,$29\;.set\tpop"
6881 [(set_attr "type" "unknown")
6882 ; Since rdhwr always generates a trap for now, putting it in a delay
6883 ; slot would make the kernel's emulation of it much slower.
6884 (set_attr "can_delay" "no")
6885 (set_attr "mode" "<MODE>")])
6887 ;; In MIPS16 mode, the TLS base pointer is accessed by a
6888 ;; libgcc helper function __mips16_rdhwr(), as 'rdhwr' is not
6889 ;; accessible in MIPS16.
6891 ;; This is not represented as a call insn, to avoid the
6892 ;; unnecesarry clobbering of caller-save registers by a
6893 ;; function consisting only of: "rdhwr $3,$29; j $31; nop;"
6895 ;; A $25 clobber is added to cater for a $25 load stub added by the
6896 ;; linker to __mips16_rdhwr when the call is made from non-PIC code.
6898 (define_insn_and_split "tls_get_tp_mips16_<mode>"
6899 [(set (match_operand:P 0 "register_operand" "=d")
6900 (unspec:P [(match_operand:P 1 "call_insn_operand" "dS")]
6902 (clobber (reg:P TLS_GET_TP_REGNUM))
6903 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6904 (clobber (reg:P RETURN_ADDR_REGNUM))]
6905 "HAVE_AS_TLS && TARGET_MIPS16"
6907 "&& reload_completed"
6908 [(parallel [(set (reg:P TLS_GET_TP_REGNUM)
6909 (unspec:P [(match_dup 1)] UNSPEC_TLS_GET_TP))
6910 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6911 (clobber (reg:P RETURN_ADDR_REGNUM))])
6912 (set (match_dup 0) (reg:P TLS_GET_TP_REGNUM))]
6914 [(set_attr "type" "multi")
6915 (set_attr "insn_count" "4")
6916 (set_attr "mode" "<MODE>")])
6918 (define_insn "*tls_get_tp_mips16_call_<mode>"
6919 [(set (reg:P TLS_GET_TP_REGNUM)
6920 (unspec:P [(match_operand:P 0 "call_insn_operand" "dS")]
6922 (clobber (reg:P PIC_FUNCTION_ADDR_REGNUM))
6923 (clobber (reg:P RETURN_ADDR_REGNUM))]
6924 "HAVE_AS_TLS && TARGET_MIPS16"
6925 { return MIPS_CALL ("jal", operands, 0, -1); }
6926 [(set_attr "type" "call")
6927 (set_attr "insn_count" "3")
6928 (set_attr "mode" "<MODE>")])
6930 ;; Named pattern for expanding thread pointer reference.
6931 (define_expand "get_thread_pointer<mode>"
6932 [(match_operand:P 0 "register_operand" "=d")]
6935 mips_expand_thread_pointer (operands[0]);
6940 ;; Synchronization instructions.
6944 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
6946 (include "mips-ps-3d.md")
6948 ; The MIPS DSP Instructions.
6950 (include "mips-dsp.md")
6952 ; The MIPS DSP REV 2 Instructions.
6954 (include "mips-dspr2.md")
6956 ; MIPS fixed-point instructions.
6957 (include "mips-fixed.md")
6959 ; microMIPS patterns.
6960 (include "micromips.md")
6962 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
6963 (include "loongson.md")
6965 (define_c_enum "unspec" [
6966 UNSPEC_ADDRESS_FIRST