gcc/config/mips/mips.opt

   1 ; Options for the MIPS port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2016 Free Software Foundation, Inc.
   4 ;
   5 ; This file is part of GCC.
   6 ;
   7 ; GCC is free software; you can redistribute it and/or modify it under
   8 ; the terms of the GNU General Public License as published by the Free
   9 ; Software Foundation; either version 3, or (at your option) any later
  10 ; version.
  11 ;
  12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ; License for more details.
  16 ;
  17 ; You should have received a copy of the GNU General Public License
  18 ; along with GCC; see the file COPYING3.  If not see
  19 ; <http://www.gnu.org/licenses/>.
  20
  21 HeaderInclude
  22 config/mips/mips-opts.h
  23
  24 EB
  25 Driver
  26
  27 EL
  28 Driver
  29
  30 mabi=
  31 Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT)
  32 -mabi=ABI       Generate code that conforms to the given ABI.
  33
  34 Enum
  35 Name(mips_abi) Type(int)
  36 Known MIPS ABIs (for use with the -mabi= option):
  37
  38 EnumValue
  39 Enum(mips_abi) String(32) Value(ABI_32)
  40
  41 EnumValue
  42 Enum(mips_abi) String(o64) Value(ABI_O64)
  43
  44 EnumValue
  45 Enum(mips_abi) String(n32) Value(ABI_N32)
  46
  47 EnumValue
  48 Enum(mips_abi) String(64) Value(ABI_64)
  49
  50 EnumValue
  51 Enum(mips_abi) String(eabi) Value(ABI_EABI)
  52
  53 mabicalls
  54 Target Report Mask(ABICALLS)
  55 Generate code that can be used in SVR4-style dynamic objects.
  56
  57 mmad
  58 Target Report Var(TARGET_MAD)
  59 Use PMC-style 'mad' instructions.
  60
  61 mimadd
  62 Target Report Mask(IMADD)
  63 Use integer madd/msub instructions.
  64
  65 march=
  66 Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value)
  67 -march=ISA      Generate code for the given ISA.
  68
  69 mbranch-cost=
  70 Target RejectNegative Joined UInteger Var(mips_branch_cost)
  71 -mbranch-cost=COST      Set the cost of branches to roughly COST instructions.
  72
  73 mbranch-likely
  74 Target Report Mask(BRANCHLIKELY)
  75 Use Branch Likely instructions, overriding the architecture default.
  76
  77 mflip-mips16
  78 Target Report Var(TARGET_FLIP_MIPS16)
  79 Switch on/off MIPS16 ASE on alternating functions for compiler testing.
  80
  81 mcheck-zero-division
  82 Target Report Mask(CHECK_ZERO_DIV)
  83 Trap on integer divide by zero.
  84
  85 mcode-readable=
  86 Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES)
  87 -mcode-readable=SETTING Specify when instructions are allowed to access code.
  88
  89 Enum
  90 Name(mips_code_readable_setting) Type(enum mips_code_readable_setting)
  91 Valid arguments to -mcode-readable=:
  92
  93 EnumValue
  94 Enum(mips_code_readable_setting) String(yes) Value(CODE_READABLE_YES)
  95
  96 EnumValue
  97 Enum(mips_code_readable_setting) String(pcrel) Value(CODE_READABLE_PCREL)
  98
  99 EnumValue
 100 Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO)
 101
 102 mdivide-breaks
 103 Target Report RejectNegative Mask(DIVIDE_BREAKS)
 104 Use branch-and-break sequences to check for integer divide by zero.
 105
 106 mdivide-traps
 107 Target Report RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
 108 Use trap instructions to check for integer divide by zero.
 109
 110 mdmx
 111 Target Report RejectNegative Var(TARGET_MDMX)
 112 Allow the use of MDMX instructions.
 113
 114 mdouble-float
 115 Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
 116 Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
 117
 118 mdsp
 119 Target Report Var(TARGET_DSP)
 120 Use MIPS-DSP instructions.
 121
 122 mdspr2
 123 Target Report Var(TARGET_DSPR2)
 124 Use MIPS-DSP REV 2 instructions.
 125
 126 mdebug
 127 Target Var(TARGET_DEBUG_MODE) Undocumented
 128
 129 mdebugd
 130 Target Var(TARGET_DEBUG_D_MODE) Undocumented
 131
 132 meb
 133 Target Report RejectNegative Mask(BIG_ENDIAN)
 134 Use big-endian byte order.
 135
 136 mel
 137 Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
 138 Use little-endian byte order.
 139
 140 membedded-data
 141 Target Report Var(TARGET_EMBEDDED_DATA)
 142 Use ROM instead of RAM.
 143
 144 meva
 145 Target Report Var(TARGET_EVA)
 146 Use Enhanced Virtual Addressing instructions.
 147
 148 mexplicit-relocs
 149 Target Report Mask(EXPLICIT_RELOCS)
 150 Use NewABI-style %reloc() assembly operators.
 151
 152 mextern-sdata
 153 Target Report Var(TARGET_EXTERN_SDATA) Init(1)
 154 Use -G for data that is not defined by the current object.
 155
 156 mfix-24k
 157 Target Report Var(TARGET_FIX_24K)
 158 Work around certain 24K errata.
 159
 160 mfix-r4000
 161 Target Report Mask(FIX_R4000)
 162 Work around certain R4000 errata.
 163
 164 mfix-r4400
 165 Target Report Mask(FIX_R4400)
 166 Work around certain R4400 errata.
 167
 168 mfix-rm7000
 169 Target Report Var(TARGET_FIX_RM7000)
 170 Work around certain RM7000 errata.
 171
 172 mfix-r10000
 173 Target Report Mask(FIX_R10000)
 174 Work around certain R10000 errata.
 175
 176 mfix-sb1
 177 Target Report Var(TARGET_FIX_SB1)
 178 Work around errata for early SB-1 revision 2 cores.
 179
 180 mfix-vr4120
 181 Target Report Var(TARGET_FIX_VR4120)
 182 Work around certain VR4120 errata.
 183
 184 mfix-vr4130
 185 Target Report Var(TARGET_FIX_VR4130)
 186 Work around VR4130 mflo/mfhi errata.
 187
 188 mfix4300
 189 Target Report Var(TARGET_4300_MUL_FIX)
 190 Work around an early 4300 hardware bug.
 191
 192 mfp-exceptions
 193 Target Report Var(TARGET_FP_EXCEPTIONS) Init(1)
 194 FP exceptions are enabled.
 195
 196 mfp32
 197 Target Report RejectNegative InverseMask(FLOAT64)
 198 Use 32-bit floating-point registers.
 199
 200 mfpxx
 201 Target Report RejectNegative Mask(FLOATXX)
 202 Conform to the o32 FPXX ABI.
 203
 204 mfp64
 205 Target Report RejectNegative Mask(FLOAT64)
 206 Use 64-bit floating-point registers.
 207
 208 mflush-func=
 209 Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC)
 210 -mflush-func=FUNC       Use FUNC to flush the cache before calling stack trampolines.
 211
 212 mabs=
 213 Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_abs) Init(MIPS_IEEE_754_DEFAULT)
 214 -mabs=MODE      Select the IEEE 754 ABS/NEG instruction execution mode.
 215
 216 mnan=
 217 Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_nan) Init(MIPS_IEEE_754_DEFAULT)
 218 -mnan=ENCODING  Select the IEEE 754 NaN data encoding.
 219
 220 Enum
 221 Name(mips_ieee_754_value) Type(int)
 222 Known MIPS IEEE 754 settings (for use with the -mabs= and -mnan= options):
 223
 224 EnumValue
 225 Enum(mips_ieee_754_value) String(2008) Value(MIPS_IEEE_754_2008)
 226
 227 EnumValue
 228 Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY)
 229
 230 mgp32
 231 Target Report RejectNegative InverseMask(64BIT)
 232 Use 32-bit general registers.
 233
 234 mgp64
 235 Target Report RejectNegative Mask(64BIT)
 236 Use 64-bit general registers.
 237
 238 mgpopt
 239 Target Report Var(TARGET_GPOPT) Init(1)
 240 Use GP-relative addressing to access small data.
 241
 242 mplt
 243 Target Report Var(TARGET_PLT)
 244 When generating -mabicalls code, allow executables to use PLTs and copy relocations.
 245
 246 mhard-float
 247 Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
 248 Allow the use of hardware floating-point ABI and instructions.
 249
 250 minterlink-compressed
 251 Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0)
 252 Generate code that is link-compatible with MIPS16 and microMIPS code.
 253
 254 minterlink-mips16
 255 Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0)
 256 An alias for minterlink-compressed provided for backward-compatibility.
 257
 258 mips
 259 Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option)
 260 -mipsN  Generate code for ISA level N.
 261
 262 mips16
 263 Target Report RejectNegative Mask(MIPS16)
 264 Generate MIPS16 code.
 265
 266 mips3d
 267 Target Report RejectNegative Var(TARGET_MIPS3D)
 268 Use MIPS-3D instructions.
 269
 270 mllsc
 271 Target Report Mask(LLSC)
 272 Use ll, sc and sync instructions.
 273
 274 mlocal-sdata
 275 Target Report Var(TARGET_LOCAL_SDATA) Init(1)
 276 Use -G for object-local data.
 277
 278 mlong-calls
 279 Target Report Var(TARGET_LONG_CALLS)
 280 Use indirect calls.
 281
 282 mlong32
 283 Target Report RejectNegative InverseMask(LONG64, LONG32)
 284 Use a 32-bit long type.
 285
 286 mlong64
 287 Target Report RejectNegative Mask(LONG64)
 288 Use a 64-bit long type.
 289
 290 mmcount-ra-address
 291 Target Report Var(TARGET_MCOUNT_RA_ADDRESS)
 292 Pass the address of the ra save location to _mcount in $12.
 293
 294 mmemcpy
 295 Target Report Mask(MEMCPY)
 296 Don't optimize block moves.
 297
 298 mmicromips
 299 Target Report Mask(MICROMIPS)
 300 Use microMIPS instructions.
 301
 302 mmt
 303 Target Report Var(TARGET_MT)
 304 Allow the use of MT instructions.
 305
 306 mno-float
 307 Target Report RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT)
 308 Prevent the use of all floating-point operations.
 309
 310 mmcu
 311 Target Report Var(TARGET_MCU)
 312 Use MCU instructions.
 313
 314 mno-flush-func
 315 Target RejectNegative
 316 Do not use a cache-flushing function before calling stack trampolines.
 317
 318 mno-mdmx
 319 Target Report RejectNegative Var(TARGET_MDMX, 0)
 320 Do not use MDMX instructions.
 321
 322 mno-mips16
 323 Target Report RejectNegative InverseMask(MIPS16)
 324 Generate normal-mode code.
 325
 326 mno-mips3d
 327 Target Report RejectNegative Var(TARGET_MIPS3D, 0)
 328 Do not use MIPS-3D instructions.
 329
 330 mpaired-single
 331 Target Report Mask(PAIRED_SINGLE_FLOAT)
 332 Use paired-single floating-point instructions.
 333
 334 mr10k-cache-barrier=
 335 Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE)
 336 -mr10k-cache-barrier=SETTING    Specify when r10k cache barriers should be inserted.
 337
 338 Enum
 339 Name(mips_r10k_cache_barrier_setting) Type(enum mips_r10k_cache_barrier_setting)
 340 Valid arguments to -mr10k-cache-barrier=:
 341
 342 EnumValue
 343 Enum(mips_r10k_cache_barrier_setting) String(load-store) Value(R10K_CACHE_BARRIER_LOAD_STORE)
 344
 345 EnumValue
 346 Enum(mips_r10k_cache_barrier_setting) String(store) Value(R10K_CACHE_BARRIER_STORE)
 347
 348 EnumValue
 349 Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE)
 350
 351 mrelax-pic-calls
 352 Target Report Mask(RELAX_PIC_CALLS)
 353 Try to allow the linker to turn PIC calls into direct calls.
 354
 355 mshared
 356 Target Report Var(TARGET_SHARED) Init(1)
 357 When generating -mabicalls code, make the code suitable for use in shared libraries.
 358
 359 msingle-float
 360 Target Report RejectNegative Mask(SINGLE_FLOAT)
 361 Restrict the use of hardware floating-point instructions to 32-bit operations.
 362
 363 msmartmips
 364 Target Report Mask(SMARTMIPS)
 365 Use SmartMIPS instructions.
 366
 367 msoft-float
 368 Target Report RejectNegative Mask(SOFT_FLOAT_ABI)
 369 Prevent the use of all hardware floating-point instructions.
 370
 371 msplit-addresses
 372 Target Report Mask(SPLIT_ADDRESSES)
 373 Optimize lui/addiu address loads.
 374
 375 msym32
 376 Target Report Var(TARGET_SYM32)
 377 Assume all symbols have 32-bit values.
 378
 379 msynci
 380 Target Report Mask(SYNCI)
 381 Use synci instruction to invalidate i-cache.
 382
 383 mlra
 384 Target Report Var(mips_lra_flag) Init(1) Save
 385 Use LRA instead of reload.
 386
 387 mtune=
 388 Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
 389 -mtune=PROCESSOR        Optimize the output for PROCESSOR.
 390
 391 muninit-const-in-rodata
 392 Target Report Var(TARGET_UNINIT_CONST_IN_RODATA)
 393 Put uninitialized constants in ROM (needs -membedded-data).
 394
 395 mvirt
 396 Target Report Var(TARGET_VIRT)
 397 Use Virtualization Application Specific instructions.
 398
 399 mxpa
 400 Target Report Var(TARGET_XPA)
 401 Use eXtended Physical Address (XPA) instructions.
 402
 403 mvr4130-align
 404 Target Report Mask(VR4130_ALIGN)
 405 Perform VR4130-specific alignment optimizations.
 406
 407 mxgot
 408 Target Report Var(TARGET_XGOT)
 409 Lift restrictions on GOT size.
 410
 411 modd-spreg
 412 Target Report Mask(ODD_SPREG)
 413 Enable use of odd-numbered single-precision registers.
 414
 415 mframe-header-opt
 416 Target Report Var(flag_frame_header_optimization) Optimization
 417 Optimize frame header.
 418
 419 noasmopt
 420 Driver
 421
 422 mload-store-pairs
 423 Target Report Var(TARGET_LOAD_STORE_PAIRS) Init(1)
 424 Enable load/store bonding.
 425
 426 mcompact-branches=
 427 Target RejectNegative JoinedOrMissing Var(mips_cb) Report Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL)
 428 Specify the compact branch usage policy.
 429
 430 Enum
 431 Name(mips_cb_setting) Type(enum mips_cb_setting)
 432 Policies available for use with -mcompact-branches=:
 433
 434 EnumValue
 435 Enum(mips_cb_setting) String(never) Value(MIPS_CB_NEVER)
 436
 437 EnumValue
 438 Enum(mips_cb_setting) String(optimal) Value(MIPS_CB_OPTIMAL)
 439
 440 EnumValue
 441 Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS)