1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996-2014 Free Software Foundation, Inc.
3 Contributed by Jeff Law (law@cygnus.com).
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "stor-layout.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
48 #include "diagnostic-core.h"
50 #include "tm-constrs.h"
52 #include "target-def.h"
53 #include "dominance.h"
59 #include "cfgcleanup.h"
61 #include "basic-block.h"
68 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
69 names are not prefixed by underscores, to tell whether to prefix a
70 label with a plus sign or not, so that the assembler can tell
71 symbol names from register names. */
72 int mn10300_protect_label
;
74 /* Selected processor type for tuning. */
75 enum processor_type mn10300_tune_cpu
= PROCESSOR_DEFAULT
;
82 static int cc_flags_for_mode(machine_mode
);
83 static int cc_flags_for_code(enum rtx_code
);
85 /* Implement TARGET_OPTION_OVERRIDE. */
87 mn10300_option_override (void)
90 target_flags
&= ~MASK_MULT_BUG
;
93 /* Disable scheduling for the MN10300 as we do
94 not have timing information available for it. */
95 flag_schedule_insns
= 0;
96 flag_schedule_insns_after_reload
= 0;
98 /* Force enable splitting of wide types, as otherwise it is trivial
99 to run out of registers. Indeed, this works so well that register
100 allocation problems are now more common *without* optimization,
101 when this flag is not enabled by default. */
102 flag_split_wide_types
= 1;
105 if (mn10300_tune_string
)
107 if (strcasecmp (mn10300_tune_string
, "mn10300") == 0)
108 mn10300_tune_cpu
= PROCESSOR_MN10300
;
109 else if (strcasecmp (mn10300_tune_string
, "am33") == 0)
110 mn10300_tune_cpu
= PROCESSOR_AM33
;
111 else if (strcasecmp (mn10300_tune_string
, "am33-2") == 0)
112 mn10300_tune_cpu
= PROCESSOR_AM33_2
;
113 else if (strcasecmp (mn10300_tune_string
, "am34") == 0)
114 mn10300_tune_cpu
= PROCESSOR_AM34
;
116 error ("-mtune= expects mn10300, am33, am33-2, or am34");
121 mn10300_file_start (void)
123 default_file_start ();
126 fprintf (asm_out_file
, "\t.am33_2\n");
127 else if (TARGET_AM33
)
128 fprintf (asm_out_file
, "\t.am33\n");
131 /* Note: This list must match the liw_op attribute in mn10300.md. */
133 static const char *liw_op_names
[] =
135 "add", "cmp", "sub", "mov",
141 /* Print operand X using operand code CODE to assembly language output file
145 mn10300_print_operand (FILE *file
, rtx x
, int code
)
151 unsigned int liw_op
= UINTVAL (x
);
153 gcc_assert (TARGET_ALLOW_LIW
);
154 gcc_assert (liw_op
< LIW_OP_MAX
);
155 fputs (liw_op_names
[liw_op
], file
);
162 enum rtx_code cmp
= GET_CODE (x
);
163 machine_mode mode
= GET_MODE (XEXP (x
, 0));
168 cmp
= reverse_condition (cmp
);
169 have_flags
= cc_flags_for_mode (mode
);
180 /* bge is smaller than bnc. */
181 str
= (have_flags
& CC_FLAG_V
? "ge" : "nc");
184 str
= (have_flags
& CC_FLAG_V
? "lt" : "ns");
232 gcc_checking_assert ((cc_flags_for_code (cmp
) & ~have_flags
) == 0);
238 /* This is used for the operand to a call instruction;
239 if it's a REG, enclose it in parens, else output
240 the operand normally. */
244 mn10300_print_operand (file
, x
, 0);
248 mn10300_print_operand (file
, x
, 0);
252 switch (GET_CODE (x
))
256 output_address (XEXP (x
, 0));
261 fprintf (file
, "fd%d", REGNO (x
) - 18);
269 /* These are the least significant word in a 64bit value. */
271 switch (GET_CODE (x
))
275 output_address (XEXP (x
, 0));
280 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
284 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
292 switch (GET_MODE (x
))
295 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
296 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
297 fprintf (file
, "0x%lx", val
[0]);
300 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
301 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
[0]);
302 fprintf (file
, "0x%lx", val
[0]);
306 mn10300_print_operand_address (file
,
307 GEN_INT (CONST_DOUBLE_LOW (x
)));
318 split_double (x
, &low
, &high
);
319 fprintf (file
, "%ld", (long)INTVAL (low
));
328 /* Similarly, but for the most significant word. */
330 switch (GET_CODE (x
))
334 x
= adjust_address (x
, SImode
, 4);
335 output_address (XEXP (x
, 0));
340 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
344 fprintf (file
, "%s", reg_names
[subreg_regno (x
) + 1]);
352 switch (GET_MODE (x
))
355 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
356 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
357 fprintf (file
, "0x%lx", val
[1]);
363 mn10300_print_operand_address (file
,
364 GEN_INT (CONST_DOUBLE_HIGH (x
)));
375 split_double (x
, &low
, &high
);
376 fprintf (file
, "%ld", (long)INTVAL (high
));
387 if (REG_P (XEXP (x
, 0)))
388 output_address (gen_rtx_PLUS (SImode
, XEXP (x
, 0), const0_rtx
));
390 output_address (XEXP (x
, 0));
395 gcc_assert (INTVAL (x
) >= -128 && INTVAL (x
) <= 255);
396 fprintf (file
, "%d", (int)((~INTVAL (x
)) & 0xff));
400 gcc_assert (INTVAL (x
) >= -128 && INTVAL (x
) <= 255);
401 fprintf (file
, "%d", (int)(INTVAL (x
) & 0xff));
404 /* For shift counts. The hardware ignores the upper bits of
405 any immediate, but the assembler will flag an out of range
406 shift count as an error. So we mask off the high bits
407 of the immediate here. */
411 fprintf (file
, "%d", (int)(INTVAL (x
) & 0x1f));
417 switch (GET_CODE (x
))
421 output_address (XEXP (x
, 0));
430 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
434 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
437 /* This will only be single precision.... */
443 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
444 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
445 fprintf (file
, "0x%lx", val
);
455 mn10300_print_operand_address (file
, x
);
464 /* Output assembly language output for the address ADDR to FILE. */
467 mn10300_print_operand_address (FILE *file
, rtx addr
)
469 switch (GET_CODE (addr
))
472 mn10300_print_operand (file
, XEXP (addr
, 0), 0);
477 mn10300_print_operand (file
, XEXP (addr
, 0), 0);
480 mn10300_print_operand (file
, XEXP (addr
, 1), 0);
484 mn10300_print_operand (file
, addr
, 0);
488 rtx base
= XEXP (addr
, 0);
489 rtx index
= XEXP (addr
, 1);
491 if (REG_P (index
) && !REG_OK_FOR_INDEX_P (index
))
497 gcc_assert (REG_P (index
) && REG_OK_FOR_INDEX_P (index
));
499 gcc_assert (REG_OK_FOR_BASE_P (base
));
501 mn10300_print_operand (file
, index
, 0);
503 mn10300_print_operand (file
, base
, 0);
507 output_addr_const (file
, addr
);
510 output_addr_const (file
, addr
);
515 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA.
517 Used for PIC-specific UNSPECs. */
520 mn10300_asm_output_addr_const_extra (FILE *file
, rtx x
)
522 if (GET_CODE (x
) == UNSPEC
)
527 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
528 output_addr_const (file
, XVECEXP (x
, 0, 0));
531 output_addr_const (file
, XVECEXP (x
, 0, 0));
532 fputs ("@GOT", file
);
535 output_addr_const (file
, XVECEXP (x
, 0, 0));
536 fputs ("@GOTOFF", file
);
539 output_addr_const (file
, XVECEXP (x
, 0, 0));
540 fputs ("@PLT", file
);
542 case UNSPEC_GOTSYM_OFF
:
543 assemble_name (file
, GOT_SYMBOL_NAME
);
545 output_addr_const (file
, XVECEXP (x
, 0, 0));
557 /* Count the number of FP registers that have to be saved. */
559 fp_regs_to_save (void)
566 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
567 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
573 /* Print a set of registers in the format required by "movm" and "ret".
574 Register K is saved if bit K of MASK is set. The data and address
575 registers can be stored individually, but the extended registers cannot.
576 We assume that the mask already takes that into account. For instance,
577 bits 14 to 17 must have the same value. */
580 mn10300_print_reg_list (FILE *file
, int mask
)
588 for (i
= 0; i
< FIRST_EXTENDED_REGNUM
; i
++)
589 if ((mask
& (1 << i
)) != 0)
593 fputs (reg_names
[i
], file
);
597 if ((mask
& 0x3c000) != 0)
599 gcc_assert ((mask
& 0x3c000) == 0x3c000);
602 fputs ("exreg1", file
);
609 /* If the MDR register is never clobbered, we can use the RETF instruction
610 which takes the address from the MDR register. This is 3 cycles faster
611 than having to load the address from the stack. */
614 mn10300_can_use_retf_insn (void)
616 /* Don't bother if we're not optimizing. In this case we won't
617 have proper access to df_regs_ever_live_p. */
621 /* EH returns alter the saved return address; MDR is not current. */
622 if (crtl
->calls_eh_return
)
625 /* Obviously not if MDR is ever clobbered. */
626 if (df_regs_ever_live_p (MDR_REG
))
629 /* ??? Careful not to use this during expand_epilogue etc. */
630 gcc_assert (!in_sequence_p ());
631 return leaf_function_p ();
635 mn10300_can_use_rets_insn (void)
637 return !mn10300_initial_offset (ARG_POINTER_REGNUM
, STACK_POINTER_REGNUM
);
640 /* Returns the set of live, callee-saved registers as a bitmask. The
641 callee-saved extended registers cannot be stored individually, so
642 all of them will be included in the mask if any one of them is used.
643 Also returns the number of bytes in the registers in the mask if
644 BYTES_SAVED is not NULL. */
647 mn10300_get_live_callee_saved_regs (unsigned int * bytes_saved
)
654 for (i
= 0; i
<= LAST_EXTENDED_REGNUM
; i
++)
655 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
661 if ((mask
& 0x3c000) != 0)
663 for (i
= 0x04000; i
< 0x40000; i
<<= 1)
671 * bytes_saved
= count
* UNITS_PER_WORD
;
679 RTX_FRAME_RELATED_P (r
) = 1;
683 /* Generate an instruction that pushes several registers onto the stack.
684 Register K will be saved if bit K in MASK is set. The function does
685 nothing if MASK is zero.
687 To be compatible with the "movm" instruction, the lowest-numbered
688 register must be stored in the lowest slot. If MASK is the set
689 { R1,...,RN }, where R1...RN are ordered least first, the generated
690 instruction will have the form:
693 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
694 (set (mem:SI (plus:SI (reg:SI 9)
698 (set (mem:SI (plus:SI (reg:SI 9)
703 mn10300_gen_multiple_store (unsigned int mask
)
705 /* The order in which registers are stored, from SP-4 through SP-N*4. */
706 static const unsigned int store_order
[8] = {
707 /* e2, e3: never saved */
708 FIRST_EXTENDED_REGNUM
+ 4,
709 FIRST_EXTENDED_REGNUM
+ 5,
710 FIRST_EXTENDED_REGNUM
+ 6,
711 FIRST_EXTENDED_REGNUM
+ 7,
712 /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */
713 FIRST_DATA_REGNUM
+ 2,
714 FIRST_DATA_REGNUM
+ 3,
715 FIRST_ADDRESS_REGNUM
+ 2,
716 FIRST_ADDRESS_REGNUM
+ 3,
717 /* d0, d1, a0, a1, mdr, lir, lar: never saved. */
727 for (i
= count
= 0; i
< ARRAY_SIZE(store_order
); ++i
)
729 unsigned regno
= store_order
[i
];
731 if (((mask
>> regno
) & 1) == 0)
735 x
= plus_constant (Pmode
, stack_pointer_rtx
, count
* -4);
736 x
= gen_frame_mem (SImode
, x
);
737 x
= gen_rtx_SET (VOIDmode
, x
, gen_rtx_REG (SImode
, regno
));
740 /* Remove the register from the mask so that... */
741 mask
&= ~(1u << regno
);
744 /* ... we can make sure that we didn't try to use a register
745 not listed in the store order. */
746 gcc_assert (mask
== 0);
748 /* Create the instruction that updates the stack pointer. */
749 x
= plus_constant (Pmode
, stack_pointer_rtx
, count
* -4);
750 x
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, x
);
753 /* We need one PARALLEL element to update the stack pointer and
754 an additional element for each register that is stored. */
755 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (count
+ 1, elts
));
759 static inline unsigned int
760 popcount (unsigned int mask
)
762 unsigned int count
= 0;
767 mask
&= ~ (mask
& - mask
);
773 mn10300_expand_prologue (void)
775 HOST_WIDE_INT size
= mn10300_frame_size ();
778 mask
= mn10300_get_live_callee_saved_regs (NULL
);
779 /* If we use any of the callee-saved registers, save them now. */
780 mn10300_gen_multiple_store (mask
);
782 if (flag_stack_usage_info
)
783 current_function_static_stack_size
= size
+ popcount (mask
) * 4;
785 if (TARGET_AM33_2
&& fp_regs_to_save ())
787 int num_regs_to_save
= fp_regs_to_save (), i
;
793 save_sp_partial_merge
,
797 unsigned int strategy_size
= (unsigned)-1, this_strategy_size
;
800 if (flag_stack_usage_info
)
801 current_function_static_stack_size
+= num_regs_to_save
* 4;
803 /* We have several different strategies to save FP registers.
804 We can store them using SP offsets, which is beneficial if
805 there are just a few registers to save, or we can use `a0' in
806 post-increment mode (`a0' is the only call-clobbered address
807 register that is never used to pass information to a
808 function). Furthermore, if we don't need a frame pointer, we
809 can merge the two SP adds into a single one, but this isn't
810 always beneficial; sometimes we can just split the two adds
811 so that we don't exceed a 16-bit constant size. The code
812 below will select which strategy to use, so as to generate
813 smallest code. Ties are broken in favor or shorter sequences
814 (in terms of number of instructions). */
816 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
817 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
818 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
819 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
821 /* We add 0 * (S) in two places to promote to the type of S,
822 so that all arms of the conditional have the same type. */
823 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
824 (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \
825 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
826 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
828 #define SIZE_FMOV_SP_(S,N) \
829 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
830 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
831 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
832 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
834 /* Consider alternative save_sp_merge only if we don't need the
835 frame pointer and size is nonzero. */
836 if (! frame_pointer_needed
&& size
)
838 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
839 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
840 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
841 this_strategy_size
+= SIZE_FMOV_SP (size
, num_regs_to_save
);
843 if (this_strategy_size
< strategy_size
)
845 strategy
= save_sp_merge
;
846 strategy_size
= this_strategy_size
;
850 /* Consider alternative save_sp_no_merge unconditionally. */
851 /* Insn: add -4 * num_regs_to_save, sp. */
852 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
853 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
854 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
857 /* Insn: add -size, sp. */
858 this_strategy_size
+= SIZE_ADD_SP (-size
);
861 if (this_strategy_size
< strategy_size
)
863 strategy
= save_sp_no_merge
;
864 strategy_size
= this_strategy_size
;
867 /* Consider alternative save_sp_partial_merge only if we don't
868 need a frame pointer and size is reasonably large. */
869 if (! frame_pointer_needed
&& size
+ 4 * num_regs_to_save
> 128)
871 /* Insn: add -128, sp. */
872 this_strategy_size
= SIZE_ADD_SP (-128);
873 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
874 this_strategy_size
+= SIZE_FMOV_SP (128 - 4 * num_regs_to_save
,
878 /* Insn: add 128-size, sp. */
879 this_strategy_size
+= SIZE_ADD_SP (128 - size
);
882 if (this_strategy_size
< strategy_size
)
884 strategy
= save_sp_partial_merge
;
885 strategy_size
= this_strategy_size
;
889 /* Consider alternative save_a0_merge only if we don't need a
890 frame pointer, size is nonzero and the user hasn't
891 changed the calling conventions of a0. */
892 if (! frame_pointer_needed
&& size
893 && call_really_used_regs
[FIRST_ADDRESS_REGNUM
]
894 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
896 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
897 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
898 /* Insn: mov sp, a0. */
899 this_strategy_size
++;
902 /* Insn: add size, a0. */
903 this_strategy_size
+= SIZE_ADD_AX (size
);
905 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
906 this_strategy_size
+= 3 * num_regs_to_save
;
908 if (this_strategy_size
< strategy_size
)
910 strategy
= save_a0_merge
;
911 strategy_size
= this_strategy_size
;
915 /* Consider alternative save_a0_no_merge if the user hasn't
916 changed the calling conventions of a0. */
917 if (call_really_used_regs
[FIRST_ADDRESS_REGNUM
]
918 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
920 /* Insn: add -4 * num_regs_to_save, sp. */
921 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
922 /* Insn: mov sp, a0. */
923 this_strategy_size
++;
924 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
925 this_strategy_size
+= 3 * num_regs_to_save
;
928 /* Insn: add -size, sp. */
929 this_strategy_size
+= SIZE_ADD_SP (-size
);
932 if (this_strategy_size
< strategy_size
)
934 strategy
= save_a0_no_merge
;
935 strategy_size
= this_strategy_size
;
939 /* Emit the initial SP add, common to all strategies. */
942 case save_sp_no_merge
:
943 case save_a0_no_merge
:
944 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
946 GEN_INT (-4 * num_regs_to_save
))));
950 case save_sp_partial_merge
:
951 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
954 xsize
= 128 - 4 * num_regs_to_save
;
960 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
962 GEN_INT (-(size
+ 4 * num_regs_to_save
)))));
963 /* We'll have to adjust FP register saves according to the
966 /* Since we've already created the stack frame, don't do it
967 again at the end of the function. */
975 /* Now prepare register a0, if we have decided to use it. */
979 case save_sp_no_merge
:
980 case save_sp_partial_merge
:
985 case save_a0_no_merge
:
986 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
);
987 F (emit_insn (gen_movsi (reg
, stack_pointer_rtx
)));
989 F (emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (xsize
))));
990 reg
= gen_rtx_POST_INC (SImode
, reg
);
997 /* Now actually save the FP registers. */
998 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
999 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
1007 /* If we aren't using `a0', use an SP offset. */
1010 addr
= gen_rtx_PLUS (SImode
,
1015 addr
= stack_pointer_rtx
;
1020 F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode
, addr
),
1021 gen_rtx_REG (SFmode
, i
))));
1025 /* Now put the frame pointer into the frame pointer register. */
1026 if (frame_pointer_needed
)
1027 F (emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
));
1029 /* Allocate stack for this frame. */
1031 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1035 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
1036 emit_insn (gen_load_pic ());
1040 mn10300_expand_epilogue (void)
1042 HOST_WIDE_INT size
= mn10300_frame_size ();
1043 unsigned int reg_save_bytes
;
1045 mn10300_get_live_callee_saved_regs (& reg_save_bytes
);
1047 if (TARGET_AM33_2
&& fp_regs_to_save ())
1049 int num_regs_to_save
= fp_regs_to_save (), i
;
1052 /* We have several options to restore FP registers. We could
1053 load them from SP offsets, but, if there are enough FP
1054 registers to restore, we win if we use a post-increment
1057 /* If we have a frame pointer, it's the best option, because we
1058 already know it has the value we want. */
1059 if (frame_pointer_needed
)
1060 reg
= gen_rtx_REG (SImode
, FRAME_POINTER_REGNUM
);
1061 /* Otherwise, we may use `a1', since it's call-clobbered and
1062 it's never used for return values. But only do so if it's
1063 smaller than using SP offsets. */
1066 enum { restore_sp_post_adjust
,
1067 restore_sp_pre_adjust
,
1068 restore_sp_partial_adjust
,
1069 restore_a1
} strategy
;
1070 unsigned int this_strategy_size
, strategy_size
= (unsigned)-1;
1072 /* Consider using sp offsets before adjusting sp. */
1073 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1074 this_strategy_size
= SIZE_FMOV_SP (size
, num_regs_to_save
);
1075 /* If size is too large, we'll have to adjust SP with an
1077 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1079 /* Insn: add size + 4 * num_regs_to_save, sp. */
1080 this_strategy_size
+= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
);
1082 /* If we don't have to restore any non-FP registers,
1083 we'll be able to save one byte by using rets. */
1084 if (! reg_save_bytes
)
1085 this_strategy_size
--;
1087 if (this_strategy_size
< strategy_size
)
1089 strategy
= restore_sp_post_adjust
;
1090 strategy_size
= this_strategy_size
;
1093 /* Consider using sp offsets after adjusting sp. */
1094 /* Insn: add size, sp. */
1095 this_strategy_size
= SIZE_ADD_SP (size
);
1096 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1097 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
1098 /* We're going to use ret to release the FP registers
1099 save area, so, no savings. */
1101 if (this_strategy_size
< strategy_size
)
1103 strategy
= restore_sp_pre_adjust
;
1104 strategy_size
= this_strategy_size
;
1107 /* Consider using sp offsets after partially adjusting sp.
1108 When size is close to 32Kb, we may be able to adjust SP
1109 with an imm16 add instruction while still using fmov
1111 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1113 /* Insn: add size + 4 * num_regs_to_save
1114 + reg_save_bytes - 252,sp. */
1115 this_strategy_size
= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
1116 + (int) reg_save_bytes
- 252);
1117 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1118 this_strategy_size
+= SIZE_FMOV_SP (252 - reg_save_bytes
1119 - 4 * num_regs_to_save
,
1121 /* We're going to use ret to release the FP registers
1122 save area, so, no savings. */
1124 if (this_strategy_size
< strategy_size
)
1126 strategy
= restore_sp_partial_adjust
;
1127 strategy_size
= this_strategy_size
;
1131 /* Consider using a1 in post-increment mode, as long as the
1132 user hasn't changed the calling conventions of a1. */
1133 if (call_really_used_regs
[FIRST_ADDRESS_REGNUM
+ 1]
1134 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
+1])
1136 /* Insn: mov sp,a1. */
1137 this_strategy_size
= 1;
1140 /* Insn: add size,a1. */
1141 this_strategy_size
+= SIZE_ADD_AX (size
);
1143 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1144 this_strategy_size
+= 3 * num_regs_to_save
;
1145 /* If size is large enough, we may be able to save a
1147 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1149 /* Insn: mov a1,sp. */
1150 this_strategy_size
+= 2;
1152 /* If we don't have to restore any non-FP registers,
1153 we'll be able to save one byte by using rets. */
1154 if (! reg_save_bytes
)
1155 this_strategy_size
--;
1157 if (this_strategy_size
< strategy_size
)
1159 strategy
= restore_a1
;
1160 strategy_size
= this_strategy_size
;
1166 case restore_sp_post_adjust
:
1169 case restore_sp_pre_adjust
:
1170 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1176 case restore_sp_partial_adjust
:
1177 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1179 GEN_INT (size
+ 4 * num_regs_to_save
1180 + reg_save_bytes
- 252)));
1181 size
= 252 - reg_save_bytes
- 4 * num_regs_to_save
;
1185 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
+ 1);
1186 emit_insn (gen_movsi (reg
, stack_pointer_rtx
));
1188 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
1196 /* Adjust the selected register, if any, for post-increment. */
1198 reg
= gen_rtx_POST_INC (SImode
, reg
);
1200 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
1201 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
1209 /* If we aren't using a post-increment register, use an
1211 addr
= gen_rtx_PLUS (SImode
,
1216 addr
= stack_pointer_rtx
;
1220 emit_insn (gen_movsf (gen_rtx_REG (SFmode
, i
),
1221 gen_rtx_MEM (SFmode
, addr
)));
1224 /* If we were using the restore_a1 strategy and the number of
1225 bytes to be released won't fit in the `ret' byte, copy `a1'
1226 to `sp', to avoid having to use `add' to adjust it. */
1227 if (! frame_pointer_needed
&& reg
&& size
+ reg_save_bytes
> 255)
1229 emit_move_insn (stack_pointer_rtx
, XEXP (reg
, 0));
1234 /* Maybe cut back the stack, except for the register save area.
1236 If the frame pointer exists, then use the frame pointer to
1239 If the stack size + register save area is more than 255 bytes,
1240 then the stack must be cut back here since the size + register
1241 save size is too big for a ret/retf instruction.
1243 Else leave it alone, it will be cut back as part of the
1244 ret/retf instruction, or there wasn't any stack to begin with.
1246 Under no circumstances should the register save area be
1247 deallocated here, that would leave a window where an interrupt
1248 could occur and trash the register save area. */
1249 if (frame_pointer_needed
)
1251 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
1254 else if (size
+ reg_save_bytes
> 255)
1256 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1262 /* Adjust the stack and restore callee-saved registers, if any. */
1263 if (mn10300_can_use_rets_insn ())
1264 emit_jump_insn (ret_rtx
);
1266 emit_jump_insn (gen_return_ret (GEN_INT (size
+ reg_save_bytes
)));
1269 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1270 This function is for MATCH_PARALLEL and so assumes OP is known to be
1271 parallel. If OP is a multiple store, return a mask indicating which
1272 registers it saves. Return 0 otherwise. */
1275 mn10300_store_multiple_regs (rtx op
)
1283 count
= XVECLEN (op
, 0);
1287 /* Check that first instruction has the form (set (sp) (plus A B)) */
1288 elt
= XVECEXP (op
, 0, 0);
1289 if (GET_CODE (elt
) != SET
1290 || (! REG_P (SET_DEST (elt
)))
1291 || REGNO (SET_DEST (elt
)) != STACK_POINTER_REGNUM
1292 || GET_CODE (SET_SRC (elt
)) != PLUS
)
1295 /* Check that A is the stack pointer and B is the expected stack size.
1296 For OP to match, each subsequent instruction should push a word onto
1297 the stack. We therefore expect the first instruction to create
1298 COUNT-1 stack slots. */
1299 elt
= SET_SRC (elt
);
1300 if ((! REG_P (XEXP (elt
, 0)))
1301 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1302 || (! CONST_INT_P (XEXP (elt
, 1)))
1303 || INTVAL (XEXP (elt
, 1)) != -(count
- 1) * 4)
1307 for (i
= 1; i
< count
; i
++)
1309 /* Check that element i is a (set (mem M) R). */
1310 /* ??? Validate the register order a-la mn10300_gen_multiple_store.
1311 Remember: the ordering is *not* monotonic. */
1312 elt
= XVECEXP (op
, 0, i
);
1313 if (GET_CODE (elt
) != SET
1314 || (! MEM_P (SET_DEST (elt
)))
1315 || (! REG_P (SET_SRC (elt
))))
1318 /* Remember which registers are to be saved. */
1319 last
= REGNO (SET_SRC (elt
));
1320 mask
|= (1 << last
);
1322 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1323 elt
= XEXP (SET_DEST (elt
), 0);
1324 if (GET_CODE (elt
) != PLUS
1325 || (! REG_P (XEXP (elt
, 0)))
1326 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1327 || (! CONST_INT_P (XEXP (elt
, 1)))
1328 || INTVAL (XEXP (elt
, 1)) != -i
* 4)
1332 /* All or none of the callee-saved extended registers must be in the set. */
1333 if ((mask
& 0x3c000) != 0
1334 && (mask
& 0x3c000) != 0x3c000)
1340 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
1343 mn10300_preferred_reload_class (rtx x
, reg_class_t rclass
)
1345 if (x
== stack_pointer_rtx
&& rclass
!= SP_REGS
)
1346 return (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
1349 && !HARD_REGISTER_P (x
))
1350 || (GET_CODE (x
) == SUBREG
1351 && REG_P (SUBREG_REG (x
))
1352 && !HARD_REGISTER_P (SUBREG_REG (x
))))
1353 return LIMIT_RELOAD_CLASS (GET_MODE (x
), rclass
);
1358 /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
1361 mn10300_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
1363 if (x
== stack_pointer_rtx
&& rclass
!= SP_REGS
)
1364 return (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
1368 /* Implement TARGET_SECONDARY_RELOAD. */
1371 mn10300_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
1372 machine_mode mode
, secondary_reload_info
*sri
)
1374 enum reg_class rclass
= (enum reg_class
) rclass_i
;
1375 enum reg_class xclass
= NO_REGS
;
1376 unsigned int xregno
= INVALID_REGNUM
;
1381 if (xregno
>= FIRST_PSEUDO_REGISTER
)
1382 xregno
= true_regnum (x
);
1383 if (xregno
!= INVALID_REGNUM
)
1384 xclass
= REGNO_REG_CLASS (xregno
);
1389 /* Memory load/stores less than a full word wide can't have an
1390 address or stack pointer destination. They must use a data
1391 register as an intermediate register. */
1392 if (rclass
!= DATA_REGS
1393 && (mode
== QImode
|| mode
== HImode
)
1394 && xclass
== NO_REGS
)
1397 /* We can only move SP to/from an address register. */
1399 && rclass
== SP_REGS
1400 && xclass
!= ADDRESS_REGS
)
1401 return ADDRESS_REGS
;
1403 && xclass
== SP_REGS
1404 && rclass
!= ADDRESS_REGS
1405 && rclass
!= SP_OR_ADDRESS_REGS
)
1406 return ADDRESS_REGS
;
1409 /* We can't directly load sp + const_int into a register;
1410 we must use an address register as an scratch. */
1412 && rclass
!= SP_REGS
1413 && rclass
!= SP_OR_ADDRESS_REGS
1414 && rclass
!= SP_OR_GENERAL_REGS
1415 && GET_CODE (x
) == PLUS
1416 && (XEXP (x
, 0) == stack_pointer_rtx
1417 || XEXP (x
, 1) == stack_pointer_rtx
))
1419 sri
->icode
= CODE_FOR_reload_plus_sp_const
;
1423 /* We can only move MDR to/from a data register. */
1424 if (rclass
== MDR_REGS
&& xclass
!= DATA_REGS
)
1426 if (xclass
== MDR_REGS
&& rclass
!= DATA_REGS
)
1429 /* We can't load/store an FP register from a constant address. */
1431 && (rclass
== FP_REGS
|| xclass
== FP_REGS
)
1432 && (xclass
== NO_REGS
|| rclass
== NO_REGS
))
1436 if (xregno
>= FIRST_PSEUDO_REGISTER
&& xregno
!= INVALID_REGNUM
)
1438 addr
= reg_equiv_mem (xregno
);
1440 addr
= XEXP (addr
, 0);
1445 if (addr
&& CONSTANT_ADDRESS_P (addr
))
1446 return GENERAL_REGS
;
1448 /* Otherwise assume no secondary reloads are needed. */
1453 mn10300_frame_size (void)
1455 /* size includes the fixed stack space needed for function calls. */
1456 int size
= get_frame_size () + crtl
->outgoing_args_size
;
1458 /* And space for the return pointer. */
1459 size
+= crtl
->outgoing_args_size
? 4 : 0;
1465 mn10300_initial_offset (int from
, int to
)
1469 gcc_assert (from
== ARG_POINTER_REGNUM
|| from
== FRAME_POINTER_REGNUM
);
1470 gcc_assert (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
1472 if (to
== STACK_POINTER_REGNUM
)
1473 diff
= mn10300_frame_size ();
1475 /* The difference between the argument pointer and the frame pointer
1476 is the size of the callee register save area. */
1477 if (from
== ARG_POINTER_REGNUM
)
1479 unsigned int reg_save_bytes
;
1481 mn10300_get_live_callee_saved_regs (& reg_save_bytes
);
1482 diff
+= reg_save_bytes
;
1483 diff
+= 4 * fp_regs_to_save ();
1489 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1492 mn10300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1494 /* Return values > 8 bytes in length in memory. */
1495 return (int_size_in_bytes (type
) > 8
1496 || int_size_in_bytes (type
) == 0
1497 || TYPE_MODE (type
) == BLKmode
);
1500 /* Flush the argument registers to the stack for a stdarg function;
1501 return the new argument pointer. */
1503 mn10300_builtin_saveregs (void)
1506 tree fntype
= TREE_TYPE (current_function_decl
);
1507 int argadj
= ((!stdarg_p (fntype
))
1508 ? UNITS_PER_WORD
: 0);
1509 alias_set_type set
= get_varargs_alias_set ();
1512 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, argadj
);
1514 offset
= crtl
->args
.arg_offset_rtx
;
1516 mem
= gen_rtx_MEM (SImode
, crtl
->args
.internal_arg_pointer
);
1517 set_mem_alias_set (mem
, set
);
1518 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
1520 mem
= gen_rtx_MEM (SImode
,
1521 plus_constant (Pmode
,
1522 crtl
->args
.internal_arg_pointer
, 4));
1523 set_mem_alias_set (mem
, set
);
1524 emit_move_insn (mem
, gen_rtx_REG (SImode
, 1));
1526 return copy_to_reg (expand_binop (Pmode
, add_optab
,
1527 crtl
->args
.internal_arg_pointer
,
1528 offset
, 0, 0, OPTAB_LIB_WIDEN
));
1532 mn10300_va_start (tree valist
, rtx nextarg
)
1534 nextarg
= expand_builtin_saveregs ();
1535 std_expand_builtin_va_start (valist
, nextarg
);
1538 /* Return true when a parameter should be passed by reference. */
1541 mn10300_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1542 machine_mode mode
, const_tree type
,
1543 bool named ATTRIBUTE_UNUSED
)
1545 unsigned HOST_WIDE_INT size
;
1548 size
= int_size_in_bytes (type
);
1550 size
= GET_MODE_SIZE (mode
);
1552 return (size
> 8 || size
== 0);
1555 /* Return an RTX to represent where a value with mode MODE will be returned
1556 from a function. If the result is NULL_RTX, the argument is pushed. */
1559 mn10300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1560 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1562 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1563 rtx result
= NULL_RTX
;
1566 /* We only support using 2 data registers as argument registers. */
1569 /* Figure out the size of the object to be passed. */
1570 if (mode
== BLKmode
)
1571 size
= int_size_in_bytes (type
);
1573 size
= GET_MODE_SIZE (mode
);
1575 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1577 /* Don't pass this arg via a register if all the argument registers
1579 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1582 /* Don't pass this arg via a register if it would be split between
1583 registers and memory. */
1584 if (type
== NULL_TREE
1585 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1588 switch (cum
->nbytes
/ UNITS_PER_WORD
)
1591 result
= gen_rtx_REG (mode
, FIRST_ARGUMENT_REGNUM
);
1594 result
= gen_rtx_REG (mode
, FIRST_ARGUMENT_REGNUM
+ 1);
1603 /* Update the data in CUM to advance over an argument
1604 of mode MODE and data type TYPE.
1605 (TYPE is null for libcalls where that information may not be available.) */
1608 mn10300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1609 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1611 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1613 cum
->nbytes
+= (mode
!= BLKmode
1614 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1615 : (int_size_in_bytes (type
) + 3) & ~3);
1618 /* Return the number of bytes of registers to use for an argument passed
1619 partially in registers and partially in memory. */
1622 mn10300_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
1623 tree type
, bool named ATTRIBUTE_UNUSED
)
1625 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1628 /* We only support using 2 data registers as argument registers. */
1631 /* Figure out the size of the object to be passed. */
1632 if (mode
== BLKmode
)
1633 size
= int_size_in_bytes (type
);
1635 size
= GET_MODE_SIZE (mode
);
1637 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1639 /* Don't pass this arg via a register if all the argument registers
1641 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1644 if (cum
->nbytes
+ size
<= nregs
* UNITS_PER_WORD
)
1647 /* Don't pass this arg via a register if it would be split between
1648 registers and memory. */
1649 if (type
== NULL_TREE
1650 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1653 return nregs
* UNITS_PER_WORD
- cum
->nbytes
;
1656 /* Return the location of the function's value. This will be either
1657 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1658 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1659 we only return the PARALLEL for outgoing values; we do not want
1660 callers relying on this extra copy. */
1663 mn10300_function_value (const_tree valtype
,
1664 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1668 machine_mode mode
= TYPE_MODE (valtype
);
1670 if (! POINTER_TYPE_P (valtype
))
1671 return gen_rtx_REG (mode
, FIRST_DATA_REGNUM
);
1672 else if (! TARGET_PTR_A0D0
|| ! outgoing
1673 || cfun
->returns_struct
)
1674 return gen_rtx_REG (mode
, FIRST_ADDRESS_REGNUM
);
1676 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (2));
1678 = gen_rtx_EXPR_LIST (VOIDmode
,
1679 gen_rtx_REG (mode
, FIRST_ADDRESS_REGNUM
),
1683 = gen_rtx_EXPR_LIST (VOIDmode
,
1684 gen_rtx_REG (mode
, FIRST_DATA_REGNUM
),
1689 /* Implements TARGET_LIBCALL_VALUE. */
1692 mn10300_libcall_value (machine_mode mode
,
1693 const_rtx fun ATTRIBUTE_UNUSED
)
1695 return gen_rtx_REG (mode
, FIRST_DATA_REGNUM
);
1698 /* Implements FUNCTION_VALUE_REGNO_P. */
1701 mn10300_function_value_regno_p (const unsigned int regno
)
1703 return (regno
== FIRST_DATA_REGNUM
|| regno
== FIRST_ADDRESS_REGNUM
);
1706 /* Output an addition operation. */
1709 mn10300_output_add (rtx operands
[3], bool need_flags
)
1711 rtx dest
, src1
, src2
;
1712 unsigned int dest_regnum
, src1_regnum
, src2_regnum
;
1713 enum reg_class src1_class
, src2_class
, dest_class
;
1719 dest_regnum
= true_regnum (dest
);
1720 src1_regnum
= true_regnum (src1
);
1722 dest_class
= REGNO_REG_CLASS (dest_regnum
);
1723 src1_class
= REGNO_REG_CLASS (src1_regnum
);
1725 if (CONST_INT_P (src2
))
1727 gcc_assert (dest_regnum
== src1_regnum
);
1729 if (src2
== const1_rtx
&& !need_flags
)
1731 if (INTVAL (src2
) == 4 && !need_flags
&& dest_class
!= DATA_REGS
)
1734 gcc_assert (!need_flags
|| dest_class
!= SP_REGS
);
1737 else if (CONSTANT_P (src2
))
1740 src2_regnum
= true_regnum (src2
);
1741 src2_class
= REGNO_REG_CLASS (src2_regnum
);
1743 if (dest_regnum
== src1_regnum
)
1745 if (dest_regnum
== src2_regnum
)
1748 /* The rest of the cases are reg = reg+reg. For AM33, we can implement
1749 this directly, as below, but when optimizing for space we can sometimes
1750 do better by using a mov+add. For MN103, we claimed that we could
1751 implement a three-operand add because the various move and add insns
1752 change sizes across register classes, and we can often do better than
1753 reload in choosing which operand to move. */
1754 if (TARGET_AM33
&& optimize_insn_for_speed_p ())
1755 return "add %2,%1,%0";
1757 /* Catch cases where no extended register was used. */
1758 if (src1_class
!= EXTENDED_REGS
1759 && src2_class
!= EXTENDED_REGS
1760 && dest_class
!= EXTENDED_REGS
)
1762 /* We have to copy one of the sources into the destination, then
1763 add the other source to the destination.
1765 Carefully select which source to copy to the destination; a
1766 naive implementation will waste a byte when the source classes
1767 are different and the destination is an address register.
1768 Selecting the lowest cost register copy will optimize this
1770 if (src1_class
== dest_class
)
1771 return "mov %1,%0\n\tadd %2,%0";
1773 return "mov %2,%0\n\tadd %1,%0";
1776 /* At least one register is an extended register. */
1778 /* The three operand add instruction on the am33 is a win iff the
1779 output register is an extended register, or if both source
1780 registers are extended registers. */
1781 if (dest_class
== EXTENDED_REGS
|| src1_class
== src2_class
)
1782 return "add %2,%1,%0";
1784 /* It is better to copy one of the sources to the destination, then
1785 perform a 2 address add. The destination in this case must be
1786 an address or data register and one of the sources must be an
1787 extended register and the remaining source must not be an extended
1790 The best code for this case is to copy the extended reg to the
1791 destination, then emit a two address add. */
1792 if (src1_class
== EXTENDED_REGS
)
1793 return "mov %1,%0\n\tadd %2,%0";
1795 return "mov %2,%0\n\tadd %1,%0";
1798 /* Return 1 if X contains a symbolic expression. We know these
1799 expressions will have one of a few well defined forms, so
1800 we need only check those forms. */
1803 mn10300_symbolic_operand (rtx op
,
1804 machine_mode mode ATTRIBUTE_UNUSED
)
1806 switch (GET_CODE (op
))
1813 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1814 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1815 && CONST_INT_P (XEXP (op
, 1)));
1821 /* Try machine dependent ways of modifying an illegitimate address
1822 to be legitimate. If we find one, return the new valid address.
1823 This macro is used in only one place: `memory_address' in explow.c.
1825 OLDX is the address as it was before break_out_memory_refs was called.
1826 In some cases it is useful to look at this to decide what needs to be done.
1828 Normally it is always safe for this macro to do nothing. It exists to
1829 recognize opportunities to optimize the output.
1831 But on a few ports with segmented architectures and indexed addressing
1832 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1835 mn10300_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1836 machine_mode mode ATTRIBUTE_UNUSED
)
1838 if (flag_pic
&& ! mn10300_legitimate_pic_operand_p (x
))
1839 x
= mn10300_legitimize_pic_address (oldx
, NULL_RTX
);
1841 /* Uh-oh. We might have an address for x[n-100000]. This needs
1842 special handling to avoid creating an indexed memory address
1843 with x-100000 as the base. */
1844 if (GET_CODE (x
) == PLUS
1845 && mn10300_symbolic_operand (XEXP (x
, 1), VOIDmode
))
1847 /* Ugly. We modify things here so that the address offset specified
1848 by the index expression is computed first, then added to x to form
1849 the entire address. */
1851 rtx regx1
, regy1
, regy2
, y
;
1853 /* Strip off any CONST. */
1855 if (GET_CODE (y
) == CONST
)
1858 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1860 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1861 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1862 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1863 regx1
= force_reg (Pmode
,
1864 gen_rtx_fmt_ee (GET_CODE (y
), Pmode
, regx1
,
1866 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1872 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1873 @GOTOFF in `reg'. */
1876 mn10300_legitimize_pic_address (rtx orig
, rtx reg
)
1880 if (GET_CODE (orig
) == LABEL_REF
1881 || (GET_CODE (orig
) == SYMBOL_REF
1882 && (CONSTANT_POOL_ADDRESS_P (orig
)
1883 || ! MN10300_GLOBAL_P (orig
))))
1886 reg
= gen_reg_rtx (Pmode
);
1888 x
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, orig
), UNSPEC_GOTOFF
);
1889 x
= gen_rtx_CONST (SImode
, x
);
1890 emit_move_insn (reg
, x
);
1892 x
= emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1894 else if (GET_CODE (orig
) == SYMBOL_REF
)
1897 reg
= gen_reg_rtx (Pmode
);
1899 x
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, orig
), UNSPEC_GOT
);
1900 x
= gen_rtx_CONST (SImode
, x
);
1901 x
= gen_rtx_PLUS (SImode
, pic_offset_table_rtx
, x
);
1902 x
= gen_const_mem (SImode
, x
);
1904 x
= emit_move_insn (reg
, x
);
1909 set_unique_reg_note (x
, REG_EQUAL
, orig
);
1913 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1914 isn't protected by a PIC unspec; nonzero otherwise. */
1917 mn10300_legitimate_pic_operand_p (rtx x
)
1922 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1925 if (GET_CODE (x
) == UNSPEC
1926 && (XINT (x
, 1) == UNSPEC_PIC
1927 || XINT (x
, 1) == UNSPEC_GOT
1928 || XINT (x
, 1) == UNSPEC_GOTOFF
1929 || XINT (x
, 1) == UNSPEC_PLT
1930 || XINT (x
, 1) == UNSPEC_GOTSYM_OFF
))
1933 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
1934 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
1940 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1941 if (! mn10300_legitimate_pic_operand_p (XVECEXP (x
, i
, j
)))
1944 else if (fmt
[i
] == 'e'
1945 && ! mn10300_legitimate_pic_operand_p (XEXP (x
, i
)))
1952 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1953 legitimate, and FALSE otherwise.
1955 On the mn10300, the value in the address register must be
1956 in the same memory space/segment as the effective address.
1958 This is problematical for reload since it does not understand
1959 that base+index != index+base in a memory reference.
1961 Note it is still possible to use reg+reg addressing modes,
1962 it's just much more difficult. For a discussion of a possible
1963 workaround and solution, see the comments in pa.c before the
1964 function record_unscaled_index_insn_codes. */
1967 mn10300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1971 if (CONSTANT_ADDRESS_P (x
))
1972 return !flag_pic
|| mn10300_legitimate_pic_operand_p (x
);
1974 if (RTX_OK_FOR_BASE_P (x
, strict
))
1977 if (TARGET_AM33
&& (mode
== SImode
|| mode
== SFmode
|| mode
== HImode
))
1979 if (GET_CODE (x
) == POST_INC
)
1980 return RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
);
1981 if (GET_CODE (x
) == POST_MODIFY
)
1982 return (RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
)
1983 && CONSTANT_ADDRESS_P (XEXP (x
, 1)));
1986 if (GET_CODE (x
) != PLUS
)
1990 index
= XEXP (x
, 1);
1996 /* ??? Without AM33 generalized (Ri,Rn) addressing, reg+reg
1997 addressing is hard to satisfy. */
2001 return (REGNO_GENERAL_P (REGNO (base
), strict
)
2002 && REGNO_GENERAL_P (REGNO (index
), strict
));
2005 if (!REGNO_STRICT_OK_FOR_BASE_P (REGNO (base
), strict
))
2008 if (CONST_INT_P (index
))
2009 return IN_RANGE (INTVAL (index
), -1 - 0x7fffffff, 0x7fffffff);
2011 if (CONSTANT_ADDRESS_P (index
))
2012 return !flag_pic
|| mn10300_legitimate_pic_operand_p (index
);
2018 mn10300_regno_in_class_p (unsigned regno
, int rclass
, bool strict
)
2020 if (regno
>= FIRST_PSEUDO_REGISTER
)
2026 regno
= reg_renumber
[regno
];
2027 if (regno
== INVALID_REGNUM
)
2030 return TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
);
2034 mn10300_legitimize_reload_address (rtx x
,
2035 machine_mode mode ATTRIBUTE_UNUSED
,
2036 int opnum
, int type
,
2037 int ind_levels ATTRIBUTE_UNUSED
)
2039 bool any_change
= false;
2041 /* See above re disabling reg+reg addressing for MN103. */
2045 if (GET_CODE (x
) != PLUS
)
2048 if (XEXP (x
, 0) == stack_pointer_rtx
)
2050 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2051 GENERAL_REGS
, GET_MODE (x
), VOIDmode
, 0, 0,
2052 opnum
, (enum reload_type
) type
);
2055 if (XEXP (x
, 1) == stack_pointer_rtx
)
2057 push_reload (XEXP (x
, 1), NULL_RTX
, &XEXP (x
, 1), NULL
,
2058 GENERAL_REGS
, GET_MODE (x
), VOIDmode
, 0, 0,
2059 opnum
, (enum reload_type
) type
);
2063 return any_change
? x
: NULL_RTX
;
2066 /* Implement TARGET_LEGITIMATE_CONSTANT_P. Returns TRUE if X is a valid
2067 constant. Note that some "constants" aren't valid, such as TLS
2068 symbols and unconverted GOT-based references, so we eliminate
2072 mn10300_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2074 switch (GET_CODE (x
))
2079 if (GET_CODE (x
) == PLUS
)
2081 if (! CONST_INT_P (XEXP (x
, 1)))
2086 /* Only some unspecs are valid as "constants". */
2087 if (GET_CODE (x
) == UNSPEC
)
2089 switch (XINT (x
, 1))
2101 /* We must have drilled down to a symbol. */
2102 if (! mn10300_symbolic_operand (x
, Pmode
))
2113 /* Undo pic address legitimization for the benefit of debug info. */
2116 mn10300_delegitimize_address (rtx orig_x
)
2118 rtx x
= orig_x
, ret
, addend
= NULL
;
2123 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
2126 if (XEXP (x
, 0) == pic_offset_table_rtx
)
2128 /* With the REG+REG addressing of AM33, var-tracking can re-assemble
2129 some odd-looking "addresses" that were never valid in the first place.
2130 We need to look harder to avoid warnings being emitted. */
2131 else if (GET_CODE (XEXP (x
, 0)) == PLUS
)
2133 rtx x0
= XEXP (x
, 0);
2134 rtx x00
= XEXP (x0
, 0);
2135 rtx x01
= XEXP (x0
, 1);
2137 if (x00
== pic_offset_table_rtx
)
2139 else if (x01
== pic_offset_table_rtx
)
2149 if (GET_CODE (x
) != CONST
)
2152 if (GET_CODE (x
) != UNSPEC
)
2155 ret
= XVECEXP (x
, 0, 0);
2156 if (XINT (x
, 1) == UNSPEC_GOTOFF
)
2158 else if (XINT (x
, 1) == UNSPEC_GOT
)
2163 gcc_assert (GET_CODE (ret
) == SYMBOL_REF
);
2164 if (need_mem
!= MEM_P (orig_x
))
2166 if (need_mem
&& addend
)
2169 ret
= gen_rtx_PLUS (Pmode
, addend
, ret
);
2173 /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is
2174 the 3-byte fully general instruction; for MN103 this is the 2-byte form
2175 with an address register. */
2178 mn10300_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2179 addr_space_t as ATTRIBUTE_UNUSED
, bool speed
)
2184 switch (GET_CODE (x
))
2189 /* We assume all of these require a 32-bit constant, even though
2190 some symbol and label references can be relaxed. */
2191 return speed
? 1 : 4;
2199 /* Assume any symbolic offset is a 32-bit constant. */
2200 i
= (CONST_INT_P (XEXP (x
, 1)) ? INTVAL (XEXP (x
, 1)) : 0x12345678);
2201 if (IN_RANGE (i
, -128, 127))
2202 return speed
? 0 : 1;
2205 if (IN_RANGE (i
, -0x800000, 0x7fffff))
2211 index
= XEXP (x
, 1);
2212 if (register_operand (index
, SImode
))
2214 /* Attempt to minimize the number of registers in the address.
2215 This is similar to what other ports do. */
2216 if (register_operand (base
, SImode
))
2220 index
= XEXP (x
, 0);
2223 /* Assume any symbolic offset is a 32-bit constant. */
2224 i
= (CONST_INT_P (XEXP (x
, 1)) ? INTVAL (XEXP (x
, 1)) : 0x12345678);
2225 if (IN_RANGE (i
, -128, 127))
2226 return speed
? 0 : 1;
2227 if (IN_RANGE (i
, -32768, 32767))
2228 return speed
? 0 : 2;
2229 return speed
? 2 : 6;
2232 return rtx_cost (x
, MEM
, 0, speed
);
2236 /* Implement the TARGET_REGISTER_MOVE_COST hook.
2238 Recall that the base value of 2 is required by assumptions elsewhere
2239 in the body of the compiler, and that cost 2 is special-cased as an
2240 early exit from reload meaning no work is required. */
2243 mn10300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2244 reg_class_t ifrom
, reg_class_t ito
)
2246 enum reg_class from
= (enum reg_class
) ifrom
;
2247 enum reg_class to
= (enum reg_class
) ito
;
2248 enum reg_class scratch
, test
;
2250 /* Simplify the following code by unifying the fp register classes. */
2251 if (to
== FP_ACC_REGS
)
2253 if (from
== FP_ACC_REGS
)
2256 /* Diagnose invalid moves by costing them as two moves. */
2261 scratch
= (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
2262 else if (to
== MDR_REGS
)
2263 scratch
= DATA_REGS
;
2264 else if (to
== FP_REGS
&& to
!= from
)
2265 scratch
= GENERAL_REGS
;
2269 if (from
== SP_REGS
)
2270 scratch
= (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
2271 else if (from
== MDR_REGS
)
2272 scratch
= DATA_REGS
;
2273 else if (from
== FP_REGS
&& to
!= from
)
2274 scratch
= GENERAL_REGS
;
2276 if (scratch
!= NO_REGS
&& !reg_class_subset_p (test
, scratch
))
2277 return (mn10300_register_move_cost (VOIDmode
, from
, scratch
)
2278 + mn10300_register_move_cost (VOIDmode
, scratch
, to
));
2280 /* From here on, all we need consider are legal combinations. */
2284 /* The scale here is bytes * 2. */
2286 if (from
== to
&& (to
== ADDRESS_REGS
|| to
== DATA_REGS
))
2289 if (from
== SP_REGS
)
2290 return (to
== ADDRESS_REGS
? 2 : 6);
2292 /* For MN103, all remaining legal moves are two bytes. */
2297 return (from
== ADDRESS_REGS
? 4 : 6);
2299 if ((from
== ADDRESS_REGS
|| from
== DATA_REGS
)
2300 && (to
== ADDRESS_REGS
|| to
== DATA_REGS
))
2303 if (to
== EXTENDED_REGS
)
2304 return (to
== from
? 6 : 4);
2306 /* What's left are SP_REGS, FP_REGS, or combinations of the above. */
2311 /* The scale here is cycles * 2. */
2315 if (from
== FP_REGS
)
2318 /* All legal moves between integral registers are single cycle. */
2323 /* Implement the TARGET_MEMORY_MOVE_COST hook.
2325 Given lack of the form of the address, this must be speed-relative,
2326 though we should never be less expensive than a size-relative register
2327 move cost above. This is not a problem. */
2330 mn10300_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2331 reg_class_t iclass
, bool in ATTRIBUTE_UNUSED
)
2333 enum reg_class rclass
= (enum reg_class
) iclass
;
2335 if (rclass
== FP_REGS
)
2340 /* Implement the TARGET_RTX_COSTS hook.
2342 Speed-relative costs are relative to COSTS_N_INSNS, which is intended
2343 to represent cycles. Size-relative costs are in bytes. */
2346 mn10300_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2347 int *ptotal
, bool speed
)
2349 /* This value is used for SYMBOL_REF etc where we want to pretend
2350 we have a full 32-bit constant. */
2351 HOST_WIDE_INT i
= 0x12345678;
2361 if (outer_code
== SET
)
2363 /* 16-bit integer loads have latency 1, 32-bit loads 2. */
2364 if (IN_RANGE (i
, -32768, 32767))
2365 total
= COSTS_N_INSNS (1);
2367 total
= COSTS_N_INSNS (2);
2371 /* 16-bit integer operands don't affect latency;
2372 24-bit and 32-bit operands add a cycle. */
2373 if (IN_RANGE (i
, -32768, 32767))
2376 total
= COSTS_N_INSNS (1);
2381 if (outer_code
== SET
)
2385 else if (IN_RANGE (i
, -128, 127))
2387 else if (IN_RANGE (i
, -32768, 32767))
2394 /* Reference here is ADD An,Dn, vs ADD imm,Dn. */
2395 if (IN_RANGE (i
, -128, 127))
2397 else if (IN_RANGE (i
, -32768, 32767))
2399 else if (TARGET_AM33
&& IN_RANGE (i
, -0x01000000, 0x00ffffff))
2411 /* We assume all of these require a 32-bit constant, even though
2412 some symbol and label references can be relaxed. */
2416 switch (XINT (x
, 1))
2422 case UNSPEC_GOTSYM_OFF
:
2423 /* The PIC unspecs also resolve to a 32-bit constant. */
2427 /* Assume any non-listed unspec is some sort of arithmetic. */
2428 goto do_arith_costs
;
2432 /* Notice the size difference of INC and INC4. */
2433 if (!speed
&& outer_code
== SET
&& CONST_INT_P (XEXP (x
, 1)))
2435 i
= INTVAL (XEXP (x
, 1));
2436 if (i
== 1 || i
== 4)
2438 total
= 1 + rtx_cost (XEXP (x
, 0), PLUS
, 0, speed
);
2442 goto do_arith_costs
;
2456 total
= (speed
? COSTS_N_INSNS (1) : 2);
2460 /* Notice the size difference of ASL2 and variants. */
2461 if (!speed
&& CONST_INT_P (XEXP (x
, 1)))
2462 switch (INTVAL (XEXP (x
, 1)))
2477 total
= (speed
? COSTS_N_INSNS (1) : 3);
2481 total
= (speed
? COSTS_N_INSNS (3) : 2);
2488 total
= (speed
? COSTS_N_INSNS (39)
2489 /* Include space to load+retrieve MDR. */
2490 : code
== MOD
|| code
== UMOD
? 6 : 4);
2494 total
= mn10300_address_cost (XEXP (x
, 0), GET_MODE (x
),
2495 MEM_ADDR_SPACE (x
), speed
);
2497 total
= COSTS_N_INSNS (2 + total
);
2501 /* Probably not implemented. Assume external call. */
2502 total
= (speed
? COSTS_N_INSNS (10) : 7);
2514 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2515 may access it using GOTOFF instead of GOT. */
2518 mn10300_encode_section_info (tree decl
, rtx rtl
, int first
)
2522 default_encode_section_info (decl
, rtl
, first
);
2527 symbol
= XEXP (rtl
, 0);
2528 if (GET_CODE (symbol
) != SYMBOL_REF
)
2532 SYMBOL_REF_FLAG (symbol
) = (*targetm
.binds_local_p
) (decl
);
2535 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2536 and readonly data size. So we crank up the case threshold value to
2537 encourage a series of if/else comparisons to implement many small switch
2538 statements. In theory, this value could be increased much more if we
2539 were solely optimizing for space, but we keep it "reasonable" to avoid
2540 serious code efficiency lossage. */
2543 mn10300_case_values_threshold (void)
2548 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2551 mn10300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2553 rtx mem
, disp
, fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2555 /* This is a strict alignment target, which means that we play
2556 some games to make sure that the locations at which we need
2557 to store <chain> and <disp> wind up at aligned addresses.
2560 0xfc 0xdd mov chain,a1
2562 0xf8 0xed 0x00 btst 0,d1
2566 Note that the two extra insns are effectively nops; they
2567 clobber the flags but do not affect the contents of D0 or D1. */
2569 disp
= expand_binop (SImode
, sub_optab
, fnaddr
,
2570 plus_constant (Pmode
, XEXP (m_tramp
, 0), 11),
2571 NULL_RTX
, 1, OPTAB_DIRECT
);
2573 mem
= adjust_address (m_tramp
, SImode
, 0);
2574 emit_move_insn (mem
, gen_int_mode (0xddfc0028, SImode
));
2575 mem
= adjust_address (m_tramp
, SImode
, 4);
2576 emit_move_insn (mem
, chain_value
);
2577 mem
= adjust_address (m_tramp
, SImode
, 8);
2578 emit_move_insn (mem
, gen_int_mode (0xdc00edf8, SImode
));
2579 mem
= adjust_address (m_tramp
, SImode
, 12);
2580 emit_move_insn (mem
, disp
);
2583 /* Output the assembler code for a C++ thunk function.
2584 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2585 is the decl for the target function. DELTA is an immediate constant
2586 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2587 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2588 additionally added to THIS. Finally jump to the entry point of
2592 mn10300_asm_output_mi_thunk (FILE * file
,
2593 tree thunk_fndecl ATTRIBUTE_UNUSED
,
2594 HOST_WIDE_INT delta
,
2595 HOST_WIDE_INT vcall_offset
,
2600 /* Get the register holding the THIS parameter. Handle the case
2601 where there is a hidden first argument for a returned structure. */
2602 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
2603 _this
= reg_names
[FIRST_ARGUMENT_REGNUM
+ 1];
2605 _this
= reg_names
[FIRST_ARGUMENT_REGNUM
];
2607 fprintf (file
, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START
);
2610 fprintf (file
, "\tadd %d, %s\n", (int) delta
, _this
);
2614 const char * scratch
= reg_names
[FIRST_ADDRESS_REGNUM
+ 1];
2616 fprintf (file
, "\tmov %s, %s\n", _this
, scratch
);
2617 fprintf (file
, "\tmov (%s), %s\n", scratch
, scratch
);
2618 fprintf (file
, "\tadd %d, %s\n", (int) vcall_offset
, scratch
);
2619 fprintf (file
, "\tmov (%s), %s\n", scratch
, scratch
);
2620 fprintf (file
, "\tadd %s, %s\n", scratch
, _this
);
2623 fputs ("\tjmp ", file
);
2624 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
2628 /* Return true if mn10300_output_mi_thunk would be able to output the
2629 assembler code for the thunk function specified by the arguments
2630 it is passed, and false otherwise. */
2633 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
2634 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
2635 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2636 const_tree function ATTRIBUTE_UNUSED
)
2642 mn10300_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2644 if (REGNO_REG_CLASS (regno
) == FP_REGS
2645 || REGNO_REG_CLASS (regno
) == FP_ACC_REGS
)
2646 /* Do not store integer values in FP registers. */
2647 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ((regno
& 1) == 0);
2649 if (! TARGET_AM33
&& REGNO_REG_CLASS (regno
) == EXTENDED_REGS
)
2652 if (((regno
) & 1) == 0 || GET_MODE_SIZE (mode
) == 4)
2655 if (REGNO_REG_CLASS (regno
) == DATA_REGS
2656 || (TARGET_AM33
&& REGNO_REG_CLASS (regno
) == ADDRESS_REGS
)
2657 || REGNO_REG_CLASS (regno
) == EXTENDED_REGS
)
2658 return GET_MODE_SIZE (mode
) <= 4;
2664 mn10300_modes_tieable (machine_mode mode1
, machine_mode mode2
)
2666 if (GET_MODE_CLASS (mode1
) == MODE_FLOAT
2667 && GET_MODE_CLASS (mode2
) != MODE_FLOAT
)
2670 if (GET_MODE_CLASS (mode2
) == MODE_FLOAT
2671 && GET_MODE_CLASS (mode1
) != MODE_FLOAT
)
2676 || (GET_MODE_SIZE (mode1
) <= 4 && GET_MODE_SIZE (mode2
) <= 4))
2683 cc_flags_for_mode (machine_mode mode
)
2688 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_C
| CC_FLAG_V
;
2690 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_C
;
2692 return CC_FLAG_Z
| CC_FLAG_N
;
2701 cc_flags_for_code (enum rtx_code code
)
2714 case GT
: /* ~(Z|(N^V)) */
2715 case LE
: /* Z|(N^V) */
2716 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_V
;
2722 case GTU
: /* ~(C | Z) */
2723 case LEU
: /* C | Z */
2724 return CC_FLAG_Z
| CC_FLAG_C
;
2742 mn10300_select_cc_mode (enum rtx_code code
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2746 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2747 return CC_FLOATmode
;
2749 req
= cc_flags_for_code (code
);
2751 if (req
& CC_FLAG_V
)
2753 if (req
& CC_FLAG_C
)
2759 set_is_load_p (rtx set
)
2761 return MEM_P (SET_SRC (set
));
2765 set_is_store_p (rtx set
)
2767 return MEM_P (SET_DEST (set
));
2770 /* Update scheduling costs for situations that cannot be
2771 described using the attributes and DFA machinery.
2772 DEP is the insn being scheduled.
2773 INSN is the previous insn.
2774 COST is the current cycle cost for DEP. */
2777 mn10300_adjust_sched_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep
, int cost
)
2786 /* We are only interested in pairs of SET. */
2787 insn_set
= single_set (insn
);
2791 dep_set
= single_set (dep
);
2795 /* For the AM34 a load instruction that follows a
2796 store instruction incurs an extra cycle of delay. */
2797 if (mn10300_tune_cpu
== PROCESSOR_AM34
2798 && set_is_load_p (dep_set
)
2799 && set_is_store_p (insn_set
))
2802 /* For the AM34 a non-store, non-branch FPU insn that follows
2803 another FPU insn incurs a one cycle throughput increase. */
2804 else if (mn10300_tune_cpu
== PROCESSOR_AM34
2805 && ! set_is_store_p (insn_set
)
2807 && GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set
))) == MODE_FLOAT
2808 && GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set
))) == MODE_FLOAT
)
2811 /* Resolve the conflict described in section 1-7-4 of
2812 Chapter 3 of the MN103E Series Instruction Manual
2815 "When the preceding instruction is a CPU load or
2816 store instruction, a following FPU instruction
2817 cannot be executed until the CPU completes the
2818 latency period even though there are no register
2819 or flag dependencies between them." */
2821 /* Only the AM33-2 (and later) CPUs have FPU instructions. */
2822 if (! TARGET_AM33_2
)
2825 /* If a data dependence already exists then the cost is correct. */
2826 if (REG_NOTE_KIND (link
) == 0)
2829 /* Check that the instruction about to scheduled is an FPU instruction. */
2830 if (GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set
))) != MODE_FLOAT
)
2833 /* Now check to see if the previous instruction is a load or store. */
2834 if (! set_is_load_p (insn_set
) && ! set_is_store_p (insn_set
))
2837 /* XXX: Verify: The text of 1-7-4 implies that the restriction
2838 only applies when an INTEGER load/store precedes an FPU
2839 instruction, but is this true ? For now we assume that it is. */
2840 if (GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set
))) != MODE_INT
)
2843 /* Extract the latency value from the timings attribute. */
2844 timings
= get_attr_timings (insn
);
2845 return timings
< 100 ? (timings
% 10) : (timings
% 100);
2849 mn10300_conditional_register_usage (void)
2855 for (i
= FIRST_EXTENDED_REGNUM
;
2856 i
<= LAST_EXTENDED_REGNUM
; i
++)
2857 fixed_regs
[i
] = call_used_regs
[i
] = 1;
2861 for (i
= FIRST_FP_REGNUM
;
2862 i
<= LAST_FP_REGNUM
; i
++)
2863 fixed_regs
[i
] = call_used_regs
[i
] = 1;
2866 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] =
2867 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2870 /* Worker function for TARGET_MD_ASM_CLOBBERS.
2871 We do this in the mn10300 backend to maintain source compatibility
2872 with the old cc0-based compiler. */
2875 mn10300_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED
,
2876 tree inputs ATTRIBUTE_UNUSED
,
2879 clobbers
= tree_cons (NULL_TREE
, build_string (5, "EPSW"),
2884 /* A helper function for splitting cbranch patterns after reload. */
2887 mn10300_split_cbranch (machine_mode cmp_mode
, rtx cmp_op
, rtx label_ref
)
2891 flags
= gen_rtx_REG (cmp_mode
, CC_REG
);
2892 x
= gen_rtx_COMPARE (cmp_mode
, XEXP (cmp_op
, 0), XEXP (cmp_op
, 1));
2893 x
= gen_rtx_SET (VOIDmode
, flags
, x
);
2896 x
= gen_rtx_fmt_ee (GET_CODE (cmp_op
), VOIDmode
, flags
, const0_rtx
);
2897 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
, label_ref
, pc_rtx
);
2898 x
= gen_rtx_SET (VOIDmode
, pc_rtx
, x
);
2902 /* A helper function for matching parallels that set the flags. */
2905 mn10300_match_ccmode (rtx insn
, machine_mode cc_mode
)
2908 machine_mode flags_mode
;
2910 gcc_checking_assert (XVECLEN (PATTERN (insn
), 0) == 2);
2912 op1
= XVECEXP (PATTERN (insn
), 0, 1);
2913 gcc_checking_assert (GET_CODE (SET_SRC (op1
)) == COMPARE
);
2915 flags
= SET_DEST (op1
);
2916 flags_mode
= GET_MODE (flags
);
2918 if (GET_MODE (SET_SRC (op1
)) != flags_mode
)
2920 if (GET_MODE_CLASS (flags_mode
) != MODE_CC
)
2923 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
2924 if (cc_flags_for_mode (flags_mode
) & ~cc_flags_for_mode (cc_mode
))
2930 /* This function is used to help split:
2932 (set (reg) (and (reg) (int)))
2936 (set (reg) (shift (reg) (int))
2937 (set (reg) (shift (reg) (int))
2939 where the shitfs will be shorter than the "and" insn.
2941 It returns the number of bits that should be shifted. A positive
2942 values means that the low bits are to be cleared (and hence the
2943 shifts should be right followed by left) whereas a negative value
2944 means that the high bits are to be cleared (left followed by right).
2945 Zero is returned when it would not be economical to split the AND. */
2948 mn10300_split_and_operand_count (rtx op
)
2950 HOST_WIDE_INT val
= INTVAL (op
);
2955 /* High bit is set, look for bits clear at the bottom. */
2956 count
= exact_log2 (-val
);
2959 /* This is only size win if we can use the asl2 insn. Otherwise we
2960 would be replacing 1 6-byte insn with 2 3-byte insns. */
2961 if (count
> (optimize_insn_for_speed_p () ? 2 : 4))
2967 /* High bit is clear, look for bits set at the bottom. */
2968 count
= exact_log2 (val
+ 1);
2970 /* Again, this is only a size win with asl2. */
2971 if (count
> (optimize_insn_for_speed_p () ? 2 : 4))
2980 enum attr_liw_op op
;
2985 /* Decide if the given insn is a candidate for LIW bundling. If it is then
2986 extract the operands and LIW attributes from the insn and use them to fill
2987 in the liw_data structure. Return true upon success or false if the insn
2988 cannot be bundled. */
2991 extract_bundle (rtx_insn
*insn
, struct liw_data
* pdata
)
2993 bool allow_consts
= true;
2996 gcc_assert (pdata
!= NULL
);
3000 /* Make sure that we are dealing with a simple SET insn. */
3001 p
= single_set (insn
);
3005 /* Make sure that it could go into one of the LIW pipelines. */
3006 pdata
->slot
= get_attr_liw (insn
);
3007 if (pdata
->slot
== LIW_BOTH
)
3010 pdata
->op
= get_attr_liw_op (insn
);
3015 pdata
->dest
= SET_DEST (p
);
3016 pdata
->src
= SET_SRC (p
);
3019 pdata
->dest
= XEXP (SET_SRC (p
), 0);
3020 pdata
->src
= XEXP (SET_SRC (p
), 1);
3027 /* The AND, OR and XOR long instruction words only accept register arguments. */
3028 allow_consts
= false;
3031 pdata
->dest
= SET_DEST (p
);
3032 pdata
->src
= XEXP (SET_SRC (p
), 1);
3036 if (! REG_P (pdata
->dest
))
3039 if (REG_P (pdata
->src
))
3042 return allow_consts
&& satisfies_constraint_O (pdata
->src
);
3045 /* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated
3046 the instructions with the assumption that LIW1 would be executed before LIW2
3047 so we must check for overlaps between their sources and destinations. */
3050 check_liw_constraints (struct liw_data
* pliw1
, struct liw_data
* pliw2
)
3052 /* Check for slot conflicts. */
3053 if (pliw2
->slot
== pliw1
->slot
&& pliw1
->slot
!= LIW_EITHER
)
3056 /* If either operation is a compare, then "dest" is really an input; the real
3057 destination is CC_REG. So these instructions need different checks. */
3059 /* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will
3060 check its values prior to any changes made by OP. */
3061 if (pliw1
->op
== LIW_OP_CMP
)
3063 /* Two sequential comparisons means dead code, which ought to
3064 have been eliminated given that bundling only happens with
3065 optimization. We cannot bundle them in any case. */
3066 gcc_assert (pliw1
->op
!= pliw2
->op
);
3070 /* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared
3071 is the destination of OP, as the CMP will look at the old value, not the new
3073 if (pliw2
->op
== LIW_OP_CMP
)
3075 if (REGNO (pliw2
->dest
) == REGNO (pliw1
->dest
))
3078 if (REG_P (pliw2
->src
))
3079 return REGNO (pliw2
->src
) != REGNO (pliw1
->dest
);
3084 /* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the
3085 same destination register. */
3086 if (REGNO (pliw2
->dest
) == REGNO (pliw1
->dest
))
3089 /* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination
3090 of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when
3091 we can replace the source in OP2 with the source of OP1. */
3092 if (REG_P (pliw2
->src
) && REGNO (pliw2
->src
) == REGNO (pliw1
->dest
))
3094 if (pliw1
->op
== LIW_OP_MOV
&& REG_P (pliw1
->src
))
3096 if (! REG_P (pliw1
->src
)
3097 && (pliw2
->op
== LIW_OP_AND
3098 || pliw2
->op
== LIW_OP_OR
3099 || pliw2
->op
== LIW_OP_XOR
))
3102 pliw2
->src
= pliw1
->src
;
3108 /* Everything else is OK. */
3112 /* Combine pairs of insns into LIW bundles. */
3115 mn10300_bundle_liw (void)
3119 for (r
= get_insns (); r
!= NULL
; r
= next_nonnote_nondebug_insn (r
))
3121 rtx_insn
*insn1
, *insn2
;
3122 struct liw_data liw1
, liw2
;
3125 if (! extract_bundle (insn1
, & liw1
))
3128 insn2
= next_nonnote_nondebug_insn (insn1
);
3129 if (! extract_bundle (insn2
, & liw2
))
3132 /* Check for source/destination overlap. */
3133 if (! check_liw_constraints (& liw1
, & liw2
))
3136 if (liw1
.slot
== LIW_OP2
|| liw2
.slot
== LIW_OP1
)
3138 struct liw_data temp
;
3145 delete_insn (insn2
);
3148 if (liw1
.op
== LIW_OP_CMP
)
3149 insn2_pat
= gen_cmp_liw (liw2
.dest
, liw2
.src
, liw1
.dest
, liw1
.src
,
3151 else if (liw2
.op
== LIW_OP_CMP
)
3152 insn2_pat
= gen_liw_cmp (liw1
.dest
, liw1
.src
, liw2
.dest
, liw2
.src
,
3155 insn2_pat
= gen_liw (liw1
.dest
, liw2
.dest
, liw1
.src
, liw2
.src
,
3156 GEN_INT (liw1
.op
), GEN_INT (liw2
.op
));
3158 insn2
= emit_insn_after (insn2_pat
, insn1
);
3159 delete_insn (insn1
);
3164 #define DUMP(reason, insn) \
3169 fprintf (dump_file, reason "\n"); \
3170 if (insn != NULL_RTX) \
3171 print_rtl_single (dump_file, insn); \
3172 fprintf(dump_file, "\n"); \
3177 /* Replace the BRANCH insn with a Lcc insn that goes to LABEL.
3178 Insert a SETLB insn just before LABEL. */
3181 mn10300_insert_setlb_lcc (rtx label
, rtx branch
)
3183 rtx lcc
, comparison
, cmp_reg
;
3185 if (LABEL_NUSES (label
) > 1)
3189 /* This label is used both as an entry point to the loop
3190 and as a loop-back point for the loop. We need to separate
3191 these two functions so that the SETLB happens upon entry,
3192 but the loop-back does not go to the SETLB instruction. */
3193 DUMP ("Inserting SETLB insn after:", label
);
3194 insn
= emit_insn_after (gen_setlb (), label
);
3195 label
= gen_label_rtx ();
3196 emit_label_after (label
, insn
);
3197 DUMP ("Created new loop-back label:", label
);
3201 DUMP ("Inserting SETLB insn before:", label
);
3202 emit_insn_before (gen_setlb (), label
);
3205 comparison
= XEXP (SET_SRC (PATTERN (branch
)), 0);
3206 cmp_reg
= XEXP (comparison
, 0);
3207 gcc_assert (REG_P (cmp_reg
));
3209 /* If the comparison has not already been split out of the branch
3211 gcc_assert (REGNO (cmp_reg
) == CC_REG
);
3213 if (GET_MODE (cmp_reg
) == CC_FLOATmode
)
3214 lcc
= gen_FLcc (comparison
, label
);
3216 lcc
= gen_Lcc (comparison
, label
);
3218 rtx_insn
*jump
= emit_jump_insn_before (lcc
, branch
);
3219 mark_jump_label (XVECEXP (PATTERN (lcc
), 0, 0), jump
, 0);
3220 JUMP_LABEL (jump
) = label
;
3221 DUMP ("Replacing branch insn...", branch
);
3222 DUMP ("... with Lcc insn:", jump
);
3223 delete_insn (branch
);
3227 mn10300_block_contains_call (basic_block block
)
3231 FOR_BB_INSNS (block
, insn
)
3239 mn10300_loop_contains_call_insn (loop_p loop
)
3242 bool result
= false;
3245 bbs
= get_loop_body (loop
);
3247 for (i
= 0; i
< loop
->num_nodes
; i
++)
3248 if (mn10300_block_contains_call (bbs
[i
]))
3259 mn10300_scan_for_setlb_lcc (void)
3263 DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX
);
3266 compute_bb_for_insn ();
3268 /* Find the loops. */
3269 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
3271 /* FIXME: For now we only investigate innermost loops. In practice however
3272 if an inner loop is not suitable for use with the SETLB/Lcc insns, it may
3273 be the case that its parent loop is suitable. Thus we should check all
3274 loops, but work from the innermost outwards. */
3275 FOR_EACH_LOOP (loop
, LI_ONLY_INNERMOST
)
3277 const char * reason
= NULL
;
3279 /* Check to see if we can modify this loop. If we cannot
3280 then set 'reason' to describe why it could not be done. */
3281 if (loop
->latch
== NULL
)
3282 reason
= "it contains multiple latches";
3283 else if (loop
->header
!= loop
->latch
)
3284 /* FIXME: We could handle loops that span multiple blocks,
3285 but this requires a lot more work tracking down the branches
3286 that need altering, so for now keep things simple. */
3287 reason
= "the loop spans multiple blocks";
3288 else if (mn10300_loop_contains_call_insn (loop
))
3289 reason
= "it contains CALL insns";
3292 rtx_insn
*branch
= BB_END (loop
->latch
);
3294 gcc_assert (JUMP_P (branch
));
3295 if (single_set (branch
) == NULL_RTX
|| ! any_condjump_p (branch
))
3296 /* We cannot optimize tablejumps and the like. */
3297 /* FIXME: We could handle unconditional jumps. */
3298 reason
= "it is not a simple loop";
3304 flow_loop_dump (loop
, dump_file
, NULL
, 0);
3306 label
= BB_HEAD (loop
->header
);
3307 gcc_assert (LABEL_P (label
));
3309 mn10300_insert_setlb_lcc (label
, branch
);
3313 if (dump_file
&& reason
!= NULL
)
3314 fprintf (dump_file
, "Loop starting with insn %d is not suitable because %s\n",
3315 INSN_UID (BB_HEAD (loop
->header
)),
3319 loop_optimizer_finalize ();
3321 df_finish_pass (false);
3323 DUMP ("SETLB scan complete", NULL_RTX
);
3327 mn10300_reorg (void)
3329 /* These are optimizations, so only run them if optimizing. */
3330 if (TARGET_AM33
&& (optimize
> 0 || optimize_size
))
3332 if (TARGET_ALLOW_SETLB
)
3333 mn10300_scan_for_setlb_lcc ();
3335 if (TARGET_ALLOW_LIW
)
3336 mn10300_bundle_liw ();
3340 /* Initialize the GCC target structure. */
3342 #undef TARGET_MACHINE_DEPENDENT_REORG
3343 #define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg
3345 #undef TARGET_ASM_ALIGNED_HI_OP
3346 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
3348 #undef TARGET_LEGITIMIZE_ADDRESS
3349 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
3351 #undef TARGET_ADDRESS_COST
3352 #define TARGET_ADDRESS_COST mn10300_address_cost
3353 #undef TARGET_REGISTER_MOVE_COST
3354 #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost
3355 #undef TARGET_MEMORY_MOVE_COST
3356 #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost
3357 #undef TARGET_RTX_COSTS
3358 #define TARGET_RTX_COSTS mn10300_rtx_costs
3360 #undef TARGET_ASM_FILE_START
3361 #define TARGET_ASM_FILE_START mn10300_file_start
3362 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
3363 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
3365 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
3366 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra
3368 #undef TARGET_OPTION_OVERRIDE
3369 #define TARGET_OPTION_OVERRIDE mn10300_option_override
3371 #undef TARGET_ENCODE_SECTION_INFO
3372 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
3374 #undef TARGET_PROMOTE_PROTOTYPES
3375 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
3376 #undef TARGET_RETURN_IN_MEMORY
3377 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
3378 #undef TARGET_PASS_BY_REFERENCE
3379 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
3380 #undef TARGET_CALLEE_COPIES
3381 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
3382 #undef TARGET_ARG_PARTIAL_BYTES
3383 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
3384 #undef TARGET_FUNCTION_ARG
3385 #define TARGET_FUNCTION_ARG mn10300_function_arg
3386 #undef TARGET_FUNCTION_ARG_ADVANCE
3387 #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance
3389 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
3390 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
3391 #undef TARGET_EXPAND_BUILTIN_VA_START
3392 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
3394 #undef TARGET_CASE_VALUES_THRESHOLD
3395 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
3397 #undef TARGET_LEGITIMATE_ADDRESS_P
3398 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
3399 #undef TARGET_DELEGITIMIZE_ADDRESS
3400 #define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address
3401 #undef TARGET_LEGITIMATE_CONSTANT_P
3402 #define TARGET_LEGITIMATE_CONSTANT_P mn10300_legitimate_constant_p
3404 #undef TARGET_PREFERRED_RELOAD_CLASS
3405 #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class
3406 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
3407 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS \
3408 mn10300_preferred_output_reload_class
3409 #undef TARGET_SECONDARY_RELOAD
3410 #define TARGET_SECONDARY_RELOAD mn10300_secondary_reload
3412 #undef TARGET_TRAMPOLINE_INIT
3413 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
3415 #undef TARGET_FUNCTION_VALUE
3416 #define TARGET_FUNCTION_VALUE mn10300_function_value
3417 #undef TARGET_LIBCALL_VALUE
3418 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
3420 #undef TARGET_ASM_OUTPUT_MI_THUNK
3421 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
3422 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3423 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
3425 #undef TARGET_SCHED_ADJUST_COST
3426 #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost
3428 #undef TARGET_CONDITIONAL_REGISTER_USAGE
3429 #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage
3431 #undef TARGET_MD_ASM_CLOBBERS
3432 #define TARGET_MD_ASM_CLOBBERS mn10300_md_asm_clobbers
3434 #undef TARGET_FLAGS_REGNUM
3435 #define TARGET_FLAGS_REGNUM CC_REG
3437 struct gcc_target targetm
= TARGET_INITIALIZER
;