gcc/config/mn10300/mn10300.md

   1 ;; GCC machine description for Matsushita MN10300
   2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
   3 ;; 2005, 2006, 2007, 2008, 2009, 2010
   4 ;; Free Software Foundation, Inc.
   5 ;; Contributed by Jeff Law (law@cygnus.com).
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify
  10 ;; it under the terms of the GNU General Public License as published by
  11 ;; the Free Software Foundation; either version 3, or (at your option)
  12 ;; any later version.
  13
  14 ;; GCC is distributed in the hope that it will be useful,
  15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ;; GNU General Public License for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;; The original PO technology requires these to be ordered by speed,
  24 ;; so that assigner will pick the fastest.
  25
  26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
  27
  28 (define_constants [
  29   (PIC_REG   6)
  30   (SP_REG    9)
  31   (MDR_REG  50)
  32   (CC_REG   51)
  33
  34   (UNSPEC_PIC           1)
  35   (UNSPEC_GOT           2)
  36   (UNSPEC_GOTOFF        3)
  37   (UNSPEC_PLT           4)
  38   (UNSPEC_GOTSYM_OFF    5)
  39
  40   (UNSPEC_EXT           6)
  41   (UNSPEC_BSCH          7)
  42 ])
  43
  44 (include "predicates.md")
  45 (include "constraints.md")
  46
  47 ;; Processor type.  This attribute must exactly match the processor_type
  48 ;; enumeration in mn10300.h.
  49 (define_attr "cpu" "mn10300,am33,am33_2,am34"
  50   (const (symbol_ref "(enum attr_cpu) mn10300_tune_cpu")))
  51
  52 ;; Used to control the "enabled" attribute on a per-instruction basis.
  53 (define_attr "isa" "base,am33,am33_2,am34"
  54   (const_string "base"))
  55
  56 (define_attr "enabled" ""
  57   (cond [(eq_attr "isa" "base")
  58          (const_int 1)
  59
  60          (and (eq_attr "isa" "am33")
  61               (ne (symbol_ref "TARGET_AM33") (const_int 0)))
  62          (const_int 1)
  63
  64          (and (eq_attr "isa" "am33_2")
  65               (ne (symbol_ref "TARGET_AM33_2") (const_int 0)))
  66          (const_int 1)
  67
  68          (and (eq_attr "isa" "am34")
  69               (ne (symbol_ref "TARGET_AM34") (const_int 0)))
  70          (const_int 1)
  71         ]
  72         (const_int 0))
  73 )
  74
  75 (define_mode_iterator INT [QI HI SI])
  76
  77 \f
  78 ;; ----------------------------------------------------------------------
  79 ;; Pipeline description.
  80 ;; ----------------------------------------------------------------------
  81
  82 ;; The AM33 only has a single pipeline.  It has five stages (fetch,
  83 ;; decode, execute, memory access, writeback) each of which normally
  84 ;; takes a single CPU clock cycle.
  85
  86 ;; The timings attribute consists of two numbers, the first is the
  87 ;; throughput, which is the number of cycles the instruction takes
  88 ;; to execute and generate a result.  The second is the latency
  89 ;; which is the effective number of cycles the instruction takes to
  90 ;; execute if its result is used by the following instruction.  The
  91 ;; latency is always greater than or equal to the throughput.
  92 ;; These values were taken from the Appendix of the "MN103E Series
  93 ;; Instruction Manual" and the timings for the AM34.
  94
  95 ;; Note - it would be nice to use strings rather than integers for
  96 ;; the possible values of this attribute, so that we can have the
  97 ;; gcc build mechanism check for values that are not supported by
  98 ;; the reservations below.  But this will not work because the code
  99 ;; in mn10300_adjust_sched_cost() needs integers not strings.
 100
 101 (define_attr "timings" "" (const_int 11))
 102
 103 (define_automaton "pipelining")
 104 (define_cpu_unit "throughput" "pipelining")
 105
 106 (define_insn_reservation "throughput__1_latency__1"  1
 107   (eq_attr "timings" "11") "throughput")
 108 (define_insn_reservation "throughput__1_latency__2"  2
 109   (eq_attr "timings" "12") "throughput,nothing")
 110 (define_insn_reservation "throughput__1_latency__3"  3
 111   (eq_attr "timings" "13") "throughput,nothing*2")
 112 (define_insn_reservation "throughput__1_latency__4"  4
 113   (eq_attr "timings" "14") "throughput,nothing*3")
 114 (define_insn_reservation "throughput__2_latency__2"  2
 115   (eq_attr "timings" "22") "throughput*2")
 116 (define_insn_reservation "throughput__2_latency__3"  3
 117   (eq_attr "timings" "23") "throughput*2,nothing")
 118 (define_insn_reservation "throughput__2_latency__4"  4
 119   (eq_attr "timings" "24") "throughput*2,nothing*2")
 120 (define_insn_reservation "throughput__2_latency__5"  5
 121   (eq_attr "timings" "25") "throughput*2,nothing*3")
 122 (define_insn_reservation "throughput__3_latency__3"  3
 123   (eq_attr "timings" "33") "throughput*3")
 124 (define_insn_reservation "throughput__3_latency__7"  7
 125   (eq_attr "timings" "37") "throughput*3,nothing*4")
 126 (define_insn_reservation "throughput__4_latency__4"  4
 127   (eq_attr "timings" "44") "throughput*4")
 128 (define_insn_reservation "throughput__4_latency__7"  7
 129   (eq_attr "timings" "47") "throughput*4,nothing*3")
 130 (define_insn_reservation "throughput__4_latency__8"  8
 131   (eq_attr "timings" "48") "throughput*4,nothing*4")
 132 (define_insn_reservation "throughput__5_latency__5"  5
 133   (eq_attr "timings" "55") "throughput*5")
 134 (define_insn_reservation "throughput__6_latency__6"  6
 135   (eq_attr "timings" "66") "throughput*6")
 136 (define_insn_reservation "throughput__7_latency__7"  7
 137   (eq_attr "timings" "77") "throughput*7")
 138 (define_insn_reservation "throughput__7_latency__8"  8
 139   (eq_attr "timings" "78") "throughput*7,nothing")
 140 (define_insn_reservation "throughput__8_latency__8"  8
 141   (eq_attr "timings" "88") "throughput*8")
 142 (define_insn_reservation "throughput__9_latency__9"  9
 143   (eq_attr "timings" "99") "throughput*9")
 144 (define_insn_reservation "throughput__8_latency_14" 14
 145   (eq_attr "timings" "814") "throughput*8,nothing*6")
 146 (define_insn_reservation "throughput__9_latency_10" 10
 147   (eq_attr "timings" "910") "throughput*9,nothing")
 148 (define_insn_reservation "throughput_10_latency_10" 10
 149   (eq_attr "timings" "1010") "throughput*10")
 150 (define_insn_reservation "throughput_12_latency_16" 16
 151   (eq_attr "timings" "1216") "throughput*12,nothing*4")
 152 (define_insn_reservation "throughput_13_latency_13" 13
 153   (eq_attr "timings" "1313") "throughput*13")
 154 (define_insn_reservation "throughput_14_latency_14" 14
 155   (eq_attr "timings" "1414") "throughput*14")
 156 (define_insn_reservation "throughput_13_latency_17" 17
 157   (eq_attr "timings" "1317") "throughput*13,nothing*4")
 158 (define_insn_reservation "throughput_23_latency_27" 27
 159   (eq_attr "timings" "2327") "throughput*23,nothing*4")
 160 (define_insn_reservation "throughput_25_latency_31" 31
 161   (eq_attr "timings" "2531") "throughput*25,nothing*6")
 162 (define_insn_reservation "throughput_38_latency_39" 39
 163   (eq_attr "timings" "3839") "throughput*38,nothing")
 164 (define_insn_reservation "throughput_39_latency_40" 40
 165   (eq_attr "timings" "3940") "throughput*39,nothing")
 166 (define_insn_reservation "throughput_40_latency_40" 40
 167   (eq_attr "timings" "4040") "throughput*40")
 168 (define_insn_reservation "throughput_41_latency_42" 42
 169   (eq_attr "timings" "4142") "throughput*41,nothing")
 170 (define_insn_reservation "throughput_42_latency_43" 44
 171   (eq_attr "timings" "4243") "throughput*42,nothing")
 172 (define_insn_reservation "throughput_43_latency_44" 44
 173   (eq_attr "timings" "4344") "throughput*43,nothing")
 174 (define_insn_reservation "throughput_45_latency_46" 46
 175   (eq_attr "timings" "4546") "throughput*45,nothing")
 176 (define_insn_reservation "throughput_47_latency_53" 53
 177   (eq_attr "timings" "4753") "throughput*47,nothing*6")
 178
 179 ;; Note - the conflict between memory load/store instructions
 180 ;; and floating point instructions described in section 1-7-4
 181 ;; of Chapter 3 of the MN103E Series Instruction Manual is
 182 ;; handled by the mn10300_adjust_sched_cost function.
 183 \f
 184 ;; ----------------------------------------------------------------------
 185 ;; MOVE INSTRUCTIONS
 186 ;; ----------------------------------------------------------------------
 187
 188 ;; movqi
 189
 190 (define_expand "movqi"
 191   [(set (match_operand:QI 0 "nonimmediate_operand")
 192         (match_operand:QI 1 "general_operand"))]
 193   ""
 194 {
 195   /* One of the ops has to be in a register.  */
 196   if (!register_operand (operand0, QImode)
 197       && !register_operand (operand1, QImode))
 198     operands[1] = force_reg (QImode, operand1);
 199 })
 200
 201 (define_insn "*movqi_internal"
 202   [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m")
 203         (match_operand:QI 1 "general_operand"      "  0,D*r,  i,m,D"))]
 204   "(register_operand (operands[0], QImode)
 205     || register_operand (operands[1], QImode))"
 206 {
 207   switch (which_alternative)
 208     {
 209     case 0:
 210       return "";
 211     case 1:
 212     case 2:
 213       return "mov %1,%0";
 214     case 3:
 215     case 4:
 216       return "movbu %1,%0";
 217     default:
 218       gcc_unreachable ();
 219     }
 220 }
 221   [(set_attr_alternative "timings"
 222          [(const_int 11)
 223           (const_int 11)
 224           (const_int 11)
 225           (if_then_else (eq_attr "cpu" "am34")
 226                         (const_int 13) (const_int 24))
 227           (if_then_else (eq_attr "cpu" "am34")
 228                         (const_int 11) (const_int 22))
 229          ])]
 230 )
 231
 232 ;; movhi
 233
 234 (define_expand "movhi"
 235   [(set (match_operand:HI 0 "nonimmediate_operand")
 236         (match_operand:HI 1 "general_operand"))]
 237   ""
 238 {
 239   /* One of the ops has to be in a register.  */
 240   if (!register_operand (operand1, HImode)
 241       && !register_operand (operand0, HImode))
 242     operands[1] = force_reg (HImode, operand1);
 243 })
 244
 245 (define_insn "*movhi_internal"
 246   [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m")
 247         (match_operand:HI 1 "general_operand"      "  0,  i,D*r,m,D"))]
 248   "(register_operand (operands[0], HImode)
 249     || register_operand (operands[1], HImode))"
 250 {
 251   switch (which_alternative)
 252     {
 253     case 0:
 254       return "";
 255     case 1:
 256       /* Note that "MOV imm8,An" is already zero-extending, and is 2 bytes.
 257          We have "MOV imm16,Dn" at 3 bytes.  The only win for the 4 byte
 258          movu is for an 8-bit unsigned move into Rn.  */
 259       if (TARGET_AM33
 260           && CONST_INT_P (operands[1])
 261           && IN_RANGE (INTVAL (operands[1]), 0x80, 0xff)
 262           && REGNO_EXTENDED_P (REGNO (operands[0]), 1))
 263         return "movu %1,%0";
 264       /* FALLTHRU */
 265     case 2:
 266       return "mov %1,%0";
 267     case 3:
 268     case 4:
 269       return "movhu %1,%0";
 270     default:
 271       gcc_unreachable ();
 272     }
 273 }
 274   [(set_attr_alternative "timings"
 275          [(const_int 11)
 276           (const_int 11)
 277           (if_then_else (eq_attr "cpu" "am34")
 278                         (const_int 11) (const_int 22))
 279           (if_then_else (eq_attr "cpu" "am34")
 280                         (const_int 13) (const_int 24))
 281           (if_then_else (eq_attr "cpu" "am34")
 282                         (const_int 11) (const_int 22))
 283          ])]
 284 )
 285
 286 ;; movsi and helpers
 287
 288 ;; We use this to handle addition of two values when one operand is the
 289 ;; stack pointer and the other is a memory reference of some kind.  Reload
 290 ;; does not handle them correctly without this expander.
 291 (define_expand "reload_plus_sp_const"
 292   [(set (match_operand:SI     0 "register_operand" "=r")
 293         (match_operand:SI     1 "impossible_plus_operand" ""))
 294    (clobber (match_operand:SI 2 "register_operand" "=&A"))]
 295   ""
 296 {
 297   rtx dest, scratch, other;
 298
 299   dest = operands[0];
 300   scratch = operands[2];
 301
 302   other = XEXP (operands[1], 1);
 303   if (other == stack_pointer_rtx)
 304     other = XEXP (operands[1], 0);
 305
 306   if (true_regnum (other) == true_regnum (dest))
 307     {
 308       gcc_assert (true_regnum (scratch) != true_regnum (dest));
 309       emit_move_insn (scratch, stack_pointer_rtx);
 310       emit_insn (gen_addsi3 (dest, dest, scratch));
 311     }
 312   else if (TARGET_AM33 || REGNO_REG_CLASS (true_regnum (dest)) == ADDRESS_REGS)
 313     {
 314       emit_move_insn (dest, stack_pointer_rtx);
 315       if (other == stack_pointer_rtx)
 316         emit_insn (gen_addsi3 (dest, dest, dest));
 317       else if (other != const0_rtx)
 318         emit_insn (gen_addsi3 (dest, dest, other));
 319     }
 320   else
 321     {
 322       emit_move_insn (scratch, stack_pointer_rtx);
 323       if (other == stack_pointer_rtx)
 324         {
 325           emit_move_insn (dest, scratch);
 326           emit_insn (gen_addsi3 (dest, dest, dest));
 327         }
 328       else if (other != const0_rtx)
 329         {
 330           emit_move_insn (dest, other);
 331           emit_insn (gen_addsi3 (dest, dest, scratch));
 332         }
 333       else
 334         emit_move_insn (dest, scratch);
 335     }
 336   DONE;
 337 })
 338
 339 (define_expand "movsi"
 340   [(set (match_operand:SI 0 "nonimmediate_operand")
 341         (match_operand:SI 1 "general_operand"))]
 342   ""
 343 {
 344   /* One of the ops has to be in a register.  */
 345   if (!register_operand (operand1, SImode)
 346       && !register_operand (operand0, SImode))
 347     operands[1] = force_reg (SImode, operand1);
 348   if (flag_pic)
 349     {
 350       rtx temp;
 351       if (SYMBOLIC_CONST_P (operands[1]))
 352         {
 353           if (MEM_P (operands[0]))
 354             operands[1] = force_reg (Pmode, operands[1]);
 355           else
 356             {
 357               temp = (!can_create_pseudo_p ()
 358                       ? operands[0]
 359                       : gen_reg_rtx (Pmode));
 360               operands[1] = mn10300_legitimize_pic_address (operands[1], temp);
 361             }
 362         }
 363       else if (GET_CODE (operands[1]) == CONST
 364                && GET_CODE (XEXP (operands[1], 0)) == PLUS
 365                && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
 366         {
 367           temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
 368           temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
 369                                                  temp);
 370           operands[1] = expand_binop (SImode, add_optab, temp,
 371                                       XEXP (XEXP (operands[1], 0), 1),
 372                                       (!can_create_pseudo_p ()
 373                                        ? temp
 374                                        : gen_reg_rtx (Pmode)),
 375                                       0, OPTAB_LIB_WIDEN);
 376         }
 377     }
 378 })
 379
 380 (define_insn "*movsi_internal"
 381   [(set (match_operand:SI 0 "nonimmediate_operand"
 382                           "=r,r,r,m,r, A,*y,*y,*z,*d")
 383         (match_operand:SI 1 "general_operand"
 384                           " 0,i,r,r,m,*y, A, i,*d,*z"))]
 385   "register_operand (operands[0], SImode)
 386    || register_operand (operands[1], SImode)"
 387 {
 388   switch (which_alternative)
 389     {
 390     case 0:
 391       return "";
 392     case 1: /* imm-reg*/
 393       /* See movhi for a discussion of sizes for 8-bit movu.  Note that the
 394          24-bit movu is 6 bytes, which is the same size as the full 32-bit
 395          mov form for An and Dn.  So again movu is only a win for Rn.  */
 396       if (TARGET_AM33
 397           && CONST_INT_P (operands[1])
 398           && REGNO_EXTENDED_P (REGNO (operands[0]), 1))
 399         {
 400           HOST_WIDE_INT val = INTVAL (operands[1]);
 401           if (IN_RANGE (val, 0x80, 0xff)
 402               || IN_RANGE (val, 0x800000, 0xffffff))
 403             return "movu %1,%0";
 404         }
 405       /* FALLTHRU */
 406     case 2:  /* reg-reg */
 407     case 3:  /* reg-mem */
 408     case 4:  /* mem-reg */
 409     case 5:  /* sp-reg */
 410     case 6:  /* reg-sp */
 411     case 7:  /* imm-sp */
 412     case 8:  /* reg-mdr */
 413     case 9:  /* mdr-reg */
 414       return "mov %1,%0";
 415     default:
 416       gcc_unreachable ();
 417     }
 418 }
 419   [(set_attr "isa" "*,*,*,*,*,*,*,am33,*,*")
 420    (set_attr_alternative "timings"
 421          [(const_int 11)
 422           (const_int 22)
 423           (const_int 11)
 424           (if_then_else (eq_attr "cpu" "am34")
 425                         (const_int 11) (const_int 22))
 426           (if_then_else (eq_attr "cpu" "am34")
 427                         (const_int 13) (const_int 24))
 428           (if_then_else (eq_attr "cpu" "am34")
 429                         (const_int 11) (const_int 22))
 430           (if_then_else (eq_attr "cpu" "am34")
 431                         (const_int 13) (const_int 24))
 432           (const_int 11)
 433           (const_int 11)
 434           (const_int 11)
 435          ])]
 436 )
 437
 438 (define_expand "movsf"
 439   [(set (match_operand:SF 0 "nonimmediate_operand")
 440         (match_operand:SF 1 "general_operand"))]
 441   "TARGET_AM33_2"
 442 {
 443   /* One of the ops has to be in a register.  */
 444   if (!register_operand (operand1, SFmode)
 445       && !register_operand (operand0, SFmode))
 446     operands[1] = force_reg (SFmode, operand1);
 447 })
 448
 449 (define_insn "*movsf_internal"
 450   [(set (match_operand:SF 0 "nonimmediate_operand" "=rf,r,f,r,f,r,f,r,m,f,Q")
 451         (match_operand:SF 1 "general_operand"      "  0,F,F,r,f,f,r,m,r,Q,f"))]
 452   "TARGET_AM33_2
 453    && (register_operand (operands[0], SFmode)
 454        || register_operand (operands[1], SFmode))"
 455 {
 456   switch (which_alternative)
 457     {
 458     case 0:
 459       return "";
 460     case 1:
 461     case 3:
 462     case 7:
 463     case 8:
 464       return "mov %1,%0";
 465     case 2:
 466     case 4:
 467     case 5:
 468     case 6:
 469     case 9:
 470     case 10:
 471       return "fmov %1,%0";
 472     default:
 473       gcc_unreachable ();
 474     }
 475 }
 476   [(set_attr_alternative "timings"
 477                  [(const_int 11)
 478                   (const_int 22)
 479                   (if_then_else (eq_attr "cpu" "am34")
 480                                 (const_int 47) (const_int 25))
 481                   (const_int 11)
 482                   (if_then_else (eq_attr "cpu" "am34")
 483                                 (const_int 13) (const_int 14))
 484                   (if_then_else (eq_attr "cpu" "am34")
 485                                 (const_int 13) (const_int 12))
 486                   (if_then_else (eq_attr "cpu" "am34")
 487                                 (const_int 13) (const_int 14))
 488                   (if_then_else (eq_attr "cpu" "am34")
 489                                 (const_int 13) (const_int 24))
 490                   (if_then_else (eq_attr "cpu" "am34")
 491                                 (const_int 13) (const_int 24))
 492                   (if_then_else (eq_attr "cpu" "am34")
 493                                 (const_int 13) (const_int 24))
 494                   (if_then_else (eq_attr "cpu" "am34")
 495                                 (const_int 13) (const_int 24))
 496                  ])]
 497 )
 498
 499 ;; If the flags register is not live, generate CLR instead of MOV 0.
 500 ;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal
 501 ;; but not a win for ADDRESS_REGS.
 502 (define_peephole2
 503   [(set (match_operand:INT 0 "register_operand" "") (const_int 0))]
 504   "peep2_regno_dead_p (0, CC_REG)
 505    && (REGNO_DATA_P (REGNO (operands[0]), 1)
 506        || REGNO_EXTENDED_P (REGNO (operands[0]), 1))"
 507   [(parallel [(set (match_dup 0) (const_int 0))
 508               (clobber (reg:CC CC_REG))])]
 509 )
 510
 511 (define_insn "*mov<mode>_clr"
 512   [(set (match_operand:INT 0 "register_operand" "=D")
 513         (const_int 0))
 514    (clobber (reg:CC CC_REG))]
 515   ""
 516   "clr %0"
 517 )
 518 \f
 519 ;; ----------------------------------------------------------------------
 520 ;; ADD INSTRUCTIONS
 521 ;; ----------------------------------------------------------------------
 522
 523 (define_insn "addsi3"
 524   [(set (match_operand:SI          0 "register_operand"  "=r,!*y,!r")
 525         (plus:SI (match_operand:SI 1 "register_operand"  "%0,  0, r")
 526                  (match_operand:SI 2 "nonmemory_operand" "ri,  i, r")))
 527    (clobber (reg:CC CC_REG))]
 528   ""
 529   { return mn10300_output_add (operands, false); }
 530   [(set_attr "timings" "11,11,22")]
 531 )
 532
 533 ;; Note that ADD IMM,SP does not set the flags, so omit that here.
 534 (define_insn "*addsi3_flags"
 535   [(set (match_operand:SI          0 "register_operand"  "=r,!r")
 536         (plus:SI (match_operand:SI 1 "register_operand"  "%0, r")
 537                  (match_operand:SI 2 "nonmemory_operand" "ri, r")))
 538    (set (reg CC_REG)
 539         (compare (plus:SI (match_dup 1) (match_dup 2))
 540                  (const_int 0)))]
 541   "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
 542   { return mn10300_output_add (operands, true); }
 543   [(set_attr "timings" "11,22")]
 544 )
 545
 546 ;; ----------------------------------------------------------------------
 547 ;; SUBTRACT INSTRUCTIONS
 548 ;; ----------------------------------------------------------------------
 549
 550 (define_insn "subsi3"
 551   [(set (match_operand:SI           0 "register_operand"  "=r,r")
 552         (minus:SI (match_operand:SI 1 "register_operand"  " 0,r")
 553                   (match_operand:SI 2 "nonmemory_operand" "ri,r")))
 554    (clobber (reg:CC CC_REG))]
 555   ""
 556   "@
 557    sub %2,%0
 558    sub %2,%1,%0"
 559   [(set_attr "isa" "*,am33")
 560    (set_attr "timings" "11,22")]
 561 )
 562
 563 (define_insn "*subsi3_flags"
 564   [(set (match_operand:SI           0 "register_operand"  "=r,r")
 565         (minus:SI (match_operand:SI 1 "register_operand"  " 0,r")
 566                   (match_operand:SI 2 "nonmemory_operand" "ri,r")))
 567    (set (reg CC_REG)
 568         (compare (minus:SI (match_dup 1) (match_dup 2))
 569                  (const_int 0)))]
 570   "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
 571   "@
 572    sub %2,%0
 573    sub %2,%1,%0"
 574   [(set_attr "isa" "*,am33")
 575    (set_attr "timings" "11,22")]
 576 )
 577
 578 (define_insn_and_split "negsi2"
 579   [(set (match_operand:SI         0 "register_operand"  "=D,&r")
 580         (neg:SI (match_operand:SI 1 "register_operand"  " 0, r")))
 581    (clobber (reg:CC CC_REG))]
 582   ""
 583   "#"
 584   "&& reload_completed"
 585   [(const_int 0)]
 586 {
 587   /* Recall that twos-compliment is ones-compliment plus one.  When
 588      allocated in DATA_REGS this is 2+1 bytes; otherwise (for am33)
 589      this is 3+3 bytes.
 590
 591      For AM33, it would have been possible to load zero and use the
 592      three-address subtract to have a total size of 3+4*N bytes for
 593      multiple negations, plus increased throughput.  Not attempted here.  */
 594
 595   if (true_regnum (operands[0]) == true_regnum (operands[1]))
 596     {
 597       emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
 598       emit_insn (gen_addsi3 (operands[0], operands[0], const1_rtx));
 599     }
 600   else
 601     {
 602       emit_move_insn (operands[0], const0_rtx);
 603       emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
 604     }
 605   DONE;
 606 })
 607
 608 ;; ----------------------------------------------------------------------
 609 ;; MULTIPLY INSTRUCTIONS
 610 ;; ----------------------------------------------------------------------
 611
 612 ;; ??? Note that AM33 has a third multiply variant that puts the high part
 613 ;; into the MDRQ register, however this variant also constrains the inputs
 614 ;; to be in DATA_REGS and thus isn't as helpful as it might be considering
 615 ;; the existance of the 4-operand multiply.  Nor is there a set of divide
 616 ;; insns that use MDRQ.  Given that there is an IMM->MDRQ insn, this would
 617 ;; have been very handy for starting udivmodsi4...
 618
 619 (define_expand "mulsidi3"
 620   [(set (match_operand:DI 0 "register_operand" "")
 621         (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
 622                  (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
 623   ""
 624 {
 625   emit_insn (gen_mulsidi3_internal (gen_lowpart (SImode, operands[0]),
 626                                     gen_highpart (SImode, operands[0]),
 627                                     operands[1], operands[2]));
 628   DONE;
 629 })
 630
 631 (define_insn "mulsidi3_internal"
 632   [(set (match_operand:SI          0 "register_operand" "=D,r")
 633         (mult:SI (match_operand:SI 2 "register_operand" "%0,r")
 634                  (match_operand:SI 3 "register_operand" " D,r")))
 635    (set (match_operand:SI          1 "register_operand" "=z,r")
 636         (truncate:SI
 637           (ashiftrt:DI
 638             (mult:DI (sign_extend:DI (match_dup 2))
 639                      (sign_extend:DI (match_dup 3)))
 640             (const_int 32))))
 641    (clobber (reg:CC CC_REG))]
 642   ""
 643 {
 644   if (which_alternative == 1)
 645     return "mul %2,%3,%1,%0";
 646   else if (TARGET_MULT_BUG)
 647     return "nop\;nop\;mul %3,%0";
 648   else
 649     return "mul %3,%0";
 650 }
 651   [(set_attr "isa" "*,am33")
 652    (set (attr "timings")
 653         (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
 654 )
 655
 656 (define_expand "umulsidi3"
 657   [(set (match_operand:DI 0 "register_operand" "")
 658         (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
 659                  (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
 660    (clobber (reg:CC CC_REG))]
 661   ""
 662 {
 663   emit_insn (gen_umulsidi3_internal (gen_lowpart (SImode, operands[0]),
 664                                      gen_highpart (SImode, operands[0]),
 665                                      operands[1], operands[2]));
 666   DONE;
 667 })
 668
 669 (define_insn "umulsidi3_internal"
 670   [(set (match_operand:SI          0 "register_operand" "=D,r")
 671         (mult:SI (match_operand:SI 2 "register_operand" "%0,r")
 672                  (match_operand:SI 3 "register_operand" " D,r")))
 673    (set (match_operand:SI          1 "register_operand" "=z,r")
 674         (truncate:SI
 675           (lshiftrt:DI
 676             (mult:DI (zero_extend:DI (match_dup 2))
 677                      (zero_extend:DI (match_dup 3)))
 678             (const_int 32))))
 679    (clobber (reg:CC CC_REG))]
 680   ""
 681 {
 682   if (which_alternative == 1)
 683     return "mulu %2,%3,%1,%0";
 684   else if (TARGET_MULT_BUG)
 685     return "nop\;nop\;mulu %3,%0";
 686   else
 687     return "mulu %3,%0";
 688 }
 689   [(set_attr "isa" "*,am33")
 690    (set (attr "timings")
 691         (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
 692 )
 693
 694 (define_expand "mulsi3"
 695   [(parallel [(set (match_operand:SI          0 "register_operand"  "")
 696                    (mult:SI (match_operand:SI 1 "register_operand"  "")
 697                             (match_operand:SI 2 "nonmemory_operand" "")))
 698               (clobber (match_scratch:SI      3 ""))
 699               (clobber (reg:CC CC_REG))])]
 700   ""
 701 )
 702
 703 (define_insn "*mulsi3"
 704   [(set (match_operand:SI          0 "register_operand"  "=D, r,r")
 705         (mult:SI (match_operand:SI 2 "register_operand"  "%0, 0,r")
 706                  (match_operand:SI 3 "nonmemory_operand" " D,ri,r")))
 707    (clobber (match_scratch:SI      1                     "=z, z,r"))
 708    (clobber (reg:CC CC_REG))]
 709   ""
 710 {
 711   if (which_alternative == 2)
 712     return "mul %2,%3,%1,%0";
 713   else if (TARGET_MULT_BUG)
 714     return "nop\;nop\;mul %3,%0";
 715   else
 716     return "mul %3,%0";
 717 }
 718   [(set_attr "isa" "*,am33,am33")
 719    (set (attr "timings")
 720         (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
 721 )
 722
 723 (define_expand "udivmodsi4"
 724   [(parallel [(set (match_operand:SI          0 "register_operand")
 725                    (udiv:SI (match_operand:SI 1 "register_operand")
 726                             (match_operand:SI 2 "register_operand")))
 727               (set (match_operand:SI          3 "register_operand")
 728                    (umod:SI (match_dup 1) (match_dup 2)))
 729               (use (const_int 0))
 730               (clobber (reg:CC CC_REG))])]
 731   ""
 732 )
 733
 734 ;; Note the trick to get reload to put the zero into the MDR register,
 735 ;; rather than exposing the load early and letting CSE or someone try
 736 ;; to share the zeros between division insns.  Which tends to result
 737 ;; in sequences like 0->r0->d0->mdr.
 738
 739 (define_insn "*udivmodsi4"
 740   [(set (match_operand:SI          0 "register_operand" "=D")
 741         (udiv:SI (match_operand:SI 2 "register_operand" " 0")
 742                  (match_operand:SI 3 "register_operand" " D")))
 743    (set (match_operand:SI          1 "register_operand" "=z")
 744         (umod:SI (match_dup 2) (match_dup 3)))
 745    (use (match_operand:SI          4 "nonmemory_operand" " 1"))
 746    (clobber (reg:CC CC_REG))]
 747   ""
 748   "divu %3,%0"
 749   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
 750                                        (const_int 3839) (const_int 4243)))]
 751 )
 752
 753 (define_expand "divmodsi4"
 754   [(parallel [(set (match_operand:SI          0 "register_operand" "")
 755                    (div:SI (match_operand:SI  1 "register_operand" "")
 756                            (match_operand:SI  2 "register_operand" "")))
 757               (set (match_operand:SI          3 "register_operand" "")
 758                    (mod:SI (match_dup 1) (match_dup 2)))
 759               (use (match_dup 4))
 760               (clobber (reg:CC CC_REG))])]
 761   ""
 762 {
 763   operands[4] = gen_reg_rtx (SImode);
 764   emit_insn (gen_ext_internal (operands[4], operands[1]));
 765 })
 766
 767 ;; ??? Ideally we'd represent this via shift, but it seems like adding a
 768 ;; special-case pattern for (ashiftrt x 31) is just as likely to result
 769 ;; in poor register allocation choices.
 770 (define_insn "ext_internal"
 771   [(set (match_operand:SI 0 "register_operand" "=z")
 772         (unspec:SI [(match_operand:SI 1 "register_operand" "D")] UNSPEC_EXT))]
 773   ""
 774   "ext %1"
 775 )
 776
 777 (define_insn "*divmodsi4"
 778   [(set (match_operand:SI          0 "register_operand" "=D")
 779         (div:SI (match_operand:SI  2 "register_operand" " 0")
 780                 (match_operand:SI  3 "register_operand" " D")))
 781    (set (match_operand:SI          1 "register_operand" "=z")
 782         (mod:SI (match_dup 2) (match_dup 3)))
 783    (use (match_operand:SI          4 "register_operand" " 1"))
 784    (clobber (reg:CC CC_REG))]
 785   ""
 786   "div %3,%0";
 787   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
 788                                        (const_int 3839) (const_int 4243)))]
 789 )
 790
 791 \f
 792 ;; ----------------------------------------------------------------------
 793 ;; AND INSTRUCTIONS
 794 ;; ----------------------------------------------------------------------
 795
 796 (define_insn "andsi3"
 797   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
 798         (and:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
 799                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
 800    (clobber (reg:CC CC_REG))]
 801   ""
 802   "@
 803    and %2,%0
 804    and %2,%0
 805    and %2,%1,%0"
 806   [(set_attr "isa" "*,*,am33")
 807    (set_attr "timings" "22,11,11")]
 808 )
 809
 810 (define_insn "*andsi3_flags"
 811   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
 812         (and:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
 813                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
 814    (set (reg CC_REG)
 815         (compare (and:SI (match_dup 1) (match_dup 2))
 816                  (const_int 0)))]
 817   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
 818   "@
 819    and %2,%0
 820    and %2,%0
 821    and %2,%1,%0"
 822   [(set_attr "isa" "*,*,am33")
 823    (set_attr "timings" "22,11,11")]
 824 )
 825
 826 ;; Make sure we generate extensions instead of ANDs.
 827
 828 (define_split
 829   [(parallel [(set (match_operand:SI 0 "register_operand" "")
 830                    (and:SI (match_operand:SI 1 "register_operand" "")
 831                            (const_int 255)))
 832               (clobber (reg:CC CC_REG))])]
 833   ""
 834   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
 835   { operands[1] = gen_lowpart (QImode, operands[1]); }
 836 )
 837
 838 (define_split
 839   [(parallel [(set (match_operand:SI 0 "register_operand" "")
 840                    (and:SI (match_operand:SI 1 "register_operand" "")
 841                            (const_int 65535)))
 842               (clobber (reg:CC CC_REG))])]
 843   ""
 844   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
 845   { operands[1] = gen_lowpart (HImode, operands[1]); }
 846 )
 847
 848 ;; Split AND by an appropriate constant into two shifts.  Recall that
 849 ;; operations with a full 32-bit immediate require an extra cycle, so
 850 ;; this is a size optimization with no speed penalty.  This only applies
 851 ;; do DATA_REGS; the shift insns that AM33 adds are too large for a win.
 852
 853 (define_split
 854   [(parallel [(set (match_operand:SI 0 "register_operand" "")
 855                    (and:SI (match_dup 0)
 856                            (match_operand:SI 1 "const_int_operand" "")))
 857               (clobber (reg:CC CC_REG))])]
 858   "reload_completed
 859    && REGNO_DATA_P (true_regnum (operands[0]), 1)
 860    && mn10300_split_and_operand_count (operands[1]) != 0"
 861   [(const_int 0)]
 862 {
 863   int count = mn10300_split_and_operand_count (operands[1]);
 864   if (count > 0)
 865     {
 866       emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (count)));
 867       emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (count)));
 868     }
 869   else
 870     {
 871       emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (-count)));
 872       emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (-count)));
 873     }
 874   DONE;
 875 })
 876
 877 ;; ----------------------------------------------------------------------
 878 ;; OR INSTRUCTIONS
 879 ;; ----------------------------------------------------------------------
 880
 881 (define_insn "iorsi3"
 882   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
 883         (ior:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
 884                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
 885    (clobber (reg:CC CC_REG))]
 886   ""
 887   "@
 888    or %2,%0
 889    or %2,%0
 890    or %2,%1,%0"
 891   [(set_attr "isa" "*,*,am33")
 892    (set_attr "timings" "22,11,11")]
 893 )
 894
 895 (define_insn "*iorsi3_flags"
 896   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
 897         (ior:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
 898                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
 899    (set (reg CC_REG)
 900         (compare (ior:SI (match_dup 1) (match_dup 2))
 901                  (const_int 0)))]
 902   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
 903   "@
 904    or %2,%0
 905    or %2,%0
 906    or %2,%1,%0"
 907   [(set_attr "isa" "*,*,am33")
 908    (set_attr "timings" "22,11,11")]
 909 )
 910
 911 ;; ----------------------------------------------------------------------
 912 ;; XOR INSTRUCTIONS
 913 ;; ----------------------------------------------------------------------
 914
 915 (define_insn "xorsi3"
 916   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
 917         (xor:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
 918                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
 919    (clobber (reg:CC CC_REG))]
 920   ""
 921   "@
 922    xor %2,%0
 923    xor %2,%0
 924    xor %2,%1,%0"
 925   [(set_attr "isa" "*,*,am33")
 926    (set_attr "timings" "22,11,11")]
 927 )
 928
 929 (define_insn "*xorsi3_flags"
 930   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
 931         (xor:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
 932                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
 933    (set (reg CC_REG)
 934         (compare (xor:SI (match_dup 1) (match_dup 2))
 935                  (const_int 0)))]
 936   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
 937   "@
 938    xor %2,%0
 939    xor %2,%0
 940    xor %2,%1,%0"
 941   [(set_attr "isa" "*,*,am33")
 942    (set_attr "timings" "22,11,11")]
 943 )
 944
 945 ;; ----------------------------------------------------------------------
 946 ;; NOT INSTRUCTIONS
 947 ;; ----------------------------------------------------------------------
 948
 949 (define_insn "one_cmplsi2"
 950   [(set (match_operand:SI         0 "register_operand" "=D")
 951         (not:SI (match_operand:SI 1 "register_operand" " 0")))
 952    (clobber (reg:CC CC_REG))]
 953   ""
 954   "not %0"
 955 )
 956
 957 (define_insn "*one_cmplsi2_flags"
 958   [(set (match_operand:SI         0 "register_operand" "=D")
 959         (not:SI (match_operand:SI 1 "register_operand" " 0")))
 960    (set (reg CC_REG)
 961         (compare (not:SI (match_dup 1))
 962                  (const_int 0)))]
 963   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
 964   "not %0"
 965 )
 966 \f
 967 ;; ----------------------------------------------------------------------
 968 ;; COMPARE AND BRANCH INSTRUCTIONS
 969 ;; ----------------------------------------------------------------------
 970
 971 ;; We expand the comparison into a single insn so that it will not be split
 972 ;; up by reload.
 973 (define_expand "cbranchsi4"
 974   [(set (pc)
 975         (if_then_else
 976               (match_operator                    0 "ordered_comparison_operator"
 977                               [(match_operand:SI 1 "register_operand")
 978                                (match_operand:SI 2 "nonmemory_operand")])
 979               (label_ref (match_operand 3 ""))
 980               (pc)))]
 981   ""
 982   ""
 983 )
 984
 985 (define_insn_and_split "*cbranchsi4_cmp"
 986   [(set (pc)
 987         (if_then_else (match_operator           3 "ordered_comparison_operator"
 988                        [(match_operand:SI       0 "register_operand"  "r")
 989                         (match_operand:SI       1 "nonmemory_operand" "ri")])
 990                       (match_operand            2 "label_ref_operand" "")
 991                       (pc)))]
 992   ""
 993   "#"
 994   "reload_completed"
 995   [(const_int 0)]
 996 {
 997   mn10300_split_cbranch (CCmode, operands[3], operands[2]);
 998   DONE;
 999 })
1000
1001 (define_insn "*cmpsi"
1002   [(set (reg CC_REG)
1003         (compare (match_operand:SI 0 "register_operand"  "r")
1004                  (match_operand:SI 1 "nonmemory_operand" "ri")))]
1005   "reload_completed"
1006 {
1007   /* The operands of CMP must be distinct registers.  In the case where
1008      we've failed to optimize the comparison of a register to itself, we
1009      must use another method to set the Z flag.  We can achieve this
1010      effect with a BTST 0,D0.  This will not alter the contents of D0;
1011      the use of d0 is arbitrary; any data register would work.  */
1012   if (rtx_equal_p (operands[0], operands[1]))
1013     return "btst 0,d0";
1014   else
1015     return "cmp %1,%0";
1016 }
1017   [(set_attr_alternative "timings"
1018      [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))])]
1019 )
1020
1021 (define_insn "*integer_conditional_branch"
1022   [(set (pc)
1023         (if_then_else (match_operator 0 "comparison_operator"
1024                         [(match_operand 2 "int_mode_flags" "")
1025                          (const_int 0)])
1026                       (label_ref (match_operand 1 "" ""))
1027                       (pc)))]
1028   "reload_completed"
1029   "b%b0 %1"
1030 )
1031
1032 (define_insn_and_split "*cbranchsi4_btst"
1033   [(set (pc)
1034         (if_then_else
1035           (match_operator 3 "CCZN_comparison_operator"
1036             [(and:SI (match_operand:SI 0 "register_operand" "D")
1037                      (match_operand:SI 1 "immediate_operand" "i"))
1038              (const_int 0)])
1039           (match_operand 2 "label_ref_operand" "")
1040           (pc)))]
1041   ""
1042   "#"
1043   "reload_completed"
1044   [(const_int 0)]
1045 {
1046   mn10300_split_cbranch (CCZNmode, operands[3], operands[2]);
1047   DONE;
1048 })
1049
1050 (define_insn "*btstsi"
1051   [(set (reg:CCZN CC_REG)
1052         (compare:CCZN
1053           (and:SI (match_operand:SI 0 "register_operand" "D")
1054                   (match_operand:SI 1 "immediate_operand" "i"))
1055           (const_int 0)))]
1056   "reload_completed"
1057   "btst %1,%0"
1058 )
1059
1060 (define_expand "cbranchsf4"
1061   [(set (pc)
1062       (if_then_else
1063             (match_operator                    0 "ordered_comparison_operator"
1064                             [(match_operand:SF 1 "register_operand")
1065                              (match_operand:SF 2 "nonmemory_operand")])
1066             (label_ref (match_operand 3 ""))
1067             (pc)))]
1068   "TARGET_AM33_2"
1069   ""
1070 )
1071
1072 (define_insn_and_split "*cbranchsf4_cmp"
1073   [(set (pc)
1074         (if_then_else (match_operator            3 "ordered_comparison_operator"
1075                         [(match_operand:SF       0 "register_operand"  "f")
1076                          (match_operand:SF       1 "nonmemory_operand" "fF")])
1077                       (match_operand             2 "label_ref_operand" "")
1078                       (pc)))
1079    ]
1080   "TARGET_AM33_2"
1081   "#"
1082   "&& reload_completed"
1083   [(const_int 0)]
1084 {
1085   mn10300_split_cbranch (CC_FLOATmode, operands[3], operands[2]);
1086   DONE;
1087 })
1088
1089 (define_insn "*am33_cmpsf"
1090   [(set (reg:CC_FLOAT CC_REG)
1091         (compare:CC_FLOAT (match_operand:SF 0 "register_operand"  "f")
1092                           (match_operand:SF 1 "nonmemory_operand" "fF")))]
1093   "TARGET_AM33_2 && reload_completed"
1094   "fcmp %1, %0"
1095   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1096                                        (const_int 17) (const_int 25)))]
1097 )
1098
1099 (define_insn "*float_conditional_branch"
1100   [(set (pc)
1101         (if_then_else (match_operator 0 "comparison_operator"
1102                                       [(reg:CC_FLOAT CC_REG) (const_int 0)])
1103                       (label_ref (match_operand 1 "" ""))
1104                       (pc)))]
1105   "TARGET_AM33_2 && reload_completed"
1106   "fb%b0 %1"
1107   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1108                                        (const_int 44) (const_int 33)))]
1109 )
1110
1111 ;; Unconditional and other jump instructions.
1112
1113 (define_insn "jump"
1114   [(set (pc)
1115         (label_ref (match_operand 0 "" "")))]
1116   ""
1117   "jmp %l0"
1118   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1119                                        (const_int 11) (const_int 44)))]
1120 )
1121
1122 (define_insn "indirect_jump"
1123   [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1124   ""
1125   "jmp (%0)"
1126   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1127                                        (const_int 11) (const_int 33)))]
1128 )
1129
1130 (define_expand "builtin_setjmp_receiver"
1131   [(match_operand 0 "" "")]
1132   "flag_pic"
1133 {
1134   emit_insn (gen_load_pic ());
1135   DONE;
1136 })
1137
1138 (define_expand "casesi"
1139   [(match_operand:SI 0 "register_operand")
1140    (match_operand:SI 1 "immediate_operand")
1141    (match_operand:SI 2 "immediate_operand")
1142    (match_operand 3 "" "") (match_operand 4 "")]
1143   ""
1144 {
1145   rtx table = gen_reg_rtx (SImode);
1146   rtx index = gen_reg_rtx (SImode);
1147   rtx addr = gen_reg_rtx (Pmode);
1148   rtx test;
1149
1150   emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
1151   emit_insn (gen_addsi3 (index, operands[0], GEN_INT (- INTVAL (operands[1]))));
1152   test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]);
1153   emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4]));
1154
1155   emit_insn (gen_ashlsi3 (index, index, const2_rtx));
1156   emit_move_insn (addr, gen_rtx_MEM (SImode,
1157                                      gen_rtx_PLUS (SImode, table, index)));
1158   if (flag_pic)
1159     emit_insn (gen_addsi3 (addr, addr, table));
1160
1161   emit_jump_insn (gen_tablejump (addr, operands[3]));
1162   DONE;
1163 })
1164
1165 (define_insn "tablejump"
1166   [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1167    (use (label_ref (match_operand 1 "" "")))]
1168   ""
1169   "jmp (%0)"
1170   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1171                                        (const_int 11) (const_int 33)))]
1172 )
1173
1174 ;; Call subroutine with no return value.
1175
1176 (define_expand "call"
1177   [(call (match_operand:QI 0 "general_operand")
1178          (match_operand:SI 1 "general_operand"))]
1179   ""
1180 {
1181   rtx fn = XEXP (operands[0], 0);
1182
1183   if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
1184     {
1185       if (MN10300_GLOBAL_P (fn))
1186         {
1187           /* The PLT code won't run on AM30, but then, there's no
1188              shared library support for AM30 either, so we just assume
1189              the linker is going to adjust all @PLT relocs to the
1190              actual symbols.  */
1191           emit_use (pic_offset_table_rtx);
1192           fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
1193         }
1194       else
1195         fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
1196     }
1197   if (! call_address_operand (fn, VOIDmode))
1198     fn = force_reg (SImode, fn);
1199
1200   XEXP (operands[0], 0) = fn;
1201 })
1202
1203 (define_insn "*call_internal"
1204   [(call (mem:QI (match_operand:SI 0 "call_address_operand" "a,S"))
1205          (match_operand:SI 1 "" ""))]
1206   ""
1207   "@
1208    calls %C0
1209    call %C0,[],0"
1210   [(set_attr_alternative "timings"
1211                          [(if_then_else (eq_attr "cpu" "am34")
1212                                         (const_int 33) (const_int 44))
1213                           (if_then_else (eq_attr "cpu" "am34")
1214                                         (const_int 55) (const_int 33))
1215                          ])
1216   ]
1217 )
1218
1219 ;; Call subroutine, returning value in operand 0
1220 ;; (which must be a hard register).
1221
1222 (define_expand "call_value"
1223   [(set (match_operand 0 "")
1224         (call (match_operand:QI 1 "general_operand")
1225               (match_operand:SI 2 "general_operand")))]
1226   ""
1227 {
1228   rtx fn = XEXP (operands[1], 0);
1229
1230   if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
1231     {
1232       if (MN10300_GLOBAL_P (fn))
1233         {
1234           /* The PLT code won't run on AM30, but then, there's no
1235              shared library support for AM30 either, so we just assume
1236              the linker is going to adjust all @PLT relocs to the
1237              actual symbols.  */
1238           emit_use (pic_offset_table_rtx);
1239           fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
1240         }
1241       else
1242         fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
1243     }
1244   if (! call_address_operand (fn, VOIDmode))
1245     fn = force_reg (SImode, fn);
1246
1247   XEXP (operands[1], 0) = fn;
1248 })
1249
1250 (define_insn "call_value_internal"
1251   [(set (match_operand 0 "" "")
1252         (call (mem:QI (match_operand:SI 1 "call_address_operand" "a,S"))
1253               (match_operand:SI 2 "" "")))]
1254   ""
1255   "@
1256    calls %C1
1257    call %C1,[],0"
1258   [(set_attr_alternative "timings"
1259                          [(if_then_else (eq_attr "cpu" "am34")
1260                                         (const_int 33) (const_int 44))
1261                           (if_then_else (eq_attr "cpu" "am34")
1262                                         (const_int 55) (const_int 33))
1263                          ])
1264   ]
1265 )
1266
1267 (define_expand "untyped_call"
1268   [(parallel [(call (match_operand 0 "")
1269                     (const_int 0))
1270               (match_operand 1 "")
1271               (match_operand 2 "")])]
1272   ""
1273 {
1274   int i;
1275
1276   emit_call_insn (gen_call (operands[0], const0_rtx));
1277
1278   for (i = 0; i < XVECLEN (operands[2], 0); i++)
1279     {
1280       rtx set = XVECEXP (operands[2], 0, i);
1281       emit_move_insn (SET_DEST (set), SET_SRC (set));
1282     }
1283   DONE;
1284 })
1285
1286 (define_insn "nop"
1287   [(const_int 0)]
1288   ""
1289   "nop"
1290 )
1291 \f
1292 ;; ----------------------------------------------------------------------
1293 ;; EXTEND INSTRUCTIONS
1294 ;; ----------------------------------------------------------------------
1295
1296 (define_insn "zero_extendqisi2"
1297   [(set (match_operand:SI 0 "register_operand"      "=D,D,r")
1298         (zero_extend:SI
1299          (match_operand:QI 1 "nonimmediate_operand" " 0,m,r")))]
1300   ""
1301   "@
1302    extbu %0
1303    movbu %1,%0
1304    extbu %1,%0"
1305   [(set_attr "isa" "*,*,am33")
1306    (set_attr_alternative "timings"
1307                  [(const_int 11)
1308                   (if_then_else (eq_attr "cpu" "am34")
1309                                 (const_int 13) (const_int 24))
1310                   (const_int 11)
1311                  ])]
1312 )
1313
1314 (define_insn "zero_extendhisi2"
1315   [(set (match_operand:SI 0 "register_operand"      "=D,D,r")
1316         (zero_extend:SI
1317          (match_operand:HI 1 "nonimmediate_operand" " 0,m,r")))]
1318   ""
1319   "@
1320    exthu %0
1321    movhu %1,%0
1322    exthu %1,%0"
1323   [(set_attr "isa" "*,*,am33")
1324    (set_attr_alternative "timings"
1325                  [(const_int 11)
1326                   (if_then_else (eq_attr "cpu" "am34")
1327                                 (const_int 13) (const_int 24))
1328                   (const_int 11)])]
1329 )
1330
1331 (define_insn "extendqisi2"
1332   [(set (match_operand:SI 0 "register_operand" "=D,r")
1333         (sign_extend:SI
1334          (match_operand:QI 1 "register_operand" "0,r")))]
1335   ""
1336   "@
1337    extb %0
1338    extb %1,%0"
1339   [(set_attr "isa" "*,am33")]
1340 )
1341
1342 (define_insn "extendhisi2"
1343   [(set (match_operand:SI 0 "register_operand" "=D,r")
1344         (sign_extend:SI
1345          (match_operand:HI 1 "register_operand" "0,r")))]
1346   ""
1347   "@
1348    exth %0
1349    exth %1,%0"
1350   [(set_attr "isa" "*,am33")]
1351 )
1352 \f
1353 ;; ----------------------------------------------------------------------
1354 ;; SHIFTS
1355 ;; ----------------------------------------------------------------------
1356
1357 (define_insn "ashlsi3"
1358   [(set (match_operand:SI  0 "register_operand"  "=r,D,d,d, D,r")
1359         (ashift:SI
1360           (match_operand:SI 1 "register_operand"  " 0,0,0,0, 0,r")
1361           (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,Di,r")))
1362    (clobber (reg:CC CC_REG))]
1363   ""
1364   "@
1365    add %0,%0
1366    asl2 %0
1367    asl2 %0\;add %0,%0
1368    asl2 %0\;asl2 %0
1369    asl %S2,%0
1370    asl %2,%1,%0"
1371   [(set_attr "isa" "*,*,*,*,*,am33")
1372    (set_attr "timings" "11,11,22,22,11,11")]
1373 )
1374
1375 (define_insn "lshrsi3"
1376   [(set (match_operand:SI  0 "register_operand"  "=D,r")
1377         (lshiftrt:SI
1378           (match_operand:SI 1 "register_operand"  " 0,r")
1379           (match_operand:QI 2 "nonmemory_operand" "Di,r")))
1380    (clobber (reg:CC CC_REG))]
1381   ""
1382   "@
1383    lsr %S2,%0
1384    lsr %2,%1,%0"
1385   [(set_attr "isa" "*,am33")]
1386 )
1387
1388 (define_insn "ashrsi3"
1389   [(set (match_operand:SI  0 "register_operand"  "=D,r")
1390         (ashiftrt:SI
1391           (match_operand:SI 1 "register_operand"  " 0,r")
1392           (match_operand:QI 2 "nonmemory_operand" "Di,r")))
1393    (clobber (reg:CC CC_REG))]
1394   ""
1395   "@
1396    asr %S2,%0
1397    asr %2,%1,%0"
1398   [(set_attr "isa" "*,am33")]
1399 )
1400
1401 ;; ----------------------------------------------------------------------
1402 ;; MISCELANEOUS
1403 ;; ----------------------------------------------------------------------
1404
1405 (define_expand "clzsi2"
1406   [(parallel [(set (match_operand:SI 0 "register_operand" "")
1407                    (unspec:SI [(match_operand:SI 1 "register_operand" "")
1408                                (const_int 0)] UNSPEC_BSCH))
1409               (clobber (reg:CC CC_REG))])]
1410   "TARGET_AM33"
1411 )
1412
1413 (define_insn "*bsch"
1414   [(set (match_operand:SI 0 "register_operand" "=r")
1415         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1416                     (match_operand:SI 2 "nonmemory_operand" "0")]
1417                    UNSPEC_BSCH))
1418    (clobber (reg:CC CC_REG))]
1419   "TARGET_AM33"
1420   "bsch %1,%0"
1421 )
1422
1423 ;; ----------------------------------------------------------------------
1424 ;; FP INSTRUCTIONS
1425 ;; ----------------------------------------------------------------------
1426
1427 (define_insn "abssf2"
1428   [(set (match_operand:SF         0 "register_operand" "=f,f")
1429         (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
1430   "TARGET_AM33_2"
1431   "@
1432    fabs %0
1433    fabs %1, %0"
1434   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1435                                        (const_int 17) (const_int 14)))]
1436 )
1437
1438 (define_insn "negsf2"
1439   [(set (match_operand:SF         0 "register_operand" "=f,f")
1440         (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
1441   "TARGET_AM33_2"
1442   "@
1443    fneg %0
1444    fneg %1, %0"
1445   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1446                                        (const_int 17) (const_int 14)))]
1447 )
1448
1449 (define_expand "sqrtsf2"
1450   [(set (match_operand:SF 0 "register_operand" "")
1451         (sqrt:SF (match_operand:SF 1 "register_operand" "")))]
1452   "TARGET_AM33_2 && flag_unsafe_math_optimizations"
1453 {
1454   rtx scratch = gen_reg_rtx (SFmode);
1455   emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
1456   emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
1457                          scratch));
1458   DONE;
1459 })
1460
1461 (define_insn "rsqrtsf2"
1462   [(set (match_operand:SF                  0 "register_operand" "=f,f")
1463         (div:SF (match_operand:SF          2 "const_1f_operand" "F,F")
1464                 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))
1465    (clobber (reg:CC_FLOAT CC_REG))]
1466   "TARGET_AM33_2"
1467   "@
1468    frsqrt %0
1469    frsqrt %1, %0"
1470   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1471                                        (const_int 4753) (const_int 2327)))]
1472 )
1473
1474 (define_insn "addsf3"
1475   [(set (match_operand:SF          0 "register_operand" "=f,f")
1476         (plus:SF (match_operand:SF 1 "register_operand" "%0,f")
1477                  (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1478    (clobber (reg:CC_FLOAT CC_REG))]
1479   "TARGET_AM33_2"
1480   "@
1481    fadd %2, %0
1482    fadd %2, %1, %0"
1483   [(set_attr_alternative "timings"
1484                          [(if_then_else (eq_attr "cpu" "am34")
1485                                         (const_int 17) (const_int 14))
1486                           (if_then_else (eq_attr "cpu" "am34")
1487                                         (const_int 17) (const_int 25))
1488                          ])]
1489 )
1490
1491 (define_insn "subsf3"
1492   [(set (match_operand:SF           0 "register_operand" "=f,f")
1493         (minus:SF (match_operand:SF 1 "register_operand" "0,f")
1494                   (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1495    (clobber (reg:CC_FLOAT CC_REG))]
1496   "TARGET_AM33_2"
1497   "@
1498    fsub %2, %0
1499    fsub %2, %1, %0"
1500   [(set_attr_alternative "timings"
1501                          [(if_then_else (eq_attr "cpu" "am34")
1502                                         (const_int 17) (const_int 14))
1503                           (if_then_else (eq_attr "cpu" "am34")
1504                                         (const_int 17) (const_int 25))
1505                          ])]
1506 )
1507
1508 (define_insn "mulsf3"
1509   [(set (match_operand:SF          0 "register_operand" "=f,f")
1510         (mult:SF (match_operand:SF 1 "register_operand" "%0,f")
1511                  (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1512   (clobber (reg:CC_FLOAT CC_REG))
1513   ]
1514   "TARGET_AM33_2"
1515   "@
1516    fmul %2, %0
1517    fmul %2, %1, %0"
1518   [(set_attr_alternative "timings"
1519                          [(if_then_else (eq_attr "cpu" "am34")
1520                                         (const_int 17) (const_int 14))
1521                           (if_then_else (eq_attr "cpu" "am34")
1522                                         (const_int 17) (const_int 25))
1523                          ])]
1524 )
1525
1526 (define_insn "divsf3"
1527   [(set (match_operand:SF         0 "register_operand" "=f,f")
1528         (div:SF (match_operand:SF 1 "register_operand"  "0,f")
1529                 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1530    (clobber (reg:CC_FLOAT CC_REG))]
1531   "TARGET_AM33_2"
1532   "@
1533    fdiv %2, %0
1534    fdiv %2, %1, %0"
1535   [(set_attr_alternative "timings"
1536                          [(if_then_else (eq_attr "cpu" "am34")
1537                                         (const_int 2531) (const_int 1216))
1538                           (if_then_else (eq_attr "cpu" "am34")
1539                                         (const_int 2531) (const_int 1317))
1540                          ])]
1541 )
1542
1543 (define_insn "fmasf4"
1544   [(set (match_operand:SF         0 "register_operand" "=c")
1545         (fma:SF (match_operand:SF 1 "register_operand" "f")
1546                 (match_operand:SF 2 "register_operand" "f")
1547                 (match_operand:SF 3 "register_operand" "f")))
1548    (clobber (reg:CC_FLOAT CC_REG))
1549   ]
1550   "TARGET_AM33_2"
1551   "fmadd %1, %2, %3, %0"
1552   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1553                                        (const_int 17) (const_int 24)))]
1554 )
1555
1556 (define_insn "fmssf4"
1557   [(set (match_operand:SF                 0 "register_operand" "=c")
1558         (fma:SF (match_operand:SF         1 "register_operand" "f")
1559                 (match_operand:SF         2 "register_operand" "f")
1560                 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
1561    (clobber (reg:CC_FLOAT CC_REG))
1562   ]
1563   "TARGET_AM33_2"
1564   "fmsub %1, %2, %3, %0"
1565   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1566                                        (const_int 17) (const_int 24)))]
1567 )
1568
1569 (define_insn "fnmasf4"
1570   [(set (match_operand:SF                 0 "register_operand" "=c")
1571         (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
1572                 (match_operand:SF         2 "register_operand" "f")
1573                 (match_operand:SF         3 "register_operand" "f")))
1574    (clobber (reg:CC_FLOAT CC_REG))
1575   ]
1576   "TARGET_AM33_2"
1577   "fnmadd %1, %2, %3, %0"
1578   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1579                                        (const_int 17) (const_int 24)))]
1580 )
1581
1582 (define_insn "fnmssf4"
1583   [(set (match_operand:SF                 0 "register_operand" "=c")
1584         (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
1585                 (match_operand:SF         2 "register_operand" "f")
1586                 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
1587    (clobber (reg:CC_FLOAT CC_REG))
1588   ]
1589   "TARGET_AM33_2"
1590   "fnmsub %1, %2, %3, %0"
1591   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1592                                        (const_int 17) (const_int 24)))]
1593 )
1594
1595 ;; ----------------------------------------------------------------------
1596 ;; PROLOGUE/EPILOGUE
1597 ;; ----------------------------------------------------------------------
1598 (define_expand "prologue"
1599   [(const_int 0)]
1600   ""
1601   { mn10300_expand_prologue (); DONE; }
1602 )
1603
1604 (define_expand "epilogue"
1605   [(return)]
1606   ""
1607   { mn10300_expand_epilogue (); DONE; }
1608 )
1609
1610 (define_insn "return"
1611   [(return)]
1612   "mn10300_can_use_rets_insn ()"
1613 {
1614   /* The RETF insn is 4 cycles faster than RETS, though 1 byte larger.  */
1615   if (optimize_insn_for_speed_p () && mn10300_can_use_retf_insn ())
1616     return "retf [],0";
1617   else
1618     return "rets";
1619 })
1620
1621 (define_insn "return_ret"
1622   [(return)
1623    (use (match_operand:SI 0 "const_int_operand" ""))]
1624   ""
1625 {
1626   /* The RETF insn is up to 3 cycles faster than RET.  */
1627   fputs ((mn10300_can_use_retf_insn () ? "\tretf " : "\tret "), asm_out_file);
1628   mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ());
1629   fprintf (asm_out_file, ",%d\n", (int) INTVAL (operands[0]));
1630   return "";
1631 })
1632
1633 ;; This instruction matches one generated by mn10300_gen_multiple_store()
1634 (define_insn "store_movm"
1635   [(match_parallel 0 "mn10300_store_multiple_operation"
1636     [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])]
1637   ""
1638 {
1639   fputs ("\tmovm ", asm_out_file);
1640   mn10300_print_reg_list (asm_out_file,
1641                           mn10300_store_multiple_operation (operands[0],
1642                                                             VOIDmode));
1643   fprintf (asm_out_file, ",(sp)\n");
1644   return "";
1645 }
1646   ;; Assume that no more than 8 registers will be pushed.
1647   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1648                                        (const_int 99) (const_int 88)))]
1649 )
1650
1651 (define_expand "load_pic"
1652   [(const_int 0)]
1653   "flag_pic"
1654 {
1655   if (TARGET_AM33)
1656     emit_insn (gen_am33_load_pic (pic_offset_table_rtx));
1657   else if (mn10300_frame_size () == 0)
1658     emit_insn (gen_mn10300_load_pic0 (pic_offset_table_rtx));
1659   else
1660     emit_insn (gen_mn10300_load_pic1 (pic_offset_table_rtx));
1661   DONE;
1662 })
1663
1664 (define_insn "am33_load_pic"
1665   [(set (match_operand:SI 0 "register_operand" "=a")
1666         (unspec:SI [(const_int 0)] UNSPEC_GOT))
1667    (clobber (reg:CC CC_REG))]
1668   "TARGET_AM33"
1669 {
1670   operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
1671   return ".LPIC%=:\;mov pc,%0\;add %1-(.LPIC%=-.),%0";
1672 }
1673   [(set_attr "timings" "33")]
1674 )
1675
1676 ;; Load pic register with push/pop of stack.
1677 (define_insn "mn10300_load_pic0"
1678   [(set (match_operand:SI 0 "register_operand" "=a")
1679         (unspec:SI [(const_int 0)] UNSPEC_GOT))
1680    (clobber (reg:SI MDR_REG))
1681    (clobber (reg:CC CC_REG))]
1682   ""
1683 {
1684   operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
1685   return ("add -4,sp\;"
1686           "calls .LPIC%=\n"
1687           ".LPIC%=:\;"
1688           "movm (sp),[%0]\;"
1689           "add %1-(.LPIC%=-.),%0");
1690 }
1691   [(set_attr "timings" "88")]
1692 )
1693
1694 ;; Load pic register re-using existing stack space.
1695 (define_insn "mn10300_load_pic1"
1696   [(set (match_operand:SI 0 "register_operand" "=a")
1697         (unspec:SI [(const_int 0)] UNSPEC_GOT))
1698    (clobber (mem:SI (reg:SI SP_REG)))
1699    (clobber (reg:SI MDR_REG))
1700    (clobber (reg:CC CC_REG))]
1701   ""
1702 {
1703   operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
1704   return ("calls .LPIC%=\n"
1705           ".LPIC%=:\;"
1706           "mov (sp),%0\;"
1707           "add %1-(.LPIC%=-.),%0");
1708 }
1709   [(set_attr "timings" "66")]
1710 )