gcc/config/mn10300/mn10300.md

   1 ;; GCC machine description for Matsushita MN10300
   2 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
   3 ;; 2005, 2006, 2007, 2008, 2009, 2010
   4 ;; Free Software Foundation, Inc.
   5 ;; Contributed by Jeff Law (law@cygnus.com).
   6
   7 ;; This file is part of GCC.
   8
   9 ;; GCC is free software; you can redistribute it and/or modify
  10 ;; it under the terms of the GNU General Public License as published by
  11 ;; the Free Software Foundation; either version 3, or (at your option)
  12 ;; any later version.
  13
  14 ;; GCC is distributed in the hope that it will be useful,
  15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ;; GNU General Public License for more details.
  18
  19 ;; You should have received a copy of the GNU General Public License
  20 ;; along with GCC; see the file COPYING3.  If not see
  21 ;; <http://www.gnu.org/licenses/>.
  22
  23 ;; The original PO technology requires these to be ordered by speed,
  24 ;; so that assigner will pick the fastest.
  25
  26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
  27
  28 (define_constants [
  29   (PIC_REG   6)
  30   (SP_REG    9)
  31   (MDR_REG  50)
  32   (CC_REG   51)
  33
  34   (UNSPEC_PIC           1)
  35   (UNSPEC_GOT           2)
  36   (UNSPEC_GOTOFF        3)
  37   (UNSPEC_PLT           4)
  38   (UNSPEC_GOTSYM_OFF    5)
  39
  40   (UNSPEC_EXT           6)
  41   (UNSPEC_BSCH          7)
  42 ])
  43
  44 (include "predicates.md")
  45 (include "constraints.md")
  46
  47 ;; Processor type.  This attribute must exactly match the processor_type
  48 ;; enumeration in mn10300.h.
  49 (define_attr "cpu" "mn10300,am33,am33_2,am34"
  50   (const (symbol_ref "(enum attr_cpu) mn10300_tune_cpu")))
  51
  52 ;; Used to control the "enabled" attribute on a per-instruction basis.
  53 (define_attr "isa" "base,am33,am33_2,am34"
  54   (const_string "base"))
  55
  56 (define_attr "enabled" ""
  57   (cond [(eq_attr "isa" "base")
  58          (const_int 1)
  59
  60          (and (eq_attr "isa" "am33")
  61               (ne (symbol_ref "TARGET_AM33") (const_int 0)))
  62          (const_int 1)
  63
  64          (and (eq_attr "isa" "am33_2")
  65               (ne (symbol_ref "TARGET_AM33_2") (const_int 0)))
  66          (const_int 1)
  67
  68          (and (eq_attr "isa" "am34")
  69               (ne (symbol_ref "TARGET_AM34") (const_int 0)))
  70          (const_int 1)
  71         ]
  72         (const_int 0))
  73 )
  74
  75 (define_mode_iterator INT [QI HI SI])
  76
  77 \f
  78 ;; ----------------------------------------------------------------------
  79 ;; Pipeline description.
  80 ;; ----------------------------------------------------------------------
  81
  82 ;; The AM33 only has a single pipeline.  It has five stages (fetch,
  83 ;; decode, execute, memory access, writeback) each of which normally
  84 ;; takes a single CPU clock cycle.
  85
  86 ;; The timings attribute consists of two numbers, the first is the
  87 ;; throughput, which is the number of cycles the instruction takes
  88 ;; to execute and generate a result.  The second is the latency
  89 ;; which is the effective number of cycles the instruction takes to
  90 ;; execute if its result is used by the following instruction.  The
  91 ;; latency is always greater than or equal to the throughput.
  92 ;; These values were taken from the Appendix of the "MN103E Series
  93 ;; Instruction Manual" and the timings for the AM34.
  94
  95 ;; Note - it would be nice to use strings rather than integers for
  96 ;; the possible values of this attribute, so that we can have the
  97 ;; gcc build mechanism check for values that are not supported by
  98 ;; the reservations below.  But this will not work because the code
  99 ;; in mn10300_adjust_sched_cost() needs integers not strings.
 100
 101 (define_attr "timings" "" (const_int 11))
 102
 103 (define_automaton "pipelining")
 104 (define_cpu_unit "throughput" "pipelining")
 105
 106 (define_insn_reservation "throughput__1_latency__1"  1
 107   (eq_attr "timings" "11") "throughput")
 108 (define_insn_reservation "throughput__1_latency__2"  2
 109   (eq_attr "timings" "12") "throughput,nothing")
 110 (define_insn_reservation "throughput__1_latency__3"  3
 111   (eq_attr "timings" "13") "throughput,nothing*2")
 112 (define_insn_reservation "throughput__1_latency__4"  4
 113   (eq_attr "timings" "14") "throughput,nothing*3")
 114 (define_insn_reservation "throughput__2_latency__2"  2
 115   (eq_attr "timings" "22") "throughput*2")
 116 (define_insn_reservation "throughput__2_latency__3"  3
 117   (eq_attr "timings" "23") "throughput*2,nothing")
 118 (define_insn_reservation "throughput__2_latency__4"  4
 119   (eq_attr "timings" "24") "throughput*2,nothing*2")
 120 (define_insn_reservation "throughput__2_latency__5"  5
 121   (eq_attr "timings" "25") "throughput*2,nothing*3")
 122 (define_insn_reservation "throughput__3_latency__3"  3
 123   (eq_attr "timings" "33") "throughput*3")
 124 (define_insn_reservation "throughput__3_latency__7"  7
 125   (eq_attr "timings" "37") "throughput*3,nothing*4")
 126 (define_insn_reservation "throughput__4_latency__4"  4
 127   (eq_attr "timings" "44") "throughput*4")
 128 (define_insn_reservation "throughput__4_latency__7"  7
 129   (eq_attr "timings" "47") "throughput*4,nothing*3")
 130 (define_insn_reservation "throughput__4_latency__8"  8
 131   (eq_attr "timings" "48") "throughput*4,nothing*4")
 132 (define_insn_reservation "throughput__5_latency__5"  5
 133   (eq_attr "timings" "55") "throughput*5")
 134 (define_insn_reservation "throughput__6_latency__6"  6
 135   (eq_attr "timings" "66") "throughput*6")
 136 (define_insn_reservation "throughput__7_latency__7"  7
 137   (eq_attr "timings" "77") "throughput*7")
 138 (define_insn_reservation "throughput__7_latency__8"  8
 139   (eq_attr "timings" "78") "throughput*7,nothing")
 140 (define_insn_reservation "throughput__8_latency__8"  8
 141   (eq_attr "timings" "88") "throughput*8")
 142 (define_insn_reservation "throughput__9_latency__9"  9
 143   (eq_attr "timings" "99") "throughput*9")
 144 (define_insn_reservation "throughput__8_latency_14" 14
 145   (eq_attr "timings" "814") "throughput*8,nothing*6")
 146 (define_insn_reservation "throughput__9_latency_10" 10
 147   (eq_attr "timings" "910") "throughput*9,nothing")
 148 (define_insn_reservation "throughput_10_latency_10" 10
 149   (eq_attr "timings" "1010") "throughput*10")
 150 (define_insn_reservation "throughput_12_latency_16" 16
 151   (eq_attr "timings" "1216") "throughput*12,nothing*4")
 152 (define_insn_reservation "throughput_13_latency_13" 13
 153   (eq_attr "timings" "1313") "throughput*13")
 154 (define_insn_reservation "throughput_14_latency_14" 14
 155   (eq_attr "timings" "1414") "throughput*14")
 156 (define_insn_reservation "throughput_13_latency_17" 17
 157   (eq_attr "timings" "1317") "throughput*13,nothing*4")
 158 (define_insn_reservation "throughput_23_latency_27" 27
 159   (eq_attr "timings" "2327") "throughput*23,nothing*4")
 160 (define_insn_reservation "throughput_25_latency_31" 31
 161   (eq_attr "timings" "2531") "throughput*25,nothing*6")
 162 (define_insn_reservation "throughput_38_latency_39" 39
 163   (eq_attr "timings" "3839") "throughput*38,nothing")
 164 (define_insn_reservation "throughput_39_latency_40" 40
 165   (eq_attr "timings" "3940") "throughput*39,nothing")
 166 (define_insn_reservation "throughput_40_latency_40" 40
 167   (eq_attr "timings" "4040") "throughput*40")
 168 (define_insn_reservation "throughput_41_latency_42" 42
 169   (eq_attr "timings" "4142") "throughput*41,nothing")
 170 (define_insn_reservation "throughput_42_latency_43" 44
 171   (eq_attr "timings" "4243") "throughput*42,nothing")
 172 (define_insn_reservation "throughput_43_latency_44" 44
 173   (eq_attr "timings" "4344") "throughput*43,nothing")
 174 (define_insn_reservation "throughput_45_latency_46" 46
 175   (eq_attr "timings" "4546") "throughput*45,nothing")
 176 (define_insn_reservation "throughput_47_latency_53" 53
 177   (eq_attr "timings" "4753") "throughput*47,nothing*6")
 178
 179 ;; Note - the conflict between memory load/store instructions
 180 ;; and floating point instructions described in section 1-7-4
 181 ;; of Chapter 3 of the MN103E Series Instruction Manual is
 182 ;; handled by the mn10300_adjust_sched_cost function.
 183 \f
 184 ;; ----------------------------------------------------------------------
 185 ;; MOVE INSTRUCTIONS
 186 ;; ----------------------------------------------------------------------
 187
 188 ;; movqi
 189
 190 (define_expand "movqi"
 191   [(set (match_operand:QI 0 "nonimmediate_operand")
 192         (match_operand:QI 1 "general_operand"))]
 193   ""
 194 {
 195   /* One of the ops has to be in a register.  */
 196   if (!register_operand (operand0, QImode)
 197       && !register_operand (operand1, QImode))
 198     operands[1] = force_reg (QImode, operand1);
 199 })
 200
 201 (define_insn "*movqi_internal"
 202   [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m")
 203         (match_operand:QI 1 "general_operand"      "  0,D*r,  i,m,D"))]
 204   "(register_operand (operands[0], QImode)
 205     || register_operand (operands[1], QImode))"
 206 {
 207   switch (which_alternative)
 208     {
 209     case 0:
 210       return "";
 211     case 1:
 212     case 2:
 213       return "mov %1,%0";
 214     case 3:
 215     case 4:
 216       return "movbu %1,%0";
 217     default:
 218       gcc_unreachable ();
 219     }
 220 }
 221   [(set_attr_alternative "timings"
 222          [(const_int 11)
 223           (const_int 11)
 224           (const_int 11)
 225           (if_then_else (eq_attr "cpu" "am34")
 226                         (const_int 13) (const_int 24))
 227           (if_then_else (eq_attr "cpu" "am34")
 228                         (const_int 11) (const_int 22))
 229          ])]
 230 )
 231
 232 ;; movhi
 233
 234 (define_expand "movhi"
 235   [(set (match_operand:HI 0 "nonimmediate_operand")
 236         (match_operand:HI 1 "general_operand"))]
 237   ""
 238 {
 239   /* One of the ops has to be in a register.  */
 240   if (!register_operand (operand1, HImode)
 241       && !register_operand (operand0, HImode))
 242     operands[1] = force_reg (HImode, operand1);
 243 })
 244
 245 (define_insn "*movhi_internal"
 246   [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m")
 247         (match_operand:HI 1 "general_operand"      "  0,  i,D*r,m,D"))]
 248   "(register_operand (operands[0], HImode)
 249     || register_operand (operands[1], HImode))"
 250 {
 251   switch (which_alternative)
 252     {
 253     case 0:
 254       return "";
 255     case 1:
 256       /* Note that "MOV imm8,An" is already zero-extending, and is 2 bytes.
 257          We have "MOV imm16,Dn" at 3 bytes.  The only win for the 4 byte
 258          movu is for an 8-bit unsigned move into Rn.  */
 259       if (TARGET_AM33
 260           && CONST_INT_P (operands[1])
 261           && IN_RANGE (INTVAL (operands[1]), 0x80, 0xff)
 262           && REGNO_EXTENDED_P (REGNO (operands[0]), 1))
 263         return "movu %1,%0";
 264       /* FALLTHRU */
 265     case 2:
 266       return "mov %1,%0";
 267     case 3:
 268     case 4:
 269       return "movhu %1,%0";
 270     default:
 271       gcc_unreachable ();
 272     }
 273 }
 274   [(set_attr_alternative "timings"
 275          [(const_int 11)
 276           (const_int 11)
 277           (if_then_else (eq_attr "cpu" "am34")
 278                         (const_int 11) (const_int 22))
 279           (if_then_else (eq_attr "cpu" "am34")
 280                         (const_int 13) (const_int 24))
 281           (if_then_else (eq_attr "cpu" "am34")
 282                         (const_int 11) (const_int 22))
 283          ])]
 284 )
 285
 286 ;; movsi and helpers
 287
 288 ;; We use this to handle addition of two values when one operand is the
 289 ;; stack pointer and the other is a memory reference of some kind.  Reload
 290 ;; does not handle them correctly without this expander.
 291 (define_expand "reload_plus_sp_const"
 292   [(set (match_operand:SI     0 "register_operand" "=r")
 293         (match_operand:SI     1 "impossible_plus_operand" ""))
 294    (clobber (match_operand:SI 2 "register_operand" "=&A"))]
 295   ""
 296 {
 297   rtx dest, scratch, other;
 298
 299   dest = operands[0];
 300   scratch = operands[2];
 301
 302   other = XEXP (operands[1], 1);
 303   if (other == stack_pointer_rtx)
 304     other = XEXP (operands[1], 0);
 305
 306   if (true_regnum (other) == true_regnum (dest))
 307     {
 308       gcc_assert (true_regnum (scratch) != true_regnum (dest));
 309       emit_move_insn (scratch, stack_pointer_rtx);
 310       emit_insn (gen_addsi3 (dest, dest, scratch));
 311     }
 312   else if (TARGET_AM33 || REGNO_REG_CLASS (true_regnum (dest)) == ADDRESS_REGS)
 313     {
 314       emit_move_insn (dest, stack_pointer_rtx);
 315       if (other == stack_pointer_rtx)
 316         emit_insn (gen_addsi3 (dest, dest, dest));
 317       else if (other != const0_rtx)
 318         emit_insn (gen_addsi3 (dest, dest, other));
 319     }
 320   else
 321     {
 322       emit_move_insn (scratch, stack_pointer_rtx);
 323       if (other == stack_pointer_rtx)
 324         {
 325           emit_move_insn (dest, scratch);
 326           emit_insn (gen_addsi3 (dest, dest, dest));
 327         }
 328       else if (other != const0_rtx)
 329         {
 330           emit_move_insn (dest, other);
 331           emit_insn (gen_addsi3 (dest, dest, scratch));
 332         }
 333       else
 334         emit_move_insn (dest, scratch);
 335     }
 336   DONE;
 337 })
 338
 339 (define_expand "movsi"
 340   [(set (match_operand:SI 0 "nonimmediate_operand")
 341         (match_operand:SI 1 "general_operand"))]
 342   ""
 343 {
 344   /* One of the ops has to be in a register.  */
 345   if (!register_operand (operand1, SImode)
 346       && !register_operand (operand0, SImode))
 347     operands[1] = force_reg (SImode, operand1);
 348   if (flag_pic)
 349     {
 350       rtx temp;
 351       if (SYMBOLIC_CONST_P (operands[1]))
 352         {
 353           if (MEM_P (operands[0]))
 354             operands[1] = force_reg (Pmode, operands[1]);
 355           else
 356             {
 357               temp = (!can_create_pseudo_p ()
 358                       ? operands[0]
 359                       : gen_reg_rtx (Pmode));
 360               operands[1] = mn10300_legitimize_pic_address (operands[1], temp);
 361             }
 362         }
 363       else if (GET_CODE (operands[1]) == CONST
 364                && GET_CODE (XEXP (operands[1], 0)) == PLUS
 365                && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
 366         {
 367           temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
 368           temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
 369                                                  temp);
 370           operands[1] = expand_binop (SImode, add_optab, temp,
 371                                       XEXP (XEXP (operands[1], 0), 1),
 372                                       (!can_create_pseudo_p ()
 373                                        ? temp
 374                                        : gen_reg_rtx (Pmode)),
 375                                       0, OPTAB_LIB_WIDEN);
 376         }
 377     }
 378 })
 379
 380 (define_insn "*movsi_internal"
 381   [(set (match_operand:SI 0 "nonimmediate_operand"
 382                           "=r,r,r,m,r, A,*y,*y,*z,*d")
 383         (match_operand:SI 1 "general_operand"
 384                           " 0,i,r,r,m,*y, A, i,*d,*z"))]
 385   "register_operand (operands[0], SImode)
 386    || register_operand (operands[1], SImode)"
 387 {
 388   switch (which_alternative)
 389     {
 390     case 0:
 391       return "";
 392     case 1: /* imm-reg*/
 393       /* See movhi for a discussion of sizes for 8-bit movu.  Note that the
 394          24-bit movu is 6 bytes, which is the same size as the full 32-bit
 395          mov form for An and Dn.  So again movu is only a win for Rn.  */
 396       if (TARGET_AM33
 397           && CONST_INT_P (operands[1])
 398           && REGNO_EXTENDED_P (REGNO (operands[0]), 1))
 399         {
 400           HOST_WIDE_INT val = INTVAL (operands[1]);
 401           if (IN_RANGE (val, 0x80, 0xff)
 402               || IN_RANGE (val, 0x800000, 0xffffff))
 403             return "movu %1,%0";
 404         }
 405       /* FALLTHRU */
 406     case 2:  /* reg-reg */
 407     case 3:  /* reg-mem */
 408     case 4:  /* mem-reg */
 409     case 5:  /* sp-reg */
 410     case 6:  /* reg-sp */
 411     case 7:  /* imm-sp */
 412     case 8:  /* reg-mdr */
 413     case 9:  /* mdr-reg */
 414       return "mov %1,%0";
 415     default:
 416       gcc_unreachable ();
 417     }
 418 }
 419   [(set_attr "isa" "*,*,*,*,*,*,*,am33,*,*")
 420    (set_attr_alternative "timings"
 421          [(const_int 11)
 422           (const_int 22)
 423           (const_int 11)
 424           (if_then_else (eq_attr "cpu" "am34")
 425                         (const_int 11) (const_int 22))
 426           (if_then_else (eq_attr "cpu" "am34")
 427                         (const_int 13) (const_int 24))
 428           (if_then_else (eq_attr "cpu" "am34")
 429                         (const_int 11) (const_int 22))
 430           (if_then_else (eq_attr "cpu" "am34")
 431                         (const_int 13) (const_int 24))
 432           (const_int 11)
 433           (const_int 11)
 434           (const_int 11)
 435          ])]
 436 )
 437
 438 (define_expand "movsf"
 439   [(set (match_operand:SF 0 "nonimmediate_operand")
 440         (match_operand:SF 1 "general_operand"))]
 441   "TARGET_AM33_2"
 442 {
 443   /* One of the ops has to be in a register.  */
 444   if (!register_operand (operand1, SFmode)
 445       && !register_operand (operand0, SFmode))
 446     operands[1] = force_reg (SFmode, operand1);
 447 })
 448
 449 (define_insn "*movsf_internal"
 450   [(set (match_operand:SF 0 "nonimmediate_operand" "=rf,r,f,r,f,r,f,r,m,f,Q")
 451         (match_operand:SF 1 "general_operand"      "  0,F,F,r,f,f,r,m,r,Q,f"))]
 452   "TARGET_AM33_2
 453    && (register_operand (operands[0], SFmode)
 454        || register_operand (operands[1], SFmode))"
 455 {
 456   switch (which_alternative)
 457     {
 458     case 0:
 459       return "";
 460     case 1:
 461     case 3:
 462     case 7:
 463     case 8:
 464       return "mov %1,%0";
 465     case 2:
 466     case 4:
 467     case 5:
 468     case 6:
 469     case 9:
 470     case 10:
 471       return "fmov %1,%0";
 472     default:
 473       gcc_unreachable ();
 474     }
 475 }
 476   [(set_attr_alternative "timings"
 477                  [(const_int 11)
 478                   (const_int 22)
 479                   (if_then_else (eq_attr "cpu" "am34")
 480                                 (const_int 47) (const_int 25))
 481                   (const_int 11)
 482                   (if_then_else (eq_attr "cpu" "am34")
 483                                 (const_int 13) (const_int 14))
 484                   (if_then_else (eq_attr "cpu" "am34")
 485                                 (const_int 13) (const_int 12))
 486                   (if_then_else (eq_attr "cpu" "am34")
 487                                 (const_int 13) (const_int 14))
 488                   (if_then_else (eq_attr "cpu" "am34")
 489                                 (const_int 13) (const_int 24))
 490                   (if_then_else (eq_attr "cpu" "am34")
 491                                 (const_int 13) (const_int 24))
 492                   (if_then_else (eq_attr "cpu" "am34")
 493                                 (const_int 13) (const_int 24))
 494                   (if_then_else (eq_attr "cpu" "am34")
 495                                 (const_int 13) (const_int 24))
 496                  ])]
 497 )
 498
 499 ;; If the flags register is not live, generate CLR instead of MOV 0.
 500 ;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal
 501 ;; but not a win for ADDRESS_REGS.
 502 (define_peephole2
 503   [(set (match_operand:INT 0 "register_operand" "") (const_int 0))]
 504   "peep2_regno_dead_p (0, CC_REG)
 505    && (REGNO_DATA_P (REGNO (operands[0]), 1)
 506        || REGNO_EXTENDED_P (REGNO (operands[0]), 1))"
 507   [(parallel [(set (match_dup 0) (const_int 0))
 508               (clobber (reg:CC CC_REG))])]
 509 )
 510
 511 (define_insn "*mov<mode>_clr"
 512   [(set (match_operand:INT 0 "register_operand" "=D")
 513         (const_int 0))
 514    (clobber (reg:CC CC_REG))]
 515   ""
 516   "clr %0"
 517 )
 518 \f
 519 ;; ----------------------------------------------------------------------
 520 ;; ADD INSTRUCTIONS
 521 ;; ----------------------------------------------------------------------
 522
 523 (define_insn "addsi3"
 524   [(set (match_operand:SI          0 "register_operand"  "=r,!*y,!r")
 525         (plus:SI (match_operand:SI 1 "register_operand"  "%0,  0, r")
 526                  (match_operand:SI 2 "nonmemory_operand" "ri,  i, r")))
 527    (clobber (reg:CC CC_REG))]
 528   ""
 529   { return mn10300_output_add (operands, false); }
 530   [(set_attr "timings" "11,11,22")]
 531 )
 532
 533 ;; Note that ADD IMM,SP does not set the flags, so omit that here.
 534 (define_insn "*addsi3_flags"
 535   [(set (match_operand:SI          0 "register_operand"  "=r,!r")
 536         (plus:SI (match_operand:SI 1 "register_operand"  "%0, r")
 537                  (match_operand:SI 2 "nonmemory_operand" "ri, r")))
 538    (set (reg CC_REG)
 539         (compare (plus:SI (match_dup 1) (match_dup 2))
 540                  (const_int 0)))]
 541   "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
 542   { return mn10300_output_add (operands, true); }
 543   [(set_attr "timings" "11,22")]
 544 )
 545
 546 ;; A helper to expand the above, with the CC_MODE filled in.
 547 (define_expand "addsi3_flags"
 548   [(parallel [(set (match_operand:SI 0 "register_operand")
 549                    (plus:SI (match_operand:SI 1 "register_operand")
 550                             (match_operand:SI 2 "nonmemory_operand")))
 551               (set (reg:CCZNC CC_REG)
 552                    (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2))
 553                                   (const_int 0)))])]
 554   ""
 555 )
 556
 557 (define_insn "addc_internal"
 558   [(set (match_operand:SI 0 "register_operand"            "=D,r,r")
 559         (plus:SI
 560           (plus:SI
 561             (ltu:SI (reg:CC CC_REG) (const_int 0))
 562             (match_operand:SI 1 "register_operand"        "%0,0,r"))
 563           (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r")))
 564     (clobber (reg:CC CC_REG))]
 565   "reload_completed"
 566   "@
 567    addc %2,%0
 568    addc %2,%0
 569    addc %2,%1,%0"
 570   [(set_attr "isa" "*,am33,am33")]
 571 )
 572
 573 (define_expand "adddi3"
 574   [(set (match_operand:DI 0 "register_operand" "")
 575         (plus:DI (match_operand:DI 1 "register_operand" "")
 576                  (match_operand:DI 2 "nonmemory_operand" "")))]
 577   ""
 578 {
 579   rtx op0l, op0h, op1l, op1h, op2l, op2h;
 580
 581   op0l = gen_lowpart (SImode, operands[0]);
 582   op1l = gen_lowpart (SImode, operands[1]);
 583   op2l = gen_lowpart (SImode, operands[2]);
 584   op0h = gen_highpart (SImode, operands[0]);
 585   op1h = gen_highpart (SImode, operands[1]);
 586   op2h = gen_highpart_mode (SImode, DImode, operands[2]);
 587
 588   if (!reg_or_am33_const_operand (op2h, SImode))
 589     op2h = force_reg (SImode, op2h);
 590
 591   emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
 592   DONE;
 593 })
 594
 595 ;; Note that reload only supports one commutative operand.  Thus we cannot
 596 ;; auto-swap both the high and low outputs with their matching constraints.
 597 ;; For MN103, we're strapped for registers but thankfully the alternatives
 598 ;; are few.  For AM33, it becomes much easier to not represent the early
 599 ;; clobber and 6 permutations of immediate and three-operand adds, but
 600 ;; instead allocate a scratch register and do the expansion by hand.
 601
 602 (define_insn_and_split "adddi3_internal"
 603   [(set (match_operand:SI          0 "register_operand"   "=r, r, r")
 604         (plus:SI (match_operand:SI 2 "register_operand"   "%0, 0, r")
 605                  (match_operand:SI 3 "nonmemory_operand"  "ri,ri,ri")))
 606    (set (match_operand:SI          1 "register_operand"   "=D, D, r")
 607         (plus:SI
 608           (plus:SI
 609             (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2))
 610             (match_operand:SI      4 "register_operand"   " 1, D, r"))
 611           (match_operand:SI 5 "reg_or_am33_const_operand" " D, 1,ri")))
 612    (clobber (match_scratch:SI      6                      "=X, X,&r"))
 613    (clobber (reg:CC CC_REG))]
 614   ""
 615   "#"
 616   "reload_completed"
 617   [(const_int 0)]
 618 {
 619   rtx op0l = operands[0];
 620   rtx op0h = operands[1];
 621   rtx op1l = operands[2];
 622   rtx op2l = operands[3];
 623   rtx op1h = operands[4];
 624   rtx op2h = operands[5];
 625   rtx scratch = operands[6];
 626   rtx x;
 627
 628   if (reg_overlap_mentioned_p (op0l, op1h))
 629     {
 630       emit_move_insn (scratch, op0l);
 631       op1h = scratch;
 632       if (reg_overlap_mentioned_p (op0l, op2h))
 633         op2h = scratch;
 634     }
 635   else if (reg_overlap_mentioned_p (op0l, op2h))
 636     {
 637       emit_move_insn (scratch, op0l);
 638       op2h = scratch;
 639     }
 640
 641   if (rtx_equal_p (op0l, op1l))
 642     ;
 643   else if (rtx_equal_p (op0l, op2l))
 644     x = op1l, op1l = op2l, op2l = x;
 645   else
 646     {
 647       gcc_assert (TARGET_AM33);
 648       if (!REG_P (op2l))
 649         {
 650           emit_move_insn (op0l, op2l);
 651           op2l = op1l;
 652           op1l = op0l;
 653         }
 654     }
 655   emit_insn (gen_addsi3_flags (op0l, op1l, op2l));
 656
 657   if (rtx_equal_p (op0h, op1h))
 658     ;
 659   else if (rtx_equal_p (op0h, op2h))
 660     x = op1h, op1h = op2h, op2h = x;
 661   else
 662     {
 663       gcc_assert (TARGET_AM33);
 664       if (!REG_P (op2h))
 665         {
 666           emit_move_insn (op0h, op2h);
 667           op2h = op1h;
 668           op1h = op0h;
 669         }
 670     }
 671   emit_insn (gen_addc_internal (op0h, op1h, op2h));
 672   DONE;
 673 }
 674   [(set_attr "isa" "*,*,am33")]
 675 )
 676
 677 ;; The following pattern is generated by combine when it proves that one
 678 ;; of the inputs to the low-part of the double-word add is zero, and thus
 679 ;; no carry is generated into the high-part.
 680
 681 (define_insn_and_split "*adddi3_degenerate"
 682   [(set (match_operand:SI          0 "register_operand"  "=&r,&r")
 683         (match_operand:SI          2 "nonmemory_operand" "  0, 0"))
 684    (set (match_operand:SI          1 "register_operand"  "=r , r")
 685         (plus:SI (match_operand:SI 3 "register_operand"  "%1 , r")
 686                  (match_operand:SI 4 "nonmemory_operand" "ri, r")))
 687    (clobber (reg:CC CC_REG))]
 688   ""
 689   "#"
 690   ""
 691   [(const_int 0)]
 692 {
 693   rtx scratch = NULL_RTX;
 694   if (!rtx_equal_p (operands[0], operands[2]))
 695     {
 696       gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1]));
 697       if (reg_overlap_mentioned_p (operands[0], operands[3])
 698           || reg_overlap_mentioned_p (operands[0], operands[4]))
 699         {
 700           scratch = gen_reg_rtx (SImode);
 701           emit_move_insn (scratch, operands[2]);
 702         }
 703       else
 704         emit_move_insn (operands[0], operands[2]);
 705     }
 706   emit_insn (gen_addsi3 (operands[1], operands[3], operands[4]));
 707   if (scratch)
 708     emit_move_insn (operands[0], scratch);
 709   DONE;
 710 })
 711
 712 ;; ----------------------------------------------------------------------
 713 ;; SUBTRACT INSTRUCTIONS
 714 ;; ----------------------------------------------------------------------
 715
 716 (define_insn "subsi3"
 717   [(set (match_operand:SI           0 "register_operand"  "=r,r")
 718         (minus:SI (match_operand:SI 1 "register_operand"  " 0,r")
 719                   (match_operand:SI 2 "nonmemory_operand" "ri,r")))
 720    (clobber (reg:CC CC_REG))]
 721   ""
 722   "@
 723    sub %2,%0
 724    sub %2,%1,%0"
 725   [(set_attr "isa" "*,am33")
 726    (set_attr "timings" "11,22")]
 727 )
 728
 729 (define_insn "*subsi3_flags"
 730   [(set (match_operand:SI           0 "register_operand"  "=r,r")
 731         (minus:SI (match_operand:SI 1 "register_operand"  " 0,r")
 732                   (match_operand:SI 2 "nonmemory_operand" "ri,r")))
 733    (set (reg CC_REG)
 734         (compare (minus:SI (match_dup 1) (match_dup 2))
 735                  (const_int 0)))]
 736   "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
 737   "@
 738    sub %2,%0
 739    sub %2,%1,%0"
 740   [(set_attr "isa" "*,am33")
 741    (set_attr "timings" "11,22")]
 742 )
 743
 744 ;; A helper to expand the above, with the CC_MODE filled in.
 745 (define_expand "subsi3_flags"
 746   [(parallel [(set (match_operand:SI 0 "register_operand")
 747                    (minus:SI (match_operand:SI 1 "register_operand")
 748                              (match_operand:SI 2 "nonmemory_operand")))
 749               (set (reg:CCZNC CC_REG)
 750                    (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2))
 751                                   (const_int 0)))])]
 752   ""
 753 )
 754
 755 (define_insn "subc_internal"
 756   [(set (match_operand:SI 0 "register_operand"                      "=D,r,r")
 757         (minus:SI
 758           (minus:SI (match_operand:SI 1 "register_operand"          " 0,0,r")
 759                     (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r"))
 760           (geu:SI (reg:CC CC_REG) (const_int 0))))
 761    (clobber (reg:CC CC_REG))]
 762   "reload_completed"
 763   "@
 764    subc %2,%0
 765    subc %2,%0
 766    subc %2,%1,%0"
 767   [(set_attr "isa" "*,am33,am33")]
 768 )
 769
 770 (define_expand "subdi3"
 771   [(set (match_operand:DI 0 "register_operand" "")
 772         (minus:DI (match_operand:DI 1 "register_operand" "")
 773                   (match_operand:DI 2 "nonmemory_operand" "")))]
 774   ""
 775 {
 776   rtx op0l, op0h, op1l, op1h, op2l, op2h;
 777
 778   op0l = gen_lowpart (SImode, operands[0]);
 779   op1l = gen_lowpart (SImode, operands[1]);
 780   op2l = gen_lowpart (SImode, operands[2]);
 781   op0h = gen_highpart (SImode, operands[0]);
 782   op1h = gen_highpart (SImode, operands[1]);
 783   op2h = gen_highpart_mode (SImode, DImode, operands[2]);
 784
 785   if (!reg_or_am33_const_operand (op2h, SImode))
 786     op2h = force_reg (SImode, op2h);
 787
 788   emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op1h, op2l, op2h));
 789   DONE;
 790 })
 791
 792 ;; As with adddi3, the use of the scratch register helps reduce the
 793 ;; number of permutations for AM33.
 794 ;; ??? The early clobber on op0 avoids a reload bug wherein both output
 795 ;; registers are set the same.  Consider negate, where both op2 and op3
 796 ;; are 0, are csed to the same input register, and reload fails to undo
 797 ;; the cse when satisfying the matching constraints.
 798
 799 (define_insn_and_split "subdi3_internal"
 800   [(set (match_operand:SI     0 "register_operand"         "=&r, r")
 801         (minus:SI
 802           (match_operand:SI   2 "register_operand"         "  0, r")
 803           (match_operand:SI   4 "nonmemory_operand"        " ri,ri")))
 804    (set (match_operand:SI     1 "register_operand"         "=D , r")
 805         (minus:SI
 806           (minus:SI
 807             (match_operand:SI 3 "register_operand"         "  1, r")
 808             (match_operand:SI 5 "reg_or_am33_const_operand" " D,ri"))
 809           (ltu:SI (match_dup 2) (match_dup 4))))
 810    (clobber (match_scratch:SI 6                            "=X ,&r"))
 811    (clobber (reg:CC CC_REG))]
 812   ""
 813   "#"
 814   "reload_completed"
 815   [(const_int 0)]
 816 {
 817   rtx op0l = operands[0];
 818   rtx op0h = operands[1];
 819   rtx op1l = operands[2];
 820   rtx op1h = operands[3];
 821   rtx op2l = operands[4];
 822   rtx op2h = operands[5];
 823   rtx scratch = operands[6];
 824
 825   if (reg_overlap_mentioned_p (op0l, op1h))
 826     {
 827       emit_move_insn (scratch, op0l);
 828       op1h = scratch;
 829       if (reg_overlap_mentioned_p (op0l, op2h))
 830         op2h = scratch;
 831     }
 832   else if (reg_overlap_mentioned_p (op0l, op2h))
 833     {
 834       emit_move_insn (scratch, op0l);
 835       op2h = scratch;
 836     }
 837
 838   if (!rtx_equal_p (op0l, op1l))
 839     {
 840       gcc_assert (TARGET_AM33);
 841       if (!REG_P (op2l))
 842         {
 843           emit_move_insn (op0l, op1l);
 844           op1l = op0l;
 845         }
 846     }
 847   emit_insn (gen_subsi3_flags (op0l, op1l, op2l));
 848
 849   if (!rtx_equal_p (op0h, op1h))
 850     {
 851       gcc_assert (TARGET_AM33);
 852       if (!REG_P (op2h))
 853         {
 854           emit_move_insn (op0h, op1h);
 855           op1h = op0h;
 856         }
 857     }
 858   emit_insn (gen_subc_internal (op0h, op1h, op2h));
 859   DONE;
 860 }
 861   [(set_attr "isa" "*,am33")]
 862 )
 863
 864 ;; The following pattern is generated by combine when it proves that one
 865 ;; of the inputs to the low-part of the double-word sub is zero, and thus
 866 ;; no carry is generated into the high-part.
 867
 868 (define_insn_and_split "*subdi3_degenerate"
 869   [(set (match_operand:SI          0 "register_operand"   "=&r,&r")
 870         (match_operand:SI          2 "nonmemory_operand"  "  0, 0"))
 871    (set (match_operand:SI          1 "register_operand"   "=r , r")
 872         (minus:SI (match_operand:SI 3 "register_operand"  "  1, r")
 873                   (match_operand:SI 4 "nonmemory_operand" " ri, r")))
 874    (clobber (reg:CC CC_REG))]
 875   ""
 876   "#"
 877   ""
 878   [(const_int 0)]
 879 {
 880   rtx scratch = NULL_RTX;
 881   if (!rtx_equal_p (operands[0], operands[2]))
 882     {
 883       gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1]));
 884       if (reg_overlap_mentioned_p (operands[0], operands[3])
 885           || reg_overlap_mentioned_p (operands[0], operands[4]))
 886         {
 887           scratch = gen_reg_rtx (SImode);
 888           emit_move_insn (scratch, operands[2]);
 889         }
 890       else
 891         emit_move_insn (operands[0], operands[2]);
 892     }
 893   emit_insn (gen_subsi3 (operands[1], operands[3], operands[4]));
 894   if (scratch)
 895     emit_move_insn (operands[0], scratch);
 896   DONE;
 897 })
 898
 899 (define_insn_and_split "negsi2"
 900   [(set (match_operand:SI         0 "register_operand"  "=D,&r")
 901         (neg:SI (match_operand:SI 1 "register_operand"  " 0, r")))
 902    (clobber (reg:CC CC_REG))]
 903   ""
 904   "#"
 905   "&& reload_completed"
 906   [(const_int 0)]
 907 {
 908   /* Recall that twos-compliment is ones-compliment plus one.  When
 909      allocated in DATA_REGS this is 2+1 bytes; otherwise (for am33)
 910      this is 3+3 bytes.
 911
 912      For AM33, it would have been possible to load zero and use the
 913      three-address subtract to have a total size of 3+4*N bytes for
 914      multiple negations, plus increased throughput.  Not attempted here.  */
 915
 916   if (true_regnum (operands[0]) == true_regnum (operands[1]))
 917     {
 918       emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
 919       emit_insn (gen_addsi3 (operands[0], operands[0], const1_rtx));
 920     }
 921   else
 922     {
 923       emit_move_insn (operands[0], const0_rtx);
 924       emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
 925     }
 926   DONE;
 927 })
 928
 929 ;; ----------------------------------------------------------------------
 930 ;; MULTIPLY INSTRUCTIONS
 931 ;; ----------------------------------------------------------------------
 932
 933 ;; ??? Note that AM33 has a third multiply variant that puts the high part
 934 ;; into the MDRQ register, however this variant also constrains the inputs
 935 ;; to be in DATA_REGS and thus isn't as helpful as it might be considering
 936 ;; the existance of the 4-operand multiply.  Nor is there a set of divide
 937 ;; insns that use MDRQ.  Given that there is an IMM->MDRQ insn, this would
 938 ;; have been very handy for starting udivmodsi4...
 939
 940 (define_expand "mulsidi3"
 941   [(set (match_operand:DI 0 "register_operand" "")
 942         (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
 943                  (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
 944   ""
 945 {
 946   emit_insn (gen_mulsidi3_internal (gen_lowpart (SImode, operands[0]),
 947                                     gen_highpart (SImode, operands[0]),
 948                                     operands[1], operands[2]));
 949   DONE;
 950 })
 951
 952 (define_insn "mulsidi3_internal"
 953   [(set (match_operand:SI          0 "register_operand" "=D,r")
 954         (mult:SI (match_operand:SI 2 "register_operand" "%0,r")
 955                  (match_operand:SI 3 "register_operand" " D,r")))
 956    (set (match_operand:SI          1 "register_operand" "=z,r")
 957         (truncate:SI
 958           (ashiftrt:DI
 959             (mult:DI (sign_extend:DI (match_dup 2))
 960                      (sign_extend:DI (match_dup 3)))
 961             (const_int 32))))
 962    (clobber (reg:CC CC_REG))]
 963   ""
 964 {
 965   if (which_alternative == 1)
 966     return "mul %2,%3,%1,%0";
 967   else if (TARGET_MULT_BUG)
 968     return "nop\;nop\;mul %3,%0";
 969   else
 970     return "mul %3,%0";
 971 }
 972   [(set_attr "isa" "*,am33")
 973    (set (attr "timings")
 974         (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
 975 )
 976
 977 (define_expand "umulsidi3"
 978   [(set (match_operand:DI 0 "register_operand" "")
 979         (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
 980                  (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
 981    (clobber (reg:CC CC_REG))]
 982   ""
 983 {
 984   emit_insn (gen_umulsidi3_internal (gen_lowpart (SImode, operands[0]),
 985                                      gen_highpart (SImode, operands[0]),
 986                                      operands[1], operands[2]));
 987   DONE;
 988 })
 989
 990 (define_insn "umulsidi3_internal"
 991   [(set (match_operand:SI          0 "register_operand" "=D,r")
 992         (mult:SI (match_operand:SI 2 "register_operand" "%0,r")
 993                  (match_operand:SI 3 "register_operand" " D,r")))
 994    (set (match_operand:SI          1 "register_operand" "=z,r")
 995         (truncate:SI
 996           (lshiftrt:DI
 997             (mult:DI (zero_extend:DI (match_dup 2))
 998                      (zero_extend:DI (match_dup 3)))
 999             (const_int 32))))
1000    (clobber (reg:CC CC_REG))]
1001   ""
1002 {
1003   if (which_alternative == 1)
1004     return "mulu %2,%3,%1,%0";
1005   else if (TARGET_MULT_BUG)
1006     return "nop\;nop\;mulu %3,%0";
1007   else
1008     return "mulu %3,%0";
1009 }
1010   [(set_attr "isa" "*,am33")
1011    (set (attr "timings")
1012         (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1013 )
1014
1015 (define_expand "mulsi3"
1016   [(parallel [(set (match_operand:SI          0 "register_operand"  "")
1017                    (mult:SI (match_operand:SI 1 "register_operand"  "")
1018                             (match_operand:SI 2 "nonmemory_operand" "")))
1019               (clobber (match_scratch:SI      3 ""))
1020               (clobber (reg:CC CC_REG))])]
1021   ""
1022 )
1023
1024 (define_insn "*mulsi3"
1025   [(set (match_operand:SI          0 "register_operand"  "=D, r,r")
1026         (mult:SI (match_operand:SI 2 "register_operand"  "%0, 0,r")
1027                  (match_operand:SI 3 "nonmemory_operand" " D,ri,r")))
1028    (clobber (match_scratch:SI      1                     "=z, z,r"))
1029    (clobber (reg:CC CC_REG))]
1030   ""
1031 {
1032   if (which_alternative == 2)
1033     return "mul %2,%3,%1,%0";
1034   else if (TARGET_MULT_BUG)
1035     return "nop\;nop\;mul %3,%0";
1036   else
1037     return "mul %3,%0";
1038 }
1039   [(set_attr "isa" "*,am33,am33")
1040    (set (attr "timings")
1041         (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1042 )
1043
1044 (define_expand "udivmodsi4"
1045   [(parallel [(set (match_operand:SI          0 "register_operand")
1046                    (udiv:SI (match_operand:SI 1 "register_operand")
1047                             (match_operand:SI 2 "register_operand")))
1048               (set (match_operand:SI          3 "register_operand")
1049                    (umod:SI (match_dup 1) (match_dup 2)))
1050               (use (const_int 0))
1051               (clobber (reg:CC CC_REG))])]
1052   ""
1053 )
1054
1055 ;; Note the trick to get reload to put the zero into the MDR register,
1056 ;; rather than exposing the load early and letting CSE or someone try
1057 ;; to share the zeros between division insns.  Which tends to result
1058 ;; in sequences like 0->r0->d0->mdr.
1059
1060 (define_insn "*udivmodsi4"
1061   [(set (match_operand:SI          0 "register_operand" "=D")
1062         (udiv:SI (match_operand:SI 2 "register_operand" " 0")
1063                  (match_operand:SI 3 "register_operand" " D")))
1064    (set (match_operand:SI          1 "register_operand" "=z")
1065         (umod:SI (match_dup 2) (match_dup 3)))
1066    (use (match_operand:SI          4 "nonmemory_operand" " 1"))
1067    (clobber (reg:CC CC_REG))]
1068   ""
1069   "divu %3,%0"
1070   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1071                                        (const_int 3839) (const_int 4243)))]
1072 )
1073
1074 (define_expand "divmodsi4"
1075   [(parallel [(set (match_operand:SI          0 "register_operand" "")
1076                    (div:SI (match_operand:SI  1 "register_operand" "")
1077                            (match_operand:SI  2 "register_operand" "")))
1078               (set (match_operand:SI          3 "register_operand" "")
1079                    (mod:SI (match_dup 1) (match_dup 2)))
1080               (use (match_dup 4))
1081               (clobber (reg:CC CC_REG))])]
1082   ""
1083 {
1084   operands[4] = gen_reg_rtx (SImode);
1085   emit_insn (gen_ext_internal (operands[4], operands[1]));
1086 })
1087
1088 ;; ??? Ideally we'd represent this via shift, but it seems like adding a
1089 ;; special-case pattern for (ashiftrt x 31) is just as likely to result
1090 ;; in poor register allocation choices.
1091 (define_insn "ext_internal"
1092   [(set (match_operand:SI 0 "register_operand" "=z")
1093         (unspec:SI [(match_operand:SI 1 "register_operand" "D")] UNSPEC_EXT))]
1094   ""
1095   "ext %1"
1096 )
1097
1098 (define_insn "*divmodsi4"
1099   [(set (match_operand:SI          0 "register_operand" "=D")
1100         (div:SI (match_operand:SI  2 "register_operand" " 0")
1101                 (match_operand:SI  3 "register_operand" " D")))
1102    (set (match_operand:SI          1 "register_operand" "=z")
1103         (mod:SI (match_dup 2) (match_dup 3)))
1104    (use (match_operand:SI          4 "register_operand" " 1"))
1105    (clobber (reg:CC CC_REG))]
1106   ""
1107   "div %3,%0";
1108   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1109                                        (const_int 3839) (const_int 4243)))]
1110 )
1111
1112 \f
1113 ;; ----------------------------------------------------------------------
1114 ;; AND INSTRUCTIONS
1115 ;; ----------------------------------------------------------------------
1116
1117 (define_insn "andsi3"
1118   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
1119         (and:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
1120                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1121    (clobber (reg:CC CC_REG))]
1122   ""
1123   "@
1124    and %2,%0
1125    and %2,%0
1126    and %2,%1,%0"
1127   [(set_attr "isa" "*,*,am33")
1128    (set_attr "timings" "22,11,11")]
1129 )
1130
1131 (define_insn "*andsi3_flags"
1132   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
1133         (and:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
1134                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1135    (set (reg CC_REG)
1136         (compare (and:SI (match_dup 1) (match_dup 2))
1137                  (const_int 0)))]
1138   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1139   "@
1140    and %2,%0
1141    and %2,%0
1142    and %2,%1,%0"
1143   [(set_attr "isa" "*,*,am33")
1144    (set_attr "timings" "22,11,11")]
1145 )
1146
1147 ;; Make sure we generate extensions instead of ANDs.
1148
1149 (define_split
1150   [(parallel [(set (match_operand:SI 0 "register_operand" "")
1151                    (and:SI (match_operand:SI 1 "register_operand" "")
1152                            (const_int 255)))
1153               (clobber (reg:CC CC_REG))])]
1154   ""
1155   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
1156   { operands[1] = gen_lowpart (QImode, operands[1]); }
1157 )
1158
1159 (define_split
1160   [(parallel [(set (match_operand:SI 0 "register_operand" "")
1161                    (and:SI (match_operand:SI 1 "register_operand" "")
1162                            (const_int 65535)))
1163               (clobber (reg:CC CC_REG))])]
1164   ""
1165   [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
1166   { operands[1] = gen_lowpart (HImode, operands[1]); }
1167 )
1168
1169 ;; Split AND by an appropriate constant into two shifts.  Recall that
1170 ;; operations with a full 32-bit immediate require an extra cycle, so
1171 ;; this is a size optimization with no speed penalty.  This only applies
1172 ;; do DATA_REGS; the shift insns that AM33 adds are too large for a win.
1173
1174 (define_split
1175   [(parallel [(set (match_operand:SI 0 "register_operand" "")
1176                    (and:SI (match_dup 0)
1177                            (match_operand:SI 1 "const_int_operand" "")))
1178               (clobber (reg:CC CC_REG))])]
1179   "reload_completed
1180    && REGNO_DATA_P (true_regnum (operands[0]), 1)
1181    && mn10300_split_and_operand_count (operands[1]) != 0"
1182   [(const_int 0)]
1183 {
1184   int count = mn10300_split_and_operand_count (operands[1]);
1185   if (count > 0)
1186     {
1187       emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (count)));
1188       emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (count)));
1189     }
1190   else
1191     {
1192       emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (-count)));
1193       emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (-count)));
1194     }
1195   DONE;
1196 })
1197
1198 ;; ----------------------------------------------------------------------
1199 ;; OR INSTRUCTIONS
1200 ;; ----------------------------------------------------------------------
1201
1202 (define_insn "iorsi3"
1203   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
1204         (ior:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
1205                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1206    (clobber (reg:CC CC_REG))]
1207   ""
1208   "@
1209    or %2,%0
1210    or %2,%0
1211    or %2,%1,%0"
1212   [(set_attr "isa" "*,*,am33")
1213    (set_attr "timings" "22,11,11")]
1214 )
1215
1216 (define_insn "*iorsi3_flags"
1217   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
1218         (ior:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
1219                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1220    (set (reg CC_REG)
1221         (compare (ior:SI (match_dup 1) (match_dup 2))
1222                  (const_int 0)))]
1223   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1224   "@
1225    or %2,%0
1226    or %2,%0
1227    or %2,%1,%0"
1228   [(set_attr "isa" "*,*,am33")
1229    (set_attr "timings" "22,11,11")]
1230 )
1231
1232 ;; ----------------------------------------------------------------------
1233 ;; XOR INSTRUCTIONS
1234 ;; ----------------------------------------------------------------------
1235
1236 (define_insn "xorsi3"
1237   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
1238         (xor:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
1239                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1240    (clobber (reg:CC CC_REG))]
1241   ""
1242   "@
1243    xor %2,%0
1244    xor %2,%0
1245    xor %2,%1,%0"
1246   [(set_attr "isa" "*,*,am33")
1247    (set_attr "timings" "22,11,11")]
1248 )
1249
1250 (define_insn "*xorsi3_flags"
1251   [(set (match_operand:SI         0 "register_operand"  "=D,D,r")
1252         (xor:SI (match_operand:SI 1 "register_operand"  "%0,0,r")
1253                 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1254    (set (reg CC_REG)
1255         (compare (xor:SI (match_dup 1) (match_dup 2))
1256                  (const_int 0)))]
1257   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1258   "@
1259    xor %2,%0
1260    xor %2,%0
1261    xor %2,%1,%0"
1262   [(set_attr "isa" "*,*,am33")
1263    (set_attr "timings" "22,11,11")]
1264 )
1265
1266 ;; ----------------------------------------------------------------------
1267 ;; NOT INSTRUCTIONS
1268 ;; ----------------------------------------------------------------------
1269
1270 (define_insn "one_cmplsi2"
1271   [(set (match_operand:SI         0 "register_operand" "=D")
1272         (not:SI (match_operand:SI 1 "register_operand" " 0")))
1273    (clobber (reg:CC CC_REG))]
1274   ""
1275   "not %0"
1276 )
1277
1278 (define_insn "*one_cmplsi2_flags"
1279   [(set (match_operand:SI         0 "register_operand" "=D")
1280         (not:SI (match_operand:SI 1 "register_operand" " 0")))
1281    (set (reg CC_REG)
1282         (compare (not:SI (match_dup 1))
1283                  (const_int 0)))]
1284   "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1285   "not %0"
1286 )
1287 \f
1288 ;; ----------------------------------------------------------------------
1289 ;; COMPARE AND BRANCH INSTRUCTIONS
1290 ;; ----------------------------------------------------------------------
1291
1292 ;; We expand the comparison into a single insn so that it will not be split
1293 ;; up by reload.
1294 (define_expand "cbranchsi4"
1295   [(set (pc)
1296         (if_then_else
1297               (match_operator                    0 "ordered_comparison_operator"
1298                               [(match_operand:SI 1 "register_operand")
1299                                (match_operand:SI 2 "nonmemory_operand")])
1300               (label_ref (match_operand 3 ""))
1301               (pc)))]
1302   ""
1303   ""
1304 )
1305
1306 (define_insn_and_split "*cbranchsi4_cmp"
1307   [(set (pc)
1308         (if_then_else (match_operator           3 "ordered_comparison_operator"
1309                        [(match_operand:SI       0 "register_operand"  "r")
1310                         (match_operand:SI       1 "nonmemory_operand" "ri")])
1311                       (match_operand            2 "label_ref_operand" "")
1312                       (pc)))]
1313   ""
1314   "#"
1315   "reload_completed"
1316   [(const_int 0)]
1317 {
1318   mn10300_split_cbranch (CCmode, operands[3], operands[2]);
1319   DONE;
1320 })
1321
1322 (define_insn "*cmpsi"
1323   [(set (reg CC_REG)
1324         (compare (match_operand:SI 0 "register_operand"  "r")
1325                  (match_operand:SI 1 "nonmemory_operand" "ri")))]
1326   "reload_completed"
1327 {
1328   /* The operands of CMP must be distinct registers.  In the case where
1329      we've failed to optimize the comparison of a register to itself, we
1330      must use another method to set the Z flag.  We can achieve this
1331      effect with a BTST 0,D0.  This will not alter the contents of D0;
1332      the use of d0 is arbitrary; any data register would work.  */
1333   if (rtx_equal_p (operands[0], operands[1]))
1334     return "btst 0,d0";
1335   else
1336     return "cmp %1,%0";
1337 }
1338   [(set_attr_alternative "timings"
1339      [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))])]
1340 )
1341
1342 (define_insn "*integer_conditional_branch"
1343   [(set (pc)
1344         (if_then_else (match_operator 0 "comparison_operator"
1345                         [(match_operand 2 "int_mode_flags" "")
1346                          (const_int 0)])
1347                       (label_ref (match_operand 1 "" ""))
1348                       (pc)))]
1349   "reload_completed"
1350   "b%b0 %1"
1351 )
1352
1353 (define_insn_and_split "*cbranchsi4_btst"
1354   [(set (pc)
1355         (if_then_else
1356           (match_operator 3 "CCZN_comparison_operator"
1357             [(and:SI (match_operand:SI 0 "register_operand" "D")
1358                      (match_operand:SI 1 "immediate_operand" "i"))
1359              (const_int 0)])
1360           (match_operand 2 "label_ref_operand" "")
1361           (pc)))]
1362   ""
1363   "#"
1364   "reload_completed"
1365   [(const_int 0)]
1366 {
1367   mn10300_split_cbranch (CCZNmode, operands[3], operands[2]);
1368   DONE;
1369 })
1370
1371 (define_insn "*btstsi"
1372   [(set (reg:CCZN CC_REG)
1373         (compare:CCZN
1374           (and:SI (match_operand:SI 0 "register_operand" "D")
1375                   (match_operand:SI 1 "immediate_operand" "i"))
1376           (const_int 0)))]
1377   "reload_completed"
1378   "btst %1,%0"
1379 )
1380
1381 (define_expand "cbranchsf4"
1382   [(set (pc)
1383       (if_then_else
1384             (match_operator                    0 "ordered_comparison_operator"
1385                             [(match_operand:SF 1 "register_operand")
1386                              (match_operand:SF 2 "nonmemory_operand")])
1387             (label_ref (match_operand 3 ""))
1388             (pc)))]
1389   "TARGET_AM33_2"
1390   ""
1391 )
1392
1393 (define_insn_and_split "*cbranchsf4_cmp"
1394   [(set (pc)
1395         (if_then_else (match_operator            3 "ordered_comparison_operator"
1396                         [(match_operand:SF       0 "register_operand"  "f")
1397                          (match_operand:SF       1 "nonmemory_operand" "fF")])
1398                       (match_operand             2 "label_ref_operand" "")
1399                       (pc)))
1400    ]
1401   "TARGET_AM33_2"
1402   "#"
1403   "&& reload_completed"
1404   [(const_int 0)]
1405 {
1406   mn10300_split_cbranch (CC_FLOATmode, operands[3], operands[2]);
1407   DONE;
1408 })
1409
1410 (define_insn "*am33_cmpsf"
1411   [(set (reg:CC_FLOAT CC_REG)
1412         (compare:CC_FLOAT (match_operand:SF 0 "register_operand"  "f")
1413                           (match_operand:SF 1 "nonmemory_operand" "fF")))]
1414   "TARGET_AM33_2 && reload_completed"
1415   "fcmp %1, %0"
1416   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1417                                        (const_int 17) (const_int 25)))]
1418 )
1419
1420 (define_insn "*float_conditional_branch"
1421   [(set (pc)
1422         (if_then_else (match_operator 0 "comparison_operator"
1423                                       [(reg:CC_FLOAT CC_REG) (const_int 0)])
1424                       (label_ref (match_operand 1 "" ""))
1425                       (pc)))]
1426   "TARGET_AM33_2 && reload_completed"
1427   "fb%b0 %1"
1428   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1429                                        (const_int 44) (const_int 33)))]
1430 )
1431
1432 ;; Unconditional and other jump instructions.
1433
1434 (define_insn "jump"
1435   [(set (pc)
1436         (label_ref (match_operand 0 "" "")))]
1437   ""
1438   "jmp %l0"
1439   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1440                                        (const_int 11) (const_int 44)))]
1441 )
1442
1443 (define_insn "indirect_jump"
1444   [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1445   ""
1446   "jmp (%0)"
1447   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1448                                        (const_int 11) (const_int 33)))]
1449 )
1450
1451 (define_expand "builtin_setjmp_receiver"
1452   [(match_operand 0 "" "")]
1453   "flag_pic"
1454 {
1455   emit_insn (gen_load_pic ());
1456   DONE;
1457 })
1458
1459 (define_expand "casesi"
1460   [(match_operand:SI 0 "register_operand")
1461    (match_operand:SI 1 "immediate_operand")
1462    (match_operand:SI 2 "immediate_operand")
1463    (match_operand 3 "" "") (match_operand 4 "")]
1464   ""
1465 {
1466   rtx table = gen_reg_rtx (SImode);
1467   rtx index = gen_reg_rtx (SImode);
1468   rtx addr = gen_reg_rtx (Pmode);
1469   rtx test;
1470
1471   emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
1472   emit_insn (gen_addsi3 (index, operands[0], GEN_INT (- INTVAL (operands[1]))));
1473   test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]);
1474   emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4]));
1475
1476   emit_insn (gen_ashlsi3 (index, index, const2_rtx));
1477   emit_move_insn (addr, gen_rtx_MEM (SImode,
1478                                      gen_rtx_PLUS (SImode, table, index)));
1479   if (flag_pic)
1480     emit_insn (gen_addsi3 (addr, addr, table));
1481
1482   emit_jump_insn (gen_tablejump (addr, operands[3]));
1483   DONE;
1484 })
1485
1486 (define_insn "tablejump"
1487   [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1488    (use (label_ref (match_operand 1 "" "")))]
1489   ""
1490   "jmp (%0)"
1491   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1492                                        (const_int 11) (const_int 33)))]
1493 )
1494
1495 ;; Call subroutine with no return value.
1496
1497 (define_expand "call"
1498   [(call (match_operand:QI 0 "general_operand")
1499          (match_operand:SI 1 "general_operand"))]
1500   ""
1501 {
1502   rtx fn = XEXP (operands[0], 0);
1503
1504   if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
1505     {
1506       if (MN10300_GLOBAL_P (fn))
1507         {
1508           /* The PLT code won't run on AM30, but then, there's no
1509              shared library support for AM30 either, so we just assume
1510              the linker is going to adjust all @PLT relocs to the
1511              actual symbols.  */
1512           emit_use (pic_offset_table_rtx);
1513           fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
1514         }
1515       else
1516         fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
1517     }
1518   if (! call_address_operand (fn, VOIDmode))
1519     fn = force_reg (SImode, fn);
1520
1521   XEXP (operands[0], 0) = fn;
1522 })
1523
1524 (define_insn "*call_internal"
1525   [(call (mem:QI (match_operand:SI 0 "call_address_operand" "a,S"))
1526          (match_operand:SI 1 "" ""))]
1527   ""
1528   "@
1529    calls %C0
1530    call %C0,[],0"
1531   [(set_attr_alternative "timings"
1532                          [(if_then_else (eq_attr "cpu" "am34")
1533                                         (const_int 33) (const_int 44))
1534                           (if_then_else (eq_attr "cpu" "am34")
1535                                         (const_int 55) (const_int 33))
1536                          ])
1537   ]
1538 )
1539
1540 ;; Call subroutine, returning value in operand 0
1541 ;; (which must be a hard register).
1542
1543 (define_expand "call_value"
1544   [(set (match_operand 0 "")
1545         (call (match_operand:QI 1 "general_operand")
1546               (match_operand:SI 2 "general_operand")))]
1547   ""
1548 {
1549   rtx fn = XEXP (operands[1], 0);
1550
1551   if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
1552     {
1553       if (MN10300_GLOBAL_P (fn))
1554         {
1555           /* The PLT code won't run on AM30, but then, there's no
1556              shared library support for AM30 either, so we just assume
1557              the linker is going to adjust all @PLT relocs to the
1558              actual symbols.  */
1559           emit_use (pic_offset_table_rtx);
1560           fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
1561         }
1562       else
1563         fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
1564     }
1565   if (! call_address_operand (fn, VOIDmode))
1566     fn = force_reg (SImode, fn);
1567
1568   XEXP (operands[1], 0) = fn;
1569 })
1570
1571 (define_insn "call_value_internal"
1572   [(set (match_operand 0 "" "")
1573         (call (mem:QI (match_operand:SI 1 "call_address_operand" "a,S"))
1574               (match_operand:SI 2 "" "")))]
1575   ""
1576   "@
1577    calls %C1
1578    call %C1,[],0"
1579   [(set_attr_alternative "timings"
1580                          [(if_then_else (eq_attr "cpu" "am34")
1581                                         (const_int 33) (const_int 44))
1582                           (if_then_else (eq_attr "cpu" "am34")
1583                                         (const_int 55) (const_int 33))
1584                          ])
1585   ]
1586 )
1587
1588 (define_expand "untyped_call"
1589   [(parallel [(call (match_operand 0 "")
1590                     (const_int 0))
1591               (match_operand 1 "")
1592               (match_operand 2 "")])]
1593   ""
1594 {
1595   int i;
1596
1597   emit_call_insn (gen_call (operands[0], const0_rtx));
1598
1599   for (i = 0; i < XVECLEN (operands[2], 0); i++)
1600     {
1601       rtx set = XVECEXP (operands[2], 0, i);
1602       emit_move_insn (SET_DEST (set), SET_SRC (set));
1603     }
1604   DONE;
1605 })
1606
1607 (define_insn "nop"
1608   [(const_int 0)]
1609   ""
1610   "nop"
1611 )
1612 \f
1613 ;; ----------------------------------------------------------------------
1614 ;; EXTEND INSTRUCTIONS
1615 ;; ----------------------------------------------------------------------
1616
1617 (define_insn "zero_extendqisi2"
1618   [(set (match_operand:SI 0 "register_operand"      "=D,D,r")
1619         (zero_extend:SI
1620          (match_operand:QI 1 "nonimmediate_operand" " 0,m,r")))]
1621   ""
1622   "@
1623    extbu %0
1624    movbu %1,%0
1625    extbu %1,%0"
1626   [(set_attr "isa" "*,*,am33")
1627    (set_attr_alternative "timings"
1628                  [(const_int 11)
1629                   (if_then_else (eq_attr "cpu" "am34")
1630                                 (const_int 13) (const_int 24))
1631                   (const_int 11)
1632                  ])]
1633 )
1634
1635 (define_insn "zero_extendhisi2"
1636   [(set (match_operand:SI 0 "register_operand"      "=D,D,r")
1637         (zero_extend:SI
1638          (match_operand:HI 1 "nonimmediate_operand" " 0,m,r")))]
1639   ""
1640   "@
1641    exthu %0
1642    movhu %1,%0
1643    exthu %1,%0"
1644   [(set_attr "isa" "*,*,am33")
1645    (set_attr_alternative "timings"
1646                  [(const_int 11)
1647                   (if_then_else (eq_attr "cpu" "am34")
1648                                 (const_int 13) (const_int 24))
1649                   (const_int 11)])]
1650 )
1651
1652 (define_insn "extendqisi2"
1653   [(set (match_operand:SI 0 "register_operand" "=D,r")
1654         (sign_extend:SI
1655          (match_operand:QI 1 "register_operand" "0,r")))]
1656   ""
1657   "@
1658    extb %0
1659    extb %1,%0"
1660   [(set_attr "isa" "*,am33")]
1661 )
1662
1663 (define_insn "extendhisi2"
1664   [(set (match_operand:SI 0 "register_operand" "=D,r")
1665         (sign_extend:SI
1666          (match_operand:HI 1 "register_operand" "0,r")))]
1667   ""
1668   "@
1669    exth %0
1670    exth %1,%0"
1671   [(set_attr "isa" "*,am33")]
1672 )
1673 \f
1674 ;; ----------------------------------------------------------------------
1675 ;; SHIFTS
1676 ;; ----------------------------------------------------------------------
1677
1678 (define_insn "ashlsi3"
1679   [(set (match_operand:SI  0 "register_operand"  "=r,D,d,d, D,r")
1680         (ashift:SI
1681           (match_operand:SI 1 "register_operand"  " 0,0,0,0, 0,r")
1682           (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,Di,r")))
1683    (clobber (reg:CC CC_REG))]
1684   ""
1685   "@
1686    add %0,%0
1687    asl2 %0
1688    asl2 %0\;add %0,%0
1689    asl2 %0\;asl2 %0
1690    asl %S2,%0
1691    asl %2,%1,%0"
1692   [(set_attr "isa" "*,*,*,*,*,am33")
1693    (set_attr "timings" "11,11,22,22,11,11")]
1694 )
1695
1696 (define_insn "lshrsi3"
1697   [(set (match_operand:SI  0 "register_operand"  "=D,r")
1698         (lshiftrt:SI
1699           (match_operand:SI 1 "register_operand"  " 0,r")
1700           (match_operand:QI 2 "nonmemory_operand" "Di,r")))
1701    (clobber (reg:CC CC_REG))]
1702   ""
1703   "@
1704    lsr %S2,%0
1705    lsr %2,%1,%0"
1706   [(set_attr "isa" "*,am33")]
1707 )
1708
1709 (define_insn "ashrsi3"
1710   [(set (match_operand:SI  0 "register_operand"  "=D,r")
1711         (ashiftrt:SI
1712           (match_operand:SI 1 "register_operand"  " 0,r")
1713           (match_operand:QI 2 "nonmemory_operand" "Di,r")))
1714    (clobber (reg:CC CC_REG))]
1715   ""
1716   "@
1717    asr %S2,%0
1718    asr %2,%1,%0"
1719   [(set_attr "isa" "*,am33")]
1720 )
1721
1722 ;; ----------------------------------------------------------------------
1723 ;; MISCELANEOUS
1724 ;; ----------------------------------------------------------------------
1725
1726 (define_expand "clzsi2"
1727   [(parallel [(set (match_operand:SI 0 "register_operand" "")
1728                    (unspec:SI [(match_operand:SI 1 "register_operand" "")
1729                                (const_int 0)] UNSPEC_BSCH))
1730               (clobber (reg:CC CC_REG))])]
1731   "TARGET_AM33"
1732 )
1733
1734 (define_insn "*bsch"
1735   [(set (match_operand:SI 0 "register_operand" "=r")
1736         (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1737                     (match_operand:SI 2 "nonmemory_operand" "0")]
1738                    UNSPEC_BSCH))
1739    (clobber (reg:CC CC_REG))]
1740   "TARGET_AM33"
1741   "bsch %1,%0"
1742 )
1743
1744 ;; ----------------------------------------------------------------------
1745 ;; FP INSTRUCTIONS
1746 ;; ----------------------------------------------------------------------
1747
1748 (define_insn "abssf2"
1749   [(set (match_operand:SF         0 "register_operand" "=f,f")
1750         (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
1751   "TARGET_AM33_2"
1752   "@
1753    fabs %0
1754    fabs %1, %0"
1755   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1756                                        (const_int 17) (const_int 14)))]
1757 )
1758
1759 (define_insn "negsf2"
1760   [(set (match_operand:SF         0 "register_operand" "=f,f")
1761         (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
1762   "TARGET_AM33_2"
1763   "@
1764    fneg %0
1765    fneg %1, %0"
1766   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1767                                        (const_int 17) (const_int 14)))]
1768 )
1769
1770 (define_expand "sqrtsf2"
1771   [(set (match_operand:SF 0 "register_operand" "")
1772         (sqrt:SF (match_operand:SF 1 "register_operand" "")))]
1773   "TARGET_AM33_2 && flag_unsafe_math_optimizations"
1774 {
1775   rtx scratch = gen_reg_rtx (SFmode);
1776   emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
1777   emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
1778                          scratch));
1779   DONE;
1780 })
1781
1782 (define_insn "rsqrtsf2"
1783   [(set (match_operand:SF                  0 "register_operand" "=f,f")
1784         (div:SF (match_operand:SF          2 "const_1f_operand" "F,F")
1785                 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))
1786    (clobber (reg:CC_FLOAT CC_REG))]
1787   "TARGET_AM33_2"
1788   "@
1789    frsqrt %0
1790    frsqrt %1, %0"
1791   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1792                                        (const_int 4753) (const_int 2327)))]
1793 )
1794
1795 (define_insn "addsf3"
1796   [(set (match_operand:SF          0 "register_operand" "=f,f")
1797         (plus:SF (match_operand:SF 1 "register_operand" "%0,f")
1798                  (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1799    (clobber (reg:CC_FLOAT CC_REG))]
1800   "TARGET_AM33_2"
1801   "@
1802    fadd %2, %0
1803    fadd %2, %1, %0"
1804   [(set_attr_alternative "timings"
1805                          [(if_then_else (eq_attr "cpu" "am34")
1806                                         (const_int 17) (const_int 14))
1807                           (if_then_else (eq_attr "cpu" "am34")
1808                                         (const_int 17) (const_int 25))
1809                          ])]
1810 )
1811
1812 (define_insn "subsf3"
1813   [(set (match_operand:SF           0 "register_operand" "=f,f")
1814         (minus:SF (match_operand:SF 1 "register_operand" "0,f")
1815                   (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1816    (clobber (reg:CC_FLOAT CC_REG))]
1817   "TARGET_AM33_2"
1818   "@
1819    fsub %2, %0
1820    fsub %2, %1, %0"
1821   [(set_attr_alternative "timings"
1822                          [(if_then_else (eq_attr "cpu" "am34")
1823                                         (const_int 17) (const_int 14))
1824                           (if_then_else (eq_attr "cpu" "am34")
1825                                         (const_int 17) (const_int 25))
1826                          ])]
1827 )
1828
1829 (define_insn "mulsf3"
1830   [(set (match_operand:SF          0 "register_operand" "=f,f")
1831         (mult:SF (match_operand:SF 1 "register_operand" "%0,f")
1832                  (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1833   (clobber (reg:CC_FLOAT CC_REG))
1834   ]
1835   "TARGET_AM33_2"
1836   "@
1837    fmul %2, %0
1838    fmul %2, %1, %0"
1839   [(set_attr_alternative "timings"
1840                          [(if_then_else (eq_attr "cpu" "am34")
1841                                         (const_int 17) (const_int 14))
1842                           (if_then_else (eq_attr "cpu" "am34")
1843                                         (const_int 17) (const_int 25))
1844                          ])]
1845 )
1846
1847 (define_insn "divsf3"
1848   [(set (match_operand:SF         0 "register_operand" "=f,f")
1849         (div:SF (match_operand:SF 1 "register_operand"  "0,f")
1850                 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1851    (clobber (reg:CC_FLOAT CC_REG))]
1852   "TARGET_AM33_2"
1853   "@
1854    fdiv %2, %0
1855    fdiv %2, %1, %0"
1856   [(set_attr_alternative "timings"
1857                          [(if_then_else (eq_attr "cpu" "am34")
1858                                         (const_int 2531) (const_int 1216))
1859                           (if_then_else (eq_attr "cpu" "am34")
1860                                         (const_int 2531) (const_int 1317))
1861                          ])]
1862 )
1863
1864 (define_insn "fmasf4"
1865   [(set (match_operand:SF         0 "register_operand" "=c")
1866         (fma:SF (match_operand:SF 1 "register_operand" "f")
1867                 (match_operand:SF 2 "register_operand" "f")
1868                 (match_operand:SF 3 "register_operand" "f")))
1869    (clobber (reg:CC_FLOAT CC_REG))
1870   ]
1871   "TARGET_AM33_2"
1872   "fmadd %1, %2, %3, %0"
1873   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1874                                        (const_int 17) (const_int 24)))]
1875 )
1876
1877 (define_insn "fmssf4"
1878   [(set (match_operand:SF                 0 "register_operand" "=c")
1879         (fma:SF (match_operand:SF         1 "register_operand" "f")
1880                 (match_operand:SF         2 "register_operand" "f")
1881                 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
1882    (clobber (reg:CC_FLOAT CC_REG))
1883   ]
1884   "TARGET_AM33_2"
1885   "fmsub %1, %2, %3, %0"
1886   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1887                                        (const_int 17) (const_int 24)))]
1888 )
1889
1890 (define_insn "fnmasf4"
1891   [(set (match_operand:SF                 0 "register_operand" "=c")
1892         (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
1893                 (match_operand:SF         2 "register_operand" "f")
1894                 (match_operand:SF         3 "register_operand" "f")))
1895    (clobber (reg:CC_FLOAT CC_REG))
1896   ]
1897   "TARGET_AM33_2"
1898   "fnmadd %1, %2, %3, %0"
1899   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1900                                        (const_int 17) (const_int 24)))]
1901 )
1902
1903 (define_insn "fnmssf4"
1904   [(set (match_operand:SF                 0 "register_operand" "=c")
1905         (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
1906                 (match_operand:SF         2 "register_operand" "f")
1907                 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
1908    (clobber (reg:CC_FLOAT CC_REG))
1909   ]
1910   "TARGET_AM33_2"
1911   "fnmsub %1, %2, %3, %0"
1912   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1913                                        (const_int 17) (const_int 24)))]
1914 )
1915
1916 ;; ----------------------------------------------------------------------
1917 ;; PROLOGUE/EPILOGUE
1918 ;; ----------------------------------------------------------------------
1919 (define_expand "prologue"
1920   [(const_int 0)]
1921   ""
1922   { mn10300_expand_prologue (); DONE; }
1923 )
1924
1925 (define_expand "epilogue"
1926   [(return)]
1927   ""
1928   { mn10300_expand_epilogue (); DONE; }
1929 )
1930
1931 (define_insn "return"
1932   [(return)]
1933   "mn10300_can_use_rets_insn ()"
1934 {
1935   /* The RETF insn is 4 cycles faster than RETS, though 1 byte larger.  */
1936   if (optimize_insn_for_speed_p () && mn10300_can_use_retf_insn ())
1937     return "retf [],0";
1938   else
1939     return "rets";
1940 })
1941
1942 (define_insn "return_ret"
1943   [(return)
1944    (use (match_operand:SI 0 "const_int_operand" ""))]
1945   ""
1946 {
1947   /* The RETF insn is up to 3 cycles faster than RET.  */
1948   fputs ((mn10300_can_use_retf_insn () ? "\tretf " : "\tret "), asm_out_file);
1949   mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs ());
1950   fprintf (asm_out_file, ",%d\n", (int) INTVAL (operands[0]));
1951   return "";
1952 })
1953
1954 ;; This instruction matches one generated by mn10300_gen_multiple_store()
1955 (define_insn "store_movm"
1956   [(match_parallel 0 "mn10300_store_multiple_operation"
1957     [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])]
1958   ""
1959 {
1960   fputs ("\tmovm ", asm_out_file);
1961   mn10300_print_reg_list (asm_out_file,
1962                           mn10300_store_multiple_operation (operands[0],
1963                                                             VOIDmode));
1964   fprintf (asm_out_file, ",(sp)\n");
1965   return "";
1966 }
1967   ;; Assume that no more than 8 registers will be pushed.
1968   [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1969                                        (const_int 99) (const_int 88)))]
1970 )
1971
1972 (define_expand "load_pic"
1973   [(const_int 0)]
1974   "flag_pic"
1975 {
1976   if (TARGET_AM33)
1977     emit_insn (gen_am33_load_pic (pic_offset_table_rtx));
1978   else if (mn10300_frame_size () == 0)
1979     emit_insn (gen_mn10300_load_pic0 (pic_offset_table_rtx));
1980   else
1981     emit_insn (gen_mn10300_load_pic1 (pic_offset_table_rtx));
1982   DONE;
1983 })
1984
1985 (define_insn "am33_load_pic"
1986   [(set (match_operand:SI 0 "register_operand" "=a")
1987         (unspec:SI [(const_int 0)] UNSPEC_GOT))
1988    (clobber (reg:CC CC_REG))]
1989   "TARGET_AM33"
1990 {
1991   operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
1992   return ".LPIC%=:\;mov pc,%0\;add %1-(.LPIC%=-.),%0";
1993 }
1994   [(set_attr "timings" "33")]
1995 )
1996
1997 ;; Load pic register with push/pop of stack.
1998 (define_insn "mn10300_load_pic0"
1999   [(set (match_operand:SI 0 "register_operand" "=a")
2000         (unspec:SI [(const_int 0)] UNSPEC_GOT))
2001    (clobber (reg:SI MDR_REG))
2002    (clobber (reg:CC CC_REG))]
2003   ""
2004 {
2005   operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
2006   return ("add -4,sp\;"
2007           "calls .LPIC%=\n"
2008           ".LPIC%=:\;"
2009           "movm (sp),[%0]\;"
2010           "add %1-(.LPIC%=-.),%0");
2011 }
2012   [(set_attr "timings" "88")]
2013 )
2014
2015 ;; Load pic register re-using existing stack space.
2016 (define_insn "mn10300_load_pic1"
2017   [(set (match_operand:SI 0 "register_operand" "=a")
2018         (unspec:SI [(const_int 0)] UNSPEC_GOT))
2019    (clobber (mem:SI (reg:SI SP_REG)))
2020    (clobber (reg:SI MDR_REG))
2021    (clobber (reg:CC CC_REG))]
2022   ""
2023 {
2024   operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
2025   return ("calls .LPIC%=\n"
2026           ".LPIC%=:\;"
2027           "mov (sp),%0\;"
2028           "add %1-(.LPIC%=-.),%0");
2029 }
2030   [(set_attr "timings" "66")]
2031 )